Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:31:07.179172 lava-dispatcher, installed at version: 2024.05
2 11:31:07.179376 start: 0 validate
3 11:31:07.179488 Start time: 2024-07-17 11:31:07.179482+00:00 (UTC)
4 11:31:07.179624 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:07.179767 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:31:08.644601 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:08.644771 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:31:08.918291 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:31:08.918469 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:31:53.945375 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:31:53.945940 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:31:54.469672 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:31:54.470347 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:31:54.746283 validate duration: 47.57
16 11:31:54.747356 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:31:54.747822 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:31:54.748216 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:31:54.748837 Not decompressing ramdisk as can be used compressed.
20 11:31:54.749256 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:31:54.749556 saving as /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/ramdisk/initrd.cpio.gz
22 11:31:54.749840 total size: 5628169 (5 MB)
23 11:32:05.107991 progress 0 % (0 MB)
24 11:32:05.117056 progress 5 % (0 MB)
25 11:32:05.125169 progress 10 % (0 MB)
26 11:32:05.130959 progress 15 % (0 MB)
27 11:32:05.135648 progress 20 % (1 MB)
28 11:32:05.139232 progress 25 % (1 MB)
29 11:32:05.142594 progress 30 % (1 MB)
30 11:32:05.145427 progress 35 % (1 MB)
31 11:32:05.147908 progress 40 % (2 MB)
32 11:32:05.150308 progress 45 % (2 MB)
33 11:32:05.152404 progress 50 % (2 MB)
34 11:32:05.154592 progress 55 % (2 MB)
35 11:32:05.156634 progress 60 % (3 MB)
36 11:32:05.158436 progress 65 % (3 MB)
37 11:32:05.160247 progress 70 % (3 MB)
38 11:32:05.161926 progress 75 % (4 MB)
39 11:32:05.163693 progress 80 % (4 MB)
40 11:32:05.165129 progress 85 % (4 MB)
41 11:32:05.166760 progress 90 % (4 MB)
42 11:32:05.168373 progress 95 % (5 MB)
43 11:32:05.169695 progress 100 % (5 MB)
44 11:32:05.169898 5 MB downloaded in 10.42 s (0.52 MB/s)
45 11:32:05.170043 end: 1.1.1 http-download (duration 00:00:10) [common]
47 11:32:05.170275 end: 1.1 download-retry (duration 00:00:10) [common]
48 11:32:05.170354 start: 1.2 download-retry (timeout 00:09:50) [common]
49 11:32:05.170427 start: 1.2.1 http-download (timeout 00:09:50) [common]
50 11:32:05.170562 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:32:05.170623 saving as /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/kernel/Image
52 11:32:05.170675 total size: 54813184 (52 MB)
53 11:32:05.170728 No compression specified
54 11:32:05.432751 progress 0 % (0 MB)
55 11:32:05.479268 progress 5 % (2 MB)
56 11:32:05.496783 progress 10 % (5 MB)
57 11:32:05.510246 progress 15 % (7 MB)
58 11:32:05.523781 progress 20 % (10 MB)
59 11:32:05.537089 progress 25 % (13 MB)
60 11:32:05.550373 progress 30 % (15 MB)
61 11:32:05.564048 progress 35 % (18 MB)
62 11:32:05.577627 progress 40 % (20 MB)
63 11:32:05.591033 progress 45 % (23 MB)
64 11:32:05.604930 progress 50 % (26 MB)
65 11:32:05.618482 progress 55 % (28 MB)
66 11:32:05.631810 progress 60 % (31 MB)
67 11:32:05.645741 progress 65 % (34 MB)
68 11:32:05.659577 progress 70 % (36 MB)
69 11:32:05.672952 progress 75 % (39 MB)
70 11:32:05.686935 progress 80 % (41 MB)
71 11:32:05.700670 progress 85 % (44 MB)
72 11:32:05.715188 progress 90 % (47 MB)
73 11:32:05.728878 progress 95 % (49 MB)
74 11:32:05.742915 progress 100 % (52 MB)
75 11:32:05.743161 52 MB downloaded in 0.57 s (91.31 MB/s)
76 11:32:05.743307 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:32:05.743543 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:32:05.743621 start: 1.3 download-retry (timeout 00:09:49) [common]
80 11:32:05.743695 start: 1.3.1 http-download (timeout 00:09:49) [common]
81 11:32:05.743855 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:32:05.743958 saving as /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/dtb/mt8192-asurada-spherion-r0.dtb
83 11:32:05.744090 total size: 47258 (0 MB)
84 11:32:05.744161 No compression specified
85 11:32:06.006506 progress 69 % (0 MB)
86 11:32:06.006794 progress 100 % (0 MB)
87 11:32:06.006944 0 MB downloaded in 0.26 s (0.17 MB/s)
88 11:32:06.007072 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:32:06.007273 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:32:06.007348 start: 1.4 download-retry (timeout 00:09:49) [common]
92 11:32:06.007421 start: 1.4.1 http-download (timeout 00:09:49) [common]
93 11:32:06.007544 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:32:06.007603 saving as /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/nfsrootfs/full.rootfs.tar
95 11:32:06.007655 total size: 120894716 (115 MB)
96 11:32:06.007709 Using unxz to decompress xz
97 11:32:06.273571 progress 0 % (0 MB)
98 11:32:06.660126 progress 5 % (5 MB)
99 11:32:07.030245 progress 10 % (11 MB)
100 11:32:07.392472 progress 15 % (17 MB)
101 11:32:07.740532 progress 20 % (23 MB)
102 11:32:08.054597 progress 25 % (28 MB)
103 11:32:08.417826 progress 30 % (34 MB)
104 11:32:08.761355 progress 35 % (40 MB)
105 11:32:08.942304 progress 40 % (46 MB)
106 11:32:09.133731 progress 45 % (51 MB)
107 11:32:09.481363 progress 50 % (57 MB)
108 11:32:09.866720 progress 55 % (63 MB)
109 11:32:10.222833 progress 60 % (69 MB)
110 11:32:10.579086 progress 65 % (74 MB)
111 11:32:10.941548 progress 70 % (80 MB)
112 11:32:11.306758 progress 75 % (86 MB)
113 11:32:11.658082 progress 80 % (92 MB)
114 11:32:12.014458 progress 85 % (98 MB)
115 11:32:12.364978 progress 90 % (103 MB)
116 11:32:12.707592 progress 95 % (109 MB)
117 11:32:13.075399 progress 100 % (115 MB)
118 11:32:13.080911 115 MB downloaded in 7.07 s (16.30 MB/s)
119 11:32:13.081076 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:32:13.081289 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:32:13.081367 start: 1.5 download-retry (timeout 00:09:42) [common]
123 11:32:13.081442 start: 1.5.1 http-download (timeout 00:09:42) [common]
124 11:32:13.081573 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:32:13.081635 saving as /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/modules/modules.tar
126 11:32:13.081688 total size: 8610184 (8 MB)
127 11:32:13.081743 Using unxz to decompress xz
128 11:32:13.082986 progress 0 % (0 MB)
129 11:32:13.103534 progress 5 % (0 MB)
130 11:32:13.128681 progress 10 % (0 MB)
131 11:32:13.153518 progress 15 % (1 MB)
132 11:32:13.178502 progress 20 % (1 MB)
133 11:32:13.202752 progress 25 % (2 MB)
134 11:32:13.227295 progress 30 % (2 MB)
135 11:32:13.250560 progress 35 % (2 MB)
136 11:32:13.276877 progress 40 % (3 MB)
137 11:32:13.302251 progress 45 % (3 MB)
138 11:32:13.326623 progress 50 % (4 MB)
139 11:32:13.351604 progress 55 % (4 MB)
140 11:32:13.376052 progress 60 % (4 MB)
141 11:32:13.399370 progress 65 % (5 MB)
142 11:32:13.425528 progress 70 % (5 MB)
143 11:32:13.457384 progress 75 % (6 MB)
144 11:32:13.490481 progress 80 % (6 MB)
145 11:32:13.515843 progress 85 % (7 MB)
146 11:32:13.539881 progress 90 % (7 MB)
147 11:32:13.565144 progress 95 % (7 MB)
148 11:32:13.591627 progress 100 % (8 MB)
149 11:32:13.597424 8 MB downloaded in 0.52 s (15.92 MB/s)
150 11:32:13.597670 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:32:13.598025 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:32:13.598149 start: 1.6 prepare-tftp-overlay (timeout 00:09:41) [common]
154 11:32:13.598270 start: 1.6.1 extract-nfsrootfs (timeout 00:09:41) [common]
155 11:32:17.736691 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp
156 11:32:17.736906 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:32:17.737037 start: 1.6.2 lava-overlay (timeout 00:09:37) [common]
158 11:32:17.737237 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue
159 11:32:17.737366 makedir: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin
160 11:32:17.737476 makedir: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/tests
161 11:32:17.737567 makedir: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/results
162 11:32:17.737652 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-add-keys
163 11:32:17.737796 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-add-sources
164 11:32:17.737915 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-background-process-start
165 11:32:17.738058 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-background-process-stop
166 11:32:17.738184 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-common-functions
167 11:32:17.738316 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-echo-ipv4
168 11:32:17.738434 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-install-packages
169 11:32:17.738546 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-installed-packages
170 11:32:17.738657 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-os-build
171 11:32:17.738767 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-probe-channel
172 11:32:17.738901 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-probe-ip
173 11:32:17.739014 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-target-ip
174 11:32:17.739124 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-target-mac
175 11:32:17.739237 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-target-storage
176 11:32:17.739364 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-case
177 11:32:17.739483 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-event
178 11:32:17.739593 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-feedback
179 11:32:17.739703 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-raise
180 11:32:17.739814 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-reference
181 11:32:17.739940 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-runner
182 11:32:17.740052 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-set
183 11:32:17.740162 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-test-shell
184 11:32:17.740279 Updating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-add-keys (debian)
185 11:32:17.740430 Updating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-add-sources (debian)
186 11:32:17.740560 Updating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-install-packages (debian)
187 11:32:17.740684 Updating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-installed-packages (debian)
188 11:32:17.740807 Updating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/bin/lava-os-build (debian)
189 11:32:17.740915 Creating /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/environment
190 11:32:17.741022 LAVA metadata
191 11:32:17.741087 - LAVA_JOB_ID=14864574
192 11:32:17.741142 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:32:17.741248 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:37) [common]
194 11:32:17.741304 skipped lava-vland-overlay
195 11:32:17.741374 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:32:17.741447 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:37) [common]
197 11:32:17.741535 skipped lava-multinode-overlay
198 11:32:17.741602 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:32:17.741671 start: 1.6.2.3 test-definition (timeout 00:09:37) [common]
200 11:32:17.741739 Loading test definitions
201 11:32:17.741815 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:37) [common]
202 11:32:17.741872 Using /lava-14864574 at stage 0
203 11:32:17.742186 uuid=14864574_1.6.2.3.1 testdef=None
204 11:32:17.742298 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:32:17.742411 start: 1.6.2.3.2 test-overlay (timeout 00:09:37) [common]
206 11:32:17.742849 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:32:17.743047 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:37) [common]
209 11:32:17.743586 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:32:17.743804 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:37) [common]
212 11:32:17.744379 runner path: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/0/tests/0_timesync-off test_uuid 14864574_1.6.2.3.1
213 11:32:17.744553 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:32:17.744795 start: 1.6.2.3.5 git-repo-action (timeout 00:09:37) [common]
216 11:32:17.744861 Using /lava-14864574 at stage 0
217 11:32:17.744951 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:32:17.745027 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/0/tests/1_kselftest-arm64'
219 11:32:21.200851 Running '/usr/bin/git checkout kernelci.org
220 11:32:21.338227 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:32:21.338678 uuid=14864574_1.6.2.3.5 testdef=None
222 11:32:21.338787 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:32:21.339097 start: 1.6.2.3.6 test-overlay (timeout 00:09:33) [common]
225 11:32:21.339845 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:32:21.340097 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:33) [common]
228 11:32:21.341173 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:32:21.341510 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:33) [common]
231 11:32:21.342564 runner path: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/0/tests/1_kselftest-arm64 test_uuid 14864574_1.6.2.3.5
232 11:32:21.342662 BOARD='mt8192-asurada-spherion-r0'
233 11:32:21.342735 BRANCH='cip-gitlab'
234 11:32:21.342818 SKIPFILE='/dev/null'
235 11:32:21.342886 SKIP_INSTALL='True'
236 11:32:21.342936 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:32:21.342993 TST_CASENAME=''
238 11:32:21.343075 TST_CMDFILES='arm64'
239 11:32:21.343242 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:32:21.343428 Creating lava-test-runner.conf files
242 11:32:21.343485 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864574/lava-overlay-78_giwue/lava-14864574/0 for stage 0
243 11:32:21.343572 - 0_timesync-off
244 11:32:21.343634 - 1_kselftest-arm64
245 11:32:21.343724 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:32:21.343803 start: 1.6.2.4 compress-overlay (timeout 00:09:33) [common]
247 11:32:28.980989 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:32:28.981155 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:26) [common]
249 11:32:28.981275 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:32:28.981390 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:32:28.981498 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:26) [common]
252 11:32:29.137776 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:32:29.138036 start: 1.6.4 extract-modules (timeout 00:09:26) [common]
254 11:32:29.138160 extracting modules file /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp
255 11:32:29.431813 extracting modules file /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864574/extract-overlay-ramdisk-l3sc9qrc/ramdisk
256 11:32:29.678615 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:32:29.678810 start: 1.6.5 apply-overlay-tftp (timeout 00:09:25) [common]
258 11:32:29.678894 [common] Applying overlay to NFS
259 11:32:29.678954 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864574/compress-overlay-8zb4kzrp/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp
260 11:32:30.679015 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:32:30.679194 start: 1.6.6 configure-preseed-file (timeout 00:09:24) [common]
262 11:32:30.679322 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:32:30.679432 start: 1.6.7 compress-ramdisk (timeout 00:09:24) [common]
264 11:32:30.679531 Building ramdisk /var/lib/lava/dispatcher/tmp/14864574/extract-overlay-ramdisk-l3sc9qrc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864574/extract-overlay-ramdisk-l3sc9qrc/ramdisk
265 11:32:30.978250 >> 129966 blocks
266 11:32:33.175461 rename /var/lib/lava/dispatcher/tmp/14864574/extract-overlay-ramdisk-l3sc9qrc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/ramdisk/ramdisk.cpio.gz
267 11:32:33.175682 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:32:33.175809 start: 1.6.8 prepare-kernel (timeout 00:09:22) [common]
269 11:32:33.175922 start: 1.6.8.1 prepare-fit (timeout 00:09:22) [common]
270 11:32:33.176037 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/kernel/Image']
271 11:32:48.198366 Returned 0 in 15 seconds
272 11:32:48.198522 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/kernel/image.itb
273 11:32:48.702762 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:32:48.702878 output: Created: Wed Jul 17 12:32:48 2024
275 11:32:48.702938 output: Image 0 (kernel-1)
276 11:32:48.702992 output: Description:
277 11:32:48.703045 output: Created: Wed Jul 17 12:32:48 2024
278 11:32:48.703096 output: Type: Kernel Image
279 11:32:48.703147 output: Compression: lzma compressed
280 11:32:48.703200 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:32:48.703251 output: Architecture: AArch64
282 11:32:48.703300 output: OS: Linux
283 11:32:48.703348 output: Load Address: 0x00000000
284 11:32:48.703397 output: Entry Point: 0x00000000
285 11:32:48.703445 output: Hash algo: crc32
286 11:32:48.703493 output: Hash value: 83448d17
287 11:32:48.703541 output: Image 1 (fdt-1)
288 11:32:48.703589 output: Description: mt8192-asurada-spherion-r0
289 11:32:48.703637 output: Created: Wed Jul 17 12:32:48 2024
290 11:32:48.703685 output: Type: Flat Device Tree
291 11:32:48.703732 output: Compression: uncompressed
292 11:32:48.703780 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:32:48.703828 output: Architecture: AArch64
294 11:32:48.703876 output: Hash algo: crc32
295 11:32:48.703923 output: Hash value: 0f8e4d2e
296 11:32:48.703970 output: Image 2 (ramdisk-1)
297 11:32:48.704017 output: Description: unavailable
298 11:32:48.704065 output: Created: Wed Jul 17 12:32:48 2024
299 11:32:48.704114 output: Type: RAMDisk Image
300 11:32:48.704161 output: Compression: uncompressed
301 11:32:48.704209 output: Data Size: 18721543 Bytes = 18282.76 KiB = 17.85 MiB
302 11:32:48.704257 output: Architecture: AArch64
303 11:32:48.704304 output: OS: Linux
304 11:32:48.704351 output: Load Address: unavailable
305 11:32:48.704398 output: Entry Point: unavailable
306 11:32:48.704445 output: Hash algo: crc32
307 11:32:48.704493 output: Hash value: e9303b8a
308 11:32:48.704540 output: Default Configuration: 'conf-1'
309 11:32:48.704586 output: Configuration 0 (conf-1)
310 11:32:48.704633 output: Description: mt8192-asurada-spherion-r0
311 11:32:48.704680 output: Kernel: kernel-1
312 11:32:48.704728 output: Init Ramdisk: ramdisk-1
313 11:32:48.704775 output: FDT: fdt-1
314 11:32:48.704823 output: Loadables: kernel-1
315 11:32:48.704872 output:
316 11:32:48.704972 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 11:32:48.705047 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 11:32:48.705122 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 11:32:48.705197 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
320 11:32:48.705271 No LXC device requested
321 11:32:48.705367 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:32:48.705456 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
323 11:32:48.705524 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:32:48.705579 Checking files for TFTP limit of 4294967296 bytes.
325 11:32:48.705951 end: 1 tftp-deploy (duration 00:00:54) [common]
326 11:32:48.706051 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:32:48.706140 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:32:48.706229 substitutions:
329 11:32:48.706287 - {DTB}: 14864574/tftp-deploy-lg88ucyt/dtb/mt8192-asurada-spherion-r0.dtb
330 11:32:48.706342 - {INITRD}: 14864574/tftp-deploy-lg88ucyt/ramdisk/ramdisk.cpio.gz
331 11:32:48.706395 - {KERNEL}: 14864574/tftp-deploy-lg88ucyt/kernel/Image
332 11:32:48.706446 - {LAVA_MAC}: None
333 11:32:48.706496 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp
334 11:32:48.706546 - {NFS_SERVER_IP}: 192.168.201.1
335 11:32:48.706595 - {PRESEED_CONFIG}: None
336 11:32:48.706650 - {PRESEED_LOCAL}: None
337 11:32:48.706700 - {RAMDISK}: 14864574/tftp-deploy-lg88ucyt/ramdisk/ramdisk.cpio.gz
338 11:32:48.706748 - {ROOT_PART}: None
339 11:32:48.706796 - {ROOT}: None
340 11:32:48.706845 - {SERVER_IP}: 192.168.201.1
341 11:32:48.706895 - {TEE}: None
342 11:32:48.706956 Parsed boot commands:
343 11:32:48.707003 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:32:48.707139 Parsed boot commands: tftpboot 192.168.201.1 14864574/tftp-deploy-lg88ucyt/kernel/image.itb 14864574/tftp-deploy-lg88ucyt/kernel/cmdline
345 11:32:48.707219 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:32:48.707293 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:32:48.707365 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:32:48.707435 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:32:48.707490 Not connected, no need to disconnect.
350 11:32:48.707556 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:32:48.707626 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:32:48.707680 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 11:32:48.710665 Setting prompt string to ['lava-test: # ']
354 11:32:48.710981 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:32:48.711080 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:32:48.711167 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:32:48.711248 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:32:48.711417 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 11:32:57.867739 >> Command sent successfully.
360 11:32:57.871860 Returned 0 in 9 seconds
361 11:32:57.872004 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:32:57.872201 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:32:57.872285 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:32:57.872357 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:32:57.872412 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:32:57.872473 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:32:57.872801 [Enter `^Ec?' for help]
369 11:32:59.298243
370 11:32:59.298349
371 11:32:59.298422 F0: 102B 0000
372 11:32:59.298480
373 11:32:59.298532 F3: 1001 0000 [0200]
374 11:32:59.298591
375 11:32:59.301673 F3: 1001 0000
376 11:32:59.301753
377 11:32:59.301813 F7: 102D 0000
378 11:32:59.301868
379 11:32:59.305770 F1: 0000 0000
380 11:32:59.305849
381 11:32:59.305909 V0: 0000 0000 [0001]
382 11:32:59.305963
383 11:32:59.306028 00: 0007 8000
384 11:32:59.306083
385 11:32:59.309061 01: 0000 0000
386 11:32:59.309137
387 11:32:59.309216 BP: 0C00 0209 [0000]
388 11:32:59.309314
389 11:32:59.313031 G0: 1182 0000
390 11:32:59.313129
391 11:32:59.313232 EC: 0000 0021 [4000]
392 11:32:59.313312
393 11:32:59.316567 S7: 0000 0000 [0000]
394 11:32:59.316671
395 11:32:59.316755 CC: 0000 0000 [0001]
396 11:32:59.316837
397 11:32:59.320450 T0: 0000 0040 [010F]
398 11:32:59.320525
399 11:32:59.320586 Jump to BL
400 11:32:59.320670
401 11:32:59.345573
402 11:32:59.345670
403 11:32:59.353004 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:32:59.356885 ARM64: Exception handlers installed.
405 11:32:59.360643 ARM64: Testing exception
406 11:32:59.364271 ARM64: Done test exception
407 11:32:59.367624 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:32:59.379745 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:32:59.387543 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:32:59.398149 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:32:59.405525 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:32:59.412095 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:32:59.422163 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:32:59.429019 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:32:59.448028 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:32:59.451350 WDT: Last reset was cold boot
417 11:32:59.454694 SPI1(PAD0) initialized at 2873684 Hz
418 11:32:59.458142 SPI5(PAD0) initialized at 992727 Hz
419 11:32:59.461946 VBOOT: Loading verstage.
420 11:32:59.468603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:32:59.471727 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:32:59.474916 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:32:59.478284 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:32:59.485775 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:32:59.492225 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:32:59.503260 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 11:32:59.503360
428 11:32:59.503445
429 11:32:59.513456 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:32:59.516476 ARM64: Exception handlers installed.
431 11:32:59.519767 ARM64: Testing exception
432 11:32:59.519836 ARM64: Done test exception
433 11:32:59.526771 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:32:59.530335 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:32:59.544038 Probing TPM: . done!
436 11:32:59.544130 TPM ready after 0 ms
437 11:32:59.550697 Connected to device vid:did:rid of 1ae0:0028:00
438 11:32:59.557554 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:32:59.560964 Initialized TPM device CR50 revision 0
440 11:32:59.609709 tlcl_send_startup: Startup return code is 0
441 11:32:59.609880 TPM: setup succeeded
442 11:32:59.621360 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:32:59.630186 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:32:59.639789 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:32:59.648794 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:32:59.652642 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:32:59.655663 in-header: 03 07 00 00 08 00 00 00
448 11:32:59.659381 in-data: aa e4 47 04 13 02 00 00
449 11:32:59.662738 Chrome EC: UHEPI supported
450 11:32:59.668955 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:32:59.672946 in-header: 03 a9 00 00 08 00 00 00
452 11:32:59.676104 in-data: 84 60 60 08 00 00 00 00
453 11:32:59.676178 Phase 1
454 11:32:59.682713 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:32:59.689118 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:32:59.692605 VB2:vb2_check_recovery() Recovery was requested manually
457 11:32:59.699476 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:32:59.699553 Recovery requested (1009000e)
459 11:32:59.708796 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:32:59.714175 tlcl_extend: response is 0
461 11:32:59.722190 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:32:59.727526 tlcl_extend: response is 0
463 11:32:59.734262 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:32:59.754926 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:32:59.761642 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:32:59.761720
467 11:32:59.761779
468 11:32:59.771277 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:32:59.774620 ARM64: Exception handlers installed.
470 11:32:59.778494 ARM64: Testing exception
471 11:32:59.778577 ARM64: Done test exception
472 11:32:59.800502 pmic_efuse_setting: Set efuses in 11 msecs
473 11:32:59.803940 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:32:59.810683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:32:59.813904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:32:59.820825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:32:59.823835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:32:59.830673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:32:59.833878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:32:59.837209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:32:59.844091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:32:59.847356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:32:59.854206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:32:59.857160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:32:59.860427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:32:59.867021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:32:59.873775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:32:59.877099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:32:59.883924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:32:59.936465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:32:59.936593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:32:59.936686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:32:59.936775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:32:59.936862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:32:59.936948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:32:59.937033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:32:59.937119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:32:59.937218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:32:59.939778 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:32:59.946384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:32:59.949391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:32:59.953378 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:32:59.960181 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:32:59.963326 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:32:59.970202 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:32:59.973738 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:32:59.979756 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:32:59.983156 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:32:59.989876 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:32:59.993141 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:33:00.001096 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:33:00.004477 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:33:00.007763 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:33:00.011165 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:33:00.017606 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:33:00.021280 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:33:00.024412 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:33:00.031189 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:33:00.034440 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:33:00.037723 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:33:00.041118 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:33:00.047506 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:33:00.050919 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:33:00.054162 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:33:00.064229 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:33:00.071329 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:33:00.077901 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:33:00.084706 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:33:00.094279 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:33:00.097693 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:33:00.101098 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:33:00.107794 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:33:00.114390 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
534 11:33:00.118101 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:33:00.124647 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:33:00.128442 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:33:00.137733 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 11:33:00.147204 [RTC]rtc_get_frequency_meter,154: input=23, output=943
539 11:33:00.156997 [RTC]rtc_get_frequency_meter,154: input=19, output=852
540 11:33:00.166382 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 11:33:00.175668 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 11:33:00.184936 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 11:33:00.195298 [RTC]rtc_get_frequency_meter,154: input=17, output=803
544 11:33:00.197893 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:33:00.205514 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
546 11:33:00.208982 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:33:00.211700 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:33:00.218914 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:33:00.221692 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:33:00.225113 ADC[4]: Raw value=905834 ID=7
551 11:33:00.225188 ADC[3]: Raw value=213072 ID=1
552 11:33:00.228490 RAM Code: 0x71
553 11:33:00.232355 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:33:00.238742 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:33:00.245764 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:33:00.252368 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:33:00.255340 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:33:00.258956 in-header: 03 07 00 00 08 00 00 00
559 11:33:00.261978 in-data: aa e4 47 04 13 02 00 00
560 11:33:00.265816 Chrome EC: UHEPI supported
561 11:33:00.272037 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:33:00.275744 in-header: 03 a9 00 00 08 00 00 00
563 11:33:00.279226 in-data: 84 60 60 08 00 00 00 00
564 11:33:00.282203 MRC: failed to locate region type 0.
565 11:33:00.289483 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:33:00.292141 DRAM-K: Running full calibration
567 11:33:00.299473 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:33:00.299550 header.status = 0x0
569 11:33:00.302207 header.version = 0x6 (expected: 0x6)
570 11:33:00.305727 header.size = 0xd00 (expected: 0xd00)
571 11:33:00.309149 header.flags = 0x0
572 11:33:00.312543 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:33:00.331450 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:33:00.338194 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:33:00.341422 dram_init: ddr_geometry: 2
576 11:33:00.345307 [EMI] MDL number = 2
577 11:33:00.345389 [EMI] Get MDL freq = 0
578 11:33:00.348382 dram_init: ddr_type: 0
579 11:33:00.348458 is_discrete_lpddr4: 1
580 11:33:00.351436 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:33:00.351510
582 11:33:00.351568
583 11:33:00.354813 [Bian_co] ETT version 0.0.0.1
584 11:33:00.361414 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:33:00.361490
586 11:33:00.364722 dramc_set_vcore_voltage set vcore to 650000
587 11:33:00.368622 Read voltage for 800, 4
588 11:33:00.368697 Vio18 = 0
589 11:33:00.368756 Vcore = 650000
590 11:33:00.368810 Vdram = 0
591 11:33:00.371822 Vddq = 0
592 11:33:00.371897 Vmddr = 0
593 11:33:00.375182 dram_init: config_dvfs: 1
594 11:33:00.378456 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:33:00.384844 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:33:00.388413 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 11:33:00.391510 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 11:33:00.394698 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:33:00.398568 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:33:00.401623 MEM_TYPE=3, freq_sel=18
601 11:33:00.405039 sv_algorithm_assistance_LP4_1600
602 11:33:00.408351 ============ PULL DRAM RESETB DOWN ============
603 11:33:00.411647 ========== PULL DRAM RESETB DOWN end =========
604 11:33:00.418530 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:33:00.421811 ===================================
606 11:33:00.425216 LPDDR4 DRAM CONFIGURATION
607 11:33:00.428683 ===================================
608 11:33:00.428758 EX_ROW_EN[0] = 0x0
609 11:33:00.431372 EX_ROW_EN[1] = 0x0
610 11:33:00.431449 LP4Y_EN = 0x0
611 11:33:00.435325 WORK_FSP = 0x0
612 11:33:00.435400 WL = 0x2
613 11:33:00.438170 RL = 0x2
614 11:33:00.438246 BL = 0x2
615 11:33:00.442117 RPST = 0x0
616 11:33:00.442192 RD_PRE = 0x0
617 11:33:00.445538 WR_PRE = 0x1
618 11:33:00.445651 WR_PST = 0x0
619 11:33:00.448208 DBI_WR = 0x0
620 11:33:00.448342 DBI_RD = 0x0
621 11:33:00.452080 OTF = 0x1
622 11:33:00.455213 ===================================
623 11:33:00.458373 ===================================
624 11:33:00.458443 ANA top config
625 11:33:00.461537 ===================================
626 11:33:00.464948 DLL_ASYNC_EN = 0
627 11:33:00.468210 ALL_SLAVE_EN = 1
628 11:33:00.471535 NEW_RANK_MODE = 1
629 11:33:00.471631 DLL_IDLE_MODE = 1
630 11:33:00.474967 LP45_APHY_COMB_EN = 1
631 11:33:00.478800 TX_ODT_DIS = 1
632 11:33:00.481996 NEW_8X_MODE = 1
633 11:33:00.485350 ===================================
634 11:33:00.488738 ===================================
635 11:33:00.488840 data_rate = 1600
636 11:33:00.492009 CKR = 1
637 11:33:00.495709 DQ_P2S_RATIO = 8
638 11:33:00.498895 ===================================
639 11:33:00.502132 CA_P2S_RATIO = 8
640 11:33:00.505573 DQ_CA_OPEN = 0
641 11:33:00.508937 DQ_SEMI_OPEN = 0
642 11:33:00.509032 CA_SEMI_OPEN = 0
643 11:33:00.512252 CA_FULL_RATE = 0
644 11:33:00.515404 DQ_CKDIV4_EN = 1
645 11:33:00.519135 CA_CKDIV4_EN = 1
646 11:33:00.522100 CA_PREDIV_EN = 0
647 11:33:00.525670 PH8_DLY = 0
648 11:33:00.525765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:33:00.528715 DQ_AAMCK_DIV = 4
650 11:33:00.532352 CA_AAMCK_DIV = 4
651 11:33:00.535427 CA_ADMCK_DIV = 4
652 11:33:00.539089 DQ_TRACK_CA_EN = 0
653 11:33:00.542604 CA_PICK = 800
654 11:33:00.542678 CA_MCKIO = 800
655 11:33:00.545233 MCKIO_SEMI = 0
656 11:33:00.548573 PLL_FREQ = 3068
657 11:33:00.551969 DQ_UI_PI_RATIO = 32
658 11:33:00.555331 CA_UI_PI_RATIO = 0
659 11:33:00.559259 ===================================
660 11:33:00.562411 ===================================
661 11:33:00.562480 memory_type:LPDDR4
662 11:33:00.565625 GP_NUM : 10
663 11:33:00.568833 SRAM_EN : 1
664 11:33:00.568925 MD32_EN : 0
665 11:33:00.572108 ===================================
666 11:33:00.575563 [ANA_INIT] >>>>>>>>>>>>>>
667 11:33:00.578936 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:33:00.582262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:33:00.586267 ===================================
670 11:33:00.589589 data_rate = 1600,PCW = 0X7600
671 11:33:00.589685 ===================================
672 11:33:00.593364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:33:00.600934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:33:00.604042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:33:00.611102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:33:00.615078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:33:00.618631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:33:00.618726 [ANA_INIT] flow start
679 11:33:00.622104 [ANA_INIT] PLL >>>>>>>>
680 11:33:00.625343 [ANA_INIT] PLL <<<<<<<<
681 11:33:00.625435 [ANA_INIT] MIDPI >>>>>>>>
682 11:33:00.628658 [ANA_INIT] MIDPI <<<<<<<<
683 11:33:00.631862 [ANA_INIT] DLL >>>>>>>>
684 11:33:00.631952 [ANA_INIT] flow end
685 11:33:00.635401 ============ LP4 DIFF to SE enter ============
686 11:33:00.641786 ============ LP4 DIFF to SE exit ============
687 11:33:00.641868 [ANA_INIT] <<<<<<<<<<<<<
688 11:33:00.645545 [Flow] Enable top DCM control >>>>>
689 11:33:00.648537 [Flow] Enable top DCM control <<<<<
690 11:33:00.652107 Enable DLL master slave shuffle
691 11:33:00.658617 ==============================================================
692 11:33:00.658688 Gating Mode config
693 11:33:00.665301 ==============================================================
694 11:33:00.668614 Config description:
695 11:33:00.678783 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:33:00.685530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:33:00.688775 SELPH_MODE 0: By rank 1: By Phase
698 11:33:00.695273 ==============================================================
699 11:33:00.698712 GAT_TRACK_EN = 1
700 11:33:00.698783 RX_GATING_MODE = 2
701 11:33:00.702025 RX_GATING_TRACK_MODE = 2
702 11:33:00.705443 SELPH_MODE = 1
703 11:33:00.708719 PICG_EARLY_EN = 1
704 11:33:00.711992 VALID_LAT_VALUE = 1
705 11:33:00.719165 ==============================================================
706 11:33:00.721793 Enter into Gating configuration >>>>
707 11:33:00.725279 Exit from Gating configuration <<<<
708 11:33:00.728576 Enter into DVFS_PRE_config >>>>>
709 11:33:00.738592 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:33:00.742281 Exit from DVFS_PRE_config <<<<<
711 11:33:00.745442 Enter into PICG configuration >>>>
712 11:33:00.748839 Exit from PICG configuration <<<<
713 11:33:00.752167 [RX_INPUT] configuration >>>>>
714 11:33:00.752246 [RX_INPUT] configuration <<<<<
715 11:33:00.759223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:33:00.765473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:33:00.769413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:33:00.775475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:33:00.782481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:33:00.789389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:33:00.792689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:33:00.795991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:33:00.802439 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:33:00.805742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:33:00.808968 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:33:00.812208 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:33:00.815504 ===================================
728 11:33:00.819032 LPDDR4 DRAM CONFIGURATION
729 11:33:00.822653 ===================================
730 11:33:00.826046 EX_ROW_EN[0] = 0x0
731 11:33:00.826133 EX_ROW_EN[1] = 0x0
732 11:33:00.829394 LP4Y_EN = 0x0
733 11:33:00.829461 WORK_FSP = 0x0
734 11:33:00.832103 WL = 0x2
735 11:33:00.832189 RL = 0x2
736 11:33:00.835501 BL = 0x2
737 11:33:00.835595 RPST = 0x0
738 11:33:00.838883 RD_PRE = 0x0
739 11:33:00.838972 WR_PRE = 0x1
740 11:33:00.842259 WR_PST = 0x0
741 11:33:00.842338 DBI_WR = 0x0
742 11:33:00.845453 DBI_RD = 0x0
743 11:33:00.845517 OTF = 0x1
744 11:33:00.849220 ===================================
745 11:33:00.855636 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:33:00.859065 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:33:00.862454 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:33:00.865878 ===================================
749 11:33:00.869264 LPDDR4 DRAM CONFIGURATION
750 11:33:00.872411 ===================================
751 11:33:00.875495 EX_ROW_EN[0] = 0x10
752 11:33:00.875561 EX_ROW_EN[1] = 0x0
753 11:33:00.879119 LP4Y_EN = 0x0
754 11:33:00.879207 WORK_FSP = 0x0
755 11:33:00.882280 WL = 0x2
756 11:33:00.882355 RL = 0x2
757 11:33:00.886155 BL = 0x2
758 11:33:00.886231 RPST = 0x0
759 11:33:00.889480 RD_PRE = 0x0
760 11:33:00.889573 WR_PRE = 0x1
761 11:33:00.892693 WR_PST = 0x0
762 11:33:00.892763 DBI_WR = 0x0
763 11:33:00.895765 DBI_RD = 0x0
764 11:33:00.895851 OTF = 0x1
765 11:33:00.899501 ===================================
766 11:33:00.906270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:33:00.910069 nWR fixed to 40
768 11:33:00.913372 [ModeRegInit_LP4] CH0 RK0
769 11:33:00.913469 [ModeRegInit_LP4] CH0 RK1
770 11:33:00.917043 [ModeRegInit_LP4] CH1 RK0
771 11:33:00.920293 [ModeRegInit_LP4] CH1 RK1
772 11:33:00.920385 match AC timing 13
773 11:33:00.926858 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:33:00.930259 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:33:00.933710 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:33:00.940471 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:33:00.943979 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:33:00.944049 [EMI DOE] emi_dcm 0
779 11:33:00.950660 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:33:00.950735 ==
781 11:33:00.953951 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:33:00.957351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:33:00.957441 ==
784 11:33:00.963692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:33:00.966976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:33:00.977562 [CA 0] Center 36 (6~67) winsize 62
787 11:33:00.980872 [CA 1] Center 36 (6~67) winsize 62
788 11:33:00.984088 [CA 2] Center 34 (4~65) winsize 62
789 11:33:00.987873 [CA 3] Center 34 (4~64) winsize 61
790 11:33:00.990984 [CA 4] Center 33 (3~63) winsize 61
791 11:33:00.994529 [CA 5] Center 32 (2~62) winsize 61
792 11:33:00.994597
793 11:33:00.998316 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:33:00.998385
795 11:33:01.002104 [CATrainingPosCal] consider 1 rank data
796 11:33:01.005051 u2DelayCellTimex100 = 270/100 ps
797 11:33:01.008240 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 11:33:01.012074 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 11:33:01.015432 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 11:33:01.018766 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 11:33:01.022038 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 11:33:01.028324 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 11:33:01.028416
804 11:33:01.032026 CA PerBit enable=1, Macro0, CA PI delay=32
805 11:33:01.032090
806 11:33:01.035276 [CBTSetCACLKResult] CA Dly = 32
807 11:33:01.035339 CS Dly: 5 (0~36)
808 11:33:01.035413 ==
809 11:33:01.038683 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:33:01.042102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:33:01.042170 ==
812 11:33:01.048886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:33:01.055442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:33:01.064232 [CA 0] Center 36 (6~67) winsize 62
815 11:33:01.067538 [CA 1] Center 36 (6~67) winsize 62
816 11:33:01.070803 [CA 2] Center 34 (3~65) winsize 63
817 11:33:01.073982 [CA 3] Center 34 (3~65) winsize 63
818 11:33:01.077092 [CA 4] Center 33 (3~63) winsize 61
819 11:33:01.080332 [CA 5] Center 32 (2~63) winsize 62
820 11:33:01.080425
821 11:33:01.083750 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:33:01.083839
823 11:33:01.087231 [CATrainingPosCal] consider 2 rank data
824 11:33:01.090536 u2DelayCellTimex100 = 270/100 ps
825 11:33:01.093902 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 11:33:01.097845 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 11:33:01.100959 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 11:33:01.107342 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 11:33:01.110455 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 11:33:01.114297 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 11:33:01.114373
832 11:33:01.117399 CA PerBit enable=1, Macro0, CA PI delay=32
833 11:33:01.117488
834 11:33:01.120802 [CBTSetCACLKResult] CA Dly = 32
835 11:33:01.120894 CS Dly: 5 (0~37)
836 11:33:01.120975
837 11:33:01.123817 ----->DramcWriteLeveling(PI) begin...
838 11:33:01.127495 ==
839 11:33:01.127588 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:33:01.134134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:33:01.134215 ==
842 11:33:01.137952 Write leveling (Byte 0): 35 => 35
843 11:33:01.140815 Write leveling (Byte 1): 32 => 32
844 11:33:01.140891 DramcWriteLeveling(PI) end<-----
845 11:33:01.144543
846 11:33:01.144630 ==
847 11:33:01.147760 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:33:01.151100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:33:01.151170 ==
850 11:33:01.154416 [Gating] SW mode calibration
851 11:33:01.161086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:33:01.164470 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:33:01.168660 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:33:01.174783 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:33:01.178157 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 11:33:01.181461 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:33:01.188577 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:33:01.191348 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:33:01.194788 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:33:01.201575 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:33:01.204848 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:33:01.208650 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:33:01.215107 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:33:01.218500 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:33:01.221156 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:33:01.228519 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:33:01.231640 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:33:01.234852 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:33:01.241666 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:33:01.244893 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:33:01.248698 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 11:33:01.251393 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:33:01.258108 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:33:01.261792 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:33:01.264787 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:33:01.271947 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:33:01.274656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:33:01.278311 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:33:01.285071 0 9 8 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
880 11:33:01.288340 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:33:01.291625 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:33:01.298179 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:33:01.301691 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:33:01.305209 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:33:01.311969 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:33:01.315198 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
887 11:33:01.318878 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (1 0)
888 11:33:01.322146 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 11:33:01.328932 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:33:01.332277 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:33:01.335611 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:33:01.342310 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:33:01.345557 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:33:01.348790 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 11:33:01.355344 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
896 11:33:01.359156 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
897 11:33:01.362505 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:33:01.368836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:33:01.372329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:33:01.375444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:33:01.381974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:33:01.385607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:33:01.388837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 11:33:01.392136 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:33:01.398811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:33:01.402178 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:33:01.405573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:33:01.412390 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:33:01.415937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:33:01.419315 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:33:01.425736 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:33:01.428900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:33:01.432122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:33:01.438807 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:33:01.442799 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:33:01.445494 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:33:01.452000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:33:01.455887 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:33:01.459237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:33:01.465630 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 11:33:01.465725 Total UI for P1: 0, mck2ui 16
922 11:33:01.472173 best dqsien dly found for B0: ( 0, 14, 6)
923 11:33:01.475309 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:33:01.479416 Total UI for P1: 0, mck2ui 16
925 11:33:01.482474 best dqsien dly found for B1: ( 0, 14, 10)
926 11:33:01.485743 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 11:33:01.488883 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:33:01.488983
929 11:33:01.492598 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 11:33:01.495545 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:33:01.499120 [Gating] SW calibration Done
932 11:33:01.499216 ==
933 11:33:01.502098 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:33:01.505910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:33:01.506020 ==
936 11:33:01.509277 RX Vref Scan: 0
937 11:33:01.509354
938 11:33:01.512545 RX Vref 0 -> 0, step: 1
939 11:33:01.512649
940 11:33:01.512735 RX Delay -130 -> 252, step: 16
941 11:33:01.518711 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
942 11:33:01.522155 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 11:33:01.525564 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:33:01.528918 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:33:01.532091 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 11:33:01.538926 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 11:33:01.541979 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 11:33:01.545903 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 11:33:01.549302 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
950 11:33:01.552650 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 11:33:01.558694 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 11:33:01.562157 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
953 11:33:01.565948 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
954 11:33:01.568922 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
955 11:33:01.572088 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 11:33:01.578672 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
957 11:33:01.578741 ==
958 11:33:01.581973 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:33:01.586106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:33:01.586180 ==
961 11:33:01.586236 DQS Delay:
962 11:33:01.589328 DQS0 = 0, DQS1 = 0
963 11:33:01.589418 DQM Delay:
964 11:33:01.592284 DQM0 = 90, DQM1 = 84
965 11:33:01.592381 DQ Delay:
966 11:33:01.595726 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 11:33:01.599139 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
968 11:33:01.602278 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
969 11:33:01.606033 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
970 11:33:01.606114
971 11:33:01.606171
972 11:33:01.606230 ==
973 11:33:01.608722 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:33:01.612203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:33:01.612303 ==
976 11:33:01.612367
977 11:33:01.615770
978 11:33:01.615837 TX Vref Scan disable
979 11:33:01.618877 == TX Byte 0 ==
980 11:33:01.622746 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
981 11:33:01.625568 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
982 11:33:01.628952 == TX Byte 1 ==
983 11:33:01.632453 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
984 11:33:01.635717 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
985 11:33:01.635791 ==
986 11:33:01.639218 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:33:01.645769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:33:01.645844 ==
989 11:33:01.657771 TX Vref=22, minBit 8, minWin=27, winSum=445
990 11:33:01.661068 TX Vref=24, minBit 8, minWin=27, winSum=450
991 11:33:01.664381 TX Vref=26, minBit 8, minWin=27, winSum=452
992 11:33:01.667809 TX Vref=28, minBit 5, minWin=28, winSum=456
993 11:33:01.671101 TX Vref=30, minBit 5, minWin=28, winSum=455
994 11:33:01.674499 TX Vref=32, minBit 10, minWin=27, winSum=451
995 11:33:01.681232 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 28
996 11:33:01.681311
997 11:33:01.684149 Final TX Range 1 Vref 28
998 11:33:01.684248
999 11:33:01.684332 ==
1000 11:33:01.687477 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:33:01.690938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:33:01.691021 ==
1003 11:33:01.691077
1004 11:33:01.694267
1005 11:33:01.694332 TX Vref Scan disable
1006 11:33:01.697518 == TX Byte 0 ==
1007 11:33:01.701109 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1008 11:33:01.704467 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1009 11:33:01.707810 == TX Byte 1 ==
1010 11:33:01.711120 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1011 11:33:01.714558 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1012 11:33:01.714632
1013 11:33:01.717707 [DATLAT]
1014 11:33:01.717803 Freq=800, CH0 RK0
1015 11:33:01.717885
1016 11:33:01.721471 DATLAT Default: 0xa
1017 11:33:01.721562 0, 0xFFFF, sum = 0
1018 11:33:01.724739 1, 0xFFFF, sum = 0
1019 11:33:01.724806 2, 0xFFFF, sum = 0
1020 11:33:01.727865 3, 0xFFFF, sum = 0
1021 11:33:01.727932 4, 0xFFFF, sum = 0
1022 11:33:01.731174 5, 0xFFFF, sum = 0
1023 11:33:01.731250 6, 0xFFFF, sum = 0
1024 11:33:01.734826 7, 0xFFFF, sum = 0
1025 11:33:01.734928 8, 0xFFFF, sum = 0
1026 11:33:01.738149 9, 0x0, sum = 1
1027 11:33:01.738246 10, 0x0, sum = 2
1028 11:33:01.741462 11, 0x0, sum = 3
1029 11:33:01.741554 12, 0x0, sum = 4
1030 11:33:01.744810 best_step = 10
1031 11:33:01.744874
1032 11:33:01.744928 ==
1033 11:33:01.747687 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:33:01.750915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:33:01.751008 ==
1036 11:33:01.754343 RX Vref Scan: 1
1037 11:33:01.754408
1038 11:33:01.754474 Set Vref Range= 32 -> 127
1039 11:33:01.754530
1040 11:33:01.757825 RX Vref 32 -> 127, step: 1
1041 11:33:01.757908
1042 11:33:01.761507 RX Delay -95 -> 252, step: 8
1043 11:33:01.761592
1044 11:33:01.764608 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:33:01.768206 [Byte1]: 32
1046 11:33:01.768292
1047 11:33:01.771160 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:33:01.774469 [Byte1]: 33
1049 11:33:01.777892
1050 11:33:01.777984 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:33:01.781576 [Byte1]: 34
1052 11:33:01.785810
1053 11:33:01.785901 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:33:01.789040 [Byte1]: 35
1055 11:33:01.793357
1056 11:33:01.793445 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:33:01.796559 [Byte1]: 36
1058 11:33:01.800629
1059 11:33:01.800727 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:33:01.803955 [Byte1]: 37
1061 11:33:01.808576
1062 11:33:01.808669 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:33:01.811700 [Byte1]: 38
1064 11:33:01.816223
1065 11:33:01.816317 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:33:01.819612 [Byte1]: 39
1067 11:33:01.823493
1068 11:33:01.823567 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:33:01.826678 [Byte1]: 40
1070 11:33:01.831502
1071 11:33:01.831576 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:33:01.834235 [Byte1]: 41
1073 11:33:01.838759
1074 11:33:01.838855 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:33:01.841946 [Byte1]: 42
1076 11:33:01.846251
1077 11:33:01.846316 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:33:01.850141 [Byte1]: 43
1079 11:33:01.854159
1080 11:33:01.854228 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:33:01.857454 [Byte1]: 44
1082 11:33:01.861528
1083 11:33:01.861609 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:33:01.864757 [Byte1]: 45
1085 11:33:01.868936
1086 11:33:01.869005 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:33:01.872306 [Byte1]: 46
1088 11:33:01.876913
1089 11:33:01.877002 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:33:01.879901 [Byte1]: 47
1091 11:33:01.884148
1092 11:33:01.884238 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:33:01.887804 [Byte1]: 48
1094 11:33:01.891799
1095 11:33:01.891891 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:33:01.895046 [Byte1]: 49
1097 11:33:01.899603
1098 11:33:01.899694 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:33:01.902769 [Byte1]: 50
1100 11:33:01.907158
1101 11:33:01.907250 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:33:01.910591 [Byte1]: 51
1103 11:33:01.914619
1104 11:33:01.914712 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:33:01.918396 [Byte1]: 52
1106 11:33:01.921984
1107 11:33:01.922086 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:33:01.925798 [Byte1]: 53
1109 11:33:01.930275
1110 11:33:01.930349 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:33:01.933348 [Byte1]: 54
1112 11:33:01.937477
1113 11:33:01.937551 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:33:01.944121 [Byte1]: 55
1115 11:33:01.944217
1116 11:33:01.947578 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:33:01.950885 [Byte1]: 56
1118 11:33:01.950979
1119 11:33:01.954058 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:33:01.957014 [Byte1]: 57
1121 11:33:01.957107
1122 11:33:01.960586 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:33:01.963940 [Byte1]: 58
1124 11:33:01.968015
1125 11:33:01.968085 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:33:01.971280 [Byte1]: 59
1127 11:33:01.975535
1128 11:33:01.975621 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:33:01.978995 [Byte1]: 60
1130 11:33:01.982909
1131 11:33:01.983001 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:33:01.986206 [Byte1]: 61
1133 11:33:01.990578
1134 11:33:01.990677 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:33:01.993895 [Byte1]: 62
1136 11:33:01.998154
1137 11:33:01.998223 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:33:02.001495 [Byte1]: 63
1139 11:33:02.006011
1140 11:33:02.006126 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:33:02.009309 [Byte1]: 64
1142 11:33:02.013803
1143 11:33:02.013900 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:33:02.016998 [Byte1]: 65
1145 11:33:02.020938
1146 11:33:02.021030 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:33:02.024287 [Byte1]: 66
1148 11:33:02.028645
1149 11:33:02.028716 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:33:02.032380 [Byte1]: 67
1151 11:33:02.036517
1152 11:33:02.036619 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:33:02.042605 [Byte1]: 68
1154 11:33:02.042699
1155 11:33:02.046141 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:33:02.049627 [Byte1]: 69
1157 11:33:02.049733
1158 11:33:02.053206 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:33:02.055941 [Byte1]: 70
1160 11:33:02.056011
1161 11:33:02.059481 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:33:02.062870 [Byte1]: 71
1163 11:33:02.066466
1164 11:33:02.066537 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:33:02.069764 [Byte1]: 72
1166 11:33:02.074458
1167 11:33:02.074529 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:33:02.077693 [Byte1]: 73
1169 11:33:02.081887
1170 11:33:02.081994 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:33:02.085511 [Byte1]: 74
1172 11:33:02.089456
1173 11:33:02.089562 Final RX Vref Byte 0 = 59 to rank0
1174 11:33:02.093191 Final RX Vref Byte 1 = 58 to rank0
1175 11:33:02.096033 Final RX Vref Byte 0 = 59 to rank1
1176 11:33:02.099677 Final RX Vref Byte 1 = 58 to rank1==
1177 11:33:02.102976 Dram Type= 6, Freq= 0, CH_0, rank 0
1178 11:33:02.109622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 11:33:02.109719 ==
1180 11:33:02.109805 DQS Delay:
1181 11:33:02.109899 DQS0 = 0, DQS1 = 0
1182 11:33:02.112778 DQM Delay:
1183 11:33:02.112878 DQM0 = 92, DQM1 = 86
1184 11:33:02.116159 DQ Delay:
1185 11:33:02.119861 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1186 11:33:02.119927 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1187 11:33:02.123033 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1188 11:33:02.126215 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1189 11:33:02.130150
1190 11:33:02.130220
1191 11:33:02.136736 [DQSOSCAuto] RK0, (LSB)MR18= 0x5248, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
1192 11:33:02.140004 CH0 RK0: MR19=606, MR18=5248
1193 11:33:02.146680 CH0_RK0: MR19=0x606, MR18=0x5248, DQSOSC=389, MR23=63, INC=97, DEC=65
1194 11:33:02.146762
1195 11:33:02.149802 ----->DramcWriteLeveling(PI) begin...
1196 11:33:02.149881 ==
1197 11:33:02.153248 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 11:33:02.156753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 11:33:02.156830 ==
1200 11:33:02.160060 Write leveling (Byte 0): 33 => 33
1201 11:33:02.163426 Write leveling (Byte 1): 31 => 31
1202 11:33:02.166803 DramcWriteLeveling(PI) end<-----
1203 11:33:02.166879
1204 11:33:02.166938 ==
1205 11:33:02.170246 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:33:02.173555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:33:02.173656 ==
1208 11:33:02.176945 [Gating] SW mode calibration
1209 11:33:02.183418 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1210 11:33:02.189922 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1211 11:33:02.193230 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 11:33:02.196455 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 11:33:02.203210 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1214 11:33:02.206680 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1215 11:33:02.209911 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:33:02.257401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:33:02.257506 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:33:02.257751 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:33:02.257819 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:33:02.258086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:33:02.258146 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:33:02.258209 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:33:02.258444 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:33:02.258506 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:33:02.258568 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:33:02.258621 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:33:02.278449 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:33:02.278712 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1229 11:33:02.278959 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1230 11:33:02.282574 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:33:02.282651 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:33:02.286041 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:33:02.288735 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:33:02.295358 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:33:02.298958 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:33:02.301837 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:33:02.309293 0 9 8 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 1)
1238 11:33:02.311913 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 11:33:02.315367 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 11:33:02.318862 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:33:02.325653 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:33:02.328953 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:33:02.332172 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:33:02.339073 0 10 4 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 0)
1245 11:33:02.342382 0 10 8 | B1->B0 | 2828 2c2c | 0 0 | (1 0) (0 0)
1246 11:33:02.345559 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:33:02.352837 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:33:02.355929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:33:02.359145 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:33:02.365721 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:33:02.369027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:33:02.372111 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1253 11:33:02.379179 0 11 8 | B1->B0 | 4343 4242 | 0 0 | (0 0) (0 0)
1254 11:33:02.382462 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 11:33:02.385898 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 11:33:02.389308 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:33:02.396040 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:33:02.398885 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:33:02.402279 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:33:02.408989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:33:02.412775 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:33:02.415718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:33:02.422895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:33:02.425578 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:33:02.428948 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:33:02.435855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:33:02.439034 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:33:02.442301 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:33:02.449362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:33:02.452307 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:33:02.455778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:33:02.462861 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:33:02.466025 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:33:02.469494 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:33:02.476235 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:33:02.479415 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1277 11:33:02.482536 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1278 11:33:02.485702 Total UI for P1: 0, mck2ui 16
1279 11:33:02.489152 best dqsien dly found for B0: ( 0, 14, 4)
1280 11:33:02.492387 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1281 11:33:02.495685 Total UI for P1: 0, mck2ui 16
1282 11:33:02.499190 best dqsien dly found for B1: ( 0, 14, 8)
1283 11:33:02.502553 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1284 11:33:02.506136 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1285 11:33:02.506225
1286 11:33:02.512706 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1287 11:33:02.516144 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 11:33:02.516258 [Gating] SW calibration Done
1289 11:33:02.519490 ==
1290 11:33:02.519594 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:33:02.526014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:33:02.526147 ==
1293 11:33:02.526249 RX Vref Scan: 0
1294 11:33:02.526332
1295 11:33:02.529525 RX Vref 0 -> 0, step: 1
1296 11:33:02.529634
1297 11:33:02.532815 RX Delay -130 -> 252, step: 16
1298 11:33:02.536173 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1299 11:33:02.539490 iDelay=222, Bit 1, Center 101 (-2 ~ 205) 208
1300 11:33:02.542926 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1301 11:33:02.549689 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1302 11:33:02.553004 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1303 11:33:02.556409 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1304 11:33:02.559670 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1305 11:33:02.562865 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1306 11:33:02.569575 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1307 11:33:02.572855 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1308 11:33:02.576428 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1309 11:33:02.579372 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1310 11:33:02.582956 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1311 11:33:02.589968 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1312 11:33:02.593215 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1313 11:33:02.596783 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1314 11:33:02.596876 ==
1315 11:33:02.599657 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 11:33:02.603044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 11:33:02.603127 ==
1318 11:33:02.606217 DQS Delay:
1319 11:33:02.606316 DQS0 = 0, DQS1 = 0
1320 11:33:02.609526 DQM Delay:
1321 11:33:02.609617 DQM0 = 94, DQM1 = 82
1322 11:33:02.609692 DQ Delay:
1323 11:33:02.612928 DQ0 =93, DQ1 =101, DQ2 =85, DQ3 =85
1324 11:33:02.616312 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1325 11:33:02.619660 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1326 11:33:02.623017 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1327 11:33:02.623086
1328 11:33:02.623143
1329 11:33:02.626294 ==
1330 11:33:02.626387 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 11:33:02.632996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 11:33:02.633089 ==
1333 11:33:02.633175
1334 11:33:02.633256
1335 11:33:02.636359 TX Vref Scan disable
1336 11:33:02.636449 == TX Byte 0 ==
1337 11:33:02.640207 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1338 11:33:02.646703 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1339 11:33:02.646797 == TX Byte 1 ==
1340 11:33:02.649721 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1341 11:33:02.656390 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1342 11:33:02.656488 ==
1343 11:33:02.659852 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 11:33:02.663175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 11:33:02.663242 ==
1346 11:33:02.676072 TX Vref=22, minBit 9, minWin=27, winSum=448
1347 11:33:02.679600 TX Vref=24, minBit 2, minWin=28, winSum=453
1348 11:33:02.683159 TX Vref=26, minBit 8, minWin=27, winSum=454
1349 11:33:02.686289 TX Vref=28, minBit 4, minWin=28, winSum=459
1350 11:33:02.689493 TX Vref=30, minBit 3, minWin=28, winSum=457
1351 11:33:02.693480 TX Vref=32, minBit 4, minWin=28, winSum=455
1352 11:33:02.699801 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1353 11:33:02.699872
1354 11:33:02.703070 Final TX Range 1 Vref 28
1355 11:33:02.703160
1356 11:33:02.703251 ==
1357 11:33:02.706356 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:33:02.709496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:33:02.709587 ==
1360 11:33:02.709669
1361 11:33:02.712934
1362 11:33:02.713039 TX Vref Scan disable
1363 11:33:02.716290 == TX Byte 0 ==
1364 11:33:02.719618 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1365 11:33:02.722918 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1366 11:33:02.726221 == TX Byte 1 ==
1367 11:33:02.729546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1368 11:33:02.733002 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1369 11:33:02.733098
1370 11:33:02.736328 [DATLAT]
1371 11:33:02.736416 Freq=800, CH0 RK1
1372 11:33:02.736500
1373 11:33:02.739723 DATLAT Default: 0xa
1374 11:33:02.739809 0, 0xFFFF, sum = 0
1375 11:33:02.743166 1, 0xFFFF, sum = 0
1376 11:33:02.743260 2, 0xFFFF, sum = 0
1377 11:33:02.746504 3, 0xFFFF, sum = 0
1378 11:33:02.746569 4, 0xFFFF, sum = 0
1379 11:33:02.749804 5, 0xFFFF, sum = 0
1380 11:33:02.749891 6, 0xFFFF, sum = 0
1381 11:33:02.753252 7, 0xFFFF, sum = 0
1382 11:33:02.753339 8, 0xFFFF, sum = 0
1383 11:33:02.756264 9, 0x0, sum = 1
1384 11:33:02.756355 10, 0x0, sum = 2
1385 11:33:02.760002 11, 0x0, sum = 3
1386 11:33:02.760067 12, 0x0, sum = 4
1387 11:33:02.762973 best_step = 10
1388 11:33:02.763036
1389 11:33:02.763095 ==
1390 11:33:02.766331 Dram Type= 6, Freq= 0, CH_0, rank 1
1391 11:33:02.770356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 11:33:02.770423 ==
1393 11:33:02.773694 RX Vref Scan: 0
1394 11:33:02.773780
1395 11:33:02.773864 RX Vref 0 -> 0, step: 1
1396 11:33:02.773941
1397 11:33:02.777054 RX Delay -79 -> 252, step: 8
1398 11:33:02.783235 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1399 11:33:02.786426 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1400 11:33:02.790269 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1401 11:33:02.793332 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1402 11:33:02.796653 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1403 11:33:02.800328 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1404 11:33:02.806912 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1405 11:33:02.809967 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1406 11:33:02.813259 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1407 11:33:02.816650 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1408 11:33:02.820119 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1409 11:33:02.826718 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1410 11:33:02.830190 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1411 11:33:02.833604 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1412 11:33:02.836848 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1413 11:33:02.840600 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1414 11:33:02.840696 ==
1415 11:33:02.843984 Dram Type= 6, Freq= 0, CH_0, rank 1
1416 11:33:02.850160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 11:33:02.850229 ==
1418 11:33:02.850284 DQS Delay:
1419 11:33:02.853420 DQS0 = 0, DQS1 = 0
1420 11:33:02.853508 DQM Delay:
1421 11:33:02.853590 DQM0 = 93, DQM1 = 84
1422 11:33:02.856817 DQ Delay:
1423 11:33:02.860168 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
1424 11:33:02.863565 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1425 11:33:02.866907 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
1426 11:33:02.870180 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1427 11:33:02.870254
1428 11:33:02.870311
1429 11:33:02.877096 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1430 11:33:02.880671 CH0 RK1: MR19=606, MR18=4B1B
1431 11:33:02.887215 CH0_RK1: MR19=0x606, MR18=0x4B1B, DQSOSC=391, MR23=63, INC=96, DEC=64
1432 11:33:02.890659 [RxdqsGatingPostProcess] freq 800
1433 11:33:02.893921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1434 11:33:02.897141 Pre-setting of DQS Precalculation
1435 11:33:02.903860 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1436 11:33:02.903935 ==
1437 11:33:02.907125 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:33:02.910703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:33:02.910779 ==
1440 11:33:02.916993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 11:33:02.923337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 11:33:02.931469 [CA 0] Center 36 (6~67) winsize 62
1443 11:33:02.934849 [CA 1] Center 36 (6~67) winsize 62
1444 11:33:02.938165 [CA 2] Center 35 (5~66) winsize 62
1445 11:33:02.941317 [CA 3] Center 34 (4~65) winsize 62
1446 11:33:02.944335 [CA 4] Center 34 (4~65) winsize 62
1447 11:33:02.947838 [CA 5] Center 34 (4~65) winsize 62
1448 11:33:02.947910
1449 11:33:02.951149 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 11:33:02.951219
1451 11:33:02.954696 [CATrainingPosCal] consider 1 rank data
1452 11:33:02.957899 u2DelayCellTimex100 = 270/100 ps
1453 11:33:02.961120 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 11:33:02.964481 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 11:33:02.967886 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1456 11:33:02.974693 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 11:33:02.978137 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 11:33:02.981466 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 11:33:02.981557
1460 11:33:02.984793 CA PerBit enable=1, Macro0, CA PI delay=34
1461 11:33:02.984874
1462 11:33:02.988130 [CBTSetCACLKResult] CA Dly = 34
1463 11:33:02.988195 CS Dly: 5 (0~36)
1464 11:33:02.988250 ==
1465 11:33:02.991197 Dram Type= 6, Freq= 0, CH_1, rank 1
1466 11:33:02.997889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 11:33:02.997981 ==
1468 11:33:03.001230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1469 11:33:03.008093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1470 11:33:03.017223 [CA 0] Center 36 (6~67) winsize 62
1471 11:33:03.020523 [CA 1] Center 37 (6~68) winsize 63
1472 11:33:03.024146 [CA 2] Center 35 (5~66) winsize 62
1473 11:33:03.027291 [CA 3] Center 34 (4~65) winsize 62
1474 11:33:03.030892 [CA 4] Center 35 (4~66) winsize 63
1475 11:33:03.033958 [CA 5] Center 34 (4~65) winsize 62
1476 11:33:03.034086
1477 11:33:03.037294 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1478 11:33:03.037391
1479 11:33:03.040736 [CATrainingPosCal] consider 2 rank data
1480 11:33:03.044170 u2DelayCellTimex100 = 270/100 ps
1481 11:33:03.047522 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 11:33:03.050954 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1483 11:33:03.057402 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1484 11:33:03.061028 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 11:33:03.064078 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 11:33:03.067317 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 11:33:03.067386
1488 11:33:03.070695 CA PerBit enable=1, Macro0, CA PI delay=34
1489 11:33:03.070771
1490 11:33:03.074303 [CBTSetCACLKResult] CA Dly = 34
1491 11:33:03.074378 CS Dly: 6 (0~38)
1492 11:33:03.074436
1493 11:33:03.077687 ----->DramcWriteLeveling(PI) begin...
1494 11:33:03.077763 ==
1495 11:33:03.080996 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 11:33:03.087720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 11:33:03.087819 ==
1498 11:33:03.091139 Write leveling (Byte 0): 29 => 29
1499 11:33:03.093871 Write leveling (Byte 1): 26 => 26
1500 11:33:03.093946 DramcWriteLeveling(PI) end<-----
1501 11:33:03.097306
1502 11:33:03.097379 ==
1503 11:33:03.100781 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 11:33:03.104171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 11:33:03.104246 ==
1506 11:33:03.107321 [Gating] SW mode calibration
1507 11:33:03.114161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1508 11:33:03.117541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1509 11:33:03.124502 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1510 11:33:03.127433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1511 11:33:03.131109 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:33:03.137429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:33:03.141321 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:33:03.144262 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:33:03.151494 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:33:03.154826 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:33:03.157651 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:33:03.161091 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:33:03.167717 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:33:03.171045 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:33:03.174856 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:33:03.181475 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:33:03.184506 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:33:03.187972 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:33:03.194388 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1526 11:33:03.197793 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1527 11:33:03.201149 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:33:03.207915 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:33:03.211435 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:33:03.214784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:33:03.221747 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:33:03.224803 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:33:03.227937 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:33:03.231714 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1535 11:33:03.238461 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1536 11:33:03.241678 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 11:33:03.244731 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:33:03.251845 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:33:03.255125 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:33:03.258229 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:33:03.264869 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:33:03.268192 0 10 4 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
1543 11:33:03.271794 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:33:03.278689 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:33:03.281479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:33:03.285021 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:33:03.288454 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:33:03.295490 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:33:03.298458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:33:03.301907 0 11 4 | B1->B0 | 2a2a 3636 | 1 0 | (1 1) (0 0)
1551 11:33:03.308962 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1552 11:33:03.311666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:33:03.315098 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:33:03.321816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:33:03.325304 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:33:03.328572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:33:03.335580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:33:03.338942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1559 11:33:03.342021 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:33:03.348882 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:33:03.352075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:33:03.356034 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:33:03.359105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:33:03.365846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:33:03.368835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:33:03.371898 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:33:03.378796 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:33:03.381938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:33:03.385893 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:33:03.392187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:33:03.395578 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:33:03.398991 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:33:03.405778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1574 11:33:03.408843 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1575 11:33:03.412713 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 11:33:03.415419 Total UI for P1: 0, mck2ui 16
1577 11:33:03.418870 best dqsien dly found for B0: ( 0, 14, 4)
1578 11:33:03.422658 Total UI for P1: 0, mck2ui 16
1579 11:33:03.425852 best dqsien dly found for B1: ( 0, 14, 2)
1580 11:33:03.429170 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1581 11:33:03.432646 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1582 11:33:03.432744
1583 11:33:03.435337 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 11:33:03.442512 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 11:33:03.442612 [Gating] SW calibration Done
1586 11:33:03.442695 ==
1587 11:33:03.445672 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 11:33:03.452351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 11:33:03.452419 ==
1590 11:33:03.452474 RX Vref Scan: 0
1591 11:33:03.452526
1592 11:33:03.455829 RX Vref 0 -> 0, step: 1
1593 11:33:03.455894
1594 11:33:03.459182 RX Delay -130 -> 252, step: 16
1595 11:33:03.462474 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 11:33:03.465873 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1597 11:33:03.469078 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1598 11:33:03.475687 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1599 11:33:03.479011 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1600 11:33:03.482177 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1601 11:33:03.485795 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1602 11:33:03.488856 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1603 11:33:03.492534 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1604 11:33:03.499042 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1605 11:33:03.502284 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1606 11:33:03.505693 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1607 11:33:03.509117 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1608 11:33:03.512568 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1609 11:33:03.519227 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1610 11:33:03.522407 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1611 11:33:03.522498 ==
1612 11:33:03.526036 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 11:33:03.528987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 11:33:03.529063 ==
1615 11:33:03.532796 DQS Delay:
1616 11:33:03.532867 DQS0 = 0, DQS1 = 0
1617 11:33:03.532921 DQM Delay:
1618 11:33:03.535942 DQM0 = 92, DQM1 = 87
1619 11:33:03.536011 DQ Delay:
1620 11:33:03.539295 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1621 11:33:03.542748 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1622 11:33:03.545911 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1623 11:33:03.549087 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1624 11:33:03.549162
1625 11:33:03.549220
1626 11:33:03.549273 ==
1627 11:33:03.552831 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 11:33:03.558893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 11:33:03.558973 ==
1630 11:33:03.559030
1631 11:33:03.559083
1632 11:33:03.559133 TX Vref Scan disable
1633 11:33:03.562879 == TX Byte 0 ==
1634 11:33:03.566326 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1635 11:33:03.569612 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1636 11:33:03.573062 == TX Byte 1 ==
1637 11:33:03.576330 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1638 11:33:03.579482 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1639 11:33:03.582946 ==
1640 11:33:03.583023 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:33:03.589514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:33:03.589589 ==
1643 11:33:03.602016 TX Vref=22, minBit 4, minWin=26, winSum=434
1644 11:33:03.605326 TX Vref=24, minBit 0, minWin=27, winSum=442
1645 11:33:03.608458 TX Vref=26, minBit 2, minWin=27, winSum=451
1646 11:33:03.612179 TX Vref=28, minBit 1, minWin=27, winSum=446
1647 11:33:03.615098 TX Vref=30, minBit 1, minWin=27, winSum=451
1648 11:33:03.618951 TX Vref=32, minBit 2, minWin=27, winSum=449
1649 11:33:03.625026 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 26
1650 11:33:03.625123
1651 11:33:03.628488 Final TX Range 1 Vref 26
1652 11:33:03.628571
1653 11:33:03.628668 ==
1654 11:33:03.631716 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 11:33:03.635512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 11:33:03.635590 ==
1657 11:33:03.635684
1658 11:33:03.635770
1659 11:33:03.638597 TX Vref Scan disable
1660 11:33:03.642190 == TX Byte 0 ==
1661 11:33:03.645166 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1662 11:33:03.648938 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1663 11:33:03.652336 == TX Byte 1 ==
1664 11:33:03.655599 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1665 11:33:03.658756 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1666 11:33:03.662401
1667 11:33:03.662499 [DATLAT]
1668 11:33:03.662575 Freq=800, CH1 RK0
1669 11:33:03.662632
1670 11:33:03.665825 DATLAT Default: 0xa
1671 11:33:03.665915 0, 0xFFFF, sum = 0
1672 11:33:03.668670 1, 0xFFFF, sum = 0
1673 11:33:03.668760 2, 0xFFFF, sum = 0
1674 11:33:03.672078 3, 0xFFFF, sum = 0
1675 11:33:03.672147 4, 0xFFFF, sum = 0
1676 11:33:03.675383 5, 0xFFFF, sum = 0
1677 11:33:03.675451 6, 0xFFFF, sum = 0
1678 11:33:03.678737 7, 0xFFFF, sum = 0
1679 11:33:03.678814 8, 0xFFFF, sum = 0
1680 11:33:03.681915 9, 0x0, sum = 1
1681 11:33:03.681997 10, 0x0, sum = 2
1682 11:33:03.685935 11, 0x0, sum = 3
1683 11:33:03.686025 12, 0x0, sum = 4
1684 11:33:03.688586 best_step = 10
1685 11:33:03.688664
1686 11:33:03.688742 ==
1687 11:33:03.691919 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 11:33:03.695339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 11:33:03.695416 ==
1690 11:33:03.698633 RX Vref Scan: 1
1691 11:33:03.698710
1692 11:33:03.698786 Set Vref Range= 32 -> 127
1693 11:33:03.698858
1694 11:33:03.701995 RX Vref 32 -> 127, step: 1
1695 11:33:03.702101
1696 11:33:03.705335 RX Delay -79 -> 252, step: 8
1697 11:33:03.705440
1698 11:33:03.708700 Set Vref, RX VrefLevel [Byte0]: 32
1699 11:33:03.712035 [Byte1]: 32
1700 11:33:03.712099
1701 11:33:03.715366 Set Vref, RX VrefLevel [Byte0]: 33
1702 11:33:03.719086 [Byte1]: 33
1703 11:33:03.722274
1704 11:33:03.722379 Set Vref, RX VrefLevel [Byte0]: 34
1705 11:33:03.725332 [Byte1]: 34
1706 11:33:03.729782
1707 11:33:03.729861 Set Vref, RX VrefLevel [Byte0]: 35
1708 11:33:03.733243 [Byte1]: 35
1709 11:33:03.737093
1710 11:33:03.737188 Set Vref, RX VrefLevel [Byte0]: 36
1711 11:33:03.740352 [Byte1]: 36
1712 11:33:03.744541
1713 11:33:03.744635 Set Vref, RX VrefLevel [Byte0]: 37
1714 11:33:03.747809 [Byte1]: 37
1715 11:33:03.752202
1716 11:33:03.752292 Set Vref, RX VrefLevel [Byte0]: 38
1717 11:33:03.755793 [Byte1]: 38
1718 11:33:03.759686
1719 11:33:03.759773 Set Vref, RX VrefLevel [Byte0]: 39
1720 11:33:03.766065 [Byte1]: 39
1721 11:33:03.766166
1722 11:33:03.769788 Set Vref, RX VrefLevel [Byte0]: 40
1723 11:33:03.773005 [Byte1]: 40
1724 11:33:03.773083
1725 11:33:03.776305 Set Vref, RX VrefLevel [Byte0]: 41
1726 11:33:03.779664 [Byte1]: 41
1727 11:33:03.779750
1728 11:33:03.783090 Set Vref, RX VrefLevel [Byte0]: 42
1729 11:33:03.786364 [Byte1]: 42
1730 11:33:03.790294
1731 11:33:03.790355 Set Vref, RX VrefLevel [Byte0]: 43
1732 11:33:03.793617 [Byte1]: 43
1733 11:33:03.797814
1734 11:33:03.797889 Set Vref, RX VrefLevel [Byte0]: 44
1735 11:33:03.800915 [Byte1]: 44
1736 11:33:03.804907
1737 11:33:03.804982 Set Vref, RX VrefLevel [Byte0]: 45
1738 11:33:03.808257 [Byte1]: 45
1739 11:33:03.812957
1740 11:33:03.813032 Set Vref, RX VrefLevel [Byte0]: 46
1741 11:33:03.816087 [Byte1]: 46
1742 11:33:03.820193
1743 11:33:03.820268 Set Vref, RX VrefLevel [Byte0]: 47
1744 11:33:03.823484 [Byte1]: 47
1745 11:33:03.827610
1746 11:33:03.827684 Set Vref, RX VrefLevel [Byte0]: 48
1747 11:33:03.830854 [Byte1]: 48
1748 11:33:03.835339
1749 11:33:03.835414 Set Vref, RX VrefLevel [Byte0]: 49
1750 11:33:03.838393 [Byte1]: 49
1751 11:33:03.843017
1752 11:33:03.843093 Set Vref, RX VrefLevel [Byte0]: 50
1753 11:33:03.846422 [Byte1]: 50
1754 11:33:03.850546
1755 11:33:03.850621 Set Vref, RX VrefLevel [Byte0]: 51
1756 11:33:03.853962 [Byte1]: 51
1757 11:33:03.857966
1758 11:33:03.858075 Set Vref, RX VrefLevel [Byte0]: 52
1759 11:33:03.861154 [Byte1]: 52
1760 11:33:03.865405
1761 11:33:03.865480 Set Vref, RX VrefLevel [Byte0]: 53
1762 11:33:03.868572 [Byte1]: 53
1763 11:33:03.873041
1764 11:33:03.873116 Set Vref, RX VrefLevel [Byte0]: 54
1765 11:33:03.876251 [Byte1]: 54
1766 11:33:03.880452
1767 11:33:03.880527 Set Vref, RX VrefLevel [Byte0]: 55
1768 11:33:03.884160 [Byte1]: 55
1769 11:33:03.888125
1770 11:33:03.888224 Set Vref, RX VrefLevel [Byte0]: 56
1771 11:33:03.891364 [Byte1]: 56
1772 11:33:03.896000
1773 11:33:03.896085 Set Vref, RX VrefLevel [Byte0]: 57
1774 11:33:03.899334 [Byte1]: 57
1775 11:33:03.903475
1776 11:33:03.903577 Set Vref, RX VrefLevel [Byte0]: 58
1777 11:33:03.906914 [Byte1]: 58
1778 11:33:03.910871
1779 11:33:03.910947 Set Vref, RX VrefLevel [Byte0]: 59
1780 11:33:03.914329 [Byte1]: 59
1781 11:33:03.918331
1782 11:33:03.918406 Set Vref, RX VrefLevel [Byte0]: 60
1783 11:33:03.921699 [Byte1]: 60
1784 11:33:03.926240
1785 11:33:03.926315 Set Vref, RX VrefLevel [Byte0]: 61
1786 11:33:03.929299 [Byte1]: 61
1787 11:33:03.933366
1788 11:33:03.933441 Set Vref, RX VrefLevel [Byte0]: 62
1789 11:33:03.936840 [Byte1]: 62
1790 11:33:03.940904
1791 11:33:03.940979 Set Vref, RX VrefLevel [Byte0]: 63
1792 11:33:03.944354 [Byte1]: 63
1793 11:33:03.948741
1794 11:33:03.948816 Set Vref, RX VrefLevel [Byte0]: 64
1795 11:33:03.951848 [Byte1]: 64
1796 11:33:03.956051
1797 11:33:03.956126 Set Vref, RX VrefLevel [Byte0]: 65
1798 11:33:03.959576 [Byte1]: 65
1799 11:33:03.963687
1800 11:33:03.963762 Set Vref, RX VrefLevel [Byte0]: 66
1801 11:33:03.967136 [Byte1]: 66
1802 11:33:03.970949
1803 11:33:03.971023 Set Vref, RX VrefLevel [Byte0]: 67
1804 11:33:03.974629 [Byte1]: 67
1805 11:33:03.978585
1806 11:33:03.978685 Set Vref, RX VrefLevel [Byte0]: 68
1807 11:33:03.981793 [Byte1]: 68
1808 11:33:03.986347
1809 11:33:03.986448 Set Vref, RX VrefLevel [Byte0]: 69
1810 11:33:03.989623 [Byte1]: 69
1811 11:33:03.994166
1812 11:33:03.994248 Set Vref, RX VrefLevel [Byte0]: 70
1813 11:33:03.997357 [Byte1]: 70
1814 11:33:04.001188
1815 11:33:04.001258 Final RX Vref Byte 0 = 59 to rank0
1816 11:33:04.005165 Final RX Vref Byte 1 = 55 to rank0
1817 11:33:04.008291 Final RX Vref Byte 0 = 59 to rank1
1818 11:33:04.011719 Final RX Vref Byte 1 = 55 to rank1==
1819 11:33:04.015074 Dram Type= 6, Freq= 0, CH_1, rank 0
1820 11:33:04.021292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 11:33:04.021388 ==
1822 11:33:04.021470 DQS Delay:
1823 11:33:04.021527 DQS0 = 0, DQS1 = 0
1824 11:33:04.024537 DQM Delay:
1825 11:33:04.024600 DQM0 = 94, DQM1 = 90
1826 11:33:04.028074 DQ Delay:
1827 11:33:04.031275 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1828 11:33:04.035064 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =92
1829 11:33:04.038214 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1830 11:33:04.041716 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1831 11:33:04.041806
1832 11:33:04.041888
1833 11:33:04.047816 [DQSOSCAuto] RK0, (LSB)MR18= 0x3652, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1834 11:33:04.051179 CH1 RK0: MR19=606, MR18=3652
1835 11:33:04.057946 CH1_RK0: MR19=0x606, MR18=0x3652, DQSOSC=389, MR23=63, INC=97, DEC=65
1836 11:33:04.058077
1837 11:33:04.061839 ----->DramcWriteLeveling(PI) begin...
1838 11:33:04.061926 ==
1839 11:33:04.064797 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 11:33:04.067962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 11:33:04.068030 ==
1842 11:33:04.071588 Write leveling (Byte 0): 27 => 27
1843 11:33:04.074766 Write leveling (Byte 1): 28 => 28
1844 11:33:04.077933 DramcWriteLeveling(PI) end<-----
1845 11:33:04.078059
1846 11:33:04.078142 ==
1847 11:33:04.081672 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 11:33:04.084779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 11:33:04.084870 ==
1850 11:33:04.088010 [Gating] SW mode calibration
1851 11:33:04.095027 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1852 11:33:04.101574 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1853 11:33:04.104839 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1854 11:33:04.108035 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1855 11:33:04.114624 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:33:04.117961 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:33:04.121289 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:33:04.128700 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:33:04.131433 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:33:04.134896 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:33:04.141411 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:33:04.145304 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:33:04.148717 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:33:04.154719 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:33:04.158123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:33:04.161514 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:33:04.164924 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:33:04.171545 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:33:04.174753 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1870 11:33:04.178180 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 11:33:04.184961 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:33:04.188337 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:33:04.191616 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:33:04.198129 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:33:04.201898 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:33:04.204848 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:33:04.211850 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:33:04.215284 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1879 11:33:04.218349 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1880 11:33:04.225291 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 11:33:04.228629 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 11:33:04.231985 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 11:33:04.238079 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 11:33:04.241484 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 11:33:04.244718 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 11:33:04.251743 0 10 4 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 1)
1887 11:33:04.255053 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1888 11:33:04.258404 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:33:04.261799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:33:04.268764 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:33:04.271443 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:33:04.275380 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:33:04.282130 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1894 11:33:04.284782 0 11 4 | B1->B0 | 3737 2f2f | 0 0 | (0 0) (0 0)
1895 11:33:04.288231 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1896 11:33:04.295412 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 11:33:04.298453 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 11:33:04.302134 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 11:33:04.308512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 11:33:04.311808 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 11:33:04.315248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1902 11:33:04.321729 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1903 11:33:04.325043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1904 11:33:04.328773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:33:04.332119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:33:04.338932 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:33:04.341861 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:33:04.345647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:33:04.352362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:33:04.355666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:33:04.359038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:33:04.365843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:33:04.369175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:33:04.372628 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:33:04.379328 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:33:04.382747 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:33:04.385468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1918 11:33:04.388894 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1919 11:33:04.395686 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:33:04.398985 Total UI for P1: 0, mck2ui 16
1921 11:33:04.402462 best dqsien dly found for B0: ( 0, 14, 2)
1922 11:33:04.405919 Total UI for P1: 0, mck2ui 16
1923 11:33:04.409134 best dqsien dly found for B1: ( 0, 14, 2)
1924 11:33:04.412268 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1925 11:33:04.415569 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1926 11:33:04.415663
1927 11:33:04.418819 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1928 11:33:04.422416 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1929 11:33:04.425380 [Gating] SW calibration Done
1930 11:33:04.425470 ==
1931 11:33:04.428974 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:33:04.432375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:33:04.432472 ==
1934 11:33:04.436012 RX Vref Scan: 0
1935 11:33:04.436132
1936 11:33:04.436190 RX Vref 0 -> 0, step: 1
1937 11:33:04.436318
1938 11:33:04.438995 RX Delay -130 -> 252, step: 16
1939 11:33:04.442689 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1940 11:33:04.449201 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1941 11:33:04.452437 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1942 11:33:04.455658 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1943 11:33:04.459324 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1944 11:33:04.462284 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1945 11:33:04.469028 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1946 11:33:04.472760 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1947 11:33:04.476106 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1948 11:33:04.479452 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1949 11:33:04.482643 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1950 11:33:04.489435 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1951 11:33:04.492730 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1952 11:33:04.495538 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1953 11:33:04.499528 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1954 11:33:04.502348 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1955 11:33:04.505639 ==
1956 11:33:04.509012 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:33:04.512362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:33:04.512461 ==
1959 11:33:04.512544 DQS Delay:
1960 11:33:04.515732 DQS0 = 0, DQS1 = 0
1961 11:33:04.515824 DQM Delay:
1962 11:33:04.519614 DQM0 = 93, DQM1 = 86
1963 11:33:04.519700 DQ Delay:
1964 11:33:04.522663 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =85
1965 11:33:04.525997 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1966 11:33:04.529486 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1967 11:33:04.532936 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1968 11:33:04.533030
1969 11:33:04.533112
1970 11:33:04.533201 ==
1971 11:33:04.536134 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:33:04.539294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:33:04.539365 ==
1974 11:33:04.539437
1975 11:33:04.539493
1976 11:33:04.542457 TX Vref Scan disable
1977 11:33:04.545964 == TX Byte 0 ==
1978 11:33:04.549495 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1979 11:33:04.552558 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1980 11:33:04.556017 == TX Byte 1 ==
1981 11:33:04.559941 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1982 11:33:04.563083 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1983 11:33:04.563152 ==
1984 11:33:04.566138 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:33:04.569568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:33:04.569662 ==
1987 11:33:04.583507 TX Vref=22, minBit 2, minWin=26, winSum=442
1988 11:33:04.587294 TX Vref=24, minBit 0, minWin=27, winSum=445
1989 11:33:04.590249 TX Vref=26, minBit 1, minWin=27, winSum=448
1990 11:33:04.593678 TX Vref=28, minBit 2, minWin=27, winSum=452
1991 11:33:04.596792 TX Vref=30, minBit 2, minWin=27, winSum=451
1992 11:33:04.600306 TX Vref=32, minBit 2, minWin=27, winSum=449
1993 11:33:04.606903 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1994 11:33:04.607047
1995 11:33:04.610524 Final TX Range 1 Vref 28
1996 11:33:04.610619
1997 11:33:04.610706 ==
1998 11:33:04.613703 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 11:33:04.617185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 11:33:04.617283 ==
2001 11:33:04.617368
2002 11:33:04.617460
2003 11:33:04.620632 TX Vref Scan disable
2004 11:33:04.623779 == TX Byte 0 ==
2005 11:33:04.627204 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 11:33:04.630312 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 11:33:04.634285 == TX Byte 1 ==
2008 11:33:04.637031 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2009 11:33:04.640259 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2010 11:33:04.640354
2011 11:33:04.643641 [DATLAT]
2012 11:33:04.643746 Freq=800, CH1 RK1
2013 11:33:04.643833
2014 11:33:04.647000 DATLAT Default: 0xa
2015 11:33:04.647098 0, 0xFFFF, sum = 0
2016 11:33:04.650391 1, 0xFFFF, sum = 0
2017 11:33:04.650483 2, 0xFFFF, sum = 0
2018 11:33:04.653652 3, 0xFFFF, sum = 0
2019 11:33:04.653752 4, 0xFFFF, sum = 0
2020 11:33:04.656930 5, 0xFFFF, sum = 0
2021 11:33:04.657025 6, 0xFFFF, sum = 0
2022 11:33:04.660218 7, 0xFFFF, sum = 0
2023 11:33:04.660320 8, 0xFFFF, sum = 0
2024 11:33:04.663956 9, 0x0, sum = 1
2025 11:33:04.664049 10, 0x0, sum = 2
2026 11:33:04.667696 11, 0x0, sum = 3
2027 11:33:04.667790 12, 0x0, sum = 4
2028 11:33:04.670647 best_step = 10
2029 11:33:04.670715
2030 11:33:04.670770 ==
2031 11:33:04.673778 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:33:04.677305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:33:04.677407 ==
2034 11:33:04.680637 RX Vref Scan: 0
2035 11:33:04.680739
2036 11:33:04.680824 RX Vref 0 -> 0, step: 1
2037 11:33:04.680910
2038 11:33:04.683944 RX Delay -79 -> 252, step: 8
2039 11:33:04.690583 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2040 11:33:04.693830 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2041 11:33:04.697402 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2042 11:33:04.700486 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2043 11:33:04.703641 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2044 11:33:04.707321 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2045 11:33:04.714170 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2046 11:33:04.717580 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2047 11:33:04.720223 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2048 11:33:04.724295 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2049 11:33:04.727632 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2050 11:33:04.731052 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2051 11:33:04.737441 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2052 11:33:04.740785 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2053 11:33:04.743949 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2054 11:33:04.747374 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2055 11:33:04.747440 ==
2056 11:33:04.750815 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 11:33:04.757556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 11:33:04.757631 ==
2059 11:33:04.757690 DQS Delay:
2060 11:33:04.757745 DQS0 = 0, DQS1 = 0
2061 11:33:04.760877 DQM Delay:
2062 11:33:04.760966 DQM0 = 97, DQM1 = 91
2063 11:33:04.764297 DQ Delay:
2064 11:33:04.767705 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2065 11:33:04.771027 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2066 11:33:04.774283 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2067 11:33:04.777594 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2068 11:33:04.777686
2069 11:33:04.777769
2070 11:33:04.784490 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
2071 11:33:04.787316 CH1 RK1: MR19=606, MR18=4F18
2072 11:33:04.794252 CH1_RK1: MR19=0x606, MR18=0x4F18, DQSOSC=390, MR23=63, INC=97, DEC=64
2073 11:33:04.797410 [RxdqsGatingPostProcess] freq 800
2074 11:33:04.800666 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 11:33:04.803956 Pre-setting of DQS Precalculation
2076 11:33:04.810798 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 11:33:04.817263 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 11:33:04.824240 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 11:33:04.824314
2080 11:33:04.824373
2081 11:33:04.827775 [Calibration Summary] 1600 Mbps
2082 11:33:04.827869 CH 0, Rank 0
2083 11:33:04.831091 SW Impedance : PASS
2084 11:33:04.834235 DUTY Scan : NO K
2085 11:33:04.834325 ZQ Calibration : PASS
2086 11:33:04.837692 Jitter Meter : NO K
2087 11:33:04.840994 CBT Training : PASS
2088 11:33:04.841095 Write leveling : PASS
2089 11:33:04.844256 RX DQS gating : PASS
2090 11:33:04.844358 RX DQ/DQS(RDDQC) : PASS
2091 11:33:04.847566 TX DQ/DQS : PASS
2092 11:33:04.850759 RX DATLAT : PASS
2093 11:33:04.850831 RX DQ/DQS(Engine): PASS
2094 11:33:04.854215 TX OE : NO K
2095 11:33:04.854315 All Pass.
2096 11:33:04.854400
2097 11:33:04.857503 CH 0, Rank 1
2098 11:33:04.857598 SW Impedance : PASS
2099 11:33:04.860837 DUTY Scan : NO K
2100 11:33:04.864256 ZQ Calibration : PASS
2101 11:33:04.864360 Jitter Meter : NO K
2102 11:33:04.867729 CBT Training : PASS
2103 11:33:04.870985 Write leveling : PASS
2104 11:33:04.871083 RX DQS gating : PASS
2105 11:33:04.874387 RX DQ/DQS(RDDQC) : PASS
2106 11:33:04.877625 TX DQ/DQS : PASS
2107 11:33:04.877728 RX DATLAT : PASS
2108 11:33:04.880841 RX DQ/DQS(Engine): PASS
2109 11:33:04.880938 TX OE : NO K
2110 11:33:04.884129 All Pass.
2111 11:33:04.884241
2112 11:33:04.884341 CH 1, Rank 0
2113 11:33:04.887564 SW Impedance : PASS
2114 11:33:04.887663 DUTY Scan : NO K
2115 11:33:04.890882 ZQ Calibration : PASS
2116 11:33:04.894308 Jitter Meter : NO K
2117 11:33:04.894379 CBT Training : PASS
2118 11:33:04.897911 Write leveling : PASS
2119 11:33:04.901212 RX DQS gating : PASS
2120 11:33:04.901313 RX DQ/DQS(RDDQC) : PASS
2121 11:33:04.904538 TX DQ/DQS : PASS
2122 11:33:04.907662 RX DATLAT : PASS
2123 11:33:04.907756 RX DQ/DQS(Engine): PASS
2124 11:33:04.910812 TX OE : NO K
2125 11:33:04.910902 All Pass.
2126 11:33:04.910996
2127 11:33:04.914201 CH 1, Rank 1
2128 11:33:04.914298 SW Impedance : PASS
2129 11:33:04.917638 DUTY Scan : NO K
2130 11:33:04.921155 ZQ Calibration : PASS
2131 11:33:04.921247 Jitter Meter : NO K
2132 11:33:04.924473 CBT Training : PASS
2133 11:33:04.924566 Write leveling : PASS
2134 11:33:04.927887 RX DQS gating : PASS
2135 11:33:04.931163 RX DQ/DQS(RDDQC) : PASS
2136 11:33:04.931261 TX DQ/DQS : PASS
2137 11:33:04.934447 RX DATLAT : PASS
2138 11:33:04.937759 RX DQ/DQS(Engine): PASS
2139 11:33:04.937849 TX OE : NO K
2140 11:33:04.940850 All Pass.
2141 11:33:04.940941
2142 11:33:04.941022 DramC Write-DBI off
2143 11:33:04.944387 PER_BANK_REFRESH: Hybrid Mode
2144 11:33:04.944485 TX_TRACKING: ON
2145 11:33:04.947667 [GetDramInforAfterCalByMRR] Vendor 6.
2146 11:33:04.954533 [GetDramInforAfterCalByMRR] Revision 606.
2147 11:33:04.957655 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 11:33:04.957765 MR0 0x3b3b
2149 11:33:04.957858 MR8 0x5151
2150 11:33:04.961336 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 11:33:04.961424
2152 11:33:04.964335 MR0 0x3b3b
2153 11:33:04.964425 MR8 0x5151
2154 11:33:04.967498 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 11:33:04.967591
2156 11:33:04.978268 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 11:33:04.980982 [FAST_K] Save calibration result to emmc
2158 11:33:04.984400 [FAST_K] Save calibration result to emmc
2159 11:33:04.988135 dram_init: config_dvfs: 1
2160 11:33:04.991487 dramc_set_vcore_voltage set vcore to 662500
2161 11:33:04.994896 Read voltage for 1200, 2
2162 11:33:04.994988 Vio18 = 0
2163 11:33:04.995080 Vcore = 662500
2164 11:33:04.997682 Vdram = 0
2165 11:33:04.997777 Vddq = 0
2166 11:33:04.997861 Vmddr = 0
2167 11:33:05.004943 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 11:33:05.008090 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 11:33:05.011332 MEM_TYPE=3, freq_sel=15
2170 11:33:05.014541 sv_algorithm_assistance_LP4_1600
2171 11:33:05.017671 ============ PULL DRAM RESETB DOWN ============
2172 11:33:05.021034 ========== PULL DRAM RESETB DOWN end =========
2173 11:33:05.027783 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 11:33:05.031036 ===================================
2175 11:33:05.031146 LPDDR4 DRAM CONFIGURATION
2176 11:33:05.034382 ===================================
2177 11:33:05.037906 EX_ROW_EN[0] = 0x0
2178 11:33:05.041196 EX_ROW_EN[1] = 0x0
2179 11:33:05.041286 LP4Y_EN = 0x0
2180 11:33:05.044511 WORK_FSP = 0x0
2181 11:33:05.044609 WL = 0x4
2182 11:33:05.047955 RL = 0x4
2183 11:33:05.048045 BL = 0x2
2184 11:33:05.051240 RPST = 0x0
2185 11:33:05.051332 RD_PRE = 0x0
2186 11:33:05.055113 WR_PRE = 0x1
2187 11:33:05.055207 WR_PST = 0x0
2188 11:33:05.058331 DBI_WR = 0x0
2189 11:33:05.058415 DBI_RD = 0x0
2190 11:33:05.061541 OTF = 0x1
2191 11:33:05.064669 ===================================
2192 11:33:05.068296 ===================================
2193 11:33:05.068395 ANA top config
2194 11:33:05.071407 ===================================
2195 11:33:05.075064 DLL_ASYNC_EN = 0
2196 11:33:05.077948 ALL_SLAVE_EN = 0
2197 11:33:05.078064 NEW_RANK_MODE = 1
2198 11:33:05.081223 DLL_IDLE_MODE = 1
2199 11:33:05.084932 LP45_APHY_COMB_EN = 1
2200 11:33:05.088238 TX_ODT_DIS = 1
2201 11:33:05.088346 NEW_8X_MODE = 1
2202 11:33:05.091394 ===================================
2203 11:33:05.095132 ===================================
2204 11:33:05.098377 data_rate = 2400
2205 11:33:05.101899 CKR = 1
2206 11:33:05.105196 DQ_P2S_RATIO = 8
2207 11:33:05.108340 ===================================
2208 11:33:05.111816 CA_P2S_RATIO = 8
2209 11:33:05.115127 DQ_CA_OPEN = 0
2210 11:33:05.115217 DQ_SEMI_OPEN = 0
2211 11:33:05.118457 CA_SEMI_OPEN = 0
2212 11:33:05.121804 CA_FULL_RATE = 0
2213 11:33:05.125062 DQ_CKDIV4_EN = 0
2214 11:33:05.128407 CA_CKDIV4_EN = 0
2215 11:33:05.128487 CA_PREDIV_EN = 0
2216 11:33:05.132039 PH8_DLY = 17
2217 11:33:05.135352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 11:33:05.138790 DQ_AAMCK_DIV = 4
2219 11:33:05.142235 CA_AAMCK_DIV = 4
2220 11:33:05.145515 CA_ADMCK_DIV = 4
2221 11:33:05.145582 DQ_TRACK_CA_EN = 0
2222 11:33:05.148827 CA_PICK = 1200
2223 11:33:05.152234 CA_MCKIO = 1200
2224 11:33:05.154957 MCKIO_SEMI = 0
2225 11:33:05.158662 PLL_FREQ = 2366
2226 11:33:05.162146 DQ_UI_PI_RATIO = 32
2227 11:33:05.165501 CA_UI_PI_RATIO = 0
2228 11:33:05.168912 ===================================
2229 11:33:05.172254 ===================================
2230 11:33:05.172322 memory_type:LPDDR4
2231 11:33:05.175451 GP_NUM : 10
2232 11:33:05.178426 SRAM_EN : 1
2233 11:33:05.178537 MD32_EN : 0
2234 11:33:05.181737 ===================================
2235 11:33:05.185069 [ANA_INIT] >>>>>>>>>>>>>>
2236 11:33:05.188848 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 11:33:05.191840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 11:33:05.195090 ===================================
2239 11:33:05.198603 data_rate = 2400,PCW = 0X5b00
2240 11:33:05.201826 ===================================
2241 11:33:05.205433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 11:33:05.208996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 11:33:05.215435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 11:33:05.218556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 11:33:05.221925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 11:33:05.225048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 11:33:05.228375 [ANA_INIT] flow start
2248 11:33:05.232365 [ANA_INIT] PLL >>>>>>>>
2249 11:33:05.232469 [ANA_INIT] PLL <<<<<<<<
2250 11:33:05.235168 [ANA_INIT] MIDPI >>>>>>>>
2251 11:33:05.239037 [ANA_INIT] MIDPI <<<<<<<<
2252 11:33:05.239113 [ANA_INIT] DLL >>>>>>>>
2253 11:33:05.241870 [ANA_INIT] DLL <<<<<<<<
2254 11:33:05.245330 [ANA_INIT] flow end
2255 11:33:05.248727 ============ LP4 DIFF to SE enter ============
2256 11:33:05.252171 ============ LP4 DIFF to SE exit ============
2257 11:33:05.255626 [ANA_INIT] <<<<<<<<<<<<<
2258 11:33:05.259103 [Flow] Enable top DCM control >>>>>
2259 11:33:05.262387 [Flow] Enable top DCM control <<<<<
2260 11:33:05.265545 Enable DLL master slave shuffle
2261 11:33:05.268924 ==============================================================
2262 11:33:05.272311 Gating Mode config
2263 11:33:05.275730 ==============================================================
2264 11:33:05.279681 Config description:
2265 11:33:05.289435 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 11:33:05.296007 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 11:33:05.299322 SELPH_MODE 0: By rank 1: By Phase
2268 11:33:05.305846 ==============================================================
2269 11:33:05.309178 GAT_TRACK_EN = 1
2270 11:33:05.313182 RX_GATING_MODE = 2
2271 11:33:05.316294 RX_GATING_TRACK_MODE = 2
2272 11:33:05.316387 SELPH_MODE = 1
2273 11:33:05.319738 PICG_EARLY_EN = 1
2274 11:33:05.322863 VALID_LAT_VALUE = 1
2275 11:33:05.329364 ==============================================================
2276 11:33:05.332922 Enter into Gating configuration >>>>
2277 11:33:05.335735 Exit from Gating configuration <<<<
2278 11:33:05.339166 Enter into DVFS_PRE_config >>>>>
2279 11:33:05.349662 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 11:33:05.352809 Exit from DVFS_PRE_config <<<<<
2281 11:33:05.356340 Enter into PICG configuration >>>>
2282 11:33:05.359729 Exit from PICG configuration <<<<
2283 11:33:05.362522 [RX_INPUT] configuration >>>>>
2284 11:33:05.366460 [RX_INPUT] configuration <<<<<
2285 11:33:05.369739 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 11:33:05.376296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 11:33:05.383016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 11:33:05.389169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 11:33:05.392996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 11:33:05.399361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 11:33:05.402617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 11:33:05.409154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 11:33:05.412532 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 11:33:05.415805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 11:33:05.419754 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 11:33:05.425821 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 11:33:05.429251 ===================================
2298 11:33:05.429350 LPDDR4 DRAM CONFIGURATION
2299 11:33:05.433194 ===================================
2300 11:33:05.436461 EX_ROW_EN[0] = 0x0
2301 11:33:05.439639 EX_ROW_EN[1] = 0x0
2302 11:33:05.439741 LP4Y_EN = 0x0
2303 11:33:05.442784 WORK_FSP = 0x0
2304 11:33:05.442882 WL = 0x4
2305 11:33:05.446151 RL = 0x4
2306 11:33:05.446247 BL = 0x2
2307 11:33:05.449376 RPST = 0x0
2308 11:33:05.449478 RD_PRE = 0x0
2309 11:33:05.452717 WR_PRE = 0x1
2310 11:33:05.452788 WR_PST = 0x0
2311 11:33:05.456251 DBI_WR = 0x0
2312 11:33:05.456346 DBI_RD = 0x0
2313 11:33:05.459560 OTF = 0x1
2314 11:33:05.462922 ===================================
2315 11:33:05.466275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 11:33:05.469939 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 11:33:05.476371 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 11:33:05.479481 ===================================
2319 11:33:05.479588 LPDDR4 DRAM CONFIGURATION
2320 11:33:05.482834 ===================================
2321 11:33:05.486255 EX_ROW_EN[0] = 0x10
2322 11:33:05.486358 EX_ROW_EN[1] = 0x0
2323 11:33:05.489467 LP4Y_EN = 0x0
2324 11:33:05.489565 WORK_FSP = 0x0
2325 11:33:05.492892 WL = 0x4
2326 11:33:05.492984 RL = 0x4
2327 11:33:05.496184 BL = 0x2
2328 11:33:05.499392 RPST = 0x0
2329 11:33:05.499475 RD_PRE = 0x0
2330 11:33:05.502762 WR_PRE = 0x1
2331 11:33:05.502835 WR_PST = 0x0
2332 11:33:05.506524 DBI_WR = 0x0
2333 11:33:05.506621 DBI_RD = 0x0
2334 11:33:05.509665 OTF = 0x1
2335 11:33:05.513313 ===================================
2336 11:33:05.516768 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 11:33:05.519880 ==
2338 11:33:05.519977 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 11:33:05.526368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 11:33:05.526467 ==
2341 11:33:05.529830 [Duty_Offset_Calibration]
2342 11:33:05.529931 B0:2 B1:1 CA:1
2343 11:33:05.530032
2344 11:33:05.533158 [DutyScan_Calibration_Flow] k_type=0
2345 11:33:05.542518
2346 11:33:05.542623 ==CLK 0==
2347 11:33:05.545808 Final CLK duty delay cell = 0
2348 11:33:05.548934 [0] MAX Duty = 5187%(X100), DQS PI = 24
2349 11:33:05.552128 [0] MIN Duty = 4844%(X100), DQS PI = 48
2350 11:33:05.552233 [0] AVG Duty = 5015%(X100)
2351 11:33:05.555472
2352 11:33:05.558884 CH0 CLK Duty spec in!! Max-Min= 343%
2353 11:33:05.562268 [DutyScan_Calibration_Flow] ====Done====
2354 11:33:05.562342
2355 11:33:05.565483 [DutyScan_Calibration_Flow] k_type=1
2356 11:33:05.580847
2357 11:33:05.580942 ==DQS 0 ==
2358 11:33:05.584328 Final DQS duty delay cell = -4
2359 11:33:05.587768 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2360 11:33:05.591229 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2361 11:33:05.594351 [-4] AVG Duty = 4937%(X100)
2362 11:33:05.594445
2363 11:33:05.594531 ==DQS 1 ==
2364 11:33:05.597727 Final DQS duty delay cell = 0
2365 11:33:05.601071 [0] MAX Duty = 5156%(X100), DQS PI = 62
2366 11:33:05.604418 [0] MIN Duty = 5000%(X100), DQS PI = 32
2367 11:33:05.607784 [0] AVG Duty = 5078%(X100)
2368 11:33:05.607879
2369 11:33:05.611200 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2370 11:33:05.611301
2371 11:33:05.614390 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2372 11:33:05.617427 [DutyScan_Calibration_Flow] ====Done====
2373 11:33:05.617521
2374 11:33:05.621259 [DutyScan_Calibration_Flow] k_type=3
2375 11:33:05.637593
2376 11:33:05.637699 ==DQM 0 ==
2377 11:33:05.641556 Final DQM duty delay cell = 0
2378 11:33:05.644253 [0] MAX Duty = 5156%(X100), DQS PI = 30
2379 11:33:05.647814 [0] MIN Duty = 4875%(X100), DQS PI = 58
2380 11:33:05.651138 [0] AVG Duty = 5015%(X100)
2381 11:33:05.651211
2382 11:33:05.651290 ==DQM 1 ==
2383 11:33:05.654613 Final DQM duty delay cell = 0
2384 11:33:05.657728 [0] MAX Duty = 5093%(X100), DQS PI = 0
2385 11:33:05.660983 [0] MIN Duty = 5031%(X100), DQS PI = 14
2386 11:33:05.661085 [0] AVG Duty = 5062%(X100)
2387 11:33:05.664239
2388 11:33:05.667694 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2389 11:33:05.667790
2390 11:33:05.670942 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2391 11:33:05.674992 [DutyScan_Calibration_Flow] ====Done====
2392 11:33:05.675062
2393 11:33:05.678089 [DutyScan_Calibration_Flow] k_type=2
2394 11:33:05.693890
2395 11:33:05.693988 ==DQ 0 ==
2396 11:33:05.697740 Final DQ duty delay cell = 0
2397 11:33:05.701597 [0] MAX Duty = 5031%(X100), DQS PI = 26
2398 11:33:05.704136 [0] MIN Duty = 4844%(X100), DQS PI = 62
2399 11:33:05.704230 [0] AVG Duty = 4937%(X100)
2400 11:33:05.704323
2401 11:33:05.707886 ==DQ 1 ==
2402 11:33:05.710782 Final DQ duty delay cell = 0
2403 11:33:05.714253 [0] MAX Duty = 5093%(X100), DQS PI = 24
2404 11:33:05.717656 [0] MIN Duty = 4907%(X100), DQS PI = 36
2405 11:33:05.717751 [0] AVG Duty = 5000%(X100)
2406 11:33:05.717839
2407 11:33:05.720829 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2408 11:33:05.724124
2409 11:33:05.724222 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2410 11:33:05.731233 [DutyScan_Calibration_Flow] ====Done====
2411 11:33:05.731306 ==
2412 11:33:05.734662 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 11:33:05.737745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 11:33:05.737835 ==
2415 11:33:05.740901 [Duty_Offset_Calibration]
2416 11:33:05.740969 B0:1 B1:0 CA:0
2417 11:33:05.741024
2418 11:33:05.744599 [DutyScan_Calibration_Flow] k_type=0
2419 11:33:05.753477
2420 11:33:05.753567 ==CLK 0==
2421 11:33:05.756841 Final CLK duty delay cell = -4
2422 11:33:05.760221 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2423 11:33:05.763498 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2424 11:33:05.766908 [-4] AVG Duty = 4953%(X100)
2425 11:33:05.766976
2426 11:33:05.770060 CH1 CLK Duty spec in!! Max-Min= 93%
2427 11:33:05.773296 [DutyScan_Calibration_Flow] ====Done====
2428 11:33:05.773362
2429 11:33:05.776721 [DutyScan_Calibration_Flow] k_type=1
2430 11:33:05.792920
2431 11:33:05.792998 ==DQS 0 ==
2432 11:33:05.796856 Final DQS duty delay cell = 0
2433 11:33:05.799548 [0] MAX Duty = 5062%(X100), DQS PI = 56
2434 11:33:05.802987 [0] MIN Duty = 4906%(X100), DQS PI = 6
2435 11:33:05.803074 [0] AVG Duty = 4984%(X100)
2436 11:33:05.803158
2437 11:33:05.806264 ==DQS 1 ==
2438 11:33:05.809631 Final DQS duty delay cell = 0
2439 11:33:05.812804 [0] MAX Duty = 5187%(X100), DQS PI = 52
2440 11:33:05.816699 [0] MIN Duty = 4938%(X100), DQS PI = 42
2441 11:33:05.816794 [0] AVG Duty = 5062%(X100)
2442 11:33:05.816876
2443 11:33:05.822951 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2444 11:33:05.823052
2445 11:33:05.826704 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2446 11:33:05.829609 [DutyScan_Calibration_Flow] ====Done====
2447 11:33:05.829697
2448 11:33:05.833060 [DutyScan_Calibration_Flow] k_type=3
2449 11:33:05.849674
2450 11:33:05.849790 ==DQM 0 ==
2451 11:33:05.852732 Final DQM duty delay cell = 0
2452 11:33:05.856579 [0] MAX Duty = 5156%(X100), DQS PI = 38
2453 11:33:05.859994 [0] MIN Duty = 5031%(X100), DQS PI = 28
2454 11:33:05.860073 [0] AVG Duty = 5093%(X100)
2455 11:33:05.863366
2456 11:33:05.863463 ==DQM 1 ==
2457 11:33:05.866060 Final DQM duty delay cell = 0
2458 11:33:05.869336 [0] MAX Duty = 5062%(X100), DQS PI = 10
2459 11:33:05.872722 [0] MIN Duty = 4875%(X100), DQS PI = 4
2460 11:33:05.872814 [0] AVG Duty = 4968%(X100)
2461 11:33:05.876670
2462 11:33:05.880048 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2463 11:33:05.880146
2464 11:33:05.882885 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2465 11:33:05.886236 [DutyScan_Calibration_Flow] ====Done====
2466 11:33:05.886306
2467 11:33:05.889655 [DutyScan_Calibration_Flow] k_type=2
2468 11:33:05.905190
2469 11:33:05.905288 ==DQ 0 ==
2470 11:33:05.908599 Final DQ duty delay cell = -4
2471 11:33:05.912117 [-4] MAX Duty = 5062%(X100), DQS PI = 24
2472 11:33:05.915466 [-4] MIN Duty = 4938%(X100), DQS PI = 4
2473 11:33:05.919000 [-4] AVG Duty = 5000%(X100)
2474 11:33:05.919093
2475 11:33:05.919177 ==DQ 1 ==
2476 11:33:05.921610 Final DQ duty delay cell = 0
2477 11:33:05.925014 [0] MAX Duty = 5093%(X100), DQS PI = 10
2478 11:33:05.928998 [0] MIN Duty = 4938%(X100), DQS PI = 0
2479 11:33:05.929076 [0] AVG Duty = 5015%(X100)
2480 11:33:05.932405
2481 11:33:05.935504 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2482 11:33:05.935579
2483 11:33:05.938686 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2484 11:33:05.941463 [DutyScan_Calibration_Flow] ====Done====
2485 11:33:05.944932 nWR fixed to 30
2486 11:33:05.948212 [ModeRegInit_LP4] CH0 RK0
2487 11:33:05.948305 [ModeRegInit_LP4] CH0 RK1
2488 11:33:05.951526 [ModeRegInit_LP4] CH1 RK0
2489 11:33:05.955147 [ModeRegInit_LP4] CH1 RK1
2490 11:33:05.955223 match AC timing 7
2491 11:33:05.961870 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 11:33:05.965043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 11:33:05.968652 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 11:33:05.974933 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 11:33:05.978650 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 11:33:05.978719 ==
2497 11:33:05.981500 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 11:33:05.984886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 11:33:05.984962 ==
2500 11:33:05.991617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 11:33:05.998495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 11:33:06.005356 [CA 0] Center 39 (8~70) winsize 63
2503 11:33:06.008646 [CA 1] Center 39 (8~70) winsize 63
2504 11:33:06.012412 [CA 2] Center 35 (5~66) winsize 62
2505 11:33:06.015836 [CA 3] Center 34 (4~65) winsize 62
2506 11:33:06.018706 [CA 4] Center 33 (3~64) winsize 62
2507 11:33:06.022664 [CA 5] Center 32 (3~62) winsize 60
2508 11:33:06.022739
2509 11:33:06.025396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2510 11:33:06.025470
2511 11:33:06.028812 [CATrainingPosCal] consider 1 rank data
2512 11:33:06.032166 u2DelayCellTimex100 = 270/100 ps
2513 11:33:06.035527 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2514 11:33:06.038922 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2515 11:33:06.045630 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2516 11:33:06.048885 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2517 11:33:06.052286 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2518 11:33:06.055815 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2519 11:33:06.055904
2520 11:33:06.059151 CA PerBit enable=1, Macro0, CA PI delay=32
2521 11:33:06.059236
2522 11:33:06.062451 [CBTSetCACLKResult] CA Dly = 32
2523 11:33:06.062541 CS Dly: 6 (0~37)
2524 11:33:06.062614 ==
2525 11:33:06.065815 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 11:33:06.072138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 11:33:06.072265 ==
2528 11:33:06.075780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 11:33:06.082294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2530 11:33:06.091111 [CA 0] Center 38 (8~69) winsize 62
2531 11:33:06.094445 [CA 1] Center 38 (8~69) winsize 62
2532 11:33:06.097732 [CA 2] Center 35 (4~66) winsize 63
2533 11:33:06.101368 [CA 3] Center 34 (4~65) winsize 62
2534 11:33:06.104523 [CA 4] Center 33 (3~64) winsize 62
2535 11:33:06.107837 [CA 5] Center 32 (3~62) winsize 60
2536 11:33:06.107928
2537 11:33:06.111178 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 11:33:06.111252
2539 11:33:06.115093 [CATrainingPosCal] consider 2 rank data
2540 11:33:06.118155 u2DelayCellTimex100 = 270/100 ps
2541 11:33:06.121962 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2542 11:33:06.124732 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2543 11:33:06.131260 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2544 11:33:06.134643 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2545 11:33:06.138669 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2546 11:33:06.142032 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2547 11:33:06.142122
2548 11:33:06.144872 CA PerBit enable=1, Macro0, CA PI delay=32
2549 11:33:06.144946
2550 11:33:06.148389 [CBTSetCACLKResult] CA Dly = 32
2551 11:33:06.148464 CS Dly: 6 (0~38)
2552 11:33:06.148538
2553 11:33:06.151770 ----->DramcWriteLeveling(PI) begin...
2554 11:33:06.151845 ==
2555 11:33:06.154904 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 11:33:06.161714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 11:33:06.161790 ==
2558 11:33:06.164970 Write leveling (Byte 0): 33 => 33
2559 11:33:06.168401 Write leveling (Byte 1): 30 => 30
2560 11:33:06.168476 DramcWriteLeveling(PI) end<-----
2561 11:33:06.168567
2562 11:33:06.171793 ==
2563 11:33:06.175129 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 11:33:06.178598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 11:33:06.178688 ==
2566 11:33:06.182029 [Gating] SW mode calibration
2567 11:33:06.188165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 11:33:06.191484 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 11:33:06.198285 0 15 0 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
2570 11:33:06.201501 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2571 11:33:06.205269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 11:33:06.211671 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 11:33:06.215025 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 11:33:06.218439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 11:33:06.225259 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2576 11:33:06.228322 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2577 11:33:06.231974 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2578 11:33:06.235098 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 11:33:06.242238 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 11:33:06.245271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 11:33:06.248513 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 11:33:06.255257 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 11:33:06.258316 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2584 11:33:06.261729 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2585 11:33:06.268535 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2586 11:33:06.271935 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 11:33:06.275399 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 11:33:06.281982 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 11:33:06.285438 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 11:33:06.288817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 11:33:06.295603 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2592 11:33:06.298851 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2593 11:33:06.301707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 11:33:06.309100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:33:06.312421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:33:06.315166 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:33:06.318533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:33:06.325155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:33:06.328408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:33:06.331706 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:33:06.338835 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:33:06.342199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:33:06.345348 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:33:06.351806 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:33:06.355500 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 11:33:06.358638 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:33:06.365634 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:33:06.368602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2609 11:33:06.372201 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:33:06.375263 Total UI for P1: 0, mck2ui 16
2611 11:33:06.378604 best dqsien dly found for B0: ( 1, 3, 28)
2612 11:33:06.381934 Total UI for P1: 0, mck2ui 16
2613 11:33:06.385404 best dqsien dly found for B1: ( 1, 3, 30)
2614 11:33:06.388889 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2615 11:33:06.392338 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2616 11:33:06.392442
2617 11:33:06.395747 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2618 11:33:06.401795 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2619 11:33:06.401870 [Gating] SW calibration Done
2620 11:33:06.401951 ==
2621 11:33:06.405169 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:33:06.411955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:33:06.412030 ==
2624 11:33:06.412088 RX Vref Scan: 0
2625 11:33:06.412141
2626 11:33:06.415376 RX Vref 0 -> 0, step: 1
2627 11:33:06.415451
2628 11:33:06.418785 RX Delay -40 -> 252, step: 8
2629 11:33:06.422267 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2630 11:33:06.425410 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2631 11:33:06.428756 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2632 11:33:06.435445 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2633 11:33:06.438828 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2634 11:33:06.442040 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2635 11:33:06.445793 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2636 11:33:06.449200 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2637 11:33:06.452573 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2638 11:33:06.458781 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2639 11:33:06.462416 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2640 11:33:06.465584 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2641 11:33:06.469406 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2642 11:33:06.472751 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2643 11:33:06.478988 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2644 11:33:06.482378 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2645 11:33:06.482466 ==
2646 11:33:06.485584 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:33:06.488889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:33:06.488960 ==
2649 11:33:06.492813 DQS Delay:
2650 11:33:06.492912 DQS0 = 0, DQS1 = 0
2651 11:33:06.492995 DQM Delay:
2652 11:33:06.495536 DQM0 = 121, DQM1 = 113
2653 11:33:06.495629 DQ Delay:
2654 11:33:06.499389 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2655 11:33:06.502696 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2656 11:33:06.505705 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2657 11:33:06.512907 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2658 11:33:06.513032
2659 11:33:06.513107
2660 11:33:06.513191 ==
2661 11:33:06.516143 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:33:06.519563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:33:06.519655 ==
2664 11:33:06.519762
2665 11:33:06.519832
2666 11:33:06.522250 TX Vref Scan disable
2667 11:33:06.522354 == TX Byte 0 ==
2668 11:33:06.529862 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2669 11:33:06.532503 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2670 11:33:06.532580 == TX Byte 1 ==
2671 11:33:06.539288 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2672 11:33:06.542722 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2673 11:33:06.542825 ==
2674 11:33:06.546047 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:33:06.549341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:33:06.549443 ==
2677 11:33:06.562148 TX Vref=22, minBit 10, minWin=24, winSum=404
2678 11:33:06.565335 TX Vref=24, minBit 3, minWin=25, winSum=411
2679 11:33:06.568408 TX Vref=26, minBit 7, minWin=25, winSum=418
2680 11:33:06.571669 TX Vref=28, minBit 13, minWin=25, winSum=421
2681 11:33:06.574695 TX Vref=30, minBit 12, minWin=25, winSum=422
2682 11:33:06.581859 TX Vref=32, minBit 10, minWin=25, winSum=419
2683 11:33:06.585083 [TxChooseVref] Worse bit 12, Min win 25, Win sum 422, Final Vref 30
2684 11:33:06.585181
2685 11:33:06.587997 Final TX Range 1 Vref 30
2686 11:33:06.588085
2687 11:33:06.588211 ==
2688 11:33:06.591629 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 11:33:06.594866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 11:33:06.598093 ==
2691 11:33:06.598207
2692 11:33:06.598304
2693 11:33:06.598375 TX Vref Scan disable
2694 11:33:06.601631 == TX Byte 0 ==
2695 11:33:06.605137 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2696 11:33:06.608550 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2697 11:33:06.611986 == TX Byte 1 ==
2698 11:33:06.615350 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2699 11:33:06.618547 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2700 11:33:06.622182
2701 11:33:06.622321 [DATLAT]
2702 11:33:06.622447 Freq=1200, CH0 RK0
2703 11:33:06.622564
2704 11:33:06.625130 DATLAT Default: 0xd
2705 11:33:06.625228 0, 0xFFFF, sum = 0
2706 11:33:06.628961 1, 0xFFFF, sum = 0
2707 11:33:06.629085 2, 0xFFFF, sum = 0
2708 11:33:06.631883 3, 0xFFFF, sum = 0
2709 11:33:06.631979 4, 0xFFFF, sum = 0
2710 11:33:06.635403 5, 0xFFFF, sum = 0
2711 11:33:06.635502 6, 0xFFFF, sum = 0
2712 11:33:06.638895 7, 0xFFFF, sum = 0
2713 11:33:06.642160 8, 0xFFFF, sum = 0
2714 11:33:06.642249 9, 0xFFFF, sum = 0
2715 11:33:06.644988 10, 0xFFFF, sum = 0
2716 11:33:06.645075 11, 0xFFFF, sum = 0
2717 11:33:06.648486 12, 0x0, sum = 1
2718 11:33:06.648586 13, 0x0, sum = 2
2719 11:33:06.651963 14, 0x0, sum = 3
2720 11:33:06.652057 15, 0x0, sum = 4
2721 11:33:06.652141 best_step = 13
2722 11:33:06.652220
2723 11:33:06.655268 ==
2724 11:33:06.658372 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:33:06.662352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:33:06.662446 ==
2727 11:33:06.662517 RX Vref Scan: 1
2728 11:33:06.662570
2729 11:33:06.665169 Set Vref Range= 32 -> 127
2730 11:33:06.665235
2731 11:33:06.668530 RX Vref 32 -> 127, step: 1
2732 11:33:06.668646
2733 11:33:06.672155 RX Delay -13 -> 252, step: 4
2734 11:33:06.672256
2735 11:33:06.675458 Set Vref, RX VrefLevel [Byte0]: 32
2736 11:33:06.678887 [Byte1]: 32
2737 11:33:06.678954
2738 11:33:06.682272 Set Vref, RX VrefLevel [Byte0]: 33
2739 11:33:06.685483 [Byte1]: 33
2740 11:33:06.685559
2741 11:33:06.688496 Set Vref, RX VrefLevel [Byte0]: 34
2742 11:33:06.692175 [Byte1]: 34
2743 11:33:06.696422
2744 11:33:06.696498 Set Vref, RX VrefLevel [Byte0]: 35
2745 11:33:06.699500 [Byte1]: 35
2746 11:33:06.704398
2747 11:33:06.704474 Set Vref, RX VrefLevel [Byte0]: 36
2748 11:33:06.707537 [Byte1]: 36
2749 11:33:06.712114
2750 11:33:06.712191 Set Vref, RX VrefLevel [Byte0]: 37
2751 11:33:06.715527 [Byte1]: 37
2752 11:33:06.719682
2753 11:33:06.719760 Set Vref, RX VrefLevel [Byte0]: 38
2754 11:33:06.723098 [Byte1]: 38
2755 11:33:06.728041
2756 11:33:06.728117 Set Vref, RX VrefLevel [Byte0]: 39
2757 11:33:06.731282 [Byte1]: 39
2758 11:33:06.735945
2759 11:33:06.736022 Set Vref, RX VrefLevel [Byte0]: 40
2760 11:33:06.739073 [Byte1]: 40
2761 11:33:06.743410
2762 11:33:06.743505 Set Vref, RX VrefLevel [Byte0]: 41
2763 11:33:06.746894 [Byte1]: 41
2764 11:33:06.751452
2765 11:33:06.751528 Set Vref, RX VrefLevel [Byte0]: 42
2766 11:33:06.754746 [Byte1]: 42
2767 11:33:06.759363
2768 11:33:06.759440 Set Vref, RX VrefLevel [Byte0]: 43
2769 11:33:06.762182 [Byte1]: 43
2770 11:33:06.767399
2771 11:33:06.767475 Set Vref, RX VrefLevel [Byte0]: 44
2772 11:33:06.770692 [Byte1]: 44
2773 11:33:06.774737
2774 11:33:06.774815 Set Vref, RX VrefLevel [Byte0]: 45
2775 11:33:06.778614 [Byte1]: 45
2776 11:33:06.782655
2777 11:33:06.782731 Set Vref, RX VrefLevel [Byte0]: 46
2778 11:33:06.786146 [Byte1]: 46
2779 11:33:06.790946
2780 11:33:06.791026 Set Vref, RX VrefLevel [Byte0]: 47
2781 11:33:06.794070 [Byte1]: 47
2782 11:33:06.799148
2783 11:33:06.799225 Set Vref, RX VrefLevel [Byte0]: 48
2784 11:33:06.802265 [Byte1]: 48
2785 11:33:06.806524
2786 11:33:06.806601 Set Vref, RX VrefLevel [Byte0]: 49
2787 11:33:06.809829 [Byte1]: 49
2788 11:33:06.814237
2789 11:33:06.814340 Set Vref, RX VrefLevel [Byte0]: 50
2790 11:33:06.818029 [Byte1]: 50
2791 11:33:06.822533
2792 11:33:06.822611 Set Vref, RX VrefLevel [Byte0]: 51
2793 11:33:06.825864 [Byte1]: 51
2794 11:33:06.829923
2795 11:33:06.830003 Set Vref, RX VrefLevel [Byte0]: 52
2796 11:33:06.833274 [Byte1]: 52
2797 11:33:06.838015
2798 11:33:06.838095 Set Vref, RX VrefLevel [Byte0]: 53
2799 11:33:06.841488 [Byte1]: 53
2800 11:33:06.846047
2801 11:33:06.846126 Set Vref, RX VrefLevel [Byte0]: 54
2802 11:33:06.849335 [Byte1]: 54
2803 11:33:06.854065
2804 11:33:06.854145 Set Vref, RX VrefLevel [Byte0]: 55
2805 11:33:06.857332 [Byte1]: 55
2806 11:33:06.861839
2807 11:33:06.861918 Set Vref, RX VrefLevel [Byte0]: 56
2808 11:33:06.864908 [Byte1]: 56
2809 11:33:06.869809
2810 11:33:06.869888 Set Vref, RX VrefLevel [Byte0]: 57
2811 11:33:06.872793 [Byte1]: 57
2812 11:33:06.877817
2813 11:33:06.877896 Set Vref, RX VrefLevel [Byte0]: 58
2814 11:33:06.880825 [Byte1]: 58
2815 11:33:06.885658
2816 11:33:06.885737 Set Vref, RX VrefLevel [Byte0]: 59
2817 11:33:06.888627 [Byte1]: 59
2818 11:33:06.893220
2819 11:33:06.893300 Set Vref, RX VrefLevel [Byte0]: 60
2820 11:33:06.896758 [Byte1]: 60
2821 11:33:06.901120
2822 11:33:06.901198 Set Vref, RX VrefLevel [Byte0]: 61
2823 11:33:06.904463 [Byte1]: 61
2824 11:33:06.909030
2825 11:33:06.909109 Set Vref, RX VrefLevel [Byte0]: 62
2826 11:33:06.912336 [Byte1]: 62
2827 11:33:06.917149
2828 11:33:06.917228 Set Vref, RX VrefLevel [Byte0]: 63
2829 11:33:06.920512 [Byte1]: 63
2830 11:33:06.924967
2831 11:33:06.925047 Set Vref, RX VrefLevel [Byte0]: 64
2832 11:33:06.928145 [Byte1]: 64
2833 11:33:06.933136
2834 11:33:06.933215 Set Vref, RX VrefLevel [Byte0]: 65
2835 11:33:06.935835 [Byte1]: 65
2836 11:33:06.940568
2837 11:33:06.940647 Set Vref, RX VrefLevel [Byte0]: 66
2838 11:33:06.943957 [Byte1]: 66
2839 11:33:06.948626
2840 11:33:06.948724 Set Vref, RX VrefLevel [Byte0]: 67
2841 11:33:06.952088 [Byte1]: 67
2842 11:33:06.956690
2843 11:33:06.956767 Set Vref, RX VrefLevel [Byte0]: 68
2844 11:33:06.960009 [Byte1]: 68
2845 11:33:06.964682
2846 11:33:06.964762 Set Vref, RX VrefLevel [Byte0]: 69
2847 11:33:06.967987 [Byte1]: 69
2848 11:33:06.972747
2849 11:33:06.972823 Set Vref, RX VrefLevel [Byte0]: 70
2850 11:33:06.975437 [Byte1]: 70
2851 11:33:06.980132
2852 11:33:06.980213 Final RX Vref Byte 0 = 54 to rank0
2853 11:33:06.983559 Final RX Vref Byte 1 = 48 to rank0
2854 11:33:06.986913 Final RX Vref Byte 0 = 54 to rank1
2855 11:33:06.990057 Final RX Vref Byte 1 = 48 to rank1==
2856 11:33:06.993323 Dram Type= 6, Freq= 0, CH_0, rank 0
2857 11:33:07.000011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 11:33:07.000089 ==
2859 11:33:07.000148 DQS Delay:
2860 11:33:07.000203 DQS0 = 0, DQS1 = 0
2861 11:33:07.003657 DQM Delay:
2862 11:33:07.003734 DQM0 = 120, DQM1 = 111
2863 11:33:07.006981 DQ Delay:
2864 11:33:07.010146 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2865 11:33:07.013604 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2866 11:33:07.016700 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
2867 11:33:07.020373 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2868 11:33:07.020477
2869 11:33:07.020567
2870 11:33:07.026766 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2871 11:33:07.030668 CH0 RK0: MR19=404, MR18=1610
2872 11:33:07.037018 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2873 11:33:07.037096
2874 11:33:07.040273 ----->DramcWriteLeveling(PI) begin...
2875 11:33:07.040376 ==
2876 11:33:07.043677 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 11:33:07.046914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 11:33:07.050503 ==
2879 11:33:07.050609 Write leveling (Byte 0): 35 => 35
2880 11:33:07.053360 Write leveling (Byte 1): 29 => 29
2881 11:33:07.056863 DramcWriteLeveling(PI) end<-----
2882 11:33:07.056955
2883 11:33:07.057032 ==
2884 11:33:07.060240 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 11:33:07.066599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 11:33:07.066698 ==
2887 11:33:07.066787 [Gating] SW mode calibration
2888 11:33:07.077049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2889 11:33:07.079880 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2890 11:33:07.083454 0 15 0 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 1)
2891 11:33:07.090417 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 11:33:07.093244 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 11:33:07.096928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 11:33:07.103581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 11:33:07.107132 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 11:33:07.109902 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2897 11:33:07.116865 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (1 0) (0 1)
2898 11:33:07.120592 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 11:33:07.123721 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 11:33:07.130647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 11:33:07.133674 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 11:33:07.136860 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 11:33:07.143416 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 11:33:07.147091 1 0 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2905 11:33:07.150078 1 0 28 | B1->B0 | 4242 4141 | 0 0 | (0 0) (0 0)
2906 11:33:07.157149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 11:33:07.160437 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 11:33:07.163643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 11:33:07.166883 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 11:33:07.173872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 11:33:07.177266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:33:07.180676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2913 11:33:07.186800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2914 11:33:07.190255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2915 11:33:07.193749 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 11:33:07.200403 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 11:33:07.203828 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 11:33:07.207252 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 11:33:07.213914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:33:07.217351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:33:07.220766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 11:33:07.226756 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 11:33:07.230180 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 11:33:07.233642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:33:07.240288 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:33:07.243692 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:33:07.247450 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:33:07.250448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2929 11:33:07.257135 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2930 11:33:07.260625 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2931 11:33:07.263675 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 11:33:07.267110 Total UI for P1: 0, mck2ui 16
2933 11:33:07.270246 best dqsien dly found for B0: ( 1, 3, 28)
2934 11:33:07.273648 Total UI for P1: 0, mck2ui 16
2935 11:33:07.277526 best dqsien dly found for B1: ( 1, 3, 28)
2936 11:33:07.280538 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2937 11:33:07.284047 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2938 11:33:07.284123
2939 11:33:07.290771 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2940 11:33:07.293909 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2941 11:33:07.297315 [Gating] SW calibration Done
2942 11:33:07.297415 ==
2943 11:33:07.300629 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 11:33:07.303859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 11:33:07.303937 ==
2946 11:33:07.303996 RX Vref Scan: 0
2947 11:33:07.304052
2948 11:33:07.307252 RX Vref 0 -> 0, step: 1
2949 11:33:07.307316
2950 11:33:07.310732 RX Delay -40 -> 252, step: 8
2951 11:33:07.314199 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2952 11:33:07.316893 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2953 11:33:07.320337 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2954 11:33:07.327108 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2955 11:33:07.330448 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2956 11:33:07.333862 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2957 11:33:07.337284 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2958 11:33:07.340909 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2959 11:33:07.347515 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2960 11:33:07.350871 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2961 11:33:07.354215 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2962 11:33:07.357480 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2963 11:33:07.360767 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2964 11:33:07.367451 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2965 11:33:07.370694 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2966 11:33:07.374340 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2967 11:33:07.374430 ==
2968 11:33:07.377440 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 11:33:07.381196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 11:33:07.381277 ==
2971 11:33:07.384170 DQS Delay:
2972 11:33:07.384280 DQS0 = 0, DQS1 = 0
2973 11:33:07.387737 DQM Delay:
2974 11:33:07.387844 DQM0 = 122, DQM1 = 112
2975 11:33:07.387931 DQ Delay:
2976 11:33:07.391055 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2977 11:33:07.394398 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2978 11:33:07.401177 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2979 11:33:07.404073 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2980 11:33:07.404166
2981 11:33:07.404251
2982 11:33:07.404307 ==
2983 11:33:07.407819 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 11:33:07.411209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 11:33:07.411284 ==
2986 11:33:07.411341
2987 11:33:07.411410
2988 11:33:07.414305 TX Vref Scan disable
2989 11:33:07.414379 == TX Byte 0 ==
2990 11:33:07.421213 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2991 11:33:07.424217 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2992 11:33:07.424292 == TX Byte 1 ==
2993 11:33:07.431174 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2994 11:33:07.434502 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2995 11:33:07.434578 ==
2996 11:33:07.437916 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:33:07.440683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:33:07.440780 ==
2999 11:33:07.454869 TX Vref=22, minBit 1, minWin=25, winSum=415
3000 11:33:07.458261 TX Vref=24, minBit 0, minWin=26, winSum=420
3001 11:33:07.461657 TX Vref=26, minBit 1, minWin=25, winSum=421
3002 11:33:07.465037 TX Vref=28, minBit 5, minWin=25, winSum=428
3003 11:33:07.468282 TX Vref=30, minBit 5, minWin=25, winSum=430
3004 11:33:07.471664 TX Vref=32, minBit 5, minWin=25, winSum=427
3005 11:33:07.477872 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 24
3006 11:33:07.477968
3007 11:33:07.481276 Final TX Range 1 Vref 24
3008 11:33:07.481343
3009 11:33:07.481397 ==
3010 11:33:07.484408 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 11:33:07.488180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 11:33:07.488258 ==
3013 11:33:07.488316
3014 11:33:07.488370
3015 11:33:07.491189 TX Vref Scan disable
3016 11:33:07.494979 == TX Byte 0 ==
3017 11:33:07.497960 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3018 11:33:07.501495 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3019 11:33:07.504459 == TX Byte 1 ==
3020 11:33:07.507956 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3021 11:33:07.511382 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3022 11:33:07.511473
3023 11:33:07.514753 [DATLAT]
3024 11:33:07.514819 Freq=1200, CH0 RK1
3025 11:33:07.514876
3026 11:33:07.517809 DATLAT Default: 0xd
3027 11:33:07.517886 0, 0xFFFF, sum = 0
3028 11:33:07.521048 1, 0xFFFF, sum = 0
3029 11:33:07.521116 2, 0xFFFF, sum = 0
3030 11:33:07.525022 3, 0xFFFF, sum = 0
3031 11:33:07.525100 4, 0xFFFF, sum = 0
3032 11:33:07.528001 5, 0xFFFF, sum = 0
3033 11:33:07.528079 6, 0xFFFF, sum = 0
3034 11:33:07.531087 7, 0xFFFF, sum = 0
3035 11:33:07.531165 8, 0xFFFF, sum = 0
3036 11:33:07.534578 9, 0xFFFF, sum = 0
3037 11:33:07.538098 10, 0xFFFF, sum = 0
3038 11:33:07.538200 11, 0xFFFF, sum = 0
3039 11:33:07.541086 12, 0x0, sum = 1
3040 11:33:07.541163 13, 0x0, sum = 2
3041 11:33:07.541224 14, 0x0, sum = 3
3042 11:33:07.544983 15, 0x0, sum = 4
3043 11:33:07.545073 best_step = 13
3044 11:33:07.545158
3045 11:33:07.547702 ==
3046 11:33:07.547779 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 11:33:07.554313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 11:33:07.554419 ==
3049 11:33:07.554506 RX Vref Scan: 0
3050 11:33:07.554593
3051 11:33:07.557646 RX Vref 0 -> 0, step: 1
3052 11:33:07.557736
3053 11:33:07.560944 RX Delay -13 -> 252, step: 4
3054 11:33:07.564309 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3055 11:33:07.567680 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3056 11:33:07.574494 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3057 11:33:07.577844 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3058 11:33:07.581160 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3059 11:33:07.584371 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3060 11:33:07.587930 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3061 11:33:07.593970 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3062 11:33:07.597883 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3063 11:33:07.600844 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3064 11:33:07.604210 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3065 11:33:07.607387 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3066 11:33:07.613877 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3067 11:33:07.617818 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3068 11:33:07.620710 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3069 11:33:07.623998 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3070 11:33:07.624077 ==
3071 11:33:07.627293 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 11:33:07.633989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 11:33:07.634083 ==
3074 11:33:07.634140 DQS Delay:
3075 11:33:07.637384 DQS0 = 0, DQS1 = 0
3076 11:33:07.637459 DQM Delay:
3077 11:33:07.640713 DQM0 = 120, DQM1 = 109
3078 11:33:07.640787 DQ Delay:
3079 11:33:07.644252 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3080 11:33:07.647105 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3081 11:33:07.650779 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3082 11:33:07.653867 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3083 11:33:07.653965
3084 11:33:07.654095
3085 11:33:07.664158 [DQSOSCAuto] RK1, (LSB)MR18= 0x15f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 401 ps
3086 11:33:07.664235 CH0 RK1: MR19=403, MR18=15F6
3087 11:33:07.670720 CH0_RK1: MR19=0x403, MR18=0x15F6, DQSOSC=401, MR23=63, INC=40, DEC=27
3088 11:33:07.674161 [RxdqsGatingPostProcess] freq 1200
3089 11:33:07.680980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3090 11:33:07.684418 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 11:33:07.687685 best DQS1 dly(2T, 0.5T) = (0, 11)
3092 11:33:07.690831 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 11:33:07.693617 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3094 11:33:07.696941 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 11:33:07.697076 best DQS1 dly(2T, 0.5T) = (0, 11)
3096 11:33:07.700335 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 11:33:07.703623 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3098 11:33:07.706871 Pre-setting of DQS Precalculation
3099 11:33:07.714177 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3100 11:33:07.714276 ==
3101 11:33:07.716795 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 11:33:07.720496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 11:33:07.720576 ==
3104 11:33:07.727327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 11:33:07.733951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3106 11:33:07.740512 [CA 0] Center 37 (7~68) winsize 62
3107 11:33:07.744088 [CA 1] Center 37 (7~68) winsize 62
3108 11:33:07.747459 [CA 2] Center 35 (5~65) winsize 61
3109 11:33:07.750851 [CA 3] Center 34 (4~65) winsize 62
3110 11:33:07.753943 [CA 4] Center 34 (4~64) winsize 61
3111 11:33:07.757700 [CA 5] Center 33 (3~63) winsize 61
3112 11:33:07.757794
3113 11:33:07.760800 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3114 11:33:07.760872
3115 11:33:07.764259 [CATrainingPosCal] consider 1 rank data
3116 11:33:07.767503 u2DelayCellTimex100 = 270/100 ps
3117 11:33:07.770751 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 11:33:07.773931 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 11:33:07.780689 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3120 11:33:07.784113 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3121 11:33:07.787502 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 11:33:07.790771 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3123 11:33:07.790849
3124 11:33:07.794022 CA PerBit enable=1, Macro0, CA PI delay=33
3125 11:33:07.794099
3126 11:33:07.797514 [CBTSetCACLKResult] CA Dly = 33
3127 11:33:07.797592 CS Dly: 7 (0~38)
3128 11:33:07.797651 ==
3129 11:33:07.800886 Dram Type= 6, Freq= 0, CH_1, rank 1
3130 11:33:07.807643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:33:07.807720 ==
3132 11:33:07.810888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 11:33:07.816727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3134 11:33:07.826316 [CA 0] Center 37 (7~68) winsize 62
3135 11:33:07.829787 [CA 1] Center 37 (7~68) winsize 62
3136 11:33:07.833354 [CA 2] Center 35 (5~66) winsize 62
3137 11:33:07.836235 [CA 3] Center 34 (4~65) winsize 62
3138 11:33:07.839704 [CA 4] Center 34 (4~65) winsize 62
3139 11:33:07.843033 [CA 5] Center 34 (4~64) winsize 61
3140 11:33:07.843109
3141 11:33:07.846364 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3142 11:33:07.846441
3143 11:33:07.849808 [CATrainingPosCal] consider 2 rank data
3144 11:33:07.853143 u2DelayCellTimex100 = 270/100 ps
3145 11:33:07.856519 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 11:33:07.859854 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 11:33:07.866389 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3148 11:33:07.869367 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3149 11:33:07.873155 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 11:33:07.876399 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3151 11:33:07.876502
3152 11:33:07.879808 CA PerBit enable=1, Macro0, CA PI delay=33
3153 11:33:07.879877
3154 11:33:07.882619 [CBTSetCACLKResult] CA Dly = 33
3155 11:33:07.882685 CS Dly: 8 (0~40)
3156 11:33:07.882739
3157 11:33:07.886483 ----->DramcWriteLeveling(PI) begin...
3158 11:33:07.889667 ==
3159 11:33:07.892841 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 11:33:07.896500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 11:33:07.896566 ==
3162 11:33:07.899403 Write leveling (Byte 0): 27 => 27
3163 11:33:07.902954 Write leveling (Byte 1): 28 => 28
3164 11:33:07.906280 DramcWriteLeveling(PI) end<-----
3165 11:33:07.906350
3166 11:33:07.906417 ==
3167 11:33:07.909628 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 11:33:07.912843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 11:33:07.912908 ==
3170 11:33:07.916246 [Gating] SW mode calibration
3171 11:33:07.922913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3172 11:33:07.929714 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3173 11:33:07.933093 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 11:33:07.935835 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 11:33:07.942756 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 11:33:07.945946 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 11:33:07.949186 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 11:33:07.956223 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 11:33:07.959162 0 15 24 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 1)
3180 11:33:07.962474 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3181 11:33:07.966280 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 11:33:07.972387 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 11:33:07.975707 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 11:33:07.979403 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 11:33:07.985844 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 11:33:07.989008 1 0 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
3187 11:33:07.992318 1 0 24 | B1->B0 | 2c2c 4040 | 0 1 | (1 1) (0 0)
3188 11:33:07.999037 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3189 11:33:08.002547 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 11:33:08.005884 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 11:33:08.012692 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 11:33:08.015596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 11:33:08.018970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 11:33:08.025930 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3195 11:33:08.029279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3196 11:33:08.032611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 11:33:08.039441 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 11:33:08.042247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 11:33:08.045563 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 11:33:08.052374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 11:33:08.055792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:33:08.059116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:33:08.065937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:33:08.068832 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 11:33:08.072677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 11:33:08.078771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:33:08.082715 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:33:08.085906 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:33:08.089351 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:33:08.095446 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:33:08.098854 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3212 11:33:08.102659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 11:33:08.105821 Total UI for P1: 0, mck2ui 16
3214 11:33:08.108686 best dqsien dly found for B0: ( 1, 3, 24)
3215 11:33:08.112271 Total UI for P1: 0, mck2ui 16
3216 11:33:08.115342 best dqsien dly found for B1: ( 1, 3, 24)
3217 11:33:08.118696 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3218 11:33:08.122549 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3219 11:33:08.125716
3220 11:33:08.128924 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3221 11:33:08.132326 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3222 11:33:08.135720 [Gating] SW calibration Done
3223 11:33:08.135796 ==
3224 11:33:08.139382 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:33:08.142373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 11:33:08.142450 ==
3227 11:33:08.142526 RX Vref Scan: 0
3228 11:33:08.142597
3229 11:33:08.145602 RX Vref 0 -> 0, step: 1
3230 11:33:08.145692
3231 11:33:08.148985 RX Delay -40 -> 252, step: 8
3232 11:33:08.151727 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3233 11:33:08.155085 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3234 11:33:08.161836 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3235 11:33:08.165060 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3236 11:33:08.168527 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3237 11:33:08.171905 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3238 11:33:08.175175 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3239 11:33:08.181881 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3240 11:33:08.185207 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3241 11:33:08.188496 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3242 11:33:08.192132 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3243 11:33:08.195436 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3244 11:33:08.201595 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3245 11:33:08.204810 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3246 11:33:08.208540 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3247 11:33:08.211471 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3248 11:33:08.211545 ==
3249 11:33:08.215023 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 11:33:08.221512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 11:33:08.221602 ==
3252 11:33:08.221659 DQS Delay:
3253 11:33:08.224814 DQS0 = 0, DQS1 = 0
3254 11:33:08.224891 DQM Delay:
3255 11:33:08.224966 DQM0 = 120, DQM1 = 116
3256 11:33:08.228344 DQ Delay:
3257 11:33:08.231790 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3258 11:33:08.235093 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3259 11:33:08.238441 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3260 11:33:08.241541 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3261 11:33:08.241617
3262 11:33:08.241735
3263 11:33:08.241820 ==
3264 11:33:08.245344 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 11:33:08.248517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 11:33:08.251438 ==
3267 11:33:08.251550
3268 11:33:08.251624
3269 11:33:08.251695 TX Vref Scan disable
3270 11:33:08.254901 == TX Byte 0 ==
3271 11:33:08.258539 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3272 11:33:08.261317 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3273 11:33:08.264742 == TX Byte 1 ==
3274 11:33:08.268595 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3275 11:33:08.271920 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3276 11:33:08.272003 ==
3277 11:33:08.275342 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 11:33:08.281419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 11:33:08.281485 ==
3280 11:33:08.292256 TX Vref=22, minBit 10, minWin=24, winSum=409
3281 11:33:08.295696 TX Vref=24, minBit 9, minWin=25, winSum=418
3282 11:33:08.299002 TX Vref=26, minBit 1, minWin=26, winSum=423
3283 11:33:08.302252 TX Vref=28, minBit 1, minWin=26, winSum=428
3284 11:33:08.305384 TX Vref=30, minBit 10, minWin=25, winSum=427
3285 11:33:08.311975 TX Vref=32, minBit 1, minWin=26, winSum=426
3286 11:33:08.315527 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3287 11:33:08.315593
3288 11:33:08.319082 Final TX Range 1 Vref 28
3289 11:33:08.319147
3290 11:33:08.319199 ==
3291 11:33:08.322103 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:33:08.325598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:33:08.325692 ==
3294 11:33:08.328754
3295 11:33:08.328829
3296 11:33:08.328939 TX Vref Scan disable
3297 11:33:08.332319 == TX Byte 0 ==
3298 11:33:08.335418 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3299 11:33:08.338655 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3300 11:33:08.341921 == TX Byte 1 ==
3301 11:33:08.345335 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3302 11:33:08.348663 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3303 11:33:08.351971
3304 11:33:08.352047 [DATLAT]
3305 11:33:08.352123 Freq=1200, CH1 RK0
3306 11:33:08.352195
3307 11:33:08.355304 DATLAT Default: 0xd
3308 11:33:08.355402 0, 0xFFFF, sum = 0
3309 11:33:08.359110 1, 0xFFFF, sum = 0
3310 11:33:08.359190 2, 0xFFFF, sum = 0
3311 11:33:08.362352 3, 0xFFFF, sum = 0
3312 11:33:08.362430 4, 0xFFFF, sum = 0
3313 11:33:08.365234 5, 0xFFFF, sum = 0
3314 11:33:08.365299 6, 0xFFFF, sum = 0
3315 11:33:08.368819 7, 0xFFFF, sum = 0
3316 11:33:08.372315 8, 0xFFFF, sum = 0
3317 11:33:08.372386 9, 0xFFFF, sum = 0
3318 11:33:08.375677 10, 0xFFFF, sum = 0
3319 11:33:08.375753 11, 0xFFFF, sum = 0
3320 11:33:08.378690 12, 0x0, sum = 1
3321 11:33:08.378763 13, 0x0, sum = 2
3322 11:33:08.382002 14, 0x0, sum = 3
3323 11:33:08.382108 15, 0x0, sum = 4
3324 11:33:08.382164 best_step = 13
3325 11:33:08.382221
3326 11:33:08.385269 ==
3327 11:33:08.388754 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 11:33:08.392080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 11:33:08.392171 ==
3330 11:33:08.392261 RX Vref Scan: 1
3331 11:33:08.392333
3332 11:33:08.395340 Set Vref Range= 32 -> 127
3333 11:33:08.395402
3334 11:33:08.398796 RX Vref 32 -> 127, step: 1
3335 11:33:08.398859
3336 11:33:08.402252 RX Delay -5 -> 252, step: 4
3337 11:33:08.402323
3338 11:33:08.405697 Set Vref, RX VrefLevel [Byte0]: 32
3339 11:33:08.408543 [Byte1]: 32
3340 11:33:08.408609
3341 11:33:08.411754 Set Vref, RX VrefLevel [Byte0]: 33
3342 11:33:08.415151 [Byte1]: 33
3343 11:33:08.415218
3344 11:33:08.418444 Set Vref, RX VrefLevel [Byte0]: 34
3345 11:33:08.421655 [Byte1]: 34
3346 11:33:08.426087
3347 11:33:08.426211 Set Vref, RX VrefLevel [Byte0]: 35
3348 11:33:08.429276 [Byte1]: 35
3349 11:33:08.434095
3350 11:33:08.434187 Set Vref, RX VrefLevel [Byte0]: 36
3351 11:33:08.437380 [Byte1]: 36
3352 11:33:08.441704
3353 11:33:08.441797 Set Vref, RX VrefLevel [Byte0]: 37
3354 11:33:08.445195 [Byte1]: 37
3355 11:33:08.449742
3356 11:33:08.449843 Set Vref, RX VrefLevel [Byte0]: 38
3357 11:33:08.452839 [Byte1]: 38
3358 11:33:08.457411
3359 11:33:08.457479 Set Vref, RX VrefLevel [Byte0]: 39
3360 11:33:08.460858 [Byte1]: 39
3361 11:33:08.465586
3362 11:33:08.465650 Set Vref, RX VrefLevel [Byte0]: 40
3363 11:33:08.468926 [Byte1]: 40
3364 11:33:08.472942
3365 11:33:08.473034 Set Vref, RX VrefLevel [Byte0]: 41
3366 11:33:08.476745 [Byte1]: 41
3367 11:33:08.480822
3368 11:33:08.480897 Set Vref, RX VrefLevel [Byte0]: 42
3369 11:33:08.484814 [Byte1]: 42
3370 11:33:08.488896
3371 11:33:08.488966 Set Vref, RX VrefLevel [Byte0]: 43
3372 11:33:08.492476 [Byte1]: 43
3373 11:33:08.496630
3374 11:33:08.496699 Set Vref, RX VrefLevel [Byte0]: 44
3375 11:33:08.500414 [Byte1]: 44
3376 11:33:08.504616
3377 11:33:08.504705 Set Vref, RX VrefLevel [Byte0]: 45
3378 11:33:08.507961 [Byte1]: 45
3379 11:33:08.512600
3380 11:33:08.512666 Set Vref, RX VrefLevel [Byte0]: 46
3381 11:33:08.515907 [Byte1]: 46
3382 11:33:08.520213
3383 11:33:08.520281 Set Vref, RX VrefLevel [Byte0]: 47
3384 11:33:08.523494 [Byte1]: 47
3385 11:33:08.528152
3386 11:33:08.528225 Set Vref, RX VrefLevel [Byte0]: 48
3387 11:33:08.531403 [Byte1]: 48
3388 11:33:08.535782
3389 11:33:08.535854 Set Vref, RX VrefLevel [Byte0]: 49
3390 11:33:08.539477 [Byte1]: 49
3391 11:33:08.543795
3392 11:33:08.543870 Set Vref, RX VrefLevel [Byte0]: 50
3393 11:33:08.547146 [Byte1]: 50
3394 11:33:08.551918
3395 11:33:08.551997 Set Vref, RX VrefLevel [Byte0]: 51
3396 11:33:08.554963 [Byte1]: 51
3397 11:33:08.559277
3398 11:33:08.559344 Set Vref, RX VrefLevel [Byte0]: 52
3399 11:33:08.562756 [Byte1]: 52
3400 11:33:08.567745
3401 11:33:08.567813 Set Vref, RX VrefLevel [Byte0]: 53
3402 11:33:08.571080 [Byte1]: 53
3403 11:33:08.575145
3404 11:33:08.575220 Set Vref, RX VrefLevel [Byte0]: 54
3405 11:33:08.578487 [Byte1]: 54
3406 11:33:08.583014
3407 11:33:08.583082 Set Vref, RX VrefLevel [Byte0]: 55
3408 11:33:08.586438 [Byte1]: 55
3409 11:33:08.591143
3410 11:33:08.591212 Set Vref, RX VrefLevel [Byte0]: 56
3411 11:33:08.594461 [Byte1]: 56
3412 11:33:08.599025
3413 11:33:08.599088 Set Vref, RX VrefLevel [Byte0]: 57
3414 11:33:08.602132 [Byte1]: 57
3415 11:33:08.607050
3416 11:33:08.607114 Set Vref, RX VrefLevel [Byte0]: 58
3417 11:33:08.609950 [Byte1]: 58
3418 11:33:08.614709
3419 11:33:08.614817 Set Vref, RX VrefLevel [Byte0]: 59
3420 11:33:08.617854 [Byte1]: 59
3421 11:33:08.622508
3422 11:33:08.622607 Set Vref, RX VrefLevel [Byte0]: 60
3423 11:33:08.625922 [Byte1]: 60
3424 11:33:08.630680
3425 11:33:08.630755 Set Vref, RX VrefLevel [Byte0]: 61
3426 11:33:08.633383 [Byte1]: 61
3427 11:33:08.638157
3428 11:33:08.638232 Set Vref, RX VrefLevel [Byte0]: 62
3429 11:33:08.644455 [Byte1]: 62
3430 11:33:08.644530
3431 11:33:08.648170 Set Vref, RX VrefLevel [Byte0]: 63
3432 11:33:08.651217 [Byte1]: 63
3433 11:33:08.651310
3434 11:33:08.654565 Set Vref, RX VrefLevel [Byte0]: 64
3435 11:33:08.657999 [Byte1]: 64
3436 11:33:08.662109
3437 11:33:08.662183 Set Vref, RX VrefLevel [Byte0]: 65
3438 11:33:08.665474 [Byte1]: 65
3439 11:33:08.669221
3440 11:33:08.669295 Set Vref, RX VrefLevel [Byte0]: 66
3441 11:33:08.672981 [Byte1]: 66
3442 11:33:08.677613
3443 11:33:08.677701 Set Vref, RX VrefLevel [Byte0]: 67
3444 11:33:08.680622 [Byte1]: 67
3445 11:33:08.685661
3446 11:33:08.685736 Set Vref, RX VrefLevel [Byte0]: 68
3447 11:33:08.688734 [Byte1]: 68
3448 11:33:08.693183
3449 11:33:08.693258 Set Vref, RX VrefLevel [Byte0]: 69
3450 11:33:08.696482 [Byte1]: 69
3451 11:33:08.701230
3452 11:33:08.701304 Final RX Vref Byte 0 = 54 to rank0
3453 11:33:08.704527 Final RX Vref Byte 1 = 54 to rank0
3454 11:33:08.707898 Final RX Vref Byte 0 = 54 to rank1
3455 11:33:08.711115 Final RX Vref Byte 1 = 54 to rank1==
3456 11:33:08.714481 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 11:33:08.720850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 11:33:08.720926 ==
3459 11:33:08.720984 DQS Delay:
3460 11:33:08.721037 DQS0 = 0, DQS1 = 0
3461 11:33:08.724242 DQM Delay:
3462 11:33:08.724317 DQM0 = 120, DQM1 = 117
3463 11:33:08.727291 DQ Delay:
3464 11:33:08.731119 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3465 11:33:08.734206 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3466 11:33:08.737574 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3467 11:33:08.741013 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3468 11:33:08.741080
3469 11:33:08.741135
3470 11:33:08.750936 [DQSOSCAuto] RK0, (LSB)MR18= 0x719, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3471 11:33:08.751066 CH1 RK0: MR19=404, MR18=719
3472 11:33:08.757231 CH1_RK0: MR19=0x404, MR18=0x719, DQSOSC=400, MR23=63, INC=40, DEC=27
3473 11:33:08.757353
3474 11:33:08.760866 ----->DramcWriteLeveling(PI) begin...
3475 11:33:08.760976 ==
3476 11:33:08.763703 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 11:33:08.767022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 11:33:08.770457 ==
3479 11:33:08.770568 Write leveling (Byte 0): 25 => 25
3480 11:33:08.773818 Write leveling (Byte 1): 28 => 28
3481 11:33:08.777318 DramcWriteLeveling(PI) end<-----
3482 11:33:08.777395
3483 11:33:08.777454 ==
3484 11:33:08.780769 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 11:33:08.787244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 11:33:08.787326 ==
3487 11:33:08.790282 [Gating] SW mode calibration
3488 11:33:08.797280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 11:33:08.800726 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 11:33:08.806880 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 11:33:08.810521 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 11:33:08.813859 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 11:33:08.820521 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:33:08.823735 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 11:33:08.827083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:33:08.830476 0 15 24 | B1->B0 | 2929 3333 | 1 1 | (1 0) (1 1)
3497 11:33:08.837273 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 11:33:08.840540 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 11:33:08.843956 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 11:33:08.850294 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:33:08.853691 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:33:08.856774 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:33:08.863796 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3504 11:33:08.866792 1 0 24 | B1->B0 | 4444 3333 | 0 1 | (1 1) (0 0)
3505 11:33:08.870233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 11:33:08.876927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 11:33:08.880338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 11:33:08.883783 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:33:08.889974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:33:08.893333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:33:08.896720 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3512 11:33:08.903132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3513 11:33:08.906847 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3514 11:33:08.909847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 11:33:08.916890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 11:33:08.919887 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:33:08.923426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:33:08.930131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:33:08.933433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:33:08.936937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:33:08.943014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:33:08.946911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:33:08.950278 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:33:08.956891 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:33:08.959782 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:33:08.963628 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:33:08.966872 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3528 11:33:08.973126 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3529 11:33:08.976887 Total UI for P1: 0, mck2ui 16
3530 11:33:08.980214 best dqsien dly found for B1: ( 1, 3, 20)
3531 11:33:08.983555 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3532 11:33:08.986961 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:33:08.989819 Total UI for P1: 0, mck2ui 16
3534 11:33:08.993116 best dqsien dly found for B0: ( 1, 3, 26)
3535 11:33:08.996459 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3536 11:33:08.999783 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3537 11:33:08.999866
3538 11:33:09.006620 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3539 11:33:09.009900 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3540 11:33:09.013114 [Gating] SW calibration Done
3541 11:33:09.013189 ==
3542 11:33:09.016809 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 11:33:09.020070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 11:33:09.020146 ==
3545 11:33:09.020205 RX Vref Scan: 0
3546 11:33:09.020258
3547 11:33:09.023382 RX Vref 0 -> 0, step: 1
3548 11:33:09.023492
3549 11:33:09.026667 RX Delay -40 -> 252, step: 8
3550 11:33:09.029917 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3551 11:33:09.033085 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3552 11:33:09.039715 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3553 11:33:09.043020 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3554 11:33:09.046368 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3555 11:33:09.049538 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3556 11:33:09.052953 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3557 11:33:09.059889 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3558 11:33:09.063304 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3559 11:33:09.066478 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3560 11:33:09.069424 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3561 11:33:09.073196 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3562 11:33:09.079340 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3563 11:33:09.082929 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3564 11:33:09.086485 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3565 11:33:09.089524 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3566 11:33:09.089599 ==
3567 11:33:09.092634 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:33:09.099500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:33:09.099575 ==
3570 11:33:09.099632 DQS Delay:
3571 11:33:09.099685 DQS0 = 0, DQS1 = 0
3572 11:33:09.102772 DQM Delay:
3573 11:33:09.102848 DQM0 = 119, DQM1 = 117
3574 11:33:09.106159 DQ Delay:
3575 11:33:09.109682 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3576 11:33:09.112972 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3577 11:33:09.116442 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =111
3578 11:33:09.119526 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3579 11:33:09.119600
3580 11:33:09.119658
3581 11:33:09.119711 ==
3582 11:33:09.122759 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 11:33:09.126581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 11:33:09.129844 ==
3585 11:33:09.129943
3586 11:33:09.130054
3587 11:33:09.130125 TX Vref Scan disable
3588 11:33:09.133182 == TX Byte 0 ==
3589 11:33:09.135890 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3590 11:33:09.140007 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3591 11:33:09.142728 == TX Byte 1 ==
3592 11:33:09.145969 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 11:33:09.149306 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 11:33:09.149387 ==
3595 11:33:09.152606 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 11:33:09.159194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 11:33:09.159271 ==
3598 11:33:09.170388 TX Vref=22, minBit 1, minWin=25, winSum=415
3599 11:33:09.173739 TX Vref=24, minBit 9, minWin=25, winSum=422
3600 11:33:09.177179 TX Vref=26, minBit 1, minWin=26, winSum=428
3601 11:33:09.179774 TX Vref=28, minBit 1, minWin=26, winSum=431
3602 11:33:09.183503 TX Vref=30, minBit 2, minWin=26, winSum=430
3603 11:33:09.189947 TX Vref=32, minBit 0, minWin=26, winSum=427
3604 11:33:09.193334 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3605 11:33:09.193432
3606 11:33:09.196855 Final TX Range 1 Vref 28
3607 11:33:09.196950
3608 11:33:09.197033 ==
3609 11:33:09.199863 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 11:33:09.203650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 11:33:09.203746 ==
3612 11:33:09.203838
3613 11:33:09.206381
3614 11:33:09.206450 TX Vref Scan disable
3615 11:33:09.210268 == TX Byte 0 ==
3616 11:33:09.213027 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3617 11:33:09.216318 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3618 11:33:09.220326 == TX Byte 1 ==
3619 11:33:09.223695 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 11:33:09.226899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 11:33:09.226997
3622 11:33:09.229938 [DATLAT]
3623 11:33:09.230060 Freq=1200, CH1 RK1
3624 11:33:09.230153
3625 11:33:09.233230 DATLAT Default: 0xd
3626 11:33:09.233383 0, 0xFFFF, sum = 0
3627 11:33:09.236308 1, 0xFFFF, sum = 0
3628 11:33:09.236458 2, 0xFFFF, sum = 0
3629 11:33:09.239857 3, 0xFFFF, sum = 0
3630 11:33:09.240013 4, 0xFFFF, sum = 0
3631 11:33:09.243228 5, 0xFFFF, sum = 0
3632 11:33:09.243376 6, 0xFFFF, sum = 0
3633 11:33:09.246715 7, 0xFFFF, sum = 0
3634 11:33:09.250080 8, 0xFFFF, sum = 0
3635 11:33:09.250227 9, 0xFFFF, sum = 0
3636 11:33:09.253401 10, 0xFFFF, sum = 0
3637 11:33:09.253549 11, 0xFFFF, sum = 0
3638 11:33:09.256651 12, 0x0, sum = 1
3639 11:33:09.256780 13, 0x0, sum = 2
3640 11:33:09.260025 14, 0x0, sum = 3
3641 11:33:09.260123 15, 0x0, sum = 4
3642 11:33:09.260215 best_step = 13
3643 11:33:09.260296
3644 11:33:09.263342 ==
3645 11:33:09.266363 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 11:33:09.269637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 11:33:09.269736 ==
3648 11:33:09.269831 RX Vref Scan: 0
3649 11:33:09.269916
3650 11:33:09.272814 RX Vref 0 -> 0, step: 1
3651 11:33:09.272905
3652 11:33:09.276473 RX Delay -5 -> 252, step: 4
3653 11:33:09.279719 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3654 11:33:09.286419 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3655 11:33:09.289652 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3656 11:33:09.292790 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3657 11:33:09.296750 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3658 11:33:09.299958 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3659 11:33:09.303231 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3660 11:33:09.309803 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3661 11:33:09.312948 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3662 11:33:09.315898 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3663 11:33:09.319386 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3664 11:33:09.326420 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3665 11:33:09.329900 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3666 11:33:09.333077 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3667 11:33:09.336260 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3668 11:33:09.339422 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3669 11:33:09.339507 ==
3670 11:33:09.343314 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 11:33:09.350035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 11:33:09.350139 ==
3673 11:33:09.350228 DQS Delay:
3674 11:33:09.352738 DQS0 = 0, DQS1 = 0
3675 11:33:09.352833 DQM Delay:
3676 11:33:09.356695 DQM0 = 120, DQM1 = 118
3677 11:33:09.356800 DQ Delay:
3678 11:33:09.359483 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3679 11:33:09.362945 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3680 11:33:09.366359 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3681 11:33:09.369637 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3682 11:33:09.369734
3683 11:33:09.369821
3684 11:33:09.379680 [DQSOSCAuto] RK1, (LSB)MR18= 0x18f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 400 ps
3685 11:33:09.379786 CH1 RK1: MR19=403, MR18=18F4
3686 11:33:09.386243 CH1_RK1: MR19=0x403, MR18=0x18F4, DQSOSC=400, MR23=63, INC=40, DEC=27
3687 11:33:09.389724 [RxdqsGatingPostProcess] freq 1200
3688 11:33:09.396343 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 11:33:09.399690 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 11:33:09.402938 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 11:33:09.405930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 11:33:09.409267 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 11:33:09.412581 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 11:33:09.415977 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 11:33:09.416070 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 11:33:09.419350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 11:33:09.422609 Pre-setting of DQS Precalculation
3698 11:33:09.429659 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 11:33:09.436272 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 11:33:09.442637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 11:33:09.442736
3702 11:33:09.442836
3703 11:33:09.445986 [Calibration Summary] 2400 Mbps
3704 11:33:09.449482 CH 0, Rank 0
3705 11:33:09.449581 SW Impedance : PASS
3706 11:33:09.452595 DUTY Scan : NO K
3707 11:33:09.452689 ZQ Calibration : PASS
3708 11:33:09.455724 Jitter Meter : NO K
3709 11:33:09.459574 CBT Training : PASS
3710 11:33:09.459670 Write leveling : PASS
3711 11:33:09.463019 RX DQS gating : PASS
3712 11:33:09.465678 RX DQ/DQS(RDDQC) : PASS
3713 11:33:09.465773 TX DQ/DQS : PASS
3714 11:33:09.468994 RX DATLAT : PASS
3715 11:33:09.473042 RX DQ/DQS(Engine): PASS
3716 11:33:09.473136 TX OE : NO K
3717 11:33:09.476375 All Pass.
3718 11:33:09.476471
3719 11:33:09.476556 CH 0, Rank 1
3720 11:33:09.479040 SW Impedance : PASS
3721 11:33:09.479132 DUTY Scan : NO K
3722 11:33:09.482458 ZQ Calibration : PASS
3723 11:33:09.485791 Jitter Meter : NO K
3724 11:33:09.485885 CBT Training : PASS
3725 11:33:09.489278 Write leveling : PASS
3726 11:33:09.492594 RX DQS gating : PASS
3727 11:33:09.492692 RX DQ/DQS(RDDQC) : PASS
3728 11:33:09.495884 TX DQ/DQS : PASS
3729 11:33:09.498869 RX DATLAT : PASS
3730 11:33:09.498959 RX DQ/DQS(Engine): PASS
3731 11:33:09.502604 TX OE : NO K
3732 11:33:09.502680 All Pass.
3733 11:33:09.502756
3734 11:33:09.505805 CH 1, Rank 0
3735 11:33:09.505901 SW Impedance : PASS
3736 11:33:09.508942 DUTY Scan : NO K
3737 11:33:09.509038 ZQ Calibration : PASS
3738 11:33:09.512178 Jitter Meter : NO K
3739 11:33:09.515776 CBT Training : PASS
3740 11:33:09.515868 Write leveling : PASS
3741 11:33:09.519202 RX DQS gating : PASS
3742 11:33:09.522568 RX DQ/DQS(RDDQC) : PASS
3743 11:33:09.522665 TX DQ/DQS : PASS
3744 11:33:09.526096 RX DATLAT : PASS
3745 11:33:09.528788 RX DQ/DQS(Engine): PASS
3746 11:33:09.528882 TX OE : NO K
3747 11:33:09.532115 All Pass.
3748 11:33:09.532210
3749 11:33:09.532297 CH 1, Rank 1
3750 11:33:09.535457 SW Impedance : PASS
3751 11:33:09.535552 DUTY Scan : NO K
3752 11:33:09.538839 ZQ Calibration : PASS
3753 11:33:09.542042 Jitter Meter : NO K
3754 11:33:09.542144 CBT Training : PASS
3755 11:33:09.545297 Write leveling : PASS
3756 11:33:09.548732 RX DQS gating : PASS
3757 11:33:09.548826 RX DQ/DQS(RDDQC) : PASS
3758 11:33:09.551868 TX DQ/DQS : PASS
3759 11:33:09.555565 RX DATLAT : PASS
3760 11:33:09.555664 RX DQ/DQS(Engine): PASS
3761 11:33:09.558512 TX OE : NO K
3762 11:33:09.558605 All Pass.
3763 11:33:09.558692
3764 11:33:09.562037 DramC Write-DBI off
3765 11:33:09.565428 PER_BANK_REFRESH: Hybrid Mode
3766 11:33:09.565524 TX_TRACKING: ON
3767 11:33:09.575136 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 11:33:09.578499 [FAST_K] Save calibration result to emmc
3769 11:33:09.581764 dramc_set_vcore_voltage set vcore to 650000
3770 11:33:09.585206 Read voltage for 600, 5
3771 11:33:09.585300 Vio18 = 0
3772 11:33:09.585385 Vcore = 650000
3773 11:33:09.588556 Vdram = 0
3774 11:33:09.588647 Vddq = 0
3775 11:33:09.588733 Vmddr = 0
3776 11:33:09.595334 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 11:33:09.598828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 11:33:09.601987 MEM_TYPE=3, freq_sel=19
3779 11:33:09.605332 sv_algorithm_assistance_LP4_1600
3780 11:33:09.608580 ============ PULL DRAM RESETB DOWN ============
3781 11:33:09.611601 ========== PULL DRAM RESETB DOWN end =========
3782 11:33:09.618788 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 11:33:09.621887 ===================================
3784 11:33:09.621995 LPDDR4 DRAM CONFIGURATION
3785 11:33:09.624908 ===================================
3786 11:33:09.628582 EX_ROW_EN[0] = 0x0
3787 11:33:09.631872 EX_ROW_EN[1] = 0x0
3788 11:33:09.631976 LP4Y_EN = 0x0
3789 11:33:09.635260 WORK_FSP = 0x0
3790 11:33:09.635329 WL = 0x2
3791 11:33:09.638638 RL = 0x2
3792 11:33:09.638736 BL = 0x2
3793 11:33:09.642026 RPST = 0x0
3794 11:33:09.642115 RD_PRE = 0x0
3795 11:33:09.645334 WR_PRE = 0x1
3796 11:33:09.645398 WR_PST = 0x0
3797 11:33:09.648501 DBI_WR = 0x0
3798 11:33:09.648565 DBI_RD = 0x0
3799 11:33:09.651897 OTF = 0x1
3800 11:33:09.655280 ===================================
3801 11:33:09.658511 ===================================
3802 11:33:09.658579 ANA top config
3803 11:33:09.661962 ===================================
3804 11:33:09.665128 DLL_ASYNC_EN = 0
3805 11:33:09.668489 ALL_SLAVE_EN = 1
3806 11:33:09.668585 NEW_RANK_MODE = 1
3807 11:33:09.671918 DLL_IDLE_MODE = 1
3808 11:33:09.675102 LP45_APHY_COMB_EN = 1
3809 11:33:09.678816 TX_ODT_DIS = 1
3810 11:33:09.681767 NEW_8X_MODE = 1
3811 11:33:09.681844 ===================================
3812 11:33:09.685142 ===================================
3813 11:33:09.688829 data_rate = 1200
3814 11:33:09.692305 CKR = 1
3815 11:33:09.695170 DQ_P2S_RATIO = 8
3816 11:33:09.699033 ===================================
3817 11:33:09.701706 CA_P2S_RATIO = 8
3818 11:33:09.705087 DQ_CA_OPEN = 0
3819 11:33:09.705181 DQ_SEMI_OPEN = 0
3820 11:33:09.708610 CA_SEMI_OPEN = 0
3821 11:33:09.711938 CA_FULL_RATE = 0
3822 11:33:09.715203 DQ_CKDIV4_EN = 1
3823 11:33:09.718595 CA_CKDIV4_EN = 1
3824 11:33:09.721924 CA_PREDIV_EN = 0
3825 11:33:09.722023 PH8_DLY = 0
3826 11:33:09.725673 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 11:33:09.728836 DQ_AAMCK_DIV = 4
3828 11:33:09.731749 CA_AAMCK_DIV = 4
3829 11:33:09.735551 CA_ADMCK_DIV = 4
3830 11:33:09.738486 DQ_TRACK_CA_EN = 0
3831 11:33:09.738553 CA_PICK = 600
3832 11:33:09.742141 CA_MCKIO = 600
3833 11:33:09.745156 MCKIO_SEMI = 0
3834 11:33:09.748829 PLL_FREQ = 2288
3835 11:33:09.752005 DQ_UI_PI_RATIO = 32
3836 11:33:09.755302 CA_UI_PI_RATIO = 0
3837 11:33:09.758732 ===================================
3838 11:33:09.761436 ===================================
3839 11:33:09.764791 memory_type:LPDDR4
3840 11:33:09.764857 GP_NUM : 10
3841 11:33:09.768152 SRAM_EN : 1
3842 11:33:09.768244 MD32_EN : 0
3843 11:33:09.771354 ===================================
3844 11:33:09.774760 [ANA_INIT] >>>>>>>>>>>>>>
3845 11:33:09.778269 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 11:33:09.781478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 11:33:09.784866 ===================================
3848 11:33:09.788219 data_rate = 1200,PCW = 0X5800
3849 11:33:09.792077 ===================================
3850 11:33:09.795169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 11:33:09.798651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 11:33:09.805071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 11:33:09.808180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 11:33:09.811812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 11:33:09.818535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 11:33:09.818634 [ANA_INIT] flow start
3857 11:33:09.822047 [ANA_INIT] PLL >>>>>>>>
3858 11:33:09.822124 [ANA_INIT] PLL <<<<<<<<
3859 11:33:09.825300 [ANA_INIT] MIDPI >>>>>>>>
3860 11:33:09.828642 [ANA_INIT] MIDPI <<<<<<<<
3861 11:33:09.831854 [ANA_INIT] DLL >>>>>>>>
3862 11:33:09.831934 [ANA_INIT] flow end
3863 11:33:09.835099 ============ LP4 DIFF to SE enter ============
3864 11:33:09.841624 ============ LP4 DIFF to SE exit ============
3865 11:33:09.841702 [ANA_INIT] <<<<<<<<<<<<<
3866 11:33:09.844680 [Flow] Enable top DCM control >>>>>
3867 11:33:09.848038 [Flow] Enable top DCM control <<<<<
3868 11:33:09.851474 Enable DLL master slave shuffle
3869 11:33:09.857973 ==============================================================
3870 11:33:09.858063 Gating Mode config
3871 11:33:09.864754 ==============================================================
3872 11:33:09.868396 Config description:
3873 11:33:09.878382 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 11:33:09.884878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 11:33:09.888327 SELPH_MODE 0: By rank 1: By Phase
3876 11:33:09.895120 ==============================================================
3877 11:33:09.897922 GAT_TRACK_EN = 1
3878 11:33:09.901300 RX_GATING_MODE = 2
3879 11:33:09.901381 RX_GATING_TRACK_MODE = 2
3880 11:33:09.904474 SELPH_MODE = 1
3881 11:33:09.907651 PICG_EARLY_EN = 1
3882 11:33:09.911510 VALID_LAT_VALUE = 1
3883 11:33:09.917978 ==============================================================
3884 11:33:09.921212 Enter into Gating configuration >>>>
3885 11:33:09.925023 Exit from Gating configuration <<<<
3886 11:33:09.928342 Enter into DVFS_PRE_config >>>>>
3887 11:33:09.938280 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 11:33:09.941586 Exit from DVFS_PRE_config <<<<<
3889 11:33:09.944806 Enter into PICG configuration >>>>
3890 11:33:09.947936 Exit from PICG configuration <<<<
3891 11:33:09.951252 [RX_INPUT] configuration >>>>>
3892 11:33:09.951329 [RX_INPUT] configuration <<<<<
3893 11:33:09.958275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 11:33:09.964794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 11:33:09.971525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 11:33:09.974686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 11:33:09.981195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 11:33:09.988377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 11:33:09.991904 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 11:33:09.994593 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 11:33:10.001267 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 11:33:10.004635 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 11:33:10.008000 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 11:33:10.014519 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 11:33:10.017962 ===================================
3906 11:33:10.018066 LPDDR4 DRAM CONFIGURATION
3907 11:33:10.021127 ===================================
3908 11:33:10.024952 EX_ROW_EN[0] = 0x0
3909 11:33:10.025029 EX_ROW_EN[1] = 0x0
3910 11:33:10.027899 LP4Y_EN = 0x0
3911 11:33:10.031513 WORK_FSP = 0x0
3912 11:33:10.031589 WL = 0x2
3913 11:33:10.034638 RL = 0x2
3914 11:33:10.034715 BL = 0x2
3915 11:33:10.037816 RPST = 0x0
3916 11:33:10.037908 RD_PRE = 0x0
3917 11:33:10.041140 WR_PRE = 0x1
3918 11:33:10.041217 WR_PST = 0x0
3919 11:33:10.044568 DBI_WR = 0x0
3920 11:33:10.044645 DBI_RD = 0x0
3921 11:33:10.047828 OTF = 0x1
3922 11:33:10.051474 ===================================
3923 11:33:10.054473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 11:33:10.057767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 11:33:10.061034 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 11:33:10.064899 ===================================
3927 11:33:10.068162 LPDDR4 DRAM CONFIGURATION
3928 11:33:10.071417 ===================================
3929 11:33:10.074760 EX_ROW_EN[0] = 0x10
3930 11:33:10.074836 EX_ROW_EN[1] = 0x0
3931 11:33:10.078296 LP4Y_EN = 0x0
3932 11:33:10.078372 WORK_FSP = 0x0
3933 11:33:10.081613 WL = 0x2
3934 11:33:10.081689 RL = 0x2
3935 11:33:10.084937 BL = 0x2
3936 11:33:10.085014 RPST = 0x0
3937 11:33:10.088090 RD_PRE = 0x0
3938 11:33:10.088166 WR_PRE = 0x1
3939 11:33:10.090964 WR_PST = 0x0
3940 11:33:10.094711 DBI_WR = 0x0
3941 11:33:10.094792 DBI_RD = 0x0
3942 11:33:10.097956 OTF = 0x1
3943 11:33:10.101409 ===================================
3944 11:33:10.104785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 11:33:10.109670 nWR fixed to 30
3946 11:33:10.113080 [ModeRegInit_LP4] CH0 RK0
3947 11:33:10.113156 [ModeRegInit_LP4] CH0 RK1
3948 11:33:10.116441 [ModeRegInit_LP4] CH1 RK0
3949 11:33:10.119696 [ModeRegInit_LP4] CH1 RK1
3950 11:33:10.119767 match AC timing 17
3951 11:33:10.126534 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 11:33:10.129950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 11:33:10.133202 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 11:33:10.139728 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 11:33:10.143317 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 11:33:10.143393 ==
3957 11:33:10.146173 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 11:33:10.149617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 11:33:10.149706 ==
3960 11:33:10.156533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 11:33:10.162790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3962 11:33:10.166440 [CA 0] Center 36 (5~67) winsize 63
3963 11:33:10.169840 [CA 1] Center 35 (5~66) winsize 62
3964 11:33:10.173219 [CA 2] Center 34 (3~65) winsize 63
3965 11:33:10.176527 [CA 3] Center 33 (3~64) winsize 62
3966 11:33:10.179839 [CA 4] Center 33 (2~64) winsize 63
3967 11:33:10.183104 [CA 5] Center 32 (2~63) winsize 62
3968 11:33:10.183180
3969 11:33:10.186305 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3970 11:33:10.186382
3971 11:33:10.189845 [CATrainingPosCal] consider 1 rank data
3972 11:33:10.193169 u2DelayCellTimex100 = 270/100 ps
3973 11:33:10.196407 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3974 11:33:10.199591 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3975 11:33:10.202913 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3976 11:33:10.205976 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3977 11:33:10.209469 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3978 11:33:10.212908 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3979 11:33:10.216208
3980 11:33:10.219488 CA PerBit enable=1, Macro0, CA PI delay=32
3981 11:33:10.219578
3982 11:33:10.222749 [CBTSetCACLKResult] CA Dly = 32
3983 11:33:10.222837 CS Dly: 4 (0~35)
3984 11:33:10.222927 ==
3985 11:33:10.226251 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 11:33:10.229663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 11:33:10.229757 ==
3988 11:33:10.235855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 11:33:10.242800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3990 11:33:10.246109 [CA 0] Center 35 (5~66) winsize 62
3991 11:33:10.249379 [CA 1] Center 35 (5~66) winsize 62
3992 11:33:10.252822 [CA 2] Center 34 (3~65) winsize 63
3993 11:33:10.256067 [CA 3] Center 33 (3~64) winsize 62
3994 11:33:10.259194 [CA 4] Center 33 (2~64) winsize 63
3995 11:33:10.262950 [CA 5] Center 32 (2~63) winsize 62
3996 11:33:10.263017
3997 11:33:10.265931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3998 11:33:10.266026
3999 11:33:10.269346 [CATrainingPosCal] consider 2 rank data
4000 11:33:10.272883 u2DelayCellTimex100 = 270/100 ps
4001 11:33:10.275849 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4002 11:33:10.279477 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4003 11:33:10.282586 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4004 11:33:10.286335 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4005 11:33:10.289529 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4006 11:33:10.296093 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4007 11:33:10.296172
4008 11:33:10.299619 CA PerBit enable=1, Macro0, CA PI delay=32
4009 11:33:10.299697
4010 11:33:10.302737 [CBTSetCACLKResult] CA Dly = 32
4011 11:33:10.302814 CS Dly: 4 (0~36)
4012 11:33:10.302873
4013 11:33:10.306042 ----->DramcWriteLeveling(PI) begin...
4014 11:33:10.306120 ==
4015 11:33:10.309315 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 11:33:10.312515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 11:33:10.315869 ==
4018 11:33:10.315946 Write leveling (Byte 0): 34 => 34
4019 11:33:10.319805 Write leveling (Byte 1): 32 => 32
4020 11:33:10.322586 DramcWriteLeveling(PI) end<-----
4021 11:33:10.322663
4022 11:33:10.322742 ==
4023 11:33:10.326371 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 11:33:10.332442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 11:33:10.332547 ==
4026 11:33:10.335790 [Gating] SW mode calibration
4027 11:33:10.342715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 11:33:10.345929 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 11:33:10.352638 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 11:33:10.355889 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 11:33:10.358967 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 11:33:10.365749 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
4033 11:33:10.369076 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4034 11:33:10.372359 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4035 11:33:10.375715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 11:33:10.382490 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:33:10.385857 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:33:10.389370 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:33:10.395840 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:33:10.398993 0 10 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
4041 11:33:10.402508 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4042 11:33:10.409264 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 11:33:10.412428 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 11:33:10.415703 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:33:10.422070 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:33:10.425689 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:33:10.428845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:33:10.435659 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4049 11:33:10.439102 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4050 11:33:10.442589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 11:33:10.448837 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:33:10.452213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:33:10.455819 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:33:10.462082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:33:10.465410 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:33:10.469314 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:33:10.475460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:33:10.479034 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:33:10.482446 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:33:10.485822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:33:10.492379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:33:10.495407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:33:10.499074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:33:10.505332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4065 11:33:10.509180 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4066 11:33:10.512245 Total UI for P1: 0, mck2ui 16
4067 11:33:10.515551 best dqsien dly found for B0: ( 0, 13, 12)
4068 11:33:10.519175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:33:10.522251 Total UI for P1: 0, mck2ui 16
4070 11:33:10.525370 best dqsien dly found for B1: ( 0, 13, 18)
4071 11:33:10.528912 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4072 11:33:10.531898 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4073 11:33:10.535321
4074 11:33:10.538848 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4075 11:33:10.542439 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4076 11:33:10.545409 [Gating] SW calibration Done
4077 11:33:10.545485 ==
4078 11:33:10.548540 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 11:33:10.552063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 11:33:10.552166 ==
4081 11:33:10.552258 RX Vref Scan: 0
4082 11:33:10.552339
4083 11:33:10.555443 RX Vref 0 -> 0, step: 1
4084 11:33:10.555528
4085 11:33:10.558878 RX Delay -230 -> 252, step: 16
4086 11:33:10.562259 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4087 11:33:10.565709 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4088 11:33:10.572447 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4089 11:33:10.575597 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4090 11:33:10.579153 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4091 11:33:10.582143 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4092 11:33:10.588717 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4093 11:33:10.592128 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4094 11:33:10.595473 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4095 11:33:10.598964 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4096 11:33:10.605424 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4097 11:33:10.608572 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4098 11:33:10.612149 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4099 11:33:10.615203 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4100 11:33:10.618791 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4101 11:33:10.625415 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4102 11:33:10.625509 ==
4103 11:33:10.628836 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 11:33:10.632274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 11:33:10.632339 ==
4106 11:33:10.632392 DQS Delay:
4107 11:33:10.635442 DQS0 = 0, DQS1 = 0
4108 11:33:10.635521 DQM Delay:
4109 11:33:10.638483 DQM0 = 52, DQM1 = 45
4110 11:33:10.638546 DQ Delay:
4111 11:33:10.641780 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4112 11:33:10.644929 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4113 11:33:10.648363 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4114 11:33:10.652179 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4115 11:33:10.652253
4116 11:33:10.652311
4117 11:33:10.652363 ==
4118 11:33:10.655102 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 11:33:10.659036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 11:33:10.661947 ==
4121 11:33:10.662063
4122 11:33:10.662139
4123 11:33:10.662194 TX Vref Scan disable
4124 11:33:10.664951 == TX Byte 0 ==
4125 11:33:10.668243 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4126 11:33:10.671687 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4127 11:33:10.674990 == TX Byte 1 ==
4128 11:33:10.678372 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4129 11:33:10.681840 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4130 11:33:10.685149 ==
4131 11:33:10.685237 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 11:33:10.691992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 11:33:10.692083 ==
4134 11:33:10.692163
4135 11:33:10.692241
4136 11:33:10.694849 TX Vref Scan disable
4137 11:33:10.694984 == TX Byte 0 ==
4138 11:33:10.701444 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4139 11:33:10.704881 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4140 11:33:10.704946 == TX Byte 1 ==
4141 11:33:10.711632 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4142 11:33:10.714880 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4143 11:33:10.714955
4144 11:33:10.715012 [DATLAT]
4145 11:33:10.718209 Freq=600, CH0 RK0
4146 11:33:10.718284
4147 11:33:10.718341 DATLAT Default: 0x9
4148 11:33:10.721513 0, 0xFFFF, sum = 0
4149 11:33:10.721590 1, 0xFFFF, sum = 0
4150 11:33:10.724716 2, 0xFFFF, sum = 0
4151 11:33:10.724792 3, 0xFFFF, sum = 0
4152 11:33:10.728633 4, 0xFFFF, sum = 0
4153 11:33:10.728709 5, 0xFFFF, sum = 0
4154 11:33:10.731565 6, 0xFFFF, sum = 0
4155 11:33:10.734682 7, 0xFFFF, sum = 0
4156 11:33:10.734756 8, 0x0, sum = 1
4157 11:33:10.734819 9, 0x0, sum = 2
4158 11:33:10.737907 10, 0x0, sum = 3
4159 11:33:10.737976 11, 0x0, sum = 4
4160 11:33:10.741192 best_step = 9
4161 11:33:10.741260
4162 11:33:10.741316 ==
4163 11:33:10.745018 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 11:33:10.748151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:33:10.748227 ==
4166 11:33:10.751549 RX Vref Scan: 1
4167 11:33:10.751622
4168 11:33:10.751680 RX Vref 0 -> 0, step: 1
4169 11:33:10.751733
4170 11:33:10.754929 RX Delay -179 -> 252, step: 8
4171 11:33:10.755003
4172 11:33:10.758275 Set Vref, RX VrefLevel [Byte0]: 54
4173 11:33:10.761756 [Byte1]: 48
4174 11:33:10.765547
4175 11:33:10.765621 Final RX Vref Byte 0 = 54 to rank0
4176 11:33:10.768743 Final RX Vref Byte 1 = 48 to rank0
4177 11:33:10.771900 Final RX Vref Byte 0 = 54 to rank1
4178 11:33:10.775480 Final RX Vref Byte 1 = 48 to rank1==
4179 11:33:10.778467 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 11:33:10.785204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:33:10.785279 ==
4182 11:33:10.785336 DQS Delay:
4183 11:33:10.785389 DQS0 = 0, DQS1 = 0
4184 11:33:10.788613 DQM Delay:
4185 11:33:10.788687 DQM0 = 52, DQM1 = 47
4186 11:33:10.791908 DQ Delay:
4187 11:33:10.795224 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4188 11:33:10.798494 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4189 11:33:10.798564 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4190 11:33:10.805221 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4191 11:33:10.805304
4192 11:33:10.805377
4193 11:33:10.812151 [DQSOSCAuto] RK0, (LSB)MR18= 0x796c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4194 11:33:10.814859 CH0 RK0: MR19=808, MR18=796C
4195 11:33:10.822202 CH0_RK0: MR19=0x808, MR18=0x796C, DQSOSC=387, MR23=63, INC=175, DEC=116
4196 11:33:10.822295
4197 11:33:10.824872 ----->DramcWriteLeveling(PI) begin...
4198 11:33:10.825007 ==
4199 11:33:10.828198 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 11:33:10.831522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 11:33:10.831592 ==
4202 11:33:10.834889 Write leveling (Byte 0): 33 => 33
4203 11:33:10.838092 Write leveling (Byte 1): 30 => 30
4204 11:33:10.841858 DramcWriteLeveling(PI) end<-----
4205 11:33:10.841955
4206 11:33:10.842075 ==
4207 11:33:10.844836 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 11:33:10.848008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 11:33:10.848075 ==
4210 11:33:10.851615 [Gating] SW mode calibration
4211 11:33:10.857998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 11:33:10.864972 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4213 11:33:10.868298 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 11:33:10.874427 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 11:33:10.878276 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 11:33:10.881653 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4217 11:33:10.888196 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (1 1) (1 1)
4218 11:33:10.891393 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:33:10.894857 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:33:10.897910 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:33:10.904662 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:33:10.908049 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:33:10.911220 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:33:10.918018 0 10 12 | B1->B0 | 2727 2e2d | 0 1 | (0 0) (0 0)
4225 11:33:10.921719 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4226 11:33:10.924931 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:33:10.931657 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:33:10.934892 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:33:10.938277 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:33:10.944544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:33:10.947861 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:33:10.951102 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4233 11:33:10.958138 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4234 11:33:10.961260 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:33:10.964499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:33:10.971128 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:33:10.974224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:33:10.977694 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:33:10.984315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:33:10.987718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:33:10.991033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:33:10.997871 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:33:11.001175 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:33:11.004428 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:33:11.010889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:33:11.014488 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:33:11.017751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:33:11.021227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4249 11:33:11.024288 Total UI for P1: 0, mck2ui 16
4250 11:33:11.027483 best dqsien dly found for B0: ( 0, 13, 10)
4251 11:33:11.034260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:33:11.037369 Total UI for P1: 0, mck2ui 16
4253 11:33:11.040776 best dqsien dly found for B1: ( 0, 13, 14)
4254 11:33:11.044146 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4255 11:33:11.047484 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4256 11:33:11.047554
4257 11:33:11.050841 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4258 11:33:11.054397 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4259 11:33:11.057564 [Gating] SW calibration Done
4260 11:33:11.057660 ==
4261 11:33:11.060908 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 11:33:11.064126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 11:33:11.064197 ==
4264 11:33:11.067986 RX Vref Scan: 0
4265 11:33:11.068053
4266 11:33:11.068109 RX Vref 0 -> 0, step: 1
4267 11:33:11.070714
4268 11:33:11.070779 RX Delay -230 -> 252, step: 16
4269 11:33:11.077858 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4270 11:33:11.081019 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4271 11:33:11.083944 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4272 11:33:11.087703 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4273 11:33:11.094268 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4274 11:33:11.097670 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4275 11:33:11.100943 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4276 11:33:11.104223 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4277 11:33:11.107705 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4278 11:33:11.114169 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4279 11:33:11.117307 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4280 11:33:11.120960 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4281 11:33:11.124036 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4282 11:33:11.130857 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4283 11:33:11.134250 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4284 11:33:11.137405 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4285 11:33:11.137506 ==
4286 11:33:11.140544 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 11:33:11.143973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 11:33:11.147302 ==
4289 11:33:11.147369 DQS Delay:
4290 11:33:11.147425 DQS0 = 0, DQS1 = 0
4291 11:33:11.150727 DQM Delay:
4292 11:33:11.150793 DQM0 = 52, DQM1 = 43
4293 11:33:11.150847 DQ Delay:
4294 11:33:11.153927 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4295 11:33:11.157386 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4296 11:33:11.160734 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4297 11:33:11.164177 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4298 11:33:11.164243
4299 11:33:11.164322
4300 11:33:11.167401 ==
4301 11:33:11.170639 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 11:33:11.173927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 11:33:11.174026 ==
4304 11:33:11.174096
4305 11:33:11.174153
4306 11:33:11.177285 TX Vref Scan disable
4307 11:33:11.177346 == TX Byte 0 ==
4308 11:33:11.183988 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4309 11:33:11.187236 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4310 11:33:11.187308 == TX Byte 1 ==
4311 11:33:11.193647 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4312 11:33:11.197274 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4313 11:33:11.197342 ==
4314 11:33:11.200513 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 11:33:11.203906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 11:33:11.203977 ==
4317 11:33:11.204036
4318 11:33:11.204090
4319 11:33:11.207206 TX Vref Scan disable
4320 11:33:11.210676 == TX Byte 0 ==
4321 11:33:11.214036 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4322 11:33:11.217314 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4323 11:33:11.220124 == TX Byte 1 ==
4324 11:33:11.223532 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4325 11:33:11.226844 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4326 11:33:11.226918
4327 11:33:11.230230 [DATLAT]
4328 11:33:11.230297 Freq=600, CH0 RK1
4329 11:33:11.230352
4330 11:33:11.233906 DATLAT Default: 0x9
4331 11:33:11.233994 0, 0xFFFF, sum = 0
4332 11:33:11.237053 1, 0xFFFF, sum = 0
4333 11:33:11.237118 2, 0xFFFF, sum = 0
4334 11:33:11.240171 3, 0xFFFF, sum = 0
4335 11:33:11.240236 4, 0xFFFF, sum = 0
4336 11:33:11.243412 5, 0xFFFF, sum = 0
4337 11:33:11.243483 6, 0xFFFF, sum = 0
4338 11:33:11.246863 7, 0xFFFF, sum = 0
4339 11:33:11.246930 8, 0x0, sum = 1
4340 11:33:11.250036 9, 0x0, sum = 2
4341 11:33:11.250102 10, 0x0, sum = 3
4342 11:33:11.253226 11, 0x0, sum = 4
4343 11:33:11.253295 best_step = 9
4344 11:33:11.253352
4345 11:33:11.253410 ==
4346 11:33:11.256953 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:33:11.263613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:33:11.263684 ==
4349 11:33:11.263741 RX Vref Scan: 0
4350 11:33:11.263795
4351 11:33:11.266482 RX Vref 0 -> 0, step: 1
4352 11:33:11.266572
4353 11:33:11.270329 RX Delay -163 -> 252, step: 8
4354 11:33:11.273595 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4355 11:33:11.276732 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4356 11:33:11.283414 iDelay=197, Bit 2, Center 48 (-99 ~ 196) 296
4357 11:33:11.286793 iDelay=197, Bit 3, Center 48 (-99 ~ 196) 296
4358 11:33:11.290111 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4359 11:33:11.293414 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4360 11:33:11.296699 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4361 11:33:11.303151 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4362 11:33:11.306352 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4363 11:33:11.309676 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4364 11:33:11.313065 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4365 11:33:11.316372 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4366 11:33:11.323186 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4367 11:33:11.326508 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4368 11:33:11.329789 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4369 11:33:11.333213 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4370 11:33:11.333286 ==
4371 11:33:11.336517 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 11:33:11.343095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 11:33:11.343169 ==
4374 11:33:11.343230 DQS Delay:
4375 11:33:11.346358 DQS0 = 0, DQS1 = 0
4376 11:33:11.346424 DQM Delay:
4377 11:33:11.349368 DQM0 = 51, DQM1 = 46
4378 11:33:11.349432 DQ Delay:
4379 11:33:11.353040 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4380 11:33:11.356404 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4381 11:33:11.359865 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4382 11:33:11.363117 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4383 11:33:11.363223
4384 11:33:11.363310
4385 11:33:11.369219 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
4386 11:33:11.373037 CH0 RK1: MR19=808, MR18=6E2F
4387 11:33:11.379091 CH0_RK1: MR19=0x808, MR18=0x6E2F, DQSOSC=389, MR23=63, INC=173, DEC=115
4388 11:33:11.382578 [RxdqsGatingPostProcess] freq 600
4389 11:33:11.389563 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4390 11:33:11.389656 Pre-setting of DQS Precalculation
4391 11:33:11.396012 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4392 11:33:11.396112 ==
4393 11:33:11.399243 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 11:33:11.402438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 11:33:11.402506 ==
4396 11:33:11.408861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 11:33:11.416009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4398 11:33:11.419371 [CA 0] Center 36 (5~67) winsize 63
4399 11:33:11.422749 [CA 1] Center 36 (5~67) winsize 63
4400 11:33:11.426243 [CA 2] Center 34 (4~65) winsize 62
4401 11:33:11.429595 [CA 3] Center 34 (4~65) winsize 62
4402 11:33:11.432890 [CA 4] Center 34 (4~65) winsize 62
4403 11:33:11.436243 [CA 5] Center 34 (3~65) winsize 63
4404 11:33:11.436335
4405 11:33:11.439668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4406 11:33:11.439734
4407 11:33:11.442908 [CATrainingPosCal] consider 1 rank data
4408 11:33:11.446222 u2DelayCellTimex100 = 270/100 ps
4409 11:33:11.449629 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4410 11:33:11.452933 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4411 11:33:11.456327 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4412 11:33:11.458975 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 11:33:11.462725 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 11:33:11.465786 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4415 11:33:11.465874
4416 11:33:11.472723 CA PerBit enable=1, Macro0, CA PI delay=34
4417 11:33:11.472793
4418 11:33:11.472848 [CBTSetCACLKResult] CA Dly = 34
4419 11:33:11.476247 CS Dly: 5 (0~36)
4420 11:33:11.476333 ==
4421 11:33:11.479457 Dram Type= 6, Freq= 0, CH_1, rank 1
4422 11:33:11.482193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 11:33:11.482261 ==
4424 11:33:11.489246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 11:33:11.495790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4426 11:33:11.499166 [CA 0] Center 36 (5~67) winsize 63
4427 11:33:11.502348 [CA 1] Center 36 (5~67) winsize 63
4428 11:33:11.505533 [CA 2] Center 34 (4~65) winsize 62
4429 11:33:11.509323 [CA 3] Center 34 (4~65) winsize 62
4430 11:33:11.512311 [CA 4] Center 35 (4~66) winsize 63
4431 11:33:11.515782 [CA 5] Center 34 (3~65) winsize 63
4432 11:33:11.515868
4433 11:33:11.518861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4434 11:33:11.518945
4435 11:33:11.522027 [CATrainingPosCal] consider 2 rank data
4436 11:33:11.525202 u2DelayCellTimex100 = 270/100 ps
4437 11:33:11.529165 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4438 11:33:11.531831 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4439 11:33:11.535188 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4440 11:33:11.538568 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4441 11:33:11.541975 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4442 11:33:11.548893 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4443 11:33:11.548980
4444 11:33:11.552153 CA PerBit enable=1, Macro0, CA PI delay=34
4445 11:33:11.552226
4446 11:33:11.555579 [CBTSetCACLKResult] CA Dly = 34
4447 11:33:11.555643 CS Dly: 6 (0~39)
4448 11:33:11.555701
4449 11:33:11.558332 ----->DramcWriteLeveling(PI) begin...
4450 11:33:11.558400 ==
4451 11:33:11.562305 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 11:33:11.565599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 11:33:11.568310 ==
4454 11:33:11.568397 Write leveling (Byte 0): 30 => 30
4455 11:33:11.571990 Write leveling (Byte 1): 31 => 31
4456 11:33:11.575216 DramcWriteLeveling(PI) end<-----
4457 11:33:11.575279
4458 11:33:11.575330 ==
4459 11:33:11.578920 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 11:33:11.585475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 11:33:11.585565 ==
4462 11:33:11.585655 [Gating] SW mode calibration
4463 11:33:11.595423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4464 11:33:11.598647 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4465 11:33:11.602329 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 11:33:11.608702 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 11:33:11.612163 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4468 11:33:11.615001 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 0)
4469 11:33:11.621837 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 11:33:11.625318 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 11:33:11.628899 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:33:11.635329 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:33:11.638306 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:33:11.642177 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:33:11.648279 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:33:11.651601 0 10 12 | B1->B0 | 3838 3939 | 1 1 | (0 0) (0 0)
4477 11:33:11.655497 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 11:33:11.661530 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 11:33:11.665396 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:33:11.668722 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:33:11.674984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:33:11.678171 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:33:11.681877 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:33:11.688221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4485 11:33:11.691947 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 11:33:11.695364 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 11:33:11.701898 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:33:11.705246 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:33:11.708665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:33:11.711828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:33:11.718794 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:33:11.722122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:33:11.725251 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:33:11.731720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:33:11.734847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:33:11.738575 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:33:11.745366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:33:11.748470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:33:11.751503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:33:11.758811 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4501 11:33:11.758886 Total UI for P1: 0, mck2ui 16
4502 11:33:11.765446 best dqsien dly found for B0: ( 0, 13, 10)
4503 11:33:11.768814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:33:11.772250 Total UI for P1: 0, mck2ui 16
4505 11:33:11.774878 best dqsien dly found for B1: ( 0, 13, 12)
4506 11:33:11.778332 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4507 11:33:11.781653 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4508 11:33:11.781733
4509 11:33:11.785045 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4510 11:33:11.788160 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4511 11:33:11.791794 [Gating] SW calibration Done
4512 11:33:11.791863 ==
4513 11:33:11.794937 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 11:33:11.798192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 11:33:11.801459 ==
4516 11:33:11.801528 RX Vref Scan: 0
4517 11:33:11.801588
4518 11:33:11.804863 RX Vref 0 -> 0, step: 1
4519 11:33:11.804927
4520 11:33:11.808152 RX Delay -230 -> 252, step: 16
4521 11:33:11.812079 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4522 11:33:11.815255 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4523 11:33:11.818720 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4524 11:33:11.825211 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4525 11:33:11.827968 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4526 11:33:11.831798 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4527 11:33:11.835270 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4528 11:33:11.838655 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4529 11:33:11.845217 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4530 11:33:11.848370 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4531 11:33:11.851612 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4532 11:33:11.854826 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4533 11:33:11.861870 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4534 11:33:11.865395 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4535 11:33:11.868505 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4536 11:33:11.871960 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4537 11:33:11.872034 ==
4538 11:33:11.875283 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 11:33:11.882021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 11:33:11.882109 ==
4541 11:33:11.882166 DQS Delay:
4542 11:33:11.882220 DQS0 = 0, DQS1 = 0
4543 11:33:11.885325 DQM Delay:
4544 11:33:11.885392 DQM0 = 49, DQM1 = 46
4545 11:33:11.888207 DQ Delay:
4546 11:33:11.891471 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4547 11:33:11.891539 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4548 11:33:11.894903 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4549 11:33:11.898669 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4550 11:33:11.901594
4551 11:33:11.901660
4552 11:33:11.901715 ==
4553 11:33:11.905505 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 11:33:11.908242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 11:33:11.908316 ==
4556 11:33:11.908375
4557 11:33:11.908428
4558 11:33:11.911465 TX Vref Scan disable
4559 11:33:11.911533 == TX Byte 0 ==
4560 11:33:11.918219 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 11:33:11.922033 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 11:33:11.922102 == TX Byte 1 ==
4563 11:33:11.928644 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4564 11:33:11.932028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4565 11:33:11.932101 ==
4566 11:33:11.935310 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:33:11.938438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:33:11.938506 ==
4569 11:33:11.938563
4570 11:33:11.938617
4571 11:33:11.941619 TX Vref Scan disable
4572 11:33:11.945069 == TX Byte 0 ==
4573 11:33:11.948533 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4574 11:33:11.951538 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4575 11:33:11.954727 == TX Byte 1 ==
4576 11:33:11.958577 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4577 11:33:11.961995 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4578 11:33:11.962078
4579 11:33:11.964691 [DATLAT]
4580 11:33:11.964768 Freq=600, CH1 RK0
4581 11:33:11.964828
4582 11:33:11.968719 DATLAT Default: 0x9
4583 11:33:11.968788 0, 0xFFFF, sum = 0
4584 11:33:11.971856 1, 0xFFFF, sum = 0
4585 11:33:11.971922 2, 0xFFFF, sum = 0
4586 11:33:11.974792 3, 0xFFFF, sum = 0
4587 11:33:11.974857 4, 0xFFFF, sum = 0
4588 11:33:11.978383 5, 0xFFFF, sum = 0
4589 11:33:11.978448 6, 0xFFFF, sum = 0
4590 11:33:11.981983 7, 0xFFFF, sum = 0
4591 11:33:11.982072 8, 0x0, sum = 1
4592 11:33:11.984679 9, 0x0, sum = 2
4593 11:33:11.984781 10, 0x0, sum = 3
4594 11:33:11.988183 11, 0x0, sum = 4
4595 11:33:11.988285 best_step = 9
4596 11:33:11.988378
4597 11:33:11.988460 ==
4598 11:33:11.991504 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 11:33:11.995022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:33:11.998470 ==
4601 11:33:11.998536 RX Vref Scan: 1
4602 11:33:11.998592
4603 11:33:12.001750 RX Vref 0 -> 0, step: 1
4604 11:33:12.001818
4605 11:33:12.005026 RX Delay -163 -> 252, step: 8
4606 11:33:12.005120
4607 11:33:12.008223 Set Vref, RX VrefLevel [Byte0]: 54
4608 11:33:12.011758 [Byte1]: 54
4609 11:33:12.011831
4610 11:33:12.014878 Final RX Vref Byte 0 = 54 to rank0
4611 11:33:12.018513 Final RX Vref Byte 1 = 54 to rank0
4612 11:33:12.021484 Final RX Vref Byte 0 = 54 to rank1
4613 11:33:12.024843 Final RX Vref Byte 1 = 54 to rank1==
4614 11:33:12.028095 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 11:33:12.031899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:33:12.031974 ==
4617 11:33:12.032034 DQS Delay:
4618 11:33:12.035433 DQS0 = 0, DQS1 = 0
4619 11:33:12.035525 DQM Delay:
4620 11:33:12.038154 DQM0 = 48, DQM1 = 44
4621 11:33:12.038226 DQ Delay:
4622 11:33:12.041490 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4623 11:33:12.044825 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4624 11:33:12.048223 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4625 11:33:12.051998 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4626 11:33:12.052067
4627 11:33:12.052122
4628 11:33:12.061562 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4629 11:33:12.061638 CH1 RK0: MR19=808, MR18=4B70
4630 11:33:12.068270 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4631 11:33:12.068341
4632 11:33:12.071695 ----->DramcWriteLeveling(PI) begin...
4633 11:33:12.071763 ==
4634 11:33:12.075073 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 11:33:12.081278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 11:33:12.081348 ==
4637 11:33:12.084488 Write leveling (Byte 0): 28 => 28
4638 11:33:12.088244 Write leveling (Byte 1): 31 => 31
4639 11:33:12.088316 DramcWriteLeveling(PI) end<-----
4640 11:33:12.088373
4641 11:33:12.091375 ==
4642 11:33:12.094813 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 11:33:12.098171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:33:12.098245 ==
4645 11:33:12.101051 [Gating] SW mode calibration
4646 11:33:12.108041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4647 11:33:12.111614 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4648 11:33:12.118205 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 11:33:12.121384 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 11:33:12.124670 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 11:33:12.131244 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 1)
4652 11:33:12.134379 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4653 11:33:12.137654 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 11:33:12.144515 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:33:12.147901 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:33:12.151262 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 11:33:12.157825 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:33:12.161077 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:33:12.164230 0 10 12 | B1->B0 | 3a3a 3737 | 0 0 | (1 1) (1 1)
4660 11:33:12.171222 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 11:33:12.174484 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 11:33:12.177907 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 11:33:12.184596 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:33:12.187929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:33:12.191244 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:33:12.197339 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:33:12.200648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 11:33:12.204145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 11:33:12.207878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:33:12.214080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:33:12.217430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:33:12.220944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:33:12.227401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:33:12.230771 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:33:12.234154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:33:12.240728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:33:12.244405 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:33:12.247492 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:33:12.254593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:33:12.257930 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:33:12.261232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:33:12.267979 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:33:12.271291 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4684 11:33:12.273973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:33:12.277727 Total UI for P1: 0, mck2ui 16
4686 11:33:12.280781 best dqsien dly found for B0: ( 0, 13, 14)
4687 11:33:12.284673 Total UI for P1: 0, mck2ui 16
4688 11:33:12.287330 best dqsien dly found for B1: ( 0, 13, 12)
4689 11:33:12.290697 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4690 11:33:12.294169 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4691 11:33:12.294234
4692 11:33:12.297576 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4693 11:33:12.304423 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4694 11:33:12.304517 [Gating] SW calibration Done
4695 11:33:12.304608 ==
4696 11:33:12.307782 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 11:33:12.314633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 11:33:12.314710 ==
4699 11:33:12.314770 RX Vref Scan: 0
4700 11:33:12.314825
4701 11:33:12.317833 RX Vref 0 -> 0, step: 1
4702 11:33:12.317909
4703 11:33:12.321267 RX Delay -230 -> 252, step: 16
4704 11:33:12.324491 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4705 11:33:12.327705 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4706 11:33:12.331266 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4707 11:33:12.338124 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4708 11:33:12.340877 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4709 11:33:12.344735 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4710 11:33:12.348021 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4711 11:33:12.354383 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4712 11:33:12.357548 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4713 11:33:12.361357 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4714 11:33:12.364558 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4715 11:33:12.367864 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4716 11:33:12.374637 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4717 11:33:12.377377 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4718 11:33:12.381352 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4719 11:33:12.384520 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4720 11:33:12.387650 ==
4721 11:33:12.387740 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 11:33:12.394309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 11:33:12.394384 ==
4724 11:33:12.394447 DQS Delay:
4725 11:33:12.397813 DQS0 = 0, DQS1 = 0
4726 11:33:12.397897 DQM Delay:
4727 11:33:12.401226 DQM0 = 48, DQM1 = 48
4728 11:33:12.401308 DQ Delay:
4729 11:33:12.404545 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4730 11:33:12.408012 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4731 11:33:12.410578 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4732 11:33:12.413929 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4733 11:33:12.414046
4734 11:33:12.414105
4735 11:33:12.414161 ==
4736 11:33:12.417356 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 11:33:12.420861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 11:33:12.420928 ==
4739 11:33:12.420983
4740 11:33:12.421034
4741 11:33:12.424173 TX Vref Scan disable
4742 11:33:12.427466 == TX Byte 0 ==
4743 11:33:12.430940 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4744 11:33:12.434258 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4745 11:33:12.437630 == TX Byte 1 ==
4746 11:33:12.440908 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4747 11:33:12.444094 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4748 11:33:12.444165 ==
4749 11:33:12.447848 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:33:12.450864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:33:12.454455 ==
4752 11:33:12.454523
4753 11:33:12.454582
4754 11:33:12.454634 TX Vref Scan disable
4755 11:33:12.457881 == TX Byte 0 ==
4756 11:33:12.461384 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4757 11:33:12.467751 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4758 11:33:12.467819 == TX Byte 1 ==
4759 11:33:12.471607 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 11:33:12.477914 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 11:33:12.478011
4762 11:33:12.478104 [DATLAT]
4763 11:33:12.478174 Freq=600, CH1 RK1
4764 11:33:12.478225
4765 11:33:12.480974 DATLAT Default: 0x9
4766 11:33:12.481048 0, 0xFFFF, sum = 0
4767 11:33:12.484478 1, 0xFFFF, sum = 0
4768 11:33:12.488013 2, 0xFFFF, sum = 0
4769 11:33:12.488085 3, 0xFFFF, sum = 0
4770 11:33:12.490967 4, 0xFFFF, sum = 0
4771 11:33:12.491034 5, 0xFFFF, sum = 0
4772 11:33:12.494407 6, 0xFFFF, sum = 0
4773 11:33:12.494474 7, 0xFFFF, sum = 0
4774 11:33:12.498002 8, 0x0, sum = 1
4775 11:33:12.498078 9, 0x0, sum = 2
4776 11:33:12.498134 10, 0x0, sum = 3
4777 11:33:12.501118 11, 0x0, sum = 4
4778 11:33:12.501183 best_step = 9
4779 11:33:12.501241
4780 11:33:12.501292 ==
4781 11:33:12.504112 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:33:12.511165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:33:12.511242 ==
4784 11:33:12.511306 RX Vref Scan: 0
4785 11:33:12.511360
4786 11:33:12.514553 RX Vref 0 -> 0, step: 1
4787 11:33:12.514618
4788 11:33:12.518069 RX Delay -163 -> 252, step: 8
4789 11:33:12.521423 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4790 11:33:12.527511 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4791 11:33:12.531042 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4792 11:33:12.534533 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4793 11:33:12.537315 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4794 11:33:12.540663 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4795 11:33:12.547356 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4796 11:33:12.550736 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4797 11:33:12.554689 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4798 11:33:12.558084 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4799 11:33:12.560901 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4800 11:33:12.567643 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4801 11:33:12.570727 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4802 11:33:12.574587 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4803 11:33:12.577697 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4804 11:33:12.580857 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4805 11:33:12.584240 ==
4806 11:33:12.587739 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 11:33:12.590859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 11:33:12.590933 ==
4809 11:33:12.590993 DQS Delay:
4810 11:33:12.594615 DQS0 = 0, DQS1 = 0
4811 11:33:12.594686 DQM Delay:
4812 11:33:12.597840 DQM0 = 48, DQM1 = 46
4813 11:33:12.597906 DQ Delay:
4814 11:33:12.600624 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4815 11:33:12.604594 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =48
4816 11:33:12.607234 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4817 11:33:12.610948 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4818 11:33:12.611016
4819 11:33:12.611072
4820 11:33:12.617089 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4821 11:33:12.621048 CH1 RK1: MR19=808, MR18=6F26
4822 11:33:12.627156 CH1_RK1: MR19=0x808, MR18=0x6F26, DQSOSC=389, MR23=63, INC=173, DEC=115
4823 11:33:12.630922 [RxdqsGatingPostProcess] freq 600
4824 11:33:12.637607 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4825 11:33:12.637689 Pre-setting of DQS Precalculation
4826 11:33:12.644466 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4827 11:33:12.650604 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4828 11:33:12.657213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4829 11:33:12.657287
4830 11:33:12.657366
4831 11:33:12.660673 [Calibration Summary] 1200 Mbps
4832 11:33:12.664073 CH 0, Rank 0
4833 11:33:12.664142 SW Impedance : PASS
4834 11:33:12.667555 DUTY Scan : NO K
4835 11:33:12.667637 ZQ Calibration : PASS
4836 11:33:12.670955 Jitter Meter : NO K
4837 11:33:12.674265 CBT Training : PASS
4838 11:33:12.674339 Write leveling : PASS
4839 11:33:12.677509 RX DQS gating : PASS
4840 11:33:12.680781 RX DQ/DQS(RDDQC) : PASS
4841 11:33:12.680875 TX DQ/DQS : PASS
4842 11:33:12.684196 RX DATLAT : PASS
4843 11:33:12.687590 RX DQ/DQS(Engine): PASS
4844 11:33:12.687661 TX OE : NO K
4845 11:33:12.690976 All Pass.
4846 11:33:12.691045
4847 11:33:12.691100 CH 0, Rank 1
4848 11:33:12.694145 SW Impedance : PASS
4849 11:33:12.694215 DUTY Scan : NO K
4850 11:33:12.697251 ZQ Calibration : PASS
4851 11:33:12.700687 Jitter Meter : NO K
4852 11:33:12.700780 CBT Training : PASS
4853 11:33:12.703949 Write leveling : PASS
4854 11:33:12.707189 RX DQS gating : PASS
4855 11:33:12.707259 RX DQ/DQS(RDDQC) : PASS
4856 11:33:12.710496 TX DQ/DQS : PASS
4857 11:33:12.710563 RX DATLAT : PASS
4858 11:33:12.713775 RX DQ/DQS(Engine): PASS
4859 11:33:12.717086 TX OE : NO K
4860 11:33:12.717158 All Pass.
4861 11:33:12.717214
4862 11:33:12.717266 CH 1, Rank 0
4863 11:33:12.720356 SW Impedance : PASS
4864 11:33:12.724200 DUTY Scan : NO K
4865 11:33:12.724270 ZQ Calibration : PASS
4866 11:33:12.727565 Jitter Meter : NO K
4867 11:33:12.730706 CBT Training : PASS
4868 11:33:12.730776 Write leveling : PASS
4869 11:33:12.734082 RX DQS gating : PASS
4870 11:33:12.737429 RX DQ/DQS(RDDQC) : PASS
4871 11:33:12.737516 TX DQ/DQS : PASS
4872 11:33:12.740330 RX DATLAT : PASS
4873 11:33:12.743624 RX DQ/DQS(Engine): PASS
4874 11:33:12.743717 TX OE : NO K
4875 11:33:12.747088 All Pass.
4876 11:33:12.747154
4877 11:33:12.747217 CH 1, Rank 1
4878 11:33:12.750611 SW Impedance : PASS
4879 11:33:12.750683 DUTY Scan : NO K
4880 11:33:12.754091 ZQ Calibration : PASS
4881 11:33:12.757342 Jitter Meter : NO K
4882 11:33:12.757412 CBT Training : PASS
4883 11:33:12.760634 Write leveling : PASS
4884 11:33:12.763904 RX DQS gating : PASS
4885 11:33:12.763970 RX DQ/DQS(RDDQC) : PASS
4886 11:33:12.767316 TX DQ/DQS : PASS
4887 11:33:12.767382 RX DATLAT : PASS
4888 11:33:12.770685 RX DQ/DQS(Engine): PASS
4889 11:33:12.773396 TX OE : NO K
4890 11:33:12.773461 All Pass.
4891 11:33:12.773515
4892 11:33:12.776800 DramC Write-DBI off
4893 11:33:12.780218 PER_BANK_REFRESH: Hybrid Mode
4894 11:33:12.780291 TX_TRACKING: ON
4895 11:33:12.790148 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4896 11:33:12.793465 [FAST_K] Save calibration result to emmc
4897 11:33:12.796884 dramc_set_vcore_voltage set vcore to 662500
4898 11:33:12.796951 Read voltage for 933, 3
4899 11:33:12.800132 Vio18 = 0
4900 11:33:12.800198 Vcore = 662500
4901 11:33:12.800251 Vdram = 0
4902 11:33:12.803477 Vddq = 0
4903 11:33:12.803542 Vmddr = 0
4904 11:33:12.806777 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4905 11:33:12.813774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4906 11:33:12.817044 MEM_TYPE=3, freq_sel=17
4907 11:33:12.820432 sv_algorithm_assistance_LP4_1600
4908 11:33:12.823231 ============ PULL DRAM RESETB DOWN ============
4909 11:33:12.826523 ========== PULL DRAM RESETB DOWN end =========
4910 11:33:12.833669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4911 11:33:12.837143 ===================================
4912 11:33:12.837215 LPDDR4 DRAM CONFIGURATION
4913 11:33:12.840506 ===================================
4914 11:33:12.843863 EX_ROW_EN[0] = 0x0
4915 11:33:12.843928 EX_ROW_EN[1] = 0x0
4916 11:33:12.847203 LP4Y_EN = 0x0
4917 11:33:12.847267 WORK_FSP = 0x0
4918 11:33:12.850274 WL = 0x3
4919 11:33:12.853758 RL = 0x3
4920 11:33:12.853868 BL = 0x2
4921 11:33:12.856863 RPST = 0x0
4922 11:33:12.856933 RD_PRE = 0x0
4923 11:33:12.859825 WR_PRE = 0x1
4924 11:33:12.859932 WR_PST = 0x0
4925 11:33:12.863308 DBI_WR = 0x0
4926 11:33:12.863387 DBI_RD = 0x0
4927 11:33:12.866420 OTF = 0x1
4928 11:33:12.869860 ===================================
4929 11:33:12.873453 ===================================
4930 11:33:12.873526 ANA top config
4931 11:33:12.876254 ===================================
4932 11:33:12.880243 DLL_ASYNC_EN = 0
4933 11:33:12.883071 ALL_SLAVE_EN = 1
4934 11:33:12.883140 NEW_RANK_MODE = 1
4935 11:33:12.886428 DLL_IDLE_MODE = 1
4936 11:33:12.889896 LP45_APHY_COMB_EN = 1
4937 11:33:12.893216 TX_ODT_DIS = 1
4938 11:33:12.896678 NEW_8X_MODE = 1
4939 11:33:12.899800 ===================================
4940 11:33:12.903209 ===================================
4941 11:33:12.903333 data_rate = 1866
4942 11:33:12.906368 CKR = 1
4943 11:33:12.909701 DQ_P2S_RATIO = 8
4944 11:33:12.912985 ===================================
4945 11:33:12.916271 CA_P2S_RATIO = 8
4946 11:33:12.919570 DQ_CA_OPEN = 0
4947 11:33:12.923357 DQ_SEMI_OPEN = 0
4948 11:33:12.923427 CA_SEMI_OPEN = 0
4949 11:33:12.926668 CA_FULL_RATE = 0
4950 11:33:12.929394 DQ_CKDIV4_EN = 1
4951 11:33:12.932624 CA_CKDIV4_EN = 1
4952 11:33:12.936050 CA_PREDIV_EN = 0
4953 11:33:12.939318 PH8_DLY = 0
4954 11:33:12.939390 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4955 11:33:12.942744 DQ_AAMCK_DIV = 4
4956 11:33:12.946220 CA_AAMCK_DIV = 4
4957 11:33:12.949577 CA_ADMCK_DIV = 4
4958 11:33:12.952925 DQ_TRACK_CA_EN = 0
4959 11:33:12.956289 CA_PICK = 933
4960 11:33:12.956360 CA_MCKIO = 933
4961 11:33:12.959574 MCKIO_SEMI = 0
4962 11:33:12.962928 PLL_FREQ = 3732
4963 11:33:12.966219 DQ_UI_PI_RATIO = 32
4964 11:33:12.969561 CA_UI_PI_RATIO = 0
4965 11:33:12.972867 ===================================
4966 11:33:12.976062 ===================================
4967 11:33:12.979071 memory_type:LPDDR4
4968 11:33:12.979148 GP_NUM : 10
4969 11:33:12.982701 SRAM_EN : 1
4970 11:33:12.982777 MD32_EN : 0
4971 11:33:12.986246 ===================================
4972 11:33:12.989299 [ANA_INIT] >>>>>>>>>>>>>>
4973 11:33:12.992573 <<<<<< [CONFIGURE PHASE]: ANA_TX
4974 11:33:12.995974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4975 11:33:12.999274 ===================================
4976 11:33:13.002511 data_rate = 1866,PCW = 0X8f00
4977 11:33:13.005770 ===================================
4978 11:33:13.008941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4979 11:33:13.015771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 11:33:13.018986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 11:33:13.025660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4982 11:33:13.028836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4983 11:33:13.032793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4984 11:33:13.032863 [ANA_INIT] flow start
4985 11:33:13.035831 [ANA_INIT] PLL >>>>>>>>
4986 11:33:13.038994 [ANA_INIT] PLL <<<<<<<<
4987 11:33:13.039064 [ANA_INIT] MIDPI >>>>>>>>
4988 11:33:13.042178 [ANA_INIT] MIDPI <<<<<<<<
4989 11:33:13.046110 [ANA_INIT] DLL >>>>>>>>
4990 11:33:13.046177 [ANA_INIT] flow end
4991 11:33:13.052096 ============ LP4 DIFF to SE enter ============
4992 11:33:13.055604 ============ LP4 DIFF to SE exit ============
4993 11:33:13.058903 [ANA_INIT] <<<<<<<<<<<<<
4994 11:33:13.062279 [Flow] Enable top DCM control >>>>>
4995 11:33:13.062345 [Flow] Enable top DCM control <<<<<
4996 11:33:13.065610 Enable DLL master slave shuffle
4997 11:33:13.072342 ==============================================================
4998 11:33:13.075534 Gating Mode config
4999 11:33:13.078931 ==============================================================
5000 11:33:13.082233 Config description:
5001 11:33:13.092278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5002 11:33:13.099054 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5003 11:33:13.102870 SELPH_MODE 0: By rank 1: By Phase
5004 11:33:13.108964 ==============================================================
5005 11:33:13.112152 GAT_TRACK_EN = 1
5006 11:33:13.115456 RX_GATING_MODE = 2
5007 11:33:13.115532 RX_GATING_TRACK_MODE = 2
5008 11:33:13.118821 SELPH_MODE = 1
5009 11:33:13.122307 PICG_EARLY_EN = 1
5010 11:33:13.125649 VALID_LAT_VALUE = 1
5011 11:33:13.132228 ==============================================================
5012 11:33:13.135787 Enter into Gating configuration >>>>
5013 11:33:13.139400 Exit from Gating configuration <<<<
5014 11:33:13.142515 Enter into DVFS_PRE_config >>>>>
5015 11:33:13.152469 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5016 11:33:13.155680 Exit from DVFS_PRE_config <<<<<
5017 11:33:13.159171 Enter into PICG configuration >>>>
5018 11:33:13.162610 Exit from PICG configuration <<<<
5019 11:33:13.166041 [RX_INPUT] configuration >>>>>
5020 11:33:13.168950 [RX_INPUT] configuration <<<<<
5021 11:33:13.172355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5022 11:33:13.178938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5023 11:33:13.185935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5024 11:33:13.192526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5025 11:33:13.195375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 11:33:13.202543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 11:33:13.205364 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5028 11:33:13.212142 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5029 11:33:13.215711 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5030 11:33:13.219044 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5031 11:33:13.222464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5032 11:33:13.229128 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 11:33:13.232428 ===================================
5034 11:33:13.232529 LPDDR4 DRAM CONFIGURATION
5035 11:33:13.235313 ===================================
5036 11:33:13.238691 EX_ROW_EN[0] = 0x0
5037 11:33:13.242223 EX_ROW_EN[1] = 0x0
5038 11:33:13.242287 LP4Y_EN = 0x0
5039 11:33:13.245600 WORK_FSP = 0x0
5040 11:33:13.245664 WL = 0x3
5041 11:33:13.248910 RL = 0x3
5042 11:33:13.248977 BL = 0x2
5043 11:33:13.252416 RPST = 0x0
5044 11:33:13.252509 RD_PRE = 0x0
5045 11:33:13.255737 WR_PRE = 0x1
5046 11:33:13.255802 WR_PST = 0x0
5047 11:33:13.258880 DBI_WR = 0x0
5048 11:33:13.258981 DBI_RD = 0x0
5049 11:33:13.261893 OTF = 0x1
5050 11:33:13.265709 ===================================
5051 11:33:13.268936 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5052 11:33:13.272265 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5053 11:33:13.279110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 11:33:13.281984 ===================================
5055 11:33:13.282083 LPDDR4 DRAM CONFIGURATION
5056 11:33:13.285572 ===================================
5057 11:33:13.289095 EX_ROW_EN[0] = 0x10
5058 11:33:13.289198 EX_ROW_EN[1] = 0x0
5059 11:33:13.292655 LP4Y_EN = 0x0
5060 11:33:13.292757 WORK_FSP = 0x0
5061 11:33:13.295487 WL = 0x3
5062 11:33:13.295596 RL = 0x3
5063 11:33:13.299028 BL = 0x2
5064 11:33:13.302676 RPST = 0x0
5065 11:33:13.302773 RD_PRE = 0x0
5066 11:33:13.305482 WR_PRE = 0x1
5067 11:33:13.305572 WR_PST = 0x0
5068 11:33:13.309101 DBI_WR = 0x0
5069 11:33:13.309170 DBI_RD = 0x0
5070 11:33:13.312592 OTF = 0x1
5071 11:33:13.316038 ===================================
5072 11:33:13.318653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5073 11:33:13.324304 nWR fixed to 30
5074 11:33:13.327984 [ModeRegInit_LP4] CH0 RK0
5075 11:33:13.328083 [ModeRegInit_LP4] CH0 RK1
5076 11:33:13.330796 [ModeRegInit_LP4] CH1 RK0
5077 11:33:13.334025 [ModeRegInit_LP4] CH1 RK1
5078 11:33:13.334120 match AC timing 9
5079 11:33:13.341013 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5080 11:33:13.344484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5081 11:33:13.347838 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5082 11:33:13.353905 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5083 11:33:13.357550 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5084 11:33:13.357627 ==
5085 11:33:13.360929 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 11:33:13.364520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 11:33:13.364620 ==
5088 11:33:13.370736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 11:33:13.377701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5090 11:33:13.380760 [CA 0] Center 37 (6~68) winsize 63
5091 11:33:13.384153 [CA 1] Center 37 (6~68) winsize 63
5092 11:33:13.387331 [CA 2] Center 34 (4~65) winsize 62
5093 11:33:13.390694 [CA 3] Center 34 (3~65) winsize 63
5094 11:33:13.393999 [CA 4] Center 33 (2~64) winsize 63
5095 11:33:13.397267 [CA 5] Center 32 (2~62) winsize 61
5096 11:33:13.397373
5097 11:33:13.400552 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5098 11:33:13.400622
5099 11:33:13.403991 [CATrainingPosCal] consider 1 rank data
5100 11:33:13.407494 u2DelayCellTimex100 = 270/100 ps
5101 11:33:13.410312 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5102 11:33:13.413686 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5103 11:33:13.417194 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5104 11:33:13.420625 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5105 11:33:13.423902 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5106 11:33:13.427301 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5107 11:33:13.430583
5108 11:33:13.433751 CA PerBit enable=1, Macro0, CA PI delay=32
5109 11:33:13.433845
5110 11:33:13.437404 [CBTSetCACLKResult] CA Dly = 32
5111 11:33:13.437497 CS Dly: 5 (0~36)
5112 11:33:13.437581 ==
5113 11:33:13.440473 Dram Type= 6, Freq= 0, CH_0, rank 1
5114 11:33:13.443640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:33:13.443710 ==
5116 11:33:13.450272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 11:33:13.457143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5118 11:33:13.460867 [CA 0] Center 37 (7~68) winsize 62
5119 11:33:13.464130 [CA 1] Center 37 (7~68) winsize 62
5120 11:33:13.467578 [CA 2] Center 34 (4~65) winsize 62
5121 11:33:13.470269 [CA 3] Center 34 (3~65) winsize 63
5122 11:33:13.473611 [CA 4] Center 32 (2~63) winsize 62
5123 11:33:13.477065 [CA 5] Center 32 (2~62) winsize 61
5124 11:33:13.477134
5125 11:33:13.480595 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5126 11:33:13.480693
5127 11:33:13.484064 [CATrainingPosCal] consider 2 rank data
5128 11:33:13.486764 u2DelayCellTimex100 = 270/100 ps
5129 11:33:13.490852 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5130 11:33:13.493800 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5131 11:33:13.496835 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5132 11:33:13.500477 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5133 11:33:13.506915 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5134 11:33:13.510414 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5135 11:33:13.510500
5136 11:33:13.513671 CA PerBit enable=1, Macro0, CA PI delay=32
5137 11:33:13.513783
5138 11:33:13.517060 [CBTSetCACLKResult] CA Dly = 32
5139 11:33:13.517171 CS Dly: 5 (0~37)
5140 11:33:13.517257
5141 11:33:13.519982 ----->DramcWriteLeveling(PI) begin...
5142 11:33:13.520091 ==
5143 11:33:13.523298 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 11:33:13.530362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 11:33:13.530464 ==
5146 11:33:13.533221 Write leveling (Byte 0): 31 => 31
5147 11:33:13.533318 Write leveling (Byte 1): 27 => 27
5148 11:33:13.536703 DramcWriteLeveling(PI) end<-----
5149 11:33:13.536794
5150 11:33:13.540403 ==
5151 11:33:13.540497 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 11:33:13.546888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 11:33:13.546992 ==
5154 11:33:13.550467 [Gating] SW mode calibration
5155 11:33:13.556669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5156 11:33:13.560098 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5157 11:33:13.567034 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5158 11:33:13.570688 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 11:33:13.573441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 11:33:13.580485 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 11:33:13.583436 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 11:33:13.586910 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 11:33:13.593318 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5164 11:33:13.596737 0 14 28 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
5165 11:33:13.600297 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5166 11:33:13.603346 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 11:33:13.610043 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 11:33:13.613446 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 11:33:13.617042 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 11:33:13.623626 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 11:33:13.626901 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5172 11:33:13.629896 0 15 28 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
5173 11:33:13.636810 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5174 11:33:13.640161 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 11:33:13.643604 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 11:33:13.650041 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:33:13.653302 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:33:13.657026 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 11:33:13.663318 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 11:33:13.666818 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5181 11:33:13.670110 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5182 11:33:13.676641 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 11:33:13.679813 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:33:13.683662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:33:13.690214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:33:13.693016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:33:13.696414 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:33:13.703077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:33:13.706496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:33:13.709892 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:33:13.716308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:33:13.719666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:33:13.722928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:33:13.726783 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:33:13.733485 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:33:13.736138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 11:33:13.740039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:33:13.743198 Total UI for P1: 0, mck2ui 16
5199 11:33:13.746357 best dqsien dly found for B0: ( 1, 2, 28)
5200 11:33:13.749419 Total UI for P1: 0, mck2ui 16
5201 11:33:13.753030 best dqsien dly found for B1: ( 1, 2, 30)
5202 11:33:13.756423 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5203 11:33:13.762898 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5204 11:33:13.762970
5205 11:33:13.766300 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5206 11:33:13.769725 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5207 11:33:13.773225 [Gating] SW calibration Done
5208 11:33:13.773316 ==
5209 11:33:13.775888 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 11:33:13.779825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 11:33:13.779911 ==
5212 11:33:13.779997 RX Vref Scan: 0
5213 11:33:13.782358
5214 11:33:13.782425 RX Vref 0 -> 0, step: 1
5215 11:33:13.782481
5216 11:33:13.785946 RX Delay -80 -> 252, step: 8
5217 11:33:13.789353 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5218 11:33:13.792643 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5219 11:33:13.799174 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5220 11:33:13.803014 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5221 11:33:13.806124 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5222 11:33:13.808817 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5223 11:33:13.812214 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5224 11:33:13.819129 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5225 11:33:13.822571 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5226 11:33:13.825359 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5227 11:33:13.828781 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5228 11:33:13.832369 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5229 11:33:13.835491 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5230 11:33:13.842103 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5231 11:33:13.845149 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5232 11:33:13.848512 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5233 11:33:13.848646 ==
5234 11:33:13.852008 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 11:33:13.855497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 11:33:13.858654 ==
5237 11:33:13.858728 DQS Delay:
5238 11:33:13.858788 DQS0 = 0, DQS1 = 0
5239 11:33:13.861793 DQM Delay:
5240 11:33:13.861888 DQM0 = 104, DQM1 = 94
5241 11:33:13.865085 DQ Delay:
5242 11:33:13.868611 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5243 11:33:13.871637 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5244 11:33:13.874922 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5245 11:33:13.878404 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5246 11:33:13.878496
5247 11:33:13.878574
5248 11:33:13.878638 ==
5249 11:33:13.881936 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 11:33:13.885151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 11:33:13.885227 ==
5252 11:33:13.885286
5253 11:33:13.885339
5254 11:33:13.888543 TX Vref Scan disable
5255 11:33:13.888619 == TX Byte 0 ==
5256 11:33:13.894929 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5257 11:33:13.898220 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5258 11:33:13.898292 == TX Byte 1 ==
5259 11:33:13.904941 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5260 11:33:13.908903 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5261 11:33:13.908990 ==
5262 11:33:13.911617 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 11:33:13.915105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 11:33:13.915180 ==
5265 11:33:13.915238
5266 11:33:13.917962
5267 11:33:13.918037 TX Vref Scan disable
5268 11:33:13.921417 == TX Byte 0 ==
5269 11:33:13.924964 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5270 11:33:13.928387 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5271 11:33:13.931256 == TX Byte 1 ==
5272 11:33:13.934792 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5273 11:33:13.941607 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5274 11:33:13.941710
5275 11:33:13.941804 [DATLAT]
5276 11:33:13.941892 Freq=933, CH0 RK0
5277 11:33:13.941988
5278 11:33:13.945077 DATLAT Default: 0xd
5279 11:33:13.945169 0, 0xFFFF, sum = 0
5280 11:33:13.948427 1, 0xFFFF, sum = 0
5281 11:33:13.948521 2, 0xFFFF, sum = 0
5282 11:33:13.951641 3, 0xFFFF, sum = 0
5283 11:33:13.951721 4, 0xFFFF, sum = 0
5284 11:33:13.954765 5, 0xFFFF, sum = 0
5285 11:33:13.958100 6, 0xFFFF, sum = 0
5286 11:33:13.958214 7, 0xFFFF, sum = 0
5287 11:33:13.961380 8, 0xFFFF, sum = 0
5288 11:33:13.961458 9, 0xFFFF, sum = 0
5289 11:33:13.964961 10, 0x0, sum = 1
5290 11:33:13.965061 11, 0x0, sum = 2
5291 11:33:13.965153 12, 0x0, sum = 3
5292 11:33:13.968384 13, 0x0, sum = 4
5293 11:33:13.968486 best_step = 11
5294 11:33:13.968572
5295 11:33:13.968660 ==
5296 11:33:13.971195 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:33:13.978179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:33:13.978265 ==
5299 11:33:13.978326 RX Vref Scan: 1
5300 11:33:13.978395
5301 11:33:13.981188 RX Vref 0 -> 0, step: 1
5302 11:33:13.981288
5303 11:33:13.984988 RX Delay -53 -> 252, step: 4
5304 11:33:13.985090
5305 11:33:13.988001 Set Vref, RX VrefLevel [Byte0]: 54
5306 11:33:13.991424 [Byte1]: 48
5307 11:33:13.991502
5308 11:33:13.994822 Final RX Vref Byte 0 = 54 to rank0
5309 11:33:13.998058 Final RX Vref Byte 1 = 48 to rank0
5310 11:33:14.001596 Final RX Vref Byte 0 = 54 to rank1
5311 11:33:14.005067 Final RX Vref Byte 1 = 48 to rank1==
5312 11:33:14.007942 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 11:33:14.011466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 11:33:14.011574 ==
5315 11:33:14.014926 DQS Delay:
5316 11:33:14.015029 DQS0 = 0, DQS1 = 0
5317 11:33:14.018189 DQM Delay:
5318 11:33:14.018266 DQM0 = 104, DQM1 = 94
5319 11:33:14.018348 DQ Delay:
5320 11:33:14.021646 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5321 11:33:14.024593 DQ4 =104, DQ5 =94, DQ6 =114, DQ7 =110
5322 11:33:14.028111 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =88
5323 11:33:14.034568 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5324 11:33:14.034665
5325 11:33:14.034754
5326 11:33:14.040969 [DQSOSCAuto] RK0, (LSB)MR18= 0x352d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
5327 11:33:14.044340 CH0 RK0: MR19=505, MR18=352D
5328 11:33:14.051471 CH0_RK0: MR19=0x505, MR18=0x352D, DQSOSC=405, MR23=63, INC=66, DEC=44
5329 11:33:14.051550
5330 11:33:14.054240 ----->DramcWriteLeveling(PI) begin...
5331 11:33:14.054343 ==
5332 11:33:14.057680 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 11:33:14.060989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 11:33:14.061089 ==
5335 11:33:14.064772 Write leveling (Byte 0): 32 => 32
5336 11:33:14.067741 Write leveling (Byte 1): 30 => 30
5337 11:33:14.071037 DramcWriteLeveling(PI) end<-----
5338 11:33:14.071110
5339 11:33:14.071169 ==
5340 11:33:14.074466 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 11:33:14.078088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 11:33:14.078164 ==
5343 11:33:14.080788 [Gating] SW mode calibration
5344 11:33:14.087483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5345 11:33:14.093980 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5346 11:33:14.097870 0 14 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
5347 11:33:14.104146 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 11:33:14.107438 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 11:33:14.110614 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 11:33:14.117848 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 11:33:14.120690 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 11:33:14.124142 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 11:33:14.127431 0 14 28 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
5354 11:33:14.134450 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
5355 11:33:14.137708 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 11:33:14.141200 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 11:33:14.147556 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 11:33:14.151233 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 11:33:14.153881 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:33:14.161031 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5361 11:33:14.163797 0 15 28 | B1->B0 | 3e3e 3737 | 0 0 | (0 0) (0 0)
5362 11:33:14.167281 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:33:14.174157 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:33:14.177390 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:33:14.180667 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 11:33:14.187515 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 11:33:14.190451 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 11:33:14.193991 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:33:14.200846 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5370 11:33:14.203828 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:33:14.207182 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:33:14.213816 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:33:14.216936 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:33:14.220656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:33:14.227365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:33:14.230832 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:33:14.233919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:33:14.240022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:33:14.244059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:33:14.246866 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:33:14.253646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:33:14.257179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:33:14.260079 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:33:14.263544 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5385 11:33:14.270783 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5386 11:33:14.273635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:33:14.277223 Total UI for P1: 0, mck2ui 16
5388 11:33:14.280124 best dqsien dly found for B0: ( 1, 2, 26)
5389 11:33:14.283737 Total UI for P1: 0, mck2ui 16
5390 11:33:14.286911 best dqsien dly found for B1: ( 1, 2, 28)
5391 11:33:14.290184 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5392 11:33:14.293822 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5393 11:33:14.293893
5394 11:33:14.296791 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5395 11:33:14.300161 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5396 11:33:14.303366 [Gating] SW calibration Done
5397 11:33:14.303437 ==
5398 11:33:14.306836 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 11:33:14.313791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 11:33:14.313862 ==
5401 11:33:14.313919 RX Vref Scan: 0
5402 11:33:14.314003
5403 11:33:14.317088 RX Vref 0 -> 0, step: 1
5404 11:33:14.317178
5405 11:33:14.320263 RX Delay -80 -> 252, step: 8
5406 11:33:14.323394 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5407 11:33:14.327014 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5408 11:33:14.330263 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5409 11:33:14.333457 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5410 11:33:14.340234 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5411 11:33:14.343561 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5412 11:33:14.346766 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5413 11:33:14.350205 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5414 11:33:14.353149 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5415 11:33:14.360157 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5416 11:33:14.363680 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5417 11:33:14.366710 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5418 11:33:14.370014 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5419 11:33:14.372770 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5420 11:33:14.376266 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5421 11:33:14.383189 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5422 11:33:14.383286 ==
5423 11:33:14.385939 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 11:33:14.389283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 11:33:14.389377 ==
5426 11:33:14.389467 DQS Delay:
5427 11:33:14.392902 DQS0 = 0, DQS1 = 0
5428 11:33:14.392998 DQM Delay:
5429 11:33:14.396421 DQM0 = 105, DQM1 = 94
5430 11:33:14.396518 DQ Delay:
5431 11:33:14.399638 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5432 11:33:14.402870 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5433 11:33:14.406385 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5434 11:33:14.409784 DQ12 =95, DQ13 =103, DQ14 =103, DQ15 =99
5435 11:33:14.409880
5436 11:33:14.409968
5437 11:33:14.410061 ==
5438 11:33:14.413016 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 11:33:14.419603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 11:33:14.419699 ==
5441 11:33:14.419788
5442 11:33:14.419873
5443 11:33:14.419956 TX Vref Scan disable
5444 11:33:14.423043 == TX Byte 0 ==
5445 11:33:14.426265 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5446 11:33:14.432851 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5447 11:33:14.432950 == TX Byte 1 ==
5448 11:33:14.436068 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5449 11:33:14.443179 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5450 11:33:14.443256 ==
5451 11:33:14.446597 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 11:33:14.449435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 11:33:14.449530 ==
5454 11:33:14.449618
5455 11:33:14.449705
5456 11:33:14.452904 TX Vref Scan disable
5457 11:33:14.453002 == TX Byte 0 ==
5458 11:33:14.459585 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5459 11:33:14.463019 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5460 11:33:14.463100 == TX Byte 1 ==
5461 11:33:14.469724 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5462 11:33:14.472886 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5463 11:33:14.472980
5464 11:33:14.473071 [DATLAT]
5465 11:33:14.475972 Freq=933, CH0 RK1
5466 11:33:14.476063
5467 11:33:14.476145 DATLAT Default: 0xb
5468 11:33:14.479852 0, 0xFFFF, sum = 0
5469 11:33:14.479955 1, 0xFFFF, sum = 0
5470 11:33:14.482843 2, 0xFFFF, sum = 0
5471 11:33:14.482938 3, 0xFFFF, sum = 0
5472 11:33:14.486302 4, 0xFFFF, sum = 0
5473 11:33:14.486403 5, 0xFFFF, sum = 0
5474 11:33:14.489766 6, 0xFFFF, sum = 0
5475 11:33:14.492601 7, 0xFFFF, sum = 0
5476 11:33:14.492694 8, 0xFFFF, sum = 0
5477 11:33:14.496178 9, 0xFFFF, sum = 0
5478 11:33:14.496271 10, 0x0, sum = 1
5479 11:33:14.496368 11, 0x0, sum = 2
5480 11:33:14.499803 12, 0x0, sum = 3
5481 11:33:14.499897 13, 0x0, sum = 4
5482 11:33:14.503060 best_step = 11
5483 11:33:14.503125
5484 11:33:14.503180 ==
5485 11:33:14.505862 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 11:33:14.509388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:33:14.509478 ==
5488 11:33:14.512786 RX Vref Scan: 0
5489 11:33:14.512880
5490 11:33:14.512969 RX Vref 0 -> 0, step: 1
5491 11:33:14.513051
5492 11:33:14.515895 RX Delay -53 -> 252, step: 4
5493 11:33:14.523446 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5494 11:33:14.526395 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5495 11:33:14.530383 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5496 11:33:14.533206 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5497 11:33:14.536676 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5498 11:33:14.543488 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5499 11:33:14.546686 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5500 11:33:14.549882 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5501 11:33:14.553847 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5502 11:33:14.557284 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5503 11:33:14.563389 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5504 11:33:14.566876 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5505 11:33:14.570281 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5506 11:33:14.573702 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5507 11:33:14.577114 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5508 11:33:14.583225 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5509 11:33:14.583326 ==
5510 11:33:14.586631 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 11:33:14.590224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 11:33:14.590293 ==
5513 11:33:14.590348 DQS Delay:
5514 11:33:14.593637 DQS0 = 0, DQS1 = 0
5515 11:33:14.593726 DQM Delay:
5516 11:33:14.596943 DQM0 = 104, DQM1 = 94
5517 11:33:14.597012 DQ Delay:
5518 11:33:14.599728 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5519 11:33:14.603338 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5520 11:33:14.606797 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5521 11:33:14.610277 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5522 11:33:14.610355
5523 11:33:14.610414
5524 11:33:14.619978 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5525 11:33:14.620056 CH0 RK1: MR19=505, MR18=2C04
5526 11:33:14.626284 CH0_RK1: MR19=0x505, MR18=0x2C04, DQSOSC=408, MR23=63, INC=65, DEC=43
5527 11:33:14.629959 [RxdqsGatingPostProcess] freq 933
5528 11:33:14.636300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5529 11:33:14.639628 best DQS0 dly(2T, 0.5T) = (0, 10)
5530 11:33:14.643004 best DQS1 dly(2T, 0.5T) = (0, 10)
5531 11:33:14.646722 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5532 11:33:14.649883 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5533 11:33:14.653009 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 11:33:14.656688 best DQS1 dly(2T, 0.5T) = (0, 10)
5535 11:33:14.659734 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 11:33:14.659835 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5537 11:33:14.663263 Pre-setting of DQS Precalculation
5538 11:33:14.670075 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5539 11:33:14.670180 ==
5540 11:33:14.672948 Dram Type= 6, Freq= 0, CH_1, rank 0
5541 11:33:14.676380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 11:33:14.676454 ==
5543 11:33:14.682665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 11:33:14.689683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 11:33:14.692995 [CA 0] Center 36 (6~67) winsize 62
5546 11:33:14.696506 [CA 1] Center 37 (6~68) winsize 63
5547 11:33:14.699436 [CA 2] Center 34 (4~65) winsize 62
5548 11:33:14.703146 [CA 3] Center 34 (4~65) winsize 62
5549 11:33:14.706266 [CA 4] Center 34 (4~65) winsize 62
5550 11:33:14.709742 [CA 5] Center 33 (3~64) winsize 62
5551 11:33:14.709841
5552 11:33:14.713409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 11:33:14.713513
5554 11:33:14.716191 [CATrainingPosCal] consider 1 rank data
5555 11:33:14.719617 u2DelayCellTimex100 = 270/100 ps
5556 11:33:14.723270 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 11:33:14.726778 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5558 11:33:14.729703 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 11:33:14.733273 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5560 11:33:14.736245 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 11:33:14.739658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 11:33:14.739749
5563 11:33:14.743197 CA PerBit enable=1, Macro0, CA PI delay=33
5564 11:33:14.746596
5565 11:33:14.746676 [CBTSetCACLKResult] CA Dly = 33
5566 11:33:14.749845 CS Dly: 6 (0~37)
5567 11:33:14.749933 ==
5568 11:33:14.752903 Dram Type= 6, Freq= 0, CH_1, rank 1
5569 11:33:14.756370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 11:33:14.756460 ==
5571 11:33:14.763189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5572 11:33:14.769393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5573 11:33:14.772987 [CA 0] Center 37 (6~68) winsize 63
5574 11:33:14.775972 [CA 1] Center 37 (6~68) winsize 63
5575 11:33:14.779512 [CA 2] Center 35 (4~66) winsize 63
5576 11:33:14.782546 [CA 3] Center 34 (4~65) winsize 62
5577 11:33:14.785931 [CA 4] Center 34 (4~65) winsize 62
5578 11:33:14.789583 [CA 5] Center 34 (4~64) winsize 61
5579 11:33:14.789685
5580 11:33:14.792730 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5581 11:33:14.792824
5582 11:33:14.796346 [CATrainingPosCal] consider 2 rank data
5583 11:33:14.799749 u2DelayCellTimex100 = 270/100 ps
5584 11:33:14.803107 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5585 11:33:14.805899 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5586 11:33:14.809507 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5587 11:33:14.812846 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5588 11:33:14.816175 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5589 11:33:14.819512 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5590 11:33:14.819605
5591 11:33:14.825792 CA PerBit enable=1, Macro0, CA PI delay=34
5592 11:33:14.825865
5593 11:33:14.825923 [CBTSetCACLKResult] CA Dly = 34
5594 11:33:14.829337 CS Dly: 7 (0~39)
5595 11:33:14.829413
5596 11:33:14.832925 ----->DramcWriteLeveling(PI) begin...
5597 11:33:14.833017 ==
5598 11:33:14.835796 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 11:33:14.839436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 11:33:14.839512 ==
5601 11:33:14.843015 Write leveling (Byte 0): 23 => 23
5602 11:33:14.845926 Write leveling (Byte 1): 27 => 27
5603 11:33:14.849332 DramcWriteLeveling(PI) end<-----
5604 11:33:14.849431
5605 11:33:14.849506 ==
5606 11:33:14.852890 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 11:33:14.855826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 11:33:14.859301 ==
5609 11:33:14.859381 [Gating] SW mode calibration
5610 11:33:14.865890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5611 11:33:14.872542 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5612 11:33:14.875707 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 11:33:14.882833 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 11:33:14.886212 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 11:33:14.889469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 11:33:14.896281 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 11:33:14.899359 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5618 11:33:14.902617 0 14 24 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
5619 11:33:14.909238 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5620 11:33:14.912849 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 11:33:14.916179 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 11:33:14.923002 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 11:33:14.926065 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 11:33:14.929363 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 11:33:14.932510 0 15 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5626 11:33:14.939345 0 15 24 | B1->B0 | 2c2c 3232 | 1 0 | (0 0) (0 0)
5627 11:33:14.942957 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5628 11:33:14.945869 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 11:33:14.953184 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 11:33:14.955842 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 11:33:14.959398 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:33:14.965929 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:33:14.969207 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:33:14.972921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5635 11:33:14.979256 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 11:33:14.982304 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 11:33:14.985747 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 11:33:14.992179 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 11:33:14.995374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:33:14.998855 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:33:15.005128 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:33:15.008840 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:33:15.012132 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:33:15.019044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:33:15.021739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:33:15.025703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:33:15.031754 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:33:15.035152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:33:15.038411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:33:15.045213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5651 11:33:15.048148 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5652 11:33:15.051820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:33:15.055298 Total UI for P1: 0, mck2ui 16
5654 11:33:15.058053 best dqsien dly found for B0: ( 1, 2, 28)
5655 11:33:15.061421 Total UI for P1: 0, mck2ui 16
5656 11:33:15.064920 best dqsien dly found for B1: ( 1, 2, 26)
5657 11:33:15.068337 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5658 11:33:15.071760 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5659 11:33:15.071840
5660 11:33:15.078500 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5661 11:33:15.081876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5662 11:33:15.081953 [Gating] SW calibration Done
5663 11:33:15.084760 ==
5664 11:33:15.088208 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 11:33:15.091418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 11:33:15.091485 ==
5667 11:33:15.091562 RX Vref Scan: 0
5668 11:33:15.091617
5669 11:33:15.094708 RX Vref 0 -> 0, step: 1
5670 11:33:15.094772
5671 11:33:15.098732 RX Delay -80 -> 252, step: 8
5672 11:33:15.101944 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5673 11:33:15.105103 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5674 11:33:15.108391 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5675 11:33:15.114639 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5676 11:33:15.118695 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5677 11:33:15.121272 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5678 11:33:15.124866 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5679 11:33:15.128361 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5680 11:33:15.131783 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5681 11:33:15.135303 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5682 11:33:15.141661 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5683 11:33:15.145088 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5684 11:33:15.148397 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5685 11:33:15.151645 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5686 11:33:15.155063 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5687 11:33:15.161441 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5688 11:33:15.161528 ==
5689 11:33:15.164589 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 11:33:15.168313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 11:33:15.168419 ==
5692 11:33:15.168507 DQS Delay:
5693 11:33:15.171734 DQS0 = 0, DQS1 = 0
5694 11:33:15.171807 DQM Delay:
5695 11:33:15.174566 DQM0 = 101, DQM1 = 97
5696 11:33:15.174637 DQ Delay:
5697 11:33:15.178164 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5698 11:33:15.181606 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5699 11:33:15.185012 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5700 11:33:15.187772 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5701 11:33:15.187841
5702 11:33:15.187897
5703 11:33:15.187954 ==
5704 11:33:15.191222 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 11:33:15.198335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 11:33:15.198409 ==
5707 11:33:15.198465
5708 11:33:15.198519
5709 11:33:15.198577 TX Vref Scan disable
5710 11:33:15.201644 == TX Byte 0 ==
5711 11:33:15.205212 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5712 11:33:15.211799 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5713 11:33:15.211871 == TX Byte 1 ==
5714 11:33:15.214745 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 11:33:15.221501 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 11:33:15.221593 ==
5717 11:33:15.224668 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 11:33:15.228058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 11:33:15.228130 ==
5720 11:33:15.228186
5721 11:33:15.228239
5722 11:33:15.231808 TX Vref Scan disable
5723 11:33:15.231880 == TX Byte 0 ==
5724 11:33:15.238032 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5725 11:33:15.241317 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5726 11:33:15.241392 == TX Byte 1 ==
5727 11:33:15.247755 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5728 11:33:15.251327 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5729 11:33:15.251401
5730 11:33:15.251460 [DATLAT]
5731 11:33:15.254501 Freq=933, CH1 RK0
5732 11:33:15.254578
5733 11:33:15.254634 DATLAT Default: 0xd
5734 11:33:15.257784 0, 0xFFFF, sum = 0
5735 11:33:15.257875 1, 0xFFFF, sum = 0
5736 11:33:15.261128 2, 0xFFFF, sum = 0
5737 11:33:15.261197 3, 0xFFFF, sum = 0
5738 11:33:15.264523 4, 0xFFFF, sum = 0
5739 11:33:15.268260 5, 0xFFFF, sum = 0
5740 11:33:15.268354 6, 0xFFFF, sum = 0
5741 11:33:15.271469 7, 0xFFFF, sum = 0
5742 11:33:15.271570 8, 0xFFFF, sum = 0
5743 11:33:15.274798 9, 0xFFFF, sum = 0
5744 11:33:15.274866 10, 0x0, sum = 1
5745 11:33:15.277968 11, 0x0, sum = 2
5746 11:33:15.278055 12, 0x0, sum = 3
5747 11:33:15.278113 13, 0x0, sum = 4
5748 11:33:15.281147 best_step = 11
5749 11:33:15.281233
5750 11:33:15.281324 ==
5751 11:33:15.284266 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 11:33:15.288024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 11:33:15.288101 ==
5754 11:33:15.291637 RX Vref Scan: 1
5755 11:33:15.291705
5756 11:33:15.291762 RX Vref 0 -> 0, step: 1
5757 11:33:15.294277
5758 11:33:15.294340 RX Delay -45 -> 252, step: 4
5759 11:33:15.294398
5760 11:33:15.297703 Set Vref, RX VrefLevel [Byte0]: 54
5761 11:33:15.301069 [Byte1]: 54
5762 11:33:15.305200
5763 11:33:15.305264 Final RX Vref Byte 0 = 54 to rank0
5764 11:33:15.308614 Final RX Vref Byte 1 = 54 to rank0
5765 11:33:15.311911 Final RX Vref Byte 0 = 54 to rank1
5766 11:33:15.315244 Final RX Vref Byte 1 = 54 to rank1==
5767 11:33:15.318733 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 11:33:15.325562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 11:33:15.325652 ==
5770 11:33:15.325733 DQS Delay:
5771 11:33:15.325816 DQS0 = 0, DQS1 = 0
5772 11:33:15.328729 DQM Delay:
5773 11:33:15.328790 DQM0 = 102, DQM1 = 99
5774 11:33:15.332383 DQ Delay:
5775 11:33:15.335246 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5776 11:33:15.338595 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5777 11:33:15.342430 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5778 11:33:15.345351 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =106
5779 11:33:15.345437
5780 11:33:15.345494
5781 11:33:15.352849 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5782 11:33:15.355392 CH1 RK0: MR19=505, MR18=1F37
5783 11:33:15.362131 CH1_RK0: MR19=0x505, MR18=0x1F37, DQSOSC=404, MR23=63, INC=66, DEC=44
5784 11:33:15.362233
5785 11:33:15.365235 ----->DramcWriteLeveling(PI) begin...
5786 11:33:15.365304 ==
5787 11:33:15.368741 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 11:33:15.372065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 11:33:15.372133 ==
5790 11:33:15.375143 Write leveling (Byte 0): 27 => 27
5791 11:33:15.378845 Write leveling (Byte 1): 27 => 27
5792 11:33:15.382012 DramcWriteLeveling(PI) end<-----
5793 11:33:15.382103
5794 11:33:15.382192 ==
5795 11:33:15.385285 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 11:33:15.388616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:33:15.391794 ==
5798 11:33:15.391858 [Gating] SW mode calibration
5799 11:33:15.402135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5800 11:33:15.404925 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5801 11:33:15.408293 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 11:33:15.415168 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 11:33:15.418373 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 11:33:15.421694 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 11:33:15.428250 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 11:33:15.431679 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 11:33:15.435077 0 14 24 | B1->B0 | 2c2c 3232 | 0 1 | (0 1) (1 0)
5808 11:33:15.441776 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5809 11:33:15.445081 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 11:33:15.448362 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 11:33:15.455325 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 11:33:15.458301 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 11:33:15.461424 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 11:33:15.468625 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 11:33:15.471624 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (1 1) (0 0)
5816 11:33:15.475018 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5817 11:33:15.481827 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 11:33:15.484923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 11:33:15.488400 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 11:33:15.494918 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 11:33:15.497960 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 11:33:15.501483 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:33:15.507787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5824 11:33:15.511575 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 11:33:15.514818 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 11:33:15.518340 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 11:33:15.524367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 11:33:15.527819 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:33:15.531282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:33:15.537976 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:33:15.541400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:33:15.544674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:33:15.551348 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:33:15.554576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:33:15.557997 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:33:15.564328 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:33:15.567879 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:33:15.571163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:33:15.577886 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:33:15.580792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5841 11:33:15.584069 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:33:15.587428 Total UI for P1: 0, mck2ui 16
5843 11:33:15.590844 best dqsien dly found for B0: ( 1, 2, 28)
5844 11:33:15.594667 Total UI for P1: 0, mck2ui 16
5845 11:33:15.597951 best dqsien dly found for B1: ( 1, 2, 28)
5846 11:33:15.601178 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5847 11:33:15.604271 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5848 11:33:15.604338
5849 11:33:15.611349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5850 11:33:15.614746 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5851 11:33:15.614815 [Gating] SW calibration Done
5852 11:33:15.618140 ==
5853 11:33:15.621202 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 11:33:15.624267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 11:33:15.624364 ==
5856 11:33:15.624448 RX Vref Scan: 0
5857 11:33:15.624533
5858 11:33:15.627830 RX Vref 0 -> 0, step: 1
5859 11:33:15.627918
5860 11:33:15.631245 RX Delay -80 -> 252, step: 8
5861 11:33:15.633977 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5862 11:33:15.637377 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5863 11:33:15.640922 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5864 11:33:15.647784 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5865 11:33:15.651331 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5866 11:33:15.654165 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5867 11:33:15.657382 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5868 11:33:15.661237 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5869 11:33:15.664493 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5870 11:33:15.667520 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5871 11:33:15.674085 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5872 11:33:15.677994 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5873 11:33:15.680859 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5874 11:33:15.684115 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5875 11:33:15.687418 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5876 11:33:15.694367 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5877 11:33:15.694443 ==
5878 11:33:15.698073 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 11:33:15.700695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 11:33:15.700775 ==
5881 11:33:15.700870 DQS Delay:
5882 11:33:15.704696 DQS0 = 0, DQS1 = 0
5883 11:33:15.704797 DQM Delay:
5884 11:33:15.707441 DQM0 = 101, DQM1 = 98
5885 11:33:15.707517 DQ Delay:
5886 11:33:15.710722 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5887 11:33:15.714021 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5888 11:33:15.717595 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5889 11:33:15.720815 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5890 11:33:15.720892
5891 11:33:15.720951
5892 11:33:15.721006 ==
5893 11:33:15.724130 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 11:33:15.727362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 11:33:15.731216 ==
5896 11:33:15.731297
5897 11:33:15.731387
5898 11:33:15.731474 TX Vref Scan disable
5899 11:33:15.734493 == TX Byte 0 ==
5900 11:33:15.737655 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5901 11:33:15.740496 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5902 11:33:15.743947 == TX Byte 1 ==
5903 11:33:15.747315 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5904 11:33:15.750797 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5905 11:33:15.754237 ==
5906 11:33:15.757154 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 11:33:15.761212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 11:33:15.761315 ==
5909 11:33:15.761401
5910 11:33:15.761484
5911 11:33:15.764434 TX Vref Scan disable
5912 11:33:15.764525 == TX Byte 0 ==
5913 11:33:15.770922 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5914 11:33:15.774409 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5915 11:33:15.774501 == TX Byte 1 ==
5916 11:33:15.780554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 11:33:15.783950 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 11:33:15.784047
5919 11:33:15.784133 [DATLAT]
5920 11:33:15.787228 Freq=933, CH1 RK1
5921 11:33:15.787294
5922 11:33:15.787349 DATLAT Default: 0xb
5923 11:33:15.790993 0, 0xFFFF, sum = 0
5924 11:33:15.791089 1, 0xFFFF, sum = 0
5925 11:33:15.794349 2, 0xFFFF, sum = 0
5926 11:33:15.794442 3, 0xFFFF, sum = 0
5927 11:33:15.797401 4, 0xFFFF, sum = 0
5928 11:33:15.797496 5, 0xFFFF, sum = 0
5929 11:33:15.800590 6, 0xFFFF, sum = 0
5930 11:33:15.800658 7, 0xFFFF, sum = 0
5931 11:33:15.803684 8, 0xFFFF, sum = 0
5932 11:33:15.803748 9, 0xFFFF, sum = 0
5933 11:33:15.807482 10, 0x0, sum = 1
5934 11:33:15.807558 11, 0x0, sum = 2
5935 11:33:15.810717 12, 0x0, sum = 3
5936 11:33:15.810796 13, 0x0, sum = 4
5937 11:33:15.814073 best_step = 11
5938 11:33:15.814169
5939 11:33:15.814251 ==
5940 11:33:15.817593 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:33:15.820291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:33:15.820381 ==
5943 11:33:15.823560 RX Vref Scan: 0
5944 11:33:15.823655
5945 11:33:15.823749 RX Vref 0 -> 0, step: 1
5946 11:33:15.823830
5947 11:33:15.827262 RX Delay -45 -> 252, step: 4
5948 11:33:15.834605 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5949 11:33:15.837312 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5950 11:33:15.840667 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5951 11:33:15.844921 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5952 11:33:15.847672 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5953 11:33:15.854131 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5954 11:33:15.857612 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5955 11:33:15.860963 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5956 11:33:15.863949 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5957 11:33:15.867247 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5958 11:33:15.870716 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5959 11:33:15.877717 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5960 11:33:15.881162 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5961 11:33:15.883831 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5962 11:33:15.887375 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5963 11:33:15.890800 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5964 11:33:15.894074 ==
5965 11:33:15.897320 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 11:33:15.900762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 11:33:15.900871 ==
5968 11:33:15.900961 DQS Delay:
5969 11:33:15.904030 DQS0 = 0, DQS1 = 0
5970 11:33:15.904133 DQM Delay:
5971 11:33:15.907261 DQM0 = 104, DQM1 = 99
5972 11:33:15.907365 DQ Delay:
5973 11:33:15.910480 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =98
5974 11:33:15.913794 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5975 11:33:15.917108 DQ8 =88, DQ9 =88, DQ10 =102, DQ11 =92
5976 11:33:15.920870 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5977 11:33:15.920942
5978 11:33:15.921015
5979 11:33:15.930367 [DQSOSCAuto] RK1, (LSB)MR18= 0x3104, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5980 11:33:15.930477 CH1 RK1: MR19=505, MR18=3104
5981 11:33:15.937183 CH1_RK1: MR19=0x505, MR18=0x3104, DQSOSC=406, MR23=63, INC=65, DEC=43
5982 11:33:15.940382 [RxdqsGatingPostProcess] freq 933
5983 11:33:15.947130 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5984 11:33:15.950404 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 11:33:15.953712 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 11:33:15.956871 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 11:33:15.960198 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 11:33:15.963477 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 11:33:15.963570 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 11:33:15.966963 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 11:33:15.970475 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 11:33:15.973959 Pre-setting of DQS Precalculation
5993 11:33:15.980406 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5994 11:33:15.987013 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5995 11:33:15.993198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5996 11:33:15.993270
5997 11:33:15.993356
5998 11:33:15.996623 [Calibration Summary] 1866 Mbps
5999 11:33:15.999978 CH 0, Rank 0
6000 11:33:16.000048 SW Impedance : PASS
6001 11:33:16.003971 DUTY Scan : NO K
6002 11:33:16.004065 ZQ Calibration : PASS
6003 11:33:16.007279 Jitter Meter : NO K
6004 11:33:16.010439 CBT Training : PASS
6005 11:33:16.010517 Write leveling : PASS
6006 11:33:16.013621 RX DQS gating : PASS
6007 11:33:16.016764 RX DQ/DQS(RDDQC) : PASS
6008 11:33:16.016883 TX DQ/DQS : PASS
6009 11:33:16.020177 RX DATLAT : PASS
6010 11:33:16.023491 RX DQ/DQS(Engine): PASS
6011 11:33:16.023570 TX OE : NO K
6012 11:33:16.026681 All Pass.
6013 11:33:16.026755
6014 11:33:16.026814 CH 0, Rank 1
6015 11:33:16.029985 SW Impedance : PASS
6016 11:33:16.030090 DUTY Scan : NO K
6017 11:33:16.033344 ZQ Calibration : PASS
6018 11:33:16.036574 Jitter Meter : NO K
6019 11:33:16.036686 CBT Training : PASS
6020 11:33:16.040038 Write leveling : PASS
6021 11:33:16.043314 RX DQS gating : PASS
6022 11:33:16.043383 RX DQ/DQS(RDDQC) : PASS
6023 11:33:16.046846 TX DQ/DQS : PASS
6024 11:33:16.046913 RX DATLAT : PASS
6025 11:33:16.050192 RX DQ/DQS(Engine): PASS
6026 11:33:16.053308 TX OE : NO K
6027 11:33:16.053374 All Pass.
6028 11:33:16.053434
6029 11:33:16.053488 CH 1, Rank 0
6030 11:33:16.056442 SW Impedance : PASS
6031 11:33:16.059973 DUTY Scan : NO K
6032 11:33:16.060035 ZQ Calibration : PASS
6033 11:33:16.063346 Jitter Meter : NO K
6034 11:33:16.066322 CBT Training : PASS
6035 11:33:16.066390 Write leveling : PASS
6036 11:33:16.070198 RX DQS gating : PASS
6037 11:33:16.073268 RX DQ/DQS(RDDQC) : PASS
6038 11:33:16.073328 TX DQ/DQS : PASS
6039 11:33:16.076742 RX DATLAT : PASS
6040 11:33:16.080079 RX DQ/DQS(Engine): PASS
6041 11:33:16.080140 TX OE : NO K
6042 11:33:16.082768 All Pass.
6043 11:33:16.082835
6044 11:33:16.082888 CH 1, Rank 1
6045 11:33:16.086449 SW Impedance : PASS
6046 11:33:16.086508 DUTY Scan : NO K
6047 11:33:16.089655 ZQ Calibration : PASS
6048 11:33:16.093077 Jitter Meter : NO K
6049 11:33:16.093135 CBT Training : PASS
6050 11:33:16.096514 Write leveling : PASS
6051 11:33:16.099828 RX DQS gating : PASS
6052 11:33:16.099928 RX DQ/DQS(RDDQC) : PASS
6053 11:33:16.103307 TX DQ/DQS : PASS
6054 11:33:16.103378 RX DATLAT : PASS
6055 11:33:16.106670 RX DQ/DQS(Engine): PASS
6056 11:33:16.109363 TX OE : NO K
6057 11:33:16.109448 All Pass.
6058 11:33:16.109505
6059 11:33:16.112730 DramC Write-DBI off
6060 11:33:16.116674 PER_BANK_REFRESH: Hybrid Mode
6061 11:33:16.116740 TX_TRACKING: ON
6062 11:33:16.126595 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6063 11:33:16.129976 [FAST_K] Save calibration result to emmc
6064 11:33:16.133419 dramc_set_vcore_voltage set vcore to 650000
6065 11:33:16.133525 Read voltage for 400, 6
6066 11:33:16.136623 Vio18 = 0
6067 11:33:16.136698 Vcore = 650000
6068 11:33:16.136786 Vdram = 0
6069 11:33:16.139818 Vddq = 0
6070 11:33:16.139890 Vmddr = 0
6071 11:33:16.143072 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6072 11:33:16.149827 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6073 11:33:16.153289 MEM_TYPE=3, freq_sel=20
6074 11:33:16.156081 sv_algorithm_assistance_LP4_800
6075 11:33:16.159634 ============ PULL DRAM RESETB DOWN ============
6076 11:33:16.163024 ========== PULL DRAM RESETB DOWN end =========
6077 11:33:16.169708 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6078 11:33:16.172907 ===================================
6079 11:33:16.173001 LPDDR4 DRAM CONFIGURATION
6080 11:33:16.176077 ===================================
6081 11:33:16.179446 EX_ROW_EN[0] = 0x0
6082 11:33:16.179518 EX_ROW_EN[1] = 0x0
6083 11:33:16.182992 LP4Y_EN = 0x0
6084 11:33:16.183061 WORK_FSP = 0x0
6085 11:33:16.186691 WL = 0x2
6086 11:33:16.186785 RL = 0x2
6087 11:33:16.189126 BL = 0x2
6088 11:33:16.193002 RPST = 0x0
6089 11:33:16.193094 RD_PRE = 0x0
6090 11:33:16.196263 WR_PRE = 0x1
6091 11:33:16.196362 WR_PST = 0x0
6092 11:33:16.199516 DBI_WR = 0x0
6093 11:33:16.199588 DBI_RD = 0x0
6094 11:33:16.202961 OTF = 0x1
6095 11:33:16.206309 ===================================
6096 11:33:16.209873 ===================================
6097 11:33:16.209967 ANA top config
6098 11:33:16.212581 ===================================
6099 11:33:16.216097 DLL_ASYNC_EN = 0
6100 11:33:16.219480 ALL_SLAVE_EN = 1
6101 11:33:16.219550 NEW_RANK_MODE = 1
6102 11:33:16.222840 DLL_IDLE_MODE = 1
6103 11:33:16.226355 LP45_APHY_COMB_EN = 1
6104 11:33:16.229637 TX_ODT_DIS = 1
6105 11:33:16.229724 NEW_8X_MODE = 1
6106 11:33:16.232857 ===================================
6107 11:33:16.236029 ===================================
6108 11:33:16.239267 data_rate = 800
6109 11:33:16.242768 CKR = 1
6110 11:33:16.245987 DQ_P2S_RATIO = 4
6111 11:33:16.249293 ===================================
6112 11:33:16.252796 CA_P2S_RATIO = 4
6113 11:33:16.255937 DQ_CA_OPEN = 0
6114 11:33:16.256035 DQ_SEMI_OPEN = 1
6115 11:33:16.259941 CA_SEMI_OPEN = 1
6116 11:33:16.262671 CA_FULL_RATE = 0
6117 11:33:16.266172 DQ_CKDIV4_EN = 0
6118 11:33:16.269642 CA_CKDIV4_EN = 1
6119 11:33:16.273060 CA_PREDIV_EN = 0
6120 11:33:16.273144 PH8_DLY = 0
6121 11:33:16.275764 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6122 11:33:16.279206 DQ_AAMCK_DIV = 0
6123 11:33:16.282645 CA_AAMCK_DIV = 0
6124 11:33:16.285983 CA_ADMCK_DIV = 4
6125 11:33:16.289295 DQ_TRACK_CA_EN = 0
6126 11:33:16.289395 CA_PICK = 800
6127 11:33:16.292772 CA_MCKIO = 400
6128 11:33:16.296399 MCKIO_SEMI = 400
6129 11:33:16.299588 PLL_FREQ = 3016
6130 11:33:16.302708 DQ_UI_PI_RATIO = 32
6131 11:33:16.306328 CA_UI_PI_RATIO = 32
6132 11:33:16.309179 ===================================
6133 11:33:16.312825 ===================================
6134 11:33:16.315841 memory_type:LPDDR4
6135 11:33:16.315936 GP_NUM : 10
6136 11:33:16.319388 SRAM_EN : 1
6137 11:33:16.319484 MD32_EN : 0
6138 11:33:16.322833 ===================================
6139 11:33:16.326164 [ANA_INIT] >>>>>>>>>>>>>>
6140 11:33:16.329562 <<<<<< [CONFIGURE PHASE]: ANA_TX
6141 11:33:16.332337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6142 11:33:16.335974 ===================================
6143 11:33:16.339286 data_rate = 800,PCW = 0X7400
6144 11:33:16.342401 ===================================
6145 11:33:16.346085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6146 11:33:16.349234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 11:33:16.362407 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 11:33:16.365784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6149 11:33:16.368942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6150 11:33:16.372255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6151 11:33:16.375810 [ANA_INIT] flow start
6152 11:33:16.379188 [ANA_INIT] PLL >>>>>>>>
6153 11:33:16.379284 [ANA_INIT] PLL <<<<<<<<
6154 11:33:16.382653 [ANA_INIT] MIDPI >>>>>>>>
6155 11:33:16.385509 [ANA_INIT] MIDPI <<<<<<<<
6156 11:33:16.385605 [ANA_INIT] DLL >>>>>>>>
6157 11:33:16.388852 [ANA_INIT] flow end
6158 11:33:16.392293 ============ LP4 DIFF to SE enter ============
6159 11:33:16.395692 ============ LP4 DIFF to SE exit ============
6160 11:33:16.399158 [ANA_INIT] <<<<<<<<<<<<<
6161 11:33:16.402486 [Flow] Enable top DCM control >>>>>
6162 11:33:16.405801 [Flow] Enable top DCM control <<<<<
6163 11:33:16.408784 Enable DLL master slave shuffle
6164 11:33:16.415473 ==============================================================
6165 11:33:16.415557 Gating Mode config
6166 11:33:16.422630 ==============================================================
6167 11:33:16.422702 Config description:
6168 11:33:16.432565 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6169 11:33:16.438919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6170 11:33:16.446023 SELPH_MODE 0: By rank 1: By Phase
6171 11:33:16.448673 ==============================================================
6172 11:33:16.452567 GAT_TRACK_EN = 0
6173 11:33:16.455712 RX_GATING_MODE = 2
6174 11:33:16.458719 RX_GATING_TRACK_MODE = 2
6175 11:33:16.462961 SELPH_MODE = 1
6176 11:33:16.465732 PICG_EARLY_EN = 1
6177 11:33:16.469245 VALID_LAT_VALUE = 1
6178 11:33:16.475417 ==============================================================
6179 11:33:16.478672 Enter into Gating configuration >>>>
6180 11:33:16.482054 Exit from Gating configuration <<<<
6181 11:33:16.482160 Enter into DVFS_PRE_config >>>>>
6182 11:33:16.495926 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6183 11:33:16.499129 Exit from DVFS_PRE_config <<<<<
6184 11:33:16.502467 Enter into PICG configuration >>>>
6185 11:33:16.505071 Exit from PICG configuration <<<<
6186 11:33:16.508641 [RX_INPUT] configuration >>>>>
6187 11:33:16.508725 [RX_INPUT] configuration <<<<<
6188 11:33:16.515413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6189 11:33:16.522451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6190 11:33:16.525859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 11:33:16.531997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 11:33:16.538596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 11:33:16.545464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 11:33:16.548563 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6195 11:33:16.552184 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6196 11:33:16.558824 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6197 11:33:16.561884 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6198 11:33:16.564908 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6199 11:33:16.568844 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 11:33:16.572068 ===================================
6201 11:33:16.575367 LPDDR4 DRAM CONFIGURATION
6202 11:33:16.578486 ===================================
6203 11:33:16.582031 EX_ROW_EN[0] = 0x0
6204 11:33:16.582127 EX_ROW_EN[1] = 0x0
6205 11:33:16.585217 LP4Y_EN = 0x0
6206 11:33:16.585309 WORK_FSP = 0x0
6207 11:33:16.588309 WL = 0x2
6208 11:33:16.588405 RL = 0x2
6209 11:33:16.592023 BL = 0x2
6210 11:33:16.592093 RPST = 0x0
6211 11:33:16.595378 RD_PRE = 0x0
6212 11:33:16.595470 WR_PRE = 0x1
6213 11:33:16.598800 WR_PST = 0x0
6214 11:33:16.598874 DBI_WR = 0x0
6215 11:33:16.602263 DBI_RD = 0x0
6216 11:33:16.604950 OTF = 0x1
6217 11:33:16.608309 ===================================
6218 11:33:16.611761 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6219 11:33:16.615094 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6220 11:33:16.618437 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 11:33:16.621679 ===================================
6222 11:33:16.624922 LPDDR4 DRAM CONFIGURATION
6223 11:33:16.628275 ===================================
6224 11:33:16.631559 EX_ROW_EN[0] = 0x10
6225 11:33:16.631626 EX_ROW_EN[1] = 0x0
6226 11:33:16.634977 LP4Y_EN = 0x0
6227 11:33:16.635049 WORK_FSP = 0x0
6228 11:33:16.638297 WL = 0x2
6229 11:33:16.638359 RL = 0x2
6230 11:33:16.641570 BL = 0x2
6231 11:33:16.641636 RPST = 0x0
6232 11:33:16.644817 RD_PRE = 0x0
6233 11:33:16.644881 WR_PRE = 0x1
6234 11:33:16.648865 WR_PST = 0x0
6235 11:33:16.648925 DBI_WR = 0x0
6236 11:33:16.651559 DBI_RD = 0x0
6237 11:33:16.651618 OTF = 0x1
6238 11:33:16.654827 ===================================
6239 11:33:16.661637 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6240 11:33:16.666680 nWR fixed to 30
6241 11:33:16.669662 [ModeRegInit_LP4] CH0 RK0
6242 11:33:16.669727 [ModeRegInit_LP4] CH0 RK1
6243 11:33:16.673085 [ModeRegInit_LP4] CH1 RK0
6244 11:33:16.676360 [ModeRegInit_LP4] CH1 RK1
6245 11:33:16.676433 match AC timing 19
6246 11:33:16.683380 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6247 11:33:16.686714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6248 11:33:16.690020 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6249 11:33:16.696456 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6250 11:33:16.699453 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6251 11:33:16.699518 ==
6252 11:33:16.703164 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 11:33:16.706393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 11:33:16.706463 ==
6255 11:33:16.713320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 11:33:16.720041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6257 11:33:16.722834 [CA 0] Center 36 (8~64) winsize 57
6258 11:33:16.726119 [CA 1] Center 36 (8~64) winsize 57
6259 11:33:16.729391 [CA 2] Center 36 (8~64) winsize 57
6260 11:33:16.729451 [CA 3] Center 36 (8~64) winsize 57
6261 11:33:16.733316 [CA 4] Center 36 (8~64) winsize 57
6262 11:33:16.736022 [CA 5] Center 36 (8~64) winsize 57
6263 11:33:16.736095
6264 11:33:16.739368 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6265 11:33:16.742642
6266 11:33:16.746058 [CATrainingPosCal] consider 1 rank data
6267 11:33:16.746137 u2DelayCellTimex100 = 270/100 ps
6268 11:33:16.753234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:33:16.756558 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 11:33:16.759772 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:33:16.762947 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:33:16.766920 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:33:16.770192 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:33:16.770259
6275 11:33:16.772903 CA PerBit enable=1, Macro0, CA PI delay=36
6276 11:33:16.772973
6277 11:33:16.776276 [CBTSetCACLKResult] CA Dly = 36
6278 11:33:16.779598 CS Dly: 1 (0~32)
6279 11:33:16.779663 ==
6280 11:33:16.782760 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 11:33:16.786417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 11:33:16.786490 ==
6283 11:33:16.792932 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 11:33:16.796335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 11:33:16.799656 [CA 0] Center 36 (8~64) winsize 57
6286 11:33:16.803102 [CA 1] Center 36 (8~64) winsize 57
6287 11:33:16.806514 [CA 2] Center 36 (8~64) winsize 57
6288 11:33:16.809855 [CA 3] Center 36 (8~64) winsize 57
6289 11:33:16.812859 [CA 4] Center 36 (8~64) winsize 57
6290 11:33:16.816247 [CA 5] Center 36 (8~64) winsize 57
6291 11:33:16.816321
6292 11:33:16.819381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 11:33:16.819448
6294 11:33:16.822591 [CATrainingPosCal] consider 2 rank data
6295 11:33:16.826358 u2DelayCellTimex100 = 270/100 ps
6296 11:33:16.829693 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:33:16.833214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:33:16.836421 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:33:16.839685 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:33:16.846411 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:33:16.849253 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:33:16.849326
6303 11:33:16.853088 CA PerBit enable=1, Macro0, CA PI delay=36
6304 11:33:16.853161
6305 11:33:16.856373 [CBTSetCACLKResult] CA Dly = 36
6306 11:33:16.856441 CS Dly: 1 (0~32)
6307 11:33:16.856496
6308 11:33:16.859858 ----->DramcWriteLeveling(PI) begin...
6309 11:33:16.859924 ==
6310 11:33:16.862595 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 11:33:16.869513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 11:33:16.869581 ==
6313 11:33:16.872846 Write leveling (Byte 0): 40 => 8
6314 11:33:16.872910 Write leveling (Byte 1): 40 => 8
6315 11:33:16.876073 DramcWriteLeveling(PI) end<-----
6316 11:33:16.876138
6317 11:33:16.879629 ==
6318 11:33:16.879692 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:33:16.885763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:33:16.885836 ==
6321 11:33:16.889119 [Gating] SW mode calibration
6322 11:33:16.895883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6323 11:33:16.899173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6324 11:33:16.905669 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 11:33:16.909275 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 11:33:16.912652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 11:33:16.919269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 11:33:16.923012 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 11:33:16.926147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 11:33:16.932422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 11:33:16.936034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 11:33:16.939147 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 11:33:16.942203 Total UI for P1: 0, mck2ui 16
6334 11:33:16.945960 best dqsien dly found for B0: ( 0, 14, 24)
6335 11:33:16.949418 Total UI for P1: 0, mck2ui 16
6336 11:33:16.952850 best dqsien dly found for B1: ( 0, 14, 24)
6337 11:33:16.956108 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6338 11:33:16.958874 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6339 11:33:16.958964
6340 11:33:16.962303 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 11:33:16.969141 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 11:33:16.969238 [Gating] SW calibration Done
6343 11:33:16.969330 ==
6344 11:33:16.972361 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 11:33:16.978865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 11:33:16.978942 ==
6347 11:33:16.979000 RX Vref Scan: 0
6348 11:33:16.979055
6349 11:33:16.982317 RX Vref 0 -> 0, step: 1
6350 11:33:16.982393
6351 11:33:16.985636 RX Delay -410 -> 252, step: 16
6352 11:33:16.989048 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6353 11:33:16.992349 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6354 11:33:16.999232 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6355 11:33:17.001883 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6356 11:33:17.005860 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6357 11:33:17.009148 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6358 11:33:17.015183 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6359 11:33:17.018583 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6360 11:33:17.022031 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6361 11:33:17.025174 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6362 11:33:17.032119 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6363 11:33:17.035613 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6364 11:33:17.038698 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6365 11:33:17.041904 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6366 11:33:17.048604 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6367 11:33:17.051940 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6368 11:33:17.052026 ==
6369 11:33:17.055297 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 11:33:17.058530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 11:33:17.058636 ==
6372 11:33:17.061644 DQS Delay:
6373 11:33:17.061757 DQS0 = 27, DQS1 = 35
6374 11:33:17.065157 DQM Delay:
6375 11:33:17.065230 DQM0 = 10, DQM1 = 11
6376 11:33:17.065291 DQ Delay:
6377 11:33:17.068635 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6378 11:33:17.071599 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6379 11:33:17.075386 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6380 11:33:17.078601 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6381 11:33:17.078674
6382 11:33:17.078757
6383 11:33:17.078814 ==
6384 11:33:17.081996 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 11:33:17.088842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 11:33:17.088953 ==
6387 11:33:17.089040
6388 11:33:17.089120
6389 11:33:17.089216 TX Vref Scan disable
6390 11:33:17.091688 == TX Byte 0 ==
6391 11:33:17.095052 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 11:33:17.098511 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 11:33:17.101820 == TX Byte 1 ==
6394 11:33:17.105292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 11:33:17.108546 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 11:33:17.108622 ==
6397 11:33:17.112046 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 11:33:17.118552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 11:33:17.118620 ==
6400 11:33:17.118679
6401 11:33:17.118740
6402 11:33:17.118791 TX Vref Scan disable
6403 11:33:17.121819 == TX Byte 0 ==
6404 11:33:17.125259 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 11:33:17.128605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 11:33:17.131899 == TX Byte 1 ==
6407 11:33:17.135430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 11:33:17.138033 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 11:33:17.138130
6410 11:33:17.141428 [DATLAT]
6411 11:33:17.141494 Freq=400, CH0 RK0
6412 11:33:17.141549
6413 11:33:17.145137 DATLAT Default: 0xf
6414 11:33:17.145206 0, 0xFFFF, sum = 0
6415 11:33:17.148240 1, 0xFFFF, sum = 0
6416 11:33:17.148311 2, 0xFFFF, sum = 0
6417 11:33:17.151452 3, 0xFFFF, sum = 0
6418 11:33:17.151529 4, 0xFFFF, sum = 0
6419 11:33:17.155177 5, 0xFFFF, sum = 0
6420 11:33:17.155253 6, 0xFFFF, sum = 0
6421 11:33:17.158170 7, 0xFFFF, sum = 0
6422 11:33:17.158247 8, 0xFFFF, sum = 0
6423 11:33:17.161497 9, 0xFFFF, sum = 0
6424 11:33:17.161574 10, 0xFFFF, sum = 0
6425 11:33:17.164801 11, 0xFFFF, sum = 0
6426 11:33:17.168168 12, 0xFFFF, sum = 0
6427 11:33:17.168244 13, 0x0, sum = 1
6428 11:33:17.171411 14, 0x0, sum = 2
6429 11:33:17.171488 15, 0x0, sum = 3
6430 11:33:17.171546 16, 0x0, sum = 4
6431 11:33:17.174832 best_step = 14
6432 11:33:17.174906
6433 11:33:17.174963 ==
6434 11:33:17.178174 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 11:33:17.181515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 11:33:17.181590 ==
6437 11:33:17.184813 RX Vref Scan: 1
6438 11:33:17.184907
6439 11:33:17.184990 RX Vref 0 -> 0, step: 1
6440 11:33:17.185087
6441 11:33:17.188223 RX Delay -311 -> 252, step: 8
6442 11:33:17.188302
6443 11:33:17.191982 Set Vref, RX VrefLevel [Byte0]: 54
6444 11:33:17.194900 [Byte1]: 48
6445 11:33:17.199902
6446 11:33:17.199990 Final RX Vref Byte 0 = 54 to rank0
6447 11:33:17.202896 Final RX Vref Byte 1 = 48 to rank0
6448 11:33:17.206501 Final RX Vref Byte 0 = 54 to rank1
6449 11:33:17.209715 Final RX Vref Byte 1 = 48 to rank1==
6450 11:33:17.213216 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 11:33:17.220005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 11:33:17.220079 ==
6453 11:33:17.220135 DQS Delay:
6454 11:33:17.220187 DQS0 = 28, DQS1 = 36
6455 11:33:17.223334 DQM Delay:
6456 11:33:17.223410 DQM0 = 10, DQM1 = 13
6457 11:33:17.226635 DQ Delay:
6458 11:33:17.226723 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6459 11:33:17.230107 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6460 11:33:17.233271 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6461 11:33:17.236070 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6462 11:33:17.236143
6463 11:33:17.236215
6464 11:33:17.246212 [DQSOSCAuto] RK0, (LSB)MR18= 0xdac7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 382 ps
6465 11:33:17.249751 CH0 RK0: MR19=C0C, MR18=DAC7
6466 11:33:17.256311 CH0_RK0: MR19=0xC0C, MR18=0xDAC7, DQSOSC=382, MR23=63, INC=404, DEC=269
6467 11:33:17.256401 ==
6468 11:33:17.259508 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 11:33:17.262886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 11:33:17.262975 ==
6471 11:33:17.266401 [Gating] SW mode calibration
6472 11:33:17.273083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 11:33:17.276559 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6474 11:33:17.282700 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 11:33:17.286024 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 11:33:17.289394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 11:33:17.296004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 11:33:17.299341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 11:33:17.302795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 11:33:17.309326 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 11:33:17.312639 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 11:33:17.316129 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 11:33:17.319540 Total UI for P1: 0, mck2ui 16
6484 11:33:17.322625 best dqsien dly found for B0: ( 0, 14, 24)
6485 11:33:17.326250 Total UI for P1: 0, mck2ui 16
6486 11:33:17.329220 best dqsien dly found for B1: ( 0, 14, 24)
6487 11:33:17.332777 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6488 11:33:17.336099 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6489 11:33:17.336171
6490 11:33:17.342998 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 11:33:17.345987 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 11:33:17.349915 [Gating] SW calibration Done
6493 11:33:17.349987 ==
6494 11:33:17.353104 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 11:33:17.355845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 11:33:17.355911 ==
6497 11:33:17.355967 RX Vref Scan: 0
6498 11:33:17.356019
6499 11:33:17.359863 RX Vref 0 -> 0, step: 1
6500 11:33:17.359955
6501 11:33:17.363008 RX Delay -410 -> 252, step: 16
6502 11:33:17.366412 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6503 11:33:17.372462 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6504 11:33:17.376385 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6505 11:33:17.379399 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6506 11:33:17.382855 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6507 11:33:17.386367 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6508 11:33:17.392392 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6509 11:33:17.395706 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6510 11:33:17.399075 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6511 11:33:17.402431 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6512 11:33:17.409262 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6513 11:33:17.412661 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6514 11:33:17.416179 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6515 11:33:17.422234 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6516 11:33:17.425495 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6517 11:33:17.428755 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6518 11:33:17.428826 ==
6519 11:33:17.431983 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 11:33:17.435268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 11:33:17.438608 ==
6522 11:33:17.438674 DQS Delay:
6523 11:33:17.438765 DQS0 = 27, DQS1 = 35
6524 11:33:17.442363 DQM Delay:
6525 11:33:17.442459 DQM0 = 17, DQM1 = 16
6526 11:33:17.445323 DQ Delay:
6527 11:33:17.445398 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6528 11:33:17.449029 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6529 11:33:17.452086 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6530 11:33:17.455557 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6531 11:33:17.455619
6532 11:33:17.455679
6533 11:33:17.458997 ==
6534 11:33:17.459065 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 11:33:17.465457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 11:33:17.465528 ==
6537 11:33:17.465584
6538 11:33:17.465636
6539 11:33:17.468928 TX Vref Scan disable
6540 11:33:17.469000 == TX Byte 0 ==
6541 11:33:17.472086 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6542 11:33:17.475357 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6543 11:33:17.478816 == TX Byte 1 ==
6544 11:33:17.482219 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 11:33:17.485760 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 11:33:17.489170 ==
6547 11:33:17.492322 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 11:33:17.495440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 11:33:17.495512 ==
6550 11:33:17.495568
6551 11:33:17.495620
6552 11:33:17.499109 TX Vref Scan disable
6553 11:33:17.499182 == TX Byte 0 ==
6554 11:33:17.501986 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6555 11:33:17.508876 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6556 11:33:17.508972 == TX Byte 1 ==
6557 11:33:17.512263 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6558 11:33:17.515620 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6559 11:33:17.519059
6560 11:33:17.519129 [DATLAT]
6561 11:33:17.519185 Freq=400, CH0 RK1
6562 11:33:17.519238
6563 11:33:17.522413 DATLAT Default: 0xe
6564 11:33:17.522506 0, 0xFFFF, sum = 0
6565 11:33:17.525247 1, 0xFFFF, sum = 0
6566 11:33:17.525337 2, 0xFFFF, sum = 0
6567 11:33:17.528587 3, 0xFFFF, sum = 0
6568 11:33:17.528689 4, 0xFFFF, sum = 0
6569 11:33:17.532008 5, 0xFFFF, sum = 0
6570 11:33:17.532075 6, 0xFFFF, sum = 0
6571 11:33:17.535297 7, 0xFFFF, sum = 0
6572 11:33:17.538674 8, 0xFFFF, sum = 0
6573 11:33:17.538774 9, 0xFFFF, sum = 0
6574 11:33:17.542088 10, 0xFFFF, sum = 0
6575 11:33:17.542165 11, 0xFFFF, sum = 0
6576 11:33:17.545433 12, 0xFFFF, sum = 0
6577 11:33:17.545503 13, 0x0, sum = 1
6578 11:33:17.548657 14, 0x0, sum = 2
6579 11:33:17.548728 15, 0x0, sum = 3
6580 11:33:17.551832 16, 0x0, sum = 4
6581 11:33:17.551933 best_step = 14
6582 11:33:17.552018
6583 11:33:17.552098 ==
6584 11:33:17.555619 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 11:33:17.559143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:33:17.559213 ==
6587 11:33:17.562293 RX Vref Scan: 0
6588 11:33:17.562391
6589 11:33:17.565567 RX Vref 0 -> 0, step: 1
6590 11:33:17.565657
6591 11:33:17.565748 RX Delay -311 -> 252, step: 8
6592 11:33:17.574052 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6593 11:33:17.577364 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6594 11:33:17.580805 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6595 11:33:17.584111 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6596 11:33:17.590459 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6597 11:33:17.593908 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6598 11:33:17.597355 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6599 11:33:17.600801 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6600 11:33:17.607334 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6601 11:33:17.610581 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6602 11:33:17.614392 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6603 11:33:17.617556 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6604 11:33:17.624009 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6605 11:33:17.627342 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6606 11:33:17.630711 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6607 11:33:17.634016 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6608 11:33:17.637457 ==
6609 11:33:17.640917 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 11:33:17.644126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 11:33:17.644197 ==
6612 11:33:17.644261 DQS Delay:
6613 11:33:17.647523 DQS0 = 24, DQS1 = 32
6614 11:33:17.647584 DQM Delay:
6615 11:33:17.650327 DQM0 = 8, DQM1 = 10
6616 11:33:17.650388 DQ Delay:
6617 11:33:17.653789 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6618 11:33:17.657085 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6619 11:33:17.660703 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6620 11:33:17.664015 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6621 11:33:17.664083
6622 11:33:17.664139
6623 11:33:17.670716 [DQSOSCAuto] RK1, (LSB)MR18= 0xc665, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6624 11:33:17.674021 CH0 RK1: MR19=C0C, MR18=C665
6625 11:33:17.680262 CH0_RK1: MR19=0xC0C, MR18=0xC665, DQSOSC=385, MR23=63, INC=398, DEC=265
6626 11:33:17.683685 [RxdqsGatingPostProcess] freq 400
6627 11:33:17.687053 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6628 11:33:17.690360 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 11:33:17.693705 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 11:33:17.696905 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 11:33:17.700663 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 11:33:17.703836 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 11:33:17.707285 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 11:33:17.710212 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 11:33:17.713777 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 11:33:17.717426 Pre-setting of DQS Precalculation
6637 11:33:17.720513 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6638 11:33:17.720580 ==
6639 11:33:17.723671 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 11:33:17.730292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 11:33:17.730365 ==
6642 11:33:17.733831 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 11:33:17.740185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6644 11:33:17.743576 [CA 0] Center 36 (8~64) winsize 57
6645 11:33:17.746879 [CA 1] Center 36 (8~64) winsize 57
6646 11:33:17.750274 [CA 2] Center 36 (8~64) winsize 57
6647 11:33:17.753626 [CA 3] Center 36 (8~64) winsize 57
6648 11:33:17.756932 [CA 4] Center 36 (8~64) winsize 57
6649 11:33:17.760239 [CA 5] Center 36 (8~64) winsize 57
6650 11:33:17.760301
6651 11:33:17.763695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6652 11:33:17.763759
6653 11:33:17.766944 [CATrainingPosCal] consider 1 rank data
6654 11:33:17.770555 u2DelayCellTimex100 = 270/100 ps
6655 11:33:17.773496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:33:17.777132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 11:33:17.780598 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:33:17.783839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:33:17.787211 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:33:17.790567 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:33:17.790635
6662 11:33:17.797360 CA PerBit enable=1, Macro0, CA PI delay=36
6663 11:33:17.797436
6664 11:33:17.797493 [CBTSetCACLKResult] CA Dly = 36
6665 11:33:17.800687 CS Dly: 1 (0~32)
6666 11:33:17.800753 ==
6667 11:33:17.803391 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 11:33:17.806715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 11:33:17.806780 ==
6670 11:33:17.813491 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 11:33:17.820479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6672 11:33:17.823567 [CA 0] Center 36 (8~64) winsize 57
6673 11:33:17.826637 [CA 1] Center 36 (8~64) winsize 57
6674 11:33:17.830394 [CA 2] Center 36 (8~64) winsize 57
6675 11:33:17.833234 [CA 3] Center 36 (8~64) winsize 57
6676 11:33:17.833337 [CA 4] Center 36 (8~64) winsize 57
6677 11:33:17.837157 [CA 5] Center 36 (8~64) winsize 57
6678 11:33:17.837235
6679 11:33:17.843644 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6680 11:33:17.843744
6681 11:33:17.846690 [CATrainingPosCal] consider 2 rank data
6682 11:33:17.850310 u2DelayCellTimex100 = 270/100 ps
6683 11:33:17.853178 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:33:17.856716 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:33:17.859978 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:33:17.863729 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:33:17.867012 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:33:17.870340 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:33:17.870448
6690 11:33:17.873654 CA PerBit enable=1, Macro0, CA PI delay=36
6691 11:33:17.873760
6692 11:33:17.876890 [CBTSetCACLKResult] CA Dly = 36
6693 11:33:17.880041 CS Dly: 1 (0~32)
6694 11:33:17.880135
6695 11:33:17.883672 ----->DramcWriteLeveling(PI) begin...
6696 11:33:17.883741 ==
6697 11:33:17.886786 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 11:33:17.889839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 11:33:17.889937 ==
6700 11:33:17.893274 Write leveling (Byte 0): 40 => 8
6701 11:33:17.896609 Write leveling (Byte 1): 40 => 8
6702 11:33:17.900046 DramcWriteLeveling(PI) end<-----
6703 11:33:17.900139
6704 11:33:17.900235 ==
6705 11:33:17.903344 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:33:17.906785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:33:17.906857 ==
6708 11:33:17.910165 [Gating] SW mode calibration
6709 11:33:17.916943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6710 11:33:17.923700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6711 11:33:17.927168 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 11:33:17.929827 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 11:33:17.936863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 11:33:17.939648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 11:33:17.943158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 11:33:17.950089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 11:33:17.952891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 11:33:17.956243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 11:33:17.962906 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 11:33:17.963009 Total UI for P1: 0, mck2ui 16
6721 11:33:17.969672 best dqsien dly found for B0: ( 0, 14, 24)
6722 11:33:17.969741 Total UI for P1: 0, mck2ui 16
6723 11:33:17.976448 best dqsien dly found for B1: ( 0, 14, 24)
6724 11:33:17.979361 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6725 11:33:17.982928 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6726 11:33:17.983027
6727 11:33:17.986149 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 11:33:17.989457 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 11:33:17.992832 [Gating] SW calibration Done
6730 11:33:17.992902 ==
6731 11:33:17.995967 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 11:33:17.999822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 11:33:17.999897 ==
6734 11:33:18.002925 RX Vref Scan: 0
6735 11:33:18.002993
6736 11:33:18.003049 RX Vref 0 -> 0, step: 1
6737 11:33:18.003107
6738 11:33:18.006169 RX Delay -410 -> 252, step: 16
6739 11:33:18.013041 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6740 11:33:18.016389 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6741 11:33:18.019905 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6742 11:33:18.022598 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6743 11:33:18.029375 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6744 11:33:18.032801 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6745 11:33:18.035640 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6746 11:33:18.038981 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6747 11:33:18.045831 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6748 11:33:18.049175 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6749 11:33:18.052545 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6750 11:33:18.055885 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6751 11:33:18.062836 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6752 11:33:18.065790 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6753 11:33:18.068796 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6754 11:33:18.072389 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6755 11:33:18.075851 ==
6756 11:33:18.079554 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 11:33:18.082646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 11:33:18.082744 ==
6759 11:33:18.082916 DQS Delay:
6760 11:33:18.085769 DQS0 = 35, DQS1 = 35
6761 11:33:18.085864 DQM Delay:
6762 11:33:18.088870 DQM0 = 17, DQM1 = 12
6763 11:33:18.088951 DQ Delay:
6764 11:33:18.092621 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6765 11:33:18.095476 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6766 11:33:18.098785 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6767 11:33:18.102615 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6768 11:33:18.102693
6769 11:33:18.102752
6770 11:33:18.102806 ==
6771 11:33:18.105815 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 11:33:18.108938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 11:33:18.109058 ==
6774 11:33:18.109134
6775 11:33:18.109192
6776 11:33:18.112623 TX Vref Scan disable
6777 11:33:18.112706 == TX Byte 0 ==
6778 11:33:18.119387 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 11:33:18.121975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 11:33:18.122062 == TX Byte 1 ==
6781 11:33:18.128658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 11:33:18.132019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 11:33:18.132083 ==
6784 11:33:18.135465 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 11:33:18.138800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 11:33:18.138886 ==
6787 11:33:18.138947
6788 11:33:18.139002
6789 11:33:18.142213 TX Vref Scan disable
6790 11:33:18.142283 == TX Byte 0 ==
6791 11:33:18.148982 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 11:33:18.152076 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 11:33:18.152145 == TX Byte 1 ==
6794 11:33:18.159225 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 11:33:18.161957 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 11:33:18.162050
6797 11:33:18.162114 [DATLAT]
6798 11:33:18.165344 Freq=400, CH1 RK0
6799 11:33:18.165418
6800 11:33:18.165475 DATLAT Default: 0xf
6801 11:33:18.168736 0, 0xFFFF, sum = 0
6802 11:33:18.168802 1, 0xFFFF, sum = 0
6803 11:33:18.171991 2, 0xFFFF, sum = 0
6804 11:33:18.172055 3, 0xFFFF, sum = 0
6805 11:33:18.175266 4, 0xFFFF, sum = 0
6806 11:33:18.175332 5, 0xFFFF, sum = 0
6807 11:33:18.178602 6, 0xFFFF, sum = 0
6808 11:33:18.178670 7, 0xFFFF, sum = 0
6809 11:33:18.181895 8, 0xFFFF, sum = 0
6810 11:33:18.181965 9, 0xFFFF, sum = 0
6811 11:33:18.185770 10, 0xFFFF, sum = 0
6812 11:33:18.188747 11, 0xFFFF, sum = 0
6813 11:33:18.188818 12, 0xFFFF, sum = 0
6814 11:33:18.192365 13, 0x0, sum = 1
6815 11:33:18.192436 14, 0x0, sum = 2
6816 11:33:18.192492 15, 0x0, sum = 3
6817 11:33:18.195209 16, 0x0, sum = 4
6818 11:33:18.195278 best_step = 14
6819 11:33:18.195330
6820 11:33:18.198644 ==
6821 11:33:18.198721 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 11:33:18.205140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 11:33:18.205216 ==
6824 11:33:18.205274 RX Vref Scan: 1
6825 11:33:18.205328
6826 11:33:18.208419 RX Vref 0 -> 0, step: 1
6827 11:33:18.208510
6828 11:33:18.212051 RX Delay -311 -> 252, step: 8
6829 11:33:18.212124
6830 11:33:18.215631 Set Vref, RX VrefLevel [Byte0]: 54
6831 11:33:18.218599 [Byte1]: 54
6832 11:33:18.222069
6833 11:33:18.222138 Final RX Vref Byte 0 = 54 to rank0
6834 11:33:18.225101 Final RX Vref Byte 1 = 54 to rank0
6835 11:33:18.228795 Final RX Vref Byte 0 = 54 to rank1
6836 11:33:18.231794 Final RX Vref Byte 1 = 54 to rank1==
6837 11:33:18.235210 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 11:33:18.242144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 11:33:18.242218 ==
6840 11:33:18.242277 DQS Delay:
6841 11:33:18.245636 DQS0 = 32, DQS1 = 32
6842 11:33:18.245707 DQM Delay:
6843 11:33:18.245764 DQM0 = 13, DQM1 = 9
6844 11:33:18.248394 DQ Delay:
6845 11:33:18.251739 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6846 11:33:18.251807 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6847 11:33:18.255006 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6848 11:33:18.258920 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6849 11:33:18.258987
6850 11:33:18.262210
6851 11:33:18.268586 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ed6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6852 11:33:18.271907 CH1 RK0: MR19=C0C, MR18=9ED6
6853 11:33:18.278499 CH1_RK0: MR19=0xC0C, MR18=0x9ED6, DQSOSC=383, MR23=63, INC=402, DEC=268
6854 11:33:18.278575 ==
6855 11:33:18.281858 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 11:33:18.285271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 11:33:18.285343 ==
6858 11:33:18.288588 [Gating] SW mode calibration
6859 11:33:18.295184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6860 11:33:18.298582 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6861 11:33:18.304895 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 11:33:18.308454 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 11:33:18.311443 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 11:33:18.318564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 11:33:18.321848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 11:33:18.325254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 11:33:18.331705 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 11:33:18.334788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 11:33:18.338719 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 11:33:18.341548 Total UI for P1: 0, mck2ui 16
6871 11:33:18.344890 best dqsien dly found for B0: ( 0, 14, 24)
6872 11:33:18.348421 Total UI for P1: 0, mck2ui 16
6873 11:33:18.351719 best dqsien dly found for B1: ( 0, 14, 24)
6874 11:33:18.355318 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6875 11:33:18.358787 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6876 11:33:18.358852
6877 11:33:18.364900 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 11:33:18.368265 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 11:33:18.371336 [Gating] SW calibration Done
6880 11:33:18.371411 ==
6881 11:33:18.375133 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 11:33:18.377846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 11:33:18.377979 ==
6884 11:33:18.378062 RX Vref Scan: 0
6885 11:33:18.381731
6886 11:33:18.381845 RX Vref 0 -> 0, step: 1
6887 11:33:18.381945
6888 11:33:18.384999 RX Delay -410 -> 252, step: 16
6889 11:33:18.388353 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6890 11:33:18.394375 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6891 11:33:18.397704 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6892 11:33:18.401092 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6893 11:33:18.404497 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6894 11:33:18.411263 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6895 11:33:18.414575 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6896 11:33:18.417840 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6897 11:33:18.421016 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6898 11:33:18.427843 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6899 11:33:18.430951 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6900 11:33:18.434089 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6901 11:33:18.437478 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6902 11:33:18.444241 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6903 11:33:18.447616 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6904 11:33:18.450834 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6905 11:33:18.450897 ==
6906 11:33:18.454440 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 11:33:18.457953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 11:33:18.460932 ==
6909 11:33:18.460996 DQS Delay:
6910 11:33:18.461058 DQS0 = 35, DQS1 = 35
6911 11:33:18.464370 DQM Delay:
6912 11:33:18.464432 DQM0 = 18, DQM1 = 14
6913 11:33:18.467820 DQ Delay:
6914 11:33:18.471051 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6915 11:33:18.474605 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6916 11:33:18.474676 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6917 11:33:18.477279 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6918 11:33:18.480702
6919 11:33:18.480789
6920 11:33:18.480884 ==
6921 11:33:18.484345 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 11:33:18.487598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 11:33:18.487668 ==
6924 11:33:18.487724
6925 11:33:18.487776
6926 11:33:18.490938 TX Vref Scan disable
6927 11:33:18.491007 == TX Byte 0 ==
6928 11:33:18.494264 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 11:33:18.500529 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 11:33:18.500598 == TX Byte 1 ==
6931 11:33:18.503984 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 11:33:18.510594 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 11:33:18.510662 ==
6934 11:33:18.513665 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 11:33:18.517085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 11:33:18.517149 ==
6937 11:33:18.517204
6938 11:33:18.517262
6939 11:33:18.520484 TX Vref Scan disable
6940 11:33:18.520578 == TX Byte 0 ==
6941 11:33:18.523788 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 11:33:18.530381 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 11:33:18.530458 == TX Byte 1 ==
6944 11:33:18.533893 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6945 11:33:18.540770 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6946 11:33:18.540876
6947 11:33:18.540972 [DATLAT]
6948 11:33:18.541055 Freq=400, CH1 RK1
6949 11:33:18.543914
6950 11:33:18.543982 DATLAT Default: 0xe
6951 11:33:18.547361 0, 0xFFFF, sum = 0
6952 11:33:18.547430 1, 0xFFFF, sum = 0
6953 11:33:18.550652 2, 0xFFFF, sum = 0
6954 11:33:18.550720 3, 0xFFFF, sum = 0
6955 11:33:18.553787 4, 0xFFFF, sum = 0
6956 11:33:18.553852 5, 0xFFFF, sum = 0
6957 11:33:18.557227 6, 0xFFFF, sum = 0
6958 11:33:18.557293 7, 0xFFFF, sum = 0
6959 11:33:18.560545 8, 0xFFFF, sum = 0
6960 11:33:18.560649 9, 0xFFFF, sum = 0
6961 11:33:18.563837 10, 0xFFFF, sum = 0
6962 11:33:18.563911 11, 0xFFFF, sum = 0
6963 11:33:18.567239 12, 0xFFFF, sum = 0
6964 11:33:18.567340 13, 0x0, sum = 1
6965 11:33:18.570610 14, 0x0, sum = 2
6966 11:33:18.570674 15, 0x0, sum = 3
6967 11:33:18.574169 16, 0x0, sum = 4
6968 11:33:18.574242 best_step = 14
6969 11:33:18.574301
6970 11:33:18.574353 ==
6971 11:33:18.577274 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 11:33:18.583720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 11:33:18.583787 ==
6974 11:33:18.583845 RX Vref Scan: 0
6975 11:33:18.583903
6976 11:33:18.587224 RX Vref 0 -> 0, step: 1
6977 11:33:18.587289
6978 11:33:18.590667 RX Delay -311 -> 252, step: 8
6979 11:33:18.596951 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6980 11:33:18.600388 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6981 11:33:18.603758 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6982 11:33:18.606763 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6983 11:33:18.614090 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6984 11:33:18.616587 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6985 11:33:18.619917 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6986 11:33:18.623886 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6987 11:33:18.627110 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6988 11:33:18.633274 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6989 11:33:18.636929 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6990 11:33:18.640310 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6991 11:33:18.646740 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6992 11:33:18.649979 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6993 11:33:18.653291 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6994 11:33:18.656548 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6995 11:33:18.656645 ==
6996 11:33:18.659853 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 11:33:18.666618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 11:33:18.666740 ==
6999 11:33:18.666848 DQS Delay:
7000 11:33:18.669941 DQS0 = 32, DQS1 = 32
7001 11:33:18.670063 DQM Delay:
7002 11:33:18.673449 DQM0 = 14, DQM1 = 11
7003 11:33:18.673538 DQ Delay:
7004 11:33:18.676729 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7005 11:33:18.680185 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =16
7006 11:33:18.683541 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7007 11:33:18.686145 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7008 11:33:18.686225
7009 11:33:18.686304
7010 11:33:18.692953 [DQSOSCAuto] RK1, (LSB)MR18= 0xd060, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 384 ps
7011 11:33:18.696925 CH1 RK1: MR19=C0C, MR18=D060
7012 11:33:18.703005 CH1_RK1: MR19=0xC0C, MR18=0xD060, DQSOSC=384, MR23=63, INC=400, DEC=267
7013 11:33:18.706667 [RxdqsGatingPostProcess] freq 400
7014 11:33:18.709711 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7015 11:33:18.712952 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 11:33:18.716163 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 11:33:18.719949 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 11:33:18.723296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 11:33:18.726791 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 11:33:18.729954 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 11:33:18.733245 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 11:33:18.736291 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 11:33:18.739939 Pre-setting of DQS Precalculation
7024 11:33:18.742846 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7025 11:33:18.753016 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7026 11:33:18.759492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7027 11:33:18.759629
7028 11:33:18.759734
7029 11:33:18.762747 [Calibration Summary] 800 Mbps
7030 11:33:18.762838 CH 0, Rank 0
7031 11:33:18.766174 SW Impedance : PASS
7032 11:33:18.766275 DUTY Scan : NO K
7033 11:33:18.769378 ZQ Calibration : PASS
7034 11:33:18.772936 Jitter Meter : NO K
7035 11:33:18.773001 CBT Training : PASS
7036 11:33:18.776263 Write leveling : PASS
7037 11:33:18.779653 RX DQS gating : PASS
7038 11:33:18.779754 RX DQ/DQS(RDDQC) : PASS
7039 11:33:18.783065 TX DQ/DQS : PASS
7040 11:33:18.783130 RX DATLAT : PASS
7041 11:33:18.786349 RX DQ/DQS(Engine): PASS
7042 11:33:18.789661 TX OE : NO K
7043 11:33:18.789747 All Pass.
7044 11:33:18.789826
7045 11:33:18.789919 CH 0, Rank 1
7046 11:33:18.793165 SW Impedance : PASS
7047 11:33:18.796402 DUTY Scan : NO K
7048 11:33:18.796489 ZQ Calibration : PASS
7049 11:33:18.799933 Jitter Meter : NO K
7050 11:33:18.802610 CBT Training : PASS
7051 11:33:18.802698 Write leveling : NO K
7052 11:33:18.805828 RX DQS gating : PASS
7053 11:33:18.809288 RX DQ/DQS(RDDQC) : PASS
7054 11:33:18.809376 TX DQ/DQS : PASS
7055 11:33:18.812582 RX DATLAT : PASS
7056 11:33:18.816421 RX DQ/DQS(Engine): PASS
7057 11:33:18.816486 TX OE : NO K
7058 11:33:18.819615 All Pass.
7059 11:33:18.819699
7060 11:33:18.819758 CH 1, Rank 0
7061 11:33:18.822778 SW Impedance : PASS
7062 11:33:18.822870 DUTY Scan : NO K
7063 11:33:18.826118 ZQ Calibration : PASS
7064 11:33:18.829429 Jitter Meter : NO K
7065 11:33:18.829510 CBT Training : PASS
7066 11:33:18.832814 Write leveling : PASS
7067 11:33:18.832905 RX DQS gating : PASS
7068 11:33:18.836199 RX DQ/DQS(RDDQC) : PASS
7069 11:33:18.839459 TX DQ/DQS : PASS
7070 11:33:18.839526 RX DATLAT : PASS
7071 11:33:18.842723 RX DQ/DQS(Engine): PASS
7072 11:33:18.846302 TX OE : NO K
7073 11:33:18.846396 All Pass.
7074 11:33:18.846476
7075 11:33:18.846565 CH 1, Rank 1
7076 11:33:18.849190 SW Impedance : PASS
7077 11:33:18.852858 DUTY Scan : NO K
7078 11:33:18.852958 ZQ Calibration : PASS
7079 11:33:18.856191 Jitter Meter : NO K
7080 11:33:18.859593 CBT Training : PASS
7081 11:33:18.859680 Write leveling : NO K
7082 11:33:18.862898 RX DQS gating : PASS
7083 11:33:18.866243 RX DQ/DQS(RDDQC) : PASS
7084 11:33:18.866358 TX DQ/DQS : PASS
7085 11:33:18.869397 RX DATLAT : PASS
7086 11:33:18.872853 RX DQ/DQS(Engine): PASS
7087 11:33:18.872941 TX OE : NO K
7088 11:33:18.873028 All Pass.
7089 11:33:18.876273
7090 11:33:18.876399 DramC Write-DBI off
7091 11:33:18.879071 PER_BANK_REFRESH: Hybrid Mode
7092 11:33:18.879166 TX_TRACKING: ON
7093 11:33:18.889624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7094 11:33:18.893071 [FAST_K] Save calibration result to emmc
7095 11:33:18.896408 dramc_set_vcore_voltage set vcore to 725000
7096 11:33:18.899118 Read voltage for 1600, 0
7097 11:33:18.899230 Vio18 = 0
7098 11:33:18.902575 Vcore = 725000
7099 11:33:18.902638 Vdram = 0
7100 11:33:18.902704 Vddq = 0
7101 11:33:18.902756 Vmddr = 0
7102 11:33:18.909313 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7103 11:33:18.916213 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7104 11:33:18.916298 MEM_TYPE=3, freq_sel=13
7105 11:33:18.919666 sv_algorithm_assistance_LP4_3733
7106 11:33:18.922354 ============ PULL DRAM RESETB DOWN ============
7107 11:33:18.928830 ========== PULL DRAM RESETB DOWN end =========
7108 11:33:18.932435 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7109 11:33:18.935464 ===================================
7110 11:33:18.939234 LPDDR4 DRAM CONFIGURATION
7111 11:33:18.942645 ===================================
7112 11:33:18.942717 EX_ROW_EN[0] = 0x0
7113 11:33:18.945869 EX_ROW_EN[1] = 0x0
7114 11:33:18.945970 LP4Y_EN = 0x0
7115 11:33:18.949335 WORK_FSP = 0x1
7116 11:33:18.952077 WL = 0x5
7117 11:33:18.952144 RL = 0x5
7118 11:33:18.955390 BL = 0x2
7119 11:33:18.955460 RPST = 0x0
7120 11:33:18.958696 RD_PRE = 0x0
7121 11:33:18.958790 WR_PRE = 0x1
7122 11:33:18.961925 WR_PST = 0x1
7123 11:33:18.962045 DBI_WR = 0x0
7124 11:33:18.965194 DBI_RD = 0x0
7125 11:33:18.965291 OTF = 0x1
7126 11:33:18.968637 ===================================
7127 11:33:18.971863 ===================================
7128 11:33:18.975561 ANA top config
7129 11:33:18.978866 ===================================
7130 11:33:18.978954 DLL_ASYNC_EN = 0
7131 11:33:18.981953 ALL_SLAVE_EN = 0
7132 11:33:18.985099 NEW_RANK_MODE = 1
7133 11:33:18.988321 DLL_IDLE_MODE = 1
7134 11:33:18.988389 LP45_APHY_COMB_EN = 1
7135 11:33:18.992102 TX_ODT_DIS = 0
7136 11:33:18.995012 NEW_8X_MODE = 1
7137 11:33:18.998499 ===================================
7138 11:33:19.001826 ===================================
7139 11:33:19.005292 data_rate = 3200
7140 11:33:19.008260 CKR = 1
7141 11:33:19.012210 DQ_P2S_RATIO = 8
7142 11:33:19.015034 ===================================
7143 11:33:19.015103 CA_P2S_RATIO = 8
7144 11:33:19.018455 DQ_CA_OPEN = 0
7145 11:33:19.021949 DQ_SEMI_OPEN = 0
7146 11:33:19.025350 CA_SEMI_OPEN = 0
7147 11:33:19.028794 CA_FULL_RATE = 0
7148 11:33:19.032104 DQ_CKDIV4_EN = 0
7149 11:33:19.032168 CA_CKDIV4_EN = 0
7150 11:33:19.035449 CA_PREDIV_EN = 0
7151 11:33:19.038611 PH8_DLY = 12
7152 11:33:19.041780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7153 11:33:19.044996 DQ_AAMCK_DIV = 4
7154 11:33:19.048803 CA_AAMCK_DIV = 4
7155 11:33:19.048872 CA_ADMCK_DIV = 4
7156 11:33:19.051913 DQ_TRACK_CA_EN = 0
7157 11:33:19.055226 CA_PICK = 1600
7158 11:33:19.058538 CA_MCKIO = 1600
7159 11:33:19.061652 MCKIO_SEMI = 0
7160 11:33:19.064982 PLL_FREQ = 3068
7161 11:33:19.068834 DQ_UI_PI_RATIO = 32
7162 11:33:19.068898 CA_UI_PI_RATIO = 0
7163 11:33:19.072010 ===================================
7164 11:33:19.075590 ===================================
7165 11:33:19.078870 memory_type:LPDDR4
7166 11:33:19.082014 GP_NUM : 10
7167 11:33:19.082081 SRAM_EN : 1
7168 11:33:19.085476 MD32_EN : 0
7169 11:33:19.088731 ===================================
7170 11:33:19.092015 [ANA_INIT] >>>>>>>>>>>>>>
7171 11:33:19.095325 <<<<<< [CONFIGURE PHASE]: ANA_TX
7172 11:33:19.098778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7173 11:33:19.102237 ===================================
7174 11:33:19.102305 data_rate = 3200,PCW = 0X7600
7175 11:33:19.105304 ===================================
7176 11:33:19.108419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7177 11:33:19.115232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 11:33:19.121911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 11:33:19.124848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7180 11:33:19.128142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7181 11:33:19.131597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7182 11:33:19.134877 [ANA_INIT] flow start
7183 11:33:19.134989 [ANA_INIT] PLL >>>>>>>>
7184 11:33:19.138332 [ANA_INIT] PLL <<<<<<<<
7185 11:33:19.141633 [ANA_INIT] MIDPI >>>>>>>>
7186 11:33:19.144967 [ANA_INIT] MIDPI <<<<<<<<
7187 11:33:19.145064 [ANA_INIT] DLL >>>>>>>>
7188 11:33:19.148278 [ANA_INIT] DLL <<<<<<<<
7189 11:33:19.151811 [ANA_INIT] flow end
7190 11:33:19.155109 ============ LP4 DIFF to SE enter ============
7191 11:33:19.158057 ============ LP4 DIFF to SE exit ============
7192 11:33:19.161461 [ANA_INIT] <<<<<<<<<<<<<
7193 11:33:19.165108 [Flow] Enable top DCM control >>>>>
7194 11:33:19.168487 [Flow] Enable top DCM control <<<<<
7195 11:33:19.171827 Enable DLL master slave shuffle
7196 11:33:19.174962 ==============================================================
7197 11:33:19.178239 Gating Mode config
7198 11:33:19.181583 ==============================================================
7199 11:33:19.184774 Config description:
7200 11:33:19.194778 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7201 11:33:19.201749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7202 11:33:19.204870 SELPH_MODE 0: By rank 1: By Phase
7203 11:33:19.211656 ==============================================================
7204 11:33:19.214822 GAT_TRACK_EN = 1
7205 11:33:19.218329 RX_GATING_MODE = 2
7206 11:33:19.221551 RX_GATING_TRACK_MODE = 2
7207 11:33:19.224698 SELPH_MODE = 1
7208 11:33:19.227870 PICG_EARLY_EN = 1
7209 11:33:19.227946 VALID_LAT_VALUE = 1
7210 11:33:19.234874 ==============================================================
7211 11:33:19.237890 Enter into Gating configuration >>>>
7212 11:33:19.241582 Exit from Gating configuration <<<<
7213 11:33:19.244977 Enter into DVFS_PRE_config >>>>>
7214 11:33:19.254368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7215 11:33:19.257693 Exit from DVFS_PRE_config <<<<<
7216 11:33:19.261041 Enter into PICG configuration >>>>
7217 11:33:19.264215 Exit from PICG configuration <<<<
7218 11:33:19.267612 [RX_INPUT] configuration >>>>>
7219 11:33:19.271221 [RX_INPUT] configuration <<<<<
7220 11:33:19.274407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7221 11:33:19.280930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7222 11:33:19.287600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 11:33:19.294565 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 11:33:19.301396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 11:33:19.307963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 11:33:19.311320 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7227 11:33:19.314474 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7228 11:33:19.317788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7229 11:33:19.321151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7230 11:33:19.327781 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7231 11:33:19.331010 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 11:33:19.334352 ===================================
7233 11:33:19.337657 LPDDR4 DRAM CONFIGURATION
7234 11:33:19.340924 ===================================
7235 11:33:19.341001 EX_ROW_EN[0] = 0x0
7236 11:33:19.344287 EX_ROW_EN[1] = 0x0
7237 11:33:19.344363 LP4Y_EN = 0x0
7238 11:33:19.347600 WORK_FSP = 0x1
7239 11:33:19.347677 WL = 0x5
7240 11:33:19.350928 RL = 0x5
7241 11:33:19.351004 BL = 0x2
7242 11:33:19.354494 RPST = 0x0
7243 11:33:19.354570 RD_PRE = 0x0
7244 11:33:19.357832 WR_PRE = 0x1
7245 11:33:19.357918 WR_PST = 0x1
7246 11:33:19.360893 DBI_WR = 0x0
7247 11:33:19.364341 DBI_RD = 0x0
7248 11:33:19.364408 OTF = 0x1
7249 11:33:19.367695 ===================================
7250 11:33:19.371027 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7251 11:33:19.374355 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7252 11:33:19.380834 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 11:33:19.384694 ===================================
7254 11:33:19.387233 LPDDR4 DRAM CONFIGURATION
7255 11:33:19.390889 ===================================
7256 11:33:19.390964 EX_ROW_EN[0] = 0x10
7257 11:33:19.394269 EX_ROW_EN[1] = 0x0
7258 11:33:19.394335 LP4Y_EN = 0x0
7259 11:33:19.397647 WORK_FSP = 0x1
7260 11:33:19.397712 WL = 0x5
7261 11:33:19.400834 RL = 0x5
7262 11:33:19.400904 BL = 0x2
7263 11:33:19.404269 RPST = 0x0
7264 11:33:19.404350 RD_PRE = 0x0
7265 11:33:19.407672 WR_PRE = 0x1
7266 11:33:19.407743 WR_PST = 0x1
7267 11:33:19.411126 DBI_WR = 0x0
7268 11:33:19.411222 DBI_RD = 0x0
7269 11:33:19.414305 OTF = 0x1
7270 11:33:19.417614 ===================================
7271 11:33:19.424052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7272 11:33:19.424155 ==
7273 11:33:19.427417 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 11:33:19.430767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 11:33:19.430843 ==
7276 11:33:19.433991 [Duty_Offset_Calibration]
7277 11:33:19.434100 B0:2 B1:1 CA:1
7278 11:33:19.434191
7279 11:33:19.437351 [DutyScan_Calibration_Flow] k_type=0
7280 11:33:19.448769
7281 11:33:19.448846 ==CLK 0==
7282 11:33:19.452186 Final CLK duty delay cell = 0
7283 11:33:19.455485 [0] MAX Duty = 5187%(X100), DQS PI = 24
7284 11:33:19.458778 [0] MIN Duty = 4876%(X100), DQS PI = 48
7285 11:33:19.458849 [0] AVG Duty = 5031%(X100)
7286 11:33:19.461956
7287 11:33:19.465046 CH0 CLK Duty spec in!! Max-Min= 311%
7288 11:33:19.468589 [DutyScan_Calibration_Flow] ====Done====
7289 11:33:19.468656
7290 11:33:19.471943 [DutyScan_Calibration_Flow] k_type=1
7291 11:33:19.487913
7292 11:33:19.487986 ==DQS 0 ==
7293 11:33:19.491010 Final DQS duty delay cell = -4
7294 11:33:19.494060 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7295 11:33:19.497703 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7296 11:33:19.501086 [-4] AVG Duty = 4891%(X100)
7297 11:33:19.501157
7298 11:33:19.501220 ==DQS 1 ==
7299 11:33:19.504293 Final DQS duty delay cell = 0
7300 11:33:19.507463 [0] MAX Duty = 5187%(X100), DQS PI = 4
7301 11:33:19.510848 [0] MIN Duty = 5031%(X100), DQS PI = 30
7302 11:33:19.514330 [0] AVG Duty = 5109%(X100)
7303 11:33:19.514400
7304 11:33:19.517747 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7305 11:33:19.517814
7306 11:33:19.521302 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7307 11:33:19.524390 [DutyScan_Calibration_Flow] ====Done====
7308 11:33:19.524467
7309 11:33:19.527624 [DutyScan_Calibration_Flow] k_type=3
7310 11:33:19.545177
7311 11:33:19.545273 ==DQM 0 ==
7312 11:33:19.548392 Final DQM duty delay cell = 0
7313 11:33:19.551849 [0] MAX Duty = 5187%(X100), DQS PI = 26
7314 11:33:19.555137 [0] MIN Duty = 4844%(X100), DQS PI = 60
7315 11:33:19.555202 [0] AVG Duty = 5015%(X100)
7316 11:33:19.558544
7317 11:33:19.558608 ==DQM 1 ==
7318 11:33:19.561986 Final DQM duty delay cell = 0
7319 11:33:19.565260 [0] MAX Duty = 5187%(X100), DQS PI = 2
7320 11:33:19.568771 [0] MIN Duty = 5031%(X100), DQS PI = 48
7321 11:33:19.568837 [0] AVG Duty = 5109%(X100)
7322 11:33:19.568891
7323 11:33:19.575441 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7324 11:33:19.575517
7325 11:33:19.578742 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7326 11:33:19.581782 [DutyScan_Calibration_Flow] ====Done====
7327 11:33:19.581860
7328 11:33:19.584888 [DutyScan_Calibration_Flow] k_type=2
7329 11:33:19.601953
7330 11:33:19.602056 ==DQ 0 ==
7331 11:33:19.605641 Final DQ duty delay cell = 0
7332 11:33:19.609063 [0] MAX Duty = 5062%(X100), DQS PI = 26
7333 11:33:19.611905 [0] MIN Duty = 4907%(X100), DQS PI = 0
7334 11:33:19.611979 [0] AVG Duty = 4984%(X100)
7335 11:33:19.615499
7336 11:33:19.615569 ==DQ 1 ==
7337 11:33:19.618770 Final DQ duty delay cell = 0
7338 11:33:19.621916 [0] MAX Duty = 5093%(X100), DQS PI = 20
7339 11:33:19.625189 [0] MIN Duty = 4907%(X100), DQS PI = 32
7340 11:33:19.625269 [0] AVG Duty = 5000%(X100)
7341 11:33:19.625332
7342 11:33:19.628521 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7343 11:33:19.632075
7344 11:33:19.635175 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7345 11:33:19.639012 [DutyScan_Calibration_Flow] ====Done====
7346 11:33:19.639083 ==
7347 11:33:19.642096 Dram Type= 6, Freq= 0, CH_1, rank 0
7348 11:33:19.645498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7349 11:33:19.645570 ==
7350 11:33:19.648822 [Duty_Offset_Calibration]
7351 11:33:19.648893 B0:1 B1:0 CA:0
7352 11:33:19.648957
7353 11:33:19.651980 [DutyScan_Calibration_Flow] k_type=0
7354 11:33:19.661486
7355 11:33:19.661557 ==CLK 0==
7356 11:33:19.664779 Final CLK duty delay cell = -4
7357 11:33:19.668215 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7358 11:33:19.671559 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7359 11:33:19.674879 [-4] AVG Duty = 4922%(X100)
7360 11:33:19.674947
7361 11:33:19.678260 CH1 CLK Duty spec in!! Max-Min= 156%
7362 11:33:19.681762 [DutyScan_Calibration_Flow] ====Done====
7363 11:33:19.681823
7364 11:33:19.684485 [DutyScan_Calibration_Flow] k_type=1
7365 11:33:19.701433
7366 11:33:19.701510 ==DQS 0 ==
7367 11:33:19.705290 Final DQS duty delay cell = 0
7368 11:33:19.708109 [0] MAX Duty = 5062%(X100), DQS PI = 10
7369 11:33:19.711830 [0] MIN Duty = 4844%(X100), DQS PI = 0
7370 11:33:19.711901 [0] AVG Duty = 4953%(X100)
7371 11:33:19.714763
7372 11:33:19.714836 ==DQS 1 ==
7373 11:33:19.718230 Final DQS duty delay cell = 0
7374 11:33:19.721745 [0] MAX Duty = 5249%(X100), DQS PI = 18
7375 11:33:19.724667 [0] MIN Duty = 4938%(X100), DQS PI = 8
7376 11:33:19.724777 [0] AVG Duty = 5093%(X100)
7377 11:33:19.728219
7378 11:33:19.731493 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7379 11:33:19.731576
7380 11:33:19.734636 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7381 11:33:19.737986 [DutyScan_Calibration_Flow] ====Done====
7382 11:33:19.738089
7383 11:33:19.741433 [DutyScan_Calibration_Flow] k_type=3
7384 11:33:19.758717
7385 11:33:19.758828 ==DQM 0 ==
7386 11:33:19.761892 Final DQM duty delay cell = 0
7387 11:33:19.765089 [0] MAX Duty = 5187%(X100), DQS PI = 8
7388 11:33:19.768509 [0] MIN Duty = 4969%(X100), DQS PI = 48
7389 11:33:19.768605 [0] AVG Duty = 5078%(X100)
7390 11:33:19.771835
7391 11:33:19.771925 ==DQM 1 ==
7392 11:33:19.775297 Final DQM duty delay cell = 0
7393 11:33:19.778608 [0] MAX Duty = 5093%(X100), DQS PI = 16
7394 11:33:19.782394 [0] MIN Duty = 4907%(X100), DQS PI = 50
7395 11:33:19.782466 [0] AVG Duty = 5000%(X100)
7396 11:33:19.785321
7397 11:33:19.788735 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7398 11:33:19.788807
7399 11:33:19.791526 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7400 11:33:19.794905 [DutyScan_Calibration_Flow] ====Done====
7401 11:33:19.794972
7402 11:33:19.798370 [DutyScan_Calibration_Flow] k_type=2
7403 11:33:19.814439
7404 11:33:19.814518 ==DQ 0 ==
7405 11:33:19.817791 Final DQ duty delay cell = -4
7406 11:33:19.821172 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7407 11:33:19.824147 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7408 11:33:19.827638 [-4] AVG Duty = 4953%(X100)
7409 11:33:19.827716
7410 11:33:19.827772 ==DQ 1 ==
7411 11:33:19.830843 Final DQ duty delay cell = 0
7412 11:33:19.834260 [0] MAX Duty = 5093%(X100), DQS PI = 16
7413 11:33:19.837432 [0] MIN Duty = 4938%(X100), DQS PI = 8
7414 11:33:19.840718 [0] AVG Duty = 5015%(X100)
7415 11:33:19.840794
7416 11:33:19.844379 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7417 11:33:19.844446
7418 11:33:19.847979 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7419 11:33:19.851205 [DutyScan_Calibration_Flow] ====Done====
7420 11:33:19.854667 nWR fixed to 30
7421 11:33:19.854740 [ModeRegInit_LP4] CH0 RK0
7422 11:33:19.857544 [ModeRegInit_LP4] CH0 RK1
7423 11:33:19.860726 [ModeRegInit_LP4] CH1 RK0
7424 11:33:19.863904 [ModeRegInit_LP4] CH1 RK1
7425 11:33:19.863976 match AC timing 5
7426 11:33:19.870975 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7427 11:33:19.874164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7428 11:33:19.877190 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7429 11:33:19.884163 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7430 11:33:19.887372 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7431 11:33:19.887444 [MiockJmeterHQA]
7432 11:33:19.887500
7433 11:33:19.890810 [DramcMiockJmeter] u1RxGatingPI = 0
7434 11:33:19.894198 0 : 4363, 4137
7435 11:33:19.894261 4 : 4252, 4027
7436 11:33:19.897454 8 : 4252, 4027
7437 11:33:19.897515 12 : 4252, 4027
7438 11:33:19.897568 16 : 4253, 4027
7439 11:33:19.900988 20 : 4253, 4026
7440 11:33:19.901052 24 : 4252, 4027
7441 11:33:19.904395 28 : 4363, 4137
7442 11:33:19.904456 32 : 4252, 4027
7443 11:33:19.907751 36 : 4253, 4026
7444 11:33:19.907810 40 : 4252, 4027
7445 11:33:19.907861 44 : 4252, 4027
7446 11:33:19.911137 48 : 4253, 4026
7447 11:33:19.911194 52 : 4363, 4138
7448 11:33:19.914442 56 : 4363, 4137
7449 11:33:19.914505 60 : 4250, 4027
7450 11:33:19.917882 64 : 4250, 4027
7451 11:33:19.917941 68 : 4250, 4026
7452 11:33:19.920550 72 : 4250, 4027
7453 11:33:19.920609 76 : 4250, 4027
7454 11:33:19.920665 80 : 4361, 4137
7455 11:33:19.923995 84 : 4250, 4027
7456 11:33:19.924055 88 : 4250, 55
7457 11:33:19.927390 92 : 4253, 0
7458 11:33:19.927451 96 : 4363, 0
7459 11:33:19.927501 100 : 4250, 0
7460 11:33:19.930807 104 : 4250, 0
7461 11:33:19.930865 108 : 4253, 0
7462 11:33:19.933973 112 : 4250, 0
7463 11:33:19.934080 116 : 4250, 0
7464 11:33:19.934136 120 : 4249, 0
7465 11:33:19.937617 124 : 4360, 0
7466 11:33:19.937690 128 : 4361, 0
7467 11:33:19.940795 132 : 4360, 0
7468 11:33:19.940863 136 : 4250, 0
7469 11:33:19.940937 140 : 4360, 0
7470 11:33:19.943909 144 : 4361, 0
7471 11:33:19.944010 148 : 4250, 0
7472 11:33:19.944094 152 : 4250, 0
7473 11:33:19.947371 156 : 4250, 0
7474 11:33:19.947435 160 : 4253, 0
7475 11:33:19.950594 164 : 4249, 0
7476 11:33:19.950656 168 : 4250, 0
7477 11:33:19.950708 172 : 4253, 0
7478 11:33:19.953893 176 : 4360, 0
7479 11:33:19.953967 180 : 4250, 0
7480 11:33:19.957209 184 : 4360, 0
7481 11:33:19.957278 188 : 4250, 0
7482 11:33:19.957334 192 : 4250, 0
7483 11:33:19.960674 196 : 4363, 0
7484 11:33:19.960733 200 : 4250, 0
7485 11:33:19.964034 204 : 4250, 1354
7486 11:33:19.964095 208 : 4249, 4018
7487 11:33:19.967334 212 : 4252, 4030
7488 11:33:19.967393 216 : 4250, 4027
7489 11:33:19.970472 220 : 4250, 4026
7490 11:33:19.970533 224 : 4360, 4138
7491 11:33:19.970588 228 : 4252, 4029
7492 11:33:19.973661 232 : 4361, 4138
7493 11:33:19.973718 236 : 4361, 4137
7494 11:33:19.976850 240 : 4250, 4027
7495 11:33:19.976910 244 : 4250, 4027
7496 11:33:19.980245 248 : 4360, 4137
7497 11:33:19.980312 252 : 4250, 4026
7498 11:33:19.983326 256 : 4250, 4027
7499 11:33:19.983391 260 : 4253, 4029
7500 11:33:19.987102 264 : 4250, 4027
7501 11:33:19.987160 268 : 4250, 4026
7502 11:33:19.990118 272 : 4250, 4026
7503 11:33:19.990218 276 : 4360, 4138
7504 11:33:19.993276 280 : 4250, 4027
7505 11:33:19.993343 284 : 4250, 4026
7506 11:33:19.996631 288 : 4361, 4137
7507 11:33:19.996707 292 : 4250, 4027
7508 11:33:19.996768 296 : 4250, 4027
7509 11:33:19.999824 300 : 4360, 4137
7510 11:33:19.999921 304 : 4250, 4026
7511 11:33:20.003627 308 : 4250, 3944
7512 11:33:20.003796 312 : 4250, 1703
7513 11:33:20.003917
7514 11:33:20.007041 MIOCK jitter meter ch=0
7515 11:33:20.007112
7516 11:33:20.010215 1T = (312-88) = 224 dly cells
7517 11:33:20.016829 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7518 11:33:20.016903 ==
7519 11:33:20.019553 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 11:33:20.023027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 11:33:20.023096 ==
7522 11:33:20.029574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 11:33:20.033018 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 11:33:20.036451 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 11:33:20.042972 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 11:33:20.051806 [CA 0] Center 42 (12~73) winsize 62
7527 11:33:20.055154 [CA 1] Center 42 (12~73) winsize 62
7528 11:33:20.059065 [CA 2] Center 37 (8~67) winsize 60
7529 11:33:20.061757 [CA 3] Center 37 (7~67) winsize 61
7530 11:33:20.065154 [CA 4] Center 36 (6~66) winsize 61
7531 11:33:20.068455 [CA 5] Center 35 (6~64) winsize 59
7532 11:33:20.068522
7533 11:33:20.071911 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 11:33:20.071984
7535 11:33:20.075276 [CATrainingPosCal] consider 1 rank data
7536 11:33:20.078624 u2DelayCellTimex100 = 290/100 ps
7537 11:33:20.081914 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7538 11:33:20.088402 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7539 11:33:20.091967 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7540 11:33:20.095203 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7541 11:33:20.098414 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7542 11:33:20.101645 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7543 11:33:20.101712
7544 11:33:20.104944 CA PerBit enable=1, Macro0, CA PI delay=35
7545 11:33:20.105011
7546 11:33:20.108200 [CBTSetCACLKResult] CA Dly = 35
7547 11:33:20.111408 CS Dly: 9 (0~40)
7548 11:33:20.114917 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 11:33:20.118354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 11:33:20.118422 ==
7551 11:33:20.121375 Dram Type= 6, Freq= 0, CH_0, rank 1
7552 11:33:20.124809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 11:33:20.128342 ==
7554 11:33:20.131334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 11:33:20.134726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 11:33:20.141300 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 11:33:20.144768 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 11:33:20.155667 [CA 0] Center 42 (12~73) winsize 62
7559 11:33:20.158315 [CA 1] Center 42 (12~73) winsize 62
7560 11:33:20.161515 [CA 2] Center 37 (8~67) winsize 60
7561 11:33:20.165201 [CA 3] Center 37 (7~68) winsize 62
7562 11:33:20.168121 [CA 4] Center 35 (6~65) winsize 60
7563 11:33:20.171651 [CA 5] Center 35 (5~65) winsize 61
7564 11:33:20.171720
7565 11:33:20.175178 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7566 11:33:20.175245
7567 11:33:20.178324 [CATrainingPosCal] consider 2 rank data
7568 11:33:20.181535 u2DelayCellTimex100 = 290/100 ps
7569 11:33:20.184964 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7570 11:33:20.191606 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7571 11:33:20.195053 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7572 11:33:20.198362 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7573 11:33:20.201742 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7574 11:33:20.204880 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7575 11:33:20.204976
7576 11:33:20.208306 CA PerBit enable=1, Macro0, CA PI delay=35
7577 11:33:20.208408
7578 11:33:20.211730 [CBTSetCACLKResult] CA Dly = 35
7579 11:33:20.215155 CS Dly: 10 (0~42)
7580 11:33:20.217816 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 11:33:20.221205 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 11:33:20.221271
7583 11:33:20.225015 ----->DramcWriteLeveling(PI) begin...
7584 11:33:20.225083 ==
7585 11:33:20.228329 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 11:33:20.231603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 11:33:20.234723 ==
7588 11:33:20.234788 Write leveling (Byte 0): 34 => 34
7589 11:33:20.238756 Write leveling (Byte 1): 27 => 27
7590 11:33:20.241754 DramcWriteLeveling(PI) end<-----
7591 11:33:20.241823
7592 11:33:20.241920 ==
7593 11:33:20.244685 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 11:33:20.251929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 11:33:20.251996 ==
7596 11:33:20.252056 [Gating] SW mode calibration
7597 11:33:20.261692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7598 11:33:20.265152 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7599 11:33:20.268503 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7600 11:33:20.275131 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7601 11:33:20.278263 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7602 11:33:20.281724 1 4 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)
7603 11:33:20.288238 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
7604 11:33:20.291735 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7605 11:33:20.294849 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7606 11:33:20.301743 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7607 11:33:20.304708 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7608 11:33:20.308034 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7609 11:33:20.314688 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7610 11:33:20.317946 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7611 11:33:20.321352 1 5 16 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (0 0)
7612 11:33:20.328156 1 5 20 | B1->B0 | 2424 2b2b | 0 0 | (1 0) (0 0)
7613 11:33:20.331387 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7614 11:33:20.334824 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7615 11:33:20.340878 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 11:33:20.344930 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7617 11:33:20.347506 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7618 11:33:20.354193 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7619 11:33:20.357849 1 6 16 | B1->B0 | 2727 4645 | 0 1 | (0 0) (0 0)
7620 11:33:20.361173 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7621 11:33:20.367882 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7622 11:33:20.370847 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 11:33:20.374701 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 11:33:20.381489 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 11:33:20.384217 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 11:33:20.388063 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 11:33:20.394672 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 11:33:20.397671 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 11:33:20.400992 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:33:20.408012 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:33:20.411181 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:33:20.414731 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 11:33:20.417722 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 11:33:20.424801 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 11:33:20.428176 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 11:33:20.430879 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 11:33:20.438092 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 11:33:20.441535 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 11:33:20.444912 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 11:33:20.451031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 11:33:20.454359 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 11:33:20.457700 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 11:33:20.464159 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 11:33:20.464227 Total UI for P1: 0, mck2ui 16
7645 11:33:20.471338 best dqsien dly found for B0: ( 1, 9, 10)
7646 11:33:20.474792 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 11:33:20.477865 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:33:20.481079 Total UI for P1: 0, mck2ui 16
7649 11:33:20.484618 best dqsien dly found for B1: ( 1, 9, 18)
7650 11:33:20.487704 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7651 11:33:20.491035 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7652 11:33:20.491111
7653 11:33:20.497366 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7654 11:33:20.501252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7655 11:33:20.501321 [Gating] SW calibration Done
7656 11:33:20.504586 ==
7657 11:33:20.507301 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 11:33:20.511210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 11:33:20.511282 ==
7660 11:33:20.511337 RX Vref Scan: 0
7661 11:33:20.511389
7662 11:33:20.514472 RX Vref 0 -> 0, step: 1
7663 11:33:20.514536
7664 11:33:20.517313 RX Delay 0 -> 252, step: 8
7665 11:33:20.520688 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7666 11:33:20.524654 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7667 11:33:20.527813 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7668 11:33:20.534359 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7669 11:33:20.537890 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7670 11:33:20.541001 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7671 11:33:20.544452 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7672 11:33:20.547874 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7673 11:33:20.551189 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7674 11:33:20.557773 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7675 11:33:20.561214 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7676 11:33:20.564628 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7677 11:33:20.567969 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7678 11:33:20.574590 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7679 11:33:20.577655 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7680 11:33:20.580813 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7681 11:33:20.580883 ==
7682 11:33:20.584324 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 11:33:20.587707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 11:33:20.587775 ==
7685 11:33:20.590990 DQS Delay:
7686 11:33:20.591055 DQS0 = 0, DQS1 = 0
7687 11:33:20.591110 DQM Delay:
7688 11:33:20.594192 DQM0 = 136, DQM1 = 130
7689 11:33:20.594257 DQ Delay:
7690 11:33:20.597366 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7691 11:33:20.600915 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7692 11:33:20.607602 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7693 11:33:20.610605 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7694 11:33:20.610688
7695 11:33:20.610749
7696 11:33:20.610808 ==
7697 11:33:20.613760 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 11:33:20.617177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 11:33:20.617251 ==
7700 11:33:20.617308
7701 11:33:20.617363
7702 11:33:20.620965 TX Vref Scan disable
7703 11:33:20.624124 == TX Byte 0 ==
7704 11:33:20.627593 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7705 11:33:20.630878 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7706 11:33:20.634258 == TX Byte 1 ==
7707 11:33:20.637429 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7708 11:33:20.640735 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7709 11:33:20.640825 ==
7710 11:33:20.643917 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 11:33:20.647578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 11:33:20.650524 ==
7713 11:33:20.662223
7714 11:33:20.665514 TX Vref early break, caculate TX vref
7715 11:33:20.668892 TX Vref=16, minBit 1, minWin=23, winSum=379
7716 11:33:20.672261 TX Vref=18, minBit 7, minWin=22, winSum=387
7717 11:33:20.675590 TX Vref=20, minBit 7, minWin=24, winSum=404
7718 11:33:20.678916 TX Vref=22, minBit 7, minWin=24, winSum=410
7719 11:33:20.682189 TX Vref=24, minBit 5, minWin=25, winSum=420
7720 11:33:20.688800 TX Vref=26, minBit 4, minWin=25, winSum=423
7721 11:33:20.692185 TX Vref=28, minBit 6, minWin=25, winSum=426
7722 11:33:20.695473 TX Vref=30, minBit 1, minWin=25, winSum=414
7723 11:33:20.698884 TX Vref=32, minBit 2, minWin=24, winSum=406
7724 11:33:20.702175 TX Vref=34, minBit 6, minWin=23, winSum=397
7725 11:33:20.708864 [TxChooseVref] Worse bit 6, Min win 25, Win sum 426, Final Vref 28
7726 11:33:20.708960
7727 11:33:20.712066 Final TX Range 0 Vref 28
7728 11:33:20.712130
7729 11:33:20.712184 ==
7730 11:33:20.715810 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 11:33:20.718607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 11:33:20.718683 ==
7733 11:33:20.718738
7734 11:33:20.718789
7735 11:33:20.722402 TX Vref Scan disable
7736 11:33:20.729045 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7737 11:33:20.729156 == TX Byte 0 ==
7738 11:33:20.732487 u2DelayCellOfst[0]=10 cells (3 PI)
7739 11:33:20.735343 u2DelayCellOfst[1]=16 cells (5 PI)
7740 11:33:20.738615 u2DelayCellOfst[2]=10 cells (3 PI)
7741 11:33:20.741993 u2DelayCellOfst[3]=10 cells (3 PI)
7742 11:33:20.745437 u2DelayCellOfst[4]=6 cells (2 PI)
7743 11:33:20.748647 u2DelayCellOfst[5]=0 cells (0 PI)
7744 11:33:20.752045 u2DelayCellOfst[6]=16 cells (5 PI)
7745 11:33:20.752112 u2DelayCellOfst[7]=16 cells (5 PI)
7746 11:33:20.758603 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7747 11:33:20.761896 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7748 11:33:20.761986 == TX Byte 1 ==
7749 11:33:20.765100 u2DelayCellOfst[8]=0 cells (0 PI)
7750 11:33:20.768994 u2DelayCellOfst[9]=0 cells (0 PI)
7751 11:33:20.771791 u2DelayCellOfst[10]=10 cells (3 PI)
7752 11:33:20.775626 u2DelayCellOfst[11]=3 cells (1 PI)
7753 11:33:20.779033 u2DelayCellOfst[12]=10 cells (3 PI)
7754 11:33:20.781751 u2DelayCellOfst[13]=10 cells (3 PI)
7755 11:33:20.785170 u2DelayCellOfst[14]=13 cells (4 PI)
7756 11:33:20.788502 u2DelayCellOfst[15]=10 cells (3 PI)
7757 11:33:20.791769 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7758 11:33:20.798671 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7759 11:33:20.798760 DramC Write-DBI on
7760 11:33:20.798861 ==
7761 11:33:20.802013 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 11:33:20.805393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 11:33:20.805480 ==
7764 11:33:20.808836
7765 11:33:20.808903
7766 11:33:20.808956 TX Vref Scan disable
7767 11:33:20.811550 == TX Byte 0 ==
7768 11:33:20.814975 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7769 11:33:20.818875 == TX Byte 1 ==
7770 11:33:20.822118 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7771 11:33:20.822188 DramC Write-DBI off
7772 11:33:20.825597
7773 11:33:20.825684 [DATLAT]
7774 11:33:20.825763 Freq=1600, CH0 RK0
7775 11:33:20.825855
7776 11:33:20.828652 DATLAT Default: 0xf
7777 11:33:20.828751 0, 0xFFFF, sum = 0
7778 11:33:20.831777 1, 0xFFFF, sum = 0
7779 11:33:20.835389 2, 0xFFFF, sum = 0
7780 11:33:20.835454 3, 0xFFFF, sum = 0
7781 11:33:20.838555 4, 0xFFFF, sum = 0
7782 11:33:20.838652 5, 0xFFFF, sum = 0
7783 11:33:20.842072 6, 0xFFFF, sum = 0
7784 11:33:20.842145 7, 0xFFFF, sum = 0
7785 11:33:20.844890 8, 0xFFFF, sum = 0
7786 11:33:20.844957 9, 0xFFFF, sum = 0
7787 11:33:20.848420 10, 0xFFFF, sum = 0
7788 11:33:20.848487 11, 0xFFFF, sum = 0
7789 11:33:20.851763 12, 0xFFFF, sum = 0
7790 11:33:20.851828 13, 0xFFFF, sum = 0
7791 11:33:20.855054 14, 0x0, sum = 1
7792 11:33:20.855150 15, 0x0, sum = 2
7793 11:33:20.858544 16, 0x0, sum = 3
7794 11:33:20.858611 17, 0x0, sum = 4
7795 11:33:20.861946 best_step = 15
7796 11:33:20.862083
7797 11:33:20.862160 ==
7798 11:33:20.865143 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 11:33:20.868489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 11:33:20.868555 ==
7801 11:33:20.868609 RX Vref Scan: 1
7802 11:33:20.871889
7803 11:33:20.871976 Set Vref Range= 24 -> 127
7804 11:33:20.872058
7805 11:33:20.875151 RX Vref 24 -> 127, step: 1
7806 11:33:20.875240
7807 11:33:20.878235 RX Delay 27 -> 252, step: 4
7808 11:33:20.878321
7809 11:33:20.881472 Set Vref, RX VrefLevel [Byte0]: 24
7810 11:33:20.885274 [Byte1]: 24
7811 11:33:20.885341
7812 11:33:20.888104 Set Vref, RX VrefLevel [Byte0]: 25
7813 11:33:20.891571 [Byte1]: 25
7814 11:33:20.891639
7815 11:33:20.894974 Set Vref, RX VrefLevel [Byte0]: 26
7816 11:33:20.898405 [Byte1]: 26
7817 11:33:20.902397
7818 11:33:20.902461 Set Vref, RX VrefLevel [Byte0]: 27
7819 11:33:20.905154 [Byte1]: 27
7820 11:33:20.909687
7821 11:33:20.909753 Set Vref, RX VrefLevel [Byte0]: 28
7822 11:33:20.913060 [Byte1]: 28
7823 11:33:20.917117
7824 11:33:20.917196 Set Vref, RX VrefLevel [Byte0]: 29
7825 11:33:20.920714 [Byte1]: 29
7826 11:33:20.924806
7827 11:33:20.924870 Set Vref, RX VrefLevel [Byte0]: 30
7828 11:33:20.928096 [Byte1]: 30
7829 11:33:20.932168
7830 11:33:20.932240 Set Vref, RX VrefLevel [Byte0]: 31
7831 11:33:20.935495 [Byte1]: 31
7832 11:33:20.939322
7833 11:33:20.939394 Set Vref, RX VrefLevel [Byte0]: 32
7834 11:33:20.942596 [Byte1]: 32
7835 11:33:20.947059
7836 11:33:20.947130 Set Vref, RX VrefLevel [Byte0]: 33
7837 11:33:20.950394 [Byte1]: 33
7838 11:33:20.954432
7839 11:33:20.954501 Set Vref, RX VrefLevel [Byte0]: 34
7840 11:33:20.957677 [Byte1]: 34
7841 11:33:20.962312
7842 11:33:20.962406 Set Vref, RX VrefLevel [Byte0]: 35
7843 11:33:20.965347 [Byte1]: 35
7844 11:33:20.969469
7845 11:33:20.969565 Set Vref, RX VrefLevel [Byte0]: 36
7846 11:33:20.972814 [Byte1]: 36
7847 11:33:20.977337
7848 11:33:20.977437 Set Vref, RX VrefLevel [Byte0]: 37
7849 11:33:20.980597 [Byte1]: 37
7850 11:33:20.984588
7851 11:33:20.984660 Set Vref, RX VrefLevel [Byte0]: 38
7852 11:33:20.988371 [Byte1]: 38
7853 11:33:20.992526
7854 11:33:20.992593 Set Vref, RX VrefLevel [Byte0]: 39
7855 11:33:20.995778 [Byte1]: 39
7856 11:33:20.999706
7857 11:33:20.999772 Set Vref, RX VrefLevel [Byte0]: 40
7858 11:33:21.003434 [Byte1]: 40
7859 11:33:21.007305
7860 11:33:21.007370 Set Vref, RX VrefLevel [Byte0]: 41
7861 11:33:21.010767 [Byte1]: 41
7862 11:33:21.015384
7863 11:33:21.015456 Set Vref, RX VrefLevel [Byte0]: 42
7864 11:33:21.018267 [Byte1]: 42
7865 11:33:21.022856
7866 11:33:21.022918 Set Vref, RX VrefLevel [Byte0]: 43
7867 11:33:21.025590 [Byte1]: 43
7868 11:33:21.029710
7869 11:33:21.029777 Set Vref, RX VrefLevel [Byte0]: 44
7870 11:33:21.033059 [Byte1]: 44
7871 11:33:21.037832
7872 11:33:21.037922 Set Vref, RX VrefLevel [Byte0]: 45
7873 11:33:21.041097 [Byte1]: 45
7874 11:33:21.044934
7875 11:33:21.045021 Set Vref, RX VrefLevel [Byte0]: 46
7876 11:33:21.048242 [Byte1]: 46
7877 11:33:21.052799
7878 11:33:21.052860 Set Vref, RX VrefLevel [Byte0]: 47
7879 11:33:21.056096 [Byte1]: 47
7880 11:33:21.060138
7881 11:33:21.060198 Set Vref, RX VrefLevel [Byte0]: 48
7882 11:33:21.063436 [Byte1]: 48
7883 11:33:21.067438
7884 11:33:21.067503 Set Vref, RX VrefLevel [Byte0]: 49
7885 11:33:21.070868 [Byte1]: 49
7886 11:33:21.075062
7887 11:33:21.075128 Set Vref, RX VrefLevel [Byte0]: 50
7888 11:33:21.078808 [Byte1]: 50
7889 11:33:21.082641
7890 11:33:21.082707 Set Vref, RX VrefLevel [Byte0]: 51
7891 11:33:21.085820 [Byte1]: 51
7892 11:33:21.090210
7893 11:33:21.090279 Set Vref, RX VrefLevel [Byte0]: 52
7894 11:33:21.093726 [Byte1]: 52
7895 11:33:21.097954
7896 11:33:21.098076 Set Vref, RX VrefLevel [Byte0]: 53
7897 11:33:21.101383 [Byte1]: 53
7898 11:33:21.105272
7899 11:33:21.105339 Set Vref, RX VrefLevel [Byte0]: 54
7900 11:33:21.109067 [Byte1]: 54
7901 11:33:21.113072
7902 11:33:21.113170 Set Vref, RX VrefLevel [Byte0]: 55
7903 11:33:21.116482 [Byte1]: 55
7904 11:33:21.120410
7905 11:33:21.120508 Set Vref, RX VrefLevel [Byte0]: 56
7906 11:33:21.123517 [Byte1]: 56
7907 11:33:21.128362
7908 11:33:21.128426 Set Vref, RX VrefLevel [Byte0]: 57
7909 11:33:21.131314 [Byte1]: 57
7910 11:33:21.135696
7911 11:33:21.135787 Set Vref, RX VrefLevel [Byte0]: 58
7912 11:33:21.138830 [Byte1]: 58
7913 11:33:21.143047
7914 11:33:21.143113 Set Vref, RX VrefLevel [Byte0]: 59
7915 11:33:21.146401 [Byte1]: 59
7916 11:33:21.150329
7917 11:33:21.150429 Set Vref, RX VrefLevel [Byte0]: 60
7918 11:33:21.154106 [Byte1]: 60
7919 11:33:21.157962
7920 11:33:21.158096 Set Vref, RX VrefLevel [Byte0]: 61
7921 11:33:21.161291 [Byte1]: 61
7922 11:33:21.166141
7923 11:33:21.166238 Set Vref, RX VrefLevel [Byte0]: 62
7924 11:33:21.168832 [Byte1]: 62
7925 11:33:21.173009
7926 11:33:21.173102 Set Vref, RX VrefLevel [Byte0]: 63
7927 11:33:21.176289 [Byte1]: 63
7928 11:33:21.180428
7929 11:33:21.180530 Set Vref, RX VrefLevel [Byte0]: 64
7930 11:33:21.183835 [Byte1]: 64
7931 11:33:21.188295
7932 11:33:21.188394 Set Vref, RX VrefLevel [Byte0]: 65
7933 11:33:21.191533 [Byte1]: 65
7934 11:33:21.195609
7935 11:33:21.195684 Set Vref, RX VrefLevel [Byte0]: 66
7936 11:33:21.202315 [Byte1]: 66
7937 11:33:21.202432
7938 11:33:21.205580 Set Vref, RX VrefLevel [Byte0]: 67
7939 11:33:21.208805 [Byte1]: 67
7940 11:33:21.208868
7941 11:33:21.211850 Set Vref, RX VrefLevel [Byte0]: 68
7942 11:33:21.215458 [Byte1]: 68
7943 11:33:21.215593
7944 11:33:21.218897 Set Vref, RX VrefLevel [Byte0]: 69
7945 11:33:21.222276 [Byte1]: 69
7946 11:33:21.225785
7947 11:33:21.225919 Set Vref, RX VrefLevel [Byte0]: 70
7948 11:33:21.229082 [Byte1]: 70
7949 11:33:21.233531
7950 11:33:21.233627 Set Vref, RX VrefLevel [Byte0]: 71
7951 11:33:21.236827 [Byte1]: 71
7952 11:33:21.240818
7953 11:33:21.240917 Set Vref, RX VrefLevel [Byte0]: 72
7954 11:33:21.244059 [Byte1]: 72
7955 11:33:21.248223
7956 11:33:21.248377 Set Vref, RX VrefLevel [Byte0]: 73
7957 11:33:21.251792 [Byte1]: 73
7958 11:33:21.256046
7959 11:33:21.256122 Set Vref, RX VrefLevel [Byte0]: 74
7960 11:33:21.259297 [Byte1]: 74
7961 11:33:21.263759
7962 11:33:21.263838 Final RX Vref Byte 0 = 60 to rank0
7963 11:33:21.267026 Final RX Vref Byte 1 = 63 to rank0
7964 11:33:21.270467 Final RX Vref Byte 0 = 60 to rank1
7965 11:33:21.273231 Final RX Vref Byte 1 = 63 to rank1==
7966 11:33:21.276648 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 11:33:21.283450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 11:33:21.283520 ==
7969 11:33:21.283577 DQS Delay:
7970 11:33:21.283639 DQS0 = 0, DQS1 = 0
7971 11:33:21.286680 DQM Delay:
7972 11:33:21.286749 DQM0 = 134, DQM1 = 127
7973 11:33:21.289944 DQ Delay:
7974 11:33:21.293386 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7975 11:33:21.296598 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7976 11:33:21.300366 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7977 11:33:21.303555 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7978 11:33:21.303624
7979 11:33:21.303679
7980 11:33:21.303735
7981 11:33:21.306993 [DramC_TX_OE_Calibration] TA2
7982 11:33:21.309823 Original DQ_B0 (3 6) =30, OEN = 27
7983 11:33:21.313164 Original DQ_B1 (3 6) =30, OEN = 27
7984 11:33:21.316557 24, 0x0, End_B0=24 End_B1=24
7985 11:33:21.316625 25, 0x0, End_B0=25 End_B1=25
7986 11:33:21.320053 26, 0x0, End_B0=26 End_B1=26
7987 11:33:21.323429 27, 0x0, End_B0=27 End_B1=27
7988 11:33:21.326750 28, 0x0, End_B0=28 End_B1=28
7989 11:33:21.326821 29, 0x0, End_B0=29 End_B1=29
7990 11:33:21.330158 30, 0x0, End_B0=30 End_B1=30
7991 11:33:21.333206 31, 0x4141, End_B0=30 End_B1=30
7992 11:33:21.336577 Byte0 end_step=30 best_step=27
7993 11:33:21.340127 Byte1 end_step=30 best_step=27
7994 11:33:21.343243 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 11:33:21.346811 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 11:33:21.346878
7997 11:33:21.346940
7998 11:33:21.353222 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7999 11:33:21.356382 CH0 RK0: MR19=303, MR18=2723
8000 11:33:21.363252 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8001 11:33:21.363344
8002 11:33:21.366317 ----->DramcWriteLeveling(PI) begin...
8003 11:33:21.366412 ==
8004 11:33:21.369738 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 11:33:21.372797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 11:33:21.372890 ==
8007 11:33:21.376102 Write leveling (Byte 0): 37 => 37
8008 11:33:21.379529 Write leveling (Byte 1): 27 => 27
8009 11:33:21.383324 DramcWriteLeveling(PI) end<-----
8010 11:33:21.383407
8011 11:33:21.383492 ==
8012 11:33:21.386083 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 11:33:21.389568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 11:33:21.389634 ==
8015 11:33:21.393031 [Gating] SW mode calibration
8016 11:33:21.399862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 11:33:21.406776 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 11:33:21.409814 1 4 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8019 11:33:21.413183 1 4 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8020 11:33:21.419856 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 11:33:21.423254 1 4 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8022 11:33:21.426766 1 4 16 | B1->B0 | 2c2c 3c3b | 1 1 | (1 1) (1 1)
8023 11:33:21.432852 1 4 20 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (1 1)
8024 11:33:21.436042 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8025 11:33:21.439957 1 4 28 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
8026 11:33:21.446051 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8027 11:33:21.449278 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
8028 11:33:21.452689 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 11:33:21.459787 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8030 11:33:21.462796 1 5 16 | B1->B0 | 2828 2524 | 0 1 | (1 0) (1 0)
8031 11:33:21.466279 1 5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8032 11:33:21.473134 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8033 11:33:21.475840 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8034 11:33:21.479658 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8035 11:33:21.486030 1 6 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8036 11:33:21.489651 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 11:33:21.493020 1 6 12 | B1->B0 | 2727 3736 | 0 1 | (0 0) (0 0)
8038 11:33:21.499296 1 6 16 | B1->B0 | 4040 4645 | 0 1 | (0 0) (0 0)
8039 11:33:21.502702 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8040 11:33:21.505833 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8041 11:33:21.512498 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 11:33:21.515708 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 11:33:21.519261 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 11:33:21.525988 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 11:33:21.529405 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8046 11:33:21.532075 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8047 11:33:21.538842 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:33:21.542230 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:33:21.545566 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:33:21.552101 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:33:21.555490 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:33:21.559012 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:33:21.562424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:33:21.569075 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:33:21.572346 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 11:33:21.575408 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:33:21.582184 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:33:21.585420 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:33:21.588767 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:33:21.595516 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 11:33:21.598845 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8062 11:33:21.602032 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8063 11:33:21.609019 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 11:33:21.609117 Total UI for P1: 0, mck2ui 16
8065 11:33:21.615415 best dqsien dly found for B0: ( 1, 9, 14)
8066 11:33:21.615491 Total UI for P1: 0, mck2ui 16
8067 11:33:21.622332 best dqsien dly found for B1: ( 1, 9, 14)
8068 11:33:21.625748 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8069 11:33:21.628980 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8070 11:33:21.629081
8071 11:33:21.631790 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8072 11:33:21.635319 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8073 11:33:21.639187 [Gating] SW calibration Done
8074 11:33:21.639266 ==
8075 11:33:21.641897 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 11:33:21.645181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 11:33:21.645259 ==
8078 11:33:21.648490 RX Vref Scan: 0
8079 11:33:21.648567
8080 11:33:21.648643 RX Vref 0 -> 0, step: 1
8081 11:33:21.648715
8082 11:33:21.652307 RX Delay 0 -> 252, step: 8
8083 11:33:21.655651 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8084 11:33:21.661732 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8085 11:33:21.665205 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8086 11:33:21.668652 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8087 11:33:21.671884 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8088 11:33:21.675191 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8089 11:33:21.681997 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8090 11:33:21.685159 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8091 11:33:21.688255 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8092 11:33:21.691979 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8093 11:33:21.695418 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8094 11:33:21.701629 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8095 11:33:21.704881 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8096 11:33:21.708138 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8097 11:33:21.711820 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8098 11:33:21.718505 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8099 11:33:21.718608 ==
8100 11:33:21.721817 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 11:33:21.725199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 11:33:21.725268 ==
8103 11:33:21.725324 DQS Delay:
8104 11:33:21.728664 DQS0 = 0, DQS1 = 0
8105 11:33:21.728727 DQM Delay:
8106 11:33:21.731779 DQM0 = 137, DQM1 = 130
8107 11:33:21.731844 DQ Delay:
8108 11:33:21.735295 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8109 11:33:21.738292 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8110 11:33:21.741808 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8111 11:33:21.745112 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8112 11:33:21.745205
8113 11:33:21.745288
8114 11:33:21.745371 ==
8115 11:33:21.748085 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 11:33:21.754709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 11:33:21.754805 ==
8118 11:33:21.754889
8119 11:33:21.754968
8120 11:33:21.755050 TX Vref Scan disable
8121 11:33:21.758916 == TX Byte 0 ==
8122 11:33:21.762257 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8123 11:33:21.768665 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8124 11:33:21.768737 == TX Byte 1 ==
8125 11:33:21.771951 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8126 11:33:21.778764 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8127 11:33:21.778838 ==
8128 11:33:21.782208 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 11:33:21.785564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 11:33:21.785654 ==
8131 11:33:21.798816
8132 11:33:21.802293 TX Vref early break, caculate TX vref
8133 11:33:21.805588 TX Vref=16, minBit 3, minWin=22, winSum=386
8134 11:33:21.809121 TX Vref=18, minBit 3, minWin=23, winSum=394
8135 11:33:21.811787 TX Vref=20, minBit 1, minWin=24, winSum=406
8136 11:33:21.815283 TX Vref=22, minBit 1, minWin=25, winSum=416
8137 11:33:21.819081 TX Vref=24, minBit 1, minWin=25, winSum=421
8138 11:33:21.825342 TX Vref=26, minBit 1, minWin=25, winSum=424
8139 11:33:21.828828 TX Vref=28, minBit 3, minWin=25, winSum=422
8140 11:33:21.832210 TX Vref=30, minBit 0, minWin=25, winSum=417
8141 11:33:21.835612 TX Vref=32, minBit 0, minWin=24, winSum=409
8142 11:33:21.838953 TX Vref=34, minBit 1, minWin=24, winSum=400
8143 11:33:21.845314 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8144 11:33:21.845387
8145 11:33:21.848874 Final TX Range 0 Vref 26
8146 11:33:21.848976
8147 11:33:21.849063 ==
8148 11:33:21.852119 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 11:33:21.855417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 11:33:21.855482 ==
8151 11:33:21.855538
8152 11:33:21.855631
8153 11:33:21.858855 TX Vref Scan disable
8154 11:33:21.865162 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8155 11:33:21.865254 == TX Byte 0 ==
8156 11:33:21.868626 u2DelayCellOfst[0]=13 cells (4 PI)
8157 11:33:21.871993 u2DelayCellOfst[1]=16 cells (5 PI)
8158 11:33:21.875613 u2DelayCellOfst[2]=10 cells (3 PI)
8159 11:33:21.878646 u2DelayCellOfst[3]=13 cells (4 PI)
8160 11:33:21.881923 u2DelayCellOfst[4]=10 cells (3 PI)
8161 11:33:21.885198 u2DelayCellOfst[5]=0 cells (0 PI)
8162 11:33:21.888309 u2DelayCellOfst[6]=16 cells (5 PI)
8163 11:33:21.892073 u2DelayCellOfst[7]=16 cells (5 PI)
8164 11:33:21.895362 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8165 11:33:21.898817 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8166 11:33:21.901569 == TX Byte 1 ==
8167 11:33:21.901664 u2DelayCellOfst[8]=0 cells (0 PI)
8168 11:33:21.904978 u2DelayCellOfst[9]=0 cells (0 PI)
8169 11:33:21.908215 u2DelayCellOfst[10]=6 cells (2 PI)
8170 11:33:21.911965 u2DelayCellOfst[11]=6 cells (2 PI)
8171 11:33:21.914993 u2DelayCellOfst[12]=10 cells (3 PI)
8172 11:33:21.918710 u2DelayCellOfst[13]=10 cells (3 PI)
8173 11:33:21.921419 u2DelayCellOfst[14]=13 cells (4 PI)
8174 11:33:21.924709 u2DelayCellOfst[15]=10 cells (3 PI)
8175 11:33:21.928562 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8176 11:33:21.935219 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8177 11:33:21.935328 DramC Write-DBI on
8178 11:33:21.935403 ==
8179 11:33:21.938662 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 11:33:21.942067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 11:33:21.944707 ==
8182 11:33:21.944802
8183 11:33:21.944891
8184 11:33:21.944981 TX Vref Scan disable
8185 11:33:21.948735 == TX Byte 0 ==
8186 11:33:21.952148 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8187 11:33:21.955317 == TX Byte 1 ==
8188 11:33:21.958565 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8189 11:33:21.961814 DramC Write-DBI off
8190 11:33:21.961883
8191 11:33:21.961972 [DATLAT]
8192 11:33:21.962111 Freq=1600, CH0 RK1
8193 11:33:21.962198
8194 11:33:21.965200 DATLAT Default: 0xf
8195 11:33:21.965267 0, 0xFFFF, sum = 0
8196 11:33:21.968695 1, 0xFFFF, sum = 0
8197 11:33:21.968792 2, 0xFFFF, sum = 0
8198 11:33:21.972017 3, 0xFFFF, sum = 0
8199 11:33:21.974733 4, 0xFFFF, sum = 0
8200 11:33:21.974802 5, 0xFFFF, sum = 0
8201 11:33:21.978125 6, 0xFFFF, sum = 0
8202 11:33:21.978199 7, 0xFFFF, sum = 0
8203 11:33:21.981478 8, 0xFFFF, sum = 0
8204 11:33:21.981549 9, 0xFFFF, sum = 0
8205 11:33:21.985232 10, 0xFFFF, sum = 0
8206 11:33:21.985303 11, 0xFFFF, sum = 0
8207 11:33:21.988632 12, 0xFFFF, sum = 0
8208 11:33:21.988702 13, 0xFFFF, sum = 0
8209 11:33:21.991671 14, 0x0, sum = 1
8210 11:33:21.991745 15, 0x0, sum = 2
8211 11:33:21.994890 16, 0x0, sum = 3
8212 11:33:21.994966 17, 0x0, sum = 4
8213 11:33:21.998508 best_step = 15
8214 11:33:21.998603
8215 11:33:21.998669 ==
8216 11:33:22.001660 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 11:33:22.005056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 11:33:22.005150 ==
8219 11:33:22.005235 RX Vref Scan: 0
8220 11:33:22.008255
8221 11:33:22.008342 RX Vref 0 -> 0, step: 1
8222 11:33:22.008403
8223 11:33:22.011568 RX Delay 19 -> 252, step: 4
8224 11:33:22.015261 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8225 11:33:22.022169 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8226 11:33:22.024816 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8227 11:33:22.028416 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8228 11:33:22.031907 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8229 11:33:22.035132 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8230 11:33:22.038341 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8231 11:33:22.044910 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8232 11:33:22.048383 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8233 11:33:22.051786 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8234 11:33:22.055148 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8235 11:33:22.058470 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8236 11:33:22.065017 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8237 11:33:22.068458 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8238 11:33:22.071853 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8239 11:33:22.075238 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8240 11:33:22.075333 ==
8241 11:33:22.078097 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 11:33:22.084736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 11:33:22.084810 ==
8244 11:33:22.084868 DQS Delay:
8245 11:33:22.088030 DQS0 = 0, DQS1 = 0
8246 11:33:22.088104 DQM Delay:
8247 11:33:22.088161 DQM0 = 134, DQM1 = 126
8248 11:33:22.091876 DQ Delay:
8249 11:33:22.095157 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8250 11:33:22.098668 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8251 11:33:22.101329 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8252 11:33:22.104760 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =134
8253 11:33:22.104848
8254 11:33:22.104904
8255 11:33:22.104956
8256 11:33:22.108095 [DramC_TX_OE_Calibration] TA2
8257 11:33:22.111313 Original DQ_B0 (3 6) =30, OEN = 27
8258 11:33:22.114608 Original DQ_B1 (3 6) =30, OEN = 27
8259 11:33:22.118122 24, 0x0, End_B0=24 End_B1=24
8260 11:33:22.118216 25, 0x0, End_B0=25 End_B1=25
8261 11:33:22.121675 26, 0x0, End_B0=26 End_B1=26
8262 11:33:22.124931 27, 0x0, End_B0=27 End_B1=27
8263 11:33:22.128392 28, 0x0, End_B0=28 End_B1=28
8264 11:33:22.131473 29, 0x0, End_B0=29 End_B1=29
8265 11:33:22.131540 30, 0x0, End_B0=30 End_B1=30
8266 11:33:22.134794 31, 0x5151, End_B0=30 End_B1=30
8267 11:33:22.138119 Byte0 end_step=30 best_step=27
8268 11:33:22.141761 Byte1 end_step=30 best_step=27
8269 11:33:22.144662 Byte0 TX OE(2T, 0.5T) = (3, 3)
8270 11:33:22.147986 Byte1 TX OE(2T, 0.5T) = (3, 3)
8271 11:33:22.148088
8272 11:33:22.148172
8273 11:33:22.154853 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8274 11:33:22.158161 CH0 RK1: MR19=303, MR18=220A
8275 11:33:22.165401 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8276 11:33:22.168089 [RxdqsGatingPostProcess] freq 1600
8277 11:33:22.171365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8278 11:33:22.174734 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 11:33:22.178185 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 11:33:22.181474 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 11:33:22.184878 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 11:33:22.188166 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 11:33:22.191577 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 11:33:22.194902 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 11:33:22.198126 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 11:33:22.201318 Pre-setting of DQS Precalculation
8287 11:33:22.204906 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8288 11:33:22.204980 ==
8289 11:33:22.208247 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 11:33:22.211502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 11:33:22.211570 ==
8292 11:33:22.218311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 11:33:22.221027 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 11:33:22.228293 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 11:33:22.231487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 11:33:22.241616 [CA 0] Center 42 (12~72) winsize 61
8297 11:33:22.245082 [CA 1] Center 42 (12~72) winsize 61
8298 11:33:22.248091 [CA 2] Center 38 (9~68) winsize 60
8299 11:33:22.251401 [CA 3] Center 38 (9~67) winsize 59
8300 11:33:22.254459 [CA 4] Center 38 (9~68) winsize 60
8301 11:33:22.258213 [CA 5] Center 37 (8~67) winsize 60
8302 11:33:22.258286
8303 11:33:22.261163 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 11:33:22.261341
8305 11:33:22.264428 [CATrainingPosCal] consider 1 rank data
8306 11:33:22.267811 u2DelayCellTimex100 = 290/100 ps
8307 11:33:22.271159 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8308 11:33:22.278190 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8309 11:33:22.281270 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8310 11:33:22.284483 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8311 11:33:22.288012 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8312 11:33:22.291178 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8313 11:33:22.291247
8314 11:33:22.294569 CA PerBit enable=1, Macro0, CA PI delay=37
8315 11:33:22.294645
8316 11:33:22.297794 [CBTSetCACLKResult] CA Dly = 37
8317 11:33:22.297892 CS Dly: 11 (0~42)
8318 11:33:22.304424 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 11:33:22.308420 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 11:33:22.308494 ==
8321 11:33:22.311683 Dram Type= 6, Freq= 0, CH_1, rank 1
8322 11:33:22.315015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 11:33:22.315091 ==
8324 11:33:22.321178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 11:33:22.324677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 11:33:22.331349 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 11:33:22.334769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 11:33:22.344963 [CA 0] Center 42 (12~72) winsize 61
8329 11:33:22.348311 [CA 1] Center 42 (13~72) winsize 60
8330 11:33:22.351382 [CA 2] Center 39 (10~68) winsize 59
8331 11:33:22.354656 [CA 3] Center 38 (9~68) winsize 60
8332 11:33:22.358353 [CA 4] Center 39 (9~69) winsize 61
8333 11:33:22.361269 [CA 5] Center 37 (8~67) winsize 60
8334 11:33:22.361344
8335 11:33:22.364504 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8336 11:33:22.364580
8337 11:33:22.367854 [CATrainingPosCal] consider 2 rank data
8338 11:33:22.371279 u2DelayCellTimex100 = 290/100 ps
8339 11:33:22.374904 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8340 11:33:22.381586 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8341 11:33:22.384549 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8342 11:33:22.388134 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8343 11:33:22.391866 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8344 11:33:22.394931 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8345 11:33:22.395007
8346 11:33:22.397957 CA PerBit enable=1, Macro0, CA PI delay=37
8347 11:33:22.398070
8348 11:33:22.401166 [CBTSetCACLKResult] CA Dly = 37
8349 11:33:22.404459 CS Dly: 12 (0~45)
8350 11:33:22.408125 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 11:33:22.411184 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 11:33:22.411261
8353 11:33:22.414743 ----->DramcWriteLeveling(PI) begin...
8354 11:33:22.414813 ==
8355 11:33:22.417911 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 11:33:22.421350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 11:33:22.424670 ==
8358 11:33:22.424745 Write leveling (Byte 0): 26 => 26
8359 11:33:22.428142 Write leveling (Byte 1): 28 => 28
8360 11:33:22.430796 DramcWriteLeveling(PI) end<-----
8361 11:33:22.430866
8362 11:33:22.430921 ==
8363 11:33:22.434189 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 11:33:22.441003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 11:33:22.441073 ==
8366 11:33:22.441137 [Gating] SW mode calibration
8367 11:33:22.451070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8368 11:33:22.454593 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8369 11:33:22.458041 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 11:33:22.464759 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 11:33:22.467795 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
8372 11:33:22.471391 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8373 11:33:22.477751 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 11:33:22.480965 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 11:33:22.484289 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 11:33:22.491171 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 11:33:22.494403 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 11:33:22.497556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 11:33:22.504633 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8380 11:33:22.507818 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8381 11:33:22.510865 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8382 11:33:22.517622 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 11:33:22.521323 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 11:33:22.524358 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 11:33:22.531167 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 11:33:22.534504 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 11:33:22.537814 1 6 8 | B1->B0 | 2727 4141 | 0 0 | (0 0) (0 0)
8388 11:33:22.544518 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:33:22.547919 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 11:33:22.551290 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 11:33:22.557961 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 11:33:22.561309 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 11:33:22.564703 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 11:33:22.567983 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 11:33:22.574761 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 11:33:22.577858 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 11:33:22.581042 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:33:22.587973 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:33:22.590945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:33:22.594698 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:33:22.600820 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:33:22.604178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:33:22.607450 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:33:22.614325 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:33:22.617541 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:33:22.620873 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:33:22.627530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:33:22.630873 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:33:22.634293 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 11:33:22.640707 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:33:22.644275 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 11:33:22.647966 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 11:33:22.653964 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 11:33:22.654099 Total UI for P1: 0, mck2ui 16
8415 11:33:22.661162 best dqsien dly found for B0: ( 1, 9, 10)
8416 11:33:22.661237 Total UI for P1: 0, mck2ui 16
8417 11:33:22.664426 best dqsien dly found for B1: ( 1, 9, 10)
8418 11:33:22.670651 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8419 11:33:22.673938 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8420 11:33:22.674021
8421 11:33:22.677509 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8422 11:33:22.680888 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 11:33:22.684591 [Gating] SW calibration Done
8424 11:33:22.684666 ==
8425 11:33:22.687707 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 11:33:22.690931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 11:33:22.691006 ==
8428 11:33:22.694531 RX Vref Scan: 0
8429 11:33:22.694606
8430 11:33:22.694665 RX Vref 0 -> 0, step: 1
8431 11:33:22.694719
8432 11:33:22.697626 RX Delay 0 -> 252, step: 8
8433 11:33:22.700685 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8434 11:33:22.704386 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8435 11:33:22.710931 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8436 11:33:22.714261 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 11:33:22.717480 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8438 11:33:22.720668 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8439 11:33:22.724191 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8440 11:33:22.730994 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8441 11:33:22.734194 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8442 11:33:22.737453 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8443 11:33:22.740828 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8444 11:33:22.744271 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8445 11:33:22.750454 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8446 11:33:22.753643 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8447 11:33:22.757564 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8448 11:33:22.760790 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8449 11:33:22.760865 ==
8450 11:33:22.764306 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 11:33:22.770681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 11:33:22.770757 ==
8453 11:33:22.770815 DQS Delay:
8454 11:33:22.770869 DQS0 = 0, DQS1 = 0
8455 11:33:22.773865 DQM Delay:
8456 11:33:22.773963 DQM0 = 137, DQM1 = 132
8457 11:33:22.777551 DQ Delay:
8458 11:33:22.780901 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8459 11:33:22.784238 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8460 11:33:22.787079 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8461 11:33:22.790439 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8462 11:33:22.790514
8463 11:33:22.790611
8464 11:33:22.790696 ==
8465 11:33:22.793703 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 11:33:22.796992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 11:33:22.800827 ==
8468 11:33:22.800928
8469 11:33:22.800985
8470 11:33:22.801039 TX Vref Scan disable
8471 11:33:22.804164 == TX Byte 0 ==
8472 11:33:22.807251 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 11:33:22.810412 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 11:33:22.814160 == TX Byte 1 ==
8475 11:33:22.817302 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8476 11:33:22.820841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8477 11:33:22.820917 ==
8478 11:33:22.824142 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 11:33:22.830634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 11:33:22.830711 ==
8481 11:33:22.841801
8482 11:33:22.845272 TX Vref early break, caculate TX vref
8483 11:33:22.848754 TX Vref=16, minBit 1, minWin=22, winSum=375
8484 11:33:22.852120 TX Vref=18, minBit 5, minWin=23, winSum=385
8485 11:33:22.855494 TX Vref=20, minBit 0, minWin=23, winSum=395
8486 11:33:22.858923 TX Vref=22, minBit 0, minWin=25, winSum=408
8487 11:33:22.862397 TX Vref=24, minBit 6, minWin=25, winSum=421
8488 11:33:22.868589 TX Vref=26, minBit 1, minWin=25, winSum=426
8489 11:33:22.871787 TX Vref=28, minBit 0, minWin=25, winSum=427
8490 11:33:22.875482 TX Vref=30, minBit 0, minWin=25, winSum=417
8491 11:33:22.878811 TX Vref=32, minBit 10, minWin=24, winSum=412
8492 11:33:22.881959 TX Vref=34, minBit 0, minWin=24, winSum=401
8493 11:33:22.888237 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8494 11:33:22.888337
8495 11:33:22.892152 Final TX Range 0 Vref 28
8496 11:33:22.892252
8497 11:33:22.892340 ==
8498 11:33:22.895289 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 11:33:22.898729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 11:33:22.898805 ==
8501 11:33:22.898863
8502 11:33:22.898916
8503 11:33:22.902066 TX Vref Scan disable
8504 11:33:22.908618 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8505 11:33:22.908694 == TX Byte 0 ==
8506 11:33:22.911735 u2DelayCellOfst[0]=20 cells (6 PI)
8507 11:33:22.915125 u2DelayCellOfst[1]=13 cells (4 PI)
8508 11:33:22.918401 u2DelayCellOfst[2]=0 cells (0 PI)
8509 11:33:22.921534 u2DelayCellOfst[3]=10 cells (3 PI)
8510 11:33:22.925384 u2DelayCellOfst[4]=10 cells (3 PI)
8511 11:33:22.928754 u2DelayCellOfst[5]=20 cells (6 PI)
8512 11:33:22.932131 u2DelayCellOfst[6]=20 cells (6 PI)
8513 11:33:22.934822 u2DelayCellOfst[7]=6 cells (2 PI)
8514 11:33:22.938189 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8515 11:33:22.941547 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 11:33:22.945210 == TX Byte 1 ==
8517 11:33:22.945286 u2DelayCellOfst[8]=0 cells (0 PI)
8518 11:33:22.948449 u2DelayCellOfst[9]=3 cells (1 PI)
8519 11:33:22.951690 u2DelayCellOfst[10]=10 cells (3 PI)
8520 11:33:22.954761 u2DelayCellOfst[11]=3 cells (1 PI)
8521 11:33:22.958303 u2DelayCellOfst[12]=13 cells (4 PI)
8522 11:33:22.961415 u2DelayCellOfst[13]=16 cells (5 PI)
8523 11:33:22.964998 u2DelayCellOfst[14]=16 cells (5 PI)
8524 11:33:22.968312 u2DelayCellOfst[15]=16 cells (5 PI)
8525 11:33:22.971740 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8526 11:33:22.978434 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 11:33:22.978504 DramC Write-DBI on
8528 11:33:22.978559 ==
8529 11:33:22.981869 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 11:33:22.985242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 11:33:22.988271 ==
8532 11:33:22.988365
8533 11:33:22.988455
8534 11:33:22.988542 TX Vref Scan disable
8535 11:33:22.991278 == TX Byte 0 ==
8536 11:33:22.994829 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8537 11:33:22.998163 == TX Byte 1 ==
8538 11:33:23.001450 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8539 11:33:23.004689 DramC Write-DBI off
8540 11:33:23.004760
8541 11:33:23.004822 [DATLAT]
8542 11:33:23.004895 Freq=1600, CH1 RK0
8543 11:33:23.004974
8544 11:33:23.008325 DATLAT Default: 0xf
8545 11:33:23.008416 0, 0xFFFF, sum = 0
8546 11:33:23.011191 1, 0xFFFF, sum = 0
8547 11:33:23.015076 2, 0xFFFF, sum = 0
8548 11:33:23.015148 3, 0xFFFF, sum = 0
8549 11:33:23.017740 4, 0xFFFF, sum = 0
8550 11:33:23.017833 5, 0xFFFF, sum = 0
8551 11:33:23.021458 6, 0xFFFF, sum = 0
8552 11:33:23.021555 7, 0xFFFF, sum = 0
8553 11:33:23.024808 8, 0xFFFF, sum = 0
8554 11:33:23.024885 9, 0xFFFF, sum = 0
8555 11:33:23.028138 10, 0xFFFF, sum = 0
8556 11:33:23.028214 11, 0xFFFF, sum = 0
8557 11:33:23.031251 12, 0xFFFF, sum = 0
8558 11:33:23.031327 13, 0xFFFF, sum = 0
8559 11:33:23.034761 14, 0x0, sum = 1
8560 11:33:23.034837 15, 0x0, sum = 2
8561 11:33:23.038181 16, 0x0, sum = 3
8562 11:33:23.038257 17, 0x0, sum = 4
8563 11:33:23.041675 best_step = 15
8564 11:33:23.041750
8565 11:33:23.041806 ==
8566 11:33:23.045110 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 11:33:23.047805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 11:33:23.047882 ==
8569 11:33:23.047940 RX Vref Scan: 1
8570 11:33:23.051053
8571 11:33:23.051128 Set Vref Range= 24 -> 127
8572 11:33:23.051186
8573 11:33:23.055021 RX Vref 24 -> 127, step: 1
8574 11:33:23.055097
8575 11:33:23.058426 RX Delay 27 -> 252, step: 4
8576 11:33:23.058501
8577 11:33:23.061748 Set Vref, RX VrefLevel [Byte0]: 24
8578 11:33:23.064931 [Byte1]: 24
8579 11:33:23.065006
8580 11:33:23.067951 Set Vref, RX VrefLevel [Byte0]: 25
8581 11:33:23.071605 [Byte1]: 25
8582 11:33:23.071681
8583 11:33:23.075035 Set Vref, RX VrefLevel [Byte0]: 26
8584 11:33:23.077733 [Byte1]: 26
8585 11:33:23.081696
8586 11:33:23.081771 Set Vref, RX VrefLevel [Byte0]: 27
8587 11:33:23.085041 [Byte1]: 27
8588 11:33:23.089068
8589 11:33:23.089142 Set Vref, RX VrefLevel [Byte0]: 28
8590 11:33:23.092435 [Byte1]: 28
8591 11:33:23.097093
8592 11:33:23.097168 Set Vref, RX VrefLevel [Byte0]: 29
8593 11:33:23.100127 [Byte1]: 29
8594 11:33:23.104260
8595 11:33:23.104335 Set Vref, RX VrefLevel [Byte0]: 30
8596 11:33:23.107197 [Byte1]: 30
8597 11:33:23.111721
8598 11:33:23.111817 Set Vref, RX VrefLevel [Byte0]: 31
8599 11:33:23.115009 [Byte1]: 31
8600 11:33:23.119008
8601 11:33:23.119100 Set Vref, RX VrefLevel [Byte0]: 32
8602 11:33:23.122691 [Byte1]: 32
8603 11:33:23.126637
8604 11:33:23.126712 Set Vref, RX VrefLevel [Byte0]: 33
8605 11:33:23.130155 [Byte1]: 33
8606 11:33:23.134301
8607 11:33:23.134377 Set Vref, RX VrefLevel [Byte0]: 34
8608 11:33:23.137994 [Byte1]: 34
8609 11:33:23.142285
8610 11:33:23.142359 Set Vref, RX VrefLevel [Byte0]: 35
8611 11:33:23.145531 [Byte1]: 35
8612 11:33:23.149516
8613 11:33:23.149591 Set Vref, RX VrefLevel [Byte0]: 36
8614 11:33:23.153066 [Byte1]: 36
8615 11:33:23.156978
8616 11:33:23.157057 Set Vref, RX VrefLevel [Byte0]: 37
8617 11:33:23.160162 [Byte1]: 37
8618 11:33:23.164846
8619 11:33:23.164921 Set Vref, RX VrefLevel [Byte0]: 38
8620 11:33:23.168216 [Byte1]: 38
8621 11:33:23.172221
8622 11:33:23.172295 Set Vref, RX VrefLevel [Byte0]: 39
8623 11:33:23.175350 [Byte1]: 39
8624 11:33:23.179822
8625 11:33:23.179898 Set Vref, RX VrefLevel [Byte0]: 40
8626 11:33:23.182729 [Byte1]: 40
8627 11:33:23.187400
8628 11:33:23.187474 Set Vref, RX VrefLevel [Byte0]: 41
8629 11:33:23.190113 [Byte1]: 41
8630 11:33:23.194914
8631 11:33:23.195022 Set Vref, RX VrefLevel [Byte0]: 42
8632 11:33:23.198333 [Byte1]: 42
8633 11:33:23.202408
8634 11:33:23.202483 Set Vref, RX VrefLevel [Byte0]: 43
8635 11:33:23.205802 [Byte1]: 43
8636 11:33:23.209625
8637 11:33:23.209723 Set Vref, RX VrefLevel [Byte0]: 44
8638 11:33:23.212817 [Byte1]: 44
8639 11:33:23.216964
8640 11:33:23.217039 Set Vref, RX VrefLevel [Byte0]: 45
8641 11:33:23.220706 [Byte1]: 45
8642 11:33:23.224679
8643 11:33:23.224753 Set Vref, RX VrefLevel [Byte0]: 46
8644 11:33:23.228064 [Byte1]: 46
8645 11:33:23.232202
8646 11:33:23.232299 Set Vref, RX VrefLevel [Byte0]: 47
8647 11:33:23.235410 [Byte1]: 47
8648 11:33:23.239921
8649 11:33:23.239999 Set Vref, RX VrefLevel [Byte0]: 48
8650 11:33:23.246212 [Byte1]: 48
8651 11:33:23.246287
8652 11:33:23.250237 Set Vref, RX VrefLevel [Byte0]: 49
8653 11:33:23.253225 [Byte1]: 49
8654 11:33:23.253301
8655 11:33:23.256035 Set Vref, RX VrefLevel [Byte0]: 50
8656 11:33:23.259293 [Byte1]: 50
8657 11:33:23.259368
8658 11:33:23.262981 Set Vref, RX VrefLevel [Byte0]: 51
8659 11:33:23.266190 [Byte1]: 51
8660 11:33:23.269922
8661 11:33:23.270057 Set Vref, RX VrefLevel [Byte0]: 52
8662 11:33:23.273461 [Byte1]: 52
8663 11:33:23.277250
8664 11:33:23.277344 Set Vref, RX VrefLevel [Byte0]: 53
8665 11:33:23.280500 [Byte1]: 53
8666 11:33:23.285334
8667 11:33:23.285425 Set Vref, RX VrefLevel [Byte0]: 54
8668 11:33:23.288621 [Byte1]: 54
8669 11:33:23.292803
8670 11:33:23.292897 Set Vref, RX VrefLevel [Byte0]: 55
8671 11:33:23.295696 [Byte1]: 55
8672 11:33:23.300431
8673 11:33:23.300525 Set Vref, RX VrefLevel [Byte0]: 56
8674 11:33:23.303293 [Byte1]: 56
8675 11:33:23.307819
8676 11:33:23.307894 Set Vref, RX VrefLevel [Byte0]: 57
8677 11:33:23.311258 [Byte1]: 57
8678 11:33:23.315251
8679 11:33:23.315323 Set Vref, RX VrefLevel [Byte0]: 58
8680 11:33:23.318710 [Byte1]: 58
8681 11:33:23.322409
8682 11:33:23.322487 Set Vref, RX VrefLevel [Byte0]: 59
8683 11:33:23.325918 [Byte1]: 59
8684 11:33:23.330507
8685 11:33:23.330583 Set Vref, RX VrefLevel [Byte0]: 60
8686 11:33:23.333218 [Byte1]: 60
8687 11:33:23.337926
8688 11:33:23.338060 Set Vref, RX VrefLevel [Byte0]: 61
8689 11:33:23.341243 [Byte1]: 61
8690 11:33:23.345313
8691 11:33:23.345388 Set Vref, RX VrefLevel [Byte0]: 62
8692 11:33:23.348739 [Byte1]: 62
8693 11:33:23.352960
8694 11:33:23.353035 Set Vref, RX VrefLevel [Byte0]: 63
8695 11:33:23.356230 [Byte1]: 63
8696 11:33:23.360169
8697 11:33:23.360244 Set Vref, RX VrefLevel [Byte0]: 64
8698 11:33:23.363869 [Byte1]: 64
8699 11:33:23.367910
8700 11:33:23.367985 Set Vref, RX VrefLevel [Byte0]: 65
8701 11:33:23.371129 [Byte1]: 65
8702 11:33:23.375459
8703 11:33:23.375529 Set Vref, RX VrefLevel [Byte0]: 66
8704 11:33:23.378533 [Byte1]: 66
8705 11:33:23.382614
8706 11:33:23.382682 Set Vref, RX VrefLevel [Byte0]: 67
8707 11:33:23.386143 [Byte1]: 67
8708 11:33:23.390407
8709 11:33:23.390476 Set Vref, RX VrefLevel [Byte0]: 68
8710 11:33:23.393958 [Byte1]: 68
8711 11:33:23.398361
8712 11:33:23.398434 Set Vref, RX VrefLevel [Byte0]: 69
8713 11:33:23.401484 [Byte1]: 69
8714 11:33:23.405794
8715 11:33:23.405868 Set Vref, RX VrefLevel [Byte0]: 70
8716 11:33:23.408676 [Byte1]: 70
8717 11:33:23.413019
8718 11:33:23.413094 Set Vref, RX VrefLevel [Byte0]: 71
8719 11:33:23.416417 [Byte1]: 71
8720 11:33:23.420556
8721 11:33:23.420623 Set Vref, RX VrefLevel [Byte0]: 72
8722 11:33:23.423976 [Byte1]: 72
8723 11:33:23.428018
8724 11:33:23.428095 Set Vref, RX VrefLevel [Byte0]: 73
8725 11:33:23.431343 [Byte1]: 73
8726 11:33:23.435611
8727 11:33:23.435688 Set Vref, RX VrefLevel [Byte0]: 74
8728 11:33:23.438903 [Byte1]: 74
8729 11:33:23.442976
8730 11:33:23.443053 Set Vref, RX VrefLevel [Byte0]: 75
8731 11:33:23.446353 [Byte1]: 75
8732 11:33:23.450523
8733 11:33:23.450640 Set Vref, RX VrefLevel [Byte0]: 76
8734 11:33:23.453886 [Byte1]: 76
8735 11:33:23.457971
8736 11:33:23.458067 Set Vref, RX VrefLevel [Byte0]: 77
8737 11:33:23.461418 [Byte1]: 77
8738 11:33:23.465998
8739 11:33:23.466084 Final RX Vref Byte 0 = 59 to rank0
8740 11:33:23.469190 Final RX Vref Byte 1 = 58 to rank0
8741 11:33:23.472174 Final RX Vref Byte 0 = 59 to rank1
8742 11:33:23.475998 Final RX Vref Byte 1 = 58 to rank1==
8743 11:33:23.479421 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 11:33:23.486179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 11:33:23.486256 ==
8746 11:33:23.486315 DQS Delay:
8747 11:33:23.486369 DQS0 = 0, DQS1 = 0
8748 11:33:23.489193 DQM Delay:
8749 11:33:23.489268 DQM0 = 133, DQM1 = 131
8750 11:33:23.492418 DQ Delay:
8751 11:33:23.495729 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8752 11:33:23.498807 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8753 11:33:23.502439 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8754 11:33:23.505938 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8755 11:33:23.506037
8756 11:33:23.506142
8757 11:33:23.506226
8758 11:33:23.509090 [DramC_TX_OE_Calibration] TA2
8759 11:33:23.512893 Original DQ_B0 (3 6) =30, OEN = 27
8760 11:33:23.515788 Original DQ_B1 (3 6) =30, OEN = 27
8761 11:33:23.519386 24, 0x0, End_B0=24 End_B1=24
8762 11:33:23.519455 25, 0x0, End_B0=25 End_B1=25
8763 11:33:23.522399 26, 0x0, End_B0=26 End_B1=26
8764 11:33:23.525421 27, 0x0, End_B0=27 End_B1=27
8765 11:33:23.528899 28, 0x0, End_B0=28 End_B1=28
8766 11:33:23.528970 29, 0x0, End_B0=29 End_B1=29
8767 11:33:23.532332 30, 0x0, End_B0=30 End_B1=30
8768 11:33:23.535637 31, 0x4141, End_B0=30 End_B1=30
8769 11:33:23.538892 Byte0 end_step=30 best_step=27
8770 11:33:23.542164 Byte1 end_step=30 best_step=27
8771 11:33:23.545800 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 11:33:23.545871 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 11:33:23.549139
8774 11:33:23.549203
8775 11:33:23.555303 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8776 11:33:23.558590 CH1 RK0: MR19=303, MR18=1B28
8777 11:33:23.565454 CH1_RK0: MR19=0x303, MR18=0x1B28, DQSOSC=389, MR23=63, INC=24, DEC=16
8778 11:33:23.565527
8779 11:33:23.568979 ----->DramcWriteLeveling(PI) begin...
8780 11:33:23.569092 ==
8781 11:33:23.572195 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 11:33:23.575692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:33:23.575778 ==
8784 11:33:23.578847 Write leveling (Byte 0): 26 => 26
8785 11:33:23.582175 Write leveling (Byte 1): 30 => 30
8786 11:33:23.585286 DramcWriteLeveling(PI) end<-----
8787 11:33:23.585368
8788 11:33:23.585423 ==
8789 11:33:23.588865 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 11:33:23.592082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 11:33:23.592156 ==
8792 11:33:23.595431 [Gating] SW mode calibration
8793 11:33:23.602120 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 11:33:23.608253 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 11:33:23.611490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 11:33:23.615307 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 11:33:23.622105 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
8798 11:33:23.625230 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8799 11:33:23.628682 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 11:33:23.634947 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 11:33:23.638394 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 11:33:23.642035 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 11:33:23.648158 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 11:33:23.651864 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 11:33:23.655073 1 5 8 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 0)
8806 11:33:23.661869 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 11:33:23.665145 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 11:33:23.668581 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 11:33:23.674843 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 11:33:23.678237 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 11:33:23.681607 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 11:33:23.688404 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8813 11:33:23.691725 1 6 8 | B1->B0 | 4040 2424 | 0 0 | (0 0) (0 0)
8814 11:33:23.694484 1 6 12 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
8815 11:33:23.701830 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 11:33:23.704782 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 11:33:23.708371 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 11:33:23.714988 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 11:33:23.718422 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 11:33:23.721826 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 11:33:23.724702 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 11:33:23.731952 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 11:33:23.735127 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:33:23.738396 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:33:23.745130 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:33:23.748303 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:33:23.751245 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:33:23.758109 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:33:23.761275 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 11:33:23.764649 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 11:33:23.771002 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 11:33:23.774422 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 11:33:23.777791 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 11:33:23.784620 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 11:33:23.787996 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 11:33:23.791409 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 11:33:23.798163 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 11:33:23.801506 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8839 11:33:23.804835 Total UI for P1: 0, mck2ui 16
8840 11:33:23.807616 best dqsien dly found for B1: ( 1, 9, 6)
8841 11:33:23.810916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:33:23.814178 Total UI for P1: 0, mck2ui 16
8843 11:33:23.817538 best dqsien dly found for B0: ( 1, 9, 12)
8844 11:33:23.821043 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8845 11:33:23.824586 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8846 11:33:23.824653
8847 11:33:23.831248 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 11:33:23.834300 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8849 11:33:23.834376 [Gating] SW calibration Done
8850 11:33:23.837516 ==
8851 11:33:23.841005 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 11:33:23.844282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 11:33:23.844355 ==
8854 11:33:23.844413 RX Vref Scan: 0
8855 11:33:23.844466
8856 11:33:23.847387 RX Vref 0 -> 0, step: 1
8857 11:33:23.847455
8858 11:33:23.850980 RX Delay 0 -> 252, step: 8
8859 11:33:23.854251 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8860 11:33:23.857513 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8861 11:33:23.860973 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8862 11:33:23.867379 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8863 11:33:23.870539 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8864 11:33:23.874261 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8865 11:33:23.877530 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8866 11:33:23.880841 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8867 11:33:23.887724 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8868 11:33:23.891222 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8869 11:33:23.894567 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8870 11:33:23.897197 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8871 11:33:23.900655 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8872 11:33:23.907355 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8873 11:33:23.910690 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8874 11:33:23.914038 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8875 11:33:23.914115 ==
8876 11:33:23.917397 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 11:33:23.920672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 11:33:23.923938 ==
8879 11:33:23.924012 DQS Delay:
8880 11:33:23.924070 DQS0 = 0, DQS1 = 0
8881 11:33:23.927377 DQM Delay:
8882 11:33:23.927452 DQM0 = 136, DQM1 = 133
8883 11:33:23.930550 DQ Delay:
8884 11:33:23.933847 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8885 11:33:23.937630 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8886 11:33:23.941004 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8887 11:33:23.944083 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8888 11:33:23.944158
8889 11:33:23.944217
8890 11:33:23.944270 ==
8891 11:33:23.947529 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 11:33:23.950715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 11:33:23.950791 ==
8894 11:33:23.950849
8895 11:33:23.950903
8896 11:33:23.953854 TX Vref Scan disable
8897 11:33:23.957769 == TX Byte 0 ==
8898 11:33:23.960946 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 11:33:23.963956 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 11:33:23.967940 == TX Byte 1 ==
8901 11:33:23.970592 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8902 11:33:23.974640 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8903 11:33:23.974710 ==
8904 11:33:23.977320 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:33:23.980712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:33:23.983936 ==
8907 11:33:23.996539
8908 11:33:23.999629 TX Vref early break, caculate TX vref
8909 11:33:24.003128 TX Vref=16, minBit 0, minWin=22, winSum=381
8910 11:33:24.006206 TX Vref=18, minBit 6, minWin=23, winSum=389
8911 11:33:24.009645 TX Vref=20, minBit 0, minWin=23, winSum=402
8912 11:33:24.012964 TX Vref=22, minBit 0, minWin=23, winSum=406
8913 11:33:24.016339 TX Vref=24, minBit 0, minWin=25, winSum=417
8914 11:33:24.023001 TX Vref=26, minBit 0, minWin=25, winSum=426
8915 11:33:24.026437 TX Vref=28, minBit 0, minWin=26, winSum=425
8916 11:33:24.029948 TX Vref=30, minBit 6, minWin=24, winSum=416
8917 11:33:24.032600 TX Vref=32, minBit 0, minWin=25, winSum=410
8918 11:33:24.035914 TX Vref=34, minBit 6, minWin=24, winSum=405
8919 11:33:24.039849 TX Vref=36, minBit 0, minWin=22, winSum=391
8920 11:33:24.045807 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8921 11:33:24.045883
8922 11:33:24.049233 Final TX Range 0 Vref 28
8923 11:33:24.049299
8924 11:33:24.049356 ==
8925 11:33:24.053207 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 11:33:24.056250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 11:33:24.056322 ==
8928 11:33:24.056403
8929 11:33:24.056486
8930 11:33:24.059410 TX Vref Scan disable
8931 11:33:24.065694 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8932 11:33:24.065768 == TX Byte 0 ==
8933 11:33:24.069415 u2DelayCellOfst[0]=16 cells (5 PI)
8934 11:33:24.072485 u2DelayCellOfst[1]=10 cells (3 PI)
8935 11:33:24.076019 u2DelayCellOfst[2]=0 cells (0 PI)
8936 11:33:24.079111 u2DelayCellOfst[3]=6 cells (2 PI)
8937 11:33:24.082425 u2DelayCellOfst[4]=6 cells (2 PI)
8938 11:33:24.085892 u2DelayCellOfst[5]=16 cells (5 PI)
8939 11:33:24.089124 u2DelayCellOfst[6]=20 cells (6 PI)
8940 11:33:24.092371 u2DelayCellOfst[7]=6 cells (2 PI)
8941 11:33:24.095838 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8942 11:33:24.099332 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8943 11:33:24.102501 == TX Byte 1 ==
8944 11:33:24.105699 u2DelayCellOfst[8]=0 cells (0 PI)
8945 11:33:24.105773 u2DelayCellOfst[9]=3 cells (1 PI)
8946 11:33:24.109289 u2DelayCellOfst[10]=10 cells (3 PI)
8947 11:33:24.112480 u2DelayCellOfst[11]=3 cells (1 PI)
8948 11:33:24.115626 u2DelayCellOfst[12]=13 cells (4 PI)
8949 11:33:24.119172 u2DelayCellOfst[13]=16 cells (5 PI)
8950 11:33:24.122834 u2DelayCellOfst[14]=16 cells (5 PI)
8951 11:33:24.125783 u2DelayCellOfst[15]=16 cells (5 PI)
8952 11:33:24.129111 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8953 11:33:24.135750 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8954 11:33:24.135825 DramC Write-DBI on
8955 11:33:24.135882 ==
8956 11:33:24.139141 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 11:33:24.145864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 11:33:24.145940 ==
8959 11:33:24.145998
8960 11:33:24.146090
8961 11:33:24.146141 TX Vref Scan disable
8962 11:33:24.149445 == TX Byte 0 ==
8963 11:33:24.152898 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8964 11:33:24.156218 == TX Byte 1 ==
8965 11:33:24.159742 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8966 11:33:24.162981 DramC Write-DBI off
8967 11:33:24.163051
8968 11:33:24.163108 [DATLAT]
8969 11:33:24.163161 Freq=1600, CH1 RK1
8970 11:33:24.163216
8971 11:33:24.166252 DATLAT Default: 0xf
8972 11:33:24.166319 0, 0xFFFF, sum = 0
8973 11:33:24.169680 1, 0xFFFF, sum = 0
8974 11:33:24.169748 2, 0xFFFF, sum = 0
8975 11:33:24.172805 3, 0xFFFF, sum = 0
8976 11:33:24.175998 4, 0xFFFF, sum = 0
8977 11:33:24.176069 5, 0xFFFF, sum = 0
8978 11:33:24.179518 6, 0xFFFF, sum = 0
8979 11:33:24.179595 7, 0xFFFF, sum = 0
8980 11:33:24.182635 8, 0xFFFF, sum = 0
8981 11:33:24.182702 9, 0xFFFF, sum = 0
8982 11:33:24.185749 10, 0xFFFF, sum = 0
8983 11:33:24.185814 11, 0xFFFF, sum = 0
8984 11:33:24.189280 12, 0xFFFF, sum = 0
8985 11:33:24.189346 13, 0xFFFF, sum = 0
8986 11:33:24.192774 14, 0x0, sum = 1
8987 11:33:24.192841 15, 0x0, sum = 2
8988 11:33:24.195972 16, 0x0, sum = 3
8989 11:33:24.196046 17, 0x0, sum = 4
8990 11:33:24.199171 best_step = 15
8991 11:33:24.199241
8992 11:33:24.199296 ==
8993 11:33:24.202310 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 11:33:24.205685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 11:33:24.205782 ==
8996 11:33:24.209000 RX Vref Scan: 0
8997 11:33:24.209064
8998 11:33:24.209118 RX Vref 0 -> 0, step: 1
8999 11:33:24.209175
9000 11:33:24.212403 RX Delay 19 -> 252, step: 4
9001 11:33:24.215666 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9002 11:33:24.222866 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9003 11:33:24.226147 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9004 11:33:24.229159 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9005 11:33:24.232648 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9006 11:33:24.236382 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9007 11:33:24.239699 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9008 11:33:24.245874 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9009 11:33:24.249113 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9010 11:33:24.252863 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9011 11:33:24.256206 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9012 11:33:24.258988 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9013 11:33:24.265615 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9014 11:33:24.269057 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9015 11:33:24.272415 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9016 11:33:24.275714 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9017 11:33:24.275793 ==
9018 11:33:24.278918 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 11:33:24.285645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 11:33:24.285721 ==
9021 11:33:24.285779 DQS Delay:
9022 11:33:24.288999 DQS0 = 0, DQS1 = 0
9023 11:33:24.289073 DQM Delay:
9024 11:33:24.292342 DQM0 = 134, DQM1 = 130
9025 11:33:24.292414 DQ Delay:
9026 11:33:24.295479 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9027 11:33:24.298761 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9028 11:33:24.302326 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9029 11:33:24.305850 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9030 11:33:24.305918
9031 11:33:24.305976
9032 11:33:24.306054
9033 11:33:24.308868 [DramC_TX_OE_Calibration] TA2
9034 11:33:24.312435 Original DQ_B0 (3 6) =30, OEN = 27
9035 11:33:24.315629 Original DQ_B1 (3 6) =30, OEN = 27
9036 11:33:24.319159 24, 0x0, End_B0=24 End_B1=24
9037 11:33:24.319233 25, 0x0, End_B0=25 End_B1=25
9038 11:33:24.322269 26, 0x0, End_B0=26 End_B1=26
9039 11:33:24.325776 27, 0x0, End_B0=27 End_B1=27
9040 11:33:24.329137 28, 0x0, End_B0=28 End_B1=28
9041 11:33:24.332576 29, 0x0, End_B0=29 End_B1=29
9042 11:33:24.332652 30, 0x0, End_B0=30 End_B1=30
9043 11:33:24.335834 31, 0x4141, End_B0=30 End_B1=30
9044 11:33:24.339163 Byte0 end_step=30 best_step=27
9045 11:33:24.342308 Byte1 end_step=30 best_step=27
9046 11:33:24.345884 Byte0 TX OE(2T, 0.5T) = (3, 3)
9047 11:33:24.348950 Byte1 TX OE(2T, 0.5T) = (3, 3)
9048 11:33:24.349082
9049 11:33:24.349145
9050 11:33:24.355912 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9051 11:33:24.359100 CH1 RK1: MR19=303, MR18=2309
9052 11:33:24.365863 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9053 11:33:24.368969 [RxdqsGatingPostProcess] freq 1600
9054 11:33:24.372330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9055 11:33:24.375655 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 11:33:24.378807 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 11:33:24.382336 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 11:33:24.385446 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 11:33:24.388856 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 11:33:24.392189 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 11:33:24.395544 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 11:33:24.398964 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 11:33:24.402327 Pre-setting of DQS Precalculation
9064 11:33:24.405734 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9065 11:33:24.412252 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9066 11:33:24.418770 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 11:33:24.421879
9068 11:33:24.421977
9069 11:33:24.422087 [Calibration Summary] 3200 Mbps
9070 11:33:24.425509 CH 0, Rank 0
9071 11:33:24.425601 SW Impedance : PASS
9072 11:33:24.428853 DUTY Scan : NO K
9073 11:33:24.432339 ZQ Calibration : PASS
9074 11:33:24.432428 Jitter Meter : NO K
9075 11:33:24.435277 CBT Training : PASS
9076 11:33:24.438520 Write leveling : PASS
9077 11:33:24.438592 RX DQS gating : PASS
9078 11:33:24.441913 RX DQ/DQS(RDDQC) : PASS
9079 11:33:24.445174 TX DQ/DQS : PASS
9080 11:33:24.445275 RX DATLAT : PASS
9081 11:33:24.448457 RX DQ/DQS(Engine): PASS
9082 11:33:24.451726 TX OE : PASS
9083 11:33:24.451825 All Pass.
9084 11:33:24.451910
9085 11:33:24.451996 CH 0, Rank 1
9086 11:33:24.455091 SW Impedance : PASS
9087 11:33:24.458714 DUTY Scan : NO K
9088 11:33:24.458805 ZQ Calibration : PASS
9089 11:33:24.462339 Jitter Meter : NO K
9090 11:33:24.465085 CBT Training : PASS
9091 11:33:24.465157 Write leveling : PASS
9092 11:33:24.468747 RX DQS gating : PASS
9093 11:33:24.468822 RX DQ/DQS(RDDQC) : PASS
9094 11:33:24.472202 TX DQ/DQS : PASS
9095 11:33:24.475123 RX DATLAT : PASS
9096 11:33:24.475199 RX DQ/DQS(Engine): PASS
9097 11:33:24.478512 TX OE : PASS
9098 11:33:24.478591 All Pass.
9099 11:33:24.478650
9100 11:33:24.481818 CH 1, Rank 0
9101 11:33:24.481894 SW Impedance : PASS
9102 11:33:24.485134 DUTY Scan : NO K
9103 11:33:24.488518 ZQ Calibration : PASS
9104 11:33:24.488592 Jitter Meter : NO K
9105 11:33:24.491633 CBT Training : PASS
9106 11:33:24.495034 Write leveling : PASS
9107 11:33:24.495108 RX DQS gating : PASS
9108 11:33:24.498516 RX DQ/DQS(RDDQC) : PASS
9109 11:33:24.501937 TX DQ/DQS : PASS
9110 11:33:24.502072 RX DATLAT : PASS
9111 11:33:24.505304 RX DQ/DQS(Engine): PASS
9112 11:33:24.508652 TX OE : PASS
9113 11:33:24.508726 All Pass.
9114 11:33:24.508783
9115 11:33:24.508873 CH 1, Rank 1
9116 11:33:24.511371 SW Impedance : PASS
9117 11:33:24.515201 DUTY Scan : NO K
9118 11:33:24.515275 ZQ Calibration : PASS
9119 11:33:24.518461 Jitter Meter : NO K
9120 11:33:24.521855 CBT Training : PASS
9121 11:33:24.521943 Write leveling : PASS
9122 11:33:24.524669 RX DQS gating : PASS
9123 11:33:24.524756 RX DQ/DQS(RDDQC) : PASS
9124 11:33:24.527889 TX DQ/DQS : PASS
9125 11:33:24.531260 RX DATLAT : PASS
9126 11:33:24.531335 RX DQ/DQS(Engine): PASS
9127 11:33:24.534541 TX OE : PASS
9128 11:33:24.534632 All Pass.
9129 11:33:24.534704
9130 11:33:24.538272 DramC Write-DBI on
9131 11:33:24.541288 PER_BANK_REFRESH: Hybrid Mode
9132 11:33:24.541362 TX_TRACKING: ON
9133 11:33:24.551591 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9134 11:33:24.558326 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9135 11:33:24.565139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 11:33:24.571629 [FAST_K] Save calibration result to emmc
9137 11:33:24.571704 sync common calibartion params.
9138 11:33:24.574956 sync cbt_mode0:1, 1:1
9139 11:33:24.578267 dram_init: ddr_geometry: 2
9140 11:33:24.578364 dram_init: ddr_geometry: 2
9141 11:33:24.581349 dram_init: ddr_geometry: 2
9142 11:33:24.584989 0:dram_rank_size:100000000
9143 11:33:24.587930 1:dram_rank_size:100000000
9144 11:33:24.591483 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9145 11:33:24.594583 DFS_SHUFFLE_HW_MODE: ON
9146 11:33:24.598149 dramc_set_vcore_voltage set vcore to 725000
9147 11:33:24.601340 Read voltage for 1600, 0
9148 11:33:24.601406 Vio18 = 0
9149 11:33:24.604482 Vcore = 725000
9150 11:33:24.604560 Vdram = 0
9151 11:33:24.604638 Vddq = 0
9152 11:33:24.604710 Vmddr = 0
9153 11:33:24.607814 switch to 3200 Mbps bootup
9154 11:33:24.611350 [DramcRunTimeConfig]
9155 11:33:24.611428 PHYPLL
9156 11:33:24.611505 DPM_CONTROL_AFTERK: ON
9157 11:33:24.614749 PER_BANK_REFRESH: ON
9158 11:33:24.618103 REFRESH_OVERHEAD_REDUCTION: ON
9159 11:33:24.621457 CMD_PICG_NEW_MODE: OFF
9160 11:33:24.621535 XRTWTW_NEW_MODE: ON
9161 11:33:24.624630 XRTRTR_NEW_MODE: ON
9162 11:33:24.624717 TX_TRACKING: ON
9163 11:33:24.627980 RDSEL_TRACKING: OFF
9164 11:33:24.628055 DQS Precalculation for DVFS: ON
9165 11:33:24.631207 RX_TRACKING: OFF
9166 11:33:24.631275 HW_GATING DBG: ON
9167 11:33:24.634650 ZQCS_ENABLE_LP4: ON
9168 11:33:24.637947 RX_PICG_NEW_MODE: ON
9169 11:33:24.638031 TX_PICG_NEW_MODE: ON
9170 11:33:24.641292 ENABLE_RX_DCM_DPHY: ON
9171 11:33:24.644639 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9172 11:33:24.644714 DUMMY_READ_FOR_TRACKING: OFF
9173 11:33:24.647810 !!! SPM_CONTROL_AFTERK: OFF
9174 11:33:24.650871 !!! SPM could not control APHY
9175 11:33:24.654560 IMPEDANCE_TRACKING: ON
9176 11:33:24.654635 TEMP_SENSOR: ON
9177 11:33:24.657504 HW_SAVE_FOR_SR: OFF
9178 11:33:24.657575 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9179 11:33:24.664635 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9180 11:33:24.664708 Read ODT Tracking: ON
9181 11:33:24.667753 Refresh Rate DeBounce: ON
9182 11:33:24.670887 DFS_NO_QUEUE_FLUSH: ON
9183 11:33:24.670963 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9184 11:33:24.674668 ENABLE_DFS_RUNTIME_MRW: OFF
9185 11:33:24.677988 DDR_RESERVE_NEW_MODE: ON
9186 11:33:24.681401 MR_CBT_SWITCH_FREQ: ON
9187 11:33:24.681473 =========================
9188 11:33:24.700406 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9189 11:33:24.704331 dram_init: ddr_geometry: 2
9190 11:33:24.721899 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9191 11:33:24.725278 dram_init: dram init end (result: 0)
9192 11:33:24.731835 DRAM-K: Full calibration passed in 24428 msecs
9193 11:33:24.735265 MRC: failed to locate region type 0.
9194 11:33:24.735336 DRAM rank0 size:0x100000000,
9195 11:33:24.738671 DRAM rank1 size=0x100000000
9196 11:33:24.748768 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9197 11:33:24.755626 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9198 11:33:24.762116 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9199 11:33:24.768820 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9200 11:33:24.771792 DRAM rank0 size:0x100000000,
9201 11:33:24.775194 DRAM rank1 size=0x100000000
9202 11:33:24.775260 CBMEM:
9203 11:33:24.778272 IMD: root @ 0xfffff000 254 entries.
9204 11:33:24.781981 IMD: root @ 0xffffec00 62 entries.
9205 11:33:24.785009 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9206 11:33:24.788334 WARNING: RO_VPD is uninitialized or empty.
9207 11:33:24.795019 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9208 11:33:24.802262 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9209 11:33:24.814856 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9210 11:33:24.826711 BS: romstage times (exec / console): total (unknown) / 23963 ms
9211 11:33:24.826791
9212 11:33:24.826852
9213 11:33:24.836189 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9214 11:33:24.839903 ARM64: Exception handlers installed.
9215 11:33:24.843194 ARM64: Testing exception
9216 11:33:24.846358 ARM64: Done test exception
9217 11:33:24.846434 Enumerating buses...
9218 11:33:24.849732 Show all devs... Before device enumeration.
9219 11:33:24.853208 Root Device: enabled 1
9220 11:33:24.856720 CPU_CLUSTER: 0: enabled 1
9221 11:33:24.856795 CPU: 00: enabled 1
9222 11:33:24.859978 Compare with tree...
9223 11:33:24.860053 Root Device: enabled 1
9224 11:33:24.862655 CPU_CLUSTER: 0: enabled 1
9225 11:33:24.866065 CPU: 00: enabled 1
9226 11:33:24.866141 Root Device scanning...
9227 11:33:24.869451 scan_static_bus for Root Device
9228 11:33:24.873149 CPU_CLUSTER: 0 enabled
9229 11:33:24.876407 scan_static_bus for Root Device done
9230 11:33:24.879692 scan_bus: bus Root Device finished in 8 msecs
9231 11:33:24.879768 done
9232 11:33:24.886538 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9233 11:33:24.889766 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9234 11:33:24.896183 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9235 11:33:24.899695 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9236 11:33:24.902638 Allocating resources...
9237 11:33:24.902713 Reading resources...
9238 11:33:24.909359 Root Device read_resources bus 0 link: 0
9239 11:33:24.909434 DRAM rank0 size:0x100000000,
9240 11:33:24.913218 DRAM rank1 size=0x100000000
9241 11:33:24.916442 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9242 11:33:24.919697 CPU: 00 missing read_resources
9243 11:33:24.923179 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9244 11:33:24.929304 Root Device read_resources bus 0 link: 0 done
9245 11:33:24.929380 Done reading resources.
9246 11:33:24.936013 Show resources in subtree (Root Device)...After reading.
9247 11:33:24.939289 Root Device child on link 0 CPU_CLUSTER: 0
9248 11:33:24.942760 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 11:33:24.952488 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 11:33:24.952564 CPU: 00
9251 11:33:24.956002 Root Device assign_resources, bus 0 link: 0
9252 11:33:24.959188 CPU_CLUSTER: 0 missing set_resources
9253 11:33:24.962534 Root Device assign_resources, bus 0 link: 0 done
9254 11:33:24.966143 Done setting resources.
9255 11:33:24.972370 Show resources in subtree (Root Device)...After assigning values.
9256 11:33:24.975714 Root Device child on link 0 CPU_CLUSTER: 0
9257 11:33:24.979566 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 11:33:24.989319 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 11:33:24.989398 CPU: 00
9260 11:33:24.992582 Done allocating resources.
9261 11:33:24.995851 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9262 11:33:24.999227 Enabling resources...
9263 11:33:24.999305 done.
9264 11:33:25.005876 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9265 11:33:25.005954 Initializing devices...
9266 11:33:25.008920 Root Device init
9267 11:33:25.009019 init hardware done!
9268 11:33:25.012136 0x00000018: ctrlr->caps
9269 11:33:25.015981 52.000 MHz: ctrlr->f_max
9270 11:33:25.016061 0.400 MHz: ctrlr->f_min
9271 11:33:25.018689 0x40ff8080: ctrlr->voltages
9272 11:33:25.018791 sclk: 390625
9273 11:33:25.021995 Bus Width = 1
9274 11:33:25.022111 sclk: 390625
9275 11:33:25.025217 Bus Width = 1
9276 11:33:25.025294 Early init status = 3
9277 11:33:25.031946 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9278 11:33:25.035275 in-header: 03 fc 00 00 01 00 00 00
9279 11:33:25.035352 in-data: 00
9280 11:33:25.042016 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9281 11:33:25.045341 in-header: 03 fd 00 00 00 00 00 00
9282 11:33:25.048690 in-data:
9283 11:33:25.051982 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 11:33:25.055335 in-header: 03 fc 00 00 01 00 00 00
9285 11:33:25.058653 in-data: 00
9286 11:33:25.061922 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9287 11:33:25.066450 in-header: 03 fd 00 00 00 00 00 00
9288 11:33:25.069605 in-data:
9289 11:33:25.073171 [SSUSB] Setting up USB HOST controller...
9290 11:33:25.076408 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9291 11:33:25.079690 [SSUSB] phy power-on done.
9292 11:33:25.083190 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9293 11:33:25.090136 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9294 11:33:25.093293 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9295 11:33:25.099777 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9296 11:33:25.106525 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9297 11:33:25.112949 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9298 11:33:25.119839 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9299 11:33:25.126357 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9300 11:33:25.129535 SPM: binary array size = 0x9dc
9301 11:33:25.133348 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9302 11:33:25.139566 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9303 11:33:25.146326 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9304 11:33:25.149748 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9305 11:33:25.153157 configure_display: Starting display init
9306 11:33:25.190152 anx7625_power_on_init: Init interface.
9307 11:33:25.193265 anx7625_disable_pd_protocol: Disabled PD feature.
9308 11:33:25.196404 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9309 11:33:25.224326 anx7625_start_dp_work: Secure OCM version=00
9310 11:33:25.227189 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9311 11:33:25.241953 sp_tx_get_edid_block: EDID Block = 1
9312 11:33:25.344860 Extracted contents:
9313 11:33:25.348327 header: 00 ff ff ff ff ff ff 00
9314 11:33:25.351478 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9315 11:33:25.354409 version: 01 04
9316 11:33:25.357729 basic params: 95 1f 11 78 0a
9317 11:33:25.361377 chroma info: 76 90 94 55 54 90 27 21 50 54
9318 11:33:25.365050 established: 00 00 00
9319 11:33:25.371426 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9320 11:33:25.374731 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9321 11:33:25.381378 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 11:33:25.387857 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9323 11:33:25.394660 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9324 11:33:25.397929 extensions: 00
9325 11:33:25.398037 checksum: fb
9326 11:33:25.398097
9327 11:33:25.400753 Manufacturer: IVO Model 57d Serial Number 0
9328 11:33:25.404183 Made week 0 of 2020
9329 11:33:25.404245 EDID version: 1.4
9330 11:33:25.407572 Digital display
9331 11:33:25.410921 6 bits per primary color channel
9332 11:33:25.410988 DisplayPort interface
9333 11:33:25.414304 Maximum image size: 31 cm x 17 cm
9334 11:33:25.417646 Gamma: 220%
9335 11:33:25.417706 Check DPMS levels
9336 11:33:25.420960 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9337 11:33:25.427802 First detailed timing is preferred timing
9338 11:33:25.427872 Established timings supported:
9339 11:33:25.431230 Standard timings supported:
9340 11:33:25.434595 Detailed timings
9341 11:33:25.437882 Hex of detail: 383680a07038204018303c0035ae10000019
9342 11:33:25.441201 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9343 11:33:25.447339 0780 0798 07c8 0820 hborder 0
9344 11:33:25.450805 0438 043b 0447 0458 vborder 0
9345 11:33:25.454374 -hsync -vsync
9346 11:33:25.454441 Did detailed timing
9347 11:33:25.460671 Hex of detail: 000000000000000000000000000000000000
9348 11:33:25.460750 Manufacturer-specified data, tag 0
9349 11:33:25.467646 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9350 11:33:25.467725 ASCII string: InfoVision
9351 11:33:25.474218 Hex of detail: 000000fe00523134304e574635205248200a
9352 11:33:25.477852 ASCII string: R140NWF5 RH
9353 11:33:25.477951 Checksum
9354 11:33:25.478077 Checksum: 0xfb (valid)
9355 11:33:25.484186 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9356 11:33:25.487445 DSI data_rate: 832800000 bps
9357 11:33:25.490632 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9358 11:33:25.497327 anx7625_parse_edid: pixelclock(138800).
9359 11:33:25.500780 hactive(1920), hsync(48), hfp(24), hbp(88)
9360 11:33:25.504102 vactive(1080), vsync(12), vfp(3), vbp(17)
9361 11:33:25.507537 anx7625_dsi_config: config dsi.
9362 11:33:25.514320 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9363 11:33:25.526983 anx7625_dsi_config: success to config DSI
9364 11:33:25.530301 anx7625_dp_start: MIPI phy setup OK.
9365 11:33:25.533458 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9366 11:33:25.536993 mtk_ddp_mode_set invalid vrefresh 60
9367 11:33:25.540187 main_disp_path_setup
9368 11:33:25.540279 ovl_layer_smi_id_en
9369 11:33:25.543494 ovl_layer_smi_id_en
9370 11:33:25.543575 ccorr_config
9371 11:33:25.543640 aal_config
9372 11:33:25.546800 gamma_config
9373 11:33:25.546880 postmask_config
9374 11:33:25.550211 dither_config
9375 11:33:25.553437 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9376 11:33:25.559778 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9377 11:33:25.563060 Root Device init finished in 551 msecs
9378 11:33:25.566793 CPU_CLUSTER: 0 init
9379 11:33:25.572975 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9380 11:33:25.576313 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9381 11:33:25.579754 APU_MBOX 0x190000b0 = 0x10001
9382 11:33:25.582956 APU_MBOX 0x190001b0 = 0x10001
9383 11:33:25.586754 APU_MBOX 0x190005b0 = 0x10001
9384 11:33:25.589853 APU_MBOX 0x190006b0 = 0x10001
9385 11:33:25.592965 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9386 11:33:25.605942 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9387 11:33:25.618840 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9388 11:33:25.624794 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9389 11:33:25.636291 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9390 11:33:25.645514 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9391 11:33:25.649144 CPU_CLUSTER: 0 init finished in 81 msecs
9392 11:33:25.652557 Devices initialized
9393 11:33:25.655830 Show all devs... After init.
9394 11:33:25.655900 Root Device: enabled 1
9395 11:33:25.659225 CPU_CLUSTER: 0: enabled 1
9396 11:33:25.662463 CPU: 00: enabled 1
9397 11:33:25.665757 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9398 11:33:25.669001 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9399 11:33:25.672137 ELOG: NV offset 0x57f000 size 0x1000
9400 11:33:25.678926 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9401 11:33:25.685535 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9402 11:33:25.688978 ELOG: Event(17) added with size 13 at 2024-07-17 11:33:09 UTC
9403 11:33:25.692137 out: cmd=0x121: 03 db 21 01 00 00 00 00
9404 11:33:25.695676 in-header: 03 47 00 00 2c 00 00 00
9405 11:33:25.709104 in-data: f7 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 11:33:25.715822 ELOG: Event(A1) added with size 10 at 2024-07-17 11:33:09 UTC
9407 11:33:25.722576 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9408 11:33:25.728915 ELOG: Event(A0) added with size 9 at 2024-07-17 11:33:10 UTC
9409 11:33:25.732321 elog_add_boot_reason: Logged dev mode boot
9410 11:33:25.735668 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9411 11:33:25.739062 Finalize devices...
9412 11:33:25.739140 Devices finalized
9413 11:33:25.745779 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9414 11:33:25.749086 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9415 11:33:25.752440 in-header: 03 07 00 00 08 00 00 00
9416 11:33:25.755920 in-data: aa e4 47 04 13 02 00 00
9417 11:33:25.758933 Chrome EC: UHEPI supported
9418 11:33:25.765490 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9419 11:33:25.769047 in-header: 03 a9 00 00 08 00 00 00
9420 11:33:25.772174 in-data: 84 60 60 08 00 00 00 00
9421 11:33:25.775985 ELOG: Event(91) added with size 10 at 2024-07-17 11:33:10 UTC
9422 11:33:25.782314 Chrome EC: clear events_b mask to 0x0000000020004000
9423 11:33:25.789174 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9424 11:33:25.792758 in-header: 03 fd 00 00 00 00 00 00
9425 11:33:25.792836 in-data:
9426 11:33:25.799255 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9427 11:33:25.802643 Writing coreboot table at 0xffe64000
9428 11:33:25.805984 0. 000000000010a000-0000000000113fff: RAMSTAGE
9429 11:33:25.809380 1. 0000000040000000-00000000400fffff: RAM
9430 11:33:25.812817 2. 0000000040100000-000000004032afff: RAMSTAGE
9431 11:33:25.816278 3. 000000004032b000-00000000545fffff: RAM
9432 11:33:25.822846 4. 0000000054600000-000000005465ffff: BL31
9433 11:33:25.826022 5. 0000000054660000-00000000ffe63fff: RAM
9434 11:33:25.829155 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9435 11:33:25.835906 7. 0000000100000000-000000023fffffff: RAM
9436 11:33:25.835977 Passing 5 GPIOs to payload:
9437 11:33:25.842956 NAME | PORT | POLARITY | VALUE
9438 11:33:25.845973 EC in RW | 0x000000aa | low | undefined
9439 11:33:25.849380 EC interrupt | 0x00000005 | low | undefined
9440 11:33:25.856119 TPM interrupt | 0x000000ab | high | undefined
9441 11:33:25.859543 SD card detect | 0x00000011 | high | undefined
9442 11:33:25.866263 speaker enable | 0x00000093 | high | undefined
9443 11:33:25.869662 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9444 11:33:25.872823 in-header: 03 f9 00 00 02 00 00 00
9445 11:33:25.872890 in-data: 02 00
9446 11:33:25.876179 ADC[4]: Raw value=904726 ID=7
9447 11:33:25.879610 ADC[3]: Raw value=213441 ID=1
9448 11:33:25.879708 RAM Code: 0x71
9449 11:33:25.882553 ADC[6]: Raw value=75332 ID=0
9450 11:33:25.886045 ADC[5]: Raw value=213072 ID=1
9451 11:33:25.886124 SKU Code: 0x1
9452 11:33:25.892927 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fe3f
9453 11:33:25.895891 coreboot table: 964 bytes.
9454 11:33:25.899645 IMD ROOT 0. 0xfffff000 0x00001000
9455 11:33:25.902809 IMD SMALL 1. 0xffffe000 0x00001000
9456 11:33:25.905791 RO MCACHE 2. 0xffffc000 0x00001104
9457 11:33:25.909613 CONSOLE 3. 0xfff7c000 0x00080000
9458 11:33:25.912298 FMAP 4. 0xfff7b000 0x00000452
9459 11:33:25.915645 TIME STAMP 5. 0xfff7a000 0x00000910
9460 11:33:25.919230 VBOOT WORK 6. 0xfff66000 0x00014000
9461 11:33:25.922614 RAMOOPS 7. 0xffe66000 0x00100000
9462 11:33:25.925817 COREBOOT 8. 0xffe64000 0x00002000
9463 11:33:25.925884 IMD small region:
9464 11:33:25.929209 IMD ROOT 0. 0xffffec00 0x00000400
9465 11:33:25.932533 VPD 1. 0xffffeb80 0x0000006c
9466 11:33:25.935921 MMC STATUS 2. 0xffffeb60 0x00000004
9467 11:33:25.942483 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9468 11:33:25.948665 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9469 11:33:25.987885 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9470 11:33:25.991032 Checking segment from ROM address 0x40100000
9471 11:33:25.994788 Checking segment from ROM address 0x4010001c
9472 11:33:26.001373 Loading segment from ROM address 0x40100000
9473 11:33:26.001442 code (compression=0)
9474 11:33:26.011035 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9475 11:33:26.017625 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9476 11:33:26.017695 it's not compressed!
9477 11:33:26.024192 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9478 11:33:26.030979 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9479 11:33:26.048502 Loading segment from ROM address 0x4010001c
9480 11:33:26.048574 Entry Point 0x80000000
9481 11:33:26.051805 Loaded segments
9482 11:33:26.054679 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9483 11:33:26.061764 Jumping to boot code at 0x80000000(0xffe64000)
9484 11:33:26.068415 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9485 11:33:26.074973 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9486 11:33:26.082737 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9487 11:33:26.086059 Checking segment from ROM address 0x40100000
9488 11:33:26.089369 Checking segment from ROM address 0x4010001c
9489 11:33:26.096032 Loading segment from ROM address 0x40100000
9490 11:33:26.096104 code (compression=1)
9491 11:33:26.102817 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9492 11:33:26.112811 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9493 11:33:26.112883 using LZMA
9494 11:33:26.120982 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9495 11:33:26.127915 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9496 11:33:26.131095 Loading segment from ROM address 0x4010001c
9497 11:33:26.131161 Entry Point 0x54601000
9498 11:33:26.134257 Loaded segments
9499 11:33:26.137684 NOTICE: MT8192 bl31_setup
9500 11:33:26.144475 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9501 11:33:26.147860 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9502 11:33:26.151185 WARNING: region 0:
9503 11:33:26.154590 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 11:33:26.154656 WARNING: region 1:
9505 11:33:26.161289 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9506 11:33:26.164629 WARNING: region 2:
9507 11:33:26.167890 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9508 11:33:26.171330 WARNING: region 3:
9509 11:33:26.174694 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 11:33:26.177860 WARNING: region 4:
9511 11:33:26.184836 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 11:33:26.184914 WARNING: region 5:
9513 11:33:26.188041 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 11:33:26.190891 WARNING: region 6:
9515 11:33:26.194619 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 11:33:26.197743 WARNING: region 7:
9517 11:33:26.200977 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 11:33:26.207621 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9519 11:33:26.210834 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9520 11:33:26.214645 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9521 11:33:26.221299 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9522 11:33:26.224734 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9523 11:33:26.228007 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9524 11:33:26.234369 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9525 11:33:26.238084 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9526 11:33:26.244457 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9527 11:33:26.248186 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9528 11:33:26.251281 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9529 11:33:26.257989 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9530 11:33:26.261347 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9531 11:33:26.264660 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9532 11:33:26.271342 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9533 11:33:26.274015 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9534 11:33:26.280877 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9535 11:33:26.284196 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9536 11:33:26.287993 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9537 11:33:26.294698 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9538 11:33:26.297879 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9539 11:33:26.301147 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9540 11:33:26.307863 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9541 11:33:26.310817 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9542 11:33:26.317824 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9543 11:33:26.320898 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9544 11:33:26.324129 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9545 11:33:26.330922 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9546 11:33:26.334268 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9547 11:33:26.340852 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9548 11:33:26.344228 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9549 11:33:26.347501 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9550 11:33:26.353989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9551 11:33:26.357386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9552 11:33:26.360950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9553 11:33:26.364077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9554 11:33:26.371017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9555 11:33:26.374342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9556 11:33:26.378119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9557 11:33:26.381479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9558 11:33:26.387672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9559 11:33:26.391458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9560 11:33:26.394546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9561 11:33:26.398219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9562 11:33:26.404656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9563 11:33:26.408082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9564 11:33:26.411431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9565 11:33:26.414879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9566 11:33:26.421283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9567 11:33:26.424773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9568 11:33:26.431350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9569 11:33:26.434641 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9570 11:33:26.437679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9571 11:33:26.444840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9572 11:33:26.448630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9573 11:33:26.454478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9574 11:33:26.457903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9575 11:33:26.464305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9576 11:33:26.467742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9577 11:33:26.471678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9578 11:33:26.477782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9579 11:33:26.481566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9580 11:33:26.488339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9581 11:33:26.491060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9582 11:33:26.497663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9583 11:33:26.501538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9584 11:33:26.507673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9585 11:33:26.511456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9586 11:33:26.514841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9587 11:33:26.520967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9588 11:33:26.524350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9589 11:33:26.531017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9590 11:33:26.534266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9591 11:33:26.540858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9592 11:33:26.544871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9593 11:33:26.547715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9594 11:33:26.554265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9595 11:33:26.557759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9596 11:33:26.564288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9597 11:33:26.567647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9598 11:33:26.574859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9599 11:33:26.577521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9600 11:33:26.581368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9601 11:33:26.587573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9602 11:33:26.591330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9603 11:33:26.597525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9604 11:33:26.600948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9605 11:33:26.607646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9606 11:33:26.610916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9607 11:33:26.614116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9608 11:33:26.621148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9609 11:33:26.624563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9610 11:33:26.630894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9611 11:33:26.634267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9612 11:33:26.641041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9613 11:33:26.644229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9614 11:33:26.647362 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9615 11:33:26.654139 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9616 11:33:26.657349 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9617 11:33:26.661174 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9618 11:33:26.664213 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9619 11:33:26.670635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9620 11:33:26.674320 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9621 11:33:26.681360 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9622 11:33:26.684359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9623 11:33:26.687859 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9624 11:33:26.694195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9625 11:33:26.697310 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9626 11:33:26.703929 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9627 11:33:26.707426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9628 11:33:26.710683 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9629 11:33:26.717544 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9630 11:33:26.720789 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9631 11:33:26.727643 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9632 11:33:26.730855 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9633 11:33:26.734160 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9634 11:33:26.737549 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9635 11:33:26.744234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9636 11:33:26.747611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9637 11:33:26.750947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9638 11:33:26.757449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9639 11:33:26.760859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9640 11:33:26.764286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9641 11:33:26.767765 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9642 11:33:26.774673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9643 11:33:26.777568 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9644 11:33:26.784149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9645 11:33:26.787444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9646 11:33:26.791098 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9647 11:33:26.797179 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9648 11:33:26.800849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9649 11:33:26.807511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9650 11:33:26.810481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9651 11:33:26.813941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9652 11:33:26.820781 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9653 11:33:26.824192 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9654 11:33:26.830731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9655 11:33:26.833859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9656 11:33:26.837641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9657 11:33:26.844331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9658 11:33:26.847082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9659 11:33:26.850474 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9660 11:33:26.857683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9661 11:33:26.860503 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9662 11:33:26.867172 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9663 11:33:26.870556 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9664 11:33:26.873896 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9665 11:33:26.880535 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9666 11:33:26.883866 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9667 11:33:26.890313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9668 11:33:26.894230 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9669 11:33:26.897540 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9670 11:33:26.904179 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9671 11:33:26.907415 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9672 11:33:26.910699 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9673 11:33:26.917073 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9674 11:33:26.920161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9675 11:33:26.926808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9676 11:33:26.930344 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9677 11:33:26.933903 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9678 11:33:26.940328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9679 11:33:26.943430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9680 11:33:26.949932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9681 11:33:26.954026 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9682 11:33:26.956688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9683 11:33:26.963375 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9684 11:33:26.966674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9685 11:33:26.973374 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9686 11:33:26.976731 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9687 11:33:26.980196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9688 11:33:26.986969 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9689 11:33:26.990410 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9690 11:33:26.993754 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9691 11:33:27.000167 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9692 11:33:27.003673 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9693 11:33:27.009920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9694 11:33:27.013934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9695 11:33:27.016850 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9696 11:33:27.023483 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9697 11:33:27.026848 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9698 11:33:27.033462 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9699 11:33:27.036856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9700 11:33:27.040072 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9701 11:33:27.046911 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9702 11:33:27.050405 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9703 11:33:27.056827 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9704 11:33:27.060002 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9705 11:33:27.063113 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9706 11:33:27.069755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9707 11:33:27.073166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9708 11:33:27.079973 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9709 11:33:27.083329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9710 11:33:27.086683 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9711 11:33:27.093620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9712 11:33:27.096484 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9713 11:33:27.103500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9714 11:33:27.106735 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9715 11:33:27.109941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9716 11:33:27.116369 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9717 11:33:27.119820 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9718 11:33:27.126788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9719 11:33:27.130165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9720 11:33:27.136679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9721 11:33:27.139718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9722 11:33:27.143537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9723 11:33:27.149552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9724 11:33:27.153099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9725 11:33:27.160224 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9726 11:33:27.163259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9727 11:33:27.166639 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9728 11:33:27.173171 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9729 11:33:27.176644 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9730 11:33:27.182949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9731 11:33:27.186242 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9732 11:33:27.189669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9733 11:33:27.196804 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9734 11:33:27.200210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9735 11:33:27.206856 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9736 11:33:27.210250 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9737 11:33:27.216944 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9738 11:33:27.219594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9739 11:33:27.223026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9740 11:33:27.229630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9741 11:33:27.233598 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9742 11:33:27.240009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9743 11:33:27.243721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9744 11:33:27.246491 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9745 11:33:27.253338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9746 11:33:27.256943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9747 11:33:27.260178 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9748 11:33:27.266837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9749 11:33:27.269609 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9750 11:33:27.273006 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9751 11:33:27.276736 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9752 11:33:27.282937 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9753 11:33:27.286697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9754 11:33:27.290268 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9755 11:33:27.296648 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9756 11:33:27.300102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9757 11:33:27.303249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9758 11:33:27.309848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9759 11:33:27.313277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9760 11:33:27.319842 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9761 11:33:27.323189 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9762 11:33:27.326514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9763 11:33:27.333528 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9764 11:33:27.336395 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9765 11:33:27.339647 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9766 11:33:27.346284 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9767 11:33:27.349585 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9768 11:33:27.353286 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9769 11:33:27.359674 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9770 11:33:27.363570 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9771 11:33:27.366688 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9772 11:33:27.373684 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9773 11:33:27.376381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9774 11:33:27.383132 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9775 11:33:27.386441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9776 11:33:27.389870 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9777 11:33:27.396678 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9778 11:33:27.399984 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9779 11:33:27.403165 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9780 11:33:27.409972 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9781 11:33:27.413258 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9782 11:33:27.416351 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9783 11:33:27.423396 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9784 11:33:27.426263 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9785 11:33:27.433337 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9786 11:33:27.436752 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9787 11:33:27.440229 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9788 11:33:27.443507 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9789 11:33:27.446889 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9790 11:33:27.453765 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9791 11:33:27.456448 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9792 11:33:27.459738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9793 11:33:27.463662 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9794 11:33:27.470389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9795 11:33:27.473334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9796 11:33:27.476483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9797 11:33:27.479589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9798 11:33:27.486950 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9799 11:33:27.490157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9800 11:33:27.493676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9801 11:33:27.499833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9802 11:33:27.503296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9803 11:33:27.509972 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9804 11:33:27.513256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9805 11:33:27.519741 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9806 11:33:27.523299 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9807 11:33:27.526460 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9808 11:33:27.533092 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9809 11:33:27.536629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9810 11:33:27.539934 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9811 11:33:27.546386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9812 11:33:27.549865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9813 11:33:27.556709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9814 11:33:27.560103 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9815 11:33:27.563607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9816 11:33:27.570058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9817 11:33:27.573170 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9818 11:33:27.579916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9819 11:33:27.583163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9820 11:33:27.587043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9821 11:33:27.593471 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9822 11:33:27.596802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9823 11:33:27.603097 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9824 11:33:27.606446 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9825 11:33:27.609961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9826 11:33:27.616808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9827 11:33:27.620295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9828 11:33:27.627021 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9829 11:33:27.629619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9830 11:33:27.636374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9831 11:33:27.639756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9832 11:33:27.642998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9833 11:33:27.650090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9834 11:33:27.653358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9835 11:33:27.659967 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9836 11:33:27.663097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9837 11:33:27.666336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9838 11:33:27.673050 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9839 11:33:27.676284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9840 11:33:27.683210 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9841 11:33:27.686443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9842 11:33:27.689701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9843 11:33:27.696343 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9844 11:33:27.699638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9845 11:33:27.706829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9846 11:33:27.709662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9847 11:33:27.713035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9848 11:33:27.719720 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9849 11:33:27.723019 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9850 11:33:27.729583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9851 11:33:27.733068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9852 11:33:27.736397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9853 11:33:27.743054 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9854 11:33:27.746538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9855 11:33:27.752956 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9856 11:33:27.756433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9857 11:33:27.759851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9858 11:33:27.766732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9859 11:33:27.769965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9860 11:33:27.776372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9861 11:33:27.779903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9862 11:33:27.786283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9863 11:33:27.789774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9864 11:33:27.792963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9865 11:33:27.799501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9866 11:33:27.803129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9867 11:33:27.809371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9868 11:33:27.812874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9869 11:33:27.816276 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9870 11:33:27.822688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9871 11:33:27.826158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9872 11:33:27.832830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9873 11:33:27.836298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9874 11:33:27.839728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9875 11:33:27.846235 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9876 11:33:27.849677 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9877 11:33:27.856189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9878 11:33:27.859393 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9879 11:33:27.866228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9880 11:33:27.869651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9881 11:33:27.873006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9882 11:33:27.879252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9883 11:33:27.882512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9884 11:33:27.889140 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9885 11:33:27.892852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9886 11:33:27.899417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9887 11:33:27.902791 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9888 11:33:27.906161 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9889 11:33:27.912822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9890 11:33:27.915936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9891 11:33:27.922653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9892 11:33:27.925818 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9893 11:33:27.932728 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9894 11:33:27.935843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9895 11:33:27.939211 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9896 11:33:27.945882 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9897 11:33:27.949443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9898 11:33:27.955974 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9899 11:33:27.959296 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9900 11:33:27.965913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9901 11:33:27.969150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9902 11:33:27.972620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9903 11:33:27.979330 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9904 11:33:27.982759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9905 11:33:27.989570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9906 11:33:27.992249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9907 11:33:27.998823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9908 11:33:28.002767 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9909 11:33:28.009348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9910 11:33:28.012635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9911 11:33:28.015925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9912 11:33:28.022526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9913 11:33:28.026002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9914 11:33:28.032261 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9915 11:33:28.036271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9916 11:33:28.039546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9917 11:33:28.046150 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9918 11:33:28.049275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9919 11:33:28.055787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9920 11:33:28.059290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9921 11:33:28.062692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9922 11:33:28.069284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9923 11:33:28.072420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9924 11:33:28.079070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9925 11:33:28.082692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9926 11:33:28.089415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9927 11:33:28.092666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9928 11:33:28.099577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9929 11:33:28.102697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9930 11:33:28.109112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9931 11:33:28.112731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9932 11:33:28.118973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9933 11:33:28.122385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9934 11:33:28.128947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9935 11:33:28.132412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9936 11:33:28.139105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9937 11:33:28.142523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9938 11:33:28.149298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9939 11:33:28.152698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9940 11:33:28.159250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9941 11:33:28.162668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9942 11:33:28.169150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9943 11:33:28.172579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9944 11:33:28.178964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9945 11:33:28.182021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9946 11:33:28.188852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9947 11:33:28.192169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9948 11:33:28.199032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9949 11:33:28.202349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9950 11:33:28.209012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9951 11:33:28.212108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9952 11:33:28.215976 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9953 11:33:28.219492 INFO: [APUAPC] vio 0
9954 11:33:28.221970 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9955 11:33:28.229269 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9956 11:33:28.232664 INFO: [APUAPC] D0_APC_0: 0x400510
9957 11:33:28.235319 INFO: [APUAPC] D0_APC_1: 0x0
9958 11:33:28.239222 INFO: [APUAPC] D0_APC_2: 0x1540
9959 11:33:28.239302 INFO: [APUAPC] D0_APC_3: 0x0
9960 11:33:28.242632 INFO: [APUAPC] D1_APC_0: 0xffffffff
9961 11:33:28.246001 INFO: [APUAPC] D1_APC_1: 0xffffffff
9962 11:33:28.249273 INFO: [APUAPC] D1_APC_2: 0x3fffff
9963 11:33:28.252845 INFO: [APUAPC] D1_APC_3: 0x0
9964 11:33:28.255958 INFO: [APUAPC] D2_APC_0: 0xffffffff
9965 11:33:28.259315 INFO: [APUAPC] D2_APC_1: 0xffffffff
9966 11:33:28.262483 INFO: [APUAPC] D2_APC_2: 0x3fffff
9967 11:33:28.265962 INFO: [APUAPC] D2_APC_3: 0x0
9968 11:33:28.269324 INFO: [APUAPC] D3_APC_0: 0xffffffff
9969 11:33:28.272688 INFO: [APUAPC] D3_APC_1: 0xffffffff
9970 11:33:28.276039 INFO: [APUAPC] D3_APC_2: 0x3fffff
9971 11:33:28.279409 INFO: [APUAPC] D3_APC_3: 0x0
9972 11:33:28.282615 INFO: [APUAPC] D4_APC_0: 0xffffffff
9973 11:33:28.285988 INFO: [APUAPC] D4_APC_1: 0xffffffff
9974 11:33:28.288688 INFO: [APUAPC] D4_APC_2: 0x3fffff
9975 11:33:28.292079 INFO: [APUAPC] D4_APC_3: 0x0
9976 11:33:28.295888 INFO: [APUAPC] D5_APC_0: 0xffffffff
9977 11:33:28.299046 INFO: [APUAPC] D5_APC_1: 0xffffffff
9978 11:33:28.302249 INFO: [APUAPC] D5_APC_2: 0x3fffff
9979 11:33:28.305538 INFO: [APUAPC] D5_APC_3: 0x0
9980 11:33:28.308681 INFO: [APUAPC] D6_APC_0: 0xffffffff
9981 11:33:28.312301 INFO: [APUAPC] D6_APC_1: 0xffffffff
9982 11:33:28.315377 INFO: [APUAPC] D6_APC_2: 0x3fffff
9983 11:33:28.318808 INFO: [APUAPC] D6_APC_3: 0x0
9984 11:33:28.322253 INFO: [APUAPC] D7_APC_0: 0xffffffff
9985 11:33:28.325914 INFO: [APUAPC] D7_APC_1: 0xffffffff
9986 11:33:28.328917 INFO: [APUAPC] D7_APC_2: 0x3fffff
9987 11:33:28.332437 INFO: [APUAPC] D7_APC_3: 0x0
9988 11:33:28.335519 INFO: [APUAPC] D8_APC_0: 0xffffffff
9989 11:33:28.339067 INFO: [APUAPC] D8_APC_1: 0xffffffff
9990 11:33:28.342132 INFO: [APUAPC] D8_APC_2: 0x3fffff
9991 11:33:28.345725 INFO: [APUAPC] D8_APC_3: 0x0
9992 11:33:28.348730 INFO: [APUAPC] D9_APC_0: 0xffffffff
9993 11:33:28.352286 INFO: [APUAPC] D9_APC_1: 0xffffffff
9994 11:33:28.356083 INFO: [APUAPC] D9_APC_2: 0x3fffff
9995 11:33:28.358852 INFO: [APUAPC] D9_APC_3: 0x0
9996 11:33:28.362255 INFO: [APUAPC] D10_APC_0: 0xffffffff
9997 11:33:28.365509 INFO: [APUAPC] D10_APC_1: 0xffffffff
9998 11:33:28.368816 INFO: [APUAPC] D10_APC_2: 0x3fffff
9999 11:33:28.372316 INFO: [APUAPC] D10_APC_3: 0x0
10000 11:33:28.375776 INFO: [APUAPC] D11_APC_0: 0xffffffff
10001 11:33:28.378937 INFO: [APUAPC] D11_APC_1: 0xffffffff
10002 11:33:28.382397 INFO: [APUAPC] D11_APC_2: 0x3fffff
10003 11:33:28.385825 INFO: [APUAPC] D11_APC_3: 0x0
10004 11:33:28.388732 INFO: [APUAPC] D12_APC_0: 0xffffffff
10005 11:33:28.392055 INFO: [APUAPC] D12_APC_1: 0xffffffff
10006 11:33:28.395468 INFO: [APUAPC] D12_APC_2: 0x3fffff
10007 11:33:28.398864 INFO: [APUAPC] D12_APC_3: 0x0
10008 11:33:28.402154 INFO: [APUAPC] D13_APC_0: 0xffffffff
10009 11:33:28.405487 INFO: [APUAPC] D13_APC_1: 0xffffffff
10010 11:33:28.408770 INFO: [APUAPC] D13_APC_2: 0x3fffff
10011 11:33:28.412194 INFO: [APUAPC] D13_APC_3: 0x0
10012 11:33:28.415615 INFO: [APUAPC] D14_APC_0: 0xffffffff
10013 11:33:28.418876 INFO: [APUAPC] D14_APC_1: 0xffffffff
10014 11:33:28.422336 INFO: [APUAPC] D14_APC_2: 0x3fffff
10015 11:33:28.425681 INFO: [APUAPC] D14_APC_3: 0x0
10016 11:33:28.428837 INFO: [APUAPC] D15_APC_0: 0xffffffff
10017 11:33:28.432196 INFO: [APUAPC] D15_APC_1: 0xffffffff
10018 11:33:28.435645 INFO: [APUAPC] D15_APC_2: 0x3fffff
10019 11:33:28.438813 INFO: [APUAPC] D15_APC_3: 0x0
10020 11:33:28.438888 INFO: [APUAPC] APC_CON: 0x4
10021 11:33:28.441931 INFO: [NOCDAPC] D0_APC_0: 0x0
10022 11:33:28.445268 INFO: [NOCDAPC] D0_APC_1: 0x0
10023 11:33:28.448990 INFO: [NOCDAPC] D1_APC_0: 0x0
10024 11:33:28.452186 INFO: [NOCDAPC] D1_APC_1: 0xfff
10025 11:33:28.455386 INFO: [NOCDAPC] D2_APC_0: 0x0
10026 11:33:28.458656 INFO: [NOCDAPC] D2_APC_1: 0xfff
10027 11:33:28.462420 INFO: [NOCDAPC] D3_APC_0: 0x0
10028 11:33:28.465216 INFO: [NOCDAPC] D3_APC_1: 0xfff
10029 11:33:28.468978 INFO: [NOCDAPC] D4_APC_0: 0x0
10030 11:33:28.469176 INFO: [NOCDAPC] D4_APC_1: 0xfff
10031 11:33:28.471997 INFO: [NOCDAPC] D5_APC_0: 0x0
10032 11:33:28.475491 INFO: [NOCDAPC] D5_APC_1: 0xfff
10033 11:33:28.478808 INFO: [NOCDAPC] D6_APC_0: 0x0
10034 11:33:28.481831 INFO: [NOCDAPC] D6_APC_1: 0xfff
10035 11:33:28.485444 INFO: [NOCDAPC] D7_APC_0: 0x0
10036 11:33:28.488850 INFO: [NOCDAPC] D7_APC_1: 0xfff
10037 11:33:28.492237 INFO: [NOCDAPC] D8_APC_0: 0x0
10038 11:33:28.495664 INFO: [NOCDAPC] D8_APC_1: 0xfff
10039 11:33:28.498988 INFO: [NOCDAPC] D9_APC_0: 0x0
10040 11:33:28.502302 INFO: [NOCDAPC] D9_APC_1: 0xfff
10041 11:33:28.502439 INFO: [NOCDAPC] D10_APC_0: 0x0
10042 11:33:28.505000 INFO: [NOCDAPC] D10_APC_1: 0xfff
10043 11:33:28.508487 INFO: [NOCDAPC] D11_APC_0: 0x0
10044 11:33:28.512266 INFO: [NOCDAPC] D11_APC_1: 0xfff
10045 11:33:28.515635 INFO: [NOCDAPC] D12_APC_0: 0x0
10046 11:33:28.518350 INFO: [NOCDAPC] D12_APC_1: 0xfff
10047 11:33:28.521678 INFO: [NOCDAPC] D13_APC_0: 0x0
10048 11:33:28.525114 INFO: [NOCDAPC] D13_APC_1: 0xfff
10049 11:33:28.528331 INFO: [NOCDAPC] D14_APC_0: 0x0
10050 11:33:28.531821 INFO: [NOCDAPC] D14_APC_1: 0xfff
10051 11:33:28.535038 INFO: [NOCDAPC] D15_APC_0: 0x0
10052 11:33:28.538475 INFO: [NOCDAPC] D15_APC_1: 0xfff
10053 11:33:28.541851 INFO: [NOCDAPC] APC_CON: 0x4
10054 11:33:28.545301 INFO: [APUAPC] set_apusys_apc done
10055 11:33:28.548520 INFO: [DEVAPC] devapc_init done
10056 11:33:28.551631 INFO: GICv3 without legacy support detected.
10057 11:33:28.555086 INFO: ARM GICv3 driver initialized in EL3
10058 11:33:28.558553 INFO: Maximum SPI INTID supported: 639
10059 11:33:28.561921 INFO: BL31: Initializing runtime services
10060 11:33:28.568613 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10061 11:33:28.571984 INFO: SPM: enable CPC mode
10062 11:33:28.575293 INFO: mcdi ready for mcusys-off-idle and system suspend
10063 11:33:28.581936 INFO: BL31: Preparing for EL3 exit to normal world
10064 11:33:28.585019 INFO: Entry point address = 0x80000000
10065 11:33:28.585097 INFO: SPSR = 0x8
10066 11:33:28.592703
10067 11:33:28.592779
10068 11:33:28.592837
10069 11:33:28.595931 Starting depthcharge on Spherion...
10070 11:33:28.596009
10071 11:33:28.596072 Wipe memory regions:
10072 11:33:28.596127
10073 11:33:28.596757 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10074 11:33:28.596847 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10075 11:33:28.596923 Setting prompt string to ['asurada:']
10076 11:33:28.596986 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10077 11:33:28.599598 [0x00000040000000, 0x00000054600000)
10078 11:33:28.721803
10079 11:33:28.721917 [0x00000054660000, 0x00000080000000)
10080 11:33:28.982184
10081 11:33:28.982294 [0x000000821a7280, 0x000000ffe64000)
10082 11:33:29.727182
10083 11:33:29.727296 [0x00000100000000, 0x00000240000000)
10084 11:33:31.617395
10085 11:33:31.620529 Initializing XHCI USB controller at 0x11200000.
10086 11:33:32.659045
10087 11:33:32.662339 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10088 11:33:32.662434
10089 11:33:32.662523
10090 11:33:32.662811 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 11:33:32.662895 Sending line: 'tftpboot 192.168.201.1 14864574/tftp-deploy-lg88ucyt/kernel/image.itb 14864574/tftp-deploy-lg88ucyt/kernel/cmdline '
10093 11:33:32.763404 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 11:33:32.763495 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10095 11:33:32.767462 asurada: tftpboot 192.168.201.1 14864574/tftp-deploy-lg88ucyt/kernel/image.ittp-deploy-lg88ucyt/kernel/cmdline
10096 11:33:32.767541
10097 11:33:32.767603 Waiting for link
10098 11:33:32.925928
10099 11:33:32.926064 R8152: Initializing
10100 11:33:32.926125
10101 11:33:32.929267 Version 9 (ocp_data = 6010)
10102 11:33:32.929343
10103 11:33:32.932562 R8152: Done initializing
10104 11:33:32.932654
10105 11:33:32.932757 Adding net device
10106 11:33:34.880087
10107 11:33:34.880247 done.
10108 11:33:34.880339
10109 11:33:34.880408 MAC: 00:e0:4c:78:7a:aa
10110 11:33:34.880474
10111 11:33:34.883853 Sending DHCP discover... done.
10112 11:33:34.883954
10113 11:33:34.887026 Waiting for reply... done.
10114 11:33:34.887127
10115 11:33:34.890172 Sending DHCP request... done.
10116 11:33:34.890283
10117 11:33:34.890370 Waiting for reply... done.
10118 11:33:34.890449
10119 11:33:34.893539 My ip is 192.168.201.12
10120 11:33:34.893660
10121 11:33:34.896977 The DHCP server ip is 192.168.201.1
10122 11:33:34.897101
10123 11:33:34.900269 TFTP server IP predefined by user: 192.168.201.1
10124 11:33:34.900408
10125 11:33:34.907152 Bootfile predefined by user: 14864574/tftp-deploy-lg88ucyt/kernel/image.itb
10126 11:33:34.907310
10127 11:33:34.910292 Sending tftp read request... done.
10128 11:33:34.910475
10129 11:33:34.917310 Waiting for the transfer...
10130 11:33:34.917387
10131 11:33:35.190248 00000000 ################################################################
10132 11:33:35.190355
10133 11:33:35.456516 00080000 ################################################################
10134 11:33:35.456648
10135 11:33:35.719913 00100000 ################################################################
10136 11:33:35.720021
10137 11:33:35.983957 00180000 ################################################################
10138 11:33:35.984090
10139 11:33:36.236364 00200000 ################################################################
10140 11:33:36.236472
10141 11:33:36.492463 00280000 ################################################################
10142 11:33:36.492596
10143 11:33:36.761109 00300000 ################################################################
10144 11:33:36.761244
10145 11:33:37.043185 00380000 ################################################################
10146 11:33:37.043297
10147 11:33:37.328023 00400000 ################################################################
10148 11:33:37.328162
10149 11:33:37.617251 00480000 ################################################################
10150 11:33:37.617361
10151 11:33:37.896515 00500000 ################################################################
10152 11:33:37.896626
10153 11:33:38.188235 00580000 ################################################################
10154 11:33:38.188345
10155 11:33:38.461811 00600000 ################################################################
10156 11:33:38.461941
10157 11:33:38.733462 00680000 ################################################################
10158 11:33:38.733622
10159 11:33:38.991332 00700000 ################################################################
10160 11:33:38.991443
10161 11:33:39.252705 00780000 ################################################################
10162 11:33:39.252820
10163 11:33:39.509771 00800000 ################################################################
10164 11:33:39.509919
10165 11:33:39.772768 00880000 ################################################################
10166 11:33:39.772876
10167 11:33:40.036126 00900000 ################################################################
10168 11:33:40.036262
10169 11:33:40.302889 00980000 ################################################################
10170 11:33:40.302998
10171 11:33:40.568073 00a00000 ################################################################
10172 11:33:40.568181
10173 11:33:40.834309 00a80000 ################################################################
10174 11:33:40.834419
10175 11:33:41.097865 00b00000 ################################################################
10176 11:33:41.097999
10177 11:33:41.439980 00b80000 ################################################################
10178 11:33:41.440096
10179 11:33:41.793599 00c00000 ################################################################
10180 11:33:41.793720
10181 11:33:42.150135 00c80000 ################################################################
10182 11:33:42.150247
10183 11:33:42.476121 00d00000 ################################################################
10184 11:33:42.476231
10185 11:33:42.738764 00d80000 ################################################################
10186 11:33:42.738883
10187 11:33:43.023988 00e00000 ################################################################
10188 11:33:43.024109
10189 11:33:43.312077 00e80000 ################################################################
10190 11:33:43.312202
10191 11:33:43.593747 00f00000 ################################################################
10192 11:33:43.593882
10193 11:33:43.883023 00f80000 ################################################################
10194 11:33:43.883175
10195 11:33:44.181720 01000000 ################################################################
10196 11:33:44.181877
10197 11:33:44.462159 01080000 ################################################################
10198 11:33:44.462267
10199 11:33:44.740416 01100000 ################################################################
10200 11:33:44.740549
10201 11:33:45.018388 01180000 ################################################################
10202 11:33:45.018496
10203 11:33:45.279967 01200000 ################################################################
10204 11:33:45.280110
10205 11:33:45.553616 01280000 ################################################################
10206 11:33:45.553724
10207 11:33:45.810284 01300000 ################################################################
10208 11:33:45.810415
10209 11:33:46.082219 01380000 ################################################################
10210 11:33:46.082375
10211 11:33:46.357142 01400000 ################################################################
10212 11:33:46.357248
10213 11:33:46.640593 01480000 ################################################################
10214 11:33:46.640738
10215 11:33:46.928407 01500000 ################################################################
10216 11:33:46.928549
10217 11:33:47.199455 01580000 ################################################################
10218 11:33:47.199599
10219 11:33:47.494515 01600000 ################################################################
10220 11:33:47.494635
10221 11:33:47.762995 01680000 ################################################################
10222 11:33:47.763108
10223 11:33:48.021092 01700000 ################################################################
10224 11:33:48.021226
10225 11:33:48.276889 01780000 ################################################################
10226 11:33:48.277015
10227 11:33:48.545821 01800000 ################################################################
10228 11:33:48.545959
10229 11:33:48.814270 01880000 ################################################################
10230 11:33:48.814391
10231 11:33:49.092219 01900000 ################################################################
10232 11:33:49.092362
10233 11:33:49.370298 01980000 ################################################################
10234 11:33:49.370416
10235 11:33:49.631013 01a00000 ################################################################
10236 11:33:49.631150
10237 11:33:49.898081 01a80000 ################################################################
10238 11:33:49.898221
10239 11:33:50.186885 01b00000 ################################################################
10240 11:33:50.187008
10241 11:33:50.450219 01b80000 ################################################################
10242 11:33:50.450333
10243 11:33:50.710890 01c00000 ################################################################
10244 11:33:50.711026
10245 11:33:50.974579 01c80000 ################################################################
10246 11:33:50.974686
10247 11:33:51.237798 01d00000 ################################################################
10248 11:33:51.237906
10249 11:33:51.496166 01d80000 ################################################################
10250 11:33:51.496273
10251 11:33:51.706960 01e00000 ##################################################### done.
10252 11:33:51.710283
10253 11:33:51.710363 The bootfile was 31889122 bytes long.
10254 11:33:51.714035
10255 11:33:51.714118 Sending tftp read request... done.
10256 11:33:51.714180
10257 11:33:51.717016 Waiting for the transfer...
10258 11:33:51.717094
10259 11:33:51.720437 00000000 # done.
10260 11:33:51.720524
10261 11:33:51.726998 Command line loaded dynamically from TFTP file: 14864574/tftp-deploy-lg88ucyt/kernel/cmdline
10262 11:33:51.727147
10263 11:33:51.750228 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10264 11:33:51.750363
10265 11:33:51.750423 Loading FIT.
10266 11:33:51.750478
10267 11:33:51.753486 Image ramdisk-1 has 18721543 bytes.
10268 11:33:51.753560
10269 11:33:51.756743 Image fdt-1 has 47258 bytes.
10270 11:33:51.756816
10271 11:33:51.760302 Image kernel-1 has 13118294 bytes.
10272 11:33:51.760376
10273 11:33:51.770252 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10274 11:33:51.770333
10275 11:33:51.786855 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10276 11:33:51.786946
10277 11:33:51.789994 Choosing best match conf-1 for compat google,spherion-rev2.
10278 11:33:51.795653
10279 11:33:51.800331 Connected to device vid:did:rid of 1ae0:0028:00
10280 11:33:51.808439
10281 11:33:51.811601 tpm_get_response: command 0x17b, return code 0x0
10282 11:33:51.811686
10283 11:33:51.814989 ec_init: CrosEC protocol v3 supported (256, 248)
10284 11:33:51.819455
10285 11:33:51.822364 tpm_cleanup: add release locality here.
10286 11:33:51.822487
10287 11:33:51.822571 Shutting down all USB controllers.
10288 11:33:51.825579
10289 11:33:51.825686 Removing current net device
10290 11:33:51.825771
10291 11:33:51.832719 Exiting depthcharge with code 4 at timestamp: 52483075
10292 11:33:51.832919
10293 11:33:51.835562 LZMA decompressing kernel-1 to 0x821a6718
10294 11:33:51.835702
10295 11:33:51.839333 LZMA decompressing kernel-1 to 0x40000000
10296 11:33:53.454398
10297 11:33:53.454525 jumping to kernel
10298 11:33:53.454974 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10299 11:33:53.455066 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10300 11:33:53.455129 Setting prompt string to ['Linux version [0-9]']
10301 11:33:53.455188 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10302 11:33:53.455254 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10303 11:33:53.535809
10304 11:33:53.538920 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10305 11:33:53.542887 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10306 11:33:53.542978 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10307 11:33:53.543044 Setting prompt string to []
10308 11:33:53.543112 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10309 11:33:53.543174 Using line separator: #'\n'#
10310 11:33:53.543225 No login prompt set.
10311 11:33:53.543277 Parsing kernel messages
10312 11:33:53.543325 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10313 11:33:53.543419 [login-action] Waiting for messages, (timeout 00:03:55)
10314 11:33:53.543474 Waiting using forced prompt support (timeout 00:01:58)
10315 11:33:53.562260 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10316 11:33:53.565997 [ 0.000000] random: crng init done
10317 11:33:53.569255 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10318 11:33:53.572653 [ 0.000000] efi: UEFI not found.
10319 11:33:53.582739 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10320 11:33:53.588764 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10321 11:33:53.599070 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10322 11:33:53.609078 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10323 11:33:53.615304 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10324 11:33:53.618751 [ 0.000000] printk: bootconsole [mtk8250] enabled
10325 11:33:53.626811 [ 0.000000] NUMA: No NUMA configuration found
10326 11:33:53.633849 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10327 11:33:53.640191 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10328 11:33:53.640266 [ 0.000000] Zone ranges:
10329 11:33:53.646673 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10330 11:33:53.650162 [ 0.000000] DMA32 empty
10331 11:33:53.656851 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10332 11:33:53.660101 [ 0.000000] Movable zone start for each node
10333 11:33:53.663622 [ 0.000000] Early memory node ranges
10334 11:33:53.669865 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10335 11:33:53.677038 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10336 11:33:53.683655 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10337 11:33:53.690165 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10338 11:33:53.696999 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10339 11:33:53.703374 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10340 11:33:53.760345 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10341 11:33:53.767376 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10342 11:33:53.773804 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10343 11:33:53.777272 [ 0.000000] psci: probing for conduit method from DT.
10344 11:33:53.783726 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10345 11:33:53.787256 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10346 11:33:53.793776 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10347 11:33:53.797086 [ 0.000000] psci: SMC Calling Convention v1.2
10348 11:33:53.803675 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10349 11:33:53.807338 [ 0.000000] Detected VIPT I-cache on CPU0
10350 11:33:53.813954 [ 0.000000] CPU features: detected: GIC system register CPU interface
10351 11:33:53.820267 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10352 11:33:53.827011 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10353 11:33:53.833362 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10354 11:33:53.840139 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10355 11:33:53.847358 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10356 11:33:53.853537 [ 0.000000] alternatives: applying boot alternatives
10357 11:33:53.857209 [ 0.000000] Fallback order for Node 0: 0
10358 11:33:53.863429 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10359 11:33:53.867279 [ 0.000000] Policy zone: Normal
10360 11:33:53.890017 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10361 11:33:53.903632 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10362 11:33:53.913669 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10363 11:33:53.923653 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10364 11:33:53.929912 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10365 11:33:53.933376 <6>[ 0.000000] software IO TLB: area num 8.
10366 11:33:53.990740 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10367 11:33:54.140760 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10368 11:33:54.147145 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10369 11:33:54.153207 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10370 11:33:54.156748 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10371 11:33:54.163452 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10372 11:33:54.169582 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10373 11:33:54.173775 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10374 11:33:54.183159 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10375 11:33:54.189474 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10376 11:33:54.193397 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10377 11:33:54.201396 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10378 11:33:54.204429 <6>[ 0.000000] GICv3: 608 SPIs implemented
10379 11:33:54.211192 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10380 11:33:54.214447 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10381 11:33:54.217421 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10382 11:33:54.227179 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10383 11:33:54.237463 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10384 11:33:54.250818 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10385 11:33:54.257576 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10386 11:33:54.266272 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10387 11:33:54.279413 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10388 11:33:54.286336 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10389 11:33:54.293149 <6>[ 0.009176] Console: colour dummy device 80x25
10390 11:33:54.303162 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10391 11:33:54.309474 <6>[ 0.024338] pid_max: default: 32768 minimum: 301
10392 11:33:54.312743 <6>[ 0.029241] LSM: Security Framework initializing
10393 11:33:54.319852 <6>[ 0.034179] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 11:33:54.329421 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 11:33:54.336137 <6>[ 0.051467] cblist_init_generic: Setting adjustable number of callback queues.
10396 11:33:54.342937 <6>[ 0.058907] cblist_init_generic: Setting shift to 3 and lim to 1.
10397 11:33:54.352715 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10398 11:33:54.356385 <6>[ 0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 11:33:54.363280 <6>[ 0.079076] rcu: Hierarchical SRCU implementation.
10400 11:33:54.369235 <6>[ 0.084122] rcu: Max phase no-delay instances is 1000.
10401 11:33:54.376455 <6>[ 0.091188] EFI services will not be available.
10402 11:33:54.379243 <6>[ 0.096175] smp: Bringing up secondary CPUs ...
10403 11:33:54.387307 <6>[ 0.101229] Detected VIPT I-cache on CPU1
10404 11:33:54.394122 <6>[ 0.101299] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 11:33:54.400343 <6>[ 0.101331] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 11:33:54.403543 <6>[ 0.101674] Detected VIPT I-cache on CPU2
10407 11:33:54.411175 <6>[ 0.101728] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 11:33:54.420853 <6>[ 0.101746] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 11:33:54.423997 <6>[ 0.102008] Detected VIPT I-cache on CPU3
10410 11:33:54.430394 <6>[ 0.102056] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 11:33:54.437317 <6>[ 0.102070] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 11:33:54.440793 <6>[ 0.102377] CPU features: detected: Spectre-v4
10413 11:33:54.447217 <6>[ 0.102384] CPU features: detected: Spectre-BHB
10414 11:33:54.450919 <6>[ 0.102390] Detected PIPT I-cache on CPU4
10415 11:33:54.457235 <6>[ 0.102452] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 11:33:54.464300 <6>[ 0.102469] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 11:33:54.470716 <6>[ 0.102766] Detected PIPT I-cache on CPU5
10418 11:33:54.477801 <6>[ 0.102830] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 11:33:54.484179 <6>[ 0.102846] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 11:33:54.487913 <6>[ 0.103130] Detected PIPT I-cache on CPU6
10421 11:33:54.494447 <6>[ 0.103195] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 11:33:54.501192 <6>[ 0.103211] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 11:33:54.507176 <6>[ 0.103507] Detected PIPT I-cache on CPU7
10424 11:33:54.514537 <6>[ 0.103573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 11:33:54.520723 <6>[ 0.103588] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 11:33:54.524348 <6>[ 0.103636] smp: Brought up 1 node, 8 CPUs
10427 11:33:54.530531 <6>[ 0.245214] SMP: Total of 8 processors activated.
10428 11:33:54.534167 <6>[ 0.250135] CPU features: detected: 32-bit EL0 Support
10429 11:33:54.543414 <6>[ 0.255498] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 11:33:54.550496 <6>[ 0.264298] CPU features: detected: Common not Private translations
10431 11:33:54.553568 <6>[ 0.270775] CPU features: detected: CRC32 instructions
10432 11:33:54.560630 <6>[ 0.276126] CPU features: detected: RCpc load-acquire (LDAPR)
10433 11:33:54.567280 <6>[ 0.282123] CPU features: detected: LSE atomic instructions
10434 11:33:54.573573 <6>[ 0.287904] CPU features: detected: Privileged Access Never
10435 11:33:54.576733 <6>[ 0.293684] CPU features: detected: RAS Extension Support
10436 11:33:54.587084 <6>[ 0.299292] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 11:33:54.590145 <6>[ 0.306562] CPU: All CPU(s) started at EL2
10438 11:33:54.596564 <6>[ 0.310879] alternatives: applying system-wide alternatives
10439 11:33:54.605986 <6>[ 0.321749] devtmpfs: initialized
10440 11:33:54.621144 <6>[ 0.330651] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 11:33:54.628184 <6>[ 0.340613] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 11:33:54.634433 <6>[ 0.348841] pinctrl core: initialized pinctrl subsystem
10443 11:33:54.637682 <6>[ 0.355518] DMI not present or invalid.
10444 11:33:54.644567 <6>[ 0.359934] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 11:33:54.654467 <6>[ 0.366835] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 11:33:54.660904 <6>[ 0.374421] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 11:33:54.671247 <6>[ 0.382635] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 11:33:54.674071 <6>[ 0.390876] audit: initializing netlink subsys (disabled)
10449 11:33:54.684146 <5>[ 0.396573] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10450 11:33:54.691115 <6>[ 0.397285] thermal_sys: Registered thermal governor 'step_wise'
10451 11:33:54.697207 <6>[ 0.404536] thermal_sys: Registered thermal governor 'power_allocator'
10452 11:33:54.700805 <6>[ 0.410792] cpuidle: using governor menu
10453 11:33:54.707806 <6>[ 0.421750] NET: Registered PF_QIPCRTR protocol family
10454 11:33:54.714514 <6>[ 0.427255] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 11:33:54.721180 <6>[ 0.434358] ASID allocator initialised with 32768 entries
10456 11:33:54.724112 <6>[ 0.440938] Serial: AMBA PL011 UART driver
10457 11:33:54.734668 <4>[ 0.450310] Trying to register duplicate clock ID: 134
10458 11:33:54.794664 <6>[ 0.513436] KASLR enabled
10459 11:33:54.808550 <6>[ 0.521056] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 11:33:54.814941 <6>[ 0.528067] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 11:33:54.821547 <6>[ 0.534557] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 11:33:54.828374 <6>[ 0.541559] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 11:33:54.834850 <6>[ 0.548044] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 11:33:54.841295 <6>[ 0.555050] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 11:33:54.848125 <6>[ 0.561539] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 11:33:54.854438 <6>[ 0.568542] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 11:33:54.857986 <6>[ 0.576023] ACPI: Interpreter disabled.
10468 11:33:54.866063 <6>[ 0.582467] iommu: Default domain type: Translated
10469 11:33:54.872976 <6>[ 0.587618] iommu: DMA domain TLB invalidation policy: strict mode
10470 11:33:54.876572 <5>[ 0.594274] SCSI subsystem initialized
10471 11:33:54.883120 <6>[ 0.598525] usbcore: registered new interface driver usbfs
10472 11:33:54.889393 <6>[ 0.604257] usbcore: registered new interface driver hub
10473 11:33:54.892750 <6>[ 0.609810] usbcore: registered new device driver usb
10474 11:33:54.899601 <6>[ 0.615937] pps_core: LinuxPPS API ver. 1 registered
10475 11:33:54.909338 <6>[ 0.621130] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 11:33:54.913108 <6>[ 0.630467] PTP clock support registered
10477 11:33:54.915979 <6>[ 0.634709] EDAC MC: Ver: 3.0.0
10478 11:33:54.923705 <6>[ 0.639915] FPGA manager framework
10479 11:33:54.926917 <6>[ 0.643592] Advanced Linux Sound Architecture Driver Initialized.
10480 11:33:54.930677 <6>[ 0.650396] vgaarb: loaded
10481 11:33:54.937281 <6>[ 0.653565] clocksource: Switched to clocksource arch_sys_counter
10482 11:33:54.944409 <5>[ 0.660012] VFS: Disk quotas dquot_6.6.0
10483 11:33:54.950644 <6>[ 0.664196] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 11:33:54.953811 <6>[ 0.671383] pnp: PnP ACPI: disabled
10485 11:33:54.961948 <6>[ 0.678115] NET: Registered PF_INET protocol family
10486 11:33:54.971692 <6>[ 0.683705] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 11:33:54.982955 <6>[ 0.696012] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 11:33:54.992943 <6>[ 0.704822] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 11:33:54.999608 <6>[ 0.712790] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 11:33:55.006217 <6>[ 0.721493] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 11:33:55.018137 <6>[ 0.731243] TCP: Hash tables configured (established 65536 bind 65536)
10492 11:33:55.024613 <6>[ 0.738113] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 11:33:55.031625 <6>[ 0.745308] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 11:33:55.038478 <6>[ 0.753020] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 11:33:55.044693 <6>[ 0.759165] RPC: Registered named UNIX socket transport module.
10496 11:33:55.048598 <6>[ 0.765321] RPC: Registered udp transport module.
10497 11:33:55.055171 <6>[ 0.770252] RPC: Registered tcp transport module.
10498 11:33:55.062020 <6>[ 0.775185] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 11:33:55.064876 <6>[ 0.781853] PCI: CLS 0 bytes, default 64
10500 11:33:55.068010 <6>[ 0.786212] Unpacking initramfs...
10501 11:33:55.078468 <6>[ 0.789929] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 11:33:55.084985 <6>[ 0.798560] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 11:33:55.091381 <6>[ 0.807363] kvm [1]: IPA Size Limit: 40 bits
10504 11:33:55.095344 <6>[ 0.811889] kvm [1]: GICv3: no GICV resource entry
10505 11:33:55.101467 <6>[ 0.816908] kvm [1]: disabling GICv2 emulation
10506 11:33:55.108126 <6>[ 0.821591] kvm [1]: GIC system register CPU interface enabled
10507 11:33:55.111223 <6>[ 0.827751] kvm [1]: vgic interrupt IRQ18
10508 11:33:55.118305 <6>[ 0.833631] kvm [1]: VHE mode initialized successfully
10509 11:33:55.124926 <5>[ 0.840005] Initialise system trusted keyrings
10510 11:33:55.131407 <6>[ 0.844802] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 11:33:55.138615 <6>[ 0.854744] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 11:33:55.145137 <5>[ 0.861112] NFS: Registering the id_resolver key type
10513 11:33:55.148604 <5>[ 0.866411] Key type id_resolver registered
10514 11:33:55.155021 <5>[ 0.870825] Key type id_legacy registered
10515 11:33:55.161483 <6>[ 0.875106] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 11:33:55.168645 <6>[ 0.882026] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 11:33:55.174975 <6>[ 0.889727] 9p: Installing v9fs 9p2000 file system support
10518 11:33:55.211710 <5>[ 0.927713] Key type asymmetric registered
10519 11:33:55.215601 <5>[ 0.932044] Asymmetric key parser 'x509' registered
10520 11:33:55.224701 <6>[ 0.937177] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 11:33:55.228242 <6>[ 0.944789] io scheduler mq-deadline registered
10522 11:33:55.231618 <6>[ 0.949550] io scheduler kyber registered
10523 11:33:55.250888 <6>[ 0.966608] EINJ: ACPI disabled.
10524 11:33:55.283641 <4>[ 0.993007] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 11:33:55.293456 <4>[ 1.003646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 11:33:55.308430 <6>[ 1.024601] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 11:33:55.316987 <6>[ 1.032728] printk: console [ttyS0] disabled
10528 11:33:55.344673 <6>[ 1.057360] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 11:33:55.351468 <6>[ 1.066833] printk: console [ttyS0] enabled
10530 11:33:55.354563 <6>[ 1.066833] printk: console [ttyS0] enabled
10531 11:33:55.361354 <6>[ 1.075732] printk: bootconsole [mtk8250] disabled
10532 11:33:55.364470 <6>[ 1.075732] printk: bootconsole [mtk8250] disabled
10533 11:33:55.371264 <6>[ 1.086754] SuperH (H)SCI(F) driver initialized
10534 11:33:55.373949 <6>[ 1.092045] msm_serial: driver initialized
10535 11:33:55.387863 <6>[ 1.100982] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10536 11:33:55.398499 <6>[ 1.109527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10537 11:33:55.404429 <6>[ 1.118070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10538 11:33:55.414456 <6>[ 1.126697] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10539 11:33:55.421310 <6>[ 1.135404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10540 11:33:55.431371 <6>[ 1.144116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10541 11:33:55.441156 <6>[ 1.152656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10542 11:33:55.447873 <6>[ 1.161455] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10543 11:33:55.457855 <6>[ 1.169998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10544 11:33:55.468859 <6>[ 1.185501] loop: module loaded
10545 11:33:55.475429 <6>[ 1.191583] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10546 11:33:55.498747 <4>[ 1.215039] mtk-pmic-keys: Failed to locate of_node [id: -1]
10547 11:33:55.506371 <6>[ 1.221825] megasas: 07.719.03.00-rc1
10548 11:33:55.515052 <6>[ 1.231397] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10549 11:33:55.525318 <6>[ 1.240939] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10550 11:33:55.541025 <6>[ 1.257007] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10551 11:33:55.597002 <6>[ 1.306593] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10552 11:33:55.868228 <6>[ 1.584509] Freeing initrd memory: 18280K
10553 11:33:55.879462 <6>[ 1.596011] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10554 11:33:55.890062 <6>[ 1.606724] tun: Universal TUN/TAP device driver, 1.6
10555 11:33:55.893888 <6>[ 1.612774] thunder_xcv, ver 1.0
10556 11:33:55.897065 <6>[ 1.616278] thunder_bgx, ver 1.0
10557 11:33:55.900576 <6>[ 1.619793] nicpf, ver 1.0
10558 11:33:55.910760 <6>[ 1.623812] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10559 11:33:55.913994 <6>[ 1.631289] hns3: Copyright (c) 2017 Huawei Corporation.
10560 11:33:55.917552 <6>[ 1.636882] hclge is initializing
10561 11:33:55.924259 <6>[ 1.640458] e1000: Intel(R) PRO/1000 Network Driver
10562 11:33:55.930859 <6>[ 1.645588] e1000: Copyright (c) 1999-2006 Intel Corporation.
10563 11:33:55.934042 <6>[ 1.651601] e1000e: Intel(R) PRO/1000 Network Driver
10564 11:33:55.941018 <6>[ 1.656817] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10565 11:33:55.947248 <6>[ 1.663003] igb: Intel(R) Gigabit Ethernet Network Driver
10566 11:33:55.954523 <6>[ 1.668653] igb: Copyright (c) 2007-2014 Intel Corporation.
10567 11:33:55.960902 <6>[ 1.674489] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10568 11:33:55.967561 <6>[ 1.681008] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10569 11:33:55.971115 <6>[ 1.687469] sky2: driver version 1.30
10570 11:33:55.977592 <6>[ 1.692401] usbcore: registered new device driver r8152-cfgselector
10571 11:33:55.984580 <6>[ 1.698940] usbcore: registered new interface driver r8152
10572 11:33:55.987915 <6>[ 1.704753] VFIO - User Level meta-driver version: 0.3
10573 11:33:55.997060 <6>[ 1.713004] usbcore: registered new interface driver usb-storage
10574 11:33:56.003241 <6>[ 1.719454] usbcore: registered new device driver onboard-usb-hub
10575 11:33:56.012368 <6>[ 1.728588] mt6397-rtc mt6359-rtc: registered as rtc0
10576 11:33:56.022499 <6>[ 1.734051] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:33:40 UTC (1721216020)
10577 11:33:56.025734 <6>[ 1.743619] i2c_dev: i2c /dev entries driver
10578 11:33:56.039821 <4>[ 1.755775] cpu cpu0: supply cpu not found, using dummy regulator
10579 11:33:56.046573 <4>[ 1.762200] cpu cpu1: supply cpu not found, using dummy regulator
10580 11:33:56.053123 <4>[ 1.768606] cpu cpu2: supply cpu not found, using dummy regulator
10581 11:33:56.060706 <4>[ 1.775010] cpu cpu3: supply cpu not found, using dummy regulator
10582 11:33:56.066577 <4>[ 1.781422] cpu cpu4: supply cpu not found, using dummy regulator
10583 11:33:56.073483 <4>[ 1.787821] cpu cpu5: supply cpu not found, using dummy regulator
10584 11:33:56.079672 <4>[ 1.794217] cpu cpu6: supply cpu not found, using dummy regulator
10585 11:33:56.086667 <4>[ 1.800620] cpu cpu7: supply cpu not found, using dummy regulator
10586 11:33:56.105510 <6>[ 1.821248] cpu cpu0: EM: created perf domain
10587 11:33:56.108504 <6>[ 1.826191] cpu cpu4: EM: created perf domain
10588 11:33:56.115770 <6>[ 1.831781] sdhci: Secure Digital Host Controller Interface driver
10589 11:33:56.122683 <6>[ 1.838211] sdhci: Copyright(c) Pierre Ossman
10590 11:33:56.129514 <6>[ 1.843173] Synopsys Designware Multimedia Card Interface Driver
10591 11:33:56.135849 <6>[ 1.849825] sdhci-pltfm: SDHCI platform and OF driver helper
10592 11:33:56.139094 <6>[ 1.849899] mmc0: CQHCI version 5.10
10593 11:33:56.145606 <6>[ 1.859820] ledtrig-cpu: registered to indicate activity on CPUs
10594 11:33:56.152006 <6>[ 1.866767] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10595 11:33:56.158940 <6>[ 1.873811] usbcore: registered new interface driver usbhid
10596 11:33:56.162135 <6>[ 1.879633] usbhid: USB HID core driver
10597 11:33:56.169132 <6>[ 1.883841] spi_master spi0: will run message pump with realtime priority
10598 11:33:56.214832 <6>[ 1.924170] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10599 11:33:56.233541 <6>[ 1.939484] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10600 11:33:56.237131 <6>[ 1.953050] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10601 11:33:56.244488 <6>[ 1.960170] cros-ec-spi spi0.0: Chrome EC device registered
10602 11:33:56.251365 <6>[ 1.966196] mmc0: Command Queue Engine enabled
10603 11:33:56.257551 <6>[ 1.970952] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10604 11:33:56.260841 <6>[ 1.978815] mmcblk0: mmc0:0001 DA4128 116 GiB
10605 11:33:56.272931 <6>[ 1.988919] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10606 11:33:56.281217 <6>[ 1.996673] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10607 11:33:56.290625 <6>[ 2.000779] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10608 11:33:56.293915 <6>[ 2.002681] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 11:33:56.300514 <6>[ 2.012617] NET: Registered PF_PACKET protocol family
10610 11:33:56.307285 <6>[ 2.017234] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10611 11:33:56.310959 <6>[ 2.021838] 9pnet: Installing 9P2000 support
10612 11:33:56.317375 <5>[ 2.032845] Key type dns_resolver registered
10613 11:33:56.320873 <6>[ 2.037923] registered taskstats version 1
10614 11:33:56.327187 <5>[ 2.042308] Loading compiled-in X.509 certificates
10615 11:33:56.355696 <4>[ 2.064755] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 11:33:56.365418 <4>[ 2.075571] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 11:33:56.380367 <6>[ 2.096387] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 11:33:56.387275 <6>[ 2.103193] xhci-mtk 11200000.usb: xHCI Host Controller
10619 11:33:56.394200 <6>[ 2.108690] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 11:33:56.404164 <6>[ 2.116555] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 11:33:56.410188 <6>[ 2.125986] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 11:33:56.417302 <6>[ 2.132074] xhci-mtk 11200000.usb: xHCI Host Controller
10623 11:33:56.424085 <6>[ 2.137551] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 11:33:56.430333 <6>[ 2.145197] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 11:33:56.437415 <6>[ 2.152985] hub 1-0:1.0: USB hub found
10626 11:33:56.440369 <6>[ 2.157016] hub 1-0:1.0: 1 port detected
10627 11:33:56.447376 <6>[ 2.161306] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 11:33:56.454416 <6>[ 2.170042] hub 2-0:1.0: USB hub found
10629 11:33:56.457378 <6>[ 2.174066] hub 2-0:1.0: 1 port detected
10630 11:33:56.465159 <6>[ 2.181240] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 11:33:56.481938 <6>[ 2.194752] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10632 11:33:56.492241 <6>[ 2.203159] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10633 11:33:56.498695 <6>[ 2.211503] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10634 11:33:56.509012 <6>[ 2.219842] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10635 11:33:56.515442 <6>[ 2.228181] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10636 11:33:56.525417 <6>[ 2.236520] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10637 11:33:56.532125 <6>[ 2.244859] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10638 11:33:56.542296 <6>[ 2.253198] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10639 11:33:56.548274 <6>[ 2.261538] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10640 11:33:56.558287 <6>[ 2.269880] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10641 11:33:56.565083 <6>[ 2.278221] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10642 11:33:56.575190 <6>[ 2.286568] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10643 11:33:56.581505 <6>[ 2.294906] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10644 11:33:56.591598 <6>[ 2.303245] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10645 11:33:56.598533 <6>[ 2.311584] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10646 11:33:56.605494 <6>[ 2.320273] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10647 11:33:56.611960 <6>[ 2.327403] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10648 11:33:56.618445 <6>[ 2.334208] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10649 11:33:56.624821 <6>[ 2.340974] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10650 11:33:56.634994 <6>[ 2.347944] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10651 11:33:56.641894 <6>[ 2.354794] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10652 11:33:56.651231 <6>[ 2.363928] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10653 11:33:56.661602 <6>[ 2.373048] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10654 11:33:56.671598 <6>[ 2.382345] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10655 11:33:56.681304 <6>[ 2.391812] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10656 11:33:56.687891 <6>[ 2.401280] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10657 11:33:56.697895 <6>[ 2.410399] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10658 11:33:56.707578 <6>[ 2.419866] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10659 11:33:56.718099 <6>[ 2.428986] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10660 11:33:56.728044 <6>[ 2.438285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10661 11:33:56.737688 <6>[ 2.448445] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10662 11:33:56.747777 <6>[ 2.460288] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10663 11:33:56.755195 <6>[ 2.471415] Trying to probe devices needed for running init ...
10664 11:33:56.765533 <3>[ 2.478502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10665 11:33:56.869304 <6>[ 2.581854] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10666 11:33:57.023384 <6>[ 2.739575] hub 1-1:1.0: USB hub found
10667 11:33:57.026789 <6>[ 2.743970] hub 1-1:1.0: 4 ports detected
10668 11:33:57.036789 <6>[ 2.752994] hub 1-1:1.0: USB hub found
10669 11:33:57.040083 <6>[ 2.757369] hub 1-1:1.0: 4 ports detected
10670 11:33:57.149477 <6>[ 2.862185] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 11:33:57.175893 <6>[ 2.891851] hub 2-1:1.0: USB hub found
10672 11:33:57.179050 <6>[ 2.896388] hub 2-1:1.0: 3 ports detected
10673 11:33:57.190982 <6>[ 2.907428] hub 2-1:1.0: USB hub found
10674 11:33:57.194443 <6>[ 2.912002] hub 2-1:1.0: 3 ports detected
10675 11:33:57.360823 <6>[ 3.073882] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 11:33:57.493610 <6>[ 3.209685] hub 1-1.4:1.0: USB hub found
10677 11:33:57.497330 <6>[ 3.214348] hub 1-1.4:1.0: 2 ports detected
10678 11:33:57.511743 <6>[ 3.227868] hub 1-1.4:1.0: USB hub found
10679 11:33:57.515736 <6>[ 3.232544] hub 1-1.4:1.0: 2 ports detected
10680 11:33:57.572828 <6>[ 3.286097] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 11:33:57.681855 <6>[ 3.394513] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10682 11:33:57.717399 <4>[ 3.430138] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10683 11:33:57.726951 <4>[ 3.439247] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10684 11:33:57.771140 <6>[ 3.487402] r8152 2-1.3:1.0 eth0: v1.12.13
10685 11:33:57.812918 <6>[ 3.525700] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10686 11:33:58.009088 <6>[ 3.721812] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10687 11:33:59.449473 <6>[ 5.165528] r8152 2-1.3:1.0 eth0: carrier on
10688 11:34:02.308698 <5>[ 5.193653] Sending DHCP requests .., OK
10689 11:34:02.315461 <6>[ 8.030054] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10690 11:34:02.319469 <6>[ 8.038347] IP-Config: Complete:
10691 11:34:02.332109 <6>[ 8.041848] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10692 11:34:02.339189 <6>[ 8.052557] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10693 11:34:02.346312 <6>[ 8.061173] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10694 11:34:02.352474 <6>[ 8.061182] nameserver0=192.168.201.1
10695 11:34:02.356394 <6>[ 8.073334] clk: Disabling unused clocks
10696 11:34:02.358839 <6>[ 8.079088] ALSA device list:
10697 11:34:02.365710 <6>[ 8.082331] No soundcards found.
10698 11:34:02.373284 <6>[ 8.089928] Freeing unused kernel memory: 8512K
10699 11:34:02.376836 <6>[ 8.094859] Run /init as init process
10700 11:34:02.385974 Loading, please wait...
10701 11:34:02.411904 Starting systemd-udevd version 252.22-1~deb12u1
10702 11:34:02.656413 <6>[ 8.369796] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10703 11:34:02.667684 <6>[ 8.380749] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 11:34:02.674422 <6>[ 8.383805] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 11:34:02.684024 <6>[ 8.389170] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10706 11:34:02.690949 <6>[ 8.397539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10707 11:34:02.700488 <6>[ 8.405800] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10708 11:34:02.710874 <4>[ 8.413519] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10709 11:34:02.717419 <3>[ 8.424369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 11:34:02.724021 <6>[ 8.431463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10711 11:34:02.731187 <6>[ 8.432526] mc: Linux media interface: v0.10
10712 11:34:02.737199 <6>[ 8.433808] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10713 11:34:02.743975 <3>[ 8.439703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 11:34:02.754263 <4>[ 8.442263] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10715 11:34:02.760740 <4>[ 8.442853] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10716 11:34:02.766995 <6>[ 8.447170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10717 11:34:02.777006 <6>[ 8.448591] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10718 11:34:02.780613 <6>[ 8.450179] videodev: Linux video capture interface: v2.00
10719 11:34:02.791243 <3>[ 8.452146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:34:02.797726 <6>[ 8.458449] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10721 11:34:02.804726 <6>[ 8.461656] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10722 11:34:02.811174 <6>[ 8.467645] remoteproc remoteproc0: scp is available
10723 11:34:02.817441 <6>[ 8.474719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10724 11:34:02.827650 <6>[ 8.474732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10725 11:34:02.834088 <3>[ 8.478361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 11:34:02.844498 <3>[ 8.478387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 11:34:02.850645 <3>[ 8.478392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 11:34:02.860822 <3>[ 8.478397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 11:34:02.868131 <3>[ 8.478401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 11:34:02.874147 <3>[ 8.478939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 11:34:02.884232 <3>[ 8.479517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 11:34:02.891250 <3>[ 8.479530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 11:34:02.900715 <3>[ 8.479533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 11:34:02.907748 <3>[ 8.479791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:34:02.917495 <3>[ 8.479806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 11:34:02.923989 <3>[ 8.479814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 11:34:02.934392 <3>[ 8.479828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 11:34:02.941203 <3>[ 8.479836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 11:34:02.947498 <3>[ 8.479878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 11:34:02.953946 <6>[ 8.482444] remoteproc remoteproc0: powering up scp
10741 11:34:02.964577 <4>[ 8.487338] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10742 11:34:02.967784 <4>[ 8.487338] Fallback method does not support PEC.
10743 11:34:02.977512 <3>[ 8.513714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10744 11:34:02.984464 <6>[ 8.519409] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10745 11:34:02.990904 <6>[ 8.519431] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10746 11:34:03.000520 <6>[ 8.548690] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10747 11:34:03.007524 <6>[ 8.550950] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10748 11:34:03.017334 <6>[ 8.578442] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10749 11:34:03.027135 <3>[ 8.579184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 11:34:03.030837 <6>[ 8.581764] pci_bus 0000:00: root bus resource [bus 00-ff]
10751 11:34:03.037318 <6>[ 8.581768] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10752 11:34:03.047174 <6>[ 8.581770] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10753 11:34:03.053932 <6>[ 8.581804] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10754 11:34:03.063503 <6>[ 8.590280] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10755 11:34:03.070058 <6>[ 8.597949] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 11:34:03.076627 <6>[ 8.598014] pci 0000:00:00.0: supports D1 D2
10757 11:34:03.083012 <6>[ 8.598016] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10758 11:34:03.089651 <6>[ 8.598984] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10759 11:34:03.097013 <6>[ 8.645688] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10760 11:34:03.106326 <6>[ 8.646582] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10761 11:34:03.113119 <6>[ 8.648166] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 11:34:03.119730 <6>[ 8.648219] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 11:34:03.126426 <6>[ 8.648256] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 11:34:03.133619 <6>[ 8.648273] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 11:34:03.139938 <6>[ 8.648423] pci 0000:01:00.0: supports D1 D2
10766 11:34:03.146450 <6>[ 8.648427] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 11:34:03.152810 <6>[ 8.657673] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10768 11:34:03.159798 <6>[ 8.662723] remoteproc remoteproc0: remote processor scp is now up
10769 11:34:03.162995 <6>[ 8.663389] Bluetooth: Core ver 2.22
10770 11:34:03.169630 <6>[ 8.663505] NET: Registered PF_BLUETOOTH protocol family
10771 11:34:03.176014 <6>[ 8.663509] Bluetooth: HCI device and connection manager initialized
10772 11:34:03.179914 <6>[ 8.663535] Bluetooth: HCI socket layer initialized
10773 11:34:03.186102 <6>[ 8.663542] Bluetooth: L2CAP socket layer initialized
10774 11:34:03.189440 <6>[ 8.663572] Bluetooth: SCO socket layer initialized
10775 11:34:03.199575 <6>[ 8.664723] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10776 11:34:03.205988 <6>[ 8.665178] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10777 11:34:03.219652 <6>[ 8.666198] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10778 11:34:03.226414 <6>[ 8.666472] usbcore: registered new interface driver uvcvideo
10779 11:34:03.232503 <6>[ 8.669055] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10780 11:34:03.239703 <6>[ 8.670877] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10781 11:34:03.245870 <6>[ 8.676630] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10782 11:34:03.255998 <6>[ 8.689580] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10783 11:34:03.262705 <6>[ 8.689594] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10784 11:34:03.269469 <6>[ 8.722175] usbcore: registered new interface driver btusb
10785 11:34:03.278931 <4>[ 8.723126] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10786 11:34:03.285560 <3>[ 8.723135] Bluetooth: hci0: Failed to load firmware file (-2)
10787 11:34:03.291998 <3>[ 8.723140] Bluetooth: hci0: Failed to set up firmware (-2)
10788 11:34:03.302333 <4>[ 8.723144] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10789 11:34:03.309211 <6>[ 8.728600] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10790 11:34:03.318860 <6>[ 9.032099] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10791 11:34:03.322737 <6>[ 9.040235] pci 0000:00:00.0: PCI bridge to [bus 01]
10792 11:34:03.332450 <6>[ 9.045479] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 11:34:03.339263 <6>[ 9.053645] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10794 11:34:03.345631 <6>[ 9.060476] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10795 11:34:03.352613 <6>[ 9.067220] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10796 11:34:03.367409 <5>[ 9.081119] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10797 11:34:03.390775 <5>[ 9.104449] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10798 11:34:03.397279 <5>[ 9.111841] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10799 11:34:03.407399 <4>[ 9.120300] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10800 11:34:03.410921 <6>[ 9.129193] cfg80211: failed to load regulatory.db
10801 11:34:03.461123 <6>[ 9.174217] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 11:34:03.467415 <6>[ 9.181731] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10803 11:34:03.491604 <6>[ 9.208388] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 11:34:03.595602 <6>[ 9.309390] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10805 11:34:03.598712 <6>[ 9.309390]
10806 11:34:03.602027 Begin: Loading essential drivers ... done.
10807 11:34:03.605717 Begin: Running /scripts/init-premount ... done.
10808 11:34:03.612785 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10809 11:34:03.622067 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10810 11:34:03.625746 Device /sys/class/net/eth0 found
10811 11:34:03.626261 done.
10812 11:34:03.644266 Begin: Waiting up to 180 secs for any network device to become available ... done.
10813 11:34:03.689280 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10814 11:34:03.698784 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10815 11:34:03.704947 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 11:34:03.711665 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 11:34:03.718513 host : mt8192-asurada-spherion-r0-cbg-0
10818 11:34:03.724968 domain : lava-rack
10819 11:34:03.728263 rootserver: 192.168.201.1 rootpath:
10820 11:34:03.731207 filename :
10821 11:34:03.802082 done.
10822 11:34:03.808515 Begin: Running /scripts/nfs-bottom ... done.
10823 11:34:03.827940 Begin: Running /scripts/init-bottom ... done.
10824 11:34:03.866427 <6>[ 9.579862] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10825 11:34:05.146248 <6>[ 10.863847] NET: Registered PF_INET6 protocol family
10826 11:34:05.153788 <6>[ 10.871418] Segment Routing with IPv6
10827 11:34:05.157291 <6>[ 10.875439] In-situ OAM (IOAM) with IPv6
10828 11:34:05.323083 <30>[ 11.013860] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10829 11:34:05.329812 <30>[ 11.046987] systemd[1]: Detected architecture arm64.
10830 11:34:05.336503
10831 11:34:05.339801 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10832 11:34:05.339878
10833 11:34:05.361864 <30>[ 11.078868] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10834 11:34:06.355849 <30>[ 12.068866] systemd[1]: Queued start job for default target graphical.target.
10835 11:34:06.397244 <30>[ 12.111208] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10836 11:34:06.404113 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10837 11:34:06.425817 <30>[ 12.139599] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10838 11:34:06.435750 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10839 11:34:06.457852 <30>[ 12.171603] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10840 11:34:06.467757 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10841 11:34:06.489438 <30>[ 12.203198] systemd[1]: Created slice user.slice - User and Session Slice.
10842 11:34:06.496102 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10843 11:34:06.520333 <30>[ 12.230739] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10844 11:34:06.530748 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10845 11:34:06.547642 <30>[ 12.258107] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10846 11:34:06.554088 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10847 11:34:06.582635 <30>[ 12.286499] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10848 11:34:06.592313 <30>[ 12.306449] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10849 11:34:06.599345 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10850 11:34:06.616180 <30>[ 12.330264] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10851 11:34:06.626196 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10852 11:34:06.644032 <30>[ 12.357947] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10853 11:34:06.654535 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10854 11:34:06.669235 <30>[ 12.386402] systemd[1]: Reached target paths.target - Path Units.
10855 11:34:06.675901 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10856 11:34:06.696595 <30>[ 12.410331] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10857 11:34:06.703035 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10858 11:34:06.716947 <30>[ 12.433853] systemd[1]: Reached target slices.target - Slice Units.
10859 11:34:06.727153 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10860 11:34:06.740766 <30>[ 12.457913] systemd[1]: Reached target swap.target - Swaps.
10861 11:34:06.747471 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10862 11:34:06.768900 <30>[ 12.482362] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10863 11:34:06.778288 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10864 11:34:06.797031 <30>[ 12.510837] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10865 11:34:06.807013 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10866 11:34:06.826116 <30>[ 12.539932] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10867 11:34:06.836420 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10868 11:34:06.854379 <30>[ 12.568011] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10869 11:34:06.864178 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10870 11:34:06.880705 <30>[ 12.594490] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10871 11:34:06.886837 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10872 11:34:06.905403 <30>[ 12.619357] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10873 11:34:06.915307 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10874 11:34:06.934576 <30>[ 12.648771] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10875 11:34:06.944855 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10876 11:34:06.960296 <30>[ 12.674345] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10877 11:34:06.970033 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10878 11:34:07.027882 <30>[ 12.742035] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10879 11:34:07.034131 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10880 11:34:07.047423 <30>[ 12.761818] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10881 11:34:07.054316 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10882 11:34:07.076514 <30>[ 12.790739] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10883 11:34:07.082946 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10884 11:34:07.111208 <30>[ 12.818568] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10885 11:34:07.126238 <30>[ 12.840553] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10886 11:34:07.135960 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10887 11:34:07.212806 <30>[ 12.926660] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10888 11:34:07.218939 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10889 11:34:07.245405 <30>[ 12.959417] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10890 11:34:07.251719 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10891 11:34:07.277381 <30>[ 12.991460] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10892 11:34:07.287316 Startin<6>[ 13.000659] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10893 11:34:07.293840 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10894 11:34:07.352177 <30>[ 13.066614] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10895 11:34:07.361994 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10896 11:34:07.385454 <30>[ 13.099540] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10897 11:34:07.391800 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10898 11:34:07.418419 <30>[ 13.131861] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10899 11:34:07.424463 Startin<6>[ 13.141184] fuse: init (API version 7.37)
10900 11:34:07.431385 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10901 11:34:07.457987 <30>[ 13.171713] systemd[1]: Starting systemd-journald.service - Journal Service...
10902 11:34:07.464214 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10903 11:34:07.496790 <30>[ 13.210732] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10904 11:34:07.502741 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10905 11:34:07.533749 <30>[ 13.244619] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10906 11:34:07.540377 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10907 11:34:07.564215 <30>[ 13.278078] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10908 11:34:07.573454 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10909 11:34:07.596061 <30>[ 13.310068] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10910 11:34:07.609332 Starting [0;1;39msyste<3>[ 13.321735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:34:07.612854 md-udev-trig…[0m - Coldplug All udev Devices...
10912 11:34:07.638244 <30>[ 13.351722] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10913 11:34:07.644335 <3>[ 13.353214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 11:34:07.654563 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10915 11:34:07.671972 <30>[ 13.386273] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10916 11:34:07.678325 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10917 11:34:07.694352 <3>[ 13.408633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:34:07.703926 <30>[ 13.417979] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10919 11:34:07.710730 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10920 11:34:07.723784 <3>[ 13.437829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:34:07.733795 <30>[ 13.448001] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10922 11:34:07.743390 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10923 11:34:07.761438 <30>[ 13.475706] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10924 11:34:07.768576 <3>[ 13.483330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:34:07.778069 <30>[ 13.483684] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10926 11:34:07.784900 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10927 11:34:07.805554 <30>[ 13.519184] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10928 11:34:07.811802 <3>[ 13.520102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:34:07.821878 <30>[ 13.527191] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10930 11:34:07.828715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10931 11:34:07.843188 <3>[ 13.557054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 11:34:07.853014 <30>[ 13.567047] systemd[1]: modprobe@drm.service: Deactivated successfully.
10933 11:34:07.859730 <30>[ 13.574946] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10934 11:34:07.873463 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.586428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:34:07.876436 rm.service[0m - Load Kernel Module drm.
10936 11:34:07.897546 <30>[ 13.611508] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10937 11:34:07.907681 <30>[ 13.619860] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10938 11:34:07.917671 [[0;32m OK [0m] Finished [0<3>[ 13.631712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 11:34:07.924359 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10940 11:34:07.942274 <30>[ 13.659062] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10941 11:34:07.952878 <30>[ 13.667013] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10942 11:34:07.962773 [[0;32m OK [<3>[ 13.676005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:34:07.969142 0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10944 11:34:07.990740 <30>[ 13.708034] systemd[1]: modprobe@loop.service: Deactivated successfully.
10945 11:34:08.001965 <30>[ 13.716045] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10946 11:34:08.011587 [[0;32m OK [<3>[ 13.724878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:34:08.021179 <3>[ 13.725590] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10948 11:34:08.037711 0m] Finished [0<4>[ 13.742814] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10949 11:34:08.044977 <3>[ 13.759822] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10950 11:34:08.048989 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10951 11:34:08.058929 <3>[ 13.771970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:34:08.070192 <30>[ 13.784694] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10953 11:34:08.080278 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10954 11:34:08.098319 <3>[ 13.812393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:34:08.111696 <30>[ 13.822384] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10956 11:34:08.118116 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10957 11:34:08.138177 <3>[ 13.852638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 11:34:08.148852 <30>[ 13.862992] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10959 11:34:08.158917 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10960 11:34:08.176001 <30>[ 13.890253] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10961 11:34:08.183211 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10962 11:34:08.205395 <30>[ 13.919355] systemd[1]: Reached target network-pre.target - Preparation for Network.
10963 11:34:08.211797 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10964 11:34:08.260545 <30>[ 13.974271] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10965 11:34:08.266266 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10966 11:34:08.292607 <30>[ 14.006966] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10967 11:34:08.298849 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10968 11:34:08.323057 <30>[ 14.034019] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10969 11:34:08.339680 <30>[ 14.047701] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10970 11:34:08.376269 <30>[ 14.090667] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10971 11:34:08.382465 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10972 11:34:08.409956 <30>[ 14.120842] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10973 11:34:08.424122 <30>[ 14.138438] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10974 11:34:08.431077 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10975 11:34:08.459245 <30>[ 14.173130] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10976 11:34:08.465912 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10977 11:34:08.495585 <30>[ 14.210132] systemd[1]: Started systemd-journald.service - Journal Service.
10978 11:34:08.502102 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10979 11:34:08.525388 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10980 11:34:08.545088 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10981 11:34:08.565248 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10982 11:34:08.585699 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10983 11:34:08.604945 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10984 11:34:08.657095 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10985 11:34:08.680205 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10986 11:34:08.714443 <46>[ 14.428994] systemd-journald[311]: Received client request to flush runtime journal.
10987 11:34:09.219270 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10988 11:34:09.236163 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10989 11:34:09.256176 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10990 11:34:09.516571 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10991 11:34:10.138781 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10992 11:34:10.188138 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10993 11:34:10.237202 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10994 11:34:10.289697 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10995 11:34:10.382907 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10996 11:34:10.656740 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10997 11:34:10.682160 <6>[ 16.399868] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10998 11:34:10.700016 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10999 11:34:10.734734 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11000 11:34:10.840861 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11001 11:34:10.860807 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11002 11:34:10.912676 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11003 11:34:10.936315 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11004 11:34:10.968964 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11005 11:34:11.000627 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11006 11:34:11.076896 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11007 11:34:11.104167 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11008 11:34:11.124242 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11009 11:34:11.153356 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11010 11:34:11.256738 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11011 11:34:11.275570 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11012 11:34:11.291983 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11013 11:34:11.307491 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11014 11:34:11.330880 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11015 11:34:11.350792 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11016 11:34:11.367482 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11017 11:34:11.387043 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11018 11:34:11.407331 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11019 11:34:11.423616 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11020 11:34:11.441662 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11021 11:34:11.459851 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11022 11:34:11.466136 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11023 11:34:11.504915 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11024 11:34:11.539232 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11025 11:34:11.636150 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11026 11:34:11.665627 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11027 11:34:11.797127 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11028 11:34:11.857091 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11029 11:34:11.882048 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11030 11:34:11.899980 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11031 11:34:11.929191 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11032 11:34:11.949418 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11033 11:34:11.981750 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11034 11:34:12.002133 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11035 11:34:12.020546 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11036 11:34:12.081438 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11037 11:34:12.121795 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11038 11:34:12.232567
11039 11:34:12.235488 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11040 11:34:12.236015
11041 11:34:12.239009 debian-bookworm-arm64 login: root (automatic login)
11042 11:34:12.239403
11043 11:34:12.538490 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11044 11:34:12.538663
11045 11:34:12.545309 The programs included with the Debian GNU/Linux system are free software;
11046 11:34:12.551856 the exact distribution terms for each program are described in the
11047 11:34:12.555655 individual files in /usr/share/doc/*/copyright.
11048 11:34:12.555933
11049 11:34:12.562110 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11050 11:34:12.565283 permitted by applicable law.
11051 11:34:13.580096 Matched prompt #10: / #
11053 11:34:13.580317 Setting prompt string to ['/ #']
11054 11:34:13.580402 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11056 11:34:13.580572 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11057 11:34:13.580685 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11058 11:34:13.580744 Setting prompt string to ['/ #']
11059 11:34:13.580796 Forcing a shell prompt, looking for ['/ #']
11060 11:34:13.580850 Sending line: ''
11062 11:34:13.631235 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11063 11:34:13.631316 Waiting using forced prompt support (timeout 00:02:30)
11064 11:34:13.636984 / #
11065 11:34:13.637372 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11066 11:34:13.637510 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11067 11:34:13.637610 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp'"
11069 11:34:13.744526 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864574/extract-nfsrootfs-enihzkjp'
11070 11:34:13.745179 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11072 11:34:13.852884 / # export NFS_SERVER_IP='192.168.201.1'
11073 11:34:13.853722 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11074 11:34:13.854273 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11075 11:34:13.854738 end: 2 depthcharge-action (duration 00:01:25) [common]
11076 11:34:13.855355 start: 3 lava-test-retry (timeout 00:07:41) [common]
11077 11:34:13.855977 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11078 11:34:13.856488 Using namespace: common
11079 11:34:13.857002 Sending line: '#'
11081 11:34:13.958392 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11082 11:34:13.964246 / # #
11083 11:34:13.964886 Using /lava-14864574
11084 11:34:13.965195 Sending line: 'export SHELL=/bin/bash'
11086 11:34:14.072204 / # export SHELL=/bin/bash
11087 11:34:14.072803 Sending line: '. /lava-14864574/environment'
11089 11:34:14.179965 / # . /lava-14864574/environment
11090 11:34:14.186075 Sending line: '/lava-14864574/bin/lava-test-runner /lava-14864574/0'
11092 11:34:14.287406 Test shell timeout: 10s (minimum of the action and connection timeout)
11093 11:34:14.292945 / # /lava-14864574/bin/lava-test-runner /lava-14864574/0
11094 11:34:14.550738 + export TESTRUN_ID=0_timesync-off
11095 11:34:14.554049 + TESTRUN_ID=0_timesync-off
11096 11:34:14.557325 + cd /lava-14864574/0/tests/0_timesync-off
11097 11:34:14.560694 ++ cat uuid
11098 11:34:14.566609 + UUID=14864574_1.6.2.3.1
11099 11:34:14.566958 + set +x
11100 11:34:14.573422 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864574_1.6.2.3.1>
11101 11:34:14.574148 Received signal: <STARTRUN> 0_timesync-off 14864574_1.6.2.3.1
11102 11:34:14.574501 Starting test lava.0_timesync-off (14864574_1.6.2.3.1)
11103 11:34:14.575008 Skipping test definition patterns.
11104 11:34:14.576496 + systemctl stop systemd-timesyncd
11105 11:34:14.662061 + set +x
11106 11:34:14.665141 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864574_1.6.2.3.1>
11107 11:34:14.665766 Received signal: <ENDRUN> 0_timesync-off 14864574_1.6.2.3.1
11108 11:34:14.666271 Ending use of test pattern.
11109 11:34:14.666649 Ending test lava.0_timesync-off (14864574_1.6.2.3.1), duration 0.09
11111 11:34:14.741536 + export TESTRUN_ID=1_kselftest-arm64
11112 11:34:14.741970 + TESTRUN_ID=1_kselftest-arm64
11113 11:34:14.748338 + cd /lava-14864574/0/tests/1_kselftest-arm64
11114 11:34:14.748703 ++ cat uuid
11115 11:34:14.753331 + UUID=14864574_1.6.2.3.5
11116 11:34:14.753701 + set +x
11117 11:34:14.759738 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14864574_1.6.2.3.5>
11118 11:34:14.760325 Received signal: <STARTRUN> 1_kselftest-arm64 14864574_1.6.2.3.5
11119 11:34:14.760673 Starting test lava.1_kselftest-arm64 (14864574_1.6.2.3.5)
11120 11:34:14.761106 Skipping test definition patterns.
11121 11:34:14.763163 + cd ./automated/linux/kselftest/
11122 11:34:14.792599 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11123 11:34:14.831998 INFO: install_deps skipped
11124 11:34:15.341698 --2024-07-17 11:33:59-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11125 11:34:15.348016 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11126 11:34:15.475002 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11127 11:34:15.607543 HTTP request sent, awaiting response... 200 OK
11128 11:34:15.610811 Length: 1920476 (1.8M) [application/octet-stream]
11129 11:34:15.614155 Saving to: 'kselftest_armhf.tar.gz'
11130 11:34:15.614652
11131 11:34:15.614980
11132 11:34:15.868676 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11133 11:34:16.131976 kselftest_armhf.tar 2%[ ] 47.81K 183KB/s
11134 11:34:16.576714 kselftest_armhf.tar 11%[=> ] 216.08K 413KB/s
11135 11:34:16.662090 kselftest_armhf.tar 43%[=======> ] 817.06K 844KB/s
11136 11:34:16.668512 kselftest_armhf.tar 100%[===================>] 1.83M 1.74MB/s in 1.1s
11137 11:34:16.668977
11138 11:34:16.836489 2024-07-17 11:34:01 (1.74 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
11139 11:34:16.836610
11140 11:34:23.330913 skiplist:
11141 11:34:23.333994 ========================================
11142 11:34:23.337106 ========================================
11143 11:34:23.375779 arm64:tags_test
11144 11:34:23.379372 arm64:run_tags_test.sh
11145 11:34:23.379466 arm64:fake_sigreturn_bad_magic
11146 11:34:23.382557 arm64:fake_sigreturn_bad_size
11147 11:34:23.386116 arm64:fake_sigreturn_bad_size_for_magic0
11148 11:34:23.389245 arm64:fake_sigreturn_duplicated_fpsimd
11149 11:34:23.392364 arm64:fake_sigreturn_misaligned_sp
11150 11:34:23.395876 arm64:fake_sigreturn_missing_fpsimd
11151 11:34:23.399588 arm64:fake_sigreturn_sme_change_vl
11152 11:34:23.402553 arm64:fake_sigreturn_sve_change_vl
11153 11:34:23.405937 arm64:mangle_pstate_invalid_compat_toggle
11154 11:34:23.408835 arm64:mangle_pstate_invalid_daif_bits
11155 11:34:23.412557 arm64:mangle_pstate_invalid_mode_el1h
11156 11:34:23.415765 arm64:mangle_pstate_invalid_mode_el1t
11157 11:34:23.419584 arm64:mangle_pstate_invalid_mode_el2h
11158 11:34:23.423470 arm64:mangle_pstate_invalid_mode_el2t
11159 11:34:23.425811 arm64:mangle_pstate_invalid_mode_el3h
11160 11:34:23.429748 arm64:mangle_pstate_invalid_mode_el3t
11161 11:34:23.432748 arm64:sme_trap_no_sm
11162 11:34:23.436033 arm64:sme_trap_non_streaming
11163 11:34:23.436311 arm64:sme_trap_za
11164 11:34:23.439615 arm64:sme_vl
11165 11:34:23.440076 arm64:ssve_regs
11166 11:34:23.442905 arm64:sve_regs
11167 11:34:23.443283 arm64:sve_vl
11168 11:34:23.443692 arm64:za_no_regs
11169 11:34:23.445824 arm64:za_regs
11170 11:34:23.446355 arm64:pac
11171 11:34:23.449505 arm64:fp-stress
11172 11:34:23.449911 arm64:sve-ptrace
11173 11:34:23.452608 arm64:sve-probe-vls
11174 11:34:23.453001 arm64:vec-syscfg
11175 11:34:23.453322 arm64:za-fork
11176 11:34:23.456101 arm64:za-ptrace
11177 11:34:23.456511 arm64:check_buffer_fill
11178 11:34:23.459430 arm64:check_child_memory
11179 11:34:23.462606 arm64:check_gcr_el1_cswitch
11180 11:34:23.465838 arm64:check_ksm_options
11181 11:34:23.466362 arm64:check_mmap_options
11182 11:34:23.469023 arm64:check_prctl
11183 11:34:23.469427 arm64:check_tags_inclusion
11184 11:34:23.472817 arm64:check_user_mem
11185 11:34:23.473220 arm64:btitest
11186 11:34:23.476057 arm64:nobtitest
11187 11:34:23.476433 arm64:hwcap
11188 11:34:23.479420 arm64:ptrace
11189 11:34:23.479818 arm64:syscall-abi
11190 11:34:23.480165 arm64:tpidr2
11191 11:34:23.485954 ============== Tests to run ===============
11192 11:34:23.486418 arm64:tags_test
11193 11:34:23.489189 arm64:run_tags_test.sh
11194 11:34:23.492902 arm64:fake_sigreturn_bad_magic
11195 11:34:23.493285 arm64:fake_sigreturn_bad_size
11196 11:34:23.495853 arm64:fake_sigreturn_bad_size_for_magic0
11197 11:34:23.499109 arm64:fake_sigreturn_duplicated_fpsimd
11198 11:34:23.502351 arm64:fake_sigreturn_misaligned_sp
11199 11:34:23.506116 arm64:fake_sigreturn_missing_fpsimd
11200 11:34:23.509355 arm64:fake_sigreturn_sme_change_vl
11201 11:34:23.513199 arm64:fake_sigreturn_sve_change_vl
11202 11:34:23.515645 arm64:mangle_pstate_invalid_compat_toggle
11203 11:34:23.519150 arm64:mangle_pstate_invalid_daif_bits
11204 11:34:23.522698 arm64:mangle_pstate_invalid_mode_el1h
11205 11:34:23.525874 arm64:mangle_pstate_invalid_mode_el1t
11206 11:34:23.529091 arm64:mangle_pstate_invalid_mode_el2h
11207 11:34:23.532656 arm64:mangle_pstate_invalid_mode_el2t
11208 11:34:23.535514 arm64:mangle_pstate_invalid_mode_el3h
11209 11:34:23.542177 arm64:mangle_pstate_invalid_mode_el3t
11210 11:34:23.542573 arm64:sme_trap_no_sm
11211 11:34:23.545600 arm64:sme_trap_non_streaming
11212 11:34:23.546161 arm64:sme_trap_za
11213 11:34:23.548853 arm64:sme_vl
11214 11:34:23.549366 arm64:ssve_regs
11215 11:34:23.552515 arm64:sve_regs
11216 11:34:23.552922 arm64:sve_vl
11217 11:34:23.553346 arm64:za_no_regs
11218 11:34:23.555532 arm64:za_regs
11219 11:34:23.555910 arm64:pac
11220 11:34:23.558662 arm64:fp-stress
11221 11:34:23.559041 arm64:sve-ptrace
11222 11:34:23.562968 arm64:sve-probe-vls
11223 11:34:23.563347 arm64:vec-syscfg
11224 11:34:23.563642 arm64:za-fork
11225 11:34:23.565733 arm64:za-ptrace
11226 11:34:23.569103 arm64:check_buffer_fill
11227 11:34:23.569602 arm64:check_child_memory
11228 11:34:23.572549 arm64:check_gcr_el1_cswitch
11229 11:34:23.575689 arm64:check_ksm_options
11230 11:34:23.576069 arm64:check_mmap_options
11231 11:34:23.578647 arm64:check_prctl
11232 11:34:23.582380 arm64:check_tags_inclusion
11233 11:34:23.582773 arm64:check_user_mem
11234 11:34:23.585526 arm64:btitest
11235 11:34:23.585936 arm64:nobtitest
11236 11:34:23.586408 arm64:hwcap
11237 11:34:23.588599 arm64:ptrace
11238 11:34:23.589059 arm64:syscall-abi
11239 11:34:23.592201 arm64:tpidr2
11240 11:34:23.595437 ===========End Tests to run ===============
11241 11:34:23.596032 shardfile-arm64 pass
11242 11:34:23.804455 <12>[ 29.523718] kselftest: Running tests in arm64
11243 11:34:23.814316 TAP version 13
11244 11:34:23.830654 1..48
11245 11:34:23.851044 # selftests: arm64: tags_test
11246 11:34:24.317368 ok 1 selftests: arm64: tags_test
11247 11:34:24.333097 # selftests: arm64: run_tags_test.sh
11248 11:34:24.389156 # --------------------
11249 11:34:24.392646 # running tags test
11250 11:34:24.392723 # --------------------
11251 11:34:24.396519 # [PASS]
11252 11:34:24.399132 ok 2 selftests: arm64: run_tags_test.sh
11253 11:34:24.412523 # selftests: arm64: fake_sigreturn_bad_magic
11254 11:34:24.479624 # Registered handlers for all signals.
11255 11:34:24.479714 # Detected MINSTKSIGSZ:4720
11256 11:34:24.483029 # Testcase initialized.
11257 11:34:24.486325 # uc context validated.
11258 11:34:24.489781 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11259 11:34:24.492897 # Handled SIG_COPYCTX
11260 11:34:24.492977 # Available space:3568
11261 11:34:24.499487 # Using badly built context - ERR: BAD MAGIC !
11262 11:34:24.505940 # SIG_OK -- SP:0xFFFFDC716C40 si_addr@:0xffffdc716c40 si_code:2 token@:0xffffdc7159e0 offset:-4704
11263 11:34:24.509598 # ==>> completed. PASS(1)
11264 11:34:24.516136 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11265 11:34:24.523146 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDC7159E0
11266 11:34:24.526059 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11267 11:34:24.532667 # selftests: arm64: fake_sigreturn_bad_size
11268 11:34:24.549445 # Registered handlers for all signals.
11269 11:34:24.549633 # Detected MINSTKSIGSZ:4720
11270 11:34:24.553096 # Testcase initialized.
11271 11:34:24.556383 # uc context validated.
11272 11:34:24.559673 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11273 11:34:24.562642 # Handled SIG_COPYCTX
11274 11:34:24.562809 # Available space:3568
11275 11:34:24.565938 # uc context validated.
11276 11:34:24.573068 # Using badly built context - ERR: Bad size for esr_context
11277 11:34:24.579042 # SIG_OK -- SP:0xFFFFCFC5F120 si_addr@:0xffffcfc5f120 si_code:2 token@:0xffffcfc5dec0 offset:-4704
11278 11:34:24.582687 # ==>> completed. PASS(1)
11279 11:34:24.589092 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11280 11:34:24.595869 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCFC5DEC0
11281 11:34:24.599065 ok 4 selftests: arm64: fake_sigreturn_bad_size
11282 11:34:24.605551 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11283 11:34:24.643450 # Registered handlers for all signals.
11284 11:34:24.643534 # Detected MINSTKSIGSZ:4720
11285 11:34:24.646742 # Testcase initialized.
11286 11:34:24.650126 # uc context validated.
11287 11:34:24.653067 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11288 11:34:24.656680 # Handled SIG_COPYCTX
11289 11:34:24.656755 # Available space:3568
11290 11:34:24.663173 # Using badly built context - ERR: Bad size for terminator
11291 11:34:24.673285 # SIG_OK -- SP:0xFFFFE4A91000 si_addr@:0xffffe4a91000 si_code:2 token@:0xffffe4a8fda0 offset:-4704
11292 11:34:24.673671 # ==>> completed. PASS(1)
11293 11:34:24.683640 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11294 11:34:24.690537 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE4A8FDA0
11295 11:34:24.693558 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11296 11:34:24.699626 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11297 11:34:24.729064 # Registered handlers for all signals.
11298 11:34:24.729558 # Detected MINSTKSIGSZ:4720
11299 11:34:24.732148 # Testcase initialized.
11300 11:34:24.735649 # uc context validated.
11301 11:34:24.739310 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11302 11:34:24.742419 # Handled SIG_COPYCTX
11303 11:34:24.742813 # Available space:3568
11304 11:34:24.749027 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11305 11:34:24.759288 # SIG_OK -- SP:0xFFFFCEC839B0 si_addr@:0xffffcec839b0 si_code:2 token@:0xffffcec82750 offset:-4704
11306 11:34:24.759814 # ==>> completed. PASS(1)
11307 11:34:24.769013 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11308 11:34:24.776099 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCEC82750
11309 11:34:24.779509 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11310 11:34:24.782619 # selftests: arm64: fake_sigreturn_misaligned_sp
11311 11:34:24.807710 # Registered handlers for all signals.
11312 11:34:24.808223 # Detected MINSTKSIGSZ:4720
11313 11:34:24.810647 # Testcase initialized.
11314 11:34:24.813818 # uc context validated.
11315 11:34:24.816944 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11316 11:34:24.820574 # Handled SIG_COPYCTX
11317 11:34:24.827558 # SIG_OK -- SP:0xFFFFD06F1613 si_addr@:0xffffd06f1613 si_code:2 token@:0xffffd06f1613 offset:0
11318 11:34:24.830149 # ==>> completed. PASS(1)
11319 11:34:24.836861 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11320 11:34:24.844124 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD06F1613
11321 11:34:24.850444 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11322 11:34:24.853593 # selftests: arm64: fake_sigreturn_missing_fpsimd
11323 11:34:24.892311 # Registered handlers for all signals.
11324 11:34:24.892768 # Detected MINSTKSIGSZ:4720
11325 11:34:24.895466 # Testcase initialized.
11326 11:34:24.898597 # uc context validated.
11327 11:34:24.901873 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11328 11:34:24.905869 # Handled SIG_COPYCTX
11329 11:34:24.908403 # Mangling template header. Spare space:4096
11330 11:34:24.911707 # Using badly built context - ERR: Missing FPSIMD
11331 11:34:24.922524 # SIG_OK -- SP:0xFFFFF2F40BE0 si_addr@:0xfffff2f40be0 si_code:2 token@:0xfffff2f3f980 offset:-4704
11332 11:34:24.925040 # ==>> completed. PASS(1)
11333 11:34:24.932006 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11334 11:34:24.938285 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF2F3F980
11335 11:34:24.941724 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11336 11:34:24.948518 # selftests: arm64: fake_sigreturn_sme_change_vl
11337 11:34:24.976379 # Registered handlers for all signals.
11338 11:34:24.976821 # Detected MINSTKSIGSZ:4720
11339 11:34:24.980002 # ==>> completed. SKIP.
11340 11:34:24.986268 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11341 11:34:24.989504 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11342 11:34:24.998449 # selftests: arm64: fake_sigreturn_sve_change_vl
11343 11:34:25.053575 # Registered handlers for all signals.
11344 11:34:25.054044 # Detected MINSTKSIGSZ:4720
11345 11:34:25.056658 # ==>> completed. SKIP.
11346 11:34:25.063414 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11347 11:34:25.066455 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11348 11:34:25.074344 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11349 11:34:25.151288 # Registered handlers for all signals.
11350 11:34:25.151744 # Detected MINSTKSIGSZ:4720
11351 11:34:25.154363 # Testcase initialized.
11352 11:34:25.157372 # uc context validated.
11353 11:34:25.157814 # Handled SIG_TRIG
11354 11:34:25.167573 # SIG_OK -- SP:0xFFFFD3B0FB70 si_addr@:0xffffd3b0fb70 si_code:2 token@:(nil) offset:-281474233334640
11355 11:34:25.170638 # ==>> completed. PASS(1)
11356 11:34:25.177178 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11357 11:34:25.183556 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11358 11:34:25.187136 # selftests: arm64: mangle_pstate_invalid_daif_bits
11359 11:34:25.244316 # Registered handlers for all signals.
11360 11:34:25.244849 # Detected MINSTKSIGSZ:4720
11361 11:34:25.247260 # Testcase initialized.
11362 11:34:25.250565 # uc context validated.
11363 11:34:25.250972 # Handled SIG_TRIG
11364 11:34:25.260895 # SIG_OK -- SP:0xFFFFC19A4310 si_addr@:0xffffc19a4310 si_code:2 token@:(nil) offset:-281473929855760
11365 11:34:25.263940 # ==>> completed. PASS(1)
11366 11:34:25.270491 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11367 11:34:25.273553 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11368 11:34:25.280440 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11369 11:34:25.317334 # Registered handlers for all signals.
11370 11:34:25.317721 # Detected MINSTKSIGSZ:4720
11371 11:34:25.320630 # Testcase initialized.
11372 11:34:25.324083 # uc context validated.
11373 11:34:25.324647 # Handled SIG_TRIG
11374 11:34:25.334758 # SIG_OK -- SP:0xFFFFDC9E3F30 si_addr@:0xffffdc9e3f30 si_code:2 token@:(nil) offset:-281474383101744
11375 11:34:25.337239 # ==>> completed. PASS(1)
11376 11:34:25.343712 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11377 11:34:25.347117 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11378 11:34:25.353420 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11379 11:34:25.400071 # Registered handlers for all signals.
11380 11:34:25.400555 # Detected MINSTKSIGSZ:4720
11381 11:34:25.403118 # Testcase initialized.
11382 11:34:25.406695 # uc context validated.
11383 11:34:25.407171 # Handled SIG_TRIG
11384 11:34:25.416662 # SIG_OK -- SP:0xFFFFF0CB3B70 si_addr@:0xfffff0cb3b70 si_code:2 token@:(nil) offset:-281474721594224
11385 11:34:25.420244 # ==>> completed. PASS(1)
11386 11:34:25.426552 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11387 11:34:25.430184 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11388 11:34:25.433576 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11389 11:34:25.469427 # Registered handlers for all signals.
11390 11:34:25.469860 # Detected MINSTKSIGSZ:4720
11391 11:34:25.472632 # Testcase initialized.
11392 11:34:25.476941 # uc context validated.
11393 11:34:25.477434 # Handled SIG_TRIG
11394 11:34:25.486514 # SIG_OK -- SP:0xFFFFEBF0BED0 si_addr@:0xffffebf0bed0 si_code:2 token@:(nil) offset:-281474640166608
11395 11:34:25.489201 # ==>> completed. PASS(1)
11396 11:34:25.496651 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11397 11:34:25.499231 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11398 11:34:25.505883 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11399 11:34:25.559388 # Registered handlers for all signals.
11400 11:34:25.559825 # Detected MINSTKSIGSZ:4720
11401 11:34:25.562489 # Testcase initialized.
11402 11:34:25.565925 # uc context validated.
11403 11:34:25.566448 # Handled SIG_TRIG
11404 11:34:25.576461 # SIG_OK -- SP:0xFFFFCEC9A240 si_addr@:0xffffcec9a240 si_code:2 token@:(nil) offset:-281474151064128
11405 11:34:25.579894 # ==>> completed. PASS(1)
11406 11:34:25.586404 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11407 11:34:25.589280 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11408 11:34:25.595800 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11409 11:34:25.641045 # Registered handlers for all signals.
11410 11:34:25.641551 # Detected MINSTKSIGSZ:4720
11411 11:34:25.643942 # Testcase initialized.
11412 11:34:25.647393 # uc context validated.
11413 11:34:25.647898 # Handled SIG_TRIG
11414 11:34:25.657176 # SIG_OK -- SP:0xFFFFD322A6B0 si_addr@:0xffffd322a6b0 si_code:2 token@:(nil) offset:-281474224006832
11415 11:34:25.660293 # ==>> completed. PASS(1)
11416 11:34:25.667332 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11417 11:34:25.670643 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11418 11:34:25.677012 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11419 11:34:25.724194 # Registered handlers for all signals.
11420 11:34:25.724303 # Detected MINSTKSIGSZ:4720
11421 11:34:25.727014 # Testcase initialized.
11422 11:34:25.730871 # uc context validated.
11423 11:34:25.730947 # Handled SIG_TRIG
11424 11:34:25.740892 # SIG_OK -- SP:0xFFFFC9AFA2A0 si_addr@:0xffffc9afa2a0 si_code:2 token@:(nil) offset:-281474065474208
11425 11:34:25.743547 # ==>> completed. PASS(1)
11426 11:34:25.750093 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11427 11:34:25.753801 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11428 11:34:25.756791 # selftests: arm64: sme_trap_no_sm
11429 11:34:25.797760 # Registered handlers for all signals.
11430 11:34:25.797879 # Detected MINSTKSIGSZ:4720
11431 11:34:25.801574 # ==>> completed. SKIP.
11432 11:34:25.811336 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11433 11:34:25.814057 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11434 11:34:25.817975 # selftests: arm64: sme_trap_non_streaming
11435 11:34:25.880297 # Registered handlers for all signals.
11436 11:34:25.880399 # Detected MINSTKSIGSZ:4720
11437 11:34:25.883379 # ==>> completed. SKIP.
11438 11:34:25.893661 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11439 11:34:25.900377 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11440 11:34:25.903792 # selftests: arm64: sme_trap_za
11441 11:34:25.952900 # Registered handlers for all signals.
11442 11:34:25.952988 # Detected MINSTKSIGSZ:4720
11443 11:34:25.955779 # Testcase initialized.
11444 11:34:25.966404 # SIG_OK -- SP:0xFFFFD0F241D0 si_addr@:0xaaaad13f2480 si_code:1 token@:(nil) offset:-187650631738496
11445 11:34:25.966480 # ==>> completed. PASS(1)
11446 11:34:25.975638 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11447 11:34:25.978958 ok 21 selftests: arm64: sme_trap_za
11448 11:34:25.979075 # selftests: arm64: sme_vl
11449 11:34:26.041794 # Registered handlers for all signals.
11450 11:34:26.042330 # Detected MINSTKSIGSZ:4720
11451 11:34:26.045820 # ==>> completed. SKIP.
11452 11:34:26.048465 # # SME VL :: Check that we get the right SME VL reported
11453 11:34:26.051988 ok 22 selftests: arm64: sme_vl # SKIP
11454 11:34:26.059341 # selftests: arm64: ssve_regs
11455 11:34:26.128569 # Registered handlers for all signals.
11456 11:34:26.128982 # Detected MINSTKSIGSZ:4720
11457 11:34:26.132099 # ==>> completed. SKIP.
11458 11:34:26.138705 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11459 11:34:26.145199 ok 23 selftests: arm64: ssve_regs # SKIP
11460 11:34:26.145608 # selftests: arm64: sve_regs
11461 11:34:26.222501 # Registered handlers for all signals.
11462 11:34:26.222909 # Detected MINSTKSIGSZ:4720
11463 11:34:26.225703 # ==>> completed. SKIP.
11464 11:34:26.232585 # # SVE registers :: Check that we get the right SVE registers reported
11465 11:34:26.235788 ok 24 selftests: arm64: sve_regs # SKIP
11466 11:34:26.246823 # selftests: arm64: sve_vl
11467 11:34:26.325413 # Registered handlers for all signals.
11468 11:34:26.325815 # Detected MINSTKSIGSZ:4720
11469 11:34:26.328953 # ==>> completed. SKIP.
11470 11:34:26.335234 # # SVE VL :: Check that we get the right SVE VL reported
11471 11:34:26.338954 ok 25 selftests: arm64: sve_vl # SKIP
11472 11:34:26.343518 # selftests: arm64: za_no_regs
11473 11:34:26.430080 # Registered handlers for all signals.
11474 11:34:26.430484 # Detected MINSTKSIGSZ:4720
11475 11:34:26.433001 # ==>> completed. SKIP.
11476 11:34:26.440172 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11477 11:34:26.443193 ok 26 selftests: arm64: za_no_regs # SKIP
11478 11:34:26.448145 # selftests: arm64: za_regs
11479 11:34:26.506766 # Registered handlers for all signals.
11480 11:34:26.507171 # Detected MINSTKSIGSZ:4720
11481 11:34:26.510000 # ==>> completed. SKIP.
11482 11:34:26.516900 # # ZA register :: Check that we get the right ZA registers reported
11483 11:34:26.520144 ok 27 selftests: arm64: za_regs # SKIP
11484 11:34:26.524120 # selftests: arm64: pac
11485 11:34:26.594608 # TAP version 13
11486 11:34:26.595055 # 1..7
11487 11:34:26.597850 # # Starting 7 tests from 1 test cases.
11488 11:34:26.601200 # # RUN global.corrupt_pac ...
11489 11:34:26.604703 # # SKIP PAUTH not enabled
11490 11:34:26.608018 # # OK global.corrupt_pac
11491 11:34:26.611396 # ok 1 # SKIP PAUTH not enabled
11492 11:34:26.618307 # # RUN global.pac_instructions_not_nop ...
11493 11:34:26.621305 # # SKIP PAUTH not enabled
11494 11:34:26.624457 # # OK global.pac_instructions_not_nop
11495 11:34:26.627916 # ok 2 # SKIP PAUTH not enabled
11496 11:34:26.634558 # # RUN global.pac_instructions_not_nop_generic ...
11497 11:34:26.637663 # # SKIP Generic PAUTH not enabled
11498 11:34:26.641177 # # OK global.pac_instructions_not_nop_generic
11499 11:34:26.644310 # ok 3 # SKIP Generic PAUTH not enabled
11500 11:34:26.650806 # # RUN global.single_thread_different_keys ...
11501 11:34:26.654754 # # SKIP PAUTH not enabled
11502 11:34:26.660943 # # OK global.single_thread_different_keys
11503 11:34:26.661320 # ok 4 # SKIP PAUTH not enabled
11504 11:34:26.667430 # # RUN global.exec_changed_keys ...
11505 11:34:26.671003 # # SKIP PAUTH not enabled
11506 11:34:26.674650 # # OK global.exec_changed_keys
11507 11:34:26.677921 # ok 5 # SKIP PAUTH not enabled
11508 11:34:26.680857 # # RUN global.context_switch_keep_keys ...
11509 11:34:26.684527 # # SKIP PAUTH not enabled
11510 11:34:26.690791 # # OK global.context_switch_keep_keys
11511 11:34:26.691212 # ok 6 # SKIP PAUTH not enabled
11512 11:34:26.697599 # # RUN global.context_switch_keep_keys_generic ...
11513 11:34:26.700835 # # SKIP Generic PAUTH not enabled
11514 11:34:26.707249 # # OK global.context_switch_keep_keys_generic
11515 11:34:26.710646 # ok 7 # SKIP Generic PAUTH not enabled
11516 11:34:26.713959 # # PASSED: 7 / 7 tests passed.
11517 11:34:26.716956 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11518 11:34:26.721079 ok 28 selftests: arm64: pac
11519 11:34:26.723694 # selftests: arm64: fp-stress
11520 11:34:34.293642 <6>[ 40.017657] vpu: disabling
11521 11:34:34.296977 <6>[ 40.020707] vproc2: disabling
11522 11:34:34.300409 <6>[ 40.023980] vproc1: disabling
11523 11:34:34.303474 <6>[ 40.027253] vaud18: disabling
11524 11:34:34.310716 <6>[ 40.030686] vsram_others: disabling
11525 11:34:34.313775 <6>[ 40.034581] va09: disabling
11526 11:34:34.316913 <6>[ 40.037698] vsram_md: disabling
11527 11:34:34.320441 <6>[ 40.041197] Vgpu: disabling
11528 11:34:36.675117 # TAP version 13
11529 11:34:36.675241 # 1..16
11530 11:34:36.677969 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11531 11:34:36.681058 # # Will run for 10s
11532 11:34:36.681133 # # Started FPSIMD-0-0
11533 11:34:36.684445 # # Started FPSIMD-0-1
11534 11:34:36.687814 # # Started FPSIMD-1-0
11535 11:34:36.687908 # # Started FPSIMD-1-1
11536 11:34:36.691129 # # Started FPSIMD-2-0
11537 11:34:36.691218 # # Started FPSIMD-2-1
11538 11:34:36.694617 # # Started FPSIMD-3-0
11539 11:34:36.697739 # # Started FPSIMD-3-1
11540 11:34:36.697812 # # Started FPSIMD-4-0
11541 11:34:36.701264 # # Started FPSIMD-4-1
11542 11:34:36.704312 # # Started FPSIMD-5-0
11543 11:34:36.704396 # # Started FPSIMD-5-1
11544 11:34:36.707862 # # Started FPSIMD-6-0
11545 11:34:36.707935 # # Started FPSIMD-6-1
11546 11:34:36.710962 # # Started FPSIMD-7-0
11547 11:34:36.714836 # # Started FPSIMD-7-1
11548 11:34:36.717967 # # FPSIMD-0-0: Vector length: 128 bits
11549 11:34:36.718093 # # FPSIMD-0-0: PID: 1171
11550 11:34:36.724649 # # FPSIMD-1-0: Vector length: 128 bits
11551 11:34:36.724724 # # FPSIMD-1-0: PID: 1173
11552 11:34:36.727798 # # FPSIMD-1-1: Vector length: 128 bits
11553 11:34:36.731173 # # FPSIMD-1-1: PID: 1174
11554 11:34:36.734324 # # FPSIMD-0-1: Vector length: 128 bits
11555 11:34:36.737993 # # FPSIMD-0-1: PID: 1172
11556 11:34:36.741092 # # FPSIMD-2-0: Vector length: 128 bits
11557 11:34:36.744573 # # FPSIMD-2-0: PID: 1175
11558 11:34:36.747703 # # FPSIMD-3-0: Vector length: 128 bits
11559 11:34:36.747799 # # FPSIMD-3-0: PID: 1177
11560 11:34:36.750975 # # FPSIMD-2-1: Vector length: 128 bits
11561 11:34:36.754539 # # FPSIMD-2-1: PID: 1176
11562 11:34:36.757914 # # FPSIMD-5-1: Vector length: 128 bits
11563 11:34:36.761280 # # FPSIMD-5-1: PID: 1182
11564 11:34:36.764745 # # FPSIMD-5-0: Vector length: 128 bits
11565 11:34:36.767639 # # FPSIMD-5-0: PID: 1181
11566 11:34:36.771112 # # FPSIMD-6-1: Vector length: 128 bits
11567 11:34:36.771185 # # FPSIMD-6-1: PID: 1184
11568 11:34:36.777748 # # FPSIMD-4-1: Vector length: 128 bits
11569 11:34:36.777822 # # FPSIMD-4-1: PID: 1180
11570 11:34:36.780967 # # FPSIMD-7-1: Vector length: 128 bits
11571 11:34:36.784164 # # FPSIMD-7-1: PID: 1186
11572 11:34:36.787500 # # FPSIMD-3-1: Vector length: 128 bits
11573 11:34:36.791308 # # FPSIMD-3-1: PID: 1178
11574 11:34:36.794339 # # FPSIMD-4-0: Vector length: 128 bits
11575 11:34:36.797791 # # FPSIMD-4-0: PID: 1179
11576 11:34:36.800819 # # FPSIMD-7-0: Vector length: 128 bits
11577 11:34:36.800893 # # FPSIMD-7-0: PID: 1185
11578 11:34:36.804264 # # FPSIMD-6-0: Vector length: 128 bits
11579 11:34:36.807621 # # FPSIMD-6-0: PID: 1183
11580 11:34:36.811171 # # Finishing up...
11581 11:34:36.817610 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1045801, signals=10
11582 11:34:36.824409 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=939596, signals=10
11583 11:34:36.830491 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1252554, signals=10
11584 11:34:36.837323 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=842155, signals=10
11585 11:34:36.847024 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1121952, signals=10
11586 11:34:36.853595 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1510212, signals=10
11587 11:34:36.860917 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=2142498, signals=10
11588 11:34:36.860993 # ok 1 FPSIMD-0-0
11589 11:34:36.863661 # ok 2 FPSIMD-0-1
11590 11:34:36.863734 # ok 3 FPSIMD-1-0
11591 11:34:36.866948 # ok 4 FPSIMD-1-1
11592 11:34:36.867022 # ok 5 FPSIMD-2-0
11593 11:34:36.870396 # ok 6 FPSIMD-2-1
11594 11:34:36.870469 # ok 7 FPSIMD-3-0
11595 11:34:36.873913 # ok 8 FPSIMD-3-1
11596 11:34:36.874017 # ok 9 FPSIMD-4-0
11597 11:34:36.877387 # ok 10 FPSIMD-4-1
11598 11:34:36.877461 # ok 11 FPSIMD-5-0
11599 11:34:36.880545 # ok 12 FPSIMD-5-1
11600 11:34:36.880618 # ok 13 FPSIMD-6-0
11601 11:34:36.883433 # ok 14 FPSIMD-6-1
11602 11:34:36.886924 # ok 15 FPSIMD-7-0
11603 11:34:36.886997 # ok 16 FPSIMD-7-1
11604 11:34:36.893649 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1001014, signals=9
11605 11:34:36.900315 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1040765, signals=10
11606 11:34:36.909970 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1509728, signals=10
11607 11:34:36.916798 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1045125, signals=9
11608 11:34:36.923055 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1247597, signals=10
11609 11:34:36.929667 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1600349, signals=10
11610 11:34:36.936320 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1447047, signals=10
11611 11:34:36.943049 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=841173, signals=10
11612 11:34:36.952941 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=813449, signals=9
11613 11:34:36.956061 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11614 11:34:36.959413 ok 29 selftests: arm64: fp-stress
11615 11:34:36.962935 # selftests: arm64: sve-ptrace
11616 11:34:36.963009 # TAP version 13
11617 11:34:36.965909 # 1..4104
11618 11:34:36.965985 # ok 2 # SKIP SVE not available
11619 11:34:36.972879 # # Planned tests != run tests (4104 != 1)
11620 11:34:36.976291 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11621 11:34:36.979181 ok 30 selftests: arm64: sve-ptrace # SKIP
11622 11:34:36.982818 # selftests: arm64: sve-probe-vls
11623 11:34:36.985843 # TAP version 13
11624 11:34:36.985941 # 1..2
11625 11:34:36.989356 # ok 2 # SKIP SVE not available
11626 11:34:36.993177 # # Planned tests != run tests (2 != 1)
11627 11:34:36.995894 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11628 11:34:37.002824 ok 31 selftests: arm64: sve-probe-vls # SKIP
11629 11:34:37.002966 # selftests: arm64: vec-syscfg
11630 11:34:37.005496 # TAP version 13
11631 11:34:37.005591 # 1..20
11632 11:34:37.009073 # ok 1 # SKIP SVE not supported
11633 11:34:37.012714 # ok 2 # SKIP SVE not supported
11634 11:34:37.016021 # ok 3 # SKIP SVE not supported
11635 11:34:37.019419 # ok 4 # SKIP SVE not supported
11636 11:34:37.019516 # ok 5 # SKIP SVE not supported
11637 11:34:37.022476 # ok 6 # SKIP SVE not supported
11638 11:34:37.026648 # ok 7 # SKIP SVE not supported
11639 11:34:37.029423 # ok 8 # SKIP SVE not supported
11640 11:34:37.032377 # ok 9 # SKIP SVE not supported
11641 11:34:37.035690 # ok 10 # SKIP SVE not supported
11642 11:34:37.039341 # ok 11 # SKIP SME not supported
11643 11:34:37.042435 # ok 12 # SKIP SME not supported
11644 11:34:37.042532 # ok 13 # SKIP SME not supported
11645 11:34:37.045934 # ok 14 # SKIP SME not supported
11646 11:34:37.049318 # ok 15 # SKIP SME not supported
11647 11:34:37.052529 # ok 16 # SKIP SME not supported
11648 11:34:37.055760 # ok 17 # SKIP SME not supported
11649 11:34:37.058760 # ok 18 # SKIP SME not supported
11650 11:34:37.062130 # ok 19 # SKIP SME not supported
11651 11:34:37.065996 # ok 20 # SKIP SME not supported
11652 11:34:37.069110 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11653 11:34:37.072070 ok 32 selftests: arm64: vec-syscfg
11654 11:34:37.075320 # selftests: arm64: za-fork
11655 11:34:37.075416 # TAP version 13
11656 11:34:37.078835 # 1..1
11657 11:34:37.078931 # # PID: 1263
11658 11:34:37.082035 # # SME support not present
11659 11:34:37.082141 # ok 0 skipped
11660 11:34:37.088611 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11661 11:34:37.092024 ok 33 selftests: arm64: za-fork
11662 11:34:37.092121 # selftests: arm64: za-ptrace
11663 11:34:37.095443 # TAP version 13
11664 11:34:37.095543 # 1..1
11665 11:34:37.098605 # ok 2 # SKIP SME not available
11666 11:34:37.101862 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11667 11:34:37.105711 ok 34 selftests: arm64: za-ptrace # SKIP
11668 11:34:37.111990 # selftests: arm64: check_buffer_fill
11669 11:34:37.112088 # # SKIP: MTE features unavailable
11670 11:34:37.118914 ok 35 selftests: arm64: check_buffer_fill # SKIP
11671 11:34:37.135573 # selftests: arm64: check_child_memory
11672 11:34:37.162556 # # SKIP: MTE features unavailable
11673 11:34:37.168984 ok 36 selftests: arm64: check_child_memory # SKIP
11674 11:34:37.184004 # selftests: arm64: check_gcr_el1_cswitch
11675 11:34:37.233311 # # SKIP: MTE features unavailable
11676 11:34:37.241226 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11677 11:34:37.255012 # selftests: arm64: check_ksm_options
11678 11:34:37.306626 # # SKIP: MTE features unavailable
11679 11:34:37.315087 ok 38 selftests: arm64: check_ksm_options # SKIP
11680 11:34:37.331193 # selftests: arm64: check_mmap_options
11681 11:34:37.372240 # # SKIP: MTE features unavailable
11682 11:34:37.379016 ok 39 selftests: arm64: check_mmap_options # SKIP
11683 11:34:37.391456 # selftests: arm64: check_prctl
11684 11:34:37.426607 # TAP version 13
11685 11:34:37.426726 # 1..5
11686 11:34:37.429605 # ok 1 check_basic_read
11687 11:34:37.429706 # ok 2 NONE
11688 11:34:37.433809 # ok 3 # SKIP SYNC
11689 11:34:37.433910 # ok 4 # SKIP ASYNC
11690 11:34:37.436092 # ok 5 # SKIP SYNC+ASYNC
11691 11:34:37.439630 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11692 11:34:37.442577 ok 40 selftests: arm64: check_prctl
11693 11:34:37.445808 # selftests: arm64: check_tags_inclusion
11694 11:34:37.494266 # # SKIP: MTE features unavailable
11695 11:34:37.503072 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11696 11:34:37.515999 # selftests: arm64: check_user_mem
11697 11:34:37.567708 # # SKIP: MTE features unavailable
11698 11:34:37.574780 ok 42 selftests: arm64: check_user_mem # SKIP
11699 11:34:37.585801 # selftests: arm64: btitest
11700 11:34:37.638266 # TAP version 13
11701 11:34:37.638395 # 1..18
11702 11:34:37.642326 # # HWCAP_PACA not present
11703 11:34:37.645086 # # HWCAP2_BTI not present
11704 11:34:37.645178 # # Test binary built for BTI
11705 11:34:37.651727 # ok 1 nohint_func/call_using_br_x0 # SKIP
11706 11:34:37.654654 # ok 1 nohint_func/call_using_br_x16 # SKIP
11707 11:34:37.658371 # ok 1 nohint_func/call_using_blr # SKIP
11708 11:34:37.662187 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11709 11:34:37.664674 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11710 11:34:37.671271 # ok 1 bti_none_func/call_using_blr # SKIP
11711 11:34:37.674998 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11712 11:34:37.678073 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11713 11:34:37.681252 # ok 1 bti_c_func/call_using_blr # SKIP
11714 11:34:37.684639 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11715 11:34:37.688008 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11716 11:34:37.691454 # ok 1 bti_j_func/call_using_blr # SKIP
11717 11:34:37.695188 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11718 11:34:37.698310 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11719 11:34:37.704652 # ok 1 bti_jc_func/call_using_blr # SKIP
11720 11:34:37.708345 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11721 11:34:37.711716 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11722 11:34:37.714766 # ok 1 paciasp_func/call_using_blr # SKIP
11723 11:34:37.721153 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11724 11:34:37.724609 # # WARNING - EXPECTED TEST COUNT WRONG
11725 11:34:37.727697 ok 43 selftests: arm64: btitest
11726 11:34:37.727792 # selftests: arm64: nobtitest
11727 11:34:37.731377 # TAP version 13
11728 11:34:37.731471 # 1..18
11729 11:34:37.734271 # # HWCAP_PACA not present
11730 11:34:37.737846 # # HWCAP2_BTI not present
11731 11:34:37.741175 # # Test binary not built for BTI
11732 11:34:37.744320 # ok 1 nohint_func/call_using_br_x0 # SKIP
11733 11:34:37.747522 # ok 1 nohint_func/call_using_br_x16 # SKIP
11734 11:34:37.751207 # ok 1 nohint_func/call_using_blr # SKIP
11735 11:34:37.754486 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11736 11:34:37.757441 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11737 11:34:37.764216 # ok 1 bti_none_func/call_using_blr # SKIP
11738 11:34:37.767556 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11739 11:34:37.771041 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11740 11:34:37.774174 # ok 1 bti_c_func/call_using_blr # SKIP
11741 11:34:37.777547 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11742 11:34:37.780730 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11743 11:34:37.784151 # ok 1 bti_j_func/call_using_blr # SKIP
11744 11:34:37.787188 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11745 11:34:37.794229 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11746 11:34:37.797108 # ok 1 bti_jc_func/call_using_blr # SKIP
11747 11:34:37.800533 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11748 11:34:37.804102 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11749 11:34:37.807088 # ok 1 paciasp_func/call_using_blr # SKIP
11750 11:34:37.813627 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11751 11:34:37.817368 # # WARNING - EXPECTED TEST COUNT WRONG
11752 11:34:37.820002 ok 44 selftests: arm64: nobtitest
11753 11:34:37.823237 # selftests: arm64: hwcap
11754 11:34:37.823338 # TAP version 13
11755 11:34:37.823426 # 1..28
11756 11:34:37.827190 # ok 1 cpuinfo_match_RNG
11757 11:34:37.830232 # # SIGILL reported for RNG
11758 11:34:37.830331 # ok 2 # SKIP sigill_RNG
11759 11:34:37.834050 # ok 3 cpuinfo_match_SME
11760 11:34:37.836885 # ok 4 sigill_SME
11761 11:34:37.837004 # ok 5 cpuinfo_match_SVE
11762 11:34:37.840075 # ok 6 sigill_SVE
11763 11:34:37.840163 # ok 7 cpuinfo_match_SVE 2
11764 11:34:37.843731 # # SIGILL reported for SVE 2
11765 11:34:37.846634 # ok 8 # SKIP sigill_SVE 2
11766 11:34:37.850276 # ok 9 cpuinfo_match_SVE AES
11767 11:34:37.853240 # # SIGILL reported for SVE AES
11768 11:34:37.853305 # ok 10 # SKIP sigill_SVE AES
11769 11:34:37.856982 # ok 11 cpuinfo_match_SVE2 PMULL
11770 11:34:37.859930 # # SIGILL reported for SVE2 PMULL
11771 11:34:37.863767 # ok 12 # SKIP sigill_SVE2 PMULL
11772 11:34:37.866890 # ok 13 cpuinfo_match_SVE2 BITPERM
11773 11:34:37.869825 # # SIGILL reported for SVE2 BITPERM
11774 11:34:37.873170 # ok 14 # SKIP sigill_SVE2 BITPERM
11775 11:34:37.876323 # ok 15 cpuinfo_match_SVE2 SHA3
11776 11:34:37.879958 # # SIGILL reported for SVE2 SHA3
11777 11:34:37.882997 # ok 16 # SKIP sigill_SVE2 SHA3
11778 11:34:37.887029 # ok 17 cpuinfo_match_SVE2 SM4
11779 11:34:37.887102 # # SIGILL reported for SVE2 SM4
11780 11:34:37.889639 # ok 18 # SKIP sigill_SVE2 SM4
11781 11:34:37.892997 # ok 19 cpuinfo_match_SVE2 I8MM
11782 11:34:37.896580 # # SIGILL reported for SVE2 I8MM
11783 11:34:37.899328 # ok 20 # SKIP sigill_SVE2 I8MM
11784 11:34:37.902671 # ok 21 cpuinfo_match_SVE2 F32MM
11785 11:34:37.905829 # # SIGILL reported for SVE2 F32MM
11786 11:34:37.909563 # ok 22 # SKIP sigill_SVE2 F32MM
11787 11:34:37.912835 # ok 23 cpuinfo_match_SVE2 F64MM
11788 11:34:37.916147 # # SIGILL reported for SVE2 F64MM
11789 11:34:37.916273 # ok 24 # SKIP sigill_SVE2 F64MM
11790 11:34:37.919254 # ok 25 cpuinfo_match_SVE2 BF16
11791 11:34:37.922539 # # SIGILL reported for SVE2 BF16
11792 11:34:37.926071 # ok 26 # SKIP sigill_SVE2 BF16
11793 11:34:37.929423 # ok 27 cpuinfo_match_SVE2 EBF16
11794 11:34:37.932461 # ok 28 # SKIP sigill_SVE2 EBF16
11795 11:34:37.935625 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11796 11:34:37.938900 ok 45 selftests: arm64: hwcap
11797 11:34:37.942347 # selftests: arm64: ptrace
11798 11:34:37.945696 # TAP version 13
11799 11:34:37.945772 # 1..7
11800 11:34:37.948769 # # Parent is 1505, child is 1506
11801 11:34:37.948858 # ok 1 read_tpidr_one
11802 11:34:37.952603 # ok 2 write_tpidr_one
11803 11:34:37.955554 # ok 3 verify_tpidr_one
11804 11:34:37.955630 # ok 4 count_tpidrs
11805 11:34:37.958712 # ok 5 tpidr2_write
11806 11:34:37.958819 # ok 6 tpidr2_read
11807 11:34:37.962043 # ok 7 write_tpidr_only
11808 11:34:37.965720 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11809 11:34:37.968716 ok 46 selftests: arm64: ptrace
11810 11:34:37.972044 # selftests: arm64: syscall-abi
11811 11:34:37.972163 # TAP version 13
11812 11:34:37.975666 # 1..2
11813 11:34:37.975774 # ok 1 getpid() FPSIMD
11814 11:34:37.978949 # ok 2 sched_yield() FPSIMD
11815 11:34:37.985659 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11816 11:34:37.988842 ok 47 selftests: arm64: syscall-abi
11817 11:34:37.988925 # selftests: arm64: tpidr2
11818 11:34:38.039774 # Segmentation fault
11819 11:34:38.046870 not ok 48 selftests: arm64: tpidr2 # exit=139
11820 11:34:39.497067 arm64_tags_test pass
11821 11:34:39.500945 arm64_run_tags_test_sh pass
11822 11:34:39.503855 arm64_fake_sigreturn_bad_magic pass
11823 11:34:39.507312 arm64_fake_sigreturn_bad_size pass
11824 11:34:39.510334 arm64_fake_sigreturn_bad_size_for_magic0 pass
11825 11:34:39.513553 arm64_fake_sigreturn_duplicated_fpsimd pass
11826 11:34:39.517225 arm64_fake_sigreturn_misaligned_sp pass
11827 11:34:39.520344 arm64_fake_sigreturn_missing_fpsimd pass
11828 11:34:39.524163 arm64_fake_sigreturn_sme_change_vl skip
11829 11:34:39.526654 arm64_fake_sigreturn_sve_change_vl skip
11830 11:34:39.533327 arm64_mangle_pstate_invalid_compat_toggle pass
11831 11:34:39.537006 arm64_mangle_pstate_invalid_daif_bits pass
11832 11:34:39.539986 arm64_mangle_pstate_invalid_mode_el1h pass
11833 11:34:39.543848 arm64_mangle_pstate_invalid_mode_el1t pass
11834 11:34:39.546943 arm64_mangle_pstate_invalid_mode_el2h pass
11835 11:34:39.553326 arm64_mangle_pstate_invalid_mode_el2t pass
11836 11:34:39.556360 arm64_mangle_pstate_invalid_mode_el3h pass
11837 11:34:39.559913 arm64_mangle_pstate_invalid_mode_el3t pass
11838 11:34:39.562972 arm64_sme_trap_no_sm skip
11839 11:34:39.563114 arm64_sme_trap_non_streaming skip
11840 11:34:39.566498 arm64_sme_trap_za pass
11841 11:34:39.569966 arm64_sme_vl skip
11842 11:34:39.570106 arm64_ssve_regs skip
11843 11:34:39.573064 arm64_sve_regs skip
11844 11:34:39.573195 arm64_sve_vl skip
11845 11:34:39.576179 arm64_za_no_regs skip
11846 11:34:39.576309 arm64_za_regs skip
11847 11:34:39.579587 arm64_pac_PAUTH_not_enabled skip
11848 11:34:39.583060 arm64_pac_PAUTH_not_enabled_dup2 skip
11849 11:34:39.586356 arm64_pac_Generic_PAUTH_not_enabled skip
11850 11:34:39.590059 arm64_pac_PAUTH_not_enabled_dup3 skip
11851 11:34:39.593509 arm64_pac_PAUTH_not_enabled_dup4 skip
11852 11:34:39.596661 arm64_pac_PAUTH_not_enabled_dup5 skip
11853 11:34:39.602933 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11854 11:34:39.603059 arm64_pac pass
11855 11:34:39.606532 arm64_fp-stress_FPSIMD-0-0 pass
11856 11:34:39.609943 arm64_fp-stress_FPSIMD-0-1 pass
11857 11:34:39.612841 arm64_fp-stress_FPSIMD-1-0 pass
11858 11:34:39.616180 arm64_fp-stress_FPSIMD-1-1 pass
11859 11:34:39.616280 arm64_fp-stress_FPSIMD-2-0 pass
11860 11:34:39.619893 arm64_fp-stress_FPSIMD-2-1 pass
11861 11:34:39.623510 arm64_fp-stress_FPSIMD-3-0 pass
11862 11:34:39.626274 arm64_fp-stress_FPSIMD-3-1 pass
11863 11:34:39.629375 arm64_fp-stress_FPSIMD-4-0 pass
11864 11:34:39.633397 arm64_fp-stress_FPSIMD-4-1 pass
11865 11:34:39.636110 arm64_fp-stress_FPSIMD-5-0 pass
11866 11:34:39.636264 arm64_fp-stress_FPSIMD-5-1 pass
11867 11:34:39.639557 arm64_fp-stress_FPSIMD-6-0 pass
11868 11:34:39.643291 arm64_fp-stress_FPSIMD-6-1 pass
11869 11:34:39.645762 arm64_fp-stress_FPSIMD-7-0 pass
11870 11:34:39.649260 arm64_fp-stress_FPSIMD-7-1 pass
11871 11:34:39.649395 arm64_fp-stress pass
11872 11:34:39.655959 arm64_sve-ptrace_SVE_not_available skip
11873 11:34:39.656118 arm64_sve-ptrace skip
11874 11:34:39.659633 arm64_sve-probe-vls_SVE_not_available skip
11875 11:34:39.662460 arm64_sve-probe-vls skip
11876 11:34:39.665809 arm64_vec-syscfg_SVE_not_supported skip
11877 11:34:39.669092 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11878 11:34:39.675568 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11879 11:34:39.679367 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11880 11:34:39.682393 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11881 11:34:39.685568 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11882 11:34:39.688618 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11883 11:34:39.695382 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11884 11:34:39.698558 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11885 11:34:39.702303 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11886 11:34:39.705465 arm64_vec-syscfg_SME_not_supported skip
11887 11:34:39.708503 arm64_vec-syscfg_SME_not_supported_dup2 skip
11888 11:34:39.715297 arm64_vec-syscfg_SME_not_supported_dup3 skip
11889 11:34:39.718594 arm64_vec-syscfg_SME_not_supported_dup4 skip
11890 11:34:39.722365 arm64_vec-syscfg_SME_not_supported_dup5 skip
11891 11:34:39.725296 arm64_vec-syscfg_SME_not_supported_dup6 skip
11892 11:34:39.728699 arm64_vec-syscfg_SME_not_supported_dup7 skip
11893 11:34:39.735824 arm64_vec-syscfg_SME_not_supported_dup8 skip
11894 11:34:39.738701 arm64_vec-syscfg_SME_not_supported_dup9 skip
11895 11:34:39.741827 arm64_vec-syscfg_SME_not_supported_dup10 skip
11896 11:34:39.745152 arm64_vec-syscfg pass
11897 11:34:39.745241 arm64_za-fork_skipped pass
11898 11:34:39.748235 arm64_za-fork pass
11899 11:34:39.751417 arm64_za-ptrace_SME_not_available skip
11900 11:34:39.751500 arm64_za-ptrace skip
11901 11:34:39.754941 arm64_check_buffer_fill skip
11902 11:34:39.758301 arm64_check_child_memory skip
11903 11:34:39.761162 arm64_check_gcr_el1_cswitch skip
11904 11:34:39.764540 arm64_check_ksm_options skip
11905 11:34:39.768250 arm64_check_mmap_options skip
11906 11:34:39.771713 arm64_check_prctl_check_basic_read pass
11907 11:34:39.771825 arm64_check_prctl_NONE pass
11908 11:34:39.774549 arm64_check_prctl_SYNC skip
11909 11:34:39.778114 arm64_check_prctl_ASYNC skip
11910 11:34:39.781083 arm64_check_prctl_SYNC_ASYNC skip
11911 11:34:39.784648 arm64_check_prctl pass
11912 11:34:39.784794 arm64_check_tags_inclusion skip
11913 11:34:39.788084 arm64_check_user_mem skip
11914 11:34:39.791673 arm64_btitest_nohint_func_call_using_br_x0 skip
11915 11:34:39.798254 arm64_btitest_nohint_func_call_using_br_x16 skip
11916 11:34:39.801506 arm64_btitest_nohint_func_call_using_blr skip
11917 11:34:39.804903 arm64_btitest_bti_none_func_call_using_br_x0 skip
11918 11:34:39.811378 arm64_btitest_bti_none_func_call_using_br_x16 skip
11919 11:34:39.814367 arm64_btitest_bti_none_func_call_using_blr skip
11920 11:34:39.817896 arm64_btitest_bti_c_func_call_using_br_x0 skip
11921 11:34:39.821336 arm64_btitest_bti_c_func_call_using_br_x16 skip
11922 11:34:39.827945 arm64_btitest_bti_c_func_call_using_blr skip
11923 11:34:39.831144 arm64_btitest_bti_j_func_call_using_br_x0 skip
11924 11:34:39.834871 arm64_btitest_bti_j_func_call_using_br_x16 skip
11925 11:34:39.837866 arm64_btitest_bti_j_func_call_using_blr skip
11926 11:34:39.844152 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11927 11:34:39.847534 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11928 11:34:39.851078 arm64_btitest_bti_jc_func_call_using_blr skip
11929 11:34:39.854895 arm64_btitest_paciasp_func_call_using_br_x0 skip
11930 11:34:39.860931 arm64_btitest_paciasp_func_call_using_br_x16 skip
11931 11:34:39.863993 arm64_btitest_paciasp_func_call_using_blr skip
11932 11:34:39.867499 arm64_btitest pass
11933 11:34:39.870832 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11934 11:34:39.874366 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11935 11:34:39.880883 arm64_nobtitest_nohint_func_call_using_blr skip
11936 11:34:39.884503 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11937 11:34:39.887336 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11938 11:34:39.894081 arm64_nobtitest_bti_none_func_call_using_blr skip
11939 11:34:39.898329 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11940 11:34:39.901101 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11941 11:34:39.907414 arm64_nobtitest_bti_c_func_call_using_blr skip
11942 11:34:39.910908 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11943 11:34:39.914045 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11944 11:34:39.920229 arm64_nobtitest_bti_j_func_call_using_blr skip
11945 11:34:39.923728 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11946 11:34:39.927247 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11947 11:34:39.934270 arm64_nobtitest_bti_jc_func_call_using_blr skip
11948 11:34:39.937111 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11949 11:34:39.940483 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11950 11:34:39.946752 arm64_nobtitest_paciasp_func_call_using_blr skip
11951 11:34:39.946859 arm64_nobtitest pass
11952 11:34:39.950136 arm64_hwcap_cpuinfo_match_RNG pass
11953 11:34:39.953753 arm64_hwcap_sigill_RNG skip
11954 11:34:39.957057 arm64_hwcap_cpuinfo_match_SME pass
11955 11:34:39.960452 arm64_hwcap_sigill_SME pass
11956 11:34:39.963641 arm64_hwcap_cpuinfo_match_SVE pass
11957 11:34:39.963729 arm64_hwcap_sigill_SVE pass
11958 11:34:39.967120 arm64_hwcap_cpuinfo_match_SVE_2 pass
11959 11:34:39.970628 arm64_hwcap_sigill_SVE_2 skip
11960 11:34:39.973627 arm64_hwcap_cpuinfo_match_SVE_AES pass
11961 11:34:39.977151 arm64_hwcap_sigill_SVE_AES skip
11962 11:34:39.980312 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11963 11:34:39.983998 arm64_hwcap_sigill_SVE2_PMULL skip
11964 11:34:39.987021 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11965 11:34:39.990141 arm64_hwcap_sigill_SVE2_BITPERM skip
11966 11:34:39.993907 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11967 11:34:39.996767 arm64_hwcap_sigill_SVE2_SHA3 skip
11968 11:34:39.999997 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11969 11:34:40.003540 arm64_hwcap_sigill_SVE2_SM4 skip
11970 11:34:40.006631 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11971 11:34:40.010165 arm64_hwcap_sigill_SVE2_I8MM skip
11972 11:34:40.013646 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11973 11:34:40.016669 arm64_hwcap_sigill_SVE2_F32MM skip
11974 11:34:40.020479 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11975 11:34:40.023473 arm64_hwcap_sigill_SVE2_F64MM skip
11976 11:34:40.026719 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11977 11:34:40.030302 arm64_hwcap_sigill_SVE2_BF16 skip
11978 11:34:40.033281 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11979 11:34:40.036681 arm64_hwcap_sigill_SVE2_EBF16 skip
11980 11:34:40.039816 arm64_hwcap pass
11981 11:34:40.044051 arm64_ptrace_read_tpidr_one pass
11982 11:34:40.047129 arm64_ptrace_write_tpidr_one pass
11983 11:34:40.049731 arm64_ptrace_verify_tpidr_one pass
11984 11:34:40.049837 arm64_ptrace_count_tpidrs pass
11985 11:34:40.052941 arm64_ptrace_tpidr2_write pass
11986 11:34:40.056489 arm64_ptrace_tpidr2_read pass
11987 11:34:40.059864 arm64_ptrace_write_tpidr_only pass
11988 11:34:40.063164 arm64_ptrace pass
11989 11:34:40.066669 arm64_syscall-abi_getpid_FPSIMD pass
11990 11:34:40.069716 arm64_syscall-abi_sched_yield_FPSIMD pass
11991 11:34:40.069802 arm64_syscall-abi pass
11992 11:34:40.072990 arm64_tpidr2 fail
11993 11:34:40.076416 + ../../utils/send-to-lava.sh ./output/result.txt
11994 11:34:40.082928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11995 11:34:40.083233 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11997 11:34:40.089474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11998 11:34:40.089755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12000 11:34:40.093127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12001 11:34:40.093377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12003 11:34:40.103161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12004 11:34:40.103441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12006 11:34:40.109470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12007 11:34:40.109741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12009 11:34:40.116543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12010 11:34:40.116806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12012 11:34:40.122667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12013 11:34:40.122929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12015 11:34:40.144492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12016 11:34:40.144839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12018 11:34:40.179609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12019 11:34:40.179903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12021 11:34:40.213472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12022 11:34:40.213807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12024 11:34:40.248335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12025 11:34:40.248701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12027 11:34:40.292705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12028 11:34:40.293044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12030 11:34:40.354771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12031 11:34:40.355107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12033 11:34:40.394987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12034 11:34:40.395326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12036 11:34:40.428935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12037 11:34:40.429272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12039 11:34:40.462672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12040 11:34:40.462961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12042 11:34:40.499254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12043 11:34:40.499596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12045 11:34:40.535003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12046 11:34:40.535294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12048 11:34:40.576926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12049 11:34:40.577244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12051 11:34:40.617551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12052 11:34:40.617841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12054 11:34:40.660613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12056 11:34:40.664588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12057 11:34:40.700543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12058 11:34:40.700845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12060 11:34:40.745696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12061 11:34:40.745990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12063 11:34:40.786916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12064 11:34:40.787207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12066 11:34:40.829060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12067 11:34:40.829372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12069 11:34:40.871151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12070 11:34:40.871446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12072 11:34:40.912286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12073 11:34:40.912579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12075 11:34:40.952063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12076 11:34:40.952354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12078 11:34:40.985336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12080 11:34:40.988939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12081 11:34:41.027104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12082 11:34:41.027421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12084 11:34:41.062975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12085 11:34:41.063291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12087 11:34:41.104599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12088 11:34:41.104892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12090 11:34:41.147345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12091 11:34:41.147637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12093 11:34:41.181486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12094 11:34:41.181780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12096 11:34:41.219163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12097 11:34:41.219453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12099 11:34:41.260592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12100 11:34:41.260880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12102 11:34:41.301981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12103 11:34:41.302293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12105 11:34:41.339844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12106 11:34:41.340136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12108 11:34:41.383234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12109 11:34:41.383555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12111 11:34:41.419767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12112 11:34:41.420057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12114 11:34:41.459947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12115 11:34:41.460283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12117 11:34:41.503216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12118 11:34:41.503554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12120 11:34:41.542420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12121 11:34:41.542749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12123 11:34:41.586995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12124 11:34:41.587330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12126 11:34:41.630653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12127 11:34:41.630989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12129 11:34:41.676032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12130 11:34:41.676372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12132 11:34:41.713013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12133 11:34:41.713358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12135 11:34:41.748336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12136 11:34:41.748671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12138 11:34:41.785381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12139 11:34:41.785719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12141 11:34:41.816180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12142 11:34:41.816515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12144 11:34:41.855128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12145 11:34:41.855463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12147 11:34:41.899959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12148 11:34:41.900288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12150 11:34:41.939492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12151 11:34:41.939821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12153 11:34:41.981097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12154 11:34:41.981426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12156 11:34:42.019097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12157 11:34:42.019456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12159 11:34:42.062193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12160 11:34:42.062484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12162 11:34:42.099786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12163 11:34:42.100076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12165 11:34:42.139498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12166 11:34:42.139827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12168 11:34:42.181940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12169 11:34:42.182317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12171 11:34:42.222974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12172 11:34:42.223305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12174 11:34:42.259570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12175 11:34:42.259897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12177 11:34:42.299792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12178 11:34:42.300117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12180 11:34:42.337941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12181 11:34:42.338299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12183 11:34:42.376887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12184 11:34:42.377173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12186 11:34:42.414337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12187 11:34:42.414648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12189 11:34:42.451703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12190 11:34:42.452016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12192 11:34:42.485654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12193 11:34:42.485965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12195 11:34:42.521986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12196 11:34:42.522300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12198 11:34:42.557781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12199 11:34:42.558112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12201 11:34:42.595860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12202 11:34:42.596190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12204 11:34:42.630913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12205 11:34:42.631204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12207 11:34:42.667727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12208 11:34:42.668109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12210 11:34:42.703189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12211 11:34:42.703480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12213 11:34:42.739150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12214 11:34:42.739484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12216 11:34:42.775584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12217 11:34:42.775878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12219 11:34:42.817902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12220 11:34:42.818237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12222 11:34:42.862321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12223 11:34:42.862638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12225 11:34:42.898927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12226 11:34:42.899213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12228 11:34:42.938902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12229 11:34:42.939225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12231 11:34:42.972811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12232 11:34:42.973106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12234 11:34:43.015570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12235 11:34:43.015857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12237 11:34:43.046968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12238 11:34:43.047264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12240 11:34:43.085200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12241 11:34:43.085499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12243 11:34:43.126847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12244 11:34:43.127135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12246 11:34:43.166062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12248 11:34:43.168562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12249 11:34:43.204975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12250 11:34:43.205284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12252 11:34:43.241970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12253 11:34:43.242304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12255 11:34:43.284973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12256 11:34:43.285268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12258 11:34:43.324410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12259 11:34:43.324697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12261 11:34:43.363465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12262 11:34:43.363752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12264 11:34:43.406952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12265 11:34:43.407245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12267 11:34:43.446118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12269 11:34:43.449318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12270 11:34:43.490311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12271 11:34:43.490598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12273 11:34:43.533188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12274 11:34:43.533479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12276 11:34:43.575303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12277 11:34:43.575602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12279 11:34:43.618152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12280 11:34:43.618442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12282 11:34:43.651340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12283 11:34:43.651667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12285 11:34:43.690322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12286 11:34:43.690609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12288 11:34:43.726933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12289 11:34:43.727233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12291 11:34:43.765044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12292 11:34:43.765337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12294 11:34:43.802341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12295 11:34:43.802632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12297 11:34:43.844273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12298 11:34:43.844630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12300 11:34:43.880827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12301 11:34:43.881125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12303 11:34:43.917023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12304 11:34:43.917370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12306 11:34:43.950804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12307 11:34:43.951095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12309 11:34:43.989824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12310 11:34:43.990113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12312 11:34:44.025907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12313 11:34:44.026224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12315 11:34:44.064579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12316 11:34:44.064869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12318 11:34:44.108328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12319 11:34:44.108618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12321 11:34:44.145798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12322 11:34:44.146113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12324 11:34:44.187126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12325 11:34:44.187466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12327 11:34:44.223610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12328 11:34:44.223939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12330 11:34:44.255078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12331 11:34:44.255368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12333 11:34:44.288345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12334 11:34:44.288634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12336 11:34:44.327097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12337 11:34:44.327388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12339 11:34:44.364093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12340 11:34:44.364406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12342 11:34:44.401969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12343 11:34:44.402322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12345 11:34:44.443443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12346 11:34:44.443756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12348 11:34:44.477580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12349 11:34:44.477868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12351 11:34:44.513626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12352 11:34:44.513939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12354 11:34:44.553361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12355 11:34:44.553671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12357 11:34:44.595407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12358 11:34:44.595745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12360 11:34:44.635693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12361 11:34:44.635984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12363 11:34:44.671867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12364 11:34:44.672158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12366 11:34:44.711232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12367 11:34:44.711580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12369 11:34:44.747722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12370 11:34:44.748044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12372 11:34:44.784998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12373 11:34:44.785289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12375 11:34:44.818214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12376 11:34:44.818506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12378 11:34:44.860186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12379 11:34:44.860497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12381 11:34:44.903049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12382 11:34:44.903339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12384 11:34:44.936474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12385 11:34:44.936757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12387 11:34:44.977912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12388 11:34:44.978247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12390 11:34:45.019289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12391 11:34:45.019622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12393 11:34:45.059818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12394 11:34:45.060130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12396 11:34:45.092813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12397 11:34:45.093131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12399 11:34:45.132775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12400 11:34:45.133062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12402 11:34:45.172246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12403 11:34:45.172537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12405 11:34:45.213273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12406 11:34:45.213549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12408 11:34:45.247020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12409 11:34:45.247290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12411 11:34:45.292079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12412 11:34:45.292359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12414 11:34:45.323967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12415 11:34:45.324239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12417 11:34:45.367378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12418 11:34:45.367699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12420 11:34:45.408021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12421 11:34:45.408324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12423 11:34:45.452756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12424 11:34:45.453059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12426 11:34:45.487199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12427 11:34:45.487475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12429 11:34:45.528641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12430 11:34:45.528916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12432 11:34:45.563747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12433 11:34:45.564024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12435 11:34:45.596424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12436 11:34:45.596702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12438 11:34:45.631799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12440 11:34:45.634586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12441 11:34:45.674659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12442 11:34:45.674965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12444 11:34:45.708714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12446 11:34:45.711330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12447 11:34:45.747171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12448 11:34:45.747516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12450 11:34:45.781103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12452 11:34:45.783805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12453 11:34:45.822125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12454 11:34:45.822447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12456 11:34:45.860193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12457 11:34:45.860507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12459 11:34:45.900039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12460 11:34:45.900332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12462 11:34:45.940023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12463 11:34:45.940336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12465 11:34:45.975267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12466 11:34:45.975557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12468 11:34:46.013463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12470 11:34:46.016579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12471 11:34:46.053900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12472 11:34:46.054279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12474 11:34:46.094224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12475 11:34:46.094541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12477 11:34:46.125361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12478 11:34:46.125662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12480 11:34:46.163258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12482 11:34:46.165651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12483 11:34:46.197678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12485 11:34:46.200461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12486 11:34:46.237401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12487 11:34:46.237713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12489 11:34:46.275335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12490 11:34:46.275621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12492 11:34:46.310563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12493 11:34:46.310887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12495 11:34:46.347693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12496 11:34:46.348002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12498 11:34:46.385879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12499 11:34:46.386216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12501 11:34:46.415841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12502 11:34:46.416128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12504 11:34:46.457181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12505 11:34:46.457530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12507 11:34:46.494894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12508 11:34:46.495216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12510 11:34:46.530390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12511 11:34:46.530684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12513 11:34:46.568140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=fail>
12514 11:34:46.568263 + set +x
12515 11:34:46.568491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=fail
12517 11:34:46.574359 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14864574_1.6.2.3.5>
12518 11:34:46.574612 Received signal: <ENDRUN> 1_kselftest-arm64 14864574_1.6.2.3.5
12519 11:34:46.574684 Ending use of test pattern.
12520 11:34:46.574740 Ending test lava.1_kselftest-arm64 (14864574_1.6.2.3.5), duration 31.81
12522 11:34:46.577794 <LAVA_TEST_RUNNER EXIT>
12523 11:34:46.578023 ok: lava_test_shell seems to have completed
12524 11:34:46.578875 shardfile-arm64: pass
arm64_tags_test: pass
arm64_run_tags_test_sh: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_fp-stress: pass
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-probe-vls: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg: pass
arm64_za-fork_skipped: pass
arm64_za-fork: pass
arm64_za-ptrace_SME_not_available: skip
arm64_za-ptrace: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest: pass
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SVE_AES: skip
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_write_tpidr_only: pass
arm64_ptrace: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi: pass
arm64_tpidr2: fail
12525 11:34:46.579039 end: 3.1 lava-test-shell (duration 00:00:33) [common]
12526 11:34:46.579117 end: 3 lava-test-retry (duration 00:00:33) [common]
12527 11:34:46.579193 start: 4 finalize (timeout 00:07:08) [common]
12528 11:34:46.579267 start: 4.1 power-off (timeout 00:00:30) [common]
12529 11:34:46.579383 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
12530 11:34:48.659863 >> Command sent successfully.
12531 11:34:48.663163 Returned 0 in 2 seconds
12532 11:34:48.663362 end: 4.1 power-off (duration 00:00:02) [common]
12534 11:34:48.663642 start: 4.2 read-feedback (timeout 00:07:06) [common]
12535 11:34:48.663819 Listened to connection for namespace 'common' for up to 1s
12536 11:34:49.663988 Finalising connection for namespace 'common'
12537 11:34:49.664127 Disconnecting from shell: Finalise
12538 11:34:49.664189 / #
12539 11:34:49.764439 end: 4.2 read-feedback (duration 00:00:01) [common]
12540 11:34:49.764576 end: 4 finalize (duration 00:00:03) [common]
12541 11:34:49.764669 Cleaning after the job
12542 11:34:49.764745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/ramdisk
12543 11:34:49.767213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/kernel
12544 11:34:49.778455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/dtb
12545 11:34:49.778694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/nfsrootfs
12546 11:34:49.847060 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864574/tftp-deploy-lg88ucyt/modules
12547 11:34:49.852828 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864574
12548 11:34:50.472767 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864574
12549 11:34:50.472924 Job finished correctly