Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:35:03.842048 lava-dispatcher, installed at version: 2024.05
2 11:35:03.842293 start: 0 validate
3 11:35:03.842405 Start time: 2024-07-17 11:35:03.842400+00:00 (UTC)
4 11:35:03.842530 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:35:03.842672 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:35:04.103984 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:35:04.104683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:35:04.367996 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:35:04.368739 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:35:04.628927 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:35:04.629068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:35:04.888270 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:35:04.888856 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:35:05.158856 validate duration: 1.32
16 11:35:05.159104 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:35:05.159212 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:35:05.159292 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:35:05.159455 Not decompressing ramdisk as can be used compressed.
20 11:35:05.159551 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:35:05.159612 saving as /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/ramdisk/initrd.cpio.gz
22 11:35:05.159671 total size: 5628169 (5 MB)
23 11:35:05.160633 progress 0 % (0 MB)
24 11:35:05.162404 progress 5 % (0 MB)
25 11:35:05.163896 progress 10 % (0 MB)
26 11:35:05.165284 progress 15 % (0 MB)
27 11:35:05.166764 progress 20 % (1 MB)
28 11:35:05.168086 progress 25 % (1 MB)
29 11:35:05.169573 progress 30 % (1 MB)
30 11:35:05.171075 progress 35 % (1 MB)
31 11:35:05.172403 progress 40 % (2 MB)
32 11:35:05.173917 progress 45 % (2 MB)
33 11:35:05.175310 progress 50 % (2 MB)
34 11:35:05.176757 progress 55 % (2 MB)
35 11:35:05.178263 progress 60 % (3 MB)
36 11:35:05.179549 progress 65 % (3 MB)
37 11:35:05.180990 progress 70 % (3 MB)
38 11:35:05.182327 progress 75 % (4 MB)
39 11:35:05.183762 progress 80 % (4 MB)
40 11:35:05.185090 progress 85 % (4 MB)
41 11:35:05.186560 progress 90 % (4 MB)
42 11:35:05.187991 progress 95 % (5 MB)
43 11:35:05.189282 progress 100 % (5 MB)
44 11:35:05.189475 5 MB downloaded in 0.03 s (180.12 MB/s)
45 11:35:05.189610 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:35:05.189826 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:35:05.189904 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:35:05.189978 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:35:05.190113 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:35:05.190174 saving as /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/kernel/Image
52 11:35:05.190227 total size: 54813184 (52 MB)
53 11:35:05.190279 No compression specified
54 11:35:05.191272 progress 0 % (0 MB)
55 11:35:05.204292 progress 5 % (2 MB)
56 11:35:05.217524 progress 10 % (5 MB)
57 11:35:05.230366 progress 15 % (7 MB)
58 11:35:05.243445 progress 20 % (10 MB)
59 11:35:05.256809 progress 25 % (13 MB)
60 11:35:05.269642 progress 30 % (15 MB)
61 11:35:05.282739 progress 35 % (18 MB)
62 11:35:05.295977 progress 40 % (20 MB)
63 11:35:05.308933 progress 45 % (23 MB)
64 11:35:05.322194 progress 50 % (26 MB)
65 11:35:05.335260 progress 55 % (28 MB)
66 11:35:05.348054 progress 60 % (31 MB)
67 11:35:05.361058 progress 65 % (34 MB)
68 11:35:05.374213 progress 70 % (36 MB)
69 11:35:05.387323 progress 75 % (39 MB)
70 11:35:05.400594 progress 80 % (41 MB)
71 11:35:05.413948 progress 85 % (44 MB)
72 11:35:05.427112 progress 90 % (47 MB)
73 11:35:05.440093 progress 95 % (49 MB)
74 11:35:05.452819 progress 100 % (52 MB)
75 11:35:05.453019 52 MB downloaded in 0.26 s (198.92 MB/s)
76 11:35:05.453159 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:35:05.453367 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:35:05.453446 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:35:05.453521 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:35:05.453652 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:35:05.453713 saving as /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/dtb/mt8192-asurada-spherion-r0.dtb
83 11:35:05.453764 total size: 47258 (0 MB)
84 11:35:05.453815 No compression specified
85 11:35:05.454910 progress 69 % (0 MB)
86 11:35:05.455162 progress 100 % (0 MB)
87 11:35:05.455305 0 MB downloaded in 0.00 s (29.30 MB/s)
88 11:35:05.455415 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:35:05.455614 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:35:05.455688 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:35:05.455763 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:35:05.455868 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:35:05.455928 saving as /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/nfsrootfs/full.rootfs.tar
95 11:35:05.455980 total size: 120894716 (115 MB)
96 11:35:05.456034 Using unxz to decompress xz
97 11:35:05.457191 progress 0 % (0 MB)
98 11:35:05.784980 progress 5 % (5 MB)
99 11:35:06.117554 progress 10 % (11 MB)
100 11:35:06.452830 progress 15 % (17 MB)
101 11:35:06.764506 progress 20 % (23 MB)
102 11:35:07.061921 progress 25 % (28 MB)
103 11:35:07.397090 progress 30 % (34 MB)
104 11:35:07.707181 progress 35 % (40 MB)
105 11:35:07.873226 progress 40 % (46 MB)
106 11:35:08.052283 progress 45 % (51 MB)
107 11:35:08.347159 progress 50 % (57 MB)
108 11:35:08.694065 progress 55 % (63 MB)
109 11:35:09.021104 progress 60 % (69 MB)
110 11:35:09.355228 progress 65 % (74 MB)
111 11:35:09.705698 progress 70 % (80 MB)
112 11:35:10.054668 progress 75 % (86 MB)
113 11:35:10.373984 progress 80 % (92 MB)
114 11:35:10.704002 progress 85 % (98 MB)
115 11:35:11.043842 progress 90 % (103 MB)
116 11:35:11.367474 progress 95 % (109 MB)
117 11:35:11.721971 progress 100 % (115 MB)
118 11:35:11.727356 115 MB downloaded in 6.27 s (18.38 MB/s)
119 11:35:11.727554 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:35:11.727887 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:35:11.727991 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:35:11.728091 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:35:11.728248 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:35:11.728333 saving as /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/modules/modules.tar
126 11:35:11.728410 total size: 8610184 (8 MB)
127 11:35:11.728490 Using unxz to decompress xz
128 11:35:11.730193 progress 0 % (0 MB)
129 11:35:11.749963 progress 5 % (0 MB)
130 11:35:11.774002 progress 10 % (0 MB)
131 11:35:11.798556 progress 15 % (1 MB)
132 11:35:11.823158 progress 20 % (1 MB)
133 11:35:11.847500 progress 25 % (2 MB)
134 11:35:11.870469 progress 30 % (2 MB)
135 11:35:11.893451 progress 35 % (2 MB)
136 11:35:11.918841 progress 40 % (3 MB)
137 11:35:11.942157 progress 45 % (3 MB)
138 11:35:11.965053 progress 50 % (4 MB)
139 11:35:11.988735 progress 55 % (4 MB)
140 11:35:12.011902 progress 60 % (4 MB)
141 11:35:12.034400 progress 65 % (5 MB)
142 11:35:12.058574 progress 70 % (5 MB)
143 11:35:12.084401 progress 75 % (6 MB)
144 11:35:12.110639 progress 80 % (6 MB)
145 11:35:12.133246 progress 85 % (7 MB)
146 11:35:12.155371 progress 90 % (7 MB)
147 11:35:12.177495 progress 95 % (7 MB)
148 11:35:12.199245 progress 100 % (8 MB)
149 11:35:12.204435 8 MB downloaded in 0.48 s (17.25 MB/s)
150 11:35:12.204583 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:35:12.204788 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:35:12.204864 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:35:12.204942 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:35:15.593810 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741
156 11:35:15.593981 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:35:15.594066 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 11:35:15.594265 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv
159 11:35:15.594379 makedir: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin
160 11:35:15.594466 makedir: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/tests
161 11:35:15.594552 makedir: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/results
162 11:35:15.594645 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-add-keys
163 11:35:15.594819 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-add-sources
164 11:35:15.594931 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-background-process-start
165 11:35:15.595043 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-background-process-stop
166 11:35:15.595164 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-common-functions
167 11:35:15.595275 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-echo-ipv4
168 11:35:15.595388 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-install-packages
169 11:35:15.595496 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-installed-packages
170 11:35:15.595603 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-os-build
171 11:35:15.595711 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-probe-channel
172 11:35:15.595818 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-probe-ip
173 11:35:15.595926 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-target-ip
174 11:35:15.596030 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-target-mac
175 11:35:15.596136 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-target-storage
176 11:35:15.596243 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-case
177 11:35:15.596349 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-event
178 11:35:15.596454 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-feedback
179 11:35:15.596559 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-raise
180 11:35:15.596728 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-reference
181 11:35:15.596886 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-runner
182 11:35:15.597054 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-set
183 11:35:15.597158 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-test-shell
184 11:35:15.597265 Updating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-add-keys (debian)
185 11:35:15.597397 Updating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-add-sources (debian)
186 11:35:15.597513 Updating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-install-packages (debian)
187 11:35:15.597631 Updating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-installed-packages (debian)
188 11:35:15.597747 Updating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/bin/lava-os-build (debian)
189 11:35:15.597850 Creating /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/environment
190 11:35:15.597930 LAVA metadata
191 11:35:15.597989 - LAVA_JOB_ID=14864619
192 11:35:15.598041 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:35:15.598161 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
194 11:35:15.598242 skipped lava-vland-overlay
195 11:35:15.598307 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:35:15.598375 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
197 11:35:15.598427 skipped lava-multinode-overlay
198 11:35:15.598488 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:35:15.598554 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
200 11:35:15.598614 Loading test definitions
201 11:35:15.598723 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
202 11:35:15.598789 Using /lava-14864619 at stage 0
203 11:35:15.599054 uuid=14864619_1.6.2.3.1 testdef=None
204 11:35:15.599130 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:35:15.599201 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
206 11:35:15.599574 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:35:15.599764 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
209 11:35:15.600250 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:35:15.600448 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
212 11:35:15.600914 runner path: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/0/tests/0_timesync-off test_uuid 14864619_1.6.2.3.1
213 11:35:15.601050 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:35:15.601240 start: 1.6.2.3.5 git-repo-action (timeout 00:09:50) [common]
216 11:35:15.601301 Using /lava-14864619 at stage 0
217 11:35:15.601382 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:35:15.601453 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/0/tests/1_kselftest-dt'
219 11:35:18.002509 Running '/usr/bin/git checkout kernelci.org
220 11:35:18.145932 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 11:35:18.146325 uuid=14864619_1.6.2.3.5 testdef=None
222 11:35:18.146428 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:35:18.146618 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 11:35:18.147238 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:35:18.147434 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 11:35:18.148353 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:35:18.148561 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 11:35:18.149393 runner path: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/0/tests/1_kselftest-dt test_uuid 14864619_1.6.2.3.5
232 11:35:18.149471 BOARD='mt8192-asurada-spherion-r0'
233 11:35:18.149528 BRANCH='cip-gitlab'
234 11:35:18.149579 SKIPFILE='/dev/null'
235 11:35:18.149628 SKIP_INSTALL='True'
236 11:35:18.149676 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:35:18.149726 TST_CASENAME=''
238 11:35:18.149773 TST_CMDFILES='dt'
239 11:35:18.149898 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:35:18.150072 Creating lava-test-runner.conf files
242 11:35:18.150200 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864619/lava-overlay-nrsrqarv/lava-14864619/0 for stage 0
243 11:35:18.150283 - 0_timesync-off
244 11:35:18.150340 - 1_kselftest-dt
245 11:35:18.150424 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:35:18.150498 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 11:35:25.485564 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:35:25.485699 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 11:35:25.485786 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:35:25.485865 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:35:25.485942 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 11:35:25.629495 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:35:25.629656 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 11:35:25.629755 extracting modules file /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741
255 11:35:25.855840 extracting modules file /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864619/extract-overlay-ramdisk-y2xq43qs/ramdisk
256 11:35:26.077500 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:35:26.077638 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 11:35:26.077719 [common] Applying overlay to NFS
259 11:35:26.077778 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864619/compress-overlay-w9b84f7m/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741
260 11:35:26.898741 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:35:26.898880 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 11:35:26.898984 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:35:26.899064 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 11:35:26.899135 Building ramdisk /var/lib/lava/dispatcher/tmp/14864619/extract-overlay-ramdisk-y2xq43qs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864619/extract-overlay-ramdisk-y2xq43qs/ramdisk
265 11:35:27.177599 >> 129966 blocks
266 11:35:29.305462 rename /var/lib/lava/dispatcher/tmp/14864619/extract-overlay-ramdisk-y2xq43qs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/ramdisk/ramdisk.cpio.gz
267 11:35:29.305615 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:35:29.305702 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 11:35:29.305779 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 11:35:29.305856 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/kernel/Image']
271 11:35:42.753704 Returned 0 in 13 seconds
272 11:35:42.753892 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/kernel/image.itb
273 11:35:43.102630 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:35:43.102760 output: Created: Wed Jul 17 12:35:43 2024
275 11:35:43.102906 output: Image 0 (kernel-1)
276 11:35:43.103003 output: Description:
277 11:35:43.103053 output: Created: Wed Jul 17 12:35:43 2024
278 11:35:43.103103 output: Type: Kernel Image
279 11:35:43.103151 output: Compression: lzma compressed
280 11:35:43.103201 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:35:43.103249 output: Architecture: AArch64
282 11:35:43.103295 output: OS: Linux
283 11:35:43.103340 output: Load Address: 0x00000000
284 11:35:43.103387 output: Entry Point: 0x00000000
285 11:35:43.103433 output: Hash algo: crc32
286 11:35:43.103479 output: Hash value: 83448d17
287 11:35:43.103526 output: Image 1 (fdt-1)
288 11:35:43.103573 output: Description: mt8192-asurada-spherion-r0
289 11:35:43.103619 output: Created: Wed Jul 17 12:35:43 2024
290 11:35:43.103666 output: Type: Flat Device Tree
291 11:35:43.103712 output: Compression: uncompressed
292 11:35:43.103758 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:35:43.103805 output: Architecture: AArch64
294 11:35:43.103852 output: Hash algo: crc32
295 11:35:43.103897 output: Hash value: 0f8e4d2e
296 11:35:43.103942 output: Image 2 (ramdisk-1)
297 11:35:43.103987 output: Description: unavailable
298 11:35:43.104033 output: Created: Wed Jul 17 12:35:43 2024
299 11:35:43.104079 output: Type: RAMDisk Image
300 11:35:43.104125 output: Compression: uncompressed
301 11:35:43.104170 output: Data Size: 18717702 Bytes = 18279.01 KiB = 17.85 MiB
302 11:35:43.104216 output: Architecture: AArch64
303 11:35:43.104260 output: OS: Linux
304 11:35:43.104305 output: Load Address: unavailable
305 11:35:43.104351 output: Entry Point: unavailable
306 11:35:43.104396 output: Hash algo: crc32
307 11:35:43.104441 output: Hash value: f03c95fd
308 11:35:43.104486 output: Default Configuration: 'conf-1'
309 11:35:43.104531 output: Configuration 0 (conf-1)
310 11:35:43.104576 output: Description: mt8192-asurada-spherion-r0
311 11:35:43.104622 output: Kernel: kernel-1
312 11:35:43.104668 output: Init Ramdisk: ramdisk-1
313 11:35:43.104713 output: FDT: fdt-1
314 11:35:43.104775 output: Loadables: kernel-1
315 11:35:43.104833 output:
316 11:35:43.104929 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:35:43.105000 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:35:43.105072 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 11:35:43.105144 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 11:35:43.105199 No LXC device requested
321 11:35:43.105262 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:35:43.105330 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 11:35:43.105393 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:35:43.105445 Checking files for TFTP limit of 4294967296 bytes.
325 11:35:43.105796 end: 1 tftp-deploy (duration 00:00:38) [common]
326 11:35:43.105881 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:35:43.105956 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:35:43.106042 substitutions:
329 11:35:43.106107 - {DTB}: 14864619/tftp-deploy-s5l1j54j/dtb/mt8192-asurada-spherion-r0.dtb
330 11:35:43.106196 - {INITRD}: 14864619/tftp-deploy-s5l1j54j/ramdisk/ramdisk.cpio.gz
331 11:35:43.106247 - {KERNEL}: 14864619/tftp-deploy-s5l1j54j/kernel/Image
332 11:35:43.106297 - {LAVA_MAC}: None
333 11:35:43.106344 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741
334 11:35:43.106392 - {NFS_SERVER_IP}: 192.168.201.1
335 11:35:43.106439 - {PRESEED_CONFIG}: None
336 11:35:43.106494 - {PRESEED_LOCAL}: None
337 11:35:43.106542 - {RAMDISK}: 14864619/tftp-deploy-s5l1j54j/ramdisk/ramdisk.cpio.gz
338 11:35:43.106589 - {ROOT_PART}: None
339 11:35:43.106635 - {ROOT}: None
340 11:35:43.106682 - {SERVER_IP}: 192.168.201.1
341 11:35:43.106728 - {TEE}: None
342 11:35:43.106799 Parsed boot commands:
343 11:35:43.106861 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:35:43.107041 Parsed boot commands: tftpboot 192.168.201.1 14864619/tftp-deploy-s5l1j54j/kernel/image.itb 14864619/tftp-deploy-s5l1j54j/kernel/cmdline
345 11:35:43.107118 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:35:43.107189 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:35:43.107259 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:35:43.107328 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:35:43.107381 Not connected, no need to disconnect.
350 11:35:43.107444 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:35:43.107510 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:35:43.107578 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 11:35:43.110386 Setting prompt string to ['lava-test: # ']
354 11:35:43.110678 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:35:43.110768 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:35:43.110855 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:35:43.110953 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:35:43.111156 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 11:35:52.339950 >> Command sent successfully.
360 11:35:52.353923 Returned 0 in 9 seconds
361 11:35:52.354554 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:35:52.355644 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:35:52.356086 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:35:52.356448 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:35:52.356743 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:35:52.357046 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:35:52.358741 [Enter `^Ec?' for help]
369 11:35:53.789344
370 11:35:53.789594
371 11:35:53.789743 F0: 102B 0000
372 11:35:53.789889
373 11:35:53.790018 F3: 1001 0000 [0200]
374 11:35:53.792731
375 11:35:53.792978 F3: 1001 0000
376 11:35:53.793128
377 11:35:53.793256 F7: 102D 0000
378 11:35:53.793382
379 11:35:53.795658 F1: 0000 0000
380 11:35:53.795877
381 11:35:53.796042 V0: 0000 0000 [0001]
382 11:35:53.796195
383 11:35:53.799232 00: 0007 8000
384 11:35:53.799505
385 11:35:53.799711 01: 0000 0000
386 11:35:53.799907
387 11:35:53.802240 BP: 0C00 0209 [0000]
388 11:35:53.802626
389 11:35:53.802841 G0: 1182 0000
390 11:35:53.803030
391 11:35:53.805915 EC: 0000 0021 [4000]
392 11:35:53.806295
393 11:35:53.806565 S7: 0000 0000 [0000]
394 11:35:53.806812
395 11:35:53.810171 CC: 0000 0000 [0001]
396 11:35:53.810677
397 11:35:53.811006 T0: 0000 0040 [010F]
398 11:35:53.811307
399 11:35:53.811589 Jump to BL
400 11:35:53.813260
401 11:35:53.836604
402 11:35:53.837090
403 11:35:53.844067 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:35:53.847332 ARM64: Exception handlers installed.
405 11:35:53.850857 ARM64: Testing exception
406 11:35:53.854558 ARM64: Done test exception
407 11:35:53.861961 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:35:53.873210 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:35:53.876134 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:35:53.888161 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:35:53.895289 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:35:53.902231 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:35:53.913692 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:35:53.921094 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:35:53.940349 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:35:53.943504 WDT: Last reset was cold boot
417 11:35:53.947625 SPI1(PAD0) initialized at 2873684 Hz
418 11:35:53.951194 SPI5(PAD0) initialized at 992727 Hz
419 11:35:53.951666 VBOOT: Loading verstage.
420 11:35:53.958713 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:35:53.962426 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:35:53.966770 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:35:53.969625 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:35:53.977340 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:35:53.984299 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:35:53.995031 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
427 11:35:53.995631
428 11:35:53.995975
429 11:35:54.006188 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:35:54.006694 ARM64: Exception handlers installed.
431 11:35:54.009833 ARM64: Testing exception
432 11:35:54.013371 ARM64: Done test exception
433 11:35:54.017422 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:35:54.020875 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:35:54.035813 Probing TPM: . done!
436 11:35:54.036318 TPM ready after 0 ms
437 11:35:54.042842 Connected to device vid:did:rid of 1ae0:0028:00
438 11:35:54.049698 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:35:54.110868 Initialized TPM device CR50 revision 0
440 11:35:54.124505 tlcl_send_startup: Startup return code is 0
441 11:35:54.124948 TPM: setup succeeded
442 11:35:54.138634 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:35:54.146766 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:35:54.157152 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:35:54.165666 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:35:54.171423 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:35:54.172164 in-header: 03 07 00 00 08 00 00 00
448 11:35:54.175515 in-data: aa e4 47 04 13 02 00 00
449 11:35:54.178481 Chrome EC: UHEPI supported
450 11:35:54.185454 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:35:54.189115 in-header: 03 a9 00 00 08 00 00 00
452 11:35:54.192118 in-data: 84 60 60 08 00 00 00 00
453 11:35:54.192285 Phase 1
454 11:35:54.195411 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:35:54.201748 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:35:54.209157 VB2:vb2_check_recovery() Recovery was requested manually
457 11:35:54.211911 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:35:54.215469 Recovery requested (1009000e)
459 11:35:54.223554 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:35:54.229019 tlcl_extend: response is 0
461 11:35:54.236932 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:35:54.242296 tlcl_extend: response is 0
463 11:35:54.249511 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:35:54.270076 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
465 11:35:54.276550 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:35:54.276837
467 11:35:54.277049
468 11:35:54.286783 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:35:54.290538 ARM64: Exception handlers installed.
470 11:35:54.293026 ARM64: Testing exception
471 11:35:54.293448 ARM64: Done test exception
472 11:35:54.315400 pmic_efuse_setting: Set efuses in 11 msecs
473 11:35:54.318828 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:35:54.325318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:35:54.328577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:35:54.335515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:35:54.338672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:35:54.345627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:35:54.348651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:35:54.352059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:35:54.358719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:35:54.362079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:35:54.369016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:35:54.372101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:35:54.375214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:35:54.381737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:35:54.388394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:35:54.392116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:35:54.398419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:35:54.405427 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:35:54.411837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:35:54.415489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:35:54.421723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:35:54.425493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:35:54.432837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:35:54.436660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:35:54.443320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:35:54.450821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:35:54.454181 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:35:54.460925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:35:54.464366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:35:54.470682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:35:54.474407 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:35:54.481583 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:35:54.484813 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:35:54.488172 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:35:54.495168 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:35:54.498402 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:35:54.504974 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:35:54.508016 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:35:54.514538 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:35:54.518563 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:35:54.521378 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:35:54.527835 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:35:54.531257 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:35:54.535091 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:35:54.541422 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:35:54.544539 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:35:54.548216 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:35:54.555157 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:35:54.558522 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:35:54.561376 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:35:54.564811 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:35:54.571252 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:35:54.578150 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:35:54.587838 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:35:54.591159 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:35:54.598172 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:35:54.608287 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:35:54.611353 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:35:54.618189 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:35:54.621304 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:35:54.628076 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x37
534 11:35:54.634658 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:35:54.637794 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:35:54.641121 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:35:54.653361 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 11:35:54.656195 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 11:35:54.662813 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 11:35:54.666463 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
541 11:35:54.669636 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 11:35:54.673062 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
543 11:35:54.675746 ADC[4]: Raw value=897780 ID=7
544 11:35:54.679781 ADC[3]: Raw value=213070 ID=1
545 11:35:54.680165 RAM Code: 0x71
546 11:35:54.686250 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 11:35:54.689090 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 11:35:54.699284 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 11:35:54.706543 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 11:35:54.709517 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 11:35:54.712385 in-header: 03 07 00 00 08 00 00 00
552 11:35:54.715741 in-data: aa e4 47 04 13 02 00 00
553 11:35:54.719079 Chrome EC: UHEPI supported
554 11:35:54.725776 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 11:35:54.729305 in-header: 03 a9 00 00 08 00 00 00
556 11:35:54.732416 in-data: 84 60 60 08 00 00 00 00
557 11:35:54.735805 MRC: failed to locate region type 0.
558 11:35:54.742917 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 11:35:54.745741 DRAM-K: Running full calibration
560 11:35:54.752772 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 11:35:54.753175 header.status = 0x0
562 11:35:54.755947 header.version = 0x6 (expected: 0x6)
563 11:35:54.759191 header.size = 0xd00 (expected: 0xd00)
564 11:35:54.762458 header.flags = 0x0
565 11:35:54.769540 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 11:35:54.785419 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 11:35:54.791945 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 11:35:54.795249 dram_init: ddr_geometry: 2
569 11:35:54.799187 [EMI] MDL number = 2
570 11:35:54.799671 [EMI] Get MDL freq = 0
571 11:35:54.801733 dram_init: ddr_type: 0
572 11:35:54.802158 is_discrete_lpddr4: 1
573 11:35:54.805673 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 11:35:54.806066
575 11:35:54.806500
576 11:35:54.808494 [Bian_co] ETT version 0.0.0.1
577 11:35:54.815413 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 11:35:54.815812
579 11:35:54.819131 dramc_set_vcore_voltage set vcore to 650000
580 11:35:54.819531 Read voltage for 800, 4
581 11:35:54.822028 Vio18 = 0
582 11:35:54.822459 Vcore = 650000
583 11:35:54.822853 Vdram = 0
584 11:35:54.825319 Vddq = 0
585 11:35:54.825714 Vmddr = 0
586 11:35:54.829003 dram_init: config_dvfs: 1
587 11:35:54.832155 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 11:35:54.838833 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 11:35:54.841773 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 11:35:54.845299 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 11:35:54.848572 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 11:35:54.852149 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 11:35:54.855233 MEM_TYPE=3, freq_sel=18
594 11:35:54.858722 sv_algorithm_assistance_LP4_1600
595 11:35:54.862410 ============ PULL DRAM RESETB DOWN ============
596 11:35:54.865616 ========== PULL DRAM RESETB DOWN end =========
597 11:35:54.872631 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 11:35:54.875396 ===================================
599 11:35:54.875821 LPDDR4 DRAM CONFIGURATION
600 11:35:54.878770 ===================================
601 11:35:54.882046 EX_ROW_EN[0] = 0x0
602 11:35:54.885753 EX_ROW_EN[1] = 0x0
603 11:35:54.885828 LP4Y_EN = 0x0
604 11:35:54.888776 WORK_FSP = 0x0
605 11:35:54.888856 WL = 0x2
606 11:35:54.892207 RL = 0x2
607 11:35:54.892286 BL = 0x2
608 11:35:54.895334 RPST = 0x0
609 11:35:54.895444 RD_PRE = 0x0
610 11:35:54.898356 WR_PRE = 0x1
611 11:35:54.898456 WR_PST = 0x0
612 11:35:54.901688 DBI_WR = 0x0
613 11:35:54.901781 DBI_RD = 0x0
614 11:35:54.905180 OTF = 0x1
615 11:35:54.908401 ===================================
616 11:35:54.911869 ===================================
617 11:35:54.911981 ANA top config
618 11:35:54.915285 ===================================
619 11:35:54.918375 DLL_ASYNC_EN = 0
620 11:35:54.922128 ALL_SLAVE_EN = 1
621 11:35:54.925522 NEW_RANK_MODE = 1
622 11:35:54.925600 DLL_IDLE_MODE = 1
623 11:35:54.928526 LP45_APHY_COMB_EN = 1
624 11:35:54.931877 TX_ODT_DIS = 1
625 11:35:54.935220 NEW_8X_MODE = 1
626 11:35:54.938845 ===================================
627 11:35:54.941581 ===================================
628 11:35:54.944860 data_rate = 1600
629 11:35:54.944938 CKR = 1
630 11:35:54.948767 DQ_P2S_RATIO = 8
631 11:35:54.951433 ===================================
632 11:35:54.954909 CA_P2S_RATIO = 8
633 11:35:54.958349 DQ_CA_OPEN = 0
634 11:35:54.961645 DQ_SEMI_OPEN = 0
635 11:35:54.961722 CA_SEMI_OPEN = 0
636 11:35:54.964849 CA_FULL_RATE = 0
637 11:35:54.968208 DQ_CKDIV4_EN = 1
638 11:35:54.971974 CA_CKDIV4_EN = 1
639 11:35:54.975335 CA_PREDIV_EN = 0
640 11:35:54.978326 PH8_DLY = 0
641 11:35:54.978404 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 11:35:54.981992 DQ_AAMCK_DIV = 4
643 11:35:54.984928 CA_AAMCK_DIV = 4
644 11:35:54.988224 CA_ADMCK_DIV = 4
645 11:35:54.991714 DQ_TRACK_CA_EN = 0
646 11:35:54.995215 CA_PICK = 800
647 11:35:54.995293 CA_MCKIO = 800
648 11:35:54.998471 MCKIO_SEMI = 0
649 11:35:55.001884 PLL_FREQ = 3068
650 11:35:55.005035 DQ_UI_PI_RATIO = 32
651 11:35:55.008208 CA_UI_PI_RATIO = 0
652 11:35:55.011761 ===================================
653 11:35:55.015136 ===================================
654 11:35:55.018499 memory_type:LPDDR4
655 11:35:55.018577 GP_NUM : 10
656 11:35:55.021541 SRAM_EN : 1
657 11:35:55.021618 MD32_EN : 0
658 11:35:55.025276 ===================================
659 11:35:55.028264 [ANA_INIT] >>>>>>>>>>>>>>
660 11:35:55.031849 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 11:35:55.035142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 11:35:55.038844 ===================================
663 11:35:55.041651 data_rate = 1600,PCW = 0X7600
664 11:35:55.045227 ===================================
665 11:35:55.048949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:35:55.051743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 11:35:55.058747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 11:35:55.065008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 11:35:55.068558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 11:35:55.071602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 11:35:55.071691 [ANA_INIT] flow start
672 11:35:55.074822 [ANA_INIT] PLL >>>>>>>>
673 11:35:55.078676 [ANA_INIT] PLL <<<<<<<<
674 11:35:55.078782 [ANA_INIT] MIDPI >>>>>>>>
675 11:35:55.082066 [ANA_INIT] MIDPI <<<<<<<<
676 11:35:55.085972 [ANA_INIT] DLL >>>>>>>>
677 11:35:55.086049 [ANA_INIT] flow end
678 11:35:55.089598 ============ LP4 DIFF to SE enter ============
679 11:35:55.093416 ============ LP4 DIFF to SE exit ============
680 11:35:55.096913 [ANA_INIT] <<<<<<<<<<<<<
681 11:35:55.100441 [Flow] Enable top DCM control >>>>>
682 11:35:55.104274 [Flow] Enable top DCM control <<<<<
683 11:35:55.108051 Enable DLL master slave shuffle
684 11:35:55.112114 ==============================================================
685 11:35:55.112189 Gating Mode config
686 11:35:55.119295 ==============================================================
687 11:35:55.122408 Config description:
688 11:35:55.128867 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 11:35:55.136129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 11:35:55.142640 SELPH_MODE 0: By rank 1: By Phase
691 11:35:55.149237 ==============================================================
692 11:35:55.149311 GAT_TRACK_EN = 1
693 11:35:55.152077 RX_GATING_MODE = 2
694 11:35:55.155694 RX_GATING_TRACK_MODE = 2
695 11:35:55.159069 SELPH_MODE = 1
696 11:35:55.162259 PICG_EARLY_EN = 1
697 11:35:55.165416 VALID_LAT_VALUE = 1
698 11:35:55.172124 ==============================================================
699 11:35:55.175648 Enter into Gating configuration >>>>
700 11:35:55.178880 Exit from Gating configuration <<<<
701 11:35:55.182119 Enter into DVFS_PRE_config >>>>>
702 11:35:55.192072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 11:35:55.195628 Exit from DVFS_PRE_config <<<<<
704 11:35:55.198648 Enter into PICG configuration >>>>
705 11:35:55.202209 Exit from PICG configuration <<<<
706 11:35:55.205332 [RX_INPUT] configuration >>>>>
707 11:35:55.205408 [RX_INPUT] configuration <<<<<
708 11:35:55.212115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 11:35:55.218740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 11:35:55.222123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 11:35:55.228789 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 11:35:55.235729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 11:35:55.242444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 11:35:55.245485 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 11:35:55.249236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 11:35:55.255768 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 11:35:55.258594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 11:35:55.262083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 11:35:55.265597 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 11:35:55.268718 ===================================
721 11:35:55.272005 LPDDR4 DRAM CONFIGURATION
722 11:35:55.275535 ===================================
723 11:35:55.279175 EX_ROW_EN[0] = 0x0
724 11:35:55.279251 EX_ROW_EN[1] = 0x0
725 11:35:55.281978 LP4Y_EN = 0x0
726 11:35:55.282077 WORK_FSP = 0x0
727 11:35:55.285465 WL = 0x2
728 11:35:55.285539 RL = 0x2
729 11:35:55.289388 BL = 0x2
730 11:35:55.289463 RPST = 0x0
731 11:35:55.292728 RD_PRE = 0x0
732 11:35:55.292803 WR_PRE = 0x1
733 11:35:55.296006 WR_PST = 0x0
734 11:35:55.296081 DBI_WR = 0x0
735 11:35:55.298725 DBI_RD = 0x0
736 11:35:55.298800 OTF = 0x1
737 11:35:55.302500 ===================================
738 11:35:55.309338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 11:35:55.312523 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 11:35:55.315750 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 11:35:55.318881 ===================================
742 11:35:55.322460 LPDDR4 DRAM CONFIGURATION
743 11:35:55.325853 ===================================
744 11:35:55.329274 EX_ROW_EN[0] = 0x10
745 11:35:55.329386 EX_ROW_EN[1] = 0x0
746 11:35:55.332362 LP4Y_EN = 0x0
747 11:35:55.332514 WORK_FSP = 0x0
748 11:35:55.335810 WL = 0x2
749 11:35:55.336236 RL = 0x2
750 11:35:55.339208 BL = 0x2
751 11:35:55.339640 RPST = 0x0
752 11:35:55.342730 RD_PRE = 0x0
753 11:35:55.343155 WR_PRE = 0x1
754 11:35:55.345481 WR_PST = 0x0
755 11:35:55.345557 DBI_WR = 0x0
756 11:35:55.349088 DBI_RD = 0x0
757 11:35:55.349169 OTF = 0x1
758 11:35:55.352411 ===================================
759 11:35:55.359179 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 11:35:55.363475 nWR fixed to 40
761 11:35:55.367258 [ModeRegInit_LP4] CH0 RK0
762 11:35:55.367361 [ModeRegInit_LP4] CH0 RK1
763 11:35:55.370548 [ModeRegInit_LP4] CH1 RK0
764 11:35:55.373617 [ModeRegInit_LP4] CH1 RK1
765 11:35:55.373743 match AC timing 13
766 11:35:55.380009 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 11:35:55.383494 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 11:35:55.386887 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 11:35:55.393616 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 11:35:55.396624 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 11:35:55.396847 [EMI DOE] emi_dcm 0
772 11:35:55.403803 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 11:35:55.404221 ==
774 11:35:55.407455 Dram Type= 6, Freq= 0, CH_0, rank 0
775 11:35:55.410260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 11:35:55.410720 ==
777 11:35:55.416773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 11:35:55.423279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 11:35:55.431112 [CA 0] Center 38 (7~69) winsize 63
780 11:35:55.434414 [CA 1] Center 37 (7~68) winsize 62
781 11:35:55.437719 [CA 2] Center 35 (5~66) winsize 62
782 11:35:55.441517 [CA 3] Center 35 (5~66) winsize 62
783 11:35:55.444633 [CA 4] Center 34 (4~65) winsize 62
784 11:35:55.448018 [CA 5] Center 34 (4~65) winsize 62
785 11:35:55.448498
786 11:35:55.451676 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 11:35:55.452105
788 11:35:55.454529 [CATrainingPosCal] consider 1 rank data
789 11:35:55.458193 u2DelayCellTimex100 = 270/100 ps
790 11:35:55.461255 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 11:35:55.464921 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 11:35:55.471391 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 11:35:55.474656 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 11:35:55.478684 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 11:35:55.481800 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 11:35:55.482239
797 11:35:55.485307 CA PerBit enable=1, Macro0, CA PI delay=34
798 11:35:55.485733
799 11:35:55.488687 [CBTSetCACLKResult] CA Dly = 34
800 11:35:55.489142 CS Dly: 6 (0~37)
801 11:35:55.489774 ==
802 11:35:55.492448 Dram Type= 6, Freq= 0, CH_0, rank 1
803 11:35:55.495191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:35:55.498973 ==
805 11:35:55.501695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 11:35:55.508762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 11:35:55.517961 [CA 0] Center 38 (7~69) winsize 63
808 11:35:55.521049 [CA 1] Center 38 (7~69) winsize 63
809 11:35:55.524439 [CA 2] Center 35 (5~66) winsize 62
810 11:35:55.527418 [CA 3] Center 35 (5~66) winsize 62
811 11:35:55.530824 [CA 4] Center 34 (4~65) winsize 62
812 11:35:55.534263 [CA 5] Center 34 (4~65) winsize 62
813 11:35:55.534859
814 11:35:55.537542 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 11:35:55.537982
816 11:35:55.540770 [CATrainingPosCal] consider 2 rank data
817 11:35:55.544351 u2DelayCellTimex100 = 270/100 ps
818 11:35:55.547744 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 11:35:55.550822 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 11:35:55.557695 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 11:35:55.561011 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 11:35:55.564343 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 11:35:55.567538 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 11:35:55.568099
825 11:35:55.570735 CA PerBit enable=1, Macro0, CA PI delay=34
826 11:35:55.571156
827 11:35:55.574087 [CBTSetCACLKResult] CA Dly = 34
828 11:35:55.574521 CS Dly: 6 (0~38)
829 11:35:55.574817
830 11:35:55.577186 ----->DramcWriteLeveling(PI) begin...
831 11:35:55.580700 ==
832 11:35:55.583925 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:35:55.587408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 11:35:55.587795 ==
835 11:35:55.590583 Write leveling (Byte 0): 32 => 32
836 11:35:55.594197 Write leveling (Byte 1): 31 => 31
837 11:35:55.597520 DramcWriteLeveling(PI) end<-----
838 11:35:55.597907
839 11:35:55.598256 ==
840 11:35:55.600632 Dram Type= 6, Freq= 0, CH_0, rank 0
841 11:35:55.603951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 11:35:55.604444 ==
843 11:35:55.607252 [Gating] SW mode calibration
844 11:35:55.614237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 11:35:55.617591 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 11:35:55.623940 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 11:35:55.627339 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 11:35:55.630750 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 11:35:55.637258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 11:35:55.641166 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:35:55.644207 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:35:55.650665 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:35:55.653846 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:35:55.657086 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:35:55.664504 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:35:55.667506 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:35:55.671085 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:35:55.677558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:35:55.681148 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:35:55.684675 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:35:55.688183 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:35:55.694859 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:35:55.697785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:35:55.701445 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
865 11:35:55.707674 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
866 11:35:55.711274 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:35:55.714417 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:35:55.720945 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:35:55.724843 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:35:55.727656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:35:55.734645 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:35:55.738314 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:35:55.741708 0 9 12 | B1->B0 | 2626 3232 | 0 1 | (0 0) (0 0)
874 11:35:55.747791 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 11:35:55.751090 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 11:35:55.754806 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 11:35:55.761138 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 11:35:55.764523 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:35:55.767892 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:35:55.774320 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
881 11:35:55.778021 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (1 0)
882 11:35:55.781401 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 11:35:55.785004 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 11:35:55.790598 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 11:35:55.793938 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:35:55.797586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:35:55.804427 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:35:55.808143 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
889 11:35:55.811013 0 11 12 | B1->B0 | 3535 4343 | 1 0 | (0 0) (0 0)
890 11:35:55.817647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:35:55.821234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 11:35:55.824395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:35:55.831169 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:35:55.834968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:35:55.838137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:35:55.844269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 11:35:55.847860 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:35:55.851346 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:35:55.857820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:35:55.861380 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:35:55.864592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:35:55.867907 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:35:55.874567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:35:55.878042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:35:55.881550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:35:55.887977 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:35:55.891290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:35:55.894411 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:35:55.901200 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:35:55.904697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:35:55.907807 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:35:55.914767 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
913 11:35:55.915153 Total UI for P1: 0, mck2ui 16
914 11:35:55.921102 best dqsien dly found for B0: ( 0, 14, 6)
915 11:35:55.924198 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 11:35:55.927419 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:35:55.931303 Total UI for P1: 0, mck2ui 16
918 11:35:55.934138 best dqsien dly found for B1: ( 0, 14, 12)
919 11:35:55.938096 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
920 11:35:55.941034 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 11:35:55.941416
922 11:35:55.947422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
923 11:35:55.950740 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 11:35:55.951127 [Gating] SW calibration Done
925 11:35:55.954156 ==
926 11:35:55.957158 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:35:55.961353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:35:55.961739 ==
929 11:35:55.962038 RX Vref Scan: 0
930 11:35:55.962372
931 11:35:55.964166 RX Vref 0 -> 0, step: 1
932 11:35:55.964550
933 11:35:55.967539 RX Delay -130 -> 252, step: 16
934 11:35:55.970658 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
935 11:35:55.974383 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
936 11:35:55.980748 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
937 11:35:55.984191 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
938 11:35:55.987553 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
939 11:35:55.991017 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
940 11:35:55.994083 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
941 11:35:55.997858 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
942 11:35:56.004266 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
943 11:35:56.007366 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
944 11:35:56.010942 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
945 11:35:56.014147 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
946 11:35:56.018023 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
947 11:35:56.024543 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
948 11:35:56.027848 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
949 11:35:56.031173 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
950 11:35:56.031746 ==
951 11:35:56.034371 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:35:56.037467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 11:35:56.037896 ==
954 11:35:56.040858 DQS Delay:
955 11:35:56.041281 DQS0 = 0, DQS1 = 0
956 11:35:56.044445 DQM Delay:
957 11:35:56.044864 DQM0 = 81, DQM1 = 70
958 11:35:56.045192 DQ Delay:
959 11:35:56.047559 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
960 11:35:56.051058 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
961 11:35:56.054483 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 11:35:56.057875 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 11:35:56.058350
964 11:35:56.058685
965 11:35:56.060908 ==
966 11:35:56.064301 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:35:56.067657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:35:56.068084 ==
969 11:35:56.068411
970 11:35:56.068710
971 11:35:56.070858 TX Vref Scan disable
972 11:35:56.071282 == TX Byte 0 ==
973 11:35:56.074060 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
974 11:35:56.081074 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
975 11:35:56.081503 == TX Byte 1 ==
976 11:35:56.084552 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 11:35:56.090950 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 11:35:56.091204 ==
979 11:35:56.093707 Dram Type= 6, Freq= 0, CH_0, rank 0
980 11:35:56.096908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 11:35:56.097084 ==
982 11:35:56.110550 TX Vref=22, minBit 1, minWin=26, winSum=430
983 11:35:56.113384 TX Vref=24, minBit 14, minWin=26, winSum=437
984 11:35:56.116876 TX Vref=26, minBit 0, minWin=27, winSum=439
985 11:35:56.120267 TX Vref=28, minBit 5, minWin=27, winSum=442
986 11:35:56.123951 TX Vref=30, minBit 9, minWin=27, winSum=442
987 11:35:56.130587 TX Vref=32, minBit 10, minWin=26, winSum=440
988 11:35:56.133678 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 28
989 11:35:56.133797
990 11:35:56.136789 Final TX Range 1 Vref 28
991 11:35:56.136893
992 11:35:56.136986 ==
993 11:35:56.140509 Dram Type= 6, Freq= 0, CH_0, rank 0
994 11:35:56.143876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 11:35:56.143964 ==
996 11:35:56.147113
997 11:35:56.147198
998 11:35:56.147265 TX Vref Scan disable
999 11:35:56.150426 == TX Byte 0 ==
1000 11:35:56.153863 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1001 11:35:56.160468 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1002 11:35:56.160569 == TX Byte 1 ==
1003 11:35:56.163848 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 11:35:56.166851 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 11:35:56.170243
1006 11:35:56.170367 [DATLAT]
1007 11:35:56.170465 Freq=800, CH0 RK0
1008 11:35:56.170555
1009 11:35:56.173839 DATLAT Default: 0xa
1010 11:35:56.173978 0, 0xFFFF, sum = 0
1011 11:35:56.177438 1, 0xFFFF, sum = 0
1012 11:35:56.177607 2, 0xFFFF, sum = 0
1013 11:35:56.180732 3, 0xFFFF, sum = 0
1014 11:35:56.180895 4, 0xFFFF, sum = 0
1015 11:35:56.184024 5, 0xFFFF, sum = 0
1016 11:35:56.187125 6, 0xFFFF, sum = 0
1017 11:35:56.187313 7, 0xFFFF, sum = 0
1018 11:35:56.190368 8, 0xFFFF, sum = 0
1019 11:35:56.190594 9, 0x0, sum = 1
1020 11:35:56.190769 10, 0x0, sum = 2
1021 11:35:56.194216 11, 0x0, sum = 3
1022 11:35:56.194500 12, 0x0, sum = 4
1023 11:35:56.197075 best_step = 10
1024 11:35:56.197415
1025 11:35:56.197704 ==
1026 11:35:56.200808 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 11:35:56.204649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 11:35:56.205118 ==
1029 11:35:56.207117 RX Vref Scan: 1
1030 11:35:56.207501
1031 11:35:56.207800 Set Vref Range= 32 -> 127
1032 11:35:56.210763
1033 11:35:56.211146 RX Vref 32 -> 127, step: 1
1034 11:35:56.211447
1035 11:35:56.213941 RX Delay -111 -> 252, step: 8
1036 11:35:56.214370
1037 11:35:56.217573 Set Vref, RX VrefLevel [Byte0]: 32
1038 11:35:56.220527 [Byte1]: 32
1039 11:35:56.220933
1040 11:35:56.224048 Set Vref, RX VrefLevel [Byte0]: 33
1041 11:35:56.227171 [Byte1]: 33
1042 11:35:56.231019
1043 11:35:56.231404 Set Vref, RX VrefLevel [Byte0]: 34
1044 11:35:56.234553 [Byte1]: 34
1045 11:35:56.239128
1046 11:35:56.239554 Set Vref, RX VrefLevel [Byte0]: 35
1047 11:35:56.242073 [Byte1]: 35
1048 11:35:56.246371
1049 11:35:56.246864 Set Vref, RX VrefLevel [Byte0]: 36
1050 11:35:56.249603 [Byte1]: 36
1051 11:35:56.253910
1052 11:35:56.254358 Set Vref, RX VrefLevel [Byte0]: 37
1053 11:35:56.257807 [Byte1]: 37
1054 11:35:56.261986
1055 11:35:56.262429 Set Vref, RX VrefLevel [Byte0]: 38
1056 11:35:56.265368 [Byte1]: 38
1057 11:35:56.269899
1058 11:35:56.270397 Set Vref, RX VrefLevel [Byte0]: 39
1059 11:35:56.272718 [Byte1]: 39
1060 11:35:56.277688
1061 11:35:56.278252 Set Vref, RX VrefLevel [Byte0]: 40
1062 11:35:56.280834 [Byte1]: 40
1063 11:35:56.284477
1064 11:35:56.284862 Set Vref, RX VrefLevel [Byte0]: 41
1065 11:35:56.288028 [Byte1]: 41
1066 11:35:56.292297
1067 11:35:56.292685 Set Vref, RX VrefLevel [Byte0]: 42
1068 11:35:56.296321 [Byte1]: 42
1069 11:35:56.300147
1070 11:35:56.300529 Set Vref, RX VrefLevel [Byte0]: 43
1071 11:35:56.303548 [Byte1]: 43
1072 11:35:56.307469
1073 11:35:56.307854 Set Vref, RX VrefLevel [Byte0]: 44
1074 11:35:56.310698 [Byte1]: 44
1075 11:35:56.314976
1076 11:35:56.315050 Set Vref, RX VrefLevel [Byte0]: 45
1077 11:35:56.318824 [Byte1]: 45
1078 11:35:56.322836
1079 11:35:56.322910 Set Vref, RX VrefLevel [Byte0]: 46
1080 11:35:56.325921 [Byte1]: 46
1081 11:35:56.330161
1082 11:35:56.330236 Set Vref, RX VrefLevel [Byte0]: 47
1083 11:35:56.333584 [Byte1]: 47
1084 11:35:56.337685
1085 11:35:56.337761 Set Vref, RX VrefLevel [Byte0]: 48
1086 11:35:56.341533 [Byte1]: 48
1087 11:35:56.345710
1088 11:35:56.345784 Set Vref, RX VrefLevel [Byte0]: 49
1089 11:35:56.349060 [Byte1]: 49
1090 11:35:56.353235
1091 11:35:56.353313 Set Vref, RX VrefLevel [Byte0]: 50
1092 11:35:56.356881 [Byte1]: 50
1093 11:35:56.360808
1094 11:35:56.360888 Set Vref, RX VrefLevel [Byte0]: 51
1095 11:35:56.364185 [Byte1]: 51
1096 11:35:56.368934
1097 11:35:56.369008 Set Vref, RX VrefLevel [Byte0]: 52
1098 11:35:56.371939 [Byte1]: 52
1099 11:35:56.376323
1100 11:35:56.376402 Set Vref, RX VrefLevel [Byte0]: 53
1101 11:35:56.379427 [Byte1]: 53
1102 11:35:56.383877
1103 11:35:56.383970 Set Vref, RX VrefLevel [Byte0]: 54
1104 11:35:56.386958 [Byte1]: 54
1105 11:35:56.391267
1106 11:35:56.391342 Set Vref, RX VrefLevel [Byte0]: 55
1107 11:35:56.395161 [Byte1]: 55
1108 11:35:56.399448
1109 11:35:56.399534 Set Vref, RX VrefLevel [Byte0]: 56
1110 11:35:56.402781 [Byte1]: 56
1111 11:35:56.406746
1112 11:35:56.406839 Set Vref, RX VrefLevel [Byte0]: 57
1113 11:35:56.410145 [Byte1]: 57
1114 11:35:56.414818
1115 11:35:56.414986 Set Vref, RX VrefLevel [Byte0]: 58
1116 11:35:56.417790 [Byte1]: 58
1117 11:35:56.422449
1118 11:35:56.422670 Set Vref, RX VrefLevel [Byte0]: 59
1119 11:35:56.425690 [Byte1]: 59
1120 11:35:56.429940
1121 11:35:56.430186 Set Vref, RX VrefLevel [Byte0]: 60
1122 11:35:56.433071 [Byte1]: 60
1123 11:35:56.437255
1124 11:35:56.437440 Set Vref, RX VrefLevel [Byte0]: 61
1125 11:35:56.440872 [Byte1]: 61
1126 11:35:56.444988
1127 11:35:56.445263 Set Vref, RX VrefLevel [Byte0]: 62
1128 11:35:56.448693 [Byte1]: 62
1129 11:35:56.452978
1130 11:35:56.453423 Set Vref, RX VrefLevel [Byte0]: 63
1131 11:35:56.456718 [Byte1]: 63
1132 11:35:56.460555
1133 11:35:56.461056 Set Vref, RX VrefLevel [Byte0]: 64
1134 11:35:56.463954 [Byte1]: 64
1135 11:35:56.468024
1136 11:35:56.468448 Set Vref, RX VrefLevel [Byte0]: 65
1137 11:35:56.471570 [Byte1]: 65
1138 11:35:56.476122
1139 11:35:56.476557 Set Vref, RX VrefLevel [Byte0]: 66
1140 11:35:56.479406 [Byte1]: 66
1141 11:35:56.484052
1142 11:35:56.484476 Set Vref, RX VrefLevel [Byte0]: 67
1143 11:35:56.486975 [Byte1]: 67
1144 11:35:56.491648
1145 11:35:56.492146 Set Vref, RX VrefLevel [Byte0]: 68
1146 11:35:56.494832 [Byte1]: 68
1147 11:35:56.499468
1148 11:35:56.500135 Set Vref, RX VrefLevel [Byte0]: 69
1149 11:35:56.502034 [Byte1]: 69
1150 11:35:56.506875
1151 11:35:56.507302 Set Vref, RX VrefLevel [Byte0]: 70
1152 11:35:56.509902 [Byte1]: 70
1153 11:35:56.514447
1154 11:35:56.514928 Set Vref, RX VrefLevel [Byte0]: 71
1155 11:35:56.517387 [Byte1]: 71
1156 11:35:56.522076
1157 11:35:56.525080 Set Vref, RX VrefLevel [Byte0]: 72
1158 11:35:56.528214 [Byte1]: 72
1159 11:35:56.528709
1160 11:35:56.531877 Set Vref, RX VrefLevel [Byte0]: 73
1161 11:35:56.534830 [Byte1]: 73
1162 11:35:56.535255
1163 11:35:56.538479 Set Vref, RX VrefLevel [Byte0]: 74
1164 11:35:56.541875 [Byte1]: 74
1165 11:35:56.542442
1166 11:35:56.545084 Set Vref, RX VrefLevel [Byte0]: 75
1167 11:35:56.548438 [Byte1]: 75
1168 11:35:56.552241
1169 11:35:56.552743 Set Vref, RX VrefLevel [Byte0]: 76
1170 11:35:56.556104 [Byte1]: 76
1171 11:35:56.560210
1172 11:35:56.560710 Set Vref, RX VrefLevel [Byte0]: 77
1173 11:35:56.563766 [Byte1]: 77
1174 11:35:56.568102
1175 11:35:56.568531 Set Vref, RX VrefLevel [Byte0]: 78
1176 11:35:56.570850 [Byte1]: 78
1177 11:35:56.575281
1178 11:35:56.575768 Set Vref, RX VrefLevel [Byte0]: 79
1179 11:35:56.578715 [Byte1]: 79
1180 11:35:56.582835
1181 11:35:56.583356 Set Vref, RX VrefLevel [Byte0]: 80
1182 11:35:56.586569 [Byte1]: 80
1183 11:35:56.590470
1184 11:35:56.590877 Final RX Vref Byte 0 = 59 to rank0
1185 11:35:56.594135 Final RX Vref Byte 1 = 57 to rank0
1186 11:35:56.597191 Final RX Vref Byte 0 = 59 to rank1
1187 11:35:56.600504 Final RX Vref Byte 1 = 57 to rank1==
1188 11:35:56.604236 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 11:35:56.610604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 11:35:56.611243 ==
1191 11:35:56.611904 DQS Delay:
1192 11:35:56.612467 DQS0 = 0, DQS1 = 0
1193 11:35:56.614699 DQM Delay:
1194 11:35:56.615126 DQM0 = 82, DQM1 = 68
1195 11:35:56.617295 DQ Delay:
1196 11:35:56.620418 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1197 11:35:56.620895 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1198 11:35:56.624065 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1199 11:35:56.630339 DQ12 =76, DQ13 =68, DQ14 =80, DQ15 =76
1200 11:35:56.630773
1201 11:35:56.631080
1202 11:35:56.637211 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1203 11:35:56.640537 CH0 RK0: MR19=606, MR18=2A29
1204 11:35:56.647393 CH0_RK0: MR19=0x606, MR18=0x2A29, DQSOSC=399, MR23=63, INC=92, DEC=61
1205 11:35:56.647970
1206 11:35:56.650896 ----->DramcWriteLeveling(PI) begin...
1207 11:35:56.651286 ==
1208 11:35:56.653653 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 11:35:56.656993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 11:35:56.657382 ==
1211 11:35:56.660282 Write leveling (Byte 0): 31 => 31
1212 11:35:56.663921 Write leveling (Byte 1): 32 => 32
1213 11:35:56.667127 DramcWriteLeveling(PI) end<-----
1214 11:35:56.667520
1215 11:35:56.668013 ==
1216 11:35:56.670798 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 11:35:56.674270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 11:35:56.674681 ==
1219 11:35:56.677042 [Gating] SW mode calibration
1220 11:35:56.683981 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 11:35:56.690842 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 11:35:56.693995 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 11:35:56.697142 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 11:35:56.703949 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 11:35:56.707002 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:35:56.751647 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:35:56.752190 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:35:56.752569 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:35:56.753081 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:35:56.753963 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:35:56.754405 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:35:56.754736 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:35:56.755037 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:35:56.755319 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:35:56.755660 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:35:56.795748 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:35:56.796652 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:35:56.797116 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:35:56.797480 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 11:35:56.797784 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1241 11:35:56.798073 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1242 11:35:56.798513 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:35:56.798808 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:35:56.799253 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:35:56.799690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:35:56.812309 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:35:56.813239 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1248 11:35:56.813636 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
1249 11:35:56.813952 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1250 11:35:56.815807 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:35:56.822993 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:35:56.825499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:35:56.829668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 11:35:56.835611 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 11:35:56.838791 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1256 11:35:56.842219 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
1257 11:35:56.849056 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1258 11:35:56.852653 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:35:56.855589 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:35:56.862537 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:35:56.865813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:35:56.869040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:35:56.875948 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1264 11:35:56.879009 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
1265 11:35:56.882420 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1266 11:35:56.886181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:35:56.892691 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:35:56.895733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:35:56.898965 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:35:56.905725 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:35:56.909299 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 11:35:56.912852 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1273 11:35:56.918796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:35:56.922687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:35:56.926042 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:35:56.932974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:35:56.935634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:35:56.938992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:35:56.945808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:35:56.949075 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:35:56.952417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:35:56.958826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:35:56.962397 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:35:56.965763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:35:56.972293 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:35:56.975505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:35:56.978758 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:35:56.985707 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1289 11:35:56.986290 Total UI for P1: 0, mck2ui 16
1290 11:35:56.988797 best dqsien dly found for B0: ( 0, 14, 6)
1291 11:35:56.995481 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1292 11:35:56.998788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 11:35:57.002556 Total UI for P1: 0, mck2ui 16
1294 11:35:57.006011 best dqsien dly found for B1: ( 0, 14, 10)
1295 11:35:57.009126 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1296 11:35:57.012313 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1297 11:35:57.012743
1298 11:35:57.016126 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 11:35:57.019209 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1300 11:35:57.022266 [Gating] SW calibration Done
1301 11:35:57.022695 ==
1302 11:35:57.025842 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 11:35:57.032076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 11:35:57.032658 ==
1305 11:35:57.033001 RX Vref Scan: 0
1306 11:35:57.033310
1307 11:35:57.035378 RX Vref 0 -> 0, step: 1
1308 11:35:57.035803
1309 11:35:57.038645 RX Delay -130 -> 252, step: 16
1310 11:35:57.042086 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1311 11:35:57.045981 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1312 11:35:57.048982 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1313 11:35:57.052358 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1314 11:35:57.058644 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1315 11:35:57.062268 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1316 11:35:57.065511 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1317 11:35:57.068845 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1318 11:35:57.072042 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1319 11:35:57.078866 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1320 11:35:57.082057 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1321 11:35:57.086207 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1322 11:35:57.089110 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1323 11:35:57.092193 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1324 11:35:57.098843 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1325 11:35:57.101832 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1326 11:35:57.102366 ==
1327 11:35:57.105611 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:35:57.109131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:35:57.109630 ==
1330 11:35:57.112209 DQS Delay:
1331 11:35:57.112640 DQS0 = 0, DQS1 = 0
1332 11:35:57.112973 DQM Delay:
1333 11:35:57.116008 DQM0 = 76, DQM1 = 69
1334 11:35:57.116505 DQ Delay:
1335 11:35:57.118778 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1336 11:35:57.122184 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1337 11:35:57.125432 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1338 11:35:57.129101 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1339 11:35:57.129710
1340 11:35:57.130052
1341 11:35:57.130432 ==
1342 11:35:57.132023 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:35:57.139058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:35:57.139490 ==
1345 11:35:57.139819
1346 11:35:57.140128
1347 11:35:57.140419 TX Vref Scan disable
1348 11:35:57.142606 == TX Byte 0 ==
1349 11:35:57.145976 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1350 11:35:57.152427 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1351 11:35:57.152928 == TX Byte 1 ==
1352 11:35:57.155541 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1353 11:35:57.162521 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1354 11:35:57.163008 ==
1355 11:35:57.165316 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 11:35:57.169103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 11:35:57.169601 ==
1358 11:35:57.181476 TX Vref=22, minBit 11, minWin=26, winSum=435
1359 11:35:57.184667 TX Vref=24, minBit 1, minWin=27, winSum=439
1360 11:35:57.188113 TX Vref=26, minBit 1, minWin=27, winSum=444
1361 11:35:57.191082 TX Vref=28, minBit 1, minWin=27, winSum=447
1362 11:35:57.194893 TX Vref=30, minBit 2, minWin=27, winSum=445
1363 11:35:57.201258 TX Vref=32, minBit 1, minWin=27, winSum=444
1364 11:35:57.205044 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1365 11:35:57.205473
1366 11:35:57.208001 Final TX Range 1 Vref 28
1367 11:35:57.208503
1368 11:35:57.208834 ==
1369 11:35:57.211535 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 11:35:57.214767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:35:57.215194 ==
1372 11:35:57.215522
1373 11:35:57.217716
1374 11:35:57.218179 TX Vref Scan disable
1375 11:35:57.221381 == TX Byte 0 ==
1376 11:35:57.224681 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1377 11:35:57.227972 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1378 11:35:57.231108 == TX Byte 1 ==
1379 11:35:57.234297 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1380 11:35:57.238000 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1381 11:35:57.240734
1382 11:35:57.241146 [DATLAT]
1383 11:35:57.241497 Freq=800, CH0 RK1
1384 11:35:57.241758
1385 11:35:57.244056 DATLAT Default: 0xa
1386 11:35:57.244352 0, 0xFFFF, sum = 0
1387 11:35:57.247439 1, 0xFFFF, sum = 0
1388 11:35:57.247750 2, 0xFFFF, sum = 0
1389 11:35:57.250786 3, 0xFFFF, sum = 0
1390 11:35:57.254438 4, 0xFFFF, sum = 0
1391 11:35:57.254733 5, 0xFFFF, sum = 0
1392 11:35:57.257237 6, 0xFFFF, sum = 0
1393 11:35:57.257661 7, 0xFFFF, sum = 0
1394 11:35:57.260849 8, 0xFFFF, sum = 0
1395 11:35:57.261141 9, 0x0, sum = 1
1396 11:35:57.261367 10, 0x0, sum = 2
1397 11:35:57.264384 11, 0x0, sum = 3
1398 11:35:57.264709 12, 0x0, sum = 4
1399 11:35:57.267251 best_step = 10
1400 11:35:57.267577
1401 11:35:57.267926 ==
1402 11:35:57.270807 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 11:35:57.273990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 11:35:57.274419 ==
1405 11:35:57.277334 RX Vref Scan: 0
1406 11:35:57.277701
1407 11:35:57.280588 RX Vref 0 -> 0, step: 1
1408 11:35:57.280877
1409 11:35:57.281103 RX Delay -111 -> 252, step: 8
1410 11:35:57.287839 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1411 11:35:57.290747 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1412 11:35:57.294243 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1413 11:35:57.297691 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1414 11:35:57.301190 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1415 11:35:57.308254 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1416 11:35:57.311423 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1417 11:35:57.314594 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1418 11:35:57.317654 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1419 11:35:57.321254 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1420 11:35:57.327606 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1421 11:35:57.330848 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1422 11:35:57.334751 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1423 11:35:57.338321 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1424 11:35:57.341747 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1425 11:35:57.348130 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1426 11:35:57.348571 ==
1427 11:35:57.351339 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 11:35:57.354441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 11:35:57.354860 ==
1430 11:35:57.355152 DQS Delay:
1431 11:35:57.357721 DQS0 = 0, DQS1 = 0
1432 11:35:57.358186 DQM Delay:
1433 11:35:57.361197 DQM0 = 79, DQM1 = 69
1434 11:35:57.361695 DQ Delay:
1435 11:35:57.364687 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1436 11:35:57.367825 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1437 11:35:57.371055 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1438 11:35:57.374495 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1439 11:35:57.374872
1440 11:35:57.375159
1441 11:35:57.384739 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1442 11:35:57.385200 CH0 RK1: MR19=606, MR18=4C26
1443 11:35:57.391142 CH0_RK1: MR19=0x606, MR18=0x4C26, DQSOSC=390, MR23=63, INC=97, DEC=64
1444 11:35:57.394627 [RxdqsGatingPostProcess] freq 800
1445 11:35:57.401190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 11:35:57.404243 Pre-setting of DQS Precalculation
1447 11:35:57.407944 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 11:35:57.408449 ==
1449 11:35:57.411016 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 11:35:57.414244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:35:57.414683 ==
1452 11:35:57.420867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 11:35:57.428213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 11:35:57.436013 [CA 0] Center 36 (6~67) winsize 62
1455 11:35:57.439745 [CA 1] Center 36 (6~67) winsize 62
1456 11:35:57.442614 [CA 2] Center 34 (5~64) winsize 60
1457 11:35:57.446465 [CA 3] Center 34 (4~64) winsize 61
1458 11:35:57.449559 [CA 4] Center 34 (4~65) winsize 62
1459 11:35:57.453328 [CA 5] Center 34 (4~64) winsize 61
1460 11:35:57.453790
1461 11:35:57.456131 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1462 11:35:57.456513
1463 11:35:57.459431 [CATrainingPosCal] consider 1 rank data
1464 11:35:57.462568 u2DelayCellTimex100 = 270/100 ps
1465 11:35:57.465849 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 11:35:57.473098 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 11:35:57.477063 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1468 11:35:57.479741 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 11:35:57.482610 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 11:35:57.485906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1471 11:35:57.486351
1472 11:35:57.489454 CA PerBit enable=1, Macro0, CA PI delay=34
1473 11:35:57.489842
1474 11:35:57.492784 [CBTSetCACLKResult] CA Dly = 34
1475 11:35:57.493171 CS Dly: 5 (0~36)
1476 11:35:57.495990 ==
1477 11:35:57.496448 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 11:35:57.503127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 11:35:57.503637 ==
1480 11:35:57.506020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 11:35:57.512927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 11:35:57.522390 [CA 0] Center 36 (6~67) winsize 62
1483 11:35:57.525455 [CA 1] Center 36 (6~67) winsize 62
1484 11:35:57.529048 [CA 2] Center 34 (4~65) winsize 62
1485 11:35:57.532054 [CA 3] Center 33 (3~64) winsize 62
1486 11:35:57.536121 [CA 4] Center 34 (4~65) winsize 62
1487 11:35:57.539640 [CA 5] Center 34 (4~64) winsize 61
1488 11:35:57.540065
1489 11:35:57.542350 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1490 11:35:57.542772
1491 11:35:57.545909 [CATrainingPosCal] consider 2 rank data
1492 11:35:57.548914 u2DelayCellTimex100 = 270/100 ps
1493 11:35:57.552084 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 11:35:57.555470 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 11:35:57.562709 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1496 11:35:57.565946 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 11:35:57.568973 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 11:35:57.572521 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 11:35:57.572947
1500 11:35:57.575494 CA PerBit enable=1, Macro0, CA PI delay=34
1501 11:35:57.575919
1502 11:35:57.578807 [CBTSetCACLKResult] CA Dly = 34
1503 11:35:57.579228 CS Dly: 5 (0~37)
1504 11:35:57.579564
1505 11:35:57.582574 ----->DramcWriteLeveling(PI) begin...
1506 11:35:57.585658 ==
1507 11:35:57.586042 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 11:35:57.592311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 11:35:57.592710 ==
1510 11:35:57.595802 Write leveling (Byte 0): 27 => 27
1511 11:35:57.598879 Write leveling (Byte 1): 30 => 30
1512 11:35:57.602922 DramcWriteLeveling(PI) end<-----
1513 11:35:57.603403
1514 11:35:57.603883 ==
1515 11:35:57.605673 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 11:35:57.609003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 11:35:57.609499 ==
1518 11:35:57.612114 [Gating] SW mode calibration
1519 11:35:57.618726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 11:35:57.622089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 11:35:57.628875 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 11:35:57.632269 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1523 11:35:57.636252 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1524 11:35:57.642336 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:35:57.645837 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:35:57.648856 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:35:57.655289 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:35:57.659014 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:35:57.662478 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:35:57.668737 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:35:57.672139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:35:57.675286 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:35:57.682531 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:35:57.685313 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:35:57.688928 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:35:57.695757 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:35:57.699331 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1538 11:35:57.702266 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:35:57.705733 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1540 11:35:57.712467 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:35:57.715512 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:35:57.719169 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:35:57.725492 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:35:57.729038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:35:57.732422 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:35:57.738847 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1547 11:35:57.742193 0 9 8 | B1->B0 | 2929 2827 | 1 1 | (1 1) (1 1)
1548 11:35:57.745801 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:35:57.753064 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:35:57.755800 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:35:57.759408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 11:35:57.765699 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 11:35:57.769066 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 11:35:57.772394 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
1555 11:35:57.779274 0 10 8 | B1->B0 | 2d2d 2c2c | 0 1 | (1 0) (1 0)
1556 11:35:57.782382 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:35:57.785679 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:35:57.788788 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:35:57.795456 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:35:57.798999 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:35:57.802074 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 11:35:57.808757 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1563 11:35:57.812369 0 11 8 | B1->B0 | 3838 3838 | 0 1 | (0 0) (0 0)
1564 11:35:57.815336 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:35:57.822152 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:35:57.825704 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:35:57.829159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:35:57.835450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 11:35:57.839130 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 11:35:57.842173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 11:35:57.848785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:35:57.852050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:35:57.855690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:35:57.862024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:35:57.865508 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:35:57.868985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:35:57.875103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:35:57.878421 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:35:57.881857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:35:57.888942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:35:57.891774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:35:57.895167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:35:57.902462 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:35:57.905294 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:35:57.908795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:35:57.915260 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1587 11:35:57.919007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1588 11:35:57.922465 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1589 11:35:57.924956 Total UI for P1: 0, mck2ui 16
1590 11:35:57.928215 best dqsien dly found for B0: ( 0, 14, 6)
1591 11:35:57.932194 Total UI for P1: 0, mck2ui 16
1592 11:35:57.935207 best dqsien dly found for B1: ( 0, 14, 8)
1593 11:35:57.938494 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1594 11:35:57.942514 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1595 11:35:57.943014
1596 11:35:57.945298 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 11:35:57.948821 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1598 11:35:57.952043 [Gating] SW calibration Done
1599 11:35:57.952462 ==
1600 11:35:57.955123 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 11:35:57.961681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 11:35:57.962132 ==
1603 11:35:57.962473 RX Vref Scan: 0
1604 11:35:57.962778
1605 11:35:57.965153 RX Vref 0 -> 0, step: 1
1606 11:35:57.965577
1607 11:35:57.968485 RX Delay -130 -> 252, step: 16
1608 11:35:57.971478 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1609 11:35:57.975343 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1610 11:35:57.978048 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1611 11:35:57.982072 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1612 11:35:57.988262 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1613 11:35:57.991643 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1614 11:35:57.994911 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1615 11:35:57.998058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1616 11:35:58.001819 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1617 11:35:58.008272 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1618 11:35:58.011831 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1619 11:35:58.015045 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1620 11:35:58.018403 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1621 11:35:58.021483 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1622 11:35:58.028343 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1623 11:35:58.031575 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1624 11:35:58.032051 ==
1625 11:35:58.034694 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 11:35:58.038074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 11:35:58.038497 ==
1628 11:35:58.041133 DQS Delay:
1629 11:35:58.041512 DQS0 = 0, DQS1 = 0
1630 11:35:58.044992 DQM Delay:
1631 11:35:58.045373 DQM0 = 79, DQM1 = 70
1632 11:35:58.045668 DQ Delay:
1633 11:35:58.048076 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1634 11:35:58.051524 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1635 11:35:58.054827 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1636 11:35:58.058370 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1637 11:35:58.058763
1638 11:35:58.059058
1639 11:35:58.059334 ==
1640 11:35:58.061458 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:35:58.068492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:35:58.068954 ==
1643 11:35:58.069251
1644 11:35:58.069535
1645 11:35:58.069837 TX Vref Scan disable
1646 11:35:58.071576 == TX Byte 0 ==
1647 11:35:58.075455 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1648 11:35:58.078511 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1649 11:35:58.081803 == TX Byte 1 ==
1650 11:35:58.084825 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1651 11:35:58.088647 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1652 11:35:58.091804 ==
1653 11:35:58.095022 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 11:35:58.098163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 11:35:58.098679 ==
1656 11:35:58.111307 TX Vref=22, minBit 1, minWin=27, winSum=442
1657 11:35:58.114879 TX Vref=24, minBit 1, minWin=27, winSum=443
1658 11:35:58.117821 TX Vref=26, minBit 1, minWin=27, winSum=444
1659 11:35:58.121090 TX Vref=28, minBit 1, minWin=27, winSum=447
1660 11:35:58.124765 TX Vref=30, minBit 0, minWin=27, winSum=446
1661 11:35:58.127330 TX Vref=32, minBit 5, minWin=27, winSum=449
1662 11:35:58.134432 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 32
1663 11:35:58.134813
1664 11:35:58.137642 Final TX Range 1 Vref 32
1665 11:35:58.138020
1666 11:35:58.138415 ==
1667 11:35:58.141059 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 11:35:58.144157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 11:35:58.144540 ==
1670 11:35:58.144830
1671 11:35:58.147512
1672 11:35:58.147890 TX Vref Scan disable
1673 11:35:58.150850 == TX Byte 0 ==
1674 11:35:58.154347 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1675 11:35:58.161728 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1676 11:35:58.162242 == TX Byte 1 ==
1677 11:35:58.164761 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1678 11:35:58.167741 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1679 11:35:58.170900
1680 11:35:58.171301 [DATLAT]
1681 11:35:58.171696 Freq=800, CH1 RK0
1682 11:35:58.172181
1683 11:35:58.174290 DATLAT Default: 0xa
1684 11:35:58.174701 0, 0xFFFF, sum = 0
1685 11:35:58.177394 1, 0xFFFF, sum = 0
1686 11:35:58.177800 2, 0xFFFF, sum = 0
1687 11:35:58.181473 3, 0xFFFF, sum = 0
1688 11:35:58.181965 4, 0xFFFF, sum = 0
1689 11:35:58.184209 5, 0xFFFF, sum = 0
1690 11:35:58.187731 6, 0xFFFF, sum = 0
1691 11:35:58.188197 7, 0xFFFF, sum = 0
1692 11:35:58.190714 8, 0xFFFF, sum = 0
1693 11:35:58.191253 9, 0x0, sum = 1
1694 11:35:58.191582 10, 0x0, sum = 2
1695 11:35:58.193977 11, 0x0, sum = 3
1696 11:35:58.194391 12, 0x0, sum = 4
1697 11:35:58.197467 best_step = 10
1698 11:35:58.197845
1699 11:35:58.198184 ==
1700 11:35:58.201943 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 11:35:58.203996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 11:35:58.204384 ==
1703 11:35:58.207494 RX Vref Scan: 1
1704 11:35:58.207872
1705 11:35:58.208165 Set Vref Range= 32 -> 127
1706 11:35:58.208439
1707 11:35:58.211008 RX Vref 32 -> 127, step: 1
1708 11:35:58.211463
1709 11:35:58.214486 RX Delay -111 -> 252, step: 8
1710 11:35:58.214949
1711 11:35:58.218038 Set Vref, RX VrefLevel [Byte0]: 32
1712 11:35:58.220976 [Byte1]: 32
1713 11:35:58.221411
1714 11:35:58.224370 Set Vref, RX VrefLevel [Byte0]: 33
1715 11:35:58.227566 [Byte1]: 33
1716 11:35:58.231332
1717 11:35:58.234650 Set Vref, RX VrefLevel [Byte0]: 34
1718 11:35:58.238036 [Byte1]: 34
1719 11:35:58.238512
1720 11:35:58.241522 Set Vref, RX VrefLevel [Byte0]: 35
1721 11:35:58.244376 [Byte1]: 35
1722 11:35:58.244759
1723 11:35:58.247685 Set Vref, RX VrefLevel [Byte0]: 36
1724 11:35:58.251278 [Byte1]: 36
1725 11:35:58.251658
1726 11:35:58.254491 Set Vref, RX VrefLevel [Byte0]: 37
1727 11:35:58.257903 [Byte1]: 37
1728 11:35:58.262668
1729 11:35:58.263125 Set Vref, RX VrefLevel [Byte0]: 38
1730 11:35:58.265357 [Byte1]: 38
1731 11:35:58.270362
1732 11:35:58.270824 Set Vref, RX VrefLevel [Byte0]: 39
1733 11:35:58.272943 [Byte1]: 39
1734 11:35:58.277404
1735 11:35:58.277784 Set Vref, RX VrefLevel [Byte0]: 40
1736 11:35:58.280442 [Byte1]: 40
1737 11:35:58.285029
1738 11:35:58.285412 Set Vref, RX VrefLevel [Byte0]: 41
1739 11:35:58.288135 [Byte1]: 41
1740 11:35:58.292820
1741 11:35:58.293269 Set Vref, RX VrefLevel [Byte0]: 42
1742 11:35:58.296139 [Byte1]: 42
1743 11:35:58.300085
1744 11:35:58.300462 Set Vref, RX VrefLevel [Byte0]: 43
1745 11:35:58.303696 [Byte1]: 43
1746 11:35:58.307789
1747 11:35:58.308214 Set Vref, RX VrefLevel [Byte0]: 44
1748 11:35:58.311340 [Byte1]: 44
1749 11:35:58.315827
1750 11:35:58.316285 Set Vref, RX VrefLevel [Byte0]: 45
1751 11:35:58.318954 [Byte1]: 45
1752 11:35:58.323877
1753 11:35:58.324338 Set Vref, RX VrefLevel [Byte0]: 46
1754 11:35:58.326504 [Byte1]: 46
1755 11:35:58.330608
1756 11:35:58.330994 Set Vref, RX VrefLevel [Byte0]: 47
1757 11:35:58.334092 [Byte1]: 47
1758 11:35:58.338588
1759 11:35:58.338967 Set Vref, RX VrefLevel [Byte0]: 48
1760 11:35:58.342247 [Byte1]: 48
1761 11:35:58.346204
1762 11:35:58.346584 Set Vref, RX VrefLevel [Byte0]: 49
1763 11:35:58.349094 [Byte1]: 49
1764 11:35:58.353680
1765 11:35:58.354056 Set Vref, RX VrefLevel [Byte0]: 50
1766 11:35:58.357244 [Byte1]: 50
1767 11:35:58.361393
1768 11:35:58.361774 Set Vref, RX VrefLevel [Byte0]: 51
1769 11:35:58.364979 [Byte1]: 51
1770 11:35:58.369273
1771 11:35:58.369729 Set Vref, RX VrefLevel [Byte0]: 52
1772 11:35:58.372579 [Byte1]: 52
1773 11:35:58.377104
1774 11:35:58.377567 Set Vref, RX VrefLevel [Byte0]: 53
1775 11:35:58.380107 [Byte1]: 53
1776 11:35:58.384069
1777 11:35:58.384448 Set Vref, RX VrefLevel [Byte0]: 54
1778 11:35:58.388041 [Byte1]: 54
1779 11:35:58.391781
1780 11:35:58.392161 Set Vref, RX VrefLevel [Byte0]: 55
1781 11:35:58.395317 [Byte1]: 55
1782 11:35:58.399596
1783 11:35:58.400055 Set Vref, RX VrefLevel [Byte0]: 56
1784 11:35:58.403216 [Byte1]: 56
1785 11:35:58.407568
1786 11:35:58.408007 Set Vref, RX VrefLevel [Byte0]: 57
1787 11:35:58.410784 [Byte1]: 57
1788 11:35:58.415209
1789 11:35:58.415664 Set Vref, RX VrefLevel [Byte0]: 58
1790 11:35:58.417898 [Byte1]: 58
1791 11:35:58.422387
1792 11:35:58.422786 Set Vref, RX VrefLevel [Byte0]: 59
1793 11:35:58.426201 [Byte1]: 59
1794 11:35:58.430244
1795 11:35:58.430761 Set Vref, RX VrefLevel [Byte0]: 60
1796 11:35:58.433609 [Byte1]: 60
1797 11:35:58.438322
1798 11:35:58.438845 Set Vref, RX VrefLevel [Byte0]: 61
1799 11:35:58.441040 [Byte1]: 61
1800 11:35:58.445202
1801 11:35:58.445639 Set Vref, RX VrefLevel [Byte0]: 62
1802 11:35:58.448973 [Byte1]: 62
1803 11:35:58.453534
1804 11:35:58.453931 Set Vref, RX VrefLevel [Byte0]: 63
1805 11:35:58.456880 [Byte1]: 63
1806 11:35:58.461168
1807 11:35:58.461649 Set Vref, RX VrefLevel [Byte0]: 64
1808 11:35:58.464141 [Byte1]: 64
1809 11:35:58.468127
1810 11:35:58.468525 Set Vref, RX VrefLevel [Byte0]: 65
1811 11:35:58.471744 [Byte1]: 65
1812 11:35:58.476355
1813 11:35:58.476753 Set Vref, RX VrefLevel [Byte0]: 66
1814 11:35:58.479368 [Byte1]: 66
1815 11:35:58.484580
1816 11:35:58.485047 Set Vref, RX VrefLevel [Byte0]: 67
1817 11:35:58.486908 [Byte1]: 67
1818 11:35:58.491553
1819 11:35:58.492197 Set Vref, RX VrefLevel [Byte0]: 68
1820 11:35:58.494634 [Byte1]: 68
1821 11:35:58.498938
1822 11:35:58.499427 Set Vref, RX VrefLevel [Byte0]: 69
1823 11:35:58.502437 [Byte1]: 69
1824 11:35:58.506727
1825 11:35:58.507151 Set Vref, RX VrefLevel [Byte0]: 70
1826 11:35:58.510064 [Byte1]: 70
1827 11:35:58.514499
1828 11:35:58.515012 Set Vref, RX VrefLevel [Byte0]: 71
1829 11:35:58.517904 [Byte1]: 71
1830 11:35:58.522069
1831 11:35:58.522554 Set Vref, RX VrefLevel [Byte0]: 72
1832 11:35:58.525594 [Byte1]: 72
1833 11:35:58.529789
1834 11:35:58.530267 Set Vref, RX VrefLevel [Byte0]: 73
1835 11:35:58.532971 [Byte1]: 73
1836 11:35:58.537507
1837 11:35:58.537980 Set Vref, RX VrefLevel [Byte0]: 74
1838 11:35:58.540596 [Byte1]: 74
1839 11:35:58.544895
1840 11:35:58.545295 Set Vref, RX VrefLevel [Byte0]: 75
1841 11:35:58.548377 [Byte1]: 75
1842 11:35:58.552526
1843 11:35:58.552907 Set Vref, RX VrefLevel [Byte0]: 76
1844 11:35:58.555672 [Byte1]: 76
1845 11:35:58.560145
1846 11:35:58.560522 Final RX Vref Byte 0 = 59 to rank0
1847 11:35:58.564455 Final RX Vref Byte 1 = 54 to rank0
1848 11:35:58.567019 Final RX Vref Byte 0 = 59 to rank1
1849 11:35:58.570595 Final RX Vref Byte 1 = 54 to rank1==
1850 11:35:58.573374 Dram Type= 6, Freq= 0, CH_1, rank 0
1851 11:35:58.580041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 11:35:58.580457 ==
1853 11:35:58.580755 DQS Delay:
1854 11:35:58.581029 DQS0 = 0, DQS1 = 0
1855 11:35:58.584083 DQM Delay:
1856 11:35:58.584462 DQM0 = 81, DQM1 = 71
1857 11:35:58.587002 DQ Delay:
1858 11:35:58.590556 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1859 11:35:58.590936 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1860 11:35:58.594191 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1861 11:35:58.597308 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1862 11:35:58.597710
1863 11:35:58.600121
1864 11:35:58.607036 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1865 11:35:58.610346 CH1 RK0: MR19=606, MR18=1721
1866 11:35:58.616725 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1867 11:35:58.617169
1868 11:35:58.620318 ----->DramcWriteLeveling(PI) begin...
1869 11:35:58.620702 ==
1870 11:35:58.623522 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 11:35:58.627478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 11:35:58.627864 ==
1873 11:35:58.630456 Write leveling (Byte 0): 27 => 27
1874 11:35:58.633800 Write leveling (Byte 1): 31 => 31
1875 11:35:58.637032 DramcWriteLeveling(PI) end<-----
1876 11:35:58.637490
1877 11:35:58.637786 ==
1878 11:35:58.640248 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 11:35:58.643880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 11:35:58.644263 ==
1881 11:35:58.646764 [Gating] SW mode calibration
1882 11:35:58.653436 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1883 11:35:58.660246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1884 11:35:58.664429 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1885 11:35:58.667063 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1886 11:35:58.673633 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1887 11:35:58.677269 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:35:58.680274 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:35:58.686802 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:35:58.690421 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:35:58.693748 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:35:58.700758 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:35:58.703897 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:35:58.706936 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:35:58.714176 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:35:58.717603 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:35:58.720421 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:35:58.723541 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:35:58.730035 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:35:58.733511 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1901 11:35:58.736960 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1902 11:35:58.743286 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:35:58.746760 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:35:58.749828 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:35:58.756926 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:35:58.759995 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:35:58.763248 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:35:58.770002 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:35:58.773621 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1910 11:35:58.776547 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1911 11:35:58.783169 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:35:58.787232 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 11:35:58.790064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:35:58.796655 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:35:58.799450 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:35:58.802827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:35:58.809440 0 10 4 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (0 0)
1918 11:35:58.813110 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1919 11:35:58.816633 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:35:58.822907 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:35:58.826252 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:35:58.829994 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:35:58.833267 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:35:58.839592 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1925 11:35:58.843164 0 11 4 | B1->B0 | 2929 3b3b | 1 1 | (0 0) (0 0)
1926 11:35:58.846635 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1927 11:35:58.852766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 11:35:58.856476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:35:58.859507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:35:58.866492 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:35:58.869560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:35:58.873153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:35:58.879678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1934 11:35:58.882802 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1935 11:35:58.887165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:35:58.893373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:35:58.896711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:35:58.899849 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:35:58.906541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:35:58.909794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:35:58.913337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:35:58.919828 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:35:58.923281 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:35:58.926890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:35:58.933041 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:35:58.936887 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:35:58.939940 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:35:58.943336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:35:58.950195 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1950 11:35:58.953104 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1951 11:35:58.956715 Total UI for P1: 0, mck2ui 16
1952 11:35:58.960534 best dqsien dly found for B0: ( 0, 14, 4)
1953 11:35:58.963400 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1954 11:35:58.966791 Total UI for P1: 0, mck2ui 16
1955 11:35:58.969602 best dqsien dly found for B1: ( 0, 14, 8)
1956 11:35:58.973370 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1957 11:35:58.976565 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1958 11:35:58.977291
1959 11:35:58.983343 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 11:35:58.986579 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1961 11:35:58.986964 [Gating] SW calibration Done
1962 11:35:58.990798 ==
1963 11:35:58.991176 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 11:35:58.996495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 11:35:58.996879 ==
1966 11:35:58.997174 RX Vref Scan: 0
1967 11:35:58.997445
1968 11:35:59.000054 RX Vref 0 -> 0, step: 1
1969 11:35:59.000462
1970 11:35:59.003090 RX Delay -130 -> 252, step: 16
1971 11:35:59.006442 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1972 11:35:59.010211 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1973 11:35:59.013361 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1974 11:35:59.019781 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1975 11:35:59.023420 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1976 11:35:59.027119 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1977 11:35:59.029620 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1978 11:35:59.033675 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1979 11:35:59.039648 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1980 11:35:59.043035 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1981 11:35:59.046425 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1982 11:35:59.049892 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1983 11:35:59.053221 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1984 11:35:59.059347 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1985 11:35:59.063036 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1986 11:35:59.066053 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1987 11:35:59.066626 ==
1988 11:35:59.069413 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 11:35:59.073049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 11:35:59.076038 ==
1991 11:35:59.076495 DQS Delay:
1992 11:35:59.076850 DQS0 = 0, DQS1 = 0
1993 11:35:59.079554 DQM Delay:
1994 11:35:59.080125 DQM0 = 78, DQM1 = 76
1995 11:35:59.083157 DQ Delay:
1996 11:35:59.086217 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1997 11:35:59.086678 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1998 11:35:59.089924 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =61
1999 11:35:59.092750 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2000 11:35:59.096024
2001 11:35:59.096409
2002 11:35:59.096704 ==
2003 11:35:59.099468 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:35:59.102860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:35:59.103249 ==
2006 11:35:59.103544
2007 11:35:59.103816
2008 11:35:59.106508 TX Vref Scan disable
2009 11:35:59.106947 == TX Byte 0 ==
2010 11:35:59.112730 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2011 11:35:59.116074 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2012 11:35:59.116415 == TX Byte 1 ==
2013 11:35:59.122567 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2014 11:35:59.126072 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2015 11:35:59.126517 ==
2016 11:35:59.129424 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 11:35:59.132485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 11:35:59.132868 ==
2019 11:35:59.147304 TX Vref=22, minBit 5, minWin=27, winSum=450
2020 11:35:59.150299 TX Vref=24, minBit 5, minWin=27, winSum=452
2021 11:35:59.153807 TX Vref=26, minBit 1, minWin=28, winSum=459
2022 11:35:59.157124 TX Vref=28, minBit 0, minWin=28, winSum=459
2023 11:35:59.160040 TX Vref=30, minBit 1, minWin=28, winSum=462
2024 11:35:59.163451 TX Vref=32, minBit 1, minWin=27, winSum=461
2025 11:35:59.170207 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 30
2026 11:35:59.170659
2027 11:35:59.173899 Final TX Range 1 Vref 30
2028 11:35:59.174477
2029 11:35:59.174993 ==
2030 11:35:59.176548 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 11:35:59.180005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 11:35:59.180226 ==
2033 11:35:59.180416
2034 11:35:59.183425
2035 11:35:59.183592 TX Vref Scan disable
2036 11:35:59.186605 == TX Byte 0 ==
2037 11:35:59.190016 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2038 11:35:59.193668 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2039 11:35:59.196440 == TX Byte 1 ==
2040 11:35:59.199960 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2041 11:35:59.206755 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2042 11:35:59.206986
2043 11:35:59.207165 [DATLAT]
2044 11:35:59.207333 Freq=800, CH1 RK1
2045 11:35:59.207499
2046 11:35:59.210454 DATLAT Default: 0xa
2047 11:35:59.210747 0, 0xFFFF, sum = 0
2048 11:35:59.213390 1, 0xFFFF, sum = 0
2049 11:35:59.213767 2, 0xFFFF, sum = 0
2050 11:35:59.216657 3, 0xFFFF, sum = 0
2051 11:35:59.217046 4, 0xFFFF, sum = 0
2052 11:35:59.219779 5, 0xFFFF, sum = 0
2053 11:35:59.223308 6, 0xFFFF, sum = 0
2054 11:35:59.223694 7, 0xFFFF, sum = 0
2055 11:35:59.226595 8, 0xFFFF, sum = 0
2056 11:35:59.227119 9, 0x0, sum = 1
2057 11:35:59.227560 10, 0x0, sum = 2
2058 11:35:59.230237 11, 0x0, sum = 3
2059 11:35:59.230563 12, 0x0, sum = 4
2060 11:35:59.233597 best_step = 10
2061 11:35:59.234058
2062 11:35:59.234407 ==
2063 11:35:59.237295 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 11:35:59.240262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 11:35:59.240649 ==
2066 11:35:59.243127 RX Vref Scan: 0
2067 11:35:59.243505
2068 11:35:59.243799 RX Vref 0 -> 0, step: 1
2069 11:35:59.244072
2070 11:35:59.246549 RX Delay -111 -> 252, step: 8
2071 11:35:59.253699 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2072 11:35:59.257111 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2073 11:35:59.260304 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2074 11:35:59.263577 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2075 11:35:59.266871 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2076 11:35:59.273920 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2077 11:35:59.277099 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2078 11:35:59.280259 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2079 11:35:59.283745 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2080 11:35:59.286800 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2081 11:35:59.293857 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2082 11:35:59.296843 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2083 11:35:59.300605 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2084 11:35:59.303999 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2085 11:35:59.307127 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2086 11:35:59.313387 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2087 11:35:59.313770 ==
2088 11:35:59.317268 Dram Type= 6, Freq= 0, CH_1, rank 1
2089 11:35:59.320637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2090 11:35:59.321018 ==
2091 11:35:59.321313 DQS Delay:
2092 11:35:59.323574 DQS0 = 0, DQS1 = 0
2093 11:35:59.323952 DQM Delay:
2094 11:35:59.326952 DQM0 = 77, DQM1 = 74
2095 11:35:59.327333 DQ Delay:
2096 11:35:59.330603 DQ0 =84, DQ1 =72, DQ2 =64, DQ3 =72
2097 11:35:59.333461 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2098 11:35:59.337064 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2099 11:35:59.340236 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2100 11:35:59.340769
2101 11:35:59.341195
2102 11:35:59.346737 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2103 11:35:59.350615 CH1 RK1: MR19=606, MR18=2139
2104 11:35:59.356836 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2105 11:35:59.360039 [RxdqsGatingPostProcess] freq 800
2106 11:35:59.366511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2107 11:35:59.369569 Pre-setting of DQS Precalculation
2108 11:35:59.373415 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2109 11:35:59.380301 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2110 11:35:59.386521 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2111 11:35:59.389948
2112 11:35:59.390452
2113 11:35:59.390757 [Calibration Summary] 1600 Mbps
2114 11:35:59.393435 CH 0, Rank 0
2115 11:35:59.393842 SW Impedance : PASS
2116 11:35:59.396467 DUTY Scan : NO K
2117 11:35:59.399763 ZQ Calibration : PASS
2118 11:35:59.400272 Jitter Meter : NO K
2119 11:35:59.403201 CBT Training : PASS
2120 11:35:59.406557 Write leveling : PASS
2121 11:35:59.406932 RX DQS gating : PASS
2122 11:35:59.409714 RX DQ/DQS(RDDQC) : PASS
2123 11:35:59.413578 TX DQ/DQS : PASS
2124 11:35:59.414220 RX DATLAT : PASS
2125 11:35:59.417004 RX DQ/DQS(Engine): PASS
2126 11:35:59.419566 TX OE : NO K
2127 11:35:59.420129 All Pass.
2128 11:35:59.420584
2129 11:35:59.421018 CH 0, Rank 1
2130 11:35:59.423088 SW Impedance : PASS
2131 11:35:59.426082 DUTY Scan : NO K
2132 11:35:59.426610 ZQ Calibration : PASS
2133 11:35:59.429518 Jitter Meter : NO K
2134 11:35:59.432837 CBT Training : PASS
2135 11:35:59.433352 Write leveling : PASS
2136 11:35:59.437023 RX DQS gating : PASS
2137 11:35:59.439694 RX DQ/DQS(RDDQC) : PASS
2138 11:35:59.440093 TX DQ/DQS : PASS
2139 11:35:59.442897 RX DATLAT : PASS
2140 11:35:59.443280 RX DQ/DQS(Engine): PASS
2141 11:35:59.446454 TX OE : NO K
2142 11:35:59.446840 All Pass.
2143 11:35:59.447185
2144 11:35:59.449419 CH 1, Rank 0
2145 11:35:59.449939 SW Impedance : PASS
2146 11:35:59.453021 DUTY Scan : NO K
2147 11:35:59.456245 ZQ Calibration : PASS
2148 11:35:59.456624 Jitter Meter : NO K
2149 11:35:59.459903 CBT Training : PASS
2150 11:35:59.463017 Write leveling : PASS
2151 11:35:59.463395 RX DQS gating : PASS
2152 11:35:59.466684 RX DQ/DQS(RDDQC) : PASS
2153 11:35:59.469828 TX DQ/DQS : PASS
2154 11:35:59.470262 RX DATLAT : PASS
2155 11:35:59.473135 RX DQ/DQS(Engine): PASS
2156 11:35:59.476745 TX OE : NO K
2157 11:35:59.477218 All Pass.
2158 11:35:59.477517
2159 11:35:59.477790 CH 1, Rank 1
2160 11:35:59.479898 SW Impedance : PASS
2161 11:35:59.480238 DUTY Scan : NO K
2162 11:35:59.482944 ZQ Calibration : PASS
2163 11:35:59.486468 Jitter Meter : NO K
2164 11:35:59.486853 CBT Training : PASS
2165 11:35:59.489859 Write leveling : PASS
2166 11:35:59.493000 RX DQS gating : PASS
2167 11:35:59.493426 RX DQ/DQS(RDDQC) : PASS
2168 11:35:59.495971 TX DQ/DQS : PASS
2169 11:35:59.499443 RX DATLAT : PASS
2170 11:35:59.499825 RX DQ/DQS(Engine): PASS
2171 11:35:59.502676 TX OE : NO K
2172 11:35:59.503105 All Pass.
2173 11:35:59.503403
2174 11:35:59.506131 DramC Write-DBI off
2175 11:35:59.509437 PER_BANK_REFRESH: Hybrid Mode
2176 11:35:59.509834 TX_TRACKING: ON
2177 11:35:59.513133 [GetDramInforAfterCalByMRR] Vendor 6.
2178 11:35:59.516141 [GetDramInforAfterCalByMRR] Revision 606.
2179 11:35:59.519702 [GetDramInforAfterCalByMRR] Revision 2 0.
2180 11:35:59.522984 MR0 0x3b3b
2181 11:35:59.523440 MR8 0x5151
2182 11:35:59.526001 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 11:35:59.526428
2184 11:35:59.526725 MR0 0x3b3b
2185 11:35:59.529840 MR8 0x5151
2186 11:35:59.532662 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 11:35:59.533044
2188 11:35:59.542875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2189 11:35:59.546500 [FAST_K] Save calibration result to emmc
2190 11:35:59.549628 [FAST_K] Save calibration result to emmc
2191 11:35:59.550009 dram_init: config_dvfs: 1
2192 11:35:59.556561 dramc_set_vcore_voltage set vcore to 662500
2193 11:35:59.557023 Read voltage for 1200, 2
2194 11:35:59.559813 Vio18 = 0
2195 11:35:59.560196 Vcore = 662500
2196 11:35:59.560492 Vdram = 0
2197 11:35:59.560782 Vddq = 0
2198 11:35:59.562773 Vmddr = 0
2199 11:35:59.566676 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2200 11:35:59.572983 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2201 11:35:59.576558 MEM_TYPE=3, freq_sel=15
2202 11:35:59.576969 sv_algorithm_assistance_LP4_1600
2203 11:35:59.583147 ============ PULL DRAM RESETB DOWN ============
2204 11:35:59.586211 ========== PULL DRAM RESETB DOWN end =========
2205 11:35:59.589701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2206 11:35:59.592769 ===================================
2207 11:35:59.596100 LPDDR4 DRAM CONFIGURATION
2208 11:35:59.599548 ===================================
2209 11:35:59.602775 EX_ROW_EN[0] = 0x0
2210 11:35:59.603169 EX_ROW_EN[1] = 0x0
2211 11:35:59.606179 LP4Y_EN = 0x0
2212 11:35:59.606575 WORK_FSP = 0x0
2213 11:35:59.609208 WL = 0x4
2214 11:35:59.609649 RL = 0x4
2215 11:35:59.612850 BL = 0x2
2216 11:35:59.613242 RPST = 0x0
2217 11:35:59.616680 RD_PRE = 0x0
2218 11:35:59.617154 WR_PRE = 0x1
2219 11:35:59.619385 WR_PST = 0x0
2220 11:35:59.619777 DBI_WR = 0x0
2221 11:35:59.622571 DBI_RD = 0x0
2222 11:35:59.622963 OTF = 0x1
2223 11:35:59.626272 ===================================
2224 11:35:59.629250 ===================================
2225 11:35:59.633155 ANA top config
2226 11:35:59.636013 ===================================
2227 11:35:59.639503 DLL_ASYNC_EN = 0
2228 11:35:59.639579 ALL_SLAVE_EN = 0
2229 11:35:59.642391 NEW_RANK_MODE = 1
2230 11:35:59.645579 DLL_IDLE_MODE = 1
2231 11:35:59.649623 LP45_APHY_COMB_EN = 1
2232 11:35:59.649741 TX_ODT_DIS = 1
2233 11:35:59.652279 NEW_8X_MODE = 1
2234 11:35:59.656296 ===================================
2235 11:35:59.658919 ===================================
2236 11:35:59.662736 data_rate = 2400
2237 11:35:59.665656 CKR = 1
2238 11:35:59.669185 DQ_P2S_RATIO = 8
2239 11:35:59.672357 ===================================
2240 11:35:59.675683 CA_P2S_RATIO = 8
2241 11:35:59.675769 DQ_CA_OPEN = 0
2242 11:35:59.679173 DQ_SEMI_OPEN = 0
2243 11:35:59.682754 CA_SEMI_OPEN = 0
2244 11:35:59.685921 CA_FULL_RATE = 0
2245 11:35:59.688856 DQ_CKDIV4_EN = 0
2246 11:35:59.692515 CA_CKDIV4_EN = 0
2247 11:35:59.692655 CA_PREDIV_EN = 0
2248 11:35:59.696092 PH8_DLY = 17
2249 11:35:59.699372 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2250 11:35:59.702213 DQ_AAMCK_DIV = 4
2251 11:35:59.705869 CA_AAMCK_DIV = 4
2252 11:35:59.709148 CA_ADMCK_DIV = 4
2253 11:35:59.709294 DQ_TRACK_CA_EN = 0
2254 11:35:59.712377 CA_PICK = 1200
2255 11:35:59.716105 CA_MCKIO = 1200
2256 11:35:59.719548 MCKIO_SEMI = 0
2257 11:35:59.722753 PLL_FREQ = 2366
2258 11:35:59.726055 DQ_UI_PI_RATIO = 32
2259 11:35:59.729103 CA_UI_PI_RATIO = 0
2260 11:35:59.732683 ===================================
2261 11:35:59.736011 ===================================
2262 11:35:59.736371 memory_type:LPDDR4
2263 11:35:59.739434 GP_NUM : 10
2264 11:35:59.739811 SRAM_EN : 1
2265 11:35:59.742776 MD32_EN : 0
2266 11:35:59.746026 ===================================
2267 11:35:59.749225 [ANA_INIT] >>>>>>>>>>>>>>
2268 11:35:59.753109 <<<<<< [CONFIGURE PHASE]: ANA_TX
2269 11:35:59.756801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2270 11:35:59.759565 ===================================
2271 11:35:59.760037 data_rate = 2400,PCW = 0X5b00
2272 11:35:59.762537 ===================================
2273 11:35:59.766366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2274 11:35:59.773070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 11:35:59.779569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 11:35:59.782332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2277 11:35:59.785854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2278 11:35:59.789493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2279 11:35:59.792455 [ANA_INIT] flow start
2280 11:35:59.795748 [ANA_INIT] PLL >>>>>>>>
2281 11:35:59.796108 [ANA_INIT] PLL <<<<<<<<
2282 11:35:59.799171 [ANA_INIT] MIDPI >>>>>>>>
2283 11:35:59.802702 [ANA_INIT] MIDPI <<<<<<<<
2284 11:35:59.803057 [ANA_INIT] DLL >>>>>>>>
2285 11:35:59.805902 [ANA_INIT] DLL <<<<<<<<
2286 11:35:59.809684 [ANA_INIT] flow end
2287 11:35:59.812693 ============ LP4 DIFF to SE enter ============
2288 11:35:59.816066 ============ LP4 DIFF to SE exit ============
2289 11:35:59.819358 [ANA_INIT] <<<<<<<<<<<<<
2290 11:35:59.823039 [Flow] Enable top DCM control >>>>>
2291 11:35:59.825763 [Flow] Enable top DCM control <<<<<
2292 11:35:59.829549 Enable DLL master slave shuffle
2293 11:35:59.832936 ==============================================================
2294 11:35:59.835978 Gating Mode config
2295 11:35:59.842512 ==============================================================
2296 11:35:59.842871 Config description:
2297 11:35:59.852769 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2298 11:35:59.858848 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2299 11:35:59.862318 SELPH_MODE 0: By rank 1: By Phase
2300 11:35:59.869037 ==============================================================
2301 11:35:59.872795 GAT_TRACK_EN = 1
2302 11:35:59.876073 RX_GATING_MODE = 2
2303 11:35:59.879115 RX_GATING_TRACK_MODE = 2
2304 11:35:59.882877 SELPH_MODE = 1
2305 11:35:59.886186 PICG_EARLY_EN = 1
2306 11:35:59.889736 VALID_LAT_VALUE = 1
2307 11:35:59.892389 ==============================================================
2308 11:35:59.896270 Enter into Gating configuration >>>>
2309 11:35:59.898999 Exit from Gating configuration <<<<
2310 11:35:59.902427 Enter into DVFS_PRE_config >>>>>
2311 11:35:59.912234 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2312 11:35:59.915955 Exit from DVFS_PRE_config <<<<<
2313 11:35:59.919193 Enter into PICG configuration >>>>
2314 11:35:59.922907 Exit from PICG configuration <<<<
2315 11:35:59.925833 [RX_INPUT] configuration >>>>>
2316 11:35:59.929526 [RX_INPUT] configuration <<<<<
2317 11:35:59.935465 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2318 11:35:59.938685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2319 11:35:59.945869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2320 11:35:59.952265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2321 11:35:59.958919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 11:35:59.965656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 11:35:59.968971 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2324 11:35:59.972544 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2325 11:35:59.975392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2326 11:35:59.982234 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2327 11:35:59.985751 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2328 11:35:59.988989 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 11:35:59.992731 ===================================
2330 11:35:59.995456 LPDDR4 DRAM CONFIGURATION
2331 11:35:59.998897 ===================================
2332 11:35:59.999288 EX_ROW_EN[0] = 0x0
2333 11:36:00.002435 EX_ROW_EN[1] = 0x0
2334 11:36:00.002822 LP4Y_EN = 0x0
2335 11:36:00.006005 WORK_FSP = 0x0
2336 11:36:00.006434 WL = 0x4
2337 11:36:00.008771 RL = 0x4
2338 11:36:00.012380 BL = 0x2
2339 11:36:00.012847 RPST = 0x0
2340 11:36:00.015290 RD_PRE = 0x0
2341 11:36:00.015674 WR_PRE = 0x1
2342 11:36:00.019196 WR_PST = 0x0
2343 11:36:00.019609 DBI_WR = 0x0
2344 11:36:00.022145 DBI_RD = 0x0
2345 11:36:00.022534 OTF = 0x1
2346 11:36:00.025395 ===================================
2347 11:36:00.028900 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2348 11:36:00.035880 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2349 11:36:00.039033 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2350 11:36:00.042684 ===================================
2351 11:36:00.045847 LPDDR4 DRAM CONFIGURATION
2352 11:36:00.049514 ===================================
2353 11:36:00.050197 EX_ROW_EN[0] = 0x10
2354 11:36:00.052512 EX_ROW_EN[1] = 0x0
2355 11:36:00.052898 LP4Y_EN = 0x0
2356 11:36:00.055806 WORK_FSP = 0x0
2357 11:36:00.056192 WL = 0x4
2358 11:36:00.058983 RL = 0x4
2359 11:36:00.059417 BL = 0x2
2360 11:36:00.062411 RPST = 0x0
2361 11:36:00.062831 RD_PRE = 0x0
2362 11:36:00.065504 WR_PRE = 0x1
2363 11:36:00.065893 WR_PST = 0x0
2364 11:36:00.068852 DBI_WR = 0x0
2365 11:36:00.069271 DBI_RD = 0x0
2366 11:36:00.072311 OTF = 0x1
2367 11:36:00.075612 ===================================
2368 11:36:00.082383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2369 11:36:00.082799 ==
2370 11:36:00.085628 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 11:36:00.088989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 11:36:00.089541 ==
2373 11:36:00.092870 [Duty_Offset_Calibration]
2374 11:36:00.093371 B0:2 B1:0 CA:3
2375 11:36:00.093872
2376 11:36:00.095474 [DutyScan_Calibration_Flow] k_type=0
2377 11:36:00.105775
2378 11:36:00.105981 ==CLK 0==
2379 11:36:00.109241 Final CLK duty delay cell = 0
2380 11:36:00.112404 [0] MAX Duty = 5062%(X100), DQS PI = 20
2381 11:36:00.115825 [0] MIN Duty = 4906%(X100), DQS PI = 54
2382 11:36:00.119225 [0] AVG Duty = 4984%(X100)
2383 11:36:00.119363
2384 11:36:00.122755 CH0 CLK Duty spec in!! Max-Min= 156%
2385 11:36:00.125544 [DutyScan_Calibration_Flow] ====Done====
2386 11:36:00.125663
2387 11:36:00.129115 [DutyScan_Calibration_Flow] k_type=1
2388 11:36:00.144569
2389 11:36:00.144688 ==DQS 0 ==
2390 11:36:00.147710 Final DQS duty delay cell = 0
2391 11:36:00.151578 [0] MAX Duty = 5062%(X100), DQS PI = 12
2392 11:36:00.154473 [0] MIN Duty = 4876%(X100), DQS PI = 50
2393 11:36:00.154600 [0] AVG Duty = 4969%(X100)
2394 11:36:00.157763
2395 11:36:00.157925 ==DQS 1 ==
2396 11:36:00.160766 Final DQS duty delay cell = -4
2397 11:36:00.164670 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2398 11:36:00.167643 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2399 11:36:00.170868 [-4] AVG Duty = 4937%(X100)
2400 11:36:00.170957
2401 11:36:00.174583 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2402 11:36:00.174658
2403 11:36:00.177874 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2404 11:36:00.181157 [DutyScan_Calibration_Flow] ====Done====
2405 11:36:00.181232
2406 11:36:00.184427 [DutyScan_Calibration_Flow] k_type=3
2407 11:36:00.201671
2408 11:36:00.201746 ==DQM 0 ==
2409 11:36:00.205581 Final DQM duty delay cell = 0
2410 11:36:00.209291 [0] MAX Duty = 5093%(X100), DQS PI = 10
2411 11:36:00.212243 [0] MIN Duty = 4876%(X100), DQS PI = 0
2412 11:36:00.212626 [0] AVG Duty = 4984%(X100)
2413 11:36:00.215522
2414 11:36:00.215908 ==DQM 1 ==
2415 11:36:00.219079 Final DQM duty delay cell = 4
2416 11:36:00.222548 [4] MAX Duty = 5124%(X100), DQS PI = 50
2417 11:36:00.225411 [4] MIN Duty = 5000%(X100), DQS PI = 14
2418 11:36:00.225793 [4] AVG Duty = 5062%(X100)
2419 11:36:00.228956
2420 11:36:00.231929 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2421 11:36:00.232311
2422 11:36:00.235525 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2423 11:36:00.238838 [DutyScan_Calibration_Flow] ====Done====
2424 11:36:00.239220
2425 11:36:00.241992 [DutyScan_Calibration_Flow] k_type=2
2426 11:36:00.256570
2427 11:36:00.256646 ==DQ 0 ==
2428 11:36:00.259887 Final DQ duty delay cell = -4
2429 11:36:00.263620 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2430 11:36:00.266562 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2431 11:36:00.270128 [-4] AVG Duty = 4969%(X100)
2432 11:36:00.270203
2433 11:36:00.270260 ==DQ 1 ==
2434 11:36:00.273533 Final DQ duty delay cell = -4
2435 11:36:00.276947 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2436 11:36:00.280305 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2437 11:36:00.283515 [-4] AVG Duty = 4938%(X100)
2438 11:36:00.283590
2439 11:36:00.287105 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2440 11:36:00.287181
2441 11:36:00.290047 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2442 11:36:00.293388 [DutyScan_Calibration_Flow] ====Done====
2443 11:36:00.293463 ==
2444 11:36:00.296975 Dram Type= 6, Freq= 0, CH_1, rank 0
2445 11:36:00.300502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 11:36:00.300579 ==
2447 11:36:00.303167 [Duty_Offset_Calibration]
2448 11:36:00.303243 B0:1 B1:-2 CA:0
2449 11:36:00.303301
2450 11:36:00.307007 [DutyScan_Calibration_Flow] k_type=0
2451 11:36:00.317444
2452 11:36:00.317522 ==CLK 0==
2453 11:36:00.320321 Final CLK duty delay cell = 0
2454 11:36:00.324012 [0] MAX Duty = 5031%(X100), DQS PI = 16
2455 11:36:00.327379 [0] MIN Duty = 4844%(X100), DQS PI = 58
2456 11:36:00.327455 [0] AVG Duty = 4937%(X100)
2457 11:36:00.330930
2458 11:36:00.333971 CH1 CLK Duty spec in!! Max-Min= 187%
2459 11:36:00.337261 [DutyScan_Calibration_Flow] ====Done====
2460 11:36:00.337336
2461 11:36:00.340717 [DutyScan_Calibration_Flow] k_type=1
2462 11:36:00.355614
2463 11:36:00.355690 ==DQS 0 ==
2464 11:36:00.358885 Final DQS duty delay cell = -4
2465 11:36:00.362299 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2466 11:36:00.366053 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2467 11:36:00.369185 [-4] AVG Duty = 4953%(X100)
2468 11:36:00.369259
2469 11:36:00.369317 ==DQS 1 ==
2470 11:36:00.372696 Final DQS duty delay cell = 0
2471 11:36:00.376026 [0] MAX Duty = 5062%(X100), DQS PI = 0
2472 11:36:00.379248 [0] MIN Duty = 4875%(X100), DQS PI = 26
2473 11:36:00.382378 [0] AVG Duty = 4968%(X100)
2474 11:36:00.382454
2475 11:36:00.385869 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2476 11:36:00.385944
2477 11:36:00.389057 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2478 11:36:00.392899 [DutyScan_Calibration_Flow] ====Done====
2479 11:36:00.392975
2480 11:36:00.395828 [DutyScan_Calibration_Flow] k_type=3
2481 11:36:00.412508
2482 11:36:00.412589 ==DQM 0 ==
2483 11:36:00.416181 Final DQM duty delay cell = 0
2484 11:36:00.419032 [0] MAX Duty = 5000%(X100), DQS PI = 22
2485 11:36:00.422151 [0] MIN Duty = 4876%(X100), DQS PI = 0
2486 11:36:00.422227 [0] AVG Duty = 4938%(X100)
2487 11:36:00.425551
2488 11:36:00.425625 ==DQM 1 ==
2489 11:36:00.429328 Final DQM duty delay cell = 0
2490 11:36:00.432173 [0] MAX Duty = 5031%(X100), DQS PI = 36
2491 11:36:00.435721 [0] MIN Duty = 4907%(X100), DQS PI = 4
2492 11:36:00.435795 [0] AVG Duty = 4969%(X100)
2493 11:36:00.439126
2494 11:36:00.442445 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2495 11:36:00.442520
2496 11:36:00.445427 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2497 11:36:00.448727 [DutyScan_Calibration_Flow] ====Done====
2498 11:36:00.448802
2499 11:36:00.452323 [DutyScan_Calibration_Flow] k_type=2
2500 11:36:00.468847
2501 11:36:00.468922 ==DQ 0 ==
2502 11:36:00.471949 Final DQ duty delay cell = 0
2503 11:36:00.475824 [0] MAX Duty = 5062%(X100), DQS PI = 12
2504 11:36:00.479017 [0] MIN Duty = 4938%(X100), DQS PI = 54
2505 11:36:00.479092 [0] AVG Duty = 5000%(X100)
2506 11:36:00.479150
2507 11:36:00.482162 ==DQ 1 ==
2508 11:36:00.485858 Final DQ duty delay cell = 0
2509 11:36:00.488639 [0] MAX Duty = 5125%(X100), DQS PI = 34
2510 11:36:00.492148 [0] MIN Duty = 4938%(X100), DQS PI = 26
2511 11:36:00.492223 [0] AVG Duty = 5031%(X100)
2512 11:36:00.492281
2513 11:36:00.495601 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2514 11:36:00.498817
2515 11:36:00.502241 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2516 11:36:00.505612 [DutyScan_Calibration_Flow] ====Done====
2517 11:36:00.508875 nWR fixed to 30
2518 11:36:00.508950 [ModeRegInit_LP4] CH0 RK0
2519 11:36:00.512002 [ModeRegInit_LP4] CH0 RK1
2520 11:36:00.515129 [ModeRegInit_LP4] CH1 RK0
2521 11:36:00.515203 [ModeRegInit_LP4] CH1 RK1
2522 11:36:00.518653 match AC timing 7
2523 11:36:00.522023 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2524 11:36:00.525638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2525 11:36:00.532305 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2526 11:36:00.535683 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2527 11:36:00.542135 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2528 11:36:00.542209 ==
2529 11:36:00.545911 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 11:36:00.548849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 11:36:00.548924 ==
2532 11:36:00.555633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 11:36:00.559114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 11:36:00.568680 [CA 0] Center 40 (10~71) winsize 62
2535 11:36:00.572057 [CA 1] Center 39 (9~70) winsize 62
2536 11:36:00.575414 [CA 2] Center 36 (6~66) winsize 61
2537 11:36:00.579083 [CA 3] Center 35 (5~66) winsize 62
2538 11:36:00.582705 [CA 4] Center 34 (4~65) winsize 62
2539 11:36:00.585432 [CA 5] Center 33 (3~63) winsize 61
2540 11:36:00.585508
2541 11:36:00.588842 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2542 11:36:00.588918
2543 11:36:00.592257 [CATrainingPosCal] consider 1 rank data
2544 11:36:00.595356 u2DelayCellTimex100 = 270/100 ps
2545 11:36:00.598869 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2546 11:36:00.605501 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2547 11:36:00.608937 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2548 11:36:00.612228 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 11:36:00.615308 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2550 11:36:00.618903 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2551 11:36:00.618978
2552 11:36:00.622081 CA PerBit enable=1, Macro0, CA PI delay=33
2553 11:36:00.622193
2554 11:36:00.625306 [CBTSetCACLKResult] CA Dly = 33
2555 11:36:00.625382 CS Dly: 7 (0~38)
2556 11:36:00.628869 ==
2557 11:36:00.632061 Dram Type= 6, Freq= 0, CH_0, rank 1
2558 11:36:00.635569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 11:36:00.635645 ==
2560 11:36:00.639034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2561 11:36:00.645374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2562 11:36:00.654900 [CA 0] Center 40 (10~70) winsize 61
2563 11:36:00.658038 [CA 1] Center 39 (9~70) winsize 62
2564 11:36:00.661742 [CA 2] Center 35 (5~66) winsize 62
2565 11:36:00.664760 [CA 3] Center 35 (5~66) winsize 62
2566 11:36:00.668289 [CA 4] Center 34 (4~65) winsize 62
2567 11:36:00.671547 [CA 5] Center 33 (3~63) winsize 61
2568 11:36:00.671622
2569 11:36:00.674970 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2570 11:36:00.675046
2571 11:36:00.678299 [CATrainingPosCal] consider 2 rank data
2572 11:36:00.681655 u2DelayCellTimex100 = 270/100 ps
2573 11:36:00.685355 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2574 11:36:00.691895 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2575 11:36:00.695067 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2576 11:36:00.698083 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2577 11:36:00.701908 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2578 11:36:00.704791 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2579 11:36:00.704867
2580 11:36:00.708331 CA PerBit enable=1, Macro0, CA PI delay=33
2581 11:36:00.708406
2582 11:36:00.711636 [CBTSetCACLKResult] CA Dly = 33
2583 11:36:00.711711 CS Dly: 8 (0~40)
2584 11:36:00.714688
2585 11:36:00.718019 ----->DramcWriteLeveling(PI) begin...
2586 11:36:00.718095 ==
2587 11:36:00.721232 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 11:36:00.724765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 11:36:00.724863 ==
2590 11:36:00.728174 Write leveling (Byte 0): 33 => 33
2591 11:36:00.731738 Write leveling (Byte 1): 30 => 30
2592 11:36:00.734994 DramcWriteLeveling(PI) end<-----
2593 11:36:00.735062
2594 11:36:00.735117 ==
2595 11:36:00.738020 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 11:36:00.741639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 11:36:00.741702 ==
2598 11:36:00.744637 [Gating] SW mode calibration
2599 11:36:00.751258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2600 11:36:00.758243 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2601 11:36:00.761513 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2602 11:36:00.764667 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2603 11:36:00.771442 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 11:36:00.774663 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 11:36:00.778317 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 11:36:00.781598 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:36:00.788122 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:36:00.791735 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2609 11:36:00.794933 1 0 0 | B1->B0 | 3131 2525 | 0 0 | (0 0) (1 0)
2610 11:36:00.801523 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2611 11:36:00.804886 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 11:36:00.808101 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 11:36:00.814491 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:36:00.818114 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:36:00.821568 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:36:00.827727 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2617 11:36:00.831115 1 1 0 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
2618 11:36:00.834589 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2619 11:36:00.841553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:36:00.844785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 11:36:00.848094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:36:00.854349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:36:00.857598 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:36:00.861035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 11:36:00.867777 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 11:36:00.870790 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2627 11:36:00.874115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:36:00.880814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:36:00.884171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:36:00.888069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:36:00.894076 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:36:00.897884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:36:00.900654 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:36:00.907644 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:36:00.911116 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:36:00.913946 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:36:00.920810 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:36:00.924362 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:36:00.927393 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:36:00.933784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2641 11:36:00.937206 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2642 11:36:00.940758 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 11:36:00.944045 Total UI for P1: 0, mck2ui 16
2644 11:36:00.947491 best dqsien dly found for B0: ( 1, 3, 30)
2645 11:36:00.950913 Total UI for P1: 0, mck2ui 16
2646 11:36:00.954305 best dqsien dly found for B1: ( 1, 4, 2)
2647 11:36:00.957898 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2648 11:36:00.960808 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2649 11:36:00.960901
2650 11:36:00.964619 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2651 11:36:00.967355 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2652 11:36:00.971016 [Gating] SW calibration Done
2653 11:36:00.971126 ==
2654 11:36:00.974080 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 11:36:00.980915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 11:36:00.981120 ==
2657 11:36:00.981232 RX Vref Scan: 0
2658 11:36:00.981333
2659 11:36:00.984298 RX Vref 0 -> 0, step: 1
2660 11:36:00.984464
2661 11:36:00.987631 RX Delay -40 -> 252, step: 8
2662 11:36:00.991164 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2663 11:36:00.993775 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2664 11:36:00.997534 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2665 11:36:01.000866 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2666 11:36:01.007160 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2667 11:36:01.010698 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2668 11:36:01.013880 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2669 11:36:01.017212 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2670 11:36:01.020503 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2671 11:36:01.023914 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2672 11:36:01.030514 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2673 11:36:01.034002 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2674 11:36:01.037214 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2675 11:36:01.040753 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2676 11:36:01.043907 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2677 11:36:01.050538 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2678 11:36:01.050645 ==
2679 11:36:01.054056 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 11:36:01.057237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 11:36:01.057314 ==
2682 11:36:01.057399 DQS Delay:
2683 11:36:01.060652 DQS0 = 0, DQS1 = 0
2684 11:36:01.060746 DQM Delay:
2685 11:36:01.064029 DQM0 = 111, DQM1 = 103
2686 11:36:01.064120 DQ Delay:
2687 11:36:01.067702 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2688 11:36:01.070737 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2689 11:36:01.073975 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2690 11:36:01.077303 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2691 11:36:01.077398
2692 11:36:01.077481
2693 11:36:01.080982 ==
2694 11:36:01.081102 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 11:36:01.087241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 11:36:01.087393 ==
2697 11:36:01.087515
2698 11:36:01.087595
2699 11:36:01.090335 TX Vref Scan disable
2700 11:36:01.090400 == TX Byte 0 ==
2701 11:36:01.093738 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2702 11:36:01.100507 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2703 11:36:01.100601 == TX Byte 1 ==
2704 11:36:01.103822 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 11:36:01.110828 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 11:36:01.110935 ==
2707 11:36:01.113498 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 11:36:01.116823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 11:36:01.116915 ==
2710 11:36:01.129285 TX Vref=22, minBit 4, minWin=25, winSum=415
2711 11:36:01.132831 TX Vref=24, minBit 7, minWin=25, winSum=423
2712 11:36:01.135704 TX Vref=26, minBit 7, minWin=26, winSum=429
2713 11:36:01.139269 TX Vref=28, minBit 7, minWin=26, winSum=435
2714 11:36:01.142814 TX Vref=30, minBit 13, minWin=26, winSum=435
2715 11:36:01.149388 TX Vref=32, minBit 2, minWin=26, winSum=429
2716 11:36:01.152654 [TxChooseVref] Worse bit 7, Min win 26, Win sum 435, Final Vref 28
2717 11:36:01.152745
2718 11:36:01.156123 Final TX Range 1 Vref 28
2719 11:36:01.156214
2720 11:36:01.156298 ==
2721 11:36:01.159410 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 11:36:01.162673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 11:36:01.162767 ==
2724 11:36:01.162851
2725 11:36:01.166397
2726 11:36:01.166466 TX Vref Scan disable
2727 11:36:01.169185 == TX Byte 0 ==
2728 11:36:01.172373 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2729 11:36:01.176200 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2730 11:36:01.179015 == TX Byte 1 ==
2731 11:36:01.182520 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2732 11:36:01.185917 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2733 11:36:01.189651
2734 11:36:01.189740 [DATLAT]
2735 11:36:01.189825 Freq=1200, CH0 RK0
2736 11:36:01.189905
2737 11:36:01.193025 DATLAT Default: 0xd
2738 11:36:01.193115 0, 0xFFFF, sum = 0
2739 11:36:01.196109 1, 0xFFFF, sum = 0
2740 11:36:01.196201 2, 0xFFFF, sum = 0
2741 11:36:01.199187 3, 0xFFFF, sum = 0
2742 11:36:01.199285 4, 0xFFFF, sum = 0
2743 11:36:01.202411 5, 0xFFFF, sum = 0
2744 11:36:01.205897 6, 0xFFFF, sum = 0
2745 11:36:01.206008 7, 0xFFFF, sum = 0
2746 11:36:01.209432 8, 0xFFFF, sum = 0
2747 11:36:01.209522 9, 0xFFFF, sum = 0
2748 11:36:01.212281 10, 0xFFFF, sum = 0
2749 11:36:01.212400 11, 0xFFFF, sum = 0
2750 11:36:01.215744 12, 0x0, sum = 1
2751 11:36:01.215860 13, 0x0, sum = 2
2752 11:36:01.219122 14, 0x0, sum = 3
2753 11:36:01.219248 15, 0x0, sum = 4
2754 11:36:01.219353 best_step = 13
2755 11:36:01.219455
2756 11:36:01.222602 ==
2757 11:36:01.225580 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 11:36:01.229186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 11:36:01.229268 ==
2760 11:36:01.229340 RX Vref Scan: 1
2761 11:36:01.229444
2762 11:36:01.232357 Set Vref Range= 32 -> 127
2763 11:36:01.232480
2764 11:36:01.236012 RX Vref 32 -> 127, step: 1
2765 11:36:01.236132
2766 11:36:01.239169 RX Delay -37 -> 252, step: 4
2767 11:36:01.239291
2768 11:36:01.242517 Set Vref, RX VrefLevel [Byte0]: 32
2769 11:36:01.245947 [Byte1]: 32
2770 11:36:01.246068
2771 11:36:01.248896 Set Vref, RX VrefLevel [Byte0]: 33
2772 11:36:01.252528 [Byte1]: 33
2773 11:36:01.256330
2774 11:36:01.256477 Set Vref, RX VrefLevel [Byte0]: 34
2775 11:36:01.259602 [Byte1]: 34
2776 11:36:01.263940
2777 11:36:01.264091 Set Vref, RX VrefLevel [Byte0]: 35
2778 11:36:01.267220 [Byte1]: 35
2779 11:36:01.271948
2780 11:36:01.272037 Set Vref, RX VrefLevel [Byte0]: 36
2781 11:36:01.275088 [Byte1]: 36
2782 11:36:01.279949
2783 11:36:01.280037 Set Vref, RX VrefLevel [Byte0]: 37
2784 11:36:01.283039 [Byte1]: 37
2785 11:36:01.287692
2786 11:36:01.287779 Set Vref, RX VrefLevel [Byte0]: 38
2787 11:36:01.290779 [Byte1]: 38
2788 11:36:01.296309
2789 11:36:01.296398 Set Vref, RX VrefLevel [Byte0]: 39
2790 11:36:01.299027 [Byte1]: 39
2791 11:36:01.303902
2792 11:36:01.303964 Set Vref, RX VrefLevel [Byte0]: 40
2793 11:36:01.306956 [Byte1]: 40
2794 11:36:01.311786
2795 11:36:01.311865 Set Vref, RX VrefLevel [Byte0]: 41
2796 11:36:01.315254 [Byte1]: 41
2797 11:36:01.319897
2798 11:36:01.319996 Set Vref, RX VrefLevel [Byte0]: 42
2799 11:36:01.323225 [Byte1]: 42
2800 11:36:01.327714
2801 11:36:01.327816 Set Vref, RX VrefLevel [Byte0]: 43
2802 11:36:01.331149 [Byte1]: 43
2803 11:36:01.336005
2804 11:36:01.336127 Set Vref, RX VrefLevel [Byte0]: 44
2805 11:36:01.339102 [Byte1]: 44
2806 11:36:01.343863
2807 11:36:01.344000 Set Vref, RX VrefLevel [Byte0]: 45
2808 11:36:01.347347 [Byte1]: 45
2809 11:36:01.351982
2810 11:36:01.352320 Set Vref, RX VrefLevel [Byte0]: 46
2811 11:36:01.354981 [Byte1]: 46
2812 11:36:01.360268
2813 11:36:01.360536 Set Vref, RX VrefLevel [Byte0]: 47
2814 11:36:01.363738 [Byte1]: 47
2815 11:36:01.367978
2816 11:36:01.368326 Set Vref, RX VrefLevel [Byte0]: 48
2817 11:36:01.371340 [Byte1]: 48
2818 11:36:01.376147
2819 11:36:01.376640 Set Vref, RX VrefLevel [Byte0]: 49
2820 11:36:01.379630 [Byte1]: 49
2821 11:36:01.384155
2822 11:36:01.384587 Set Vref, RX VrefLevel [Byte0]: 50
2823 11:36:01.387450 [Byte1]: 50
2824 11:36:01.392053
2825 11:36:01.392474 Set Vref, RX VrefLevel [Byte0]: 51
2826 11:36:01.395067 [Byte1]: 51
2827 11:36:01.399756
2828 11:36:01.399830 Set Vref, RX VrefLevel [Byte0]: 52
2829 11:36:01.403330 [Byte1]: 52
2830 11:36:01.407675
2831 11:36:01.407750 Set Vref, RX VrefLevel [Byte0]: 53
2832 11:36:01.411173 [Byte1]: 53
2833 11:36:01.415583
2834 11:36:01.415657 Set Vref, RX VrefLevel [Byte0]: 54
2835 11:36:01.419185 [Byte1]: 54
2836 11:36:01.423455
2837 11:36:01.423529 Set Vref, RX VrefLevel [Byte0]: 55
2838 11:36:01.426862 [Byte1]: 55
2839 11:36:01.431626
2840 11:36:01.431700 Set Vref, RX VrefLevel [Byte0]: 56
2841 11:36:01.434989 [Byte1]: 56
2842 11:36:01.439598
2843 11:36:01.439676 Set Vref, RX VrefLevel [Byte0]: 57
2844 11:36:01.442964 [Byte1]: 57
2845 11:36:01.447443
2846 11:36:01.447517 Set Vref, RX VrefLevel [Byte0]: 58
2847 11:36:01.451008 [Byte1]: 58
2848 11:36:01.455477
2849 11:36:01.455551 Set Vref, RX VrefLevel [Byte0]: 59
2850 11:36:01.459023 [Byte1]: 59
2851 11:36:01.463501
2852 11:36:01.463575 Set Vref, RX VrefLevel [Byte0]: 60
2853 11:36:01.466935 [Byte1]: 60
2854 11:36:01.471465
2855 11:36:01.471540 Set Vref, RX VrefLevel [Byte0]: 61
2856 11:36:01.475012 [Byte1]: 61
2857 11:36:01.479424
2858 11:36:01.479500 Set Vref, RX VrefLevel [Byte0]: 62
2859 11:36:01.483057 [Byte1]: 62
2860 11:36:01.487924
2861 11:36:01.487998 Set Vref, RX VrefLevel [Byte0]: 63
2862 11:36:01.490800 [Byte1]: 63
2863 11:36:01.495816
2864 11:36:01.495891 Set Vref, RX VrefLevel [Byte0]: 64
2865 11:36:01.499156 [Byte1]: 64
2866 11:36:01.503887
2867 11:36:01.503961 Set Vref, RX VrefLevel [Byte0]: 65
2868 11:36:01.506832 [Byte1]: 65
2869 11:36:01.511899
2870 11:36:01.511972 Set Vref, RX VrefLevel [Byte0]: 66
2871 11:36:01.515086 [Byte1]: 66
2872 11:36:01.520059
2873 11:36:01.520133 Set Vref, RX VrefLevel [Byte0]: 67
2874 11:36:01.523056 [Byte1]: 67
2875 11:36:01.527746
2876 11:36:01.527819 Set Vref, RX VrefLevel [Byte0]: 68
2877 11:36:01.530714 [Byte1]: 68
2878 11:36:01.535443
2879 11:36:01.535517 Set Vref, RX VrefLevel [Byte0]: 69
2880 11:36:01.538778 [Byte1]: 69
2881 11:36:01.543589
2882 11:36:01.543663 Set Vref, RX VrefLevel [Byte0]: 70
2883 11:36:01.547269 [Byte1]: 70
2884 11:36:01.551493
2885 11:36:01.551567 Set Vref, RX VrefLevel [Byte0]: 71
2886 11:36:01.554685 [Byte1]: 71
2887 11:36:01.559903
2888 11:36:01.559977 Set Vref, RX VrefLevel [Byte0]: 72
2889 11:36:01.563358 [Byte1]: 72
2890 11:36:01.567898
2891 11:36:01.567973 Set Vref, RX VrefLevel [Byte0]: 73
2892 11:36:01.571200 [Byte1]: 73
2893 11:36:01.575621
2894 11:36:01.575695 Final RX Vref Byte 0 = 61 to rank0
2895 11:36:01.579358 Final RX Vref Byte 1 = 52 to rank0
2896 11:36:01.582133 Final RX Vref Byte 0 = 61 to rank1
2897 11:36:01.585510 Final RX Vref Byte 1 = 52 to rank1==
2898 11:36:01.589285 Dram Type= 6, Freq= 0, CH_0, rank 0
2899 11:36:01.595674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 11:36:01.595749 ==
2901 11:36:01.595807 DQS Delay:
2902 11:36:01.595860 DQS0 = 0, DQS1 = 0
2903 11:36:01.598941 DQM Delay:
2904 11:36:01.599017 DQM0 = 111, DQM1 = 101
2905 11:36:01.602275 DQ Delay:
2906 11:36:01.605441 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =106
2907 11:36:01.609147 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2908 11:36:01.612470 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2909 11:36:01.615555 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2910 11:36:01.615650
2911 11:36:01.615733
2912 11:36:01.621825 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2913 11:36:01.625279 CH0 RK0: MR19=303, MR18=FCFC
2914 11:36:01.632140 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2915 11:36:01.632232
2916 11:36:01.635420 ----->DramcWriteLeveling(PI) begin...
2917 11:36:01.635515 ==
2918 11:36:01.639006 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 11:36:01.641941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 11:36:01.645255 ==
2921 11:36:01.645322 Write leveling (Byte 0): 30 => 30
2922 11:36:01.648565 Write leveling (Byte 1): 29 => 29
2923 11:36:01.652421 DramcWriteLeveling(PI) end<-----
2924 11:36:01.652514
2925 11:36:01.652594 ==
2926 11:36:01.655699 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 11:36:01.662028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 11:36:01.662177 ==
2929 11:36:01.662264 [Gating] SW mode calibration
2930 11:36:01.672253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2931 11:36:01.675509 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2932 11:36:01.682193 0 15 0 | B1->B0 | 2828 3433 | 0 1 | (0 0) (1 1)
2933 11:36:01.685706 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 11:36:01.689099 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 11:36:01.692007 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 11:36:01.698730 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 11:36:01.702632 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 11:36:01.705497 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2939 11:36:01.712471 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2940 11:36:01.716157 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2941 11:36:01.719041 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 11:36:01.725126 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 11:36:01.729448 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 11:36:01.732200 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 11:36:01.738677 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 11:36:01.742188 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2947 11:36:01.745635 1 0 28 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2948 11:36:01.752286 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2949 11:36:01.755630 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 11:36:01.759307 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 11:36:01.766056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 11:36:01.768932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 11:36:01.772126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 11:36:01.779180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2955 11:36:01.782277 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2956 11:36:01.786019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2957 11:36:01.789413 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:36:01.796191 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:36:01.799094 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:36:01.802335 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:36:01.809079 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:36:01.812471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:36:01.815544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:36:01.822238 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:36:01.825711 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:36:01.829599 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:36:01.835271 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 11:36:01.838812 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 11:36:01.842059 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:36:01.849463 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2971 11:36:01.852592 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2972 11:36:01.855332 Total UI for P1: 0, mck2ui 16
2973 11:36:01.859070 best dqsien dly found for B0: ( 1, 3, 24)
2974 11:36:01.862439 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 11:36:01.865662 Total UI for P1: 0, mck2ui 16
2976 11:36:01.868691 best dqsien dly found for B1: ( 1, 3, 28)
2977 11:36:01.872358 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2978 11:36:01.875380 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2979 11:36:01.875847
2980 11:36:01.882258 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2981 11:36:01.885954 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2982 11:36:01.886504 [Gating] SW calibration Done
2983 11:36:01.889127 ==
2984 11:36:01.889630 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 11:36:01.895326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 11:36:01.895752 ==
2987 11:36:01.896079 RX Vref Scan: 0
2988 11:36:01.896380
2989 11:36:01.898935 RX Vref 0 -> 0, step: 1
2990 11:36:01.899357
2991 11:36:01.902226 RX Delay -40 -> 252, step: 8
2992 11:36:01.905638 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2993 11:36:01.909165 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2994 11:36:01.912375 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2995 11:36:01.919009 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2996 11:36:01.922297 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2997 11:36:01.925871 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2998 11:36:01.928849 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2999 11:36:01.932429 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3000 11:36:01.938062 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3001 11:36:01.941424 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3002 11:36:01.944781 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3003 11:36:01.948439 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3004 11:36:01.951747 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3005 11:36:01.958411 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3006 11:36:01.961603 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3007 11:36:01.964866 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3008 11:36:01.964942 ==
3009 11:36:01.967970 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:36:01.971814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:36:01.971891 ==
3012 11:36:01.975073 DQS Delay:
3013 11:36:01.975148 DQS0 = 0, DQS1 = 0
3014 11:36:01.975206 DQM Delay:
3015 11:36:01.978375 DQM0 = 112, DQM1 = 101
3016 11:36:01.978450 DQ Delay:
3017 11:36:01.981928 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3018 11:36:01.985165 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3019 11:36:01.988587 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3020 11:36:01.995207 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3021 11:36:01.995345
3022 11:36:01.995424
3023 11:36:01.995497 ==
3024 11:36:01.998646 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 11:36:02.001720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 11:36:02.001833 ==
3027 11:36:02.001920
3028 11:36:02.002000
3029 11:36:02.005047 TX Vref Scan disable
3030 11:36:02.005172 == TX Byte 0 ==
3031 11:36:02.011602 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3032 11:36:02.015333 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3033 11:36:02.015492 == TX Byte 1 ==
3034 11:36:02.021811 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3035 11:36:02.025403 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3036 11:36:02.025620 ==
3037 11:36:02.028369 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 11:36:02.031880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 11:36:02.032152 ==
3040 11:36:02.044641 TX Vref=22, minBit 1, minWin=26, winSum=427
3041 11:36:02.048127 TX Vref=24, minBit 5, minWin=26, winSum=433
3042 11:36:02.051730 TX Vref=26, minBit 1, minWin=26, winSum=437
3043 11:36:02.054469 TX Vref=28, minBit 2, minWin=27, winSum=437
3044 11:36:02.057807 TX Vref=30, minBit 10, minWin=26, winSum=442
3045 11:36:02.064631 TX Vref=32, minBit 2, minWin=27, winSum=443
3046 11:36:02.067945 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 32
3047 11:36:02.068378
3048 11:36:02.071174 Final TX Range 1 Vref 32
3049 11:36:02.071561
3050 11:36:02.071873 ==
3051 11:36:02.074398 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 11:36:02.077639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 11:36:02.081010 ==
3054 11:36:02.081437
3055 11:36:02.081751
3056 11:36:02.082024 TX Vref Scan disable
3057 11:36:02.084135 == TX Byte 0 ==
3058 11:36:02.087450 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3059 11:36:02.094619 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3060 11:36:02.095008 == TX Byte 1 ==
3061 11:36:02.097441 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3062 11:36:02.101255 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3063 11:36:02.104199
3064 11:36:02.104580 [DATLAT]
3065 11:36:02.104874 Freq=1200, CH0 RK1
3066 11:36:02.105153
3067 11:36:02.107767 DATLAT Default: 0xd
3068 11:36:02.108167 0, 0xFFFF, sum = 0
3069 11:36:02.111008 1, 0xFFFF, sum = 0
3070 11:36:02.111397 2, 0xFFFF, sum = 0
3071 11:36:02.113976 3, 0xFFFF, sum = 0
3072 11:36:02.117670 4, 0xFFFF, sum = 0
3073 11:36:02.118151 5, 0xFFFF, sum = 0
3074 11:36:02.120633 6, 0xFFFF, sum = 0
3075 11:36:02.121020 7, 0xFFFF, sum = 0
3076 11:36:02.124130 8, 0xFFFF, sum = 0
3077 11:36:02.124518 9, 0xFFFF, sum = 0
3078 11:36:02.127563 10, 0xFFFF, sum = 0
3079 11:36:02.127951 11, 0xFFFF, sum = 0
3080 11:36:02.131102 12, 0x0, sum = 1
3081 11:36:02.131491 13, 0x0, sum = 2
3082 11:36:02.133913 14, 0x0, sum = 3
3083 11:36:02.134338 15, 0x0, sum = 4
3084 11:36:02.137159 best_step = 13
3085 11:36:02.137539
3086 11:36:02.137835 ==
3087 11:36:02.140685 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 11:36:02.144361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 11:36:02.144748 ==
3090 11:36:02.145045 RX Vref Scan: 0
3091 11:36:02.145317
3092 11:36:02.147216 RX Vref 0 -> 0, step: 1
3093 11:36:02.147600
3094 11:36:02.150679 RX Delay -37 -> 252, step: 4
3095 11:36:02.157019 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3096 11:36:02.160468 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3097 11:36:02.164094 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3098 11:36:02.167190 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3099 11:36:02.170499 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3100 11:36:02.176889 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3101 11:36:02.180419 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3102 11:36:02.183428 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3103 11:36:02.186795 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3104 11:36:02.190568 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3105 11:36:02.196525 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3106 11:36:02.199830 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3107 11:36:02.203622 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3108 11:36:02.206684 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3109 11:36:02.210209 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3110 11:36:02.216528 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3111 11:36:02.216913 ==
3112 11:36:02.220288 Dram Type= 6, Freq= 0, CH_0, rank 1
3113 11:36:02.223113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 11:36:02.223500 ==
3115 11:36:02.223798 DQS Delay:
3116 11:36:02.226700 DQS0 = 0, DQS1 = 0
3117 11:36:02.227182 DQM Delay:
3118 11:36:02.229937 DQM0 = 110, DQM1 = 101
3119 11:36:02.230355 DQ Delay:
3120 11:36:02.233004 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3121 11:36:02.236428 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3122 11:36:02.240081 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3123 11:36:02.243454 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3124 11:36:02.243837
3125 11:36:02.244129
3126 11:36:02.253106 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3127 11:36:02.256849 CH0 RK1: MR19=403, MR18=14FC
3128 11:36:02.263156 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3129 11:36:02.263593 [RxdqsGatingPostProcess] freq 1200
3130 11:36:02.269422 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3131 11:36:02.273001 best DQS0 dly(2T, 0.5T) = (0, 11)
3132 11:36:02.276428 best DQS1 dly(2T, 0.5T) = (0, 12)
3133 11:36:02.279762 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3134 11:36:02.283447 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3135 11:36:02.286442 best DQS0 dly(2T, 0.5T) = (0, 11)
3136 11:36:02.289338 best DQS1 dly(2T, 0.5T) = (0, 11)
3137 11:36:02.292794 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3138 11:36:02.296362 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3139 11:36:02.300134 Pre-setting of DQS Precalculation
3140 11:36:02.302937 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3141 11:36:02.303326 ==
3142 11:36:02.306268 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 11:36:02.309562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 11:36:02.312767 ==
3145 11:36:02.316202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 11:36:02.322526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 11:36:02.330707 [CA 0] Center 37 (7~67) winsize 61
3148 11:36:02.333959 [CA 1] Center 37 (7~68) winsize 62
3149 11:36:02.337295 [CA 2] Center 34 (4~64) winsize 61
3150 11:36:02.340649 [CA 3] Center 33 (3~64) winsize 62
3151 11:36:02.343962 [CA 4] Center 34 (4~64) winsize 61
3152 11:36:02.347730 [CA 5] Center 33 (3~63) winsize 61
3153 11:36:02.348166
3154 11:36:02.350619 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 11:36:02.351055
3156 11:36:02.353733 [CATrainingPosCal] consider 1 rank data
3157 11:36:02.357169 u2DelayCellTimex100 = 270/100 ps
3158 11:36:02.360479 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3159 11:36:02.367284 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 11:36:02.370481 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 11:36:02.374080 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3162 11:36:02.376880 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 11:36:02.380782 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 11:36:02.381169
3165 11:36:02.383772 CA PerBit enable=1, Macro0, CA PI delay=33
3166 11:36:02.384255
3167 11:36:02.386704 [CBTSetCACLKResult] CA Dly = 33
3168 11:36:02.387173 CS Dly: 5 (0~36)
3169 11:36:02.390371 ==
3170 11:36:02.393327 Dram Type= 6, Freq= 0, CH_1, rank 1
3171 11:36:02.397044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 11:36:02.397465 ==
3173 11:36:02.400275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3174 11:36:02.406471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3175 11:36:02.416603 [CA 0] Center 37 (7~67) winsize 61
3176 11:36:02.419657 [CA 1] Center 37 (7~68) winsize 62
3177 11:36:02.422872 [CA 2] Center 34 (4~65) winsize 62
3178 11:36:02.426022 [CA 3] Center 33 (3~64) winsize 62
3179 11:36:02.429028 [CA 4] Center 34 (4~65) winsize 62
3180 11:36:02.432545 [CA 5] Center 33 (3~63) winsize 61
3181 11:36:02.432921
3182 11:36:02.435864 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3183 11:36:02.436273
3184 11:36:02.439226 [CATrainingPosCal] consider 2 rank data
3185 11:36:02.442909 u2DelayCellTimex100 = 270/100 ps
3186 11:36:02.445870 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3187 11:36:02.452916 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3188 11:36:02.455852 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 11:36:02.459111 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 11:36:02.462338 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 11:36:02.465770 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3192 11:36:02.466199
3193 11:36:02.469197 CA PerBit enable=1, Macro0, CA PI delay=33
3194 11:36:02.469673
3195 11:36:02.472128 [CBTSetCACLKResult] CA Dly = 33
3196 11:36:02.475595 CS Dly: 6 (0~39)
3197 11:36:02.476112
3198 11:36:02.479070 ----->DramcWriteLeveling(PI) begin...
3199 11:36:02.479527 ==
3200 11:36:02.482092 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 11:36:02.486075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 11:36:02.486534 ==
3203 11:36:02.488490 Write leveling (Byte 0): 26 => 26
3204 11:36:02.492018 Write leveling (Byte 1): 28 => 28
3205 11:36:02.495540 DramcWriteLeveling(PI) end<-----
3206 11:36:02.496052
3207 11:36:02.496438 ==
3208 11:36:02.498975 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 11:36:02.502417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 11:36:02.502925 ==
3211 11:36:02.504769 [Gating] SW mode calibration
3212 11:36:02.512078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3213 11:36:02.518312 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3214 11:36:02.521604 0 15 0 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (0 0)
3215 11:36:02.525083 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 11:36:02.531520 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 11:36:02.534602 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 11:36:02.537980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 11:36:02.544629 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 11:36:02.547852 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 11:36:02.551387 0 15 28 | B1->B0 | 2c2c 2a2a | 1 1 | (1 0) (1 0)
3222 11:36:02.557763 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 11:36:02.560596 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 11:36:02.564195 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 11:36:02.570903 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 11:36:02.574061 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 11:36:02.577355 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 11:36:02.584305 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3229 11:36:02.587684 1 0 28 | B1->B0 | 3e3e 4343 | 0 0 | (1 1) (0 0)
3230 11:36:02.590626 1 1 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
3231 11:36:02.597313 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:36:02.600858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 11:36:02.604254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 11:36:02.611169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 11:36:02.613875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 11:36:02.617397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 11:36:02.623816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3238 11:36:02.627532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3239 11:36:02.630369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:36:02.636988 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:36:02.640341 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:36:02.643769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:36:02.650283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:36:02.653513 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:36:02.657064 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:36:02.664016 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:36:02.666805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 11:36:02.670210 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:36:02.677178 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 11:36:02.680390 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 11:36:02.683292 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 11:36:02.689857 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 11:36:02.693161 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3254 11:36:02.696573 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 11:36:02.700023 Total UI for P1: 0, mck2ui 16
3256 11:36:02.703343 best dqsien dly found for B0: ( 1, 3, 28)
3257 11:36:02.706713 Total UI for P1: 0, mck2ui 16
3258 11:36:02.710242 best dqsien dly found for B1: ( 1, 3, 28)
3259 11:36:02.713141 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3260 11:36:02.717066 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3261 11:36:02.717473
3262 11:36:02.723303 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3263 11:36:02.726966 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3264 11:36:02.727362 [Gating] SW calibration Done
3265 11:36:02.730001 ==
3266 11:36:02.733053 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 11:36:02.736476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 11:36:02.736844 ==
3269 11:36:02.737179 RX Vref Scan: 0
3270 11:36:02.737475
3271 11:36:02.739592 RX Vref 0 -> 0, step: 1
3272 11:36:02.740115
3273 11:36:02.742960 RX Delay -40 -> 252, step: 8
3274 11:36:02.746453 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3275 11:36:02.749898 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3276 11:36:02.753541 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3277 11:36:02.759847 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3278 11:36:02.763243 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3279 11:36:02.766159 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3280 11:36:02.769816 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3281 11:36:02.772855 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3282 11:36:02.779386 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3283 11:36:02.782656 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3284 11:36:02.785889 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3285 11:36:02.789371 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3286 11:36:02.792617 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3287 11:36:02.799876 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3288 11:36:02.802576 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3289 11:36:02.805865 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3290 11:36:02.806374 ==
3291 11:36:02.809069 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:36:02.815310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:36:02.815387 ==
3294 11:36:02.815446 DQS Delay:
3295 11:36:02.815508 DQS0 = 0, DQS1 = 0
3296 11:36:02.819346 DQM Delay:
3297 11:36:02.819425 DQM0 = 114, DQM1 = 105
3298 11:36:02.822216 DQ Delay:
3299 11:36:02.825337 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =115
3300 11:36:02.828671 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3301 11:36:02.832035 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3302 11:36:02.835255 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3303 11:36:02.835319
3304 11:36:02.835372
3305 11:36:02.835423 ==
3306 11:36:02.839176 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 11:36:02.842191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 11:36:02.842261 ==
3309 11:36:02.842317
3310 11:36:02.845756
3311 11:36:02.846091 TX Vref Scan disable
3312 11:36:02.849219 == TX Byte 0 ==
3313 11:36:02.852262 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3314 11:36:02.855796 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3315 11:36:02.859059 == TX Byte 1 ==
3316 11:36:02.862783 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3317 11:36:02.865617 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3318 11:36:02.866091 ==
3319 11:36:02.869176 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 11:36:02.875506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 11:36:02.875939 ==
3322 11:36:02.886199 TX Vref=22, minBit 8, minWin=24, winSum=406
3323 11:36:02.889730 TX Vref=24, minBit 10, minWin=24, winSum=409
3324 11:36:02.892976 TX Vref=26, minBit 8, minWin=25, winSum=421
3325 11:36:02.896185 TX Vref=28, minBit 9, minWin=25, winSum=423
3326 11:36:02.899443 TX Vref=30, minBit 9, minWin=25, winSum=423
3327 11:36:02.906089 TX Vref=32, minBit 9, minWin=25, winSum=422
3328 11:36:02.909109 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
3329 11:36:02.909567
3330 11:36:02.912275 Final TX Range 1 Vref 28
3331 11:36:02.912753
3332 11:36:02.913284 ==
3333 11:36:02.915798 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 11:36:02.919281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 11:36:02.922479 ==
3336 11:36:02.922864
3337 11:36:02.923161
3338 11:36:02.923432 TX Vref Scan disable
3339 11:36:02.925564 == TX Byte 0 ==
3340 11:36:02.929049 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3341 11:36:02.936167 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3342 11:36:02.936569 == TX Byte 1 ==
3343 11:36:02.939425 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3344 11:36:02.945599 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3345 11:36:02.945989
3346 11:36:02.946331 [DATLAT]
3347 11:36:02.946612 Freq=1200, CH1 RK0
3348 11:36:02.946878
3349 11:36:02.948881 DATLAT Default: 0xd
3350 11:36:02.952019 0, 0xFFFF, sum = 0
3351 11:36:02.952407 1, 0xFFFF, sum = 0
3352 11:36:02.955761 2, 0xFFFF, sum = 0
3353 11:36:02.956149 3, 0xFFFF, sum = 0
3354 11:36:02.959333 4, 0xFFFF, sum = 0
3355 11:36:02.959723 5, 0xFFFF, sum = 0
3356 11:36:02.962417 6, 0xFFFF, sum = 0
3357 11:36:02.962804 7, 0xFFFF, sum = 0
3358 11:36:02.965718 8, 0xFFFF, sum = 0
3359 11:36:02.966147 9, 0xFFFF, sum = 0
3360 11:36:02.968538 10, 0xFFFF, sum = 0
3361 11:36:02.968928 11, 0xFFFF, sum = 0
3362 11:36:02.971902 12, 0x0, sum = 1
3363 11:36:02.972335 13, 0x0, sum = 2
3364 11:36:02.975541 14, 0x0, sum = 3
3365 11:36:02.975956 15, 0x0, sum = 4
3366 11:36:02.979112 best_step = 13
3367 11:36:02.979504
3368 11:36:02.979894 ==
3369 11:36:02.982321 Dram Type= 6, Freq= 0, CH_1, rank 0
3370 11:36:02.985124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3371 11:36:02.985643 ==
3372 11:36:02.986078 RX Vref Scan: 1
3373 11:36:02.988580
3374 11:36:02.989043 Set Vref Range= 32 -> 127
3375 11:36:02.989458
3376 11:36:02.992151 RX Vref 32 -> 127, step: 1
3377 11:36:02.992635
3378 11:36:02.995062 RX Delay -21 -> 252, step: 4
3379 11:36:02.995532
3380 11:36:02.998722 Set Vref, RX VrefLevel [Byte0]: 32
3381 11:36:03.001706 [Byte1]: 32
3382 11:36:03.002201
3383 11:36:03.004903 Set Vref, RX VrefLevel [Byte0]: 33
3384 11:36:03.008790 [Byte1]: 33
3385 11:36:03.012365
3386 11:36:03.012568 Set Vref, RX VrefLevel [Byte0]: 34
3387 11:36:03.015538 [Byte1]: 34
3388 11:36:03.020257
3389 11:36:03.020420 Set Vref, RX VrefLevel [Byte0]: 35
3390 11:36:03.023115 [Byte1]: 35
3391 11:36:03.027719
3392 11:36:03.027792 Set Vref, RX VrefLevel [Byte0]: 36
3393 11:36:03.031151 [Byte1]: 36
3394 11:36:03.035682
3395 11:36:03.035755 Set Vref, RX VrefLevel [Byte0]: 37
3396 11:36:03.038735 [Byte1]: 37
3397 11:36:03.043686
3398 11:36:03.043759 Set Vref, RX VrefLevel [Byte0]: 38
3399 11:36:03.047301 [Byte1]: 38
3400 11:36:03.051546
3401 11:36:03.051630 Set Vref, RX VrefLevel [Byte0]: 39
3402 11:36:03.054919 [Byte1]: 39
3403 11:36:03.059730
3404 11:36:03.059831 Set Vref, RX VrefLevel [Byte0]: 40
3405 11:36:03.063325 [Byte1]: 40
3406 11:36:03.067348
3407 11:36:03.067457 Set Vref, RX VrefLevel [Byte0]: 41
3408 11:36:03.071235 [Byte1]: 41
3409 11:36:03.075546
3410 11:36:03.075682 Set Vref, RX VrefLevel [Byte0]: 42
3411 11:36:03.079105 [Byte1]: 42
3412 11:36:03.083421
3413 11:36:03.083556 Set Vref, RX VrefLevel [Byte0]: 43
3414 11:36:03.086661 [Byte1]: 43
3415 11:36:03.091202
3416 11:36:03.091381 Set Vref, RX VrefLevel [Byte0]: 44
3417 11:36:03.095379 [Byte1]: 44
3418 11:36:03.099698
3419 11:36:03.100042 Set Vref, RX VrefLevel [Byte0]: 45
3420 11:36:03.103433 [Byte1]: 45
3421 11:36:03.107913
3422 11:36:03.108354 Set Vref, RX VrefLevel [Byte0]: 46
3423 11:36:03.110945 [Byte1]: 46
3424 11:36:03.115764
3425 11:36:03.116345 Set Vref, RX VrefLevel [Byte0]: 47
3426 11:36:03.119088 [Byte1]: 47
3427 11:36:03.123349
3428 11:36:03.123846 Set Vref, RX VrefLevel [Byte0]: 48
3429 11:36:03.127077 [Byte1]: 48
3430 11:36:03.131458
3431 11:36:03.131949 Set Vref, RX VrefLevel [Byte0]: 49
3432 11:36:03.134649 [Byte1]: 49
3433 11:36:03.139229
3434 11:36:03.139678 Set Vref, RX VrefLevel [Byte0]: 50
3435 11:36:03.142207 [Byte1]: 50
3436 11:36:03.147064
3437 11:36:03.147486 Set Vref, RX VrefLevel [Byte0]: 51
3438 11:36:03.150402 [Byte1]: 51
3439 11:36:03.154665
3440 11:36:03.155193 Set Vref, RX VrefLevel [Byte0]: 52
3441 11:36:03.158021 [Byte1]: 52
3442 11:36:03.162698
3443 11:36:03.163117 Set Vref, RX VrefLevel [Byte0]: 53
3444 11:36:03.165944 [Byte1]: 53
3445 11:36:03.171144
3446 11:36:03.171573 Set Vref, RX VrefLevel [Byte0]: 54
3447 11:36:03.174416 [Byte1]: 54
3448 11:36:03.178756
3449 11:36:03.179305 Set Vref, RX VrefLevel [Byte0]: 55
3450 11:36:03.182346 [Byte1]: 55
3451 11:36:03.186761
3452 11:36:03.187186 Set Vref, RX VrefLevel [Byte0]: 56
3453 11:36:03.189276 [Byte1]: 56
3454 11:36:03.194394
3455 11:36:03.194469 Set Vref, RX VrefLevel [Byte0]: 57
3456 11:36:03.197775 [Byte1]: 57
3457 11:36:03.201968
3458 11:36:03.202042 Set Vref, RX VrefLevel [Byte0]: 58
3459 11:36:03.205944 [Byte1]: 58
3460 11:36:03.210563
3461 11:36:03.211045 Set Vref, RX VrefLevel [Byte0]: 59
3462 11:36:03.214089 [Byte1]: 59
3463 11:36:03.218258
3464 11:36:03.218712 Set Vref, RX VrefLevel [Byte0]: 60
3465 11:36:03.221483 [Byte1]: 60
3466 11:36:03.226034
3467 11:36:03.226782 Set Vref, RX VrefLevel [Byte0]: 61
3468 11:36:03.229612 [Byte1]: 61
3469 11:36:03.234134
3470 11:36:03.234681 Set Vref, RX VrefLevel [Byte0]: 62
3471 11:36:03.237369 [Byte1]: 62
3472 11:36:03.242506
3473 11:36:03.242890 Set Vref, RX VrefLevel [Byte0]: 63
3474 11:36:03.245344 [Byte1]: 63
3475 11:36:03.250192
3476 11:36:03.250576 Set Vref, RX VrefLevel [Byte0]: 64
3477 11:36:03.253248 [Byte1]: 64
3478 11:36:03.258581
3479 11:36:03.258963 Set Vref, RX VrefLevel [Byte0]: 65
3480 11:36:03.261182 [Byte1]: 65
3481 11:36:03.266043
3482 11:36:03.266470 Set Vref, RX VrefLevel [Byte0]: 66
3483 11:36:03.268688 [Byte1]: 66
3484 11:36:03.273740
3485 11:36:03.274178 Final RX Vref Byte 0 = 58 to rank0
3486 11:36:03.276704 Final RX Vref Byte 1 = 50 to rank0
3487 11:36:03.280213 Final RX Vref Byte 0 = 58 to rank1
3488 11:36:03.284013 Final RX Vref Byte 1 = 50 to rank1==
3489 11:36:03.286929 Dram Type= 6, Freq= 0, CH_1, rank 0
3490 11:36:03.293596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:36:03.293992 ==
3492 11:36:03.294347 DQS Delay:
3493 11:36:03.297124 DQS0 = 0, DQS1 = 0
3494 11:36:03.297516 DQM Delay:
3495 11:36:03.297819 DQM0 = 114, DQM1 = 105
3496 11:36:03.300178 DQ Delay:
3497 11:36:03.303726 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =110
3498 11:36:03.306841 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3499 11:36:03.309823 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3500 11:36:03.313447 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3501 11:36:03.313828
3502 11:36:03.314169
3503 11:36:03.323596 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 416 ps
3504 11:36:03.323984 CH1 RK0: MR19=303, MR18=F0F6
3505 11:36:03.329947 CH1_RK0: MR19=0x303, MR18=0xF0F6, DQSOSC=414, MR23=63, INC=38, DEC=25
3506 11:36:03.330442
3507 11:36:03.333445 ----->DramcWriteLeveling(PI) begin...
3508 11:36:03.333831 ==
3509 11:36:03.336852 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:36:03.343769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:36:03.344250 ==
3512 11:36:03.346893 Write leveling (Byte 0): 24 => 24
3513 11:36:03.347276 Write leveling (Byte 1): 30 => 30
3514 11:36:03.349647 DramcWriteLeveling(PI) end<-----
3515 11:36:03.350029
3516 11:36:03.352938 ==
3517 11:36:03.353318 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 11:36:03.359746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:36:03.360131 ==
3520 11:36:03.363341 [Gating] SW mode calibration
3521 11:36:03.369382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3522 11:36:03.373253 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3523 11:36:03.379783 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:36:03.383081 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:36:03.386338 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:36:03.392958 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:36:03.396736 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 11:36:03.399512 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3529 11:36:03.406184 0 15 24 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 0)
3530 11:36:03.409945 0 15 28 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
3531 11:36:03.413024 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:36:03.419325 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:36:03.422880 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:36:03.425846 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:36:03.432562 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 11:36:03.436182 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 11:36:03.439091 1 0 24 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
3538 11:36:03.445995 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3539 11:36:03.449116 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:36:03.452633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:36:03.458989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:36:03.463031 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:36:03.465791 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 11:36:03.469036 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 11:36:03.475868 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3546 11:36:03.479082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3547 11:36:03.482198 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:36:03.489274 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:36:03.492308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:36:03.495940 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:36:03.502279 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:36:03.505446 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:36:03.508866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:36:03.515712 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:36:03.519218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:36:03.522465 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:36:03.529300 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:36:03.532162 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:36:03.535904 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:36:03.542140 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3561 11:36:03.545763 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3562 11:36:03.549502 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 11:36:03.552164 Total UI for P1: 0, mck2ui 16
3564 11:36:03.555544 best dqsien dly found for B0: ( 1, 3, 22)
3565 11:36:03.559135 Total UI for P1: 0, mck2ui 16
3566 11:36:03.562206 best dqsien dly found for B1: ( 1, 3, 24)
3567 11:36:03.565502 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3568 11:36:03.568467 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3569 11:36:03.568892
3570 11:36:03.575289 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3571 11:36:03.578647 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3572 11:36:03.579188 [Gating] SW calibration Done
3573 11:36:03.581862 ==
3574 11:36:03.585172 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 11:36:03.588397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 11:36:03.588824 ==
3577 11:36:03.589154 RX Vref Scan: 0
3578 11:36:03.589478
3579 11:36:03.591644 RX Vref 0 -> 0, step: 1
3580 11:36:03.592025
3581 11:36:03.594970 RX Delay -40 -> 252, step: 8
3582 11:36:03.598344 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3583 11:36:03.602092 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3584 11:36:03.608352 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3585 11:36:03.611554 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3586 11:36:03.614655 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3587 11:36:03.618040 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3588 11:36:03.621504 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3589 11:36:03.628516 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3590 11:36:03.631366 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3591 11:36:03.634904 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3592 11:36:03.638226 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3593 11:36:03.641602 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3594 11:36:03.644834 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3595 11:36:03.651301 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3596 11:36:03.655148 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3597 11:36:03.658169 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3598 11:36:03.658634 ==
3599 11:36:03.661736 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:36:03.665497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:36:03.668283 ==
3602 11:36:03.668805 DQS Delay:
3603 11:36:03.669265 DQS0 = 0, DQS1 = 0
3604 11:36:03.671572 DQM Delay:
3605 11:36:03.672169 DQM0 = 110, DQM1 = 106
3606 11:36:03.675213 DQ Delay:
3607 11:36:03.678342 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3608 11:36:03.681254 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3609 11:36:03.684537 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3610 11:36:03.688472 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3611 11:36:03.688896
3612 11:36:03.689225
3613 11:36:03.689529 ==
3614 11:36:03.691957 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:36:03.694957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:36:03.695401 ==
3617 11:36:03.695730
3618 11:36:03.696028
3619 11:36:03.698455 TX Vref Scan disable
3620 11:36:03.701427 == TX Byte 0 ==
3621 11:36:03.705013 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3622 11:36:03.708596 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3623 11:36:03.711368 == TX Byte 1 ==
3624 11:36:03.715022 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3625 11:36:03.718468 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3626 11:36:03.718888 ==
3627 11:36:03.721126 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 11:36:03.724683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 11:36:03.728196 ==
3630 11:36:03.738745 TX Vref=22, minBit 0, minWin=25, winSum=429
3631 11:36:03.741774 TX Vref=24, minBit 0, minWin=26, winSum=429
3632 11:36:03.745223 TX Vref=26, minBit 1, minWin=26, winSum=434
3633 11:36:03.748388 TX Vref=28, minBit 0, minWin=27, winSum=439
3634 11:36:03.751164 TX Vref=30, minBit 0, minWin=27, winSum=436
3635 11:36:03.755235 TX Vref=32, minBit 9, minWin=25, winSum=431
3636 11:36:03.761294 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
3637 11:36:03.761448
3638 11:36:03.764773 Final TX Range 1 Vref 28
3639 11:36:03.764879
3640 11:36:03.764963 ==
3641 11:36:03.767994 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 11:36:03.771142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 11:36:03.771219 ==
3644 11:36:03.774507
3645 11:36:03.774581
3646 11:36:03.774640 TX Vref Scan disable
3647 11:36:03.778284 == TX Byte 0 ==
3648 11:36:03.781494 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3649 11:36:03.784960 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3650 11:36:03.787645 == TX Byte 1 ==
3651 11:36:03.791245 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3652 11:36:03.797606 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3653 11:36:03.797687
3654 11:36:03.797749 [DATLAT]
3655 11:36:03.797806 Freq=1200, CH1 RK1
3656 11:36:03.797862
3657 11:36:03.801364 DATLAT Default: 0xd
3658 11:36:03.801510 0, 0xFFFF, sum = 0
3659 11:36:03.804399 1, 0xFFFF, sum = 0
3660 11:36:03.808195 2, 0xFFFF, sum = 0
3661 11:36:03.808351 3, 0xFFFF, sum = 0
3662 11:36:03.810773 4, 0xFFFF, sum = 0
3663 11:36:03.810983 5, 0xFFFF, sum = 0
3664 11:36:03.814238 6, 0xFFFF, sum = 0
3665 11:36:03.814364 7, 0xFFFF, sum = 0
3666 11:36:03.817521 8, 0xFFFF, sum = 0
3667 11:36:03.817634 9, 0xFFFF, sum = 0
3668 11:36:03.820751 10, 0xFFFF, sum = 0
3669 11:36:03.820876 11, 0xFFFF, sum = 0
3670 11:36:03.824306 12, 0x0, sum = 1
3671 11:36:03.824433 13, 0x0, sum = 2
3672 11:36:03.828018 14, 0x0, sum = 3
3673 11:36:03.828159 15, 0x0, sum = 4
3674 11:36:03.830612 best_step = 13
3675 11:36:03.830769
3676 11:36:03.830891 ==
3677 11:36:03.834232 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 11:36:03.837188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 11:36:03.837392 ==
3680 11:36:03.837536 RX Vref Scan: 0
3681 11:36:03.841100
3682 11:36:03.841317 RX Vref 0 -> 0, step: 1
3683 11:36:03.841486
3684 11:36:03.844068 RX Delay -21 -> 252, step: 4
3685 11:36:03.850883 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3686 11:36:03.854156 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3687 11:36:03.857218 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3688 11:36:03.860715 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3689 11:36:03.863869 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3690 11:36:03.870907 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3691 11:36:03.874080 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3692 11:36:03.876802 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3693 11:36:03.880538 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3694 11:36:03.884154 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3695 11:36:03.889978 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3696 11:36:03.893526 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3697 11:36:03.896619 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3698 11:36:03.900139 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3699 11:36:03.903452 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3700 11:36:03.910209 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3701 11:36:03.910302 ==
3702 11:36:03.913329 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 11:36:03.916597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 11:36:03.916711 ==
3705 11:36:03.916798 DQS Delay:
3706 11:36:03.920229 DQS0 = 0, DQS1 = 0
3707 11:36:03.920340 DQM Delay:
3708 11:36:03.923250 DQM0 = 111, DQM1 = 108
3709 11:36:03.923373 DQ Delay:
3710 11:36:03.926539 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =110
3711 11:36:03.930131 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3712 11:36:03.933704 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3713 11:36:03.936810 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =116
3714 11:36:03.937009
3715 11:36:03.940281
3716 11:36:03.946874 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3717 11:36:03.949999 CH1 RK1: MR19=304, MR18=F707
3718 11:36:03.956347 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3719 11:36:03.959782 [RxdqsGatingPostProcess] freq 1200
3720 11:36:03.963263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3721 11:36:03.966366 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 11:36:03.969571 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 11:36:03.973135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 11:36:03.976262 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 11:36:03.979681 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 11:36:03.983216 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 11:36:03.986359 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 11:36:03.990246 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 11:36:03.993462 Pre-setting of DQS Precalculation
3730 11:36:03.996577 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3731 11:36:04.003272 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3732 11:36:04.013025 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3733 11:36:04.013413
3734 11:36:04.013707
3735 11:36:04.016536 [Calibration Summary] 2400 Mbps
3736 11:36:04.016921 CH 0, Rank 0
3737 11:36:04.019477 SW Impedance : PASS
3738 11:36:04.019875 DUTY Scan : NO K
3739 11:36:04.023091 ZQ Calibration : PASS
3740 11:36:04.026240 Jitter Meter : NO K
3741 11:36:04.026740 CBT Training : PASS
3742 11:36:04.030503 Write leveling : PASS
3743 11:36:04.032954 RX DQS gating : PASS
3744 11:36:04.033378 RX DQ/DQS(RDDQC) : PASS
3745 11:36:04.036329 TX DQ/DQS : PASS
3746 11:36:04.038899 RX DATLAT : PASS
3747 11:36:04.039326 RX DQ/DQS(Engine): PASS
3748 11:36:04.042401 TX OE : NO K
3749 11:36:04.042829 All Pass.
3750 11:36:04.043155
3751 11:36:04.045709 CH 0, Rank 1
3752 11:36:04.046173 SW Impedance : PASS
3753 11:36:04.049258 DUTY Scan : NO K
3754 11:36:04.052992 ZQ Calibration : PASS
3755 11:36:04.053496 Jitter Meter : NO K
3756 11:36:04.055742 CBT Training : PASS
3757 11:36:04.056166 Write leveling : PASS
3758 11:36:04.059039 RX DQS gating : PASS
3759 11:36:04.062634 RX DQ/DQS(RDDQC) : PASS
3760 11:36:04.063059 TX DQ/DQS : PASS
3761 11:36:04.065596 RX DATLAT : PASS
3762 11:36:04.068971 RX DQ/DQS(Engine): PASS
3763 11:36:04.069449 TX OE : NO K
3764 11:36:04.072340 All Pass.
3765 11:36:04.072761
3766 11:36:04.073089 CH 1, Rank 0
3767 11:36:04.075028 SW Impedance : PASS
3768 11:36:04.075472 DUTY Scan : NO K
3769 11:36:04.078506 ZQ Calibration : PASS
3770 11:36:04.082231 Jitter Meter : NO K
3771 11:36:04.082667 CBT Training : PASS
3772 11:36:04.085869 Write leveling : PASS
3773 11:36:04.088884 RX DQS gating : PASS
3774 11:36:04.089380 RX DQ/DQS(RDDQC) : PASS
3775 11:36:04.092153 TX DQ/DQS : PASS
3776 11:36:04.095345 RX DATLAT : PASS
3777 11:36:04.095941 RX DQ/DQS(Engine): PASS
3778 11:36:04.098384 TX OE : NO K
3779 11:36:04.098921 All Pass.
3780 11:36:04.099370
3781 11:36:04.102129 CH 1, Rank 1
3782 11:36:04.102568 SW Impedance : PASS
3783 11:36:04.105675 DUTY Scan : NO K
3784 11:36:04.108284 ZQ Calibration : PASS
3785 11:36:04.108708 Jitter Meter : NO K
3786 11:36:04.111789 CBT Training : PASS
3787 11:36:04.114784 Write leveling : PASS
3788 11:36:04.115253 RX DQS gating : PASS
3789 11:36:04.118056 RX DQ/DQS(RDDQC) : PASS
3790 11:36:04.121542 TX DQ/DQS : PASS
3791 11:36:04.122006 RX DATLAT : PASS
3792 11:36:04.124593 RX DQ/DQS(Engine): PASS
3793 11:36:04.128181 TX OE : NO K
3794 11:36:04.128609 All Pass.
3795 11:36:04.128939
3796 11:36:04.129240 DramC Write-DBI off
3797 11:36:04.131807 PER_BANK_REFRESH: Hybrid Mode
3798 11:36:04.135447 TX_TRACKING: ON
3799 11:36:04.141718 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3800 11:36:04.145427 [FAST_K] Save calibration result to emmc
3801 11:36:04.151802 dramc_set_vcore_voltage set vcore to 650000
3802 11:36:04.152300 Read voltage for 600, 5
3803 11:36:04.155047 Vio18 = 0
3804 11:36:04.155547 Vcore = 650000
3805 11:36:04.155879 Vdram = 0
3806 11:36:04.156182 Vddq = 0
3807 11:36:04.157861 Vmddr = 0
3808 11:36:04.161510 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3809 11:36:04.168250 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3810 11:36:04.170804 MEM_TYPE=3, freq_sel=19
3811 11:36:04.170879 sv_algorithm_assistance_LP4_1600
3812 11:36:04.177245 ============ PULL DRAM RESETB DOWN ============
3813 11:36:04.180624 ========== PULL DRAM RESETB DOWN end =========
3814 11:36:04.183930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3815 11:36:04.187256 ===================================
3816 11:36:04.190424 LPDDR4 DRAM CONFIGURATION
3817 11:36:04.193763 ===================================
3818 11:36:04.197127 EX_ROW_EN[0] = 0x0
3819 11:36:04.197202 EX_ROW_EN[1] = 0x0
3820 11:36:04.200602 LP4Y_EN = 0x0
3821 11:36:04.200677 WORK_FSP = 0x0
3822 11:36:04.204150 WL = 0x2
3823 11:36:04.204224 RL = 0x2
3824 11:36:04.207237 BL = 0x2
3825 11:36:04.207311 RPST = 0x0
3826 11:36:04.210887 RD_PRE = 0x0
3827 11:36:04.210961 WR_PRE = 0x1
3828 11:36:04.213783 WR_PST = 0x0
3829 11:36:04.217515 DBI_WR = 0x0
3830 11:36:04.217590 DBI_RD = 0x0
3831 11:36:04.220405 OTF = 0x1
3832 11:36:04.223774 ===================================
3833 11:36:04.227299 ===================================
3834 11:36:04.227379 ANA top config
3835 11:36:04.230976 ===================================
3836 11:36:04.234081 DLL_ASYNC_EN = 0
3837 11:36:04.237177 ALL_SLAVE_EN = 1
3838 11:36:04.237340 NEW_RANK_MODE = 1
3839 11:36:04.240397 DLL_IDLE_MODE = 1
3840 11:36:04.243962 LP45_APHY_COMB_EN = 1
3841 11:36:04.247094 TX_ODT_DIS = 1
3842 11:36:04.250216 NEW_8X_MODE = 1
3843 11:36:04.253516 ===================================
3844 11:36:04.257098 ===================================
3845 11:36:04.257300 data_rate = 1200
3846 11:36:04.259630 CKR = 1
3847 11:36:04.263371 DQ_P2S_RATIO = 8
3848 11:36:04.266351 ===================================
3849 11:36:04.269560 CA_P2S_RATIO = 8
3850 11:36:04.272962 DQ_CA_OPEN = 0
3851 11:36:04.276660 DQ_SEMI_OPEN = 0
3852 11:36:04.276932 CA_SEMI_OPEN = 0
3853 11:36:04.280113 CA_FULL_RATE = 0
3854 11:36:04.283957 DQ_CKDIV4_EN = 1
3855 11:36:04.287042 CA_CKDIV4_EN = 1
3856 11:36:04.289866 CA_PREDIV_EN = 0
3857 11:36:04.293316 PH8_DLY = 0
3858 11:36:04.293737 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3859 11:36:04.296654 DQ_AAMCK_DIV = 4
3860 11:36:04.300061 CA_AAMCK_DIV = 4
3861 11:36:04.303592 CA_ADMCK_DIV = 4
3862 11:36:04.306518 DQ_TRACK_CA_EN = 0
3863 11:36:04.309825 CA_PICK = 600
3864 11:36:04.313278 CA_MCKIO = 600
3865 11:36:04.313703 MCKIO_SEMI = 0
3866 11:36:04.316402 PLL_FREQ = 2288
3867 11:36:04.319767 DQ_UI_PI_RATIO = 32
3868 11:36:04.322914 CA_UI_PI_RATIO = 0
3869 11:36:04.326801 ===================================
3870 11:36:04.329543 ===================================
3871 11:36:04.333289 memory_type:LPDDR4
3872 11:36:04.333712 GP_NUM : 10
3873 11:36:04.336493 SRAM_EN : 1
3874 11:36:04.339659 MD32_EN : 0
3875 11:36:04.342674 ===================================
3876 11:36:04.343107 [ANA_INIT] >>>>>>>>>>>>>>
3877 11:36:04.345917 <<<<<< [CONFIGURE PHASE]: ANA_TX
3878 11:36:04.349701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3879 11:36:04.352913 ===================================
3880 11:36:04.356114 data_rate = 1200,PCW = 0X5800
3881 11:36:04.359384 ===================================
3882 11:36:04.362639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3883 11:36:04.369239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 11:36:04.372541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3885 11:36:04.379198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3886 11:36:04.382201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3887 11:36:04.385743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3888 11:36:04.386394 [ANA_INIT] flow start
3889 11:36:04.388915 [ANA_INIT] PLL >>>>>>>>
3890 11:36:04.392522 [ANA_INIT] PLL <<<<<<<<
3891 11:36:04.392946 [ANA_INIT] MIDPI >>>>>>>>
3892 11:36:04.395988 [ANA_INIT] MIDPI <<<<<<<<
3893 11:36:04.398827 [ANA_INIT] DLL >>>>>>>>
3894 11:36:04.399253 [ANA_INIT] flow end
3895 11:36:04.405568 ============ LP4 DIFF to SE enter ============
3896 11:36:04.409206 ============ LP4 DIFF to SE exit ============
3897 11:36:04.411989 [ANA_INIT] <<<<<<<<<<<<<
3898 11:36:04.416019 [Flow] Enable top DCM control >>>>>
3899 11:36:04.419170 [Flow] Enable top DCM control <<<<<
3900 11:36:04.422077 Enable DLL master slave shuffle
3901 11:36:04.425524 ==============================================================
3902 11:36:04.428928 Gating Mode config
3903 11:36:04.432165 ==============================================================
3904 11:36:04.435146 Config description:
3905 11:36:04.446020 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3906 11:36:04.452329 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3907 11:36:04.455513 SELPH_MODE 0: By rank 1: By Phase
3908 11:36:04.462331 ==============================================================
3909 11:36:04.465636 GAT_TRACK_EN = 1
3910 11:36:04.468740 RX_GATING_MODE = 2
3911 11:36:04.472183 RX_GATING_TRACK_MODE = 2
3912 11:36:04.475269 SELPH_MODE = 1
3913 11:36:04.478477 PICG_EARLY_EN = 1
3914 11:36:04.478862 VALID_LAT_VALUE = 1
3915 11:36:04.485434 ==============================================================
3916 11:36:04.488816 Enter into Gating configuration >>>>
3917 11:36:04.492101 Exit from Gating configuration <<<<
3918 11:36:04.495361 Enter into DVFS_PRE_config >>>>>
3919 11:36:04.505050 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3920 11:36:04.508812 Exit from DVFS_PRE_config <<<<<
3921 11:36:04.511567 Enter into PICG configuration >>>>
3922 11:36:04.515189 Exit from PICG configuration <<<<
3923 11:36:04.518597 [RX_INPUT] configuration >>>>>
3924 11:36:04.522216 [RX_INPUT] configuration <<<<<
3925 11:36:04.525076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3926 11:36:04.531668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3927 11:36:04.538544 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 11:36:04.545324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 11:36:04.551295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 11:36:04.557929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 11:36:04.561293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3932 11:36:04.565113 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3933 11:36:04.568266 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3934 11:36:04.574696 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3935 11:36:04.577733 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3936 11:36:04.581150 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 11:36:04.584642 ===================================
3938 11:36:04.587994 LPDDR4 DRAM CONFIGURATION
3939 11:36:04.591095 ===================================
3940 11:36:04.591481 EX_ROW_EN[0] = 0x0
3941 11:36:04.594512 EX_ROW_EN[1] = 0x0
3942 11:36:04.598192 LP4Y_EN = 0x0
3943 11:36:04.598698 WORK_FSP = 0x0
3944 11:36:04.601524 WL = 0x2
3945 11:36:04.601904 RL = 0x2
3946 11:36:04.604261 BL = 0x2
3947 11:36:04.604760 RPST = 0x0
3948 11:36:04.607637 RD_PRE = 0x0
3949 11:36:04.608075 WR_PRE = 0x1
3950 11:36:04.610907 WR_PST = 0x0
3951 11:36:04.611269 DBI_WR = 0x0
3952 11:36:04.614427 DBI_RD = 0x0
3953 11:36:04.615097 OTF = 0x1
3954 11:36:04.617487 ===================================
3955 11:36:04.620929 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3956 11:36:04.627536 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3957 11:36:04.630983 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3958 11:36:04.634045 ===================================
3959 11:36:04.637572 LPDDR4 DRAM CONFIGURATION
3960 11:36:04.641176 ===================================
3961 11:36:04.641560 EX_ROW_EN[0] = 0x10
3962 11:36:04.644115 EX_ROW_EN[1] = 0x0
3963 11:36:04.644511 LP4Y_EN = 0x0
3964 11:36:04.647407 WORK_FSP = 0x0
3965 11:36:04.651047 WL = 0x2
3966 11:36:04.651852 RL = 0x2
3967 11:36:04.654524 BL = 0x2
3968 11:36:04.655328 RPST = 0x0
3969 11:36:04.657490 RD_PRE = 0x0
3970 11:36:04.657872 WR_PRE = 0x1
3971 11:36:04.661002 WR_PST = 0x0
3972 11:36:04.661420 DBI_WR = 0x0
3973 11:36:04.664208 DBI_RD = 0x0
3974 11:36:04.664587 OTF = 0x1
3975 11:36:04.667598 ===================================
3976 11:36:04.673924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3977 11:36:04.678028 nWR fixed to 30
3978 11:36:04.681444 [ModeRegInit_LP4] CH0 RK0
3979 11:36:04.681827 [ModeRegInit_LP4] CH0 RK1
3980 11:36:04.684744 [ModeRegInit_LP4] CH1 RK0
3981 11:36:04.687942 [ModeRegInit_LP4] CH1 RK1
3982 11:36:04.688339 match AC timing 17
3983 11:36:04.694448 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3984 11:36:04.698340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3985 11:36:04.701372 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3986 11:36:04.708343 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3987 11:36:04.711246 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3988 11:36:04.711858 ==
3989 11:36:04.714686 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 11:36:04.718008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 11:36:04.718450 ==
3992 11:36:04.724215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 11:36:04.731176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3994 11:36:04.734612 [CA 0] Center 37 (7~67) winsize 61
3995 11:36:04.737459 [CA 1] Center 37 (7~67) winsize 61
3996 11:36:04.740868 [CA 2] Center 35 (5~65) winsize 61
3997 11:36:04.744656 [CA 3] Center 35 (5~65) winsize 61
3998 11:36:04.748157 [CA 4] Center 34 (4~65) winsize 62
3999 11:36:04.751042 [CA 5] Center 34 (3~65) winsize 63
4000 11:36:04.751391
4001 11:36:04.754823 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4002 11:36:04.755161
4003 11:36:04.757579 [CATrainingPosCal] consider 1 rank data
4004 11:36:04.761060 u2DelayCellTimex100 = 270/100 ps
4005 11:36:04.764416 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4006 11:36:04.767533 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4007 11:36:04.771285 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4008 11:36:04.774526 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4009 11:36:04.777512 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4010 11:36:04.784150 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4011 11:36:04.784529
4012 11:36:04.787654 CA PerBit enable=1, Macro0, CA PI delay=34
4013 11:36:04.788099
4014 11:36:04.790858 [CBTSetCACLKResult] CA Dly = 34
4015 11:36:04.791252 CS Dly: 6 (0~37)
4016 11:36:04.791666 ==
4017 11:36:04.794601 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 11:36:04.797204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:36:04.800926 ==
4020 11:36:04.804066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4021 11:36:04.810614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4022 11:36:04.813858 [CA 0] Center 37 (7~67) winsize 61
4023 11:36:04.817560 [CA 1] Center 36 (6~67) winsize 62
4024 11:36:04.820261 [CA 2] Center 35 (5~65) winsize 61
4025 11:36:04.823968 [CA 3] Center 35 (5~65) winsize 61
4026 11:36:04.826951 [CA 4] Center 34 (4~65) winsize 62
4027 11:36:04.830772 [CA 5] Center 34 (3~65) winsize 63
4028 11:36:04.831159
4029 11:36:04.834154 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4030 11:36:04.834543
4031 11:36:04.837492 [CATrainingPosCal] consider 2 rank data
4032 11:36:04.840526 u2DelayCellTimex100 = 270/100 ps
4033 11:36:04.843656 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4034 11:36:04.847067 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4035 11:36:04.850297 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4036 11:36:04.857349 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4037 11:36:04.860502 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4038 11:36:04.864087 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4039 11:36:04.864515
4040 11:36:04.867121 CA PerBit enable=1, Macro0, CA PI delay=34
4041 11:36:04.867721
4042 11:36:04.870664 [CBTSetCACLKResult] CA Dly = 34
4043 11:36:04.871089 CS Dly: 6 (0~38)
4044 11:36:04.871418
4045 11:36:04.874256 ----->DramcWriteLeveling(PI) begin...
4046 11:36:04.874691 ==
4047 11:36:04.877270 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:36:04.884480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:36:04.884992 ==
4050 11:36:04.887069 Write leveling (Byte 0): 32 => 32
4051 11:36:04.890802 Write leveling (Byte 1): 32 => 32
4052 11:36:04.891315 DramcWriteLeveling(PI) end<-----
4053 11:36:04.891648
4054 11:36:04.894058 ==
4055 11:36:04.897231 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 11:36:04.900491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 11:36:04.900926 ==
4058 11:36:04.903846 [Gating] SW mode calibration
4059 11:36:04.910618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4060 11:36:04.913453 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4061 11:36:04.920290 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 11:36:04.923578 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 11:36:04.927064 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 11:36:04.934240 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4065 11:36:04.936634 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (1 1)
4066 11:36:04.940525 0 9 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
4067 11:36:04.946523 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:36:04.950177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:36:04.952987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:36:04.960072 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 11:36:04.962829 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 11:36:04.966809 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4073 11:36:04.973117 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4074 11:36:04.976085 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4075 11:36:04.979530 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:36:04.986663 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:36:04.989927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:36:04.993197 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:36:04.999399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4080 11:36:05.002997 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 11:36:05.006365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4082 11:36:05.012415 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:36:05.016101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:36:05.019598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:36:05.025704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:36:05.029333 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:36:05.032543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:36:05.039403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:36:05.042439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:36:05.046075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:36:05.052792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:36:05.056109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:36:05.059292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:36:05.065748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:36:05.069131 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:36:05.072605 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4097 11:36:05.079768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4098 11:36:05.080205 Total UI for P1: 0, mck2ui 16
4099 11:36:05.082198 best dqsien dly found for B0: ( 0, 13, 12)
4100 11:36:05.089069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 11:36:05.092221 Total UI for P1: 0, mck2ui 16
4102 11:36:05.095688 best dqsien dly found for B1: ( 0, 13, 16)
4103 11:36:05.099476 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4104 11:36:05.102214 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4105 11:36:05.102670
4106 11:36:05.105681 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4107 11:36:05.109239 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4108 11:36:05.112430 [Gating] SW calibration Done
4109 11:36:05.112859 ==
4110 11:36:05.115468 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 11:36:05.118801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 11:36:05.119415 ==
4113 11:36:05.121847 RX Vref Scan: 0
4114 11:36:05.122346
4115 11:36:05.125484 RX Vref 0 -> 0, step: 1
4116 11:36:05.125951
4117 11:36:05.126365 RX Delay -230 -> 252, step: 16
4118 11:36:05.132131 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4119 11:36:05.135499 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4120 11:36:05.139251 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4121 11:36:05.142262 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4122 11:36:05.149383 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4123 11:36:05.152408 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4124 11:36:05.155517 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4125 11:36:05.158821 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4126 11:36:05.162211 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4127 11:36:05.169138 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4128 11:36:05.173090 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4129 11:36:05.175375 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4130 11:36:05.178734 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4131 11:36:05.185722 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4132 11:36:05.188872 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4133 11:36:05.192296 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4134 11:36:05.192814 ==
4135 11:36:05.195799 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:36:05.198699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:36:05.202396 ==
4138 11:36:05.202904 DQS Delay:
4139 11:36:05.203370 DQS0 = 0, DQS1 = 0
4140 11:36:05.206200 DQM Delay:
4141 11:36:05.206740 DQM0 = 39, DQM1 = 31
4142 11:36:05.209490 DQ Delay:
4143 11:36:05.209936 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =41
4144 11:36:05.211893 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4145 11:36:05.215556 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4146 11:36:05.218994 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4147 11:36:05.221707
4148 11:36:05.222167
4149 11:36:05.222653 ==
4150 11:36:05.225254 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 11:36:05.228675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:36:05.229224 ==
4153 11:36:05.229659
4154 11:36:05.230077
4155 11:36:05.232120 TX Vref Scan disable
4156 11:36:05.232600 == TX Byte 0 ==
4157 11:36:05.238328 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4158 11:36:05.241677 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4159 11:36:05.242156 == TX Byte 1 ==
4160 11:36:05.248385 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4161 11:36:05.251458 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4162 11:36:05.251844 ==
4163 11:36:05.254756 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 11:36:05.258136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:36:05.258616 ==
4166 11:36:05.258946
4167 11:36:05.259312
4168 11:36:05.261468 TX Vref Scan disable
4169 11:36:05.264659 == TX Byte 0 ==
4170 11:36:05.268412 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4171 11:36:05.274864 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4172 11:36:05.275260 == TX Byte 1 ==
4173 11:36:05.278005 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4174 11:36:05.284494 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4175 11:36:05.284882
4176 11:36:05.285182 [DATLAT]
4177 11:36:05.285494 Freq=600, CH0 RK0
4178 11:36:05.285766
4179 11:36:05.287519 DATLAT Default: 0x9
4180 11:36:05.287919 0, 0xFFFF, sum = 0
4181 11:36:05.290857 1, 0xFFFF, sum = 0
4182 11:36:05.294132 2, 0xFFFF, sum = 0
4183 11:36:05.294601 3, 0xFFFF, sum = 0
4184 11:36:05.297483 4, 0xFFFF, sum = 0
4185 11:36:05.297890 5, 0xFFFF, sum = 0
4186 11:36:05.300857 6, 0xFFFF, sum = 0
4187 11:36:05.301382 7, 0xFFFF, sum = 0
4188 11:36:05.304262 8, 0x0, sum = 1
4189 11:36:05.304651 9, 0x0, sum = 2
4190 11:36:05.304954 10, 0x0, sum = 3
4191 11:36:05.307927 11, 0x0, sum = 4
4192 11:36:05.308317 best_step = 9
4193 11:36:05.308618
4194 11:36:05.308891 ==
4195 11:36:05.311535 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:36:05.318142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:36:05.318630 ==
4198 11:36:05.318935 RX Vref Scan: 1
4199 11:36:05.319307
4200 11:36:05.321248 RX Vref 0 -> 0, step: 1
4201 11:36:05.321696
4202 11:36:05.324351 RX Delay -195 -> 252, step: 8
4203 11:36:05.324820
4204 11:36:05.327631 Set Vref, RX VrefLevel [Byte0]: 61
4205 11:36:05.330766 [Byte1]: 52
4206 11:36:05.331239
4207 11:36:05.334523 Final RX Vref Byte 0 = 61 to rank0
4208 11:36:05.337741 Final RX Vref Byte 1 = 52 to rank0
4209 11:36:05.341531 Final RX Vref Byte 0 = 61 to rank1
4210 11:36:05.344249 Final RX Vref Byte 1 = 52 to rank1==
4211 11:36:05.347642 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 11:36:05.350881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:36:05.351391 ==
4214 11:36:05.354386 DQS Delay:
4215 11:36:05.354854 DQS0 = 0, DQS1 = 0
4216 11:36:05.357897 DQM Delay:
4217 11:36:05.358429 DQM0 = 33, DQM1 = 29
4218 11:36:05.358737 DQ Delay:
4219 11:36:05.360809 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4220 11:36:05.364354 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4221 11:36:05.367511 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4222 11:36:05.370743 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4223 11:36:05.371131
4224 11:36:05.371443
4225 11:36:05.380804 [DQSOSCAuto] RK0, (LSB)MR18= 0x4645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4226 11:36:05.384109 CH0 RK0: MR19=808, MR18=4645
4227 11:36:05.391055 CH0_RK0: MR19=0x808, MR18=0x4645, DQSOSC=396, MR23=63, INC=167, DEC=111
4228 11:36:05.391563
4229 11:36:05.394348 ----->DramcWriteLeveling(PI) begin...
4230 11:36:05.394861 ==
4231 11:36:05.397307 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:36:05.400936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:36:05.401446 ==
4234 11:36:05.403817 Write leveling (Byte 0): 33 => 33
4235 11:36:05.407424 Write leveling (Byte 1): 30 => 30
4236 11:36:05.410720 DramcWriteLeveling(PI) end<-----
4237 11:36:05.411227
4238 11:36:05.411567 ==
4239 11:36:05.413792 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 11:36:05.416748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:36:05.417179 ==
4242 11:36:05.420088 [Gating] SW mode calibration
4243 11:36:05.427362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4244 11:36:05.433618 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4245 11:36:05.437073 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 11:36:05.440217 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 11:36:05.446615 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4248 11:36:05.450495 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 1)
4249 11:36:05.453635 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (0 0)
4250 11:36:05.460001 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:36:05.463412 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:36:05.466824 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:36:05.473131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 11:36:05.476914 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 11:36:05.479846 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4256 11:36:05.486525 0 10 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
4257 11:36:05.489660 0 10 16 | B1->B0 | 3332 4646 | 1 0 | (0 0) (0 0)
4258 11:36:05.492907 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:36:05.499681 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:36:05.503459 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:36:05.506281 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:36:05.513340 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 11:36:05.516005 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 11:36:05.519656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4265 11:36:05.526627 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4266 11:36:05.529531 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:36:05.533169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:36:05.539697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:36:05.542796 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:36:05.545968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:36:05.553061 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:36:05.555928 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:36:05.559541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:36:05.565843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:36:05.568606 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:36:05.572079 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:36:05.578921 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:36:05.582031 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:36:05.585400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:36:05.589393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:36:05.595708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4282 11:36:05.598966 Total UI for P1: 0, mck2ui 16
4283 11:36:05.602249 best dqsien dly found for B0: ( 0, 13, 14)
4284 11:36:05.605636 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 11:36:05.609233 Total UI for P1: 0, mck2ui 16
4286 11:36:05.612617 best dqsien dly found for B1: ( 0, 13, 16)
4287 11:36:05.615825 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4288 11:36:05.618874 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4289 11:36:05.619060
4290 11:36:05.622242 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4291 11:36:05.629050 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4292 11:36:05.629325 [Gating] SW calibration Done
4293 11:36:05.629538 ==
4294 11:36:05.632204 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 11:36:05.639133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 11:36:05.639624 ==
4297 11:36:05.639933 RX Vref Scan: 0
4298 11:36:05.640211
4299 11:36:05.642186 RX Vref 0 -> 0, step: 1
4300 11:36:05.642573
4301 11:36:05.645840 RX Delay -230 -> 252, step: 16
4302 11:36:05.648788 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4303 11:36:05.651946 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4304 11:36:05.658876 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4305 11:36:05.662164 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4306 11:36:05.666245 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4307 11:36:05.669026 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4308 11:36:05.672367 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4309 11:36:05.678699 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4310 11:36:05.682242 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4311 11:36:05.685740 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4312 11:36:05.688448 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4313 11:36:05.695285 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4314 11:36:05.698569 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4315 11:36:05.702090 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4316 11:36:05.705148 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4317 11:36:05.708699 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4318 11:36:05.712351 ==
4319 11:36:05.715483 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:36:05.718727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:36:05.719116 ==
4322 11:36:05.719418 DQS Delay:
4323 11:36:05.721667 DQS0 = 0, DQS1 = 0
4324 11:36:05.722050 DQM Delay:
4325 11:36:05.725171 DQM0 = 35, DQM1 = 29
4326 11:36:05.725594 DQ Delay:
4327 11:36:05.728781 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =25
4328 11:36:05.731599 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4329 11:36:05.735505 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4330 11:36:05.738554 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4331 11:36:05.738938
4332 11:36:05.739236
4333 11:36:05.739514 ==
4334 11:36:05.741892 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 11:36:05.745243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:36:05.745631 ==
4337 11:36:05.745994
4338 11:36:05.746337
4339 11:36:05.748722 TX Vref Scan disable
4340 11:36:05.751860 == TX Byte 0 ==
4341 11:36:05.755092 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4342 11:36:05.758196 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4343 11:36:05.761803 == TX Byte 1 ==
4344 11:36:05.764922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4345 11:36:05.768365 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4346 11:36:05.768778 ==
4347 11:36:05.771770 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 11:36:05.778021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 11:36:05.778456 ==
4350 11:36:05.778762
4351 11:36:05.779039
4352 11:36:05.779304 TX Vref Scan disable
4353 11:36:05.782566 == TX Byte 0 ==
4354 11:36:05.785693 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4355 11:36:05.792554 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4356 11:36:05.792942 == TX Byte 1 ==
4357 11:36:05.796211 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4358 11:36:05.802568 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4359 11:36:05.802955
4360 11:36:05.803255 [DATLAT]
4361 11:36:05.803550 Freq=600, CH0 RK1
4362 11:36:05.803895
4363 11:36:05.805851 DATLAT Default: 0x9
4364 11:36:05.806294 0, 0xFFFF, sum = 0
4365 11:36:05.809262 1, 0xFFFF, sum = 0
4366 11:36:05.809654 2, 0xFFFF, sum = 0
4367 11:36:05.812952 3, 0xFFFF, sum = 0
4368 11:36:05.816259 4, 0xFFFF, sum = 0
4369 11:36:05.816651 5, 0xFFFF, sum = 0
4370 11:36:05.819667 6, 0xFFFF, sum = 0
4371 11:36:05.820057 7, 0xFFFF, sum = 0
4372 11:36:05.822240 8, 0x0, sum = 1
4373 11:36:05.822671 9, 0x0, sum = 2
4374 11:36:05.822989 10, 0x0, sum = 3
4375 11:36:05.825840 11, 0x0, sum = 4
4376 11:36:05.826271 best_step = 9
4377 11:36:05.826574
4378 11:36:05.826849 ==
4379 11:36:05.829220 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 11:36:05.835516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 11:36:05.835902 ==
4382 11:36:05.836200 RX Vref Scan: 0
4383 11:36:05.836477
4384 11:36:05.838933 RX Vref 0 -> 0, step: 1
4385 11:36:05.839314
4386 11:36:05.842458 RX Delay -195 -> 252, step: 8
4387 11:36:05.845595 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4388 11:36:05.852507 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4389 11:36:05.855949 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4390 11:36:05.858832 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4391 11:36:05.862333 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4392 11:36:05.868732 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4393 11:36:05.872154 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4394 11:36:05.875694 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4395 11:36:05.879038 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4396 11:36:05.882713 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4397 11:36:05.889069 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4398 11:36:05.892218 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4399 11:36:05.895406 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4400 11:36:05.898995 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4401 11:36:05.905853 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4402 11:36:05.909168 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4403 11:36:05.909674 ==
4404 11:36:05.911996 Dram Type= 6, Freq= 0, CH_0, rank 1
4405 11:36:05.915569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 11:36:05.916162 ==
4407 11:36:05.919022 DQS Delay:
4408 11:36:05.919628 DQS0 = 0, DQS1 = 0
4409 11:36:05.921906 DQM Delay:
4410 11:36:05.922463 DQM0 = 33, DQM1 = 27
4411 11:36:05.922981 DQ Delay:
4412 11:36:05.925334 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4413 11:36:05.928089 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4414 11:36:05.931906 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4415 11:36:05.935158 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4416 11:36:05.935579
4417 11:36:05.935900
4418 11:36:05.944770 [DQSOSCAuto] RK1, (LSB)MR18= 0x7342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4419 11:36:05.947816 CH0 RK1: MR19=808, MR18=7342
4420 11:36:05.954509 CH0_RK1: MR19=0x808, MR18=0x7342, DQSOSC=388, MR23=63, INC=174, DEC=116
4421 11:36:05.954891 [RxdqsGatingPostProcess] freq 600
4422 11:36:05.961382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4423 11:36:05.964538 Pre-setting of DQS Precalculation
4424 11:36:05.968108 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4425 11:36:05.971390 ==
4426 11:36:05.974421 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 11:36:05.977511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 11:36:05.977893 ==
4429 11:36:05.984208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4430 11:36:05.987387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4431 11:36:05.991820 [CA 0] Center 35 (5~66) winsize 62
4432 11:36:05.994874 [CA 1] Center 35 (5~66) winsize 62
4433 11:36:05.998339 [CA 2] Center 34 (4~65) winsize 62
4434 11:36:06.001803 [CA 3] Center 34 (3~65) winsize 63
4435 11:36:06.005036 [CA 4] Center 34 (4~65) winsize 62
4436 11:36:06.008290 [CA 5] Center 33 (3~64) winsize 62
4437 11:36:06.008666
4438 11:36:06.011585 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4439 11:36:06.011967
4440 11:36:06.014554 [CATrainingPosCal] consider 1 rank data
4441 11:36:06.017953 u2DelayCellTimex100 = 270/100 ps
4442 11:36:06.021571 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 11:36:06.027919 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 11:36:06.031358 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 11:36:06.034876 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4446 11:36:06.038445 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 11:36:06.041498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 11:36:06.041877
4449 11:36:06.044660 CA PerBit enable=1, Macro0, CA PI delay=33
4450 11:36:06.045043
4451 11:36:06.048364 [CBTSetCACLKResult] CA Dly = 33
4452 11:36:06.048863 CS Dly: 5 (0~36)
4453 11:36:06.051582 ==
4454 11:36:06.054554 Dram Type= 6, Freq= 0, CH_1, rank 1
4455 11:36:06.057827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 11:36:06.058401 ==
4457 11:36:06.062075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4458 11:36:06.067997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4459 11:36:06.072115 [CA 0] Center 36 (6~66) winsize 61
4460 11:36:06.075163 [CA 1] Center 35 (5~66) winsize 62
4461 11:36:06.078656 [CA 2] Center 34 (4~65) winsize 62
4462 11:36:06.081594 [CA 3] Center 34 (3~65) winsize 63
4463 11:36:06.085035 [CA 4] Center 34 (4~65) winsize 62
4464 11:36:06.088493 [CA 5] Center 33 (3~64) winsize 62
4465 11:36:06.088986
4466 11:36:06.091607 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4467 11:36:06.092119
4468 11:36:06.095217 [CATrainingPosCal] consider 2 rank data
4469 11:36:06.098266 u2DelayCellTimex100 = 270/100 ps
4470 11:36:06.101162 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4471 11:36:06.108570 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4472 11:36:06.111167 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4473 11:36:06.114731 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4474 11:36:06.118206 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 11:36:06.121451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 11:36:06.122001
4477 11:36:06.124494 CA PerBit enable=1, Macro0, CA PI delay=33
4478 11:36:06.124921
4479 11:36:06.127725 [CBTSetCACLKResult] CA Dly = 33
4480 11:36:06.131404 CS Dly: 5 (0~36)
4481 11:36:06.131902
4482 11:36:06.134381 ----->DramcWriteLeveling(PI) begin...
4483 11:36:06.134816 ==
4484 11:36:06.137771 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 11:36:06.141537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 11:36:06.142038 ==
4487 11:36:06.145035 Write leveling (Byte 0): 31 => 31
4488 11:36:06.147894 Write leveling (Byte 1): 31 => 31
4489 11:36:06.151080 DramcWriteLeveling(PI) end<-----
4490 11:36:06.151583
4491 11:36:06.151917 ==
4492 11:36:06.154540 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 11:36:06.157897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 11:36:06.158438 ==
4495 11:36:06.161221 [Gating] SW mode calibration
4496 11:36:06.168066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4497 11:36:06.174484 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4498 11:36:06.177810 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 11:36:06.181334 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4500 11:36:06.187590 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 11:36:06.191073 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
4502 11:36:06.194151 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4503 11:36:06.201101 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:36:06.204428 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:36:06.207715 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:36:06.214542 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 11:36:06.217590 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 11:36:06.221072 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 11:36:06.227352 0 10 12 | B1->B0 | 2c2c 2d2d | 0 1 | (0 0) (0 0)
4510 11:36:06.230632 0 10 16 | B1->B0 | 4242 4545 | 0 0 | (1 1) (0 0)
4511 11:36:06.234169 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:36:06.240570 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:36:06.244068 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:36:06.247027 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 11:36:06.254062 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 11:36:06.257074 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 11:36:06.260484 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4518 11:36:06.267476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4519 11:36:06.270685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:36:06.273281 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:36:06.280403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:36:06.283670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:36:06.286803 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:36:06.293370 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:36:06.296462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:36:06.300589 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:36:06.306589 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:36:06.309562 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:36:06.312877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:36:06.319851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:36:06.323190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 11:36:06.326624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 11:36:06.333066 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4534 11:36:06.336519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4535 11:36:06.340051 Total UI for P1: 0, mck2ui 16
4536 11:36:06.343624 best dqsien dly found for B0: ( 0, 13, 12)
4537 11:36:06.346473 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 11:36:06.349865 Total UI for P1: 0, mck2ui 16
4539 11:36:06.353312 best dqsien dly found for B1: ( 0, 13, 16)
4540 11:36:06.356077 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4541 11:36:06.359665 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4542 11:36:06.360104
4543 11:36:06.363031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4544 11:36:06.369478 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4545 11:36:06.369908 [Gating] SW calibration Done
4546 11:36:06.370296 ==
4547 11:36:06.372710 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 11:36:06.379280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 11:36:06.379710 ==
4550 11:36:06.380042 RX Vref Scan: 0
4551 11:36:06.380349
4552 11:36:06.382659 RX Vref 0 -> 0, step: 1
4553 11:36:06.383086
4554 11:36:06.385912 RX Delay -230 -> 252, step: 16
4555 11:36:06.389489 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4556 11:36:06.392566 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4557 11:36:06.399103 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4558 11:36:06.402864 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4559 11:36:06.405898 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4560 11:36:06.409347 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4561 11:36:06.412720 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4562 11:36:06.418946 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4563 11:36:06.422203 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4564 11:36:06.426005 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4565 11:36:06.429117 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4566 11:36:06.435464 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4567 11:36:06.438760 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4568 11:36:06.442003 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4569 11:36:06.445825 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4570 11:36:06.452165 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4571 11:36:06.452590 ==
4572 11:36:06.455404 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 11:36:06.458531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 11:36:06.458980 ==
4575 11:36:06.459313 DQS Delay:
4576 11:36:06.462069 DQS0 = 0, DQS1 = 0
4577 11:36:06.462523 DQM Delay:
4578 11:36:06.465116 DQM0 = 40, DQM1 = 29
4579 11:36:06.465553 DQ Delay:
4580 11:36:06.468793 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4581 11:36:06.471908 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4582 11:36:06.475573 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4583 11:36:06.479052 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4584 11:36:06.479504
4585 11:36:06.479836
4586 11:36:06.480140 ==
4587 11:36:06.481647 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:36:06.485026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:36:06.488594 ==
4590 11:36:06.488978
4591 11:36:06.489273
4592 11:36:06.489547 TX Vref Scan disable
4593 11:36:06.491997 == TX Byte 0 ==
4594 11:36:06.495162 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4595 11:36:06.498176 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4596 11:36:06.501686 == TX Byte 1 ==
4597 11:36:06.505248 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4598 11:36:06.508483 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4599 11:36:06.511975 ==
4600 11:36:06.512357 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:36:06.518369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:36:06.518757 ==
4603 11:36:06.519054
4604 11:36:06.519325
4605 11:36:06.521383 TX Vref Scan disable
4606 11:36:06.521780 == TX Byte 0 ==
4607 11:36:06.527899 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4608 11:36:06.531520 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4609 11:36:06.531905 == TX Byte 1 ==
4610 11:36:06.538072 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4611 11:36:06.541534 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4612 11:36:06.542002
4613 11:36:06.542340 [DATLAT]
4614 11:36:06.544757 Freq=600, CH1 RK0
4615 11:36:06.545177
4616 11:36:06.545477 DATLAT Default: 0x9
4617 11:36:06.548133 0, 0xFFFF, sum = 0
4618 11:36:06.548525 1, 0xFFFF, sum = 0
4619 11:36:06.551660 2, 0xFFFF, sum = 0
4620 11:36:06.554815 3, 0xFFFF, sum = 0
4621 11:36:06.555373 4, 0xFFFF, sum = 0
4622 11:36:06.558033 5, 0xFFFF, sum = 0
4623 11:36:06.558601 6, 0xFFFF, sum = 0
4624 11:36:06.562002 7, 0xFFFF, sum = 0
4625 11:36:06.562561 8, 0x0, sum = 1
4626 11:36:06.562902 9, 0x0, sum = 2
4627 11:36:06.564577 10, 0x0, sum = 3
4628 11:36:06.565089 11, 0x0, sum = 4
4629 11:36:06.567644 best_step = 9
4630 11:36:06.568069
4631 11:36:06.568399 ==
4632 11:36:06.570770 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 11:36:06.574439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 11:36:06.574872 ==
4635 11:36:06.577643 RX Vref Scan: 1
4636 11:36:06.578065
4637 11:36:06.578504 RX Vref 0 -> 0, step: 1
4638 11:36:06.580770
4639 11:36:06.581382 RX Delay -195 -> 252, step: 8
4640 11:36:06.581733
4641 11:36:06.584026 Set Vref, RX VrefLevel [Byte0]: 58
4642 11:36:06.587660 [Byte1]: 50
4643 11:36:06.592134
4644 11:36:06.592638 Final RX Vref Byte 0 = 58 to rank0
4645 11:36:06.595639 Final RX Vref Byte 1 = 50 to rank0
4646 11:36:06.598573 Final RX Vref Byte 0 = 58 to rank1
4647 11:36:06.602325 Final RX Vref Byte 1 = 50 to rank1==
4648 11:36:06.605894 Dram Type= 6, Freq= 0, CH_1, rank 0
4649 11:36:06.611631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:36:06.612063 ==
4651 11:36:06.612396 DQS Delay:
4652 11:36:06.612700 DQS0 = 0, DQS1 = 0
4653 11:36:06.614850 DQM Delay:
4654 11:36:06.615275 DQM0 = 39, DQM1 = 28
4655 11:36:06.618409 DQ Delay:
4656 11:36:06.621674 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4657 11:36:06.624824 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4658 11:36:06.628209 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4659 11:36:06.631960 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4660 11:36:06.632642
4661 11:36:06.633052
4662 11:36:06.638365 [DQSOSCAuto] RK0, (LSB)MR18= 0x2430, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4663 11:36:06.642044 CH1 RK0: MR19=808, MR18=2430
4664 11:36:06.648455 CH1_RK0: MR19=0x808, MR18=0x2430, DQSOSC=400, MR23=63, INC=163, DEC=109
4665 11:36:06.648961
4666 11:36:06.651639 ----->DramcWriteLeveling(PI) begin...
4667 11:36:06.652154 ==
4668 11:36:06.655027 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 11:36:06.658531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 11:36:06.659041 ==
4671 11:36:06.661645 Write leveling (Byte 0): 28 => 28
4672 11:36:06.664889 Write leveling (Byte 1): 31 => 31
4673 11:36:06.667800 DramcWriteLeveling(PI) end<-----
4674 11:36:06.668226
4675 11:36:06.668555 ==
4676 11:36:06.671126 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 11:36:06.674397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 11:36:06.674827 ==
4679 11:36:06.678159 [Gating] SW mode calibration
4680 11:36:06.685031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4681 11:36:06.691165 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4682 11:36:06.695010 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4683 11:36:06.702009 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 11:36:06.705279 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 11:36:06.708364 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
4686 11:36:06.714587 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4687 11:36:06.717877 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 11:36:06.721033 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:36:06.728192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 11:36:06.731003 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 11:36:06.734452 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 11:36:06.740806 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4693 11:36:06.744180 0 10 12 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4694 11:36:06.747810 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:36:06.754581 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:36:06.758036 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:36:06.761177 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:36:06.764416 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 11:36:06.770892 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 11:36:06.774299 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 11:36:06.777641 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:36:06.783861 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4703 11:36:06.787889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:36:06.791233 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:36:06.797186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:36:06.800580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:36:06.803970 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:36:06.810319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:36:06.813705 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:36:06.816973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:36:06.824119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:36:06.827232 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:36:06.830277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:36:06.837153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:36:06.840927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 11:36:06.843482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4717 11:36:06.850516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4718 11:36:06.853455 Total UI for P1: 0, mck2ui 16
4719 11:36:06.856743 best dqsien dly found for B0: ( 0, 13, 8)
4720 11:36:06.860360 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 11:36:06.863601 Total UI for P1: 0, mck2ui 16
4722 11:36:06.866545 best dqsien dly found for B1: ( 0, 13, 10)
4723 11:36:06.869662 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4724 11:36:06.873209 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4725 11:36:06.873605
4726 11:36:06.876813 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4727 11:36:06.880164 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4728 11:36:06.883473 [Gating] SW calibration Done
4729 11:36:06.883859 ==
4730 11:36:06.886459 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 11:36:06.890080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 11:36:06.893402 ==
4733 11:36:06.893789 RX Vref Scan: 0
4734 11:36:06.894088
4735 11:36:06.896597 RX Vref 0 -> 0, step: 1
4736 11:36:06.896981
4737 11:36:06.899927 RX Delay -230 -> 252, step: 16
4738 11:36:06.903324 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4739 11:36:06.906445 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4740 11:36:06.909710 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4741 11:36:06.916126 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4742 11:36:06.919525 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4743 11:36:06.923180 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4744 11:36:06.926468 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4745 11:36:06.929450 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4746 11:36:06.936614 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4747 11:36:06.939753 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4748 11:36:06.942546 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4749 11:36:06.946376 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4750 11:36:06.952460 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4751 11:36:06.956042 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4752 11:36:06.959251 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4753 11:36:06.962431 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4754 11:36:06.965930 ==
4755 11:36:06.968954 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 11:36:06.972572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 11:36:06.972960 ==
4758 11:36:06.973258 DQS Delay:
4759 11:36:06.975699 DQS0 = 0, DQS1 = 0
4760 11:36:06.976084 DQM Delay:
4761 11:36:06.979201 DQM0 = 41, DQM1 = 34
4762 11:36:06.979659 DQ Delay:
4763 11:36:06.982220 DQ0 =49, DQ1 =41, DQ2 =17, DQ3 =41
4764 11:36:06.985904 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4765 11:36:06.989304 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4766 11:36:06.992404 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4767 11:36:06.992791
4768 11:36:06.993087
4769 11:36:06.993360 ==
4770 11:36:06.995493 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 11:36:06.999384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 11:36:06.999774 ==
4773 11:36:07.000074
4774 11:36:07.000348
4775 11:36:07.002048 TX Vref Scan disable
4776 11:36:07.005892 == TX Byte 0 ==
4777 11:36:07.009125 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 11:36:07.012219 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 11:36:07.015629 == TX Byte 1 ==
4780 11:36:07.018767 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 11:36:07.022186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 11:36:07.022631 ==
4783 11:36:07.025583 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:36:07.032312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:36:07.032769 ==
4786 11:36:07.033067
4787 11:36:07.033343
4788 11:36:07.033605 TX Vref Scan disable
4789 11:36:07.036464 == TX Byte 0 ==
4790 11:36:07.039813 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4791 11:36:07.046532 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4792 11:36:07.046922 == TX Byte 1 ==
4793 11:36:07.049400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4794 11:36:07.056053 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4795 11:36:07.056445
4796 11:36:07.056742 [DATLAT]
4797 11:36:07.057022 Freq=600, CH1 RK1
4798 11:36:07.057292
4799 11:36:07.060005 DATLAT Default: 0x9
4800 11:36:07.060463 0, 0xFFFF, sum = 0
4801 11:36:07.062839 1, 0xFFFF, sum = 0
4802 11:36:07.063230 2, 0xFFFF, sum = 0
4803 11:36:07.066271 3, 0xFFFF, sum = 0
4804 11:36:07.069669 4, 0xFFFF, sum = 0
4805 11:36:07.070062 5, 0xFFFF, sum = 0
4806 11:36:07.073089 6, 0xFFFF, sum = 0
4807 11:36:07.073478 7, 0xFFFF, sum = 0
4808 11:36:07.076141 8, 0x0, sum = 1
4809 11:36:07.076537 9, 0x0, sum = 2
4810 11:36:07.076846 10, 0x0, sum = 3
4811 11:36:07.079885 11, 0x0, sum = 4
4812 11:36:07.080369 best_step = 9
4813 11:36:07.080681
4814 11:36:07.080992 ==
4815 11:36:07.082654 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 11:36:07.089885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 11:36:07.090321 ==
4818 11:36:07.090625 RX Vref Scan: 0
4819 11:36:07.090905
4820 11:36:07.093050 RX Vref 0 -> 0, step: 1
4821 11:36:07.093434
4822 11:36:07.096016 RX Delay -195 -> 252, step: 8
4823 11:36:07.099653 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4824 11:36:07.105920 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4825 11:36:07.109441 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4826 11:36:07.112609 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4827 11:36:07.115705 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4828 11:36:07.122444 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4829 11:36:07.125783 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4830 11:36:07.129237 iDelay=205, Bit 7, Center 32 (-131 ~ 196) 328
4831 11:36:07.132736 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4832 11:36:07.135950 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4833 11:36:07.142145 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4834 11:36:07.145718 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4835 11:36:07.149189 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4836 11:36:07.152329 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4837 11:36:07.159285 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4838 11:36:07.161955 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4839 11:36:07.162372 ==
4840 11:36:07.165730 Dram Type= 6, Freq= 0, CH_1, rank 1
4841 11:36:07.169351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4842 11:36:07.169738 ==
4843 11:36:07.172579 DQS Delay:
4844 11:36:07.172992 DQS0 = 0, DQS1 = 0
4845 11:36:07.176031 DQM Delay:
4846 11:36:07.176416 DQM0 = 35, DQM1 = 29
4847 11:36:07.176720 DQ Delay:
4848 11:36:07.178659 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4849 11:36:07.181846 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =32
4850 11:36:07.185591 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4851 11:36:07.189001 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4852 11:36:07.189387
4853 11:36:07.189685
4854 11:36:07.198622 [DQSOSCAuto] RK1, (LSB)MR18= 0x385a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4855 11:36:07.202256 CH1 RK1: MR19=808, MR18=385A
4856 11:36:07.205125 CH1_RK1: MR19=0x808, MR18=0x385A, DQSOSC=392, MR23=63, INC=170, DEC=113
4857 11:36:07.208476 [RxdqsGatingPostProcess] freq 600
4858 11:36:07.215018 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4859 11:36:07.218377 Pre-setting of DQS Precalculation
4860 11:36:07.222201 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4861 11:36:07.231815 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4862 11:36:07.238631 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4863 11:36:07.239018
4864 11:36:07.239316
4865 11:36:07.241698 [Calibration Summary] 1200 Mbps
4866 11:36:07.242086 CH 0, Rank 0
4867 11:36:07.245232 SW Impedance : PASS
4868 11:36:07.245618 DUTY Scan : NO K
4869 11:36:07.248504 ZQ Calibration : PASS
4870 11:36:07.251416 Jitter Meter : NO K
4871 11:36:07.251801 CBT Training : PASS
4872 11:36:07.255341 Write leveling : PASS
4873 11:36:07.258650 RX DQS gating : PASS
4874 11:36:07.259040 RX DQ/DQS(RDDQC) : PASS
4875 11:36:07.261393 TX DQ/DQS : PASS
4876 11:36:07.265075 RX DATLAT : PASS
4877 11:36:07.265527 RX DQ/DQS(Engine): PASS
4878 11:36:07.268528 TX OE : NO K
4879 11:36:07.268914 All Pass.
4880 11:36:07.269215
4881 11:36:07.271589 CH 0, Rank 1
4882 11:36:07.271978 SW Impedance : PASS
4883 11:36:07.274853 DUTY Scan : NO K
4884 11:36:07.278141 ZQ Calibration : PASS
4885 11:36:07.278555 Jitter Meter : NO K
4886 11:36:07.281656 CBT Training : PASS
4887 11:36:07.282199 Write leveling : PASS
4888 11:36:07.285407 RX DQS gating : PASS
4889 11:36:07.288316 RX DQ/DQS(RDDQC) : PASS
4890 11:36:07.288702 TX DQ/DQS : PASS
4891 11:36:07.292099 RX DATLAT : PASS
4892 11:36:07.295324 RX DQ/DQS(Engine): PASS
4893 11:36:07.295708 TX OE : NO K
4894 11:36:07.298198 All Pass.
4895 11:36:07.298584
4896 11:36:07.298883 CH 1, Rank 0
4897 11:36:07.301536 SW Impedance : PASS
4898 11:36:07.301922 DUTY Scan : NO K
4899 11:36:07.304911 ZQ Calibration : PASS
4900 11:36:07.308120 Jitter Meter : NO K
4901 11:36:07.308512 CBT Training : PASS
4902 11:36:07.311816 Write leveling : PASS
4903 11:36:07.314934 RX DQS gating : PASS
4904 11:36:07.315394 RX DQ/DQS(RDDQC) : PASS
4905 11:36:07.317682 TX DQ/DQS : PASS
4906 11:36:07.321662 RX DATLAT : PASS
4907 11:36:07.322049 RX DQ/DQS(Engine): PASS
4908 11:36:07.324329 TX OE : NO K
4909 11:36:07.324744 All Pass.
4910 11:36:07.325044
4911 11:36:07.327935 CH 1, Rank 1
4912 11:36:07.328392 SW Impedance : PASS
4913 11:36:07.331497 DUTY Scan : NO K
4914 11:36:07.334541 ZQ Calibration : PASS
4915 11:36:07.334929 Jitter Meter : NO K
4916 11:36:07.337979 CBT Training : PASS
4917 11:36:07.341112 Write leveling : PASS
4918 11:36:07.341526 RX DQS gating : PASS
4919 11:36:07.344336 RX DQ/DQS(RDDQC) : PASS
4920 11:36:07.344719 TX DQ/DQS : PASS
4921 11:36:07.347843 RX DATLAT : PASS
4922 11:36:07.351060 RX DQ/DQS(Engine): PASS
4923 11:36:07.351448 TX OE : NO K
4924 11:36:07.354197 All Pass.
4925 11:36:07.354583
4926 11:36:07.354884 DramC Write-DBI off
4927 11:36:07.357724 PER_BANK_REFRESH: Hybrid Mode
4928 11:36:07.361225 TX_TRACKING: ON
4929 11:36:07.367306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4930 11:36:07.370894 [FAST_K] Save calibration result to emmc
4931 11:36:07.374554 dramc_set_vcore_voltage set vcore to 662500
4932 11:36:07.377498 Read voltage for 933, 3
4933 11:36:07.377883 Vio18 = 0
4934 11:36:07.381155 Vcore = 662500
4935 11:36:07.381537 Vdram = 0
4936 11:36:07.381832 Vddq = 0
4937 11:36:07.384382 Vmddr = 0
4938 11:36:07.388094 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4939 11:36:07.394609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4940 11:36:07.394998 MEM_TYPE=3, freq_sel=17
4941 11:36:07.397526 sv_algorithm_assistance_LP4_1600
4942 11:36:07.404034 ============ PULL DRAM RESETB DOWN ============
4943 11:36:07.407428 ========== PULL DRAM RESETB DOWN end =========
4944 11:36:07.411042 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4945 11:36:07.413921 ===================================
4946 11:36:07.417192 LPDDR4 DRAM CONFIGURATION
4947 11:36:07.420806 ===================================
4948 11:36:07.423876 EX_ROW_EN[0] = 0x0
4949 11:36:07.424386 EX_ROW_EN[1] = 0x0
4950 11:36:07.427166 LP4Y_EN = 0x0
4951 11:36:07.427555 WORK_FSP = 0x0
4952 11:36:07.430525 WL = 0x3
4953 11:36:07.430910 RL = 0x3
4954 11:36:07.433780 BL = 0x2
4955 11:36:07.434191 RPST = 0x0
4956 11:36:07.437458 RD_PRE = 0x0
4957 11:36:07.437840 WR_PRE = 0x1
4958 11:36:07.440367 WR_PST = 0x0
4959 11:36:07.440753 DBI_WR = 0x0
4960 11:36:07.444044 DBI_RD = 0x0
4961 11:36:07.444430 OTF = 0x1
4962 11:36:07.447211 ===================================
4963 11:36:07.450648 ===================================
4964 11:36:07.453591 ANA top config
4965 11:36:07.457116 ===================================
4966 11:36:07.460299 DLL_ASYNC_EN = 0
4967 11:36:07.460684 ALL_SLAVE_EN = 1
4968 11:36:07.463452 NEW_RANK_MODE = 1
4969 11:36:07.466822 DLL_IDLE_MODE = 1
4970 11:36:07.470211 LP45_APHY_COMB_EN = 1
4971 11:36:07.473231 TX_ODT_DIS = 1
4972 11:36:07.473619 NEW_8X_MODE = 1
4973 11:36:07.476862 ===================================
4974 11:36:07.479888 ===================================
4975 11:36:07.483509 data_rate = 1866
4976 11:36:07.486470 CKR = 1
4977 11:36:07.490140 DQ_P2S_RATIO = 8
4978 11:36:07.493157 ===================================
4979 11:36:07.496586 CA_P2S_RATIO = 8
4980 11:36:07.497011 DQ_CA_OPEN = 0
4981 11:36:07.500121 DQ_SEMI_OPEN = 0
4982 11:36:07.503215 CA_SEMI_OPEN = 0
4983 11:36:07.506490 CA_FULL_RATE = 0
4984 11:36:07.509753 DQ_CKDIV4_EN = 1
4985 11:36:07.513211 CA_CKDIV4_EN = 1
4986 11:36:07.516658 CA_PREDIV_EN = 0
4987 11:36:07.517046 PH8_DLY = 0
4988 11:36:07.519934 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4989 11:36:07.522990 DQ_AAMCK_DIV = 4
4990 11:36:07.526514 CA_AAMCK_DIV = 4
4991 11:36:07.529427 CA_ADMCK_DIV = 4
4992 11:36:07.532873 DQ_TRACK_CA_EN = 0
4993 11:36:07.533224 CA_PICK = 933
4994 11:36:07.535960 CA_MCKIO = 933
4995 11:36:07.539520 MCKIO_SEMI = 0
4996 11:36:07.542860 PLL_FREQ = 3732
4997 11:36:07.546212 DQ_UI_PI_RATIO = 32
4998 11:36:07.549601 CA_UI_PI_RATIO = 0
4999 11:36:07.553128 ===================================
5000 11:36:07.555837 ===================================
5001 11:36:07.559206 memory_type:LPDDR4
5002 11:36:07.559624 GP_NUM : 10
5003 11:36:07.562333 SRAM_EN : 1
5004 11:36:07.562715 MD32_EN : 0
5005 11:36:07.565845 ===================================
5006 11:36:07.569454 [ANA_INIT] >>>>>>>>>>>>>>
5007 11:36:07.572389 <<<<<< [CONFIGURE PHASE]: ANA_TX
5008 11:36:07.575825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5009 11:36:07.578778 ===================================
5010 11:36:07.582323 data_rate = 1866,PCW = 0X8f00
5011 11:36:07.585374 ===================================
5012 11:36:07.588868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5013 11:36:07.592425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5014 11:36:07.598797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 11:36:07.605504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5016 11:36:07.609001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5017 11:36:07.612348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5018 11:36:07.612784 [ANA_INIT] flow start
5019 11:36:07.615437 [ANA_INIT] PLL >>>>>>>>
5020 11:36:07.618497 [ANA_INIT] PLL <<<<<<<<
5021 11:36:07.618880 [ANA_INIT] MIDPI >>>>>>>>
5022 11:36:07.622193 [ANA_INIT] MIDPI <<<<<<<<
5023 11:36:07.625142 [ANA_INIT] DLL >>>>>>>>
5024 11:36:07.625522 [ANA_INIT] flow end
5025 11:36:07.632341 ============ LP4 DIFF to SE enter ============
5026 11:36:07.635653 ============ LP4 DIFF to SE exit ============
5027 11:36:07.638571 [ANA_INIT] <<<<<<<<<<<<<
5028 11:36:07.641754 [Flow] Enable top DCM control >>>>>
5029 11:36:07.644748 [Flow] Enable top DCM control <<<<<
5030 11:36:07.645149 Enable DLL master slave shuffle
5031 11:36:07.651670 ==============================================================
5032 11:36:07.654662 Gating Mode config
5033 11:36:07.658436 ==============================================================
5034 11:36:07.662174 Config description:
5035 11:36:07.671418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5036 11:36:07.678016 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5037 11:36:07.681685 SELPH_MODE 0: By rank 1: By Phase
5038 11:36:07.687749 ==============================================================
5039 11:36:07.691217 GAT_TRACK_EN = 1
5040 11:36:07.694648 RX_GATING_MODE = 2
5041 11:36:07.697987 RX_GATING_TRACK_MODE = 2
5042 11:36:07.700874 SELPH_MODE = 1
5043 11:36:07.704612 PICG_EARLY_EN = 1
5044 11:36:07.704975 VALID_LAT_VALUE = 1
5045 11:36:07.710739 ==============================================================
5046 11:36:07.714069 Enter into Gating configuration >>>>
5047 11:36:07.717542 Exit from Gating configuration <<<<
5048 11:36:07.721221 Enter into DVFS_PRE_config >>>>>
5049 11:36:07.731205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5050 11:36:07.733894 Exit from DVFS_PRE_config <<<<<
5051 11:36:07.737672 Enter into PICG configuration >>>>
5052 11:36:07.740429 Exit from PICG configuration <<<<
5053 11:36:07.743625 [RX_INPUT] configuration >>>>>
5054 11:36:07.747460 [RX_INPUT] configuration <<<<<
5055 11:36:07.753981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5056 11:36:07.757348 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5057 11:36:07.763858 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5058 11:36:07.770525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5059 11:36:07.777010 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5060 11:36:07.783407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5061 11:36:07.787344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5062 11:36:07.789911 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5063 11:36:07.793359 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5064 11:36:07.800008 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5065 11:36:07.803434 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5066 11:36:07.806421 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5067 11:36:07.810397 ===================================
5068 11:36:07.813400 LPDDR4 DRAM CONFIGURATION
5069 11:36:07.816948 ===================================
5070 11:36:07.820319 EX_ROW_EN[0] = 0x0
5071 11:36:07.820704 EX_ROW_EN[1] = 0x0
5072 11:36:07.823206 LP4Y_EN = 0x0
5073 11:36:07.823604 WORK_FSP = 0x0
5074 11:36:07.826291 WL = 0x3
5075 11:36:07.826679 RL = 0x3
5076 11:36:07.829799 BL = 0x2
5077 11:36:07.830276 RPST = 0x0
5078 11:36:07.832933 RD_PRE = 0x0
5079 11:36:07.833316 WR_PRE = 0x1
5080 11:36:07.836823 WR_PST = 0x0
5081 11:36:07.837209 DBI_WR = 0x0
5082 11:36:07.839706 DBI_RD = 0x0
5083 11:36:07.840095 OTF = 0x1
5084 11:36:07.843353 ===================================
5085 11:36:07.850081 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5086 11:36:07.853088 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5087 11:36:07.856354 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5088 11:36:07.859953 ===================================
5089 11:36:07.863312 LPDDR4 DRAM CONFIGURATION
5090 11:36:07.866517 ===================================
5091 11:36:07.866905 EX_ROW_EN[0] = 0x10
5092 11:36:07.869665 EX_ROW_EN[1] = 0x0
5093 11:36:07.873142 LP4Y_EN = 0x0
5094 11:36:07.873526 WORK_FSP = 0x0
5095 11:36:07.876117 WL = 0x3
5096 11:36:07.876500 RL = 0x3
5097 11:36:07.879672 BL = 0x2
5098 11:36:07.880052 RPST = 0x0
5099 11:36:07.882720 RD_PRE = 0x0
5100 11:36:07.883098 WR_PRE = 0x1
5101 11:36:07.886150 WR_PST = 0x0
5102 11:36:07.886546 DBI_WR = 0x0
5103 11:36:07.889496 DBI_RD = 0x0
5104 11:36:07.889875 OTF = 0x1
5105 11:36:07.893223 ===================================
5106 11:36:07.899615 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5107 11:36:07.904320 nWR fixed to 30
5108 11:36:07.907146 [ModeRegInit_LP4] CH0 RK0
5109 11:36:07.907526 [ModeRegInit_LP4] CH0 RK1
5110 11:36:07.910443 [ModeRegInit_LP4] CH1 RK0
5111 11:36:07.913787 [ModeRegInit_LP4] CH1 RK1
5112 11:36:07.914209 match AC timing 9
5113 11:36:07.920564 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5114 11:36:07.923644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5115 11:36:07.926970 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5116 11:36:07.933976 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5117 11:36:07.937286 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5118 11:36:07.937664 ==
5119 11:36:07.940190 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 11:36:07.943533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 11:36:07.943968 ==
5122 11:36:07.950064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 11:36:07.956660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5124 11:36:07.960140 [CA 0] Center 38 (8~69) winsize 62
5125 11:36:07.963350 [CA 1] Center 38 (8~69) winsize 62
5126 11:36:07.966936 [CA 2] Center 35 (5~66) winsize 62
5127 11:36:07.970018 [CA 3] Center 35 (5~65) winsize 61
5128 11:36:07.973475 [CA 4] Center 34 (4~65) winsize 62
5129 11:36:07.976576 [CA 5] Center 33 (3~64) winsize 62
5130 11:36:07.976964
5131 11:36:07.979880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5132 11:36:07.980377
5133 11:36:07.983215 [CATrainingPosCal] consider 1 rank data
5134 11:36:07.986636 u2DelayCellTimex100 = 270/100 ps
5135 11:36:07.990148 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5136 11:36:07.993406 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5137 11:36:07.996591 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5138 11:36:07.999732 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5139 11:36:08.003320 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5140 11:36:08.009952 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5141 11:36:08.010387
5142 11:36:08.013985 CA PerBit enable=1, Macro0, CA PI delay=33
5143 11:36:08.014421
5144 11:36:08.016912 [CBTSetCACLKResult] CA Dly = 33
5145 11:36:08.017376 CS Dly: 6 (0~37)
5146 11:36:08.017677 ==
5147 11:36:08.019976 Dram Type= 6, Freq= 0, CH_0, rank 1
5148 11:36:08.023149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 11:36:08.026586 ==
5150 11:36:08.029763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5151 11:36:08.036846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5152 11:36:08.040189 [CA 0] Center 38 (8~69) winsize 62
5153 11:36:08.043272 [CA 1] Center 38 (8~69) winsize 62
5154 11:36:08.046331 [CA 2] Center 35 (5~66) winsize 62
5155 11:36:08.049780 [CA 3] Center 35 (5~66) winsize 62
5156 11:36:08.053708 [CA 4] Center 34 (4~65) winsize 62
5157 11:36:08.057064 [CA 5] Center 34 (4~64) winsize 61
5158 11:36:08.057486
5159 11:36:08.059800 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5160 11:36:08.060217
5161 11:36:08.062947 [CATrainingPosCal] consider 2 rank data
5162 11:36:08.066606 u2DelayCellTimex100 = 270/100 ps
5163 11:36:08.069450 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5164 11:36:08.072633 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5165 11:36:08.076267 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5166 11:36:08.082865 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5167 11:36:08.085874 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5168 11:36:08.089245 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5169 11:36:08.089625
5170 11:36:08.093179 CA PerBit enable=1, Macro0, CA PI delay=34
5171 11:36:08.093637
5172 11:36:08.095947 [CBTSetCACLKResult] CA Dly = 34
5173 11:36:08.096406 CS Dly: 7 (0~39)
5174 11:36:08.096747
5175 11:36:08.099655 ----->DramcWriteLeveling(PI) begin...
5176 11:36:08.100048 ==
5177 11:36:08.102789 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:36:08.109400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:36:08.109825 ==
5180 11:36:08.112665 Write leveling (Byte 0): 33 => 33
5181 11:36:08.116161 Write leveling (Byte 1): 31 => 31
5182 11:36:08.116567 DramcWriteLeveling(PI) end<-----
5183 11:36:08.116864
5184 11:36:08.119641 ==
5185 11:36:08.122585 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:36:08.125883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:36:08.126306 ==
5188 11:36:08.129712 [Gating] SW mode calibration
5189 11:36:08.135693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5190 11:36:08.139182 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5191 11:36:08.145678 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5192 11:36:08.149016 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5193 11:36:08.152938 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:36:08.159151 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:36:08.162417 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 11:36:08.165769 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 11:36:08.171923 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 11:36:08.175944 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5199 11:36:08.178627 0 15 0 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (1 0)
5200 11:36:08.185414 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
5201 11:36:08.189109 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:36:08.191910 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:36:08.198406 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 11:36:08.201801 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 11:36:08.205308 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 11:36:08.212416 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 11:36:08.215223 1 0 0 | B1->B0 | 2929 3b3b | 0 1 | (0 0) (0 0)
5208 11:36:08.218871 1 0 4 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5209 11:36:08.225297 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:36:08.228455 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:36:08.231574 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 11:36:08.238522 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 11:36:08.241585 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 11:36:08.245227 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5215 11:36:08.251501 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5216 11:36:08.254658 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:36:08.258314 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:36:08.264884 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:36:08.268599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:36:08.271623 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:36:08.277829 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:36:08.281251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:36:08.284492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:36:08.291383 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:36:08.294435 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:36:08.297789 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:36:08.304946 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 11:36:08.307978 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:36:08.311180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 11:36:08.317875 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 11:36:08.320972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5232 11:36:08.324431 Total UI for P1: 0, mck2ui 16
5233 11:36:08.327778 best dqsien dly found for B0: ( 1, 2, 30)
5234 11:36:08.331883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 11:36:08.334478 Total UI for P1: 0, mck2ui 16
5236 11:36:08.337711 best dqsien dly found for B1: ( 1, 3, 2)
5237 11:36:08.341470 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5238 11:36:08.344612 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5239 11:36:08.345117
5240 11:36:08.347487 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5241 11:36:08.350971 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5242 11:36:08.354050 [Gating] SW calibration Done
5243 11:36:08.354505 ==
5244 11:36:08.357820 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 11:36:08.364274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 11:36:08.364783 ==
5247 11:36:08.365116 RX Vref Scan: 0
5248 11:36:08.365419
5249 11:36:08.367583 RX Vref 0 -> 0, step: 1
5250 11:36:08.368057
5251 11:36:08.370667 RX Delay -80 -> 252, step: 8
5252 11:36:08.374374 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5253 11:36:08.377451 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5254 11:36:08.380615 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5255 11:36:08.384226 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5256 11:36:08.391004 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5257 11:36:08.393891 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5258 11:36:08.397286 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5259 11:36:08.401128 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5260 11:36:08.404151 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5261 11:36:08.410741 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5262 11:36:08.414289 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5263 11:36:08.417057 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5264 11:36:08.420208 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5265 11:36:08.423673 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5266 11:36:08.430468 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5267 11:36:08.434162 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5268 11:36:08.434690 ==
5269 11:36:08.437052 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 11:36:08.440341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 11:36:08.440847 ==
5272 11:36:08.443962 DQS Delay:
5273 11:36:08.444461 DQS0 = 0, DQS1 = 0
5274 11:36:08.444794 DQM Delay:
5275 11:36:08.446687 DQM0 = 94, DQM1 = 82
5276 11:36:08.447107 DQ Delay:
5277 11:36:08.451041 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5278 11:36:08.454083 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5279 11:36:08.457311 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5280 11:36:08.460065 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5281 11:36:08.460558
5282 11:36:08.460885
5283 11:36:08.461187 ==
5284 11:36:08.463111 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 11:36:08.469821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 11:36:08.470366 ==
5287 11:36:08.470727
5288 11:36:08.471035
5289 11:36:08.471331 TX Vref Scan disable
5290 11:36:08.473652 == TX Byte 0 ==
5291 11:36:08.477410 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5292 11:36:08.483545 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5293 11:36:08.483972 == TX Byte 1 ==
5294 11:36:08.486947 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5295 11:36:08.493391 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5296 11:36:08.493821 ==
5297 11:36:08.496853 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 11:36:08.500271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 11:36:08.500696 ==
5300 11:36:08.501027
5301 11:36:08.501329
5302 11:36:08.503431 TX Vref Scan disable
5303 11:36:08.503858 == TX Byte 0 ==
5304 11:36:08.510236 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5305 11:36:08.513696 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5306 11:36:08.514248 == TX Byte 1 ==
5307 11:36:08.519971 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5308 11:36:08.523263 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5309 11:36:08.523691
5310 11:36:08.524018 [DATLAT]
5311 11:36:08.527377 Freq=933, CH0 RK0
5312 11:36:08.527800
5313 11:36:08.528125 DATLAT Default: 0xd
5314 11:36:08.530460 0, 0xFFFF, sum = 0
5315 11:36:08.530914 1, 0xFFFF, sum = 0
5316 11:36:08.533309 2, 0xFFFF, sum = 0
5317 11:36:08.533740 3, 0xFFFF, sum = 0
5318 11:36:08.536514 4, 0xFFFF, sum = 0
5319 11:36:08.539852 5, 0xFFFF, sum = 0
5320 11:36:08.540283 6, 0xFFFF, sum = 0
5321 11:36:08.543337 7, 0xFFFF, sum = 0
5322 11:36:08.543843 8, 0xFFFF, sum = 0
5323 11:36:08.546811 9, 0xFFFF, sum = 0
5324 11:36:08.547321 10, 0x0, sum = 1
5325 11:36:08.550321 11, 0x0, sum = 2
5326 11:36:08.550840 12, 0x0, sum = 3
5327 11:36:08.551183 13, 0x0, sum = 4
5328 11:36:08.553507 best_step = 11
5329 11:36:08.554005
5330 11:36:08.554366 ==
5331 11:36:08.556669 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 11:36:08.560010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 11:36:08.560519 ==
5334 11:36:08.563793 RX Vref Scan: 1
5335 11:36:08.564291
5336 11:36:08.566567 RX Vref 0 -> 0, step: 1
5337 11:36:08.567068
5338 11:36:08.567400 RX Delay -69 -> 252, step: 4
5339 11:36:08.567705
5340 11:36:08.570430 Set Vref, RX VrefLevel [Byte0]: 61
5341 11:36:08.573296 [Byte1]: 52
5342 11:36:08.577791
5343 11:36:08.578331 Final RX Vref Byte 0 = 61 to rank0
5344 11:36:08.581367 Final RX Vref Byte 1 = 52 to rank0
5345 11:36:08.584240 Final RX Vref Byte 0 = 61 to rank1
5346 11:36:08.587686 Final RX Vref Byte 1 = 52 to rank1==
5347 11:36:08.591008 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 11:36:08.597853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:36:08.598402 ==
5350 11:36:08.598740 DQS Delay:
5351 11:36:08.599049 DQS0 = 0, DQS1 = 0
5352 11:36:08.600730 DQM Delay:
5353 11:36:08.601149 DQM0 = 95, DQM1 = 83
5354 11:36:08.604168 DQ Delay:
5355 11:36:08.607369 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5356 11:36:08.610770 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5357 11:36:08.614208 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =76
5358 11:36:08.617698 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5359 11:36:08.618243
5360 11:36:08.618584
5361 11:36:08.624099 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5362 11:36:08.627362 CH0 RK0: MR19=505, MR18=1716
5363 11:36:08.633782 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5364 11:36:08.634252
5365 11:36:08.637359 ----->DramcWriteLeveling(PI) begin...
5366 11:36:08.637873 ==
5367 11:36:08.640633 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 11:36:08.643856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 11:36:08.644374 ==
5370 11:36:08.647339 Write leveling (Byte 0): 34 => 34
5371 11:36:08.650501 Write leveling (Byte 1): 29 => 29
5372 11:36:08.653880 DramcWriteLeveling(PI) end<-----
5373 11:36:08.654432
5374 11:36:08.654765 ==
5375 11:36:08.656983 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 11:36:08.660460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 11:36:08.660880 ==
5378 11:36:08.664069 [Gating] SW mode calibration
5379 11:36:08.670022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5380 11:36:08.676915 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5381 11:36:08.680631 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
5382 11:36:08.686927 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:36:08.690595 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:36:08.693497 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:36:08.700253 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 11:36:08.703599 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 11:36:08.706467 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5388 11:36:08.713432 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
5389 11:36:08.716607 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5390 11:36:08.719719 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5391 11:36:08.726889 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:36:08.729601 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 11:36:08.733139 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 11:36:08.739520 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 11:36:08.742879 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 11:36:08.746594 0 15 28 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
5397 11:36:08.752878 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5398 11:36:08.756018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:36:08.759664 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:36:08.766298 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:36:08.769638 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 11:36:08.772906 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:36:08.779397 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 11:36:08.782762 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5405 11:36:08.785996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5406 11:36:08.792647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:36:08.795910 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:36:08.799335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:36:08.806318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:36:08.809662 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:36:08.812973 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:36:08.819638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:36:08.822329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:36:08.826149 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:36:08.832635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:36:08.835737 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:36:08.839117 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:36:08.845498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:36:08.849458 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 11:36:08.852626 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5421 11:36:08.855515 Total UI for P1: 0, mck2ui 16
5422 11:36:08.859006 best dqsien dly found for B0: ( 1, 2, 26)
5423 11:36:08.862276 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:36:08.865511 Total UI for P1: 0, mck2ui 16
5425 11:36:08.868156 best dqsien dly found for B1: ( 1, 2, 30)
5426 11:36:08.871823 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5427 11:36:08.878801 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5428 11:36:08.878878
5429 11:36:08.881728 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5430 11:36:08.884750 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5431 11:36:08.888240 [Gating] SW calibration Done
5432 11:36:08.888323 ==
5433 11:36:08.891410 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 11:36:08.894622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 11:36:08.894776 ==
5436 11:36:08.898285 RX Vref Scan: 0
5437 11:36:08.898460
5438 11:36:08.898550 RX Vref 0 -> 0, step: 1
5439 11:36:08.898630
5440 11:36:08.901310 RX Delay -80 -> 252, step: 8
5441 11:36:08.904666 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5442 11:36:08.908042 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5443 11:36:08.914694 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5444 11:36:08.917964 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5445 11:36:08.921448 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5446 11:36:08.924866 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5447 11:36:08.928347 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5448 11:36:08.934957 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5449 11:36:08.938684 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5450 11:36:08.941385 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5451 11:36:08.945399 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5452 11:36:08.948365 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5453 11:36:08.954910 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5454 11:36:08.958225 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5455 11:36:08.961868 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5456 11:36:08.964737 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5457 11:36:08.965234 ==
5458 11:36:08.967918 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 11:36:08.974707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:36:08.975217 ==
5461 11:36:08.975551 DQS Delay:
5462 11:36:08.975860 DQS0 = 0, DQS1 = 0
5463 11:36:08.978232 DQM Delay:
5464 11:36:08.978685 DQM0 = 93, DQM1 = 83
5465 11:36:08.981343 DQ Delay:
5466 11:36:08.984684 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5467 11:36:08.987766 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5468 11:36:08.991356 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5469 11:36:08.994488 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =87
5470 11:36:08.995009
5471 11:36:08.995348
5472 11:36:08.995653 ==
5473 11:36:08.997847 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 11:36:09.000693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 11:36:09.001130 ==
5476 11:36:09.001466
5477 11:36:09.001769
5478 11:36:09.004607 TX Vref Scan disable
5479 11:36:09.005029 == TX Byte 0 ==
5480 11:36:09.011015 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5481 11:36:09.013968 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5482 11:36:09.014436 == TX Byte 1 ==
5483 11:36:09.020699 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5484 11:36:09.024503 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5485 11:36:09.025009 ==
5486 11:36:09.027075 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 11:36:09.030345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:36:09.030773 ==
5489 11:36:09.033918
5490 11:36:09.034454
5491 11:36:09.034783 TX Vref Scan disable
5492 11:36:09.037569 == TX Byte 0 ==
5493 11:36:09.040580 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5494 11:36:09.047723 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5495 11:36:09.048230 == TX Byte 1 ==
5496 11:36:09.050267 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5497 11:36:09.057982 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5498 11:36:09.058543
5499 11:36:09.058877 [DATLAT]
5500 11:36:09.059180 Freq=933, CH0 RK1
5501 11:36:09.059468
5502 11:36:09.060668 DATLAT Default: 0xb
5503 11:36:09.061093 0, 0xFFFF, sum = 0
5504 11:36:09.063852 1, 0xFFFF, sum = 0
5505 11:36:09.064372 2, 0xFFFF, sum = 0
5506 11:36:09.067168 3, 0xFFFF, sum = 0
5507 11:36:09.070263 4, 0xFFFF, sum = 0
5508 11:36:09.070694 5, 0xFFFF, sum = 0
5509 11:36:09.073809 6, 0xFFFF, sum = 0
5510 11:36:09.074451 7, 0xFFFF, sum = 0
5511 11:36:09.076965 8, 0xFFFF, sum = 0
5512 11:36:09.077393 9, 0xFFFF, sum = 0
5513 11:36:09.080301 10, 0x0, sum = 1
5514 11:36:09.080732 11, 0x0, sum = 2
5515 11:36:09.083473 12, 0x0, sum = 3
5516 11:36:09.083903 13, 0x0, sum = 4
5517 11:36:09.084296 best_step = 11
5518 11:36:09.084626
5519 11:36:09.086912 ==
5520 11:36:09.090606 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 11:36:09.093553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 11:36:09.094051 ==
5523 11:36:09.094427 RX Vref Scan: 0
5524 11:36:09.094733
5525 11:36:09.096784 RX Vref 0 -> 0, step: 1
5526 11:36:09.097204
5527 11:36:09.100274 RX Delay -77 -> 252, step: 4
5528 11:36:09.107230 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5529 11:36:09.110500 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5530 11:36:09.113681 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5531 11:36:09.116648 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5532 11:36:09.120210 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5533 11:36:09.123039 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5534 11:36:09.129937 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5535 11:36:09.133009 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5536 11:36:09.136570 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5537 11:36:09.139815 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5538 11:36:09.142867 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5539 11:36:09.149837 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5540 11:36:09.152942 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5541 11:36:09.156933 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5542 11:36:09.159493 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5543 11:36:09.163121 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5544 11:36:09.163640 ==
5545 11:36:09.166178 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 11:36:09.172689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 11:36:09.173076 ==
5548 11:36:09.173374 DQS Delay:
5549 11:36:09.175822 DQS0 = 0, DQS1 = 0
5550 11:36:09.176207 DQM Delay:
5551 11:36:09.179290 DQM0 = 92, DQM1 = 84
5552 11:36:09.179456 DQ Delay:
5553 11:36:09.182334 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =86
5554 11:36:09.185580 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5555 11:36:09.188767 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5556 11:36:09.193089 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =94
5557 11:36:09.193327
5558 11:36:09.193466
5559 11:36:09.199584 [DQSOSCAuto] RK1, (LSB)MR18= 0x3112, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5560 11:36:09.202256 CH0 RK1: MR19=505, MR18=3112
5561 11:36:09.208855 CH0_RK1: MR19=0x505, MR18=0x3112, DQSOSC=406, MR23=63, INC=65, DEC=43
5562 11:36:09.212671 [RxdqsGatingPostProcess] freq 933
5563 11:36:09.219252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5564 11:36:09.219717 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 11:36:09.222059 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 11:36:09.225525 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 11:36:09.228614 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 11:36:09.232347 best DQS0 dly(2T, 0.5T) = (0, 10)
5569 11:36:09.235772 best DQS1 dly(2T, 0.5T) = (0, 10)
5570 11:36:09.238924 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5571 11:36:09.242355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5572 11:36:09.245489 Pre-setting of DQS Precalculation
5573 11:36:09.252165 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5574 11:36:09.252593 ==
5575 11:36:09.255361 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 11:36:09.258365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 11:36:09.258827 ==
5578 11:36:09.265554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 11:36:09.268731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5580 11:36:09.272792 [CA 0] Center 37 (7~67) winsize 61
5581 11:36:09.275957 [CA 1] Center 37 (7~67) winsize 61
5582 11:36:09.279025 [CA 2] Center 34 (5~64) winsize 60
5583 11:36:09.282510 [CA 3] Center 34 (4~64) winsize 61
5584 11:36:09.285847 [CA 4] Center 34 (5~64) winsize 60
5585 11:36:09.289137 [CA 5] Center 33 (4~63) winsize 60
5586 11:36:09.289565
5587 11:36:09.292277 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5588 11:36:09.292703
5589 11:36:09.296066 [CATrainingPosCal] consider 1 rank data
5590 11:36:09.299276 u2DelayCellTimex100 = 270/100 ps
5591 11:36:09.302156 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5592 11:36:09.305666 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5593 11:36:09.312364 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5594 11:36:09.316059 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5595 11:36:09.318986 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5596 11:36:09.322373 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5597 11:36:09.322752
5598 11:36:09.325944 CA PerBit enable=1, Macro0, CA PI delay=33
5599 11:36:09.326406
5600 11:36:09.329093 [CBTSetCACLKResult] CA Dly = 33
5601 11:36:09.329538 CS Dly: 6 (0~37)
5602 11:36:09.332407 ==
5603 11:36:09.332789 Dram Type= 6, Freq= 0, CH_1, rank 1
5604 11:36:09.338974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 11:36:09.339553 ==
5606 11:36:09.342797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5607 11:36:09.348689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5608 11:36:09.353131 [CA 0] Center 37 (7~67) winsize 61
5609 11:36:09.356786 [CA 1] Center 37 (7~67) winsize 61
5610 11:36:09.359387 [CA 2] Center 35 (5~65) winsize 61
5611 11:36:09.362303 [CA 3] Center 34 (4~64) winsize 61
5612 11:36:09.365418 [CA 4] Center 34 (4~64) winsize 61
5613 11:36:09.369136 [CA 5] Center 33 (3~64) winsize 62
5614 11:36:09.369656
5615 11:36:09.372313 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5616 11:36:09.372692
5617 11:36:09.375699 [CATrainingPosCal] consider 2 rank data
5618 11:36:09.378746 u2DelayCellTimex100 = 270/100 ps
5619 11:36:09.382938 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5620 11:36:09.388750 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5621 11:36:09.392119 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5622 11:36:09.395960 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5623 11:36:09.398642 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5624 11:36:09.402317 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5625 11:36:09.402773
5626 11:36:09.406042 CA PerBit enable=1, Macro0, CA PI delay=33
5627 11:36:09.406554
5628 11:36:09.408582 [CBTSetCACLKResult] CA Dly = 33
5629 11:36:09.412308 CS Dly: 7 (0~39)
5630 11:36:09.412765
5631 11:36:09.415543 ----->DramcWriteLeveling(PI) begin...
5632 11:36:09.415931 ==
5633 11:36:09.418657 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 11:36:09.422213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 11:36:09.422729 ==
5636 11:36:09.425317 Write leveling (Byte 0): 26 => 26
5637 11:36:09.428413 Write leveling (Byte 1): 29 => 29
5638 11:36:09.431672 DramcWriteLeveling(PI) end<-----
5639 11:36:09.432150
5640 11:36:09.432501 ==
5641 11:36:09.435445 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:36:09.438375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:36:09.438759 ==
5644 11:36:09.441154 [Gating] SW mode calibration
5645 11:36:09.448248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5646 11:36:09.455004 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5647 11:36:09.458437 0 14 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
5648 11:36:09.462164 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:36:09.468886 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:36:09.471430 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 11:36:09.474672 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 11:36:09.481904 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 11:36:09.484618 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 11:36:09.488109 0 14 28 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
5655 11:36:09.494733 0 15 0 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
5656 11:36:09.497981 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:36:09.501490 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:36:09.508125 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 11:36:09.511656 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 11:36:09.514260 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 11:36:09.521425 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 11:36:09.524373 0 15 28 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
5663 11:36:09.527474 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:36:09.534223 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:36:09.537483 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:36:09.541282 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 11:36:09.547444 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 11:36:09.550506 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 11:36:09.553986 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 11:36:09.560291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5671 11:36:09.564210 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:36:09.567714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:36:09.573622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:36:09.577650 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:36:09.580788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:36:09.586875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:36:09.590408 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:36:09.593694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:36:09.600952 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:36:09.603942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:36:09.606987 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:36:09.613569 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:36:09.616764 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:36:09.620198 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 11:36:09.623277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 11:36:09.629703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5687 11:36:09.632960 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 11:36:09.636360 Total UI for P1: 0, mck2ui 16
5689 11:36:09.639768 best dqsien dly found for B0: ( 1, 2, 28)
5690 11:36:09.643530 Total UI for P1: 0, mck2ui 16
5691 11:36:09.646228 best dqsien dly found for B1: ( 1, 2, 28)
5692 11:36:09.650014 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5693 11:36:09.652878 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5694 11:36:09.652966
5695 11:36:09.657284 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5696 11:36:09.663348 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5697 11:36:09.663417 [Gating] SW calibration Done
5698 11:36:09.663473 ==
5699 11:36:09.666399 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 11:36:09.672879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 11:36:09.672968 ==
5702 11:36:09.673051 RX Vref Scan: 0
5703 11:36:09.673129
5704 11:36:09.676478 RX Vref 0 -> 0, step: 1
5705 11:36:09.676543
5706 11:36:09.679492 RX Delay -80 -> 252, step: 8
5707 11:36:09.683359 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5708 11:36:09.685946 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5709 11:36:09.689365 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5710 11:36:09.692781 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5711 11:36:09.699834 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5712 11:36:09.703079 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5713 11:36:09.705942 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5714 11:36:09.709644 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5715 11:36:09.712809 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5716 11:36:09.715995 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5717 11:36:09.722444 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5718 11:36:09.726627 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5719 11:36:09.729326 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5720 11:36:09.732748 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5721 11:36:09.736426 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5722 11:36:09.743002 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5723 11:36:09.743163 ==
5724 11:36:09.745876 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:36:09.749284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:36:09.749524 ==
5727 11:36:09.749685 DQS Delay:
5728 11:36:09.752293 DQS0 = 0, DQS1 = 0
5729 11:36:09.752565 DQM Delay:
5730 11:36:09.756106 DQM0 = 96, DQM1 = 89
5731 11:36:09.756322 DQ Delay:
5732 11:36:09.759484 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5733 11:36:09.763263 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5734 11:36:09.765943 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =87
5735 11:36:09.769154 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5736 11:36:09.769622
5737 11:36:09.770040
5738 11:36:09.770503 ==
5739 11:36:09.772657 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:36:09.775900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:36:09.776309 ==
5742 11:36:09.779223
5743 11:36:09.779598
5744 11:36:09.779891 TX Vref Scan disable
5745 11:36:09.782414 == TX Byte 0 ==
5746 11:36:09.785691 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5747 11:36:09.788759 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5748 11:36:09.792202 == TX Byte 1 ==
5749 11:36:09.795336 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5750 11:36:09.798858 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5751 11:36:09.799402 ==
5752 11:36:09.801873 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 11:36:09.809033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 11:36:09.809546 ==
5755 11:36:09.809989
5756 11:36:09.810406
5757 11:36:09.810678 TX Vref Scan disable
5758 11:36:09.813756 == TX Byte 0 ==
5759 11:36:09.816537 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5760 11:36:09.822901 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5761 11:36:09.823297 == TX Byte 1 ==
5762 11:36:09.826360 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5763 11:36:09.832915 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5764 11:36:09.833387
5765 11:36:09.833891 [DATLAT]
5766 11:36:09.834352 Freq=933, CH1 RK0
5767 11:36:09.834769
5768 11:36:09.836665 DATLAT Default: 0xd
5769 11:36:09.837178 0, 0xFFFF, sum = 0
5770 11:36:09.839920 1, 0xFFFF, sum = 0
5771 11:36:09.843147 2, 0xFFFF, sum = 0
5772 11:36:09.843593 3, 0xFFFF, sum = 0
5773 11:36:09.846602 4, 0xFFFF, sum = 0
5774 11:36:09.847050 5, 0xFFFF, sum = 0
5775 11:36:09.849909 6, 0xFFFF, sum = 0
5776 11:36:09.850345 7, 0xFFFF, sum = 0
5777 11:36:09.852924 8, 0xFFFF, sum = 0
5778 11:36:09.853365 9, 0xFFFF, sum = 0
5779 11:36:09.856222 10, 0x0, sum = 1
5780 11:36:09.856711 11, 0x0, sum = 2
5781 11:36:09.860136 12, 0x0, sum = 3
5782 11:36:09.860593 13, 0x0, sum = 4
5783 11:36:09.861109 best_step = 11
5784 11:36:09.861537
5785 11:36:09.863314 ==
5786 11:36:09.863856 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 11:36:09.869701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:36:09.870262 ==
5789 11:36:09.870704 RX Vref Scan: 1
5790 11:36:09.871070
5791 11:36:09.873176 RX Vref 0 -> 0, step: 1
5792 11:36:09.873626
5793 11:36:09.876198 RX Delay -69 -> 252, step: 4
5794 11:36:09.876734
5795 11:36:09.879497 Set Vref, RX VrefLevel [Byte0]: 58
5796 11:36:09.882891 [Byte1]: 50
5797 11:36:09.883280
5798 11:36:09.886071 Final RX Vref Byte 0 = 58 to rank0
5799 11:36:09.889491 Final RX Vref Byte 1 = 50 to rank0
5800 11:36:09.893102 Final RX Vref Byte 0 = 58 to rank1
5801 11:36:09.895976 Final RX Vref Byte 1 = 50 to rank1==
5802 11:36:09.899173 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 11:36:09.902591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 11:36:09.905689 ==
5805 11:36:09.906263 DQS Delay:
5806 11:36:09.906668 DQS0 = 0, DQS1 = 0
5807 11:36:09.909372 DQM Delay:
5808 11:36:09.909744 DQM0 = 95, DQM1 = 87
5809 11:36:09.912614 DQ Delay:
5810 11:36:09.915733 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =90
5811 11:36:09.916088 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5812 11:36:09.919473 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5813 11:36:09.922553 DQ12 =98, DQ13 =92, DQ14 =92, DQ15 =92
5814 11:36:09.925823
5815 11:36:09.926301
5816 11:36:09.932712 [DQSOSCAuto] RK0, (LSB)MR18= 0x60e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5817 11:36:09.935992 CH1 RK0: MR19=505, MR18=60E
5818 11:36:09.942682 CH1_RK0: MR19=0x505, MR18=0x60E, DQSOSC=417, MR23=63, INC=62, DEC=41
5819 11:36:09.943061
5820 11:36:09.945997 ----->DramcWriteLeveling(PI) begin...
5821 11:36:09.946392 ==
5822 11:36:09.949259 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:36:09.952578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:36:09.952976 ==
5825 11:36:09.955543 Write leveling (Byte 0): 25 => 25
5826 11:36:09.959007 Write leveling (Byte 1): 27 => 27
5827 11:36:09.962402 DramcWriteLeveling(PI) end<-----
5828 11:36:09.962768
5829 11:36:09.963057 ==
5830 11:36:09.965842 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:36:09.968950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:36:09.969260 ==
5833 11:36:09.972247 [Gating] SW mode calibration
5834 11:36:09.978812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5835 11:36:09.985620 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5836 11:36:09.989155 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5837 11:36:09.992762 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:36:09.998874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:36:10.002058 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 11:36:10.005776 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 11:36:10.012114 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 11:36:10.016022 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
5843 11:36:10.019364 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5844 11:36:10.026032 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:36:10.028703 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:36:10.031871 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 11:36:10.039211 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 11:36:10.042149 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 11:36:10.045543 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 11:36:10.052147 0 15 24 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
5851 11:36:10.055425 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
5852 11:36:10.058815 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:36:10.065491 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:36:10.068485 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:36:10.072249 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 11:36:10.078466 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 11:36:10.082031 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 11:36:10.085110 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5859 11:36:10.091913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:36:10.094819 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:36:10.098278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:36:10.104743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:36:10.108396 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:36:10.111313 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:36:10.118414 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:36:10.121356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:36:10.124678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:36:10.131162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:36:10.134623 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:36:10.138184 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:36:10.144813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 11:36:10.148029 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 11:36:10.151048 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 11:36:10.154388 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5875 11:36:10.160990 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 11:36:10.164264 Total UI for P1: 0, mck2ui 16
5877 11:36:10.167991 best dqsien dly found for B0: ( 1, 2, 24)
5878 11:36:10.171109 Total UI for P1: 0, mck2ui 16
5879 11:36:10.174630 best dqsien dly found for B1: ( 1, 2, 24)
5880 11:36:10.177840 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5881 11:36:10.181393 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5882 11:36:10.181805
5883 11:36:10.184605 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5884 11:36:10.188152 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5885 11:36:10.191109 [Gating] SW calibration Done
5886 11:36:10.191491 ==
5887 11:36:10.194407 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 11:36:10.197903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 11:36:10.198339 ==
5890 11:36:10.201056 RX Vref Scan: 0
5891 11:36:10.201439
5892 11:36:10.201863 RX Vref 0 -> 0, step: 1
5893 11:36:10.204435
5894 11:36:10.204814 RX Delay -80 -> 252, step: 8
5895 11:36:10.211174 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5896 11:36:10.214384 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5897 11:36:10.217446 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5898 11:36:10.220273 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5899 11:36:10.224001 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5900 11:36:10.227621 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5901 11:36:10.234361 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5902 11:36:10.237262 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5903 11:36:10.240503 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5904 11:36:10.244199 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5905 11:36:10.247745 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5906 11:36:10.253768 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5907 11:36:10.257570 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5908 11:36:10.260411 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5909 11:36:10.263618 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5910 11:36:10.266887 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5911 11:36:10.266962 ==
5912 11:36:10.270276 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 11:36:10.276841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 11:36:10.276916 ==
5915 11:36:10.276974 DQS Delay:
5916 11:36:10.279954 DQS0 = 0, DQS1 = 0
5917 11:36:10.280028 DQM Delay:
5918 11:36:10.280086 DQM0 = 94, DQM1 = 87
5919 11:36:10.283603 DQ Delay:
5920 11:36:10.286627 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5921 11:36:10.289979 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5922 11:36:10.293746 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5923 11:36:10.296482 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5924 11:36:10.296556
5925 11:36:10.296614
5926 11:36:10.296667 ==
5927 11:36:10.300121 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 11:36:10.303468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 11:36:10.303543 ==
5930 11:36:10.303600
5931 11:36:10.303653
5932 11:36:10.306119 TX Vref Scan disable
5933 11:36:10.309699 == TX Byte 0 ==
5934 11:36:10.312796 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5935 11:36:10.316333 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5936 11:36:10.319610 == TX Byte 1 ==
5937 11:36:10.322617 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5938 11:36:10.326427 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5939 11:36:10.326502 ==
5940 11:36:10.329515 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:36:10.333083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:36:10.336122 ==
5943 11:36:10.336196
5944 11:36:10.336253
5945 11:36:10.336306 TX Vref Scan disable
5946 11:36:10.339605 == TX Byte 0 ==
5947 11:36:10.343299 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5948 11:36:10.349495 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5949 11:36:10.349570 == TX Byte 1 ==
5950 11:36:10.353081 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5951 11:36:10.359560 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5952 11:36:10.359635
5953 11:36:10.359691 [DATLAT]
5954 11:36:10.359744 Freq=933, CH1 RK1
5955 11:36:10.359795
5956 11:36:10.362852 DATLAT Default: 0xb
5957 11:36:10.362927 0, 0xFFFF, sum = 0
5958 11:36:10.366355 1, 0xFFFF, sum = 0
5959 11:36:10.369346 2, 0xFFFF, sum = 0
5960 11:36:10.369421 3, 0xFFFF, sum = 0
5961 11:36:10.372931 4, 0xFFFF, sum = 0
5962 11:36:10.373320 5, 0xFFFF, sum = 0
5963 11:36:10.376283 6, 0xFFFF, sum = 0
5964 11:36:10.376358 7, 0xFFFF, sum = 0
5965 11:36:10.379412 8, 0xFFFF, sum = 0
5966 11:36:10.379488 9, 0xFFFF, sum = 0
5967 11:36:10.382542 10, 0x0, sum = 1
5968 11:36:10.382618 11, 0x0, sum = 2
5969 11:36:10.386014 12, 0x0, sum = 3
5970 11:36:10.386090 13, 0x0, sum = 4
5971 11:36:10.386191 best_step = 11
5972 11:36:10.389512
5973 11:36:10.389585 ==
5974 11:36:10.392721 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 11:36:10.396363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 11:36:10.396459 ==
5977 11:36:10.396525 RX Vref Scan: 0
5978 11:36:10.396587
5979 11:36:10.399241 RX Vref 0 -> 0, step: 1
5980 11:36:10.399326
5981 11:36:10.402625 RX Delay -69 -> 252, step: 4
5982 11:36:10.409233 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5983 11:36:10.412292 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5984 11:36:10.416175 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5985 11:36:10.419159 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5986 11:36:10.422597 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5987 11:36:10.426513 iDelay=203, Bit 5, Center 104 (7 ~ 202) 196
5988 11:36:10.432690 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5989 11:36:10.436074 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5990 11:36:10.439867 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5991 11:36:10.442589 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5992 11:36:10.446619 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5993 11:36:10.453105 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5994 11:36:10.456529 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5995 11:36:10.459431 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5996 11:36:10.462663 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5997 11:36:10.466029 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5998 11:36:10.466544 ==
5999 11:36:10.469403 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 11:36:10.475819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 11:36:10.476207 ==
6002 11:36:10.476502 DQS Delay:
6003 11:36:10.479645 DQS0 = 0, DQS1 = 0
6004 11:36:10.480028 DQM Delay:
6005 11:36:10.480356 DQM0 = 93, DQM1 = 90
6006 11:36:10.482191 DQ Delay:
6007 11:36:10.486090 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =90
6008 11:36:10.488995 DQ4 =88, DQ5 =104, DQ6 =106, DQ7 =90
6009 11:36:10.492394 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
6010 11:36:10.495996 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
6011 11:36:10.496384
6012 11:36:10.496679
6013 11:36:10.502379 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6014 11:36:10.505599 CH1 RK1: MR19=505, MR18=D21
6015 11:36:10.511884 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
6016 11:36:10.515495 [RxdqsGatingPostProcess] freq 933
6017 11:36:10.518442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6018 11:36:10.522320 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 11:36:10.525002 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 11:36:10.528760 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 11:36:10.531819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 11:36:10.535323 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 11:36:10.538745 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 11:36:10.541807 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 11:36:10.544990 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 11:36:10.548759 Pre-setting of DQS Precalculation
6027 11:36:10.552151 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6028 11:36:10.561889 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6029 11:36:10.568328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6030 11:36:10.568402
6031 11:36:10.568459
6032 11:36:10.571965 [Calibration Summary] 1866 Mbps
6033 11:36:10.572039 CH 0, Rank 0
6034 11:36:10.575038 SW Impedance : PASS
6035 11:36:10.575112 DUTY Scan : NO K
6036 11:36:10.578578 ZQ Calibration : PASS
6037 11:36:10.582007 Jitter Meter : NO K
6038 11:36:10.582106 CBT Training : PASS
6039 11:36:10.585154 Write leveling : PASS
6040 11:36:10.588925 RX DQS gating : PASS
6041 11:36:10.588999 RX DQ/DQS(RDDQC) : PASS
6042 11:36:10.591786 TX DQ/DQS : PASS
6043 11:36:10.591861 RX DATLAT : PASS
6044 11:36:10.595067 RX DQ/DQS(Engine): PASS
6045 11:36:10.598589 TX OE : NO K
6046 11:36:10.598664 All Pass.
6047 11:36:10.598728
6048 11:36:10.598800 CH 0, Rank 1
6049 11:36:10.601697 SW Impedance : PASS
6050 11:36:10.605084 DUTY Scan : NO K
6051 11:36:10.605158 ZQ Calibration : PASS
6052 11:36:10.608139 Jitter Meter : NO K
6053 11:36:10.611365 CBT Training : PASS
6054 11:36:10.611438 Write leveling : PASS
6055 11:36:10.614990 RX DQS gating : PASS
6056 11:36:10.617735 RX DQ/DQS(RDDQC) : PASS
6057 11:36:10.617810 TX DQ/DQS : PASS
6058 11:36:10.621086 RX DATLAT : PASS
6059 11:36:10.624348 RX DQ/DQS(Engine): PASS
6060 11:36:10.624422 TX OE : NO K
6061 11:36:10.628325 All Pass.
6062 11:36:10.628399
6063 11:36:10.628455 CH 1, Rank 0
6064 11:36:10.631120 SW Impedance : PASS
6065 11:36:10.631194 DUTY Scan : NO K
6066 11:36:10.634498 ZQ Calibration : PASS
6067 11:36:10.637775 Jitter Meter : NO K
6068 11:36:10.637921 CBT Training : PASS
6069 11:36:10.641150 Write leveling : PASS
6070 11:36:10.644219 RX DQS gating : PASS
6071 11:36:10.644295 RX DQ/DQS(RDDQC) : PASS
6072 11:36:10.648380 TX DQ/DQS : PASS
6073 11:36:10.651052 RX DATLAT : PASS
6074 11:36:10.651132 RX DQ/DQS(Engine): PASS
6075 11:36:10.654405 TX OE : NO K
6076 11:36:10.654491 All Pass.
6077 11:36:10.654557
6078 11:36:10.658079 CH 1, Rank 1
6079 11:36:10.658179 SW Impedance : PASS
6080 11:36:10.660917 DUTY Scan : NO K
6081 11:36:10.660991 ZQ Calibration : PASS
6082 11:36:10.664351 Jitter Meter : NO K
6083 11:36:10.667923 CBT Training : PASS
6084 11:36:10.668009 Write leveling : PASS
6085 11:36:10.671133 RX DQS gating : PASS
6086 11:36:10.674129 RX DQ/DQS(RDDQC) : PASS
6087 11:36:10.674221 TX DQ/DQS : PASS
6088 11:36:10.677690 RX DATLAT : PASS
6089 11:36:10.680928 RX DQ/DQS(Engine): PASS
6090 11:36:10.681002 TX OE : NO K
6091 11:36:10.684315 All Pass.
6092 11:36:10.684389
6093 11:36:10.684445 DramC Write-DBI off
6094 11:36:10.687689 PER_BANK_REFRESH: Hybrid Mode
6095 11:36:10.687766 TX_TRACKING: ON
6096 11:36:10.697542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6097 11:36:10.701025 [FAST_K] Save calibration result to emmc
6098 11:36:10.704761 dramc_set_vcore_voltage set vcore to 650000
6099 11:36:10.708085 Read voltage for 400, 6
6100 11:36:10.708164 Vio18 = 0
6101 11:36:10.710838 Vcore = 650000
6102 11:36:10.710917 Vdram = 0
6103 11:36:10.710978 Vddq = 0
6104 11:36:10.714243 Vmddr = 0
6105 11:36:10.717286 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6106 11:36:10.724064 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6107 11:36:10.724151 MEM_TYPE=3, freq_sel=20
6108 11:36:10.727382 sv_algorithm_assistance_LP4_800
6109 11:36:10.734104 ============ PULL DRAM RESETB DOWN ============
6110 11:36:10.737183 ========== PULL DRAM RESETB DOWN end =========
6111 11:36:10.740592 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6112 11:36:10.744306 ===================================
6113 11:36:10.747886 LPDDR4 DRAM CONFIGURATION
6114 11:36:10.750712 ===================================
6115 11:36:10.750883 EX_ROW_EN[0] = 0x0
6116 11:36:10.753951 EX_ROW_EN[1] = 0x0
6117 11:36:10.757315 LP4Y_EN = 0x0
6118 11:36:10.757496 WORK_FSP = 0x0
6119 11:36:10.760912 WL = 0x2
6120 11:36:10.761095 RL = 0x2
6121 11:36:10.763684 BL = 0x2
6122 11:36:10.763758 RPST = 0x0
6123 11:36:10.767185 RD_PRE = 0x0
6124 11:36:10.767263 WR_PRE = 0x1
6125 11:36:10.770925 WR_PST = 0x0
6126 11:36:10.770999 DBI_WR = 0x0
6127 11:36:10.774054 DBI_RD = 0x0
6128 11:36:10.774143 OTF = 0x1
6129 11:36:10.777425 ===================================
6130 11:36:10.780597 ===================================
6131 11:36:10.784355 ANA top config
6132 11:36:10.787297 ===================================
6133 11:36:10.787382 DLL_ASYNC_EN = 0
6134 11:36:10.790397 ALL_SLAVE_EN = 1
6135 11:36:10.793634 NEW_RANK_MODE = 1
6136 11:36:10.797396 DLL_IDLE_MODE = 1
6137 11:36:10.800324 LP45_APHY_COMB_EN = 1
6138 11:36:10.800457 TX_ODT_DIS = 1
6139 11:36:10.803645 NEW_8X_MODE = 1
6140 11:36:10.807182 ===================================
6141 11:36:10.810209 ===================================
6142 11:36:10.814083 data_rate = 800
6143 11:36:10.816911 CKR = 1
6144 11:36:10.820425 DQ_P2S_RATIO = 4
6145 11:36:10.823845 ===================================
6146 11:36:10.824027 CA_P2S_RATIO = 4
6147 11:36:10.827004 DQ_CA_OPEN = 0
6148 11:36:10.830531 DQ_SEMI_OPEN = 1
6149 11:36:10.833523 CA_SEMI_OPEN = 1
6150 11:36:10.837080 CA_FULL_RATE = 0
6151 11:36:10.840362 DQ_CKDIV4_EN = 0
6152 11:36:10.840713 CA_CKDIV4_EN = 1
6153 11:36:10.843862 CA_PREDIV_EN = 0
6154 11:36:10.847551 PH8_DLY = 0
6155 11:36:10.850595 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6156 11:36:10.853739 DQ_AAMCK_DIV = 0
6157 11:36:10.857004 CA_AAMCK_DIV = 0
6158 11:36:10.857386 CA_ADMCK_DIV = 4
6159 11:36:10.860112 DQ_TRACK_CA_EN = 0
6160 11:36:10.864049 CA_PICK = 800
6161 11:36:10.867025 CA_MCKIO = 400
6162 11:36:10.870150 MCKIO_SEMI = 400
6163 11:36:10.873459 PLL_FREQ = 3016
6164 11:36:10.877202 DQ_UI_PI_RATIO = 32
6165 11:36:10.879875 CA_UI_PI_RATIO = 32
6166 11:36:10.883358 ===================================
6167 11:36:10.886565 ===================================
6168 11:36:10.886641 memory_type:LPDDR4
6169 11:36:10.889944 GP_NUM : 10
6170 11:36:10.893065 SRAM_EN : 1
6171 11:36:10.893146 MD32_EN : 0
6172 11:36:10.896716 ===================================
6173 11:36:10.899695 [ANA_INIT] >>>>>>>>>>>>>>
6174 11:36:10.903371 <<<<<< [CONFIGURE PHASE]: ANA_TX
6175 11:36:10.906043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6176 11:36:10.909930 ===================================
6177 11:36:10.913272 data_rate = 800,PCW = 0X7400
6178 11:36:10.916211 ===================================
6179 11:36:10.919637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6180 11:36:10.923270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 11:36:10.936593 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 11:36:10.939876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6183 11:36:10.942835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6184 11:36:10.945974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6185 11:36:10.949030 [ANA_INIT] flow start
6186 11:36:10.952444 [ANA_INIT] PLL >>>>>>>>
6187 11:36:10.952518 [ANA_INIT] PLL <<<<<<<<
6188 11:36:10.956057 [ANA_INIT] MIDPI >>>>>>>>
6189 11:36:10.959036 [ANA_INIT] MIDPI <<<<<<<<
6190 11:36:10.959111 [ANA_INIT] DLL >>>>>>>>
6191 11:36:10.962557 [ANA_INIT] flow end
6192 11:36:10.966231 ============ LP4 DIFF to SE enter ============
6193 11:36:10.969076 ============ LP4 DIFF to SE exit ============
6194 11:36:10.972431 [ANA_INIT] <<<<<<<<<<<<<
6195 11:36:10.975817 [Flow] Enable top DCM control >>>>>
6196 11:36:10.978753 [Flow] Enable top DCM control <<<<<
6197 11:36:10.982297 Enable DLL master slave shuffle
6198 11:36:10.988724 ==============================================================
6199 11:36:10.988799 Gating Mode config
6200 11:36:10.995606 ==============================================================
6201 11:36:10.995681 Config description:
6202 11:36:11.005856 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6203 11:36:11.012218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6204 11:36:11.018784 SELPH_MODE 0: By rank 1: By Phase
6205 11:36:11.021998 ==============================================================
6206 11:36:11.025315 GAT_TRACK_EN = 0
6207 11:36:11.028617 RX_GATING_MODE = 2
6208 11:36:11.032059 RX_GATING_TRACK_MODE = 2
6209 11:36:11.035406 SELPH_MODE = 1
6210 11:36:11.038394 PICG_EARLY_EN = 1
6211 11:36:11.041957 VALID_LAT_VALUE = 1
6212 11:36:11.048380 ==============================================================
6213 11:36:11.052275 Enter into Gating configuration >>>>
6214 11:36:11.054927 Exit from Gating configuration <<<<
6215 11:36:11.058589 Enter into DVFS_PRE_config >>>>>
6216 11:36:11.068453 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6217 11:36:11.071833 Exit from DVFS_PRE_config <<<<<
6218 11:36:11.074873 Enter into PICG configuration >>>>
6219 11:36:11.078241 Exit from PICG configuration <<<<
6220 11:36:11.081930 [RX_INPUT] configuration >>>>>
6221 11:36:11.082029 [RX_INPUT] configuration <<<<<
6222 11:36:11.087941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6223 11:36:11.095065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6224 11:36:11.098049 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 11:36:11.104839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 11:36:11.111392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 11:36:11.117834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 11:36:11.121241 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6229 11:36:11.124368 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6230 11:36:11.130837 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6231 11:36:11.134728 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6232 11:36:11.138107 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6233 11:36:11.144404 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 11:36:11.147939 ===================================
6235 11:36:11.148026 LPDDR4 DRAM CONFIGURATION
6236 11:36:11.150844 ===================================
6237 11:36:11.154242 EX_ROW_EN[0] = 0x0
6238 11:36:11.154336 EX_ROW_EN[1] = 0x0
6239 11:36:11.157524 LP4Y_EN = 0x0
6240 11:36:11.161220 WORK_FSP = 0x0
6241 11:36:11.161295 WL = 0x2
6242 11:36:11.164305 RL = 0x2
6243 11:36:11.164380 BL = 0x2
6244 11:36:11.167452 RPST = 0x0
6245 11:36:11.167529 RD_PRE = 0x0
6246 11:36:11.170735 WR_PRE = 0x1
6247 11:36:11.170810 WR_PST = 0x0
6248 11:36:11.174530 DBI_WR = 0x0
6249 11:36:11.174611 DBI_RD = 0x0
6250 11:36:11.177366 OTF = 0x1
6251 11:36:11.180853 ===================================
6252 11:36:11.184391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6253 11:36:11.187793 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6254 11:36:11.194170 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6255 11:36:11.194286 ===================================
6256 11:36:11.197912 LPDDR4 DRAM CONFIGURATION
6257 11:36:11.201126 ===================================
6258 11:36:11.204349 EX_ROW_EN[0] = 0x10
6259 11:36:11.204560 EX_ROW_EN[1] = 0x0
6260 11:36:11.207782 LP4Y_EN = 0x0
6261 11:36:11.207991 WORK_FSP = 0x0
6262 11:36:11.211104 WL = 0x2
6263 11:36:11.211310 RL = 0x2
6264 11:36:11.214060 BL = 0x2
6265 11:36:11.218074 RPST = 0x0
6266 11:36:11.218399 RD_PRE = 0x0
6267 11:36:11.221167 WR_PRE = 0x1
6268 11:36:11.221496 WR_PST = 0x0
6269 11:36:11.224698 DBI_WR = 0x0
6270 11:36:11.225053 DBI_RD = 0x0
6271 11:36:11.228442 OTF = 0x1
6272 11:36:11.231328 ===================================
6273 11:36:11.238232 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6274 11:36:11.240860 nWR fixed to 30
6275 11:36:11.241358 [ModeRegInit_LP4] CH0 RK0
6276 11:36:11.244417 [ModeRegInit_LP4] CH0 RK1
6277 11:36:11.247795 [ModeRegInit_LP4] CH1 RK0
6278 11:36:11.248294 [ModeRegInit_LP4] CH1 RK1
6279 11:36:11.251080 match AC timing 19
6280 11:36:11.254537 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6281 11:36:11.257927 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6282 11:36:11.264332 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6283 11:36:11.267738 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6284 11:36:11.274336 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6285 11:36:11.274767 ==
6286 11:36:11.277335 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 11:36:11.280919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 11:36:11.281351 ==
6289 11:36:11.287445 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 11:36:11.290845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6291 11:36:11.293691 [CA 0] Center 36 (8~64) winsize 57
6292 11:36:11.296963 [CA 1] Center 36 (8~64) winsize 57
6293 11:36:11.300151 [CA 2] Center 36 (8~64) winsize 57
6294 11:36:11.303251 [CA 3] Center 36 (8~64) winsize 57
6295 11:36:11.306490 [CA 4] Center 36 (8~64) winsize 57
6296 11:36:11.309955 [CA 5] Center 36 (8~64) winsize 57
6297 11:36:11.310030
6298 11:36:11.313183 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6299 11:36:11.313259
6300 11:36:11.316471 [CATrainingPosCal] consider 1 rank data
6301 11:36:11.319768 u2DelayCellTimex100 = 270/100 ps
6302 11:36:11.323585 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:36:11.326441 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:36:11.333750 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:36:11.336304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:36:11.339770 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:36:11.342931 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:36:11.343007
6309 11:36:11.346583 CA PerBit enable=1, Macro0, CA PI delay=36
6310 11:36:11.346659
6311 11:36:11.349682 [CBTSetCACLKResult] CA Dly = 36
6312 11:36:11.349759 CS Dly: 1 (0~32)
6313 11:36:11.353075 ==
6314 11:36:11.353151 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 11:36:11.359509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:36:11.359586 ==
6317 11:36:11.363122 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 11:36:11.369469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6319 11:36:11.372914 [CA 0] Center 36 (8~64) winsize 57
6320 11:36:11.376109 [CA 1] Center 36 (8~64) winsize 57
6321 11:36:11.379661 [CA 2] Center 36 (8~64) winsize 57
6322 11:36:11.382723 [CA 3] Center 36 (8~64) winsize 57
6323 11:36:11.386211 [CA 4] Center 36 (8~64) winsize 57
6324 11:36:11.389645 [CA 5] Center 36 (8~64) winsize 57
6325 11:36:11.389723
6326 11:36:11.392565 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6327 11:36:11.392642
6328 11:36:11.396322 [CATrainingPosCal] consider 2 rank data
6329 11:36:11.399768 u2DelayCellTimex100 = 270/100 ps
6330 11:36:11.403084 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:36:11.406194 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:36:11.409777 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:36:11.412582 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:36:11.419739 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:36:11.422960 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 11:36:11.423037
6337 11:36:11.426146 CA PerBit enable=1, Macro0, CA PI delay=36
6338 11:36:11.426222
6339 11:36:11.429246 [CBTSetCACLKResult] CA Dly = 36
6340 11:36:11.429323 CS Dly: 1 (0~32)
6341 11:36:11.429398
6342 11:36:11.432588 ----->DramcWriteLeveling(PI) begin...
6343 11:36:11.432666 ==
6344 11:36:11.436219 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 11:36:11.443031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 11:36:11.443108 ==
6347 11:36:11.445616 Write leveling (Byte 0): 40 => 8
6348 11:36:11.445693 Write leveling (Byte 1): 32 => 0
6349 11:36:11.449202 DramcWriteLeveling(PI) end<-----
6350 11:36:11.449278
6351 11:36:11.449355 ==
6352 11:36:11.452227 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:36:11.458976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:36:11.459052 ==
6355 11:36:11.462980 [Gating] SW mode calibration
6356 11:36:11.468840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6357 11:36:11.472605 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6358 11:36:11.479453 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 11:36:11.482344 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 11:36:11.485669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 11:36:11.492199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 11:36:11.495830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:36:11.499252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 11:36:11.506072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 11:36:11.509158 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 11:36:11.512716 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 11:36:11.515910 Total UI for P1: 0, mck2ui 16
6368 11:36:11.519413 best dqsien dly found for B0: ( 0, 14, 24)
6369 11:36:11.522399 Total UI for P1: 0, mck2ui 16
6370 11:36:11.525723 best dqsien dly found for B1: ( 0, 14, 24)
6371 11:36:11.529053 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6372 11:36:11.532052 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6373 11:36:11.532127
6374 11:36:11.535707 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 11:36:11.542070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 11:36:11.542153 [Gating] SW calibration Done
6377 11:36:11.542211 ==
6378 11:36:11.545109 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:36:11.552013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:36:11.552087 ==
6381 11:36:11.552144 RX Vref Scan: 0
6382 11:36:11.552196
6383 11:36:11.555106 RX Vref 0 -> 0, step: 1
6384 11:36:11.555179
6385 11:36:11.558438 RX Delay -410 -> 252, step: 16
6386 11:36:11.561945 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6387 11:36:11.565296 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6388 11:36:11.571603 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6389 11:36:11.575010 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6390 11:36:11.578553 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6391 11:36:11.582414 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6392 11:36:11.588569 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6393 11:36:11.591606 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6394 11:36:11.595243 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6395 11:36:11.598765 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6396 11:36:11.605829 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6397 11:36:11.608868 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6398 11:36:11.612037 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6399 11:36:11.615423 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6400 11:36:11.622231 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6401 11:36:11.625935 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6402 11:36:11.626734 ==
6403 11:36:11.628736 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:36:11.632204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:36:11.632623 ==
6406 11:36:11.635450 DQS Delay:
6407 11:36:11.635868 DQS0 = 59, DQS1 = 59
6408 11:36:11.639262 DQM Delay:
6409 11:36:11.639681 DQM0 = 17, DQM1 = 10
6410 11:36:11.640015 DQ Delay:
6411 11:36:11.641833 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6412 11:36:11.645298 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6413 11:36:11.649343 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6414 11:36:11.652388 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6415 11:36:11.652883
6416 11:36:11.653206
6417 11:36:11.653502 ==
6418 11:36:11.655346 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 11:36:11.662424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 11:36:11.662846 ==
6421 11:36:11.663165
6422 11:36:11.663457
6423 11:36:11.663737 TX Vref Scan disable
6424 11:36:11.665440 == TX Byte 0 ==
6425 11:36:11.668487 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6426 11:36:11.672337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6427 11:36:11.675783 == TX Byte 1 ==
6428 11:36:11.678889 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6429 11:36:11.682219 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6430 11:36:11.685516 ==
6431 11:36:11.688606 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 11:36:11.692176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 11:36:11.692598 ==
6434 11:36:11.692942
6435 11:36:11.693244
6436 11:36:11.695218 TX Vref Scan disable
6437 11:36:11.695657 == TX Byte 0 ==
6438 11:36:11.699090 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6439 11:36:11.705156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6440 11:36:11.705724 == TX Byte 1 ==
6441 11:36:11.708312 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6442 11:36:11.715507 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6443 11:36:11.716134
6444 11:36:11.716575 [DATLAT]
6445 11:36:11.716890 Freq=400, CH0 RK0
6446 11:36:11.717186
6447 11:36:11.718638 DATLAT Default: 0xf
6448 11:36:11.721945 0, 0xFFFF, sum = 0
6449 11:36:11.722414 1, 0xFFFF, sum = 0
6450 11:36:11.725115 2, 0xFFFF, sum = 0
6451 11:36:11.725540 3, 0xFFFF, sum = 0
6452 11:36:11.728400 4, 0xFFFF, sum = 0
6453 11:36:11.728832 5, 0xFFFF, sum = 0
6454 11:36:11.731891 6, 0xFFFF, sum = 0
6455 11:36:11.732321 7, 0xFFFF, sum = 0
6456 11:36:11.735064 8, 0xFFFF, sum = 0
6457 11:36:11.735490 9, 0xFFFF, sum = 0
6458 11:36:11.739120 10, 0xFFFF, sum = 0
6459 11:36:11.739630 11, 0xFFFF, sum = 0
6460 11:36:11.741663 12, 0xFFFF, sum = 0
6461 11:36:11.742197 13, 0x0, sum = 1
6462 11:36:11.744622 14, 0x0, sum = 2
6463 11:36:11.745057 15, 0x0, sum = 3
6464 11:36:11.748148 16, 0x0, sum = 4
6465 11:36:11.748656 best_step = 14
6466 11:36:11.748982
6467 11:36:11.749284 ==
6468 11:36:11.751795 Dram Type= 6, Freq= 0, CH_0, rank 0
6469 11:36:11.758077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 11:36:11.758617 ==
6471 11:36:11.758951 RX Vref Scan: 1
6472 11:36:11.759254
6473 11:36:11.761589 RX Vref 0 -> 0, step: 1
6474 11:36:11.762087
6475 11:36:11.764603 RX Delay -359 -> 252, step: 8
6476 11:36:11.765023
6477 11:36:11.768052 Set Vref, RX VrefLevel [Byte0]: 61
6478 11:36:11.771646 [Byte1]: 52
6479 11:36:11.772131
6480 11:36:11.774638 Final RX Vref Byte 0 = 61 to rank0
6481 11:36:11.777303 Final RX Vref Byte 1 = 52 to rank0
6482 11:36:11.780609 Final RX Vref Byte 0 = 61 to rank1
6483 11:36:11.784231 Final RX Vref Byte 1 = 52 to rank1==
6484 11:36:11.787088 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 11:36:11.790861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 11:36:11.793976 ==
6487 11:36:11.794051 DQS Delay:
6488 11:36:11.794133 DQS0 = 60, DQS1 = 68
6489 11:36:11.797041 DQM Delay:
6490 11:36:11.797116 DQM0 = 14, DQM1 = 13
6491 11:36:11.800455 DQ Delay:
6492 11:36:11.804020 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6493 11:36:11.804095 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6494 11:36:11.806904 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6495 11:36:11.810941 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6496 11:36:11.811017
6497 11:36:11.813788
6498 11:36:11.820469 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6499 11:36:11.823725 CH0 RK0: MR19=C0C, MR18=8381
6500 11:36:11.830243 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6501 11:36:11.830318 ==
6502 11:36:11.833760 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:36:11.836910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:36:11.836985 ==
6505 11:36:11.840128 [Gating] SW mode calibration
6506 11:36:11.846929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6507 11:36:11.853604 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6508 11:36:11.856631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 11:36:11.860076 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 11:36:11.867536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 11:36:11.869876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 11:36:11.873683 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:36:11.876566 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 11:36:11.883249 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 11:36:11.887121 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 11:36:11.889793 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 11:36:11.893512 Total UI for P1: 0, mck2ui 16
6518 11:36:11.896381 best dqsien dly found for B0: ( 0, 14, 24)
6519 11:36:11.900042 Total UI for P1: 0, mck2ui 16
6520 11:36:11.902992 best dqsien dly found for B1: ( 0, 14, 24)
6521 11:36:11.906874 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6522 11:36:11.913059 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6523 11:36:11.913130
6524 11:36:11.916683 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 11:36:11.919980 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 11:36:11.923017 [Gating] SW calibration Done
6527 11:36:11.923085 ==
6528 11:36:11.926514 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:36:11.929367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:36:11.929428 ==
6531 11:36:11.932844 RX Vref Scan: 0
6532 11:36:11.932910
6533 11:36:11.932961 RX Vref 0 -> 0, step: 1
6534 11:36:11.933010
6535 11:36:11.935919 RX Delay -410 -> 252, step: 16
6536 11:36:11.942771 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6537 11:36:11.946091 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6538 11:36:11.949293 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6539 11:36:11.952644 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6540 11:36:11.959253 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6541 11:36:11.962259 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6542 11:36:11.966288 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6543 11:36:11.969145 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6544 11:36:11.975621 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6545 11:36:11.979092 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6546 11:36:11.982520 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6547 11:36:11.985515 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6548 11:36:11.992183 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6549 11:36:11.995847 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6550 11:36:11.998902 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6551 11:36:12.002910 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6552 11:36:12.005890 ==
6553 11:36:12.005952 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:36:12.012289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:36:12.012354 ==
6556 11:36:12.012407 DQS Delay:
6557 11:36:12.015405 DQS0 = 59, DQS1 = 59
6558 11:36:12.015466 DQM Delay:
6559 11:36:12.018883 DQM0 = 16, DQM1 = 10
6560 11:36:12.018940 DQ Delay:
6561 11:36:12.022011 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6562 11:36:12.025217 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6563 11:36:12.028734 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6564 11:36:12.031927 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6565 11:36:12.031988
6566 11:36:12.032040
6567 11:36:12.032089 ==
6568 11:36:12.035074 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 11:36:12.038738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 11:36:12.038816 ==
6571 11:36:12.038874
6572 11:36:12.038927
6573 11:36:12.042255 TX Vref Scan disable
6574 11:36:12.042330 == TX Byte 0 ==
6575 11:36:12.048522 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6576 11:36:12.051675 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6577 11:36:12.051750 == TX Byte 1 ==
6578 11:36:12.058237 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6579 11:36:12.061666 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6580 11:36:12.061741 ==
6581 11:36:12.065367 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 11:36:12.068518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 11:36:12.068594 ==
6584 11:36:12.068652
6585 11:36:12.068705
6586 11:36:12.071511 TX Vref Scan disable
6587 11:36:12.075012 == TX Byte 0 ==
6588 11:36:12.078045 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6589 11:36:12.081308 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6590 11:36:12.081383 == TX Byte 1 ==
6591 11:36:12.088690 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6592 11:36:12.091699 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6593 11:36:12.091774
6594 11:36:12.091831 [DATLAT]
6595 11:36:12.094987 Freq=400, CH0 RK1
6596 11:36:12.095062
6597 11:36:12.095119 DATLAT Default: 0xe
6598 11:36:12.098087 0, 0xFFFF, sum = 0
6599 11:36:12.098200 1, 0xFFFF, sum = 0
6600 11:36:12.101898 2, 0xFFFF, sum = 0
6601 11:36:12.101973 3, 0xFFFF, sum = 0
6602 11:36:12.104872 4, 0xFFFF, sum = 0
6603 11:36:12.107856 5, 0xFFFF, sum = 0
6604 11:36:12.107932 6, 0xFFFF, sum = 0
6605 11:36:12.111287 7, 0xFFFF, sum = 0
6606 11:36:12.111363 8, 0xFFFF, sum = 0
6607 11:36:12.114975 9, 0xFFFF, sum = 0
6608 11:36:12.115051 10, 0xFFFF, sum = 0
6609 11:36:12.118061 11, 0xFFFF, sum = 0
6610 11:36:12.118144 12, 0xFFFF, sum = 0
6611 11:36:12.121352 13, 0x0, sum = 1
6612 11:36:12.121428 14, 0x0, sum = 2
6613 11:36:12.124348 15, 0x0, sum = 3
6614 11:36:12.124424 16, 0x0, sum = 4
6615 11:36:12.127701 best_step = 14
6616 11:36:12.127776
6617 11:36:12.127833 ==
6618 11:36:12.131351 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 11:36:12.134665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 11:36:12.134740 ==
6621 11:36:12.134799 RX Vref Scan: 0
6622 11:36:12.137925
6623 11:36:12.138000 RX Vref 0 -> 0, step: 1
6624 11:36:12.138058
6625 11:36:12.141296 RX Delay -359 -> 252, step: 8
6626 11:36:12.148363 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6627 11:36:12.151996 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6628 11:36:12.154917 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6629 11:36:12.158351 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6630 11:36:12.165085 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6631 11:36:12.168278 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6632 11:36:12.171495 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6633 11:36:12.178308 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6634 11:36:12.181789 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6635 11:36:12.184931 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6636 11:36:12.187904 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6637 11:36:12.194778 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6638 11:36:12.197784 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6639 11:36:12.201254 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6640 11:36:12.204426 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6641 11:36:12.211082 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6642 11:36:12.211157 ==
6643 11:36:12.214588 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 11:36:12.218140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 11:36:12.218216 ==
6646 11:36:12.218275 DQS Delay:
6647 11:36:12.221420 DQS0 = 60, DQS1 = 72
6648 11:36:12.221495 DQM Delay:
6649 11:36:12.224545 DQM0 = 11, DQM1 = 17
6650 11:36:12.224619 DQ Delay:
6651 11:36:12.228354 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6652 11:36:12.231223 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6653 11:36:12.234711 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6654 11:36:12.237700 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6655 11:36:12.237775
6656 11:36:12.237832
6657 11:36:12.244310 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6658 11:36:12.247901 CH0 RK1: MR19=C0C, MR18=CD84
6659 11:36:12.254156 CH0_RK1: MR19=0xC0C, MR18=0xCD84, DQSOSC=384, MR23=63, INC=400, DEC=267
6660 11:36:12.257456 [RxdqsGatingPostProcess] freq 400
6661 11:36:12.263920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6662 11:36:12.267701 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 11:36:12.270704 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 11:36:12.274031 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 11:36:12.277142 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 11:36:12.277218 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 11:36:12.280588 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 11:36:12.283801 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 11:36:12.287182 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 11:36:12.290655 Pre-setting of DQS Precalculation
6671 11:36:12.297217 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6672 11:36:12.297294 ==
6673 11:36:12.300931 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 11:36:12.303843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 11:36:12.303919 ==
6676 11:36:12.310419 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 11:36:12.313819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6678 11:36:12.317089 [CA 0] Center 36 (8~64) winsize 57
6679 11:36:12.320541 [CA 1] Center 36 (8~64) winsize 57
6680 11:36:12.324077 [CA 2] Center 36 (8~64) winsize 57
6681 11:36:12.327396 [CA 3] Center 36 (8~64) winsize 57
6682 11:36:12.330904 [CA 4] Center 36 (8~64) winsize 57
6683 11:36:12.333857 [CA 5] Center 36 (8~64) winsize 57
6684 11:36:12.333932
6685 11:36:12.337032 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6686 11:36:12.337107
6687 11:36:12.340744 [CATrainingPosCal] consider 1 rank data
6688 11:36:12.344092 u2DelayCellTimex100 = 270/100 ps
6689 11:36:12.347611 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:36:12.350468 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:36:12.357458 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:36:12.360227 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:36:12.363682 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:36:12.367255 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:36:12.367330
6696 11:36:12.370088 CA PerBit enable=1, Macro0, CA PI delay=36
6697 11:36:12.370197
6698 11:36:12.373678 [CBTSetCACLKResult] CA Dly = 36
6699 11:36:12.373752 CS Dly: 1 (0~32)
6700 11:36:12.376880 ==
6701 11:36:12.376956 Dram Type= 6, Freq= 0, CH_1, rank 1
6702 11:36:12.383375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:36:12.383451 ==
6704 11:36:12.387049 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 11:36:12.393618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6706 11:36:12.397370 [CA 0] Center 36 (8~64) winsize 57
6707 11:36:12.400097 [CA 1] Center 36 (8~64) winsize 57
6708 11:36:12.403596 [CA 2] Center 36 (8~64) winsize 57
6709 11:36:12.406885 [CA 3] Center 36 (8~64) winsize 57
6710 11:36:12.410596 [CA 4] Center 36 (8~64) winsize 57
6711 11:36:12.413731 [CA 5] Center 36 (8~64) winsize 57
6712 11:36:12.413819
6713 11:36:12.416814 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6714 11:36:12.416879
6715 11:36:12.419962 [CATrainingPosCal] consider 2 rank data
6716 11:36:12.423369 u2DelayCellTimex100 = 270/100 ps
6717 11:36:12.426923 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:36:12.429817 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:36:12.433233 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:36:12.436872 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:36:12.443288 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:36:12.446916 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 11:36:12.446984
6724 11:36:12.449615 CA PerBit enable=1, Macro0, CA PI delay=36
6725 11:36:12.449676
6726 11:36:12.452981 [CBTSetCACLKResult] CA Dly = 36
6727 11:36:12.453040 CS Dly: 1 (0~32)
6728 11:36:12.453094
6729 11:36:12.456381 ----->DramcWriteLeveling(PI) begin...
6730 11:36:12.456439 ==
6731 11:36:12.459517 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 11:36:12.466348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 11:36:12.466410 ==
6734 11:36:12.469786 Write leveling (Byte 0): 40 => 8
6735 11:36:12.469876 Write leveling (Byte 1): 40 => 8
6736 11:36:12.472667 DramcWriteLeveling(PI) end<-----
6737 11:36:12.472728
6738 11:36:12.476300 ==
6739 11:36:12.476363 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:36:12.482930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:36:12.482995 ==
6742 11:36:12.486244 [Gating] SW mode calibration
6743 11:36:12.492604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6744 11:36:12.496523 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6745 11:36:12.502789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 11:36:12.506032 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 11:36:12.509281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 11:36:12.516102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 11:36:12.519346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:36:12.522849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 11:36:12.529348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 11:36:12.532669 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 11:36:12.536108 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 11:36:12.539588 Total UI for P1: 0, mck2ui 16
6755 11:36:12.542618 best dqsien dly found for B0: ( 0, 14, 24)
6756 11:36:12.546026 Total UI for P1: 0, mck2ui 16
6757 11:36:12.549711 best dqsien dly found for B1: ( 0, 14, 24)
6758 11:36:12.552498 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6759 11:36:12.556184 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6760 11:36:12.556259
6761 11:36:12.559651 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 11:36:12.566491 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 11:36:12.566566 [Gating] SW calibration Done
6764 11:36:12.566626 ==
6765 11:36:12.569020 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:36:12.575817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:36:12.575893 ==
6768 11:36:12.575952 RX Vref Scan: 0
6769 11:36:12.576006
6770 11:36:12.579401 RX Vref 0 -> 0, step: 1
6771 11:36:12.579476
6772 11:36:12.582511 RX Delay -410 -> 252, step: 16
6773 11:36:12.585954 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6774 11:36:12.589657 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6775 11:36:12.596296 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6776 11:36:12.599491 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6777 11:36:12.602965 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6778 11:36:12.605654 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6779 11:36:12.612579 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6780 11:36:12.615583 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6781 11:36:12.619492 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6782 11:36:12.622301 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6783 11:36:12.628958 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6784 11:36:12.632067 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6785 11:36:12.635847 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6786 11:36:12.642591 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6787 11:36:12.645248 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6788 11:36:12.648826 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6789 11:36:12.648902 ==
6790 11:36:12.651827 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:36:12.655148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:36:12.655224 ==
6793 11:36:12.658841 DQS Delay:
6794 11:36:12.658915 DQS0 = 51, DQS1 = 67
6795 11:36:12.661811 DQM Delay:
6796 11:36:12.661887 DQM0 = 12, DQM1 = 17
6797 11:36:12.665609 DQ Delay:
6798 11:36:12.665684 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6799 11:36:12.668522 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6800 11:36:12.672017 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6801 11:36:12.675107 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6802 11:36:12.675182
6803 11:36:12.675240
6804 11:36:12.678402 ==
6805 11:36:12.678478 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 11:36:12.685167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 11:36:12.685243 ==
6808 11:36:12.685317
6809 11:36:12.685371
6810 11:36:12.688095 TX Vref Scan disable
6811 11:36:12.688170 == TX Byte 0 ==
6812 11:36:12.691516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 11:36:12.698253 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 11:36:12.698332 == TX Byte 1 ==
6815 11:36:12.701556 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 11:36:12.704942 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 11:36:12.708074 ==
6818 11:36:12.711371 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 11:36:12.714708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 11:36:12.714781 ==
6821 11:36:12.714837
6822 11:36:12.714889
6823 11:36:12.718428 TX Vref Scan disable
6824 11:36:12.718496 == TX Byte 0 ==
6825 11:36:12.720972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 11:36:12.727671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 11:36:12.727743 == TX Byte 1 ==
6828 11:36:12.731031 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 11:36:12.737642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 11:36:12.737713
6831 11:36:12.737768 [DATLAT]
6832 11:36:12.737821 Freq=400, CH1 RK0
6833 11:36:12.737872
6834 11:36:12.741082 DATLAT Default: 0xf
6835 11:36:12.744303 0, 0xFFFF, sum = 0
6836 11:36:12.744366 1, 0xFFFF, sum = 0
6837 11:36:12.747873 2, 0xFFFF, sum = 0
6838 11:36:12.747938 3, 0xFFFF, sum = 0
6839 11:36:12.750819 4, 0xFFFF, sum = 0
6840 11:36:12.750887 5, 0xFFFF, sum = 0
6841 11:36:12.754085 6, 0xFFFF, sum = 0
6842 11:36:12.754195 7, 0xFFFF, sum = 0
6843 11:36:12.757541 8, 0xFFFF, sum = 0
6844 11:36:12.757637 9, 0xFFFF, sum = 0
6845 11:36:12.761265 10, 0xFFFF, sum = 0
6846 11:36:12.761328 11, 0xFFFF, sum = 0
6847 11:36:12.764025 12, 0xFFFF, sum = 0
6848 11:36:12.764086 13, 0x0, sum = 1
6849 11:36:12.767581 14, 0x0, sum = 2
6850 11:36:12.767646 15, 0x0, sum = 3
6851 11:36:12.770835 16, 0x0, sum = 4
6852 11:36:12.770894 best_step = 14
6853 11:36:12.770944
6854 11:36:12.770992 ==
6855 11:36:12.774650 Dram Type= 6, Freq= 0, CH_1, rank 0
6856 11:36:12.777849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 11:36:12.780875 ==
6858 11:36:12.780933 RX Vref Scan: 1
6859 11:36:12.780986
6860 11:36:12.783875 RX Vref 0 -> 0, step: 1
6861 11:36:12.783932
6862 11:36:12.787267 RX Delay -375 -> 252, step: 8
6863 11:36:12.787329
6864 11:36:12.790686 Set Vref, RX VrefLevel [Byte0]: 58
6865 11:36:12.794522 [Byte1]: 50
6866 11:36:12.794616
6867 11:36:12.797312 Final RX Vref Byte 0 = 58 to rank0
6868 11:36:12.800427 Final RX Vref Byte 1 = 50 to rank0
6869 11:36:12.804119 Final RX Vref Byte 0 = 58 to rank1
6870 11:36:12.807314 Final RX Vref Byte 1 = 50 to rank1==
6871 11:36:12.810625 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 11:36:12.813780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 11:36:12.817290 ==
6874 11:36:12.817355 DQS Delay:
6875 11:36:12.817408 DQS0 = 56, DQS1 = 68
6876 11:36:12.820328 DQM Delay:
6877 11:36:12.820450 DQM0 = 13, DQM1 = 14
6878 11:36:12.823781 DQ Delay:
6879 11:36:12.823841 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6880 11:36:12.827554 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6881 11:36:12.830202 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6882 11:36:12.833627 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6883 11:36:12.833695
6884 11:36:12.833751
6885 11:36:12.843481 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6886 11:36:12.846794 CH1 RK0: MR19=C0C, MR18=5B6D
6887 11:36:12.853464 CH1_RK0: MR19=0xC0C, MR18=0x5B6D, DQSOSC=396, MR23=63, INC=376, DEC=251
6888 11:36:12.853529 ==
6889 11:36:12.856539 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:36:12.860582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:36:12.860649 ==
6892 11:36:12.863231 [Gating] SW mode calibration
6893 11:36:12.870055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6894 11:36:12.876593 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6895 11:36:12.879649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 11:36:12.883063 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 11:36:12.889654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 11:36:12.893157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 11:36:12.896434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:36:12.903119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 11:36:12.906524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 11:36:12.909625 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 11:36:12.916817 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 11:36:12.916894 Total UI for P1: 0, mck2ui 16
6905 11:36:12.919801 best dqsien dly found for B0: ( 0, 14, 24)
6906 11:36:12.922719 Total UI for P1: 0, mck2ui 16
6907 11:36:12.926083 best dqsien dly found for B1: ( 0, 14, 24)
6908 11:36:12.932869 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6909 11:36:12.936116 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6910 11:36:12.936191
6911 11:36:12.939607 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 11:36:12.942863 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 11:36:12.945799 [Gating] SW calibration Done
6914 11:36:12.945874 ==
6915 11:36:12.949798 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:36:12.952742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:36:12.952818 ==
6918 11:36:12.955722 RX Vref Scan: 0
6919 11:36:12.955797
6920 11:36:12.955855 RX Vref 0 -> 0, step: 1
6921 11:36:12.955909
6922 11:36:12.959201 RX Delay -410 -> 252, step: 16
6923 11:36:12.965740 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6924 11:36:12.969224 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6925 11:36:12.972750 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6926 11:36:12.975856 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6927 11:36:12.982317 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6928 11:36:12.985540 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6929 11:36:12.988911 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6930 11:36:12.992279 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6931 11:36:12.998860 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6932 11:36:13.002043 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6933 11:36:13.005292 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6934 11:36:13.008771 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6935 11:36:13.015380 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6936 11:36:13.018950 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6937 11:36:13.021695 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6938 11:36:13.025163 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6939 11:36:13.028918 ==
6940 11:36:13.031928 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:36:13.035007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:36:13.035084 ==
6943 11:36:13.035142 DQS Delay:
6944 11:36:13.038625 DQS0 = 59, DQS1 = 59
6945 11:36:13.038704 DQM Delay:
6946 11:36:13.041733 DQM0 = 19, DQM1 = 13
6947 11:36:13.041808 DQ Delay:
6948 11:36:13.045213 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6949 11:36:13.048456 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6950 11:36:13.051532 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6951 11:36:13.055342 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6952 11:36:13.055416
6953 11:36:13.055475
6954 11:36:13.055528 ==
6955 11:36:13.058018 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 11:36:13.061569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 11:36:13.061644 ==
6958 11:36:13.061702
6959 11:36:13.061756
6960 11:36:13.065088 TX Vref Scan disable
6961 11:36:13.068246 == TX Byte 0 ==
6962 11:36:13.071850 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6963 11:36:13.074893 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6964 11:36:13.074957 == TX Byte 1 ==
6965 11:36:13.081286 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6966 11:36:13.084788 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6967 11:36:13.084851 ==
6968 11:36:13.087889 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 11:36:13.091129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 11:36:13.091193 ==
6971 11:36:13.094377
6972 11:36:13.094439
6973 11:36:13.094491 TX Vref Scan disable
6974 11:36:13.097695 == TX Byte 0 ==
6975 11:36:13.100810 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6976 11:36:13.104495 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6977 11:36:13.107805 == TX Byte 1 ==
6978 11:36:13.111129 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6979 11:36:13.114512 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6980 11:36:13.114577
6981 11:36:13.114632 [DATLAT]
6982 11:36:13.117212 Freq=400, CH1 RK1
6983 11:36:13.117270
6984 11:36:13.120851 DATLAT Default: 0xe
6985 11:36:13.120911 0, 0xFFFF, sum = 0
6986 11:36:13.123773 1, 0xFFFF, sum = 0
6987 11:36:13.123833 2, 0xFFFF, sum = 0
6988 11:36:13.127662 3, 0xFFFF, sum = 0
6989 11:36:13.127727 4, 0xFFFF, sum = 0
6990 11:36:13.130656 5, 0xFFFF, sum = 0
6991 11:36:13.130717 6, 0xFFFF, sum = 0
6992 11:36:13.134013 7, 0xFFFF, sum = 0
6993 11:36:13.134077 8, 0xFFFF, sum = 0
6994 11:36:13.136993 9, 0xFFFF, sum = 0
6995 11:36:13.137055 10, 0xFFFF, sum = 0
6996 11:36:13.140273 11, 0xFFFF, sum = 0
6997 11:36:13.140331 12, 0xFFFF, sum = 0
6998 11:36:13.143819 13, 0x0, sum = 1
6999 11:36:13.143877 14, 0x0, sum = 2
7000 11:36:13.147086 15, 0x0, sum = 3
7001 11:36:13.147152 16, 0x0, sum = 4
7002 11:36:13.150218 best_step = 14
7003 11:36:13.150275
7004 11:36:13.150324 ==
7005 11:36:13.154116 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 11:36:13.156968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 11:36:13.157026 ==
7008 11:36:13.160314 RX Vref Scan: 0
7009 11:36:13.160372
7010 11:36:13.160424 RX Vref 0 -> 0, step: 1
7011 11:36:13.160472
7012 11:36:13.163638 RX Delay -359 -> 252, step: 8
7013 11:36:13.171389 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7014 11:36:13.174975 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7015 11:36:13.178300 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7016 11:36:13.184805 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7017 11:36:13.187941 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7018 11:36:13.191673 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7019 11:36:13.195026 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7020 11:36:13.201381 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7021 11:36:13.205201 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7022 11:36:13.208160 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7023 11:36:13.211421 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7024 11:36:13.218209 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7025 11:36:13.221405 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7026 11:36:13.224814 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7027 11:36:13.227731 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7028 11:36:13.234928 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7029 11:36:13.235039 ==
7030 11:36:13.237998 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 11:36:13.241217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 11:36:13.241342 ==
7033 11:36:13.241437 DQS Delay:
7034 11:36:13.244375 DQS0 = 60, DQS1 = 64
7035 11:36:13.244498 DQM Delay:
7036 11:36:13.248058 DQM0 = 13, DQM1 = 11
7037 11:36:13.248182 DQ Delay:
7038 11:36:13.251527 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7039 11:36:13.254750 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7040 11:36:13.257619 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7041 11:36:13.260924 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7042 11:36:13.261113
7043 11:36:13.261271
7044 11:36:13.267918 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ead, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
7045 11:36:13.271533 CH1 RK1: MR19=C0C, MR18=7EAD
7046 11:36:13.277849 CH1_RK1: MR19=0xC0C, MR18=0x7EAD, DQSOSC=388, MR23=63, INC=392, DEC=261
7047 11:36:13.281125 [RxdqsGatingPostProcess] freq 400
7048 11:36:13.287627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7049 11:36:13.291305 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 11:36:13.294473 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 11:36:13.298072 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 11:36:13.298735 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 11:36:13.301448 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 11:36:13.304838 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 11:36:13.308031 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 11:36:13.311799 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 11:36:13.314798 Pre-setting of DQS Precalculation
7058 11:36:13.321234 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7059 11:36:13.327986 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7060 11:36:13.334362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7061 11:36:13.334755
7062 11:36:13.335055
7063 11:36:13.338090 [Calibration Summary] 800 Mbps
7064 11:36:13.338619 CH 0, Rank 0
7065 11:36:13.341049 SW Impedance : PASS
7066 11:36:13.344926 DUTY Scan : NO K
7067 11:36:13.345405 ZQ Calibration : PASS
7068 11:36:13.347880 Jitter Meter : NO K
7069 11:36:13.351096 CBT Training : PASS
7070 11:36:13.351524 Write leveling : PASS
7071 11:36:13.354181 RX DQS gating : PASS
7072 11:36:13.357388 RX DQ/DQS(RDDQC) : PASS
7073 11:36:13.357576 TX DQ/DQS : PASS
7074 11:36:13.360663 RX DATLAT : PASS
7075 11:36:13.360739 RX DQ/DQS(Engine): PASS
7076 11:36:13.363864 TX OE : NO K
7077 11:36:13.363940 All Pass.
7078 11:36:13.363998
7079 11:36:13.367417 CH 0, Rank 1
7080 11:36:13.367492 SW Impedance : PASS
7081 11:36:13.370717 DUTY Scan : NO K
7082 11:36:13.373956 ZQ Calibration : PASS
7083 11:36:13.374032 Jitter Meter : NO K
7084 11:36:13.377303 CBT Training : PASS
7085 11:36:13.380293 Write leveling : NO K
7086 11:36:13.380368 RX DQS gating : PASS
7087 11:36:13.383765 RX DQ/DQS(RDDQC) : PASS
7088 11:36:13.387060 TX DQ/DQS : PASS
7089 11:36:13.387136 RX DATLAT : PASS
7090 11:36:13.390761 RX DQ/DQS(Engine): PASS
7091 11:36:13.393473 TX OE : NO K
7092 11:36:13.393548 All Pass.
7093 11:36:13.393606
7094 11:36:13.393660 CH 1, Rank 0
7095 11:36:13.397141 SW Impedance : PASS
7096 11:36:13.400355 DUTY Scan : NO K
7097 11:36:13.400431 ZQ Calibration : PASS
7098 11:36:13.403534 Jitter Meter : NO K
7099 11:36:13.406617 CBT Training : PASS
7100 11:36:13.406693 Write leveling : PASS
7101 11:36:13.410931 RX DQS gating : PASS
7102 11:36:13.414171 RX DQ/DQS(RDDQC) : PASS
7103 11:36:13.414747 TX DQ/DQS : PASS
7104 11:36:13.417426 RX DATLAT : PASS
7105 11:36:13.420972 RX DQ/DQS(Engine): PASS
7106 11:36:13.421403 TX OE : NO K
7107 11:36:13.421724 All Pass.
7108 11:36:13.424023
7109 11:36:13.424406 CH 1, Rank 1
7110 11:36:13.427426 SW Impedance : PASS
7111 11:36:13.427841 DUTY Scan : NO K
7112 11:36:13.430869 ZQ Calibration : PASS
7113 11:36:13.431280 Jitter Meter : NO K
7114 11:36:13.434092 CBT Training : PASS
7115 11:36:13.436985 Write leveling : NO K
7116 11:36:13.437572 RX DQS gating : PASS
7117 11:36:13.440415 RX DQ/DQS(RDDQC) : PASS
7118 11:36:13.443512 TX DQ/DQS : PASS
7119 11:36:13.443912 RX DATLAT : PASS
7120 11:36:13.446994 RX DQ/DQS(Engine): PASS
7121 11:36:13.450671 TX OE : NO K
7122 11:36:13.451052 All Pass.
7123 11:36:13.451350
7124 11:36:13.453299 DramC Write-DBI off
7125 11:36:13.453683 PER_BANK_REFRESH: Hybrid Mode
7126 11:36:13.456891 TX_TRACKING: ON
7127 11:36:13.463341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7128 11:36:13.469988 [FAST_K] Save calibration result to emmc
7129 11:36:13.473801 dramc_set_vcore_voltage set vcore to 725000
7130 11:36:13.474268 Read voltage for 1600, 0
7131 11:36:13.476622 Vio18 = 0
7132 11:36:13.476998 Vcore = 725000
7133 11:36:13.477287 Vdram = 0
7134 11:36:13.480101 Vddq = 0
7135 11:36:13.480591 Vmddr = 0
7136 11:36:13.483487 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7137 11:36:13.490271 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7138 11:36:13.493579 MEM_TYPE=3, freq_sel=13
7139 11:36:13.497056 sv_algorithm_assistance_LP4_3733
7140 11:36:13.499861 ============ PULL DRAM RESETB DOWN ============
7141 11:36:13.503025 ========== PULL DRAM RESETB DOWN end =========
7142 11:36:13.509004 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7143 11:36:13.512496 ===================================
7144 11:36:13.512564 LPDDR4 DRAM CONFIGURATION
7145 11:36:13.516401 ===================================
7146 11:36:13.519561 EX_ROW_EN[0] = 0x0
7147 11:36:13.519623 EX_ROW_EN[1] = 0x0
7148 11:36:13.522945 LP4Y_EN = 0x0
7149 11:36:13.525812 WORK_FSP = 0x1
7150 11:36:13.525896 WL = 0x5
7151 11:36:13.529455 RL = 0x5
7152 11:36:13.529602 BL = 0x2
7153 11:36:13.533168 RPST = 0x0
7154 11:36:13.533321 RD_PRE = 0x0
7155 11:36:13.536064 WR_PRE = 0x1
7156 11:36:13.536204 WR_PST = 0x1
7157 11:36:13.539220 DBI_WR = 0x0
7158 11:36:13.539373 DBI_RD = 0x0
7159 11:36:13.542484 OTF = 0x1
7160 11:36:13.546089 ===================================
7161 11:36:13.548975 ===================================
7162 11:36:13.549091 ANA top config
7163 11:36:13.552423 ===================================
7164 11:36:13.556215 DLL_ASYNC_EN = 0
7165 11:36:13.559410 ALL_SLAVE_EN = 0
7166 11:36:13.559771 NEW_RANK_MODE = 1
7167 11:36:13.562742 DLL_IDLE_MODE = 1
7168 11:36:13.566265 LP45_APHY_COMB_EN = 1
7169 11:36:13.569395 TX_ODT_DIS = 0
7170 11:36:13.572446 NEW_8X_MODE = 1
7171 11:36:13.575499 ===================================
7172 11:36:13.578947 ===================================
7173 11:36:13.579023 data_rate = 3200
7174 11:36:13.582079 CKR = 1
7175 11:36:13.585637 DQ_P2S_RATIO = 8
7176 11:36:13.588902 ===================================
7177 11:36:13.592179 CA_P2S_RATIO = 8
7178 11:36:13.595751 DQ_CA_OPEN = 0
7179 11:36:13.598959 DQ_SEMI_OPEN = 0
7180 11:36:13.599050 CA_SEMI_OPEN = 0
7181 11:36:13.602208 CA_FULL_RATE = 0
7182 11:36:13.605908 DQ_CKDIV4_EN = 0
7183 11:36:13.609095 CA_CKDIV4_EN = 0
7184 11:36:13.612735 CA_PREDIV_EN = 0
7185 11:36:13.616260 PH8_DLY = 12
7186 11:36:13.616609 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7187 11:36:13.619491 DQ_AAMCK_DIV = 4
7188 11:36:13.622428 CA_AAMCK_DIV = 4
7189 11:36:13.625891 CA_ADMCK_DIV = 4
7190 11:36:13.629143 DQ_TRACK_CA_EN = 0
7191 11:36:13.632447 CA_PICK = 1600
7192 11:36:13.636032 CA_MCKIO = 1600
7193 11:36:13.636505 MCKIO_SEMI = 0
7194 11:36:13.639317 PLL_FREQ = 3068
7195 11:36:13.642165 DQ_UI_PI_RATIO = 32
7196 11:36:13.645738 CA_UI_PI_RATIO = 0
7197 11:36:13.648708 ===================================
7198 11:36:13.652159 ===================================
7199 11:36:13.655851 memory_type:LPDDR4
7200 11:36:13.656272 GP_NUM : 10
7201 11:36:13.658844 SRAM_EN : 1
7202 11:36:13.662295 MD32_EN : 0
7203 11:36:13.665421 ===================================
7204 11:36:13.665826 [ANA_INIT] >>>>>>>>>>>>>>
7205 11:36:13.668813 <<<<<< [CONFIGURE PHASE]: ANA_TX
7206 11:36:13.672322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7207 11:36:13.675803 ===================================
7208 11:36:13.679135 data_rate = 3200,PCW = 0X7600
7209 11:36:13.682188 ===================================
7210 11:36:13.685414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7211 11:36:13.692293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 11:36:13.695213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 11:36:13.702189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7214 11:36:13.705147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7215 11:36:13.708534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7216 11:36:13.708919 [ANA_INIT] flow start
7217 11:36:13.711900 [ANA_INIT] PLL >>>>>>>>
7218 11:36:13.715041 [ANA_INIT] PLL <<<<<<<<
7219 11:36:13.718801 [ANA_INIT] MIDPI >>>>>>>>
7220 11:36:13.719186 [ANA_INIT] MIDPI <<<<<<<<
7221 11:36:13.722255 [ANA_INIT] DLL >>>>>>>>
7222 11:36:13.725791 [ANA_INIT] DLL <<<<<<<<
7223 11:36:13.726276 [ANA_INIT] flow end
7224 11:36:13.728587 ============ LP4 DIFF to SE enter ============
7225 11:36:13.735025 ============ LP4 DIFF to SE exit ============
7226 11:36:13.735457 [ANA_INIT] <<<<<<<<<<<<<
7227 11:36:13.738568 [Flow] Enable top DCM control >>>>>
7228 11:36:13.741812 [Flow] Enable top DCM control <<<<<
7229 11:36:13.745531 Enable DLL master slave shuffle
7230 11:36:13.752168 ==============================================================
7231 11:36:13.752553 Gating Mode config
7232 11:36:13.758339 ==============================================================
7233 11:36:13.761742 Config description:
7234 11:36:13.771476 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7235 11:36:13.778263 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7236 11:36:13.781545 SELPH_MODE 0: By rank 1: By Phase
7237 11:36:13.788219 ==============================================================
7238 11:36:13.791314 GAT_TRACK_EN = 1
7239 11:36:13.794689 RX_GATING_MODE = 2
7240 11:36:13.794758 RX_GATING_TRACK_MODE = 2
7241 11:36:13.797650 SELPH_MODE = 1
7242 11:36:13.800808 PICG_EARLY_EN = 1
7243 11:36:13.804309 VALID_LAT_VALUE = 1
7244 11:36:13.810985 ==============================================================
7245 11:36:13.814319 Enter into Gating configuration >>>>
7246 11:36:13.817442 Exit from Gating configuration <<<<
7247 11:36:13.820949 Enter into DVFS_PRE_config >>>>>
7248 11:36:13.831099 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7249 11:36:13.834007 Exit from DVFS_PRE_config <<<<<
7250 11:36:13.837716 Enter into PICG configuration >>>>
7251 11:36:13.840694 Exit from PICG configuration <<<<
7252 11:36:13.843961 [RX_INPUT] configuration >>>>>
7253 11:36:13.847643 [RX_INPUT] configuration <<<<<
7254 11:36:13.850508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7255 11:36:13.857651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7256 11:36:13.864191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 11:36:13.871012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 11:36:13.876970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 11:36:13.880246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 11:36:13.887300 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7261 11:36:13.889949 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7262 11:36:13.893333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7263 11:36:13.896894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7264 11:36:13.903623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7265 11:36:13.906734 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 11:36:13.910004 ===================================
7267 11:36:13.913165 LPDDR4 DRAM CONFIGURATION
7268 11:36:13.916770 ===================================
7269 11:36:13.916865 EX_ROW_EN[0] = 0x0
7270 11:36:13.919546 EX_ROW_EN[1] = 0x0
7271 11:36:13.919614 LP4Y_EN = 0x0
7272 11:36:13.923081 WORK_FSP = 0x1
7273 11:36:13.923156 WL = 0x5
7274 11:36:13.926505 RL = 0x5
7275 11:36:13.926572 BL = 0x2
7276 11:36:13.929934 RPST = 0x0
7277 11:36:13.933345 RD_PRE = 0x0
7278 11:36:13.933419 WR_PRE = 0x1
7279 11:36:13.936221 WR_PST = 0x1
7280 11:36:13.936299 DBI_WR = 0x0
7281 11:36:13.939436 DBI_RD = 0x0
7282 11:36:13.939544 OTF = 0x1
7283 11:36:13.943155 ===================================
7284 11:36:13.946176 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7285 11:36:13.952960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7286 11:36:13.956018 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7287 11:36:13.959416 ===================================
7288 11:36:13.963058 LPDDR4 DRAM CONFIGURATION
7289 11:36:13.965881 ===================================
7290 11:36:13.965956 EX_ROW_EN[0] = 0x10
7291 11:36:13.968989 EX_ROW_EN[1] = 0x0
7292 11:36:13.969064 LP4Y_EN = 0x0
7293 11:36:13.972391 WORK_FSP = 0x1
7294 11:36:13.972467 WL = 0x5
7295 11:36:13.976370 RL = 0x5
7296 11:36:13.976445 BL = 0x2
7297 11:36:13.979333 RPST = 0x0
7298 11:36:13.982569 RD_PRE = 0x0
7299 11:36:13.982645 WR_PRE = 0x1
7300 11:36:13.985813 WR_PST = 0x1
7301 11:36:13.985888 DBI_WR = 0x0
7302 11:36:13.989015 DBI_RD = 0x0
7303 11:36:13.989091 OTF = 0x1
7304 11:36:13.992189 ===================================
7305 11:36:13.999299 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7306 11:36:13.999375 ==
7307 11:36:14.002642 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 11:36:14.005327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 11:36:14.005409 ==
7310 11:36:14.008621 [Duty_Offset_Calibration]
7311 11:36:14.011939 B0:2 B1:0 CA:3
7312 11:36:14.012009
7313 11:36:14.015154 [DutyScan_Calibration_Flow] k_type=0
7314 11:36:14.023795
7315 11:36:14.023866 ==CLK 0==
7316 11:36:14.027110 Final CLK duty delay cell = 0
7317 11:36:14.030924 [0] MAX Duty = 5062%(X100), DQS PI = 20
7318 11:36:14.033742 [0] MIN Duty = 4875%(X100), DQS PI = 54
7319 11:36:14.037330 [0] AVG Duty = 4968%(X100)
7320 11:36:14.037406
7321 11:36:14.040354 CH0 CLK Duty spec in!! Max-Min= 187%
7322 11:36:14.043735 [DutyScan_Calibration_Flow] ====Done====
7323 11:36:14.043816
7324 11:36:14.047348 [DutyScan_Calibration_Flow] k_type=1
7325 11:36:14.063725
7326 11:36:14.063928 ==DQS 0 ==
7327 11:36:14.066801 Final DQS duty delay cell = 0
7328 11:36:14.070116 [0] MAX Duty = 5094%(X100), DQS PI = 14
7329 11:36:14.073591 [0] MIN Duty = 4875%(X100), DQS PI = 48
7330 11:36:14.077334 [0] AVG Duty = 4984%(X100)
7331 11:36:14.077495
7332 11:36:14.077617 ==DQS 1 ==
7333 11:36:14.080465 Final DQS duty delay cell = 0
7334 11:36:14.083623 [0] MAX Duty = 5156%(X100), DQS PI = 32
7335 11:36:14.087230 [0] MIN Duty = 5031%(X100), DQS PI = 10
7336 11:36:14.090401 [0] AVG Duty = 5093%(X100)
7337 11:36:14.090476
7338 11:36:14.093994 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7339 11:36:14.094093
7340 11:36:14.097168 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7341 11:36:14.100208 [DutyScan_Calibration_Flow] ====Done====
7342 11:36:14.100289
7343 11:36:14.104038 [DutyScan_Calibration_Flow] k_type=3
7344 11:36:14.121416
7345 11:36:14.121540 ==DQM 0 ==
7346 11:36:14.125309 Final DQM duty delay cell = 0
7347 11:36:14.128418 [0] MAX Duty = 5156%(X100), DQS PI = 32
7348 11:36:14.131823 [0] MIN Duty = 4844%(X100), DQS PI = 48
7349 11:36:14.135272 [0] AVG Duty = 5000%(X100)
7350 11:36:14.135449
7351 11:36:14.135593 ==DQM 1 ==
7352 11:36:14.138308 Final DQM duty delay cell = 4
7353 11:36:14.141680 [4] MAX Duty = 5187%(X100), DQS PI = 60
7354 11:36:14.145538 [4] MIN Duty = 5000%(X100), DQS PI = 14
7355 11:36:14.148136 [4] AVG Duty = 5093%(X100)
7356 11:36:14.148409
7357 11:36:14.151552 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7358 11:36:14.151992
7359 11:36:14.155315 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7360 11:36:14.158547 [DutyScan_Calibration_Flow] ====Done====
7361 11:36:14.158931
7362 11:36:14.161574 [DutyScan_Calibration_Flow] k_type=2
7363 11:36:14.178363
7364 11:36:14.178872 ==DQ 0 ==
7365 11:36:14.181662 Final DQ duty delay cell = -4
7366 11:36:14.184490 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7367 11:36:14.187814 [-4] MIN Duty = 4876%(X100), DQS PI = 2
7368 11:36:14.191447 [-4] AVG Duty = 4938%(X100)
7369 11:36:14.191522
7370 11:36:14.191580 ==DQ 1 ==
7371 11:36:14.194043 Final DQ duty delay cell = 0
7372 11:36:14.197777 [0] MAX Duty = 5156%(X100), DQS PI = 60
7373 11:36:14.201129 [0] MIN Duty = 5000%(X100), DQS PI = 14
7374 11:36:14.204266 [0] AVG Duty = 5078%(X100)
7375 11:36:14.204340
7376 11:36:14.207425 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7377 11:36:14.207499
7378 11:36:14.210681 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7379 11:36:14.214257 [DutyScan_Calibration_Flow] ====Done====
7380 11:36:14.214331 ==
7381 11:36:14.217750 Dram Type= 6, Freq= 0, CH_1, rank 0
7382 11:36:14.220641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7383 11:36:14.220727 ==
7384 11:36:14.223962 [Duty_Offset_Calibration]
7385 11:36:14.224086 B0:1 B1:-2 CA:1
7386 11:36:14.224157
7387 11:36:14.227239 [DutyScan_Calibration_Flow] k_type=0
7388 11:36:14.238291
7389 11:36:14.238465 ==CLK 0==
7390 11:36:14.241617 Final CLK duty delay cell = 0
7391 11:36:14.244800 [0] MAX Duty = 5062%(X100), DQS PI = 24
7392 11:36:14.248593 [0] MIN Duty = 4844%(X100), DQS PI = 2
7393 11:36:14.248746 [0] AVG Duty = 4953%(X100)
7394 11:36:14.251840
7395 11:36:14.254804 CH1 CLK Duty spec in!! Max-Min= 218%
7396 11:36:14.258320 [DutyScan_Calibration_Flow] ====Done====
7397 11:36:14.258503
7398 11:36:14.261628 [DutyScan_Calibration_Flow] k_type=1
7399 11:36:14.278357
7400 11:36:14.278777 ==DQS 0 ==
7401 11:36:14.281529 Final DQS duty delay cell = 0
7402 11:36:14.284782 [0] MAX Duty = 5187%(X100), DQS PI = 24
7403 11:36:14.287805 [0] MIN Duty = 5031%(X100), DQS PI = 52
7404 11:36:14.291333 [0] AVG Duty = 5109%(X100)
7405 11:36:14.291755
7406 11:36:14.292076 ==DQS 1 ==
7407 11:36:14.295030 Final DQS duty delay cell = 0
7408 11:36:14.297528 [0] MAX Duty = 5093%(X100), DQS PI = 0
7409 11:36:14.300966 [0] MIN Duty = 4875%(X100), DQS PI = 24
7410 11:36:14.304100 [0] AVG Duty = 4984%(X100)
7411 11:36:14.304174
7412 11:36:14.307648 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7413 11:36:14.307722
7414 11:36:14.311207 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7415 11:36:14.314230 [DutyScan_Calibration_Flow] ====Done====
7416 11:36:14.314304
7417 11:36:14.317428 [DutyScan_Calibration_Flow] k_type=3
7418 11:36:14.334516
7419 11:36:14.334589 ==DQM 0 ==
7420 11:36:14.337780 Final DQM duty delay cell = 0
7421 11:36:14.341110 [0] MAX Duty = 5031%(X100), DQS PI = 26
7422 11:36:14.344678 [0] MIN Duty = 4813%(X100), DQS PI = 56
7423 11:36:14.347747 [0] AVG Duty = 4922%(X100)
7424 11:36:14.347820
7425 11:36:14.347877 ==DQM 1 ==
7426 11:36:14.351580 Final DQM duty delay cell = 0
7427 11:36:14.354383 [0] MAX Duty = 5094%(X100), DQS PI = 36
7428 11:36:14.357967 [0] MIN Duty = 4875%(X100), DQS PI = 26
7429 11:36:14.361050 [0] AVG Duty = 4984%(X100)
7430 11:36:14.361123
7431 11:36:14.364290 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7432 11:36:14.364363
7433 11:36:14.368183 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7434 11:36:14.370767 [DutyScan_Calibration_Flow] ====Done====
7435 11:36:14.370847
7436 11:36:14.374286 [DutyScan_Calibration_Flow] k_type=2
7437 11:36:14.391424
7438 11:36:14.391501 ==DQ 0 ==
7439 11:36:14.394653 Final DQ duty delay cell = 0
7440 11:36:14.398296 [0] MAX Duty = 5093%(X100), DQS PI = 22
7441 11:36:14.401772 [0] MIN Duty = 4907%(X100), DQS PI = 0
7442 11:36:14.401845 [0] AVG Duty = 5000%(X100)
7443 11:36:14.401902
7444 11:36:14.404791 ==DQ 1 ==
7445 11:36:14.407744 Final DQ duty delay cell = 0
7446 11:36:14.411568 [0] MAX Duty = 5125%(X100), DQS PI = 34
7447 11:36:14.414469 [0] MIN Duty = 4969%(X100), DQS PI = 24
7448 11:36:14.414553 [0] AVG Duty = 5047%(X100)
7449 11:36:14.414612
7450 11:36:14.417707 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7451 11:36:14.421012
7452 11:36:14.424640 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7453 11:36:14.427986 [DutyScan_Calibration_Flow] ====Done====
7454 11:36:14.431773 nWR fixed to 30
7455 11:36:14.431858 [ModeRegInit_LP4] CH0 RK0
7456 11:36:14.434533 [ModeRegInit_LP4] CH0 RK1
7457 11:36:14.437809 [ModeRegInit_LP4] CH1 RK0
7458 11:36:14.440669 [ModeRegInit_LP4] CH1 RK1
7459 11:36:14.440744 match AC timing 5
7460 11:36:14.447967 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7461 11:36:14.451185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7462 11:36:14.454226 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7463 11:36:14.460720 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7464 11:36:14.464200 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7465 11:36:14.464275 [MiockJmeterHQA]
7466 11:36:14.464333
7467 11:36:14.467721 [DramcMiockJmeter] u1RxGatingPI = 0
7468 11:36:14.470929 0 : 4255, 4030
7469 11:36:14.471016 4 : 4255, 4029
7470 11:36:14.474247 8 : 4255, 4030
7471 11:36:14.474334 12 : 4257, 4031
7472 11:36:14.474402 16 : 4368, 4140
7473 11:36:14.477456 20 : 4258, 4029
7474 11:36:14.477550 24 : 4257, 4029
7475 11:36:14.480732 28 : 4258, 4029
7476 11:36:14.480835 32 : 4367, 4142
7477 11:36:14.483894 36 : 4257, 4029
7478 11:36:14.483997 40 : 4255, 4029
7479 11:36:14.487403 44 : 4257, 4029
7480 11:36:14.487515 48 : 4255, 4030
7481 11:36:14.487601 52 : 4260, 4032
7482 11:36:14.490455 56 : 4258, 4029
7483 11:36:14.490530 60 : 4253, 4029
7484 11:36:14.493569 64 : 4368, 4142
7485 11:36:14.493680 68 : 4253, 4029
7486 11:36:14.496958 72 : 4250, 4027
7487 11:36:14.497033 76 : 4366, 4140
7488 11:36:14.501160 80 : 4252, 4029
7489 11:36:14.501235 84 : 4363, 4140
7490 11:36:14.501294 88 : 4252, 4029
7491 11:36:14.503466 92 : 4363, 4140
7492 11:36:14.503542 96 : 4255, 4029
7493 11:36:14.507124 100 : 4250, 4026
7494 11:36:14.507199 104 : 4253, 3642
7495 11:36:14.510955 108 : 4367, 1
7496 11:36:14.511030 112 : 4363, 0
7497 11:36:14.511089 116 : 4255, 0
7498 11:36:14.513698 120 : 4366, 0
7499 11:36:14.513774 124 : 4363, 0
7500 11:36:14.516816 128 : 4366, 0
7501 11:36:14.516891 132 : 4255, 0
7502 11:36:14.516949 136 : 4255, 0
7503 11:36:14.520305 140 : 4253, 0
7504 11:36:14.520380 144 : 4255, 0
7505 11:36:14.523477 148 : 4257, 0
7506 11:36:14.523553 152 : 4253, 0
7507 11:36:14.523611 156 : 4252, 0
7508 11:36:14.527096 160 : 4368, 0
7509 11:36:14.527171 164 : 4253, 0
7510 11:36:14.530029 168 : 4255, 0
7511 11:36:14.530111 172 : 4368, 0
7512 11:36:14.530170 176 : 4252, 0
7513 11:36:14.533336 180 : 4366, 0
7514 11:36:14.533412 184 : 4255, 0
7515 11:36:14.536807 188 : 4253, 0
7516 11:36:14.536882 192 : 4253, 0
7517 11:36:14.536940 196 : 4252, 0
7518 11:36:14.540290 200 : 4257, 0
7519 11:36:14.540365 204 : 4253, 0
7520 11:36:14.540424 208 : 4252, 0
7521 11:36:14.543579 212 : 4257, 0
7522 11:36:14.543655 216 : 4363, 0
7523 11:36:14.546909 220 : 4253, 0
7524 11:36:14.546985 224 : 4363, 0
7525 11:36:14.547044 228 : 4255, 0
7526 11:36:14.549871 232 : 4253, 0
7527 11:36:14.549946 236 : 4368, 1032
7528 11:36:14.553620 240 : 4252, 4029
7529 11:36:14.553761 244 : 4253, 4029
7530 11:36:14.557206 248 : 4257, 4032
7531 11:36:14.557320 252 : 4253, 4029
7532 11:36:14.560074 256 : 4365, 4140
7533 11:36:14.560161 260 : 4364, 4140
7534 11:36:14.563029 264 : 4253, 4029
7535 11:36:14.563105 268 : 4365, 4140
7536 11:36:14.566410 272 : 4255, 4029
7537 11:36:14.566486 276 : 4250, 4027
7538 11:36:14.566545 280 : 4255, 4029
7539 11:36:14.570201 284 : 4257, 4032
7540 11:36:14.570278 288 : 4253, 4029
7541 11:36:14.573048 292 : 4252, 4029
7542 11:36:14.573124 296 : 4253, 4029
7543 11:36:14.576532 300 : 4252, 4029
7544 11:36:14.576609 304 : 4368, 4142
7545 11:36:14.579641 308 : 4255, 4029
7546 11:36:14.579717 312 : 4252, 4029
7547 11:36:14.583034 316 : 4365, 4140
7548 11:36:14.583116 320 : 4363, 4140
7549 11:36:14.586715 324 : 4255, 4029
7550 11:36:14.586864 328 : 4252, 4029
7551 11:36:14.589671 332 : 4363, 4140
7552 11:36:14.589797 336 : 4252, 4029
7553 11:36:14.589872 340 : 4254, 4029
7554 11:36:14.592958 344 : 4365, 4139
7555 11:36:14.593063 348 : 4253, 4029
7556 11:36:14.596328 352 : 4253, 4022
7557 11:36:14.596431 356 : 4257, 2913
7558 11:36:14.599514 360 : 4255, 1
7559 11:36:14.599618
7560 11:36:14.599697 MIOCK jitter meter ch=0
7561 11:36:14.602695
7562 11:36:14.602807 1T = (360-108) = 252 dly cells
7563 11:36:14.609346 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7564 11:36:14.609471 ==
7565 11:36:14.612843 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 11:36:14.616033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 11:36:14.616191 ==
7568 11:36:14.622882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 11:36:14.626042 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 11:36:14.633067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 11:36:14.636133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 11:36:14.646268 [CA 0] Center 44 (14~75) winsize 62
7573 11:36:14.649954 [CA 1] Center 43 (13~74) winsize 62
7574 11:36:14.653076 [CA 2] Center 40 (11~69) winsize 59
7575 11:36:14.656376 [CA 3] Center 39 (10~69) winsize 60
7576 11:36:14.660042 [CA 4] Center 37 (8~67) winsize 60
7577 11:36:14.663408 [CA 5] Center 37 (8~66) winsize 59
7578 11:36:14.663483
7579 11:36:14.666228 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7580 11:36:14.666303
7581 11:36:14.669316 [CATrainingPosCal] consider 1 rank data
7582 11:36:14.672948 u2DelayCellTimex100 = 258/100 ps
7583 11:36:14.679407 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7584 11:36:14.682699 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7585 11:36:14.686490 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7586 11:36:14.689329 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7587 11:36:14.692808 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7588 11:36:14.696154 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7589 11:36:14.696230
7590 11:36:14.699571 CA PerBit enable=1, Macro0, CA PI delay=37
7591 11:36:14.699646
7592 11:36:14.702883 [CBTSetCACLKResult] CA Dly = 37
7593 11:36:14.706437 CS Dly: 11 (0~42)
7594 11:36:14.709298 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 11:36:14.712329 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 11:36:14.712404 ==
7597 11:36:14.716167 Dram Type= 6, Freq= 0, CH_0, rank 1
7598 11:36:14.722354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 11:36:14.722436 ==
7600 11:36:14.725749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7601 11:36:14.732478 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7602 11:36:14.736036 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7603 11:36:14.742146 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7604 11:36:14.750358 [CA 0] Center 44 (14~75) winsize 62
7605 11:36:14.753320 [CA 1] Center 44 (13~75) winsize 63
7606 11:36:14.756547 [CA 2] Center 39 (10~69) winsize 60
7607 11:36:14.760038 [CA 3] Center 39 (10~69) winsize 60
7608 11:36:14.763474 [CA 4] Center 37 (8~67) winsize 60
7609 11:36:14.766681 [CA 5] Center 37 (7~67) winsize 61
7610 11:36:14.766749
7611 11:36:14.770084 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7612 11:36:14.770162
7613 11:36:14.777046 [CATrainingPosCal] consider 2 rank data
7614 11:36:14.777117 u2DelayCellTimex100 = 258/100 ps
7615 11:36:14.783247 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7616 11:36:14.786376 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7617 11:36:14.789882 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7618 11:36:14.792895 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7619 11:36:14.796381 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7620 11:36:14.799884 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7621 11:36:14.799951
7622 11:36:14.802962 CA PerBit enable=1, Macro0, CA PI delay=37
7623 11:36:14.803038
7624 11:36:14.806938 [CBTSetCACLKResult] CA Dly = 37
7625 11:36:14.809613 CS Dly: 11 (0~43)
7626 11:36:14.812976 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7627 11:36:14.816949 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7628 11:36:14.817041
7629 11:36:14.819448 ----->DramcWriteLeveling(PI) begin...
7630 11:36:14.819544 ==
7631 11:36:14.823385 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 11:36:14.830027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 11:36:14.830126 ==
7634 11:36:14.832689 Write leveling (Byte 0): 36 => 36
7635 11:36:14.836563 Write leveling (Byte 1): 28 => 28
7636 11:36:14.836654 DramcWriteLeveling(PI) end<-----
7637 11:36:14.839287
7638 11:36:14.839352 ==
7639 11:36:14.843152 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 11:36:14.845971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 11:36:14.846060 ==
7642 11:36:14.849620 [Gating] SW mode calibration
7643 11:36:14.856363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7644 11:36:14.859968 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7645 11:36:14.866011 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:36:14.869562 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:36:14.873001 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:36:14.879782 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 11:36:14.883095 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7650 11:36:14.885988 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7651 11:36:14.892670 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7652 11:36:14.896510 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 11:36:14.899259 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 11:36:14.905708 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 11:36:14.909270 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 11:36:14.912568 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7657 11:36:14.919476 1 5 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7658 11:36:14.922543 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7659 11:36:14.925698 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7660 11:36:14.932611 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 11:36:14.935756 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 11:36:14.939039 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 11:36:14.945873 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 11:36:14.948825 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7665 11:36:14.952112 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7666 11:36:14.958643 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7667 11:36:14.962333 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7668 11:36:14.965169 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 11:36:14.972188 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 11:36:14.975193 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 11:36:14.978699 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 11:36:14.984948 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 11:36:14.988712 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7674 11:36:14.992059 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7675 11:36:14.999454 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7676 11:36:15.001473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:36:15.004886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:36:15.011554 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:36:15.014974 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:36:15.017975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:36:15.024502 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 11:36:15.028252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 11:36:15.031640 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 11:36:15.037687 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 11:36:15.041414 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 11:36:15.044493 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:36:15.051107 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:36:15.054222 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:36:15.057505 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7690 11:36:15.064478 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7691 11:36:15.067637 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 11:36:15.071519 Total UI for P1: 0, mck2ui 16
7693 11:36:15.074385 best dqsien dly found for B0: ( 1, 9, 18)
7694 11:36:15.077383 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 11:36:15.081273 Total UI for P1: 0, mck2ui 16
7696 11:36:15.084146 best dqsien dly found for B1: ( 1, 9, 24)
7697 11:36:15.087262 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7698 11:36:15.090609 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7699 11:36:15.090695
7700 11:36:15.097652 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7701 11:36:15.101051 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7702 11:36:15.101153 [Gating] SW calibration Done
7703 11:36:15.104400 ==
7704 11:36:15.107417 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 11:36:15.110942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 11:36:15.111017 ==
7707 11:36:15.111076 RX Vref Scan: 0
7708 11:36:15.111133
7709 11:36:15.114032 RX Vref 0 -> 0, step: 1
7710 11:36:15.114158
7711 11:36:15.117485 RX Delay 0 -> 252, step: 8
7712 11:36:15.121051 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7713 11:36:15.124157 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7714 11:36:15.127579 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7715 11:36:15.134019 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7716 11:36:15.137156 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7717 11:36:15.140926 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7718 11:36:15.144148 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7719 11:36:15.147732 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7720 11:36:15.154054 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7721 11:36:15.156999 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7722 11:36:15.160684 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7723 11:36:15.164175 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7724 11:36:15.170402 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7725 11:36:15.173837 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7726 11:36:15.176878 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7727 11:36:15.180512 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7728 11:36:15.181189 ==
7729 11:36:15.183499 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 11:36:15.190031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 11:36:15.190499 ==
7732 11:36:15.191090 DQS Delay:
7733 11:36:15.193934 DQS0 = 0, DQS1 = 0
7734 11:36:15.194446 DQM Delay:
7735 11:36:15.194752 DQM0 = 127, DQM1 = 124
7736 11:36:15.197191 DQ Delay:
7737 11:36:15.200168 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7738 11:36:15.203815 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7739 11:36:15.206999 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7740 11:36:15.210598 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7741 11:36:15.210991
7742 11:36:15.211295
7743 11:36:15.211566 ==
7744 11:36:15.213846 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 11:36:15.216727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 11:36:15.220165 ==
7747 11:36:15.220568
7748 11:36:15.221029
7749 11:36:15.221390 TX Vref Scan disable
7750 11:36:15.223665 == TX Byte 0 ==
7751 11:36:15.226675 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7752 11:36:15.229865 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7753 11:36:15.233359 == TX Byte 1 ==
7754 11:36:15.236413 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7755 11:36:15.240028 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7756 11:36:15.243284 ==
7757 11:36:15.246182 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 11:36:15.250072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 11:36:15.250473 ==
7760 11:36:15.262898
7761 11:36:15.266404 TX Vref early break, caculate TX vref
7762 11:36:15.269399 TX Vref=16, minBit 9, minWin=21, winSum=359
7763 11:36:15.272831 TX Vref=18, minBit 8, minWin=21, winSum=374
7764 11:36:15.276001 TX Vref=20, minBit 8, minWin=22, winSum=382
7765 11:36:15.279639 TX Vref=22, minBit 8, minWin=23, winSum=395
7766 11:36:15.282457 TX Vref=24, minBit 8, minWin=24, winSum=402
7767 11:36:15.289305 TX Vref=26, minBit 8, minWin=24, winSum=412
7768 11:36:15.292668 TX Vref=28, minBit 8, minWin=24, winSum=409
7769 11:36:15.295786 TX Vref=30, minBit 8, minWin=23, winSum=402
7770 11:36:15.299497 TX Vref=32, minBit 9, minWin=22, winSum=391
7771 11:36:15.302551 TX Vref=34, minBit 8, minWin=22, winSum=385
7772 11:36:15.309025 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 26
7773 11:36:15.309469
7774 11:36:15.312601 Final TX Range 0 Vref 26
7775 11:36:15.312985
7776 11:36:15.313282 ==
7777 11:36:15.316034 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 11:36:15.318921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 11:36:15.319284 ==
7780 11:36:15.319591
7781 11:36:15.319886
7782 11:36:15.322377 TX Vref Scan disable
7783 11:36:15.329063 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7784 11:36:15.329469 == TX Byte 0 ==
7785 11:36:15.332184 u2DelayCellOfst[0]=15 cells (4 PI)
7786 11:36:15.335860 u2DelayCellOfst[1]=18 cells (5 PI)
7787 11:36:15.338859 u2DelayCellOfst[2]=11 cells (3 PI)
7788 11:36:15.342205 u2DelayCellOfst[3]=15 cells (4 PI)
7789 11:36:15.345584 u2DelayCellOfst[4]=7 cells (2 PI)
7790 11:36:15.348921 u2DelayCellOfst[5]=0 cells (0 PI)
7791 11:36:15.352543 u2DelayCellOfst[6]=22 cells (6 PI)
7792 11:36:15.355649 u2DelayCellOfst[7]=18 cells (5 PI)
7793 11:36:15.359076 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7794 11:36:15.362270 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7795 11:36:15.365455 == TX Byte 1 ==
7796 11:36:15.368528 u2DelayCellOfst[8]=0 cells (0 PI)
7797 11:36:15.368911 u2DelayCellOfst[9]=0 cells (0 PI)
7798 11:36:15.372227 u2DelayCellOfst[10]=7 cells (2 PI)
7799 11:36:15.375557 u2DelayCellOfst[11]=7 cells (2 PI)
7800 11:36:15.379057 u2DelayCellOfst[12]=11 cells (3 PI)
7801 11:36:15.381817 u2DelayCellOfst[13]=11 cells (3 PI)
7802 11:36:15.385367 u2DelayCellOfst[14]=18 cells (5 PI)
7803 11:36:15.388712 u2DelayCellOfst[15]=11 cells (3 PI)
7804 11:36:15.391532 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7805 11:36:15.398248 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7806 11:36:15.398322 DramC Write-DBI on
7807 11:36:15.398381 ==
7808 11:36:15.401300 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 11:36:15.408103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 11:36:15.408182 ==
7811 11:36:15.408258
7812 11:36:15.408326
7813 11:36:15.408415 TX Vref Scan disable
7814 11:36:15.412096 == TX Byte 0 ==
7815 11:36:15.415493 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7816 11:36:15.418672 == TX Byte 1 ==
7817 11:36:15.422324 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7818 11:36:15.425375 DramC Write-DBI off
7819 11:36:15.425463
7820 11:36:15.425550 [DATLAT]
7821 11:36:15.425620 Freq=1600, CH0 RK0
7822 11:36:15.425706
7823 11:36:15.428624 DATLAT Default: 0xf
7824 11:36:15.428688 0, 0xFFFF, sum = 0
7825 11:36:15.432050 1, 0xFFFF, sum = 0
7826 11:36:15.432114 2, 0xFFFF, sum = 0
7827 11:36:15.435405 3, 0xFFFF, sum = 0
7828 11:36:15.438617 4, 0xFFFF, sum = 0
7829 11:36:15.438687 5, 0xFFFF, sum = 0
7830 11:36:15.441821 6, 0xFFFF, sum = 0
7831 11:36:15.441887 7, 0xFFFF, sum = 0
7832 11:36:15.445660 8, 0xFFFF, sum = 0
7833 11:36:15.445728 9, 0xFFFF, sum = 0
7834 11:36:15.448499 10, 0xFFFF, sum = 0
7835 11:36:15.448566 11, 0xFFFF, sum = 0
7836 11:36:15.452042 12, 0xFFFF, sum = 0
7837 11:36:15.452109 13, 0xEFFF, sum = 0
7838 11:36:15.455138 14, 0x0, sum = 1
7839 11:36:15.455213 15, 0x0, sum = 2
7840 11:36:15.458496 16, 0x0, sum = 3
7841 11:36:15.458564 17, 0x0, sum = 4
7842 11:36:15.462017 best_step = 15
7843 11:36:15.462110
7844 11:36:15.462180 ==
7845 11:36:15.465270 Dram Type= 6, Freq= 0, CH_0, rank 0
7846 11:36:15.468595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7847 11:36:15.468661 ==
7848 11:36:15.471805 RX Vref Scan: 1
7849 11:36:15.471894
7850 11:36:15.471965 Set Vref Range= 24 -> 127
7851 11:36:15.472031
7852 11:36:15.474973 RX Vref 24 -> 127, step: 1
7853 11:36:15.475038
7854 11:36:15.478651 RX Delay 11 -> 252, step: 4
7855 11:36:15.478719
7856 11:36:15.481528 Set Vref, RX VrefLevel [Byte0]: 24
7857 11:36:15.484806 [Byte1]: 24
7858 11:36:15.484882
7859 11:36:15.488630 Set Vref, RX VrefLevel [Byte0]: 25
7860 11:36:15.491534 [Byte1]: 25
7861 11:36:15.494913
7862 11:36:15.494993 Set Vref, RX VrefLevel [Byte0]: 26
7863 11:36:15.498203 [Byte1]: 26
7864 11:36:15.502758
7865 11:36:15.502852 Set Vref, RX VrefLevel [Byte0]: 27
7866 11:36:15.505972 [Byte1]: 27
7867 11:36:15.510484
7868 11:36:15.510608 Set Vref, RX VrefLevel [Byte0]: 28
7869 11:36:15.513424 [Byte1]: 28
7870 11:36:15.517989
7871 11:36:15.518177 Set Vref, RX VrefLevel [Byte0]: 29
7872 11:36:15.521418 [Byte1]: 29
7873 11:36:15.525491
7874 11:36:15.525676 Set Vref, RX VrefLevel [Byte0]: 30
7875 11:36:15.528758 [Byte1]: 30
7876 11:36:15.532993
7877 11:36:15.533190 Set Vref, RX VrefLevel [Byte0]: 31
7878 11:36:15.536581 [Byte1]: 31
7879 11:36:15.540674
7880 11:36:15.541160 Set Vref, RX VrefLevel [Byte0]: 32
7881 11:36:15.543994 [Byte1]: 32
7882 11:36:15.548270
7883 11:36:15.548670 Set Vref, RX VrefLevel [Byte0]: 33
7884 11:36:15.551747 [Byte1]: 33
7885 11:36:15.556349
7886 11:36:15.556754 Set Vref, RX VrefLevel [Byte0]: 34
7887 11:36:15.559734 [Byte1]: 34
7888 11:36:15.563665
7889 11:36:15.564090 Set Vref, RX VrefLevel [Byte0]: 35
7890 11:36:15.567333 [Byte1]: 35
7891 11:36:15.571298
7892 11:36:15.571705 Set Vref, RX VrefLevel [Byte0]: 36
7893 11:36:15.574781 [Byte1]: 36
7894 11:36:15.578952
7895 11:36:15.579333 Set Vref, RX VrefLevel [Byte0]: 37
7896 11:36:15.582478 [Byte1]: 37
7897 11:36:15.586594
7898 11:36:15.589547 Set Vref, RX VrefLevel [Byte0]: 38
7899 11:36:15.592784 [Byte1]: 38
7900 11:36:15.593516
7901 11:36:15.596384 Set Vref, RX VrefLevel [Byte0]: 39
7902 11:36:15.599447 [Byte1]: 39
7903 11:36:15.599896
7904 11:36:15.603205 Set Vref, RX VrefLevel [Byte0]: 40
7905 11:36:15.606612 [Byte1]: 40
7906 11:36:15.609388
7907 11:36:15.609763 Set Vref, RX VrefLevel [Byte0]: 41
7908 11:36:15.612367 [Byte1]: 41
7909 11:36:15.616410
7910 11:36:15.616495 Set Vref, RX VrefLevel [Byte0]: 42
7911 11:36:15.619709 [Byte1]: 42
7912 11:36:15.623973
7913 11:36:15.624050 Set Vref, RX VrefLevel [Byte0]: 43
7914 11:36:15.627596 [Byte1]: 43
7915 11:36:15.632173
7916 11:36:15.632256 Set Vref, RX VrefLevel [Byte0]: 44
7917 11:36:15.635308 [Byte1]: 44
7918 11:36:15.639338
7919 11:36:15.639444 Set Vref, RX VrefLevel [Byte0]: 45
7920 11:36:15.643066 [Byte1]: 45
7921 11:36:15.647065
7922 11:36:15.647155 Set Vref, RX VrefLevel [Byte0]: 46
7923 11:36:15.650376 [Byte1]: 46
7924 11:36:15.654697
7925 11:36:15.654814 Set Vref, RX VrefLevel [Byte0]: 47
7926 11:36:15.657856 [Byte1]: 47
7927 11:36:15.662481
7928 11:36:15.662605 Set Vref, RX VrefLevel [Byte0]: 48
7929 11:36:15.665505 [Byte1]: 48
7930 11:36:15.670001
7931 11:36:15.670095 Set Vref, RX VrefLevel [Byte0]: 49
7932 11:36:15.673078 [Byte1]: 49
7933 11:36:15.677750
7934 11:36:15.677837 Set Vref, RX VrefLevel [Byte0]: 50
7935 11:36:15.681053 [Byte1]: 50
7936 11:36:15.685168
7937 11:36:15.685251 Set Vref, RX VrefLevel [Byte0]: 51
7938 11:36:15.689000 [Byte1]: 51
7939 11:36:15.692644
7940 11:36:15.692712 Set Vref, RX VrefLevel [Byte0]: 52
7941 11:36:15.695913 [Byte1]: 52
7942 11:36:15.700399
7943 11:36:15.700469 Set Vref, RX VrefLevel [Byte0]: 53
7944 11:36:15.703745 [Byte1]: 53
7945 11:36:15.708311
7946 11:36:15.708380 Set Vref, RX VrefLevel [Byte0]: 54
7947 11:36:15.711438 [Byte1]: 54
7948 11:36:15.716033
7949 11:36:15.716099 Set Vref, RX VrefLevel [Byte0]: 55
7950 11:36:15.718710 [Byte1]: 55
7951 11:36:15.722997
7952 11:36:15.723061 Set Vref, RX VrefLevel [Byte0]: 56
7953 11:36:15.726259 [Byte1]: 56
7954 11:36:15.730608
7955 11:36:15.730703 Set Vref, RX VrefLevel [Byte0]: 57
7956 11:36:15.734249 [Byte1]: 57
7957 11:36:15.738575
7958 11:36:15.738686 Set Vref, RX VrefLevel [Byte0]: 58
7959 11:36:15.741467 [Byte1]: 58
7960 11:36:15.745849
7961 11:36:15.745947 Set Vref, RX VrefLevel [Byte0]: 59
7962 11:36:15.749643 [Byte1]: 59
7963 11:36:15.753913
7964 11:36:15.754002 Set Vref, RX VrefLevel [Byte0]: 60
7965 11:36:15.757166 [Byte1]: 60
7966 11:36:15.761021
7967 11:36:15.761098 Set Vref, RX VrefLevel [Byte0]: 61
7968 11:36:15.764478 [Byte1]: 61
7969 11:36:15.768807
7970 11:36:15.768877 Set Vref, RX VrefLevel [Byte0]: 62
7971 11:36:15.772495 [Byte1]: 62
7972 11:36:15.776671
7973 11:36:15.776744 Set Vref, RX VrefLevel [Byte0]: 63
7974 11:36:15.779846 [Byte1]: 63
7975 11:36:15.784392
7976 11:36:15.784468 Set Vref, RX VrefLevel [Byte0]: 64
7977 11:36:15.787437 [Byte1]: 64
7978 11:36:15.792419
7979 11:36:15.792509 Set Vref, RX VrefLevel [Byte0]: 65
7980 11:36:15.795235 [Byte1]: 65
7981 11:36:15.799638
7982 11:36:15.799740 Set Vref, RX VrefLevel [Byte0]: 66
7983 11:36:15.802983 [Byte1]: 66
7984 11:36:15.807118
7985 11:36:15.807267 Set Vref, RX VrefLevel [Byte0]: 67
7986 11:36:15.810443 [Byte1]: 67
7987 11:36:15.814439
7988 11:36:15.814506 Set Vref, RX VrefLevel [Byte0]: 68
7989 11:36:15.817580 [Byte1]: 68
7990 11:36:15.822422
7991 11:36:15.822485 Set Vref, RX VrefLevel [Byte0]: 69
7992 11:36:15.825824 [Byte1]: 69
7993 11:36:15.829771
7994 11:36:15.829869 Set Vref, RX VrefLevel [Byte0]: 70
7995 11:36:15.833195 [Byte1]: 70
7996 11:36:15.837371
7997 11:36:15.837459 Set Vref, RX VrefLevel [Byte0]: 71
7998 11:36:15.840664 [Byte1]: 71
7999 11:36:15.844884
8000 11:36:15.844976 Set Vref, RX VrefLevel [Byte0]: 72
8001 11:36:15.848267 [Byte1]: 72
8002 11:36:15.853111
8003 11:36:15.853226 Set Vref, RX VrefLevel [Byte0]: 73
8004 11:36:15.856121 [Byte1]: 73
8005 11:36:15.860468
8006 11:36:15.860590 Set Vref, RX VrefLevel [Byte0]: 74
8007 11:36:15.863356 [Byte1]: 74
8008 11:36:15.868003
8009 11:36:15.868145 Set Vref, RX VrefLevel [Byte0]: 75
8010 11:36:15.871010 [Byte1]: 75
8011 11:36:15.876039
8012 11:36:15.876216 Set Vref, RX VrefLevel [Byte0]: 76
8013 11:36:15.878980 [Byte1]: 76
8014 11:36:15.883609
8015 11:36:15.883878 Final RX Vref Byte 0 = 64 to rank0
8016 11:36:15.886432 Final RX Vref Byte 1 = 60 to rank0
8017 11:36:15.890542 Final RX Vref Byte 0 = 64 to rank1
8018 11:36:15.893493 Final RX Vref Byte 1 = 60 to rank1==
8019 11:36:15.896717 Dram Type= 6, Freq= 0, CH_0, rank 0
8020 11:36:15.903175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 11:36:15.903620 ==
8022 11:36:15.904059 DQS Delay:
8023 11:36:15.904469 DQS0 = 0, DQS1 = 0
8024 11:36:15.906450 DQM Delay:
8025 11:36:15.906850 DQM0 = 126, DQM1 = 119
8026 11:36:15.909891 DQ Delay:
8027 11:36:15.913265 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8028 11:36:15.917135 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8029 11:36:15.919941 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8030 11:36:15.923531 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8031 11:36:15.924037
8032 11:36:15.924466
8033 11:36:15.924864
8034 11:36:15.926906 [DramC_TX_OE_Calibration] TA2
8035 11:36:15.929761 Original DQ_B0 (3 6) =30, OEN = 27
8036 11:36:15.933149 Original DQ_B1 (3 6) =30, OEN = 27
8037 11:36:15.936608 24, 0x0, End_B0=24 End_B1=24
8038 11:36:15.937091 25, 0x0, End_B0=25 End_B1=25
8039 11:36:15.939767 26, 0x0, End_B0=26 End_B1=26
8040 11:36:15.943359 27, 0x0, End_B0=27 End_B1=27
8041 11:36:15.946419 28, 0x0, End_B0=28 End_B1=28
8042 11:36:15.949627 29, 0x0, End_B0=29 End_B1=29
8043 11:36:15.950068 30, 0x0, End_B0=30 End_B1=30
8044 11:36:15.953195 31, 0x4141, End_B0=30 End_B1=30
8045 11:36:15.956764 Byte0 end_step=30 best_step=27
8046 11:36:15.959740 Byte1 end_step=30 best_step=27
8047 11:36:15.963063 Byte0 TX OE(2T, 0.5T) = (3, 3)
8048 11:36:15.963459 Byte1 TX OE(2T, 0.5T) = (3, 3)
8049 11:36:15.966731
8050 11:36:15.967092
8051 11:36:15.972939 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8052 11:36:15.976212 CH0 RK0: MR19=303, MR18=1212
8053 11:36:15.982578 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8054 11:36:15.982645
8055 11:36:15.985961 ----->DramcWriteLeveling(PI) begin...
8056 11:36:15.986057 ==
8057 11:36:15.989331 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 11:36:15.992831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 11:36:15.992901 ==
8060 11:36:15.996206 Write leveling (Byte 0): 33 => 33
8061 11:36:15.998847 Write leveling (Byte 1): 30 => 30
8062 11:36:16.002603 DramcWriteLeveling(PI) end<-----
8063 11:36:16.002673
8064 11:36:16.002751 ==
8065 11:36:16.005962 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 11:36:16.009482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 11:36:16.009914 ==
8068 11:36:16.013066 [Gating] SW mode calibration
8069 11:36:16.019324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8070 11:36:16.026381 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8071 11:36:16.029921 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:36:16.032851 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:36:16.040084 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:36:16.043192 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8075 11:36:16.046299 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8076 11:36:16.052643 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 11:36:16.055819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 11:36:16.058965 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 11:36:16.065821 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 11:36:16.069563 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8081 11:36:16.072559 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8082 11:36:16.079551 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8083 11:36:16.082541 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8084 11:36:16.085529 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8085 11:36:16.092661 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 11:36:16.095987 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 11:36:16.099012 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 11:36:16.105550 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 11:36:16.108761 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8090 11:36:16.112230 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8091 11:36:16.119156 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
8092 11:36:16.122271 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8093 11:36:16.125434 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 11:36:16.132062 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 11:36:16.135787 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 11:36:16.138702 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 11:36:16.145264 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8098 11:36:16.148581 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 11:36:16.151941 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 11:36:16.158860 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 11:36:16.162026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:36:16.165483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:36:16.172002 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:36:16.175066 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:36:16.178947 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:36:16.184652 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:36:16.188186 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:36:16.191348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:36:16.197884 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:36:16.201513 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:36:16.204620 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:36:16.211836 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:36:16.214649 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8114 11:36:16.217653 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 11:36:16.224817 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 11:36:16.224886 Total UI for P1: 0, mck2ui 16
8117 11:36:16.227695 best dqsien dly found for B0: ( 1, 9, 10)
8118 11:36:16.234666 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 11:36:16.237812 Total UI for P1: 0, mck2ui 16
8120 11:36:16.241207 best dqsien dly found for B1: ( 1, 9, 16)
8121 11:36:16.244663 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8122 11:36:16.247879 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8123 11:36:16.247956
8124 11:36:16.251192 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8125 11:36:16.254210 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8126 11:36:16.257792 [Gating] SW calibration Done
8127 11:36:16.257915 ==
8128 11:36:16.261266 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 11:36:16.264741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 11:36:16.264889 ==
8131 11:36:16.267702 RX Vref Scan: 0
8132 11:36:16.267861
8133 11:36:16.271669 RX Vref 0 -> 0, step: 1
8134 11:36:16.271851
8135 11:36:16.272005 RX Delay 0 -> 252, step: 8
8136 11:36:16.278055 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8137 11:36:16.281168 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8138 11:36:16.284997 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8139 11:36:16.288089 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8140 11:36:16.291351 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8141 11:36:16.298059 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8142 11:36:16.301331 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8143 11:36:16.304695 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8144 11:36:16.308005 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8145 11:36:16.311017 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8146 11:36:16.317715 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8147 11:36:16.321289 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8148 11:36:16.324670 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8149 11:36:16.327563 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8150 11:36:16.330870 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8151 11:36:16.338146 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8152 11:36:16.338559 ==
8153 11:36:16.341084 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 11:36:16.344423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 11:36:16.344881 ==
8156 11:36:16.345224 DQS Delay:
8157 11:36:16.347718 DQS0 = 0, DQS1 = 0
8158 11:36:16.348076 DQM Delay:
8159 11:36:16.351142 DQM0 = 127, DQM1 = 120
8160 11:36:16.351619 DQ Delay:
8161 11:36:16.354497 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8162 11:36:16.357445 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8163 11:36:16.361162 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8164 11:36:16.364479 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8165 11:36:16.365360
8166 11:36:16.367925
8167 11:36:16.368325 ==
8168 11:36:16.371058 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:36:16.374430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:36:16.374984 ==
8171 11:36:16.375450
8172 11:36:16.375943
8173 11:36:16.377239 TX Vref Scan disable
8174 11:36:16.377708 == TX Byte 0 ==
8175 11:36:16.384119 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8176 11:36:16.387356 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8177 11:36:16.387857 == TX Byte 1 ==
8178 11:36:16.394150 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8179 11:36:16.397681 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8180 11:36:16.398216 ==
8181 11:36:16.400985 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 11:36:16.403968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 11:36:16.404555 ==
8184 11:36:16.417818
8185 11:36:16.420686 TX Vref early break, caculate TX vref
8186 11:36:16.424368 TX Vref=16, minBit 0, minWin=22, winSum=370
8187 11:36:16.427566 TX Vref=18, minBit 0, minWin=23, winSum=379
8188 11:36:16.430784 TX Vref=20, minBit 1, minWin=23, winSum=390
8189 11:36:16.433925 TX Vref=22, minBit 0, minWin=24, winSum=404
8190 11:36:16.437391 TX Vref=24, minBit 0, minWin=24, winSum=402
8191 11:36:16.444241 TX Vref=26, minBit 0, minWin=25, winSum=413
8192 11:36:16.447455 TX Vref=28, minBit 7, minWin=25, winSum=420
8193 11:36:16.450569 TX Vref=30, minBit 8, minWin=25, winSum=414
8194 11:36:16.453846 TX Vref=32, minBit 8, minWin=24, winSum=407
8195 11:36:16.457180 TX Vref=34, minBit 0, minWin=24, winSum=393
8196 11:36:16.463736 [TxChooseVref] Worse bit 7, Min win 25, Win sum 420, Final Vref 28
8197 11:36:16.464185
8198 11:36:16.467522 Final TX Range 0 Vref 28
8199 11:36:16.467865
8200 11:36:16.468214 ==
8201 11:36:16.470356 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 11:36:16.474298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 11:36:16.474796 ==
8204 11:36:16.475109
8205 11:36:16.475385
8206 11:36:16.477054 TX Vref Scan disable
8207 11:36:16.483956 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8208 11:36:16.484320 == TX Byte 0 ==
8209 11:36:16.486965 u2DelayCellOfst[0]=11 cells (3 PI)
8210 11:36:16.490301 u2DelayCellOfst[1]=18 cells (5 PI)
8211 11:36:16.493783 u2DelayCellOfst[2]=11 cells (3 PI)
8212 11:36:16.497252 u2DelayCellOfst[3]=11 cells (3 PI)
8213 11:36:16.500868 u2DelayCellOfst[4]=7 cells (2 PI)
8214 11:36:16.503846 u2DelayCellOfst[5]=0 cells (0 PI)
8215 11:36:16.507058 u2DelayCellOfst[6]=18 cells (5 PI)
8216 11:36:16.510279 u2DelayCellOfst[7]=18 cells (5 PI)
8217 11:36:16.514009 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8218 11:36:16.517182 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8219 11:36:16.519967 == TX Byte 1 ==
8220 11:36:16.523818 u2DelayCellOfst[8]=0 cells (0 PI)
8221 11:36:16.524177 u2DelayCellOfst[9]=0 cells (0 PI)
8222 11:36:16.526724 u2DelayCellOfst[10]=3 cells (1 PI)
8223 11:36:16.529996 u2DelayCellOfst[11]=3 cells (1 PI)
8224 11:36:16.533472 u2DelayCellOfst[12]=11 cells (3 PI)
8225 11:36:16.536814 u2DelayCellOfst[13]=11 cells (3 PI)
8226 11:36:16.539983 u2DelayCellOfst[14]=15 cells (4 PI)
8227 11:36:16.543151 u2DelayCellOfst[15]=11 cells (3 PI)
8228 11:36:16.546240 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8229 11:36:16.552921 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8230 11:36:16.553022 DramC Write-DBI on
8231 11:36:16.553113 ==
8232 11:36:16.556159 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 11:36:16.562856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 11:36:16.562975 ==
8235 11:36:16.563079
8236 11:36:16.563178
8237 11:36:16.563278 TX Vref Scan disable
8238 11:36:16.566771 == TX Byte 0 ==
8239 11:36:16.569789 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8240 11:36:16.573224 == TX Byte 1 ==
8241 11:36:16.576514 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8242 11:36:16.579786 DramC Write-DBI off
8243 11:36:16.579853
8244 11:36:16.579907 [DATLAT]
8245 11:36:16.579958 Freq=1600, CH0 RK1
8246 11:36:16.580008
8247 11:36:16.583475 DATLAT Default: 0xf
8248 11:36:16.583537 0, 0xFFFF, sum = 0
8249 11:36:16.586316 1, 0xFFFF, sum = 0
8250 11:36:16.590206 2, 0xFFFF, sum = 0
8251 11:36:16.590578 3, 0xFFFF, sum = 0
8252 11:36:16.593300 4, 0xFFFF, sum = 0
8253 11:36:16.593765 5, 0xFFFF, sum = 0
8254 11:36:16.596859 6, 0xFFFF, sum = 0
8255 11:36:16.597312 7, 0xFFFF, sum = 0
8256 11:36:16.600269 8, 0xFFFF, sum = 0
8257 11:36:16.600759 9, 0xFFFF, sum = 0
8258 11:36:16.603337 10, 0xFFFF, sum = 0
8259 11:36:16.603808 11, 0xFFFF, sum = 0
8260 11:36:16.606768 12, 0xFFFF, sum = 0
8261 11:36:16.607226 13, 0xCFFF, sum = 0
8262 11:36:16.610322 14, 0x0, sum = 1
8263 11:36:16.610916 15, 0x0, sum = 2
8264 11:36:16.613382 16, 0x0, sum = 3
8265 11:36:16.613809 17, 0x0, sum = 4
8266 11:36:16.616912 best_step = 15
8267 11:36:16.617329
8268 11:36:16.617708 ==
8269 11:36:16.620367 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 11:36:16.623660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 11:36:16.624097 ==
8272 11:36:16.627158 RX Vref Scan: 0
8273 11:36:16.627577
8274 11:36:16.627920 RX Vref 0 -> 0, step: 1
8275 11:36:16.628223
8276 11:36:16.630056 RX Delay 3 -> 252, step: 4
8277 11:36:16.633306 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8278 11:36:16.639720 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8279 11:36:16.643272 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8280 11:36:16.647046 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8281 11:36:16.650049 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8282 11:36:16.652903 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8283 11:36:16.659608 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8284 11:36:16.663041 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8285 11:36:16.666729 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8286 11:36:16.669809 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8287 11:36:16.672988 iDelay=191, Bit 10, Center 116 (59 ~ 174) 116
8288 11:36:16.679663 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8289 11:36:16.682683 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8290 11:36:16.685945 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8291 11:36:16.689363 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8292 11:36:16.696245 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8293 11:36:16.696711 ==
8294 11:36:16.699886 Dram Type= 6, Freq= 0, CH_0, rank 1
8295 11:36:16.702602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 11:36:16.702994 ==
8297 11:36:16.703297 DQS Delay:
8298 11:36:16.706708 DQS0 = 0, DQS1 = 0
8299 11:36:16.707140 DQM Delay:
8300 11:36:16.709480 DQM0 = 124, DQM1 = 117
8301 11:36:16.709925 DQ Delay:
8302 11:36:16.712580 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8303 11:36:16.716188 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8304 11:36:16.719474 DQ8 =108, DQ9 =104, DQ10 =116, DQ11 =112
8305 11:36:16.722727 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8306 11:36:16.723177
8307 11:36:16.725989
8308 11:36:16.726479
8309 11:36:16.726821 [DramC_TX_OE_Calibration] TA2
8310 11:36:16.729137 Original DQ_B0 (3 6) =30, OEN = 27
8311 11:36:16.732229 Original DQ_B1 (3 6) =30, OEN = 27
8312 11:36:16.735984 24, 0x0, End_B0=24 End_B1=24
8313 11:36:16.739476 25, 0x0, End_B0=25 End_B1=25
8314 11:36:16.742472 26, 0x0, End_B0=26 End_B1=26
8315 11:36:16.742914 27, 0x0, End_B0=27 End_B1=27
8316 11:36:16.745543 28, 0x0, End_B0=28 End_B1=28
8317 11:36:16.749377 29, 0x0, End_B0=29 End_B1=29
8318 11:36:16.752200 30, 0x0, End_B0=30 End_B1=30
8319 11:36:16.755691 31, 0x4545, End_B0=30 End_B1=30
8320 11:36:16.756078 Byte0 end_step=30 best_step=27
8321 11:36:16.759006 Byte1 end_step=30 best_step=27
8322 11:36:16.762316 Byte0 TX OE(2T, 0.5T) = (3, 3)
8323 11:36:16.766066 Byte1 TX OE(2T, 0.5T) = (3, 3)
8324 11:36:16.766476
8325 11:36:16.766794
8326 11:36:16.772421 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8327 11:36:16.775963 CH0 RK1: MR19=303, MR18=2411
8328 11:36:16.782356 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8329 11:36:16.785746 [RxdqsGatingPostProcess] freq 1600
8330 11:36:16.792524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8331 11:36:16.795319 best DQS0 dly(2T, 0.5T) = (1, 1)
8332 11:36:16.798507 best DQS1 dly(2T, 0.5T) = (1, 1)
8333 11:36:16.798919 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8334 11:36:16.802025 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8335 11:36:16.805461 best DQS0 dly(2T, 0.5T) = (1, 1)
8336 11:36:16.808592 best DQS1 dly(2T, 0.5T) = (1, 1)
8337 11:36:16.812029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8338 11:36:16.815156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8339 11:36:16.818579 Pre-setting of DQS Precalculation
8340 11:36:16.825329 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8341 11:36:16.825710 ==
8342 11:36:16.828375 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 11:36:16.831752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 11:36:16.832160 ==
8345 11:36:16.838591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8346 11:36:16.841719 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8347 11:36:16.844936 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8348 11:36:16.851518 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8349 11:36:16.860386 [CA 0] Center 41 (12~71) winsize 60
8350 11:36:16.863546 [CA 1] Center 42 (13~72) winsize 60
8351 11:36:16.866725 [CA 2] Center 38 (9~67) winsize 59
8352 11:36:16.870420 [CA 3] Center 37 (8~66) winsize 59
8353 11:36:16.873520 [CA 4] Center 37 (8~67) winsize 60
8354 11:36:16.877077 [CA 5] Center 36 (7~66) winsize 60
8355 11:36:16.877448
8356 11:36:16.879897 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8357 11:36:16.880232
8358 11:36:16.883456 [CATrainingPosCal] consider 1 rank data
8359 11:36:16.886594 u2DelayCellTimex100 = 258/100 ps
8360 11:36:16.890015 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8361 11:36:16.896286 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8362 11:36:16.900423 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8363 11:36:16.903001 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8364 11:36:16.906228 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8365 11:36:16.909683 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8366 11:36:16.910060
8367 11:36:16.913042 CA PerBit enable=1, Macro0, CA PI delay=36
8368 11:36:16.913361
8369 11:36:16.916342 [CBTSetCACLKResult] CA Dly = 36
8370 11:36:16.919623 CS Dly: 9 (0~40)
8371 11:36:16.923062 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8372 11:36:16.926069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8373 11:36:16.926436 ==
8374 11:36:16.929537 Dram Type= 6, Freq= 0, CH_1, rank 1
8375 11:36:16.932909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 11:36:16.936198 ==
8377 11:36:16.939170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8378 11:36:16.942515 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8379 11:36:16.949060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8380 11:36:16.956060 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8381 11:36:16.963304 [CA 0] Center 42 (13~72) winsize 60
8382 11:36:16.966706 [CA 1] Center 42 (12~72) winsize 61
8383 11:36:16.969933 [CA 2] Center 38 (9~67) winsize 59
8384 11:36:16.973074 [CA 3] Center 36 (7~66) winsize 60
8385 11:36:16.976524 [CA 4] Center 38 (8~68) winsize 61
8386 11:36:16.979634 [CA 5] Center 36 (6~66) winsize 61
8387 11:36:16.980011
8388 11:36:16.983262 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8389 11:36:16.983615
8390 11:36:16.986792 [CATrainingPosCal] consider 2 rank data
8391 11:36:16.989361 u2DelayCellTimex100 = 258/100 ps
8392 11:36:16.992771 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8393 11:36:16.999348 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8394 11:36:17.002935 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8395 11:36:17.006560 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8396 11:36:17.009387 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8397 11:36:17.013117 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8398 11:36:17.013515
8399 11:36:17.016193 CA PerBit enable=1, Macro0, CA PI delay=36
8400 11:36:17.016571
8401 11:36:17.019562 [CBTSetCACLKResult] CA Dly = 36
8402 11:36:17.022637 CS Dly: 10 (0~43)
8403 11:36:17.025965 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8404 11:36:17.029567 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8405 11:36:17.030017
8406 11:36:17.033077 ----->DramcWriteLeveling(PI) begin...
8407 11:36:17.033461 ==
8408 11:36:17.036248 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 11:36:17.042587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 11:36:17.042973 ==
8411 11:36:17.045991 Write leveling (Byte 0): 25 => 25
8412 11:36:17.046425 Write leveling (Byte 1): 27 => 27
8413 11:36:17.049118 DramcWriteLeveling(PI) end<-----
8414 11:36:17.049490
8415 11:36:17.052408 ==
8416 11:36:17.052821 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 11:36:17.059006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 11:36:17.059395 ==
8419 11:36:17.062338 [Gating] SW mode calibration
8420 11:36:17.068828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8421 11:36:17.072452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8422 11:36:17.079165 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:36:17.082227 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:36:17.085376 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:36:17.092618 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:36:17.095983 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 11:36:17.099474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 11:36:17.105878 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 11:36:17.108893 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 11:36:17.112296 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 11:36:17.119142 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 11:36:17.122436 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 11:36:17.125774 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8434 11:36:17.132188 1 5 16 | B1->B0 | 2828 2a2a | 0 0 | (1 0) (1 0)
8435 11:36:17.135830 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 11:36:17.138950 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:36:17.145357 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 11:36:17.148800 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:36:17.152227 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 11:36:17.159065 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:36:17.161784 1 6 12 | B1->B0 | 2e2e 2d2d | 0 1 | (0 0) (0 0)
8442 11:36:17.165106 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 11:36:17.171952 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 11:36:17.175448 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 11:36:17.178688 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 11:36:17.185102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 11:36:17.188355 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 11:36:17.191676 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:36:17.195296 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 11:36:17.201701 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8451 11:36:17.205383 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8452 11:36:17.207978 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:36:17.214770 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:36:17.217992 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:36:17.222160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:36:17.228545 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:36:17.231407 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:36:17.234799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:36:17.241059 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:36:17.245104 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:36:17.248497 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:36:17.254651 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:36:17.258188 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:36:17.261096 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:36:17.267690 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8466 11:36:17.271498 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8467 11:36:17.274469 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 11:36:17.277907 Total UI for P1: 0, mck2ui 16
8469 11:36:17.281070 best dqsien dly found for B0: ( 1, 9, 16)
8470 11:36:17.284404 Total UI for P1: 0, mck2ui 16
8471 11:36:17.287740 best dqsien dly found for B1: ( 1, 9, 14)
8472 11:36:17.290810 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8473 11:36:17.294075 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8474 11:36:17.294495
8475 11:36:17.300640 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8476 11:36:17.304445 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8477 11:36:17.307927 [Gating] SW calibration Done
8478 11:36:17.308309 ==
8479 11:36:17.310910 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 11:36:17.313890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 11:36:17.314356 ==
8482 11:36:17.314855 RX Vref Scan: 0
8483 11:36:17.317696
8484 11:36:17.318297 RX Vref 0 -> 0, step: 1
8485 11:36:17.318644
8486 11:36:17.320994 RX Delay 0 -> 252, step: 8
8487 11:36:17.323947 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8488 11:36:17.327462 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8489 11:36:17.333937 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8490 11:36:17.337143 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8491 11:36:17.340870 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8492 11:36:17.343935 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8493 11:36:17.347349 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8494 11:36:17.353889 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8495 11:36:17.357265 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8496 11:36:17.360561 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8497 11:36:17.363955 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8498 11:36:17.367231 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8499 11:36:17.373913 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8500 11:36:17.377577 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8501 11:36:17.380248 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8502 11:36:17.383852 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8503 11:36:17.384277 ==
8504 11:36:17.386901 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:36:17.393984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:36:17.394592 ==
8507 11:36:17.394937 DQS Delay:
8508 11:36:17.396904 DQS0 = 0, DQS1 = 0
8509 11:36:17.397342 DQM Delay:
8510 11:36:17.397670 DQM0 = 131, DQM1 = 125
8511 11:36:17.400073 DQ Delay:
8512 11:36:17.403245 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8513 11:36:17.406956 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8514 11:36:17.410441 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8515 11:36:17.413083 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8516 11:36:17.413508
8517 11:36:17.414091
8518 11:36:17.414505 ==
8519 11:36:17.417082 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 11:36:17.423477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 11:36:17.423906 ==
8522 11:36:17.424238
8523 11:36:17.424539
8524 11:36:17.424829 TX Vref Scan disable
8525 11:36:17.426707 == TX Byte 0 ==
8526 11:36:17.429578 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8527 11:36:17.436580 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8528 11:36:17.437221 == TX Byte 1 ==
8529 11:36:17.439918 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8530 11:36:17.446446 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8531 11:36:17.446876 ==
8532 11:36:17.449552 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 11:36:17.453314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 11:36:17.453798 ==
8535 11:36:17.465416
8536 11:36:17.468586 TX Vref early break, caculate TX vref
8537 11:36:17.471801 TX Vref=16, minBit 1, minWin=22, winSum=366
8538 11:36:17.475186 TX Vref=18, minBit 11, minWin=22, winSum=372
8539 11:36:17.478589 TX Vref=20, minBit 5, minWin=23, winSum=382
8540 11:36:17.481717 TX Vref=22, minBit 11, minWin=23, winSum=397
8541 11:36:17.484970 TX Vref=24, minBit 6, minWin=24, winSum=403
8542 11:36:17.491715 TX Vref=26, minBit 5, minWin=25, winSum=413
8543 11:36:17.495282 TX Vref=28, minBit 5, minWin=25, winSum=419
8544 11:36:17.498277 TX Vref=30, minBit 0, minWin=25, winSum=420
8545 11:36:17.501915 TX Vref=32, minBit 0, minWin=25, winSum=412
8546 11:36:17.505129 TX Vref=34, minBit 1, minWin=23, winSum=395
8547 11:36:17.511678 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 30
8548 11:36:17.512254
8549 11:36:17.515186 Final TX Range 0 Vref 30
8550 11:36:17.515622
8551 11:36:17.515944 ==
8552 11:36:17.518767 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 11:36:17.522064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 11:36:17.522540 ==
8555 11:36:17.522869
8556 11:36:17.523243
8557 11:36:17.525385 TX Vref Scan disable
8558 11:36:17.532105 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8559 11:36:17.532532 == TX Byte 0 ==
8560 11:36:17.534961 u2DelayCellOfst[0]=22 cells (6 PI)
8561 11:36:17.538733 u2DelayCellOfst[1]=15 cells (4 PI)
8562 11:36:17.541978 u2DelayCellOfst[2]=0 cells (0 PI)
8563 11:36:17.545030 u2DelayCellOfst[3]=7 cells (2 PI)
8564 11:36:17.548418 u2DelayCellOfst[4]=7 cells (2 PI)
8565 11:36:17.551368 u2DelayCellOfst[5]=22 cells (6 PI)
8566 11:36:17.555044 u2DelayCellOfst[6]=22 cells (6 PI)
8567 11:36:17.558038 u2DelayCellOfst[7]=7 cells (2 PI)
8568 11:36:17.561287 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8569 11:36:17.564973 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8570 11:36:17.568508 == TX Byte 1 ==
8571 11:36:17.568931 u2DelayCellOfst[8]=0 cells (0 PI)
8572 11:36:17.571287 u2DelayCellOfst[9]=7 cells (2 PI)
8573 11:36:17.574757 u2DelayCellOfst[10]=15 cells (4 PI)
8574 11:36:17.578046 u2DelayCellOfst[11]=11 cells (3 PI)
8575 11:36:17.581309 u2DelayCellOfst[12]=18 cells (5 PI)
8576 11:36:17.584586 u2DelayCellOfst[13]=22 cells (6 PI)
8577 11:36:17.588010 u2DelayCellOfst[14]=22 cells (6 PI)
8578 11:36:17.590864 u2DelayCellOfst[15]=22 cells (6 PI)
8579 11:36:17.594562 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8580 11:36:17.600970 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8581 11:36:17.601413 DramC Write-DBI on
8582 11:36:17.601744 ==
8583 11:36:17.604382 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 11:36:17.610873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 11:36:17.611301 ==
8586 11:36:17.611814
8587 11:36:17.612348
8588 11:36:17.612741 TX Vref Scan disable
8589 11:36:17.614704 == TX Byte 0 ==
8590 11:36:17.617921 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8591 11:36:17.621534 == TX Byte 1 ==
8592 11:36:17.625014 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8593 11:36:17.628570 DramC Write-DBI off
8594 11:36:17.629054
8595 11:36:17.629384 [DATLAT]
8596 11:36:17.629687 Freq=1600, CH1 RK0
8597 11:36:17.629975
8598 11:36:17.631701 DATLAT Default: 0xf
8599 11:36:17.632121 0, 0xFFFF, sum = 0
8600 11:36:17.634705 1, 0xFFFF, sum = 0
8601 11:36:17.638234 2, 0xFFFF, sum = 0
8602 11:36:17.638664 3, 0xFFFF, sum = 0
8603 11:36:17.641515 4, 0xFFFF, sum = 0
8604 11:36:17.641943 5, 0xFFFF, sum = 0
8605 11:36:17.644905 6, 0xFFFF, sum = 0
8606 11:36:17.645336 7, 0xFFFF, sum = 0
8607 11:36:17.648147 8, 0xFFFF, sum = 0
8608 11:36:17.648572 9, 0xFFFF, sum = 0
8609 11:36:17.651063 10, 0xFFFF, sum = 0
8610 11:36:17.651490 11, 0xFFFF, sum = 0
8611 11:36:17.654937 12, 0xFFFF, sum = 0
8612 11:36:17.655368 13, 0x8FFF, sum = 0
8613 11:36:17.658199 14, 0x0, sum = 1
8614 11:36:17.658625 15, 0x0, sum = 2
8615 11:36:17.660970 16, 0x0, sum = 3
8616 11:36:17.661593 17, 0x0, sum = 4
8617 11:36:17.664507 best_step = 15
8618 11:36:17.664924
8619 11:36:17.665317 ==
8620 11:36:17.668149 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 11:36:17.670830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 11:36:17.671255 ==
8623 11:36:17.674670 RX Vref Scan: 1
8624 11:36:17.675090
8625 11:36:17.675430 Set Vref Range= 24 -> 127
8626 11:36:17.675707
8627 11:36:17.678233 RX Vref 24 -> 127, step: 1
8628 11:36:17.678660
8629 11:36:17.681148 RX Delay 11 -> 252, step: 4
8630 11:36:17.681565
8631 11:36:17.683992 Set Vref, RX VrefLevel [Byte0]: 24
8632 11:36:17.687774 [Byte1]: 24
8633 11:36:17.688198
8634 11:36:17.691113 Set Vref, RX VrefLevel [Byte0]: 25
8635 11:36:17.694342 [Byte1]: 25
8636 11:36:17.697953
8637 11:36:17.698360 Set Vref, RX VrefLevel [Byte0]: 26
8638 11:36:17.701197 [Byte1]: 26
8639 11:36:17.705061
8640 11:36:17.705443 Set Vref, RX VrefLevel [Byte0]: 27
8641 11:36:17.708497 [Byte1]: 27
8642 11:36:17.713094
8643 11:36:17.713517 Set Vref, RX VrefLevel [Byte0]: 28
8644 11:36:17.716249 [Byte1]: 28
8645 11:36:17.720379
8646 11:36:17.720816 Set Vref, RX VrefLevel [Byte0]: 29
8647 11:36:17.723765 [Byte1]: 29
8648 11:36:17.727829
8649 11:36:17.728268 Set Vref, RX VrefLevel [Byte0]: 30
8650 11:36:17.731243 [Byte1]: 30
8651 11:36:17.735953
8652 11:36:17.736440 Set Vref, RX VrefLevel [Byte0]: 31
8653 11:36:17.739094 [Byte1]: 31
8654 11:36:17.743176
8655 11:36:17.743599 Set Vref, RX VrefLevel [Byte0]: 32
8656 11:36:17.746330 [Byte1]: 32
8657 11:36:17.750605
8658 11:36:17.751027 Set Vref, RX VrefLevel [Byte0]: 33
8659 11:36:17.754348 [Byte1]: 33
8660 11:36:17.758515
8661 11:36:17.758941 Set Vref, RX VrefLevel [Byte0]: 34
8662 11:36:17.761689 [Byte1]: 34
8663 11:36:17.765899
8664 11:36:17.766353 Set Vref, RX VrefLevel [Byte0]: 35
8665 11:36:17.769314 [Byte1]: 35
8666 11:36:17.773956
8667 11:36:17.774493 Set Vref, RX VrefLevel [Byte0]: 36
8668 11:36:17.777356 [Byte1]: 36
8669 11:36:17.782009
8670 11:36:17.782540 Set Vref, RX VrefLevel [Byte0]: 37
8671 11:36:17.784710 [Byte1]: 37
8672 11:36:17.788800
8673 11:36:17.789222 Set Vref, RX VrefLevel [Byte0]: 38
8674 11:36:17.792357 [Byte1]: 38
8675 11:36:17.796658
8676 11:36:17.797078 Set Vref, RX VrefLevel [Byte0]: 39
8677 11:36:17.799968 [Byte1]: 39
8678 11:36:17.803993
8679 11:36:17.804418 Set Vref, RX VrefLevel [Byte0]: 40
8680 11:36:17.807327 [Byte1]: 40
8681 11:36:17.811706
8682 11:36:17.812126 Set Vref, RX VrefLevel [Byte0]: 41
8683 11:36:17.815053 [Byte1]: 41
8684 11:36:17.819266
8685 11:36:17.819685 Set Vref, RX VrefLevel [Byte0]: 42
8686 11:36:17.822738 [Byte1]: 42
8687 11:36:17.827065
8688 11:36:17.827484 Set Vref, RX VrefLevel [Byte0]: 43
8689 11:36:17.830443 [Byte1]: 43
8690 11:36:17.834653
8691 11:36:17.835077 Set Vref, RX VrefLevel [Byte0]: 44
8692 11:36:17.838074 [Byte1]: 44
8693 11:36:17.842473
8694 11:36:17.842894 Set Vref, RX VrefLevel [Byte0]: 45
8695 11:36:17.845630 [Byte1]: 45
8696 11:36:17.850029
8697 11:36:17.850491 Set Vref, RX VrefLevel [Byte0]: 46
8698 11:36:17.853023 [Byte1]: 46
8699 11:36:17.857645
8700 11:36:17.858065 Set Vref, RX VrefLevel [Byte0]: 47
8701 11:36:17.860849 [Byte1]: 47
8702 11:36:17.865434
8703 11:36:17.865890 Set Vref, RX VrefLevel [Byte0]: 48
8704 11:36:17.868410 [Byte1]: 48
8705 11:36:17.872839
8706 11:36:17.873263 Set Vref, RX VrefLevel [Byte0]: 49
8707 11:36:17.875818 [Byte1]: 49
8708 11:36:17.880493
8709 11:36:17.880991 Set Vref, RX VrefLevel [Byte0]: 50
8710 11:36:17.883365 [Byte1]: 50
8711 11:36:17.887685
8712 11:36:17.888108 Set Vref, RX VrefLevel [Byte0]: 51
8713 11:36:17.891212 [Byte1]: 51
8714 11:36:17.895341
8715 11:36:17.895763 Set Vref, RX VrefLevel [Byte0]: 52
8716 11:36:17.898771 [Byte1]: 52
8717 11:36:17.903132
8718 11:36:17.903553 Set Vref, RX VrefLevel [Byte0]: 53
8719 11:36:17.906397 [Byte1]: 53
8720 11:36:17.910636
8721 11:36:17.911073 Set Vref, RX VrefLevel [Byte0]: 54
8722 11:36:17.914065 [Byte1]: 54
8723 11:36:17.918407
8724 11:36:17.918830 Set Vref, RX VrefLevel [Byte0]: 55
8725 11:36:17.921867 [Byte1]: 55
8726 11:36:17.926348
8727 11:36:17.926771 Set Vref, RX VrefLevel [Byte0]: 56
8728 11:36:17.929545 [Byte1]: 56
8729 11:36:17.934143
8730 11:36:17.934650 Set Vref, RX VrefLevel [Byte0]: 57
8731 11:36:17.936887 [Byte1]: 57
8732 11:36:17.941176
8733 11:36:17.941671 Set Vref, RX VrefLevel [Byte0]: 58
8734 11:36:17.944749 [Byte1]: 58
8735 11:36:17.949185
8736 11:36:17.949678 Set Vref, RX VrefLevel [Byte0]: 59
8737 11:36:17.952404 [Byte1]: 59
8738 11:36:17.956314
8739 11:36:17.956738 Set Vref, RX VrefLevel [Byte0]: 60
8740 11:36:17.960142 [Byte1]: 60
8741 11:36:17.964406
8742 11:36:17.964971 Set Vref, RX VrefLevel [Byte0]: 61
8743 11:36:17.967614 [Byte1]: 61
8744 11:36:17.972312
8745 11:36:17.972809 Set Vref, RX VrefLevel [Byte0]: 62
8746 11:36:17.974803 [Byte1]: 62
8747 11:36:17.979645
8748 11:36:17.980141 Set Vref, RX VrefLevel [Byte0]: 63
8749 11:36:17.982897 [Byte1]: 63
8750 11:36:17.987302
8751 11:36:17.987806 Set Vref, RX VrefLevel [Byte0]: 64
8752 11:36:17.990170 [Byte1]: 64
8753 11:36:17.994442
8754 11:36:17.994937 Set Vref, RX VrefLevel [Byte0]: 65
8755 11:36:17.997843 [Byte1]: 65
8756 11:36:18.002257
8757 11:36:18.002749 Set Vref, RX VrefLevel [Byte0]: 66
8758 11:36:18.005883 [Byte1]: 66
8759 11:36:18.009476
8760 11:36:18.009920 Set Vref, RX VrefLevel [Byte0]: 67
8761 11:36:18.012833 [Byte1]: 67
8762 11:36:18.017344
8763 11:36:18.017841 Set Vref, RX VrefLevel [Byte0]: 68
8764 11:36:18.020446 [Byte1]: 68
8765 11:36:18.025000
8766 11:36:18.025496 Set Vref, RX VrefLevel [Byte0]: 69
8767 11:36:18.028687 [Byte1]: 69
8768 11:36:18.032662
8769 11:36:18.033160 Set Vref, RX VrefLevel [Byte0]: 70
8770 11:36:18.036216 [Byte1]: 70
8771 11:36:18.040549
8772 11:36:18.041043 Set Vref, RX VrefLevel [Byte0]: 71
8773 11:36:18.043681 [Byte1]: 71
8774 11:36:18.047916
8775 11:36:18.048407 Final RX Vref Byte 0 = 59 to rank0
8776 11:36:18.051775 Final RX Vref Byte 1 = 56 to rank0
8777 11:36:18.054649 Final RX Vref Byte 0 = 59 to rank1
8778 11:36:18.057973 Final RX Vref Byte 1 = 56 to rank1==
8779 11:36:18.061446 Dram Type= 6, Freq= 0, CH_1, rank 0
8780 11:36:18.068044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 11:36:18.068541 ==
8782 11:36:18.068872 DQS Delay:
8783 11:36:18.069174 DQS0 = 0, DQS1 = 0
8784 11:36:18.071018 DQM Delay:
8785 11:36:18.071439 DQM0 = 131, DQM1 = 123
8786 11:36:18.074404 DQ Delay:
8787 11:36:18.078005 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8788 11:36:18.081675 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8789 11:36:18.084506 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8790 11:36:18.087635 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8791 11:36:18.088060
8792 11:36:18.088383
8793 11:36:18.088681
8794 11:36:18.091004 [DramC_TX_OE_Calibration] TA2
8795 11:36:18.095005 Original DQ_B0 (3 6) =30, OEN = 27
8796 11:36:18.097574 Original DQ_B1 (3 6) =30, OEN = 27
8797 11:36:18.100896 24, 0x0, End_B0=24 End_B1=24
8798 11:36:18.101329 25, 0x0, End_B0=25 End_B1=25
8799 11:36:18.104608 26, 0x0, End_B0=26 End_B1=26
8800 11:36:18.107907 27, 0x0, End_B0=27 End_B1=27
8801 11:36:18.111551 28, 0x0, End_B0=28 End_B1=28
8802 11:36:18.114175 29, 0x0, End_B0=29 End_B1=29
8803 11:36:18.114606 30, 0x0, End_B0=30 End_B1=30
8804 11:36:18.117786 31, 0x4141, End_B0=30 End_B1=30
8805 11:36:18.120822 Byte0 end_step=30 best_step=27
8806 11:36:18.124573 Byte1 end_step=30 best_step=27
8807 11:36:18.127375 Byte0 TX OE(2T, 0.5T) = (3, 3)
8808 11:36:18.130723 Byte1 TX OE(2T, 0.5T) = (3, 3)
8809 11:36:18.131227
8810 11:36:18.131557
8811 11:36:18.138325 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8812 11:36:18.140835 CH1 RK0: MR19=303, MR18=A0E
8813 11:36:18.147482 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8814 11:36:18.147907
8815 11:36:18.150596 ----->DramcWriteLeveling(PI) begin...
8816 11:36:18.151026 ==
8817 11:36:18.154226 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 11:36:18.157359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 11:36:18.157784 ==
8820 11:36:18.161467 Write leveling (Byte 0): 22 => 22
8821 11:36:18.164287 Write leveling (Byte 1): 26 => 26
8822 11:36:18.167464 DramcWriteLeveling(PI) end<-----
8823 11:36:18.167889
8824 11:36:18.168215 ==
8825 11:36:18.170595 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 11:36:18.173698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 11:36:18.174150 ==
8828 11:36:18.177542 [Gating] SW mode calibration
8829 11:36:18.183988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8830 11:36:18.190294 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8831 11:36:18.193878 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:36:18.197312 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:36:18.203640 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8834 11:36:18.207272 1 4 12 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
8835 11:36:18.210237 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 11:36:18.217141 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 11:36:18.220792 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:36:18.224063 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:36:18.230235 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:36:18.233728 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8841 11:36:18.236916 1 5 8 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 0)
8842 11:36:18.243238 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8843 11:36:18.246812 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 11:36:18.250500 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 11:36:18.256618 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:36:18.260026 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:36:18.263791 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:36:18.270078 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:36:18.273674 1 6 8 | B1->B0 | 2727 4444 | 0 1 | (0 0) (0 0)
8850 11:36:18.277172 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8851 11:36:18.283732 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 11:36:18.286792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 11:36:18.290176 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:36:18.296962 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:36:18.299928 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:36:18.303750 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:36:18.309891 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8858 11:36:18.313363 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8859 11:36:18.316615 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:36:18.323164 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:36:18.326287 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:36:18.330282 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:36:18.333244 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:36:18.339939 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:36:18.343382 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:36:18.346597 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:36:18.353387 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:36:18.356597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:36:18.359810 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:36:18.366287 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:36:18.370399 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:36:18.372988 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8873 11:36:18.379470 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8874 11:36:18.383236 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8875 11:36:18.385868 Total UI for P1: 0, mck2ui 16
8876 11:36:18.389619 best dqsien dly found for B0: ( 1, 9, 6)
8877 11:36:18.393070 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:36:18.396114 Total UI for P1: 0, mck2ui 16
8879 11:36:18.399668 best dqsien dly found for B1: ( 1, 9, 10)
8880 11:36:18.402661 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8881 11:36:18.406745 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8882 11:36:18.407239
8883 11:36:18.413077 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8884 11:36:18.415999 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8885 11:36:18.419730 [Gating] SW calibration Done
8886 11:36:18.420153 ==
8887 11:36:18.422512 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 11:36:18.425935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 11:36:18.426398 ==
8890 11:36:18.426729 RX Vref Scan: 0
8891 11:36:18.427035
8892 11:36:18.429188 RX Vref 0 -> 0, step: 1
8893 11:36:18.429609
8894 11:36:18.432950 RX Delay 0 -> 252, step: 8
8895 11:36:18.436028 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8896 11:36:18.439370 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8897 11:36:18.443233 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8898 11:36:18.449484 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8899 11:36:18.452631 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8900 11:36:18.455981 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8901 11:36:18.459379 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8902 11:36:18.462781 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8903 11:36:18.469508 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8904 11:36:18.472798 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8905 11:36:18.475653 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8906 11:36:18.479657 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8907 11:36:18.483001 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8908 11:36:18.489028 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8909 11:36:18.492181 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8910 11:36:18.495701 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8911 11:36:18.496206 ==
8912 11:36:18.499114 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:36:18.502737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:36:18.505847 ==
8915 11:36:18.506392 DQS Delay:
8916 11:36:18.506734 DQS0 = 0, DQS1 = 0
8917 11:36:18.509024 DQM Delay:
8918 11:36:18.509448 DQM0 = 128, DQM1 = 128
8919 11:36:18.512348 DQ Delay:
8920 11:36:18.515760 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =123
8921 11:36:18.519163 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8922 11:36:18.522814 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8923 11:36:18.525387 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8924 11:36:18.525813
8925 11:36:18.526190
8926 11:36:18.526507 ==
8927 11:36:18.529155 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:36:18.531938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:36:18.532367 ==
8930 11:36:18.535695
8931 11:36:18.536237
8932 11:36:18.536572 TX Vref Scan disable
8933 11:36:18.538771 == TX Byte 0 ==
8934 11:36:18.541841 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8935 11:36:18.545359 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8936 11:36:18.548468 == TX Byte 1 ==
8937 11:36:18.552327 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 11:36:18.555238 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 11:36:18.555678 ==
8940 11:36:18.558409 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 11:36:18.565118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 11:36:18.565544 ==
8943 11:36:18.578499
8944 11:36:18.582231 TX Vref early break, caculate TX vref
8945 11:36:18.585048 TX Vref=16, minBit 0, minWin=23, winSum=381
8946 11:36:18.588363 TX Vref=18, minBit 3, minWin=23, winSum=391
8947 11:36:18.591883 TX Vref=20, minBit 0, minWin=23, winSum=398
8948 11:36:18.594921 TX Vref=22, minBit 0, minWin=22, winSum=403
8949 11:36:18.598424 TX Vref=24, minBit 0, minWin=24, winSum=416
8950 11:36:18.604713 TX Vref=26, minBit 5, minWin=24, winSum=423
8951 11:36:18.608025 TX Vref=28, minBit 0, minWin=24, winSum=423
8952 11:36:18.611635 TX Vref=30, minBit 0, minWin=25, winSum=417
8953 11:36:18.614494 TX Vref=32, minBit 1, minWin=24, winSum=410
8954 11:36:18.618149 TX Vref=34, minBit 1, minWin=23, winSum=402
8955 11:36:18.621720 TX Vref=36, minBit 1, minWin=23, winSum=394
8956 11:36:18.628430 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
8957 11:36:18.628975
8958 11:36:18.631320 Final TX Range 0 Vref 30
8959 11:36:18.631742
8960 11:36:18.632066 ==
8961 11:36:18.634681 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 11:36:18.637982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 11:36:18.638457 ==
8964 11:36:18.640939
8965 11:36:18.641303
8966 11:36:18.641823 TX Vref Scan disable
8967 11:36:18.648079 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8968 11:36:18.648503 == TX Byte 0 ==
8969 11:36:18.650908 u2DelayCellOfst[0]=22 cells (6 PI)
8970 11:36:18.654283 u2DelayCellOfst[1]=15 cells (4 PI)
8971 11:36:18.657572 u2DelayCellOfst[2]=0 cells (0 PI)
8972 11:36:18.661520 u2DelayCellOfst[3]=7 cells (2 PI)
8973 11:36:18.664319 u2DelayCellOfst[4]=11 cells (3 PI)
8974 11:36:18.667365 u2DelayCellOfst[5]=22 cells (6 PI)
8975 11:36:18.670964 u2DelayCellOfst[6]=22 cells (6 PI)
8976 11:36:18.674229 u2DelayCellOfst[7]=7 cells (2 PI)
8977 11:36:18.677569 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8978 11:36:18.680838 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8979 11:36:18.684524 == TX Byte 1 ==
8980 11:36:18.687263 u2DelayCellOfst[8]=0 cells (0 PI)
8981 11:36:18.691072 u2DelayCellOfst[9]=3 cells (1 PI)
8982 11:36:18.694432 u2DelayCellOfst[10]=15 cells (4 PI)
8983 11:36:18.697369 u2DelayCellOfst[11]=7 cells (2 PI)
8984 11:36:18.697883 u2DelayCellOfst[12]=18 cells (5 PI)
8985 11:36:18.700530 u2DelayCellOfst[13]=22 cells (6 PI)
8986 11:36:18.704247 u2DelayCellOfst[14]=18 cells (5 PI)
8987 11:36:18.708131 u2DelayCellOfst[15]=22 cells (6 PI)
8988 11:36:18.714455 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8989 11:36:18.717318 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8990 11:36:18.717817 DramC Write-DBI on
8991 11:36:18.720882 ==
8992 11:36:18.721301 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 11:36:18.727422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 11:36:18.727910 ==
8995 11:36:18.728238
8996 11:36:18.728537
8997 11:36:18.731094 TX Vref Scan disable
8998 11:36:18.731561 == TX Byte 0 ==
8999 11:36:18.737817 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9000 11:36:18.738375 == TX Byte 1 ==
9001 11:36:18.740937 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9002 11:36:18.743774 DramC Write-DBI off
9003 11:36:18.744196
9004 11:36:18.744526 [DATLAT]
9005 11:36:18.747246 Freq=1600, CH1 RK1
9006 11:36:18.747748
9007 11:36:18.748075 DATLAT Default: 0xf
9008 11:36:18.750702 0, 0xFFFF, sum = 0
9009 11:36:18.751215 1, 0xFFFF, sum = 0
9010 11:36:18.754001 2, 0xFFFF, sum = 0
9011 11:36:18.754450 3, 0xFFFF, sum = 0
9012 11:36:18.757435 4, 0xFFFF, sum = 0
9013 11:36:18.757942 5, 0xFFFF, sum = 0
9014 11:36:18.760666 6, 0xFFFF, sum = 0
9015 11:36:18.761172 7, 0xFFFF, sum = 0
9016 11:36:18.764177 8, 0xFFFF, sum = 0
9017 11:36:18.764751 9, 0xFFFF, sum = 0
9018 11:36:18.767331 10, 0xFFFF, sum = 0
9019 11:36:18.771172 11, 0xFFFF, sum = 0
9020 11:36:18.771679 12, 0xFFFF, sum = 0
9021 11:36:18.774092 13, 0x8FFF, sum = 0
9022 11:36:18.774593 14, 0x0, sum = 1
9023 11:36:18.777318 15, 0x0, sum = 2
9024 11:36:18.777830 16, 0x0, sum = 3
9025 11:36:18.778219 17, 0x0, sum = 4
9026 11:36:18.780590 best_step = 15
9027 11:36:18.781090
9028 11:36:18.781416 ==
9029 11:36:18.783827 Dram Type= 6, Freq= 0, CH_1, rank 1
9030 11:36:18.787031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9031 11:36:18.787459 ==
9032 11:36:18.790760 RX Vref Scan: 0
9033 11:36:18.791177
9034 11:36:18.791501 RX Vref 0 -> 0, step: 1
9035 11:36:18.791807
9036 11:36:18.793767 RX Delay 11 -> 252, step: 4
9037 11:36:18.800730 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
9038 11:36:18.803926 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9039 11:36:18.807217 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9040 11:36:18.810625 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9041 11:36:18.813766 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9042 11:36:18.820163 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9043 11:36:18.823867 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9044 11:36:18.827075 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9045 11:36:18.830592 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9046 11:36:18.833846 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9047 11:36:18.841146 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9048 11:36:18.844088 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9049 11:36:18.847118 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
9050 11:36:18.850754 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9051 11:36:18.856798 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9052 11:36:18.860571 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9053 11:36:18.861074 ==
9054 11:36:18.863604 Dram Type= 6, Freq= 0, CH_1, rank 1
9055 11:36:18.866674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9056 11:36:18.867193 ==
9057 11:36:18.869852 DQS Delay:
9058 11:36:18.870306 DQS0 = 0, DQS1 = 0
9059 11:36:18.870637 DQM Delay:
9060 11:36:18.873203 DQM0 = 127, DQM1 = 125
9061 11:36:18.873624 DQ Delay:
9062 11:36:18.876591 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
9063 11:36:18.880582 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =124
9064 11:36:18.886665 DQ8 =112, DQ9 =112, DQ10 =130, DQ11 =118
9065 11:36:18.889750 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =134
9066 11:36:18.890310
9067 11:36:18.890717
9068 11:36:18.891027
9069 11:36:18.893093 [DramC_TX_OE_Calibration] TA2
9070 11:36:18.896897 Original DQ_B0 (3 6) =30, OEN = 27
9071 11:36:18.899450 Original DQ_B1 (3 6) =30, OEN = 27
9072 11:36:18.899873 24, 0x0, End_B0=24 End_B1=24
9073 11:36:18.902829 25, 0x0, End_B0=25 End_B1=25
9074 11:36:18.906767 26, 0x0, End_B0=26 End_B1=26
9075 11:36:18.909600 27, 0x0, End_B0=27 End_B1=27
9076 11:36:18.910148 28, 0x0, End_B0=28 End_B1=28
9077 11:36:18.913176 29, 0x0, End_B0=29 End_B1=29
9078 11:36:18.916796 30, 0x0, End_B0=30 End_B1=30
9079 11:36:18.919634 31, 0x4141, End_B0=30 End_B1=30
9080 11:36:18.923143 Byte0 end_step=30 best_step=27
9081 11:36:18.926841 Byte1 end_step=30 best_step=27
9082 11:36:18.927346 Byte0 TX OE(2T, 0.5T) = (3, 3)
9083 11:36:18.929656 Byte1 TX OE(2T, 0.5T) = (3, 3)
9084 11:36:18.930200
9085 11:36:18.930535
9086 11:36:18.939474 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9087 11:36:18.943052 CH1 RK1: MR19=303, MR18=F1B
9088 11:36:18.945856 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9089 11:36:18.949335 [RxdqsGatingPostProcess] freq 1600
9090 11:36:18.956028 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9091 11:36:18.959295 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 11:36:18.962779 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 11:36:18.965807 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 11:36:18.969242 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 11:36:18.972716 best DQS0 dly(2T, 0.5T) = (1, 1)
9096 11:36:18.973236 best DQS1 dly(2T, 0.5T) = (1, 1)
9097 11:36:18.975822 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9098 11:36:18.979390 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9099 11:36:18.982228 Pre-setting of DQS Precalculation
9100 11:36:18.989246 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9101 11:36:18.995469 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9102 11:36:19.001970 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 11:36:19.002525
9104 11:36:19.002917
9105 11:36:19.005354 [Calibration Summary] 3200 Mbps
9106 11:36:19.008972 CH 0, Rank 0
9107 11:36:19.009468 SW Impedance : PASS
9108 11:36:19.012036 DUTY Scan : NO K
9109 11:36:19.012459 ZQ Calibration : PASS
9110 11:36:19.015607 Jitter Meter : NO K
9111 11:36:19.018764 CBT Training : PASS
9112 11:36:19.019265 Write leveling : PASS
9113 11:36:19.021887 RX DQS gating : PASS
9114 11:36:19.025468 RX DQ/DQS(RDDQC) : PASS
9115 11:36:19.026021 TX DQ/DQS : PASS
9116 11:36:19.028559 RX DATLAT : PASS
9117 11:36:19.031842 RX DQ/DQS(Engine): PASS
9118 11:36:19.032529 TX OE : PASS
9119 11:36:19.035057 All Pass.
9120 11:36:19.035478
9121 11:36:19.035803 CH 0, Rank 1
9122 11:36:19.038805 SW Impedance : PASS
9123 11:36:19.039302 DUTY Scan : NO K
9124 11:36:19.042089 ZQ Calibration : PASS
9125 11:36:19.045545 Jitter Meter : NO K
9126 11:36:19.046069 CBT Training : PASS
9127 11:36:19.048454 Write leveling : PASS
9128 11:36:19.051605 RX DQS gating : PASS
9129 11:36:19.052067 RX DQ/DQS(RDDQC) : PASS
9130 11:36:19.055189 TX DQ/DQS : PASS
9131 11:36:19.058569 RX DATLAT : PASS
9132 11:36:19.059073 RX DQ/DQS(Engine): PASS
9133 11:36:19.062384 TX OE : PASS
9134 11:36:19.062882 All Pass.
9135 11:36:19.063214
9136 11:36:19.065039 CH 1, Rank 0
9137 11:36:19.065461 SW Impedance : PASS
9138 11:36:19.068148 DUTY Scan : NO K
9139 11:36:19.068572 ZQ Calibration : PASS
9140 11:36:19.071899 Jitter Meter : NO K
9141 11:36:19.074976 CBT Training : PASS
9142 11:36:19.075478 Write leveling : PASS
9143 11:36:19.078248 RX DQS gating : PASS
9144 11:36:19.081568 RX DQ/DQS(RDDQC) : PASS
9145 11:36:19.082068 TX DQ/DQS : PASS
9146 11:36:19.084561 RX DATLAT : PASS
9147 11:36:19.087933 RX DQ/DQS(Engine): PASS
9148 11:36:19.088355 TX OE : PASS
9149 11:36:19.091887 All Pass.
9150 11:36:19.092389
9151 11:36:19.092724 CH 1, Rank 1
9152 11:36:19.094588 SW Impedance : PASS
9153 11:36:19.095009 DUTY Scan : NO K
9154 11:36:19.098305 ZQ Calibration : PASS
9155 11:36:19.100959 Jitter Meter : NO K
9156 11:36:19.101400 CBT Training : PASS
9157 11:36:19.104749 Write leveling : PASS
9158 11:36:19.108469 RX DQS gating : PASS
9159 11:36:19.109017 RX DQ/DQS(RDDQC) : PASS
9160 11:36:19.111588 TX DQ/DQS : PASS
9161 11:36:19.114576 RX DATLAT : PASS
9162 11:36:19.115080 RX DQ/DQS(Engine): PASS
9163 11:36:19.117903 TX OE : PASS
9164 11:36:19.118456 All Pass.
9165 11:36:19.118792
9166 11:36:19.120853 DramC Write-DBI on
9167 11:36:19.124937 PER_BANK_REFRESH: Hybrid Mode
9168 11:36:19.125445 TX_TRACKING: ON
9169 11:36:19.134205 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9170 11:36:19.140972 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9171 11:36:19.147751 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9172 11:36:19.151050 [FAST_K] Save calibration result to emmc
9173 11:36:19.154604 sync common calibartion params.
9174 11:36:19.157994 sync cbt_mode0:1, 1:1
9175 11:36:19.160993 dram_init: ddr_geometry: 2
9176 11:36:19.161492 dram_init: ddr_geometry: 2
9177 11:36:19.164198 dram_init: ddr_geometry: 2
9178 11:36:19.167563 0:dram_rank_size:100000000
9179 11:36:19.170823 1:dram_rank_size:100000000
9180 11:36:19.174703 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9181 11:36:19.177560 DFS_SHUFFLE_HW_MODE: ON
9182 11:36:19.180646 dramc_set_vcore_voltage set vcore to 725000
9183 11:36:19.183846 Read voltage for 1600, 0
9184 11:36:19.184346 Vio18 = 0
9185 11:36:19.184674 Vcore = 725000
9186 11:36:19.187029 Vdram = 0
9187 11:36:19.187194 Vddq = 0
9188 11:36:19.187321 Vmddr = 0
9189 11:36:19.190431 switch to 3200 Mbps bootup
9190 11:36:19.194405 [DramcRunTimeConfig]
9191 11:36:19.194913 PHYPLL
9192 11:36:19.195239 DPM_CONTROL_AFTERK: ON
9193 11:36:19.197619 PER_BANK_REFRESH: ON
9194 11:36:19.200378 REFRESH_OVERHEAD_REDUCTION: ON
9195 11:36:19.200798 CMD_PICG_NEW_MODE: OFF
9196 11:36:19.203754 XRTWTW_NEW_MODE: ON
9197 11:36:19.207032 XRTRTR_NEW_MODE: ON
9198 11:36:19.207532 TX_TRACKING: ON
9199 11:36:19.210279 RDSEL_TRACKING: OFF
9200 11:36:19.210703 DQS Precalculation for DVFS: ON
9201 11:36:19.213741 RX_TRACKING: OFF
9202 11:36:19.214293 HW_GATING DBG: ON
9203 11:36:19.216829 ZQCS_ENABLE_LP4: ON
9204 11:36:19.217248 RX_PICG_NEW_MODE: ON
9205 11:36:19.219965 TX_PICG_NEW_MODE: ON
9206 11:36:19.223634 ENABLE_RX_DCM_DPHY: ON
9207 11:36:19.227651 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9208 11:36:19.228154 DUMMY_READ_FOR_TRACKING: OFF
9209 11:36:19.230540 !!! SPM_CONTROL_AFTERK: OFF
9210 11:36:19.233634 !!! SPM could not control APHY
9211 11:36:19.236989 IMPEDANCE_TRACKING: ON
9212 11:36:19.237515 TEMP_SENSOR: ON
9213 11:36:19.241148 HW_SAVE_FOR_SR: OFF
9214 11:36:19.241675 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9215 11:36:19.247308 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9216 11:36:19.247795 Read ODT Tracking: ON
9217 11:36:19.250485 Refresh Rate DeBounce: ON
9218 11:36:19.250986 DFS_NO_QUEUE_FLUSH: ON
9219 11:36:19.253649 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9220 11:36:19.256901 ENABLE_DFS_RUNTIME_MRW: OFF
9221 11:36:19.260123 DDR_RESERVE_NEW_MODE: ON
9222 11:36:19.260543 MR_CBT_SWITCH_FREQ: ON
9223 11:36:19.263517 =========================
9224 11:36:19.283215 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9225 11:36:19.286015 dram_init: ddr_geometry: 2
9226 11:36:19.305036 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9227 11:36:19.307993 dram_init: dram init end (result: 0)
9228 11:36:19.314471 DRAM-K: Full calibration passed in 24557 msecs
9229 11:36:19.317531 MRC: failed to locate region type 0.
9230 11:36:19.318034 DRAM rank0 size:0x100000000,
9231 11:36:19.321187 DRAM rank1 size=0x100000000
9232 11:36:19.331191 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9233 11:36:19.337746 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9234 11:36:19.344437 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9235 11:36:19.351565 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9236 11:36:19.354251 DRAM rank0 size:0x100000000,
9237 11:36:19.357363 DRAM rank1 size=0x100000000
9238 11:36:19.357867 CBMEM:
9239 11:36:19.361057 IMD: root @ 0xfffff000 254 entries.
9240 11:36:19.364392 IMD: root @ 0xffffec00 62 entries.
9241 11:36:19.367130 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9242 11:36:19.374208 WARNING: RO_VPD is uninitialized or empty.
9243 11:36:19.377375 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9244 11:36:19.384842 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9245 11:36:19.397752 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9246 11:36:19.408988 BS: romstage times (exec / console): total (unknown) / 24022 ms
9247 11:36:19.409506
9248 11:36:19.409926
9249 11:36:19.418919 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9250 11:36:19.422301 ARM64: Exception handlers installed.
9251 11:36:19.425591 ARM64: Testing exception
9252 11:36:19.429028 ARM64: Done test exception
9253 11:36:19.429529 Enumerating buses...
9254 11:36:19.432221 Show all devs... Before device enumeration.
9255 11:36:19.435320 Root Device: enabled 1
9256 11:36:19.438667 CPU_CLUSTER: 0: enabled 1
9257 11:36:19.439172 CPU: 00: enabled 1
9258 11:36:19.442226 Compare with tree...
9259 11:36:19.442721 Root Device: enabled 1
9260 11:36:19.444995 CPU_CLUSTER: 0: enabled 1
9261 11:36:19.448239 CPU: 00: enabled 1
9262 11:36:19.448718 Root Device scanning...
9263 11:36:19.452035 scan_static_bus for Root Device
9264 11:36:19.455370 CPU_CLUSTER: 0 enabled
9265 11:36:19.458508 scan_static_bus for Root Device done
9266 11:36:19.462323 scan_bus: bus Root Device finished in 8 msecs
9267 11:36:19.462832 done
9268 11:36:19.468636 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9269 11:36:19.471562 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9270 11:36:19.479007 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9271 11:36:19.481788 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9272 11:36:19.485439 Allocating resources...
9273 11:36:19.488954 Reading resources...
9274 11:36:19.491730 Root Device read_resources bus 0 link: 0
9275 11:36:19.492173 DRAM rank0 size:0x100000000,
9276 11:36:19.494727 DRAM rank1 size=0x100000000
9277 11:36:19.498224 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9278 11:36:19.501859 CPU: 00 missing read_resources
9279 11:36:19.508258 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9280 11:36:19.511395 Root Device read_resources bus 0 link: 0 done
9281 11:36:19.511824 Done reading resources.
9282 11:36:19.517985 Show resources in subtree (Root Device)...After reading.
9283 11:36:19.521689 Root Device child on link 0 CPU_CLUSTER: 0
9284 11:36:19.524665 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 11:36:19.534705 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 11:36:19.535208 CPU: 00
9287 11:36:19.537851 Root Device assign_resources, bus 0 link: 0
9288 11:36:19.541964 CPU_CLUSTER: 0 missing set_resources
9289 11:36:19.547802 Root Device assign_resources, bus 0 link: 0 done
9290 11:36:19.548288 Done setting resources.
9291 11:36:19.554700 Show resources in subtree (Root Device)...After assigning values.
9292 11:36:19.558225 Root Device child on link 0 CPU_CLUSTER: 0
9293 11:36:19.560894 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 11:36:19.571122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 11:36:19.571619 CPU: 00
9296 11:36:19.574944 Done allocating resources.
9297 11:36:19.581152 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9298 11:36:19.581657 Enabling resources...
9299 11:36:19.581989 done.
9300 11:36:19.587847 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9301 11:36:19.588352 Initializing devices...
9302 11:36:19.591264 Root Device init
9303 11:36:19.591772 init hardware done!
9304 11:36:19.594856 0x00000018: ctrlr->caps
9305 11:36:19.597766 52.000 MHz: ctrlr->f_max
9306 11:36:19.598311 0.400 MHz: ctrlr->f_min
9307 11:36:19.600683 0x40ff8080: ctrlr->voltages
9308 11:36:19.604216 sclk: 390625
9309 11:36:19.604642 Bus Width = 1
9310 11:36:19.604971 sclk: 390625
9311 11:36:19.607635 Bus Width = 1
9312 11:36:19.608066 Early init status = 3
9313 11:36:19.614047 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9314 11:36:19.617639 in-header: 03 fc 00 00 01 00 00 00
9315 11:36:19.621117 in-data: 00
9316 11:36:19.623861 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9317 11:36:19.629703 in-header: 03 fd 00 00 00 00 00 00
9318 11:36:19.633001 in-data:
9319 11:36:19.635708 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9320 11:36:19.640567 in-header: 03 fc 00 00 01 00 00 00
9321 11:36:19.643875 in-data: 00
9322 11:36:19.646708 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9323 11:36:19.652458 in-header: 03 fd 00 00 00 00 00 00
9324 11:36:19.655978 in-data:
9325 11:36:19.659052 [SSUSB] Setting up USB HOST controller...
9326 11:36:19.662760 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9327 11:36:19.665992 [SSUSB] phy power-on done.
9328 11:36:19.669524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9329 11:36:19.675854 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9330 11:36:19.678817 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9331 11:36:19.685701 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9332 11:36:19.692219 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9333 11:36:19.698473 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9334 11:36:19.705877 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9335 11:36:19.712211 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9336 11:36:19.714997 SPM: binary array size = 0x9dc
9337 11:36:19.718201 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9338 11:36:19.725590 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9339 11:36:19.731680 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9340 11:36:19.738361 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9341 11:36:19.741720 configure_display: Starting display init
9342 11:36:19.776019 anx7625_power_on_init: Init interface.
9343 11:36:19.779291 anx7625_disable_pd_protocol: Disabled PD feature.
9344 11:36:19.782412 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9345 11:36:19.810804 anx7625_start_dp_work: Secure OCM version=00
9346 11:36:19.813641 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9347 11:36:19.828713 sp_tx_get_edid_block: EDID Block = 1
9348 11:36:19.931551 Extracted contents:
9349 11:36:19.934265 header: 00 ff ff ff ff ff ff 00
9350 11:36:19.937334 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9351 11:36:19.940805 version: 01 04
9352 11:36:19.944293 basic params: 95 1f 11 78 0a
9353 11:36:19.947463 chroma info: 76 90 94 55 54 90 27 21 50 54
9354 11:36:19.950533 established: 00 00 00
9355 11:36:19.957741 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9356 11:36:19.961125 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9357 11:36:19.967460 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 11:36:19.973640 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9359 11:36:19.980641 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9360 11:36:19.983873 extensions: 00
9361 11:36:19.984377 checksum: fb
9362 11:36:19.984712
9363 11:36:19.987295 Manufacturer: IVO Model 57d Serial Number 0
9364 11:36:19.990331 Made week 0 of 2020
9365 11:36:19.993578 EDID version: 1.4
9366 11:36:19.994049 Digital display
9367 11:36:19.996622 6 bits per primary color channel
9368 11:36:19.997057 DisplayPort interface
9369 11:36:20.000006 Maximum image size: 31 cm x 17 cm
9370 11:36:20.003545 Gamma: 220%
9371 11:36:20.003968 Check DPMS levels
9372 11:36:20.010135 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9373 11:36:20.013076 First detailed timing is preferred timing
9374 11:36:20.013499 Established timings supported:
9375 11:36:20.016534 Standard timings supported:
9376 11:36:20.020023 Detailed timings
9377 11:36:20.022997 Hex of detail: 383680a07038204018303c0035ae10000019
9378 11:36:20.030211 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9379 11:36:20.033327 0780 0798 07c8 0820 hborder 0
9380 11:36:20.036842 0438 043b 0447 0458 vborder 0
9381 11:36:20.039790 -hsync -vsync
9382 11:36:20.040214 Did detailed timing
9383 11:36:20.046492 Hex of detail: 000000000000000000000000000000000000
9384 11:36:20.049448 Manufacturer-specified data, tag 0
9385 11:36:20.052777 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9386 11:36:20.056717 ASCII string: InfoVision
9387 11:36:20.059295 Hex of detail: 000000fe00523134304e574635205248200a
9388 11:36:20.062787 ASCII string: R140NWF5 RH
9389 11:36:20.063208 Checksum
9390 11:36:20.066031 Checksum: 0xfb (valid)
9391 11:36:20.069595 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9392 11:36:20.073020 DSI data_rate: 832800000 bps
9393 11:36:20.079669 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9394 11:36:20.082833 anx7625_parse_edid: pixelclock(138800).
9395 11:36:20.086233 hactive(1920), hsync(48), hfp(24), hbp(88)
9396 11:36:20.090191 vactive(1080), vsync(12), vfp(3), vbp(17)
9397 11:36:20.092672 anx7625_dsi_config: config dsi.
9398 11:36:20.098990 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9399 11:36:20.113552 anx7625_dsi_config: success to config DSI
9400 11:36:20.116433 anx7625_dp_start: MIPI phy setup OK.
9401 11:36:20.120156 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9402 11:36:20.123355 mtk_ddp_mode_set invalid vrefresh 60
9403 11:36:20.126235 main_disp_path_setup
9404 11:36:20.126829 ovl_layer_smi_id_en
9405 11:36:20.129831 ovl_layer_smi_id_en
9406 11:36:20.130394 ccorr_config
9407 11:36:20.130725 aal_config
9408 11:36:20.132719 gamma_config
9409 11:36:20.133152 postmask_config
9410 11:36:20.136347 dither_config
9411 11:36:20.139983 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9412 11:36:20.146497 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9413 11:36:20.149383 Root Device init finished in 555 msecs
9414 11:36:20.152651 CPU_CLUSTER: 0 init
9415 11:36:20.159409 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9416 11:36:20.162972 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9417 11:36:20.166355 APU_MBOX 0x190000b0 = 0x10001
9418 11:36:20.169269 APU_MBOX 0x190001b0 = 0x10001
9419 11:36:20.172734 APU_MBOX 0x190005b0 = 0x10001
9420 11:36:20.176672 APU_MBOX 0x190006b0 = 0x10001
9421 11:36:20.179464 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9422 11:36:20.192123 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9423 11:36:20.204900 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9424 11:36:20.211078 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9425 11:36:20.222710 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9426 11:36:20.232197 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9427 11:36:20.235054 CPU_CLUSTER: 0 init finished in 81 msecs
9428 11:36:20.238507 Devices initialized
9429 11:36:20.242442 Show all devs... After init.
9430 11:36:20.242945 Root Device: enabled 1
9431 11:36:20.244850 CPU_CLUSTER: 0: enabled 1
9432 11:36:20.248603 CPU: 00: enabled 1
9433 11:36:20.251401 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9434 11:36:20.254968 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9435 11:36:20.258557 ELOG: NV offset 0x57f000 size 0x1000
9436 11:36:20.264834 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9437 11:36:20.271673 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9438 11:36:20.275216 ELOG: Event(17) added with size 13 at 2024-07-17 11:36:20 UTC
9439 11:36:20.278137 out: cmd=0x121: 03 db 21 01 00 00 00 00
9440 11:36:20.281996 in-header: 03 82 00 00 2c 00 00 00
9441 11:36:20.295103 in-data: bb 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9442 11:36:20.301969 ELOG: Event(A1) added with size 10 at 2024-07-17 11:36:20 UTC
9443 11:36:20.308659 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9444 11:36:20.315677 ELOG: Event(A0) added with size 9 at 2024-07-17 11:36:20 UTC
9445 11:36:20.318685 elog_add_boot_reason: Logged dev mode boot
9446 11:36:20.322253 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9447 11:36:20.325021 Finalize devices...
9448 11:36:20.325523 Devices finalized
9449 11:36:20.331453 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9450 11:36:20.334861 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9451 11:36:20.338289 in-header: 03 07 00 00 08 00 00 00
9452 11:36:20.342020 in-data: aa e4 47 04 13 02 00 00
9453 11:36:20.344885 Chrome EC: UHEPI supported
9454 11:36:20.351222 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9455 11:36:20.355046 in-header: 03 a9 00 00 08 00 00 00
9456 11:36:20.358682 in-data: 84 60 60 08 00 00 00 00
9457 11:36:20.361333 ELOG: Event(91) added with size 10 at 2024-07-17 11:36:20 UTC
9458 11:36:20.367897 Chrome EC: clear events_b mask to 0x0000000020004000
9459 11:36:20.374994 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9460 11:36:20.378638 in-header: 03 fd 00 00 00 00 00 00
9461 11:36:20.379148 in-data:
9462 11:36:20.385203 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9463 11:36:20.388801 Writing coreboot table at 0xffe64000
9464 11:36:20.391314 0. 000000000010a000-0000000000113fff: RAMSTAGE
9465 11:36:20.394788 1. 0000000040000000-00000000400fffff: RAM
9466 11:36:20.397913 2. 0000000040100000-000000004032afff: RAMSTAGE
9467 11:36:20.404873 3. 000000004032b000-00000000545fffff: RAM
9468 11:36:20.408476 4. 0000000054600000-000000005465ffff: BL31
9469 11:36:20.411824 5. 0000000054660000-00000000ffe63fff: RAM
9470 11:36:20.414809 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9471 11:36:20.421343 7. 0000000100000000-000000023fffffff: RAM
9472 11:36:20.421841 Passing 5 GPIOs to payload:
9473 11:36:20.428317 NAME | PORT | POLARITY | VALUE
9474 11:36:20.431358 EC in RW | 0x000000aa | low | undefined
9475 11:36:20.438054 EC interrupt | 0x00000005 | low | undefined
9476 11:36:20.441358 TPM interrupt | 0x000000ab | high | undefined
9477 11:36:20.445082 SD card detect | 0x00000011 | high | undefined
9478 11:36:20.450888 speaker enable | 0x00000093 | high | undefined
9479 11:36:20.454712 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9480 11:36:20.457960 in-header: 03 f9 00 00 02 00 00 00
9481 11:36:20.458523 in-data: 02 00
9482 11:36:20.461149 ADC[4]: Raw value=894451 ID=7
9483 11:36:20.464831 ADC[3]: Raw value=212700 ID=1
9484 11:36:20.465340 RAM Code: 0x71
9485 11:36:20.468113 ADC[6]: Raw value=74722 ID=0
9486 11:36:20.470948 ADC[5]: Raw value=211590 ID=1
9487 11:36:20.471393 SKU Code: 0x1
9488 11:36:20.477537 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 94ef
9489 11:36:20.481068 coreboot table: 964 bytes.
9490 11:36:20.484835 IMD ROOT 0. 0xfffff000 0x00001000
9491 11:36:20.487719 IMD SMALL 1. 0xffffe000 0x00001000
9492 11:36:20.491021 RO MCACHE 2. 0xffffc000 0x00001104
9493 11:36:20.494491 CONSOLE 3. 0xfff7c000 0x00080000
9494 11:36:20.497620 FMAP 4. 0xfff7b000 0x00000452
9495 11:36:20.500988 TIME STAMP 5. 0xfff7a000 0x00000910
9496 11:36:20.504216 VBOOT WORK 6. 0xfff66000 0x00014000
9497 11:36:20.507410 RAMOOPS 7. 0xffe66000 0x00100000
9498 11:36:20.510510 COREBOOT 8. 0xffe64000 0x00002000
9499 11:36:20.510955 IMD small region:
9500 11:36:20.514471 IMD ROOT 0. 0xffffec00 0x00000400
9501 11:36:20.517344 VPD 1. 0xffffeb80 0x0000006c
9502 11:36:20.520229 MMC STATUS 2. 0xffffeb60 0x00000004
9503 11:36:20.527267 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9504 11:36:20.533867 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9505 11:36:20.573990 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9506 11:36:20.576796 Checking segment from ROM address 0x40100000
9507 11:36:20.580863 Checking segment from ROM address 0x4010001c
9508 11:36:20.587372 Loading segment from ROM address 0x40100000
9509 11:36:20.588025 code (compression=0)
9510 11:36:20.597563 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9511 11:36:20.603424 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9512 11:36:20.603857 it's not compressed!
9513 11:36:20.610595 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9514 11:36:20.616700 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9515 11:36:20.633918 Loading segment from ROM address 0x4010001c
9516 11:36:20.634425 Entry Point 0x80000000
9517 11:36:20.637569 Loaded segments
9518 11:36:20.640758 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9519 11:36:20.647565 Jumping to boot code at 0x80000000(0xffe64000)
9520 11:36:20.653898 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9521 11:36:20.660276 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9522 11:36:20.668543 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9523 11:36:20.671965 Checking segment from ROM address 0x40100000
9524 11:36:20.675371 Checking segment from ROM address 0x4010001c
9525 11:36:20.681914 Loading segment from ROM address 0x40100000
9526 11:36:20.682452 code (compression=1)
9527 11:36:20.688776 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9528 11:36:20.698039 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9529 11:36:20.698577 using LZMA
9530 11:36:20.706973 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9531 11:36:20.714153 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9532 11:36:20.716783 Loading segment from ROM address 0x4010001c
9533 11:36:20.717290 Entry Point 0x54601000
9534 11:36:20.719939 Loaded segments
9535 11:36:20.723474 NOTICE: MT8192 bl31_setup
9536 11:36:20.730681 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9537 11:36:20.733539 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9538 11:36:20.737425 WARNING: region 0:
9539 11:36:20.740790 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 11:36:20.741301 WARNING: region 1:
9541 11:36:20.746872 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9542 11:36:20.750422 WARNING: region 2:
9543 11:36:20.753417 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9544 11:36:20.757017 WARNING: region 3:
9545 11:36:20.763143 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 11:36:20.763679 WARNING: region 4:
9547 11:36:20.769870 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9548 11:36:20.770418 WARNING: region 5:
9549 11:36:20.773223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 11:36:20.776917 WARNING: region 6:
9551 11:36:20.779618 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 11:36:20.783295 WARNING: region 7:
9553 11:36:20.786066 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9554 11:36:20.792904 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9555 11:36:20.796247 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9556 11:36:20.803140 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9557 11:36:20.806061 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9558 11:36:20.809754 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9559 11:36:20.816188 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9560 11:36:20.819773 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9561 11:36:20.822560 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9562 11:36:20.829358 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9563 11:36:20.832648 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9564 11:36:20.839501 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9565 11:36:20.842690 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9566 11:36:20.846174 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9567 11:36:20.852947 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9568 11:36:20.856617 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9569 11:36:20.859050 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9570 11:36:20.866398 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9571 11:36:20.869118 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9572 11:36:20.875645 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9573 11:36:20.879101 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9574 11:36:20.882587 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9575 11:36:20.888796 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9576 11:36:20.891945 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9577 11:36:20.898454 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9578 11:36:20.901825 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9579 11:36:20.904736 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9580 11:36:20.911302 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9581 11:36:20.914848 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9582 11:36:20.921498 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9583 11:36:20.924804 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9584 11:36:20.931757 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9585 11:36:20.935081 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9586 11:36:20.938139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9587 11:36:20.941720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9588 11:36:20.948243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9589 11:36:20.951113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9590 11:36:20.954764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9591 11:36:20.958287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9592 11:36:20.964937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9593 11:36:20.968057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9594 11:36:20.971259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9595 11:36:20.974941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9596 11:36:20.981826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9597 11:36:20.984848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9598 11:36:20.988372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9599 11:36:20.991651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9600 11:36:20.998486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9601 11:36:21.001160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9602 11:36:21.004957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9603 11:36:21.011507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9604 11:36:21.014640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9605 11:36:21.021455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9606 11:36:21.024867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9607 11:36:21.031364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9608 11:36:21.034143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9609 11:36:21.040977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9610 11:36:21.044457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9611 11:36:21.047896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9612 11:36:21.054296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9613 11:36:21.058004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9614 11:36:21.064370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9615 11:36:21.067545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9616 11:36:21.074221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9617 11:36:21.077582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9618 11:36:21.083671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9619 11:36:21.087074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9620 11:36:21.094144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9621 11:36:21.096920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9622 11:36:21.100711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9623 11:36:21.106745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9624 11:36:21.110485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9625 11:36:21.116907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9626 11:36:21.120400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9627 11:36:21.127087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9628 11:36:21.130648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9629 11:36:21.133536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9630 11:36:21.140020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9631 11:36:21.143299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9632 11:36:21.149859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9633 11:36:21.153385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9634 11:36:21.160083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9635 11:36:21.163539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9636 11:36:21.169859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9637 11:36:21.173490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9638 11:36:21.176471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9639 11:36:21.183394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9640 11:36:21.186413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9641 11:36:21.192949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9642 11:36:21.196151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9643 11:36:21.203109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9644 11:36:21.206012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9645 11:36:21.212820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9646 11:36:21.216071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9647 11:36:21.219740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9648 11:36:21.226467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9649 11:36:21.229439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9650 11:36:21.235897 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9651 11:36:21.239311 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9652 11:36:21.242429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9653 11:36:21.246071 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9654 11:36:21.252179 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9655 11:36:21.256108 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9656 11:36:21.262460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9657 11:36:21.265549 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9658 11:36:21.269383 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9659 11:36:21.276357 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9660 11:36:21.279015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9661 11:36:21.286299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9662 11:36:21.289625 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9663 11:36:21.292500 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9664 11:36:21.298803 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9665 11:36:21.302436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9666 11:36:21.308921 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9667 11:36:21.312511 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9668 11:36:21.315563 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9669 11:36:21.322167 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9670 11:36:21.325374 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9671 11:36:21.328708 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9672 11:36:21.335413 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9673 11:36:21.338988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9674 11:36:21.342188 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9675 11:36:21.345406 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9676 11:36:21.351752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9677 11:36:21.355235 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9678 11:36:21.358441 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9679 11:36:21.364987 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9680 11:36:21.368561 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9681 11:36:21.375109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9682 11:36:21.378506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9683 11:36:21.381440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9684 11:36:21.388341 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9685 11:36:21.391603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9686 11:36:21.394728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9687 11:36:21.402189 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9688 11:36:21.405212 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9689 11:36:21.412271 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9690 11:36:21.414509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9691 11:36:21.418684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9692 11:36:21.425179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9693 11:36:21.428259 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9694 11:36:21.434514 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9695 11:36:21.437999 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9696 11:36:21.441638 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9697 11:36:21.448080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9698 11:36:21.451427 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9699 11:36:21.457588 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9700 11:36:21.461926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9701 11:36:21.464952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9702 11:36:21.471449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9703 11:36:21.474706 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9704 11:36:21.481299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9705 11:36:21.484447 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9706 11:36:21.487456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9707 11:36:21.494321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9708 11:36:21.497368 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9709 11:36:21.503849 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9710 11:36:21.507403 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9711 11:36:21.510624 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9712 11:36:21.517700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9713 11:36:21.520542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9714 11:36:21.527177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9715 11:36:21.530577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9716 11:36:21.533723 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9717 11:36:21.540285 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9718 11:36:21.543443 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9719 11:36:21.550576 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9720 11:36:21.553571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9721 11:36:21.556938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9722 11:36:21.563503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9723 11:36:21.566886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9724 11:36:21.573359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9725 11:36:21.577008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9726 11:36:21.579827 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9727 11:36:21.586919 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9728 11:36:21.589537 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9729 11:36:21.596813 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9730 11:36:21.599626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9731 11:36:21.603105 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9732 11:36:21.610209 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9733 11:36:21.613430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9734 11:36:21.616292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9735 11:36:21.623001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9736 11:36:21.626320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9737 11:36:21.632965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9738 11:36:21.636235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9739 11:36:21.643174 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9740 11:36:21.645802 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9741 11:36:21.649128 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9742 11:36:21.655677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9743 11:36:21.658708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9744 11:36:21.666085 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9745 11:36:21.668975 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9746 11:36:21.675580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9747 11:36:21.679306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9748 11:36:21.682339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9749 11:36:21.689231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9750 11:36:21.692991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9751 11:36:21.698950 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9752 11:36:21.702668 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9753 11:36:21.705497 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9754 11:36:21.712231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9755 11:36:21.715371 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9756 11:36:21.722147 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9757 11:36:21.725099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9758 11:36:21.731827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9759 11:36:21.735065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9760 11:36:21.738160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9761 11:36:21.745284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9762 11:36:21.748688 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9763 11:36:21.754893 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9764 11:36:21.758263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9765 11:36:21.761833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9766 11:36:21.768112 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9767 11:36:21.771889 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9768 11:36:21.778572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9769 11:36:21.781696 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9770 11:36:21.788745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9771 11:36:21.791841 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9772 11:36:21.794637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9773 11:36:21.801809 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9774 11:36:21.804434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9775 11:36:21.811712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9776 11:36:21.815022 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9777 11:36:21.821120 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9778 11:36:21.824862 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9779 11:36:21.827651 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9780 11:36:21.834895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9781 11:36:21.837382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9782 11:36:21.844319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9783 11:36:21.847492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9784 11:36:21.850778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9785 11:36:21.854229 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9786 11:36:21.857615 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9787 11:36:21.864701 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9788 11:36:21.867602 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9789 11:36:21.874198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9790 11:36:21.877475 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9791 11:36:21.880672 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9792 11:36:21.887283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9793 11:36:21.891029 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9794 11:36:21.893890 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9795 11:36:21.901042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9796 11:36:21.903594 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9797 11:36:21.907187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9798 11:36:21.913896 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9799 11:36:21.917445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9800 11:36:21.923603 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9801 11:36:21.927489 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9802 11:36:21.930067 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9803 11:36:21.936462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9804 11:36:21.940486 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9805 11:36:21.946664 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9806 11:36:21.949766 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9807 11:36:21.953060 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9808 11:36:21.959792 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9809 11:36:21.963120 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9810 11:36:21.966187 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9811 11:36:21.973093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9812 11:36:21.976072 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9813 11:36:21.979705 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9814 11:36:21.986262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9815 11:36:21.989950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9816 11:36:21.996166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9817 11:36:21.999470 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9818 11:36:22.002857 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9819 11:36:22.009238 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9820 11:36:22.012951 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9821 11:36:22.019759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9822 11:36:22.022590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9823 11:36:22.026180 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9824 11:36:22.029537 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9825 11:36:22.032778 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9826 11:36:22.038937 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9827 11:36:22.042422 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9828 11:36:22.046191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9829 11:36:22.049363 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9830 11:36:22.055650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9831 11:36:22.059133 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9832 11:36:22.062372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9833 11:36:22.065769 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9834 11:36:22.072551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9835 11:36:22.075504 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9836 11:36:22.079378 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9837 11:36:22.085903 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9838 11:36:22.088761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9839 11:36:22.095394 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9840 11:36:22.098938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9841 11:36:22.105551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9842 11:36:22.108734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9843 11:36:22.112130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9844 11:36:22.118677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9845 11:36:22.122586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9846 11:36:22.128613 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9847 11:36:22.132151 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9848 11:36:22.135269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9849 11:36:22.141669 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9850 11:36:22.145080 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9851 11:36:22.152382 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9852 11:36:22.155141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9853 11:36:22.158244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9854 11:36:22.165182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9855 11:36:22.168785 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9856 11:36:22.175081 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9857 11:36:22.178257 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9858 11:36:22.184903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9859 11:36:22.188418 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9860 11:36:22.191335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9861 11:36:22.198333 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9862 11:36:22.201529 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9863 11:36:22.208560 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9864 11:36:22.211629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9865 11:36:22.215324 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9866 11:36:22.221442 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9867 11:36:22.224906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9868 11:36:22.231156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9869 11:36:22.234877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9870 11:36:22.238229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9871 11:36:22.244491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9872 11:36:22.248035 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9873 11:36:22.254869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9874 11:36:22.257538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9875 11:36:22.264283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9876 11:36:22.267382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9877 11:36:22.271326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9878 11:36:22.277663 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9879 11:36:22.281254 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9880 11:36:22.287946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9881 11:36:22.290828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9882 11:36:22.297648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9883 11:36:22.300726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9884 11:36:22.304602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9885 11:36:22.310669 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9886 11:36:22.314043 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9887 11:36:22.320638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9888 11:36:22.324167 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9889 11:36:22.327264 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9890 11:36:22.334173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9891 11:36:22.336924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9892 11:36:22.344006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9893 11:36:22.347083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9894 11:36:22.350894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9895 11:36:22.356917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9896 11:36:22.360869 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9897 11:36:22.366796 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9898 11:36:22.370314 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9899 11:36:22.373560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9900 11:36:22.380118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9901 11:36:22.383645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9902 11:36:22.390178 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9903 11:36:22.393627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9904 11:36:22.400465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9905 11:36:22.403196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9906 11:36:22.406626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9907 11:36:22.413432 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9908 11:36:22.416793 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9909 11:36:22.423176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9910 11:36:22.426680 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9911 11:36:22.433427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9912 11:36:22.436890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9913 11:36:22.439608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9914 11:36:22.446388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9915 11:36:22.449498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9916 11:36:22.455940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9917 11:36:22.459290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9918 11:36:22.466764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9919 11:36:22.470054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9920 11:36:22.476171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9921 11:36:22.479815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9922 11:36:22.483049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9923 11:36:22.489708 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9924 11:36:22.492936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9925 11:36:22.499421 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9926 11:36:22.502684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9927 11:36:22.509600 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9928 11:36:22.512900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9929 11:36:22.516107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9930 11:36:22.522782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9931 11:36:22.525897 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9932 11:36:22.532586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9933 11:36:22.535715 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9934 11:36:22.542921 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9935 11:36:22.545484 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9936 11:36:22.552830 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9937 11:36:22.555355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9938 11:36:22.558773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9939 11:36:22.565960 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9940 11:36:22.568950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9941 11:36:22.575278 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9942 11:36:22.578578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9943 11:36:22.584827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9944 11:36:22.588528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9945 11:36:22.595749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9946 11:36:22.598170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9947 11:36:22.601692 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9948 11:36:22.608440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9949 11:36:22.611242 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9950 11:36:22.618252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9951 11:36:22.621644 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9952 11:36:22.628118 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9953 11:36:22.631697 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9954 11:36:22.638248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9955 11:36:22.641335 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9956 11:36:22.644740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9957 11:36:22.651141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9958 11:36:22.654804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9959 11:36:22.661123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9960 11:36:22.664638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9961 11:36:22.671045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9962 11:36:22.674583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9963 11:36:22.681394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9964 11:36:22.684193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9965 11:36:22.690948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9966 11:36:22.694616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9967 11:36:22.697867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9968 11:36:22.703959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9969 11:36:22.707396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9970 11:36:22.713768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9971 11:36:22.717584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9972 11:36:22.724222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9973 11:36:22.727030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9974 11:36:22.734262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9975 11:36:22.736704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9976 11:36:22.743665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9977 11:36:22.746627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9978 11:36:22.753646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9979 11:36:22.756657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9980 11:36:22.763477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9981 11:36:22.769807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9982 11:36:22.773676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9983 11:36:22.779815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9984 11:36:22.783265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9985 11:36:22.789846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9986 11:36:22.793370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9987 11:36:22.799574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9988 11:36:22.802968 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9989 11:36:22.806341 INFO: [APUAPC] vio 0
9990 11:36:22.809683 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9991 11:36:22.812412 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9992 11:36:22.816032 INFO: [APUAPC] D0_APC_0: 0x400510
9993 11:36:22.819292 INFO: [APUAPC] D0_APC_1: 0x0
9994 11:36:22.822664 INFO: [APUAPC] D0_APC_2: 0x1540
9995 11:36:22.825589 INFO: [APUAPC] D0_APC_3: 0x0
9996 11:36:22.829014 INFO: [APUAPC] D1_APC_0: 0xffffffff
9997 11:36:22.832873 INFO: [APUAPC] D1_APC_1: 0xffffffff
9998 11:36:22.835676 INFO: [APUAPC] D1_APC_2: 0x3fffff
9999 11:36:22.839259 INFO: [APUAPC] D1_APC_3: 0x0
10000 11:36:22.842229 INFO: [APUAPC] D2_APC_0: 0xffffffff
10001 11:36:22.846355 INFO: [APUAPC] D2_APC_1: 0xffffffff
10002 11:36:22.849354 INFO: [APUAPC] D2_APC_2: 0x3fffff
10003 11:36:22.852588 INFO: [APUAPC] D2_APC_3: 0x0
10004 11:36:22.856023 INFO: [APUAPC] D3_APC_0: 0xffffffff
10005 11:36:22.859660 INFO: [APUAPC] D3_APC_1: 0xffffffff
10006 11:36:22.862505 INFO: [APUAPC] D3_APC_2: 0x3fffff
10007 11:36:22.866023 INFO: [APUAPC] D3_APC_3: 0x0
10008 11:36:22.868832 INFO: [APUAPC] D4_APC_0: 0xffffffff
10009 11:36:22.872887 INFO: [APUAPC] D4_APC_1: 0xffffffff
10010 11:36:22.875633 INFO: [APUAPC] D4_APC_2: 0x3fffff
10011 11:36:22.879310 INFO: [APUAPC] D4_APC_3: 0x0
10012 11:36:22.882692 INFO: [APUAPC] D5_APC_0: 0xffffffff
10013 11:36:22.886080 INFO: [APUAPC] D5_APC_1: 0xffffffff
10014 11:36:22.889059 INFO: [APUAPC] D5_APC_2: 0x3fffff
10015 11:36:22.892608 INFO: [APUAPC] D5_APC_3: 0x0
10016 11:36:22.895626 INFO: [APUAPC] D6_APC_0: 0xffffffff
10017 11:36:22.898970 INFO: [APUAPC] D6_APC_1: 0xffffffff
10018 11:36:22.902748 INFO: [APUAPC] D6_APC_2: 0x3fffff
10019 11:36:22.905511 INFO: [APUAPC] D6_APC_3: 0x0
10020 11:36:22.908356 INFO: [APUAPC] D7_APC_0: 0xffffffff
10021 11:36:22.912597 INFO: [APUAPC] D7_APC_1: 0xffffffff
10022 11:36:22.915587 INFO: [APUAPC] D7_APC_2: 0x3fffff
10023 11:36:22.918769 INFO: [APUAPC] D7_APC_3: 0x0
10024 11:36:22.921944 INFO: [APUAPC] D8_APC_0: 0xffffffff
10025 11:36:22.925603 INFO: [APUAPC] D8_APC_1: 0xffffffff
10026 11:36:22.928278 INFO: [APUAPC] D8_APC_2: 0x3fffff
10027 11:36:22.931481 INFO: [APUAPC] D8_APC_3: 0x0
10028 11:36:22.934794 INFO: [APUAPC] D9_APC_0: 0xffffffff
10029 11:36:22.938698 INFO: [APUAPC] D9_APC_1: 0xffffffff
10030 11:36:22.941607 INFO: [APUAPC] D9_APC_2: 0x3fffff
10031 11:36:22.944663 INFO: [APUAPC] D9_APC_3: 0x0
10032 11:36:22.948594 INFO: [APUAPC] D10_APC_0: 0xffffffff
10033 11:36:22.951809 INFO: [APUAPC] D10_APC_1: 0xffffffff
10034 11:36:22.954948 INFO: [APUAPC] D10_APC_2: 0x3fffff
10035 11:36:22.957944 INFO: [APUAPC] D10_APC_3: 0x0
10036 11:36:22.961508 INFO: [APUAPC] D11_APC_0: 0xffffffff
10037 11:36:22.964764 INFO: [APUAPC] D11_APC_1: 0xffffffff
10038 11:36:22.967941 INFO: [APUAPC] D11_APC_2: 0x3fffff
10039 11:36:22.971624 INFO: [APUAPC] D11_APC_3: 0x0
10040 11:36:22.974752 INFO: [APUAPC] D12_APC_0: 0xffffffff
10041 11:36:22.978557 INFO: [APUAPC] D12_APC_1: 0xffffffff
10042 11:36:22.981323 INFO: [APUAPC] D12_APC_2: 0x3fffff
10043 11:36:22.984943 INFO: [APUAPC] D12_APC_3: 0x0
10044 11:36:22.988290 INFO: [APUAPC] D13_APC_0: 0xffffffff
10045 11:36:22.991246 INFO: [APUAPC] D13_APC_1: 0xffffffff
10046 11:36:22.994377 INFO: [APUAPC] D13_APC_2: 0x3fffff
10047 11:36:22.998081 INFO: [APUAPC] D13_APC_3: 0x0
10048 11:36:23.001512 INFO: [APUAPC] D14_APC_0: 0xffffffff
10049 11:36:23.004246 INFO: [APUAPC] D14_APC_1: 0xffffffff
10050 11:36:23.007604 INFO: [APUAPC] D14_APC_2: 0x3fffff
10051 11:36:23.011470 INFO: [APUAPC] D14_APC_3: 0x0
10052 11:36:23.014631 INFO: [APUAPC] D15_APC_0: 0xffffffff
10053 11:36:23.018297 INFO: [APUAPC] D15_APC_1: 0xffffffff
10054 11:36:23.021145 INFO: [APUAPC] D15_APC_2: 0x3fffff
10055 11:36:23.024742 INFO: [APUAPC] D15_APC_3: 0x0
10056 11:36:23.028465 INFO: [APUAPC] APC_CON: 0x4
10057 11:36:23.031303 INFO: [NOCDAPC] D0_APC_0: 0x0
10058 11:36:23.031725 INFO: [NOCDAPC] D0_APC_1: 0x0
10059 11:36:23.034414 INFO: [NOCDAPC] D1_APC_0: 0x0
10060 11:36:23.038030 INFO: [NOCDAPC] D1_APC_1: 0xfff
10061 11:36:23.040864 INFO: [NOCDAPC] D2_APC_0: 0x0
10062 11:36:23.043929 INFO: [NOCDAPC] D2_APC_1: 0xfff
10063 11:36:23.047648 INFO: [NOCDAPC] D3_APC_0: 0x0
10064 11:36:23.051248 INFO: [NOCDAPC] D3_APC_1: 0xfff
10065 11:36:23.054012 INFO: [NOCDAPC] D4_APC_0: 0x0
10066 11:36:23.057412 INFO: [NOCDAPC] D4_APC_1: 0xfff
10067 11:36:23.060849 INFO: [NOCDAPC] D5_APC_0: 0x0
10068 11:36:23.063968 INFO: [NOCDAPC] D5_APC_1: 0xfff
10069 11:36:23.064463 INFO: [NOCDAPC] D6_APC_0: 0x0
10070 11:36:23.067206 INFO: [NOCDAPC] D6_APC_1: 0xfff
10071 11:36:23.070924 INFO: [NOCDAPC] D7_APC_0: 0x0
10072 11:36:23.073858 INFO: [NOCDAPC] D7_APC_1: 0xfff
10073 11:36:23.077504 INFO: [NOCDAPC] D8_APC_0: 0x0
10074 11:36:23.080283 INFO: [NOCDAPC] D8_APC_1: 0xfff
10075 11:36:23.083827 INFO: [NOCDAPC] D9_APC_0: 0x0
10076 11:36:23.087529 INFO: [NOCDAPC] D9_APC_1: 0xfff
10077 11:36:23.090336 INFO: [NOCDAPC] D10_APC_0: 0x0
10078 11:36:23.093949 INFO: [NOCDAPC] D10_APC_1: 0xfff
10079 11:36:23.097267 INFO: [NOCDAPC] D11_APC_0: 0x0
10080 11:36:23.100299 INFO: [NOCDAPC] D11_APC_1: 0xfff
10081 11:36:23.100729 INFO: [NOCDAPC] D12_APC_0: 0x0
10082 11:36:23.103614 INFO: [NOCDAPC] D12_APC_1: 0xfff
10083 11:36:23.106620 INFO: [NOCDAPC] D13_APC_0: 0x0
10084 11:36:23.109923 INFO: [NOCDAPC] D13_APC_1: 0xfff
10085 11:36:23.113766 INFO: [NOCDAPC] D14_APC_0: 0x0
10086 11:36:23.117007 INFO: [NOCDAPC] D14_APC_1: 0xfff
10087 11:36:23.120249 INFO: [NOCDAPC] D15_APC_0: 0x0
10088 11:36:23.123838 INFO: [NOCDAPC] D15_APC_1: 0xfff
10089 11:36:23.126680 INFO: [NOCDAPC] APC_CON: 0x4
10090 11:36:23.130477 INFO: [APUAPC] set_apusys_apc done
10091 11:36:23.133778 INFO: [DEVAPC] devapc_init done
10092 11:36:23.136330 INFO: GICv3 without legacy support detected.
10093 11:36:23.140256 INFO: ARM GICv3 driver initialized in EL3
10094 11:36:23.143184 INFO: Maximum SPI INTID supported: 639
10095 11:36:23.150018 INFO: BL31: Initializing runtime services
10096 11:36:23.153728 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10097 11:36:23.156608 INFO: SPM: enable CPC mode
10098 11:36:23.163411 INFO: mcdi ready for mcusys-off-idle and system suspend
10099 11:36:23.166656 INFO: BL31: Preparing for EL3 exit to normal world
10100 11:36:23.169684 INFO: Entry point address = 0x80000000
10101 11:36:23.173177 INFO: SPSR = 0x8
10102 11:36:23.178908
10103 11:36:23.179409
10104 11:36:23.179738
10105 11:36:23.181800 Starting depthcharge on Spherion...
10106 11:36:23.182342
10107 11:36:23.182673 Wipe memory regions:
10108 11:36:23.182975
10109 11:36:23.185726 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10110 11:36:23.186281 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10111 11:36:23.186698 Setting prompt string to ['asurada:']
10112 11:36:23.187057 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10113 11:36:23.187899 [0x00000040000000, 0x00000054600000)
10114 11:36:23.307420
10115 11:36:23.307905 [0x00000054660000, 0x00000080000000)
10116 11:36:23.568436
10117 11:36:23.568938 [0x000000821a7280, 0x000000ffe64000)
10118 11:36:24.313388
10119 11:36:24.314077 [0x00000100000000, 0x00000240000000)
10120 11:36:26.203361
10121 11:36:26.206457 Initializing XHCI USB controller at 0x11200000.
10122 11:36:27.244599
10123 11:36:27.247857 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10124 11:36:27.248282
10125 11:36:27.248612
10126 11:36:27.249315 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 11:36:27.249701 Sending line: 'tftpboot 192.168.201.1 14864619/tftp-deploy-s5l1j54j/kernel/image.itb 14864619/tftp-deploy-s5l1j54j/kernel/cmdline '
10129 11:36:27.351345 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10130 11:36:27.351783 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10131 11:36:27.356556 asurada: tftpboot 192.168.201.1 14864619/tftp-deploy-s5l1j54j/kernel/image.ittp-deploy-s5l1j54j/kernel/cmdline
10132 11:36:27.357068
10133 11:36:27.357400 Waiting for link
10134 11:36:27.514883
10135 11:36:27.515588 R8152: Initializing
10136 11:36:27.515944
10137 11:36:27.517985 Version 6 (ocp_data = 5c30)
10138 11:36:27.518479
10139 11:36:27.521095 R8152: Done initializing
10140 11:36:27.521515
10141 11:36:27.521947 Adding net device
10142 11:36:29.455186
10143 11:36:29.455676 done.
10144 11:36:29.456124
10145 11:36:29.456620 MAC: 00:24:32:30:78:ff
10146 11:36:29.456946
10147 11:36:29.458487 Sending DHCP discover... done.
10148 11:36:29.458909
10149 11:36:39.633674 Waiting for reply... R8152: Bulk read error 0xffffffbf
10150 11:36:39.634251
10151 11:36:39.636763 Receive failed.
10152 11:36:39.637192
10153 11:36:39.637518 done.
10154 11:36:39.637814
10155 11:36:39.640134 Sending DHCP request... done.
10156 11:36:39.640551
10157 11:36:39.646476 Waiting for reply... done.
10158 11:36:39.646642
10159 11:36:39.646776 My ip is 192.168.201.21
10160 11:36:39.646918
10161 11:36:39.649890 The DHCP server ip is 192.168.201.1
10162 11:36:39.650186
10163 11:36:39.656302 TFTP server IP predefined by user: 192.168.201.1
10164 11:36:39.656611
10165 11:36:39.663246 Bootfile predefined by user: 14864619/tftp-deploy-s5l1j54j/kernel/image.itb
10166 11:36:39.663711
10167 11:36:39.666512 Sending tftp read request... done.
10168 11:36:39.666936
10169 11:36:39.674232 Waiting for the transfer...
10170 11:36:39.674735
10171 11:36:40.403892 00000000 ################################################################
10172 11:36:40.404422
10173 11:36:41.134495 00080000 ################################################################
10174 11:36:41.135029
10175 11:36:41.846959 00100000 ################################################################
10176 11:36:41.847705
10177 11:36:42.595490 00180000 ################################################################
10178 11:36:42.596027
10179 11:36:43.330669 00200000 ################################################################
10180 11:36:43.331193
10181 11:36:44.046492 00280000 ################################################################
10182 11:36:44.046993
10183 11:36:44.772773 00300000 ################################################################
10184 11:36:44.773274
10185 11:36:45.486840 00380000 ################################################################
10186 11:36:45.487405
10187 11:36:46.159393 00400000 ################################################################
10188 11:36:46.159847
10189 11:36:46.870327 00480000 ################################################################
10190 11:36:46.870801
10191 11:36:47.594790 00500000 ################################################################
10192 11:36:47.595286
10193 11:36:48.323223 00580000 ################################################################
10194 11:36:48.323761
10195 11:36:49.048511 00600000 ################################################################
10196 11:36:49.049032
10197 11:36:49.776904 00680000 ################################################################
10198 11:36:49.777362
10199 11:36:50.523042 00700000 ################################################################
10200 11:36:50.523567
10201 11:36:51.252718 00780000 ################################################################
10202 11:36:51.253387
10203 11:36:51.981363 00800000 ################################################################
10204 11:36:51.981922
10205 11:36:52.706285 00880000 ################################################################
10206 11:36:52.706793
10207 11:36:53.431029 00900000 ################################################################
10208 11:36:53.431515
10209 11:36:54.132112 00980000 ################################################################
10210 11:36:54.132566
10211 11:36:54.857386 00a00000 ################################################################
10212 11:36:54.857845
10213 11:36:55.583165 00a80000 ################################################################
10214 11:36:55.583622
10215 11:36:56.296813 00b00000 ################################################################
10216 11:36:56.297346
10217 11:36:57.018131 00b80000 ################################################################
10218 11:36:57.018658
10219 11:36:57.744040 00c00000 ################################################################
10220 11:36:57.744586
10221 11:36:58.452872 00c80000 ################################################################
10222 11:36:58.453361
10223 11:36:59.151166 00d00000 ################################################################
10224 11:36:59.151623
10225 11:36:59.868634 00d80000 ################################################################
10226 11:36:59.869137
10227 11:37:00.594082 00e00000 ################################################################
10228 11:37:00.594649
10229 11:37:01.310006 00e80000 ################################################################
10230 11:37:01.310501
10231 11:37:02.029960 00f00000 ################################################################
10232 11:37:02.030528
10233 11:37:02.755954 00f80000 ################################################################
10234 11:37:02.756453
10235 11:37:03.479100 01000000 ################################################################
10236 11:37:03.479654
10237 11:37:04.197282 01080000 ################################################################
10238 11:37:04.197800
10239 11:37:04.926896 01100000 ################################################################
10240 11:37:04.927417
10241 11:37:05.654478 01180000 ################################################################
10242 11:37:05.655004
10243 11:37:06.370386 01200000 ################################################################
10244 11:37:06.370973
10245 11:37:07.105491 01280000 ################################################################
10246 11:37:07.106024
10247 11:37:07.833269 01300000 ################################################################
10248 11:37:07.833799
10249 11:37:08.559511 01380000 ################################################################
10250 11:37:08.560066
10251 11:37:09.283627 01400000 ################################################################
10252 11:37:09.284145
10253 11:37:10.003162 01480000 ################################################################
10254 11:37:10.003726
10255 11:37:10.725412 01500000 ################################################################
10256 11:37:10.725920
10257 11:37:11.448080 01580000 ################################################################
10258 11:37:11.448605
10259 11:37:12.167552 01600000 ################################################################
10260 11:37:12.168014
10261 11:37:12.891373 01680000 ################################################################
10262 11:37:12.891906
10263 11:37:13.605875 01700000 ################################################################
10264 11:37:13.606542
10265 11:37:14.326666 01780000 ################################################################
10266 11:37:14.327187
10267 11:37:15.040414 01800000 ################################################################
10268 11:37:15.040948
10269 11:37:15.756392 01880000 ################################################################
10270 11:37:15.756926
10271 11:37:16.463941 01900000 ################################################################
10272 11:37:16.464476
10273 11:37:17.185514 01980000 ################################################################
10274 11:37:17.186050
10275 11:37:17.923642 01a00000 ################################################################
10276 11:37:17.924163
10277 11:37:18.663564 01a80000 ################################################################
10278 11:37:18.664101
10279 11:37:19.380395 01b00000 ################################################################
10280 11:37:19.380975
10281 11:37:20.122944 01b80000 ################################################################
10282 11:37:20.123571
10283 11:37:20.846269 01c00000 ################################################################
10284 11:37:20.846943
10285 11:37:21.584988 01c80000 ################################################################
10286 11:37:21.585485
10287 11:37:22.321907 01d00000 ################################################################
10288 11:37:22.322446
10289 11:37:23.037751 01d80000 ################################################################
10290 11:37:23.038251
10291 11:37:23.639458 01e00000 ##################################################### done.
10292 11:37:23.639977
10293 11:37:23.642343 The bootfile was 31885282 bytes long.
10294 11:37:23.642801
10295 11:37:23.645839 Sending tftp read request... done.
10296 11:37:23.646298
10297 11:37:23.652616 Waiting for the transfer...
10298 11:37:23.653040
10299 11:37:23.653370 00000000 # done.
10300 11:37:23.653685
10301 11:37:23.659626 Command line loaded dynamically from TFTP file: 14864619/tftp-deploy-s5l1j54j/kernel/cmdline
10302 11:37:23.660238
10303 11:37:23.682677 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10304 11:37:23.683201
10305 11:37:23.683537 Loading FIT.
10306 11:37:23.686427
10307 11:37:23.686813 Image ramdisk-1 has 18717702 bytes.
10308 11:37:23.687126
10309 11:37:23.689284 Image fdt-1 has 47258 bytes.
10310 11:37:23.689716
10311 11:37:23.692683 Image kernel-1 has 13118294 bytes.
10312 11:37:23.693386
10313 11:37:23.702547 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 11:37:23.702936
10315 11:37:23.718692 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 11:37:23.719316
10317 11:37:23.725430 Choosing best match conf-1 for compat google,spherion-rev2.
10318 11:37:23.728899
10319 11:37:23.733543 Connected to device vid:did:rid of 1ae0:0028:00
10320 11:37:23.740552
10321 11:37:23.744224 tpm_get_response: command 0x17b, return code 0x0
10322 11:37:23.744608
10323 11:37:23.746861 ec_init: CrosEC protocol v3 supported (256, 248)
10324 11:37:23.752679
10325 11:37:23.756279 tpm_cleanup: add release locality here.
10326 11:37:23.756751
10327 11:37:23.757161 Shutting down all USB controllers.
10328 11:37:23.759384
10329 11:37:23.759885 Removing current net device
10330 11:37:23.760374
10331 11:37:23.765738 Exiting depthcharge with code 4 at timestamp: 89925600
10332 11:37:23.766343
10333 11:37:23.769086 LZMA decompressing kernel-1 to 0x821a6718
10334 11:37:23.769468
10335 11:37:23.772713 LZMA decompressing kernel-1 to 0x40000000
10336 11:37:25.386897
10337 11:37:25.387394 jumping to kernel
10338 11:37:25.389721 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10339 11:37:25.390276 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10340 11:37:25.390591 Setting prompt string to ['Linux version [0-9]']
10341 11:37:25.390726 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 11:37:25.390859 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 11:37:25.467947
10344 11:37:25.470976 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 11:37:25.474546 start: 2.2.5.1 login-action (timeout 00:03:18) [common]
10346 11:37:25.475132 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 11:37:25.475501 Setting prompt string to []
10348 11:37:25.475907 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10349 11:37:25.476285 Using line separator: #'\n'#
10350 11:37:25.476585 No login prompt set.
10351 11:37:25.476911 Parsing kernel messages
10352 11:37:25.477244 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10353 11:37:25.477780 [login-action] Waiting for messages, (timeout 00:03:18)
10354 11:37:25.478096 Waiting using forced prompt support (timeout 00:01:39)
10355 11:37:25.494203 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10356 11:37:25.497682 [ 0.000000] random: crng init done
10357 11:37:25.500620 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10358 11:37:25.504255 [ 0.000000] efi: UEFI not found.
10359 11:37:25.514324 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10360 11:37:25.520586 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10361 11:37:25.530809 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10362 11:37:25.540273 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10363 11:37:25.547021 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 11:37:25.550171 [ 0.000000] printk: bootconsole [mtk8250] enabled
10365 11:37:25.558761 [ 0.000000] NUMA: No NUMA configuration found
10366 11:37:25.565329 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 11:37:25.572245 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10368 11:37:25.572834 [ 0.000000] Zone ranges:
10369 11:37:25.578176 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 11:37:25.581541 [ 0.000000] DMA32 empty
10371 11:37:25.588209 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 11:37:25.591868 [ 0.000000] Movable zone start for each node
10373 11:37:25.594849 [ 0.000000] Early memory node ranges
10374 11:37:25.601386 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 11:37:25.608497 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 11:37:25.614526 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 11:37:25.622175 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 11:37:25.628163 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 11:37:25.634243 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 11:37:25.692337 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 11:37:25.698593 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 11:37:25.705257 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10383 11:37:25.708892 [ 0.000000] psci: probing for conduit method from DT.
10384 11:37:25.715321 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 11:37:25.718390 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 11:37:25.725208 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 11:37:25.728115 [ 0.000000] psci: SMC Calling Convention v1.2
10388 11:37:25.735393 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10389 11:37:25.738450 [ 0.000000] Detected VIPT I-cache on CPU0
10390 11:37:25.744702 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 11:37:25.751388 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 11:37:25.758648 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 11:37:25.765258 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 11:37:25.775022 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10395 11:37:25.781570 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10396 11:37:25.784886 [ 0.000000] alternatives: applying boot alternatives
10397 11:37:25.791465 [ 0.000000] Fallback order for Node 0: 0
10398 11:37:25.798086 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10399 11:37:25.801288 [ 0.000000] Policy zone: Normal
10400 11:37:25.823952 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10401 11:37:25.834473 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10402 11:37:25.845376 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10403 11:37:25.855977 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10404 11:37:25.862260 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10405 11:37:25.865337 <6>[ 0.000000] software IO TLB: area num 8.
10406 11:37:25.922579 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10407 11:37:26.071848 <6>[ 0.000000] Memory: 7945780K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406988K reserved, 32768K cma-reserved)
10408 11:37:26.078869 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10409 11:37:26.085002 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10410 11:37:26.088274 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10411 11:37:26.094618 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10412 11:37:26.101587 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10413 11:37:26.105336 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10414 11:37:26.114900 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10415 11:37:26.121206 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10416 11:37:26.127894 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10417 11:37:26.134560 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10418 11:37:26.137864 <6>[ 0.000000] GICv3: 608 SPIs implemented
10419 11:37:26.141181 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10420 11:37:26.147970 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10421 11:37:26.151065 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10422 11:37:26.157719 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10423 11:37:26.171194 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10424 11:37:26.184334 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10425 11:37:26.190817 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10426 11:37:26.198450 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10427 11:37:26.211528 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10428 11:37:26.218456 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10429 11:37:26.224997 <6>[ 0.009230] Console: colour dummy device 80x25
10430 11:37:26.235244 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10431 11:37:26.241585 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10432 11:37:26.245325 <6>[ 0.029274] LSM: Security Framework initializing
10433 11:37:26.251785 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 11:37:26.261267 <6>[ 0.042028] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 11:37:26.271227 <6>[ 0.051501] cblist_init_generic: Setting adjustable number of callback queues.
10436 11:37:26.274703 <6>[ 0.058988] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 11:37:26.284890 <6>[ 0.065327] cblist_init_generic: Setting adjustable number of callback queues.
10438 11:37:26.291037 <6>[ 0.072800] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 11:37:26.294734 <6>[ 0.079203] rcu: Hierarchical SRCU implementation.
10440 11:37:26.300860 <6>[ 0.084217] rcu: Max phase no-delay instances is 1000.
10441 11:37:26.307564 <6>[ 0.091248] EFI services will not be available.
10442 11:37:26.310996 <6>[ 0.096236] smp: Bringing up secondary CPUs ...
10443 11:37:26.319568 <6>[ 0.101283] Detected VIPT I-cache on CPU1
10444 11:37:26.326300 <6>[ 0.101355] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10445 11:37:26.333207 <6>[ 0.101385] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10446 11:37:26.336121 <6>[ 0.101730] Detected VIPT I-cache on CPU2
10447 11:37:26.342698 <6>[ 0.101784] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10448 11:37:26.352797 <6>[ 0.101802] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10449 11:37:26.355980 <6>[ 0.102066] Detected VIPT I-cache on CPU3
10450 11:37:26.362317 <6>[ 0.102114] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10451 11:37:26.369454 <6>[ 0.102129] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10452 11:37:26.372707 <6>[ 0.102434] CPU features: detected: Spectre-v4
10453 11:37:26.379438 <6>[ 0.102439] CPU features: detected: Spectre-BHB
10454 11:37:26.382696 <6>[ 0.102444] Detected PIPT I-cache on CPU4
10455 11:37:26.388986 <6>[ 0.102495] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10456 11:37:26.395361 <6>[ 0.102510] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10457 11:37:26.402755 <6>[ 0.102792] Detected PIPT I-cache on CPU5
10458 11:37:26.408835 <6>[ 0.102848] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10459 11:37:26.415512 <6>[ 0.102864] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10460 11:37:26.418974 <6>[ 0.103146] Detected PIPT I-cache on CPU6
10461 11:37:26.425698 <6>[ 0.103212] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10462 11:37:26.432151 <6>[ 0.103228] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10463 11:37:26.438817 <6>[ 0.103524] Detected PIPT I-cache on CPU7
10464 11:37:26.445469 <6>[ 0.103589] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10465 11:37:26.451705 <6>[ 0.103605] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10466 11:37:26.455226 <6>[ 0.103652] smp: Brought up 1 node, 8 CPUs
10467 11:37:26.461747 <6>[ 0.245089] SMP: Total of 8 processors activated.
10468 11:37:26.464909 <6>[ 0.250040] CPU features: detected: 32-bit EL0 Support
10469 11:37:26.474815 <6>[ 0.255404] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10470 11:37:26.481227 <6>[ 0.264204] CPU features: detected: Common not Private translations
10471 11:37:26.487669 <6>[ 0.270680] CPU features: detected: CRC32 instructions
10472 11:37:26.491780 <6>[ 0.276031] CPU features: detected: RCpc load-acquire (LDAPR)
10473 11:37:26.498086 <6>[ 0.281991] CPU features: detected: LSE atomic instructions
10474 11:37:26.504811 <6>[ 0.287773] CPU features: detected: Privileged Access Never
10475 11:37:26.511274 <6>[ 0.293552] CPU features: detected: RAS Extension Support
10476 11:37:26.517984 <6>[ 0.299195] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10477 11:37:26.520985 <6>[ 0.306414] CPU: All CPU(s) started at EL2
10478 11:37:26.527882 <6>[ 0.310731] alternatives: applying system-wide alternatives
10479 11:37:26.537391 <6>[ 0.321623] devtmpfs: initialized
10480 11:37:26.552497 <6>[ 0.330453] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10481 11:37:26.559319 <6>[ 0.340411] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10482 11:37:26.566080 <6>[ 0.348654] pinctrl core: initialized pinctrl subsystem
10483 11:37:26.569792 <6>[ 0.355353] DMI not present or invalid.
10484 11:37:26.575656 <6>[ 0.359770] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10485 11:37:26.585736 <6>[ 0.366671] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10486 11:37:26.593043 <6>[ 0.374254] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10487 11:37:26.603134 <6>[ 0.382483] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10488 11:37:26.606051 <6>[ 0.390730] audit: initializing netlink subsys (disabled)
10489 11:37:26.616080 <5>[ 0.396429] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10490 11:37:26.623042 <6>[ 0.397167] thermal_sys: Registered thermal governor 'step_wise'
10491 11:37:26.629399 <6>[ 0.404396] thermal_sys: Registered thermal governor 'power_allocator'
10492 11:37:26.633012 <6>[ 0.410649] cpuidle: using governor menu
10493 11:37:26.638889 <6>[ 0.421611] NET: Registered PF_QIPCRTR protocol family
10494 11:37:26.646149 <6>[ 0.427150] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10495 11:37:26.652445 <6>[ 0.434251] ASID allocator initialised with 32768 entries
10496 11:37:26.655316 <6>[ 0.440855] Serial: AMBA PL011 UART driver
10497 11:37:26.666162 <4>[ 0.450623] Trying to register duplicate clock ID: 134
10498 11:37:26.724711 <6>[ 0.512204] KASLR enabled
10499 11:37:26.739339 <6>[ 0.519864] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10500 11:37:26.745780 <6>[ 0.526877] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10501 11:37:26.752444 <6>[ 0.533369] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10502 11:37:26.758710 <6>[ 0.540375] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10503 11:37:26.765211 <6>[ 0.546862] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10504 11:37:26.772279 <6>[ 0.553866] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10505 11:37:26.778861 <6>[ 0.560354] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10506 11:37:26.785465 <6>[ 0.567357] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10507 11:37:26.789117 <6>[ 0.574888] ACPI: Interpreter disabled.
10508 11:37:26.797036 <6>[ 0.581329] iommu: Default domain type: Translated
10509 11:37:26.803913 <6>[ 0.586440] iommu: DMA domain TLB invalidation policy: strict mode
10510 11:37:26.807223 <5>[ 0.593092] SCSI subsystem initialized
10511 11:37:26.813343 <6>[ 0.597251] usbcore: registered new interface driver usbfs
10512 11:37:26.820428 <6>[ 0.602980] usbcore: registered new interface driver hub
10513 11:37:26.823647 <6>[ 0.608531] usbcore: registered new device driver usb
10514 11:37:26.830504 <6>[ 0.614637] pps_core: LinuxPPS API ver. 1 registered
10515 11:37:26.840618 <6>[ 0.619833] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10516 11:37:26.843604 <6>[ 0.629174] PTP clock support registered
10517 11:37:26.846811 <6>[ 0.633418] EDAC MC: Ver: 3.0.0
10518 11:37:26.854029 <6>[ 0.638580] FPGA manager framework
10519 11:37:26.861129 <6>[ 0.642262] Advanced Linux Sound Architecture Driver Initialized.
10520 11:37:26.863994 <6>[ 0.649055] vgaarb: loaded
10521 11:37:26.871101 <6>[ 0.652237] clocksource: Switched to clocksource arch_sys_counter
10522 11:37:26.874220 <5>[ 0.658679] VFS: Disk quotas dquot_6.6.0
10523 11:37:26.880616 <6>[ 0.662864] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10524 11:37:26.884129 <6>[ 0.670055] pnp: PnP ACPI: disabled
10525 11:37:26.892930 <6>[ 0.676765] NET: Registered PF_INET protocol family
10526 11:37:26.902507 <6>[ 0.682360] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10527 11:37:26.914134 <6>[ 0.694684] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10528 11:37:26.923826 <6>[ 0.703497] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10529 11:37:26.929963 <6>[ 0.711468] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10530 11:37:26.937174 <6>[ 0.720167] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10531 11:37:26.948927 <6>[ 0.729923] TCP: Hash tables configured (established 65536 bind 65536)
10532 11:37:26.955686 <6>[ 0.736790] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 11:37:26.962317 <6>[ 0.743985] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 11:37:26.969345 <6>[ 0.751685] NET: Registered PF_UNIX/PF_LOCAL protocol family
10535 11:37:26.975295 <6>[ 0.757818] RPC: Registered named UNIX socket transport module.
10536 11:37:26.979119 <6>[ 0.763973] RPC: Registered udp transport module.
10537 11:37:26.986004 <6>[ 0.768905] RPC: Registered tcp transport module.
10538 11:37:26.992161 <6>[ 0.773839] RPC: Registered tcp NFSv4.1 backchannel transport module.
10539 11:37:26.995676 <6>[ 0.780505] PCI: CLS 0 bytes, default 64
10540 11:37:26.998971 <6>[ 0.784827] Unpacking initramfs...
10541 11:37:27.015674 <6>[ 0.796748] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10542 11:37:27.026007 <6>[ 0.805392] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10543 11:37:27.028813 <6>[ 0.814234] kvm [1]: IPA Size Limit: 40 bits
10544 11:37:27.035879 <6>[ 0.818756] kvm [1]: GICv3: no GICV resource entry
10545 11:37:27.039284 <6>[ 0.823776] kvm [1]: disabling GICv2 emulation
10546 11:37:27.045871 <6>[ 0.828463] kvm [1]: GIC system register CPU interface enabled
10547 11:37:27.049142 <6>[ 0.834629] kvm [1]: vgic interrupt IRQ18
10548 11:37:27.055606 <6>[ 0.838986] kvm [1]: VHE mode initialized successfully
10549 11:37:27.062238 <5>[ 0.845503] Initialise system trusted keyrings
10550 11:37:27.068848 <6>[ 0.850310] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10551 11:37:27.076230 <6>[ 0.860279] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10552 11:37:27.082739 <5>[ 0.866653] NFS: Registering the id_resolver key type
10553 11:37:27.086362 <5>[ 0.871955] Key type id_resolver registered
10554 11:37:27.092492 <5>[ 0.876371] Key type id_legacy registered
10555 11:37:27.099108 <6>[ 0.880646] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10556 11:37:27.106164 <6>[ 0.887567] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10557 11:37:27.112647 <6>[ 0.895273] 9p: Installing v9fs 9p2000 file system support
10558 11:37:27.149387 <5>[ 0.933616] Key type asymmetric registered
10559 11:37:27.152941 <5>[ 0.937952] Asymmetric key parser 'x509' registered
10560 11:37:27.162693 <6>[ 0.943106] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10561 11:37:27.166461 <6>[ 0.950721] io scheduler mq-deadline registered
10562 11:37:27.169389 <6>[ 0.955498] io scheduler kyber registered
10563 11:37:27.188428 <6>[ 0.972833] EINJ: ACPI disabled.
10564 11:37:27.221621 <4>[ 0.999254] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 11:37:27.231639 <4>[ 1.009888] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 11:37:27.246637 <6>[ 1.031064] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10567 11:37:27.255175 <6>[ 1.039196] printk: console [ttyS0] disabled
10568 11:37:27.282932 <6>[ 1.063833] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10569 11:37:27.289526 <6>[ 1.073317] printk: console [ttyS0] enabled
10570 11:37:27.292848 <6>[ 1.073317] printk: console [ttyS0] enabled
10571 11:37:27.299137 <6>[ 1.082212] printk: bootconsole [mtk8250] disabled
10572 11:37:27.302582 <6>[ 1.082212] printk: bootconsole [mtk8250] disabled
10573 11:37:27.309310 <6>[ 1.093626] SuperH (H)SCI(F) driver initialized
10574 11:37:27.313085 <6>[ 1.098935] msm_serial: driver initialized
10575 11:37:27.326989 <6>[ 1.107953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10576 11:37:27.336716 <6>[ 1.116503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10577 11:37:27.343227 <6>[ 1.125045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10578 11:37:27.353404 <6>[ 1.133672] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10579 11:37:27.363507 <6>[ 1.142378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10580 11:37:27.369950 <6>[ 1.151097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10581 11:37:27.380315 <6>[ 1.159638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10582 11:37:27.386759 <6>[ 1.168444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10583 11:37:27.396738 <6>[ 1.176987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10584 11:37:27.408502 <6>[ 1.192639] loop: module loaded
10585 11:37:27.414937 <6>[ 1.198551] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10586 11:37:27.437260 <4>[ 1.221830] mtk-pmic-keys: Failed to locate of_node [id: -1]
10587 11:37:27.445060 <6>[ 1.228882] megasas: 07.719.03.00-rc1
10588 11:37:27.454284 <6>[ 1.238786] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10589 11:37:27.467677 <6>[ 1.251637] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10590 11:37:27.484441 <6>[ 1.268394] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10591 11:37:27.541315 <6>[ 1.318741] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10592 11:37:27.795920 <6>[ 1.580406] Freeing initrd memory: 18276K
10593 11:37:27.807980 <6>[ 1.592202] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10594 11:37:27.818807 <6>[ 1.603127] tun: Universal TUN/TAP device driver, 1.6
10595 11:37:27.822264 <6>[ 1.609199] thunder_xcv, ver 1.0
10596 11:37:27.826377 <6>[ 1.612703] thunder_bgx, ver 1.0
10597 11:37:27.828919 <6>[ 1.616192] nicpf, ver 1.0
10598 11:37:27.838952 <6>[ 1.620214] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10599 11:37:27.842548 <6>[ 1.627689] hns3: Copyright (c) 2017 Huawei Corporation.
10600 11:37:27.849137 <6>[ 1.633276] hclge is initializing
10601 11:37:27.852321 <6>[ 1.636851] e1000: Intel(R) PRO/1000 Network Driver
10602 11:37:27.859281 <6>[ 1.641980] e1000: Copyright (c) 1999-2006 Intel Corporation.
10603 11:37:27.862294 <6>[ 1.647991] e1000e: Intel(R) PRO/1000 Network Driver
10604 11:37:27.868672 <6>[ 1.653207] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10605 11:37:27.875470 <6>[ 1.659397] igb: Intel(R) Gigabit Ethernet Network Driver
10606 11:37:27.882065 <6>[ 1.665048] igb: Copyright (c) 2007-2014 Intel Corporation.
10607 11:37:27.888450 <6>[ 1.670883] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10608 11:37:27.895400 <6>[ 1.677401] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10609 11:37:27.898262 <6>[ 1.683867] sky2: driver version 1.30
10610 11:37:27.905176 <6>[ 1.688800] usbcore: registered new device driver r8152-cfgselector
10611 11:37:27.911860 <6>[ 1.695335] usbcore: registered new interface driver r8152
10612 11:37:27.918817 <6>[ 1.701154] VFIO - User Level meta-driver version: 0.3
10613 11:37:27.925217 <6>[ 1.709393] usbcore: registered new interface driver usb-storage
10614 11:37:27.931556 <6>[ 1.715841] usbcore: registered new device driver onboard-usb-hub
10615 11:37:27.940469 <6>[ 1.725028] mt6397-rtc mt6359-rtc: registered as rtc0
10616 11:37:27.951224 <6>[ 1.730493] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:37:27 UTC (1721216247)
10617 11:37:27.954096 <6>[ 1.740058] i2c_dev: i2c /dev entries driver
10618 11:37:27.967888 <4>[ 1.752094] cpu cpu0: supply cpu not found, using dummy regulator
10619 11:37:27.974306 <4>[ 1.758520] cpu cpu1: supply cpu not found, using dummy regulator
10620 11:37:27.981124 <4>[ 1.764925] cpu cpu2: supply cpu not found, using dummy regulator
10621 11:37:27.987816 <4>[ 1.771323] cpu cpu3: supply cpu not found, using dummy regulator
10622 11:37:27.994510 <4>[ 1.777732] cpu cpu4: supply cpu not found, using dummy regulator
10623 11:37:28.001012 <4>[ 1.784134] cpu cpu5: supply cpu not found, using dummy regulator
10624 11:37:28.007686 <4>[ 1.790548] cpu cpu6: supply cpu not found, using dummy regulator
10625 11:37:28.014321 <4>[ 1.796946] cpu cpu7: supply cpu not found, using dummy regulator
10626 11:37:28.033357 <6>[ 1.817576] cpu cpu0: EM: created perf domain
10627 11:37:28.036530 <6>[ 1.822504] cpu cpu4: EM: created perf domain
10628 11:37:28.044113 <6>[ 1.828139] sdhci: Secure Digital Host Controller Interface driver
10629 11:37:28.050304 <6>[ 1.834571] sdhci: Copyright(c) Pierre Ossman
10630 11:37:28.057487 <6>[ 1.839526] Synopsys Designware Multimedia Card Interface Driver
10631 11:37:28.063724 <6>[ 1.846158] sdhci-pltfm: SDHCI platform and OF driver helper
10632 11:37:28.066675 <6>[ 1.846300] mmc0: CQHCI version 5.10
10633 11:37:28.074007 <6>[ 1.856116] ledtrig-cpu: registered to indicate activity on CPUs
10634 11:37:28.080377 <6>[ 1.863006] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10635 11:37:28.087037 <6>[ 1.870057] usbcore: registered new interface driver usbhid
10636 11:37:28.090317 <6>[ 1.875893] usbhid: USB HID core driver
10637 11:37:28.097216 <6>[ 1.880091] spi_master spi0: will run message pump with realtime priority
10638 11:37:28.143670 <6>[ 1.921496] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10639 11:37:28.162722 <6>[ 1.937153] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10640 11:37:28.166454 <3>[ 1.944473] mtk-msdc 11f60000.mmc: phase error: [map:0]
10641 11:37:28.173487 <3>[ 1.956032] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10642 11:37:28.180405 <3>[ 1.961952] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10643 11:37:28.183315 <3>[ 1.968309] mmc0: error -5 whilst initialising MMC card
10644 11:37:28.190319 <6>[ 1.968557] cros-ec-spi spi0.0: Chrome EC device registered
10645 11:37:28.211071 <6>[ 1.992321] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10646 11:37:28.218508 <6>[ 2.002927] NET: Registered PF_PACKET protocol family
10647 11:37:28.221855 <6>[ 2.008355] 9pnet: Installing 9P2000 support
10648 11:37:28.228722 <5>[ 2.012912] Key type dns_resolver registered
10649 11:37:28.232161 <6>[ 2.018039] registered taskstats version 1
10650 11:37:28.238483 <5>[ 2.022433] Loading compiled-in X.509 certificates
10651 11:37:28.269094 <4>[ 2.046739] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 11:37:28.279107 <4>[ 2.057554] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 11:37:28.296703 <6>[ 2.080900] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17c14
10654 11:37:28.303225 <6>[ 2.081386] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 11:37:28.310011 <6>[ 2.093353] mmc0: Command Queue Engine enabled
10656 11:37:28.313523 <6>[ 2.093852] xhci-mtk 11200000.usb: xHCI Host Controller
10657 11:37:28.319738 <6>[ 2.098076] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10658 11:37:28.329637 <6>[ 2.103553] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10659 11:37:28.333581 <6>[ 2.110627] mmcblk0: mmc0:0001 DA4128 116 GiB
10660 11:37:28.343481 <6>[ 2.117981] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10661 11:37:28.349973 <6>[ 2.128386] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10662 11:37:28.352995 <6>[ 2.131912] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 11:37:28.359821 <6>[ 2.139152] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10664 11:37:28.366297 <6>[ 2.143838] xhci-mtk 11200000.usb: xHCI Host Controller
10665 11:37:28.369814 <6>[ 2.149707] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10666 11:37:28.379878 <6>[ 2.154491] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10667 11:37:28.386293 <6>[ 2.154501] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10668 11:37:28.392688 <6>[ 2.160404] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10669 11:37:28.396485 <6>[ 2.167687] hub 1-0:1.0: USB hub found
10670 11:37:28.399501 <6>[ 2.185190] hub 1-0:1.0: 1 port detected
10671 11:37:28.409567 <6>[ 2.189474] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10672 11:37:28.412948 <6>[ 2.197991] hub 2-0:1.0: USB hub found
10673 11:37:28.415972 <6>[ 2.201997] hub 2-0:1.0: 1 port detected
10674 11:37:28.424697 <6>[ 2.209302] mtk-msdc 11f70000.mmc: Got CD GPIO
10675 11:37:28.439438 <6>[ 2.220386] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10676 11:37:28.449426 <6>[ 2.228766] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10677 11:37:28.456022 <6>[ 2.237105] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10678 11:37:28.466094 <6>[ 2.245452] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10679 11:37:28.472381 <6>[ 2.253793] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10680 11:37:28.482234 <6>[ 2.262132] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10681 11:37:28.488880 <6>[ 2.270472] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10682 11:37:28.498899 <6>[ 2.278811] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10683 11:37:28.505497 <6>[ 2.287153] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10684 11:37:28.515909 <6>[ 2.295490] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10685 11:37:28.522276 <6>[ 2.303829] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10686 11:37:28.532468 <6>[ 2.312167] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10687 11:37:28.539101 <6>[ 2.320505] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10688 11:37:28.549069 <6>[ 2.328845] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10689 11:37:28.555653 <6>[ 2.337183] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10690 11:37:28.562083 <6>[ 2.345891] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10691 11:37:28.568400 <6>[ 2.353078] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10692 11:37:28.575500 <6>[ 2.359853] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10693 11:37:28.585741 <6>[ 2.366631] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10694 11:37:28.592030 <6>[ 2.373561] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10695 11:37:28.598621 <6>[ 2.380403] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:37:28.608264 <6>[ 2.389536] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10697 11:37:28.618882 <6>[ 2.398656] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10698 11:37:28.628427 <6>[ 2.407952] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10699 11:37:28.638558 <6>[ 2.417425] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10700 11:37:28.645136 <6>[ 2.426896] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10701 11:37:28.655396 <6>[ 2.436017] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10702 11:37:28.664665 <6>[ 2.445484] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10703 11:37:28.674684 <6>[ 2.454603] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10704 11:37:28.685371 <6>[ 2.463905] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10705 11:37:28.694502 <6>[ 2.474068] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10706 11:37:28.705162 <6>[ 2.485844] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10707 11:37:28.712261 <6>[ 2.497029] Trying to probe devices needed for running init ...
10708 11:37:28.723368 <3>[ 2.504176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10709 11:37:28.807781 <6>[ 2.588791] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 11:37:28.835896 <6>[ 2.620292] hub 2-1:1.0: USB hub found
10711 11:37:28.839472 <6>[ 2.624767] hub 2-1:1.0: 3 ports detected
10712 11:37:28.850261 <6>[ 2.634132] hub 2-1:1.0: USB hub found
10713 11:37:28.853253 <6>[ 2.638661] hub 2-1:1.0: 3 ports detected
10714 11:37:28.959379 <6>[ 2.740520] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 11:37:29.113580 <6>[ 2.897857] hub 1-1:1.0: USB hub found
10716 11:37:29.117029 <6>[ 2.902315] hub 1-1:1.0: 4 ports detected
10717 11:37:29.129436 <6>[ 2.913848] hub 1-1:1.0: USB hub found
10718 11:37:29.132698 <6>[ 2.918390] hub 1-1:1.0: 4 ports detected
10719 11:37:29.199562 <6>[ 2.980758] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10720 11:37:29.308343 <6>[ 3.089215] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10721 11:37:29.344133 <4>[ 3.125554] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10722 11:37:29.354211 <4>[ 3.134720] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10723 11:37:29.389459 <6>[ 3.174029] r8152 2-1.3:1.0 eth0: v1.12.13
10724 11:37:29.467279 <6>[ 3.248553] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 11:37:29.600270 <6>[ 3.384538] hub 1-1.4:1.0: USB hub found
10726 11:37:29.603301 <6>[ 3.389206] hub 1-1.4:1.0: 2 ports detected
10727 11:37:29.617348 <6>[ 3.402275] hub 1-1.4:1.0: USB hub found
10728 11:37:29.620570 <6>[ 3.406870] hub 1-1.4:1.0: 2 ports detected
10729 11:37:29.918913 <6>[ 3.700375] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10730 11:37:30.110896 <6>[ 3.892376] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10731 11:37:30.993125 <6>[ 4.777664] r8152 2-1.3:1.0 eth0: carrier on
10732 11:37:31.039205 <5>[ 4.808347] Sending DHCP requests ., OK
10733 11:37:31.046265 <6>[ 4.828596] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10734 11:37:31.049819 <6>[ 4.836880] IP-Config: Complete:
10735 11:37:31.063481 <6>[ 4.840375] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10736 11:37:31.069888 <6>[ 4.851094] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10737 11:37:31.076207 <6>[ 4.859712] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10738 11:37:31.082850 <6>[ 4.859721] nameserver0=192.168.201.1
10739 11:37:31.085734 <6>[ 4.871865] clk: Disabling unused clocks
10740 11:37:31.089270 <6>[ 4.877331] ALSA device list:
10741 11:37:31.095509 <6>[ 4.880583] No soundcards found.
10742 11:37:31.103896 <6>[ 4.888095] Freeing unused kernel memory: 8512K
10743 11:37:31.106742 <6>[ 4.893088] Run /init as init process
10744 11:37:31.117978 Loading, please wait...
10745 11:37:31.144473 Starting systemd-udevd version 252.22-1~deb12u1
10746 11:37:31.369121 <6>[ 5.150050] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10747 11:37:31.388829 <3>[ 5.169973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:37:31.395011 <3>[ 5.178309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:37:31.405032 <6>[ 5.185794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10750 11:37:31.411362 <3>[ 5.186604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:37:31.421538 <6>[ 5.194543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10752 11:37:31.428266 <3>[ 5.202677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:37:31.438212 <4>[ 5.210774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10754 11:37:31.444784 <6>[ 5.213546] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10755 11:37:31.454531 <6>[ 5.213584] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10756 11:37:31.461313 <6>[ 5.213598] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10757 11:37:31.471480 <3>[ 5.218424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 11:37:31.477867 <3>[ 5.218428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 11:37:31.488182 <3>[ 5.218439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 11:37:31.494251 <6>[ 5.223771] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10761 11:37:31.504437 <6>[ 5.228153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10762 11:37:31.511181 <3>[ 5.235037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 11:37:31.517735 <3>[ 5.235456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 11:37:31.524096 <6>[ 5.236887] mc: Linux media interface: v0.10
10765 11:37:31.530983 <6>[ 5.237649] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10766 11:37:31.537768 <6>[ 5.243810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10767 11:37:31.547468 <4>[ 5.244521] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10768 11:37:31.554006 <4>[ 5.252565] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10769 11:37:31.561133 <6>[ 5.260991] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10770 11:37:31.567802 <3>[ 5.267955] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 11:37:31.577956 <3>[ 5.267976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:37:31.585162 <3>[ 5.267981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 11:37:31.591963 <6>[ 5.274082] remoteproc remoteproc0: scp is available
10774 11:37:31.598700 <6>[ 5.276958] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10775 11:37:31.608365 <3>[ 5.278707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 11:37:31.615065 <3>[ 5.278736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 11:37:31.621752 <3>[ 5.278740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 11:37:31.631515 <3>[ 5.278745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 11:37:31.638447 <3>[ 5.278749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 11:37:31.647825 <3>[ 5.278804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 11:37:31.651349 <6>[ 5.284593] remoteproc remoteproc0: powering up scp
10782 11:37:31.658276 <6>[ 5.284958] videodev: Linux video capture interface: v2.00
10783 11:37:31.664583 <6>[ 5.293051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10784 11:37:31.674903 <6>[ 5.300839] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10785 11:37:31.684680 <6>[ 5.308978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10786 11:37:31.688383 <6>[ 5.313520] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10787 11:37:31.697769 <4>[ 5.321609] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10788 11:37:31.704407 <4>[ 5.321609] Fallback method does not support PEC.
10789 11:37:31.710997 <6>[ 5.334980] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10790 11:37:31.721015 <6>[ 5.349534] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10791 11:37:31.724612 <6>[ 5.351290] pci_bus 0000:00: root bus resource [bus 00-ff]
10792 11:37:31.734285 <3>[ 5.353378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 11:37:31.744381 <6>[ 5.359869] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10794 11:37:31.750699 <6>[ 5.367379] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10795 11:37:31.760973 <6>[ 5.367382] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10796 11:37:31.767015 <6>[ 5.367411] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10797 11:37:31.774202 <3>[ 5.376198] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 11:37:31.784126 <6>[ 5.379762] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10799 11:37:31.793999 <6>[ 5.380704] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10800 11:37:31.797070 <6>[ 5.421550] Bluetooth: Core ver 2.22
10801 11:37:31.800473 <6>[ 5.429000] pci 0000:00:00.0: supports D1 D2
10802 11:37:31.807095 <6>[ 5.437121] NET: Registered PF_BLUETOOTH protocol family
10803 11:37:31.813633 <6>[ 5.442144] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 11:37:31.819966 <6>[ 5.443468] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10805 11:37:31.826583 <6>[ 5.448013] Bluetooth: HCI device and connection manager initialized
10806 11:37:31.833124 <6>[ 5.448826] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10807 11:37:31.846859 <6>[ 5.450439] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10808 11:37:31.853009 <6>[ 5.450678] usbcore: registered new interface driver uvcvideo
10809 11:37:31.859736 <6>[ 5.454362] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10810 11:37:31.869743 <6>[ 5.454400] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10811 11:37:31.875889 <6>[ 5.454409] remoteproc remoteproc0: remote processor scp is now up
10812 11:37:31.882903 <6>[ 5.455822] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10813 11:37:31.886029 <6>[ 5.464171] Bluetooth: HCI socket layer initialized
10814 11:37:31.893269 <6>[ 5.464930] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10815 11:37:31.902622 <6>[ 5.466272] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10816 11:37:31.909116 <6>[ 5.468462] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10817 11:37:31.915612 <6>[ 5.473315] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10818 11:37:31.925664 <6>[ 5.473336] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10819 11:37:31.929019 <6>[ 5.479157] Bluetooth: L2CAP socket layer initialized
10820 11:37:31.938812 <6>[ 5.492860] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10821 11:37:31.942201 <6>[ 5.499582] Bluetooth: SCO socket layer initialized
10822 11:37:31.948662 <6>[ 5.565796] usbcore: registered new interface driver btusb
10823 11:37:31.958658 <4>[ 5.566801] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 11:37:31.965400 <3>[ 5.566814] Bluetooth: hci0: Failed to load firmware file (-2)
10825 11:37:31.972277 <3>[ 5.566819] Bluetooth: hci0: Failed to set up firmware (-2)
10826 11:37:31.982258 <4>[ 5.566824] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 11:37:31.985723 <6>[ 5.574767] pci 0000:01:00.0: supports D1 D2
10828 11:37:31.991764 <6>[ 5.775433] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10829 11:37:32.011380 <6>[ 5.792526] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10830 11:37:32.017784 <6>[ 5.799424] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10831 11:37:32.024492 <6>[ 5.807512] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10832 11:37:32.034584 <6>[ 5.815510] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10833 11:37:32.040550 <6>[ 5.823511] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10834 11:37:32.050521 <6>[ 5.831512] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10835 11:37:32.053918 <6>[ 5.839513] pci 0000:00:00.0: PCI bridge to [bus 01]
10836 11:37:32.063570 <6>[ 5.844729] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10837 11:37:32.070600 <6>[ 5.852848] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10838 11:37:32.077646 <6>[ 5.859675] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10839 11:37:32.083317 <6>[ 5.866529] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10840 11:37:32.100231 <5>[ 5.881999] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10841 11:37:32.121778 <5>[ 5.903341] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10842 11:37:32.128583 <5>[ 5.910835] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10843 11:37:32.138793 <4>[ 5.919322] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10844 11:37:32.142148 <6>[ 5.928215] cfg80211: failed to load regulatory.db
10845 11:37:32.196333 <6>[ 5.977903] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10846 11:37:32.202709 <6>[ 5.985560] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10847 11:37:32.227867 <6>[ 6.012615] mt7921e 0000:01:00.0: ASIC revision: 79610010
10848 11:37:32.331298 <6>[ 6.112793] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10849 11:37:32.334725 <6>[ 6.112793]
10850 11:37:32.337731 Begin: Loading essential drivers ... done.
10851 11:37:32.340764 Begin: Running /scripts/init-premount ... done.
10852 11:37:32.347731 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10853 11:37:32.357858 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10854 11:37:32.361586 Device /sys/class/net/eth0 found
10855 11:37:32.362081 done.
10856 11:37:32.367641 Begin: Waiting up to 180 secs for any network device to become available ... done.
10857 11:37:32.419240 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10858 11:37:32.426902 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10859 11:37:32.433632 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10860 11:37:32.440156 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10861 11:37:32.446830 host : mt8192-asurada-spherion-r0-cbg-8
10862 11:37:32.453964 domain : lava-rack
10863 11:37:32.456876 rootserver: 192.168.201.1 rootpath:
10864 11:37:32.459920 filename :
10865 11:37:32.518912 done.
10866 11:37:32.526907 Begin: Running /scripts/nfs-bottom ... done.
10867 11:37:32.544403 Begin: Running /scripts/init-bottom ... done.
10868 11:37:32.601705 <6>[ 6.383321] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10869 11:37:33.959218 <6>[ 7.744102] NET: Registered PF_INET6 protocol family
10870 11:37:33.966566 <6>[ 7.751671] Segment Routing with IPv6
10871 11:37:33.969848 <6>[ 7.755670] In-situ OAM (IOAM) with IPv6
10872 11:37:34.156250 <30>[ 7.914413] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10873 11:37:34.162605 <30>[ 7.947581] systemd[1]: Detected architecture arm64.
10874 11:37:34.173983
10875 11:37:34.177526 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10876 11:37:34.178029
10877 11:37:34.205903 <30>[ 7.990983] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10878 11:37:35.488450 <30>[ 9.270471] systemd[1]: Queued start job for default target graphical.target.
10879 11:37:35.528172 <30>[ 9.309468] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10880 11:37:35.534628 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10881 11:37:35.556838 <30>[ 9.338279] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10882 11:37:35.566605 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10883 11:37:35.584545 <30>[ 9.366244] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10884 11:37:35.594773 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10885 11:37:35.611913 <30>[ 9.393917] systemd[1]: Created slice user.slice - User and Session Slice.
10886 11:37:35.618412 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10887 11:37:35.642033 <30>[ 9.420858] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10888 11:37:35.652268 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10889 11:37:35.670581 <30>[ 9.448775] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10890 11:37:35.676758 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10891 11:37:35.704917 <30>[ 9.477195] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10892 11:37:35.715816 <30>[ 9.497124] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10893 11:37:35.722020 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10894 11:37:35.739165 <30>[ 9.520939] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10895 11:37:35.749054 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10896 11:37:35.766976 <30>[ 9.548633] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10897 11:37:35.776349 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10898 11:37:35.791949 <30>[ 9.577101] systemd[1]: Reached target paths.target - Path Units.
10899 11:37:35.802087 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10900 11:37:35.819250 <30>[ 9.601004] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10901 11:37:35.826229 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10902 11:37:35.839216 <30>[ 9.624520] systemd[1]: Reached target slices.target - Slice Units.
10903 11:37:35.849325 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10904 11:37:35.864393 <30>[ 9.649016] systemd[1]: Reached target swap.target - Swaps.
10905 11:37:35.870295 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10906 11:37:35.891171 <30>[ 9.673071] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10907 11:37:35.901044 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10908 11:37:35.919860 <30>[ 9.701499] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10909 11:37:35.929965 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10910 11:37:35.950978 <30>[ 9.732607] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10911 11:37:35.961061 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10912 11:37:35.980628 <30>[ 9.762455] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10913 11:37:35.990296 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10914 11:37:36.007084 <30>[ 9.789214] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10915 11:37:36.013651 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10916 11:37:36.032923 <30>[ 9.814558] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10917 11:37:36.042214 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10918 11:37:36.063639 <30>[ 9.845526] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10919 11:37:36.073311 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10920 11:37:36.091757 <30>[ 9.873061] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10921 11:37:36.101604 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10922 11:37:36.143258 <30>[ 9.924994] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10923 11:37:36.149405 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10924 11:37:36.168725 <30>[ 9.951026] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10925 11:37:36.175337 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10926 11:37:36.197089 <30>[ 9.979803] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10927 11:37:36.203970 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10928 11:37:36.228980 <30>[ 10.005115] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10929 11:37:36.244747 <30>[ 10.027120] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10930 11:37:36.254554 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10931 11:37:36.275702 <30>[ 10.057931] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10932 11:37:36.282562 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10933 11:37:36.308378 <30>[ 10.090433] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10934 11:37:36.314751 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10935 11:37:36.358671 <6>[ 10.140839] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10936 11:37:36.365498 <30>[ 10.149371] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10937 11:37:36.375325 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10938 11:37:36.397893 <30>[ 10.179903] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10939 11:37:36.408264 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10940 11:37:36.432860 <30>[ 10.214605] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10941 11:37:36.439059 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10942 11:37:36.464365 <30>[ 10.246282] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10943 11:37:36.470762 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10944 11:37:36.478452 <6>[ 10.264101] fuse: init (API version 7.37)
10945 11:37:36.500158 <30>[ 10.282408] systemd[1]: Starting systemd-journald.service - Journal Service...
10946 11:37:36.507005 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10947 11:37:36.563933 <30>[ 10.345689] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10948 11:37:36.569991 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10949 11:37:36.598168 <30>[ 10.377206] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10950 11:37:36.604925 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10951 11:37:36.627485 <30>[ 10.409273] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10952 11:37:36.637258 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10953 11:37:36.659625 <30>[ 10.441732] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10954 11:37:36.669590 <3>[ 10.446236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:37:36.676601 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10956 11:37:36.698204 <3>[ 10.480480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 11:37:36.705022 <30>[ 10.485814] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10958 11:37:36.715004 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10959 11:37:36.731698 <30>[ 10.513301] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10960 11:37:36.738355 <3>[ 10.519576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 11:37:36.747971 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10962 11:37:36.767114 <30>[ 10.549008] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10963 11:37:36.776987 <3>[ 10.551192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:37:36.783115 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10965 11:37:36.803927 <30>[ 10.585678] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10966 11:37:36.813524 <3>[ 10.586981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:37:36.820156 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10968 11:37:36.840028 <30>[ 10.621919] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10969 11:37:36.846664 <3>[ 10.625617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:37:36.856931 <30>[ 10.630055] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10971 11:37:36.863590 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10972 11:37:36.879283 <3>[ 10.661525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 11:37:36.890133 <30>[ 10.672171] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10974 11:37:36.896867 <30>[ 10.680395] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10975 11:37:36.910450 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 10.691595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 11:37:36.913720 m_mod.s…e[0m - Load Kernel Module dm_mod.
10977 11:37:36.933859 <30>[ 10.718347] systemd[1]: modprobe@drm.service: Deactivated successfully.
10978 11:37:36.944188 <3>[ 10.725226] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:37:36.949907 <30>[ 10.726163] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10980 11:37:36.959721 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10981 11:37:36.977436 <3>[ 10.759495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 11:37:36.988557 <30>[ 10.770574] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10983 11:37:36.999646 <30>[ 10.778999] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10984 11:37:37.005418 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10985 11:37:37.025422 <30>[ 10.806632] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10986 11:37:37.031768 <30>[ 10.815058] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10987 11:37:37.041487 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10988 11:37:37.059277 <30>[ 10.841310] systemd[1]: Started systemd-journald.service - Journal Service.
10989 11:37:37.065864 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10990 11:37:37.092943 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10991 11:37:37.116429 <4>[ 10.892134] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10992 11:37:37.126875 <3>[ 10.907815] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10993 11:37:37.132997 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10994 11:37:37.155685 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10995 11:37:37.172518 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10996 11:37:37.192554 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10997 11:37:37.213530 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10998 11:37:37.279034 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10999 11:37:37.301862 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11000 11:37:37.324513 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11001 11:37:37.352941 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11002 11:37:37.378487 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11003 11:37:37.404409 <46>[ 11.186886] systemd-journald[310]: Received client request to flush runtime journal.
11004 11:37:37.411279 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11005 11:37:37.450693 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11006 11:37:37.470887 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11007 11:37:37.492318 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11008 11:37:37.516568 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11009 11:37:38.517130 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11010 11:37:38.567601 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11011 11:37:38.836271 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11012 11:37:38.973501 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11013 11:37:38.995142 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11014 11:37:39.014767 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11015 11:37:39.067601 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11016 11:37:39.094871 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11017 11:37:39.369631 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11018 11:37:39.411826 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11019 11:37:39.464006 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11020 11:37:39.791161 <6>[ 13.576905] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11021 11:37:39.812030 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11022 11:37:39.859988 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11023 11:37:39.893891 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11024 11:37:39.960609 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11025 11:37:39.979045 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11026 11:37:40.038575 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11027 11:37:40.071295 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11028 11:37:40.095844 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11029 11:37:40.116348 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11030 11:37:40.137174 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11031 11:37:40.155061 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11032 11:37:40.209794 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11033 11:37:40.232363 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11034 11:37:40.300939 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11035 11:37:40.322528 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11036 11:37:40.338700 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11037 11:37:40.354407 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11038 11:37:40.381105 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11039 11:37:40.402612 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11040 11:37:40.418352 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11041 11:37:40.439155 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11042 11:37:40.458997 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11043 11:37:40.478391 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11044 11:37:40.497492 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11045 11:37:40.514402 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11046 11:37:40.530611 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11047 11:37:40.584619 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11048 11:37:40.623094 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11049 11:37:40.729729 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11050 11:37:40.759243 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11051 11:37:40.801016 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11052 11:37:40.867909 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11053 11:37:40.892138 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11054 11:37:40.911394 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11055 11:37:40.927033 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11056 11:37:40.966434 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11057 11:37:41.099885 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11058 11:37:41.121182 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11059 11:37:41.139103 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11060 11:37:41.183757 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11061 11:37:41.238438 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11062 11:37:41.327138
11063 11:37:41.329904 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11064 11:37:41.330457
11065 11:37:41.334729 debian-bookworm-arm64 login: root (automatic login)
11066 11:37:41.335305
11067 11:37:41.681659 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11068 11:37:41.682352
11069 11:37:41.687729 The programs included with the Debian GNU/Linux system are free software;
11070 11:37:41.694068 the exact distribution terms for each program are described in the
11071 11:37:41.698130 individual files in /usr/share/doc/*/copyright.
11072 11:37:41.698494
11073 11:37:41.704258 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11074 11:37:41.707643 permitted by applicable law.
11075 11:37:42.859290 Matched prompt #10: / #
11077 11:37:42.860293 Setting prompt string to ['/ #']
11078 11:37:42.860693 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11080 11:37:42.861554 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11081 11:37:42.861945 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11082 11:37:42.862290 Setting prompt string to ['/ #']
11083 11:37:42.862568 Forcing a shell prompt, looking for ['/ #']
11084 11:37:42.862836 Sending line: ''
11086 11:37:42.914072 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11087 11:37:42.914544 Waiting using forced prompt support (timeout 00:02:30)
11088 11:37:42.919679 / #
11089 11:37:42.920540 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11090 11:37:42.921033 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11091 11:37:42.921422 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741'"
11093 11:37:43.029014 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864619/extract-nfsrootfs-9lchz741'
11094 11:37:43.029766 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11096 11:37:43.137478 / # export NFS_SERVER_IP='192.168.201.1'
11097 11:37:43.138315 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11098 11:37:43.138814 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11099 11:37:43.139289 end: 2 depthcharge-action (duration 00:02:00) [common]
11100 11:37:43.139741 start: 3 lava-test-retry (timeout 00:07:22) [common]
11101 11:37:43.140184 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11102 11:37:43.140565 Using namespace: common
11103 11:37:43.140920 Sending line: '#'
11105 11:37:43.242358 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11106 11:37:43.247615 / # #
11107 11:37:43.248441 Using /lava-14864619
11108 11:37:43.248864 Sending line: 'export SHELL=/bin/bash'
11110 11:37:43.356341 / # export SHELL=/bin/bash
11111 11:37:43.357024 Sending line: '. /lava-14864619/environment'
11113 11:37:43.464263 / # . /lava-14864619/environment
11114 11:37:43.471409 Sending line: '/lava-14864619/bin/lava-test-runner /lava-14864619/0'
11116 11:37:43.572884 Test shell timeout: 10s (minimum of the action and connection timeout)
11117 11:37:43.578706 / # /lava-14864619/bin/lava-test-runner /lava-14864619/0
11118 11:37:43.889154 + export TESTRUN_ID=0_timesync-off
11119 11:37:43.892682 + TESTRUN_ID=0_timesync-off
11120 11:37:43.895878 + cd /lava-14864619/0/tests/0_timesync-off
11121 11:37:43.898916 ++ cat uuid
11122 11:37:43.907017 + UUID=14864619_1.6.2.3.1
11123 11:37:43.907453 + set +x
11124 11:37:43.913939 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864619_1.6.2.3.1>
11125 11:37:43.914670 Received signal: <STARTRUN> 0_timesync-off 14864619_1.6.2.3.1
11126 11:37:43.915000 Starting test lava.0_timesync-off (14864619_1.6.2.3.1)
11127 11:37:43.915372 Skipping test definition patterns.
11128 11:37:43.916759 + systemctl stop systemd-timesyncd
11129 11:37:44.012592 + set +x
11130 11:37:44.016300 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864619_1.6.2.3.1>
11131 11:37:44.017051 Received signal: <ENDRUN> 0_timesync-off 14864619_1.6.2.3.1
11132 11:37:44.017509 Ending use of test pattern.
11133 11:37:44.017836 Ending test lava.0_timesync-off (14864619_1.6.2.3.1), duration 0.10
11135 11:37:44.115252 + export TESTRUN_ID=1_kselftest-dt
11136 11:37:44.118375 + TESTRUN_ID=1_kselftest-dt
11137 11:37:44.121508 + cd /lava-14864619/0/tests/1_kselftest-dt
11138 11:37:44.125111 ++ cat uuid
11139 11:37:44.133516 + UUID=14864619_1.6.2.3.5
11140 11:37:44.133944 + set +x
11141 11:37:44.140258 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14864619_1.6.2.3.5>
11142 11:37:44.140873 Received signal: <STARTRUN> 1_kselftest-dt 14864619_1.6.2.3.5
11143 11:37:44.141199 Starting test lava.1_kselftest-dt (14864619_1.6.2.3.5)
11144 11:37:44.141574 Skipping test definition patterns.
11145 11:37:44.144195 + cd ./automated/linux/kselftest/
11146 11:37:44.173366 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11147 11:37:44.232340 INFO: install_deps skipped
11148 11:37:44.759706 --2024-07-17 11:37:44-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11149 11:37:44.777752 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11150 11:37:44.906768 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11151 11:37:45.038863 HTTP request sent, awaiting response... 200 OK
11152 11:37:45.042310 Length: 1920476 (1.8M) [application/octet-stream]
11153 11:37:45.045308 Saving to: 'kselftest_armhf.tar.gz'
11154 11:37:45.045732
11155 11:37:45.046055
11156 11:37:45.298560 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11157 11:37:45.556661 kselftest_armhf.tar 2%[ ] 50.15K 194KB/s
11158 11:37:45.816241 kselftest_armhf.tar 11%[=> ] 214.67K 415KB/s
11159 11:37:46.074550 kselftest_armhf.tar 47%[========> ] 898.59K 1.13MB/s
11160 11:37:46.080835 kselftest_armhf.tar 94%[=================> ] 1.73M 1.68MB/s
11161 11:37:46.087797 kselftest_armhf.tar 100%[===================>] 1.83M 1.77MB/s in 1.0s
11162 11:37:46.088313
11163 11:37:46.250614 2024-07-17 11:37:45 (1.77 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
11164 11:37:46.250756
11165 11:37:54.156313 skiplist:
11166 11:37:54.159722 ========================================
11167 11:37:54.162850 ========================================
11168 11:37:54.250080 ============== Tests to run ===============
11169 11:37:54.256258 ===========End Tests to run ===============
11170 11:37:54.262518 shardfile-dt fail
11171 11:37:54.289742 ./kselftest.sh: 139: cannot open /lava-14864619/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11172 11:37:54.293171 + ../../utils/send-to-lava.sh ./output/result.txt
11173 11:37:54.387162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11174 11:37:54.387634 + set +x
11175 11:37:54.388345 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11177 11:37:54.393517 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14864619_1.6.2.3.5>
11178 11:37:54.394248 Received signal: <ENDRUN> 1_kselftest-dt 14864619_1.6.2.3.5
11179 11:37:54.394692 Ending use of test pattern.
11180 11:37:54.395086 Ending test lava.1_kselftest-dt (14864619_1.6.2.3.5), duration 10.25
11182 11:37:54.396358 ok: lava_test_shell seems to have completed
11183 11:37:54.396910 shardfile-dt: fail
11184 11:37:54.397409 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11185 11:37:54.397894 end: 3 lava-test-retry (duration 00:00:11) [common]
11186 11:37:54.398559 start: 4 finalize (timeout 00:07:11) [common]
11187 11:37:54.399089 start: 4.1 power-off (timeout 00:00:30) [common]
11188 11:37:54.399828 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11189 11:37:56.532193 >> Command sent successfully.
11190 11:37:56.548349 Returned 0 in 2 seconds
11191 11:37:56.548921 end: 4.1 power-off (duration 00:00:02) [common]
11193 11:37:56.549833 start: 4.2 read-feedback (timeout 00:07:09) [common]
11195 11:37:56.551167 Listened to connection for namespace 'common' for up to 1s
11196 11:37:57.551676 Finalising connection for namespace 'common'
11197 11:37:57.552273 Disconnecting from shell: Finalise
11198 11:37:57.552636 / #
11199 11:37:57.653501 end: 4.2 read-feedback (duration 00:00:01) [common]
11200 11:37:57.654090 end: 4 finalize (duration 00:00:03) [common]
11201 11:37:57.654767 Cleaning after the job
11202 11:37:57.655297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/ramdisk
11203 11:37:57.666015 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/kernel
11204 11:37:57.700408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/dtb
11205 11:37:57.700734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/nfsrootfs
11206 11:37:57.766776 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864619/tftp-deploy-s5l1j54j/modules
11207 11:37:57.772279 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864619
11208 11:37:58.322791 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864619
11209 11:37:58.322960 Job finished correctly