Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:31:03.496426 lava-dispatcher, installed at version: 2024.05
2 11:31:03.496626 start: 0 validate
3 11:31:03.496745 Start time: 2024-07-17 11:31:03.496739+00:00 (UTC)
4 11:31:03.496878 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:03.497023 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:31:03.749174 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:03.749445 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:31:22.756070 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:31:22.756814 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:31:23.023100 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:31:23.023885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:31:23.542596 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:31:23.543248 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:31:26.051018 validate duration: 22.55
16 11:31:26.051267 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:31:26.051392 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:31:26.051485 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:31:26.051637 Not decompressing ramdisk as can be used compressed.
20 11:31:26.051719 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:31:26.051777 saving as /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/ramdisk/initrd.cpio.gz
22 11:31:26.051840 total size: 5628169 (5 MB)
23 11:31:26.052889 progress 0 % (0 MB)
24 11:31:26.054549 progress 5 % (0 MB)
25 11:31:26.056167 progress 10 % (0 MB)
26 11:31:26.057713 progress 15 % (0 MB)
27 11:31:26.059267 progress 20 % (1 MB)
28 11:31:26.060743 progress 25 % (1 MB)
29 11:31:26.062307 progress 30 % (1 MB)
30 11:31:26.064000 progress 35 % (1 MB)
31 11:31:26.065405 progress 40 % (2 MB)
32 11:31:26.066939 progress 45 % (2 MB)
33 11:31:26.068266 progress 50 % (2 MB)
34 11:31:26.069899 progress 55 % (2 MB)
35 11:31:26.071420 progress 60 % (3 MB)
36 11:31:26.072753 progress 65 % (3 MB)
37 11:31:26.074429 progress 70 % (3 MB)
38 11:31:26.075816 progress 75 % (4 MB)
39 11:31:26.077337 progress 80 % (4 MB)
40 11:31:26.078630 progress 85 % (4 MB)
41 11:31:26.080227 progress 90 % (4 MB)
42 11:31:26.081715 progress 95 % (5 MB)
43 11:31:26.083023 progress 100 % (5 MB)
44 11:31:26.083225 5 MB downloaded in 0.03 s (171.06 MB/s)
45 11:31:26.083371 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:31:26.083624 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:31:26.083703 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:31:26.083778 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:31:26.083912 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:31:26.083988 saving as /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/kernel/Image
52 11:31:26.084056 total size: 54813184 (52 MB)
53 11:31:26.084126 No compression specified
54 11:31:26.085248 progress 0 % (0 MB)
55 11:31:26.098715 progress 5 % (2 MB)
56 11:31:26.112288 progress 10 % (5 MB)
57 11:31:26.126008 progress 15 % (7 MB)
58 11:31:26.139809 progress 20 % (10 MB)
59 11:31:26.153537 progress 25 % (13 MB)
60 11:31:26.167256 progress 30 % (15 MB)
61 11:31:26.181120 progress 35 % (18 MB)
62 11:31:26.195144 progress 40 % (20 MB)
63 11:31:26.208929 progress 45 % (23 MB)
64 11:31:26.223077 progress 50 % (26 MB)
65 11:31:26.237028 progress 55 % (28 MB)
66 11:31:26.251482 progress 60 % (31 MB)
67 11:31:26.265921 progress 65 % (34 MB)
68 11:31:26.280592 progress 70 % (36 MB)
69 11:31:26.294729 progress 75 % (39 MB)
70 11:31:26.308646 progress 80 % (41 MB)
71 11:31:26.322079 progress 85 % (44 MB)
72 11:31:26.335959 progress 90 % (47 MB)
73 11:31:26.350075 progress 95 % (49 MB)
74 11:31:26.363467 progress 100 % (52 MB)
75 11:31:26.363712 52 MB downloaded in 0.28 s (186.92 MB/s)
76 11:31:26.363860 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:31:26.364072 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:31:26.364153 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:31:26.364230 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:31:26.364364 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:31:26.364428 saving as /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/dtb/mt8192-asurada-spherion-r0.dtb
83 11:31:26.364481 total size: 47258 (0 MB)
84 11:31:26.364535 No compression specified
85 11:31:26.365762 progress 69 % (0 MB)
86 11:31:26.366023 progress 100 % (0 MB)
87 11:31:26.366170 0 MB downloaded in 0.00 s (26.73 MB/s)
88 11:31:26.366284 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:31:26.366487 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:31:26.366563 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:31:26.366645 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:31:26.366754 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:31:26.366814 saving as /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/nfsrootfs/full.rootfs.tar
95 11:31:26.366868 total size: 120894716 (115 MB)
96 11:31:26.366923 Using unxz to decompress xz
97 11:31:26.368056 progress 0 % (0 MB)
98 11:31:26.711445 progress 5 % (5 MB)
99 11:31:27.057728 progress 10 % (11 MB)
100 11:31:27.411039 progress 15 % (17 MB)
101 11:31:27.746712 progress 20 % (23 MB)
102 11:31:28.056893 progress 25 % (28 MB)
103 11:31:28.402008 progress 30 % (34 MB)
104 11:31:28.739496 progress 35 % (40 MB)
105 11:31:28.917414 progress 40 % (46 MB)
106 11:31:29.101581 progress 45 % (51 MB)
107 11:31:29.405707 progress 50 % (57 MB)
108 11:31:29.763265 progress 55 % (63 MB)
109 11:31:30.108066 progress 60 % (69 MB)
110 11:31:30.449218 progress 65 % (74 MB)
111 11:31:30.787511 progress 70 % (80 MB)
112 11:31:31.148348 progress 75 % (86 MB)
113 11:31:31.485594 progress 80 % (92 MB)
114 11:31:31.823619 progress 85 % (98 MB)
115 11:31:32.179382 progress 90 % (103 MB)
116 11:31:32.511076 progress 95 % (109 MB)
117 11:31:32.874118 progress 100 % (115 MB)
118 11:31:32.879620 115 MB downloaded in 6.51 s (17.70 MB/s)
119 11:31:32.879833 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:31:32.880054 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:31:32.880132 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:31:32.880207 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:31:32.880339 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:31:32.880401 saving as /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/modules/modules.tar
126 11:31:32.880454 total size: 8610184 (8 MB)
127 11:31:32.880509 Using unxz to decompress xz
128 11:31:32.881850 progress 0 % (0 MB)
129 11:31:32.902279 progress 5 % (0 MB)
130 11:31:32.926891 progress 10 % (0 MB)
131 11:31:32.951627 progress 15 % (1 MB)
132 11:31:32.977175 progress 20 % (1 MB)
133 11:31:33.000892 progress 25 % (2 MB)
134 11:31:33.024979 progress 30 % (2 MB)
135 11:31:33.047696 progress 35 % (2 MB)
136 11:31:33.074101 progress 40 % (3 MB)
137 11:31:33.104951 progress 45 % (3 MB)
138 11:31:33.136755 progress 50 % (4 MB)
139 11:31:33.161827 progress 55 % (4 MB)
140 11:31:33.187018 progress 60 % (4 MB)
141 11:31:33.211237 progress 65 % (5 MB)
142 11:31:33.237788 progress 70 % (5 MB)
143 11:31:33.267256 progress 75 % (6 MB)
144 11:31:33.300342 progress 80 % (6 MB)
145 11:31:33.329141 progress 85 % (7 MB)
146 11:31:33.356970 progress 90 % (7 MB)
147 11:31:33.383572 progress 95 % (7 MB)
148 11:31:33.408724 progress 100 % (8 MB)
149 11:31:33.414183 8 MB downloaded in 0.53 s (15.38 MB/s)
150 11:31:33.414368 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:31:33.414608 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:31:33.414701 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:31:33.414792 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:31:37.031305 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri
156 11:31:37.031484 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:31:37.031570 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:31:37.031728 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu
159 11:31:37.031850 makedir: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin
160 11:31:37.031941 makedir: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/tests
161 11:31:37.032028 makedir: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/results
162 11:31:37.032110 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-add-keys
163 11:31:37.032231 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-add-sources
164 11:31:37.032345 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-background-process-start
165 11:31:37.032458 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-background-process-stop
166 11:31:37.032650 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-common-functions
167 11:31:37.032785 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-echo-ipv4
168 11:31:37.032898 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-install-packages
169 11:31:37.033009 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-installed-packages
170 11:31:37.033140 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-os-build
171 11:31:37.033269 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-probe-channel
172 11:31:37.033381 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-probe-ip
173 11:31:37.033491 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-target-ip
174 11:31:37.033602 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-target-mac
175 11:31:37.033711 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-target-storage
176 11:31:37.033824 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-case
177 11:31:37.033934 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-event
178 11:31:37.034043 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-feedback
179 11:31:37.034151 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-raise
180 11:31:37.034258 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-reference
181 11:31:37.034366 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-runner
182 11:31:37.034472 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-set
183 11:31:37.034584 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-test-shell
184 11:31:37.034695 Updating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-add-keys (debian)
185 11:31:37.034830 Updating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-add-sources (debian)
186 11:31:37.034962 Updating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-install-packages (debian)
187 11:31:37.035088 Updating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-installed-packages (debian)
188 11:31:37.035210 Updating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/bin/lava-os-build (debian)
189 11:31:37.035318 Creating /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/environment
190 11:31:37.035403 LAVA metadata
191 11:31:37.035466 - LAVA_JOB_ID=14864569
192 11:31:37.035520 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:31:37.035614 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:31:37.035669 skipped lava-vland-overlay
195 11:31:37.035736 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:31:37.035806 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:31:37.035861 skipped lava-multinode-overlay
198 11:31:37.035925 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:31:37.035993 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:31:37.036056 Loading test definitions
201 11:31:37.036142 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:31:37.036199 Using /lava-14864569 at stage 0
203 11:31:37.036472 uuid=14864569_1.6.2.3.1 testdef=None
204 11:31:37.036550 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:31:37.036624 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:31:37.037008 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:31:37.037260 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:31:37.037756 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:31:37.037960 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:31:37.038436 runner path: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/0/tests/0_timesync-off test_uuid 14864569_1.6.2.3.1
213 11:31:37.038574 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:31:37.038772 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:31:37.038834 Using /lava-14864569 at stage 0
217 11:31:37.038919 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:31:37.038994 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/0/tests/1_kselftest-tpm2'
219 11:31:40.350184 Running '/usr/bin/git checkout kernelci.org
220 11:31:40.499135 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:31:40.499533 uuid=14864569_1.6.2.3.5 testdef=None
222 11:31:40.499658 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:31:40.499880 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 11:31:40.500533 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:31:40.500736 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 11:31:40.501645 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:31:40.501859 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 11:31:40.502715 runner path: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/0/tests/1_kselftest-tpm2 test_uuid 14864569_1.6.2.3.5
232 11:31:40.502799 BOARD='mt8192-asurada-spherion-r0'
233 11:31:40.502860 BRANCH='cip-gitlab'
234 11:31:40.502914 SKIPFILE='/dev/null'
235 11:31:40.502966 SKIP_INSTALL='True'
236 11:31:40.503016 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:31:40.503069 TST_CASENAME=''
238 11:31:40.503118 TST_CMDFILES='tpm2'
239 11:31:40.503251 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:31:40.503432 Creating lava-test-runner.conf files
242 11:31:40.503487 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864569/lava-overlay-s486sydu/lava-14864569/0 for stage 0
243 11:31:40.503571 - 0_timesync-off
244 11:31:40.503630 - 1_kselftest-tpm2
245 11:31:40.503717 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:31:40.503793 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 11:31:47.845515 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:31:47.845645 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:31:47.845731 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:31:47.845811 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:31:47.845887 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:31:47.990468 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:31:47.990627 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 11:31:47.990737 extracting modules file /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri
255 11:31:48.223904 extracting modules file /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864569/extract-overlay-ramdisk-suaoxg1f/ramdisk
256 11:31:48.496951 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:31:48.497090 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 11:31:48.497176 [common] Applying overlay to NFS
259 11:31:48.497235 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864569/compress-overlay-xj5qjwkb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri
260 11:31:49.339626 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:31:49.339771 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 11:31:49.339855 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:31:49.339932 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 11:31:49.340000 Building ramdisk /var/lib/lava/dispatcher/tmp/14864569/extract-overlay-ramdisk-suaoxg1f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864569/extract-overlay-ramdisk-suaoxg1f/ramdisk
265 11:31:49.614754 >> 129966 blocks
266 11:31:51.709570 rename /var/lib/lava/dispatcher/tmp/14864569/extract-overlay-ramdisk-suaoxg1f/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/ramdisk/ramdisk.cpio.gz
267 11:31:51.709738 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:31:51.709824 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:31:51.709901 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:31:51.709983 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/kernel/Image']
271 11:32:06.857901 Returned 0 in 15 seconds
272 11:32:06.858101 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/kernel/image.itb
273 11:32:07.215211 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:32:07.215357 output: Created: Wed Jul 17 12:32:07 2024
275 11:32:07.215421 output: Image 0 (kernel-1)
276 11:32:07.215505 output: Description:
277 11:32:07.215559 output: Created: Wed Jul 17 12:32:07 2024
278 11:32:07.215642 output: Type: Kernel Image
279 11:32:07.215725 output: Compression: lzma compressed
280 11:32:07.215805 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:32:07.215870 output: Architecture: AArch64
282 11:32:07.215932 output: OS: Linux
283 11:32:07.215980 output: Load Address: 0x00000000
284 11:32:07.216029 output: Entry Point: 0x00000000
285 11:32:07.216078 output: Hash algo: crc32
286 11:32:07.216128 output: Hash value: 83448d17
287 11:32:07.216178 output: Image 1 (fdt-1)
288 11:32:07.216226 output: Description: mt8192-asurada-spherion-r0
289 11:32:07.216275 output: Created: Wed Jul 17 12:32:07 2024
290 11:32:07.216323 output: Type: Flat Device Tree
291 11:32:07.216372 output: Compression: uncompressed
292 11:32:07.216420 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:32:07.216470 output: Architecture: AArch64
294 11:32:07.216519 output: Hash algo: crc32
295 11:32:07.216566 output: Hash value: 0f8e4d2e
296 11:32:07.216614 output: Image 2 (ramdisk-1)
297 11:32:07.216662 output: Description: unavailable
298 11:32:07.216710 output: Created: Wed Jul 17 12:32:07 2024
299 11:32:07.216759 output: Type: RAMDisk Image
300 11:32:07.216807 output: Compression: uncompressed
301 11:32:07.216855 output: Data Size: 18721045 Bytes = 18282.27 KiB = 17.85 MiB
302 11:32:07.216904 output: Architecture: AArch64
303 11:32:07.216951 output: OS: Linux
304 11:32:07.216999 output: Load Address: unavailable
305 11:32:07.217046 output: Entry Point: unavailable
306 11:32:07.217094 output: Hash algo: crc32
307 11:32:07.217158 output: Hash value: f339278c
308 11:32:07.217207 output: Default Configuration: 'conf-1'
309 11:32:07.217255 output: Configuration 0 (conf-1)
310 11:32:07.217302 output: Description: mt8192-asurada-spherion-r0
311 11:32:07.217350 output: Kernel: kernel-1
312 11:32:07.217398 output: Init Ramdisk: ramdisk-1
313 11:32:07.217445 output: FDT: fdt-1
314 11:32:07.217493 output: Loadables: kernel-1
315 11:32:07.217541 output:
316 11:32:07.217643 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 11:32:07.217719 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 11:32:07.217797 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 11:32:07.217879 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 11:32:07.217942 No LXC device requested
321 11:32:07.218077 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:32:07.218188 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 11:32:07.218306 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:32:07.218402 Checking files for TFTP limit of 4294967296 bytes.
325 11:32:07.218778 end: 1 tftp-deploy (duration 00:00:41) [common]
326 11:32:07.218867 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:32:07.218945 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:32:07.219057 substitutions:
329 11:32:07.219136 - {DTB}: 14864569/tftp-deploy-8d2pnof6/dtb/mt8192-asurada-spherion-r0.dtb
330 11:32:07.219252 - {INITRD}: 14864569/tftp-deploy-8d2pnof6/ramdisk/ramdisk.cpio.gz
331 11:32:07.219343 - {KERNEL}: 14864569/tftp-deploy-8d2pnof6/kernel/Image
332 11:32:07.219401 - {LAVA_MAC}: None
333 11:32:07.219453 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri
334 11:32:07.219504 - {NFS_SERVER_IP}: 192.168.201.1
335 11:32:07.219554 - {PRESEED_CONFIG}: None
336 11:32:07.219607 - {PRESEED_LOCAL}: None
337 11:32:07.219655 - {RAMDISK}: 14864569/tftp-deploy-8d2pnof6/ramdisk/ramdisk.cpio.gz
338 11:32:07.219704 - {ROOT_PART}: None
339 11:32:07.219769 - {ROOT}: None
340 11:32:07.219832 - {SERVER_IP}: 192.168.201.1
341 11:32:07.219879 - {TEE}: None
342 11:32:07.219926 Parsed boot commands:
343 11:32:07.219973 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:32:07.220111 Parsed boot commands: tftpboot 192.168.201.1 14864569/tftp-deploy-8d2pnof6/kernel/image.itb 14864569/tftp-deploy-8d2pnof6/kernel/cmdline
345 11:32:07.220190 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:32:07.220263 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:32:07.220334 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:32:07.220405 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:32:07.220459 Not connected, no need to disconnect.
350 11:32:07.220526 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:32:07.220593 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:32:07.220646 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 11:32:07.223773 Setting prompt string to ['lava-test: # ']
354 11:32:07.224104 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:32:07.224208 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:32:07.224323 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:32:07.224464 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:32:07.224698 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
359 11:32:16.410575 >> Command sent successfully.
360 11:32:16.418224 Returned 0 in 9 seconds
361 11:32:16.418503 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:32:16.418963 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:32:16.419165 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:32:16.419330 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:32:16.419462 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:32:16.419607 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:32:16.420551 [Enter `^Ec?' for help]
369 11:32:18.053554
370 11:32:18.054053
371 11:32:18.054386 F0: 102B 0000
372 11:32:18.054710
373 11:32:18.055002 F3: 1001 0000 [0200]
374 11:32:18.056954
375 11:32:18.057424 F3: 1001 0000
376 11:32:18.057759
377 11:32:18.058059 F7: 102D 0000
378 11:32:18.058464
379 11:32:18.060515 F1: 0000 0000
380 11:32:18.061044
381 11:32:18.061425 V0: 0000 0000 [0001]
382 11:32:18.061907
383 11:32:18.062239 00: 0007 8000
384 11:32:18.062570
385 11:32:18.064021 01: 0000 0000
386 11:32:18.064453
387 11:32:18.064778 BP: 0C00 0209 [0000]
388 11:32:18.065279
389 11:32:18.068077 G0: 1182 0000
390 11:32:18.068630
391 11:32:18.069049 EC: 0000 0021 [4000]
392 11:32:18.069665
393 11:32:18.071483 S7: 0000 0000 [0000]
394 11:32:18.071905
395 11:32:18.072259 CC: 0000 0000 [0001]
396 11:32:18.072683
397 11:32:18.074872 T0: 0000 0040 [010F]
398 11:32:18.075293
399 11:32:18.075622 Jump to BL
400 11:32:18.076073
401 11:32:18.100831
402 11:32:18.101365
403 11:32:18.107811 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 11:32:18.110822 ARM64: Exception handlers installed.
405 11:32:18.114145 ARM64: Testing exception
406 11:32:18.117709 ARM64: Done test exception
407 11:32:18.124114 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 11:32:18.134187 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 11:32:18.141006 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 11:32:18.150948 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 11:32:18.157600 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 11:32:18.168179 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 11:32:18.177973 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 11:32:18.184658 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 11:32:18.203332 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 11:32:18.206402 WDT: Last reset was cold boot
417 11:32:18.209765 SPI1(PAD0) initialized at 2873684 Hz
418 11:32:18.213206 SPI5(PAD0) initialized at 992727 Hz
419 11:32:18.216807 VBOOT: Loading verstage.
420 11:32:18.223474 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 11:32:18.226475 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 11:32:18.229872 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 11:32:18.232871 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 11:32:18.240384 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 11:32:18.246904 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 11:32:18.258177 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
427 11:32:18.258581
428 11:32:18.259022
429 11:32:18.268322 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 11:32:18.271539 ARM64: Exception handlers installed.
431 11:32:18.274781 ARM64: Testing exception
432 11:32:18.275162 ARM64: Done test exception
433 11:32:18.281253 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 11:32:18.284829 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 11:32:18.298893 Probing TPM: . done!
436 11:32:18.299351 TPM ready after 0 ms
437 11:32:18.305888 Connected to device vid:did:rid of 1ae0:0028:00
438 11:32:18.316137 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 11:32:18.352437 Initialized TPM device CR50 revision 0
440 11:32:18.363921 tlcl_send_startup: Startup return code is 0
441 11:32:18.364409 TPM: setup succeeded
442 11:32:18.375334 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 11:32:18.383984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 11:32:18.394275 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 11:32:18.402715 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 11:32:18.406568 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 11:32:18.409447 in-header: 03 07 00 00 08 00 00 00
448 11:32:18.413234 in-data: aa e4 47 04 13 02 00 00
449 11:32:18.416383 Chrome EC: UHEPI supported
450 11:32:18.422814 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 11:32:18.426356 in-header: 03 a9 00 00 08 00 00 00
452 11:32:18.429643 in-data: 84 60 60 08 00 00 00 00
453 11:32:18.430194 Phase 1
454 11:32:18.432600 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 11:32:18.439871 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 11:32:18.446343 VB2:vb2_check_recovery() Recovery was requested manually
457 11:32:18.449677 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
458 11:32:18.453822 Recovery requested (1009000e)
459 11:32:18.463588 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:32:18.466868 tlcl_extend: response is 0
461 11:32:18.476591 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:32:18.479999 tlcl_extend: response is 0
463 11:32:18.486494 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:32:18.507160 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 11:32:18.514493 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:32:18.514934
467 11:32:18.515266
468 11:32:18.524186 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:32:18.527489 ARM64: Exception handlers installed.
470 11:32:18.531076 ARM64: Testing exception
471 11:32:18.531507 ARM64: Done test exception
472 11:32:18.550450 pmic_efuse_setting: Set efuses in 11 msecs
473 11:32:18.558976 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:32:18.562892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:32:18.566416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:32:18.572583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:32:18.576661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:32:18.579709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:32:18.586664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:32:18.590115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:32:18.596818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:32:18.600350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:32:18.603810 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:32:18.610049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:32:18.614195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:32:18.616946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:32:18.624800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:32:18.630679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:32:18.637695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:32:18.640944 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:32:18.648556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:32:18.654871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:32:18.657768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:32:18.665069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:32:18.671619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:32:18.675300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:32:18.681356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:32:18.685021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:32:18.691548 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:32:18.698335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:32:18.701594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:32:18.704699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:32:18.711714 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:32:18.715070 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:32:18.722056 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:32:18.725426 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:32:18.731714 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:32:18.735155 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:32:18.742328 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:32:18.745471 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:32:18.752396 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:32:18.755423 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:32:18.758746 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:32:18.766126 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:32:18.769381 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:32:18.772708 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:32:18.776432 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:32:18.783045 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:32:18.786327 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:32:18.789799 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:32:18.796593 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:32:18.799722 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:32:18.803329 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:32:18.806707 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:32:18.816655 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
526 11:32:18.823671 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:32:18.830426 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:32:18.836686 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:32:18.847217 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:32:18.850210 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:32:18.853327 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:32:18.859986 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:32:18.867241 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 11:32:18.870107 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:32:18.877307 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:32:18.880806 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:32:18.890275 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 11:32:18.899834 [RTC]rtc_get_frequency_meter,154: input=23, output=980
539 11:32:18.909096 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 11:32:18.917917 [RTC]rtc_get_frequency_meter,154: input=17, output=838
541 11:32:18.927652 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 11:32:18.937444 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 11:32:18.946889 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 11:32:18.950827 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 11:32:18.957440 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 11:32:18.960708 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:32:18.964440 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:32:18.970724 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:32:18.973858 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:32:18.977659 ADC[4]: Raw value=901328 ID=7
551 11:32:18.978160 ADC[3]: Raw value=213336 ID=1
552 11:32:18.981289 RAM Code: 0x71
553 11:32:18.984603 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:32:18.991120 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:32:18.997763 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:32:19.004342 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:32:19.007938 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:32:19.011145 in-header: 03 07 00 00 08 00 00 00
559 11:32:19.014253 in-data: aa e4 47 04 13 02 00 00
560 11:32:19.017665 Chrome EC: UHEPI supported
561 11:32:19.024744 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:32:19.027802 in-header: 03 a9 00 00 08 00 00 00
563 11:32:19.031955 in-data: 84 60 60 08 00 00 00 00
564 11:32:19.034871 MRC: failed to locate region type 0.
565 11:32:19.041194 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:32:19.044706 DRAM-K: Running full calibration
567 11:32:19.051158 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:32:19.051625 header.status = 0x0
569 11:32:19.054137 header.version = 0x6 (expected: 0x6)
570 11:32:19.057853 header.size = 0xd00 (expected: 0xd00)
571 11:32:19.061254 header.flags = 0x0
572 11:32:19.068290 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:32:19.085015 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
574 11:32:19.091361 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:32:19.094532 dram_init: ddr_geometry: 2
576 11:32:19.097955 [EMI] MDL number = 2
577 11:32:19.098381 [EMI] Get MDL freq = 0
578 11:32:19.101339 dram_init: ddr_type: 0
579 11:32:19.101858 is_discrete_lpddr4: 1
580 11:32:19.104280 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:32:19.104709
582 11:32:19.105040
583 11:32:19.108772 [Bian_co] ETT version 0.0.0.1
584 11:32:19.114763 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:32:19.115257
586 11:32:19.117770 dramc_set_vcore_voltage set vcore to 650000
587 11:32:19.118199 Read voltage for 800, 4
588 11:32:19.121214 Vio18 = 0
589 11:32:19.121725 Vcore = 650000
590 11:32:19.122059 Vdram = 0
591 11:32:19.124487 Vddq = 0
592 11:32:19.124980 Vmddr = 0
593 11:32:19.127934 dram_init: config_dvfs: 1
594 11:32:19.131279 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:32:19.137875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:32:19.141301 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 11:32:19.145027 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 11:32:19.148083 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 11:32:19.152117 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 11:32:19.154914 MEM_TYPE=3, freq_sel=18
601 11:32:19.158287 sv_algorithm_assistance_LP4_1600
602 11:32:19.161550 ============ PULL DRAM RESETB DOWN ============
603 11:32:19.165087 ========== PULL DRAM RESETB DOWN end =========
604 11:32:19.171459 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:32:19.175177 ===================================
606 11:32:19.175563 LPDDR4 DRAM CONFIGURATION
607 11:32:19.178483 ===================================
608 11:32:19.182018 EX_ROW_EN[0] = 0x0
609 11:32:19.185029 EX_ROW_EN[1] = 0x0
610 11:32:19.185461 LP4Y_EN = 0x0
611 11:32:19.188495 WORK_FSP = 0x0
612 11:32:19.188877 WL = 0x2
613 11:32:19.191957 RL = 0x2
614 11:32:19.192339 BL = 0x2
615 11:32:19.194903 RPST = 0x0
616 11:32:19.195298 RD_PRE = 0x0
617 11:32:19.198899 WR_PRE = 0x1
618 11:32:19.199400 WR_PST = 0x0
619 11:32:19.202025 DBI_WR = 0x0
620 11:32:19.202487 DBI_RD = 0x0
621 11:32:19.205189 OTF = 0x1
622 11:32:19.208986 ===================================
623 11:32:19.211952 ===================================
624 11:32:19.212451 ANA top config
625 11:32:19.215957 ===================================
626 11:32:19.219570 DLL_ASYNC_EN = 0
627 11:32:19.220074 ALL_SLAVE_EN = 1
628 11:32:19.223095 NEW_RANK_MODE = 1
629 11:32:19.227371 DLL_IDLE_MODE = 1
630 11:32:19.227756 LP45_APHY_COMB_EN = 1
631 11:32:19.230756 TX_ODT_DIS = 1
632 11:32:19.234356 NEW_8X_MODE = 1
633 11:32:19.238204 ===================================
634 11:32:19.241847 ===================================
635 11:32:19.242255 data_rate = 1600
636 11:32:19.245774 CKR = 1
637 11:32:19.250200 DQ_P2S_RATIO = 8
638 11:32:19.253423 ===================================
639 11:32:19.253805 CA_P2S_RATIO = 8
640 11:32:19.256466 DQ_CA_OPEN = 0
641 11:32:19.259919 DQ_SEMI_OPEN = 0
642 11:32:19.263722 CA_SEMI_OPEN = 0
643 11:32:19.266753 CA_FULL_RATE = 0
644 11:32:19.269900 DQ_CKDIV4_EN = 1
645 11:32:19.270313 CA_CKDIV4_EN = 1
646 11:32:19.273356 CA_PREDIV_EN = 0
647 11:32:19.276658 PH8_DLY = 0
648 11:32:19.280141 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:32:19.283869 DQ_AAMCK_DIV = 4
650 11:32:19.284327 CA_AAMCK_DIV = 4
651 11:32:19.286512 CA_ADMCK_DIV = 4
652 11:32:19.290092 DQ_TRACK_CA_EN = 0
653 11:32:19.293622 CA_PICK = 800
654 11:32:19.296658 CA_MCKIO = 800
655 11:32:19.300043 MCKIO_SEMI = 0
656 11:32:19.303188 PLL_FREQ = 3068
657 11:32:19.303576 DQ_UI_PI_RATIO = 32
658 11:32:19.306485 CA_UI_PI_RATIO = 0
659 11:32:19.310710 ===================================
660 11:32:19.313745 ===================================
661 11:32:19.317656 memory_type:LPDDR4
662 11:32:19.320158 GP_NUM : 10
663 11:32:19.320600 SRAM_EN : 1
664 11:32:19.323476 MD32_EN : 0
665 11:32:19.326745 ===================================
666 11:32:19.327129 [ANA_INIT] >>>>>>>>>>>>>>
667 11:32:19.330166 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:32:19.333569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:32:19.336785 ===================================
670 11:32:19.339927 data_rate = 1600,PCW = 0X7600
671 11:32:19.343483 ===================================
672 11:32:19.346827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:32:19.354088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:32:19.356813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:32:19.364114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:32:19.367108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:32:19.370503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:32:19.370890 [ANA_INIT] flow start
679 11:32:19.373733 [ANA_INIT] PLL >>>>>>>>
680 11:32:19.376868 [ANA_INIT] PLL <<<<<<<<
681 11:32:19.380718 [ANA_INIT] MIDPI >>>>>>>>
682 11:32:19.381219 [ANA_INIT] MIDPI <<<<<<<<
683 11:32:19.384194 [ANA_INIT] DLL >>>>>>>>
684 11:32:19.384578 [ANA_INIT] flow end
685 11:32:19.390180 ============ LP4 DIFF to SE enter ============
686 11:32:19.393909 ============ LP4 DIFF to SE exit ============
687 11:32:19.397591 [ANA_INIT] <<<<<<<<<<<<<
688 11:32:19.400764 [Flow] Enable top DCM control >>>>>
689 11:32:19.404296 [Flow] Enable top DCM control <<<<<
690 11:32:19.404686 Enable DLL master slave shuffle
691 11:32:19.410758 ==============================================================
692 11:32:19.414270 Gating Mode config
693 11:32:19.417828 ==============================================================
694 11:32:19.421402 Config description:
695 11:32:19.431054 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:32:19.438332 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:32:19.440921 SELPH_MODE 0: By rank 1: By Phase
698 11:32:19.447881 ==============================================================
699 11:32:19.451216 GAT_TRACK_EN = 1
700 11:32:19.454097 RX_GATING_MODE = 2
701 11:32:19.454478 RX_GATING_TRACK_MODE = 2
702 11:32:19.457621 SELPH_MODE = 1
703 11:32:19.461196 PICG_EARLY_EN = 1
704 11:32:19.464465 VALID_LAT_VALUE = 1
705 11:32:19.471275 ==============================================================
706 11:32:19.474525 Enter into Gating configuration >>>>
707 11:32:19.478054 Exit from Gating configuration <<<<
708 11:32:19.481240 Enter into DVFS_PRE_config >>>>>
709 11:32:19.491408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:32:19.494848 Exit from DVFS_PRE_config <<<<<
711 11:32:19.498039 Enter into PICG configuration >>>>
712 11:32:19.501764 Exit from PICG configuration <<<<
713 11:32:19.505254 [RX_INPUT] configuration >>>>>
714 11:32:19.505663 [RX_INPUT] configuration <<<<<
715 11:32:19.511817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:32:19.518486 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:32:19.521713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:32:19.528601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:32:19.535283 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:32:19.541894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:32:19.545073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:32:19.548181 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:32:19.555221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:32:19.558814 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:32:19.561921 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:32:19.565539 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:32:19.568730 ===================================
728 11:32:19.571838 LPDDR4 DRAM CONFIGURATION
729 11:32:19.575410 ===================================
730 11:32:19.578664 EX_ROW_EN[0] = 0x0
731 11:32:19.579049 EX_ROW_EN[1] = 0x0
732 11:32:19.582257 LP4Y_EN = 0x0
733 11:32:19.582637 WORK_FSP = 0x0
734 11:32:19.585222 WL = 0x2
735 11:32:19.585604 RL = 0x2
736 11:32:19.589020 BL = 0x2
737 11:32:19.589470 RPST = 0x0
738 11:32:19.592370 RD_PRE = 0x0
739 11:32:19.592749 WR_PRE = 0x1
740 11:32:19.595715 WR_PST = 0x0
741 11:32:19.596150 DBI_WR = 0x0
742 11:32:19.598867 DBI_RD = 0x0
743 11:32:19.599393 OTF = 0x1
744 11:32:19.602338 ===================================
745 11:32:19.605380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:32:19.612293 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:32:19.615912 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:32:19.618914 ===================================
749 11:32:19.622465 LPDDR4 DRAM CONFIGURATION
750 11:32:19.625613 ===================================
751 11:32:19.625995 EX_ROW_EN[0] = 0x10
752 11:32:19.629222 EX_ROW_EN[1] = 0x0
753 11:32:19.629602 LP4Y_EN = 0x0
754 11:32:19.632258 WORK_FSP = 0x0
755 11:32:19.632684 WL = 0x2
756 11:32:19.635726 RL = 0x2
757 11:32:19.639467 BL = 0x2
758 11:32:19.639929 RPST = 0x0
759 11:32:19.643058 RD_PRE = 0x0
760 11:32:19.643486 WR_PRE = 0x1
761 11:32:19.646165 WR_PST = 0x0
762 11:32:19.646544 DBI_WR = 0x0
763 11:32:19.649640 DBI_RD = 0x0
764 11:32:19.650121 OTF = 0x1
765 11:32:19.652652 ===================================
766 11:32:19.659290 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:32:19.663000 nWR fixed to 40
768 11:32:19.666555 [ModeRegInit_LP4] CH0 RK0
769 11:32:19.666988 [ModeRegInit_LP4] CH0 RK1
770 11:32:19.669967 [ModeRegInit_LP4] CH1 RK0
771 11:32:19.673592 [ModeRegInit_LP4] CH1 RK1
772 11:32:19.674026 match AC timing 13
773 11:32:19.680158 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:32:19.683357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:32:19.687052 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:32:19.693066 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:32:19.696437 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:32:19.696820 [EMI DOE] emi_dcm 0
779 11:32:19.703657 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:32:19.704042 ==
781 11:32:19.706594 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:32:19.709951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:32:19.710338 ==
784 11:32:19.716652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:32:19.720042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:32:19.730112 [CA 0] Center 37 (6~68) winsize 63
787 11:32:19.733466 [CA 1] Center 37 (6~68) winsize 63
788 11:32:19.736849 [CA 2] Center 35 (5~66) winsize 62
789 11:32:19.740943 [CA 3] Center 34 (4~65) winsize 62
790 11:32:19.743506 [CA 4] Center 34 (3~65) winsize 63
791 11:32:19.747224 [CA 5] Center 34 (4~64) winsize 61
792 11:32:19.747688
793 11:32:19.750711 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:32:19.751090
795 11:32:19.753475 [CATrainingPosCal] consider 1 rank data
796 11:32:19.756895 u2DelayCellTimex100 = 270/100 ps
797 11:32:19.760756 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
798 11:32:19.764565 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
799 11:32:19.767716 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 11:32:19.771447 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
801 11:32:19.774606 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
802 11:32:19.778148 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 11:32:19.781219
804 11:32:19.785193 CA PerBit enable=1, Macro0, CA PI delay=34
805 11:32:19.785670
806 11:32:19.788104 [CBTSetCACLKResult] CA Dly = 34
807 11:32:19.788487 CS Dly: 4 (0~35)
808 11:32:19.788784 ==
809 11:32:19.791574 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:32:19.794995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:32:19.795394 ==
812 11:32:19.802322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:32:19.809196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:32:19.816612 [CA 0] Center 37 (6~68) winsize 63
815 11:32:19.819802 [CA 1] Center 37 (7~68) winsize 62
816 11:32:19.823560 [CA 2] Center 35 (5~66) winsize 62
817 11:32:19.826777 [CA 3] Center 35 (4~66) winsize 63
818 11:32:19.830020 [CA 4] Center 34 (3~65) winsize 63
819 11:32:19.833557 [CA 5] Center 33 (3~64) winsize 62
820 11:32:19.833964
821 11:32:19.836694 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:32:19.837105
823 11:32:19.840046 [CATrainingPosCal] consider 2 rank data
824 11:32:19.843099 u2DelayCellTimex100 = 270/100 ps
825 11:32:19.846538 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
826 11:32:19.849940 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 11:32:19.853739 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 11:32:19.860344 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
829 11:32:19.863594 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
830 11:32:19.866860 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 11:32:19.867270
832 11:32:19.870127 CA PerBit enable=1, Macro0, CA PI delay=34
833 11:32:19.870525
834 11:32:19.873703 [CBTSetCACLKResult] CA Dly = 34
835 11:32:19.874101 CS Dly: 5 (0~37)
836 11:32:19.874407
837 11:32:19.877246 ----->DramcWriteLeveling(PI) begin...
838 11:32:19.877659 ==
839 11:32:19.880525 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:32:19.887107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:32:19.887459 ==
842 11:32:19.890154 Write leveling (Byte 0): 29 => 29
843 11:32:19.890373 Write leveling (Byte 1): 33 => 33
844 11:32:19.893287 DramcWriteLeveling(PI) end<-----
845 11:32:19.893510
846 11:32:19.896974 ==
847 11:32:19.897171 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:32:19.903365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:32:19.903540 ==
850 11:32:19.907331 [Gating] SW mode calibration
851 11:32:19.913796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:32:19.917052 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:32:19.920474 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:32:19.927796 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:32:19.930973 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
856 11:32:19.934002 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:32:19.940708 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:32:19.943686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:32:19.947254 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:32:19.953763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:32:19.957313 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:32:19.960621 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:32:19.967562 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:32:19.970927 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:32:19.974505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:32:19.980835 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:32:19.984384 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:32:19.987550 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:32:19.991171 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:32:19.997654 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:32:20.001219 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 11:32:20.004918 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
873 11:32:20.011514 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:32:20.014778 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:32:20.017978 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:32:20.024423 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:32:20.027969 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:32:20.031593 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:32:20.037973 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
880 11:32:20.041562 0 9 12 | B1->B0 | 2525 3131 | 1 0 | (1 1) (0 0)
881 11:32:20.045041 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:32:20.048236 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:32:20.054759 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:32:20.058605 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:32:20.061736 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:32:20.068340 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:32:20.071663 0 10 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
888 11:32:20.075179 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
889 11:32:20.081827 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:32:20.085331 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:32:20.088486 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:32:20.094958 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:32:20.098748 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:32:20.101705 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:32:20.108177 0 11 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
896 11:32:20.111474 0 11 12 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
897 11:32:20.115440 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:32:20.118201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:32:20.125068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:32:20.128519 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:32:20.131989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:32:20.139172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:32:20.141855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:32:20.145183 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 11:32:20.152194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:32:20.155338 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:32:20.159112 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:32:20.165232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:32:20.168777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:32:20.171988 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:32:20.175520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:32:20.182268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:32:20.185830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:32:20.188911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:32:20.195371 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:32:20.198722 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:32:20.201936 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:32:20.209057 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:32:20.212670 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:32:20.216250 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 11:32:20.219087 Total UI for P1: 0, mck2ui 16
922 11:32:20.222611 best dqsien dly found for B0: ( 0, 14, 8)
923 11:32:20.226064 Total UI for P1: 0, mck2ui 16
924 11:32:20.229225 best dqsien dly found for B1: ( 0, 14, 8)
925 11:32:20.232641 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 11:32:20.235786 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 11:32:20.236173
928 11:32:20.239463 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 11:32:20.242859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:32:20.246212 [Gating] SW calibration Done
931 11:32:20.246599 ==
932 11:32:20.250018 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:32:20.256183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:32:20.256574 ==
935 11:32:20.256877 RX Vref Scan: 0
936 11:32:20.257202
937 11:32:20.259536 RX Vref 0 -> 0, step: 1
938 11:32:20.260033
939 11:32:20.262728 RX Delay -130 -> 252, step: 16
940 11:32:20.266008 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:32:20.269210 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:32:20.272648 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:32:20.276234 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:32:20.282939 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:32:20.286312 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 11:32:20.289613 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 11:32:20.292857 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 11:32:20.296666 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:32:20.300263 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 11:32:20.306549 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:32:20.309915 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 11:32:20.313321 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:32:20.316376 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
954 11:32:20.323567 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:32:20.326692 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:32:20.327077 ==
957 11:32:20.329711 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:32:20.333652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:32:20.334319 ==
960 11:32:20.334838 DQS Delay:
961 11:32:20.336481 DQS0 = 0, DQS1 = 0
962 11:32:20.336918 DQM Delay:
963 11:32:20.339737 DQM0 = 85, DQM1 = 78
964 11:32:20.340202 DQ Delay:
965 11:32:20.343175 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:32:20.346524 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
967 11:32:20.349822 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 11:32:20.352993 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
969 11:32:20.353527
970 11:32:20.353959
971 11:32:20.354369 ==
972 11:32:20.356438 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:32:20.359859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:32:20.360248 ==
975 11:32:20.360549
976 11:32:20.363305
977 11:32:20.363684 TX Vref Scan disable
978 11:32:20.366646 == TX Byte 0 ==
979 11:32:20.370180 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:32:20.373498 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:32:20.376782 == TX Byte 1 ==
982 11:32:20.380034 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
983 11:32:20.383311 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
984 11:32:20.383731 ==
985 11:32:20.386943 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:32:20.393506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:32:20.393756 ==
988 11:32:20.405319 TX Vref=22, minBit 5, minWin=27, winSum=444
989 11:32:20.408391 TX Vref=24, minBit 5, minWin=27, winSum=447
990 11:32:20.411670 TX Vref=26, minBit 3, minWin=27, winSum=447
991 11:32:20.415237 TX Vref=28, minBit 0, minWin=28, winSum=452
992 11:32:20.418459 TX Vref=30, minBit 12, minWin=27, winSum=454
993 11:32:20.422062 TX Vref=32, minBit 1, minWin=28, winSum=452
994 11:32:20.428408 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
995 11:32:20.428488
996 11:32:20.431582 Final TX Range 1 Vref 28
997 11:32:20.431666
998 11:32:20.431745 ==
999 11:32:20.435090 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:32:20.438635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:32:20.438733 ==
1002 11:32:20.438798
1003 11:32:20.441698
1004 11:32:20.441775 TX Vref Scan disable
1005 11:32:20.445043 == TX Byte 0 ==
1006 11:32:20.448843 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 11:32:20.451679 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 11:32:20.455154 == TX Byte 1 ==
1009 11:32:20.458456 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1010 11:32:20.461993 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1011 11:32:20.462132
1012 11:32:20.465388 [DATLAT]
1013 11:32:20.465484 Freq=800, CH0 RK0
1014 11:32:20.465561
1015 11:32:20.468627 DATLAT Default: 0xa
1016 11:32:20.468781 0, 0xFFFF, sum = 0
1017 11:32:20.471935 1, 0xFFFF, sum = 0
1018 11:32:20.472102 2, 0xFFFF, sum = 0
1019 11:32:20.475709 3, 0xFFFF, sum = 0
1020 11:32:20.475872 4, 0xFFFF, sum = 0
1021 11:32:20.479220 5, 0xFFFF, sum = 0
1022 11:32:20.479355 6, 0xFFFF, sum = 0
1023 11:32:20.482322 7, 0xFFFF, sum = 0
1024 11:32:20.482452 8, 0xFFFF, sum = 0
1025 11:32:20.485604 9, 0x0, sum = 1
1026 11:32:20.485753 10, 0x0, sum = 2
1027 11:32:20.489189 11, 0x0, sum = 3
1028 11:32:20.489400 12, 0x0, sum = 4
1029 11:32:20.492335 best_step = 10
1030 11:32:20.492543
1031 11:32:20.492680 ==
1032 11:32:20.496087 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:32:20.499269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:32:20.499539 ==
1035 11:32:20.502480 RX Vref Scan: 1
1036 11:32:20.502796
1037 11:32:20.502997 Set Vref Range= 32 -> 127
1038 11:32:20.503177
1039 11:32:20.505923 RX Vref 32 -> 127, step: 1
1040 11:32:20.506218
1041 11:32:20.509807 RX Delay -95 -> 252, step: 8
1042 11:32:20.510193
1043 11:32:20.512693 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:32:20.515730 [Byte1]: 32
1045 11:32:20.516116
1046 11:32:20.519572 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:32:20.522987 [Byte1]: 33
1048 11:32:20.523460
1049 11:32:20.526521 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:32:20.529647 [Byte1]: 34
1051 11:32:20.533644
1052 11:32:20.534159 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:32:20.537022 [Byte1]: 35
1054 11:32:20.541201
1055 11:32:20.541835 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:32:20.544704 [Byte1]: 36
1057 11:32:20.548376
1058 11:32:20.548761 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:32:20.551705 [Byte1]: 37
1060 11:32:20.556647
1061 11:32:20.557229 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:32:20.559279 [Byte1]: 38
1063 11:32:20.563472
1064 11:32:20.564005 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:32:20.567499 [Byte1]: 39
1066 11:32:20.571698
1067 11:32:20.572172 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:32:20.574791 [Byte1]: 40
1069 11:32:20.578762
1070 11:32:20.579145 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:32:20.582762 [Byte1]: 41
1072 11:32:20.586881
1073 11:32:20.587362 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:32:20.589821 [Byte1]: 42
1075 11:32:20.593869
1076 11:32:20.594251 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:32:20.597522 [Byte1]: 43
1078 11:32:20.601707
1079 11:32:20.602141 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:32:20.605241 [Byte1]: 44
1081 11:32:20.609276
1082 11:32:20.609701 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:32:20.612307 [Byte1]: 45
1084 11:32:20.617326
1085 11:32:20.617824 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:32:20.620381 [Byte1]: 46
1087 11:32:20.624531
1088 11:32:20.625007 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:32:20.627621 [Byte1]: 47
1090 11:32:20.632296
1091 11:32:20.632717 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:32:20.635616 [Byte1]: 48
1093 11:32:20.639465
1094 11:32:20.639853 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:32:20.643063 [Byte1]: 49
1096 11:32:20.647404
1097 11:32:20.647822 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:32:20.650668 [Byte1]: 50
1099 11:32:20.654721
1100 11:32:20.655109 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:32:20.657992 [Byte1]: 51
1102 11:32:20.662332
1103 11:32:20.662840 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:32:20.666018 [Byte1]: 52
1105 11:32:20.669813
1106 11:32:20.670204 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:32:20.673418 [Byte1]: 53
1108 11:32:20.677525
1109 11:32:20.678053 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:32:20.680981 [Byte1]: 54
1111 11:32:20.685423
1112 11:32:20.685821 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:32:20.688534 [Byte1]: 55
1114 11:32:20.693170
1115 11:32:20.693656 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:32:20.696427 [Byte1]: 56
1117 11:32:20.700821
1118 11:32:20.701330 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:32:20.703722 [Byte1]: 57
1120 11:32:20.708468
1121 11:32:20.708939 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:32:20.712168 [Byte1]: 58
1123 11:32:20.715812
1124 11:32:20.716340 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:32:20.718964 [Byte1]: 59
1126 11:32:20.723349
1127 11:32:20.723793 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:32:20.726759 [Byte1]: 60
1129 11:32:20.730641
1130 11:32:20.731032 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:32:20.734540 [Byte1]: 61
1132 11:32:20.738452
1133 11:32:20.738844 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:32:20.741835 [Byte1]: 62
1135 11:32:20.745843
1136 11:32:20.746232 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:32:20.749617 [Byte1]: 63
1138 11:32:20.753682
1139 11:32:20.754417 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:32:20.757013 [Byte1]: 64
1141 11:32:20.761255
1142 11:32:20.761648 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:32:20.764589 [Byte1]: 65
1144 11:32:20.768832
1145 11:32:20.769278 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:32:20.772345 [Byte1]: 66
1147 11:32:20.776050
1148 11:32:20.776437 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:32:20.779546 [Byte1]: 67
1150 11:32:20.783913
1151 11:32:20.784443 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:32:20.787125 [Byte1]: 68
1153 11:32:20.791637
1154 11:32:20.792098 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:32:20.795295 [Byte1]: 69
1156 11:32:20.799207
1157 11:32:20.799677 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:32:20.802776 [Byte1]: 70
1159 11:32:20.806873
1160 11:32:20.807354 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:32:20.809909 [Byte1]: 71
1162 11:32:20.814706
1163 11:32:20.815173 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:32:20.818204 [Byte1]: 72
1165 11:32:20.822072
1166 11:32:20.822461 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:32:20.825478 [Byte1]: 73
1168 11:32:20.829630
1169 11:32:20.830018 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:32:20.833454 [Byte1]: 74
1171 11:32:20.837274
1172 11:32:20.837771 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:32:20.840612 [Byte1]: 75
1174 11:32:20.844601
1175 11:32:20.845195 Final RX Vref Byte 0 = 59 to rank0
1176 11:32:20.848270 Final RX Vref Byte 1 = 58 to rank0
1177 11:32:20.851923 Final RX Vref Byte 0 = 59 to rank1
1178 11:32:20.855211 Final RX Vref Byte 1 = 58 to rank1==
1179 11:32:20.858348 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 11:32:20.862119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 11:32:20.864975 ==
1182 11:32:20.865534 DQS Delay:
1183 11:32:20.865872 DQS0 = 0, DQS1 = 0
1184 11:32:20.868479 DQM Delay:
1185 11:32:20.869048 DQM0 = 86, DQM1 = 78
1186 11:32:20.871841 DQ Delay:
1187 11:32:20.872345 DQ0 =88, DQ1 =84, DQ2 =84, DQ3 =84
1188 11:32:20.874980 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1189 11:32:20.878074 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1190 11:32:20.881789 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1191 11:32:20.882298
1192 11:32:20.885246
1193 11:32:20.891718 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1194 11:32:20.894813 CH0 RK0: MR19=606, MR18=2910
1195 11:32:20.901582 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1196 11:32:20.902142
1197 11:32:20.905175 ----->DramcWriteLeveling(PI) begin...
1198 11:32:20.905531 ==
1199 11:32:20.908955 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 11:32:20.912061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 11:32:20.912572 ==
1202 11:32:20.915251 Write leveling (Byte 0): 30 => 30
1203 11:32:20.918720 Write leveling (Byte 1): 30 => 30
1204 11:32:20.922433 DramcWriteLeveling(PI) end<-----
1205 11:32:20.922866
1206 11:32:20.923200 ==
1207 11:32:20.925255 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 11:32:20.928450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 11:32:20.928841 ==
1210 11:32:20.932165 [Gating] SW mode calibration
1211 11:32:20.938695 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 11:32:20.941718 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 11:32:20.948555 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 11:32:20.952144 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 11:32:20.955355 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1216 11:32:20.962048 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:32:20.965571 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:32:20.968815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:32:20.976192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:32:20.979532 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:32:20.982768 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:32:21.029807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:32:21.030428 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:32:21.031282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:32:21.031638 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:32:21.031944 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:32:21.032353 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:32:21.032755 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:32:21.033055 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1230 11:32:21.033409 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1231 11:32:21.033700 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1232 11:32:21.033980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:32:21.073824 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:32:21.074324 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:32:21.075242 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:32:21.075629 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:32:21.076040 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:32:21.076357 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1239 11:32:21.076715 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1240 11:32:21.077020 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1241 11:32:21.077413 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:32:21.077863 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:32:21.079278 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:32:21.085930 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:32:21.089165 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:32:21.092504 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1247 11:32:21.096508 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
1248 11:32:21.102624 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1249 11:32:21.105810 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:32:21.109734 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:32:21.115783 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:32:21.119314 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:32:21.123170 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:32:21.129438 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1255 11:32:21.132758 0 11 8 | B1->B0 | 2a2a 3f3f | 0 0 | (1 1) (0 0)
1256 11:32:21.136925 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1257 11:32:21.142953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:32:21.146591 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:32:21.149974 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:32:21.153260 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:32:21.160283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:32:21.163291 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:32:21.166758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1264 11:32:21.173220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:32:21.176253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:32:21.179674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:32:21.186746 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:32:21.190169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:32:21.193521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:32:21.200217 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:32:21.203603 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:32:21.206947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:32:21.209857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:32:21.217039 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:32:21.220203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:32:21.223340 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:32:21.230029 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1278 11:32:21.233599 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1279 11:32:21.237106 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 11:32:21.243998 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 11:32:21.244401 Total UI for P1: 0, mck2ui 16
1282 11:32:21.250012 best dqsien dly found for B0: ( 0, 14, 4)
1283 11:32:21.250408 Total UI for P1: 0, mck2ui 16
1284 11:32:21.256799 best dqsien dly found for B1: ( 0, 14, 8)
1285 11:32:21.260227 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1286 11:32:21.263277 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1287 11:32:21.263663
1288 11:32:21.266778 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 11:32:21.270343 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1290 11:32:21.273982 [Gating] SW calibration Done
1291 11:32:21.274371 ==
1292 11:32:21.277329 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 11:32:21.283698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 11:32:21.284148 ==
1295 11:32:21.284458 RX Vref Scan: 0
1296 11:32:21.285103
1297 11:32:21.285471 RX Vref 0 -> 0, step: 1
1298 11:32:21.285753
1299 11:32:21.287224 RX Delay -130 -> 252, step: 16
1300 11:32:21.290334 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1301 11:32:21.293743 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1302 11:32:21.300461 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1303 11:32:21.303808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1304 11:32:21.307457 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1305 11:32:21.310423 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1306 11:32:21.313795 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1307 11:32:21.320720 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1308 11:32:21.324050 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1309 11:32:21.327370 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1310 11:32:21.330935 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1311 11:32:21.333885 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1312 11:32:21.340867 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1313 11:32:21.344110 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1314 11:32:21.347188 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1315 11:32:21.351308 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1316 11:32:21.351823 ==
1317 11:32:21.354230 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:32:21.357674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:32:21.361265 ==
1320 11:32:21.361737 DQS Delay:
1321 11:32:21.362135 DQS0 = 0, DQS1 = 0
1322 11:32:21.363961 DQM Delay:
1323 11:32:21.364344 DQM0 = 85, DQM1 = 77
1324 11:32:21.367834 DQ Delay:
1325 11:32:21.368222 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1326 11:32:21.371244 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1327 11:32:21.374667 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1328 11:32:21.377804 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1329 11:32:21.378234
1330 11:32:21.378551
1331 11:32:21.381439 ==
1332 11:32:21.384734 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:32:21.387843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:32:21.388233 ==
1335 11:32:21.388534
1336 11:32:21.388807
1337 11:32:21.391187 TX Vref Scan disable
1338 11:32:21.391576 == TX Byte 0 ==
1339 11:32:21.394227 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1340 11:32:21.401094 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1341 11:32:21.401544 == TX Byte 1 ==
1342 11:32:21.404541 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1343 11:32:21.410876 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1344 11:32:21.411272 ==
1345 11:32:21.414411 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 11:32:21.418068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 11:32:21.418470 ==
1348 11:32:21.430975 TX Vref=22, minBit 3, minWin=27, winSum=446
1349 11:32:21.433761 TX Vref=24, minBit 7, minWin=27, winSum=449
1350 11:32:21.436926 TX Vref=26, minBit 9, minWin=27, winSum=450
1351 11:32:21.440594 TX Vref=28, minBit 0, minWin=28, winSum=455
1352 11:32:21.444197 TX Vref=30, minBit 0, minWin=28, winSum=454
1353 11:32:21.447346 TX Vref=32, minBit 0, minWin=28, winSum=453
1354 11:32:21.454099 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1355 11:32:21.454206
1356 11:32:21.457480 Final TX Range 1 Vref 28
1357 11:32:21.457568
1358 11:32:21.457653 ==
1359 11:32:21.461637 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:32:21.463901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:32:21.463982 ==
1362 11:32:21.464060
1363 11:32:21.464134
1364 11:32:21.467968 TX Vref Scan disable
1365 11:32:21.471025 == TX Byte 0 ==
1366 11:32:21.474527 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1367 11:32:21.477412 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1368 11:32:21.481056 == TX Byte 1 ==
1369 11:32:21.484294 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1370 11:32:21.487811 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1371 11:32:21.487915
1372 11:32:21.491432 [DATLAT]
1373 11:32:21.491508 Freq=800, CH0 RK1
1374 11:32:21.491567
1375 11:32:21.494366 DATLAT Default: 0xa
1376 11:32:21.494441 0, 0xFFFF, sum = 0
1377 11:32:21.497504 1, 0xFFFF, sum = 0
1378 11:32:21.497580 2, 0xFFFF, sum = 0
1379 11:32:21.500826 3, 0xFFFF, sum = 0
1380 11:32:21.500901 4, 0xFFFF, sum = 0
1381 11:32:21.504039 5, 0xFFFF, sum = 0
1382 11:32:21.504116 6, 0xFFFF, sum = 0
1383 11:32:21.507943 7, 0xFFFF, sum = 0
1384 11:32:21.508021 8, 0xFFFF, sum = 0
1385 11:32:21.510560 9, 0x0, sum = 1
1386 11:32:21.510642 10, 0x0, sum = 2
1387 11:32:21.514118 11, 0x0, sum = 3
1388 11:32:21.514199 12, 0x0, sum = 4
1389 11:32:21.517525 best_step = 10
1390 11:32:21.517606
1391 11:32:21.517668 ==
1392 11:32:21.520666 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 11:32:21.524625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 11:32:21.524707 ==
1395 11:32:21.524770 RX Vref Scan: 0
1396 11:32:21.524827
1397 11:32:21.528284 RX Vref 0 -> 0, step: 1
1398 11:32:21.528364
1399 11:32:21.531489 RX Delay -95 -> 252, step: 8
1400 11:32:21.534521 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1401 11:32:21.540883 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1402 11:32:21.544858 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1403 11:32:21.547971 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1404 11:32:21.551562 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1405 11:32:21.554734 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1406 11:32:21.561110 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1407 11:32:21.564621 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1408 11:32:21.568069 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1409 11:32:21.571459 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1410 11:32:21.574978 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1411 11:32:21.578350 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1412 11:32:21.584811 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1413 11:32:21.587979 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1414 11:32:21.591770 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1415 11:32:21.594622 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1416 11:32:21.594740 ==
1417 11:32:21.598429 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 11:32:21.604940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:32:21.605040 ==
1420 11:32:21.605113 DQS Delay:
1421 11:32:21.605191 DQS0 = 0, DQS1 = 0
1422 11:32:21.608133 DQM Delay:
1423 11:32:21.608226 DQM0 = 87, DQM1 = 77
1424 11:32:21.611776 DQ Delay:
1425 11:32:21.615063 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1426 11:32:21.615157 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1427 11:32:21.618326 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1428 11:32:21.621707 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1429 11:32:21.624904
1430 11:32:21.624997
1431 11:32:21.631629 [DQSOSCAuto] RK1, (LSB)MR18= 0x321c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1432 11:32:21.634974 CH0 RK1: MR19=606, MR18=321C
1433 11:32:21.641677 CH0_RK1: MR19=0x606, MR18=0x321C, DQSOSC=397, MR23=63, INC=93, DEC=62
1434 11:32:21.641785 [RxdqsGatingPostProcess] freq 800
1435 11:32:21.648727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 11:32:21.652319 Pre-setting of DQS Precalculation
1437 11:32:21.658530 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 11:32:21.658624 ==
1439 11:32:21.661809 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:32:21.665244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:32:21.665343 ==
1442 11:32:21.668385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 11:32:21.675654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 11:32:21.684782 [CA 0] Center 36 (6~66) winsize 61
1445 11:32:21.688922 [CA 1] Center 36 (6~66) winsize 61
1446 11:32:21.691898 [CA 2] Center 34 (4~65) winsize 62
1447 11:32:21.695113 [CA 3] Center 33 (3~64) winsize 62
1448 11:32:21.698564 [CA 4] Center 34 (3~65) winsize 63
1449 11:32:21.701944 [CA 5] Center 33 (3~64) winsize 62
1450 11:32:21.702041
1451 11:32:21.705262 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1452 11:32:21.705359
1453 11:32:21.709143 [CATrainingPosCal] consider 1 rank data
1454 11:32:21.711956 u2DelayCellTimex100 = 270/100 ps
1455 11:32:21.715537 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1456 11:32:21.718934 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1457 11:32:21.722273 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 11:32:21.728946 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 11:32:21.731908 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1460 11:32:21.735672 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1461 11:32:21.735777
1462 11:32:21.738626 CA PerBit enable=1, Macro0, CA PI delay=33
1463 11:32:21.738731
1464 11:32:21.741927 [CBTSetCACLKResult] CA Dly = 33
1465 11:32:21.742044 CS Dly: 4 (0~35)
1466 11:32:21.742160 ==
1467 11:32:21.746184 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 11:32:21.752557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 11:32:21.752682 ==
1470 11:32:21.755653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 11:32:21.762585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 11:32:21.771427 [CA 0] Center 36 (6~67) winsize 62
1473 11:32:21.774521 [CA 1] Center 36 (6~66) winsize 61
1474 11:32:21.777665 [CA 2] Center 34 (4~65) winsize 62
1475 11:32:21.781240 [CA 3] Center 33 (3~64) winsize 62
1476 11:32:21.784457 [CA 4] Center 34 (3~65) winsize 63
1477 11:32:21.788144 [CA 5] Center 33 (3~64) winsize 62
1478 11:32:21.788261
1479 11:32:21.791690 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1480 11:32:21.791805
1481 11:32:21.794736 [CATrainingPosCal] consider 2 rank data
1482 11:32:21.798266 u2DelayCellTimex100 = 270/100 ps
1483 11:32:21.801395 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1484 11:32:21.804979 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1485 11:32:21.808214 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1486 11:32:21.814716 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1487 11:32:21.818162 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1488 11:32:21.821291 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1489 11:32:21.821406
1490 11:32:21.825228 CA PerBit enable=1, Macro0, CA PI delay=33
1491 11:32:21.825344
1492 11:32:21.828442 [CBTSetCACLKResult] CA Dly = 33
1493 11:32:21.828557 CS Dly: 5 (0~37)
1494 11:32:21.828670
1495 11:32:21.831639 ----->DramcWriteLeveling(PI) begin...
1496 11:32:21.831755 ==
1497 11:32:21.835359 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 11:32:21.841950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 11:32:21.842064 ==
1500 11:32:21.845010 Write leveling (Byte 0): 27 => 27
1501 11:32:21.845133 Write leveling (Byte 1): 31 => 31
1502 11:32:21.848385 DramcWriteLeveling(PI) end<-----
1503 11:32:21.848497
1504 11:32:21.851733 ==
1505 11:32:21.851861 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 11:32:21.858621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 11:32:21.858765 ==
1508 11:32:21.861932 [Gating] SW mode calibration
1509 11:32:21.868676 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 11:32:21.872158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 11:32:21.878995 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 11:32:21.882374 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 11:32:21.885763 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:32:21.889145 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:32:21.895986 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:32:21.899046 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:32:21.902468 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:32:21.908925 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:32:21.912431 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:32:21.916236 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:32:21.923144 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:32:21.925997 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:32:21.929828 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:32:21.936231 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:32:21.939210 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:32:21.942709 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1527 11:32:21.946411 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 11:32:21.952962 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1529 11:32:21.956659 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1530 11:32:21.959297 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1531 11:32:21.966175 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:32:21.969573 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:32:21.972930 0 8 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1534 11:32:21.979514 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:32:21.983415 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:32:21.986801 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:32:21.993321 0 9 8 | B1->B0 | 2727 2525 | 1 1 | (1 1) (1 1)
1538 11:32:21.996409 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:32:22.000412 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:32:22.003597 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:32:22.010055 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1542 11:32:22.013605 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1543 11:32:22.016498 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1544 11:32:22.023317 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1545 11:32:22.027156 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
1546 11:32:22.030545 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:32:22.037221 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:32:22.040769 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:32:22.043827 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:32:22.050618 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:32:22.054367 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1552 11:32:22.057157 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:32:22.060897 0 11 8 | B1->B0 | 3737 3939 | 1 0 | (0 0) (0 0)
1554 11:32:22.067111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:32:22.070811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:32:22.074480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:32:22.080781 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:32:22.084288 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:32:22.087275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:32:22.094290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:32:22.097733 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 11:32:22.100588 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:32:22.107303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:32:22.111308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:32:22.114018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:32:22.117559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:32:22.124171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:32:22.127439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:32:22.131194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:32:22.138136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:32:22.141369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:32:22.144554 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:32:22.151330 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:32:22.154986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:32:22.157915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:32:22.161729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:32:22.168354 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 11:32:22.171671 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 11:32:22.175066 Total UI for P1: 0, mck2ui 16
1580 11:32:22.177890 best dqsien dly found for B0: ( 0, 14, 8)
1581 11:32:22.181928 Total UI for P1: 0, mck2ui 16
1582 11:32:22.185190 best dqsien dly found for B1: ( 0, 14, 8)
1583 11:32:22.188251 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1584 11:32:22.191871 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1585 11:32:22.192396
1586 11:32:22.195086 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1587 11:32:22.198389 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1588 11:32:22.201916 [Gating] SW calibration Done
1589 11:32:22.202404 ==
1590 11:32:22.205363 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 11:32:22.208316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 11:32:22.211680 ==
1593 11:32:22.212158 RX Vref Scan: 0
1594 11:32:22.212492
1595 11:32:22.214843 RX Vref 0 -> 0, step: 1
1596 11:32:22.215275
1597 11:32:22.215611 RX Delay -130 -> 252, step: 16
1598 11:32:22.222158 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1599 11:32:22.225399 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1600 11:32:22.228947 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1601 11:32:22.231867 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1602 11:32:22.235284 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1603 11:32:22.241841 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1604 11:32:22.245348 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1605 11:32:22.248302 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1606 11:32:22.252213 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1607 11:32:22.255253 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1608 11:32:22.261868 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1609 11:32:22.265787 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1610 11:32:22.269088 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1611 11:32:22.272078 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1612 11:32:22.275154 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1613 11:32:22.282085 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1614 11:32:22.282515 ==
1615 11:32:22.285306 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 11:32:22.289084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 11:32:22.289531 ==
1618 11:32:22.289837 DQS Delay:
1619 11:32:22.292640 DQS0 = 0, DQS1 = 0
1620 11:32:22.293110 DQM Delay:
1621 11:32:22.295604 DQM0 = 80, DQM1 = 74
1622 11:32:22.295992 DQ Delay:
1623 11:32:22.298773 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1624 11:32:22.302590 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1625 11:32:22.305737 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1626 11:32:22.308945 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1627 11:32:22.309521
1628 11:32:22.309841
1629 11:32:22.310122 ==
1630 11:32:22.312307 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 11:32:22.315641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 11:32:22.316033 ==
1633 11:32:22.316336
1634 11:32:22.316614
1635 11:32:22.319097 TX Vref Scan disable
1636 11:32:22.322290 == TX Byte 0 ==
1637 11:32:22.325861 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 11:32:22.329375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 11:32:22.332634 == TX Byte 1 ==
1640 11:32:22.336440 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1641 11:32:22.339158 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1642 11:32:22.339550 ==
1643 11:32:22.343033 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 11:32:22.346108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 11:32:22.346502 ==
1646 11:32:22.360298 TX Vref=22, minBit 0, minWin=27, winSum=440
1647 11:32:22.363883 TX Vref=24, minBit 10, minWin=27, winSum=445
1648 11:32:22.367803 TX Vref=26, minBit 4, minWin=27, winSum=448
1649 11:32:22.370834 TX Vref=28, minBit 2, minWin=28, winSum=455
1650 11:32:22.373772 TX Vref=30, minBit 1, minWin=28, winSum=454
1651 11:32:22.377003 TX Vref=32, minBit 1, minWin=28, winSum=457
1652 11:32:22.383801 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 32
1653 11:32:22.384233
1654 11:32:22.387523 Final TX Range 1 Vref 32
1655 11:32:22.387951
1656 11:32:22.388304 ==
1657 11:32:22.390770 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 11:32:22.394124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 11:32:22.394566 ==
1660 11:32:22.395029
1661 11:32:22.395645
1662 11:32:22.397036 TX Vref Scan disable
1663 11:32:22.400345 == TX Byte 0 ==
1664 11:32:22.404476 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 11:32:22.407561 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 11:32:22.411239 == TX Byte 1 ==
1667 11:32:22.414394 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1668 11:32:22.417520 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1669 11:32:22.417905
1670 11:32:22.421042 [DATLAT]
1671 11:32:22.421464 Freq=800, CH1 RK0
1672 11:32:22.421767
1673 11:32:22.424299 DATLAT Default: 0xa
1674 11:32:22.424677 0, 0xFFFF, sum = 0
1675 11:32:22.427928 1, 0xFFFF, sum = 0
1676 11:32:22.428456 2, 0xFFFF, sum = 0
1677 11:32:22.431183 3, 0xFFFF, sum = 0
1678 11:32:22.431582 4, 0xFFFF, sum = 0
1679 11:32:22.434271 5, 0xFFFF, sum = 0
1680 11:32:22.435008 6, 0xFFFF, sum = 0
1681 11:32:22.437682 7, 0xFFFF, sum = 0
1682 11:32:22.438113 8, 0xFFFF, sum = 0
1683 11:32:22.440672 9, 0x0, sum = 1
1684 11:32:22.441061 10, 0x0, sum = 2
1685 11:32:22.444174 11, 0x0, sum = 3
1686 11:32:22.444587 12, 0x0, sum = 4
1687 11:32:22.447538 best_step = 10
1688 11:32:22.448183
1689 11:32:22.448774 ==
1690 11:32:22.451473 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 11:32:22.454798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 11:32:22.455218 ==
1693 11:32:22.455534 RX Vref Scan: 1
1694 11:32:22.457784
1695 11:32:22.458167 Set Vref Range= 32 -> 127
1696 11:32:22.458467
1697 11:32:22.460943 RX Vref 32 -> 127, step: 1
1698 11:32:22.461352
1699 11:32:22.464366 RX Delay -95 -> 252, step: 8
1700 11:32:22.464941
1701 11:32:22.467632 Set Vref, RX VrefLevel [Byte0]: 32
1702 11:32:22.471528 [Byte1]: 32
1703 11:32:22.471909
1704 11:32:22.474707 Set Vref, RX VrefLevel [Byte0]: 33
1705 11:32:22.478013 [Byte1]: 33
1706 11:32:22.478393
1707 11:32:22.481215 Set Vref, RX VrefLevel [Byte0]: 34
1708 11:32:22.484260 [Byte1]: 34
1709 11:32:22.488504
1710 11:32:22.488928 Set Vref, RX VrefLevel [Byte0]: 35
1711 11:32:22.492160 [Byte1]: 35
1712 11:32:22.496281
1713 11:32:22.496743 Set Vref, RX VrefLevel [Byte0]: 36
1714 11:32:22.499570 [Byte1]: 36
1715 11:32:22.503823
1716 11:32:22.504324 Set Vref, RX VrefLevel [Byte0]: 37
1717 11:32:22.507024 [Byte1]: 37
1718 11:32:22.511698
1719 11:32:22.512195 Set Vref, RX VrefLevel [Byte0]: 38
1720 11:32:22.515028 [Byte1]: 38
1721 11:32:22.519016
1722 11:32:22.519521 Set Vref, RX VrefLevel [Byte0]: 39
1723 11:32:22.521920 [Byte1]: 39
1724 11:32:22.526717
1725 11:32:22.527215 Set Vref, RX VrefLevel [Byte0]: 40
1726 11:32:22.529875 [Byte1]: 40
1727 11:32:22.534546
1728 11:32:22.534970 Set Vref, RX VrefLevel [Byte0]: 41
1729 11:32:22.537863 [Byte1]: 41
1730 11:32:22.541639
1731 11:32:22.542132 Set Vref, RX VrefLevel [Byte0]: 42
1732 11:32:22.544703 [Byte1]: 42
1733 11:32:22.549421
1734 11:32:22.549842 Set Vref, RX VrefLevel [Byte0]: 43
1735 11:32:22.552407 [Byte1]: 43
1736 11:32:22.557055
1737 11:32:22.557607 Set Vref, RX VrefLevel [Byte0]: 44
1738 11:32:22.560427 [Byte1]: 44
1739 11:32:22.564904
1740 11:32:22.565449 Set Vref, RX VrefLevel [Byte0]: 45
1741 11:32:22.568044 [Byte1]: 45
1742 11:32:22.571759
1743 11:32:22.572180 Set Vref, RX VrefLevel [Byte0]: 46
1744 11:32:22.575145 [Byte1]: 46
1745 11:32:22.580070
1746 11:32:22.580493 Set Vref, RX VrefLevel [Byte0]: 47
1747 11:32:22.582796 [Byte1]: 47
1748 11:32:22.587128
1749 11:32:22.587548 Set Vref, RX VrefLevel [Byte0]: 48
1750 11:32:22.590254 [Byte1]: 48
1751 11:32:22.594657
1752 11:32:22.595093 Set Vref, RX VrefLevel [Byte0]: 49
1753 11:32:22.598114 [Byte1]: 49
1754 11:32:22.602287
1755 11:32:22.602749 Set Vref, RX VrefLevel [Byte0]: 50
1756 11:32:22.606033 [Byte1]: 50
1757 11:32:22.610133
1758 11:32:22.610635 Set Vref, RX VrefLevel [Byte0]: 51
1759 11:32:22.614157 [Byte1]: 51
1760 11:32:22.617811
1761 11:32:22.618352 Set Vref, RX VrefLevel [Byte0]: 52
1762 11:32:22.620736 [Byte1]: 52
1763 11:32:22.625166
1764 11:32:22.625594 Set Vref, RX VrefLevel [Byte0]: 53
1765 11:32:22.628543 [Byte1]: 53
1766 11:32:22.633659
1767 11:32:22.634217 Set Vref, RX VrefLevel [Byte0]: 54
1768 11:32:22.636310 [Byte1]: 54
1769 11:32:22.640172
1770 11:32:22.640745 Set Vref, RX VrefLevel [Byte0]: 55
1771 11:32:22.643732 [Byte1]: 55
1772 11:32:22.648102
1773 11:32:22.648589 Set Vref, RX VrefLevel [Byte0]: 56
1774 11:32:22.651663 [Byte1]: 56
1775 11:32:22.655554
1776 11:32:22.655980 Set Vref, RX VrefLevel [Byte0]: 57
1777 11:32:22.659161 [Byte1]: 57
1778 11:32:22.663167
1779 11:32:22.663669 Set Vref, RX VrefLevel [Byte0]: 58
1780 11:32:22.666970 [Byte1]: 58
1781 11:32:22.670954
1782 11:32:22.671453 Set Vref, RX VrefLevel [Byte0]: 59
1783 11:32:22.674388 [Byte1]: 59
1784 11:32:22.678922
1785 11:32:22.679429 Set Vref, RX VrefLevel [Byte0]: 60
1786 11:32:22.681301 [Byte1]: 60
1787 11:32:22.685964
1788 11:32:22.686467 Set Vref, RX VrefLevel [Byte0]: 61
1789 11:32:22.689395 [Byte1]: 61
1790 11:32:22.693528
1791 11:32:22.694027 Set Vref, RX VrefLevel [Byte0]: 62
1792 11:32:22.697212 [Byte1]: 62
1793 11:32:22.701725
1794 11:32:22.702227 Set Vref, RX VrefLevel [Byte0]: 63
1795 11:32:22.704348 [Byte1]: 63
1796 11:32:22.709160
1797 11:32:22.709660 Set Vref, RX VrefLevel [Byte0]: 64
1798 11:32:22.712312 [Byte1]: 64
1799 11:32:22.716739
1800 11:32:22.717284 Set Vref, RX VrefLevel [Byte0]: 65
1801 11:32:22.719668 [Byte1]: 65
1802 11:32:22.724081
1803 11:32:22.724582 Set Vref, RX VrefLevel [Byte0]: 66
1804 11:32:22.727335 [Byte1]: 66
1805 11:32:22.731877
1806 11:32:22.732374 Set Vref, RX VrefLevel [Byte0]: 67
1807 11:32:22.734912 [Byte1]: 67
1808 11:32:22.739479
1809 11:32:22.739981 Set Vref, RX VrefLevel [Byte0]: 68
1810 11:32:22.742852 [Byte1]: 68
1811 11:32:22.746648
1812 11:32:22.747199 Set Vref, RX VrefLevel [Byte0]: 69
1813 11:32:22.750086 [Byte1]: 69
1814 11:32:22.754316
1815 11:32:22.754740 Set Vref, RX VrefLevel [Byte0]: 70
1816 11:32:22.758177 [Byte1]: 70
1817 11:32:22.761856
1818 11:32:22.762311 Set Vref, RX VrefLevel [Byte0]: 71
1819 11:32:22.765253 [Byte1]: 71
1820 11:32:22.769736
1821 11:32:22.770251 Set Vref, RX VrefLevel [Byte0]: 72
1822 11:32:22.772746 [Byte1]: 72
1823 11:32:22.777362
1824 11:32:22.777860 Set Vref, RX VrefLevel [Byte0]: 73
1825 11:32:22.780723 [Byte1]: 73
1826 11:32:22.784627
1827 11:32:22.785175 Set Vref, RX VrefLevel [Byte0]: 74
1828 11:32:22.788041 [Byte1]: 74
1829 11:32:22.792658
1830 11:32:22.793181 Set Vref, RX VrefLevel [Byte0]: 75
1831 11:32:22.795616 [Byte1]: 75
1832 11:32:22.799779
1833 11:32:22.800255 Set Vref, RX VrefLevel [Byte0]: 76
1834 11:32:22.802985 [Byte1]: 76
1835 11:32:22.807551
1836 11:32:22.808161 Set Vref, RX VrefLevel [Byte0]: 77
1837 11:32:22.811075 [Byte1]: 77
1838 11:32:22.815032
1839 11:32:22.815415 Set Vref, RX VrefLevel [Byte0]: 78
1840 11:32:22.818367 [Byte1]: 78
1841 11:32:22.822559
1842 11:32:22.822863 Set Vref, RX VrefLevel [Byte0]: 79
1843 11:32:22.825800 [Byte1]: 79
1844 11:32:22.830052
1845 11:32:22.830339 Set Vref, RX VrefLevel [Byte0]: 80
1846 11:32:22.833200 [Byte1]: 80
1847 11:32:22.837698
1848 11:32:22.837915 Final RX Vref Byte 0 = 62 to rank0
1849 11:32:22.840945 Final RX Vref Byte 1 = 57 to rank0
1850 11:32:22.844098 Final RX Vref Byte 0 = 62 to rank1
1851 11:32:22.847869 Final RX Vref Byte 1 = 57 to rank1==
1852 11:32:22.851094 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 11:32:22.854313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 11:32:22.857605 ==
1855 11:32:22.857799 DQS Delay:
1856 11:32:22.857950 DQS0 = 0, DQS1 = 0
1857 11:32:22.861086 DQM Delay:
1858 11:32:22.861361 DQM0 = 83, DQM1 = 73
1859 11:32:22.864564 DQ Delay:
1860 11:32:22.864795 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =84
1861 11:32:22.867759 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1862 11:32:22.871008 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1863 11:32:22.874338 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1864 11:32:22.874545
1865 11:32:22.874733
1866 11:32:22.884854 [DQSOSCAuto] RK0, (LSB)MR18= 0x3206, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
1867 11:32:22.888064 CH1 RK0: MR19=606, MR18=3206
1868 11:32:22.891637 CH1_RK0: MR19=0x606, MR18=0x3206, DQSOSC=397, MR23=63, INC=93, DEC=62
1869 11:32:22.895318
1870 11:32:22.898197 ----->DramcWriteLeveling(PI) begin...
1871 11:32:22.898612 ==
1872 11:32:22.901484 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 11:32:22.904804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 11:32:22.905247 ==
1875 11:32:22.908255 Write leveling (Byte 0): 26 => 26
1876 11:32:22.911822 Write leveling (Byte 1): 29 => 29
1877 11:32:22.915112 DramcWriteLeveling(PI) end<-----
1878 11:32:22.915534
1879 11:32:22.915860 ==
1880 11:32:22.918280 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:32:22.921506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:32:22.921880 ==
1883 11:32:22.925237 [Gating] SW mode calibration
1884 11:32:22.931570 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 11:32:22.935012 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 11:32:22.941930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 11:32:22.945045 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1888 11:32:22.948344 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1889 11:32:22.955417 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1890 11:32:22.958690 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:32:22.962343 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:32:22.968879 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:32:22.972293 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:32:22.975633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:32:22.982093 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:32:22.985768 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 11:32:22.988843 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:32:22.995709 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:32:22.998607 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:32:23.002488 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 11:32:23.005563 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:32:23.012038 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1903 11:32:23.015615 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1904 11:32:23.018976 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:32:23.025508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:32:23.029112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:32:23.032294 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:32:23.039003 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:32:23.042174 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:32:23.045946 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:32:23.052633 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1912 11:32:23.055953 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1913 11:32:23.058960 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:32:23.062795 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:32:23.069449 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:32:23.072599 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1917 11:32:23.075905 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:32:23.082677 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1919 11:32:23.086160 0 10 4 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1920 11:32:23.089184 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:32:23.095955 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:32:23.099123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:32:23.102958 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:32:23.109384 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:32:23.112801 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:32:23.116270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:32:23.122650 0 11 4 | B1->B0 | 2828 4444 | 0 0 | (0 0) (1 1)
1928 11:32:23.126251 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1929 11:32:23.129864 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:32:23.133334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:32:23.139680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:32:23.143038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:32:23.146273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:32:23.153037 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:32:23.156460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1936 11:32:23.159454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:32:23.166213 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:32:23.169638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:32:23.172972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:32:23.179455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:32:23.182712 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:32:23.186414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:32:23.192807 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:32:23.196118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:32:23.199469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:32:23.206568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:32:23.209683 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:32:23.212894 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:32:23.216190 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:32:23.223281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:32:23.226527 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1952 11:32:23.229979 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1953 11:32:23.233347 Total UI for P1: 0, mck2ui 16
1954 11:32:23.237280 best dqsien dly found for B0: ( 0, 14, 4)
1955 11:32:23.243259 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 11:32:23.243652 Total UI for P1: 0, mck2ui 16
1957 11:32:23.250042 best dqsien dly found for B1: ( 0, 14, 6)
1958 11:32:23.253356 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1959 11:32:23.256802 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1960 11:32:23.257193
1961 11:32:23.260145 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1962 11:32:23.263379 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1963 11:32:23.266839 [Gating] SW calibration Done
1964 11:32:23.267188 ==
1965 11:32:23.270345 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 11:32:23.273527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 11:32:23.273894 ==
1968 11:32:23.274209 RX Vref Scan: 0
1969 11:32:23.274543
1970 11:32:23.277083 RX Vref 0 -> 0, step: 1
1971 11:32:23.277450
1972 11:32:23.280628 RX Delay -130 -> 252, step: 16
1973 11:32:23.283528 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1974 11:32:23.287193 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1975 11:32:23.293951 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1976 11:32:23.296973 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1977 11:32:23.300266 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1978 11:32:23.303770 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1979 11:32:23.307686 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1980 11:32:23.310936 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1981 11:32:23.317572 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1982 11:32:23.320946 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1983 11:32:23.324017 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1984 11:32:23.327900 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1985 11:32:23.330804 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1986 11:32:23.337580 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1987 11:32:23.341008 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1988 11:32:23.344366 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1989 11:32:23.344776 ==
1990 11:32:23.348171 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:32:23.350860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:32:23.351273 ==
1993 11:32:23.354457 DQS Delay:
1994 11:32:23.354832 DQS0 = 0, DQS1 = 0
1995 11:32:23.357977 DQM Delay:
1996 11:32:23.358309 DQM0 = 82, DQM1 = 77
1997 11:32:23.358610 DQ Delay:
1998 11:32:23.361212 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1999 11:32:23.364513 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
2000 11:32:23.367681 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
2001 11:32:23.371176 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2002 11:32:23.371499
2003 11:32:23.371794
2004 11:32:23.372070 ==
2005 11:32:23.374692 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 11:32:23.381239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 11:32:23.381599 ==
2008 11:32:23.381885
2009 11:32:23.382156
2010 11:32:23.382421 TX Vref Scan disable
2011 11:32:23.385098 == TX Byte 0 ==
2012 11:32:23.388597 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2013 11:32:23.391818 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2014 11:32:23.394665 == TX Byte 1 ==
2015 11:32:23.398675 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2016 11:32:23.401961 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2017 11:32:23.404730 ==
2018 11:32:23.408139 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 11:32:23.411567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 11:32:23.411915 ==
2021 11:32:23.424505 TX Vref=22, minBit 1, minWin=27, winSum=441
2022 11:32:23.427529 TX Vref=24, minBit 9, minWin=27, winSum=449
2023 11:32:23.431040 TX Vref=26, minBit 1, minWin=27, winSum=444
2024 11:32:23.433967 TX Vref=28, minBit 0, minWin=28, winSum=452
2025 11:32:23.437558 TX Vref=30, minBit 0, minWin=28, winSum=452
2026 11:32:23.440739 TX Vref=32, minBit 0, minWin=28, winSum=452
2027 11:32:23.447762 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
2028 11:32:23.448344
2029 11:32:23.450935 Final TX Range 1 Vref 28
2030 11:32:23.451574
2031 11:32:23.452109 ==
2032 11:32:23.454377 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 11:32:23.457093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 11:32:23.457206 ==
2035 11:32:23.457264
2036 11:32:23.457317
2037 11:32:23.460503 TX Vref Scan disable
2038 11:32:23.464171 == TX Byte 0 ==
2039 11:32:23.467117 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2040 11:32:23.470604 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2041 11:32:23.474454 == TX Byte 1 ==
2042 11:32:23.477678 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2043 11:32:23.480841 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2044 11:32:23.480936
2045 11:32:23.484473 [DATLAT]
2046 11:32:23.484540 Freq=800, CH1 RK1
2047 11:32:23.484618
2048 11:32:23.487326 DATLAT Default: 0xa
2049 11:32:23.487392 0, 0xFFFF, sum = 0
2050 11:32:23.490894 1, 0xFFFF, sum = 0
2051 11:32:23.490983 2, 0xFFFF, sum = 0
2052 11:32:23.494821 3, 0xFFFF, sum = 0
2053 11:32:23.494916 4, 0xFFFF, sum = 0
2054 11:32:23.497568 5, 0xFFFF, sum = 0
2055 11:32:23.497645 6, 0xFFFF, sum = 0
2056 11:32:23.500818 7, 0xFFFF, sum = 0
2057 11:32:23.500895 8, 0xFFFF, sum = 0
2058 11:32:23.503990 9, 0x0, sum = 1
2059 11:32:23.504067 10, 0x0, sum = 2
2060 11:32:23.507818 11, 0x0, sum = 3
2061 11:32:23.507894 12, 0x0, sum = 4
2062 11:32:23.510754 best_step = 10
2063 11:32:23.510829
2064 11:32:23.510886 ==
2065 11:32:23.514045 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 11:32:23.517437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 11:32:23.517512 ==
2068 11:32:23.517571 RX Vref Scan: 0
2069 11:32:23.520995
2070 11:32:23.521089 RX Vref 0 -> 0, step: 1
2071 11:32:23.521193
2072 11:32:23.524242 RX Delay -95 -> 252, step: 8
2073 11:32:23.527490 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2074 11:32:23.534175 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2075 11:32:23.537727 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2076 11:32:23.541108 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2077 11:32:23.544804 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2078 11:32:23.547615 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2079 11:32:23.554339 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2080 11:32:23.557907 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2081 11:32:23.561105 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2082 11:32:23.565026 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2083 11:32:23.567758 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2084 11:32:23.571351 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2085 11:32:23.578187 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2086 11:32:23.581703 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2087 11:32:23.584554 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2088 11:32:23.588386 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2089 11:32:23.588453 ==
2090 11:32:23.591417 Dram Type= 6, Freq= 0, CH_1, rank 1
2091 11:32:23.598157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2092 11:32:23.598229 ==
2093 11:32:23.598287 DQS Delay:
2094 11:32:23.601592 DQS0 = 0, DQS1 = 0
2095 11:32:23.601660 DQM Delay:
2096 11:32:23.601731 DQM0 = 80, DQM1 = 75
2097 11:32:23.604989 DQ Delay:
2098 11:32:23.608515 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2099 11:32:23.612074 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
2100 11:32:23.615036 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2101 11:32:23.618198 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2102 11:32:23.618265
2103 11:32:23.618320
2104 11:32:23.624970 [DQSOSCAuto] RK1, (LSB)MR18= 0x2732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2105 11:32:23.628604 CH1 RK1: MR19=606, MR18=2732
2106 11:32:23.635035 CH1_RK1: MR19=0x606, MR18=0x2732, DQSOSC=397, MR23=63, INC=93, DEC=62
2107 11:32:23.638294 [RxdqsGatingPostProcess] freq 800
2108 11:32:23.642116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2109 11:32:23.645095 Pre-setting of DQS Precalculation
2110 11:32:23.652101 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2111 11:32:23.658707 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2112 11:32:23.664955 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2113 11:32:23.665062
2114 11:32:23.665165
2115 11:32:23.668693 [Calibration Summary] 1600 Mbps
2116 11:32:23.668835 CH 0, Rank 0
2117 11:32:23.672186 SW Impedance : PASS
2118 11:32:23.672284 DUTY Scan : NO K
2119 11:32:23.675582 ZQ Calibration : PASS
2120 11:32:23.678640 Jitter Meter : NO K
2121 11:32:23.678714 CBT Training : PASS
2122 11:32:23.682013 Write leveling : PASS
2123 11:32:23.685669 RX DQS gating : PASS
2124 11:32:23.685739 RX DQ/DQS(RDDQC) : PASS
2125 11:32:23.688808 TX DQ/DQS : PASS
2126 11:32:23.692507 RX DATLAT : PASS
2127 11:32:23.692581 RX DQ/DQS(Engine): PASS
2128 11:32:23.695932 TX OE : NO K
2129 11:32:23.696002 All Pass.
2130 11:32:23.696073
2131 11:32:23.696142 CH 0, Rank 1
2132 11:32:23.699418 SW Impedance : PASS
2133 11:32:23.702417 DUTY Scan : NO K
2134 11:32:23.702484 ZQ Calibration : PASS
2135 11:32:23.705818 Jitter Meter : NO K
2136 11:32:23.709243 CBT Training : PASS
2137 11:32:23.709310 Write leveling : PASS
2138 11:32:23.712835 RX DQS gating : PASS
2139 11:32:23.715848 RX DQ/DQS(RDDQC) : PASS
2140 11:32:23.715916 TX DQ/DQS : PASS
2141 11:32:23.719204 RX DATLAT : PASS
2142 11:32:23.722702 RX DQ/DQS(Engine): PASS
2143 11:32:23.722777 TX OE : NO K
2144 11:32:23.722868 All Pass.
2145 11:32:23.722956
2146 11:32:23.725882 CH 1, Rank 0
2147 11:32:23.729257 SW Impedance : PASS
2148 11:32:23.729325 DUTY Scan : NO K
2149 11:32:23.732768 ZQ Calibration : PASS
2150 11:32:23.732835 Jitter Meter : NO K
2151 11:32:23.736081 CBT Training : PASS
2152 11:32:23.739865 Write leveling : PASS
2153 11:32:23.739936 RX DQS gating : PASS
2154 11:32:23.742748 RX DQ/DQS(RDDQC) : PASS
2155 11:32:23.745944 TX DQ/DQS : PASS
2156 11:32:23.746012 RX DATLAT : PASS
2157 11:32:23.750120 RX DQ/DQS(Engine): PASS
2158 11:32:23.752601 TX OE : NO K
2159 11:32:23.752670 All Pass.
2160 11:32:23.752742
2161 11:32:23.752814 CH 1, Rank 1
2162 11:32:23.755883 SW Impedance : PASS
2163 11:32:23.759693 DUTY Scan : NO K
2164 11:32:23.759787 ZQ Calibration : PASS
2165 11:32:23.762808 Jitter Meter : NO K
2166 11:32:23.762882 CBT Training : PASS
2167 11:32:23.766347 Write leveling : PASS
2168 11:32:23.769362 RX DQS gating : PASS
2169 11:32:23.769440 RX DQ/DQS(RDDQC) : PASS
2170 11:32:23.772948 TX DQ/DQS : PASS
2171 11:32:23.776565 RX DATLAT : PASS
2172 11:32:23.776657 RX DQ/DQS(Engine): PASS
2173 11:32:23.779505 TX OE : NO K
2174 11:32:23.779578 All Pass.
2175 11:32:23.779636
2176 11:32:23.783395 DramC Write-DBI off
2177 11:32:23.786152 PER_BANK_REFRESH: Hybrid Mode
2178 11:32:23.786229 TX_TRACKING: ON
2179 11:32:23.789791 [GetDramInforAfterCalByMRR] Vendor 6.
2180 11:32:23.793260 [GetDramInforAfterCalByMRR] Revision 606.
2181 11:32:23.796832 [GetDramInforAfterCalByMRR] Revision 2 0.
2182 11:32:23.800203 MR0 0x3b3b
2183 11:32:23.800277 MR8 0x5151
2184 11:32:23.803380 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2185 11:32:23.803456
2186 11:32:23.803515 MR0 0x3b3b
2187 11:32:23.806636 MR8 0x5151
2188 11:32:23.809823 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2189 11:32:23.809897
2190 11:32:23.817171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2191 11:32:23.820488 [FAST_K] Save calibration result to emmc
2192 11:32:23.826748 [FAST_K] Save calibration result to emmc
2193 11:32:23.826822 dram_init: config_dvfs: 1
2194 11:32:23.830494 dramc_set_vcore_voltage set vcore to 662500
2195 11:32:23.833763 Read voltage for 1200, 2
2196 11:32:23.833837 Vio18 = 0
2197 11:32:23.837107 Vcore = 662500
2198 11:32:23.837203 Vdram = 0
2199 11:32:23.837260 Vddq = 0
2200 11:32:23.840400 Vmddr = 0
2201 11:32:23.843831 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2202 11:32:23.850229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2203 11:32:23.850302 MEM_TYPE=3, freq_sel=15
2204 11:32:23.853540 sv_algorithm_assistance_LP4_1600
2205 11:32:23.856818 ============ PULL DRAM RESETB DOWN ============
2206 11:32:23.863840 ========== PULL DRAM RESETB DOWN end =========
2207 11:32:23.867241 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2208 11:32:23.870440 ===================================
2209 11:32:23.873735 LPDDR4 DRAM CONFIGURATION
2210 11:32:23.877312 ===================================
2211 11:32:23.877379 EX_ROW_EN[0] = 0x0
2212 11:32:23.880676 EX_ROW_EN[1] = 0x0
2213 11:32:23.880745 LP4Y_EN = 0x0
2214 11:32:23.883886 WORK_FSP = 0x0
2215 11:32:23.883950 WL = 0x4
2216 11:32:23.887291 RL = 0x4
2217 11:32:23.890894 BL = 0x2
2218 11:32:23.890958 RPST = 0x0
2219 11:32:23.894032 RD_PRE = 0x0
2220 11:32:23.894097 WR_PRE = 0x1
2221 11:32:23.897430 WR_PST = 0x0
2222 11:32:23.897494 DBI_WR = 0x0
2223 11:32:23.901009 DBI_RD = 0x0
2224 11:32:23.901127 OTF = 0x1
2225 11:32:23.904137 ===================================
2226 11:32:23.907566 ===================================
2227 11:32:23.907640 ANA top config
2228 11:32:23.910513 ===================================
2229 11:32:23.914316 DLL_ASYNC_EN = 0
2230 11:32:23.917348 ALL_SLAVE_EN = 0
2231 11:32:23.920677 NEW_RANK_MODE = 1
2232 11:32:23.924402 DLL_IDLE_MODE = 1
2233 11:32:23.924476 LP45_APHY_COMB_EN = 1
2234 11:32:23.927546 TX_ODT_DIS = 1
2235 11:32:23.930726 NEW_8X_MODE = 1
2236 11:32:23.934264 ===================================
2237 11:32:23.937812 ===================================
2238 11:32:23.941017 data_rate = 2400
2239 11:32:23.944216 CKR = 1
2240 11:32:23.944290 DQ_P2S_RATIO = 8
2241 11:32:23.947649 ===================================
2242 11:32:23.951566 CA_P2S_RATIO = 8
2243 11:32:23.954678 DQ_CA_OPEN = 0
2244 11:32:23.957867 DQ_SEMI_OPEN = 0
2245 11:32:23.961269 CA_SEMI_OPEN = 0
2246 11:32:23.961335 CA_FULL_RATE = 0
2247 11:32:23.964140 DQ_CKDIV4_EN = 0
2248 11:32:23.967557 CA_CKDIV4_EN = 0
2249 11:32:23.971222 CA_PREDIV_EN = 0
2250 11:32:23.974543 PH8_DLY = 17
2251 11:32:23.977974 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2252 11:32:23.978041 DQ_AAMCK_DIV = 4
2253 11:32:23.980864 CA_AAMCK_DIV = 4
2254 11:32:23.984241 CA_ADMCK_DIV = 4
2255 11:32:23.987654 DQ_TRACK_CA_EN = 0
2256 11:32:23.990972 CA_PICK = 1200
2257 11:32:23.994240 CA_MCKIO = 1200
2258 11:32:23.994321 MCKIO_SEMI = 0
2259 11:32:23.997596 PLL_FREQ = 2366
2260 11:32:24.000935 DQ_UI_PI_RATIO = 32
2261 11:32:24.004439 CA_UI_PI_RATIO = 0
2262 11:32:24.008096 ===================================
2263 11:32:24.011065 ===================================
2264 11:32:24.014897 memory_type:LPDDR4
2265 11:32:24.015022 GP_NUM : 10
2266 11:32:24.018259 SRAM_EN : 1
2267 11:32:24.021894 MD32_EN : 0
2268 11:32:24.024814 ===================================
2269 11:32:24.024928 [ANA_INIT] >>>>>>>>>>>>>>
2270 11:32:24.027985 <<<<<< [CONFIGURE PHASE]: ANA_TX
2271 11:32:24.031543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2272 11:32:24.034484 ===================================
2273 11:32:24.038112 data_rate = 2400,PCW = 0X5b00
2274 11:32:24.041146 ===================================
2275 11:32:24.044408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2276 11:32:24.051197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 11:32:24.054971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 11:32:24.061282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2279 11:32:24.064734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2280 11:32:24.068163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2281 11:32:24.068230 [ANA_INIT] flow start
2282 11:32:24.071540 [ANA_INIT] PLL >>>>>>>>
2283 11:32:24.074945 [ANA_INIT] PLL <<<<<<<<
2284 11:32:24.075039 [ANA_INIT] MIDPI >>>>>>>>
2285 11:32:24.078493 [ANA_INIT] MIDPI <<<<<<<<
2286 11:32:24.081388 [ANA_INIT] DLL >>>>>>>>
2287 11:32:24.081478 [ANA_INIT] DLL <<<<<<<<
2288 11:32:24.084704 [ANA_INIT] flow end
2289 11:32:24.088254 ============ LP4 DIFF to SE enter ============
2290 11:32:24.091585 ============ LP4 DIFF to SE exit ============
2291 11:32:24.094876 [ANA_INIT] <<<<<<<<<<<<<
2292 11:32:24.098261 [Flow] Enable top DCM control >>>>>
2293 11:32:24.101902 [Flow] Enable top DCM control <<<<<
2294 11:32:24.104899 Enable DLL master slave shuffle
2295 11:32:24.111781 ==============================================================
2296 11:32:24.111855 Gating Mode config
2297 11:32:24.118693 ==============================================================
2298 11:32:24.118762 Config description:
2299 11:32:24.128818 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2300 11:32:24.135110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2301 11:32:24.142016 SELPH_MODE 0: By rank 1: By Phase
2302 11:32:24.145270 ==============================================================
2303 11:32:24.148802 GAT_TRACK_EN = 1
2304 11:32:24.151987 RX_GATING_MODE = 2
2305 11:32:24.155456 RX_GATING_TRACK_MODE = 2
2306 11:32:24.158642 SELPH_MODE = 1
2307 11:32:24.162183 PICG_EARLY_EN = 1
2308 11:32:24.165463 VALID_LAT_VALUE = 1
2309 11:32:24.168761 ==============================================================
2310 11:32:24.172382 Enter into Gating configuration >>>>
2311 11:32:24.175677 Exit from Gating configuration <<<<
2312 11:32:24.178939 Enter into DVFS_PRE_config >>>>>
2313 11:32:24.189125 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2314 11:32:24.192482 Exit from DVFS_PRE_config <<<<<
2315 11:32:24.195907 Enter into PICG configuration >>>>
2316 11:32:24.199501 Exit from PICG configuration <<<<
2317 11:32:24.202325 [RX_INPUT] configuration >>>>>
2318 11:32:24.205778 [RX_INPUT] configuration <<<<<
2319 11:32:24.208985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2320 11:32:24.216152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2321 11:32:24.222592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 11:32:24.229813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 11:32:24.236346 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 11:32:24.240036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 11:32:24.246542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2326 11:32:24.249717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2327 11:32:24.253135 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2328 11:32:24.256158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2329 11:32:24.259732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2330 11:32:24.266121 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 11:32:24.270087 ===================================
2332 11:32:24.272880 LPDDR4 DRAM CONFIGURATION
2333 11:32:24.276485 ===================================
2334 11:32:24.276560 EX_ROW_EN[0] = 0x0
2335 11:32:24.280032 EX_ROW_EN[1] = 0x0
2336 11:32:24.280119 LP4Y_EN = 0x0
2337 11:32:24.283142 WORK_FSP = 0x0
2338 11:32:24.283219 WL = 0x4
2339 11:32:24.286630 RL = 0x4
2340 11:32:24.286722 BL = 0x2
2341 11:32:24.289778 RPST = 0x0
2342 11:32:24.289869 RD_PRE = 0x0
2343 11:32:24.293099 WR_PRE = 0x1
2344 11:32:24.293236 WR_PST = 0x0
2345 11:32:24.296623 DBI_WR = 0x0
2346 11:32:24.296713 DBI_RD = 0x0
2347 11:32:24.300158 OTF = 0x1
2348 11:32:24.303451 ===================================
2349 11:32:24.306868 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2350 11:32:24.309822 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2351 11:32:24.316469 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2352 11:32:24.319791 ===================================
2353 11:32:24.319865 LPDDR4 DRAM CONFIGURATION
2354 11:32:24.323306 ===================================
2355 11:32:24.326750 EX_ROW_EN[0] = 0x10
2356 11:32:24.326826 EX_ROW_EN[1] = 0x0
2357 11:32:24.329830 LP4Y_EN = 0x0
2358 11:32:24.333371 WORK_FSP = 0x0
2359 11:32:24.333449 WL = 0x4
2360 11:32:24.336534 RL = 0x4
2361 11:32:24.336608 BL = 0x2
2362 11:32:24.340307 RPST = 0x0
2363 11:32:24.340382 RD_PRE = 0x0
2364 11:32:24.343168 WR_PRE = 0x1
2365 11:32:24.343243 WR_PST = 0x0
2366 11:32:24.346749 DBI_WR = 0x0
2367 11:32:24.346849 DBI_RD = 0x0
2368 11:32:24.349884 OTF = 0x1
2369 11:32:24.353270 ===================================
2370 11:32:24.356818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2371 11:32:24.360586 ==
2372 11:32:24.363769 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 11:32:24.366664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 11:32:24.366737 ==
2375 11:32:24.370572 [Duty_Offset_Calibration]
2376 11:32:24.370638 B0:2 B1:-1 CA:1
2377 11:32:24.370693
2378 11:32:24.373371 [DutyScan_Calibration_Flow] k_type=0
2379 11:32:24.382213
2380 11:32:24.382288 ==CLK 0==
2381 11:32:24.385578 Final CLK duty delay cell = -4
2382 11:32:24.388955 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2383 11:32:24.391944 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2384 11:32:24.395788 [-4] AVG Duty = 4937%(X100)
2385 11:32:24.395857
2386 11:32:24.398821 CH0 CLK Duty spec in!! Max-Min= 125%
2387 11:32:24.402397 [DutyScan_Calibration_Flow] ====Done====
2388 11:32:24.402462
2389 11:32:24.405448 [DutyScan_Calibration_Flow] k_type=1
2390 11:32:24.421101
2391 11:32:24.421225 ==DQS 0 ==
2392 11:32:24.424393 Final DQS duty delay cell = 0
2393 11:32:24.427623 [0] MAX Duty = 5125%(X100), DQS PI = 48
2394 11:32:24.431085 [0] MIN Duty = 5000%(X100), DQS PI = 12
2395 11:32:24.431160 [0] AVG Duty = 5062%(X100)
2396 11:32:24.434528
2397 11:32:24.434602 ==DQS 1 ==
2398 11:32:24.438083 Final DQS duty delay cell = -4
2399 11:32:24.440947 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2400 11:32:24.444514 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2401 11:32:24.448090 [-4] AVG Duty = 5062%(X100)
2402 11:32:24.448163
2403 11:32:24.451722 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2404 11:32:24.451795
2405 11:32:24.454672 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2406 11:32:24.458327 [DutyScan_Calibration_Flow] ====Done====
2407 11:32:24.458400
2408 11:32:24.461372 [DutyScan_Calibration_Flow] k_type=3
2409 11:32:24.477859
2410 11:32:24.477935 ==DQM 0 ==
2411 11:32:24.481244 Final DQM duty delay cell = 0
2412 11:32:24.484716 [0] MAX Duty = 5000%(X100), DQS PI = 54
2413 11:32:24.487784 [0] MIN Duty = 4907%(X100), DQS PI = 0
2414 11:32:24.487882 [0] AVG Duty = 4953%(X100)
2415 11:32:24.491335
2416 11:32:24.491450 ==DQM 1 ==
2417 11:32:24.494753 Final DQM duty delay cell = 0
2418 11:32:24.498021 [0] MAX Duty = 5124%(X100), DQS PI = 62
2419 11:32:24.501819 [0] MIN Duty = 4969%(X100), DQS PI = 10
2420 11:32:24.501896 [0] AVG Duty = 5046%(X100)
2421 11:32:24.501953
2422 11:32:24.504431 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2423 11:32:24.508085
2424 11:32:24.511646 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2425 11:32:24.515105 [DutyScan_Calibration_Flow] ====Done====
2426 11:32:24.515193
2427 11:32:24.517969 [DutyScan_Calibration_Flow] k_type=2
2428 11:32:24.533792
2429 11:32:24.533865 ==DQ 0 ==
2430 11:32:24.537089 Final DQ duty delay cell = -4
2431 11:32:24.540472 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2432 11:32:24.543793 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2433 11:32:24.546826 [-4] AVG Duty = 4937%(X100)
2434 11:32:24.546900
2435 11:32:24.546957 ==DQ 1 ==
2436 11:32:24.550268 Final DQ duty delay cell = 0
2437 11:32:24.553336 [0] MAX Duty = 5000%(X100), DQS PI = 18
2438 11:32:24.557087 [0] MIN Duty = 4907%(X100), DQS PI = 46
2439 11:32:24.557189 [0] AVG Duty = 4953%(X100)
2440 11:32:24.560297
2441 11:32:24.563586 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2442 11:32:24.563661
2443 11:32:24.566878 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2444 11:32:24.569974 [DutyScan_Calibration_Flow] ====Done====
2445 11:32:24.570049 ==
2446 11:32:24.573809 Dram Type= 6, Freq= 0, CH_1, rank 0
2447 11:32:24.576976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 11:32:24.577074 ==
2449 11:32:24.580041 [Duty_Offset_Calibration]
2450 11:32:24.580139 B0:1 B1:1 CA:2
2451 11:32:24.580222
2452 11:32:24.584037 [DutyScan_Calibration_Flow] k_type=0
2453 11:32:24.593549
2454 11:32:24.593647 ==CLK 0==
2455 11:32:24.597278 Final CLK duty delay cell = 0
2456 11:32:24.600451 [0] MAX Duty = 5156%(X100), DQS PI = 24
2457 11:32:24.603734 [0] MIN Duty = 4938%(X100), DQS PI = 42
2458 11:32:24.603825 [0] AVG Duty = 5047%(X100)
2459 11:32:24.603897
2460 11:32:24.607102 CH1 CLK Duty spec in!! Max-Min= 218%
2461 11:32:24.613712 [DutyScan_Calibration_Flow] ====Done====
2462 11:32:24.613796
2463 11:32:24.616988 [DutyScan_Calibration_Flow] k_type=1
2464 11:32:24.633046
2465 11:32:24.633174 ==DQS 0 ==
2466 11:32:24.636488 Final DQS duty delay cell = 0
2467 11:32:24.639483 [0] MAX Duty = 5031%(X100), DQS PI = 18
2468 11:32:24.643007 [0] MIN Duty = 4813%(X100), DQS PI = 50
2469 11:32:24.643106 [0] AVG Duty = 4922%(X100)
2470 11:32:24.646958
2471 11:32:24.647056 ==DQS 1 ==
2472 11:32:24.649904 Final DQS duty delay cell = 0
2473 11:32:24.652760 [0] MAX Duty = 5062%(X100), DQS PI = 36
2474 11:32:24.656580 [0] MIN Duty = 4907%(X100), DQS PI = 0
2475 11:32:24.656653 [0] AVG Duty = 4984%(X100)
2476 11:32:24.659651
2477 11:32:24.662948 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2478 11:32:24.663020
2479 11:32:24.666411 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2480 11:32:24.669498 [DutyScan_Calibration_Flow] ====Done====
2481 11:32:24.669575
2482 11:32:24.673249 [DutyScan_Calibration_Flow] k_type=3
2483 11:32:24.689712
2484 11:32:24.689815 ==DQM 0 ==
2485 11:32:24.692698 Final DQM duty delay cell = 0
2486 11:32:24.696232 [0] MAX Duty = 5093%(X100), DQS PI = 18
2487 11:32:24.699513 [0] MIN Duty = 4875%(X100), DQS PI = 50
2488 11:32:24.699622 [0] AVG Duty = 4984%(X100)
2489 11:32:24.702919
2490 11:32:24.702997 ==DQM 1 ==
2491 11:32:24.706201 Final DQM duty delay cell = 0
2492 11:32:24.709353 [0] MAX Duty = 5125%(X100), DQS PI = 0
2493 11:32:24.713044 [0] MIN Duty = 4938%(X100), DQS PI = 24
2494 11:32:24.713178 [0] AVG Duty = 5031%(X100)
2495 11:32:24.713239
2496 11:32:24.719604 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2497 11:32:24.719678
2498 11:32:24.723168 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2499 11:32:24.726232 [DutyScan_Calibration_Flow] ====Done====
2500 11:32:24.726305
2501 11:32:24.729335 [DutyScan_Calibration_Flow] k_type=2
2502 11:32:24.746266
2503 11:32:24.746339 ==DQ 0 ==
2504 11:32:24.749446 Final DQ duty delay cell = 0
2505 11:32:24.752847 [0] MAX Duty = 5156%(X100), DQS PI = 18
2506 11:32:24.756171 [0] MIN Duty = 4938%(X100), DQS PI = 50
2507 11:32:24.756246 [0] AVG Duty = 5047%(X100)
2508 11:32:24.756304
2509 11:32:24.759544 ==DQ 1 ==
2510 11:32:24.762703 Final DQ duty delay cell = 0
2511 11:32:24.766015 [0] MAX Duty = 5093%(X100), DQS PI = 40
2512 11:32:24.769774 [0] MIN Duty = 5000%(X100), DQS PI = 2
2513 11:32:24.769848 [0] AVG Duty = 5046%(X100)
2514 11:32:24.769906
2515 11:32:24.772623 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2516 11:32:24.772698
2517 11:32:24.776408 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2518 11:32:24.779344 [DutyScan_Calibration_Flow] ====Done====
2519 11:32:24.784741 nWR fixed to 30
2520 11:32:24.788430 [ModeRegInit_LP4] CH0 RK0
2521 11:32:24.788504 [ModeRegInit_LP4] CH0 RK1
2522 11:32:24.791392 [ModeRegInit_LP4] CH1 RK0
2523 11:32:24.794936 [ModeRegInit_LP4] CH1 RK1
2524 11:32:24.795010 match AC timing 7
2525 11:32:24.801547 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2526 11:32:24.804854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2527 11:32:24.808127 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2528 11:32:24.815365 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2529 11:32:24.818625 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2530 11:32:24.818700 ==
2531 11:32:24.821839 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 11:32:24.825088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 11:32:24.825191 ==
2534 11:32:24.831520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 11:32:24.838129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2536 11:32:24.846023 [CA 0] Center 40 (10~71) winsize 62
2537 11:32:24.849565 [CA 1] Center 39 (9~70) winsize 62
2538 11:32:24.852745 [CA 2] Center 36 (6~67) winsize 62
2539 11:32:24.855656 [CA 3] Center 36 (6~66) winsize 61
2540 11:32:24.859043 [CA 4] Center 34 (4~65) winsize 62
2541 11:32:24.862508 [CA 5] Center 34 (4~64) winsize 61
2542 11:32:24.862577
2543 11:32:24.866148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 11:32:24.866218
2545 11:32:24.869473 [CATrainingPosCal] consider 1 rank data
2546 11:32:24.872586 u2DelayCellTimex100 = 270/100 ps
2547 11:32:24.876081 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2548 11:32:24.879560 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2549 11:32:24.885713 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2550 11:32:24.889312 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2551 11:32:24.892788 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2552 11:32:24.895718 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2553 11:32:24.895809
2554 11:32:24.899320 CA PerBit enable=1, Macro0, CA PI delay=34
2555 11:32:24.899398
2556 11:32:24.902824 [CBTSetCACLKResult] CA Dly = 34
2557 11:32:24.902904 CS Dly: 7 (0~38)
2558 11:32:24.902977 ==
2559 11:32:24.906144 Dram Type= 6, Freq= 0, CH_0, rank 1
2560 11:32:24.912476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 11:32:24.912551 ==
2562 11:32:24.916058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2563 11:32:24.923038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2564 11:32:24.932039 [CA 0] Center 39 (9~70) winsize 62
2565 11:32:24.935080 [CA 1] Center 39 (9~70) winsize 62
2566 11:32:24.938200 [CA 2] Center 36 (6~67) winsize 62
2567 11:32:24.941726 [CA 3] Center 36 (5~67) winsize 63
2568 11:32:24.945024 [CA 4] Center 34 (4~65) winsize 62
2569 11:32:24.948417 [CA 5] Center 34 (4~64) winsize 61
2570 11:32:24.948492
2571 11:32:24.951618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2572 11:32:24.951688
2573 11:32:24.955394 [CATrainingPosCal] consider 2 rank data
2574 11:32:24.958496 u2DelayCellTimex100 = 270/100 ps
2575 11:32:24.962088 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2576 11:32:24.965215 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2577 11:32:24.971861 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2578 11:32:24.975271 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2579 11:32:24.978767 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2580 11:32:24.982306 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2581 11:32:24.982381
2582 11:32:24.985442 CA PerBit enable=1, Macro0, CA PI delay=34
2583 11:32:24.985516
2584 11:32:24.988371 [CBTSetCACLKResult] CA Dly = 34
2585 11:32:24.988444 CS Dly: 8 (0~41)
2586 11:32:24.988525
2587 11:32:24.991996 ----->DramcWriteLeveling(PI) begin...
2588 11:32:24.992065 ==
2589 11:32:24.995594 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 11:32:25.002472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 11:32:25.002547 ==
2592 11:32:25.005554 Write leveling (Byte 0): 30 => 30
2593 11:32:25.009241 Write leveling (Byte 1): 29 => 29
2594 11:32:25.009339 DramcWriteLeveling(PI) end<-----
2595 11:32:25.009422
2596 11:32:25.012328 ==
2597 11:32:25.015429 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 11:32:25.018897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 11:32:25.018972 ==
2600 11:32:25.022384 [Gating] SW mode calibration
2601 11:32:25.028950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2602 11:32:25.032409 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2603 11:32:25.039382 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:32:25.042654 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2605 11:32:25.045873 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2606 11:32:25.052521 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:32:25.055897 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:32:25.059437 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:32:25.062608 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:32:25.069270 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 11:32:25.072769 1 0 0 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2612 11:32:25.075877 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2613 11:32:25.082554 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:32:25.085978 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:32:25.089466 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:32:25.095802 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:32:25.099261 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:32:25.102752 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 11:32:25.109266 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2620 11:32:25.113095 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2621 11:32:25.116431 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:32:25.119932 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:32:25.126394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:32:25.129524 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:32:25.132918 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:32:25.139807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:32:25.143102 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2628 11:32:25.146020 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2629 11:32:25.152845 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:32:25.156437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:32:25.159815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:32:25.166410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:32:25.169567 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:32:25.173046 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:32:25.180127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:32:25.182800 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:32:25.186096 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:32:25.193164 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:32:25.196507 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:32:25.199844 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:32:25.203275 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:32:25.209657 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 11:32:25.213072 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2644 11:32:25.216647 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2645 11:32:25.219788 Total UI for P1: 0, mck2ui 16
2646 11:32:25.223067 best dqsien dly found for B1: ( 1, 4, 2)
2647 11:32:25.229672 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2648 11:32:25.229747 Total UI for P1: 0, mck2ui 16
2649 11:32:25.236706 best dqsien dly found for B0: ( 1, 4, 0)
2650 11:32:25.239941 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2651 11:32:25.243245 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2652 11:32:25.243320
2653 11:32:25.246568 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2654 11:32:25.250146 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2655 11:32:25.254013 [Gating] SW calibration Done
2656 11:32:25.254091 ==
2657 11:32:25.257210 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:32:25.260080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:32:25.260151 ==
2660 11:32:25.260224 RX Vref Scan: 0
2661 11:32:25.260294
2662 11:32:25.263581 RX Vref 0 -> 0, step: 1
2663 11:32:25.263646
2664 11:32:25.267052 RX Delay -40 -> 252, step: 8
2665 11:32:25.270374 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2666 11:32:25.273564 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2667 11:32:25.280620 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2668 11:32:25.283733 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2669 11:32:25.287104 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2670 11:32:25.290349 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2671 11:32:25.293678 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2672 11:32:25.297776 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2673 11:32:25.304136 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2674 11:32:25.307327 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2675 11:32:25.310399 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2676 11:32:25.313822 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2677 11:32:25.317231 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2678 11:32:25.323807 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2679 11:32:25.327534 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2680 11:32:25.331253 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2681 11:32:25.331327 ==
2682 11:32:25.334588 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:32:25.337716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:32:25.337797 ==
2685 11:32:25.340826 DQS Delay:
2686 11:32:25.340895 DQS0 = 0, DQS1 = 0
2687 11:32:25.340986 DQM Delay:
2688 11:32:25.344206 DQM0 = 115, DQM1 = 105
2689 11:32:25.344275 DQ Delay:
2690 11:32:25.347611 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2691 11:32:25.351003 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2692 11:32:25.354173 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =95
2693 11:32:25.361272 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2694 11:32:25.361348
2695 11:32:25.361404
2696 11:32:25.361471 ==
2697 11:32:25.364282 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:32:25.367559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:32:25.367628 ==
2700 11:32:25.367690
2701 11:32:25.367742
2702 11:32:25.371281 TX Vref Scan disable
2703 11:32:25.371352 == TX Byte 0 ==
2704 11:32:25.377854 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2705 11:32:25.381208 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2706 11:32:25.381278 == TX Byte 1 ==
2707 11:32:25.387995 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 11:32:25.390938 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 11:32:25.391006 ==
2710 11:32:25.394780 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:32:25.397833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:32:25.397909 ==
2713 11:32:25.410064 TX Vref=22, minBit 1, minWin=25, winSum=421
2714 11:32:25.413396 TX Vref=24, minBit 1, minWin=25, winSum=424
2715 11:32:25.417273 TX Vref=26, minBit 0, minWin=26, winSum=428
2716 11:32:25.420608 TX Vref=28, minBit 1, minWin=26, winSum=435
2717 11:32:25.423524 TX Vref=30, minBit 1, minWin=26, winSum=434
2718 11:32:25.426965 TX Vref=32, minBit 4, minWin=26, winSum=434
2719 11:32:25.433769 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
2720 11:32:25.433863
2721 11:32:25.437203 Final TX Range 1 Vref 28
2722 11:32:25.437293
2723 11:32:25.437379 ==
2724 11:32:25.440442 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:32:25.443747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:32:25.443820 ==
2727 11:32:25.443875
2728 11:32:25.443927
2729 11:32:25.447120 TX Vref Scan disable
2730 11:32:25.450547 == TX Byte 0 ==
2731 11:32:25.453822 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2732 11:32:25.457439 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2733 11:32:25.460911 == TX Byte 1 ==
2734 11:32:25.463974 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2735 11:32:25.467360 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2736 11:32:25.467434
2737 11:32:25.471054 [DATLAT]
2738 11:32:25.471122 Freq=1200, CH0 RK0
2739 11:32:25.471178
2740 11:32:25.473909 DATLAT Default: 0xd
2741 11:32:25.473972 0, 0xFFFF, sum = 0
2742 11:32:25.477757 1, 0xFFFF, sum = 0
2743 11:32:25.477826 2, 0xFFFF, sum = 0
2744 11:32:25.480992 3, 0xFFFF, sum = 0
2745 11:32:25.481082 4, 0xFFFF, sum = 0
2746 11:32:25.484287 5, 0xFFFF, sum = 0
2747 11:32:25.484357 6, 0xFFFF, sum = 0
2748 11:32:25.487583 7, 0xFFFF, sum = 0
2749 11:32:25.487658 8, 0xFFFF, sum = 0
2750 11:32:25.490781 9, 0xFFFF, sum = 0
2751 11:32:25.490847 10, 0xFFFF, sum = 0
2752 11:32:25.494471 11, 0xFFFF, sum = 0
2753 11:32:25.494542 12, 0x0, sum = 1
2754 11:32:25.497542 13, 0x0, sum = 2
2755 11:32:25.497611 14, 0x0, sum = 3
2756 11:32:25.501208 15, 0x0, sum = 4
2757 11:32:25.501275 best_step = 13
2758 11:32:25.501330
2759 11:32:25.501388 ==
2760 11:32:25.504025 Dram Type= 6, Freq= 0, CH_0, rank 0
2761 11:32:25.507635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2762 11:32:25.511202 ==
2763 11:32:25.511272 RX Vref Scan: 1
2764 11:32:25.511327
2765 11:32:25.514338 Set Vref Range= 32 -> 127
2766 11:32:25.514404
2767 11:32:25.517537 RX Vref 32 -> 127, step: 1
2768 11:32:25.517608
2769 11:32:25.517666 RX Delay -21 -> 252, step: 4
2770 11:32:25.517718
2771 11:32:25.521356 Set Vref, RX VrefLevel [Byte0]: 32
2772 11:32:25.524581 [Byte1]: 32
2773 11:32:25.528402
2774 11:32:25.528476 Set Vref, RX VrefLevel [Byte0]: 33
2775 11:32:25.531894 [Byte1]: 33
2776 11:32:25.536488
2777 11:32:25.536578 Set Vref, RX VrefLevel [Byte0]: 34
2778 11:32:25.539818 [Byte1]: 34
2779 11:32:25.544139
2780 11:32:25.544209 Set Vref, RX VrefLevel [Byte0]: 35
2781 11:32:25.547410 [Byte1]: 35
2782 11:32:25.552463
2783 11:32:25.552536 Set Vref, RX VrefLevel [Byte0]: 36
2784 11:32:25.555629 [Byte1]: 36
2785 11:32:25.560249
2786 11:32:25.560315 Set Vref, RX VrefLevel [Byte0]: 37
2787 11:32:25.563498 [Byte1]: 37
2788 11:32:25.567929
2789 11:32:25.568005 Set Vref, RX VrefLevel [Byte0]: 38
2790 11:32:25.571701 [Byte1]: 38
2791 11:32:25.576202
2792 11:32:25.576276 Set Vref, RX VrefLevel [Byte0]: 39
2793 11:32:25.579648 [Byte1]: 39
2794 11:32:25.584112
2795 11:32:25.584187 Set Vref, RX VrefLevel [Byte0]: 40
2796 11:32:25.587419 [Byte1]: 40
2797 11:32:25.591640
2798 11:32:25.591715 Set Vref, RX VrefLevel [Byte0]: 41
2799 11:32:25.595172 [Byte1]: 41
2800 11:32:25.600212
2801 11:32:25.600288 Set Vref, RX VrefLevel [Byte0]: 42
2802 11:32:25.602880 [Byte1]: 42
2803 11:32:25.607896
2804 11:32:25.607971 Set Vref, RX VrefLevel [Byte0]: 43
2805 11:32:25.610838 [Byte1]: 43
2806 11:32:25.615482
2807 11:32:25.615557 Set Vref, RX VrefLevel [Byte0]: 44
2808 11:32:25.619245 [Byte1]: 44
2809 11:32:25.623699
2810 11:32:25.623780 Set Vref, RX VrefLevel [Byte0]: 45
2811 11:32:25.626658 [Byte1]: 45
2812 11:32:25.631624
2813 11:32:25.631696 Set Vref, RX VrefLevel [Byte0]: 46
2814 11:32:25.634726 [Byte1]: 46
2815 11:32:25.639093
2816 11:32:25.639166 Set Vref, RX VrefLevel [Byte0]: 47
2817 11:32:25.642523 [Byte1]: 47
2818 11:32:25.647734
2819 11:32:25.647802 Set Vref, RX VrefLevel [Byte0]: 48
2820 11:32:25.650587 [Byte1]: 48
2821 11:32:25.655218
2822 11:32:25.655296 Set Vref, RX VrefLevel [Byte0]: 49
2823 11:32:25.658602 [Byte1]: 49
2824 11:32:25.662866
2825 11:32:25.662932 Set Vref, RX VrefLevel [Byte0]: 50
2826 11:32:25.666216 [Byte1]: 50
2827 11:32:25.671344
2828 11:32:25.671420 Set Vref, RX VrefLevel [Byte0]: 51
2829 11:32:25.674578 [Byte1]: 51
2830 11:32:25.679465
2831 11:32:25.679534 Set Vref, RX VrefLevel [Byte0]: 52
2832 11:32:25.682393 [Byte1]: 52
2833 11:32:25.686817
2834 11:32:25.686884 Set Vref, RX VrefLevel [Byte0]: 53
2835 11:32:25.690370 [Byte1]: 53
2836 11:32:25.694778
2837 11:32:25.694854 Set Vref, RX VrefLevel [Byte0]: 54
2838 11:32:25.698088 [Byte1]: 54
2839 11:32:25.702561
2840 11:32:25.702635 Set Vref, RX VrefLevel [Byte0]: 55
2841 11:32:25.705962 [Byte1]: 55
2842 11:32:25.710636
2843 11:32:25.710712 Set Vref, RX VrefLevel [Byte0]: 56
2844 11:32:25.713899 [Byte1]: 56
2845 11:32:25.718734
2846 11:32:25.718822 Set Vref, RX VrefLevel [Byte0]: 57
2847 11:32:25.721692 [Byte1]: 57
2848 11:32:25.726458
2849 11:32:25.726528 Set Vref, RX VrefLevel [Byte0]: 58
2850 11:32:25.729872 [Byte1]: 58
2851 11:32:25.734314
2852 11:32:25.734394 Set Vref, RX VrefLevel [Byte0]: 59
2853 11:32:25.737818 [Byte1]: 59
2854 11:32:25.742593
2855 11:32:25.742667 Set Vref, RX VrefLevel [Byte0]: 60
2856 11:32:25.745865 [Byte1]: 60
2857 11:32:25.750366
2858 11:32:25.750440 Set Vref, RX VrefLevel [Byte0]: 61
2859 11:32:25.753630 [Byte1]: 61
2860 11:32:25.758478
2861 11:32:25.758567 Set Vref, RX VrefLevel [Byte0]: 62
2862 11:32:25.761528 [Byte1]: 62
2863 11:32:25.766013
2864 11:32:25.766092 Set Vref, RX VrefLevel [Byte0]: 63
2865 11:32:25.769383 [Byte1]: 63
2866 11:32:25.774202
2867 11:32:25.774276 Set Vref, RX VrefLevel [Byte0]: 64
2868 11:32:25.777722 [Byte1]: 64
2869 11:32:25.782393
2870 11:32:25.782467 Set Vref, RX VrefLevel [Byte0]: 65
2871 11:32:25.785102 [Byte1]: 65
2872 11:32:25.790177
2873 11:32:25.790251 Set Vref, RX VrefLevel [Byte0]: 66
2874 11:32:25.793612 [Byte1]: 66
2875 11:32:25.797980
2876 11:32:25.798055 Set Vref, RX VrefLevel [Byte0]: 67
2877 11:32:25.801363 [Byte1]: 67
2878 11:32:25.806019
2879 11:32:25.806089 Set Vref, RX VrefLevel [Byte0]: 68
2880 11:32:25.808925 [Byte1]: 68
2881 11:32:25.813874
2882 11:32:25.813945 Final RX Vref Byte 0 = 53 to rank0
2883 11:32:25.817025 Final RX Vref Byte 1 = 53 to rank0
2884 11:32:25.820344 Final RX Vref Byte 0 = 53 to rank1
2885 11:32:25.823531 Final RX Vref Byte 1 = 53 to rank1==
2886 11:32:25.827033 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 11:32:25.830496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 11:32:25.834063 ==
2889 11:32:25.834132 DQS Delay:
2890 11:32:25.834190 DQS0 = 0, DQS1 = 0
2891 11:32:25.837333 DQM Delay:
2892 11:32:25.837400 DQM0 = 114, DQM1 = 105
2893 11:32:25.840592 DQ Delay:
2894 11:32:25.843931 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =114
2895 11:32:25.847069 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2896 11:32:25.850412 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2897 11:32:25.853879 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2898 11:32:25.853954
2899 11:32:25.854012
2900 11:32:25.860608 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2901 11:32:25.863862 CH0 RK0: MR19=303, MR18=FFEE
2902 11:32:25.870658 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2903 11:32:25.870734
2904 11:32:25.873903 ----->DramcWriteLeveling(PI) begin...
2905 11:32:25.873972 ==
2906 11:32:25.877526 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 11:32:25.880823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 11:32:25.880891 ==
2909 11:32:25.884018 Write leveling (Byte 0): 33 => 33
2910 11:32:25.887686 Write leveling (Byte 1): 29 => 29
2911 11:32:25.890836 DramcWriteLeveling(PI) end<-----
2912 11:32:25.890903
2913 11:32:25.890958 ==
2914 11:32:25.894414 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:32:25.897516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:32:25.897588 ==
2917 11:32:25.900844 [Gating] SW mode calibration
2918 11:32:25.907728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 11:32:25.914084 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 11:32:25.917425 0 15 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2921 11:32:25.924921 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2922 11:32:25.927628 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 11:32:25.931201 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 11:32:25.934630 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 11:32:25.941238 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 11:32:25.944494 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2927 11:32:25.947768 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2928 11:32:25.954894 1 0 0 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (0 0)
2929 11:32:25.957948 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 11:32:25.961231 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 11:32:25.968090 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 11:32:25.971379 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:32:25.974829 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 11:32:25.981513 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2935 11:32:25.984862 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2936 11:32:25.988112 1 1 0 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
2937 11:32:25.991546 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:32:25.998347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 11:32:26.001607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 11:32:26.004853 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:32:26.011564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:32:26.015034 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 11:32:26.018242 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 11:32:26.025015 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2945 11:32:26.028496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:32:26.031925 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:32:26.038458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 11:32:26.041839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:32:26.045522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:32:26.051998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:32:26.055035 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:32:26.058448 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:32:26.061959 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:32:26.068450 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:32:26.072389 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:32:26.075284 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:32:26.082660 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:32:26.085742 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 11:32:26.088903 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 11:32:26.095798 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2961 11:32:26.095877 Total UI for P1: 0, mck2ui 16
2962 11:32:26.102228 best dqsien dly found for B0: ( 1, 3, 26)
2963 11:32:26.105915 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 11:32:26.109362 Total UI for P1: 0, mck2ui 16
2965 11:32:26.112167 best dqsien dly found for B1: ( 1, 4, 0)
2966 11:32:26.115506 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2967 11:32:26.118864 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2968 11:32:26.118928
2969 11:32:26.122764 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2970 11:32:26.125344 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2971 11:32:26.129458 [Gating] SW calibration Done
2972 11:32:26.129525 ==
2973 11:32:26.132070 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 11:32:26.135563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 11:32:26.135650 ==
2976 11:32:26.139015 RX Vref Scan: 0
2977 11:32:26.139076
2978 11:32:26.139129 RX Vref 0 -> 0, step: 1
2979 11:32:26.139181
2980 11:32:26.142300 RX Delay -40 -> 252, step: 8
2981 11:32:26.148945 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2982 11:32:26.152614 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2983 11:32:26.155692 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2984 11:32:26.158867 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2985 11:32:26.162143 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2986 11:32:26.166073 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2987 11:32:26.172861 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2988 11:32:26.175602 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2989 11:32:26.179032 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2990 11:32:26.182584 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2991 11:32:26.186338 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2992 11:32:26.192376 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2993 11:32:26.195882 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2994 11:32:26.199376 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2995 11:32:26.202952 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2996 11:32:26.206057 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2997 11:32:26.209356 ==
2998 11:32:26.212657 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 11:32:26.215491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 11:32:26.215567 ==
3001 11:32:26.215625 DQS Delay:
3002 11:32:26.218871 DQS0 = 0, DQS1 = 0
3003 11:32:26.218950 DQM Delay:
3004 11:32:26.222345 DQM0 = 115, DQM1 = 106
3005 11:32:26.222420 DQ Delay:
3006 11:32:26.225465 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3007 11:32:26.229083 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
3008 11:32:26.232300 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3009 11:32:26.235753 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3010 11:32:26.235826
3011 11:32:26.235919
3012 11:32:26.235973 ==
3013 11:32:26.239166 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 11:32:26.245812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 11:32:26.245906 ==
3016 11:32:26.245968
3017 11:32:26.246020
3018 11:32:26.246070 TX Vref Scan disable
3019 11:32:26.249047 == TX Byte 0 ==
3020 11:32:26.252393 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3021 11:32:26.255986 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3022 11:32:26.258971 == TX Byte 1 ==
3023 11:32:26.262204 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 11:32:26.266176 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 11:32:26.269078 ==
3026 11:32:26.272533 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 11:32:26.275972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 11:32:26.276049 ==
3029 11:32:26.287032 TX Vref=22, minBit 4, minWin=25, winSum=420
3030 11:32:26.290431 TX Vref=24, minBit 0, minWin=26, winSum=430
3031 11:32:26.294256 TX Vref=26, minBit 1, minWin=26, winSum=433
3032 11:32:26.297034 TX Vref=28, minBit 2, minWin=26, winSum=431
3033 11:32:26.300547 TX Vref=30, minBit 0, minWin=27, winSum=438
3034 11:32:26.303845 TX Vref=32, minBit 4, minWin=26, winSum=434
3035 11:32:26.310931 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
3036 11:32:26.311007
3037 11:32:26.313973 Final TX Range 1 Vref 30
3038 11:32:26.314048
3039 11:32:26.314107 ==
3040 11:32:26.317313 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 11:32:26.321463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 11:32:26.321539 ==
3043 11:32:26.321598
3044 11:32:26.321651
3045 11:32:26.323908 TX Vref Scan disable
3046 11:32:26.327153 == TX Byte 0 ==
3047 11:32:26.330734 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3048 11:32:26.333903 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3049 11:32:26.337343 == TX Byte 1 ==
3050 11:32:26.340855 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3051 11:32:26.344561 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3052 11:32:26.344636
3053 11:32:26.347895 [DATLAT]
3054 11:32:26.347970 Freq=1200, CH0 RK1
3055 11:32:26.348029
3056 11:32:26.351099 DATLAT Default: 0xd
3057 11:32:26.351173 0, 0xFFFF, sum = 0
3058 11:32:26.354093 1, 0xFFFF, sum = 0
3059 11:32:26.354169 2, 0xFFFF, sum = 0
3060 11:32:26.357558 3, 0xFFFF, sum = 0
3061 11:32:26.357634 4, 0xFFFF, sum = 0
3062 11:32:26.360774 5, 0xFFFF, sum = 0
3063 11:32:26.360850 6, 0xFFFF, sum = 0
3064 11:32:26.364028 7, 0xFFFF, sum = 0
3065 11:32:26.364104 8, 0xFFFF, sum = 0
3066 11:32:26.367411 9, 0xFFFF, sum = 0
3067 11:32:26.370502 10, 0xFFFF, sum = 0
3068 11:32:26.370578 11, 0xFFFF, sum = 0
3069 11:32:26.374215 12, 0x0, sum = 1
3070 11:32:26.374291 13, 0x0, sum = 2
3071 11:32:26.374350 14, 0x0, sum = 3
3072 11:32:26.377430 15, 0x0, sum = 4
3073 11:32:26.377506 best_step = 13
3074 11:32:26.377564
3075 11:32:26.377616 ==
3076 11:32:26.380887 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 11:32:26.387035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 11:32:26.387107 ==
3079 11:32:26.387165 RX Vref Scan: 0
3080 11:32:26.387219
3081 11:32:26.391036 RX Vref 0 -> 0, step: 1
3082 11:32:26.391101
3083 11:32:26.393839 RX Delay -21 -> 252, step: 4
3084 11:32:26.397208 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3085 11:32:26.400533 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3086 11:32:26.407277 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3087 11:32:26.410493 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3088 11:32:26.413788 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3089 11:32:26.417283 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3090 11:32:26.420797 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3091 11:32:26.427514 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3092 11:32:26.430728 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3093 11:32:26.433754 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3094 11:32:26.437186 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3095 11:32:26.440462 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3096 11:32:26.447170 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3097 11:32:26.450543 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3098 11:32:26.453933 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3099 11:32:26.457607 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3100 11:32:26.457686 ==
3101 11:32:26.460795 Dram Type= 6, Freq= 0, CH_0, rank 1
3102 11:32:26.464377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 11:32:26.467382 ==
3104 11:32:26.467451 DQS Delay:
3105 11:32:26.467511 DQS0 = 0, DQS1 = 0
3106 11:32:26.470918 DQM Delay:
3107 11:32:26.470985 DQM0 = 113, DQM1 = 104
3108 11:32:26.474188 DQ Delay:
3109 11:32:26.477596 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3110 11:32:26.480911 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3111 11:32:26.484345 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3112 11:32:26.487367 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3113 11:32:26.487446
3114 11:32:26.487512
3115 11:32:26.494024 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3116 11:32:26.497416 CH0 RK1: MR19=403, MR18=7F9
3117 11:32:26.504441 CH0_RK1: MR19=0x403, MR18=0x7F9, DQSOSC=407, MR23=63, INC=39, DEC=26
3118 11:32:26.507741 [RxdqsGatingPostProcess] freq 1200
3119 11:32:26.511013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3120 11:32:26.514486 best DQS0 dly(2T, 0.5T) = (0, 12)
3121 11:32:26.517429 best DQS1 dly(2T, 0.5T) = (0, 12)
3122 11:32:26.520817 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3123 11:32:26.524339 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3124 11:32:26.527664 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 11:32:26.531026 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 11:32:26.534513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 11:32:26.538055 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 11:32:26.541017 Pre-setting of DQS Precalculation
3129 11:32:26.544592 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3130 11:32:26.544667 ==
3131 11:32:26.547916 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 11:32:26.554448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 11:32:26.554524 ==
3134 11:32:26.557897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 11:32:26.564292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3136 11:32:26.572935 [CA 0] Center 38 (8~68) winsize 61
3137 11:32:26.576290 [CA 1] Center 38 (9~68) winsize 60
3138 11:32:26.579293 [CA 2] Center 35 (5~65) winsize 61
3139 11:32:26.582747 [CA 3] Center 34 (3~65) winsize 63
3140 11:32:26.586092 [CA 4] Center 34 (4~65) winsize 62
3141 11:32:26.589403 [CA 5] Center 34 (4~64) winsize 61
3142 11:32:26.589493
3143 11:32:26.592749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 11:32:26.592847
3145 11:32:26.596163 [CATrainingPosCal] consider 1 rank data
3146 11:32:26.599877 u2DelayCellTimex100 = 270/100 ps
3147 11:32:26.602801 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3148 11:32:26.605863 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3149 11:32:26.612662 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3150 11:32:26.616488 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3151 11:32:26.619822 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3152 11:32:26.623144 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3153 11:32:26.623218
3154 11:32:26.626175 CA PerBit enable=1, Macro0, CA PI delay=34
3155 11:32:26.626250
3156 11:32:26.629758 [CBTSetCACLKResult] CA Dly = 34
3157 11:32:26.629847 CS Dly: 6 (0~37)
3158 11:32:26.629920 ==
3159 11:32:26.633071 Dram Type= 6, Freq= 0, CH_1, rank 1
3160 11:32:26.639983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 11:32:26.640060 ==
3162 11:32:26.643111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 11:32:26.650040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3164 11:32:26.658323 [CA 0] Center 38 (8~68) winsize 61
3165 11:32:26.661830 [CA 1] Center 38 (8~68) winsize 61
3166 11:32:26.665004 [CA 2] Center 34 (4~65) winsize 62
3167 11:32:26.668163 [CA 3] Center 34 (4~65) winsize 62
3168 11:32:26.671659 [CA 4] Center 34 (4~65) winsize 62
3169 11:32:26.674926 [CA 5] Center 33 (3~63) winsize 61
3170 11:32:26.674991
3171 11:32:26.677997 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3172 11:32:26.678066
3173 11:32:26.681590 [CATrainingPosCal] consider 2 rank data
3174 11:32:26.684944 u2DelayCellTimex100 = 270/100 ps
3175 11:32:26.688304 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 11:32:26.691872 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3177 11:32:26.698245 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3178 11:32:26.701850 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3179 11:32:26.705208 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3180 11:32:26.709055 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3181 11:32:26.709131
3182 11:32:26.712276 CA PerBit enable=1, Macro0, CA PI delay=33
3183 11:32:26.712367
3184 11:32:26.715167 [CBTSetCACLKResult] CA Dly = 33
3185 11:32:26.715233 CS Dly: 7 (0~40)
3186 11:32:26.715285
3187 11:32:26.718556 ----->DramcWriteLeveling(PI) begin...
3188 11:32:26.718632 ==
3189 11:32:26.721626 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 11:32:26.728519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 11:32:26.728588 ==
3192 11:32:26.731990 Write leveling (Byte 0): 26 => 26
3193 11:32:26.735070 Write leveling (Byte 1): 31 => 31
3194 11:32:26.735137 DramcWriteLeveling(PI) end<-----
3195 11:32:26.738348
3196 11:32:26.738414 ==
3197 11:32:26.742173 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 11:32:26.744988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 11:32:26.745049 ==
3200 11:32:26.748384 [Gating] SW mode calibration
3201 11:32:26.755055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3202 11:32:26.758925 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3203 11:32:26.765032 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
3204 11:32:26.768642 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 11:32:26.771704 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 11:32:26.778488 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 11:32:26.781838 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3208 11:32:26.785107 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 11:32:26.791994 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:32:26.795299 0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3211 11:32:26.798433 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3212 11:32:26.804979 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 11:32:26.808528 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 11:32:26.812110 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 11:32:26.818473 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3216 11:32:26.821873 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:32:26.824837 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:32:26.831563 1 0 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
3219 11:32:26.835102 1 1 0 | B1->B0 | 4444 3b3b | 0 0 | (0 0) (0 0)
3220 11:32:26.838301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:32:26.841753 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:32:26.848327 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:32:26.851938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:32:26.854713 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:32:26.861850 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:32:26.865187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3227 11:32:26.868209 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3228 11:32:26.875400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:32:26.878439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 11:32:26.881999 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:32:26.888511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:32:26.891800 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:32:26.895273 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:32:26.901353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:32:26.904820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:32:26.908125 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:32:26.915254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:32:26.918242 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:32:26.921627 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:32:26.928276 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:32:26.931884 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:32:26.935276 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3243 11:32:26.938552 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3244 11:32:26.942006 Total UI for P1: 0, mck2ui 16
3245 11:32:26.945231 best dqsien dly found for B1: ( 1, 3, 28)
3246 11:32:26.951669 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 11:32:26.955098 Total UI for P1: 0, mck2ui 16
3248 11:32:26.958347 best dqsien dly found for B0: ( 1, 3, 30)
3249 11:32:26.961713 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3250 11:32:26.965004 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3251 11:32:26.965104
3252 11:32:26.968225 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3253 11:32:26.971556 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3254 11:32:26.975063 [Gating] SW calibration Done
3255 11:32:26.975139 ==
3256 11:32:26.978693 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 11:32:26.981422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 11:32:26.981497 ==
3259 11:32:26.985195 RX Vref Scan: 0
3260 11:32:26.985270
3261 11:32:26.985329 RX Vref 0 -> 0, step: 1
3262 11:32:26.985384
3263 11:32:26.988237 RX Delay -40 -> 252, step: 8
3264 11:32:26.991807 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3265 11:32:26.998573 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3266 11:32:27.001906 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3267 11:32:27.005393 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3268 11:32:27.008793 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3269 11:32:27.011851 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3270 11:32:27.018879 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3271 11:32:27.021983 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3272 11:32:27.025189 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3273 11:32:27.028750 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3274 11:32:27.032188 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3275 11:32:27.038511 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3276 11:32:27.042102 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3277 11:32:27.045236 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3278 11:32:27.048651 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3279 11:32:27.051935 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3280 11:32:27.052026 ==
3281 11:32:27.055032 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 11:32:27.062149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 11:32:27.062233 ==
3284 11:32:27.062302 DQS Delay:
3285 11:32:27.065436 DQS0 = 0, DQS1 = 0
3286 11:32:27.065501 DQM Delay:
3287 11:32:27.068868 DQM0 = 115, DQM1 = 107
3288 11:32:27.068955 DQ Delay:
3289 11:32:27.072132 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3290 11:32:27.075300 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3291 11:32:27.078834 DQ8 =99, DQ9 =95, DQ10 =103, DQ11 =107
3292 11:32:27.081874 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3293 11:32:27.081967
3294 11:32:27.082048
3295 11:32:27.082130 ==
3296 11:32:27.085360 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 11:32:27.088812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 11:32:27.092135 ==
3299 11:32:27.092218
3300 11:32:27.092296
3301 11:32:27.092350 TX Vref Scan disable
3302 11:32:27.095383 == TX Byte 0 ==
3303 11:32:27.098612 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3304 11:32:27.102196 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3305 11:32:27.105586 == TX Byte 1 ==
3306 11:32:27.109026 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3307 11:32:27.112320 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3308 11:32:27.112394 ==
3309 11:32:27.115744 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 11:32:27.122275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 11:32:27.122368 ==
3312 11:32:27.133099 TX Vref=22, minBit 15, minWin=24, winSum=406
3313 11:32:27.136421 TX Vref=24, minBit 15, minWin=24, winSum=410
3314 11:32:27.140081 TX Vref=26, minBit 3, minWin=25, winSum=420
3315 11:32:27.143116 TX Vref=28, minBit 1, minWin=26, winSum=425
3316 11:32:27.146284 TX Vref=30, minBit 13, minWin=25, winSum=424
3317 11:32:27.152916 TX Vref=32, minBit 11, minWin=25, winSum=420
3318 11:32:27.156597 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 28
3319 11:32:27.156696
3320 11:32:27.159596 Final TX Range 1 Vref 28
3321 11:32:27.159693
3322 11:32:27.159786 ==
3323 11:32:27.163297 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 11:32:27.166312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 11:32:27.169616 ==
3326 11:32:27.169714
3327 11:32:27.169797
3328 11:32:27.169877 TX Vref Scan disable
3329 11:32:27.173224 == TX Byte 0 ==
3330 11:32:27.176369 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3331 11:32:27.179934 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3332 11:32:27.183448 == TX Byte 1 ==
3333 11:32:27.186639 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3334 11:32:27.189661 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3335 11:32:27.193238
3336 11:32:27.193340 [DATLAT]
3337 11:32:27.193429 Freq=1200, CH1 RK0
3338 11:32:27.193488
3339 11:32:27.196358 DATLAT Default: 0xd
3340 11:32:27.196432 0, 0xFFFF, sum = 0
3341 11:32:27.199991 1, 0xFFFF, sum = 0
3342 11:32:27.200066 2, 0xFFFF, sum = 0
3343 11:32:27.203286 3, 0xFFFF, sum = 0
3344 11:32:27.203363 4, 0xFFFF, sum = 0
3345 11:32:27.206266 5, 0xFFFF, sum = 0
3346 11:32:27.209655 6, 0xFFFF, sum = 0
3347 11:32:27.209731 7, 0xFFFF, sum = 0
3348 11:32:27.212967 8, 0xFFFF, sum = 0
3349 11:32:27.213066 9, 0xFFFF, sum = 0
3350 11:32:27.216616 10, 0xFFFF, sum = 0
3351 11:32:27.216716 11, 0xFFFF, sum = 0
3352 11:32:27.219790 12, 0x0, sum = 1
3353 11:32:27.219865 13, 0x0, sum = 2
3354 11:32:27.223301 14, 0x0, sum = 3
3355 11:32:27.223377 15, 0x0, sum = 4
3356 11:32:27.223436 best_step = 13
3357 11:32:27.227176
3358 11:32:27.227250 ==
3359 11:32:27.230252 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 11:32:27.233114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 11:32:27.233209 ==
3362 11:32:27.233267 RX Vref Scan: 1
3363 11:32:27.233320
3364 11:32:27.236668 Set Vref Range= 32 -> 127
3365 11:32:27.236742
3366 11:32:27.239915 RX Vref 32 -> 127, step: 1
3367 11:32:27.239988
3368 11:32:27.243223 RX Delay -21 -> 252, step: 4
3369 11:32:27.243297
3370 11:32:27.246675 Set Vref, RX VrefLevel [Byte0]: 32
3371 11:32:27.249490 [Byte1]: 32
3372 11:32:27.249564
3373 11:32:27.253496 Set Vref, RX VrefLevel [Byte0]: 33
3374 11:32:27.256802 [Byte1]: 33
3375 11:32:27.259536
3376 11:32:27.259609 Set Vref, RX VrefLevel [Byte0]: 34
3377 11:32:27.262926 [Byte1]: 34
3378 11:32:27.267500
3379 11:32:27.267573 Set Vref, RX VrefLevel [Byte0]: 35
3380 11:32:27.270659 [Byte1]: 35
3381 11:32:27.275494
3382 11:32:27.275567 Set Vref, RX VrefLevel [Byte0]: 36
3383 11:32:27.278743 [Byte1]: 36
3384 11:32:27.283146
3385 11:32:27.283219 Set Vref, RX VrefLevel [Byte0]: 37
3386 11:32:27.286826 [Byte1]: 37
3387 11:32:27.291112
3388 11:32:27.291192 Set Vref, RX VrefLevel [Byte0]: 38
3389 11:32:27.295001 [Byte1]: 38
3390 11:32:27.298901
3391 11:32:27.299002 Set Vref, RX VrefLevel [Byte0]: 39
3392 11:32:27.302239 [Byte1]: 39
3393 11:32:27.307062
3394 11:32:27.307139 Set Vref, RX VrefLevel [Byte0]: 40
3395 11:32:27.310367 [Byte1]: 40
3396 11:32:27.315181
3397 11:32:27.315253 Set Vref, RX VrefLevel [Byte0]: 41
3398 11:32:27.318424 [Byte1]: 41
3399 11:32:27.322818
3400 11:32:27.322915 Set Vref, RX VrefLevel [Byte0]: 42
3401 11:32:27.326026 [Byte1]: 42
3402 11:32:27.331032
3403 11:32:27.331107 Set Vref, RX VrefLevel [Byte0]: 43
3404 11:32:27.333901 [Byte1]: 43
3405 11:32:27.338799
3406 11:32:27.338872 Set Vref, RX VrefLevel [Byte0]: 44
3407 11:32:27.342238 [Byte1]: 44
3408 11:32:27.346614
3409 11:32:27.346686 Set Vref, RX VrefLevel [Byte0]: 45
3410 11:32:27.350421 [Byte1]: 45
3411 11:32:27.355013
3412 11:32:27.355116 Set Vref, RX VrefLevel [Byte0]: 46
3413 11:32:27.358204 [Byte1]: 46
3414 11:32:27.362583
3415 11:32:27.362657 Set Vref, RX VrefLevel [Byte0]: 47
3416 11:32:27.365839 [Byte1]: 47
3417 11:32:27.370554
3418 11:32:27.370654 Set Vref, RX VrefLevel [Byte0]: 48
3419 11:32:27.373966 [Byte1]: 48
3420 11:32:27.378069
3421 11:32:27.378142 Set Vref, RX VrefLevel [Byte0]: 49
3422 11:32:27.381770 [Byte1]: 49
3423 11:32:27.386430
3424 11:32:27.386509 Set Vref, RX VrefLevel [Byte0]: 50
3425 11:32:27.389771 [Byte1]: 50
3426 11:32:27.394093
3427 11:32:27.394166 Set Vref, RX VrefLevel [Byte0]: 51
3428 11:32:27.397558 [Byte1]: 51
3429 11:32:27.402083
3430 11:32:27.402155 Set Vref, RX VrefLevel [Byte0]: 52
3431 11:32:27.405369 [Byte1]: 52
3432 11:32:27.410301
3433 11:32:27.410374 Set Vref, RX VrefLevel [Byte0]: 53
3434 11:32:27.413234 [Byte1]: 53
3435 11:32:27.417709
3436 11:32:27.417783 Set Vref, RX VrefLevel [Byte0]: 54
3437 11:32:27.421423 [Byte1]: 54
3438 11:32:27.425983
3439 11:32:27.426056 Set Vref, RX VrefLevel [Byte0]: 55
3440 11:32:27.429475 [Byte1]: 55
3441 11:32:27.434054
3442 11:32:27.434127 Set Vref, RX VrefLevel [Byte0]: 56
3443 11:32:27.437052 [Byte1]: 56
3444 11:32:27.441791
3445 11:32:27.441864 Set Vref, RX VrefLevel [Byte0]: 57
3446 11:32:27.445627 [Byte1]: 57
3447 11:32:27.449631
3448 11:32:27.449704 Set Vref, RX VrefLevel [Byte0]: 58
3449 11:32:27.453023 [Byte1]: 58
3450 11:32:27.457531
3451 11:32:27.457605 Set Vref, RX VrefLevel [Byte0]: 59
3452 11:32:27.461336 [Byte1]: 59
3453 11:32:27.465781
3454 11:32:27.465854 Set Vref, RX VrefLevel [Byte0]: 60
3455 11:32:27.468973 [Byte1]: 60
3456 11:32:27.473411
3457 11:32:27.473485 Set Vref, RX VrefLevel [Byte0]: 61
3458 11:32:27.476976 [Byte1]: 61
3459 11:32:27.481111
3460 11:32:27.481220 Set Vref, RX VrefLevel [Byte0]: 62
3461 11:32:27.485257 [Byte1]: 62
3462 11:32:27.489211
3463 11:32:27.489283 Set Vref, RX VrefLevel [Byte0]: 63
3464 11:32:27.492436 [Byte1]: 63
3465 11:32:27.497033
3466 11:32:27.497107 Set Vref, RX VrefLevel [Byte0]: 64
3467 11:32:27.500263 [Byte1]: 64
3468 11:32:27.504820
3469 11:32:27.504894 Set Vref, RX VrefLevel [Byte0]: 65
3470 11:32:27.508142 [Byte1]: 65
3471 11:32:27.512798
3472 11:32:27.512871 Set Vref, RX VrefLevel [Byte0]: 66
3473 11:32:27.516347 [Byte1]: 66
3474 11:32:27.521019
3475 11:32:27.521093 Set Vref, RX VrefLevel [Byte0]: 67
3476 11:32:27.524304 [Byte1]: 67
3477 11:32:27.528902
3478 11:32:27.529014 Set Vref, RX VrefLevel [Byte0]: 68
3479 11:32:27.532440 [Byte1]: 68
3480 11:32:27.536805
3481 11:32:27.536880 Set Vref, RX VrefLevel [Byte0]: 69
3482 11:32:27.540052 [Byte1]: 69
3483 11:32:27.544784
3484 11:32:27.544859 Set Vref, RX VrefLevel [Byte0]: 70
3485 11:32:27.548048 [Byte1]: 70
3486 11:32:27.552536
3487 11:32:27.552642 Set Vref, RX VrefLevel [Byte0]: 71
3488 11:32:27.555889 [Byte1]: 71
3489 11:32:27.560317
3490 11:32:27.560392 Set Vref, RX VrefLevel [Byte0]: 72
3491 11:32:27.563944 [Byte1]: 72
3492 11:32:27.568578
3493 11:32:27.568653 Set Vref, RX VrefLevel [Byte0]: 73
3494 11:32:27.571974 [Byte1]: 73
3495 11:32:27.576723
3496 11:32:27.576798 Final RX Vref Byte 0 = 62 to rank0
3497 11:32:27.579609 Final RX Vref Byte 1 = 51 to rank0
3498 11:32:27.583070 Final RX Vref Byte 0 = 62 to rank1
3499 11:32:27.586256 Final RX Vref Byte 1 = 51 to rank1==
3500 11:32:27.589875 Dram Type= 6, Freq= 0, CH_1, rank 0
3501 11:32:27.593015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 11:32:27.596363 ==
3503 11:32:27.596438 DQS Delay:
3504 11:32:27.596497 DQS0 = 0, DQS1 = 0
3505 11:32:27.599732 DQM Delay:
3506 11:32:27.599807 DQM0 = 116, DQM1 = 108
3507 11:32:27.603335 DQ Delay:
3508 11:32:27.606443 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =116
3509 11:32:27.609533 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3510 11:32:27.612935 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3511 11:32:27.616452 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3512 11:32:27.616527
3513 11:32:27.616584
3514 11:32:27.622976 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3515 11:32:27.626591 CH1 RK0: MR19=303, MR18=FFE3
3516 11:32:27.633015 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3517 11:32:27.633093
3518 11:32:27.636412 ----->DramcWriteLeveling(PI) begin...
3519 11:32:27.636505 ==
3520 11:32:27.639542 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 11:32:27.642849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 11:32:27.646229 ==
3523 11:32:27.646305 Write leveling (Byte 0): 25 => 25
3524 11:32:27.649378 Write leveling (Byte 1): 29 => 29
3525 11:32:27.652776 DramcWriteLeveling(PI) end<-----
3526 11:32:27.652851
3527 11:32:27.652909 ==
3528 11:32:27.656155 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 11:32:27.663121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 11:32:27.663215 ==
3531 11:32:27.663306 [Gating] SW mode calibration
3532 11:32:27.673021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3533 11:32:27.676415 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3534 11:32:27.679989 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3535 11:32:27.686589 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 11:32:27.690083 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 11:32:27.693125 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 11:32:27.699510 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 11:32:27.703029 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3540 11:32:27.706416 0 15 24 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 0)
3541 11:32:27.713299 0 15 28 | B1->B0 | 2525 2323 | 1 0 | (0 1) (0 0)
3542 11:32:27.716438 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 11:32:27.719915 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 11:32:27.726354 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 11:32:27.729643 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 11:32:27.733176 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 11:32:27.740042 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 11:32:27.743506 1 0 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
3549 11:32:27.746428 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 11:32:27.750042 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 11:32:27.756376 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 11:32:27.759791 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 11:32:27.763130 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 11:32:27.769704 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 11:32:27.772963 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3556 11:32:27.776524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3557 11:32:27.783181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3558 11:32:27.786408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:32:27.790176 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:32:27.796494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 11:32:27.799925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 11:32:27.803410 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 11:32:27.810416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 11:32:27.813274 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 11:32:27.816575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 11:32:27.820011 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 11:32:27.826756 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 11:32:27.829925 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 11:32:27.833348 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:32:27.840496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 11:32:27.843365 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 11:32:27.846818 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3573 11:32:27.853448 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3574 11:32:27.853524 Total UI for P1: 0, mck2ui 16
3575 11:32:27.860027 best dqsien dly found for B0: ( 1, 3, 24)
3576 11:32:27.863488 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 11:32:27.866645 Total UI for P1: 0, mck2ui 16
3578 11:32:27.870272 best dqsien dly found for B1: ( 1, 3, 28)
3579 11:32:27.873675 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3580 11:32:27.876820 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3581 11:32:27.876895
3582 11:32:27.879853 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3583 11:32:27.883330 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3584 11:32:27.886900 [Gating] SW calibration Done
3585 11:32:27.886987 ==
3586 11:32:27.890222 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:32:27.893625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:32:27.897034 ==
3589 11:32:27.897108 RX Vref Scan: 0
3590 11:32:27.897205
3591 11:32:27.900263 RX Vref 0 -> 0, step: 1
3592 11:32:27.900338
3593 11:32:27.900447 RX Delay -40 -> 252, step: 8
3594 11:32:27.907128 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3595 11:32:27.911327 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3596 11:32:27.913735 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3597 11:32:27.917100 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3598 11:32:27.920135 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3599 11:32:27.927060 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3600 11:32:27.930883 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3601 11:32:27.933902 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3602 11:32:27.937016 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3603 11:32:27.940264 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3604 11:32:27.947035 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3605 11:32:27.950240 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3606 11:32:27.953557 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3607 11:32:27.956968 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3608 11:32:27.960142 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3609 11:32:27.966749 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3610 11:32:27.966822 ==
3611 11:32:27.970629 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:32:27.973919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:32:27.974010 ==
3614 11:32:27.974109 DQS Delay:
3615 11:32:27.976911 DQS0 = 0, DQS1 = 0
3616 11:32:27.976989 DQM Delay:
3617 11:32:27.980112 DQM0 = 112, DQM1 = 110
3618 11:32:27.980187 DQ Delay:
3619 11:32:27.983984 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3620 11:32:27.986821 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3621 11:32:27.990512 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3622 11:32:27.993913 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3623 11:32:27.994044
3624 11:32:27.994105
3625 11:32:27.994159 ==
3626 11:32:27.996984 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:32:28.003943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:32:28.004060 ==
3629 11:32:28.004121
3630 11:32:28.004176
3631 11:32:28.004227 TX Vref Scan disable
3632 11:32:28.007850 == TX Byte 0 ==
3633 11:32:28.010776 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3634 11:32:28.017393 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3635 11:32:28.017542 == TX Byte 1 ==
3636 11:32:28.020647 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3637 11:32:28.024137 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3638 11:32:28.027630 ==
3639 11:32:28.030944 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 11:32:28.034101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 11:32:28.034177 ==
3642 11:32:28.045328 TX Vref=22, minBit 3, minWin=25, winSum=420
3643 11:32:28.048966 TX Vref=24, minBit 1, minWin=25, winSum=426
3644 11:32:28.052043 TX Vref=26, minBit 0, minWin=26, winSum=427
3645 11:32:28.055424 TX Vref=28, minBit 1, minWin=26, winSum=432
3646 11:32:28.058897 TX Vref=30, minBit 0, minWin=27, winSum=435
3647 11:32:28.062193 TX Vref=32, minBit 5, minWin=26, winSum=434
3648 11:32:28.069311 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
3649 11:32:28.069387
3650 11:32:28.072054 Final TX Range 1 Vref 30
3651 11:32:28.072129
3652 11:32:28.072186 ==
3653 11:32:28.075302 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 11:32:28.078864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 11:32:28.078941 ==
3656 11:32:28.079006
3657 11:32:28.079060
3658 11:32:28.082322 TX Vref Scan disable
3659 11:32:28.085888 == TX Byte 0 ==
3660 11:32:28.089145 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3661 11:32:28.092254 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3662 11:32:28.095685 == TX Byte 1 ==
3663 11:32:28.099118 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3664 11:32:28.102191 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3665 11:32:28.102266
3666 11:32:28.105939 [DATLAT]
3667 11:32:28.106014 Freq=1200, CH1 RK1
3668 11:32:28.106080
3669 11:32:28.109326 DATLAT Default: 0xd
3670 11:32:28.109402 0, 0xFFFF, sum = 0
3671 11:32:28.112974 1, 0xFFFF, sum = 0
3672 11:32:28.113076 2, 0xFFFF, sum = 0
3673 11:32:28.116148 3, 0xFFFF, sum = 0
3674 11:32:28.116225 4, 0xFFFF, sum = 0
3675 11:32:28.119055 5, 0xFFFF, sum = 0
3676 11:32:28.119131 6, 0xFFFF, sum = 0
3677 11:32:28.122658 7, 0xFFFF, sum = 0
3678 11:32:28.122736 8, 0xFFFF, sum = 0
3679 11:32:28.126377 9, 0xFFFF, sum = 0
3680 11:32:28.126461 10, 0xFFFF, sum = 0
3681 11:32:28.129108 11, 0xFFFF, sum = 0
3682 11:32:28.129197 12, 0x0, sum = 1
3683 11:32:28.132656 13, 0x0, sum = 2
3684 11:32:28.132733 14, 0x0, sum = 3
3685 11:32:28.135906 15, 0x0, sum = 4
3686 11:32:28.135996 best_step = 13
3687 11:32:28.136057
3688 11:32:28.136113 ==
3689 11:32:28.139596 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 11:32:28.145632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 11:32:28.145710 ==
3692 11:32:28.145771 RX Vref Scan: 0
3693 11:32:28.145826
3694 11:32:28.149138 RX Vref 0 -> 0, step: 1
3695 11:32:28.149216
3696 11:32:28.152590 RX Delay -21 -> 252, step: 4
3697 11:32:28.155516 iDelay=187, Bit 0, Center 112 (43 ~ 182) 140
3698 11:32:28.159189 iDelay=187, Bit 1, Center 108 (43 ~ 174) 132
3699 11:32:28.165704 iDelay=187, Bit 2, Center 106 (43 ~ 170) 128
3700 11:32:28.168966 iDelay=187, Bit 3, Center 112 (47 ~ 178) 132
3701 11:32:28.172451 iDelay=187, Bit 4, Center 114 (51 ~ 178) 128
3702 11:32:28.175829 iDelay=187, Bit 5, Center 122 (59 ~ 186) 128
3703 11:32:28.179300 iDelay=187, Bit 6, Center 120 (55 ~ 186) 132
3704 11:32:28.182747 iDelay=187, Bit 7, Center 110 (47 ~ 174) 128
3705 11:32:28.188991 iDelay=187, Bit 8, Center 96 (31 ~ 162) 132
3706 11:32:28.192652 iDelay=187, Bit 9, Center 98 (35 ~ 162) 128
3707 11:32:28.195955 iDelay=187, Bit 10, Center 110 (43 ~ 178) 136
3708 11:32:28.199140 iDelay=187, Bit 11, Center 102 (35 ~ 170) 136
3709 11:32:28.202421 iDelay=187, Bit 12, Center 114 (51 ~ 178) 128
3710 11:32:28.209464 iDelay=187, Bit 13, Center 120 (55 ~ 186) 132
3711 11:32:28.212598 iDelay=187, Bit 14, Center 118 (55 ~ 182) 128
3712 11:32:28.215813 iDelay=187, Bit 15, Center 116 (51 ~ 182) 132
3713 11:32:28.215887 ==
3714 11:32:28.219312 Dram Type= 6, Freq= 0, CH_1, rank 1
3715 11:32:28.223154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3716 11:32:28.223253 ==
3717 11:32:28.226132 DQS Delay:
3718 11:32:28.226207 DQS0 = 0, DQS1 = 0
3719 11:32:28.229678 DQM Delay:
3720 11:32:28.229765 DQM0 = 113, DQM1 = 109
3721 11:32:28.232274 DQ Delay:
3722 11:32:28.235771 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3723 11:32:28.239073 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =110
3724 11:32:28.242554 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3725 11:32:28.245921 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3726 11:32:28.245995
3727 11:32:28.246052
3728 11:32:28.252471 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3729 11:32:28.255804 CH1 RK1: MR19=304, MR18=FB02
3730 11:32:28.262499 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3731 11:32:28.265813 [RxdqsGatingPostProcess] freq 1200
3732 11:32:28.272409 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3733 11:32:28.272485 best DQS0 dly(2T, 0.5T) = (0, 11)
3734 11:32:28.275936 best DQS1 dly(2T, 0.5T) = (0, 11)
3735 11:32:28.279505 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3736 11:32:28.282509 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3737 11:32:28.286272 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 11:32:28.289078 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 11:32:28.292816 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 11:32:28.297052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 11:32:28.299813 Pre-setting of DQS Precalculation
3742 11:32:28.302693 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3743 11:32:28.313102 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3744 11:32:28.319257 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3745 11:32:28.319357
3746 11:32:28.319440
3747 11:32:28.323016 [Calibration Summary] 2400 Mbps
3748 11:32:28.323091 CH 0, Rank 0
3749 11:32:28.326397 SW Impedance : PASS
3750 11:32:28.326471 DUTY Scan : NO K
3751 11:32:28.329908 ZQ Calibration : PASS
3752 11:32:28.333055 Jitter Meter : NO K
3753 11:32:28.333188 CBT Training : PASS
3754 11:32:28.336636 Write leveling : PASS
3755 11:32:28.339366 RX DQS gating : PASS
3756 11:32:28.339441 RX DQ/DQS(RDDQC) : PASS
3757 11:32:28.342740 TX DQ/DQS : PASS
3758 11:32:28.342814 RX DATLAT : PASS
3759 11:32:28.346294 RX DQ/DQS(Engine): PASS
3760 11:32:28.349819 TX OE : NO K
3761 11:32:28.349894 All Pass.
3762 11:32:28.349951
3763 11:32:28.350004 CH 0, Rank 1
3764 11:32:28.352905 SW Impedance : PASS
3765 11:32:28.356314 DUTY Scan : NO K
3766 11:32:28.356416 ZQ Calibration : PASS
3767 11:32:28.359750 Jitter Meter : NO K
3768 11:32:28.363086 CBT Training : PASS
3769 11:32:28.363161 Write leveling : PASS
3770 11:32:28.366421 RX DQS gating : PASS
3771 11:32:28.370129 RX DQ/DQS(RDDQC) : PASS
3772 11:32:28.370207 TX DQ/DQS : PASS
3773 11:32:28.373041 RX DATLAT : PASS
3774 11:32:28.376538 RX DQ/DQS(Engine): PASS
3775 11:32:28.376612 TX OE : NO K
3776 11:32:28.376671 All Pass.
3777 11:32:28.376725
3778 11:32:28.380727 CH 1, Rank 0
3779 11:32:28.380802 SW Impedance : PASS
3780 11:32:28.382895 DUTY Scan : NO K
3781 11:32:28.386432 ZQ Calibration : PASS
3782 11:32:28.386530 Jitter Meter : NO K
3783 11:32:28.389895 CBT Training : PASS
3784 11:32:28.393028 Write leveling : PASS
3785 11:32:28.393153 RX DQS gating : PASS
3786 11:32:28.396206 RX DQ/DQS(RDDQC) : PASS
3787 11:32:28.400370 TX DQ/DQS : PASS
3788 11:32:28.400449 RX DATLAT : PASS
3789 11:32:28.403270 RX DQ/DQS(Engine): PASS
3790 11:32:28.406183 TX OE : NO K
3791 11:32:28.406258 All Pass.
3792 11:32:28.406329
3793 11:32:28.406397 CH 1, Rank 1
3794 11:32:28.410129 SW Impedance : PASS
3795 11:32:28.412884 DUTY Scan : NO K
3796 11:32:28.412952 ZQ Calibration : PASS
3797 11:32:28.416468 Jitter Meter : NO K
3798 11:32:28.420219 CBT Training : PASS
3799 11:32:28.420319 Write leveling : PASS
3800 11:32:28.423140 RX DQS gating : PASS
3801 11:32:28.423229 RX DQ/DQS(RDDQC) : PASS
3802 11:32:28.426673 TX DQ/DQS : PASS
3803 11:32:28.429683 RX DATLAT : PASS
3804 11:32:28.429752 RX DQ/DQS(Engine): PASS
3805 11:32:28.433489 TX OE : NO K
3806 11:32:28.433589 All Pass.
3807 11:32:28.433665
3808 11:32:28.436947 DramC Write-DBI off
3809 11:32:28.439943 PER_BANK_REFRESH: Hybrid Mode
3810 11:32:28.440016 TX_TRACKING: ON
3811 11:32:28.449878 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3812 11:32:28.453608 [FAST_K] Save calibration result to emmc
3813 11:32:28.456648 dramc_set_vcore_voltage set vcore to 650000
3814 11:32:28.459979 Read voltage for 600, 5
3815 11:32:28.460045 Vio18 = 0
3816 11:32:28.460101 Vcore = 650000
3817 11:32:28.463570 Vdram = 0
3818 11:32:28.463636 Vddq = 0
3819 11:32:28.463697 Vmddr = 0
3820 11:32:28.469998 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3821 11:32:28.473875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3822 11:32:28.476929 MEM_TYPE=3, freq_sel=19
3823 11:32:28.480095 sv_algorithm_assistance_LP4_1600
3824 11:32:28.483373 ============ PULL DRAM RESETB DOWN ============
3825 11:32:28.486678 ========== PULL DRAM RESETB DOWN end =========
3826 11:32:28.493627 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3827 11:32:28.496819 ===================================
3828 11:32:28.496910 LPDDR4 DRAM CONFIGURATION
3829 11:32:28.500178 ===================================
3830 11:32:28.503531 EX_ROW_EN[0] = 0x0
3831 11:32:28.506582 EX_ROW_EN[1] = 0x0
3832 11:32:28.506673 LP4Y_EN = 0x0
3833 11:32:28.510545 WORK_FSP = 0x0
3834 11:32:28.510614 WL = 0x2
3835 11:32:28.513689 RL = 0x2
3836 11:32:28.513778 BL = 0x2
3837 11:32:28.516517 RPST = 0x0
3838 11:32:28.516601 RD_PRE = 0x0
3839 11:32:28.519767 WR_PRE = 0x1
3840 11:32:28.519859 WR_PST = 0x0
3841 11:32:28.523423 DBI_WR = 0x0
3842 11:32:28.523524 DBI_RD = 0x0
3843 11:32:28.526469 OTF = 0x1
3844 11:32:28.529975 ===================================
3845 11:32:28.533613 ===================================
3846 11:32:28.533680 ANA top config
3847 11:32:28.536850 ===================================
3848 11:32:28.540277 DLL_ASYNC_EN = 0
3849 11:32:28.543405 ALL_SLAVE_EN = 1
3850 11:32:28.547000 NEW_RANK_MODE = 1
3851 11:32:28.547107 DLL_IDLE_MODE = 1
3852 11:32:28.550204 LP45_APHY_COMB_EN = 1
3853 11:32:28.553363 TX_ODT_DIS = 1
3854 11:32:28.556755 NEW_8X_MODE = 1
3855 11:32:28.559939 ===================================
3856 11:32:28.563199 ===================================
3857 11:32:28.566744 data_rate = 1200
3858 11:32:28.566813 CKR = 1
3859 11:32:28.570219 DQ_P2S_RATIO = 8
3860 11:32:28.573391 ===================================
3861 11:32:28.576745 CA_P2S_RATIO = 8
3862 11:32:28.580298 DQ_CA_OPEN = 0
3863 11:32:28.583258 DQ_SEMI_OPEN = 0
3864 11:32:28.583327 CA_SEMI_OPEN = 0
3865 11:32:28.586623 CA_FULL_RATE = 0
3866 11:32:28.589780 DQ_CKDIV4_EN = 1
3867 11:32:28.593303 CA_CKDIV4_EN = 1
3868 11:32:28.596976 CA_PREDIV_EN = 0
3869 11:32:28.600027 PH8_DLY = 0
3870 11:32:28.600094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3871 11:32:28.603214 DQ_AAMCK_DIV = 4
3872 11:32:28.606556 CA_AAMCK_DIV = 4
3873 11:32:28.609868 CA_ADMCK_DIV = 4
3874 11:32:28.613370 DQ_TRACK_CA_EN = 0
3875 11:32:28.616695 CA_PICK = 600
3876 11:32:28.616759 CA_MCKIO = 600
3877 11:32:28.619741 MCKIO_SEMI = 0
3878 11:32:28.622971 PLL_FREQ = 2288
3879 11:32:28.626367 DQ_UI_PI_RATIO = 32
3880 11:32:28.629739 CA_UI_PI_RATIO = 0
3881 11:32:28.633495 ===================================
3882 11:32:28.637068 ===================================
3883 11:32:28.639980 memory_type:LPDDR4
3884 11:32:28.640080 GP_NUM : 10
3885 11:32:28.643221 SRAM_EN : 1
3886 11:32:28.643286 MD32_EN : 0
3887 11:32:28.646548 ===================================
3888 11:32:28.649778 [ANA_INIT] >>>>>>>>>>>>>>
3889 11:32:28.653287 <<<<<< [CONFIGURE PHASE]: ANA_TX
3890 11:32:28.656653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3891 11:32:28.660410 ===================================
3892 11:32:28.663349 data_rate = 1200,PCW = 0X5800
3893 11:32:28.666712 ===================================
3894 11:32:28.669949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3895 11:32:28.673305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3896 11:32:28.679742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3897 11:32:28.686880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3898 11:32:28.689906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3899 11:32:28.693539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3900 11:32:28.693612 [ANA_INIT] flow start
3901 11:32:28.696702 [ANA_INIT] PLL >>>>>>>>
3902 11:32:28.700024 [ANA_INIT] PLL <<<<<<<<
3903 11:32:28.700099 [ANA_INIT] MIDPI >>>>>>>>
3904 11:32:28.703336 [ANA_INIT] MIDPI <<<<<<<<
3905 11:32:28.706934 [ANA_INIT] DLL >>>>>>>>
3906 11:32:28.707007 [ANA_INIT] flow end
3907 11:32:28.709793 ============ LP4 DIFF to SE enter ============
3908 11:32:28.716575 ============ LP4 DIFF to SE exit ============
3909 11:32:28.716648 [ANA_INIT] <<<<<<<<<<<<<
3910 11:32:28.720012 [Flow] Enable top DCM control >>>>>
3911 11:32:28.723602 [Flow] Enable top DCM control <<<<<
3912 11:32:28.726832 Enable DLL master slave shuffle
3913 11:32:28.733503 ==============================================================
3914 11:32:28.733582 Gating Mode config
3915 11:32:28.740246 ==============================================================
3916 11:32:28.743124 Config description:
3917 11:32:28.753346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3918 11:32:28.760180 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3919 11:32:28.763296 SELPH_MODE 0: By rank 1: By Phase
3920 11:32:28.770109 ==============================================================
3921 11:32:28.773634 GAT_TRACK_EN = 1
3922 11:32:28.773717 RX_GATING_MODE = 2
3923 11:32:28.776990 RX_GATING_TRACK_MODE = 2
3924 11:32:28.780508 SELPH_MODE = 1
3925 11:32:28.783731 PICG_EARLY_EN = 1
3926 11:32:28.786934 VALID_LAT_VALUE = 1
3927 11:32:28.793309 ==============================================================
3928 11:32:28.796986 Enter into Gating configuration >>>>
3929 11:32:28.800052 Exit from Gating configuration <<<<
3930 11:32:28.803306 Enter into DVFS_PRE_config >>>>>
3931 11:32:28.813414 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3932 11:32:28.816978 Exit from DVFS_PRE_config <<<<<
3933 11:32:28.820191 Enter into PICG configuration >>>>
3934 11:32:28.823775 Exit from PICG configuration <<<<
3935 11:32:28.826805 [RX_INPUT] configuration >>>>>
3936 11:32:28.826880 [RX_INPUT] configuration <<<<<
3937 11:32:28.833779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3938 11:32:28.840184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3939 11:32:28.843920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3940 11:32:28.850078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3941 11:32:28.857006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3942 11:32:28.863650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3943 11:32:28.867199 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3944 11:32:28.870003 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3945 11:32:28.876791 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3946 11:32:28.880162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3947 11:32:28.883635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3948 11:32:28.887319 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3949 11:32:28.890613 ===================================
3950 11:32:28.893805 LPDDR4 DRAM CONFIGURATION
3951 11:32:28.897028 ===================================
3952 11:32:28.900384 EX_ROW_EN[0] = 0x0
3953 11:32:28.900478 EX_ROW_EN[1] = 0x0
3954 11:32:28.903584 LP4Y_EN = 0x0
3955 11:32:28.903657 WORK_FSP = 0x0
3956 11:32:28.907278 WL = 0x2
3957 11:32:28.907349 RL = 0x2
3958 11:32:28.910125 BL = 0x2
3959 11:32:28.910202 RPST = 0x0
3960 11:32:28.913614 RD_PRE = 0x0
3961 11:32:28.913680 WR_PRE = 0x1
3962 11:32:28.916858 WR_PST = 0x0
3963 11:32:28.916929 DBI_WR = 0x0
3964 11:32:28.920983 DBI_RD = 0x0
3965 11:32:28.921054 OTF = 0x1
3966 11:32:28.924192 ===================================
3967 11:32:28.930696 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3968 11:32:28.934000 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3969 11:32:28.937681 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3970 11:32:28.940807 ===================================
3971 11:32:28.944201 LPDDR4 DRAM CONFIGURATION
3972 11:32:28.947592 ===================================
3973 11:32:28.947666 EX_ROW_EN[0] = 0x10
3974 11:32:28.950810 EX_ROW_EN[1] = 0x0
3975 11:32:28.953783 LP4Y_EN = 0x0
3976 11:32:28.953858 WORK_FSP = 0x0
3977 11:32:28.957179 WL = 0x2
3978 11:32:28.957278 RL = 0x2
3979 11:32:28.960586 BL = 0x2
3980 11:32:28.960660 RPST = 0x0
3981 11:32:28.963754 RD_PRE = 0x0
3982 11:32:28.963828 WR_PRE = 0x1
3983 11:32:28.967629 WR_PST = 0x0
3984 11:32:28.967703 DBI_WR = 0x0
3985 11:32:28.970559 DBI_RD = 0x0
3986 11:32:28.970633 OTF = 0x1
3987 11:32:28.974156 ===================================
3988 11:32:28.980546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3989 11:32:28.984808 nWR fixed to 30
3990 11:32:28.988312 [ModeRegInit_LP4] CH0 RK0
3991 11:32:28.988387 [ModeRegInit_LP4] CH0 RK1
3992 11:32:28.991503 [ModeRegInit_LP4] CH1 RK0
3993 11:32:28.994753 [ModeRegInit_LP4] CH1 RK1
3994 11:32:28.994827 match AC timing 17
3995 11:32:29.001333 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3996 11:32:29.004737 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3997 11:32:29.007859 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3998 11:32:29.014748 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3999 11:32:29.018394 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4000 11:32:29.018468 ==
4001 11:32:29.021232 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 11:32:29.024524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 11:32:29.024621 ==
4004 11:32:29.031694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 11:32:29.038189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 11:32:29.041326 [CA 0] Center 36 (6~67) winsize 62
4007 11:32:29.044769 [CA 1] Center 35 (5~66) winsize 62
4008 11:32:29.048014 [CA 2] Center 34 (4~65) winsize 62
4009 11:32:29.051238 [CA 3] Center 34 (4~64) winsize 61
4010 11:32:29.054545 [CA 4] Center 33 (3~64) winsize 62
4011 11:32:29.057926 [CA 5] Center 33 (3~64) winsize 62
4012 11:32:29.057994
4013 11:32:29.061711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 11:32:29.061788
4015 11:32:29.065129 [CATrainingPosCal] consider 1 rank data
4016 11:32:29.068655 u2DelayCellTimex100 = 270/100 ps
4017 11:32:29.071593 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4018 11:32:29.074901 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4019 11:32:29.078107 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 11:32:29.081371 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4021 11:32:29.084846 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 11:32:29.088396 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 11:32:29.088460
4024 11:32:29.094992 CA PerBit enable=1, Macro0, CA PI delay=33
4025 11:32:29.095066
4026 11:32:29.095121 [CBTSetCACLKResult] CA Dly = 33
4027 11:32:29.098147 CS Dly: 5 (0~36)
4028 11:32:29.098233 ==
4029 11:32:29.101869 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 11:32:29.105393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 11:32:29.105464 ==
4032 11:32:29.111993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4033 11:32:29.118139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4034 11:32:29.121538 [CA 0] Center 36 (6~66) winsize 61
4035 11:32:29.124849 [CA 1] Center 36 (6~66) winsize 61
4036 11:32:29.128185 [CA 2] Center 34 (4~65) winsize 62
4037 11:32:29.131662 [CA 3] Center 34 (4~65) winsize 62
4038 11:32:29.135036 [CA 4] Center 33 (3~64) winsize 62
4039 11:32:29.138363 [CA 5] Center 33 (3~64) winsize 62
4040 11:32:29.138426
4041 11:32:29.141633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4042 11:32:29.141697
4043 11:32:29.145334 [CATrainingPosCal] consider 2 rank data
4044 11:32:29.148263 u2DelayCellTimex100 = 270/100 ps
4045 11:32:29.151644 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4046 11:32:29.154948 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4047 11:32:29.158364 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4048 11:32:29.162251 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4049 11:32:29.164786 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4050 11:32:29.168288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 11:32:29.168353
4052 11:32:29.175344 CA PerBit enable=1, Macro0, CA PI delay=33
4053 11:32:29.175411
4054 11:32:29.175466 [CBTSetCACLKResult] CA Dly = 33
4055 11:32:29.178108 CS Dly: 5 (0~37)
4056 11:32:29.178194
4057 11:32:29.181427 ----->DramcWriteLeveling(PI) begin...
4058 11:32:29.181491 ==
4059 11:32:29.184977 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 11:32:29.188404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 11:32:29.188473 ==
4062 11:32:29.191755 Write leveling (Byte 0): 33 => 33
4063 11:32:29.195359 Write leveling (Byte 1): 30 => 30
4064 11:32:29.198427 DramcWriteLeveling(PI) end<-----
4065 11:32:29.198532
4066 11:32:29.198619 ==
4067 11:32:29.201910 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 11:32:29.205575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 11:32:29.205649 ==
4070 11:32:29.208482 [Gating] SW mode calibration
4071 11:32:29.215191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4072 11:32:29.221846 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4073 11:32:29.225016 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4074 11:32:29.231699 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 11:32:29.235345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4076 11:32:29.238690 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4077 11:32:29.245256 0 9 16 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 1)
4078 11:32:29.248653 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
4079 11:32:29.251517 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 11:32:29.258294 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 11:32:29.261699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 11:32:29.265020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 11:32:29.271734 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 11:32:29.275106 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 11:32:29.278496 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (0 0) (1 1)
4086 11:32:29.281257 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4087 11:32:29.288131 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 11:32:29.291523 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 11:32:29.295042 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 11:32:29.301296 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 11:32:29.305062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 11:32:29.307948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 11:32:29.314899 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4094 11:32:29.318043 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:32:29.321614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:32:29.328083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 11:32:29.331234 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 11:32:29.335041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 11:32:29.341724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 11:32:29.344753 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 11:32:29.348347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 11:32:29.355096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 11:32:29.357931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 11:32:29.361666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 11:32:29.367833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:32:29.371597 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 11:32:29.374621 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 11:32:29.378224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 11:32:29.384932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4110 11:32:29.388245 Total UI for P1: 0, mck2ui 16
4111 11:32:29.391543 best dqsien dly found for B0: ( 0, 13, 14)
4112 11:32:29.394826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 11:32:29.398460 Total UI for P1: 0, mck2ui 16
4114 11:32:29.401745 best dqsien dly found for B1: ( 0, 13, 16)
4115 11:32:29.405267 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4116 11:32:29.408109 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4117 11:32:29.408176
4118 11:32:29.411572 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4119 11:32:29.414899 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4120 11:32:29.418456 [Gating] SW calibration Done
4121 11:32:29.418525 ==
4122 11:32:29.422106 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:32:29.428127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:32:29.428192 ==
4125 11:32:29.428246 RX Vref Scan: 0
4126 11:32:29.428298
4127 11:32:29.431388 RX Vref 0 -> 0, step: 1
4128 11:32:29.431454
4129 11:32:29.435209 RX Delay -230 -> 252, step: 16
4130 11:32:29.438284 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4131 11:32:29.441702 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4132 11:32:29.444666 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4133 11:32:29.451620 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4134 11:32:29.454744 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4135 11:32:29.458457 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4136 11:32:29.462041 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4137 11:32:29.464934 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4138 11:32:29.471622 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4139 11:32:29.475008 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4140 11:32:29.478336 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4141 11:32:29.481802 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4142 11:32:29.488158 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4143 11:32:29.491484 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4144 11:32:29.494753 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4145 11:32:29.498237 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4146 11:32:29.498326 ==
4147 11:32:29.501490 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:32:29.508344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:32:29.508419 ==
4150 11:32:29.508476 DQS Delay:
4151 11:32:29.511883 DQS0 = 0, DQS1 = 0
4152 11:32:29.511945 DQM Delay:
4153 11:32:29.511997 DQM0 = 42, DQM1 = 34
4154 11:32:29.515178 DQ Delay:
4155 11:32:29.518294 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4156 11:32:29.521724 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4157 11:32:29.524842 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4158 11:32:29.528469 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4159 11:32:29.528558
4160 11:32:29.528653
4161 11:32:29.528734 ==
4162 11:32:29.531813 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 11:32:29.535554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 11:32:29.535622 ==
4165 11:32:29.535679
4166 11:32:29.535730
4167 11:32:29.538503 TX Vref Scan disable
4168 11:32:29.538573 == TX Byte 0 ==
4169 11:32:29.545409 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4170 11:32:29.548405 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4171 11:32:29.548507 == TX Byte 1 ==
4172 11:32:29.555348 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4173 11:32:29.558804 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4174 11:32:29.558873 ==
4175 11:32:29.561954 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 11:32:29.565229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 11:32:29.565318 ==
4178 11:32:29.565414
4179 11:32:29.565493
4180 11:32:29.568681 TX Vref Scan disable
4181 11:32:29.571795 == TX Byte 0 ==
4182 11:32:29.575050 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4183 11:32:29.578770 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4184 11:32:29.581895 == TX Byte 1 ==
4185 11:32:29.585857 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4186 11:32:29.588592 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4187 11:32:29.588677
4188 11:32:29.591789 [DATLAT]
4189 11:32:29.591875 Freq=600, CH0 RK0
4190 11:32:29.591955
4191 11:32:29.595251 DATLAT Default: 0x9
4192 11:32:29.595345 0, 0xFFFF, sum = 0
4193 11:32:29.598744 1, 0xFFFF, sum = 0
4194 11:32:29.598844 2, 0xFFFF, sum = 0
4195 11:32:29.602188 3, 0xFFFF, sum = 0
4196 11:32:29.602291 4, 0xFFFF, sum = 0
4197 11:32:29.605500 5, 0xFFFF, sum = 0
4198 11:32:29.605569 6, 0xFFFF, sum = 0
4199 11:32:29.608966 7, 0xFFFF, sum = 0
4200 11:32:29.609061 8, 0x0, sum = 1
4201 11:32:29.611830 9, 0x0, sum = 2
4202 11:32:29.611893 10, 0x0, sum = 3
4203 11:32:29.615572 11, 0x0, sum = 4
4204 11:32:29.615637 best_step = 9
4205 11:32:29.615696
4206 11:32:29.615746 ==
4207 11:32:29.618601 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 11:32:29.621812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 11:32:29.625076 ==
4210 11:32:29.625182 RX Vref Scan: 1
4211 11:32:29.625263
4212 11:32:29.628908 RX Vref 0 -> 0, step: 1
4213 11:32:29.628972
4214 11:32:29.631957 RX Delay -195 -> 252, step: 8
4215 11:32:29.632022
4216 11:32:29.635209 Set Vref, RX VrefLevel [Byte0]: 53
4217 11:32:29.638393 [Byte1]: 53
4218 11:32:29.638483
4219 11:32:29.642103 Final RX Vref Byte 0 = 53 to rank0
4220 11:32:29.645324 Final RX Vref Byte 1 = 53 to rank0
4221 11:32:29.648533 Final RX Vref Byte 0 = 53 to rank1
4222 11:32:29.651989 Final RX Vref Byte 1 = 53 to rank1==
4223 11:32:29.655632 Dram Type= 6, Freq= 0, CH_0, rank 0
4224 11:32:29.658808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:32:29.658884 ==
4226 11:32:29.658942 DQS Delay:
4227 11:32:29.662008 DQS0 = 0, DQS1 = 0
4228 11:32:29.662082 DQM Delay:
4229 11:32:29.665503 DQM0 = 42, DQM1 = 33
4230 11:32:29.665578 DQ Delay:
4231 11:32:29.668869 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4232 11:32:29.672246 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4233 11:32:29.675577 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4234 11:32:29.679156 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4235 11:32:29.679231
4236 11:32:29.679307
4237 11:32:29.688788 [DQSOSCAuto] RK0, (LSB)MR18= 0x4929, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4238 11:32:29.688890 CH0 RK0: MR19=808, MR18=4929
4239 11:32:29.695405 CH0_RK0: MR19=0x808, MR18=0x4929, DQSOSC=396, MR23=63, INC=167, DEC=111
4240 11:32:29.695504
4241 11:32:29.698710 ----->DramcWriteLeveling(PI) begin...
4242 11:32:29.698810 ==
4243 11:32:29.701954 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 11:32:29.708666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 11:32:29.708741 ==
4246 11:32:29.711911 Write leveling (Byte 0): 33 => 33
4247 11:32:29.711985 Write leveling (Byte 1): 29 => 29
4248 11:32:29.715748 DramcWriteLeveling(PI) end<-----
4249 11:32:29.715822
4250 11:32:29.718498 ==
4251 11:32:29.721831 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 11:32:29.725232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 11:32:29.725331 ==
4254 11:32:29.728879 [Gating] SW mode calibration
4255 11:32:29.735252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4256 11:32:29.738741 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4257 11:32:29.745759 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 11:32:29.748797 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4259 11:32:29.752055 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4260 11:32:29.758976 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4261 11:32:29.762199 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4262 11:32:29.765701 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 11:32:29.772169 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 11:32:29.775462 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 11:32:29.778841 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 11:32:29.782314 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 11:32:29.788582 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 11:32:29.791856 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4269 11:32:29.795169 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4270 11:32:29.802037 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 11:32:29.805310 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 11:32:29.808826 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:32:29.815447 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 11:32:29.818626 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:32:29.821781 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 11:32:29.828545 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 11:32:29.832094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4278 11:32:29.835254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:32:29.841887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:32:29.845041 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:32:29.848677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 11:32:29.855600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 11:32:29.858783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 11:32:29.861758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 11:32:29.868737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 11:32:29.871986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 11:32:29.875162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 11:32:29.878525 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:32:29.885242 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:32:29.888810 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 11:32:29.892253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 11:32:29.898433 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 11:32:29.901834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4294 11:32:29.905071 Total UI for P1: 0, mck2ui 16
4295 11:32:29.908779 best dqsien dly found for B0: ( 0, 13, 14)
4296 11:32:29.911633 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 11:32:29.914947 Total UI for P1: 0, mck2ui 16
4298 11:32:29.918329 best dqsien dly found for B1: ( 0, 13, 16)
4299 11:32:29.921745 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4300 11:32:29.924997 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4301 11:32:29.928257
4302 11:32:29.931691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4303 11:32:29.935395 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4304 11:32:29.939037 [Gating] SW calibration Done
4305 11:32:29.939137 ==
4306 11:32:29.941837 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 11:32:29.945237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 11:32:29.945304 ==
4309 11:32:29.945360 RX Vref Scan: 0
4310 11:32:29.945413
4311 11:32:29.948590 RX Vref 0 -> 0, step: 1
4312 11:32:29.948669
4313 11:32:29.951722 RX Delay -230 -> 252, step: 16
4314 11:32:29.955738 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4315 11:32:29.958735 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4316 11:32:29.965374 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4317 11:32:29.968433 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4318 11:32:29.972572 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4319 11:32:29.975569 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4320 11:32:29.978872 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4321 11:32:29.985137 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4322 11:32:29.988784 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4323 11:32:29.991885 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4324 11:32:29.995361 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4325 11:32:30.001934 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4326 11:32:30.005272 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4327 11:32:30.008949 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4328 11:32:30.012102 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4329 11:32:30.019057 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4330 11:32:30.019128 ==
4331 11:32:30.022250 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 11:32:30.026011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 11:32:30.026087 ==
4334 11:32:30.026144 DQS Delay:
4335 11:32:30.029064 DQS0 = 0, DQS1 = 0
4336 11:32:30.029176 DQM Delay:
4337 11:32:30.032351 DQM0 = 40, DQM1 = 33
4338 11:32:30.032425 DQ Delay:
4339 11:32:30.035458 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4340 11:32:30.038732 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4341 11:32:30.042168 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4342 11:32:30.045575 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4343 11:32:30.045649
4344 11:32:30.045706
4345 11:32:30.045759 ==
4346 11:32:30.049015 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:32:30.052527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:32:30.052602 ==
4349 11:32:30.052660
4350 11:32:30.052712
4351 11:32:30.055289 TX Vref Scan disable
4352 11:32:30.058862 == TX Byte 0 ==
4353 11:32:30.062292 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4354 11:32:30.065633 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4355 11:32:30.068797 == TX Byte 1 ==
4356 11:32:30.072258 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4357 11:32:30.075499 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4358 11:32:30.075573 ==
4359 11:32:30.079295 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 11:32:30.085744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 11:32:30.085818 ==
4362 11:32:30.085876
4363 11:32:30.085929
4364 11:32:30.085980 TX Vref Scan disable
4365 11:32:30.089837 == TX Byte 0 ==
4366 11:32:30.093076 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4367 11:32:30.096806 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4368 11:32:30.100351 == TX Byte 1 ==
4369 11:32:30.103455 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4370 11:32:30.106842 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4371 11:32:30.110318
4372 11:32:30.110391 [DATLAT]
4373 11:32:30.110448 Freq=600, CH0 RK1
4374 11:32:30.110502
4375 11:32:30.113161 DATLAT Default: 0x9
4376 11:32:30.113234 0, 0xFFFF, sum = 0
4377 11:32:30.116390 1, 0xFFFF, sum = 0
4378 11:32:30.116465 2, 0xFFFF, sum = 0
4379 11:32:30.119693 3, 0xFFFF, sum = 0
4380 11:32:30.119812 4, 0xFFFF, sum = 0
4381 11:32:30.123274 5, 0xFFFF, sum = 0
4382 11:32:30.123471 6, 0xFFFF, sum = 0
4383 11:32:30.126589 7, 0xFFFF, sum = 0
4384 11:32:30.126688 8, 0x0, sum = 1
4385 11:32:30.130029 9, 0x0, sum = 2
4386 11:32:30.130103 10, 0x0, sum = 3
4387 11:32:30.133704 11, 0x0, sum = 4
4388 11:32:30.133780 best_step = 9
4389 11:32:30.133836
4390 11:32:30.133889 ==
4391 11:32:30.136795 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 11:32:30.143417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 11:32:30.143492 ==
4394 11:32:30.143549 RX Vref Scan: 0
4395 11:32:30.143602
4396 11:32:30.146482 RX Vref 0 -> 0, step: 1
4397 11:32:30.146560
4398 11:32:30.149954 RX Delay -179 -> 252, step: 8
4399 11:32:30.153067 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4400 11:32:30.159941 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4401 11:32:30.162830 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4402 11:32:30.166666 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4403 11:32:30.169823 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4404 11:32:30.173397 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4405 11:32:30.180231 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4406 11:32:30.183153 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4407 11:32:30.186446 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4408 11:32:30.189737 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4409 11:32:30.193015 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4410 11:32:30.199938 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4411 11:32:30.203149 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4412 11:32:30.206619 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4413 11:32:30.209832 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4414 11:32:30.216651 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4415 11:32:30.216748 ==
4416 11:32:30.220165 Dram Type= 6, Freq= 0, CH_0, rank 1
4417 11:32:30.222847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 11:32:30.222921 ==
4419 11:32:30.222978 DQS Delay:
4420 11:32:30.226254 DQS0 = 0, DQS1 = 0
4421 11:32:30.226327 DQM Delay:
4422 11:32:30.229497 DQM0 = 39, DQM1 = 32
4423 11:32:30.229570 DQ Delay:
4424 11:32:30.232817 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4425 11:32:30.236265 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4426 11:32:30.239488 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =20
4427 11:32:30.243025 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4428 11:32:30.243098
4429 11:32:30.243171
4430 11:32:30.253055 [DQSOSCAuto] RK1, (LSB)MR18= 0x5336, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4431 11:32:30.253196 CH0 RK1: MR19=808, MR18=5336
4432 11:32:30.259683 CH0_RK1: MR19=0x808, MR18=0x5336, DQSOSC=394, MR23=63, INC=168, DEC=112
4433 11:32:30.262735 [RxdqsGatingPostProcess] freq 600
4434 11:32:30.269492 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4435 11:32:30.272722 Pre-setting of DQS Precalculation
4436 11:32:30.276319 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4437 11:32:30.276392 ==
4438 11:32:30.279330 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 11:32:30.282997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 11:32:30.283069 ==
4441 11:32:30.289483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 11:32:30.296133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4443 11:32:30.299613 [CA 0] Center 35 (5~66) winsize 62
4444 11:32:30.303037 [CA 1] Center 35 (5~66) winsize 62
4445 11:32:30.306019 [CA 2] Center 34 (3~65) winsize 63
4446 11:32:30.309909 [CA 3] Center 34 (3~65) winsize 63
4447 11:32:30.312929 [CA 4] Center 34 (3~65) winsize 63
4448 11:32:30.316363 [CA 5] Center 33 (3~64) winsize 62
4449 11:32:30.316462
4450 11:32:30.319609 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4451 11:32:30.319701
4452 11:32:30.322741 [CATrainingPosCal] consider 1 rank data
4453 11:32:30.326148 u2DelayCellTimex100 = 270/100 ps
4454 11:32:30.329526 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4455 11:32:30.332764 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 11:32:30.336100 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4457 11:32:30.339852 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4458 11:32:30.343039 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4459 11:32:30.346181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 11:32:30.350024
4461 11:32:30.352818 CA PerBit enable=1, Macro0, CA PI delay=33
4462 11:32:30.352912
4463 11:32:30.356207 [CBTSetCACLKResult] CA Dly = 33
4464 11:32:30.356282 CS Dly: 4 (0~35)
4465 11:32:30.356341 ==
4466 11:32:30.359653 Dram Type= 6, Freq= 0, CH_1, rank 1
4467 11:32:30.362970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 11:32:30.363072 ==
4469 11:32:30.370157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4470 11:32:30.376729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4471 11:32:30.379762 [CA 0] Center 35 (5~66) winsize 62
4472 11:32:30.383116 [CA 1] Center 36 (6~66) winsize 61
4473 11:32:30.386010 [CA 2] Center 34 (4~65) winsize 62
4474 11:32:30.390132 [CA 3] Center 34 (3~65) winsize 63
4475 11:32:30.393108 [CA 4] Center 34 (3~65) winsize 63
4476 11:32:30.396056 [CA 5] Center 33 (3~64) winsize 62
4477 11:32:30.396133
4478 11:32:30.399649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4479 11:32:30.399726
4480 11:32:30.402843 [CATrainingPosCal] consider 2 rank data
4481 11:32:30.406169 u2DelayCellTimex100 = 270/100 ps
4482 11:32:30.409935 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4483 11:32:30.412965 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4484 11:32:30.416269 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4485 11:32:30.419449 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4486 11:32:30.423128 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4487 11:32:30.429499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 11:32:30.429601
4489 11:32:30.432908 CA PerBit enable=1, Macro0, CA PI delay=33
4490 11:32:30.432989
4491 11:32:30.436215 [CBTSetCACLKResult] CA Dly = 33
4492 11:32:30.436293 CS Dly: 5 (0~37)
4493 11:32:30.436353
4494 11:32:30.439580 ----->DramcWriteLeveling(PI) begin...
4495 11:32:30.439659 ==
4496 11:32:30.442955 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 11:32:30.446284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 11:32:30.450180 ==
4499 11:32:30.450257 Write leveling (Byte 0): 29 => 29
4500 11:32:30.452913 Write leveling (Byte 1): 29 => 29
4501 11:32:30.456439 DramcWriteLeveling(PI) end<-----
4502 11:32:30.456510
4503 11:32:30.456584 ==
4504 11:32:30.459756 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 11:32:30.466405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 11:32:30.466475 ==
4507 11:32:30.466535 [Gating] SW mode calibration
4508 11:32:30.476893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4509 11:32:30.479351 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4510 11:32:30.483307 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4511 11:32:30.489522 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4512 11:32:30.493149 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 11:32:30.496189 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
4514 11:32:30.502803 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4515 11:32:30.506125 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 11:32:30.509489 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4517 11:32:30.516070 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 11:32:30.519651 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 11:32:30.523078 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4520 11:32:30.529744 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 11:32:30.533076 0 10 12 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
4522 11:32:30.536646 0 10 16 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
4523 11:32:30.542871 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 11:32:30.546274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 11:32:30.549627 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 11:32:30.556132 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 11:32:30.559624 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 11:32:30.562740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 11:32:30.569713 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:32:30.573027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:32:30.576422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 11:32:30.579825 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 11:32:30.586240 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 11:32:30.589638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 11:32:30.592909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 11:32:30.599736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 11:32:30.602959 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 11:32:30.606816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 11:32:30.612937 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 11:32:30.616168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:32:30.620256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:32:30.626168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:32:30.629929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 11:32:30.633084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 11:32:30.639473 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4546 11:32:30.642718 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 11:32:30.645998 Total UI for P1: 0, mck2ui 16
4548 11:32:30.649828 best dqsien dly found for B0: ( 0, 13, 12)
4549 11:32:30.653250 Total UI for P1: 0, mck2ui 16
4550 11:32:30.656515 best dqsien dly found for B1: ( 0, 13, 14)
4551 11:32:30.659614 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4552 11:32:30.663151 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4553 11:32:30.663220
4554 11:32:30.666352 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4555 11:32:30.669574 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4556 11:32:30.673663 [Gating] SW calibration Done
4557 11:32:30.673731 ==
4558 11:32:30.676479 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:32:30.679403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:32:30.679492 ==
4561 11:32:30.683266 RX Vref Scan: 0
4562 11:32:30.683354
4563 11:32:30.686948 RX Vref 0 -> 0, step: 1
4564 11:32:30.687038
4565 11:32:30.687119 RX Delay -230 -> 252, step: 16
4566 11:32:30.693089 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4567 11:32:30.696563 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4568 11:32:30.699877 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4569 11:32:30.703174 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4570 11:32:30.709517 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4571 11:32:30.713011 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4572 11:32:30.716526 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4573 11:32:30.719563 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4574 11:32:30.723167 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4575 11:32:30.729742 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4576 11:32:30.733388 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4577 11:32:30.736643 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4578 11:32:30.740060 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4579 11:32:30.746479 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4580 11:32:30.749671 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4581 11:32:30.753012 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4582 11:32:30.753103 ==
4583 11:32:30.756497 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 11:32:30.759512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 11:32:30.763318 ==
4586 11:32:30.763383 DQS Delay:
4587 11:32:30.763440 DQS0 = 0, DQS1 = 0
4588 11:32:30.766783 DQM Delay:
4589 11:32:30.766846 DQM0 = 43, DQM1 = 35
4590 11:32:30.766900 DQ Delay:
4591 11:32:30.770026 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4592 11:32:30.773135 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4593 11:32:30.776629 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4594 11:32:30.779929 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4595 11:32:30.780018
4596 11:32:30.780100
4597 11:32:30.782863 ==
4598 11:32:30.786256 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 11:32:30.789726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:32:30.789801 ==
4601 11:32:30.789860
4602 11:32:30.789913
4603 11:32:30.792939 TX Vref Scan disable
4604 11:32:30.793016 == TX Byte 0 ==
4605 11:32:30.796363 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4606 11:32:30.803548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4607 11:32:30.803636 == TX Byte 1 ==
4608 11:32:30.806530 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4609 11:32:30.813371 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4610 11:32:30.813445 ==
4611 11:32:30.816545 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 11:32:30.819758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 11:32:30.819851 ==
4614 11:32:30.819932
4615 11:32:30.820011
4616 11:32:30.822807 TX Vref Scan disable
4617 11:32:30.826455 == TX Byte 0 ==
4618 11:32:30.830055 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4619 11:32:30.832987 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4620 11:32:30.836326 == TX Byte 1 ==
4621 11:32:30.839780 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4622 11:32:30.843188 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4623 11:32:30.843274
4624 11:32:30.846409 [DATLAT]
4625 11:32:30.846476 Freq=600, CH1 RK0
4626 11:32:30.846530
4627 11:32:30.849888 DATLAT Default: 0x9
4628 11:32:30.849974 0, 0xFFFF, sum = 0
4629 11:32:30.853316 1, 0xFFFF, sum = 0
4630 11:32:30.853408 2, 0xFFFF, sum = 0
4631 11:32:30.856343 3, 0xFFFF, sum = 0
4632 11:32:30.856431 4, 0xFFFF, sum = 0
4633 11:32:30.859680 5, 0xFFFF, sum = 0
4634 11:32:30.859757 6, 0xFFFF, sum = 0
4635 11:32:30.863287 7, 0xFFFF, sum = 0
4636 11:32:30.863382 8, 0x0, sum = 1
4637 11:32:30.866546 9, 0x0, sum = 2
4638 11:32:30.866614 10, 0x0, sum = 3
4639 11:32:30.869756 11, 0x0, sum = 4
4640 11:32:30.869823 best_step = 9
4641 11:32:30.869876
4642 11:32:30.869927 ==
4643 11:32:30.873018 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 11:32:30.876363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 11:32:30.876427 ==
4646 11:32:30.879664 RX Vref Scan: 1
4647 11:32:30.879748
4648 11:32:30.883300 RX Vref 0 -> 0, step: 1
4649 11:32:30.883383
4650 11:32:30.883441 RX Delay -195 -> 252, step: 8
4651 11:32:30.883519
4652 11:32:30.886730 Set Vref, RX VrefLevel [Byte0]: 62
4653 11:32:30.890007 [Byte1]: 51
4654 11:32:30.894099
4655 11:32:30.894166 Final RX Vref Byte 0 = 62 to rank0
4656 11:32:30.897918 Final RX Vref Byte 1 = 51 to rank0
4657 11:32:30.901218 Final RX Vref Byte 0 = 62 to rank1
4658 11:32:30.904401 Final RX Vref Byte 1 = 51 to rank1==
4659 11:32:30.907707 Dram Type= 6, Freq= 0, CH_1, rank 0
4660 11:32:30.914607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 11:32:30.914675 ==
4662 11:32:30.914731 DQS Delay:
4663 11:32:30.914787 DQS0 = 0, DQS1 = 0
4664 11:32:30.917880 DQM Delay:
4665 11:32:30.917942 DQM0 = 40, DQM1 = 32
4666 11:32:30.921252 DQ Delay:
4667 11:32:30.924104 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4668 11:32:30.928011 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4669 11:32:30.928098 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =28
4670 11:32:30.934269 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4671 11:32:30.934334
4672 11:32:30.934392
4673 11:32:30.941029 [DQSOSCAuto] RK0, (LSB)MR18= 0x490e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4674 11:32:30.944599 CH1 RK0: MR19=808, MR18=490E
4675 11:32:30.950894 CH1_RK0: MR19=0x808, MR18=0x490E, DQSOSC=396, MR23=63, INC=167, DEC=111
4676 11:32:30.950986
4677 11:32:30.954325 ----->DramcWriteLeveling(PI) begin...
4678 11:32:30.954394 ==
4679 11:32:30.957839 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 11:32:30.960896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 11:32:30.960987 ==
4682 11:32:30.964365 Write leveling (Byte 0): 30 => 30
4683 11:32:30.967608 Write leveling (Byte 1): 31 => 31
4684 11:32:30.970899 DramcWriteLeveling(PI) end<-----
4685 11:32:30.970989
4686 11:32:30.971072 ==
4687 11:32:30.974607 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 11:32:30.978013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 11:32:30.978079 ==
4690 11:32:30.981071 [Gating] SW mode calibration
4691 11:32:30.988213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4692 11:32:30.994358 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4693 11:32:30.997823 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4694 11:32:31.000994 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4695 11:32:31.007719 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4696 11:32:31.011295 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (1 1) (0 0)
4697 11:32:31.014552 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4698 11:32:31.021215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 11:32:31.024993 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 11:32:31.028061 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 11:32:31.034614 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4702 11:32:31.037872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 11:32:31.041164 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4704 11:32:31.044413 0 10 12 | B1->B0 | 3131 3939 | 1 1 | (0 0) (0 0)
4705 11:32:31.051968 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 11:32:31.054552 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:32:31.058167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 11:32:31.064613 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 11:32:31.067923 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 11:32:31.071567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 11:32:31.077697 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 11:32:31.080995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4713 11:32:31.084439 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:32:31.090939 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:32:31.094731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 11:32:31.097658 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 11:32:31.104571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 11:32:31.108462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 11:32:31.111374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 11:32:31.118091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 11:32:31.121510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 11:32:31.124878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 11:32:31.131588 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 11:32:31.134696 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 11:32:31.138014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 11:32:31.141280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 11:32:31.148084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4728 11:32:31.151496 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4729 11:32:31.154794 Total UI for P1: 0, mck2ui 16
4730 11:32:31.158187 best dqsien dly found for B0: ( 0, 13, 8)
4731 11:32:31.161796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 11:32:31.164939 Total UI for P1: 0, mck2ui 16
4733 11:32:31.168429 best dqsien dly found for B1: ( 0, 13, 12)
4734 11:32:31.171981 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4735 11:32:31.175210 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4736 11:32:31.175301
4737 11:32:31.181366 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4738 11:32:31.184589 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4739 11:32:31.184686 [Gating] SW calibration Done
4740 11:32:31.188290 ==
4741 11:32:31.191487 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:32:31.194611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:32:31.194698 ==
4744 11:32:31.194757 RX Vref Scan: 0
4745 11:32:31.194811
4746 11:32:31.198039 RX Vref 0 -> 0, step: 1
4747 11:32:31.198114
4748 11:32:31.201142 RX Delay -230 -> 252, step: 16
4749 11:32:31.204932 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4750 11:32:31.208020 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4751 11:32:31.214623 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4752 11:32:31.217845 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4753 11:32:31.221506 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4754 11:32:31.224671 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4755 11:32:31.231630 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4756 11:32:31.234827 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4757 11:32:31.237915 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4758 11:32:31.241703 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4759 11:32:31.245845 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4760 11:32:31.251145 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4761 11:32:31.254865 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4762 11:32:31.257951 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4763 11:32:31.260991 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4764 11:32:31.267617 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4765 11:32:31.267690 ==
4766 11:32:31.270880 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 11:32:31.274575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 11:32:31.274650 ==
4769 11:32:31.274708 DQS Delay:
4770 11:32:31.278153 DQS0 = 0, DQS1 = 0
4771 11:32:31.278226 DQM Delay:
4772 11:32:31.281469 DQM0 = 40, DQM1 = 35
4773 11:32:31.281579 DQ Delay:
4774 11:32:31.284612 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4775 11:32:31.287865 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4776 11:32:31.291078 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4777 11:32:31.294346 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4778 11:32:31.294411
4779 11:32:31.294484
4780 11:32:31.294591 ==
4781 11:32:31.297462 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:32:31.301344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:32:31.301420 ==
4784 11:32:31.304229
4785 11:32:31.304327
4786 11:32:31.304405 TX Vref Scan disable
4787 11:32:31.307826 == TX Byte 0 ==
4788 11:32:31.311272 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4789 11:32:31.314753 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4790 11:32:31.318024 == TX Byte 1 ==
4791 11:32:31.321000 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4792 11:32:31.324856 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4793 11:32:31.324947 ==
4794 11:32:31.327847 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 11:32:31.334838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 11:32:31.334905 ==
4797 11:32:31.334963
4798 11:32:31.335015
4799 11:32:31.335066 TX Vref Scan disable
4800 11:32:31.338837 == TX Byte 0 ==
4801 11:32:31.342180 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4802 11:32:31.345505 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4803 11:32:31.348702 == TX Byte 1 ==
4804 11:32:31.352233 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4805 11:32:31.355711 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4806 11:32:31.359025
4807 11:32:31.359114 [DATLAT]
4808 11:32:31.359196 Freq=600, CH1 RK1
4809 11:32:31.359275
4810 11:32:31.362385 DATLAT Default: 0x9
4811 11:32:31.362448 0, 0xFFFF, sum = 0
4812 11:32:31.365614 1, 0xFFFF, sum = 0
4813 11:32:31.365679 2, 0xFFFF, sum = 0
4814 11:32:31.369271 3, 0xFFFF, sum = 0
4815 11:32:31.369338 4, 0xFFFF, sum = 0
4816 11:32:31.371908 5, 0xFFFF, sum = 0
4817 11:32:31.375605 6, 0xFFFF, sum = 0
4818 11:32:31.375673 7, 0xFFFF, sum = 0
4819 11:32:31.375729 8, 0x0, sum = 1
4820 11:32:31.378939 9, 0x0, sum = 2
4821 11:32:31.379004 10, 0x0, sum = 3
4822 11:32:31.382360 11, 0x0, sum = 4
4823 11:32:31.382451 best_step = 9
4824 11:32:31.382530
4825 11:32:31.382606 ==
4826 11:32:31.385282 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 11:32:31.392518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 11:32:31.392611 ==
4829 11:32:31.392695 RX Vref Scan: 0
4830 11:32:31.392773
4831 11:32:31.395384 RX Vref 0 -> 0, step: 1
4832 11:32:31.395470
4833 11:32:31.399175 RX Delay -179 -> 252, step: 8
4834 11:32:31.402002 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4835 11:32:31.409247 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4836 11:32:31.412195 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4837 11:32:31.415534 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4838 11:32:31.418978 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4839 11:32:31.422209 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4840 11:32:31.428705 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4841 11:32:31.431961 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4842 11:32:31.435390 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4843 11:32:31.439186 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4844 11:32:31.441871 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4845 11:32:31.449045 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4846 11:32:31.451988 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4847 11:32:31.455377 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4848 11:32:31.458983 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4849 11:32:31.465261 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4850 11:32:31.465357 ==
4851 11:32:31.469000 Dram Type= 6, Freq= 0, CH_1, rank 1
4852 11:32:31.472166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4853 11:32:31.472279 ==
4854 11:32:31.472341 DQS Delay:
4855 11:32:31.475853 DQS0 = 0, DQS1 = 0
4856 11:32:31.475947 DQM Delay:
4857 11:32:31.478763 DQM0 = 38, DQM1 = 33
4858 11:32:31.478860 DQ Delay:
4859 11:32:31.482466 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4860 11:32:31.485316 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =32
4861 11:32:31.488989 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4862 11:32:31.492312 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4863 11:32:31.492395
4864 11:32:31.492454
4865 11:32:31.501909 [DQSOSCAuto] RK1, (LSB)MR18= 0x3846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4866 11:32:31.502013 CH1 RK1: MR19=808, MR18=3846
4867 11:32:31.508747 CH1_RK1: MR19=0x808, MR18=0x3846, DQSOSC=396, MR23=63, INC=167, DEC=111
4868 11:32:31.512265 [RxdqsGatingPostProcess] freq 600
4869 11:32:31.519063 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4870 11:32:31.522236 Pre-setting of DQS Precalculation
4871 11:32:31.525682 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4872 11:32:31.532126 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4873 11:32:31.538524 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4874 11:32:31.538617
4875 11:32:31.541699
4876 11:32:31.541792 [Calibration Summary] 1200 Mbps
4877 11:32:31.545535 CH 0, Rank 0
4878 11:32:31.545627 SW Impedance : PASS
4879 11:32:31.548996 DUTY Scan : NO K
4880 11:32:31.552001 ZQ Calibration : PASS
4881 11:32:31.552095 Jitter Meter : NO K
4882 11:32:31.555648 CBT Training : PASS
4883 11:32:31.558540 Write leveling : PASS
4884 11:32:31.558632 RX DQS gating : PASS
4885 11:32:31.561875 RX DQ/DQS(RDDQC) : PASS
4886 11:32:31.565224 TX DQ/DQS : PASS
4887 11:32:31.565318 RX DATLAT : PASS
4888 11:32:31.568484 RX DQ/DQS(Engine): PASS
4889 11:32:31.568577 TX OE : NO K
4890 11:32:31.571792 All Pass.
4891 11:32:31.571882
4892 11:32:31.571966 CH 0, Rank 1
4893 11:32:31.575396 SW Impedance : PASS
4894 11:32:31.575488 DUTY Scan : NO K
4895 11:32:31.578600 ZQ Calibration : PASS
4896 11:32:31.582272 Jitter Meter : NO K
4897 11:32:31.582365 CBT Training : PASS
4898 11:32:31.585217 Write leveling : PASS
4899 11:32:31.588599 RX DQS gating : PASS
4900 11:32:31.588693 RX DQ/DQS(RDDQC) : PASS
4901 11:32:31.591646 TX DQ/DQS : PASS
4902 11:32:31.594970 RX DATLAT : PASS
4903 11:32:31.595036 RX DQ/DQS(Engine): PASS
4904 11:32:31.598459 TX OE : NO K
4905 11:32:31.598527 All Pass.
4906 11:32:31.598582
4907 11:32:31.601778 CH 1, Rank 0
4908 11:32:31.601867 SW Impedance : PASS
4909 11:32:31.605259 DUTY Scan : NO K
4910 11:32:31.608555 ZQ Calibration : PASS
4911 11:32:31.608648 Jitter Meter : NO K
4912 11:32:31.611986 CBT Training : PASS
4913 11:32:31.615256 Write leveling : PASS
4914 11:32:31.615348 RX DQS gating : PASS
4915 11:32:31.618796 RX DQ/DQS(RDDQC) : PASS
4916 11:32:31.618885 TX DQ/DQS : PASS
4917 11:32:31.622126 RX DATLAT : PASS
4918 11:32:31.625226 RX DQ/DQS(Engine): PASS
4919 11:32:31.625317 TX OE : NO K
4920 11:32:31.629094 All Pass.
4921 11:32:31.629213
4922 11:32:31.629297 CH 1, Rank 1
4923 11:32:31.632165 SW Impedance : PASS
4924 11:32:31.632254 DUTY Scan : NO K
4925 11:32:31.634944 ZQ Calibration : PASS
4926 11:32:31.638943 Jitter Meter : NO K
4927 11:32:31.639032 CBT Training : PASS
4928 11:32:31.641943 Write leveling : PASS
4929 11:32:31.645396 RX DQS gating : PASS
4930 11:32:31.645487 RX DQ/DQS(RDDQC) : PASS
4931 11:32:31.648492 TX DQ/DQS : PASS
4932 11:32:31.651977 RX DATLAT : PASS
4933 11:32:31.652063 RX DQ/DQS(Engine): PASS
4934 11:32:31.655165 TX OE : NO K
4935 11:32:31.655254 All Pass.
4936 11:32:31.655332
4937 11:32:31.658731 DramC Write-DBI off
4938 11:32:31.661975 PER_BANK_REFRESH: Hybrid Mode
4939 11:32:31.662068 TX_TRACKING: ON
4940 11:32:31.671873 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4941 11:32:31.675443 [FAST_K] Save calibration result to emmc
4942 11:32:31.678481 dramc_set_vcore_voltage set vcore to 662500
4943 11:32:31.678573 Read voltage for 933, 3
4944 11:32:31.682118 Vio18 = 0
4945 11:32:31.682205 Vcore = 662500
4946 11:32:31.682285 Vdram = 0
4947 11:32:31.685592 Vddq = 0
4948 11:32:31.685683 Vmddr = 0
4949 11:32:31.688501 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4950 11:32:31.695508 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4951 11:32:31.698551 MEM_TYPE=3, freq_sel=17
4952 11:32:31.701966 sv_algorithm_assistance_LP4_1600
4953 11:32:31.705350 ============ PULL DRAM RESETB DOWN ============
4954 11:32:31.708646 ========== PULL DRAM RESETB DOWN end =========
4955 11:32:31.715313 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4956 11:32:31.718520 ===================================
4957 11:32:31.718614 LPDDR4 DRAM CONFIGURATION
4958 11:32:31.722330 ===================================
4959 11:32:31.725479 EX_ROW_EN[0] = 0x0
4960 11:32:31.725569 EX_ROW_EN[1] = 0x0
4961 11:32:31.728779 LP4Y_EN = 0x0
4962 11:32:31.728869 WORK_FSP = 0x0
4963 11:32:31.732101 WL = 0x3
4964 11:32:31.734917 RL = 0x3
4965 11:32:31.734985 BL = 0x2
4966 11:32:31.738721 RPST = 0x0
4967 11:32:31.738789 RD_PRE = 0x0
4968 11:32:31.742058 WR_PRE = 0x1
4969 11:32:31.742129 WR_PST = 0x0
4970 11:32:31.745428 DBI_WR = 0x0
4971 11:32:31.745500 DBI_RD = 0x0
4972 11:32:31.748405 OTF = 0x1
4973 11:32:31.752152 ===================================
4974 11:32:31.755476 ===================================
4975 11:32:31.755571 ANA top config
4976 11:32:31.758695 ===================================
4977 11:32:31.762094 DLL_ASYNC_EN = 0
4978 11:32:31.765410 ALL_SLAVE_EN = 1
4979 11:32:31.765479 NEW_RANK_MODE = 1
4980 11:32:31.768723 DLL_IDLE_MODE = 1
4981 11:32:31.771931 LP45_APHY_COMB_EN = 1
4982 11:32:31.775704 TX_ODT_DIS = 1
4983 11:32:31.775771 NEW_8X_MODE = 1
4984 11:32:31.778521 ===================================
4985 11:32:31.781870 ===================================
4986 11:32:31.785674 data_rate = 1866
4987 11:32:31.788982 CKR = 1
4988 11:32:31.791851 DQ_P2S_RATIO = 8
4989 11:32:31.795387 ===================================
4990 11:32:31.798678 CA_P2S_RATIO = 8
4991 11:32:31.801828 DQ_CA_OPEN = 0
4992 11:32:31.801919 DQ_SEMI_OPEN = 0
4993 11:32:31.805402 CA_SEMI_OPEN = 0
4994 11:32:31.808844 CA_FULL_RATE = 0
4995 11:32:31.811870 DQ_CKDIV4_EN = 1
4996 11:32:31.815498 CA_CKDIV4_EN = 1
4997 11:32:31.818501 CA_PREDIV_EN = 0
4998 11:32:31.818591 PH8_DLY = 0
4999 11:32:31.821940 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5000 11:32:31.825412 DQ_AAMCK_DIV = 4
5001 11:32:31.828714 CA_AAMCK_DIV = 4
5002 11:32:31.832488 CA_ADMCK_DIV = 4
5003 11:32:31.832579 DQ_TRACK_CA_EN = 0
5004 11:32:31.835359 CA_PICK = 933
5005 11:32:31.838871 CA_MCKIO = 933
5006 11:32:31.841831 MCKIO_SEMI = 0
5007 11:32:31.845133 PLL_FREQ = 3732
5008 11:32:31.848405 DQ_UI_PI_RATIO = 32
5009 11:32:31.851784 CA_UI_PI_RATIO = 0
5010 11:32:31.855521 ===================================
5011 11:32:31.858472 ===================================
5012 11:32:31.858563 memory_type:LPDDR4
5013 11:32:31.861892 GP_NUM : 10
5014 11:32:31.865389 SRAM_EN : 1
5015 11:32:31.865456 MD32_EN : 0
5016 11:32:31.868867 ===================================
5017 11:32:31.871930 [ANA_INIT] >>>>>>>>>>>>>>
5018 11:32:31.875608 <<<<<< [CONFIGURE PHASE]: ANA_TX
5019 11:32:31.878672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5020 11:32:31.881866 ===================================
5021 11:32:31.885283 data_rate = 1866,PCW = 0X8f00
5022 11:32:31.889056 ===================================
5023 11:32:31.891906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5024 11:32:31.895163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5025 11:32:31.901762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5026 11:32:31.905668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5027 11:32:31.908566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5028 11:32:31.911976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5029 11:32:31.915447 [ANA_INIT] flow start
5030 11:32:31.918852 [ANA_INIT] PLL >>>>>>>>
5031 11:32:31.918943 [ANA_INIT] PLL <<<<<<<<
5032 11:32:31.922151 [ANA_INIT] MIDPI >>>>>>>>
5033 11:32:31.925601 [ANA_INIT] MIDPI <<<<<<<<
5034 11:32:31.925690 [ANA_INIT] DLL >>>>>>>>
5035 11:32:31.928614 [ANA_INIT] flow end
5036 11:32:31.932141 ============ LP4 DIFF to SE enter ============
5037 11:32:31.935602 ============ LP4 DIFF to SE exit ============
5038 11:32:31.938824 [ANA_INIT] <<<<<<<<<<<<<
5039 11:32:31.942000 [Flow] Enable top DCM control >>>>>
5040 11:32:31.945587 [Flow] Enable top DCM control <<<<<
5041 11:32:31.949094 Enable DLL master slave shuffle
5042 11:32:31.955704 ==============================================================
5043 11:32:31.955800 Gating Mode config
5044 11:32:31.962548 ==============================================================
5045 11:32:31.962643 Config description:
5046 11:32:31.972132 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5047 11:32:31.978753 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5048 11:32:31.985378 SELPH_MODE 0: By rank 1: By Phase
5049 11:32:31.988742 ==============================================================
5050 11:32:31.992144 GAT_TRACK_EN = 1
5051 11:32:31.995479 RX_GATING_MODE = 2
5052 11:32:31.999127 RX_GATING_TRACK_MODE = 2
5053 11:32:32.002438 SELPH_MODE = 1
5054 11:32:32.006056 PICG_EARLY_EN = 1
5055 11:32:32.009001 VALID_LAT_VALUE = 1
5056 11:32:32.012273 ==============================================================
5057 11:32:32.015680 Enter into Gating configuration >>>>
5058 11:32:32.019236 Exit from Gating configuration <<<<
5059 11:32:32.022431 Enter into DVFS_PRE_config >>>>>
5060 11:32:32.035509 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5061 11:32:32.038844 Exit from DVFS_PRE_config <<<<<
5062 11:32:32.042078 Enter into PICG configuration >>>>
5063 11:32:32.045558 Exit from PICG configuration <<<<
5064 11:32:32.045652 [RX_INPUT] configuration >>>>>
5065 11:32:32.048717 [RX_INPUT] configuration <<<<<
5066 11:32:32.056184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5067 11:32:32.059147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5068 11:32:32.065832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5069 11:32:32.072562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5070 11:32:32.078859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5071 11:32:32.085505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5072 11:32:32.089043 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5073 11:32:32.092355 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5074 11:32:32.095622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5075 11:32:32.102204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5076 11:32:32.105901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5077 11:32:32.109322 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 11:32:32.112399 ===================================
5079 11:32:32.115598 LPDDR4 DRAM CONFIGURATION
5080 11:32:32.118825 ===================================
5081 11:32:32.122266 EX_ROW_EN[0] = 0x0
5082 11:32:32.122356 EX_ROW_EN[1] = 0x0
5083 11:32:32.125806 LP4Y_EN = 0x0
5084 11:32:32.125874 WORK_FSP = 0x0
5085 11:32:32.129086 WL = 0x3
5086 11:32:32.129199 RL = 0x3
5087 11:32:32.132431 BL = 0x2
5088 11:32:32.132522 RPST = 0x0
5089 11:32:32.135631 RD_PRE = 0x0
5090 11:32:32.135721 WR_PRE = 0x1
5091 11:32:32.138603 WR_PST = 0x0
5092 11:32:32.138694 DBI_WR = 0x0
5093 11:32:32.141868 DBI_RD = 0x0
5094 11:32:32.141959 OTF = 0x1
5095 11:32:32.145554 ===================================
5096 11:32:32.149235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5097 11:32:32.155231 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5098 11:32:32.158838 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5099 11:32:32.162088 ===================================
5100 11:32:32.165507 LPDDR4 DRAM CONFIGURATION
5101 11:32:32.168720 ===================================
5102 11:32:32.168816 EX_ROW_EN[0] = 0x10
5103 11:32:32.171827 EX_ROW_EN[1] = 0x0
5104 11:32:32.175580 LP4Y_EN = 0x0
5105 11:32:32.175672 WORK_FSP = 0x0
5106 11:32:32.179384 WL = 0x3
5107 11:32:32.179471 RL = 0x3
5108 11:32:32.182057 BL = 0x2
5109 11:32:32.182142 RPST = 0x0
5110 11:32:32.185339 RD_PRE = 0x0
5111 11:32:32.185429 WR_PRE = 0x1
5112 11:32:32.188565 WR_PST = 0x0
5113 11:32:32.188655 DBI_WR = 0x0
5114 11:32:32.191812 DBI_RD = 0x0
5115 11:32:32.191903 OTF = 0x1
5116 11:32:32.195458 ===================================
5117 11:32:32.201606 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5118 11:32:32.206225 nWR fixed to 30
5119 11:32:32.209091 [ModeRegInit_LP4] CH0 RK0
5120 11:32:32.209206 [ModeRegInit_LP4] CH0 RK1
5121 11:32:32.212980 [ModeRegInit_LP4] CH1 RK0
5122 11:32:32.216352 [ModeRegInit_LP4] CH1 RK1
5123 11:32:32.216442 match AC timing 9
5124 11:32:32.222709 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5125 11:32:32.226039 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5126 11:32:32.229101 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5127 11:32:32.235962 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5128 11:32:32.239496 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5129 11:32:32.239590 ==
5130 11:32:32.242846 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 11:32:32.245904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 11:32:32.245972 ==
5133 11:32:32.252731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 11:32:32.259466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5135 11:32:32.262719 [CA 0] Center 38 (8~69) winsize 62
5136 11:32:32.265871 [CA 1] Center 38 (7~69) winsize 63
5137 11:32:32.269513 [CA 2] Center 35 (5~66) winsize 62
5138 11:32:32.272933 [CA 3] Center 35 (5~66) winsize 62
5139 11:32:32.276280 [CA 4] Center 34 (4~65) winsize 62
5140 11:32:32.279760 [CA 5] Center 34 (4~64) winsize 61
5141 11:32:32.279850
5142 11:32:32.282999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5143 11:32:32.283092
5144 11:32:32.286284 [CATrainingPosCal] consider 1 rank data
5145 11:32:32.289515 u2DelayCellTimex100 = 270/100 ps
5146 11:32:32.293240 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5147 11:32:32.296104 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5148 11:32:32.299555 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5149 11:32:32.302892 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5150 11:32:32.306138 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5151 11:32:32.310067 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 11:32:32.310136
5153 11:32:32.312723 CA PerBit enable=1, Macro0, CA PI delay=34
5154 11:32:32.316517
5155 11:32:32.316605 [CBTSetCACLKResult] CA Dly = 34
5156 11:32:32.319939 CS Dly: 6 (0~37)
5157 11:32:32.320027 ==
5158 11:32:32.322861 Dram Type= 6, Freq= 0, CH_0, rank 1
5159 11:32:32.326425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 11:32:32.326515 ==
5161 11:32:32.332921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 11:32:32.339419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5163 11:32:32.342714 [CA 0] Center 38 (7~69) winsize 63
5164 11:32:32.346740 [CA 1] Center 38 (7~69) winsize 63
5165 11:32:32.349950 [CA 2] Center 35 (5~66) winsize 62
5166 11:32:32.353035 [CA 3] Center 35 (4~66) winsize 63
5167 11:32:32.356555 [CA 4] Center 33 (3~64) winsize 62
5168 11:32:32.359533 [CA 5] Center 33 (3~64) winsize 62
5169 11:32:32.359629
5170 11:32:32.362916 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5171 11:32:32.362991
5172 11:32:32.366251 [CATrainingPosCal] consider 2 rank data
5173 11:32:32.369777 u2DelayCellTimex100 = 270/100 ps
5174 11:32:32.373061 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5175 11:32:32.376256 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5176 11:32:32.379474 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5177 11:32:32.382799 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5178 11:32:32.386114 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5179 11:32:32.389467 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5180 11:32:32.389545
5181 11:32:32.393008 CA PerBit enable=1, Macro0, CA PI delay=34
5182 11:32:32.393103
5183 11:32:32.396781 [CBTSetCACLKResult] CA Dly = 34
5184 11:32:32.400176 CS Dly: 7 (0~39)
5185 11:32:32.400266
5186 11:32:32.403405 ----->DramcWriteLeveling(PI) begin...
5187 11:32:32.403498 ==
5188 11:32:32.406554 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 11:32:32.410078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 11:32:32.410149 ==
5191 11:32:32.412995 Write leveling (Byte 0): 29 => 29
5192 11:32:32.416413 Write leveling (Byte 1): 29 => 29
5193 11:32:32.419754 DramcWriteLeveling(PI) end<-----
5194 11:32:32.419846
5195 11:32:32.419927 ==
5196 11:32:32.423277 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 11:32:32.426710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 11:32:32.426800 ==
5199 11:32:32.429950 [Gating] SW mode calibration
5200 11:32:32.436594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5201 11:32:32.443345 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5202 11:32:32.446407 0 14 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5203 11:32:32.452871 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5204 11:32:32.456648 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 11:32:32.459792 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 11:32:32.462718 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 11:32:32.469705 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 11:32:32.472804 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 11:32:32.476246 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5210 11:32:32.482880 0 15 0 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
5211 11:32:32.486373 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 11:32:32.489796 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 11:32:32.496264 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 11:32:32.499542 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 11:32:32.502806 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 11:32:32.509935 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 11:32:32.512991 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5218 11:32:32.516095 1 0 0 | B1->B0 | 3231 3a3a | 1 0 | (0 0) (0 0)
5219 11:32:32.523100 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5220 11:32:32.526341 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 11:32:32.529705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 11:32:32.536321 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:32:32.539738 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 11:32:32.543239 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 11:32:32.549630 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5226 11:32:32.553023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5227 11:32:32.556158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5228 11:32:32.559765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:32:32.566436 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 11:32:32.569741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 11:32:32.573082 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 11:32:32.579851 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 11:32:32.583065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 11:32:32.587089 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 11:32:32.592761 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 11:32:32.596127 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 11:32:32.599667 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 11:32:32.606128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 11:32:32.609790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 11:32:32.612734 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 11:32:32.619260 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5242 11:32:32.623057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5243 11:32:32.625963 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 11:32:32.629530 Total UI for P1: 0, mck2ui 16
5245 11:32:32.632858 best dqsien dly found for B0: ( 1, 2, 30)
5246 11:32:32.636073 Total UI for P1: 0, mck2ui 16
5247 11:32:32.639390 best dqsien dly found for B1: ( 1, 3, 0)
5248 11:32:32.642704 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5249 11:32:32.646354 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5250 11:32:32.646446
5251 11:32:32.649549 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5252 11:32:32.656766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5253 11:32:32.656861 [Gating] SW calibration Done
5254 11:32:32.656945 ==
5255 11:32:32.659430 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 11:32:32.666203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 11:32:32.666300 ==
5258 11:32:32.666391 RX Vref Scan: 0
5259 11:32:32.666474
5260 11:32:32.669465 RX Vref 0 -> 0, step: 1
5261 11:32:32.669549
5262 11:32:32.672853 RX Delay -80 -> 252, step: 8
5263 11:32:32.676275 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5264 11:32:32.679443 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5265 11:32:32.683349 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5266 11:32:32.686299 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5267 11:32:32.689450 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5268 11:32:32.696180 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5269 11:32:32.699672 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5270 11:32:32.703009 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5271 11:32:32.706268 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5272 11:32:32.710099 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5273 11:32:32.713524 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5274 11:32:32.719590 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5275 11:32:32.723024 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5276 11:32:32.726509 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5277 11:32:32.729804 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5278 11:32:32.733038 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5279 11:32:32.733155 ==
5280 11:32:32.736400 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 11:32:32.742901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 11:32:32.742972 ==
5283 11:32:32.743030 DQS Delay:
5284 11:32:32.746642 DQS0 = 0, DQS1 = 0
5285 11:32:32.746709 DQM Delay:
5286 11:32:32.746765 DQM0 = 97, DQM1 = 87
5287 11:32:32.750054 DQ Delay:
5288 11:32:32.753196 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5289 11:32:32.756806 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5290 11:32:32.759580 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5291 11:32:32.763098 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5292 11:32:32.763175
5293 11:32:32.763233
5294 11:32:32.763287 ==
5295 11:32:32.766354 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 11:32:32.770232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 11:32:32.770308 ==
5298 11:32:32.770367
5299 11:32:32.770421
5300 11:32:32.773311 TX Vref Scan disable
5301 11:32:32.773386 == TX Byte 0 ==
5302 11:32:32.780008 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5303 11:32:32.783163 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5304 11:32:32.783239 == TX Byte 1 ==
5305 11:32:32.790261 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5306 11:32:32.793556 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5307 11:32:32.793632 ==
5308 11:32:32.796837 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 11:32:32.800392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 11:32:32.800468 ==
5311 11:32:32.800527
5312 11:32:32.803476
5313 11:32:32.803551 TX Vref Scan disable
5314 11:32:32.806608 == TX Byte 0 ==
5315 11:32:32.809771 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5316 11:32:32.813173 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5317 11:32:32.816389 == TX Byte 1 ==
5318 11:32:32.819967 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5319 11:32:32.823085 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5320 11:32:32.823161
5321 11:32:32.826469 [DATLAT]
5322 11:32:32.826544 Freq=933, CH0 RK0
5323 11:32:32.826602
5324 11:32:32.830110 DATLAT Default: 0xd
5325 11:32:32.830185 0, 0xFFFF, sum = 0
5326 11:32:32.833549 1, 0xFFFF, sum = 0
5327 11:32:32.833625 2, 0xFFFF, sum = 0
5328 11:32:32.836500 3, 0xFFFF, sum = 0
5329 11:32:32.836619 4, 0xFFFF, sum = 0
5330 11:32:32.840150 5, 0xFFFF, sum = 0
5331 11:32:32.840244 6, 0xFFFF, sum = 0
5332 11:32:32.843483 7, 0xFFFF, sum = 0
5333 11:32:32.843575 8, 0xFFFF, sum = 0
5334 11:32:32.846633 9, 0xFFFF, sum = 0
5335 11:32:32.846703 10, 0x0, sum = 1
5336 11:32:32.850114 11, 0x0, sum = 2
5337 11:32:32.850210 12, 0x0, sum = 3
5338 11:32:32.853315 13, 0x0, sum = 4
5339 11:32:32.853409 best_step = 11
5340 11:32:32.853492
5341 11:32:32.853561 ==
5342 11:32:32.856821 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 11:32:32.863960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 11:32:32.864055 ==
5345 11:32:32.864138 RX Vref Scan: 1
5346 11:32:32.864208
5347 11:32:32.866975 RX Vref 0 -> 0, step: 1
5348 11:32:32.867066
5349 11:32:32.870288 RX Delay -61 -> 252, step: 4
5350 11:32:32.870376
5351 11:32:32.873566 Set Vref, RX VrefLevel [Byte0]: 53
5352 11:32:32.876622 [Byte1]: 53
5353 11:32:32.876724
5354 11:32:32.880476 Final RX Vref Byte 0 = 53 to rank0
5355 11:32:32.883480 Final RX Vref Byte 1 = 53 to rank0
5356 11:32:32.886850 Final RX Vref Byte 0 = 53 to rank1
5357 11:32:32.890354 Final RX Vref Byte 1 = 53 to rank1==
5358 11:32:32.893795 Dram Type= 6, Freq= 0, CH_0, rank 0
5359 11:32:32.896933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 11:32:32.897025 ==
5361 11:32:32.900189 DQS Delay:
5362 11:32:32.900281 DQS0 = 0, DQS1 = 0
5363 11:32:32.900363 DQM Delay:
5364 11:32:32.903622 DQM0 = 96, DQM1 = 88
5365 11:32:32.903712 DQ Delay:
5366 11:32:32.906800 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5367 11:32:32.910313 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5368 11:32:32.913343 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =84
5369 11:32:32.916548 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98
5370 11:32:32.916639
5371 11:32:32.916723
5372 11:32:32.926928 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5373 11:32:32.930422 CH0 RK0: MR19=504, MR18=14FF
5374 11:32:32.933574 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5375 11:32:32.933649
5376 11:32:32.936307 ----->DramcWriteLeveling(PI) begin...
5377 11:32:32.940368 ==
5378 11:32:32.943104 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 11:32:32.946341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 11:32:32.946417 ==
5381 11:32:32.949595 Write leveling (Byte 0): 29 => 29
5382 11:32:32.953128 Write leveling (Byte 1): 28 => 28
5383 11:32:32.956659 DramcWriteLeveling(PI) end<-----
5384 11:32:32.956733
5385 11:32:32.956790 ==
5386 11:32:32.960542 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 11:32:32.963244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 11:32:32.963320 ==
5389 11:32:32.966615 [Gating] SW mode calibration
5390 11:32:32.973366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5391 11:32:32.976588 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5392 11:32:32.983146 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5393 11:32:32.986795 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 11:32:32.989936 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 11:32:32.996285 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 11:32:32.999850 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 11:32:33.002845 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 11:32:33.009740 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5399 11:32:33.013081 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5400 11:32:33.016549 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5401 11:32:33.023167 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5402 11:32:33.026378 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 11:32:33.030470 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 11:32:33.036544 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 11:32:33.039840 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 11:32:33.043354 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 11:32:33.049959 0 15 28 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (0 0)
5408 11:32:33.052987 1 0 0 | B1->B0 | 3535 4646 | 1 0 | (1 1) (0 0)
5409 11:32:33.056557 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 11:32:33.063033 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 11:32:33.066407 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 11:32:33.069688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 11:32:33.073257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 11:32:33.079848 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5415 11:32:33.083037 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5416 11:32:33.086763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5417 11:32:33.093310 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:32:33.096548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:32:33.099844 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 11:32:33.106521 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 11:32:33.110558 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 11:32:33.113290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 11:32:33.120097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 11:32:33.123417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 11:32:33.126338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 11:32:33.133454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 11:32:33.136512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:32:33.139919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 11:32:33.146832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:32:33.150141 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5431 11:32:33.153497 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5432 11:32:33.156581 Total UI for P1: 0, mck2ui 16
5433 11:32:33.159716 best dqsien dly found for B0: ( 1, 2, 24)
5434 11:32:33.163421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5435 11:32:33.169628 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5436 11:32:33.173018 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 11:32:33.176409 Total UI for P1: 0, mck2ui 16
5438 11:32:33.179723 best dqsien dly found for B1: ( 1, 3, 0)
5439 11:32:33.182995 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5440 11:32:33.186683 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5441 11:32:33.186754
5442 11:32:33.190252 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5443 11:32:33.193306 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5444 11:32:33.196757 [Gating] SW calibration Done
5445 11:32:33.196832 ==
5446 11:32:33.199960 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:32:33.206766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:32:33.206842 ==
5449 11:32:33.206901 RX Vref Scan: 0
5450 11:32:33.206955
5451 11:32:33.210014 RX Vref 0 -> 0, step: 1
5452 11:32:33.210089
5453 11:32:33.213317 RX Delay -80 -> 252, step: 8
5454 11:32:33.216416 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5455 11:32:33.219708 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5456 11:32:33.223190 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5457 11:32:33.226335 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5458 11:32:33.229976 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5459 11:32:33.236442 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5460 11:32:33.239972 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5461 11:32:33.243801 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5462 11:32:33.247025 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5463 11:32:33.250106 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5464 11:32:33.253267 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5465 11:32:33.259670 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5466 11:32:33.263380 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5467 11:32:33.266544 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5468 11:32:33.269857 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5469 11:32:33.273374 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5470 11:32:33.273450 ==
5471 11:32:33.276878 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 11:32:33.283555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 11:32:33.283631 ==
5474 11:32:33.283690 DQS Delay:
5475 11:32:33.286549 DQS0 = 0, DQS1 = 0
5476 11:32:33.286625 DQM Delay:
5477 11:32:33.286684 DQM0 = 95, DQM1 = 86
5478 11:32:33.289951 DQ Delay:
5479 11:32:33.293556 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5480 11:32:33.297084 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5481 11:32:33.300325 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5482 11:32:33.303471 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5483 11:32:33.303546
5484 11:32:33.303604
5485 11:32:33.303659 ==
5486 11:32:33.307404 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 11:32:33.310209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:32:33.310286 ==
5489 11:32:33.310345
5490 11:32:33.310398
5491 11:32:33.312972 TX Vref Scan disable
5492 11:32:33.316792 == TX Byte 0 ==
5493 11:32:33.319859 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5494 11:32:33.324005 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5495 11:32:33.326702 == TX Byte 1 ==
5496 11:32:33.329789 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5497 11:32:33.333441 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5498 11:32:33.333517 ==
5499 11:32:33.336912 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 11:32:33.339792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 11:32:33.339868 ==
5502 11:32:33.339926
5503 11:32:33.342957
5504 11:32:33.343057 TX Vref Scan disable
5505 11:32:33.346576 == TX Byte 0 ==
5506 11:32:33.350177 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5507 11:32:33.353470 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5508 11:32:33.356479 == TX Byte 1 ==
5509 11:32:33.360015 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5510 11:32:33.363151 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5511 11:32:33.366540
5512 11:32:33.366639 [DATLAT]
5513 11:32:33.366723 Freq=933, CH0 RK1
5514 11:32:33.366802
5515 11:32:33.369957 DATLAT Default: 0xb
5516 11:32:33.370031 0, 0xFFFF, sum = 0
5517 11:32:33.373096 1, 0xFFFF, sum = 0
5518 11:32:33.373199 2, 0xFFFF, sum = 0
5519 11:32:33.376672 3, 0xFFFF, sum = 0
5520 11:32:33.376749 4, 0xFFFF, sum = 0
5521 11:32:33.379700 5, 0xFFFF, sum = 0
5522 11:32:33.379777 6, 0xFFFF, sum = 0
5523 11:32:33.382988 7, 0xFFFF, sum = 0
5524 11:32:33.383065 8, 0xFFFF, sum = 0
5525 11:32:33.386854 9, 0xFFFF, sum = 0
5526 11:32:33.386934 10, 0x0, sum = 1
5527 11:32:33.390188 11, 0x0, sum = 2
5528 11:32:33.390264 12, 0x0, sum = 3
5529 11:32:33.393380 13, 0x0, sum = 4
5530 11:32:33.393456 best_step = 11
5531 11:32:33.393514
5532 11:32:33.393569 ==
5533 11:32:33.396829 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 11:32:33.403437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 11:32:33.403513 ==
5536 11:32:33.403571 RX Vref Scan: 0
5537 11:32:33.403625
5538 11:32:33.406661 RX Vref 0 -> 0, step: 1
5539 11:32:33.406737
5540 11:32:33.409958 RX Delay -61 -> 252, step: 4
5541 11:32:33.413261 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5542 11:32:33.416814 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5543 11:32:33.423295 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5544 11:32:33.426584 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5545 11:32:33.430069 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5546 11:32:33.433285 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5547 11:32:33.436465 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5548 11:32:33.439948 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5549 11:32:33.446226 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5550 11:32:33.449792 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5551 11:32:33.453255 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5552 11:32:33.456290 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5553 11:32:33.459640 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5554 11:32:33.466327 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5555 11:32:33.469522 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5556 11:32:33.472865 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5557 11:32:33.472946 ==
5558 11:32:33.476285 Dram Type= 6, Freq= 0, CH_0, rank 1
5559 11:32:33.479738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 11:32:33.479815 ==
5561 11:32:33.483024 DQS Delay:
5562 11:32:33.483099 DQS0 = 0, DQS1 = 0
5563 11:32:33.483157 DQM Delay:
5564 11:32:33.486207 DQM0 = 95, DQM1 = 87
5565 11:32:33.486282 DQ Delay:
5566 11:32:33.489750 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5567 11:32:33.492947 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5568 11:32:33.496223 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5569 11:32:33.499616 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =92
5570 11:32:33.499706
5571 11:32:33.499764
5572 11:32:33.509706 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5573 11:32:33.509785 CH0 RK1: MR19=505, MR18=1B08
5574 11:32:33.516386 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5575 11:32:33.519823 [RxdqsGatingPostProcess] freq 933
5576 11:32:33.526534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5577 11:32:33.529853 best DQS0 dly(2T, 0.5T) = (0, 10)
5578 11:32:33.533454 best DQS1 dly(2T, 0.5T) = (0, 11)
5579 11:32:33.536905 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5580 11:32:33.539805 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5581 11:32:33.543270 best DQS0 dly(2T, 0.5T) = (0, 10)
5582 11:32:33.543370 best DQS1 dly(2T, 0.5T) = (0, 11)
5583 11:32:33.546542 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5584 11:32:33.549882 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5585 11:32:33.553238 Pre-setting of DQS Precalculation
5586 11:32:33.560054 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5587 11:32:33.560130 ==
5588 11:32:33.563230 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 11:32:33.566652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 11:32:33.566729 ==
5591 11:32:33.573263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 11:32:33.579980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5593 11:32:33.582919 [CA 0] Center 36 (6~67) winsize 62
5594 11:32:33.586237 [CA 1] Center 36 (6~67) winsize 62
5595 11:32:33.589942 [CA 2] Center 33 (3~64) winsize 62
5596 11:32:33.593025 [CA 3] Center 33 (3~64) winsize 62
5597 11:32:33.596865 [CA 4] Center 33 (3~64) winsize 62
5598 11:32:33.596941 [CA 5] Center 33 (3~64) winsize 62
5599 11:32:33.599590
5600 11:32:33.602935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5601 11:32:33.603010
5602 11:32:33.606519 [CATrainingPosCal] consider 1 rank data
5603 11:32:33.609919 u2DelayCellTimex100 = 270/100 ps
5604 11:32:33.613417 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5605 11:32:33.616718 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 11:32:33.619760 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5607 11:32:33.623214 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 11:32:33.626648 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5609 11:32:33.629619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 11:32:33.629695
5611 11:32:33.633151 CA PerBit enable=1, Macro0, CA PI delay=33
5612 11:32:33.633268
5613 11:32:33.636760 [CBTSetCACLKResult] CA Dly = 33
5614 11:32:33.639633 CS Dly: 4 (0~35)
5615 11:32:33.639708 ==
5616 11:32:33.643310 Dram Type= 6, Freq= 0, CH_1, rank 1
5617 11:32:33.646359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:32:33.646435 ==
5619 11:32:33.653130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5620 11:32:33.660637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5621 11:32:33.663259 [CA 0] Center 36 (6~67) winsize 62
5622 11:32:33.667265 [CA 1] Center 37 (7~67) winsize 61
5623 11:32:33.669983 [CA 2] Center 33 (3~64) winsize 62
5624 11:32:33.673229 [CA 3] Center 33 (3~64) winsize 62
5625 11:32:33.676483 [CA 4] Center 34 (4~65) winsize 62
5626 11:32:33.676550 [CA 5] Center 32 (2~63) winsize 62
5627 11:32:33.676606
5628 11:32:33.683477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5629 11:32:33.683544
5630 11:32:33.686926 [CATrainingPosCal] consider 2 rank data
5631 11:32:33.689778 u2DelayCellTimex100 = 270/100 ps
5632 11:32:33.693437 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5633 11:32:33.696675 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5634 11:32:33.699775 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5635 11:32:33.703326 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5636 11:32:33.706759 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5637 11:32:33.710081 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5638 11:32:33.710158
5639 11:32:33.713389 CA PerBit enable=1, Macro0, CA PI delay=33
5640 11:32:33.713465
5641 11:32:33.716394 [CBTSetCACLKResult] CA Dly = 33
5642 11:32:33.719811 CS Dly: 5 (0~38)
5643 11:32:33.719887
5644 11:32:33.723080 ----->DramcWriteLeveling(PI) begin...
5645 11:32:33.723157 ==
5646 11:32:33.726419 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 11:32:33.730664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 11:32:33.730741 ==
5649 11:32:33.733742 Write leveling (Byte 0): 24 => 24
5650 11:32:33.736841 Write leveling (Byte 1): 26 => 26
5651 11:32:33.740327 DramcWriteLeveling(PI) end<-----
5652 11:32:33.740406
5653 11:32:33.740482 ==
5654 11:32:33.743565 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 11:32:33.746903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 11:32:33.746981 ==
5657 11:32:33.750178 [Gating] SW mode calibration
5658 11:32:33.756956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5659 11:32:33.763318 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5660 11:32:33.766433 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5661 11:32:33.770023 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 11:32:33.776918 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 11:32:33.780055 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 11:32:33.783205 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 11:32:33.790413 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 11:32:33.793439 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5667 11:32:33.797222 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5668 11:32:33.803445 0 15 0 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5669 11:32:33.807082 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 11:32:33.810611 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 11:32:33.817284 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 11:32:33.819958 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 11:32:33.823849 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 11:32:33.830068 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 11:32:33.833971 0 15 28 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
5676 11:32:33.836857 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5677 11:32:33.840151 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 11:32:33.847203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 11:32:33.850259 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 11:32:33.853391 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 11:32:33.859860 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 11:32:33.863122 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 11:32:33.866886 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5684 11:32:33.873742 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5685 11:32:33.876700 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 11:32:33.880122 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 11:32:33.886648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 11:32:33.890052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 11:32:33.893539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 11:32:33.900128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 11:32:33.903613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 11:32:33.906923 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 11:32:33.913673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 11:32:33.917445 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 11:32:33.920250 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 11:32:33.923849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 11:32:33.930154 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:32:33.934061 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:32:33.936847 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5700 11:32:33.943570 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 11:32:33.947037 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 11:32:33.950563 Total UI for P1: 0, mck2ui 16
5703 11:32:33.953737 best dqsien dly found for B0: ( 1, 2, 30)
5704 11:32:33.957037 Total UI for P1: 0, mck2ui 16
5705 11:32:33.960235 best dqsien dly found for B1: ( 1, 2, 30)
5706 11:32:33.963708 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5707 11:32:33.966793 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5708 11:32:33.966869
5709 11:32:33.970582 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5710 11:32:33.973689 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5711 11:32:33.976777 [Gating] SW calibration Done
5712 11:32:33.976845 ==
5713 11:32:33.980215 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 11:32:33.984123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:32:33.987237 ==
5716 11:32:33.987304 RX Vref Scan: 0
5717 11:32:33.987358
5718 11:32:33.990435 RX Vref 0 -> 0, step: 1
5719 11:32:33.990496
5720 11:32:33.990552 RX Delay -80 -> 252, step: 8
5721 11:32:33.997438 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5722 11:32:34.000560 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5723 11:32:34.003790 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5724 11:32:34.007345 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5725 11:32:34.011157 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5726 11:32:34.014678 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5727 11:32:34.020491 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5728 11:32:34.023808 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5729 11:32:34.027138 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5730 11:32:34.030349 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5731 11:32:34.033776 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5732 11:32:34.040766 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5733 11:32:34.043753 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5734 11:32:34.047851 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5735 11:32:34.050730 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5736 11:32:34.054395 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5737 11:32:34.054461 ==
5738 11:32:34.057148 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 11:32:34.060665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 11:32:34.064018 ==
5741 11:32:34.064108 DQS Delay:
5742 11:32:34.064168 DQS0 = 0, DQS1 = 0
5743 11:32:34.067356 DQM Delay:
5744 11:32:34.067431 DQM0 = 95, DQM1 = 89
5745 11:32:34.070602 DQ Delay:
5746 11:32:34.070677 DQ0 =99, DQ1 =95, DQ2 =79, DQ3 =95
5747 11:32:34.073929 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5748 11:32:34.077101 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5749 11:32:34.081035 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5750 11:32:34.083817
5751 11:32:34.083884
5752 11:32:34.083940 ==
5753 11:32:34.087707 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 11:32:34.090934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 11:32:34.091050 ==
5756 11:32:34.091109
5757 11:32:34.091163
5758 11:32:34.094332 TX Vref Scan disable
5759 11:32:34.094407 == TX Byte 0 ==
5760 11:32:34.100669 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5761 11:32:34.104486 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5762 11:32:34.104564 == TX Byte 1 ==
5763 11:32:34.110889 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5764 11:32:34.114298 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5765 11:32:34.114405 ==
5766 11:32:34.117474 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 11:32:34.120693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:32:34.120801 ==
5769 11:32:34.120920
5770 11:32:34.121004
5771 11:32:34.123967 TX Vref Scan disable
5772 11:32:34.127647 == TX Byte 0 ==
5773 11:32:34.130522 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5774 11:32:34.133989 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5775 11:32:34.137107 == TX Byte 1 ==
5776 11:32:34.140574 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5777 11:32:34.143917 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5778 11:32:34.143992
5779 11:32:34.147241 [DATLAT]
5780 11:32:34.147315 Freq=933, CH1 RK0
5781 11:32:34.147374
5782 11:32:34.150691 DATLAT Default: 0xd
5783 11:32:34.150802 0, 0xFFFF, sum = 0
5784 11:32:34.154240 1, 0xFFFF, sum = 0
5785 11:32:34.154305 2, 0xFFFF, sum = 0
5786 11:32:34.157858 3, 0xFFFF, sum = 0
5787 11:32:34.157930 4, 0xFFFF, sum = 0
5788 11:32:34.160703 5, 0xFFFF, sum = 0
5789 11:32:34.160791 6, 0xFFFF, sum = 0
5790 11:32:34.164085 7, 0xFFFF, sum = 0
5791 11:32:34.164221 8, 0xFFFF, sum = 0
5792 11:32:34.167510 9, 0xFFFF, sum = 0
5793 11:32:34.167607 10, 0x0, sum = 1
5794 11:32:34.170759 11, 0x0, sum = 2
5795 11:32:34.170825 12, 0x0, sum = 3
5796 11:32:34.174106 13, 0x0, sum = 4
5797 11:32:34.174174 best_step = 11
5798 11:32:34.174230
5799 11:32:34.174321 ==
5800 11:32:34.177299 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 11:32:34.180878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 11:32:34.184234 ==
5803 11:32:34.184324 RX Vref Scan: 1
5804 11:32:34.184406
5805 11:32:34.187141 RX Vref 0 -> 0, step: 1
5806 11:32:34.187228
5807 11:32:34.190981 RX Delay -61 -> 252, step: 4
5808 11:32:34.191074
5809 11:32:34.191160 Set Vref, RX VrefLevel [Byte0]: 62
5810 11:32:34.193920 [Byte1]: 51
5811 11:32:34.199006
5812 11:32:34.199102 Final RX Vref Byte 0 = 62 to rank0
5813 11:32:34.202423 Final RX Vref Byte 1 = 51 to rank0
5814 11:32:34.205578 Final RX Vref Byte 0 = 62 to rank1
5815 11:32:34.209427 Final RX Vref Byte 1 = 51 to rank1==
5816 11:32:34.212318 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 11:32:34.215944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 11:32:34.218928 ==
5819 11:32:34.219018 DQS Delay:
5820 11:32:34.219103 DQS0 = 0, DQS1 = 0
5821 11:32:34.222410 DQM Delay:
5822 11:32:34.222496 DQM0 = 98, DQM1 = 89
5823 11:32:34.225877 DQ Delay:
5824 11:32:34.229577 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5825 11:32:34.232349 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
5826 11:32:34.232437 DQ8 =78, DQ9 =76, DQ10 =94, DQ11 =84
5827 11:32:34.239366 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5828 11:32:34.239457
5829 11:32:34.239539
5830 11:32:34.246199 [DQSOSCAuto] RK0, (LSB)MR18= 0x1cf9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 412 ps
5831 11:32:34.249431 CH1 RK0: MR19=504, MR18=1CF9
5832 11:32:34.255907 CH1_RK0: MR19=0x504, MR18=0x1CF9, DQSOSC=412, MR23=63, INC=63, DEC=42
5833 11:32:34.255997
5834 11:32:34.259165 ----->DramcWriteLeveling(PI) begin...
5835 11:32:34.259262 ==
5836 11:32:34.262428 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 11:32:34.266442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 11:32:34.266536 ==
5839 11:32:34.269330 Write leveling (Byte 0): 27 => 27
5840 11:32:34.272673 Write leveling (Byte 1): 28 => 28
5841 11:32:34.276043 DramcWriteLeveling(PI) end<-----
5842 11:32:34.276132
5843 11:32:34.276213 ==
5844 11:32:34.278908 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 11:32:34.282842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:32:34.282928 ==
5847 11:32:34.286155 [Gating] SW mode calibration
5848 11:32:34.292404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 11:32:34.299530 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 11:32:34.302489 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 11:32:34.306205 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 11:32:34.312963 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 11:32:34.316084 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 11:32:34.319388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 11:32:34.326439 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 11:32:34.329346 0 14 24 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
5857 11:32:34.332476 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5858 11:32:34.339289 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 11:32:34.343147 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 11:32:34.346097 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 11:32:34.349747 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 11:32:34.356627 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 11:32:34.359553 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5864 11:32:34.362721 0 15 24 | B1->B0 | 2d2d 3636 | 0 0 | (0 0) (0 0)
5865 11:32:34.369945 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5866 11:32:34.372906 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 11:32:34.376234 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 11:32:34.382799 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 11:32:34.386381 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 11:32:34.389489 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 11:32:34.396252 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5872 11:32:34.399555 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5873 11:32:34.403837 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 11:32:34.409525 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 11:32:34.413059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 11:32:34.416625 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 11:32:34.423240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 11:32:34.426400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 11:32:34.429345 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 11:32:34.432941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 11:32:34.439523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 11:32:34.443329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 11:32:34.446194 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 11:32:34.452966 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 11:32:34.456392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 11:32:34.459582 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:32:34.466631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5888 11:32:34.469551 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5889 11:32:34.472975 Total UI for P1: 0, mck2ui 16
5890 11:32:34.476750 best dqsien dly found for B0: ( 1, 2, 20)
5891 11:32:34.479664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5892 11:32:34.486712 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 11:32:34.486808 Total UI for P1: 0, mck2ui 16
5894 11:32:34.493219 best dqsien dly found for B1: ( 1, 2, 26)
5895 11:32:34.496196 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5896 11:32:34.499795 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5897 11:32:34.499884
5898 11:32:34.502897 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5899 11:32:34.506540 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5900 11:32:34.509569 [Gating] SW calibration Done
5901 11:32:34.509709 ==
5902 11:32:34.513292 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 11:32:34.516624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 11:32:34.516700 ==
5905 11:32:34.519501 RX Vref Scan: 0
5906 11:32:34.519576
5907 11:32:34.519634 RX Vref 0 -> 0, step: 1
5908 11:32:34.519688
5909 11:32:34.523577 RX Delay -80 -> 252, step: 8
5910 11:32:34.526580 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5911 11:32:34.529794 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5912 11:32:34.536675 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5913 11:32:34.539844 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5914 11:32:34.543113 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5915 11:32:34.546582 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5916 11:32:34.549971 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5917 11:32:34.553605 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5918 11:32:34.560026 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5919 11:32:34.563231 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5920 11:32:34.566549 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5921 11:32:34.570355 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5922 11:32:34.573872 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5923 11:32:34.576511 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5924 11:32:34.583444 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5925 11:32:34.586733 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5926 11:32:34.586842 ==
5927 11:32:34.590018 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 11:32:34.593402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 11:32:34.593476 ==
5930 11:32:34.593535 DQS Delay:
5931 11:32:34.596749 DQS0 = 0, DQS1 = 0
5932 11:32:34.596823 DQM Delay:
5933 11:32:34.600221 DQM0 = 94, DQM1 = 89
5934 11:32:34.600296 DQ Delay:
5935 11:32:34.603122 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5936 11:32:34.606470 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5937 11:32:34.610351 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5938 11:32:34.613083 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5939 11:32:34.613196
5940 11:32:34.613256
5941 11:32:34.613309 ==
5942 11:32:34.616302 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 11:32:34.619544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 11:32:34.622949 ==
5945 11:32:34.623024
5946 11:32:34.623083
5947 11:32:34.623137 TX Vref Scan disable
5948 11:32:34.626385 == TX Byte 0 ==
5949 11:32:34.630014 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5950 11:32:34.633187 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5951 11:32:34.636573 == TX Byte 1 ==
5952 11:32:34.639929 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5953 11:32:34.643326 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5954 11:32:34.643401 ==
5955 11:32:34.646859 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:32:34.653347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:32:34.653429 ==
5958 11:32:34.653517
5959 11:32:34.653602
5960 11:32:34.653681 TX Vref Scan disable
5961 11:32:34.657317 == TX Byte 0 ==
5962 11:32:34.660784 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5963 11:32:34.667264 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5964 11:32:34.667339 == TX Byte 1 ==
5965 11:32:34.670884 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5966 11:32:34.677322 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5967 11:32:34.677397
5968 11:32:34.677454 [DATLAT]
5969 11:32:34.677507 Freq=933, CH1 RK1
5970 11:32:34.677558
5971 11:32:34.681008 DATLAT Default: 0xb
5972 11:32:34.681082 0, 0xFFFF, sum = 0
5973 11:32:34.684089 1, 0xFFFF, sum = 0
5974 11:32:34.684165 2, 0xFFFF, sum = 0
5975 11:32:34.687722 3, 0xFFFF, sum = 0
5976 11:32:34.687799 4, 0xFFFF, sum = 0
5977 11:32:34.690823 5, 0xFFFF, sum = 0
5978 11:32:34.694025 6, 0xFFFF, sum = 0
5979 11:32:34.694102 7, 0xFFFF, sum = 0
5980 11:32:34.697231 8, 0xFFFF, sum = 0
5981 11:32:34.697307 9, 0xFFFF, sum = 0
5982 11:32:34.700494 10, 0x0, sum = 1
5983 11:32:34.700560 11, 0x0, sum = 2
5984 11:32:34.700614 12, 0x0, sum = 3
5985 11:32:34.704274 13, 0x0, sum = 4
5986 11:32:34.704377 best_step = 11
5987 11:32:34.704466
5988 11:32:34.707523 ==
5989 11:32:34.707597 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 11:32:34.714233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 11:32:34.714309 ==
5992 11:32:34.714368 RX Vref Scan: 0
5993 11:32:34.714422
5994 11:32:34.717497 RX Vref 0 -> 0, step: 1
5995 11:32:34.717572
5996 11:32:34.720907 RX Delay -61 -> 252, step: 4
5997 11:32:34.723837 iDelay=195, Bit 0, Center 96 (7 ~ 186) 180
5998 11:32:34.730736 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5999 11:32:34.733885 iDelay=195, Bit 2, Center 84 (-5 ~ 174) 180
6000 11:32:34.737285 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
6001 11:32:34.741001 iDelay=195, Bit 4, Center 94 (3 ~ 186) 184
6002 11:32:34.744517 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
6003 11:32:34.747688 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
6004 11:32:34.750886 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
6005 11:32:34.757339 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
6006 11:32:34.760901 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
6007 11:32:34.763997 iDelay=195, Bit 10, Center 94 (3 ~ 186) 184
6008 11:32:34.767529 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
6009 11:32:34.771001 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
6010 11:32:34.777627 iDelay=195, Bit 13, Center 96 (3 ~ 190) 188
6011 11:32:34.780623 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
6012 11:32:34.784372 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
6013 11:32:34.784447 ==
6014 11:32:34.787119 Dram Type= 6, Freq= 0, CH_1, rank 1
6015 11:32:34.790893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6016 11:32:34.790969 ==
6017 11:32:34.794304 DQS Delay:
6018 11:32:34.794380 DQS0 = 0, DQS1 = 0
6019 11:32:34.794438 DQM Delay:
6020 11:32:34.797695 DQM0 = 94, DQM1 = 90
6021 11:32:34.797769 DQ Delay:
6022 11:32:34.800804 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =94
6023 11:32:34.804196 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =90
6024 11:32:34.807618 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
6025 11:32:34.810810 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =98
6026 11:32:34.810885
6027 11:32:34.810942
6028 11:32:34.820649 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6029 11:32:34.820726 CH1 RK1: MR19=505, MR18=E17
6030 11:32:34.827450 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
6031 11:32:34.830645 [RxdqsGatingPostProcess] freq 933
6032 11:32:34.837887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6033 11:32:34.840509 best DQS0 dly(2T, 0.5T) = (0, 10)
6034 11:32:34.844050 best DQS1 dly(2T, 0.5T) = (0, 10)
6035 11:32:34.847458 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6036 11:32:34.850622 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6037 11:32:34.850690 best DQS0 dly(2T, 0.5T) = (0, 10)
6038 11:32:34.854319 best DQS1 dly(2T, 0.5T) = (0, 10)
6039 11:32:34.857328 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6040 11:32:34.860926 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6041 11:32:34.864182 Pre-setting of DQS Precalculation
6042 11:32:34.870880 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6043 11:32:34.877666 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6044 11:32:34.884595 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6045 11:32:34.884671
6046 11:32:34.884795
6047 11:32:34.887493 [Calibration Summary] 1866 Mbps
6048 11:32:34.887568 CH 0, Rank 0
6049 11:32:34.890700 SW Impedance : PASS
6050 11:32:34.894470 DUTY Scan : NO K
6051 11:32:34.894541 ZQ Calibration : PASS
6052 11:32:34.897535 Jitter Meter : NO K
6053 11:32:34.900901 CBT Training : PASS
6054 11:32:34.900988 Write leveling : PASS
6055 11:32:34.904236 RX DQS gating : PASS
6056 11:32:34.907546 RX DQ/DQS(RDDQC) : PASS
6057 11:32:34.907622 TX DQ/DQS : PASS
6058 11:32:34.910798 RX DATLAT : PASS
6059 11:32:34.910874 RX DQ/DQS(Engine): PASS
6060 11:32:34.914167 TX OE : NO K
6061 11:32:34.914242 All Pass.
6062 11:32:34.914301
6063 11:32:34.917734 CH 0, Rank 1
6064 11:32:34.917809 SW Impedance : PASS
6065 11:32:34.920790 DUTY Scan : NO K
6066 11:32:34.924623 ZQ Calibration : PASS
6067 11:32:34.924698 Jitter Meter : NO K
6068 11:32:34.927712 CBT Training : PASS
6069 11:32:34.930889 Write leveling : PASS
6070 11:32:34.930964 RX DQS gating : PASS
6071 11:32:34.934194 RX DQ/DQS(RDDQC) : PASS
6072 11:32:34.937561 TX DQ/DQS : PASS
6073 11:32:34.937637 RX DATLAT : PASS
6074 11:32:34.941067 RX DQ/DQS(Engine): PASS
6075 11:32:34.944744 TX OE : NO K
6076 11:32:34.944819 All Pass.
6077 11:32:34.944877
6078 11:32:34.944931 CH 1, Rank 0
6079 11:32:34.947356 SW Impedance : PASS
6080 11:32:34.950668 DUTY Scan : NO K
6081 11:32:34.950743 ZQ Calibration : PASS
6082 11:32:34.954276 Jitter Meter : NO K
6083 11:32:34.954351 CBT Training : PASS
6084 11:32:34.957452 Write leveling : PASS
6085 11:32:34.961399 RX DQS gating : PASS
6086 11:32:34.961493 RX DQ/DQS(RDDQC) : PASS
6087 11:32:34.964203 TX DQ/DQS : PASS
6088 11:32:34.967858 RX DATLAT : PASS
6089 11:32:34.967953 RX DQ/DQS(Engine): PASS
6090 11:32:34.970748 TX OE : NO K
6091 11:32:34.970849 All Pass.
6092 11:32:34.970943
6093 11:32:34.974468 CH 1, Rank 1
6094 11:32:34.974559 SW Impedance : PASS
6095 11:32:34.977462 DUTY Scan : NO K
6096 11:32:34.981072 ZQ Calibration : PASS
6097 11:32:34.981194 Jitter Meter : NO K
6098 11:32:34.984519 CBT Training : PASS
6099 11:32:34.988109 Write leveling : PASS
6100 11:32:34.988200 RX DQS gating : PASS
6101 11:32:34.991196 RX DQ/DQS(RDDQC) : PASS
6102 11:32:34.994540 TX DQ/DQS : PASS
6103 11:32:34.994607 RX DATLAT : PASS
6104 11:32:34.997413 RX DQ/DQS(Engine): PASS
6105 11:32:34.997483 TX OE : NO K
6106 11:32:35.001263 All Pass.
6107 11:32:35.001331
6108 11:32:35.001391 DramC Write-DBI off
6109 11:32:35.004455 PER_BANK_REFRESH: Hybrid Mode
6110 11:32:35.007416 TX_TRACKING: ON
6111 11:32:35.014258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6112 11:32:35.017704 [FAST_K] Save calibration result to emmc
6113 11:32:35.023897 dramc_set_vcore_voltage set vcore to 650000
6114 11:32:35.023993 Read voltage for 400, 6
6115 11:32:35.024077 Vio18 = 0
6116 11:32:35.027659 Vcore = 650000
6117 11:32:35.027751 Vdram = 0
6118 11:32:35.027832 Vddq = 0
6119 11:32:35.030877 Vmddr = 0
6120 11:32:35.034238 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6121 11:32:35.041272 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6122 11:32:35.041367 MEM_TYPE=3, freq_sel=20
6123 11:32:35.044745 sv_algorithm_assistance_LP4_800
6124 11:32:35.050538 ============ PULL DRAM RESETB DOWN ============
6125 11:32:35.054095 ========== PULL DRAM RESETB DOWN end =========
6126 11:32:35.057724 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 11:32:35.060916 ===================================
6128 11:32:35.064153 LPDDR4 DRAM CONFIGURATION
6129 11:32:35.067607 ===================================
6130 11:32:35.067701 EX_ROW_EN[0] = 0x0
6131 11:32:35.070954 EX_ROW_EN[1] = 0x0
6132 11:32:35.074194 LP4Y_EN = 0x0
6133 11:32:35.074262 WORK_FSP = 0x0
6134 11:32:35.077760 WL = 0x2
6135 11:32:35.077826 RL = 0x2
6136 11:32:35.080732 BL = 0x2
6137 11:32:35.080822 RPST = 0x0
6138 11:32:35.084478 RD_PRE = 0x0
6139 11:32:35.084545 WR_PRE = 0x1
6140 11:32:35.087301 WR_PST = 0x0
6141 11:32:35.087389 DBI_WR = 0x0
6142 11:32:35.090956 DBI_RD = 0x0
6143 11:32:35.091054 OTF = 0x1
6144 11:32:35.094603 ===================================
6145 11:32:35.097622 ===================================
6146 11:32:35.100983 ANA top config
6147 11:32:35.104596 ===================================
6148 11:32:35.104674 DLL_ASYNC_EN = 0
6149 11:32:35.107510 ALL_SLAVE_EN = 1
6150 11:32:35.111329 NEW_RANK_MODE = 1
6151 11:32:35.114147 DLL_IDLE_MODE = 1
6152 11:32:35.117462 LP45_APHY_COMB_EN = 1
6153 11:32:35.117537 TX_ODT_DIS = 1
6154 11:32:35.121153 NEW_8X_MODE = 1
6155 11:32:35.124056 ===================================
6156 11:32:35.127849 ===================================
6157 11:32:35.130874 data_rate = 800
6158 11:32:35.134111 CKR = 1
6159 11:32:35.137478 DQ_P2S_RATIO = 4
6160 11:32:35.140963 ===================================
6161 11:32:35.141063 CA_P2S_RATIO = 4
6162 11:32:35.144254 DQ_CA_OPEN = 0
6163 11:32:35.147163 DQ_SEMI_OPEN = 1
6164 11:32:35.150639 CA_SEMI_OPEN = 1
6165 11:32:35.154059 CA_FULL_RATE = 0
6166 11:32:35.158124 DQ_CKDIV4_EN = 0
6167 11:32:35.158199 CA_CKDIV4_EN = 1
6168 11:32:35.160720 CA_PREDIV_EN = 0
6169 11:32:35.164339 PH8_DLY = 0
6170 11:32:35.167385 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6171 11:32:35.170898 DQ_AAMCK_DIV = 0
6172 11:32:35.173876 CA_AAMCK_DIV = 0
6173 11:32:35.173942 CA_ADMCK_DIV = 4
6174 11:32:35.177563 DQ_TRACK_CA_EN = 0
6175 11:32:35.180887 CA_PICK = 800
6176 11:32:35.184133 CA_MCKIO = 400
6177 11:32:35.187208 MCKIO_SEMI = 400
6178 11:32:35.190674 PLL_FREQ = 3016
6179 11:32:35.194325 DQ_UI_PI_RATIO = 32
6180 11:32:35.194417 CA_UI_PI_RATIO = 32
6181 11:32:35.197677 ===================================
6182 11:32:35.200748 ===================================
6183 11:32:35.204144 memory_type:LPDDR4
6184 11:32:35.207354 GP_NUM : 10
6185 11:32:35.207443 SRAM_EN : 1
6186 11:32:35.210807 MD32_EN : 0
6187 11:32:35.214230 ===================================
6188 11:32:35.217653 [ANA_INIT] >>>>>>>>>>>>>>
6189 11:32:35.220734 <<<<<< [CONFIGURE PHASE]: ANA_TX
6190 11:32:35.224080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6191 11:32:35.227337 ===================================
6192 11:32:35.227427 data_rate = 800,PCW = 0X7400
6193 11:32:35.230656 ===================================
6194 11:32:35.233950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6195 11:32:35.240927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 11:32:35.250809 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 11:32:35.257586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6198 11:32:35.260919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6199 11:32:35.264278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6200 11:32:35.264355 [ANA_INIT] flow start
6201 11:32:35.267801 [ANA_INIT] PLL >>>>>>>>
6202 11:32:35.270697 [ANA_INIT] PLL <<<<<<<<
6203 11:32:35.274475 [ANA_INIT] MIDPI >>>>>>>>
6204 11:32:35.274551 [ANA_INIT] MIDPI <<<<<<<<
6205 11:32:35.277917 [ANA_INIT] DLL >>>>>>>>
6206 11:32:35.280891 [ANA_INIT] flow end
6207 11:32:35.284099 ============ LP4 DIFF to SE enter ============
6208 11:32:35.287753 ============ LP4 DIFF to SE exit ============
6209 11:32:35.291076 [ANA_INIT] <<<<<<<<<<<<<
6210 11:32:35.294574 [Flow] Enable top DCM control >>>>>
6211 11:32:35.297692 [Flow] Enable top DCM control <<<<<
6212 11:32:35.301032 Enable DLL master slave shuffle
6213 11:32:35.304426 ==============================================================
6214 11:32:35.307889 Gating Mode config
6215 11:32:35.310755 ==============================================================
6216 11:32:35.314384 Config description:
6217 11:32:35.324174 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6218 11:32:35.330958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6219 11:32:35.334661 SELPH_MODE 0: By rank 1: By Phase
6220 11:32:35.341241 ==============================================================
6221 11:32:35.344193 GAT_TRACK_EN = 0
6222 11:32:35.347655 RX_GATING_MODE = 2
6223 11:32:35.350740 RX_GATING_TRACK_MODE = 2
6224 11:32:35.354308 SELPH_MODE = 1
6225 11:32:35.354402 PICG_EARLY_EN = 1
6226 11:32:35.357430 VALID_LAT_VALUE = 1
6227 11:32:35.364143 ==============================================================
6228 11:32:35.367481 Enter into Gating configuration >>>>
6229 11:32:35.370722 Exit from Gating configuration <<<<
6230 11:32:35.374184 Enter into DVFS_PRE_config >>>>>
6231 11:32:35.384003 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6232 11:32:35.387356 Exit from DVFS_PRE_config <<<<<
6233 11:32:35.390692 Enter into PICG configuration >>>>
6234 11:32:35.393899 Exit from PICG configuration <<<<
6235 11:32:35.397307 [RX_INPUT] configuration >>>>>
6236 11:32:35.400450 [RX_INPUT] configuration <<<<<
6237 11:32:35.404135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6238 11:32:35.410849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6239 11:32:35.417647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6240 11:32:35.423775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6241 11:32:35.431334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 11:32:35.434193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 11:32:35.440786 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6244 11:32:35.444214 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6245 11:32:35.447545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6246 11:32:35.450988 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6247 11:32:35.454580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6248 11:32:35.461283 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 11:32:35.464129 ===================================
6250 11:32:35.467654 LPDDR4 DRAM CONFIGURATION
6251 11:32:35.467749 ===================================
6252 11:32:35.470909 EX_ROW_EN[0] = 0x0
6253 11:32:35.474242 EX_ROW_EN[1] = 0x0
6254 11:32:35.474308 LP4Y_EN = 0x0
6255 11:32:35.477405 WORK_FSP = 0x0
6256 11:32:35.477474 WL = 0x2
6257 11:32:35.480867 RL = 0x2
6258 11:32:35.480958 BL = 0x2
6259 11:32:35.484754 RPST = 0x0
6260 11:32:35.484843 RD_PRE = 0x0
6261 11:32:35.487740 WR_PRE = 0x1
6262 11:32:35.487829 WR_PST = 0x0
6263 11:32:35.491133 DBI_WR = 0x0
6264 11:32:35.491221 DBI_RD = 0x0
6265 11:32:35.494041 OTF = 0x1
6266 11:32:35.497347 ===================================
6267 11:32:35.500573 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6268 11:32:35.504424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6269 11:32:35.511171 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 11:32:35.514749 ===================================
6271 11:32:35.514856 LPDDR4 DRAM CONFIGURATION
6272 11:32:35.517266 ===================================
6273 11:32:35.520673 EX_ROW_EN[0] = 0x10
6274 11:32:35.524484 EX_ROW_EN[1] = 0x0
6275 11:32:35.524575 LP4Y_EN = 0x0
6276 11:32:35.527683 WORK_FSP = 0x0
6277 11:32:35.527773 WL = 0x2
6278 11:32:35.531265 RL = 0x2
6279 11:32:35.531359 BL = 0x2
6280 11:32:35.534534 RPST = 0x0
6281 11:32:35.534621 RD_PRE = 0x0
6282 11:32:35.537629 WR_PRE = 0x1
6283 11:32:35.537713 WR_PST = 0x0
6284 11:32:35.540793 DBI_WR = 0x0
6285 11:32:35.540883 DBI_RD = 0x0
6286 11:32:35.544677 OTF = 0x1
6287 11:32:35.547818 ===================================
6288 11:32:35.554384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6289 11:32:35.557569 nWR fixed to 30
6290 11:32:35.557665 [ModeRegInit_LP4] CH0 RK0
6291 11:32:35.560764 [ModeRegInit_LP4] CH0 RK1
6292 11:32:35.564602 [ModeRegInit_LP4] CH1 RK0
6293 11:32:35.564693 [ModeRegInit_LP4] CH1 RK1
6294 11:32:35.567714 match AC timing 19
6295 11:32:35.571075 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6296 11:32:35.574597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6297 11:32:35.580995 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6298 11:32:35.584420 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6299 11:32:35.591422 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6300 11:32:35.591514 ==
6301 11:32:35.594487 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:32:35.597554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:32:35.597622 ==
6304 11:32:35.604192 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6305 11:32:35.607452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6306 11:32:35.611200 [CA 0] Center 36 (8~64) winsize 57
6307 11:32:35.614446 [CA 1] Center 36 (8~64) winsize 57
6308 11:32:35.617937 [CA 2] Center 36 (8~64) winsize 57
6309 11:32:35.621395 [CA 3] Center 36 (8~64) winsize 57
6310 11:32:35.624333 [CA 4] Center 36 (8~64) winsize 57
6311 11:32:35.627548 [CA 5] Center 36 (8~64) winsize 57
6312 11:32:35.627640
6313 11:32:35.630815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6314 11:32:35.630904
6315 11:32:35.634360 [CATrainingPosCal] consider 1 rank data
6316 11:32:35.637781 u2DelayCellTimex100 = 270/100 ps
6317 11:32:35.640942 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:32:35.644113 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:32:35.647932 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:32:35.650922 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:32:35.657722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:32:35.661022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:32:35.661121
6324 11:32:35.664316 CA PerBit enable=1, Macro0, CA PI delay=36
6325 11:32:35.664402
6326 11:32:35.667568 [CBTSetCACLKResult] CA Dly = 36
6327 11:32:35.667638 CS Dly: 1 (0~32)
6328 11:32:35.667697 ==
6329 11:32:35.670973 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 11:32:35.674309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:32:35.677641 ==
6332 11:32:35.680976 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 11:32:35.688014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 11:32:35.691354 [CA 0] Center 36 (8~64) winsize 57
6335 11:32:35.694341 [CA 1] Center 36 (8~64) winsize 57
6336 11:32:35.697850 [CA 2] Center 36 (8~64) winsize 57
6337 11:32:35.701039 [CA 3] Center 36 (8~64) winsize 57
6338 11:32:35.704487 [CA 4] Center 36 (8~64) winsize 57
6339 11:32:35.707807 [CA 5] Center 36 (8~64) winsize 57
6340 11:32:35.707896
6341 11:32:35.711095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 11:32:35.711186
6343 11:32:35.714728 [CATrainingPosCal] consider 2 rank data
6344 11:32:35.718073 u2DelayCellTimex100 = 270/100 ps
6345 11:32:35.721138 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 11:32:35.724767 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 11:32:35.727550 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 11:32:35.731350 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 11:32:35.734622 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 11:32:35.738403 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 11:32:35.738479
6352 11:32:35.741259 CA PerBit enable=1, Macro0, CA PI delay=36
6353 11:32:35.741333
6354 11:32:35.744273 [CBTSetCACLKResult] CA Dly = 36
6355 11:32:35.747705 CS Dly: 1 (0~32)
6356 11:32:35.747780
6357 11:32:35.751083 ----->DramcWriteLeveling(PI) begin...
6358 11:32:35.751160 ==
6359 11:32:35.754346 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 11:32:35.757742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 11:32:35.757818 ==
6362 11:32:35.761422 Write leveling (Byte 0): 40 => 8
6363 11:32:35.764361 Write leveling (Byte 1): 32 => 0
6364 11:32:35.767769 DramcWriteLeveling(PI) end<-----
6365 11:32:35.767844
6366 11:32:35.767902 ==
6367 11:32:35.771173 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:32:35.774559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:32:35.774634 ==
6370 11:32:35.777885 [Gating] SW mode calibration
6371 11:32:35.784675 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6372 11:32:35.791071 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6373 11:32:35.794759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 11:32:35.798842 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 11:32:35.804619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 11:32:35.808205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 11:32:35.811587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 11:32:35.817854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 11:32:35.821309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 11:32:35.824779 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 11:32:35.831652 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6382 11:32:35.831726 Total UI for P1: 0, mck2ui 16
6383 11:32:35.838556 best dqsien dly found for B0: ( 0, 14, 24)
6384 11:32:35.838631 Total UI for P1: 0, mck2ui 16
6385 11:32:35.841524 best dqsien dly found for B1: ( 0, 14, 24)
6386 11:32:35.848093 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6387 11:32:35.851285 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6388 11:32:35.851360
6389 11:32:35.854836 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 11:32:35.858000 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 11:32:35.861369 [Gating] SW calibration Done
6392 11:32:35.861443 ==
6393 11:32:35.864775 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 11:32:35.868241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 11:32:35.868317 ==
6396 11:32:35.871616 RX Vref Scan: 0
6397 11:32:35.871690
6398 11:32:35.871748 RX Vref 0 -> 0, step: 1
6399 11:32:35.871807
6400 11:32:35.875134 RX Delay -410 -> 252, step: 16
6401 11:32:35.878385 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6402 11:32:35.884883 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6403 11:32:35.888386 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6404 11:32:35.892167 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6405 11:32:35.894834 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6406 11:32:35.901788 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6407 11:32:35.904862 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6408 11:32:35.908775 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6409 11:32:35.911586 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6410 11:32:35.918813 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6411 11:32:35.921472 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6412 11:32:35.924740 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6413 11:32:35.928318 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6414 11:32:35.934793 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6415 11:32:35.938156 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6416 11:32:35.941453 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6417 11:32:35.941529 ==
6418 11:32:35.944745 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 11:32:35.951563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 11:32:35.951640 ==
6421 11:32:35.951698 DQS Delay:
6422 11:32:35.951753 DQS0 = 35, DQS1 = 51
6423 11:32:35.955521 DQM Delay:
6424 11:32:35.955596 DQM0 = 6, DQM1 = 10
6425 11:32:35.958227 DQ Delay:
6426 11:32:35.958304 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6427 11:32:35.961395 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6428 11:32:35.964729 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6429 11:32:35.968457 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6430 11:32:35.968532
6431 11:32:35.968660
6432 11:32:35.968741 ==
6433 11:32:35.971581 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 11:32:35.978475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 11:32:35.978552 ==
6436 11:32:35.978610
6437 11:32:35.978663
6438 11:32:35.978714 TX Vref Scan disable
6439 11:32:35.981940 == TX Byte 0 ==
6440 11:32:35.984764 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 11:32:35.988193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 11:32:35.991316 == TX Byte 1 ==
6443 11:32:35.994911 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 11:32:35.998013 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 11:32:36.001307 ==
6446 11:32:36.004738 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 11:32:36.008579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:32:36.008675 ==
6449 11:32:36.008815
6450 11:32:36.008911
6451 11:32:36.011359 TX Vref Scan disable
6452 11:32:36.011439 == TX Byte 0 ==
6453 11:32:36.014808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 11:32:36.021356 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 11:32:36.021432 == TX Byte 1 ==
6456 11:32:36.024675 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 11:32:36.031482 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 11:32:36.031577
6459 11:32:36.031660 [DATLAT]
6460 11:32:36.031778 Freq=400, CH0 RK0
6461 11:32:36.031859
6462 11:32:36.034847 DATLAT Default: 0xf
6463 11:32:36.034918 0, 0xFFFF, sum = 0
6464 11:32:36.038385 1, 0xFFFF, sum = 0
6465 11:32:36.038520 2, 0xFFFF, sum = 0
6466 11:32:36.041224 3, 0xFFFF, sum = 0
6467 11:32:36.045149 4, 0xFFFF, sum = 0
6468 11:32:36.045274 5, 0xFFFF, sum = 0
6469 11:32:36.048225 6, 0xFFFF, sum = 0
6470 11:32:36.048349 7, 0xFFFF, sum = 0
6471 11:32:36.051385 8, 0xFFFF, sum = 0
6472 11:32:36.051479 9, 0xFFFF, sum = 0
6473 11:32:36.054970 10, 0xFFFF, sum = 0
6474 11:32:36.055059 11, 0xFFFF, sum = 0
6475 11:32:36.057915 12, 0xFFFF, sum = 0
6476 11:32:36.058007 13, 0x0, sum = 1
6477 11:32:36.061321 14, 0x0, sum = 2
6478 11:32:36.061417 15, 0x0, sum = 3
6479 11:32:36.065024 16, 0x0, sum = 4
6480 11:32:36.065136 best_step = 14
6481 11:32:36.065208
6482 11:32:36.065262 ==
6483 11:32:36.067930 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 11:32:36.071182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:32:36.071314 ==
6486 11:32:36.074710 RX Vref Scan: 1
6487 11:32:36.074786
6488 11:32:36.078305 RX Vref 0 -> 0, step: 1
6489 11:32:36.078373
6490 11:32:36.078429 RX Delay -343 -> 252, step: 8
6491 11:32:36.081452
6492 11:32:36.081562 Set Vref, RX VrefLevel [Byte0]: 53
6493 11:32:36.084829 [Byte1]: 53
6494 11:32:36.090445
6495 11:32:36.090521 Final RX Vref Byte 0 = 53 to rank0
6496 11:32:36.093544 Final RX Vref Byte 1 = 53 to rank0
6497 11:32:36.097090 Final RX Vref Byte 0 = 53 to rank1
6498 11:32:36.100396 Final RX Vref Byte 1 = 53 to rank1==
6499 11:32:36.103932 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 11:32:36.110497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:32:36.110579 ==
6502 11:32:36.110638 DQS Delay:
6503 11:32:36.114018 DQS0 = 44, DQS1 = 60
6504 11:32:36.114120 DQM Delay:
6505 11:32:36.114206 DQM0 = 11, DQM1 = 13
6506 11:32:36.116883 DQ Delay:
6507 11:32:36.120536 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6508 11:32:36.120612 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6509 11:32:36.123746 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6510 11:32:36.127292 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6511 11:32:36.127395
6512 11:32:36.130430
6513 11:32:36.137458 [DQSOSCAuto] RK0, (LSB)MR18= 0x8957, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6514 11:32:36.140829 CH0 RK0: MR19=C0C, MR18=8957
6515 11:32:36.146857 CH0_RK0: MR19=0xC0C, MR18=0x8957, DQSOSC=392, MR23=63, INC=384, DEC=256
6516 11:32:36.146937 ==
6517 11:32:36.150378 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 11:32:36.153765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 11:32:36.153843 ==
6520 11:32:36.157418 [Gating] SW mode calibration
6521 11:32:36.163846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 11:32:36.167687 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 11:32:36.173966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 11:32:36.177077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 11:32:36.180716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 11:32:36.187096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 11:32:36.190435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 11:32:36.193976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 11:32:36.200739 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 11:32:36.204077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 11:32:36.207307 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 11:32:36.210873 Total UI for P1: 0, mck2ui 16
6533 11:32:36.214040 best dqsien dly found for B0: ( 0, 14, 24)
6534 11:32:36.217367 Total UI for P1: 0, mck2ui 16
6535 11:32:36.220536 best dqsien dly found for B1: ( 0, 14, 24)
6536 11:32:36.223795 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 11:32:36.227299 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 11:32:36.227374
6539 11:32:36.234102 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 11:32:36.237611 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 11:32:36.237687 [Gating] SW calibration Done
6542 11:32:36.240830 ==
6543 11:32:36.240905 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 11:32:36.247441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 11:32:36.247517 ==
6546 11:32:36.247575 RX Vref Scan: 0
6547 11:32:36.247631
6548 11:32:36.250738 RX Vref 0 -> 0, step: 1
6549 11:32:36.250813
6550 11:32:36.253980 RX Delay -410 -> 252, step: 16
6551 11:32:36.257455 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6552 11:32:36.260752 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6553 11:32:36.267533 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6554 11:32:36.270561 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6555 11:32:36.273845 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6556 11:32:36.277307 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6557 11:32:36.284333 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6558 11:32:36.287272 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6559 11:32:36.290678 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6560 11:32:36.293891 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6561 11:32:36.300551 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6562 11:32:36.304070 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6563 11:32:36.307186 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6564 11:32:36.310571 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6565 11:32:36.317713 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6566 11:32:36.321128 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6567 11:32:36.321217 ==
6568 11:32:36.324322 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 11:32:36.327713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 11:32:36.327789 ==
6571 11:32:36.330836 DQS Delay:
6572 11:32:36.330911 DQS0 = 43, DQS1 = 51
6573 11:32:36.330970 DQM Delay:
6574 11:32:36.334193 DQM0 = 11, DQM1 = 10
6575 11:32:36.334268 DQ Delay:
6576 11:32:36.337477 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6577 11:32:36.340656 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6578 11:32:36.344247 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6579 11:32:36.347927 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6580 11:32:36.348002
6581 11:32:36.348060
6582 11:32:36.348114 ==
6583 11:32:36.351159 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 11:32:36.353973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:32:36.354049 ==
6586 11:32:36.357771
6587 11:32:36.357847
6588 11:32:36.357905 TX Vref Scan disable
6589 11:32:36.360880 == TX Byte 0 ==
6590 11:32:36.364338 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6591 11:32:36.367552 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6592 11:32:36.371238 == TX Byte 1 ==
6593 11:32:36.374078 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6594 11:32:36.377639 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6595 11:32:36.377716 ==
6596 11:32:36.381258 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 11:32:36.384223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:32:36.384298 ==
6599 11:32:36.387914
6600 11:32:36.387988
6601 11:32:36.388046 TX Vref Scan disable
6602 11:32:36.391008 == TX Byte 0 ==
6603 11:32:36.394045 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6604 11:32:36.397775 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6605 11:32:36.401112 == TX Byte 1 ==
6606 11:32:36.403923 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6607 11:32:36.407255 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6608 11:32:36.407330
6609 11:32:36.407388 [DATLAT]
6610 11:32:36.411149 Freq=400, CH0 RK1
6611 11:32:36.411223
6612 11:32:36.411281 DATLAT Default: 0xe
6613 11:32:36.414723 0, 0xFFFF, sum = 0
6614 11:32:36.414798 1, 0xFFFF, sum = 0
6615 11:32:36.417335 2, 0xFFFF, sum = 0
6616 11:32:36.421038 3, 0xFFFF, sum = 0
6617 11:32:36.421138 4, 0xFFFF, sum = 0
6618 11:32:36.424081 5, 0xFFFF, sum = 0
6619 11:32:36.424157 6, 0xFFFF, sum = 0
6620 11:32:36.427435 7, 0xFFFF, sum = 0
6621 11:32:36.427511 8, 0xFFFF, sum = 0
6622 11:32:36.430804 9, 0xFFFF, sum = 0
6623 11:32:36.430880 10, 0xFFFF, sum = 0
6624 11:32:36.434139 11, 0xFFFF, sum = 0
6625 11:32:36.434214 12, 0xFFFF, sum = 0
6626 11:32:36.437758 13, 0x0, sum = 1
6627 11:32:36.437833 14, 0x0, sum = 2
6628 11:32:36.440968 15, 0x0, sum = 3
6629 11:32:36.441042 16, 0x0, sum = 4
6630 11:32:36.444319 best_step = 14
6631 11:32:36.444389
6632 11:32:36.444444 ==
6633 11:32:36.447421 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 11:32:36.451089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 11:32:36.451164 ==
6636 11:32:36.451223 RX Vref Scan: 0
6637 11:32:36.451278
6638 11:32:36.454124 RX Vref 0 -> 0, step: 1
6639 11:32:36.454199
6640 11:32:36.457404 RX Delay -343 -> 252, step: 8
6641 11:32:36.464480 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6642 11:32:36.468385 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6643 11:32:36.471396 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6644 11:32:36.474776 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6645 11:32:36.481891 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6646 11:32:36.484806 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6647 11:32:36.488247 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6648 11:32:36.491345 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6649 11:32:36.498050 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6650 11:32:36.501384 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6651 11:32:36.504981 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6652 11:32:36.508306 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6653 11:32:36.514624 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6654 11:32:36.517820 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6655 11:32:36.521364 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6656 11:32:36.528685 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6657 11:32:36.528761 ==
6658 11:32:36.531502 Dram Type= 6, Freq= 0, CH_0, rank 1
6659 11:32:36.534626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:32:36.534702 ==
6661 11:32:36.534761 DQS Delay:
6662 11:32:36.537790 DQS0 = 48, DQS1 = 60
6663 11:32:36.537866 DQM Delay:
6664 11:32:36.541537 DQM0 = 12, DQM1 = 13
6665 11:32:36.541636 DQ Delay:
6666 11:32:36.545107 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6667 11:32:36.547973 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6668 11:32:36.551309 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6669 11:32:36.554939 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6670 11:32:36.555015
6671 11:32:36.555073
6672 11:32:36.561489 [DQSOSCAuto] RK1, (LSB)MR18= 0x9c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6673 11:32:36.564359 CH0 RK1: MR19=C0C, MR18=9C6F
6674 11:32:36.570968 CH0_RK1: MR19=0xC0C, MR18=0x9C6F, DQSOSC=390, MR23=63, INC=388, DEC=258
6675 11:32:36.574694 [RxdqsGatingPostProcess] freq 400
6676 11:32:36.581247 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6677 11:32:36.581323 best DQS0 dly(2T, 0.5T) = (0, 10)
6678 11:32:36.584504 best DQS1 dly(2T, 0.5T) = (0, 10)
6679 11:32:36.587699 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6680 11:32:36.590929 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6681 11:32:36.594505 best DQS0 dly(2T, 0.5T) = (0, 10)
6682 11:32:36.597918 best DQS1 dly(2T, 0.5T) = (0, 10)
6683 11:32:36.601216 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6684 11:32:36.604434 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6685 11:32:36.608022 Pre-setting of DQS Precalculation
6686 11:32:36.614746 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6687 11:32:36.614822 ==
6688 11:32:36.617613 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:32:36.620757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:32:36.620832 ==
6691 11:32:36.627380 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6692 11:32:36.631320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6693 11:32:36.634445 [CA 0] Center 36 (8~64) winsize 57
6694 11:32:36.637973 [CA 1] Center 36 (8~64) winsize 57
6695 11:32:36.641302 [CA 2] Center 36 (8~64) winsize 57
6696 11:32:36.643950 [CA 3] Center 36 (8~64) winsize 57
6697 11:32:36.647391 [CA 4] Center 36 (8~64) winsize 57
6698 11:32:36.650651 [CA 5] Center 36 (8~64) winsize 57
6699 11:32:36.650745
6700 11:32:36.654116 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6701 11:32:36.654190
6702 11:32:36.657417 [CATrainingPosCal] consider 1 rank data
6703 11:32:36.660855 u2DelayCellTimex100 = 270/100 ps
6704 11:32:36.664113 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:32:36.667422 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:32:36.670780 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:32:36.674408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:32:36.680678 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:32:36.684375 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:32:36.684449
6711 11:32:36.688513 CA PerBit enable=1, Macro0, CA PI delay=36
6712 11:32:36.688588
6713 11:32:36.690771 [CBTSetCACLKResult] CA Dly = 36
6714 11:32:36.690845 CS Dly: 1 (0~32)
6715 11:32:36.690903 ==
6716 11:32:36.694598 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 11:32:36.697527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:32:36.700958 ==
6719 11:32:36.704183 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 11:32:36.710745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6721 11:32:36.714227 [CA 0] Center 36 (8~64) winsize 57
6722 11:32:36.717734 [CA 1] Center 36 (8~64) winsize 57
6723 11:32:36.720782 [CA 2] Center 36 (8~64) winsize 57
6724 11:32:36.724393 [CA 3] Center 36 (8~64) winsize 57
6725 11:32:36.727845 [CA 4] Center 36 (8~64) winsize 57
6726 11:32:36.731023 [CA 5] Center 36 (8~64) winsize 57
6727 11:32:36.731120
6728 11:32:36.734777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6729 11:32:36.734852
6730 11:32:36.737464 [CATrainingPosCal] consider 2 rank data
6731 11:32:36.740713 u2DelayCellTimex100 = 270/100 ps
6732 11:32:36.744327 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 11:32:36.747736 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 11:32:36.750985 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 11:32:36.754463 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 11:32:36.757698 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 11:32:36.760980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 11:32:36.761054
6739 11:32:36.764352 CA PerBit enable=1, Macro0, CA PI delay=36
6740 11:32:36.764425
6741 11:32:36.767929 [CBTSetCACLKResult] CA Dly = 36
6742 11:32:36.771522 CS Dly: 1 (0~32)
6743 11:32:36.771596
6744 11:32:36.774418 ----->DramcWriteLeveling(PI) begin...
6745 11:32:36.774493 ==
6746 11:32:36.777504 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 11:32:36.781242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 11:32:36.781343 ==
6749 11:32:36.784461 Write leveling (Byte 0): 40 => 8
6750 11:32:36.787764 Write leveling (Byte 1): 40 => 8
6751 11:32:36.790992 DramcWriteLeveling(PI) end<-----
6752 11:32:36.791066
6753 11:32:36.791123 ==
6754 11:32:36.794284 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:32:36.797727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:32:36.797802 ==
6757 11:32:36.801028 [Gating] SW mode calibration
6758 11:32:36.807578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6759 11:32:36.814427 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6760 11:32:36.817497 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 11:32:36.821056 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 11:32:36.827933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 11:32:36.830845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 11:32:36.834238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 11:32:36.841056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 11:32:36.844649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 11:32:36.847988 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 11:32:36.854646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6769 11:32:36.854720 Total UI for P1: 0, mck2ui 16
6770 11:32:36.860784 best dqsien dly found for B0: ( 0, 14, 24)
6771 11:32:36.860859 Total UI for P1: 0, mck2ui 16
6772 11:32:36.867374 best dqsien dly found for B1: ( 0, 14, 24)
6773 11:32:36.870802 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6774 11:32:36.874204 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6775 11:32:36.874278
6776 11:32:36.877923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 11:32:36.881056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 11:32:36.884082 [Gating] SW calibration Done
6779 11:32:36.884156 ==
6780 11:32:36.887525 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 11:32:36.891193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 11:32:36.891287 ==
6783 11:32:36.894400 RX Vref Scan: 0
6784 11:32:36.894474
6785 11:32:36.894531 RX Vref 0 -> 0, step: 1
6786 11:32:36.894585
6787 11:32:36.897873 RX Delay -410 -> 252, step: 16
6788 11:32:36.904433 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6789 11:32:36.907820 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6790 11:32:36.911074 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6791 11:32:36.914544 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6792 11:32:36.918091 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6793 11:32:36.924497 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6794 11:32:36.927659 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6795 11:32:36.930924 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6796 11:32:36.934512 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6797 11:32:36.941283 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6798 11:32:36.944373 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6799 11:32:36.947951 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6800 11:32:36.951383 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6801 11:32:36.957702 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6802 11:32:36.961038 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6803 11:32:36.964602 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6804 11:32:36.964692 ==
6805 11:32:36.967816 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 11:32:36.974605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 11:32:36.974699 ==
6808 11:32:36.974785 DQS Delay:
6809 11:32:36.977999 DQS0 = 51, DQS1 = 59
6810 11:32:36.978087 DQM Delay:
6811 11:32:36.978171 DQM0 = 19, DQM1 = 16
6812 11:32:36.980964 DQ Delay:
6813 11:32:36.984635 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6814 11:32:36.987748 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6815 11:32:36.987836 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6816 11:32:36.994409 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6817 11:32:36.994476
6818 11:32:36.994534
6819 11:32:36.994594 ==
6820 11:32:36.997765 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 11:32:37.001218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 11:32:37.001311 ==
6823 11:32:37.001402
6824 11:32:37.001487
6825 11:32:37.004514 TX Vref Scan disable
6826 11:32:37.004609 == TX Byte 0 ==
6827 11:32:37.007863 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 11:32:37.014658 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 11:32:37.014754 == TX Byte 1 ==
6830 11:32:37.017917 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6831 11:32:37.024629 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6832 11:32:37.024718 ==
6833 11:32:37.028151 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 11:32:37.031405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:32:37.031469 ==
6836 11:32:37.031522
6837 11:32:37.031574
6838 11:32:37.034585 TX Vref Scan disable
6839 11:32:37.034648 == TX Byte 0 ==
6840 11:32:37.037824 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 11:32:37.044696 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 11:32:37.044776 == TX Byte 1 ==
6843 11:32:37.047988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 11:32:37.054721 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 11:32:37.054788
6846 11:32:37.054843 [DATLAT]
6847 11:32:37.054901 Freq=400, CH1 RK0
6848 11:32:37.054953
6849 11:32:37.057867 DATLAT Default: 0xf
6850 11:32:37.057934 0, 0xFFFF, sum = 0
6851 11:32:37.061516 1, 0xFFFF, sum = 0
6852 11:32:37.064935 2, 0xFFFF, sum = 0
6853 11:32:37.065023 3, 0xFFFF, sum = 0
6854 11:32:37.067610 4, 0xFFFF, sum = 0
6855 11:32:37.067700 5, 0xFFFF, sum = 0
6856 11:32:37.071177 6, 0xFFFF, sum = 0
6857 11:32:37.071253 7, 0xFFFF, sum = 0
6858 11:32:37.074428 8, 0xFFFF, sum = 0
6859 11:32:37.074519 9, 0xFFFF, sum = 0
6860 11:32:37.077808 10, 0xFFFF, sum = 0
6861 11:32:37.077972 11, 0xFFFF, sum = 0
6862 11:32:37.081204 12, 0xFFFF, sum = 0
6863 11:32:37.081279 13, 0x0, sum = 1
6864 11:32:37.084709 14, 0x0, sum = 2
6865 11:32:37.084784 15, 0x0, sum = 3
6866 11:32:37.088012 16, 0x0, sum = 4
6867 11:32:37.088087 best_step = 14
6868 11:32:37.088145
6869 11:32:37.088198 ==
6870 11:32:37.091311 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 11:32:37.094631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:32:37.097863 ==
6873 11:32:37.097969 RX Vref Scan: 1
6874 11:32:37.098042
6875 11:32:37.101347 RX Vref 0 -> 0, step: 1
6876 11:32:37.101420
6877 11:32:37.104825 RX Delay -359 -> 252, step: 8
6878 11:32:37.104900
6879 11:32:37.104959 Set Vref, RX VrefLevel [Byte0]: 62
6880 11:32:37.108368 [Byte1]: 51
6881 11:32:37.113545
6882 11:32:37.113619 Final RX Vref Byte 0 = 62 to rank0
6883 11:32:37.116963 Final RX Vref Byte 1 = 51 to rank0
6884 11:32:37.120326 Final RX Vref Byte 0 = 62 to rank1
6885 11:32:37.123918 Final RX Vref Byte 1 = 51 to rank1==
6886 11:32:37.127276 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 11:32:37.134002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:32:37.134078 ==
6889 11:32:37.134136 DQS Delay:
6890 11:32:37.134189 DQS0 = 48, DQS1 = 64
6891 11:32:37.137057 DQM Delay:
6892 11:32:37.137175 DQM0 = 11, DQM1 = 16
6893 11:32:37.140362 DQ Delay:
6894 11:32:37.144002 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6895 11:32:37.144106 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6896 11:32:37.146952 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6897 11:32:37.150623 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6898 11:32:37.150699
6899 11:32:37.150773
6900 11:32:37.160309 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6901 11:32:37.163571 CH1 RK0: MR19=C0C, MR18=8C32
6902 11:32:37.170799 CH1_RK0: MR19=0xC0C, MR18=0x8C32, DQSOSC=392, MR23=63, INC=384, DEC=256
6903 11:32:37.170878 ==
6904 11:32:37.173361 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 11:32:37.176696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 11:32:37.176771 ==
6907 11:32:37.180099 [Gating] SW mode calibration
6908 11:32:37.187244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6909 11:32:37.190127 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6910 11:32:37.196749 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 11:32:37.200219 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 11:32:37.203742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 11:32:37.210456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 11:32:37.213736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 11:32:37.216852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 11:32:37.223435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 11:32:37.226659 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 11:32:37.229960 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6919 11:32:37.233389 Total UI for P1: 0, mck2ui 16
6920 11:32:37.236705 best dqsien dly found for B0: ( 0, 14, 24)
6921 11:32:37.240544 Total UI for P1: 0, mck2ui 16
6922 11:32:37.243601 best dqsien dly found for B1: ( 0, 14, 24)
6923 11:32:37.247321 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6924 11:32:37.250420 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6925 11:32:37.250498
6926 11:32:37.257352 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 11:32:37.260186 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 11:32:37.260260 [Gating] SW calibration Done
6929 11:32:37.263529 ==
6930 11:32:37.266930 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 11:32:37.270378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 11:32:37.270449 ==
6933 11:32:37.270507 RX Vref Scan: 0
6934 11:32:37.270560
6935 11:32:37.273537 RX Vref 0 -> 0, step: 1
6936 11:32:37.273602
6937 11:32:37.277177 RX Delay -410 -> 252, step: 16
6938 11:32:37.280562 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6939 11:32:37.283823 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6940 11:32:37.290305 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6941 11:32:37.293898 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6942 11:32:37.297329 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6943 11:32:37.300820 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6944 11:32:37.307093 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6945 11:32:37.310445 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6946 11:32:37.313668 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6947 11:32:37.317445 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6948 11:32:37.324515 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6949 11:32:37.327251 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6950 11:32:37.330692 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6951 11:32:37.334047 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6952 11:32:37.340673 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6953 11:32:37.344131 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6954 11:32:37.344215 ==
6955 11:32:37.347385 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 11:32:37.350998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 11:32:37.351077 ==
6958 11:32:37.354048 DQS Delay:
6959 11:32:37.354133 DQS0 = 51, DQS1 = 51
6960 11:32:37.354210 DQM Delay:
6961 11:32:37.357364 DQM0 = 17, DQM1 = 10
6962 11:32:37.357462 DQ Delay:
6963 11:32:37.360741 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6964 11:32:37.363842 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6965 11:32:37.367443 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6966 11:32:37.370939 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6967 11:32:37.371017
6968 11:32:37.371111
6969 11:32:37.371170 ==
6970 11:32:37.374249 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 11:32:37.377586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 11:32:37.381306 ==
6973 11:32:37.381390
6974 11:32:37.381466
6975 11:32:37.381537 TX Vref Scan disable
6976 11:32:37.384330 == TX Byte 0 ==
6977 11:32:37.387431 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6978 11:32:37.390595 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6979 11:32:37.394289 == TX Byte 1 ==
6980 11:32:37.397292 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6981 11:32:37.400781 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6982 11:32:37.400882 ==
6983 11:32:37.403949 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 11:32:37.407498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 11:32:37.410676 ==
6986 11:32:37.410764
6987 11:32:37.410822
6988 11:32:37.410876 TX Vref Scan disable
6989 11:32:37.414643 == TX Byte 0 ==
6990 11:32:37.417607 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6991 11:32:37.421070 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6992 11:32:37.424467 == TX Byte 1 ==
6993 11:32:37.427550 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6994 11:32:37.431026 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6995 11:32:37.431119
6996 11:32:37.431201 [DATLAT]
6997 11:32:37.434162 Freq=400, CH1 RK1
6998 11:32:37.434251
6999 11:32:37.434330 DATLAT Default: 0xe
7000 11:32:37.437747 0, 0xFFFF, sum = 0
7001 11:32:37.441102 1, 0xFFFF, sum = 0
7002 11:32:37.441212 2, 0xFFFF, sum = 0
7003 11:32:37.444257 3, 0xFFFF, sum = 0
7004 11:32:37.444324 4, 0xFFFF, sum = 0
7005 11:32:37.447737 5, 0xFFFF, sum = 0
7006 11:32:37.447813 6, 0xFFFF, sum = 0
7007 11:32:37.451102 7, 0xFFFF, sum = 0
7008 11:32:37.451178 8, 0xFFFF, sum = 0
7009 11:32:37.454359 9, 0xFFFF, sum = 0
7010 11:32:37.454435 10, 0xFFFF, sum = 0
7011 11:32:37.457766 11, 0xFFFF, sum = 0
7012 11:32:37.457896 12, 0xFFFF, sum = 0
7013 11:32:37.461053 13, 0x0, sum = 1
7014 11:32:37.461139 14, 0x0, sum = 2
7015 11:32:37.464397 15, 0x0, sum = 3
7016 11:32:37.464472 16, 0x0, sum = 4
7017 11:32:37.464531 best_step = 14
7018 11:32:37.467865
7019 11:32:37.467938 ==
7020 11:32:37.471697 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 11:32:37.474865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 11:32:37.474940 ==
7023 11:32:37.474998 RX Vref Scan: 0
7024 11:32:37.475052
7025 11:32:37.478161 RX Vref 0 -> 0, step: 1
7026 11:32:37.478234
7027 11:32:37.480940 RX Delay -343 -> 252, step: 8
7028 11:32:37.488728 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7029 11:32:37.491568 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7030 11:32:37.494898 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7031 11:32:37.498393 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7032 11:32:37.505112 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
7033 11:32:37.508471 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7034 11:32:37.511429 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7035 11:32:37.515481 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
7036 11:32:37.521817 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7037 11:32:37.524908 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7038 11:32:37.528684 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7039 11:32:37.531860 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7040 11:32:37.538345 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7041 11:32:37.542117 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7042 11:32:37.544947 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7043 11:32:37.548730 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7044 11:32:37.552077 ==
7045 11:32:37.554979 Dram Type= 6, Freq= 0, CH_1, rank 1
7046 11:32:37.558422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7047 11:32:37.558530 ==
7048 11:32:37.558655 DQS Delay:
7049 11:32:37.562146 DQS0 = 52, DQS1 = 56
7050 11:32:37.562220 DQM Delay:
7051 11:32:37.565353 DQM0 = 13, DQM1 = 9
7052 11:32:37.565427 DQ Delay:
7053 11:32:37.568599 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7054 11:32:37.571968 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7055 11:32:37.575232 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7056 11:32:37.578623 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7057 11:32:37.578722
7058 11:32:37.578804
7059 11:32:37.585092 [DQSOSCAuto] RK1, (LSB)MR18= 0x798e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7060 11:32:37.588327 CH1 RK1: MR19=C0C, MR18=798E
7061 11:32:37.595140 CH1_RK1: MR19=0xC0C, MR18=0x798E, DQSOSC=392, MR23=63, INC=384, DEC=256
7062 11:32:37.598923 [RxdqsGatingPostProcess] freq 400
7063 11:32:37.601637 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7064 11:32:37.605281 best DQS0 dly(2T, 0.5T) = (0, 10)
7065 11:32:37.608232 best DQS1 dly(2T, 0.5T) = (0, 10)
7066 11:32:37.612047 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7067 11:32:37.615640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7068 11:32:37.618597 best DQS0 dly(2T, 0.5T) = (0, 10)
7069 11:32:37.621832 best DQS1 dly(2T, 0.5T) = (0, 10)
7070 11:32:37.625267 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7071 11:32:37.628320 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7072 11:32:37.631806 Pre-setting of DQS Precalculation
7073 11:32:37.635173 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7074 11:32:37.641977 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7075 11:32:37.652361 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7076 11:32:37.652435
7077 11:32:37.652495
7078 11:32:37.655206 [Calibration Summary] 800 Mbps
7079 11:32:37.655271 CH 0, Rank 0
7080 11:32:37.658433 SW Impedance : PASS
7081 11:32:37.658498 DUTY Scan : NO K
7082 11:32:37.661932 ZQ Calibration : PASS
7083 11:32:37.661997 Jitter Meter : NO K
7084 11:32:37.665109 CBT Training : PASS
7085 11:32:37.668726 Write leveling : PASS
7086 11:32:37.668793 RX DQS gating : PASS
7087 11:32:37.671833 RX DQ/DQS(RDDQC) : PASS
7088 11:32:37.675066 TX DQ/DQS : PASS
7089 11:32:37.675133 RX DATLAT : PASS
7090 11:32:37.678552 RX DQ/DQS(Engine): PASS
7091 11:32:37.681930 TX OE : NO K
7092 11:32:37.682016 All Pass.
7093 11:32:37.682097
7094 11:32:37.682175 CH 0, Rank 1
7095 11:32:37.685330 SW Impedance : PASS
7096 11:32:37.688902 DUTY Scan : NO K
7097 11:32:37.688994 ZQ Calibration : PASS
7098 11:32:37.691829 Jitter Meter : NO K
7099 11:32:37.695961 CBT Training : PASS
7100 11:32:37.696029 Write leveling : NO K
7101 11:32:37.698948 RX DQS gating : PASS
7102 11:32:37.699036 RX DQ/DQS(RDDQC) : PASS
7103 11:32:37.701989 TX DQ/DQS : PASS
7104 11:32:37.705366 RX DATLAT : PASS
7105 11:32:37.705440 RX DQ/DQS(Engine): PASS
7106 11:32:37.708654 TX OE : NO K
7107 11:32:37.708738 All Pass.
7108 11:32:37.708830
7109 11:32:37.712055 CH 1, Rank 0
7110 11:32:37.712130 SW Impedance : PASS
7111 11:32:37.715087 DUTY Scan : NO K
7112 11:32:37.718991 ZQ Calibration : PASS
7113 11:32:37.719066 Jitter Meter : NO K
7114 11:32:37.722125 CBT Training : PASS
7115 11:32:37.725143 Write leveling : PASS
7116 11:32:37.725231 RX DQS gating : PASS
7117 11:32:37.728562 RX DQ/DQS(RDDQC) : PASS
7118 11:32:37.731830 TX DQ/DQS : PASS
7119 11:32:37.731905 RX DATLAT : PASS
7120 11:32:37.735965 RX DQ/DQS(Engine): PASS
7121 11:32:37.738446 TX OE : NO K
7122 11:32:37.738514 All Pass.
7123 11:32:37.738570
7124 11:32:37.738622 CH 1, Rank 1
7125 11:32:37.741895 SW Impedance : PASS
7126 11:32:37.745305 DUTY Scan : NO K
7127 11:32:37.745376 ZQ Calibration : PASS
7128 11:32:37.748814 Jitter Meter : NO K
7129 11:32:37.748904 CBT Training : PASS
7130 11:32:37.752163 Write leveling : NO K
7131 11:32:37.755731 RX DQS gating : PASS
7132 11:32:37.755796 RX DQ/DQS(RDDQC) : PASS
7133 11:32:37.758956 TX DQ/DQS : PASS
7134 11:32:37.762060 RX DATLAT : PASS
7135 11:32:37.762135 RX DQ/DQS(Engine): PASS
7136 11:32:37.765078 TX OE : NO K
7137 11:32:37.765173 All Pass.
7138 11:32:37.765231
7139 11:32:37.768594 DramC Write-DBI off
7140 11:32:37.771862 PER_BANK_REFRESH: Hybrid Mode
7141 11:32:37.771937 TX_TRACKING: ON
7142 11:32:37.781723 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7143 11:32:37.785689 [FAST_K] Save calibration result to emmc
7144 11:32:37.788757 dramc_set_vcore_voltage set vcore to 725000
7145 11:32:37.792014 Read voltage for 1600, 0
7146 11:32:37.792098 Vio18 = 0
7147 11:32:37.792194 Vcore = 725000
7148 11:32:37.795189 Vdram = 0
7149 11:32:37.795263 Vddq = 0
7150 11:32:37.795322 Vmddr = 0
7151 11:32:37.801964 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7152 11:32:37.805733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7153 11:32:37.808895 MEM_TYPE=3, freq_sel=13
7154 11:32:37.812187 sv_algorithm_assistance_LP4_3733
7155 11:32:37.815486 ============ PULL DRAM RESETB DOWN ============
7156 11:32:37.818868 ========== PULL DRAM RESETB DOWN end =========
7157 11:32:37.825439 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 11:32:37.828838 ===================================
7159 11:32:37.828938 LPDDR4 DRAM CONFIGURATION
7160 11:32:37.832059 ===================================
7161 11:32:37.835918 EX_ROW_EN[0] = 0x0
7162 11:32:37.839167 EX_ROW_EN[1] = 0x0
7163 11:32:37.839268 LP4Y_EN = 0x0
7164 11:32:37.842417 WORK_FSP = 0x1
7165 11:32:37.842516 WL = 0x5
7166 11:32:37.845545 RL = 0x5
7167 11:32:37.845619 BL = 0x2
7168 11:32:37.848937 RPST = 0x0
7169 11:32:37.849064 RD_PRE = 0x0
7170 11:32:37.852424 WR_PRE = 0x1
7171 11:32:37.852497 WR_PST = 0x1
7172 11:32:37.855817 DBI_WR = 0x0
7173 11:32:37.855891 DBI_RD = 0x0
7174 11:32:37.859021 OTF = 0x1
7175 11:32:37.862289 ===================================
7176 11:32:37.865599 ===================================
7177 11:32:37.865668 ANA top config
7178 11:32:37.868707 ===================================
7179 11:32:37.872170 DLL_ASYNC_EN = 0
7180 11:32:37.875915 ALL_SLAVE_EN = 0
7181 11:32:37.875981 NEW_RANK_MODE = 1
7182 11:32:37.879370 DLL_IDLE_MODE = 1
7183 11:32:37.882186 LP45_APHY_COMB_EN = 1
7184 11:32:37.885802 TX_ODT_DIS = 0
7185 11:32:37.888910 NEW_8X_MODE = 1
7186 11:32:37.892261 ===================================
7187 11:32:37.892336 ===================================
7188 11:32:37.895742 data_rate = 3200
7189 11:32:37.899135 CKR = 1
7190 11:32:37.902234 DQ_P2S_RATIO = 8
7191 11:32:37.905583 ===================================
7192 11:32:37.909422 CA_P2S_RATIO = 8
7193 11:32:37.912356 DQ_CA_OPEN = 0
7194 11:32:37.915797 DQ_SEMI_OPEN = 0
7195 11:32:37.915882 CA_SEMI_OPEN = 0
7196 11:32:37.919054 CA_FULL_RATE = 0
7197 11:32:37.922206 DQ_CKDIV4_EN = 0
7198 11:32:37.925722 CA_CKDIV4_EN = 0
7199 11:32:37.928947 CA_PREDIV_EN = 0
7200 11:32:37.932277 PH8_DLY = 12
7201 11:32:37.932352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7202 11:32:37.935680 DQ_AAMCK_DIV = 4
7203 11:32:37.938984 CA_AAMCK_DIV = 4
7204 11:32:37.942433 CA_ADMCK_DIV = 4
7205 11:32:37.945793 DQ_TRACK_CA_EN = 0
7206 11:32:37.948926 CA_PICK = 1600
7207 11:32:37.949001 CA_MCKIO = 1600
7208 11:32:37.952496 MCKIO_SEMI = 0
7209 11:32:37.955334 PLL_FREQ = 3068
7210 11:32:37.958989 DQ_UI_PI_RATIO = 32
7211 11:32:37.962286 CA_UI_PI_RATIO = 0
7212 11:32:37.965417 ===================================
7213 11:32:37.969111 ===================================
7214 11:32:37.972254 memory_type:LPDDR4
7215 11:32:37.972335 GP_NUM : 10
7216 11:32:37.975308 SRAM_EN : 1
7217 11:32:37.975400 MD32_EN : 0
7218 11:32:37.979134 ===================================
7219 11:32:37.982252 [ANA_INIT] >>>>>>>>>>>>>>
7220 11:32:37.985574 <<<<<< [CONFIGURE PHASE]: ANA_TX
7221 11:32:37.988988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7222 11:32:37.992396 ===================================
7223 11:32:37.995291 data_rate = 3200,PCW = 0X7600
7224 11:32:37.999312 ===================================
7225 11:32:38.002110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7226 11:32:38.005391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 11:32:38.012365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 11:32:38.015573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7229 11:32:38.021984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7230 11:32:38.025702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7231 11:32:38.025778 [ANA_INIT] flow start
7232 11:32:38.028916 [ANA_INIT] PLL >>>>>>>>
7233 11:32:38.032514 [ANA_INIT] PLL <<<<<<<<
7234 11:32:38.032589 [ANA_INIT] MIDPI >>>>>>>>
7235 11:32:38.035736 [ANA_INIT] MIDPI <<<<<<<<
7236 11:32:38.039151 [ANA_INIT] DLL >>>>>>>>
7237 11:32:38.039225 [ANA_INIT] DLL <<<<<<<<
7238 11:32:38.041993 [ANA_INIT] flow end
7239 11:32:38.045605 ============ LP4 DIFF to SE enter ============
7240 11:32:38.049091 ============ LP4 DIFF to SE exit ============
7241 11:32:38.052369 [ANA_INIT] <<<<<<<<<<<<<
7242 11:32:38.055299 [Flow] Enable top DCM control >>>>>
7243 11:32:38.058770 [Flow] Enable top DCM control <<<<<
7244 11:32:38.062133 Enable DLL master slave shuffle
7245 11:32:38.068866 ==============================================================
7246 11:32:38.068940 Gating Mode config
7247 11:32:38.075302 ==============================================================
7248 11:32:38.075388 Config description:
7249 11:32:38.085799 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7250 11:32:38.092487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7251 11:32:38.098972 SELPH_MODE 0: By rank 1: By Phase
7252 11:32:38.102346 ==============================================================
7253 11:32:38.105985 GAT_TRACK_EN = 1
7254 11:32:38.109028 RX_GATING_MODE = 2
7255 11:32:38.112459 RX_GATING_TRACK_MODE = 2
7256 11:32:38.115792 SELPH_MODE = 1
7257 11:32:38.119286 PICG_EARLY_EN = 1
7258 11:32:38.122895 VALID_LAT_VALUE = 1
7259 11:32:38.125553 ==============================================================
7260 11:32:38.128881 Enter into Gating configuration >>>>
7261 11:32:38.132689 Exit from Gating configuration <<<<
7262 11:32:38.135605 Enter into DVFS_PRE_config >>>>>
7263 11:32:38.148628 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7264 11:32:38.152042 Exit from DVFS_PRE_config <<<<<
7265 11:32:38.155726 Enter into PICG configuration >>>>
7266 11:32:38.155792 Exit from PICG configuration <<<<
7267 11:32:38.159136 [RX_INPUT] configuration >>>>>
7268 11:32:38.161940 [RX_INPUT] configuration <<<<<
7269 11:32:38.169232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7270 11:32:38.172025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7271 11:32:38.179153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7272 11:32:38.185622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7273 11:32:38.191789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 11:32:38.198533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 11:32:38.202028 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7276 11:32:38.205734 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7277 11:32:38.208672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7278 11:32:38.215639 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7279 11:32:38.218838 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7280 11:32:38.221975 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 11:32:38.225410 ===================================
7282 11:32:38.228735 LPDDR4 DRAM CONFIGURATION
7283 11:32:38.232846 ===================================
7284 11:32:38.232922 EX_ROW_EN[0] = 0x0
7285 11:32:38.236025 EX_ROW_EN[1] = 0x0
7286 11:32:38.239125 LP4Y_EN = 0x0
7287 11:32:38.239191 WORK_FSP = 0x1
7288 11:32:38.242031 WL = 0x5
7289 11:32:38.242108 RL = 0x5
7290 11:32:38.245883 BL = 0x2
7291 11:32:38.245947 RPST = 0x0
7292 11:32:38.248817 RD_PRE = 0x0
7293 11:32:38.248917 WR_PRE = 0x1
7294 11:32:38.252251 WR_PST = 0x1
7295 11:32:38.252313 DBI_WR = 0x0
7296 11:32:38.255545 DBI_RD = 0x0
7297 11:32:38.255618 OTF = 0x1
7298 11:32:38.258645 ===================================
7299 11:32:38.262312 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7300 11:32:38.269077 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7301 11:32:38.271959 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 11:32:38.275324 ===================================
7303 11:32:38.278860 LPDDR4 DRAM CONFIGURATION
7304 11:32:38.282068 ===================================
7305 11:32:38.282160 EX_ROW_EN[0] = 0x10
7306 11:32:38.285276 EX_ROW_EN[1] = 0x0
7307 11:32:38.285356 LP4Y_EN = 0x0
7308 11:32:38.289136 WORK_FSP = 0x1
7309 11:32:38.289215 WL = 0x5
7310 11:32:38.292397 RL = 0x5
7311 11:32:38.292487 BL = 0x2
7312 11:32:38.296255 RPST = 0x0
7313 11:32:38.299328 RD_PRE = 0x0
7314 11:32:38.299399 WR_PRE = 0x1
7315 11:32:38.302769 WR_PST = 0x1
7316 11:32:38.302840 DBI_WR = 0x0
7317 11:32:38.305878 DBI_RD = 0x0
7318 11:32:38.305978 OTF = 0x1
7319 11:32:38.309384 ===================================
7320 11:32:38.316171 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7321 11:32:38.316309 ==
7322 11:32:38.319028 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 11:32:38.322567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 11:32:38.322728 ==
7325 11:32:38.325414 [Duty_Offset_Calibration]
7326 11:32:38.328744 B0:2 B1:-1 CA:1
7327 11:32:38.328812
7328 11:32:38.332154 [DutyScan_Calibration_Flow] k_type=0
7329 11:32:38.339950
7330 11:32:38.340042 ==CLK 0==
7331 11:32:38.343299 Final CLK duty delay cell = -4
7332 11:32:38.346454 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7333 11:32:38.349540 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7334 11:32:38.353369 [-4] AVG Duty = 4937%(X100)
7335 11:32:38.353474
7336 11:32:38.356366 CH0 CLK Duty spec in!! Max-Min= 187%
7337 11:32:38.360026 [DutyScan_Calibration_Flow] ====Done====
7338 11:32:38.360119
7339 11:32:38.362870 [DutyScan_Calibration_Flow] k_type=1
7340 11:32:38.379657
7341 11:32:38.379735 ==DQS 0 ==
7342 11:32:38.382673 Final DQS duty delay cell = 0
7343 11:32:38.385989 [0] MAX Duty = 5125%(X100), DQS PI = 56
7344 11:32:38.389004 [0] MIN Duty = 5000%(X100), DQS PI = 14
7345 11:32:38.392523 [0] AVG Duty = 5062%(X100)
7346 11:32:38.392598
7347 11:32:38.392657 ==DQS 1 ==
7348 11:32:38.395645 Final DQS duty delay cell = -4
7349 11:32:38.399492 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7350 11:32:38.402603 [-4] MIN Duty = 5031%(X100), DQS PI = 18
7351 11:32:38.405832 [-4] AVG Duty = 5062%(X100)
7352 11:32:38.405908
7353 11:32:38.409511 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7354 11:32:38.409591
7355 11:32:38.412479 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7356 11:32:38.415872 [DutyScan_Calibration_Flow] ====Done====
7357 11:32:38.415946
7358 11:32:38.419034 [DutyScan_Calibration_Flow] k_type=3
7359 11:32:38.437448
7360 11:32:38.437550 ==DQM 0 ==
7361 11:32:38.439841 Final DQM duty delay cell = 0
7362 11:32:38.443407 [0] MAX Duty = 5000%(X100), DQS PI = 20
7363 11:32:38.446710 [0] MIN Duty = 4875%(X100), DQS PI = 4
7364 11:32:38.446785 [0] AVG Duty = 4937%(X100)
7365 11:32:38.449943
7366 11:32:38.450021 ==DQM 1 ==
7367 11:32:38.453327 Final DQM duty delay cell = 0
7368 11:32:38.456813 [0] MAX Duty = 5218%(X100), DQS PI = 58
7369 11:32:38.459890 [0] MIN Duty = 4969%(X100), DQS PI = 18
7370 11:32:38.459955 [0] AVG Duty = 5093%(X100)
7371 11:32:38.463079
7372 11:32:38.466786 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7373 11:32:38.466851
7374 11:32:38.469825 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7375 11:32:38.473321 [DutyScan_Calibration_Flow] ====Done====
7376 11:32:38.473385
7377 11:32:38.476541 [DutyScan_Calibration_Flow] k_type=2
7378 11:32:38.493650
7379 11:32:38.493717 ==DQ 0 ==
7380 11:32:38.497348 Final DQ duty delay cell = 0
7381 11:32:38.500043 [0] MAX Duty = 5156%(X100), DQS PI = 0
7382 11:32:38.503296 [0] MIN Duty = 5031%(X100), DQS PI = 4
7383 11:32:38.503394 [0] AVG Duty = 5093%(X100)
7384 11:32:38.503490
7385 11:32:38.507119 ==DQ 1 ==
7386 11:32:38.507184 Final DQ duty delay cell = 0
7387 11:32:38.513729 [0] MAX Duty = 5031%(X100), DQS PI = 38
7388 11:32:38.517227 [0] MIN Duty = 4907%(X100), DQS PI = 42
7389 11:32:38.517302 [0] AVG Duty = 4969%(X100)
7390 11:32:38.517360
7391 11:32:38.520231 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7392 11:32:38.520307
7393 11:32:38.523808 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7394 11:32:38.530279 [DutyScan_Calibration_Flow] ====Done====
7395 11:32:38.530355 ==
7396 11:32:38.533490 Dram Type= 6, Freq= 0, CH_1, rank 0
7397 11:32:38.537141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7398 11:32:38.537217 ==
7399 11:32:38.540266 [Duty_Offset_Calibration]
7400 11:32:38.540341 B0:1 B1:1 CA:2
7401 11:32:38.540399
7402 11:32:38.543331 [DutyScan_Calibration_Flow] k_type=0
7403 11:32:38.553507
7404 11:32:38.553605 ==CLK 0==
7405 11:32:38.557070 Final CLK duty delay cell = 0
7406 11:32:38.560717 [0] MAX Duty = 5187%(X100), DQS PI = 24
7407 11:32:38.563696 [0] MIN Duty = 4938%(X100), DQS PI = 50
7408 11:32:38.563771 [0] AVG Duty = 5062%(X100)
7409 11:32:38.563829
7410 11:32:38.566914 CH1 CLK Duty spec in!! Max-Min= 249%
7411 11:32:38.573764 [DutyScan_Calibration_Flow] ====Done====
7412 11:32:38.573837
7413 11:32:38.577181 [DutyScan_Calibration_Flow] k_type=1
7414 11:32:38.593503
7415 11:32:38.593575 ==DQS 0 ==
7416 11:32:38.596412 Final DQS duty delay cell = 0
7417 11:32:38.600434 [0] MAX Duty = 5094%(X100), DQS PI = 20
7418 11:32:38.603365 [0] MIN Duty = 4813%(X100), DQS PI = 52
7419 11:32:38.606569 [0] AVG Duty = 4953%(X100)
7420 11:32:38.606638
7421 11:32:38.606694 ==DQS 1 ==
7422 11:32:38.610472 Final DQS duty delay cell = 0
7423 11:32:38.613052 [0] MAX Duty = 5000%(X100), DQS PI = 2
7424 11:32:38.616377 [0] MIN Duty = 4938%(X100), DQS PI = 12
7425 11:32:38.616442 [0] AVG Duty = 4969%(X100)
7426 11:32:38.619998
7427 11:32:38.623419 CH1 DQS 0 Duty spec in!! Max-Min= 281%
7428 11:32:38.623484
7429 11:32:38.626850 CH1 DQS 1 Duty spec in!! Max-Min= 62%
7430 11:32:38.630200 [DutyScan_Calibration_Flow] ====Done====
7431 11:32:38.630261
7432 11:32:38.633370 [DutyScan_Calibration_Flow] k_type=3
7433 11:32:38.650053
7434 11:32:38.650120 ==DQM 0 ==
7435 11:32:38.653411 Final DQM duty delay cell = 0
7436 11:32:38.656517 [0] MAX Duty = 5124%(X100), DQS PI = 20
7437 11:32:38.659969 [0] MIN Duty = 4813%(X100), DQS PI = 52
7438 11:32:38.663350 [0] AVG Duty = 4968%(X100)
7439 11:32:38.663414
7440 11:32:38.663474 ==DQM 1 ==
7441 11:32:38.666430 Final DQM duty delay cell = 0
7442 11:32:38.670287 [0] MAX Duty = 5156%(X100), DQS PI = 60
7443 11:32:38.673033 [0] MIN Duty = 4907%(X100), DQS PI = 20
7444 11:32:38.673142 [0] AVG Duty = 5031%(X100)
7445 11:32:38.676820
7446 11:32:38.679998 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7447 11:32:38.680073
7448 11:32:38.683053 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7449 11:32:38.686691 [DutyScan_Calibration_Flow] ====Done====
7450 11:32:38.686767
7451 11:32:38.690042 [DutyScan_Calibration_Flow] k_type=2
7452 11:32:38.706778
7453 11:32:38.706854 ==DQ 0 ==
7454 11:32:38.709913 Final DQ duty delay cell = 0
7455 11:32:38.713308 [0] MAX Duty = 5125%(X100), DQS PI = 20
7456 11:32:38.717106 [0] MIN Duty = 4907%(X100), DQS PI = 52
7457 11:32:38.717219 [0] AVG Duty = 5016%(X100)
7458 11:32:38.720385
7459 11:32:38.720459 ==DQ 1 ==
7460 11:32:38.723577 Final DQ duty delay cell = 0
7461 11:32:38.726847 [0] MAX Duty = 5093%(X100), DQS PI = 6
7462 11:32:38.729929 [0] MIN Duty = 5031%(X100), DQS PI = 0
7463 11:32:38.730004 [0] AVG Duty = 5062%(X100)
7464 11:32:38.730063
7465 11:32:38.733504 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7466 11:32:38.733580
7467 11:32:38.736844 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7468 11:32:38.743329 [DutyScan_Calibration_Flow] ====Done====
7469 11:32:38.746543 nWR fixed to 30
7470 11:32:38.746619 [ModeRegInit_LP4] CH0 RK0
7471 11:32:38.749883 [ModeRegInit_LP4] CH0 RK1
7472 11:32:38.753149 [ModeRegInit_LP4] CH1 RK0
7473 11:32:38.753225 [ModeRegInit_LP4] CH1 RK1
7474 11:32:38.756941 match AC timing 5
7475 11:32:38.760241 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7476 11:32:38.763263 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7477 11:32:38.770194 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7478 11:32:38.773594 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7479 11:32:38.779948 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7480 11:32:38.780024 [MiockJmeterHQA]
7481 11:32:38.780082
7482 11:32:38.784090 [DramcMiockJmeter] u1RxGatingPI = 0
7483 11:32:38.787012 0 : 4255, 4029
7484 11:32:38.787089 4 : 4253, 4027
7485 11:32:38.787149 8 : 4257, 4029
7486 11:32:38.790321 12 : 4363, 4138
7487 11:32:38.790397 16 : 4367, 4140
7488 11:32:38.793203 20 : 4255, 4029
7489 11:32:38.793279 24 : 4257, 4029
7490 11:32:38.796701 28 : 4253, 4027
7491 11:32:38.796778 32 : 4257, 4032
7492 11:32:38.796838 36 : 4362, 4137
7493 11:32:38.800281 40 : 4366, 4139
7494 11:32:38.800357 44 : 4371, 4142
7495 11:32:38.803431 48 : 4366, 4140
7496 11:32:38.803507 52 : 4255, 4029
7497 11:32:38.806814 56 : 4254, 4029
7498 11:32:38.806891 60 : 4252, 4029
7499 11:32:38.806951 64 : 4257, 4031
7500 11:32:38.810014 68 : 4250, 4027
7501 11:32:38.810090 72 : 4250, 4027
7502 11:32:38.813261 76 : 4250, 4027
7503 11:32:38.813337 80 : 4250, 4027
7504 11:32:38.816815 84 : 4250, 4027
7505 11:32:38.816891 88 : 4361, 4138
7506 11:32:38.820277 92 : 4250, 4026
7507 11:32:38.820352 96 : 4360, 3579
7508 11:32:38.820411 100 : 4362, 0
7509 11:32:38.823555 104 : 4250, 0
7510 11:32:38.823630 108 : 4250, 0
7511 11:32:38.826898 112 : 4252, 0
7512 11:32:38.826973 116 : 4250, 0
7513 11:32:38.827032 120 : 4255, 0
7514 11:32:38.830188 124 : 4250, 0
7515 11:32:38.830263 128 : 4361, 0
7516 11:32:38.830322 132 : 4252, 0
7517 11:32:38.833380 136 : 4249, 0
7518 11:32:38.833455 140 : 4360, 0
7519 11:32:38.837275 144 : 4363, 0
7520 11:32:38.837351 148 : 4247, 0
7521 11:32:38.837409 152 : 4255, 0
7522 11:32:38.840107 156 : 4250, 0
7523 11:32:38.840182 160 : 4255, 0
7524 11:32:38.843341 164 : 4255, 0
7525 11:32:38.843416 168 : 4250, 0
7526 11:32:38.843475 172 : 4254, 0
7527 11:32:38.847274 176 : 4252, 0
7528 11:32:38.847349 180 : 4360, 0
7529 11:32:38.850255 184 : 4250, 0
7530 11:32:38.850330 188 : 4253, 0
7531 11:32:38.850388 192 : 4250, 0
7532 11:32:38.853378 196 : 4255, 0
7533 11:32:38.853453 200 : 4250, 0
7534 11:32:38.853512 204 : 4250, 0
7535 11:32:38.857106 208 : 4250, 0
7536 11:32:38.857218 212 : 4250, 84
7537 11:32:38.860096 216 : 4252, 3683
7538 11:32:38.860170 220 : 4249, 4027
7539 11:32:38.863452 224 : 4255, 4029
7540 11:32:38.863527 228 : 4250, 4027
7541 11:32:38.866656 232 : 4361, 4137
7542 11:32:38.866731 236 : 4250, 4027
7543 11:32:38.870130 240 : 4250, 4027
7544 11:32:38.870205 244 : 4252, 4029
7545 11:32:38.870263 248 : 4252, 4029
7546 11:32:38.873349 252 : 4253, 4029
7547 11:32:38.873425 256 : 4250, 4026
7548 11:32:38.877141 260 : 4250, 4027
7549 11:32:38.877230 264 : 4363, 4140
7550 11:32:38.880416 268 : 4363, 4137
7551 11:32:38.880491 272 : 4365, 4140
7552 11:32:38.883398 276 : 4253, 4027
7553 11:32:38.883498 280 : 4363, 4139
7554 11:32:38.886751 284 : 4249, 4027
7555 11:32:38.886826 288 : 4252, 4027
7556 11:32:38.890275 292 : 4250, 4027
7557 11:32:38.890350 296 : 4255, 4029
7558 11:32:38.890408 300 : 4250, 4027
7559 11:32:38.893730 304 : 4255, 4029
7560 11:32:38.893830 308 : 4363, 4140
7561 11:32:38.896935 312 : 4250, 4027
7562 11:32:38.897009 316 : 4363, 4140
7563 11:32:38.900040 320 : 4252, 4026
7564 11:32:38.900115 324 : 4252, 4029
7565 11:32:38.903454 328 : 4255, 4030
7566 11:32:38.903530 332 : 4366, 3132
7567 11:32:38.906637 336 : 4361, 37
7568 11:32:38.906712
7569 11:32:38.906769 MIOCK jitter meter ch=0
7570 11:32:38.906822
7571 11:32:38.910274 1T = (336-100) = 236 dly cells
7572 11:32:38.916644 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7573 11:32:38.916719 ==
7574 11:32:38.920306 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 11:32:38.923371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 11:32:38.923446 ==
7577 11:32:38.930082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 11:32:38.933706 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 11:32:38.937324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 11:32:38.944125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 11:32:38.952983 [CA 0] Center 44 (14~75) winsize 62
7582 11:32:38.956495 [CA 1] Center 44 (13~75) winsize 63
7583 11:32:38.960352 [CA 2] Center 40 (11~69) winsize 59
7584 11:32:38.963298 [CA 3] Center 39 (10~69) winsize 60
7585 11:32:38.966888 [CA 4] Center 37 (8~67) winsize 60
7586 11:32:38.970250 [CA 5] Center 37 (7~67) winsize 61
7587 11:32:38.970325
7588 11:32:38.973215 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 11:32:38.973289
7590 11:32:38.976465 [CATrainingPosCal] consider 1 rank data
7591 11:32:38.980364 u2DelayCellTimex100 = 275/100 ps
7592 11:32:38.983385 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7593 11:32:38.990622 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7594 11:32:38.993609 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7595 11:32:38.996732 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7596 11:32:38.999762 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7597 11:32:39.003554 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7598 11:32:39.003628
7599 11:32:39.006769 CA PerBit enable=1, Macro0, CA PI delay=37
7600 11:32:39.006843
7601 11:32:39.009989 [CBTSetCACLKResult] CA Dly = 37
7602 11:32:39.013538 CS Dly: 11 (0~42)
7603 11:32:39.016692 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 11:32:39.020033 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 11:32:39.020107 ==
7606 11:32:39.023211 Dram Type= 6, Freq= 0, CH_0, rank 1
7607 11:32:39.026732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:32:39.026807 ==
7609 11:32:39.033317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7610 11:32:39.036711 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7611 11:32:39.043712 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7612 11:32:39.046758 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7613 11:32:39.056947 [CA 0] Center 44 (13~75) winsize 63
7614 11:32:39.060524 [CA 1] Center 43 (13~74) winsize 62
7615 11:32:39.064212 [CA 2] Center 39 (10~69) winsize 60
7616 11:32:39.067028 [CA 3] Center 38 (9~68) winsize 60
7617 11:32:39.070625 [CA 4] Center 37 (7~67) winsize 61
7618 11:32:39.073823 [CA 5] Center 36 (6~67) winsize 62
7619 11:32:39.073897
7620 11:32:39.077564 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7621 11:32:39.077663
7622 11:32:39.080780 [CATrainingPosCal] consider 2 rank data
7623 11:32:39.083999 u2DelayCellTimex100 = 275/100 ps
7624 11:32:39.087284 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7625 11:32:39.093829 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7626 11:32:39.097001 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7627 11:32:39.100345 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7628 11:32:39.103832 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7629 11:32:39.107340 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7630 11:32:39.107414
7631 11:32:39.110873 CA PerBit enable=1, Macro0, CA PI delay=37
7632 11:32:39.110947
7633 11:32:39.114051 [CBTSetCACLKResult] CA Dly = 37
7634 11:32:39.117284 CS Dly: 12 (0~44)
7635 11:32:39.120822 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7636 11:32:39.123758 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7637 11:32:39.123833
7638 11:32:39.127374 ----->DramcWriteLeveling(PI) begin...
7639 11:32:39.127450 ==
7640 11:32:39.130901 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:32:39.133956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:32:39.134031 ==
7643 11:32:39.137641 Write leveling (Byte 0): 36 => 36
7644 11:32:39.140746 Write leveling (Byte 1): 29 => 29
7645 11:32:39.144448 DramcWriteLeveling(PI) end<-----
7646 11:32:39.144523
7647 11:32:39.144581 ==
7648 11:32:39.147507 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 11:32:39.154286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 11:32:39.154362 ==
7651 11:32:39.154420 [Gating] SW mode calibration
7652 11:32:39.163876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7653 11:32:39.167638 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7654 11:32:39.170712 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 11:32:39.177606 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 11:32:39.181178 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:32:39.184892 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 11:32:39.190971 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7659 11:32:39.194393 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7660 11:32:39.197838 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7661 11:32:39.204130 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 11:32:39.207508 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 11:32:39.210833 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 11:32:39.217585 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 11:32:39.220730 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7666 11:32:39.224768 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
7667 11:32:39.227774 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7668 11:32:39.234425 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7669 11:32:39.237963 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 11:32:39.241047 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 11:32:39.247925 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 11:32:39.250870 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 11:32:39.254341 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 11:32:39.260968 1 6 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7675 11:32:39.264283 1 6 20 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7676 11:32:39.268087 1 6 24 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
7677 11:32:39.274360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 11:32:39.277864 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 11:32:39.280899 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 11:32:39.287881 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 11:32:39.291593 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 11:32:39.294791 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 11:32:39.300994 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7684 11:32:39.304740 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 11:32:39.308142 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 11:32:39.311215 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:32:39.317777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:32:39.321615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:32:39.324740 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 11:32:39.331129 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 11:32:39.334522 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 11:32:39.338376 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 11:32:39.344448 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 11:32:39.348215 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 11:32:39.352023 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 11:32:39.358427 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 11:32:39.361781 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 11:32:39.365074 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 11:32:39.368481 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7700 11:32:39.375245 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7701 11:32:39.378405 Total UI for P1: 0, mck2ui 16
7702 11:32:39.382004 best dqsien dly found for B0: ( 1, 9, 18)
7703 11:32:39.384864 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7704 11:32:39.388220 Total UI for P1: 0, mck2ui 16
7705 11:32:39.391843 best dqsien dly found for B1: ( 1, 9, 22)
7706 11:32:39.394865 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7707 11:32:39.398179 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7708 11:32:39.398253
7709 11:32:39.401624 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7710 11:32:39.408366 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7711 11:32:39.408455 [Gating] SW calibration Done
7712 11:32:39.408531 ==
7713 11:32:39.411505 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:32:39.418209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:32:39.418316 ==
7716 11:32:39.418407 RX Vref Scan: 0
7717 11:32:39.418488
7718 11:32:39.421476 RX Vref 0 -> 0, step: 1
7719 11:32:39.421599
7720 11:32:39.424602 RX Delay 0 -> 252, step: 8
7721 11:32:39.428289 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7722 11:32:39.431612 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7723 11:32:39.434835 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7724 11:32:39.438461 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7725 11:32:39.445422 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7726 11:32:39.448378 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7727 11:32:39.451439 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7728 11:32:39.455246 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7729 11:32:39.458025 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7730 11:32:39.464929 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7731 11:32:39.468266 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7732 11:32:39.471638 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7733 11:32:39.475102 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7734 11:32:39.478545 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7735 11:32:39.485187 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7736 11:32:39.488458 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7737 11:32:39.488853 ==
7738 11:32:39.491834 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 11:32:39.495330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 11:32:39.495720 ==
7741 11:32:39.498576 DQS Delay:
7742 11:32:39.498978 DQS0 = 0, DQS1 = 0
7743 11:32:39.499500 DQM Delay:
7744 11:32:39.501760 DQM0 = 132, DQM1 = 123
7745 11:32:39.502261 DQ Delay:
7746 11:32:39.505019 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7747 11:32:39.508151 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7748 11:32:39.511616 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7749 11:32:39.518402 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7750 11:32:39.518805
7751 11:32:39.519104
7752 11:32:39.519393 ==
7753 11:32:39.521580 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:32:39.525052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:32:39.525513 ==
7756 11:32:39.525818
7757 11:32:39.526096
7758 11:32:39.528179 TX Vref Scan disable
7759 11:32:39.528565 == TX Byte 0 ==
7760 11:32:39.535246 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7761 11:32:39.538166 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7762 11:32:39.538572 == TX Byte 1 ==
7763 11:32:39.545098 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7764 11:32:39.548338 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7765 11:32:39.548727 ==
7766 11:32:39.551397 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 11:32:39.554935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 11:32:39.555416 ==
7769 11:32:39.569623
7770 11:32:39.573198 TX Vref early break, caculate TX vref
7771 11:32:39.576550 TX Vref=16, minBit 7, minWin=21, winSum=366
7772 11:32:39.580016 TX Vref=18, minBit 1, minWin=22, winSum=383
7773 11:32:39.583343 TX Vref=20, minBit 1, minWin=23, winSum=395
7774 11:32:39.586698 TX Vref=22, minBit 1, minWin=24, winSum=407
7775 11:32:39.589674 TX Vref=24, minBit 7, minWin=24, winSum=414
7776 11:32:39.596457 TX Vref=26, minBit 4, minWin=25, winSum=423
7777 11:32:39.599854 TX Vref=28, minBit 5, minWin=26, winSum=432
7778 11:32:39.603119 TX Vref=30, minBit 0, minWin=26, winSum=428
7779 11:32:39.606630 TX Vref=32, minBit 0, minWin=26, winSum=426
7780 11:32:39.609789 TX Vref=34, minBit 0, minWin=24, winSum=406
7781 11:32:39.616693 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
7782 11:32:39.617084
7783 11:32:39.619969 Final TX Range 0 Vref 28
7784 11:32:39.620377
7785 11:32:39.620673 ==
7786 11:32:39.623128 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 11:32:39.626573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 11:32:39.626956 ==
7789 11:32:39.627252
7790 11:32:39.627519
7791 11:32:39.630219 TX Vref Scan disable
7792 11:32:39.633356 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7793 11:32:39.636911 == TX Byte 0 ==
7794 11:32:39.639963 u2DelayCellOfst[0]=10 cells (3 PI)
7795 11:32:39.643306 u2DelayCellOfst[1]=17 cells (5 PI)
7796 11:32:39.646508 u2DelayCellOfst[2]=7 cells (2 PI)
7797 11:32:39.649818 u2DelayCellOfst[3]=10 cells (3 PI)
7798 11:32:39.653193 u2DelayCellOfst[4]=7 cells (2 PI)
7799 11:32:39.653578 u2DelayCellOfst[5]=0 cells (0 PI)
7800 11:32:39.656358 u2DelayCellOfst[6]=17 cells (5 PI)
7801 11:32:39.659903 u2DelayCellOfst[7]=17 cells (5 PI)
7802 11:32:39.666690 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7803 11:32:39.669693 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7804 11:32:39.670074 == TX Byte 1 ==
7805 11:32:39.673684 u2DelayCellOfst[8]=0 cells (0 PI)
7806 11:32:39.676559 u2DelayCellOfst[9]=0 cells (0 PI)
7807 11:32:39.680195 u2DelayCellOfst[10]=7 cells (2 PI)
7808 11:32:39.683740 u2DelayCellOfst[11]=0 cells (0 PI)
7809 11:32:39.686766 u2DelayCellOfst[12]=10 cells (3 PI)
7810 11:32:39.690126 u2DelayCellOfst[13]=7 cells (2 PI)
7811 11:32:39.693318 u2DelayCellOfst[14]=14 cells (4 PI)
7812 11:32:39.696503 u2DelayCellOfst[15]=7 cells (2 PI)
7813 11:32:39.700457 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7814 11:32:39.703223 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7815 11:32:39.706921 DramC Write-DBI on
7816 11:32:39.707301 ==
7817 11:32:39.710542 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 11:32:39.713234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 11:32:39.713620 ==
7820 11:32:39.713934
7821 11:32:39.714213
7822 11:32:39.716622 TX Vref Scan disable
7823 11:32:39.720237 == TX Byte 0 ==
7824 11:32:39.723306 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7825 11:32:39.723689 == TX Byte 1 ==
7826 11:32:39.729970 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7827 11:32:39.730419 DramC Write-DBI off
7828 11:32:39.730744
7829 11:32:39.733503 [DATLAT]
7830 11:32:39.733885 Freq=1600, CH0 RK0
7831 11:32:39.734184
7832 11:32:39.737181 DATLAT Default: 0xf
7833 11:32:39.737565 0, 0xFFFF, sum = 0
7834 11:32:39.740679 1, 0xFFFF, sum = 0
7835 11:32:39.741263 2, 0xFFFF, sum = 0
7836 11:32:39.743864 3, 0xFFFF, sum = 0
7837 11:32:39.744254 4, 0xFFFF, sum = 0
7838 11:32:39.746904 5, 0xFFFF, sum = 0
7839 11:32:39.747322 6, 0xFFFF, sum = 0
7840 11:32:39.750223 7, 0xFFFF, sum = 0
7841 11:32:39.750610 8, 0xFFFF, sum = 0
7842 11:32:39.753617 9, 0xFFFF, sum = 0
7843 11:32:39.754071 10, 0xFFFF, sum = 0
7844 11:32:39.756692 11, 0xFFFF, sum = 0
7845 11:32:39.757143 12, 0xFFFF, sum = 0
7846 11:32:39.760006 13, 0xFFFF, sum = 0
7847 11:32:39.760422 14, 0x0, sum = 1
7848 11:32:39.763224 15, 0x0, sum = 2
7849 11:32:39.763612 16, 0x0, sum = 3
7850 11:32:39.766560 17, 0x0, sum = 4
7851 11:32:39.766982 best_step = 15
7852 11:32:39.767281
7853 11:32:39.767587 ==
7854 11:32:39.769936 Dram Type= 6, Freq= 0, CH_0, rank 0
7855 11:32:39.776953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7856 11:32:39.777537 ==
7857 11:32:39.777902 RX Vref Scan: 1
7858 11:32:39.778187
7859 11:32:39.780310 Set Vref Range= 24 -> 127
7860 11:32:39.780730
7861 11:32:39.783393 RX Vref 24 -> 127, step: 1
7862 11:32:39.783803
7863 11:32:39.784304 RX Delay 11 -> 252, step: 4
7864 11:32:39.784606
7865 11:32:39.787173 Set Vref, RX VrefLevel [Byte0]: 24
7866 11:32:39.790523 [Byte1]: 24
7867 11:32:39.793999
7868 11:32:39.794381 Set Vref, RX VrefLevel [Byte0]: 25
7869 11:32:39.797722 [Byte1]: 25
7870 11:32:39.801741
7871 11:32:39.802131 Set Vref, RX VrefLevel [Byte0]: 26
7872 11:32:39.805421 [Byte1]: 26
7873 11:32:39.809434
7874 11:32:39.809813 Set Vref, RX VrefLevel [Byte0]: 27
7875 11:32:39.813337 [Byte1]: 27
7876 11:32:39.816891
7877 11:32:39.817333 Set Vref, RX VrefLevel [Byte0]: 28
7878 11:32:39.820488 [Byte1]: 28
7879 11:32:39.824483
7880 11:32:39.824904 Set Vref, RX VrefLevel [Byte0]: 29
7881 11:32:39.828133 [Byte1]: 29
7882 11:32:39.832358
7883 11:32:39.832742 Set Vref, RX VrefLevel [Byte0]: 30
7884 11:32:39.836129 [Byte1]: 30
7885 11:32:39.839865
7886 11:32:39.840274 Set Vref, RX VrefLevel [Byte0]: 31
7887 11:32:39.843251 [Byte1]: 31
7888 11:32:39.847547
7889 11:32:39.847999 Set Vref, RX VrefLevel [Byte0]: 32
7890 11:32:39.851129 [Byte1]: 32
7891 11:32:39.855375
7892 11:32:39.855930 Set Vref, RX VrefLevel [Byte0]: 33
7893 11:32:39.858599 [Byte1]: 33
7894 11:32:39.862554
7895 11:32:39.862975 Set Vref, RX VrefLevel [Byte0]: 34
7896 11:32:39.866384 [Byte1]: 34
7897 11:32:39.870607
7898 11:32:39.870989 Set Vref, RX VrefLevel [Byte0]: 35
7899 11:32:39.873875 [Byte1]: 35
7900 11:32:39.877823
7901 11:32:39.878238 Set Vref, RX VrefLevel [Byte0]: 36
7902 11:32:39.881214 [Byte1]: 36
7903 11:32:39.885830
7904 11:32:39.886210 Set Vref, RX VrefLevel [Byte0]: 37
7905 11:32:39.889077 [Byte1]: 37
7906 11:32:39.893337
7907 11:32:39.893719 Set Vref, RX VrefLevel [Byte0]: 38
7908 11:32:39.896424 [Byte1]: 38
7909 11:32:39.900968
7910 11:32:39.901443 Set Vref, RX VrefLevel [Byte0]: 39
7911 11:32:39.904449 [Byte1]: 39
7912 11:32:39.908908
7913 11:32:39.909330 Set Vref, RX VrefLevel [Byte0]: 40
7914 11:32:39.911859 [Byte1]: 40
7915 11:32:39.916260
7916 11:32:39.916636 Set Vref, RX VrefLevel [Byte0]: 41
7917 11:32:39.919421 [Byte1]: 41
7918 11:32:39.923628
7919 11:32:39.924044 Set Vref, RX VrefLevel [Byte0]: 42
7920 11:32:39.927008 [Byte1]: 42
7921 11:32:39.931604
7922 11:32:39.932066 Set Vref, RX VrefLevel [Byte0]: 43
7923 11:32:39.935186 [Byte1]: 43
7924 11:32:39.938769
7925 11:32:39.939237 Set Vref, RX VrefLevel [Byte0]: 44
7926 11:32:39.942138 [Byte1]: 44
7927 11:32:39.946580
7928 11:32:39.947083 Set Vref, RX VrefLevel [Byte0]: 45
7929 11:32:39.950014 [Byte1]: 45
7930 11:32:39.954393
7931 11:32:39.954893 Set Vref, RX VrefLevel [Byte0]: 46
7932 11:32:39.958322 [Byte1]: 46
7933 11:32:39.962101
7934 11:32:39.962596 Set Vref, RX VrefLevel [Byte0]: 47
7935 11:32:39.965463 [Byte1]: 47
7936 11:32:39.969484
7937 11:32:39.969862 Set Vref, RX VrefLevel [Byte0]: 48
7938 11:32:39.972952 [Byte1]: 48
7939 11:32:39.976933
7940 11:32:39.977396 Set Vref, RX VrefLevel [Byte0]: 49
7941 11:32:39.980517 [Byte1]: 49
7942 11:32:39.984385
7943 11:32:39.984806 Set Vref, RX VrefLevel [Byte0]: 50
7944 11:32:39.988114 [Byte1]: 50
7945 11:32:39.992220
7946 11:32:39.992664 Set Vref, RX VrefLevel [Byte0]: 51
7947 11:32:39.995406 [Byte1]: 51
7948 11:32:40.000208
7949 11:32:40.000583 Set Vref, RX VrefLevel [Byte0]: 52
7950 11:32:40.003454 [Byte1]: 52
7951 11:32:40.007217
7952 11:32:40.007639 Set Vref, RX VrefLevel [Byte0]: 53
7953 11:32:40.010587 [Byte1]: 53
7954 11:32:40.015027
7955 11:32:40.015414 Set Vref, RX VrefLevel [Byte0]: 54
7956 11:32:40.018349 [Byte1]: 54
7957 11:32:40.022804
7958 11:32:40.023188 Set Vref, RX VrefLevel [Byte0]: 55
7959 11:32:40.026184 [Byte1]: 55
7960 11:32:40.030336
7961 11:32:40.030844 Set Vref, RX VrefLevel [Byte0]: 56
7962 11:32:40.033488 [Byte1]: 56
7963 11:32:40.037593
7964 11:32:40.037980 Set Vref, RX VrefLevel [Byte0]: 57
7965 11:32:40.041039 [Byte1]: 57
7966 11:32:40.045654
7967 11:32:40.046037 Set Vref, RX VrefLevel [Byte0]: 58
7968 11:32:40.048904 [Byte1]: 58
7969 11:32:40.052847
7970 11:32:40.053263 Set Vref, RX VrefLevel [Byte0]: 59
7971 11:32:40.056230 [Byte1]: 59
7972 11:32:40.060695
7973 11:32:40.061080 Set Vref, RX VrefLevel [Byte0]: 60
7974 11:32:40.063898 [Byte1]: 60
7975 11:32:40.068379
7976 11:32:40.068765 Set Vref, RX VrefLevel [Byte0]: 61
7977 11:32:40.071603 [Byte1]: 61
7978 11:32:40.075780
7979 11:32:40.076163 Set Vref, RX VrefLevel [Byte0]: 62
7980 11:32:40.079180 [Byte1]: 62
7981 11:32:40.083639
7982 11:32:40.084023 Set Vref, RX VrefLevel [Byte0]: 63
7983 11:32:40.086678 [Byte1]: 63
7984 11:32:40.091335
7985 11:32:40.091717 Set Vref, RX VrefLevel [Byte0]: 64
7986 11:32:40.094435 [Byte1]: 64
7987 11:32:40.098696
7988 11:32:40.099098 Set Vref, RX VrefLevel [Byte0]: 65
7989 11:32:40.101925 [Byte1]: 65
7990 11:32:40.106545
7991 11:32:40.106942 Set Vref, RX VrefLevel [Byte0]: 66
7992 11:32:40.109602 [Byte1]: 66
7993 11:32:40.113914
7994 11:32:40.114317 Set Vref, RX VrefLevel [Byte0]: 67
7995 11:32:40.116920 [Byte1]: 67
7996 11:32:40.121224
7997 11:32:40.121509 Set Vref, RX VrefLevel [Byte0]: 68
7998 11:32:40.124758 [Byte1]: 68
7999 11:32:40.129238
8000 11:32:40.129524 Set Vref, RX VrefLevel [Byte0]: 69
8001 11:32:40.132177 [Byte1]: 69
8002 11:32:40.137255
8003 11:32:40.137537 Set Vref, RX VrefLevel [Byte0]: 70
8004 11:32:40.140261 [Byte1]: 70
8005 11:32:40.144148
8006 11:32:40.144430 Set Vref, RX VrefLevel [Byte0]: 71
8007 11:32:40.147735 [Byte1]: 71
8008 11:32:40.152380
8009 11:32:40.152662 Set Vref, RX VrefLevel [Byte0]: 72
8010 11:32:40.155303 [Byte1]: 72
8011 11:32:40.159303
8012 11:32:40.159585 Set Vref, RX VrefLevel [Byte0]: 73
8013 11:32:40.162861 [Byte1]: 73
8014 11:32:40.167348
8015 11:32:40.167746 Set Vref, RX VrefLevel [Byte0]: 74
8016 11:32:40.170408 [Byte1]: 74
8017 11:32:40.175007
8018 11:32:40.175404 Set Vref, RX VrefLevel [Byte0]: 75
8019 11:32:40.178254 [Byte1]: 75
8020 11:32:40.182906
8021 11:32:40.183379 Set Vref, RX VrefLevel [Byte0]: 76
8022 11:32:40.185613 [Byte1]: 76
8023 11:32:40.189910
8024 11:32:40.190311 Final RX Vref Byte 0 = 63 to rank0
8025 11:32:40.193181 Final RX Vref Byte 1 = 61 to rank0
8026 11:32:40.196490 Final RX Vref Byte 0 = 63 to rank1
8027 11:32:40.200209 Final RX Vref Byte 1 = 61 to rank1==
8028 11:32:40.203079 Dram Type= 6, Freq= 0, CH_0, rank 0
8029 11:32:40.206574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 11:32:40.210054 ==
8031 11:32:40.210452 DQS Delay:
8032 11:32:40.210849 DQS0 = 0, DQS1 = 0
8033 11:32:40.213238 DQM Delay:
8034 11:32:40.213638 DQM0 = 129, DQM1 = 121
8035 11:32:40.217265 DQ Delay:
8036 11:32:40.220289 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8037 11:32:40.223453 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8038 11:32:40.226957 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8039 11:32:40.230478 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8040 11:32:40.230861
8041 11:32:40.231156
8042 11:32:40.231515
8043 11:32:40.233523 [DramC_TX_OE_Calibration] TA2
8044 11:32:40.236765 Original DQ_B0 (3 6) =30, OEN = 27
8045 11:32:40.240470 Original DQ_B1 (3 6) =30, OEN = 27
8046 11:32:40.243355 24, 0x0, End_B0=24 End_B1=24
8047 11:32:40.243766 25, 0x0, End_B0=25 End_B1=25
8048 11:32:40.246983 26, 0x0, End_B0=26 End_B1=26
8049 11:32:40.250624 27, 0x0, End_B0=27 End_B1=27
8050 11:32:40.253878 28, 0x0, End_B0=28 End_B1=28
8051 11:32:40.254284 29, 0x0, End_B0=29 End_B1=29
8052 11:32:40.257154 30, 0x0, End_B0=30 End_B1=30
8053 11:32:40.260418 31, 0x4141, End_B0=30 End_B1=30
8054 11:32:40.263720 Byte0 end_step=30 best_step=27
8055 11:32:40.266957 Byte1 end_step=30 best_step=27
8056 11:32:40.270087 Byte0 TX OE(2T, 0.5T) = (3, 3)
8057 11:32:40.270487 Byte1 TX OE(2T, 0.5T) = (3, 3)
8058 11:32:40.270888
8059 11:32:40.271263
8060 11:32:40.280449 [DQSOSCAuto] RK0, (LSB)MR18= 0x1409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8061 11:32:40.283904 CH0 RK0: MR19=303, MR18=1409
8062 11:32:40.287133 CH0_RK0: MR19=0x303, MR18=0x1409, DQSOSC=399, MR23=63, INC=23, DEC=15
8063 11:32:40.290677
8064 11:32:40.293551 ----->DramcWriteLeveling(PI) begin...
8065 11:32:40.293974 ==
8066 11:32:40.297010 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 11:32:40.300228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 11:32:40.300667 ==
8069 11:32:40.303767 Write leveling (Byte 0): 32 => 32
8070 11:32:40.307211 Write leveling (Byte 1): 24 => 24
8071 11:32:40.310704 DramcWriteLeveling(PI) end<-----
8072 11:32:40.311208
8073 11:32:40.311639 ==
8074 11:32:40.313669 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 11:32:40.317232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 11:32:40.317641 ==
8077 11:32:40.320345 [Gating] SW mode calibration
8078 11:32:40.327044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8079 11:32:40.333438 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8080 11:32:40.336844 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 11:32:40.340351 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 11:32:40.346790 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8083 11:32:40.350475 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8084 11:32:40.353511 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8085 11:32:40.357020 1 4 20 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8086 11:32:40.363432 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 11:32:40.366811 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 11:32:40.370204 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 11:32:40.376859 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8090 11:32:40.380238 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8091 11:32:40.383641 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8092 11:32:40.390498 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8093 11:32:40.393678 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8094 11:32:40.397250 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8095 11:32:40.403822 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 11:32:40.406949 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 11:32:40.410304 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 11:32:40.417021 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8099 11:32:40.420049 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8100 11:32:40.423807 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8101 11:32:40.430527 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8102 11:32:40.433513 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 11:32:40.436962 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 11:32:40.443517 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 11:32:40.447136 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 11:32:40.450830 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8107 11:32:40.454010 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 11:32:40.460583 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8109 11:32:40.463898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 11:32:40.467053 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:32:40.473972 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:32:40.476762 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:32:40.480601 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:32:40.487160 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 11:32:40.490015 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:32:40.493514 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 11:32:40.500111 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 11:32:40.503596 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 11:32:40.507017 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 11:32:40.513253 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 11:32:40.516653 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 11:32:40.520083 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8123 11:32:40.526737 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 11:32:40.529960 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 11:32:40.533342 Total UI for P1: 0, mck2ui 16
8126 11:32:40.536505 best dqsien dly found for B0: ( 1, 9, 10)
8127 11:32:40.539929 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 11:32:40.547185 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 11:32:40.547574 Total UI for P1: 0, mck2ui 16
8130 11:32:40.550436 best dqsien dly found for B1: ( 1, 9, 18)
8131 11:32:40.557175 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8132 11:32:40.559995 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8133 11:32:40.560564
8134 11:32:40.563923 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8135 11:32:40.566963 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8136 11:32:40.570555 [Gating] SW calibration Done
8137 11:32:40.571059 ==
8138 11:32:40.573401 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 11:32:40.577178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 11:32:40.577573 ==
8141 11:32:40.580116 RX Vref Scan: 0
8142 11:32:40.580501
8143 11:32:40.580821 RX Vref 0 -> 0, step: 1
8144 11:32:40.581107
8145 11:32:40.584018 RX Delay 0 -> 252, step: 8
8146 11:32:40.586839 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8147 11:32:40.589976 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8148 11:32:40.596807 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8149 11:32:40.600204 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8150 11:32:40.604127 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8151 11:32:40.606848 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8152 11:32:40.610132 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8153 11:32:40.617039 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8154 11:32:40.620116 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8155 11:32:40.623412 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8156 11:32:40.626840 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8157 11:32:40.630445 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8158 11:32:40.636955 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8159 11:32:40.640323 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8160 11:32:40.643727 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8161 11:32:40.647344 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8162 11:32:40.647732 ==
8163 11:32:40.650432 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 11:32:40.653816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 11:32:40.657434 ==
8166 11:32:40.657820 DQS Delay:
8167 11:32:40.658122 DQS0 = 0, DQS1 = 0
8168 11:32:40.660260 DQM Delay:
8169 11:32:40.660644 DQM0 = 131, DQM1 = 123
8170 11:32:40.663919 DQ Delay:
8171 11:32:40.667047 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8172 11:32:40.670598 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8173 11:32:40.674118 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8174 11:32:40.677052 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8175 11:32:40.677482
8176 11:32:40.677786
8177 11:32:40.678067 ==
8178 11:32:40.680721 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 11:32:40.684094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 11:32:40.684557 ==
8181 11:32:40.684861
8182 11:32:40.685154
8183 11:32:40.686981 TX Vref Scan disable
8184 11:32:40.690682 == TX Byte 0 ==
8185 11:32:40.694314 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8186 11:32:40.697302 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8187 11:32:40.700723 == TX Byte 1 ==
8188 11:32:40.703820 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8189 11:32:40.707095 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8190 11:32:40.707491 ==
8191 11:32:40.710647 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:32:40.717217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:32:40.717673 ==
8194 11:32:40.731050
8195 11:32:40.734246 TX Vref early break, caculate TX vref
8196 11:32:40.737245 TX Vref=16, minBit 0, minWin=22, winSum=370
8197 11:32:40.740795 TX Vref=18, minBit 3, minWin=23, winSum=381
8198 11:32:40.744544 TX Vref=20, minBit 8, minWin=23, winSum=390
8199 11:32:40.747501 TX Vref=22, minBit 0, minWin=24, winSum=401
8200 11:32:40.750981 TX Vref=24, minBit 9, minWin=24, winSum=407
8201 11:32:40.757202 TX Vref=26, minBit 3, minWin=25, winSum=414
8202 11:32:40.761284 TX Vref=28, minBit 7, minWin=25, winSum=422
8203 11:32:40.764164 TX Vref=30, minBit 13, minWin=25, winSum=420
8204 11:32:40.767436 TX Vref=32, minBit 4, minWin=24, winSum=410
8205 11:32:40.771363 TX Vref=34, minBit 8, minWin=24, winSum=405
8206 11:32:40.774200 TX Vref=36, minBit 0, minWin=24, winSum=394
8207 11:32:40.780825 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28
8208 11:32:40.781289
8209 11:32:40.783933 Final TX Range 0 Vref 28
8210 11:32:40.784349
8211 11:32:40.784677 ==
8212 11:32:40.787287 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 11:32:40.790581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 11:32:40.790972 ==
8215 11:32:40.791283
8216 11:32:40.791563
8217 11:32:40.793657 TX Vref Scan disable
8218 11:32:40.800799 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8219 11:32:40.801245 == TX Byte 0 ==
8220 11:32:40.804160 u2DelayCellOfst[0]=14 cells (4 PI)
8221 11:32:40.807751 u2DelayCellOfst[1]=21 cells (6 PI)
8222 11:32:40.810957 u2DelayCellOfst[2]=10 cells (3 PI)
8223 11:32:40.814060 u2DelayCellOfst[3]=14 cells (4 PI)
8224 11:32:40.817515 u2DelayCellOfst[4]=10 cells (3 PI)
8225 11:32:40.820856 u2DelayCellOfst[5]=0 cells (0 PI)
8226 11:32:40.823880 u2DelayCellOfst[6]=21 cells (6 PI)
8227 11:32:40.827217 u2DelayCellOfst[7]=17 cells (5 PI)
8228 11:32:40.830849 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8229 11:32:40.834456 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8230 11:32:40.837412 == TX Byte 1 ==
8231 11:32:40.840870 u2DelayCellOfst[8]=0 cells (0 PI)
8232 11:32:40.841297 u2DelayCellOfst[9]=3 cells (1 PI)
8233 11:32:40.844338 u2DelayCellOfst[10]=10 cells (3 PI)
8234 11:32:40.847319 u2DelayCellOfst[11]=3 cells (1 PI)
8235 11:32:40.851116 u2DelayCellOfst[12]=14 cells (4 PI)
8236 11:32:40.854155 u2DelayCellOfst[13]=10 cells (3 PI)
8237 11:32:40.857468 u2DelayCellOfst[14]=17 cells (5 PI)
8238 11:32:40.860970 u2DelayCellOfst[15]=14 cells (4 PI)
8239 11:32:40.863979 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8240 11:32:40.870851 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8241 11:32:40.871244 DramC Write-DBI on
8242 11:32:40.871547 ==
8243 11:32:40.874375 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 11:32:40.880504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 11:32:40.880897 ==
8246 11:32:40.881294
8247 11:32:40.881706
8248 11:32:40.882156 TX Vref Scan disable
8249 11:32:40.884838 == TX Byte 0 ==
8250 11:32:40.888341 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8251 11:32:40.891492 == TX Byte 1 ==
8252 11:32:40.894788 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8253 11:32:40.895181 DramC Write-DBI off
8254 11:32:40.898437
8255 11:32:40.898824 [DATLAT]
8256 11:32:40.899126 Freq=1600, CH0 RK1
8257 11:32:40.899405
8258 11:32:40.900960 DATLAT Default: 0xf
8259 11:32:40.901393 0, 0xFFFF, sum = 0
8260 11:32:40.904926 1, 0xFFFF, sum = 0
8261 11:32:40.905372 2, 0xFFFF, sum = 0
8262 11:32:40.908231 3, 0xFFFF, sum = 0
8263 11:32:40.910945 4, 0xFFFF, sum = 0
8264 11:32:40.911343 5, 0xFFFF, sum = 0
8265 11:32:40.914615 6, 0xFFFF, sum = 0
8266 11:32:40.915038 7, 0xFFFF, sum = 0
8267 11:32:40.917579 8, 0xFFFF, sum = 0
8268 11:32:40.917971 9, 0xFFFF, sum = 0
8269 11:32:40.921090 10, 0xFFFF, sum = 0
8270 11:32:40.921525 11, 0xFFFF, sum = 0
8271 11:32:40.924449 12, 0xFFFF, sum = 0
8272 11:32:40.924841 13, 0xFFFF, sum = 0
8273 11:32:40.927810 14, 0x0, sum = 1
8274 11:32:40.928307 15, 0x0, sum = 2
8275 11:32:40.930938 16, 0x0, sum = 3
8276 11:32:40.931286 17, 0x0, sum = 4
8277 11:32:40.934618 best_step = 15
8278 11:32:40.935140
8279 11:32:40.935449 ==
8280 11:32:40.937794 Dram Type= 6, Freq= 0, CH_0, rank 1
8281 11:32:40.941084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 11:32:40.941615 ==
8283 11:32:40.942010 RX Vref Scan: 0
8284 11:32:40.942302
8285 11:32:40.944648 RX Vref 0 -> 0, step: 1
8286 11:32:40.945202
8287 11:32:40.947503 RX Delay 3 -> 252, step: 4
8288 11:32:40.950866 iDelay=191, Bit 0, Center 130 (75 ~ 186) 112
8289 11:32:40.958011 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8290 11:32:40.961338 iDelay=191, Bit 2, Center 126 (71 ~ 182) 112
8291 11:32:40.964863 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8292 11:32:40.967992 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8293 11:32:40.971213 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8294 11:32:40.974192 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8295 11:32:40.981164 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8296 11:32:40.984436 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8297 11:32:40.988255 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8298 11:32:40.991366 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8299 11:32:40.998179 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8300 11:32:41.001081 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8301 11:32:41.004108 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8302 11:32:41.008091 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8303 11:32:41.011620 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8304 11:32:41.012138 ==
8305 11:32:41.014252 Dram Type= 6, Freq= 0, CH_0, rank 1
8306 11:32:41.021309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:32:41.021874 ==
8308 11:32:41.022312 DQS Delay:
8309 11:32:41.024851 DQS0 = 0, DQS1 = 0
8310 11:32:41.025319 DQM Delay:
8311 11:32:41.027792 DQM0 = 128, DQM1 = 122
8312 11:32:41.028296 DQ Delay:
8313 11:32:41.030951 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =126
8314 11:32:41.034513 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8315 11:32:41.037793 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8316 11:32:41.041190 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8317 11:32:41.041589
8318 11:32:41.041890
8319 11:32:41.042186
8320 11:32:41.044217 [DramC_TX_OE_Calibration] TA2
8321 11:32:41.047689 Original DQ_B0 (3 6) =30, OEN = 27
8322 11:32:41.051373 Original DQ_B1 (3 6) =30, OEN = 27
8323 11:32:41.054795 24, 0x0, End_B0=24 End_B1=24
8324 11:32:41.055196 25, 0x0, End_B0=25 End_B1=25
8325 11:32:41.057878 26, 0x0, End_B0=26 End_B1=26
8326 11:32:41.061265 27, 0x0, End_B0=27 End_B1=27
8327 11:32:41.064603 28, 0x0, End_B0=28 End_B1=28
8328 11:32:41.067567 29, 0x0, End_B0=29 End_B1=29
8329 11:32:41.068005 30, 0x0, End_B0=30 End_B1=30
8330 11:32:41.071022 31, 0x4141, End_B0=30 End_B1=30
8331 11:32:41.074512 Byte0 end_step=30 best_step=27
8332 11:32:41.077550 Byte1 end_step=30 best_step=27
8333 11:32:41.080944 Byte0 TX OE(2T, 0.5T) = (3, 3)
8334 11:32:41.084287 Byte1 TX OE(2T, 0.5T) = (3, 3)
8335 11:32:41.084698
8336 11:32:41.084992
8337 11:32:41.091240 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8338 11:32:41.094771 CH0 RK1: MR19=303, MR18=180D
8339 11:32:41.101279 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8340 11:32:41.105001 [RxdqsGatingPostProcess] freq 1600
8341 11:32:41.108304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8342 11:32:41.111304 best DQS0 dly(2T, 0.5T) = (1, 1)
8343 11:32:41.114372 best DQS1 dly(2T, 0.5T) = (1, 1)
8344 11:32:41.118026 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8345 11:32:41.121021 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8346 11:32:41.124530 best DQS0 dly(2T, 0.5T) = (1, 1)
8347 11:32:41.127716 best DQS1 dly(2T, 0.5T) = (1, 1)
8348 11:32:41.131102 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8349 11:32:41.134509 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8350 11:32:41.134923 Pre-setting of DQS Precalculation
8351 11:32:41.141160 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8352 11:32:41.141615 ==
8353 11:32:41.144395 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 11:32:41.147619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 11:32:41.148083 ==
8356 11:32:41.154498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 11:32:41.157672 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 11:32:41.161333 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 11:32:41.167611 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 11:32:41.177373 [CA 0] Center 42 (14~71) winsize 58
8361 11:32:41.180802 [CA 1] Center 42 (13~71) winsize 59
8362 11:32:41.184408 [CA 2] Center 37 (9~66) winsize 58
8363 11:32:41.187532 [CA 3] Center 35 (6~65) winsize 60
8364 11:32:41.191107 [CA 4] Center 37 (8~67) winsize 60
8365 11:32:41.194163 [CA 5] Center 36 (7~66) winsize 60
8366 11:32:41.194547
8367 11:32:41.197964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8368 11:32:41.198351
8369 11:32:41.200964 [CATrainingPosCal] consider 1 rank data
8370 11:32:41.204235 u2DelayCellTimex100 = 275/100 ps
8371 11:32:41.207555 CA0 delay=42 (14~71),Diff = 7 PI (24 cell)
8372 11:32:41.214601 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8373 11:32:41.217631 CA2 delay=37 (9~66),Diff = 2 PI (7 cell)
8374 11:32:41.220794 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8375 11:32:41.224231 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8376 11:32:41.227475 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8377 11:32:41.227752
8378 11:32:41.230607 CA PerBit enable=1, Macro0, CA PI delay=35
8379 11:32:41.230817
8380 11:32:41.234203 [CBTSetCACLKResult] CA Dly = 35
8381 11:32:41.234410 CS Dly: 8 (0~39)
8382 11:32:41.240727 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 11:32:41.244178 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 11:32:41.244440 ==
8385 11:32:41.247804 Dram Type= 6, Freq= 0, CH_1, rank 1
8386 11:32:41.251459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 11:32:41.251668 ==
8388 11:32:41.257346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8389 11:32:41.260921 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8390 11:32:41.264226 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8391 11:32:41.271222 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8392 11:32:41.280302 [CA 0] Center 42 (13~72) winsize 60
8393 11:32:41.283919 [CA 1] Center 42 (14~71) winsize 58
8394 11:32:41.287653 [CA 2] Center 37 (9~66) winsize 58
8395 11:32:41.291008 [CA 3] Center 37 (8~66) winsize 59
8396 11:32:41.293976 [CA 4] Center 37 (8~67) winsize 60
8397 11:32:41.297456 [CA 5] Center 36 (7~66) winsize 60
8398 11:32:41.297836
8399 11:32:41.300724 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8400 11:32:41.301146
8401 11:32:41.304319 [CATrainingPosCal] consider 2 rank data
8402 11:32:41.307484 u2DelayCellTimex100 = 275/100 ps
8403 11:32:41.310746 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8404 11:32:41.318021 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8405 11:32:41.320757 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8406 11:32:41.323786 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8407 11:32:41.327550 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8408 11:32:41.330771 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8409 11:32:41.331267
8410 11:32:41.334115 CA PerBit enable=1, Macro0, CA PI delay=36
8411 11:32:41.334501
8412 11:32:41.337513 [CBTSetCACLKResult] CA Dly = 36
8413 11:32:41.337974 CS Dly: 10 (0~44)
8414 11:32:41.344106 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8415 11:32:41.347536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8416 11:32:41.347963
8417 11:32:41.351168 ----->DramcWriteLeveling(PI) begin...
8418 11:32:41.351559 ==
8419 11:32:41.353996 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 11:32:41.357692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 11:32:41.358082 ==
8422 11:32:41.360600 Write leveling (Byte 0): 25 => 25
8423 11:32:41.363995 Write leveling (Byte 1): 27 => 27
8424 11:32:41.367471 DramcWriteLeveling(PI) end<-----
8425 11:32:41.367855
8426 11:32:41.368149 ==
8427 11:32:41.370829 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 11:32:41.374413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 11:32:41.377563 ==
8430 11:32:41.377959 [Gating] SW mode calibration
8431 11:32:41.384714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8432 11:32:41.391021 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8433 11:32:41.394203 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 11:32:41.400838 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 11:32:41.404337 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 11:32:41.407761 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:32:41.414605 1 4 16 | B1->B0 | 2625 2323 | 1 0 | (1 1) (0 0)
8438 11:32:41.418149 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 11:32:41.421020 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 11:32:41.428019 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 11:32:41.431266 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 11:32:41.434193 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 11:32:41.438193 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 11:32:41.444680 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8445 11:32:41.448027 1 5 16 | B1->B0 | 2d2d 3232 | 1 0 | (1 0) (0 1)
8446 11:32:41.451199 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 11:32:41.457658 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 11:32:41.461219 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 11:32:41.464612 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 11:32:41.471460 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 11:32:41.474555 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 11:32:41.478438 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 11:32:41.484935 1 6 16 | B1->B0 | 3636 2b2b | 1 0 | (0 0) (0 0)
8454 11:32:41.487963 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 11:32:41.491227 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 11:32:41.497861 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 11:32:41.500991 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 11:32:41.504256 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 11:32:41.511492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 11:32:41.514200 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 11:32:41.518130 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8462 11:32:41.521191 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8463 11:32:41.528060 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:32:41.531346 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:32:41.534676 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:32:41.541542 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 11:32:41.544711 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 11:32:41.547944 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 11:32:41.554376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 11:32:41.558153 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 11:32:41.561361 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 11:32:41.567966 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 11:32:41.571374 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 11:32:41.574536 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 11:32:41.581842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 11:32:41.584727 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8477 11:32:41.588289 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8478 11:32:41.594758 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 11:32:41.597552 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 11:32:41.601429 Total UI for P1: 0, mck2ui 16
8481 11:32:41.604733 best dqsien dly found for B0: ( 1, 9, 16)
8482 11:32:41.608076 Total UI for P1: 0, mck2ui 16
8483 11:32:41.611616 best dqsien dly found for B1: ( 1, 9, 18)
8484 11:32:41.614638 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8485 11:32:41.618526 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8486 11:32:41.618944
8487 11:32:41.621291 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8488 11:32:41.624516 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8489 11:32:41.627991 [Gating] SW calibration Done
8490 11:32:41.628492 ==
8491 11:32:41.632004 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 11:32:41.634854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 11:32:41.635366 ==
8494 11:32:41.637845 RX Vref Scan: 0
8495 11:32:41.638248
8496 11:32:41.641254 RX Vref 0 -> 0, step: 1
8497 11:32:41.641637
8498 11:32:41.641950 RX Delay 0 -> 252, step: 8
8499 11:32:41.647979 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8500 11:32:41.651474 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8501 11:32:41.654817 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8502 11:32:41.658004 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8503 11:32:41.661427 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8504 11:32:41.664877 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8505 11:32:41.671287 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8506 11:32:41.674842 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8507 11:32:41.678317 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8508 11:32:41.680978 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8509 11:32:41.684597 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8510 11:32:41.690958 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8511 11:32:41.694527 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8512 11:32:41.698291 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8513 11:32:41.701463 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8514 11:32:41.707784 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8515 11:32:41.708295 ==
8516 11:32:41.711351 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 11:32:41.714590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 11:32:41.714979 ==
8519 11:32:41.715304 DQS Delay:
8520 11:32:41.717993 DQS0 = 0, DQS1 = 0
8521 11:32:41.718376 DQM Delay:
8522 11:32:41.721111 DQM0 = 134, DQM1 = 126
8523 11:32:41.721539 DQ Delay:
8524 11:32:41.724756 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8525 11:32:41.727862 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8526 11:32:41.731115 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8527 11:32:41.734693 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8528 11:32:41.735154
8529 11:32:41.735499
8530 11:32:41.735803 ==
8531 11:32:41.738185 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 11:32:41.744885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 11:32:41.745489 ==
8534 11:32:41.745966
8535 11:32:41.746442
8536 11:32:41.746901 TX Vref Scan disable
8537 11:32:41.747864 == TX Byte 0 ==
8538 11:32:41.751641 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8539 11:32:41.758014 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 11:32:41.758497 == TX Byte 1 ==
8541 11:32:41.761276 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8542 11:32:41.764949 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8543 11:32:41.768206 ==
8544 11:32:41.771588 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 11:32:41.775317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 11:32:41.775743 ==
8547 11:32:41.788061
8548 11:32:41.791362 TX Vref early break, caculate TX vref
8549 11:32:41.794417 TX Vref=16, minBit 10, minWin=21, winSum=364
8550 11:32:41.798365 TX Vref=18, minBit 8, minWin=21, winSum=374
8551 11:32:41.801560 TX Vref=20, minBit 8, minWin=22, winSum=388
8552 11:32:41.804747 TX Vref=22, minBit 5, minWin=24, winSum=399
8553 11:32:41.808178 TX Vref=24, minBit 5, minWin=24, winSum=405
8554 11:32:41.815051 TX Vref=26, minBit 11, minWin=25, winSum=417
8555 11:32:41.818051 TX Vref=28, minBit 11, minWin=25, winSum=418
8556 11:32:41.821220 TX Vref=30, minBit 0, minWin=25, winSum=420
8557 11:32:41.824850 TX Vref=32, minBit 0, minWin=25, winSum=415
8558 11:32:41.828134 TX Vref=34, minBit 1, minWin=24, winSum=399
8559 11:32:41.831482 TX Vref=36, minBit 3, minWin=24, winSum=394
8560 11:32:41.837950 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 30
8561 11:32:41.838360
8562 11:32:41.841757 Final TX Range 0 Vref 30
8563 11:32:41.842153
8564 11:32:41.842457 ==
8565 11:32:41.845180 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 11:32:41.848435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 11:32:41.848820 ==
8568 11:32:41.849201
8569 11:32:41.849490
8570 11:32:41.851717 TX Vref Scan disable
8571 11:32:41.858298 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8572 11:32:41.858807 == TX Byte 0 ==
8573 11:32:41.861710 u2DelayCellOfst[0]=17 cells (5 PI)
8574 11:32:41.864731 u2DelayCellOfst[1]=10 cells (3 PI)
8575 11:32:41.867881 u2DelayCellOfst[2]=0 cells (0 PI)
8576 11:32:41.871287 u2DelayCellOfst[3]=7 cells (2 PI)
8577 11:32:41.874827 u2DelayCellOfst[4]=7 cells (2 PI)
8578 11:32:41.878000 u2DelayCellOfst[5]=17 cells (5 PI)
8579 11:32:41.881161 u2DelayCellOfst[6]=17 cells (5 PI)
8580 11:32:41.881341 u2DelayCellOfst[7]=7 cells (2 PI)
8581 11:32:41.888016 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8582 11:32:41.891236 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8583 11:32:41.891425 == TX Byte 1 ==
8584 11:32:41.894564 u2DelayCellOfst[8]=0 cells (0 PI)
8585 11:32:41.898135 u2DelayCellOfst[9]=7 cells (2 PI)
8586 11:32:41.901435 u2DelayCellOfst[10]=14 cells (4 PI)
8587 11:32:41.904825 u2DelayCellOfst[11]=7 cells (2 PI)
8588 11:32:41.908641 u2DelayCellOfst[12]=17 cells (5 PI)
8589 11:32:41.911519 u2DelayCellOfst[13]=21 cells (6 PI)
8590 11:32:41.914696 u2DelayCellOfst[14]=21 cells (6 PI)
8591 11:32:41.918092 u2DelayCellOfst[15]=21 cells (6 PI)
8592 11:32:41.921665 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8593 11:32:41.928698 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8594 11:32:41.929319 DramC Write-DBI on
8595 11:32:41.929720 ==
8596 11:32:41.932127 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 11:32:41.935152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 11:32:41.935745 ==
8599 11:32:41.936151
8600 11:32:41.938591
8601 11:32:41.939014 TX Vref Scan disable
8602 11:32:41.941666 == TX Byte 0 ==
8603 11:32:41.945371 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8604 11:32:41.948603 == TX Byte 1 ==
8605 11:32:41.952061 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8606 11:32:41.952466 DramC Write-DBI off
8607 11:32:41.952868
8608 11:32:41.955113 [DATLAT]
8609 11:32:41.955511 Freq=1600, CH1 RK0
8610 11:32:41.955912
8611 11:32:41.958446 DATLAT Default: 0xf
8612 11:32:41.958843 0, 0xFFFF, sum = 0
8613 11:32:41.961747 1, 0xFFFF, sum = 0
8614 11:32:41.962157 2, 0xFFFF, sum = 0
8615 11:32:41.965052 3, 0xFFFF, sum = 0
8616 11:32:41.965501 4, 0xFFFF, sum = 0
8617 11:32:41.968591 5, 0xFFFF, sum = 0
8618 11:32:41.968996 6, 0xFFFF, sum = 0
8619 11:32:41.972047 7, 0xFFFF, sum = 0
8620 11:32:41.972454 8, 0xFFFF, sum = 0
8621 11:32:41.975490 9, 0xFFFF, sum = 0
8622 11:32:41.978656 10, 0xFFFF, sum = 0
8623 11:32:41.979060 11, 0xFFFF, sum = 0
8624 11:32:41.981897 12, 0xFFFF, sum = 0
8625 11:32:41.982302 13, 0xFFFF, sum = 0
8626 11:32:41.985177 14, 0x0, sum = 1
8627 11:32:41.985661 15, 0x0, sum = 2
8628 11:32:41.988645 16, 0x0, sum = 3
8629 11:32:41.989207 17, 0x0, sum = 4
8630 11:32:41.989679 best_step = 15
8631 11:32:41.990111
8632 11:32:41.991633 ==
8633 11:32:41.995325 Dram Type= 6, Freq= 0, CH_1, rank 0
8634 11:32:41.998798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8635 11:32:41.999181 ==
8636 11:32:41.999565 RX Vref Scan: 1
8637 11:32:41.999849
8638 11:32:42.001798 Set Vref Range= 24 -> 127
8639 11:32:42.002196
8640 11:32:42.004959 RX Vref 24 -> 127, step: 1
8641 11:32:42.005396
8642 11:32:42.008955 RX Delay 11 -> 252, step: 4
8643 11:32:42.009401
8644 11:32:42.012127 Set Vref, RX VrefLevel [Byte0]: 24
8645 11:32:42.014988 [Byte1]: 24
8646 11:32:42.015389
8647 11:32:42.018913 Set Vref, RX VrefLevel [Byte0]: 25
8648 11:32:42.022042 [Byte1]: 25
8649 11:32:42.022542
8650 11:32:42.025454 Set Vref, RX VrefLevel [Byte0]: 26
8651 11:32:42.028834 [Byte1]: 26
8652 11:32:42.031954
8653 11:32:42.032334 Set Vref, RX VrefLevel [Byte0]: 27
8654 11:32:42.035106 [Byte1]: 27
8655 11:32:42.039682
8656 11:32:42.040199 Set Vref, RX VrefLevel [Byte0]: 28
8657 11:32:42.042685 [Byte1]: 28
8658 11:32:42.046841
8659 11:32:42.047374 Set Vref, RX VrefLevel [Byte0]: 29
8660 11:32:42.050534 [Byte1]: 29
8661 11:32:42.054446
8662 11:32:42.054825 Set Vref, RX VrefLevel [Byte0]: 30
8663 11:32:42.058264 [Byte1]: 30
8664 11:32:42.062181
8665 11:32:42.062714 Set Vref, RX VrefLevel [Byte0]: 31
8666 11:32:42.065637 [Byte1]: 31
8667 11:32:42.069788
8668 11:32:42.070295 Set Vref, RX VrefLevel [Byte0]: 32
8669 11:32:42.073396 [Byte1]: 32
8670 11:32:42.077277
8671 11:32:42.077636 Set Vref, RX VrefLevel [Byte0]: 33
8672 11:32:42.080845 [Byte1]: 33
8673 11:32:42.084717
8674 11:32:42.084998 Set Vref, RX VrefLevel [Byte0]: 34
8675 11:32:42.088339 [Byte1]: 34
8676 11:32:42.092163
8677 11:32:42.092398 Set Vref, RX VrefLevel [Byte0]: 35
8678 11:32:42.096202 [Byte1]: 35
8679 11:32:42.100261
8680 11:32:42.100517 Set Vref, RX VrefLevel [Byte0]: 36
8681 11:32:42.103693 [Byte1]: 36
8682 11:32:42.107927
8683 11:32:42.108156 Set Vref, RX VrefLevel [Byte0]: 37
8684 11:32:42.111220 [Byte1]: 37
8685 11:32:42.115262
8686 11:32:42.115339 Set Vref, RX VrefLevel [Byte0]: 38
8687 11:32:42.118385 [Byte1]: 38
8688 11:32:42.122770
8689 11:32:42.122845 Set Vref, RX VrefLevel [Byte0]: 39
8690 11:32:42.126852 [Byte1]: 39
8691 11:32:42.130810
8692 11:32:42.130884 Set Vref, RX VrefLevel [Byte0]: 40
8693 11:32:42.133740 [Byte1]: 40
8694 11:32:42.137928
8695 11:32:42.138003 Set Vref, RX VrefLevel [Byte0]: 41
8696 11:32:42.141285 [Byte1]: 41
8697 11:32:42.145545
8698 11:32:42.145620 Set Vref, RX VrefLevel [Byte0]: 42
8699 11:32:42.149131 [Byte1]: 42
8700 11:32:42.153109
8701 11:32:42.153196 Set Vref, RX VrefLevel [Byte0]: 43
8702 11:32:42.156755 [Byte1]: 43
8703 11:32:42.160726
8704 11:32:42.160802 Set Vref, RX VrefLevel [Byte0]: 44
8705 11:32:42.164255 [Byte1]: 44
8706 11:32:42.169015
8707 11:32:42.169091 Set Vref, RX VrefLevel [Byte0]: 45
8708 11:32:42.171867 [Byte1]: 45
8709 11:32:42.176264
8710 11:32:42.176364 Set Vref, RX VrefLevel [Byte0]: 46
8711 11:32:42.179318 [Byte1]: 46
8712 11:32:42.183444
8713 11:32:42.183518 Set Vref, RX VrefLevel [Byte0]: 47
8714 11:32:42.186768 [Byte1]: 47
8715 11:32:42.191102
8716 11:32:42.191177 Set Vref, RX VrefLevel [Byte0]: 48
8717 11:32:42.194366 [Byte1]: 48
8718 11:32:42.198709
8719 11:32:42.198778 Set Vref, RX VrefLevel [Byte0]: 49
8720 11:32:42.202569 [Byte1]: 49
8721 11:32:42.206357
8722 11:32:42.206423 Set Vref, RX VrefLevel [Byte0]: 50
8723 11:32:42.209717 [Byte1]: 50
8724 11:32:42.214177
8725 11:32:42.214243 Set Vref, RX VrefLevel [Byte0]: 51
8726 11:32:42.217369 [Byte1]: 51
8727 11:32:42.221494
8728 11:32:42.221558 Set Vref, RX VrefLevel [Byte0]: 52
8729 11:32:42.225111 [Byte1]: 52
8730 11:32:42.229346
8731 11:32:42.229416 Set Vref, RX VrefLevel [Byte0]: 53
8732 11:32:42.232536 [Byte1]: 53
8733 11:32:42.236868
8734 11:32:42.236939 Set Vref, RX VrefLevel [Byte0]: 54
8735 11:32:42.240272 [Byte1]: 54
8736 11:32:42.244810
8737 11:32:42.244887 Set Vref, RX VrefLevel [Byte0]: 55
8738 11:32:42.247734 [Byte1]: 55
8739 11:32:42.252029
8740 11:32:42.252106 Set Vref, RX VrefLevel [Byte0]: 56
8741 11:32:42.255839 [Byte1]: 56
8742 11:32:42.259910
8743 11:32:42.259995 Set Vref, RX VrefLevel [Byte0]: 57
8744 11:32:42.263215 [Byte1]: 57
8745 11:32:42.267261
8746 11:32:42.267338 Set Vref, RX VrefLevel [Byte0]: 58
8747 11:32:42.270604 [Byte1]: 58
8748 11:32:42.274898
8749 11:32:42.274978 Set Vref, RX VrefLevel [Byte0]: 59
8750 11:32:42.278577 [Byte1]: 59
8751 11:32:42.282651
8752 11:32:42.282728 Set Vref, RX VrefLevel [Byte0]: 60
8753 11:32:42.286020 [Byte1]: 60
8754 11:32:42.290595
8755 11:32:42.290671 Set Vref, RX VrefLevel [Byte0]: 61
8756 11:32:42.294342 [Byte1]: 61
8757 11:32:42.298050
8758 11:32:42.298120 Set Vref, RX VrefLevel [Byte0]: 62
8759 11:32:42.301526 [Byte1]: 62
8760 11:32:42.305341
8761 11:32:42.305419 Set Vref, RX VrefLevel [Byte0]: 63
8762 11:32:42.308773 [Byte1]: 63
8763 11:32:42.313504
8764 11:32:42.313582 Set Vref, RX VrefLevel [Byte0]: 64
8765 11:32:42.316761 [Byte1]: 64
8766 11:32:42.320649
8767 11:32:42.320727 Set Vref, RX VrefLevel [Byte0]: 65
8768 11:32:42.324198 [Byte1]: 65
8769 11:32:42.328293
8770 11:32:42.328370 Set Vref, RX VrefLevel [Byte0]: 66
8771 11:32:42.331320 [Byte1]: 66
8772 11:32:42.336266
8773 11:32:42.336344 Set Vref, RX VrefLevel [Byte0]: 67
8774 11:32:42.339268 [Byte1]: 67
8775 11:32:42.343326
8776 11:32:42.343403 Set Vref, RX VrefLevel [Byte0]: 68
8777 11:32:42.346786 [Byte1]: 68
8778 11:32:42.350865
8779 11:32:42.350943 Set Vref, RX VrefLevel [Byte0]: 69
8780 11:32:42.354241 [Byte1]: 69
8781 11:32:42.359102
8782 11:32:42.359179 Set Vref, RX VrefLevel [Byte0]: 70
8783 11:32:42.362115 [Byte1]: 70
8784 11:32:42.366042
8785 11:32:42.366119 Set Vref, RX VrefLevel [Byte0]: 71
8786 11:32:42.369898 [Byte1]: 71
8787 11:32:42.373740
8788 11:32:42.373818 Set Vref, RX VrefLevel [Byte0]: 72
8789 11:32:42.377940 [Byte1]: 72
8790 11:32:42.381543
8791 11:32:42.381617 Set Vref, RX VrefLevel [Byte0]: 73
8792 11:32:42.384743 [Byte1]: 73
8793 11:32:42.389266
8794 11:32:42.389337 Set Vref, RX VrefLevel [Byte0]: 74
8795 11:32:42.392363 [Byte1]: 74
8796 11:32:42.396832
8797 11:32:42.396899 Set Vref, RX VrefLevel [Byte0]: 75
8798 11:32:42.400332 [Byte1]: 75
8799 11:32:42.404190
8800 11:32:42.404256 Final RX Vref Byte 0 = 61 to rank0
8801 11:32:42.407635 Final RX Vref Byte 1 = 56 to rank0
8802 11:32:42.411160 Final RX Vref Byte 0 = 61 to rank1
8803 11:32:42.414500 Final RX Vref Byte 1 = 56 to rank1==
8804 11:32:42.417856 Dram Type= 6, Freq= 0, CH_1, rank 0
8805 11:32:42.424543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 11:32:42.424612 ==
8807 11:32:42.424670 DQS Delay:
8808 11:32:42.424723 DQS0 = 0, DQS1 = 0
8809 11:32:42.428194 DQM Delay:
8810 11:32:42.428256 DQM0 = 131, DQM1 = 124
8811 11:32:42.430903 DQ Delay:
8812 11:32:42.434935 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8813 11:32:42.437704 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8814 11:32:42.441041 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8815 11:32:42.444617 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8816 11:32:42.444687
8817 11:32:42.444743
8818 11:32:42.444796
8819 11:32:42.447711 [DramC_TX_OE_Calibration] TA2
8820 11:32:42.451096 Original DQ_B0 (3 6) =30, OEN = 27
8821 11:32:42.454527 Original DQ_B1 (3 6) =30, OEN = 27
8822 11:32:42.457960 24, 0x0, End_B0=24 End_B1=24
8823 11:32:42.458026 25, 0x0, End_B0=25 End_B1=25
8824 11:32:42.461018 26, 0x0, End_B0=26 End_B1=26
8825 11:32:42.464317 27, 0x0, End_B0=27 End_B1=27
8826 11:32:42.467836 28, 0x0, End_B0=28 End_B1=28
8827 11:32:42.467900 29, 0x0, End_B0=29 End_B1=29
8828 11:32:42.471275 30, 0x0, End_B0=30 End_B1=30
8829 11:32:42.474788 31, 0x4141, End_B0=30 End_B1=30
8830 11:32:42.477951 Byte0 end_step=30 best_step=27
8831 11:32:42.481013 Byte1 end_step=30 best_step=27
8832 11:32:42.484449 Byte0 TX OE(2T, 0.5T) = (3, 3)
8833 11:32:42.484513 Byte1 TX OE(2T, 0.5T) = (3, 3)
8834 11:32:42.484567
8835 11:32:42.487905
8836 11:32:42.494269 [DQSOSCAuto] RK0, (LSB)MR18= 0x1902, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8837 11:32:42.497592 CH1 RK0: MR19=303, MR18=1902
8838 11:32:42.504694 CH1_RK0: MR19=0x303, MR18=0x1902, DQSOSC=397, MR23=63, INC=23, DEC=15
8839 11:32:42.504766
8840 11:32:42.507700 ----->DramcWriteLeveling(PI) begin...
8841 11:32:42.507768 ==
8842 11:32:42.511045 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 11:32:42.514539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 11:32:42.514605 ==
8845 11:32:42.517775 Write leveling (Byte 0): 26 => 26
8846 11:32:42.521244 Write leveling (Byte 1): 27 => 27
8847 11:32:42.524139 DramcWriteLeveling(PI) end<-----
8848 11:32:42.524203
8849 11:32:42.524258 ==
8850 11:32:42.527842 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 11:32:42.531242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 11:32:42.531324 ==
8853 11:32:42.534523 [Gating] SW mode calibration
8854 11:32:42.541132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8855 11:32:42.547945 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8856 11:32:42.551534 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 11:32:42.554503 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 11:32:42.561293 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8859 11:32:42.564637 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8860 11:32:42.568070 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 11:32:42.571447 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 11:32:42.578169 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8863 11:32:42.581540 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 11:32:42.584496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 11:32:42.591323 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8866 11:32:42.595216 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
8867 11:32:42.598177 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8868 11:32:42.604576 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8869 11:32:42.608192 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 11:32:42.611206 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 11:32:42.618063 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 11:32:42.621443 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 11:32:42.625108 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8874 11:32:42.631073 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8875 11:32:42.634729 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8876 11:32:42.638050 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 11:32:42.644821 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:32:42.648075 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 11:32:42.650975 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 11:32:42.658226 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 11:32:42.661378 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 11:32:42.664734 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8883 11:32:42.670825 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8884 11:32:42.674086 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8885 11:32:42.677625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8886 11:32:42.681137 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 11:32:42.687748 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 11:32:42.691308 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 11:32:42.694402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 11:32:42.701360 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 11:32:42.704213 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 11:32:42.707369 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 11:32:42.714261 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 11:32:42.717812 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 11:32:42.720786 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 11:32:42.727695 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 11:32:42.730870 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 11:32:42.734253 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8899 11:32:42.740888 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8900 11:32:42.740967 Total UI for P1: 0, mck2ui 16
8901 11:32:42.747607 best dqsien dly found for B0: ( 1, 9, 8)
8902 11:32:42.751104 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8903 11:32:42.754413 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8904 11:32:42.757855 Total UI for P1: 0, mck2ui 16
8905 11:32:42.761300 best dqsien dly found for B1: ( 1, 9, 14)
8906 11:32:42.764439 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8907 11:32:42.767618 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8908 11:32:42.767705
8909 11:32:42.771193 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8910 11:32:42.778179 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8911 11:32:42.778256 [Gating] SW calibration Done
8912 11:32:42.778316 ==
8913 11:32:42.780969 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 11:32:42.787763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 11:32:42.787845 ==
8916 11:32:42.787906 RX Vref Scan: 0
8917 11:32:42.787961
8918 11:32:42.791543 RX Vref 0 -> 0, step: 1
8919 11:32:42.791620
8920 11:32:42.794544 RX Delay 0 -> 252, step: 8
8921 11:32:42.798446 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8922 11:32:42.801305 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8923 11:32:42.804539 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8924 11:32:42.808278 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8925 11:32:42.814814 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8926 11:32:42.818196 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8927 11:32:42.821221 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8928 11:32:42.824415 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8929 11:32:42.828361 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8930 11:32:42.831752 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8931 11:32:42.837986 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8932 11:32:42.841507 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8933 11:32:42.845081 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8934 11:32:42.848103 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8935 11:32:42.854411 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8936 11:32:42.858131 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8937 11:32:42.858199 ==
8938 11:32:42.861359 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:32:42.864692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:32:42.864761 ==
8941 11:32:42.868258 DQS Delay:
8942 11:32:42.868322 DQS0 = 0, DQS1 = 0
8943 11:32:42.868377 DQM Delay:
8944 11:32:42.871361 DQM0 = 131, DQM1 = 128
8945 11:32:42.871426 DQ Delay:
8946 11:32:42.874774 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8947 11:32:42.877842 DQ4 =127, DQ5 =147, DQ6 =139, DQ7 =127
8948 11:32:42.881369 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8949 11:32:42.888240 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8950 11:32:42.888317
8951 11:32:42.888374
8952 11:32:42.888430 ==
8953 11:32:42.891599 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 11:32:42.894577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 11:32:42.894645 ==
8956 11:32:42.894702
8957 11:32:42.894754
8958 11:32:42.898351 TX Vref Scan disable
8959 11:32:42.898416 == TX Byte 0 ==
8960 11:32:42.904683 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8961 11:32:42.908369 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8962 11:32:42.908444 == TX Byte 1 ==
8963 11:32:42.915145 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8964 11:32:42.917980 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8965 11:32:42.918060 ==
8966 11:32:42.921329 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 11:32:42.924697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 11:32:42.924781 ==
8969 11:32:42.939125
8970 11:32:42.942552 TX Vref early break, caculate TX vref
8971 11:32:42.945734 TX Vref=16, minBit 8, minWin=22, winSum=376
8972 11:32:42.949071 TX Vref=18, minBit 8, minWin=22, winSum=387
8973 11:32:42.952635 TX Vref=20, minBit 8, minWin=23, winSum=390
8974 11:32:42.955835 TX Vref=22, minBit 5, minWin=24, winSum=404
8975 11:32:42.959076 TX Vref=24, minBit 15, minWin=24, winSum=410
8976 11:32:42.965903 TX Vref=26, minBit 0, minWin=25, winSum=417
8977 11:32:42.969513 TX Vref=28, minBit 15, minWin=25, winSum=424
8978 11:32:42.972578 TX Vref=30, minBit 0, minWin=25, winSum=417
8979 11:32:42.975705 TX Vref=32, minBit 3, minWin=25, winSum=413
8980 11:32:42.979361 TX Vref=34, minBit 5, minWin=24, winSum=409
8981 11:32:42.982472 TX Vref=36, minBit 0, minWin=24, winSum=397
8982 11:32:42.989033 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 28
8983 11:32:42.989137
8984 11:32:42.992324 Final TX Range 0 Vref 28
8985 11:32:42.992392
8986 11:32:42.992449 ==
8987 11:32:42.996406 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 11:32:42.999099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 11:32:42.999166 ==
8990 11:32:42.999222
8991 11:32:42.999292
8992 11:32:43.003003 TX Vref Scan disable
8993 11:32:43.009379 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8994 11:32:43.009451 == TX Byte 0 ==
8995 11:32:43.012712 u2DelayCellOfst[0]=21 cells (6 PI)
8996 11:32:43.016017 u2DelayCellOfst[1]=14 cells (4 PI)
8997 11:32:43.019319 u2DelayCellOfst[2]=0 cells (0 PI)
8998 11:32:43.022612 u2DelayCellOfst[3]=10 cells (3 PI)
8999 11:32:43.025814 u2DelayCellOfst[4]=10 cells (3 PI)
9000 11:32:43.029094 u2DelayCellOfst[5]=21 cells (6 PI)
9001 11:32:43.033030 u2DelayCellOfst[6]=21 cells (6 PI)
9002 11:32:43.036044 u2DelayCellOfst[7]=10 cells (3 PI)
9003 11:32:43.039590 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9004 11:32:43.042851 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9005 11:32:43.046114 == TX Byte 1 ==
9006 11:32:43.046181 u2DelayCellOfst[8]=0 cells (0 PI)
9007 11:32:43.049416 u2DelayCellOfst[9]=7 cells (2 PI)
9008 11:32:43.052522 u2DelayCellOfst[10]=10 cells (3 PI)
9009 11:32:43.056165 u2DelayCellOfst[11]=7 cells (2 PI)
9010 11:32:43.059221 u2DelayCellOfst[12]=14 cells (4 PI)
9011 11:32:43.063271 u2DelayCellOfst[13]=17 cells (5 PI)
9012 11:32:43.065983 u2DelayCellOfst[14]=17 cells (5 PI)
9013 11:32:43.069480 u2DelayCellOfst[15]=14 cells (4 PI)
9014 11:32:43.073021 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9015 11:32:43.079626 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9016 11:32:43.079698 DramC Write-DBI on
9017 11:32:43.079760 ==
9018 11:32:43.083061 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 11:32:43.086448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 11:32:43.086553 ==
9021 11:32:43.089344
9022 11:32:43.089409
9023 11:32:43.089469 TX Vref Scan disable
9024 11:32:43.092857 == TX Byte 0 ==
9025 11:32:43.096458 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9026 11:32:43.099640 == TX Byte 1 ==
9027 11:32:43.102985 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9028 11:32:43.103054 DramC Write-DBI off
9029 11:32:43.106240
9030 11:32:43.106305 [DATLAT]
9031 11:32:43.106360 Freq=1600, CH1 RK1
9032 11:32:43.106417
9033 11:32:43.109525 DATLAT Default: 0xf
9034 11:32:43.109587 0, 0xFFFF, sum = 0
9035 11:32:43.112851 1, 0xFFFF, sum = 0
9036 11:32:43.112918 2, 0xFFFF, sum = 0
9037 11:32:43.116528 3, 0xFFFF, sum = 0
9038 11:32:43.116622 4, 0xFFFF, sum = 0
9039 11:32:43.119529 5, 0xFFFF, sum = 0
9040 11:32:43.119597 6, 0xFFFF, sum = 0
9041 11:32:43.123084 7, 0xFFFF, sum = 0
9042 11:32:43.126454 8, 0xFFFF, sum = 0
9043 11:32:43.126523 9, 0xFFFF, sum = 0
9044 11:32:43.129295 10, 0xFFFF, sum = 0
9045 11:32:43.129361 11, 0xFFFF, sum = 0
9046 11:32:43.132906 12, 0xFFFF, sum = 0
9047 11:32:43.132978 13, 0xFFFF, sum = 0
9048 11:32:43.136189 14, 0x0, sum = 1
9049 11:32:43.136262 15, 0x0, sum = 2
9050 11:32:43.139672 16, 0x0, sum = 3
9051 11:32:43.139740 17, 0x0, sum = 4
9052 11:32:43.139798 best_step = 15
9053 11:32:43.143048
9054 11:32:43.143114 ==
9055 11:32:43.145932 Dram Type= 6, Freq= 0, CH_1, rank 1
9056 11:32:43.149938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9057 11:32:43.150007 ==
9058 11:32:43.150070 RX Vref Scan: 0
9059 11:32:43.150124
9060 11:32:43.152731 RX Vref 0 -> 0, step: 1
9061 11:32:43.152792
9062 11:32:43.156102 RX Delay 11 -> 252, step: 4
9063 11:32:43.159551 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9064 11:32:43.162683 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9065 11:32:43.170048 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9066 11:32:43.172934 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9067 11:32:43.176244 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9068 11:32:43.179421 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9069 11:32:43.182835 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9070 11:32:43.190140 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
9071 11:32:43.193076 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9072 11:32:43.196351 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9073 11:32:43.199771 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9074 11:32:43.202685 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9075 11:32:43.209468 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9076 11:32:43.212825 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9077 11:32:43.216185 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9078 11:32:43.219379 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9079 11:32:43.219460 ==
9080 11:32:43.222853 Dram Type= 6, Freq= 0, CH_1, rank 1
9081 11:32:43.229586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9082 11:32:43.229704 ==
9083 11:32:43.229848 DQS Delay:
9084 11:32:43.229966 DQS0 = 0, DQS1 = 0
9085 11:32:43.232699 DQM Delay:
9086 11:32:43.232774 DQM0 = 129, DQM1 = 126
9087 11:32:43.236213 DQ Delay:
9088 11:32:43.239477 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9089 11:32:43.242973 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9090 11:32:43.246179 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9091 11:32:43.249883 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9092 11:32:43.250015
9093 11:32:43.250132
9094 11:32:43.250242
9095 11:32:43.253687 [DramC_TX_OE_Calibration] TA2
9096 11:32:43.256464 Original DQ_B0 (3 6) =30, OEN = 27
9097 11:32:43.259353 Original DQ_B1 (3 6) =30, OEN = 27
9098 11:32:43.262725 24, 0x0, End_B0=24 End_B1=24
9099 11:32:43.262826 25, 0x0, End_B0=25 End_B1=25
9100 11:32:43.266170 26, 0x0, End_B0=26 End_B1=26
9101 11:32:43.269904 27, 0x0, End_B0=27 End_B1=27
9102 11:32:43.273296 28, 0x0, End_B0=28 End_B1=28
9103 11:32:43.273391 29, 0x0, End_B0=29 End_B1=29
9104 11:32:43.276045 30, 0x0, End_B0=30 End_B1=30
9105 11:32:43.279578 31, 0x4141, End_B0=30 End_B1=30
9106 11:32:43.282715 Byte0 end_step=30 best_step=27
9107 11:32:43.286160 Byte1 end_step=30 best_step=27
9108 11:32:43.289572 Byte0 TX OE(2T, 0.5T) = (3, 3)
9109 11:32:43.289650 Byte1 TX OE(2T, 0.5T) = (3, 3)
9110 11:32:43.289710
9111 11:32:43.293129
9112 11:32:43.300156 [DQSOSCAuto] RK1, (LSB)MR18= 0x1318, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9113 11:32:43.303019 CH1 RK1: MR19=303, MR18=1318
9114 11:32:43.309814 CH1_RK1: MR19=0x303, MR18=0x1318, DQSOSC=397, MR23=63, INC=23, DEC=15
9115 11:32:43.309892 [RxdqsGatingPostProcess] freq 1600
9116 11:32:43.316281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9117 11:32:43.319843 best DQS0 dly(2T, 0.5T) = (1, 1)
9118 11:32:43.322750 best DQS1 dly(2T, 0.5T) = (1, 1)
9119 11:32:43.326152 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9120 11:32:43.329358 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9121 11:32:43.332669 best DQS0 dly(2T, 0.5T) = (1, 1)
9122 11:32:43.336499 best DQS1 dly(2T, 0.5T) = (1, 1)
9123 11:32:43.339667 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9124 11:32:43.342995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9125 11:32:43.343072 Pre-setting of DQS Precalculation
9126 11:32:43.349674 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9127 11:32:43.356056 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9128 11:32:43.363412 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9129 11:32:43.363490
9130 11:32:43.363550
9131 11:32:43.366242 [Calibration Summary] 3200 Mbps
9132 11:32:43.369467 CH 0, Rank 0
9133 11:32:43.369543 SW Impedance : PASS
9134 11:32:43.373035 DUTY Scan : NO K
9135 11:32:43.376340 ZQ Calibration : PASS
9136 11:32:43.376416 Jitter Meter : NO K
9137 11:32:43.379748 CBT Training : PASS
9138 11:32:43.379825 Write leveling : PASS
9139 11:32:43.383073 RX DQS gating : PASS
9140 11:32:43.386678 RX DQ/DQS(RDDQC) : PASS
9141 11:32:43.386753 TX DQ/DQS : PASS
9142 11:32:43.389955 RX DATLAT : PASS
9143 11:32:43.392866 RX DQ/DQS(Engine): PASS
9144 11:32:43.392967 TX OE : PASS
9145 11:32:43.396101 All Pass.
9146 11:32:43.396176
9147 11:32:43.396235 CH 0, Rank 1
9148 11:32:43.399566 SW Impedance : PASS
9149 11:32:43.399641 DUTY Scan : NO K
9150 11:32:43.402894 ZQ Calibration : PASS
9151 11:32:43.406242 Jitter Meter : NO K
9152 11:32:43.406317 CBT Training : PASS
9153 11:32:43.409862 Write leveling : PASS
9154 11:32:43.413287 RX DQS gating : PASS
9155 11:32:43.413363 RX DQ/DQS(RDDQC) : PASS
9156 11:32:43.416281 TX DQ/DQS : PASS
9157 11:32:43.416372 RX DATLAT : PASS
9158 11:32:43.419804 RX DQ/DQS(Engine): PASS
9159 11:32:43.423522 TX OE : PASS
9160 11:32:43.423597 All Pass.
9161 11:32:43.423656
9162 11:32:43.423710 CH 1, Rank 0
9163 11:32:43.426338 SW Impedance : PASS
9164 11:32:43.429686 DUTY Scan : NO K
9165 11:32:43.429761 ZQ Calibration : PASS
9166 11:32:43.432767 Jitter Meter : NO K
9167 11:32:43.436262 CBT Training : PASS
9168 11:32:43.436338 Write leveling : PASS
9169 11:32:43.439827 RX DQS gating : PASS
9170 11:32:43.443158 RX DQ/DQS(RDDQC) : PASS
9171 11:32:43.443234 TX DQ/DQS : PASS
9172 11:32:43.446511 RX DATLAT : PASS
9173 11:32:43.449817 RX DQ/DQS(Engine): PASS
9174 11:32:43.449892 TX OE : PASS
9175 11:32:43.453018 All Pass.
9176 11:32:43.453093
9177 11:32:43.453189 CH 1, Rank 1
9178 11:32:43.456474 SW Impedance : PASS
9179 11:32:43.456548 DUTY Scan : NO K
9180 11:32:43.459551 ZQ Calibration : PASS
9181 11:32:43.463034 Jitter Meter : NO K
9182 11:32:43.463109 CBT Training : PASS
9183 11:32:43.466415 Write leveling : PASS
9184 11:32:43.466490 RX DQS gating : PASS
9185 11:32:43.469714 RX DQ/DQS(RDDQC) : PASS
9186 11:32:43.473055 TX DQ/DQS : PASS
9187 11:32:43.473170 RX DATLAT : PASS
9188 11:32:43.476343 RX DQ/DQS(Engine): PASS
9189 11:32:43.479893 TX OE : PASS
9190 11:32:43.479966 All Pass.
9191 11:32:43.480022
9192 11:32:43.483127 DramC Write-DBI on
9193 11:32:43.483200 PER_BANK_REFRESH: Hybrid Mode
9194 11:32:43.486284 TX_TRACKING: ON
9195 11:32:43.492864 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9196 11:32:43.503131 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9197 11:32:43.509508 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9198 11:32:43.512927 [FAST_K] Save calibration result to emmc
9199 11:32:43.516246 sync common calibartion params.
9200 11:32:43.519566 sync cbt_mode0:1, 1:1
9201 11:32:43.519632 dram_init: ddr_geometry: 2
9202 11:32:43.523278 dram_init: ddr_geometry: 2
9203 11:32:43.526487 dram_init: ddr_geometry: 2
9204 11:32:43.526554 0:dram_rank_size:100000000
9205 11:32:43.529852 1:dram_rank_size:100000000
9206 11:32:43.536682 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9207 11:32:43.536751 DFS_SHUFFLE_HW_MODE: ON
9208 11:32:43.542972 dramc_set_vcore_voltage set vcore to 725000
9209 11:32:43.543044 Read voltage for 1600, 0
9210 11:32:43.546255 Vio18 = 0
9211 11:32:43.546322 Vcore = 725000
9212 11:32:43.546379 Vdram = 0
9213 11:32:43.549739 Vddq = 0
9214 11:32:43.549804 Vmddr = 0
9215 11:32:43.553377 switch to 3200 Mbps bootup
9216 11:32:43.553445 [DramcRunTimeConfig]
9217 11:32:43.553499 PHYPLL
9218 11:32:43.556282 DPM_CONTROL_AFTERK: ON
9219 11:32:43.560123 PER_BANK_REFRESH: ON
9220 11:32:43.560207 REFRESH_OVERHEAD_REDUCTION: ON
9221 11:32:43.563338 CMD_PICG_NEW_MODE: OFF
9222 11:32:43.566741 XRTWTW_NEW_MODE: ON
9223 11:32:43.566825 XRTRTR_NEW_MODE: ON
9224 11:32:43.566909 TX_TRACKING: ON
9225 11:32:43.569935 RDSEL_TRACKING: OFF
9226 11:32:43.573313 DQS Precalculation for DVFS: ON
9227 11:32:43.573380 RX_TRACKING: OFF
9228 11:32:43.576805 HW_GATING DBG: ON
9229 11:32:43.576889 ZQCS_ENABLE_LP4: ON
9230 11:32:43.579720 RX_PICG_NEW_MODE: ON
9231 11:32:43.583431 TX_PICG_NEW_MODE: ON
9232 11:32:43.583497 ENABLE_RX_DCM_DPHY: ON
9233 11:32:43.586577 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9234 11:32:43.590219 DUMMY_READ_FOR_TRACKING: OFF
9235 11:32:43.593603 !!! SPM_CONTROL_AFTERK: OFF
9236 11:32:43.593675 !!! SPM could not control APHY
9237 11:32:43.596907 IMPEDANCE_TRACKING: ON
9238 11:32:43.596979 TEMP_SENSOR: ON
9239 11:32:43.600196 HW_SAVE_FOR_SR: OFF
9240 11:32:43.603237 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9241 11:32:43.606715 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9242 11:32:43.610168 Read ODT Tracking: ON
9243 11:32:43.610282 Refresh Rate DeBounce: ON
9244 11:32:43.613345 DFS_NO_QUEUE_FLUSH: ON
9245 11:32:43.617028 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9246 11:32:43.620394 ENABLE_DFS_RUNTIME_MRW: OFF
9247 11:32:43.620471 DDR_RESERVE_NEW_MODE: ON
9248 11:32:43.623598 MR_CBT_SWITCH_FREQ: ON
9249 11:32:43.626596 =========================
9250 11:32:43.644230 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9251 11:32:43.647359 dram_init: ddr_geometry: 2
9252 11:32:43.665606 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9253 11:32:43.668963 dram_init: dram init end (result: 0)
9254 11:32:43.675474 DRAM-K: Full calibration passed in 24620 msecs
9255 11:32:43.678970 MRC: failed to locate region type 0.
9256 11:32:43.679047 DRAM rank0 size:0x100000000,
9257 11:32:43.682846 DRAM rank1 size=0x100000000
9258 11:32:43.692760 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9259 11:32:43.699216 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9260 11:32:43.705836 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9261 11:32:43.712533 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9262 11:32:43.715958 DRAM rank0 size:0x100000000,
9263 11:32:43.719188 DRAM rank1 size=0x100000000
9264 11:32:43.719254 CBMEM:
9265 11:32:43.722432 IMD: root @ 0xfffff000 254 entries.
9266 11:32:43.726012 IMD: root @ 0xffffec00 62 entries.
9267 11:32:43.729045 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9268 11:32:43.732882 WARNING: RO_VPD is uninitialized or empty.
9269 11:32:43.739389 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9270 11:32:43.745673 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9271 11:32:43.758382 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9272 11:32:43.769725 BS: romstage times (exec / console): total (unknown) / 24119 ms
9273 11:32:43.769804
9274 11:32:43.769864
9275 11:32:43.779884 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9276 11:32:43.783238 ARM64: Exception handlers installed.
9277 11:32:43.786348 ARM64: Testing exception
9278 11:32:43.789597 ARM64: Done test exception
9279 11:32:43.789676 Enumerating buses...
9280 11:32:43.793383 Show all devs... Before device enumeration.
9281 11:32:43.796767 Root Device: enabled 1
9282 11:32:43.799681 CPU_CLUSTER: 0: enabled 1
9283 11:32:43.799758 CPU: 00: enabled 1
9284 11:32:43.803542 Compare with tree...
9285 11:32:43.803632 Root Device: enabled 1
9286 11:32:43.806311 CPU_CLUSTER: 0: enabled 1
9287 11:32:43.809638 CPU: 00: enabled 1
9288 11:32:43.809714 Root Device scanning...
9289 11:32:43.813160 scan_static_bus for Root Device
9290 11:32:43.816682 CPU_CLUSTER: 0 enabled
9291 11:32:43.819827 scan_static_bus for Root Device done
9292 11:32:43.823036 scan_bus: bus Root Device finished in 8 msecs
9293 11:32:43.823113 done
9294 11:32:43.829890 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9295 11:32:43.833032 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9296 11:32:43.839613 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9297 11:32:43.843371 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9298 11:32:43.846457 Allocating resources...
9299 11:32:43.849506 Reading resources...
9300 11:32:43.853306 Root Device read_resources bus 0 link: 0
9301 11:32:43.853383 DRAM rank0 size:0x100000000,
9302 11:32:43.856587 DRAM rank1 size=0x100000000
9303 11:32:43.859720 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9304 11:32:43.863098 CPU: 00 missing read_resources
9305 11:32:43.866195 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9306 11:32:43.873287 Root Device read_resources bus 0 link: 0 done
9307 11:32:43.873390 Done reading resources.
9308 11:32:43.879798 Show resources in subtree (Root Device)...After reading.
9309 11:32:43.883207 Root Device child on link 0 CPU_CLUSTER: 0
9310 11:32:43.886180 CPU_CLUSTER: 0 child on link 0 CPU: 00
9311 11:32:43.896330 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9312 11:32:43.896416 CPU: 00
9313 11:32:43.899809 Root Device assign_resources, bus 0 link: 0
9314 11:32:43.903612 CPU_CLUSTER: 0 missing set_resources
9315 11:32:43.906743 Root Device assign_resources, bus 0 link: 0 done
9316 11:32:43.909978 Done setting resources.
9317 11:32:43.916458 Show resources in subtree (Root Device)...After assigning values.
9318 11:32:43.919664 Root Device child on link 0 CPU_CLUSTER: 0
9319 11:32:43.923368 CPU_CLUSTER: 0 child on link 0 CPU: 00
9320 11:32:43.933490 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9321 11:32:43.933570 CPU: 00
9322 11:32:43.936437 Done allocating resources.
9323 11:32:43.939943 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9324 11:32:43.943214 Enabling resources...
9325 11:32:43.943318 done.
9326 11:32:43.946483 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9327 11:32:43.950360 Initializing devices...
9328 11:32:43.953348 Root Device init
9329 11:32:43.953452 init hardware done!
9330 11:32:43.956410 0x00000018: ctrlr->caps
9331 11:32:43.956515 52.000 MHz: ctrlr->f_max
9332 11:32:43.960073 0.400 MHz: ctrlr->f_min
9333 11:32:43.963450 0x40ff8080: ctrlr->voltages
9334 11:32:43.963523 sclk: 390625
9335 11:32:43.967268 Bus Width = 1
9336 11:32:43.967346 sclk: 390625
9337 11:32:43.967406 Bus Width = 1
9338 11:32:43.970235 Early init status = 3
9339 11:32:43.973080 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9340 11:32:43.977484 in-header: 03 fc 00 00 01 00 00 00
9341 11:32:43.980669 in-data: 00
9342 11:32:43.983846 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9343 11:32:43.988953 in-header: 03 fd 00 00 00 00 00 00
9344 11:32:43.992896 in-data:
9345 11:32:43.995088 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9346 11:32:43.999752 in-header: 03 fc 00 00 01 00 00 00
9347 11:32:44.002685 in-data: 00
9348 11:32:44.005648 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9349 11:32:44.011674 in-header: 03 fd 00 00 00 00 00 00
9350 11:32:44.014620 in-data:
9351 11:32:44.017839 [SSUSB] Setting up USB HOST controller...
9352 11:32:44.021751 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9353 11:32:44.024606 [SSUSB] phy power-on done.
9354 11:32:44.028403 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9355 11:32:44.034436 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9356 11:32:44.037814 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9357 11:32:44.044363 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9358 11:32:44.051085 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9359 11:32:44.057693 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9360 11:32:44.064640 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9361 11:32:44.071074 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9362 11:32:44.074692 SPM: binary array size = 0x9dc
9363 11:32:44.077628 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9364 11:32:44.084650 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9365 11:32:44.091444 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9366 11:32:44.094794 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9367 11:32:44.101333 configure_display: Starting display init
9368 11:32:44.134530 anx7625_power_on_init: Init interface.
9369 11:32:44.137912 anx7625_disable_pd_protocol: Disabled PD feature.
9370 11:32:44.141135 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9371 11:32:44.169247 anx7625_start_dp_work: Secure OCM version=00
9372 11:32:44.172340 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9373 11:32:44.187120 sp_tx_get_edid_block: EDID Block = 1
9374 11:32:44.289805 Extracted contents:
9375 11:32:44.293183 header: 00 ff ff ff ff ff ff 00
9376 11:32:44.296200 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9377 11:32:44.300005 version: 01 04
9378 11:32:44.303319 basic params: 95 1f 11 78 0a
9379 11:32:44.306474 chroma info: 76 90 94 55 54 90 27 21 50 54
9380 11:32:44.309702 established: 00 00 00
9381 11:32:44.316128 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9382 11:32:44.319613 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9383 11:32:44.326464 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9384 11:32:44.333097 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9385 11:32:44.339640 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9386 11:32:44.342857 extensions: 00
9387 11:32:44.342922 checksum: fb
9388 11:32:44.342977
9389 11:32:44.346122 Manufacturer: IVO Model 57d Serial Number 0
9390 11:32:44.349544 Made week 0 of 2020
9391 11:32:44.349606 EDID version: 1.4
9392 11:32:44.353156 Digital display
9393 11:32:44.356664 6 bits per primary color channel
9394 11:32:44.356734 DisplayPort interface
9395 11:32:44.359556 Maximum image size: 31 cm x 17 cm
9396 11:32:44.363162 Gamma: 220%
9397 11:32:44.363230 Check DPMS levels
9398 11:32:44.365980 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9399 11:32:44.369243 First detailed timing is preferred timing
9400 11:32:44.372762 Established timings supported:
9401 11:32:44.376197 Standard timings supported:
9402 11:32:44.376259 Detailed timings
9403 11:32:44.383080 Hex of detail: 383680a07038204018303c0035ae10000019
9404 11:32:44.386462 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9405 11:32:44.392797 0780 0798 07c8 0820 hborder 0
9406 11:32:44.396528 0438 043b 0447 0458 vborder 0
9407 11:32:44.399774 -hsync -vsync
9408 11:32:44.399850 Did detailed timing
9409 11:32:44.402754 Hex of detail: 000000000000000000000000000000000000
9410 11:32:44.406064 Manufacturer-specified data, tag 0
9411 11:32:44.412871 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9412 11:32:44.412947 ASCII string: InfoVision
9413 11:32:44.419757 Hex of detail: 000000fe00523134304e574635205248200a
9414 11:32:44.423013 ASCII string: R140NWF5 RH
9415 11:32:44.423088 Checksum
9416 11:32:44.423148 Checksum: 0xfb (valid)
9417 11:32:44.429473 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9418 11:32:44.432678 DSI data_rate: 832800000 bps
9419 11:32:44.436519 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9420 11:32:44.442645 anx7625_parse_edid: pixelclock(138800).
9421 11:32:44.446024 hactive(1920), hsync(48), hfp(24), hbp(88)
9422 11:32:44.449312 vactive(1080), vsync(12), vfp(3), vbp(17)
9423 11:32:44.452702 anx7625_dsi_config: config dsi.
9424 11:32:44.459427 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9425 11:32:44.471652 anx7625_dsi_config: success to config DSI
9426 11:32:44.475520 anx7625_dp_start: MIPI phy setup OK.
9427 11:32:44.478582 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9428 11:32:44.481724 mtk_ddp_mode_set invalid vrefresh 60
9429 11:32:44.485031 main_disp_path_setup
9430 11:32:44.485108 ovl_layer_smi_id_en
9431 11:32:44.488561 ovl_layer_smi_id_en
9432 11:32:44.488668 ccorr_config
9433 11:32:44.488727 aal_config
9434 11:32:44.491843 gamma_config
9435 11:32:44.491975 postmask_config
9436 11:32:44.494951 dither_config
9437 11:32:44.498117 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9438 11:32:44.505092 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9439 11:32:44.508362 Root Device init finished in 553 msecs
9440 11:32:44.511410 CPU_CLUSTER: 0 init
9441 11:32:44.518646 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9442 11:32:44.521734 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9443 11:32:44.524971 APU_MBOX 0x190000b0 = 0x10001
9444 11:32:44.528620 APU_MBOX 0x190001b0 = 0x10001
9445 11:32:44.531699 APU_MBOX 0x190005b0 = 0x10001
9446 11:32:44.535111 APU_MBOX 0x190006b0 = 0x10001
9447 11:32:44.538149 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9448 11:32:44.550572 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9449 11:32:44.563007 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9450 11:32:44.569713 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9451 11:32:44.581177 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9452 11:32:44.590901 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9453 11:32:44.594205 CPU_CLUSTER: 0 init finished in 81 msecs
9454 11:32:44.597244 Devices initialized
9455 11:32:44.600508 Show all devs... After init.
9456 11:32:44.600611 Root Device: enabled 1
9457 11:32:44.604148 CPU_CLUSTER: 0: enabled 1
9458 11:32:44.607102 CPU: 00: enabled 1
9459 11:32:44.610544 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9460 11:32:44.613740 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9461 11:32:44.617019 ELOG: NV offset 0x57f000 size 0x1000
9462 11:32:44.624321 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9463 11:32:44.630705 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9464 11:32:44.633701 ELOG: Event(17) added with size 13 at 2024-07-17 11:32:45 UTC
9465 11:32:44.637195 out: cmd=0x121: 03 db 21 01 00 00 00 00
9466 11:32:44.642364 in-header: 03 78 00 00 2c 00 00 00
9467 11:32:44.655092 in-data: c5 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9468 11:32:44.662171 ELOG: Event(A1) added with size 10 at 2024-07-17 11:32:45 UTC
9469 11:32:44.668565 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9470 11:32:44.671838 ELOG: Event(A0) added with size 9 at 2024-07-17 11:32:45 UTC
9471 11:32:44.678825 elog_add_boot_reason: Logged dev mode boot
9472 11:32:44.682161 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9473 11:32:44.685165 Finalize devices...
9474 11:32:44.685276 Devices finalized
9475 11:32:44.692156 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9476 11:32:44.695202 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9477 11:32:44.698621 in-header: 03 07 00 00 08 00 00 00
9478 11:32:44.701815 in-data: aa e4 47 04 13 02 00 00
9479 11:32:44.701906 Chrome EC: UHEPI supported
9480 11:32:44.708929 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9481 11:32:44.712107 in-header: 03 a9 00 00 08 00 00 00
9482 11:32:44.715375 in-data: 84 60 60 08 00 00 00 00
9483 11:32:44.721990 ELOG: Event(91) added with size 10 at 2024-07-17 11:32:45 UTC
9484 11:32:44.725728 Chrome EC: clear events_b mask to 0x0000000020004000
9485 11:32:44.732301 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9486 11:32:44.737858 in-header: 03 fd 00 00 00 00 00 00
9487 11:32:44.741108 in-data:
9488 11:32:44.744761 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9489 11:32:44.747815 Writing coreboot table at 0xffe64000
9490 11:32:44.751156 0. 000000000010a000-0000000000113fff: RAMSTAGE
9491 11:32:44.757871 1. 0000000040000000-00000000400fffff: RAM
9492 11:32:44.761188 2. 0000000040100000-000000004032afff: RAMSTAGE
9493 11:32:44.764836 3. 000000004032b000-00000000545fffff: RAM
9494 11:32:44.767735 4. 0000000054600000-000000005465ffff: BL31
9495 11:32:44.771123 5. 0000000054660000-00000000ffe63fff: RAM
9496 11:32:44.777838 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9497 11:32:44.781941 7. 0000000100000000-000000023fffffff: RAM
9498 11:32:44.785238 Passing 5 GPIOs to payload:
9499 11:32:44.788054 NAME | PORT | POLARITY | VALUE
9500 11:32:44.794420 EC in RW | 0x000000aa | low | undefined
9501 11:32:44.798064 EC interrupt | 0x00000005 | low | undefined
9502 11:32:44.801271 TPM interrupt | 0x000000ab | high | undefined
9503 11:32:44.808075 SD card detect | 0x00000011 | high | undefined
9504 11:32:44.811148 speaker enable | 0x00000093 | high | undefined
9505 11:32:44.814504 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9506 11:32:44.818031 in-header: 03 f9 00 00 02 00 00 00
9507 11:32:44.821667 in-data: 02 00
9508 11:32:44.824335 ADC[4]: Raw value=899852 ID=7
9509 11:32:44.824408 ADC[3]: Raw value=212967 ID=1
9510 11:32:44.827645 RAM Code: 0x71
9511 11:32:44.831269 ADC[6]: Raw value=74557 ID=0
9512 11:32:44.831334 ADC[5]: Raw value=211860 ID=1
9513 11:32:44.835022 SKU Code: 0x1
9514 11:32:44.837975 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27d9
9515 11:32:44.841074 coreboot table: 964 bytes.
9516 11:32:44.844390 IMD ROOT 0. 0xfffff000 0x00001000
9517 11:32:44.847552 IMD SMALL 1. 0xffffe000 0x00001000
9518 11:32:44.850872 RO MCACHE 2. 0xffffc000 0x00001104
9519 11:32:44.854318 CONSOLE 3. 0xfff7c000 0x00080000
9520 11:32:44.857305 FMAP 4. 0xfff7b000 0x00000452
9521 11:32:44.860636 TIME STAMP 5. 0xfff7a000 0x00000910
9522 11:32:44.864076 VBOOT WORK 6. 0xfff66000 0x00014000
9523 11:32:44.867365 RAMOOPS 7. 0xffe66000 0x00100000
9524 11:32:44.871041 COREBOOT 8. 0xffe64000 0x00002000
9525 11:32:44.874241 IMD small region:
9526 11:32:44.877202 IMD ROOT 0. 0xffffec00 0x00000400
9527 11:32:44.880838 VPD 1. 0xffffeb80 0x0000006c
9528 11:32:44.884004 MMC STATUS 2. 0xffffeb60 0x00000004
9529 11:32:44.887521 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9530 11:32:44.894109 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9531 11:32:44.935455 read SPI 0x3990ec 0x4f1b0: 34854 us, 9296 KB/s, 74.368 Mbps
9532 11:32:44.938552 Checking segment from ROM address 0x40100000
9533 11:32:44.942053 Checking segment from ROM address 0x4010001c
9534 11:32:44.948711 Loading segment from ROM address 0x40100000
9535 11:32:44.948786 code (compression=0)
9536 11:32:44.955105 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9537 11:32:44.964998 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9538 11:32:44.965079 it's not compressed!
9539 11:32:44.972189 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9540 11:32:44.975155 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9541 11:32:44.995232 Loading segment from ROM address 0x4010001c
9542 11:32:44.995348 Entry Point 0x80000000
9543 11:32:44.998741 Loaded segments
9544 11:32:45.002026 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9545 11:32:45.008605 Jumping to boot code at 0x80000000(0xffe64000)
9546 11:32:45.015336 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9547 11:32:45.021912 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9548 11:32:45.030675 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9549 11:32:45.032950 Checking segment from ROM address 0x40100000
9550 11:32:45.036490 Checking segment from ROM address 0x4010001c
9551 11:32:45.043038 Loading segment from ROM address 0x40100000
9552 11:32:45.043116 code (compression=1)
9553 11:32:45.049634 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9554 11:32:45.059867 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9555 11:32:45.059959 using LZMA
9556 11:32:45.068100 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9557 11:32:45.074889 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9558 11:32:45.078138 Loading segment from ROM address 0x4010001c
9559 11:32:45.078217 Entry Point 0x54601000
9560 11:32:45.081334 Loaded segments
9561 11:32:45.084915 NOTICE: MT8192 bl31_setup
9562 11:32:45.091746 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9563 11:32:45.095474 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9564 11:32:45.098623 WARNING: region 0:
9565 11:32:45.101731 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 11:32:45.101808 WARNING: region 1:
9567 11:32:45.108549 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9568 11:32:45.111818 WARNING: region 2:
9569 11:32:45.115308 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9570 11:32:45.118682 WARNING: region 3:
9571 11:32:45.121862 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 11:32:45.125127 WARNING: region 4:
9573 11:32:45.131670 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 11:32:45.131772 WARNING: region 5:
9575 11:32:45.134770 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 11:32:45.138124 WARNING: region 6:
9577 11:32:45.141793 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 11:32:45.144927 WARNING: region 7:
9579 11:32:45.148237 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 11:32:45.154858 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9581 11:32:45.157991 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9582 11:32:45.161329 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9583 11:32:45.168025 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9584 11:32:45.171590 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9585 11:32:45.174621 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9586 11:32:45.181710 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9587 11:32:45.184666 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9588 11:32:45.191683 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9589 11:32:45.194761 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9590 11:32:45.198234 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9591 11:32:45.204666 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9592 11:32:45.208009 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9593 11:32:45.211438 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9594 11:32:45.218288 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9595 11:32:45.221341 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9596 11:32:45.228232 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9597 11:32:45.231481 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9598 11:32:45.234793 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9599 11:32:45.241838 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9600 11:32:45.244837 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9601 11:32:45.248003 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9602 11:32:45.255273 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9603 11:32:45.258563 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9604 11:32:45.264798 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9605 11:32:45.268238 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9606 11:32:45.271499 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9607 11:32:45.278075 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9608 11:32:45.281874 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9609 11:32:45.288774 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9610 11:32:45.291454 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9611 11:32:45.294996 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9612 11:32:45.301612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9613 11:32:45.305229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9614 11:32:45.308529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9615 11:32:45.311694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9616 11:32:45.318184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9617 11:32:45.321515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9618 11:32:45.324885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9619 11:32:45.328416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9620 11:32:45.335135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9621 11:32:45.338291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9622 11:32:45.341575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9623 11:32:45.344829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9624 11:32:45.351548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9625 11:32:45.355140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9626 11:32:45.358066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9627 11:32:45.361505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9628 11:32:45.368290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9629 11:32:45.371666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9630 11:32:45.378115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9631 11:32:45.381531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9632 11:32:45.388005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9633 11:32:45.391868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9634 11:32:45.395027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9635 11:32:45.401673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9636 11:32:45.404661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9637 11:32:45.411181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9638 11:32:45.414885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9639 11:32:45.421147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9640 11:32:45.424772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9641 11:32:45.428050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9642 11:32:45.434938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9643 11:32:45.438099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9644 11:32:45.444462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9645 11:32:45.447821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9646 11:32:45.454723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9647 11:32:45.458165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9648 11:32:45.461446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9649 11:32:45.468105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9650 11:32:45.471509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9651 11:32:45.477950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9652 11:32:45.481349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9653 11:32:45.487954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9654 11:32:45.491409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9655 11:32:45.494554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9656 11:32:45.501098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9657 11:32:45.505059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9658 11:32:45.511558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9659 11:32:45.514726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9660 11:32:45.521179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9661 11:32:45.524478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9662 11:32:45.531547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9663 11:32:45.535125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9664 11:32:45.537935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9665 11:32:45.544561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9666 11:32:45.547807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9667 11:32:45.554341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9668 11:32:45.557788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9669 11:32:45.564416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9670 11:32:45.567892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9671 11:32:45.571212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9672 11:32:45.577734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9673 11:32:45.581177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9674 11:32:45.587953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9675 11:32:45.591221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9676 11:32:45.594480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9677 11:32:45.601029 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9678 11:32:45.604256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9679 11:32:45.607879 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9680 11:32:45.611171 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9681 11:32:45.617733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9682 11:32:45.621053 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9683 11:32:45.627656 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9684 11:32:45.631704 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9685 11:32:45.634697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9686 11:32:45.641042 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9687 11:32:45.644582 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9688 11:32:45.650795 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9689 11:32:45.654523 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9690 11:32:45.657782 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9691 11:32:45.664396 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9692 11:32:45.667690 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9693 11:32:45.674569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9694 11:32:45.677745 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9695 11:32:45.681138 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9696 11:32:45.687693 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9697 11:32:45.690781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9698 11:32:45.694209 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9699 11:32:45.701224 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9700 11:32:45.704104 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9701 11:32:45.707525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9702 11:32:45.710903 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9703 11:32:45.717660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9704 11:32:45.720853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9705 11:32:45.724557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9706 11:32:45.731314 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9707 11:32:45.734165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9708 11:32:45.741306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9709 11:32:45.744064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9710 11:32:45.747505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9711 11:32:45.754429 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9712 11:32:45.757353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9713 11:32:45.760776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9714 11:32:45.767363 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9715 11:32:45.770687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9716 11:32:45.777532 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9717 11:32:45.780808 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9718 11:32:45.784489 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9719 11:32:45.791134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9720 11:32:45.794167 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9721 11:32:45.800932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9722 11:32:45.804370 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9723 11:32:45.807438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9724 11:32:45.813988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9725 11:32:45.817634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9726 11:32:45.820768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9727 11:32:45.827623 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9728 11:32:45.830863 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9729 11:32:45.837844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9730 11:32:45.840647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9731 11:32:45.844123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9732 11:32:45.850861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9733 11:32:45.854110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9734 11:32:45.860903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9735 11:32:45.863962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9736 11:32:45.867414 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9737 11:32:45.874206 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9738 11:32:45.877806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9739 11:32:45.881107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9740 11:32:45.887353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9741 11:32:45.890740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9742 11:32:45.897755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9743 11:32:45.900738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9744 11:32:45.904573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9745 11:32:45.910891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9746 11:32:45.914327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9747 11:32:45.917744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9748 11:32:45.924537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9749 11:32:45.927622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9750 11:32:45.934231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9751 11:32:45.937457 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9752 11:32:45.940916 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9753 11:32:45.947668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9754 11:32:45.951106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9755 11:32:45.957310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9756 11:32:45.961059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9757 11:32:45.964173 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9758 11:32:45.970908 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9759 11:32:45.974133 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9760 11:32:45.980862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9761 11:32:45.984347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9762 11:32:45.987580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9763 11:32:45.994273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9764 11:32:45.997302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9765 11:32:46.001153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9766 11:32:46.007859 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9767 11:32:46.011356 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9768 11:32:46.017686 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9769 11:32:46.021347 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9770 11:32:46.024400 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9771 11:32:46.031195 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9772 11:32:46.034536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9773 11:32:46.041035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9774 11:32:46.044712 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9775 11:32:46.047816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9776 11:32:46.054332 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9777 11:32:46.057831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9778 11:32:46.064418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9779 11:32:46.067762 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9780 11:32:46.071397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9781 11:32:46.077689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9782 11:32:46.080984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9783 11:32:46.087552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9784 11:32:46.090823 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9785 11:32:46.098214 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9786 11:32:46.100809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9787 11:32:46.104684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9788 11:32:46.111017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9789 11:32:46.114653 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9790 11:32:46.121261 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9791 11:32:46.124533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9792 11:32:46.127832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9793 11:32:46.134567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9794 11:32:46.137778 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9795 11:32:46.144518 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9796 11:32:46.147743 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9797 11:32:46.151173 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9798 11:32:46.157673 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9799 11:32:46.160876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9800 11:32:46.167855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9801 11:32:46.171446 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9802 11:32:46.174689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9803 11:32:46.180966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9804 11:32:46.184420 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9805 11:32:46.191294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9806 11:32:46.194194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9807 11:32:46.201204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9808 11:32:46.204500 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9809 11:32:46.207843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9810 11:32:46.210913 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9811 11:32:46.218214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9812 11:32:46.220984 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9813 11:32:46.224487 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9814 11:32:46.227864 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9815 11:32:46.234298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9816 11:32:46.237759 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9817 11:32:46.244325 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9818 11:32:46.247800 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9819 11:32:46.251316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9820 11:32:46.257895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9821 11:32:46.261042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9822 11:32:46.264530 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9823 11:32:46.271277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9824 11:32:46.274682 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9825 11:32:46.277454 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9826 11:32:46.284293 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9827 11:32:46.287611 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9828 11:32:46.290827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9829 11:32:46.298036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9830 11:32:46.300823 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9831 11:32:46.307645 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9832 11:32:46.310840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9833 11:32:46.314398 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9834 11:32:46.320907 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9835 11:32:46.324224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9836 11:32:46.327933 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9837 11:32:46.334298 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9838 11:32:46.337666 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9839 11:32:46.344206 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9840 11:32:46.347711 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9841 11:32:46.350836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9842 11:32:46.357315 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9843 11:32:46.360786 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9844 11:32:46.364265 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9845 11:32:46.370738 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9846 11:32:46.374038 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9847 11:32:46.380419 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9848 11:32:46.384165 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9849 11:32:46.387499 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9850 11:32:46.390598 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9851 11:32:46.394301 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9852 11:32:46.400905 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9853 11:32:46.404382 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9854 11:32:46.407456 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9855 11:32:46.410921 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9856 11:32:46.417672 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9857 11:32:46.421044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9858 11:32:46.423992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9859 11:32:46.427243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9860 11:32:46.434212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9861 11:32:46.437302 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9862 11:32:46.441458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9863 11:32:46.447369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9864 11:32:46.450530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9865 11:32:46.457418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9866 11:32:46.460968 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9867 11:32:46.463893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9868 11:32:46.470965 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9869 11:32:46.474198 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9870 11:32:46.480535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9871 11:32:46.483810 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9872 11:32:46.487030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9873 11:32:46.493805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9874 11:32:46.496882 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9875 11:32:46.503797 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9876 11:32:46.507331 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9877 11:32:46.510196 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9878 11:32:46.516876 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9879 11:32:46.520342 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9880 11:32:46.526855 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9881 11:32:46.530055 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9882 11:32:46.537253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9883 11:32:46.540396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9884 11:32:46.543845 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9885 11:32:46.550290 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9886 11:32:46.553905 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9887 11:32:46.560316 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9888 11:32:46.563340 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9889 11:32:46.566948 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9890 11:32:46.573618 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9891 11:32:46.577206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9892 11:32:46.583757 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9893 11:32:46.587240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9894 11:32:46.590382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9895 11:32:46.596862 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9896 11:32:46.600968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9897 11:32:46.607166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9898 11:32:46.610002 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9899 11:32:46.613366 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9900 11:32:46.620441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9901 11:32:46.623847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9902 11:32:46.630097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9903 11:32:46.633492 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9904 11:32:46.636846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9905 11:32:46.643609 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9906 11:32:46.646930 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9907 11:32:46.653643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9908 11:32:46.656792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9909 11:32:46.660214 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9910 11:32:46.667098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9911 11:32:46.670298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9912 11:32:46.677281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9913 11:32:46.680602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9914 11:32:46.683374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9915 11:32:46.690111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9916 11:32:46.693971 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9917 11:32:46.700656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9918 11:32:46.703662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9919 11:32:46.707420 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9920 11:32:46.713636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9921 11:32:46.717028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9922 11:32:46.723491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9923 11:32:46.726908 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9924 11:32:46.733355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9925 11:32:46.736871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9926 11:32:46.740302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9927 11:32:46.746630 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9928 11:32:46.749930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9929 11:32:46.756441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9930 11:32:46.760232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9931 11:32:46.763528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9932 11:32:46.769891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9933 11:32:46.773387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9934 11:32:46.779970 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9935 11:32:46.783144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9936 11:32:46.786534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9937 11:32:46.793262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9938 11:32:46.796666 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9939 11:32:46.803818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9940 11:32:46.806662 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9941 11:32:46.813390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9942 11:32:46.816694 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9943 11:32:46.820028 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9944 11:32:46.826506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9945 11:32:46.830265 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9946 11:32:46.836650 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9947 11:32:46.839706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9948 11:32:46.846608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9949 11:32:46.850199 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9950 11:32:46.853531 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9951 11:32:46.860342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9952 11:32:46.863351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9953 11:32:46.870058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9954 11:32:46.873223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9955 11:32:46.879983 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9956 11:32:46.883393 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9957 11:32:46.886416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9958 11:32:46.893337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9959 11:32:46.896398 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9960 11:32:46.903261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9961 11:32:46.906235 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9962 11:32:46.912951 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9963 11:32:46.916478 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9964 11:32:46.923077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9965 11:32:46.926507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9966 11:32:46.929664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9967 11:32:46.936358 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9968 11:32:46.939966 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9969 11:32:46.946588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9970 11:32:46.950101 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9971 11:32:46.956467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9972 11:32:46.960246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9973 11:32:46.963379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9974 11:32:46.970115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9975 11:32:46.973645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9976 11:32:46.979866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9977 11:32:46.983217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9978 11:32:46.986524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9979 11:32:46.993322 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9980 11:32:46.996838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9981 11:32:47.003092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9982 11:32:47.006970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9983 11:32:47.009923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9984 11:32:47.016770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9985 11:32:47.020002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9986 11:32:47.027034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9987 11:32:47.030107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9988 11:32:47.036389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9989 11:32:47.039811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9990 11:32:47.046687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9991 11:32:47.050211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9992 11:32:47.056428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9993 11:32:47.059446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9994 11:32:47.066322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9995 11:32:47.070099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9996 11:32:47.076488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9997 11:32:47.079722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9998 11:32:47.086428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9999 11:32:47.090008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10000 11:32:47.096469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10001 11:32:47.099646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10002 11:32:47.106337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10003 11:32:47.109620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10004 11:32:47.116655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10005 11:32:47.119472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10006 11:32:47.126631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10007 11:32:47.129703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10008 11:32:47.136160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10009 11:32:47.139585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10010 11:32:47.146198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10011 11:32:47.149619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10012 11:32:47.156180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10013 11:32:47.159639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10014 11:32:47.162922 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10015 11:32:47.166307 INFO: [APUAPC] vio 0
10016 11:32:47.169570 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10017 11:32:47.176544 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10018 11:32:47.179576 INFO: [APUAPC] D0_APC_0: 0x400510
10019 11:32:47.182819 INFO: [APUAPC] D0_APC_1: 0x0
10020 11:32:47.186388 INFO: [APUAPC] D0_APC_2: 0x1540
10021 11:32:47.186490 INFO: [APUAPC] D0_APC_3: 0x0
10022 11:32:47.190226 INFO: [APUAPC] D1_APC_0: 0xffffffff
10023 11:32:47.192842 INFO: [APUAPC] D1_APC_1: 0xffffffff
10024 11:32:47.196272 INFO: [APUAPC] D1_APC_2: 0x3fffff
10025 11:32:47.200198 INFO: [APUAPC] D1_APC_3: 0x0
10026 11:32:47.203018 INFO: [APUAPC] D2_APC_0: 0xffffffff
10027 11:32:47.206520 INFO: [APUAPC] D2_APC_1: 0xffffffff
10028 11:32:47.209278 INFO: [APUAPC] D2_APC_2: 0x3fffff
10029 11:32:47.213274 INFO: [APUAPC] D2_APC_3: 0x0
10030 11:32:47.216592 INFO: [APUAPC] D3_APC_0: 0xffffffff
10031 11:32:47.219483 INFO: [APUAPC] D3_APC_1: 0xffffffff
10032 11:32:47.222690 INFO: [APUAPC] D3_APC_2: 0x3fffff
10033 11:32:47.226117 INFO: [APUAPC] D3_APC_3: 0x0
10034 11:32:47.229387 INFO: [APUAPC] D4_APC_0: 0xffffffff
10035 11:32:47.232616 INFO: [APUAPC] D4_APC_1: 0xffffffff
10036 11:32:47.236204 INFO: [APUAPC] D4_APC_2: 0x3fffff
10037 11:32:47.239354 INFO: [APUAPC] D4_APC_3: 0x0
10038 11:32:47.242900 INFO: [APUAPC] D5_APC_0: 0xffffffff
10039 11:32:47.246152 INFO: [APUAPC] D5_APC_1: 0xffffffff
10040 11:32:47.249519 INFO: [APUAPC] D5_APC_2: 0x3fffff
10041 11:32:47.252743 INFO: [APUAPC] D5_APC_3: 0x0
10042 11:32:47.256218 INFO: [APUAPC] D6_APC_0: 0xffffffff
10043 11:32:47.259739 INFO: [APUAPC] D6_APC_1: 0xffffffff
10044 11:32:47.262742 INFO: [APUAPC] D6_APC_2: 0x3fffff
10045 11:32:47.265951 INFO: [APUAPC] D6_APC_3: 0x0
10046 11:32:47.269481 INFO: [APUAPC] D7_APC_0: 0xffffffff
10047 11:32:47.272716 INFO: [APUAPC] D7_APC_1: 0xffffffff
10048 11:32:47.276007 INFO: [APUAPC] D7_APC_2: 0x3fffff
10049 11:32:47.279452 INFO: [APUAPC] D7_APC_3: 0x0
10050 11:32:47.282769 INFO: [APUAPC] D8_APC_0: 0xffffffff
10051 11:32:47.285895 INFO: [APUAPC] D8_APC_1: 0xffffffff
10052 11:32:47.289477 INFO: [APUAPC] D8_APC_2: 0x3fffff
10053 11:32:47.292747 INFO: [APUAPC] D8_APC_3: 0x0
10054 11:32:47.296023 INFO: [APUAPC] D9_APC_0: 0xffffffff
10055 11:32:47.299298 INFO: [APUAPC] D9_APC_1: 0xffffffff
10056 11:32:47.302907 INFO: [APUAPC] D9_APC_2: 0x3fffff
10057 11:32:47.305673 INFO: [APUAPC] D9_APC_3: 0x0
10058 11:32:47.309384 INFO: [APUAPC] D10_APC_0: 0xffffffff
10059 11:32:47.312909 INFO: [APUAPC] D10_APC_1: 0xffffffff
10060 11:32:47.316054 INFO: [APUAPC] D10_APC_2: 0x3fffff
10061 11:32:47.319399 INFO: [APUAPC] D10_APC_3: 0x0
10062 11:32:47.322674 INFO: [APUAPC] D11_APC_0: 0xffffffff
10063 11:32:47.326086 INFO: [APUAPC] D11_APC_1: 0xffffffff
10064 11:32:47.329406 INFO: [APUAPC] D11_APC_2: 0x3fffff
10065 11:32:47.332607 INFO: [APUAPC] D11_APC_3: 0x0
10066 11:32:47.336031 INFO: [APUAPC] D12_APC_0: 0xffffffff
10067 11:32:47.339334 INFO: [APUAPC] D12_APC_1: 0xffffffff
10068 11:32:47.342570 INFO: [APUAPC] D12_APC_2: 0x3fffff
10069 11:32:47.346544 INFO: [APUAPC] D12_APC_3: 0x0
10070 11:32:47.349347 INFO: [APUAPC] D13_APC_0: 0xffffffff
10071 11:32:47.352870 INFO: [APUAPC] D13_APC_1: 0xffffffff
10072 11:32:47.355966 INFO: [APUAPC] D13_APC_2: 0x3fffff
10073 11:32:47.359381 INFO: [APUAPC] D13_APC_3: 0x0
10074 11:32:47.362805 INFO: [APUAPC] D14_APC_0: 0xffffffff
10075 11:32:47.366118 INFO: [APUAPC] D14_APC_1: 0xffffffff
10076 11:32:47.369461 INFO: [APUAPC] D14_APC_2: 0x3fffff
10077 11:32:47.372765 INFO: [APUAPC] D14_APC_3: 0x0
10078 11:32:47.375541 INFO: [APUAPC] D15_APC_0: 0xffffffff
10079 11:32:47.379188 INFO: [APUAPC] D15_APC_1: 0xffffffff
10080 11:32:47.382512 INFO: [APUAPC] D15_APC_2: 0x3fffff
10081 11:32:47.385989 INFO: [APUAPC] D15_APC_3: 0x0
10082 11:32:47.389500 INFO: [APUAPC] APC_CON: 0x4
10083 11:32:47.389593 INFO: [NOCDAPC] D0_APC_0: 0x0
10084 11:32:47.392804 INFO: [NOCDAPC] D0_APC_1: 0x0
10085 11:32:47.395853 INFO: [NOCDAPC] D1_APC_0: 0x0
10086 11:32:47.399051 INFO: [NOCDAPC] D1_APC_1: 0xfff
10087 11:32:47.402413 INFO: [NOCDAPC] D2_APC_0: 0x0
10088 11:32:47.405855 INFO: [NOCDAPC] D2_APC_1: 0xfff
10089 11:32:47.409459 INFO: [NOCDAPC] D3_APC_0: 0x0
10090 11:32:47.412636 INFO: [NOCDAPC] D3_APC_1: 0xfff
10091 11:32:47.415556 INFO: [NOCDAPC] D4_APC_0: 0x0
10092 11:32:47.419435 INFO: [NOCDAPC] D4_APC_1: 0xfff
10093 11:32:47.419531 INFO: [NOCDAPC] D5_APC_0: 0x0
10094 11:32:47.422273 INFO: [NOCDAPC] D5_APC_1: 0xfff
10095 11:32:47.425737 INFO: [NOCDAPC] D6_APC_0: 0x0
10096 11:32:47.429286 INFO: [NOCDAPC] D6_APC_1: 0xfff
10097 11:32:47.432435 INFO: [NOCDAPC] D7_APC_0: 0x0
10098 11:32:47.435517 INFO: [NOCDAPC] D7_APC_1: 0xfff
10099 11:32:47.439129 INFO: [NOCDAPC] D8_APC_0: 0x0
10100 11:32:47.442289 INFO: [NOCDAPC] D8_APC_1: 0xfff
10101 11:32:47.445480 INFO: [NOCDAPC] D9_APC_0: 0x0
10102 11:32:47.448839 INFO: [NOCDAPC] D9_APC_1: 0xfff
10103 11:32:47.452116 INFO: [NOCDAPC] D10_APC_0: 0x0
10104 11:32:47.452202 INFO: [NOCDAPC] D10_APC_1: 0xfff
10105 11:32:47.455471 INFO: [NOCDAPC] D11_APC_0: 0x0
10106 11:32:47.458844 INFO: [NOCDAPC] D11_APC_1: 0xfff
10107 11:32:47.462350 INFO: [NOCDAPC] D12_APC_0: 0x0
10108 11:32:47.465649 INFO: [NOCDAPC] D12_APC_1: 0xfff
10109 11:32:47.468981 INFO: [NOCDAPC] D13_APC_0: 0x0
10110 11:32:47.472412 INFO: [NOCDAPC] D13_APC_1: 0xfff
10111 11:32:47.475418 INFO: [NOCDAPC] D14_APC_0: 0x0
10112 11:32:47.479277 INFO: [NOCDAPC] D14_APC_1: 0xfff
10113 11:32:47.482460 INFO: [NOCDAPC] D15_APC_0: 0x0
10114 11:32:47.485466 INFO: [NOCDAPC] D15_APC_1: 0xfff
10115 11:32:47.489037 INFO: [NOCDAPC] APC_CON: 0x4
10116 11:32:47.492479 INFO: [APUAPC] set_apusys_apc done
10117 11:32:47.495805 INFO: [DEVAPC] devapc_init done
10118 11:32:47.499210 INFO: GICv3 without legacy support detected.
10119 11:32:47.502674 INFO: ARM GICv3 driver initialized in EL3
10120 11:32:47.505576 INFO: Maximum SPI INTID supported: 639
10121 11:32:47.509025 INFO: BL31: Initializing runtime services
10122 11:32:47.516417 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10123 11:32:47.519265 INFO: SPM: enable CPC mode
10124 11:32:47.522143 INFO: mcdi ready for mcusys-off-idle and system suspend
10125 11:32:47.528811 INFO: BL31: Preparing for EL3 exit to normal world
10126 11:32:47.532084 INFO: Entry point address = 0x80000000
10127 11:32:47.535241 INFO: SPSR = 0x8
10128 11:32:47.539950
10129 11:32:47.540030
10130 11:32:47.540091
10131 11:32:47.543563 Starting depthcharge on Spherion...
10132 11:32:47.543631
10133 11:32:47.543696 Wipe memory regions:
10134 11:32:47.543748
10135 11:32:47.544380 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10136 11:32:47.544486 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10137 11:32:47.544560 Setting prompt string to ['asurada:']
10138 11:32:47.544625 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10139 11:32:47.546453 [0x00000040000000, 0x00000054600000)
10140 11:32:47.668490
10141 11:32:47.668588 [0x00000054660000, 0x00000080000000)
10142 11:32:47.929085
10143 11:32:47.929250 [0x000000821a7280, 0x000000ffe64000)
10144 11:32:48.673285
10145 11:32:48.673397 [0x00000100000000, 0x00000240000000)
10146 11:32:50.563900
10147 11:32:50.567246 Initializing XHCI USB controller at 0x11200000.
10148 11:32:51.605151
10149 11:32:51.608400 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10150 11:32:51.608492
10151 11:32:51.608577
10152 11:32:51.608873 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10153 11:32:51.608972 Sending line: 'tftpboot 192.168.201.1 14864569/tftp-deploy-8d2pnof6/kernel/image.itb 14864569/tftp-deploy-8d2pnof6/kernel/cmdline '
10155 11:32:51.709408 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10156 11:32:51.709509 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10157 11:32:51.714016 asurada: tftpboot 192.168.201.1 14864569/tftp-deploy-8d2pnof6/kernel/image.itp-deploy-8d2pnof6/kernel/cmdline
10158 11:32:51.714090
10159 11:32:51.714152 Waiting for link
10160 11:32:51.872033
10161 11:32:51.872170 R8152: Initializing
10162 11:32:51.872249
10163 11:32:51.875219 Version 6 (ocp_data = 5c30)
10164 11:32:51.875306
10165 11:32:51.878845 R8152: Done initializing
10166 11:32:51.878976
10167 11:32:51.879059 Adding net device
10168 11:32:53.752553
10169 11:32:53.752690 done.
10170 11:32:53.752780
10171 11:32:53.752863 MAC: 00:24:32:30:78:52
10172 11:32:53.752942
10173 11:32:53.755745 Sending DHCP discover... done.
10174 11:32:53.755812
10175 11:32:53.758932 Waiting for reply... done.
10176 11:32:53.759024
10177 11:32:53.762169 Sending DHCP request... done.
10178 11:32:53.762259
10179 11:32:53.762340 Waiting for reply... done.
10180 11:32:53.762418
10181 11:32:53.765772 My ip is 192.168.201.14
10182 11:32:53.765860
10183 11:32:53.769064 The DHCP server ip is 192.168.201.1
10184 11:32:53.769191
10185 11:32:53.772229 TFTP server IP predefined by user: 192.168.201.1
10186 11:32:53.772310
10187 11:32:53.779071 Bootfile predefined by user: 14864569/tftp-deploy-8d2pnof6/kernel/image.itb
10188 11:32:53.779162
10189 11:32:53.782407 Sending tftp read request... done.
10190 11:32:53.782496
10191 11:32:53.785315 Waiting for the transfer...
10192 11:32:53.788478
10193 11:32:54.337531 00000000 ################################################################
10194 11:32:54.337645
10195 11:32:54.886646 00080000 ################################################################
10196 11:32:54.886782
10197 11:32:55.421006 00100000 ################################################################
10198 11:32:55.421192
10199 11:32:55.958437 00180000 ################################################################
10200 11:32:55.958590
10201 11:32:56.505756 00200000 ################################################################
10202 11:32:56.505911
10203 11:32:57.029172 00280000 ################################################################
10204 11:32:57.029336
10205 11:32:57.546636 00300000 ################################################################
10206 11:32:57.546769
10207 11:32:58.085153 00380000 ################################################################
10208 11:32:58.085266
10209 11:32:58.630521 00400000 ################################################################
10210 11:32:58.630634
10211 11:32:59.172358 00480000 ################################################################
10212 11:32:59.172467
10213 11:32:59.779739 00500000 ################################################################
10214 11:32:59.779864
10215 11:33:00.327774 00580000 ################################################################
10216 11:33:00.327902
10217 11:33:00.931583 00600000 ################################################################
10218 11:33:00.932040
10219 11:33:01.545664 00680000 ################################################################
10220 11:33:01.545777
10221 11:33:02.130177 00700000 ################################################################
10222 11:33:02.130378
10223 11:33:02.721040 00780000 ################################################################
10224 11:33:02.721557
10225 11:33:03.389241 00800000 ################################################################
10226 11:33:03.389696
10227 11:33:04.025294 00880000 ################################################################
10228 11:33:04.025734
10229 11:33:04.714738 00900000 ################################################################
10230 11:33:04.715296
10231 11:33:05.319186 00980000 ################################################################
10232 11:33:05.319300
10233 11:33:05.900863 00a00000 ################################################################
10234 11:33:05.900979
10235 11:33:06.514247 00a80000 ################################################################
10236 11:33:06.514374
10237 11:33:07.082379 00b00000 ################################################################
10238 11:33:07.082497
10239 11:33:07.716588 00b80000 ################################################################
10240 11:33:07.716704
10241 11:33:08.353019 00c00000 ################################################################
10242 11:33:08.353165
10243 11:33:09.029694 00c80000 ################################################################
10244 11:33:09.030155
10245 11:33:09.755918 00d00000 ################################################################
10246 11:33:09.756380
10247 11:33:10.437523 00d80000 ################################################################
10248 11:33:10.438047
10249 11:33:11.119990 00e00000 ################################################################
10250 11:33:11.120438
10251 11:33:11.714087 00e80000 ################################################################
10252 11:33:11.714244
10253 11:33:12.314108 00f00000 ################################################################
10254 11:33:12.314227
10255 11:33:12.935884 00f80000 ################################################################
10256 11:33:12.936014
10257 11:33:13.562066 01000000 ################################################################
10258 11:33:13.562522
10259 11:33:14.232057 01080000 ################################################################
10260 11:33:14.232524
10261 11:33:14.911546 01100000 ################################################################
10262 11:33:14.912026
10263 11:33:15.543445 01180000 ################################################################
10264 11:33:15.543896
10265 11:33:16.141072 01200000 ################################################################
10266 11:33:16.141190
10267 11:33:16.698047 01280000 ################################################################
10268 11:33:16.698163
10269 11:33:17.237712 01300000 ################################################################
10270 11:33:17.237825
10271 11:33:17.777505 01380000 ################################################################
10272 11:33:17.777633
10273 11:33:18.427752 01400000 ################################################################
10274 11:33:18.428393
10275 11:33:19.031432 01480000 ################################################################
10276 11:33:19.031549
10277 11:33:19.640025 01500000 ################################################################
10278 11:33:19.640477
10279 11:33:20.269893 01580000 ################################################################
10280 11:33:20.270357
10281 11:33:20.896791 01600000 ################################################################
10282 11:33:20.896908
10283 11:33:21.449549 01680000 ################################################################
10284 11:33:21.449705
10285 11:33:22.046888 01700000 ################################################################
10286 11:33:22.047327
10287 11:33:22.631850 01780000 ################################################################
10288 11:33:22.631972
10289 11:33:23.304414 01800000 ################################################################
10290 11:33:23.304889
10291 11:33:24.003007 01880000 ################################################################
10292 11:33:24.003503
10293 11:33:24.693778 01900000 ################################################################
10294 11:33:24.694300
10295 11:33:25.362077 01980000 ################################################################
10296 11:33:25.362198
10297 11:33:26.016749 01a00000 ################################################################
10298 11:33:26.016875
10299 11:33:26.635514 01a80000 ################################################################
10300 11:33:26.635954
10301 11:33:27.338226 01b00000 ################################################################
10302 11:33:27.338730
10303 11:33:28.017450 01b80000 ################################################################
10304 11:33:28.017562
10305 11:33:28.691780 01c00000 ################################################################
10306 11:33:28.692292
10307 11:33:29.363462 01c80000 ################################################################
10308 11:33:29.363926
10309 11:33:30.007941 01d00000 ################################################################
10310 11:33:30.008083
10311 11:33:30.590290 01d80000 ################################################################
10312 11:33:30.590440
10313 11:33:31.057202 01e00000 ##################################################### done.
10314 11:33:31.057324
10315 11:33:31.060685 The bootfile was 31888626 bytes long.
10316 11:33:31.060780
10317 11:33:31.063946 Sending tftp read request... done.
10318 11:33:31.064037
10319 11:33:31.064118 Waiting for the transfer...
10320 11:33:31.064196
10321 11:33:31.067395 00000000 # done.
10322 11:33:31.067467
10323 11:33:31.074000 Command line loaded dynamically from TFTP file: 14864569/tftp-deploy-8d2pnof6/kernel/cmdline
10324 11:33:31.074085
10325 11:33:31.096951 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10326 11:33:31.097041
10327 11:33:31.097102 Loading FIT.
10328 11:33:31.097169
10329 11:33:31.100529 Image ramdisk-1 has 18721045 bytes.
10330 11:33:31.100619
10331 11:33:31.103645 Image fdt-1 has 47258 bytes.
10332 11:33:31.103741
10333 11:33:31.107522 Image kernel-1 has 13118294 bytes.
10334 11:33:31.107613
10335 11:33:31.117225 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10336 11:33:31.117322
10337 11:33:31.133642 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10338 11:33:31.133719
10339 11:33:31.137152 Choosing best match conf-1 for compat google,spherion-rev2.
10340 11:33:31.140431
10341 11:33:31.143904 Connected to device vid:did:rid of 1ae0:0028:00
10342 11:33:31.154326
10343 11:33:31.158133 tpm_get_response: command 0x17b, return code 0x0
10344 11:33:31.158203
10345 11:33:31.161010 ec_init: CrosEC protocol v3 supported (256, 248)
10346 11:33:31.165125
10347 11:33:31.168486 tpm_cleanup: add release locality here.
10348 11:33:31.168556
10349 11:33:31.171878 Shutting down all USB controllers.
10350 11:33:31.171968
10351 11:33:31.172050 Removing current net device
10352 11:33:31.172131
10353 11:33:31.178390 Exiting depthcharge with code 4 at timestamp: 73075256
10354 11:33:31.178482
10355 11:33:31.181803 LZMA decompressing kernel-1 to 0x821a6718
10356 11:33:31.181870
10357 11:33:31.184916 LZMA decompressing kernel-1 to 0x40000000
10358 11:33:32.799468
10359 11:33:32.799598 jumping to kernel
10360 11:33:32.800046 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10361 11:33:32.800140 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10362 11:33:32.800210 Setting prompt string to ['Linux version [0-9]']
10363 11:33:32.800273 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10364 11:33:32.800335 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10365 11:33:32.880033
10366 11:33:32.883318 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10367 11:33:32.886953 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10368 11:33:32.887044 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10369 11:33:32.887111 Setting prompt string to []
10370 11:33:32.887184 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10371 11:33:32.887249 Using line separator: #'\n'#
10372 11:33:32.887301 No login prompt set.
10373 11:33:32.887356 Parsing kernel messages
10374 11:33:32.887405 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10375 11:33:32.887499 [login-action] Waiting for messages, (timeout 00:03:34)
10376 11:33:32.887555 Waiting using forced prompt support (timeout 00:01:47)
10377 11:33:32.906906 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10378 11:33:32.910202 [ 0.000000] random: crng init done
10379 11:33:32.913522 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10380 11:33:32.916953 [ 0.000000] efi: UEFI not found.
10381 11:33:32.927339 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10382 11:33:32.933445 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10383 11:33:32.944003 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10384 11:33:32.953190 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10385 11:33:32.960006 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10386 11:33:32.963588 [ 0.000000] printk: bootconsole [mtk8250] enabled
10387 11:33:32.971277 [ 0.000000] NUMA: No NUMA configuration found
10388 11:33:32.977829 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10389 11:33:32.984647 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10390 11:33:32.984752 [ 0.000000] Zone ranges:
10391 11:33:32.991465 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10392 11:33:32.994626 [ 0.000000] DMA32 empty
10393 11:33:33.001368 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10394 11:33:33.004736 [ 0.000000] Movable zone start for each node
10395 11:33:33.007890 [ 0.000000] Early memory node ranges
10396 11:33:33.014782 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10397 11:33:33.021665 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10398 11:33:33.028014 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10399 11:33:33.034701 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10400 11:33:33.041590 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10401 11:33:33.047859 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10402 11:33:33.104971 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10403 11:33:33.111088 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10404 11:33:33.118040 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10405 11:33:33.121590 [ 0.000000] psci: probing for conduit method from DT.
10406 11:33:33.127814 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10407 11:33:33.131274 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10408 11:33:33.137958 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10409 11:33:33.141309 [ 0.000000] psci: SMC Calling Convention v1.2
10410 11:33:33.148304 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10411 11:33:33.151408 [ 0.000000] Detected VIPT I-cache on CPU0
10412 11:33:33.158344 [ 0.000000] CPU features: detected: GIC system register CPU interface
10413 11:33:33.164625 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10414 11:33:33.171187 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10415 11:33:33.178057 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10416 11:33:33.184623 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10417 11:33:33.191234 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10418 11:33:33.197906 [ 0.000000] alternatives: applying boot alternatives
10419 11:33:33.201275 [ 0.000000] Fallback order for Node 0: 0
10420 11:33:33.207899 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10421 11:33:33.211520 [ 0.000000] Policy zone: Normal
10422 11:33:33.234502 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10423 11:33:33.248113 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10424 11:33:33.257929 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10425 11:33:33.267904 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10426 11:33:33.274985 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10427 11:33:33.277947 <6>[ 0.000000] software IO TLB: area num 8.
10428 11:33:33.335488 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10429 11:33:33.485225 <6>[ 0.000000] Memory: 7945780K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406988K reserved, 32768K cma-reserved)
10430 11:33:33.491930 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10431 11:33:33.498223 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10432 11:33:33.501480 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10433 11:33:33.508487 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10434 11:33:33.515096 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10435 11:33:33.518492 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10436 11:33:33.528589 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10437 11:33:33.535111 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10438 11:33:33.538623 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10439 11:33:33.546112 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10440 11:33:33.549561 <6>[ 0.000000] GICv3: 608 SPIs implemented
10441 11:33:33.556165 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10442 11:33:33.559680 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10443 11:33:33.562641 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10444 11:33:33.573036 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10445 11:33:33.583053 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10446 11:33:33.596577 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10447 11:33:33.603101 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10448 11:33:33.611596 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10449 11:33:33.624980 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10450 11:33:33.631609 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10451 11:33:33.638436 <6>[ 0.009176] Console: colour dummy device 80x25
10452 11:33:33.648089 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10453 11:33:33.654867 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10454 11:33:33.657853 <6>[ 0.029253] LSM: Security Framework initializing
10455 11:33:33.664784 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10456 11:33:33.674496 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 11:33:33.681696 <6>[ 0.051425] cblist_init_generic: Setting adjustable number of callback queues.
10458 11:33:33.689040 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 11:33:33.698186 <6>[ 0.065202] cblist_init_generic: Setting adjustable number of callback queues.
10460 11:33:33.701221 <6>[ 0.072674] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 11:33:33.707724 <6>[ 0.079076] rcu: Hierarchical SRCU implementation.
10462 11:33:33.714494 <6>[ 0.084122] rcu: Max phase no-delay instances is 1000.
10463 11:33:33.720790 <6>[ 0.091180] EFI services will not be available.
10464 11:33:33.724470 <6>[ 0.096137] smp: Bringing up secondary CPUs ...
10465 11:33:33.732403 <6>[ 0.101190] Detected VIPT I-cache on CPU1
10466 11:33:33.738899 <6>[ 0.101262] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10467 11:33:33.745962 <6>[ 0.101294] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10468 11:33:33.749022 <6>[ 0.101638] Detected VIPT I-cache on CPU2
10469 11:33:33.755710 <6>[ 0.101691] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10470 11:33:33.762676 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10471 11:33:33.769209 <6>[ 0.101976] Detected VIPT I-cache on CPU3
10472 11:33:33.775983 <6>[ 0.102024] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10473 11:33:33.782287 <6>[ 0.102039] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10474 11:33:33.785751 <6>[ 0.102346] CPU features: detected: Spectre-v4
10475 11:33:33.792585 <6>[ 0.102352] CPU features: detected: Spectre-BHB
10476 11:33:33.795914 <6>[ 0.102357] Detected PIPT I-cache on CPU4
10477 11:33:33.802297 <6>[ 0.102416] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10478 11:33:33.808975 <6>[ 0.102432] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10479 11:33:33.815865 <6>[ 0.102724] Detected PIPT I-cache on CPU5
10480 11:33:33.822256 <6>[ 0.102785] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10481 11:33:33.828919 <6>[ 0.102801] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10482 11:33:33.832196 <6>[ 0.103085] Detected PIPT I-cache on CPU6
10483 11:33:33.839134 <6>[ 0.103150] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10484 11:33:33.845893 <6>[ 0.103166] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10485 11:33:33.849053 <6>[ 0.103465] Detected PIPT I-cache on CPU7
10486 11:33:33.858847 <6>[ 0.103532] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10487 11:33:33.865397 <6>[ 0.103548] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10488 11:33:33.868829 <6>[ 0.103595] smp: Brought up 1 node, 8 CPUs
10489 11:33:33.872127 <6>[ 0.245000] SMP: Total of 8 processors activated.
10490 11:33:33.878744 <6>[ 0.249921] CPU features: detected: 32-bit EL0 Support
10491 11:33:33.889436 <6>[ 0.255284] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10492 11:33:33.895210 <6>[ 0.264139] CPU features: detected: Common not Private translations
10493 11:33:33.898572 <6>[ 0.270614] CPU features: detected: CRC32 instructions
10494 11:33:33.905087 <6>[ 0.275999] CPU features: detected: RCpc load-acquire (LDAPR)
10495 11:33:33.911733 <6>[ 0.281959] CPU features: detected: LSE atomic instructions
10496 11:33:33.918747 <6>[ 0.287777] CPU features: detected: Privileged Access Never
10497 11:33:33.921669 <6>[ 0.293592] CPU features: detected: RAS Extension Support
10498 11:33:33.928204 <6>[ 0.299235] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10499 11:33:33.935211 <6>[ 0.306455] CPU: All CPU(s) started at EL2
10500 11:33:33.941180 <6>[ 0.310772] alternatives: applying system-wide alternatives
10501 11:33:33.950078 <6>[ 0.321653] devtmpfs: initialized
10502 11:33:33.962250 <6>[ 0.330419] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10503 11:33:33.972141 <6>[ 0.340378] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10504 11:33:33.978569 <6>[ 0.348630] pinctrl core: initialized pinctrl subsystem
10505 11:33:33.982475 <6>[ 0.355332] DMI not present or invalid.
10506 11:33:33.989436 <6>[ 0.359738] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10507 11:33:33.998580 <6>[ 0.366629] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10508 11:33:34.005360 <6>[ 0.374209] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10509 11:33:34.015544 <6>[ 0.382439] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10510 11:33:34.018523 <6>[ 0.390680] audit: initializing netlink subsys (disabled)
10511 11:33:34.028501 <5>[ 0.396374] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10512 11:33:34.035737 <6>[ 0.397100] thermal_sys: Registered thermal governor 'step_wise'
10513 11:33:34.042451 <6>[ 0.404342] thermal_sys: Registered thermal governor 'power_allocator'
10514 11:33:34.045026 <6>[ 0.410596] cpuidle: using governor menu
10515 11:33:34.051878 <6>[ 0.421554] NET: Registered PF_QIPCRTR protocol family
10516 11:33:34.058543 <6>[ 0.427055] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10517 11:33:34.061601 <6>[ 0.434156] ASID allocator initialised with 32768 entries
10518 11:33:34.069623 <6>[ 0.440735] Serial: AMBA PL011 UART driver
10519 11:33:34.079327 <4>[ 0.450453] Trying to register duplicate clock ID: 134
10520 11:33:34.137798 <6>[ 0.511960] KASLR enabled
10521 11:33:34.151942 <6>[ 0.519619] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10522 11:33:34.158431 <6>[ 0.526634] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10523 11:33:34.165099 <6>[ 0.533122] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10524 11:33:34.171724 <6>[ 0.540129] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10525 11:33:34.178527 <6>[ 0.546615] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10526 11:33:34.185225 <6>[ 0.553619] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10527 11:33:34.192523 <6>[ 0.560103] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10528 11:33:34.198177 <6>[ 0.567106] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10529 11:33:34.201971 <6>[ 0.574632] ACPI: Interpreter disabled.
10530 11:33:34.209792 <6>[ 0.581065] iommu: Default domain type: Translated
10531 11:33:34.216519 <6>[ 0.586177] iommu: DMA domain TLB invalidation policy: strict mode
10532 11:33:34.219663 <5>[ 0.592831] SCSI subsystem initialized
10533 11:33:34.226634 <6>[ 0.596995] usbcore: registered new interface driver usbfs
10534 11:33:34.232896 <6>[ 0.602725] usbcore: registered new interface driver hub
10535 11:33:34.236886 <6>[ 0.608275] usbcore: registered new device driver usb
10536 11:33:34.243375 <6>[ 0.614381] pps_core: LinuxPPS API ver. 1 registered
10537 11:33:34.253328 <6>[ 0.619575] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10538 11:33:34.256614 <6>[ 0.628920] PTP clock support registered
10539 11:33:34.259680 <6>[ 0.633161] EDAC MC: Ver: 3.0.0
10540 11:33:34.267277 <6>[ 0.638330] FPGA manager framework
10541 11:33:34.270600 <6>[ 0.642016] Advanced Linux Sound Architecture Driver Initialized.
10542 11:33:34.274573 <6>[ 0.648808] vgaarb: loaded
10543 11:33:34.281061 <6>[ 0.651979] clocksource: Switched to clocksource arch_sys_counter
10544 11:33:34.287797 <5>[ 0.658424] VFS: Disk quotas dquot_6.6.0
10545 11:33:34.294092 <6>[ 0.662610] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10546 11:33:34.297601 <6>[ 0.669798] pnp: PnP ACPI: disabled
10547 11:33:34.305011 <6>[ 0.676493] NET: Registered PF_INET protocol family
10548 11:33:34.314675 <6>[ 0.682089] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10549 11:33:34.326167 <6>[ 0.694342] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10550 11:33:34.335823 <6>[ 0.703159] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10551 11:33:34.342481 <6>[ 0.711131] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10552 11:33:34.349281 <6>[ 0.719835] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10553 11:33:34.361279 <6>[ 0.729564] TCP: Hash tables configured (established 65536 bind 65536)
10554 11:33:34.367936 <6>[ 0.736436] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10555 11:33:34.374377 <6>[ 0.743634] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 11:33:34.381304 <6>[ 0.751332] NET: Registered PF_UNIX/PF_LOCAL protocol family
10557 11:33:34.388087 <6>[ 0.757469] RPC: Registered named UNIX socket transport module.
10558 11:33:34.391115 <6>[ 0.763623] RPC: Registered udp transport module.
10559 11:33:34.397724 <6>[ 0.768557] RPC: Registered tcp transport module.
10560 11:33:34.404672 <6>[ 0.773490] RPC: Registered tcp NFSv4.1 backchannel transport module.
10561 11:33:34.407767 <6>[ 0.780158] PCI: CLS 0 bytes, default 64
10562 11:33:34.411231 <6>[ 0.784495] Unpacking initramfs...
10563 11:33:34.435688 <6>[ 0.804070] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10564 11:33:34.446054 <6>[ 0.812731] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10565 11:33:34.448996 <6>[ 0.821595] kvm [1]: IPA Size Limit: 40 bits
10566 11:33:34.455998 <6>[ 0.826122] kvm [1]: GICv3: no GICV resource entry
10567 11:33:34.459671 <6>[ 0.831141] kvm [1]: disabling GICv2 emulation
10568 11:33:34.465736 <6>[ 0.835827] kvm [1]: GIC system register CPU interface enabled
10569 11:33:34.469417 <6>[ 0.841985] kvm [1]: vgic interrupt IRQ18
10570 11:33:34.475660 <6>[ 0.846338] kvm [1]: VHE mode initialized successfully
10571 11:33:34.478975 <5>[ 0.852738] Initialise system trusted keyrings
10572 11:33:34.486133 <6>[ 0.857580] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10573 11:33:34.496225 <6>[ 0.867548] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10574 11:33:34.502741 <5>[ 0.873947] NFS: Registering the id_resolver key type
10575 11:33:34.505805 <5>[ 0.879244] Key type id_resolver registered
10576 11:33:34.512414 <5>[ 0.883660] Key type id_legacy registered
10577 11:33:34.519387 <6>[ 0.887940] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10578 11:33:34.526086 <6>[ 0.894863] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10579 11:33:34.532791 <6>[ 0.902590] 9p: Installing v9fs 9p2000 file system support
10580 11:33:34.568790 <5>[ 0.940189] Key type asymmetric registered
10581 11:33:34.572175 <5>[ 0.944521] Asymmetric key parser 'x509' registered
10582 11:33:34.582163 <6>[ 0.949665] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10583 11:33:34.585534 <6>[ 0.957280] io scheduler mq-deadline registered
10584 11:33:34.588644 <6>[ 0.962053] io scheduler kyber registered
10585 11:33:34.607691 <6>[ 0.979192] EINJ: ACPI disabled.
10586 11:33:34.640798 <4>[ 1.005450] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 11:33:34.650861 <4>[ 1.016094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 11:33:34.666020 <6>[ 1.037368] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10589 11:33:34.674112 <6>[ 1.045463] printk: console [ttyS0] disabled
10590 11:33:34.702205 <6>[ 1.070089] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10591 11:33:34.708145 <6>[ 1.079556] printk: console [ttyS0] enabled
10592 11:33:34.711426 <6>[ 1.079556] printk: console [ttyS0] enabled
10593 11:33:34.718485 <6>[ 1.088454] printk: bootconsole [mtk8250] disabled
10594 11:33:34.721587 <6>[ 1.088454] printk: bootconsole [mtk8250] disabled
10595 11:33:34.728175 <6>[ 1.099670] SuperH (H)SCI(F) driver initialized
10596 11:33:34.731413 <6>[ 1.104962] msm_serial: driver initialized
10597 11:33:34.746164 <6>[ 1.113924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10598 11:33:34.755920 <6>[ 1.122472] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10599 11:33:34.762668 <6>[ 1.131013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10600 11:33:34.772600 <6>[ 1.139643] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10601 11:33:34.779078 <6>[ 1.148350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10602 11:33:34.788997 <6>[ 1.157066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10603 11:33:34.798968 <6>[ 1.165606] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10604 11:33:34.805679 <6>[ 1.174412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10605 11:33:34.815396 <6>[ 1.182955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10606 11:33:34.826598 <6>[ 1.198421] loop: module loaded
10607 11:33:34.833851 <6>[ 1.204384] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10608 11:33:34.856002 <4>[ 1.227872] mtk-pmic-keys: Failed to locate of_node [id: -1]
10609 11:33:34.863266 <6>[ 1.234908] megasas: 07.719.03.00-rc1
10610 11:33:34.873520 <6>[ 1.244654] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10611 11:33:34.884195 <6>[ 1.255364] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10612 11:33:34.900486 <6>[ 1.272138] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10613 11:33:34.957503 <6>[ 1.322626] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10614 11:33:35.210740 <6>[ 1.581902] Freeing initrd memory: 18276K
10615 11:33:35.222693 <6>[ 1.593565] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10616 11:33:35.233104 <6>[ 1.604642] tun: Universal TUN/TAP device driver, 1.6
10617 11:33:35.236289 <6>[ 1.610713] thunder_xcv, ver 1.0
10618 11:33:35.239659 <6>[ 1.614219] thunder_bgx, ver 1.0
10619 11:33:35.243232 <6>[ 1.617717] nicpf, ver 1.0
10620 11:33:35.253543 <6>[ 1.621736] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10621 11:33:35.256921 <6>[ 1.629213] hns3: Copyright (c) 2017 Huawei Corporation.
10622 11:33:35.260559 <6>[ 1.634803] hclge is initializing
10623 11:33:35.266667 <6>[ 1.638385] e1000: Intel(R) PRO/1000 Network Driver
10624 11:33:35.274058 <6>[ 1.643513] e1000: Copyright (c) 1999-2006 Intel Corporation.
10625 11:33:35.277326 <6>[ 1.649526] e1000e: Intel(R) PRO/1000 Network Driver
10626 11:33:35.283371 <6>[ 1.654741] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10627 11:33:35.290384 <6>[ 1.660929] igb: Intel(R) Gigabit Ethernet Network Driver
10628 11:33:35.296995 <6>[ 1.666578] igb: Copyright (c) 2007-2014 Intel Corporation.
10629 11:33:35.303503 <6>[ 1.672413] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10630 11:33:35.306668 <6>[ 1.678931] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10631 11:33:35.313689 <6>[ 1.685392] sky2: driver version 1.30
10632 11:33:35.320335 <6>[ 1.690321] usbcore: registered new device driver r8152-cfgselector
10633 11:33:35.327290 <6>[ 1.696858] usbcore: registered new interface driver r8152
10634 11:33:35.330484 <6>[ 1.702677] VFIO - User Level meta-driver version: 0.3
10635 11:33:35.339525 <6>[ 1.710939] usbcore: registered new interface driver usb-storage
10636 11:33:35.346135 <6>[ 1.717389] usbcore: registered new device driver onboard-usb-hub
10637 11:33:35.355033 <6>[ 1.726545] mt6397-rtc mt6359-rtc: registered as rtc0
10638 11:33:35.364673 <6>[ 1.732008] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:33:35 UTC (1721216015)
10639 11:33:35.367998 <6>[ 1.741577] i2c_dev: i2c /dev entries driver
10640 11:33:35.382091 <4>[ 1.753709] cpu cpu0: supply cpu not found, using dummy regulator
10641 11:33:35.388849 <4>[ 1.760131] cpu cpu1: supply cpu not found, using dummy regulator
10642 11:33:35.395606 <4>[ 1.766527] cpu cpu2: supply cpu not found, using dummy regulator
10643 11:33:35.402384 <4>[ 1.772947] cpu cpu3: supply cpu not found, using dummy regulator
10644 11:33:35.408920 <4>[ 1.779343] cpu cpu4: supply cpu not found, using dummy regulator
10645 11:33:35.415462 <4>[ 1.785740] cpu cpu5: supply cpu not found, using dummy regulator
10646 11:33:35.422387 <4>[ 1.792135] cpu cpu6: supply cpu not found, using dummy regulator
10647 11:33:35.428821 <4>[ 1.798529] cpu cpu7: supply cpu not found, using dummy regulator
10648 11:33:35.447838 <6>[ 1.819183] cpu cpu0: EM: created perf domain
10649 11:33:35.450810 <6>[ 1.824128] cpu cpu4: EM: created perf domain
10650 11:33:35.458181 <6>[ 1.829759] sdhci: Secure Digital Host Controller Interface driver
10651 11:33:35.464992 <6>[ 1.836193] sdhci: Copyright(c) Pierre Ossman
10652 11:33:35.471432 <6>[ 1.841155] Synopsys Designware Multimedia Card Interface Driver
10653 11:33:35.477916 <6>[ 1.847784] sdhci-pltfm: SDHCI platform and OF driver helper
10654 11:33:35.481166 <6>[ 1.847813] mmc0: CQHCI version 5.10
10655 11:33:35.487844 <6>[ 1.858026] ledtrig-cpu: registered to indicate activity on CPUs
10656 11:33:35.495211 <6>[ 1.865186] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10657 11:33:35.501631 <6>[ 1.872248] usbcore: registered new interface driver usbhid
10658 11:33:35.504915 <6>[ 1.878080] usbhid: USB HID core driver
10659 11:33:35.511392 <6>[ 1.882272] spi_master spi0: will run message pump with realtime priority
10660 11:33:35.557038 <6>[ 1.921471] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10661 11:33:35.573253 <6>[ 1.937599] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10662 11:33:35.579959 <6>[ 1.949652] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10663 11:33:35.587064 <6>[ 1.958233] cros-ec-spi spi0.0: Chrome EC device registered
10664 11:33:35.594176 <6>[ 1.964336] mmc0: Command Queue Engine enabled
10665 11:33:35.600471 <6>[ 1.969117] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10666 11:33:35.603799 <6>[ 1.976761] mmcblk0: mmc0:0001 DA4128 116 GiB
10667 11:33:35.614887 <6>[ 1.986003] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 11:33:35.622005 <6>[ 1.993426] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10669 11:33:35.632364 <6>[ 1.996908] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10670 11:33:35.635491 <6>[ 1.999361] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10671 11:33:35.642503 <6>[ 2.009313] NET: Registered PF_PACKET protocol family
10672 11:33:35.648880 <6>[ 2.013886] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10673 11:33:35.652437 <6>[ 2.018576] 9pnet: Installing 9P2000 support
10674 11:33:35.658800 <5>[ 2.029571] Key type dns_resolver registered
10675 11:33:35.662449 <6>[ 2.034514] registered taskstats version 1
10676 11:33:35.669066 <5>[ 2.038894] Loading compiled-in X.509 certificates
10677 11:33:35.697682 <4>[ 2.062484] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10678 11:33:35.707464 <4>[ 2.073308] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10679 11:33:35.722005 <6>[ 2.093505] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 11:33:35.729081 <6>[ 2.100428] xhci-mtk 11200000.usb: xHCI Host Controller
10681 11:33:35.735789 <6>[ 2.105934] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 11:33:35.746133 <6>[ 2.113870] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 11:33:35.752984 <6>[ 2.123316] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 11:33:35.759836 <6>[ 2.129515] xhci-mtk 11200000.usb: xHCI Host Controller
10685 11:33:35.765960 <6>[ 2.135018] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 11:33:35.772887 <6>[ 2.142676] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 11:33:35.779580 <6>[ 2.150515] hub 1-0:1.0: USB hub found
10688 11:33:35.782923 <6>[ 2.154542] hub 1-0:1.0: 1 port detected
10689 11:33:35.789288 <6>[ 2.158830] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 11:33:35.795887 <6>[ 2.167559] hub 2-0:1.0: USB hub found
10691 11:33:35.799698 <6>[ 2.171581] hub 2-0:1.0: 1 port detected
10692 11:33:35.807407 <6>[ 2.178512] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 11:33:35.820707 <6>[ 2.188202] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10694 11:33:35.830138 <6>[ 2.196574] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10695 11:33:35.836757 <6>[ 2.204914] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10696 11:33:35.843685 <6>[ 2.213255] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10697 11:33:35.853949 <6>[ 2.221594] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10698 11:33:35.859958 <6>[ 2.229935] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10699 11:33:35.870166 <6>[ 2.238275] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10700 11:33:35.876933 <6>[ 2.246627] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10701 11:33:35.887123 <6>[ 2.254968] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10702 11:33:35.893452 <6>[ 2.263307] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10703 11:33:35.903701 <6>[ 2.271646] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10704 11:33:35.913409 <6>[ 2.279998] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10705 11:33:35.919747 <6>[ 2.288338] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10706 11:33:35.930066 <6>[ 2.296680] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10707 11:33:35.936489 <6>[ 2.305019] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10708 11:33:35.943556 <6>[ 2.313717] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10709 11:33:35.950013 <6>[ 2.320885] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10710 11:33:35.956865 <6>[ 2.327657] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10711 11:33:35.963387 <6>[ 2.334452] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10712 11:33:35.972930 <6>[ 2.341387] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10713 11:33:35.979806 <6>[ 2.348280] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10714 11:33:35.989871 <6>[ 2.357416] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10715 11:33:35.999861 <6>[ 2.366538] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10716 11:33:36.009495 <6>[ 2.375834] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10717 11:33:36.019136 <6>[ 2.385301] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10718 11:33:36.026746 <6>[ 2.394770] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10719 11:33:36.036304 <6>[ 2.403889] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10720 11:33:36.046261 <6>[ 2.413356] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10721 11:33:36.056024 <6>[ 2.422478] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10722 11:33:36.066366 <6>[ 2.431773] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10723 11:33:36.076046 <6>[ 2.441933] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10724 11:33:36.086130 <6>[ 2.453896] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10725 11:33:36.093710 <6>[ 2.465073] Trying to probe devices needed for running init ...
10726 11:33:36.104619 <3>[ 2.472431] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10727 11:33:36.211571 <6>[ 2.580123] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10728 11:33:36.367122 <6>[ 2.738371] hub 1-1:1.0: USB hub found
10729 11:33:36.369568 <6>[ 2.742893] hub 1-1:1.0: 4 ports detected
10730 11:33:36.381885 <6>[ 2.753633] hub 1-1:1.0: USB hub found
10731 11:33:36.385399 <6>[ 2.758060] hub 1-1:1.0: 4 ports detected
10732 11:33:36.492336 <6>[ 2.860617] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10733 11:33:36.518301 <6>[ 2.890195] hub 2-1:1.0: USB hub found
10734 11:33:36.521566 <6>[ 2.894752] hub 2-1:1.0: 3 ports detected
10735 11:33:36.533739 <6>[ 2.905509] hub 2-1:1.0: USB hub found
10736 11:33:36.537183 <6>[ 2.909906] hub 2-1:1.0: 3 ports detected
10737 11:33:36.707530 <6>[ 3.076306] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10738 11:33:36.840424 <6>[ 3.212052] hub 1-1.4:1.0: USB hub found
10739 11:33:36.843646 <6>[ 3.216683] hub 1-1.4:1.0: 2 ports detected
10740 11:33:36.855210 <6>[ 3.227090] hub 1-1.4:1.0: USB hub found
10741 11:33:36.858332 <6>[ 3.231602] hub 1-1.4:1.0: 2 ports detected
10742 11:33:36.927676 <6>[ 3.296382] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10743 11:33:37.036627 <6>[ 3.404967] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10744 11:33:37.073616 <4>[ 3.441915] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10745 11:33:37.083285 <4>[ 3.451037] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10746 11:33:37.122304 <6>[ 3.494422] r8152 2-1.3:1.0 eth0: v1.12.13
10747 11:33:37.159228 <6>[ 3.528021] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10748 11:33:37.347798 <6>[ 3.716160] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10749 11:33:38.789028 <6>[ 5.161030] r8152 2-1.3:1.0 eth0: carrier on
10750 11:33:41.740114 <5>[ 5.184307] Sending DHCP requests .., OK
10751 11:33:41.747186 <6>[ 8.116487] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10752 11:33:41.750707 <6>[ 8.124826] IP-Config: Complete:
10753 11:33:41.763512 <6>[ 8.128325] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10754 11:33:41.769794 <6>[ 8.139106] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10755 11:33:41.776779 <6>[ 8.147738] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10756 11:33:41.783319 <6>[ 8.147750] nameserver0=192.168.201.1
10757 11:33:41.786564 <6>[ 8.159917] clk: Disabling unused clocks
10758 11:33:41.790304 <6>[ 8.165523] ALSA device list:
10759 11:33:41.796299 <6>[ 8.168839] No soundcards found.
10760 11:33:41.804303 <6>[ 8.176755] Freeing unused kernel memory: 8512K
10761 11:33:41.807470 <6>[ 8.181636] Run /init as init process
10762 11:33:41.817166 Loading, please wait...
10763 11:33:41.844359 Starting systemd-udevd version 252.22-1~deb12u1
10764 11:33:42.096287 <6>[ 8.464808] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10765 11:33:42.102678 <6>[ 8.467510] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10766 11:33:42.112551 <6>[ 8.480721] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10767 11:33:42.119362 <6>[ 8.481065] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10768 11:33:42.129065 <6>[ 8.489513] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10769 11:33:42.132489 <6>[ 8.498200] mc: Linux media interface: v0.10
10770 11:33:42.142828 <6>[ 8.499097] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10771 11:33:42.145941 <6>[ 8.502383] remoteproc remoteproc0: scp is available
10772 11:33:42.152828 <6>[ 8.502434] remoteproc remoteproc0: powering up scp
10773 11:33:42.159341 <6>[ 8.502440] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10774 11:33:42.165926 <6>[ 8.502462] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10775 11:33:42.172450 <6>[ 8.506546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10776 11:33:42.179463 <6>[ 8.543908] videodev: Linux video capture interface: v2.00
10777 11:33:42.189276 <4>[ 8.551151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10778 11:33:42.195989 <3>[ 8.552306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 11:33:42.205982 <3>[ 8.552326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 11:33:42.212446 <3>[ 8.552331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 11:33:42.219120 <3>[ 8.560714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 11:33:42.229208 <6>[ 8.565922] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10783 11:33:42.236808 <6>[ 8.569028] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10784 11:33:42.243630 <4>[ 8.569917] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10785 11:33:42.253571 <3>[ 8.573494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 11:33:42.260235 <6>[ 8.581482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10787 11:33:42.263666 <6>[ 8.581834] Bluetooth: Core ver 2.22
10788 11:33:42.270176 <6>[ 8.582154] NET: Registered PF_BLUETOOTH protocol family
10789 11:33:42.276700 <6>[ 8.582159] Bluetooth: HCI device and connection manager initialized
10790 11:33:42.280186 <6>[ 8.582179] Bluetooth: HCI socket layer initialized
10791 11:33:42.286779 <6>[ 8.582188] Bluetooth: L2CAP socket layer initialized
10792 11:33:42.290357 <6>[ 8.582223] Bluetooth: SCO socket layer initialized
10793 11:33:42.300238 <4>[ 8.582436] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10794 11:33:42.307202 <3>[ 8.589875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 11:33:42.313262 <6>[ 8.598133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10796 11:33:42.323881 <4>[ 8.600238] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 11:33:42.327442 <4>[ 8.600238] Fallback method does not support PEC.
10798 11:33:42.336611 <3>[ 8.605847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 11:33:42.343036 <6>[ 8.609481] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10800 11:33:42.349488 <6>[ 8.609492] pci_bus 0000:00: root bus resource [bus 00-ff]
10801 11:33:42.356146 <6>[ 8.609497] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10802 11:33:42.366624 <6>[ 8.609507] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10803 11:33:42.372952 <6>[ 8.609564] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10804 11:33:42.379696 <6>[ 8.609583] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10805 11:33:42.382846 <6>[ 8.609685] pci 0000:00:00.0: supports D1 D2
10806 11:33:42.389559 <6>[ 8.609686] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10807 11:33:42.399412 <6>[ 8.611070] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10808 11:33:42.406780 <6>[ 8.611230] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10809 11:33:42.413234 <6>[ 8.611256] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10810 11:33:42.419698 <6>[ 8.611277] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10811 11:33:42.430525 <6>[ 8.611293] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10812 11:33:42.432676 <6>[ 8.611410] pci 0000:01:00.0: supports D1 D2
10813 11:33:42.439441 <6>[ 8.611412] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10814 11:33:42.446961 <6>[ 8.613436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10815 11:33:42.456135 <3>[ 8.617522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 11:33:42.463158 <3>[ 8.620717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 11:33:42.472816 <6>[ 8.623365] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10818 11:33:42.479521 <6>[ 8.623377] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10819 11:33:42.486068 <6>[ 8.623380] remoteproc remoteproc0: remote processor scp is now up
10820 11:33:42.492609 <6>[ 8.628157] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 11:33:42.502416 <6>[ 8.628235] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10822 11:33:42.508840 <6>[ 8.628241] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10823 11:33:42.515830 <6>[ 8.628256] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10824 11:33:42.526137 <6>[ 8.628272] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10825 11:33:42.532001 <6>[ 8.628290] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10826 11:33:42.538853 <6>[ 8.628309] pci 0000:00:00.0: PCI bridge to [bus 01]
10827 11:33:42.545615 <6>[ 8.628321] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10828 11:33:42.552237 <6>[ 8.628630] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10829 11:33:42.558652 <6>[ 8.628793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10830 11:33:42.568363 <6>[ 8.628799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10831 11:33:42.575482 <6>[ 8.631525] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10832 11:33:42.582280 <6>[ 8.631862] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10833 11:33:42.591935 <6>[ 8.636523] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10834 11:33:42.601999 <6>[ 8.636721] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10835 11:33:42.609236 <3>[ 8.636735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 11:33:42.615183 <3>[ 8.636763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 11:33:42.625159 <3>[ 8.636766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 11:33:42.631644 <3>[ 8.636768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 11:33:42.641715 <3>[ 8.636804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 11:33:42.648267 <3>[ 8.636808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 11:33:42.658084 <3>[ 8.636810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 11:33:42.664962 <3>[ 8.636812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 11:33:42.671678 <3>[ 8.636815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 11:33:42.681786 <3>[ 8.636825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 11:33:42.688051 <6>[ 8.642087] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10846 11:33:42.698431 <3>[ 8.648459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 11:33:42.708172 <6>[ 8.655227] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10848 11:33:42.714804 <6>[ 8.691319] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10849 11:33:42.738543 <6>[ 9.110406] usbcore: registered new interface driver btusb
10850 11:33:42.748170 <4>[ 9.110689] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10851 11:33:42.758800 <5>[ 9.112481] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10852 11:33:42.764733 <6>[ 9.112751] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10853 11:33:42.777794 <6>[ 9.113949] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10854 11:33:42.784814 <6>[ 9.114058] usbcore: registered new interface driver uvcvideo
10855 11:33:42.791836 <5>[ 9.142424] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10856 11:33:42.794741 <3>[ 9.154253] Bluetooth: hci0: Failed to load firmware file (-2)
10857 11:33:42.801264 <6>[ 9.155100] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10858 11:33:42.811902 <5>[ 9.160678] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10859 11:33:42.817839 <3>[ 9.166976] Bluetooth: hci0: Failed to set up firmware (-2)
10860 11:33:42.824476 <4>[ 9.173119] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10861 11:33:42.834947 <4>[ 9.179557] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10862 11:33:42.841218 <6>[ 9.213374] cfg80211: failed to load regulatory.db
10863 11:33:42.877047 <6>[ 9.245496] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10864 11:33:42.882994 <6>[ 9.252990] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10865 11:33:42.908394 <6>[ 9.279738] mt7921e 0000:01:00.0: ASIC revision: 79610010
10866 11:33:43.011265 <6>[ 9.379762] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10867 11:33:43.014519 <6>[ 9.379762]
10868 11:33:43.018236 Begin: Loading essential drivers ... done.
10869 11:33:43.021292 Begin: Running /scripts/init-premount ... done.
10870 11:33:43.027741 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10871 11:33:43.037360 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10872 11:33:43.040731 Device /sys/class/net/eth0 found
10873 11:33:43.041134 done.
10874 11:33:43.052669 Begin: Waiting up to 180 secs for any network device to become available ... done.
10875 11:33:43.091671 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10876 11:33:43.098558 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10877 11:33:43.105130 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10878 11:33:43.112605 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10879 11:33:43.119599 host : mt8192-asurada-spherion-r0-cbg-3
10880 11:33:43.125655 domain : lava-rack
10881 11:33:43.128694 rootserver: 192.168.201.1 rootpath:
10882 11:33:43.129257 filename :
10883 11:33:43.191717 done.
10884 11:33:43.199221 Begin: Running /scripts/nfs-bottom ... done.
10885 11:33:43.211894 Begin: Running /scripts/init-bottom ... done.
10886 11:33:43.280167 <6>[ 9.648664] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10887 11:33:44.631142 <6>[ 11.003596] NET: Registered PF_INET6 protocol family
10888 11:33:44.638621 <6>[ 11.011315] Segment Routing with IPv6
10889 11:33:44.642200 <6>[ 11.015322] In-situ OAM (IOAM) with IPv6
10890 11:33:44.828374 <30>[ 11.174027] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10891 11:33:44.834755 <30>[ 11.207154] systemd[1]: Detected architecture arm64.
10892 11:33:44.845668
10893 11:33:44.848630 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10894 11:33:44.849013
10895 11:33:44.873631 <30>[ 11.246185] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10896 11:33:46.075217 <30>[ 12.444156] systemd[1]: Queued start job for default target graphical.target.
10897 11:33:46.113226 <30>[ 12.482233] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10898 11:33:46.119603 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10899 11:33:46.141332 <30>[ 12.510332] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10900 11:33:46.151063 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10901 11:33:46.169045 <30>[ 12.538290] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10902 11:33:46.178799 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10903 11:33:46.197067 <30>[ 12.565823] systemd[1]: Created slice user.slice - User and Session Slice.
10904 11:33:46.203233 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10905 11:33:46.227524 <30>[ 12.593217] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10906 11:33:46.237206 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10907 11:33:46.259624 <30>[ 12.625202] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10908 11:33:46.265898 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10909 11:33:46.293182 <30>[ 12.652515] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10910 11:33:46.303305 <30>[ 12.672365] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10911 11:33:46.309631 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10912 11:33:46.327680 <30>[ 12.696720] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10913 11:33:46.337289 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10914 11:33:46.355128 <30>[ 12.724466] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10915 11:33:46.364984 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10916 11:33:46.380130 <30>[ 12.752889] systemd[1]: Reached target paths.target - Path Units.
10917 11:33:46.390790 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10918 11:33:46.407328 <30>[ 12.776670] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10919 11:33:46.413812 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10920 11:33:46.427348 <30>[ 12.800293] systemd[1]: Reached target slices.target - Slice Units.
10921 11:33:46.437641 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10922 11:33:46.452038 <30>[ 12.824354] systemd[1]: Reached target swap.target - Swaps.
10923 11:33:46.458460 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10924 11:33:46.479485 <30>[ 12.848381] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10925 11:33:46.488941 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10926 11:33:46.508740 <30>[ 12.877326] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10927 11:33:46.518008 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10928 11:33:46.539422 <30>[ 12.907965] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10929 11:33:46.548889 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10930 11:33:46.564822 <30>[ 12.933984] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10931 11:33:46.574869 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10932 11:33:46.592239 <30>[ 12.961145] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10933 11:33:46.598834 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10934 11:33:46.620934 <30>[ 12.990092] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10935 11:33:46.630596 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10936 11:33:46.652313 <30>[ 13.020831] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10937 11:33:46.661883 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10938 11:33:46.679819 <30>[ 13.048909] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10939 11:33:46.689326 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10940 11:33:46.747612 <30>[ 13.116783] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10941 11:33:46.753925 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10942 11:33:46.774255 <30>[ 13.142671] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10943 11:33:46.780210 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10944 11:33:46.835104 <30>[ 13.204454] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10945 11:33:46.842033 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10946 11:33:46.869853 <30>[ 13.232628] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10947 11:33:46.884451 <30>[ 13.253803] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10948 11:33:46.894216 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10949 11:33:46.916386 <30>[ 13.285765] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10950 11:33:46.926221 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10951 11:33:46.948286 <30>[ 13.317699] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10952 11:33:46.954976 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10953 11:33:46.980691 <30>[ 13.350263] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10954 11:33:46.987636 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10955 11:33:46.997240 <6>[ 13.365400] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10956 11:33:47.011873 <30>[ 13.381120] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10957 11:33:47.019104 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10958 11:33:47.079410 <30>[ 13.448840] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10959 11:33:47.086297 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10960 11:33:47.113357 <30>[ 13.482850] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10961 11:33:47.120068 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10962 11:33:47.135796 <6>[ 13.507952] fuse: init (API version 7.37)
10963 11:33:47.175929 <30>[ 13.545169] systemd[1]: Starting systemd-journald.service - Journal Service...
10964 11:33:47.182493 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10965 11:33:47.239377 <30>[ 13.608774] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10966 11:33:47.245958 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10967 11:33:47.279436 <30>[ 13.645245] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10968 11:33:47.286051 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10969 11:33:47.309970 <30>[ 13.679231] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10970 11:33:47.319356 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10971 11:33:47.336098 <3>[ 13.705456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:33:47.349592 <30>[ 13.719025] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10973 11:33:47.356237 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10974 11:33:47.374664 <3>[ 13.743763] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:33:47.391550 <30>[ 13.760821] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10976 11:33:47.398490 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10977 11:33:47.411052 <3>[ 13.780675] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:33:47.421305 <30>[ 13.790078] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10979 11:33:47.428383 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10980 11:33:47.441052 <3>[ 13.810159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 11:33:47.450927 <30>[ 13.819581] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10982 11:33:47.457817 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10983 11:33:47.470384 <3>[ 13.839537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 11:33:47.480288 <30>[ 13.849318] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10985 11:33:47.491519 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10986 11:33:47.500612 <3>[ 13.868885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 11:33:47.511290 <30>[ 13.880133] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10988 11:33:47.518165 <30>[ 13.888529] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10989 11:33:47.535065 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 13.901920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 11:33:47.537770 Load Kernel Module configfs.
10991 11:33:47.556493 <30>[ 13.925066] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10992 11:33:47.563383 <30>[ 13.933091] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10993 11:33:47.572828 <3>[ 13.934483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 11:33:47.579537 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10995 11:33:47.596544 <30>[ 13.969149] systemd[1]: modprobe@drm.service: Deactivated successfully.
10996 11:33:47.606799 <3>[ 13.972857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 11:33:47.613669 <30>[ 13.977452] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10998 11:33:47.623541 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10999 11:33:47.640453 <3>[ 14.009533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:33:47.646996 <30>[ 14.010790] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11001 11:33:47.657781 <30>[ 14.026607] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11002 11:33:47.667233 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11003 11:33:47.688782 <30>[ 14.058161] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11004 11:33:47.695209 <30>[ 14.065786] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11005 11:33:47.705426 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11006 11:33:47.723991 <30>[ 14.093304] systemd[1]: Started systemd-journald.service - Journal Service.
11007 11:33:47.730604 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11008 11:33:47.759824 [[0;32m OK [0m] Finished [0<4>[ 14.120404] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11009 11:33:47.769490 ;1;39mmodprobe@l<3>[ 14.137144] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11010 11:33:47.773210 oop.service[0m - Load Kernel Module loop.
11011 11:33:47.793322 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11012 11:33:47.813865 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11013 11:33:47.832796 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11014 11:33:47.853049 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11015 11:33:47.874399 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11016 11:33:47.919618 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11017 11:33:47.942415 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11018 11:33:47.963061 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11019 11:33:47.984763 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11020 11:33:48.011693 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11021 11:33:48.037835 <46>[ 14.407142] systemd-journald[310]: Received client request to flush runtime journal.
11022 11:33:48.061225 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11023 11:33:48.091457 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11024 11:33:48.111790 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11025 11:33:48.127850 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11026 11:33:48.148422 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11027 11:33:49.156890 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11028 11:33:49.207836 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11029 11:33:49.451749 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11030 11:33:49.591387 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11031 11:33:49.611785 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11032 11:33:49.631157 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11033 11:33:49.697545 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11034 11:33:49.720756 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11035 11:33:49.987451 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11036 11:33:50.048763 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11037 11:33:50.147631 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11038 11:33:50.405837 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slic<6>[ 16.776891] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11039 11:33:50.408951 e /system/systemd-backlight.
11040 11:33:50.476325 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11041 11:33:50.535978 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11042 11:33:50.598305 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11043 11:33:50.615717 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11044 11:33:50.635882 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11045 11:33:50.707230 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11046 11:33:50.732295 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11047 11:33:50.759491 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11048 11:33:50.769984 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11049 11:33:50.776970 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11050 11:33:50.816253 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11051 11:33:50.839150 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11052 11:33:50.979438 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11053 11:33:51.002573 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11054 11:33:51.018998 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11055 11:33:51.034841 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11056 11:33:51.062766 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11057 11:33:51.082735 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11058 11:33:51.098964 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11059 11:33:51.119273 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11060 11:33:51.138898 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11061 11:33:51.154712 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11062 11:33:51.173655 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11063 11:33:51.190720 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11064 11:33:51.197216 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11065 11:33:51.251901 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11066 11:33:51.289413 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11067 11:33:51.379241 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11068 11:33:51.408547 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11069 11:33:51.505859 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11070 11:33:51.579874 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11071 11:33:51.597845 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11072 11:33:51.614810 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11073 11:33:51.691461 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11074 11:33:51.731622 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11075 11:33:51.761275 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11076 11:33:51.785444 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11077 11:33:51.807692 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11078 11:33:51.856633 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11079 11:33:51.906453 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11080 11:33:52.006530
11081 11:33:52.009912 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11082 11:33:52.010295
11083 11:33:52.013218 debian-bookworm-arm64 login: root (automatic login)
11084 11:33:52.013632
11085 11:33:52.340634 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11086 11:33:52.340902
11087 11:33:52.346977 The programs included with the Debian GNU/Linux system are free software;
11088 11:33:52.353825 the exact distribution terms for each program are described in the
11089 11:33:52.356987 individual files in /usr/share/doc/*/copyright.
11090 11:33:52.357085
11091 11:33:52.363359 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11092 11:33:52.367027 permitted by applicable law.
11093 11:33:53.578673 Matched prompt #10: / #
11095 11:33:53.579664 Setting prompt string to ['/ #']
11096 11:33:53.580069 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11098 11:33:53.580946 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11099 11:33:53.581418 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11100 11:33:53.581769 Setting prompt string to ['/ #']
11101 11:33:53.582051 Forcing a shell prompt, looking for ['/ #']
11102 11:33:53.582329 Sending line: ''
11104 11:33:53.633528 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11105 11:33:53.633881 Waiting using forced prompt support (timeout 00:02:30)
11106 11:33:53.638846 / #
11107 11:33:53.639573 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11108 11:33:53.640009 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11109 11:33:53.640384 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri'"
11111 11:33:53.747544 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864569/extract-nfsrootfs-u8tkbpri'
11112 11:33:53.748154 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11114 11:33:53.855022 / # export NFS_SERVER_IP='192.168.201.1'
11115 11:33:53.855780 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11116 11:33:53.856248 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11117 11:33:53.856656 end: 2 depthcharge-action (duration 00:01:47) [common]
11118 11:33:53.857181 start: 3 lava-test-retry (timeout 00:07:32) [common]
11119 11:33:53.857747 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11120 11:33:53.858094 Using namespace: common
11121 11:33:53.858415 Sending line: '#'
11123 11:33:53.959647 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11124 11:33:53.965722 / # #
11125 11:33:53.966473 Using /lava-14864569
11126 11:33:53.966800 Sending line: 'export SHELL=/bin/bash'
11128 11:33:54.073622 / # export SHELL=/bin/bash
11129 11:33:54.074259 Sending line: '. /lava-14864569/environment'
11131 11:33:54.180947 / # . /lava-14864569/environment
11132 11:33:54.188687 Sending line: '/lava-14864569/bin/lava-test-runner /lava-14864569/0'
11134 11:33:54.290152 Test shell timeout: 10s (minimum of the action and connection timeout)
11135 11:33:54.295748 / # /lava-14864569/bin/lava-test-runner /lava-14864569/0
11136 11:33:54.614581 + export TESTRUN_ID=0_timesync-off
11137 11:33:54.617450 + TESTRUN_ID=0_timesync-off
11138 11:33:54.620774 + cd /lava-14864569/0/tests/0_timesync-off
11139 11:33:54.624172 ++ cat uuid
11140 11:33:54.632094 + UUID=14864569_1.6.2.3.1
11141 11:33:54.632514 + set +x
11142 11:33:54.638448 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864569_1.6.2.3.1>
11143 11:33:54.639095 Received signal: <STARTRUN> 0_timesync-off 14864569_1.6.2.3.1
11144 11:33:54.639473 Starting test lava.0_timesync-off (14864569_1.6.2.3.1)
11145 11:33:54.639840 Skipping test definition patterns.
11146 11:33:54.641560 + systemctl stop systemd-timesyncd
11147 11:33:54.721598 + set +x
11148 11:33:54.724803 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864569_1.6.2.3.1>
11149 11:33:54.725469 Received signal: <ENDRUN> 0_timesync-off 14864569_1.6.2.3.1
11150 11:33:54.725861 Ending use of test pattern.
11151 11:33:54.726150 Ending test lava.0_timesync-off (14864569_1.6.2.3.1), duration 0.09
11153 11:33:54.824558 + export TESTRUN_ID=1_kselftest-tpm2
11154 11:33:54.827961 + TESTRUN_ID=1_kselftest-tpm2
11155 11:33:54.835015 + cd /lava-14864569/0/tests/1_kselftest-tpm2
11156 11:33:54.835406 ++ cat uuid
11157 11:33:54.844528 + UUID=14864569_1.6.2.3.5
11158 11:33:54.844918 + set +x
11159 11:33:54.851079 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14864569_1.6.2.3.5>
11160 11:33:54.851704 Received signal: <STARTRUN> 1_kselftest-tpm2 14864569_1.6.2.3.5
11161 11:33:54.852020 Starting test lava.1_kselftest-tpm2 (14864569_1.6.2.3.5)
11162 11:33:54.852362 Skipping test definition patterns.
11163 11:33:54.854297 + cd ./automated/linux/kselftest/
11164 11:33:54.884430 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11165 11:33:54.941224 INFO: install_deps skipped
11166 11:33:55.471894 --2024-07-17 11:33:55-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11167 11:33:55.495151 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11168 11:33:55.625490 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11169 11:33:55.755535 HTTP request sent, awaiting response... 200 OK
11170 11:33:55.759073 Length: 1920476 (1.8M) [application/octet-stream]
11171 11:33:55.762126 Saving to: 'kselftest_armhf.tar.gz'
11172 11:33:55.762530
11173 11:33:55.762830
11174 11:33:56.014496 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11175 11:33:56.278041 kselftest_armhf.tar 2%[ ] 44.98K 174KB/s
11176 11:33:56.798608 kselftest_armhf.tar 11%[=> ] 217.50K 416KB/s
11177 11:33:56.809544 kselftest_armhf.tar 44%[=======> ] 841.10K 807KB/s
11178 11:33:56.816105 kselftest_armhf.tar 100%[===================>] 1.83M 1.74MB/s in 1.1s
11179 11:33:56.816509
11180 11:33:56.984769 2024-07-17 11:33:56 (1.74 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
11181 11:33:56.984883
11182 11:34:05.106100 skiplist:
11183 11:34:05.109664 ========================================
11184 11:34:05.112363 ========================================
11185 11:34:05.172745 tpm2:test_smoke.sh
11186 11:34:05.176284 tpm2:test_space.sh
11187 11:34:05.199481 ============== Tests to run ===============
11188 11:34:05.203290 tpm2:test_smoke.sh
11189 11:34:05.206574 tpm2:test_space.sh
11190 11:34:05.209616 ===========End Tests to run ===============
11191 11:34:05.213058 shardfile-tpm2 pass
11192 11:34:05.346681 <12>[ 31.721452] kselftest: Running tests in tpm2
11193 11:34:05.357923 TAP version 13
11194 11:34:05.375306 1..2
11195 11:34:05.413866 # selftests: tpm2: test_smoke.sh
11196 11:34:07.346594 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11197 11:34:07.353340 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11198 11:34:07.360541 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11199 11:34:07.363884 # Traceback (most recent call last):
11200 11:34:07.373793 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11201 11:34:07.373953 # if self.tpm:
11202 11:34:07.377097 # ^^^^^^^^
11203 11:34:07.380526 # AttributeError: 'Client' object has no attribute 'tpm'
11204 11:34:07.387455 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11205 11:34:07.393989 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11206 11:34:07.397216 # Traceback (most recent call last):
11207 11:34:07.407625 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11208 11:34:07.408016 # if self.tpm:
11209 11:34:07.411119 # ^^^^^^^^
11210 11:34:07.414345 # AttributeError: 'Client' object has no attribute 'tpm'
11211 11:34:07.420977 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11212 11:34:07.427834 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11213 11:34:07.430815 # Traceback (most recent call last):
11214 11:34:07.440855 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11215 11:34:07.441346 # if self.tpm:
11216 11:34:07.444481 # ^^^^^^^^
11217 11:34:07.447844 # AttributeError: 'Client' object has no attribute 'tpm'
11218 11:34:07.457641 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11219 11:34:07.464300 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11220 11:34:07.467354 # Traceback (most recent call last):
11221 11:34:07.477826 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11222 11:34:07.478218 # if self.tpm:
11223 11:34:07.480658 # ^^^^^^^^
11224 11:34:07.484085 # AttributeError: 'Client' object has no attribute 'tpm'
11225 11:34:07.490903 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11226 11:34:07.497426 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11227 11:34:07.501173 # Traceback (most recent call last):
11228 11:34:07.511313 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11229 11:34:07.511701 # if self.tpm:
11230 11:34:07.514614 # ^^^^^^^^
11231 11:34:07.517489 # AttributeError: 'Client' object has no attribute 'tpm'
11232 11:34:07.524806 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11233 11:34:07.530943 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11234 11:34:07.534272 # Traceback (most recent call last):
11235 11:34:07.544331 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11236 11:34:07.544887 # if self.tpm:
11237 11:34:07.547748 # ^^^^^^^^
11238 11:34:07.551202 # AttributeError: 'Client' object has no attribute 'tpm'
11239 11:34:07.561224 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11240 11:34:07.567988 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11241 11:34:07.571818 # Traceback (most recent call last):
11242 11:34:07.580984 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11243 11:34:07.581455 # if self.tpm:
11244 11:34:07.584700 # ^^^^^^^^
11245 11:34:07.587988 # AttributeError: 'Client' object has no attribute 'tpm'
11246 11:34:07.598219 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11247 11:34:07.601518 # Exception ignored in: <function Client.__del__ at 0xffff9003ccc0>
11248 11:34:07.604778 # Traceback (most recent call last):
11249 11:34:07.615089 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11250 11:34:07.618379 # if self.tpm:
11251 11:34:07.618766 # ^^^^^^^^
11252 11:34:07.624646 # AttributeError: 'Client' object has no attribute 'tpm'
11253 11:34:07.625032 #
11254 11:34:07.631523 # ======================================================================
11255 11:34:07.638014 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11256 11:34:07.644716 # ----------------------------------------------------------------------
11257 11:34:07.648022 # Traceback (most recent call last):
11258 11:34:07.657867 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11259 11:34:07.664866 # self.root_key = self.client.create_root_key()
11260 11:34:07.668360 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11261 11:34:07.678392 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11262 11:34:07.685838 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11263 11:34:07.690495 # ^^^^^^^^^^^^^^^^^^
11264 11:34:07.699424 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11265 11:34:07.702618 # raise ProtocolError(cc, rc)
11266 11:34:07.706493 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11267 11:34:07.706968 #
11268 11:34:07.712513 # ======================================================================
11269 11:34:07.719628 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11270 11:34:07.725903 # ----------------------------------------------------------------------
11271 11:34:07.729822 # Traceback (most recent call last):
11272 11:34:07.739660 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11273 11:34:07.743088 # self.client = tpm2.Client()
11274 11:34:07.746797 # ^^^^^^^^^^^^^
11275 11:34:07.756694 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11276 11:34:07.762721 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11277 11:34:07.766423 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11278 11:34:07.772601 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11279 11:34:07.773018 #
11280 11:34:07.779449 # ======================================================================
11281 11:34:07.785919 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11282 11:34:07.789631 # ----------------------------------------------------------------------
11283 11:34:07.793369 # Traceback (most recent call last):
11284 11:34:07.802935 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11285 11:34:07.806290 # self.client = tpm2.Client()
11286 11:34:07.809480 # ^^^^^^^^^^^^^
11287 11:34:07.819396 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11288 11:34:07.826374 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11289 11:34:07.829219 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11290 11:34:07.836118 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11291 11:34:07.836531 #
11292 11:34:07.842751 # ======================================================================
11293 11:34:07.850132 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11294 11:34:07.856033 # ----------------------------------------------------------------------
11295 11:34:07.859603 # Traceback (most recent call last):
11296 11:34:07.869441 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11297 11:34:07.872962 # self.client = tpm2.Client()
11298 11:34:07.876445 # ^^^^^^^^^^^^^
11299 11:34:07.882946 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11300 11:34:07.889551 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11301 11:34:07.893567 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11302 11:34:07.899768 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11303 11:34:07.900328 #
11304 11:34:07.906014 # ======================================================================
11305 11:34:07.912553 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11306 11:34:07.919677 # ----------------------------------------------------------------------
11307 11:34:07.923389 # Traceback (most recent call last):
11308 11:34:07.932720 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11309 11:34:07.936219 # self.client = tpm2.Client()
11310 11:34:07.939890 # ^^^^^^^^^^^^^
11311 11:34:07.949632 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11312 11:34:07.955986 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11313 11:34:07.959740 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11314 11:34:07.966320 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11315 11:34:07.966842 #
11316 11:34:07.973060 # ======================================================================
11317 11:34:07.976198 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11318 11:34:07.982923 # ----------------------------------------------------------------------
11319 11:34:07.986379 # Traceback (most recent call last):
11320 11:34:07.996248 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11321 11:34:07.999221 # self.client = tpm2.Client()
11322 11:34:08.002639 # ^^^^^^^^^^^^^
11323 11:34:08.012996 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11324 11:34:08.019656 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11325 11:34:08.023227 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11326 11:34:08.029798 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11327 11:34:08.030175 #
11328 11:34:08.036357 # ======================================================================
11329 11:34:08.042719 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11330 11:34:08.046255 # ----------------------------------------------------------------------
11331 11:34:08.049815 # Traceback (most recent call last):
11332 11:34:08.060677 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11333 11:34:08.066409 # self.client = tpm2.Client()
11334 11:34:08.066805 # ^^^^^^^^^^^^^
11335 11:34:08.076014 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11336 11:34:08.083106 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11337 11:34:08.086667 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11338 11:34:08.093878 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11339 11:34:08.094269 #
11340 11:34:08.097753 # ======================================================================
11341 11:34:08.106656 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11342 11:34:08.113630 # ----------------------------------------------------------------------
11343 11:34:08.116781 # Traceback (most recent call last):
11344 11:34:08.126918 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11345 11:34:08.129642 # self.client = tpm2.Client()
11346 11:34:08.133889 # ^^^^^^^^^^^^^
11347 11:34:08.143224 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11348 11:34:08.146661 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11349 11:34:08.153763 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11350 11:34:08.156298 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11351 11:34:08.156686 #
11352 11:34:08.163389 # ======================================================================
11353 11:34:08.173660 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11354 11:34:08.180063 # ----------------------------------------------------------------------
11355 11:34:08.183999 # Traceback (most recent call last):
11356 11:34:08.193628 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11357 11:34:08.194067 # self.client = tpm2.Client()
11358 11:34:08.196668 # ^^^^^^^^^^^^^
11359 11:34:08.206926 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11360 11:34:08.213371 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11361 11:34:08.216744 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11362 11:34:08.223877 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11363 11:34:08.224321 #
11364 11:34:08.230222 # ----------------------------------------------------------------------
11365 11:34:08.230614 # Ran 9 tests in 0.046s
11366 11:34:08.233575 #
11367 11:34:08.233964 # FAILED (errors=9)
11368 11:34:08.240297 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11369 11:34:08.246768 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11370 11:34:08.247159 #
11371 11:34:08.253686 # ----------------------------------------------------------------------
11372 11:34:08.254075 # Ran 2 tests in 0.027s
11373 11:34:08.257094 #
11374 11:34:08.257528 # OK
11375 11:34:08.260424 ok 1 selftests: tpm2: test_smoke.sh
11376 11:34:08.263935 # selftests: tpm2: test_space.sh
11377 11:34:08.266968 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11378 11:34:08.273949 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11379 11:34:08.280914 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11380 11:34:08.287144 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11381 11:34:08.287538 #
11382 11:34:08.293653 # ======================================================================
11383 11:34:08.300813 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11384 11:34:08.307133 # ----------------------------------------------------------------------
11385 11:34:08.310534 # Traceback (most recent call last):
11386 11:34:08.321375 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11387 11:34:08.324057 # root1 = space1.create_root_key()
11388 11:34:08.327319 # ^^^^^^^^^^^^^^^^^^^^^^^^
11389 11:34:08.338113 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11390 11:34:08.344471 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11391 11:34:08.347912 # ^^^^^^^^^^^^^^^^^^
11392 11:34:08.357977 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11393 11:34:08.361209 # raise ProtocolError(cc, rc)
11394 11:34:08.368486 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11395 11:34:08.368933 #
11396 11:34:08.374294 # ======================================================================
11397 11:34:08.381545 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11398 11:34:08.388078 # ----------------------------------------------------------------------
11399 11:34:08.391479 # Traceback (most recent call last):
11400 11:34:08.401059 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11401 11:34:08.404490 # space1.create_root_key()
11402 11:34:08.414127 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11403 11:34:08.420730 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11404 11:34:08.424194 # ^^^^^^^^^^^^^^^^^^
11405 11:34:08.434835 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11406 11:34:08.437494 # raise ProtocolError(cc, rc)
11407 11:34:08.444205 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11408 11:34:08.444620 #
11409 11:34:08.451509 # ======================================================================
11410 11:34:08.457630 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11411 11:34:08.461739 # ----------------------------------------------------------------------
11412 11:34:08.464547 # Traceback (most recent call last):
11413 11:34:08.477765 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11414 11:34:08.481033 # root1 = space1.create_root_key()
11415 11:34:08.484698 # ^^^^^^^^^^^^^^^^^^^^^^^^
11416 11:34:08.495008 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11417 11:34:08.501386 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11418 11:34:08.504974 # ^^^^^^^^^^^^^^^^^^
11419 11:34:08.514828 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11420 11:34:08.517967 # raise ProtocolError(cc, rc)
11421 11:34:08.524548 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11422 11:34:08.525103 #
11423 11:34:08.531943 # ======================================================================
11424 11:34:08.538108 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11425 11:34:08.544711 # ----------------------------------------------------------------------
11426 11:34:08.548114 # Traceback (most recent call last):
11427 11:34:08.557747 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11428 11:34:08.561376 # root1 = space1.create_root_key()
11429 11:34:08.564658 # ^^^^^^^^^^^^^^^^^^^^^^^^
11430 11:34:08.574842 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11431 11:34:08.581730 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11432 11:34:08.584471 # ^^^^^^^^^^^^^^^^^^
11433 11:34:08.594723 # File "/lava-14864569/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11434 11:34:08.598194 # raise ProtocolError(cc, rc)
11435 11:34:08.604726 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11436 11:34:08.604868 #
11437 11:34:08.611859 # ----------------------------------------------------------------------
11438 11:34:08.614866 # Ran 4 tests in 0.084s
11439 11:34:08.614952 #
11440 11:34:08.615013 # FAILED (errors=4)
11441 11:34:08.618367 not ok 2 selftests: tpm2: test_space.sh # exit=1
11442 11:34:09.011767 tpm2_test_smoke_sh pass
11443 11:34:09.014944 tpm2_test_space_sh fail
11444 11:34:09.086864 + ../../utils/send-to-lava.sh ./output/result.txt
11445 11:34:09.175776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11446 11:34:09.176738 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11448 11:34:09.240845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11449 11:34:09.241586 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11451 11:34:09.305734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11452 11:34:09.306585 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11454 11:34:09.308760 + set +x
11455 11:34:09.312064 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14864569_1.6.2.3.5>
11456 11:34:09.312822 Received signal: <ENDRUN> 1_kselftest-tpm2 14864569_1.6.2.3.5
11457 11:34:09.313363 Ending use of test pattern.
11458 11:34:09.313819 Ending test lava.1_kselftest-tpm2 (14864569_1.6.2.3.5), duration 14.46
11460 11:34:09.315624 <LAVA_TEST_RUNNER EXIT>
11461 11:34:09.316383 ok: lava_test_shell seems to have completed
11462 11:34:09.317184 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11463 11:34:09.317792 end: 3.1 lava-test-shell (duration 00:00:15) [common]
11464 11:34:09.318404 end: 3 lava-test-retry (duration 00:00:15) [common]
11465 11:34:09.319002 start: 4 finalize (timeout 00:07:17) [common]
11466 11:34:09.319600 start: 4.1 power-off (timeout 00:00:30) [common]
11467 11:34:09.320743 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11468 11:34:11.441108 >> Command sent successfully.
11469 11:34:11.454614 Returned 0 in 2 seconds
11470 11:34:11.455179 end: 4.1 power-off (duration 00:00:02) [common]
11472 11:34:11.456104 start: 4.2 read-feedback (timeout 00:07:15) [common]
11473 11:34:11.456696 Listened to connection for namespace 'common' for up to 1s
11474 11:34:12.457428 Finalising connection for namespace 'common'
11475 11:34:12.457582 Disconnecting from shell: Finalise
11476 11:34:12.457653 / #
11477 11:34:12.558013 end: 4.2 read-feedback (duration 00:00:01) [common]
11478 11:34:12.558169 end: 4 finalize (duration 00:00:03) [common]
11479 11:34:12.558285 Cleaning after the job
11480 11:34:12.558388 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/ramdisk
11481 11:34:12.560824 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/kernel
11482 11:34:12.571647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/dtb
11483 11:34:12.571810 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/nfsrootfs
11484 11:34:12.635182 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864569/tftp-deploy-8d2pnof6/modules
11485 11:34:12.641015 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864569
11486 11:34:13.218019 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864569
11487 11:34:13.218189 Job finished correctly