Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 51
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 88
1 11:34:27.236513 lava-dispatcher, installed at version: 2024.05
2 11:34:27.236714 start: 0 validate
3 11:34:27.236828 Start time: 2024-07-17 11:34:27.236823+00:00 (UTC)
4 11:34:27.236962 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:34:27.237106 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:34:27.521592 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:34:27.522383 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:34:27.792797 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:34:27.793597 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:34:28.063180 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:34:28.063707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:34:28.319458 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:34:28.319594 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:34:28.575963 validate duration: 1.34
16 11:34:28.576199 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:34:28.576294 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:34:28.576374 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:34:28.576528 Not decompressing ramdisk as can be used compressed.
20 11:34:28.576617 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 11:34:28.576679 saving as /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/ramdisk/initrd.cpio.gz
22 11:34:28.576734 total size: 5628151 (5 MB)
23 11:34:28.577661 progress 0 % (0 MB)
24 11:34:28.579292 progress 5 % (0 MB)
25 11:34:28.580819 progress 10 % (0 MB)
26 11:34:28.582216 progress 15 % (0 MB)
27 11:34:28.583710 progress 20 % (1 MB)
28 11:34:28.585030 progress 25 % (1 MB)
29 11:34:28.586572 progress 30 % (1 MB)
30 11:34:28.588046 progress 35 % (1 MB)
31 11:34:28.589398 progress 40 % (2 MB)
32 11:34:28.590955 progress 45 % (2 MB)
33 11:34:28.592256 progress 50 % (2 MB)
34 11:34:28.593699 progress 55 % (2 MB)
35 11:34:28.595254 progress 60 % (3 MB)
36 11:34:28.596578 progress 65 % (3 MB)
37 11:34:28.598063 progress 70 % (3 MB)
38 11:34:28.599362 progress 75 % (4 MB)
39 11:34:28.600803 progress 80 % (4 MB)
40 11:34:28.602150 progress 85 % (4 MB)
41 11:34:28.603595 progress 90 % (4 MB)
42 11:34:28.605033 progress 95 % (5 MB)
43 11:34:28.606489 progress 100 % (5 MB)
44 11:34:28.606725 5 MB downloaded in 0.03 s (179.00 MB/s)
45 11:34:28.606874 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:34:28.607093 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:34:28.607170 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:34:28.607245 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:34:28.607375 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:34:28.607435 saving as /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/kernel/Image
52 11:34:28.607487 total size: 54813184 (52 MB)
53 11:34:28.607540 No compression specified
54 11:34:28.608603 progress 0 % (0 MB)
55 11:34:28.621727 progress 5 % (2 MB)
56 11:34:28.635198 progress 10 % (5 MB)
57 11:34:28.648759 progress 15 % (7 MB)
58 11:34:28.662390 progress 20 % (10 MB)
59 11:34:28.676066 progress 25 % (13 MB)
60 11:34:28.689113 progress 30 % (15 MB)
61 11:34:28.702673 progress 35 % (18 MB)
62 11:34:28.715925 progress 40 % (20 MB)
63 11:34:28.729111 progress 45 % (23 MB)
64 11:34:28.742691 progress 50 % (26 MB)
65 11:34:28.756259 progress 55 % (28 MB)
66 11:34:28.769443 progress 60 % (31 MB)
67 11:34:28.782760 progress 65 % (34 MB)
68 11:34:28.796923 progress 70 % (36 MB)
69 11:34:28.810598 progress 75 % (39 MB)
70 11:34:28.824035 progress 80 % (41 MB)
71 11:34:28.837335 progress 85 % (44 MB)
72 11:34:28.850746 progress 90 % (47 MB)
73 11:34:28.864436 progress 95 % (49 MB)
74 11:34:28.877773 progress 100 % (52 MB)
75 11:34:28.878063 52 MB downloaded in 0.27 s (193.20 MB/s)
76 11:34:28.878275 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:34:28.878586 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:34:28.878702 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:34:28.878812 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:34:28.878946 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 11:34:28.879020 saving as /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 11:34:28.879075 total size: 57695 (0 MB)
84 11:34:28.879128 No compression specified
85 11:34:28.880799 progress 56 % (0 MB)
86 11:34:28.881138 progress 100 % (0 MB)
87 11:34:28.881354 0 MB downloaded in 0.00 s (24.16 MB/s)
88 11:34:28.881490 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:34:28.881779 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:34:28.881895 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:34:28.882000 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:34:28.882157 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 11:34:28.882221 saving as /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/nfsrootfs/full.rootfs.tar
95 11:34:28.882274 total size: 69067788 (65 MB)
96 11:34:28.882330 Using unxz to decompress xz
97 11:34:28.883692 progress 0 % (0 MB)
98 11:34:29.082477 progress 5 % (3 MB)
99 11:34:29.283159 progress 10 % (6 MB)
100 11:34:29.484263 progress 15 % (9 MB)
101 11:34:29.647168 progress 20 % (13 MB)
102 11:34:29.827948 progress 25 % (16 MB)
103 11:34:30.016827 progress 30 % (19 MB)
104 11:34:30.135983 progress 35 % (23 MB)
105 11:34:30.233550 progress 40 % (26 MB)
106 11:34:30.434291 progress 45 % (29 MB)
107 11:34:30.632779 progress 50 % (32 MB)
108 11:34:30.827265 progress 55 % (36 MB)
109 11:34:31.038436 progress 60 % (39 MB)
110 11:34:31.232616 progress 65 % (42 MB)
111 11:34:31.434133 progress 70 % (46 MB)
112 11:34:31.630346 progress 75 % (49 MB)
113 11:34:31.835491 progress 80 % (52 MB)
114 11:34:32.012462 progress 85 % (56 MB)
115 11:34:32.212497 progress 90 % (59 MB)
116 11:34:32.418709 progress 95 % (62 MB)
117 11:34:32.625731 progress 100 % (65 MB)
118 11:34:32.631934 65 MB downloaded in 3.75 s (17.57 MB/s)
119 11:34:32.632095 end: 1.4.1 http-download (duration 00:00:04) [common]
121 11:34:32.632303 end: 1.4 download-retry (duration 00:00:04) [common]
122 11:34:32.632379 start: 1.5 download-retry (timeout 00:09:56) [common]
123 11:34:32.632452 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 11:34:32.632565 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:34:32.632626 saving as /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/modules/modules.tar
126 11:34:32.632678 total size: 8610184 (8 MB)
127 11:34:32.632731 Using unxz to decompress xz
128 11:34:32.633970 progress 0 % (0 MB)
129 11:34:32.654155 progress 5 % (0 MB)
130 11:34:32.678730 progress 10 % (0 MB)
131 11:34:32.703196 progress 15 % (1 MB)
132 11:34:32.727552 progress 20 % (1 MB)
133 11:34:32.751185 progress 25 % (2 MB)
134 11:34:32.774590 progress 30 % (2 MB)
135 11:34:32.797966 progress 35 % (2 MB)
136 11:34:32.824414 progress 40 % (3 MB)
137 11:34:32.848869 progress 45 % (3 MB)
138 11:34:32.873586 progress 50 % (4 MB)
139 11:34:32.897594 progress 55 % (4 MB)
140 11:34:32.922661 progress 60 % (4 MB)
141 11:34:32.945682 progress 65 % (5 MB)
142 11:34:32.971112 progress 70 % (5 MB)
143 11:34:32.997448 progress 75 % (6 MB)
144 11:34:33.024656 progress 80 % (6 MB)
145 11:34:33.047982 progress 85 % (7 MB)
146 11:34:33.071847 progress 90 % (7 MB)
147 11:34:33.095993 progress 95 % (7 MB)
148 11:34:33.122365 progress 100 % (8 MB)
149 11:34:33.128485 8 MB downloaded in 0.50 s (16.56 MB/s)
150 11:34:33.128729 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:34:33.129063 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:34:33.129168 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 11:34:33.129270 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 11:34:34.749659 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx
156 11:34:34.749853 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:34:34.749972 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 11:34:34.750181 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6
159 11:34:34.750305 makedir: /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin
160 11:34:34.750403 makedir: /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/tests
161 11:34:34.750507 makedir: /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/results
162 11:34:34.750617 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-add-keys
163 11:34:34.750772 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-add-sources
164 11:34:34.750916 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-background-process-start
165 11:34:34.751059 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-background-process-stop
166 11:34:34.751212 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-common-functions
167 11:34:34.751357 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-echo-ipv4
168 11:34:34.751497 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-install-packages
169 11:34:34.751636 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-installed-packages
170 11:34:34.751760 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-os-build
171 11:34:34.751900 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-probe-channel
172 11:34:34.752031 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-probe-ip
173 11:34:34.752173 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-target-ip
174 11:34:34.752316 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-target-mac
175 11:34:34.752453 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-target-storage
176 11:34:34.752572 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-case
177 11:34:34.752686 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-event
178 11:34:34.752803 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-feedback
179 11:34:34.752944 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-raise
180 11:34:34.753086 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-reference
181 11:34:34.753225 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-runner
182 11:34:34.753370 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-set
183 11:34:34.753518 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-test-shell
184 11:34:34.753663 Updating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-install-packages (oe)
185 11:34:34.790578 Updating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/bin/lava-installed-packages (oe)
186 11:34:34.790752 Creating /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/environment
187 11:34:34.790873 LAVA metadata
188 11:34:34.790946 - LAVA_JOB_ID=14864601
189 11:34:34.791005 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:34:34.791120 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 11:34:34.791179 skipped lava-vland-overlay
192 11:34:34.791248 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:34:34.791321 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 11:34:34.791376 skipped lava-multinode-overlay
195 11:34:34.791441 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:34:34.791516 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 11:34:34.791583 Loading test definitions
198 11:34:34.791659 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 11:34:34.791717 Using /lava-14864601 at stage 0
200 11:34:34.792116 uuid=14864601_1.6.2.3.1 testdef=None
201 11:34:34.792247 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:34:34.792373 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 11:34:34.792876 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:34:34.793077 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 11:34:34.793613 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:34:34.793820 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 11:34:34.842609 runner path: /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/0/tests/0_lc-compliance test_uuid 14864601_1.6.2.3.1
210 11:34:34.842823 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:34:34.843013 Creating lava-test-runner.conf files
213 11:34:34.843069 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864601/lava-overlay-rvqz1cj6/lava-14864601/0 for stage 0
214 11:34:34.843151 - 0_lc-compliance
215 11:34:34.843242 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:34:34.843319 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 11:34:34.849406 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:34:34.849511 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 11:34:34.849589 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:34:34.849671 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:34:34.849803 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 11:34:34.993687 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:34:34.993832 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 11:34:34.993933 extracting modules file /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx
225 11:34:35.224072 extracting modules file /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864601/extract-overlay-ramdisk-erjvmlca/ramdisk
226 11:34:35.472462 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:34:35.472603 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 11:34:35.472683 [common] Applying overlay to NFS
229 11:34:35.472781 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864601/compress-overlay-gbcboq51/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx
230 11:34:35.479105 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:34:35.479199 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 11:34:35.479278 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:34:35.479354 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 11:34:35.479418 Building ramdisk /var/lib/lava/dispatcher/tmp/14864601/extract-overlay-ramdisk-erjvmlca/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864601/extract-overlay-ramdisk-erjvmlca/ramdisk
235 11:34:35.768543 >> 129966 blocks
236 11:34:37.894793 rename /var/lib/lava/dispatcher/tmp/14864601/extract-overlay-ramdisk-erjvmlca/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/ramdisk/ramdisk.cpio.gz
237 11:34:37.894944 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:34:37.895029 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 11:34:37.895107 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 11:34:37.895183 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/kernel/Image']
241 11:34:52.123824 Returned 0 in 14 seconds
242 11:34:52.124018 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/kernel/image.itb
243 11:34:52.497969 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:34:52.498161 output: Created: Wed Jul 17 12:34:52 2024
245 11:34:52.498250 output: Image 0 (kernel-1)
246 11:34:52.498332 output: Description:
247 11:34:52.498485 output: Created: Wed Jul 17 12:34:52 2024
248 11:34:52.498541 output: Type: Kernel Image
249 11:34:52.498593 output: Compression: lzma compressed
250 11:34:52.498645 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
251 11:34:52.498696 output: Architecture: AArch64
252 11:34:52.498744 output: OS: Linux
253 11:34:52.498792 output: Load Address: 0x00000000
254 11:34:52.498839 output: Entry Point: 0x00000000
255 11:34:52.498887 output: Hash algo: crc32
256 11:34:52.498938 output: Hash value: 83448d17
257 11:34:52.498986 output: Image 1 (fdt-1)
258 11:34:52.499033 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
259 11:34:52.499081 output: Created: Wed Jul 17 12:34:52 2024
260 11:34:52.499128 output: Type: Flat Device Tree
261 11:34:52.499176 output: Compression: uncompressed
262 11:34:52.499223 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
263 11:34:52.499272 output: Architecture: AArch64
264 11:34:52.499321 output: Hash algo: crc32
265 11:34:52.499368 output: Hash value: a9713552
266 11:34:52.499416 output: Image 2 (ramdisk-1)
267 11:34:52.499463 output: Description: unavailable
268 11:34:52.499511 output: Created: Wed Jul 17 12:34:52 2024
269 11:34:52.499560 output: Type: RAMDisk Image
270 11:34:52.499607 output: Compression: uncompressed
271 11:34:52.499654 output: Data Size: 18720610 Bytes = 18281.85 KiB = 17.85 MiB
272 11:34:52.499701 output: Architecture: AArch64
273 11:34:52.499748 output: OS: Linux
274 11:34:52.499795 output: Load Address: unavailable
275 11:34:52.499842 output: Entry Point: unavailable
276 11:34:52.499889 output: Hash algo: crc32
277 11:34:52.499936 output: Hash value: 464a0bbd
278 11:34:52.499983 output: Default Configuration: 'conf-1'
279 11:34:52.500030 output: Configuration 0 (conf-1)
280 11:34:52.500077 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
281 11:34:52.500124 output: Kernel: kernel-1
282 11:34:52.500171 output: Init Ramdisk: ramdisk-1
283 11:34:52.500218 output: FDT: fdt-1
284 11:34:52.500264 output: Loadables: kernel-1
285 11:34:52.500310 output:
286 11:34:52.500463 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 11:34:52.500537 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 11:34:52.500610 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 11:34:52.500683 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 11:34:52.500739 No LXC device requested
291 11:34:52.500803 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:34:52.500873 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 11:34:52.500938 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:34:52.500992 Checking files for TFTP limit of 4294967296 bytes.
295 11:34:52.501358 end: 1 tftp-deploy (duration 00:00:24) [common]
296 11:34:52.501444 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:34:52.501519 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:34:52.501606 substitutions:
299 11:34:52.501663 - {DTB}: 14864601/tftp-deploy-znwinunr/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
300 11:34:52.501716 - {INITRD}: 14864601/tftp-deploy-znwinunr/ramdisk/ramdisk.cpio.gz
301 11:34:52.501766 - {KERNEL}: 14864601/tftp-deploy-znwinunr/kernel/Image
302 11:34:52.501816 - {LAVA_MAC}: None
303 11:34:52.501864 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx
304 11:34:52.501912 - {NFS_SERVER_IP}: 192.168.201.1
305 11:34:52.501961 - {PRESEED_CONFIG}: None
306 11:34:52.502041 - {PRESEED_LOCAL}: None
307 11:34:52.502107 - {RAMDISK}: 14864601/tftp-deploy-znwinunr/ramdisk/ramdisk.cpio.gz
308 11:34:52.502156 - {ROOT_PART}: None
309 11:34:52.502203 - {ROOT}: None
310 11:34:52.502251 - {SERVER_IP}: 192.168.201.1
311 11:34:52.502298 - {TEE}: None
312 11:34:52.502351 Parsed boot commands:
313 11:34:52.502399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:34:52.502541 Parsed boot commands: tftpboot 192.168.201.1 14864601/tftp-deploy-znwinunr/kernel/image.itb 14864601/tftp-deploy-znwinunr/kernel/cmdline
315 11:34:52.502617 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:34:52.502688 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:34:52.502757 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:34:52.502824 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:34:52.502877 Not connected, no need to disconnect.
320 11:34:52.502940 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:34:52.503006 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:34:52.503058 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-4'
323 11:34:52.506305 Setting prompt string to ['lava-test: # ']
324 11:34:52.506653 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:34:52.506817 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:34:52.506948 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:34:52.507045 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:34:52.507222 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=reboot']
329 11:35:01.651464 >> Command sent successfully.
330 11:35:01.654879 Returned 0 in 9 seconds
331 11:35:01.655024 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:35:01.655228 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:35:01.655311 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:35:01.655384 Setting prompt string to 'Starting depthcharge on Juniper...'
336 11:35:01.655438 Changing prompt to 'Starting depthcharge on Juniper...'
337 11:35:01.655499 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
338 11:35:01.655834 [Enter `^Ec?' for help]
339 11:35:07.278904 [DL] 00000000 00000000 010701
340 11:35:07.284506
341 11:35:07.284666
342 11:35:07.284788 F0: 102B 0000
343 11:35:07.284910
344 11:35:07.285019 F3: 1006 0033 [0200]
345 11:35:07.287355
346 11:35:07.287536 F3: 4001 00E0 [0200]
347 11:35:07.287679
348 11:35:07.287809 F3: 0000 0000
349 11:35:07.290518
350 11:35:07.290732 V0: 0000 0000 [0001]
351 11:35:07.290902
352 11:35:07.291056 00: 1027 0002
353 11:35:07.291212
354 11:35:07.293956 01: 0000 0000
355 11:35:07.294198
356 11:35:07.294368 BP: 0C00 0251 [0000]
357 11:35:07.294525
358 11:35:07.297428 G0: 1182 0000
359 11:35:07.297693
360 11:35:07.297902 EC: 0004 0000 [0001]
361 11:35:07.298125
362 11:35:07.301151 S7: 0000 0000 [0000]
363 11:35:07.301495
364 11:35:07.303944 CC: 0000 0000 [0001]
365 11:35:07.304290
366 11:35:07.304559 T0: 0000 00DB [000F]
367 11:35:07.304814
368 11:35:07.305050 Jump to BL
369 11:35:07.305297
370 11:35:07.340146
371 11:35:07.340520
372 11:35:07.350205 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
373 11:35:07.352979 ARM64: Exception handlers installed.
374 11:35:07.353498 ARM64: Testing exception
375 11:35:07.356202 ARM64: Done test exception
376 11:35:07.360767 WDT: Last reset was cold boot
377 11:35:07.364331 SPI0(PAD0) initialized at 992727 Hz
378 11:35:07.367144 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
379 11:35:07.367542 Manufacturer: ef
380 11:35:07.373786 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
381 11:35:07.386509 Probing TPM: . done!
382 11:35:07.386901 TPM ready after 0 ms
383 11:35:07.394097 Connected to device vid:did:rid of 1ae0:0028:00
384 11:35:07.400455 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
385 11:35:07.435274 Initialized TPM device CR50 revision 0
386 11:35:07.447814 tlcl_send_startup: Startup return code is 0
387 11:35:07.448195 TPM: setup succeeded
388 11:35:07.457340 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
389 11:35:07.460263 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
390 11:35:07.463139 in-header: 03 19 00 00 08 00 00 00
391 11:35:07.466445 in-data: a2 e0 47 00 13 00 00 00
392 11:35:07.470071 Chrome EC: UHEPI supported
393 11:35:07.476650 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
394 11:35:07.480173 in-header: 03 a1 00 00 08 00 00 00
395 11:35:07.483056 in-data: 84 60 60 10 00 00 00 00
396 11:35:07.483454 Phase 1
397 11:35:07.487211 FMAP: area GBB found @ 3f5000 (12032 bytes)
398 11:35:07.493709 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
399 11:35:07.499438 VB2:vb2_check_recovery() Recovery was requested manually
400 11:35:07.502949 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
401 11:35:07.506818 Recovery requested (1009000e)
402 11:35:07.518951 tlcl_extend: response is 0
403 11:35:07.523716 tlcl_extend: response is 0
404 11:35:07.549056
405 11:35:07.549432
406 11:35:07.555278 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
407 11:35:07.558767 ARM64: Exception handlers installed.
408 11:35:07.561833 ARM64: Testing exception
409 11:35:07.565477 ARM64: Done test exception
410 11:35:07.580611 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x9a6d, sec=0x202a
411 11:35:07.587482 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
412 11:35:07.590693 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
413 11:35:07.599054 [RTC]rtc_get_frequency_meter,134: input=0xf, output=822
414 11:35:07.606000 [RTC]rtc_get_frequency_meter,134: input=0x7, output=698
415 11:35:07.612931 [RTC]rtc_get_frequency_meter,134: input=0xb, output=760
416 11:35:07.620138 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791
417 11:35:07.626641 [RTC]rtc_get_frequency_meter,134: input=0xe, output=806
418 11:35:07.634098 [RTC]rtc_get_frequency_meter,134: input=0xd, output=791
419 11:35:07.640802 [RTC]rtc_get_frequency_meter,134: input=0xe, output=807
420 11:35:07.644018 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x9a6d
421 11:35:07.650422 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
422 11:35:07.653868 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
423 11:35:07.660446 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
424 11:35:07.663532 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
425 11:35:07.666660 in-header: 03 19 00 00 08 00 00 00
426 11:35:07.670349 in-data: a2 e0 47 00 13 00 00 00
427 11:35:07.670760 Chrome EC: UHEPI supported
428 11:35:07.676557 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
429 11:35:07.679905 in-header: 03 a1 00 00 08 00 00 00
430 11:35:07.683079 in-data: 84 60 60 10 00 00 00 00
431 11:35:07.686128 Skip loading cached calibration data
432 11:35:07.692788 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
433 11:35:07.696505 in-header: 03 a1 00 00 08 00 00 00
434 11:35:07.699437 in-data: 84 60 60 10 00 00 00 00
435 11:35:07.705992 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
436 11:35:07.709299 in-header: 03 a1 00 00 08 00 00 00
437 11:35:07.712538 in-data: 84 60 60 10 00 00 00 00
438 11:35:07.716489 ADC[3]: Raw value=214183 ID=1
439 11:35:07.716872 Manufacturer: ef
440 11:35:07.722798 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
441 11:35:07.725976 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
442 11:35:07.729010 CBFS @ 21000 size 3d4000
443 11:35:07.735934 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
444 11:35:07.738936 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
445 11:35:07.742155 CBFS: Found @ offset 3c700 size 44
446 11:35:07.745749 DRAM-K: Full Calibration
447 11:35:07.748766 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
448 11:35:07.752544 CBFS @ 21000 size 3d4000
449 11:35:07.759029 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
450 11:35:07.759413 CBFS: Locating 'fallback/dram'
451 11:35:07.765550 CBFS: Found @ offset 24b00 size 12268
452 11:35:07.792178 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
453 11:35:07.794994 ddr_geometry: 1, config: 0x0
454 11:35:07.798727 header.status = 0x0
455 11:35:07.802207 header.magic = 0x44524d4b (expected: 0x44524d4b)
456 11:35:07.805207 header.version = 0x5 (expected: 0x5)
457 11:35:07.808467 header.size = 0x8f0 (expected: 0x8f0)
458 11:35:07.808898 header.config = 0x0
459 11:35:07.811912 header.flags = 0x0
460 11:35:07.814774 header.checksum = 0x0
461 11:35:07.821424 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
462 11:35:07.825426 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
463 11:35:07.831411 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
464 11:35:07.831795 ddr_geometry:1
465 11:35:07.834518 [EMI] new MDL number = 1
466 11:35:07.834901 dram_cbt_mode_extern: 0
467 11:35:07.837725 dram_cbt_mode [RK0]: 0, [RK1]: 0
468 11:35:07.845249 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
469 11:35:07.845632
470 11:35:07.845926
471 11:35:07.847856 [Bianco] ETT version 0.0.0.1
472 11:35:07.851215 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
473 11:35:07.851594
474 11:35:07.854527 vSetVcoreByFreq with vcore:762500, freq=1600
475 11:35:07.854909
476 11:35:07.857597 [DramcInit]
477 11:35:07.861243 AutoRefreshCKEOff AutoREF OFF
478 11:35:07.861623 DDRPhyPLLSetting-CKEOFF
479 11:35:07.864342 DDRPhyPLLSetting-CKEON
480 11:35:07.864721
481 11:35:07.865018 Enable WDQS
482 11:35:07.868833 [ModeRegInit_LP4] CH0 RK0
483 11:35:07.872078 Write Rank0 MR13 =0x18
484 11:35:07.872459 Write Rank0 MR12 =0x5d
485 11:35:07.875673 Write Rank0 MR1 =0x56
486 11:35:07.879358 Write Rank0 MR2 =0x1a
487 11:35:07.879738 Write Rank0 MR11 =0x0
488 11:35:07.881917 Write Rank0 MR22 =0x38
489 11:35:07.885596 Write Rank0 MR14 =0x5d
490 11:35:07.885978 Write Rank0 MR3 =0x30
491 11:35:07.889094 Write Rank0 MR13 =0x58
492 11:35:07.889473 Write Rank0 MR12 =0x5d
493 11:35:07.891949 Write Rank0 MR1 =0x56
494 11:35:07.895861 Write Rank0 MR2 =0x2d
495 11:35:07.896257 Write Rank0 MR11 =0x23
496 11:35:07.898516 Write Rank0 MR22 =0x34
497 11:35:07.898906 Write Rank0 MR14 =0x10
498 11:35:07.902080 Write Rank0 MR3 =0x30
499 11:35:07.905139 Write Rank0 MR13 =0xd8
500 11:35:07.905542 [ModeRegInit_LP4] CH0 RK1
501 11:35:07.908359 Write Rank1 MR13 =0x18
502 11:35:07.912056 Write Rank1 MR12 =0x5d
503 11:35:07.912503 Write Rank1 MR1 =0x56
504 11:35:07.915284 Write Rank1 MR2 =0x1a
505 11:35:07.915693 Write Rank1 MR11 =0x0
506 11:35:07.918428 Write Rank1 MR22 =0x38
507 11:35:07.922053 Write Rank1 MR14 =0x5d
508 11:35:07.922453 Write Rank1 MR3 =0x30
509 11:35:07.924748 Write Rank1 MR13 =0x58
510 11:35:07.928940 Write Rank1 MR12 =0x5d
511 11:35:07.929340 Write Rank1 MR1 =0x56
512 11:35:07.931716 Write Rank1 MR2 =0x2d
513 11:35:07.932128 Write Rank1 MR11 =0x23
514 11:35:07.934868 Write Rank1 MR22 =0x34
515 11:35:07.937929 Write Rank1 MR14 =0x10
516 11:35:07.938344 Write Rank1 MR3 =0x30
517 11:35:07.941172 Write Rank1 MR13 =0xd8
518 11:35:07.944561 [ModeRegInit_LP4] CH1 RK0
519 11:35:07.944940 Write Rank0 MR13 =0x18
520 11:35:07.948077 Write Rank0 MR12 =0x5d
521 11:35:07.950843 Write Rank0 MR1 =0x56
522 11:35:07.951220 Write Rank0 MR2 =0x1a
523 11:35:07.954429 Write Rank0 MR11 =0x0
524 11:35:07.954808 Write Rank0 MR22 =0x38
525 11:35:07.958459 Write Rank0 MR14 =0x5d
526 11:35:07.961164 Write Rank0 MR3 =0x30
527 11:35:07.961544 Write Rank0 MR13 =0x58
528 11:35:07.964727 Write Rank0 MR12 =0x5d
529 11:35:07.965121 Write Rank0 MR1 =0x56
530 11:35:07.967510 Write Rank0 MR2 =0x2d
531 11:35:07.970898 Write Rank0 MR11 =0x23
532 11:35:07.971278 Write Rank0 MR22 =0x34
533 11:35:07.973753 Write Rank0 MR14 =0x10
534 11:35:07.976977 Write Rank0 MR3 =0x30
535 11:35:07.977352 Write Rank0 MR13 =0xd8
536 11:35:07.980643 [ModeRegInit_LP4] CH1 RK1
537 11:35:07.983820 Write Rank1 MR13 =0x18
538 11:35:07.984217 Write Rank1 MR12 =0x5d
539 11:35:07.987095 Write Rank1 MR1 =0x56
540 11:35:07.987488 Write Rank1 MR2 =0x1a
541 11:35:07.990791 Write Rank1 MR11 =0x0
542 11:35:07.993776 Write Rank1 MR22 =0x38
543 11:35:07.994211 Write Rank1 MR14 =0x5d
544 11:35:07.996891 Write Rank1 MR3 =0x30
545 11:35:07.997285 Write Rank1 MR13 =0x58
546 11:35:08.000098 Write Rank1 MR12 =0x5d
547 11:35:08.003634 Write Rank1 MR1 =0x56
548 11:35:08.004028 Write Rank1 MR2 =0x2d
549 11:35:08.006826 Write Rank1 MR11 =0x23
550 11:35:08.010457 Write Rank1 MR22 =0x34
551 11:35:08.010851 Write Rank1 MR14 =0x10
552 11:35:08.013284 Write Rank1 MR3 =0x30
553 11:35:08.013665 Write Rank1 MR13 =0xd8
554 11:35:08.016623 match AC timing 3
555 11:35:08.026229 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
556 11:35:08.026615 [MiockJmeterHQA]
557 11:35:08.033184 vSetVcoreByFreq with vcore:762500, freq=1600
558 11:35:08.138280
559 11:35:08.138673 MIOCK jitter meter ch=0
560 11:35:08.138971
561 11:35:08.141397 1T = (103-19) = 84 dly cells
562 11:35:08.147708 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
563 11:35:08.150997 vSetVcoreByFreq with vcore:725000, freq=1200
564 11:35:08.251705
565 11:35:08.252095 MIOCK jitter meter ch=0
566 11:35:08.252391
567 11:35:08.254962 1T = (97-19) = 78 dly cells
568 11:35:08.262515 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
569 11:35:08.265284 vSetVcoreByFreq with vcore:725000, freq=800
570 11:35:08.365145
571 11:35:08.365542 MIOCK jitter meter ch=0
572 11:35:08.365845
573 11:35:08.368400 1T = (97-19) = 78 dly cells
574 11:35:08.374895 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
575 11:35:08.377914 vSetVcoreByFreq with vcore:762500, freq=1600
576 11:35:08.380913 vSetVcoreByFreq with vcore:762500, freq=1600
577 11:35:08.381306
578 11:35:08.381614 K DRVP
579 11:35:08.384756 1. OCD DRVP=0 CALOUT=0
580 11:35:08.387827 1. OCD DRVP=1 CALOUT=0
581 11:35:08.388221 1. OCD DRVP=2 CALOUT=0
582 11:35:08.390877 1. OCD DRVP=3 CALOUT=0
583 11:35:08.394518 1. OCD DRVP=4 CALOUT=0
584 11:35:08.394909 1. OCD DRVP=5 CALOUT=0
585 11:35:08.397775 1. OCD DRVP=6 CALOUT=0
586 11:35:08.398198 1. OCD DRVP=7 CALOUT=0
587 11:35:08.401095 1. OCD DRVP=8 CALOUT=1
588 11:35:08.401486
589 11:35:08.404261 1. OCD DRVP calibration OK! DRVP=8
590 11:35:08.404661
591 11:35:08.404959
592 11:35:08.405230
593 11:35:08.405488 K ODTN
594 11:35:08.407744 3. OCD ODTN=0 ,CALOUT=1
595 11:35:08.410816 3. OCD ODTN=1 ,CALOUT=1
596 11:35:08.411208 3. OCD ODTN=2 ,CALOUT=1
597 11:35:08.414629 3. OCD ODTN=3 ,CALOUT=1
598 11:35:08.417794 3. OCD ODTN=4 ,CALOUT=1
599 11:35:08.418218 3. OCD ODTN=5 ,CALOUT=1
600 11:35:08.420617 3. OCD ODTN=6 ,CALOUT=1
601 11:35:08.424457 3. OCD ODTN=7 ,CALOUT=0
602 11:35:08.424846
603 11:35:08.428113 3. OCD ODTN calibration OK! ODTN=7
604 11:35:08.428500
605 11:35:08.430539 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
606 11:35:08.434036 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
607 11:35:08.440705 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
608 11:35:08.441087
609 11:35:08.441381 K DRVP
610 11:35:08.441653 1. OCD DRVP=0 CALOUT=0
611 11:35:08.443780 1. OCD DRVP=1 CALOUT=0
612 11:35:08.447083 1. OCD DRVP=2 CALOUT=0
613 11:35:08.447471 1. OCD DRVP=3 CALOUT=0
614 11:35:08.450449 1. OCD DRVP=4 CALOUT=0
615 11:35:08.453941 1. OCD DRVP=5 CALOUT=0
616 11:35:08.454373 1. OCD DRVP=6 CALOUT=0
617 11:35:08.457284 1. OCD DRVP=7 CALOUT=0
618 11:35:08.460466 1. OCD DRVP=8 CALOUT=0
619 11:35:08.460856 1. OCD DRVP=9 CALOUT=1
620 11:35:08.461161
621 11:35:08.463663 1. OCD DRVP calibration OK! DRVP=9
622 11:35:08.464051
623 11:35:08.464346
624 11:35:08.464615
625 11:35:08.466785 K ODTN
626 11:35:08.467162 3. OCD ODTN=0 ,CALOUT=1
627 11:35:08.470202 3. OCD ODTN=1 ,CALOUT=1
628 11:35:08.470636 3. OCD ODTN=2 ,CALOUT=1
629 11:35:08.474051 3. OCD ODTN=3 ,CALOUT=1
630 11:35:08.476519 3. OCD ODTN=4 ,CALOUT=1
631 11:35:08.476924 3. OCD ODTN=5 ,CALOUT=1
632 11:35:08.480415 3. OCD ODTN=6 ,CALOUT=1
633 11:35:08.483745 3. OCD ODTN=7 ,CALOUT=1
634 11:35:08.484146 3. OCD ODTN=8 ,CALOUT=1
635 11:35:08.486902 3. OCD ODTN=9 ,CALOUT=1
636 11:35:08.489792 3. OCD ODTN=10 ,CALOUT=1
637 11:35:08.490231 3. OCD ODTN=11 ,CALOUT=1
638 11:35:08.493397 3. OCD ODTN=12 ,CALOUT=1
639 11:35:08.496765 3. OCD ODTN=13 ,CALOUT=1
640 11:35:08.497169 3. OCD ODTN=14 ,CALOUT=0
641 11:35:08.500069
642 11:35:08.500465 3. OCD ODTN calibration OK! ODTN=14
643 11:35:08.502965
644 11:35:08.506337 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=14
645 11:35:08.509685 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=14
646 11:35:08.513082 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=14 (After Adjust)
647 11:35:08.513476
648 11:35:08.516413 [DramcInit]
649 11:35:08.519418 AutoRefreshCKEOff AutoREF OFF
650 11:35:08.520013 DDRPhyPLLSetting-CKEOFF
651 11:35:08.523066 DDRPhyPLLSetting-CKEON
652 11:35:08.523570
653 11:35:08.524070 Enable WDQS
654 11:35:08.524559 ==
655 11:35:08.529789 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
656 11:35:08.532564 fsp= 1, odt_onoff= 1, Byte mode= 0
657 11:35:08.533045 ==
658 11:35:08.536068 [Duty_Offset_Calibration]
659 11:35:08.536409
660 11:35:08.536694 ===========================
661 11:35:08.539172 B0:2 B1:2 CA:1
662 11:35:08.560032 ==
663 11:35:08.563798 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
664 11:35:08.567359 fsp= 1, odt_onoff= 1, Byte mode= 0
665 11:35:08.567479 ==
666 11:35:08.570170 [Duty_Offset_Calibration]
667 11:35:08.570283
668 11:35:08.573296 ===========================
669 11:35:08.573397 B0:0 B1:0 CA:-1
670 11:35:08.606395 [ModeRegInit_LP4] CH0 RK0
671 11:35:08.608639 Write Rank0 MR13 =0x18
672 11:35:08.608719 Write Rank0 MR12 =0x5d
673 11:35:08.612346 Write Rank0 MR1 =0x56
674 11:35:08.615704 Write Rank0 MR2 =0x1a
675 11:35:08.615780 Write Rank0 MR11 =0x0
676 11:35:08.618651 Write Rank0 MR22 =0x38
677 11:35:08.622108 Write Rank0 MR14 =0x5d
678 11:35:08.622183 Write Rank0 MR3 =0x30
679 11:35:08.625455 Write Rank0 MR13 =0x58
680 11:35:08.625530 Write Rank0 MR12 =0x5d
681 11:35:08.628975 Write Rank0 MR1 =0x56
682 11:35:08.632554 Write Rank0 MR2 =0x2d
683 11:35:08.632630 Write Rank0 MR11 =0x23
684 11:35:08.635631 Write Rank0 MR22 =0x34
685 11:35:08.635705 Write Rank0 MR14 =0x10
686 11:35:08.638596 Write Rank0 MR3 =0x30
687 11:35:08.641760 Write Rank0 MR13 =0xd8
688 11:35:08.641860 [ModeRegInit_LP4] CH0 RK1
689 11:35:08.645514 Write Rank1 MR13 =0x18
690 11:35:08.648595 Write Rank1 MR12 =0x5d
691 11:35:08.648729 Write Rank1 MR1 =0x56
692 11:35:08.651670 Write Rank1 MR2 =0x1a
693 11:35:08.651765 Write Rank1 MR11 =0x0
694 11:35:08.655234 Write Rank1 MR22 =0x38
695 11:35:08.658170 Write Rank1 MR14 =0x5d
696 11:35:08.658263 Write Rank1 MR3 =0x30
697 11:35:08.661902 Write Rank1 MR13 =0x58
698 11:35:08.665033 Write Rank1 MR12 =0x5d
699 11:35:08.665126 Write Rank1 MR1 =0x56
700 11:35:08.668349 Write Rank1 MR2 =0x2d
701 11:35:08.668443 Write Rank1 MR11 =0x23
702 11:35:08.671230 Write Rank1 MR22 =0x34
703 11:35:08.674955 Write Rank1 MR14 =0x10
704 11:35:08.675045 Write Rank1 MR3 =0x30
705 11:35:08.678870 Write Rank1 MR13 =0xd8
706 11:35:08.681667 [ModeRegInit_LP4] CH1 RK0
707 11:35:08.681742 Write Rank0 MR13 =0x18
708 11:35:08.684835 Write Rank0 MR12 =0x5d
709 11:35:08.684911 Write Rank0 MR1 =0x56
710 11:35:08.687958 Write Rank0 MR2 =0x1a
711 11:35:08.691403 Write Rank0 MR11 =0x0
712 11:35:08.691504 Write Rank0 MR22 =0x38
713 11:35:08.694411 Write Rank0 MR14 =0x5d
714 11:35:08.697665 Write Rank0 MR3 =0x30
715 11:35:08.697767 Write Rank0 MR13 =0x58
716 11:35:08.701018 Write Rank0 MR12 =0x5d
717 11:35:08.701113 Write Rank0 MR1 =0x56
718 11:35:08.704845 Write Rank0 MR2 =0x2d
719 11:35:08.707450 Write Rank0 MR11 =0x23
720 11:35:08.707542 Write Rank0 MR22 =0x34
721 11:35:08.711097 Write Rank0 MR14 =0x10
722 11:35:08.714180 Write Rank0 MR3 =0x30
723 11:35:08.714292 Write Rank0 MR13 =0xd8
724 11:35:08.717863 [ModeRegInit_LP4] CH1 RK1
725 11:35:08.717974 Write Rank1 MR13 =0x18
726 11:35:08.720541 Write Rank1 MR12 =0x5d
727 11:35:08.724267 Write Rank1 MR1 =0x56
728 11:35:08.724381 Write Rank1 MR2 =0x1a
729 11:35:08.728064 Write Rank1 MR11 =0x0
730 11:35:08.730873 Write Rank1 MR22 =0x38
731 11:35:08.730972 Write Rank1 MR14 =0x5d
732 11:35:08.733869 Write Rank1 MR3 =0x30
733 11:35:08.733981 Write Rank1 MR13 =0x58
734 11:35:08.737720 Write Rank1 MR12 =0x5d
735 11:35:08.740931 Write Rank1 MR1 =0x56
736 11:35:08.741034 Write Rank1 MR2 =0x2d
737 11:35:08.743696 Write Rank1 MR11 =0x23
738 11:35:08.743819 Write Rank1 MR22 =0x34
739 11:35:08.747030 Write Rank1 MR14 =0x10
740 11:35:08.750464 Write Rank1 MR3 =0x30
741 11:35:08.750535 Write Rank1 MR13 =0xd8
742 11:35:08.754230 match AC timing 3
743 11:35:08.763939 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
744 11:35:08.764019 DramC Write-DBI off
745 11:35:08.767235 DramC Read-DBI off
746 11:35:08.767310 Write Rank0 MR13 =0x59
747 11:35:08.767369 ==
748 11:35:08.773747 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
749 11:35:08.777350 fsp= 1, odt_onoff= 1, Byte mode= 0
750 11:35:08.777426 ==
751 11:35:08.780318 === u2Vref_new: 0x56 --> 0x2d
752 11:35:08.783539 === u2Vref_new: 0x58 --> 0x38
753 11:35:08.786896 === u2Vref_new: 0x5a --> 0x39
754 11:35:08.789875 === u2Vref_new: 0x5c --> 0x3c
755 11:35:08.793181 === u2Vref_new: 0x5e --> 0x3d
756 11:35:08.797080 === u2Vref_new: 0x60 --> 0xa0
757 11:35:08.800184 [CA 0] Center 34 (6~63) winsize 58
758 11:35:08.803319 [CA 1] Center 35 (8~63) winsize 56
759 11:35:08.803397 [CA 2] Center 30 (2~59) winsize 58
760 11:35:08.806330 [CA 3] Center 25 (-3~53) winsize 57
761 11:35:08.810368 [CA 4] Center 25 (-2~53) winsize 56
762 11:35:08.813614 [CA 5] Center 31 (2~60) winsize 59
763 11:35:08.813689
764 11:35:08.816322 [CATrainingPosCal] consider 1 rank data
765 11:35:08.819732 u2DelayCellTimex100 = 744/100 ps
766 11:35:08.823349 CA0 delay=34 (6~63),Diff = 9 PI (11 cell)
767 11:35:08.829755 CA1 delay=35 (8~63),Diff = 10 PI (13 cell)
768 11:35:08.832991 CA2 delay=30 (2~59),Diff = 5 PI (6 cell)
769 11:35:08.836299 CA3 delay=25 (-3~53),Diff = 0 PI (0 cell)
770 11:35:08.839857 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
771 11:35:08.842914 CA5 delay=31 (2~60),Diff = 6 PI (7 cell)
772 11:35:08.843005
773 11:35:08.846730 CA PerBit enable=1, Macro0, CA PI delay=25
774 11:35:08.849899 === u2Vref_new: 0x5e --> 0x3d
775 11:35:08.849997
776 11:35:08.852852 Vref(ca) range 1: 30
777 11:35:08.852948
778 11:35:08.853037 CS Dly= 8 (39-0-32)
779 11:35:08.856425 Write Rank0 MR13 =0xd8
780 11:35:08.859267 Write Rank0 MR13 =0xd8
781 11:35:08.859344 Write Rank0 MR12 =0x5e
782 11:35:08.862875 Write Rank1 MR13 =0x59
783 11:35:08.862951 ==
784 11:35:08.865907 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
785 11:35:08.869549 fsp= 1, odt_onoff= 1, Byte mode= 0
786 11:35:08.869624 ==
787 11:35:08.872579 === u2Vref_new: 0x56 --> 0x2d
788 11:35:08.876356 === u2Vref_new: 0x58 --> 0x38
789 11:35:08.879224 === u2Vref_new: 0x5a --> 0x39
790 11:35:08.882898 === u2Vref_new: 0x5c --> 0x3c
791 11:35:08.885720 === u2Vref_new: 0x5e --> 0x3d
792 11:35:08.888906 === u2Vref_new: 0x60 --> 0xa0
793 11:35:08.892560 [CA 0] Center 35 (8~63) winsize 56
794 11:35:08.896023 [CA 1] Center 35 (7~63) winsize 57
795 11:35:08.899211 [CA 2] Center 31 (2~60) winsize 59
796 11:35:08.902087 [CA 3] Center 25 (-2~53) winsize 56
797 11:35:08.907097 [CA 4] Center 25 (-2~53) winsize 56
798 11:35:08.908943 [CA 5] Center 32 (3~61) winsize 59
799 11:35:08.909020
800 11:35:08.912342 [CATrainingPosCal] consider 2 rank data
801 11:35:08.915753 u2DelayCellTimex100 = 744/100 ps
802 11:35:08.918990 CA0 delay=35 (8~63),Diff = 10 PI (13 cell)
803 11:35:08.922471 CA1 delay=35 (8~63),Diff = 10 PI (13 cell)
804 11:35:08.925596 CA2 delay=30 (2~59),Diff = 5 PI (6 cell)
805 11:35:08.928752 CA3 delay=25 (-2~53),Diff = 0 PI (0 cell)
806 11:35:08.931898 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
807 11:35:08.938641 CA5 delay=31 (3~60),Diff = 6 PI (7 cell)
808 11:35:08.938720
809 11:35:08.941840 CA PerBit enable=1, Macro0, CA PI delay=25
810 11:35:08.945050 === u2Vref_new: 0x5e --> 0x3d
811 11:35:08.945125
812 11:35:08.945183 Vref(ca) range 1: 30
813 11:35:08.945246
814 11:35:08.948997 CS Dly= 7 (38-0-32)
815 11:35:08.949072 Write Rank1 MR13 =0xd8
816 11:35:08.951957 Write Rank1 MR13 =0xd8
817 11:35:08.954948 Write Rank1 MR12 =0x5e
818 11:35:08.958429 [RankSwap] Rank num 2, (Multi 1), Rank 0
819 11:35:08.958503 Write Rank0 MR2 =0xad
820 11:35:08.962146 [Write Leveling]
821 11:35:08.964971 delay byte0 byte1 byte2 byte3
822 11:35:08.965053
823 11:35:08.965112 10 0 0
824 11:35:08.968175 11 0 0
825 11:35:08.968251 12 0 0
826 11:35:08.971452 13 0 0
827 11:35:08.971544 14 0 0
828 11:35:08.971605 15 0 0
829 11:35:08.974497 16 0 0
830 11:35:08.974573 17 0 0
831 11:35:08.978376 18 0 0
832 11:35:08.978453 19 0 0
833 11:35:08.978512 20 0 0
834 11:35:08.981358 21 0 ff
835 11:35:08.981489 22 0 0
836 11:35:08.984886 23 0 ff
837 11:35:08.984962 24 0 ff
838 11:35:08.987722 25 0 ff
839 11:35:08.987799 26 0 ff
840 11:35:08.990944 27 0 ff
841 11:35:08.991052 28 0 ff
842 11:35:08.991135 29 0 ff
843 11:35:08.994338 30 0 ff
844 11:35:08.994414 31 0 ff
845 11:35:08.997907 32 ff ff
846 11:35:08.998018 33 ff ff
847 11:35:09.000930 34 ff ff
848 11:35:09.001006 35 ff ff
849 11:35:09.004519 36 ff ff
850 11:35:09.004595 37 ff ff
851 11:35:09.007247 38 ff ff
852 11:35:09.010756 pass bytecount = 0xff (0xff: all bytes pass)
853 11:35:09.010831
854 11:35:09.010889 DQS0 dly: 32
855 11:35:09.014154 DQS1 dly: 23
856 11:35:09.014230 Write Rank0 MR2 =0x2d
857 11:35:09.017990 [RankSwap] Rank num 2, (Multi 1), Rank 0
858 11:35:09.020954 Write Rank0 MR1 =0xd6
859 11:35:09.021030 [Gating]
860 11:35:09.021089 ==
861 11:35:09.027951 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
862 11:35:09.030559 fsp= 1, odt_onoff= 1, Byte mode= 0
863 11:35:09.030638 ==
864 11:35:09.033753 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
865 11:35:09.040295 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
866 11:35:09.043494 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
867 11:35:09.046947 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
868 11:35:09.053227 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
869 11:35:09.056487 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
870 11:35:09.060218 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
871 11:35:09.066433 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
872 11:35:09.069716 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
873 11:35:09.073481 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
874 11:35:09.076579 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
875 11:35:09.083414 3 2 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
876 11:35:09.086749 3 2 16 |2828 2c2c |(11 11)(11 10) |(1 1)(0 0)| 0
877 11:35:09.090035 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
878 11:35:09.096268 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
879 11:35:09.099541 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
880 11:35:09.103020 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
881 11:35:09.109892 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
882 11:35:09.113107 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
883 11:35:09.116093 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
884 11:35:09.122958 3 3 16 |706 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
885 11:35:09.126425 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
886 11:35:09.129391 [Byte 0] Lead/lag Transition tap number (1)
887 11:35:09.135719 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
888 11:35:09.138935 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
889 11:35:09.142603 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
890 11:35:09.146159 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
891 11:35:09.152817 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
892 11:35:09.156052 3 4 12 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
893 11:35:09.159072 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
894 11:35:09.165852 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
895 11:35:09.168763 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
896 11:35:09.172683 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
897 11:35:09.178789 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
898 11:35:09.182216 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
899 11:35:09.185702 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
900 11:35:09.192010 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
901 11:35:09.195257 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
902 11:35:09.198482 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
903 11:35:09.205347 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
904 11:35:09.208390 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
905 11:35:09.211979 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
906 11:35:09.218294 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
907 11:35:09.221538 [Byte 0] Lead/lag falling Transition (3, 6, 4)
908 11:35:09.225262 [Byte 1] Lead/lag falling Transition (3, 6, 4)
909 11:35:09.228215 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
910 11:35:09.234803 [Byte 0] Lead/lag Transition tap number (2)
911 11:35:09.238105 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
912 11:35:09.241419 [Byte 1] Lead/lag Transition tap number (3)
913 11:35:09.244921 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
914 11:35:09.247968 [Byte 0]First pass (3, 6, 16)
915 11:35:09.251135 3 6 20 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
916 11:35:09.257842 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
917 11:35:09.257949 [Byte 1]First pass (3, 6, 24)
918 11:35:09.264199 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
919 11:35:09.267406 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
920 11:35:09.270803 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
921 11:35:09.273909 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
922 11:35:09.280675 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
923 11:35:09.283901 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
924 11:35:09.288038 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
925 11:35:09.290504 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
926 11:35:09.294386 All bytes gating window > 1UI, Early break!
927 11:35:09.294487
928 11:35:09.300352 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 8)
929 11:35:09.300454
930 11:35:09.303760 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
931 11:35:09.303860
932 11:35:09.303950
933 11:35:09.304035
934 11:35:09.307168 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
935 11:35:09.307270
936 11:35:09.310650 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
937 11:35:09.310750
938 11:35:09.310838
939 11:35:09.313746 Write Rank0 MR1 =0x56
940 11:35:09.313843
941 11:35:09.316624 best RODT dly(2T, 0.5T) = (2, 3)
942 11:35:09.316721
943 11:35:09.320293 best RODT dly(2T, 0.5T) = (2, 3)
944 11:35:09.320393 ==
945 11:35:09.323519 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
946 11:35:09.327015 fsp= 1, odt_onoff= 1, Byte mode= 0
947 11:35:09.327117 ==
948 11:35:09.333719 Start DQ dly to find pass range UseTestEngine =0
949 11:35:09.336834 x-axis: bit #, y-axis: DQ dly (-127~63)
950 11:35:09.336937 RX Vref Scan = 0
951 11:35:09.340397 -26, [0] xxxxxxxx xxxxxxxx [MSB]
952 11:35:09.343337 -25, [0] xxxxxxxx xxxxxxxx [MSB]
953 11:35:09.347067 -24, [0] xxxxxxxx xxxxxxxx [MSB]
954 11:35:09.350112 -23, [0] xxxxxxxx xxxxxxxx [MSB]
955 11:35:09.353366 -22, [0] xxxxxxxx xxxxxxxx [MSB]
956 11:35:09.356551 -21, [0] xxxxxxxx xxxxxxxx [MSB]
957 11:35:09.356657 -20, [0] xxxxxxxx xxxxxxxx [MSB]
958 11:35:09.359547 -19, [0] xxxxxxxx xxxxxxxx [MSB]
959 11:35:09.362825 -18, [0] xxxxxxxx xxxxxxxx [MSB]
960 11:35:09.366185 -17, [0] xxxxxxxx xxxxxxxx [MSB]
961 11:35:09.369749 -16, [0] xxxxxxxx xxxxxxxx [MSB]
962 11:35:09.372637 -15, [0] xxxxxxxx xxxxxxxx [MSB]
963 11:35:09.376373 -14, [0] xxxxxxxx xxxxxxxx [MSB]
964 11:35:09.379353 -13, [0] xxxxxxxx xxxxxxxx [MSB]
965 11:35:09.383319 -12, [0] xxxxxxxx xxxxxxxx [MSB]
966 11:35:09.386366 -11, [0] xxxxxxxx xxxxxxxx [MSB]
967 11:35:09.386443 -10, [0] xxxxxxxx xxxxxxxx [MSB]
968 11:35:09.389806 -9, [0] xxxxxxxx xxxxxxxx [MSB]
969 11:35:09.393082 -8, [0] xxxxxxxx xxxxxxxx [MSB]
970 11:35:09.395810 -7, [0] xxxxxxxx xxxxxxxx [MSB]
971 11:35:09.399019 -6, [0] xxxxxxxx xxxxxxxx [MSB]
972 11:35:09.402479 -5, [0] xxxxxxxx xxxxxxxx [MSB]
973 11:35:09.406449 -4, [0] xxxxxxxx xxxxxxxx [MSB]
974 11:35:09.406559 -3, [0] xxxoxxxx xxxxxxxx [MSB]
975 11:35:09.409519 -2, [0] xxxoxxxx oxxxxxxx [MSB]
976 11:35:09.412402 -1, [0] xxxoxxxx oxxoxxxx [MSB]
977 11:35:09.415943 0, [0] xxxoxxxx ooxoxxxx [MSB]
978 11:35:09.419092 1, [0] xxxoxoox ooxooxxx [MSB]
979 11:35:09.422205 2, [0] xxxoxoox ooxoooxx [MSB]
980 11:35:09.425671 3, [0] xxxoxoox ooxoooox [MSB]
981 11:35:09.425768 4, [0] xoxoxooo ooxoooox [MSB]
982 11:35:09.428889 5, [0] xoxoxooo ooxooooo [MSB]
983 11:35:09.432086 6, [0] xooooooo ooxooooo [MSB]
984 11:35:09.435458 7, [0] oooooooo ooxooooo [MSB]
985 11:35:09.438988 33, [0] oooxoooo oooooooo [MSB]
986 11:35:09.442279 34, [0] oooxoxoo oooooooo [MSB]
987 11:35:09.445567 35, [0] oooxoxoo xooooooo [MSB]
988 11:35:09.445694 36, [0] oooxoxoo xxoxxooo [MSB]
989 11:35:09.448512 37, [0] oooxoxxo xxoxxxxo [MSB]
990 11:35:09.452254 38, [0] oooxoxxx xxoxxxxo [MSB]
991 11:35:09.455353 39, [0] xooxoxxx xxoxxxxo [MSB]
992 11:35:09.458381 40, [0] xxoxoxxx xxoxxxxo [MSB]
993 11:35:09.462147 41, [0] xxxxxxxx xxoxxxxx [MSB]
994 11:35:09.466093 42, [0] xxxxxxxx xxoxxxxx [MSB]
995 11:35:09.466244 43, [0] xxxxxxxx xxxxxxxx [MSB]
996 11:35:09.468523 iDelay=43, Bit 0, Center 22 (7 ~ 38) 32
997 11:35:09.475399 iDelay=43, Bit 1, Center 21 (4 ~ 39) 36
998 11:35:09.478596 iDelay=43, Bit 2, Center 23 (6 ~ 40) 35
999 11:35:09.481930 iDelay=43, Bit 3, Center 14 (-3 ~ 32) 36
1000 11:35:09.485234 iDelay=43, Bit 4, Center 23 (6 ~ 40) 35
1001 11:35:09.488561 iDelay=43, Bit 5, Center 17 (1 ~ 33) 33
1002 11:35:09.491682 iDelay=43, Bit 6, Center 18 (1 ~ 36) 36
1003 11:35:09.494843 iDelay=43, Bit 7, Center 20 (4 ~ 37) 34
1004 11:35:09.498064 iDelay=43, Bit 8, Center 16 (-2 ~ 34) 37
1005 11:35:09.501251 iDelay=43, Bit 9, Center 17 (0 ~ 35) 36
1006 11:35:09.504963 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1007 11:35:09.508088 iDelay=43, Bit 11, Center 17 (-1 ~ 35) 37
1008 11:35:09.514816 iDelay=43, Bit 12, Center 18 (1 ~ 35) 35
1009 11:35:09.518189 iDelay=43, Bit 13, Center 19 (2 ~ 36) 35
1010 11:35:09.520999 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
1011 11:35:09.524247 iDelay=43, Bit 15, Center 22 (5 ~ 40) 36
1012 11:35:09.524354 ==
1013 11:35:09.528238 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1014 11:35:09.531150 fsp= 1, odt_onoff= 1, Byte mode= 0
1015 11:35:09.531258 ==
1016 11:35:09.534503 DQS Delay:
1017 11:35:09.534606 DQS0 = 0, DQS1 = 0
1018 11:35:09.538179 DQM Delay:
1019 11:35:09.538279 DQM0 = 19, DQM1 = 19
1020 11:35:09.538367 DQ Delay:
1021 11:35:09.541059 DQ0 =22, DQ1 =21, DQ2 =23, DQ3 =14
1022 11:35:09.544425 DQ4 =23, DQ5 =17, DQ6 =18, DQ7 =20
1023 11:35:09.547727 DQ8 =16, DQ9 =17, DQ10 =25, DQ11 =17
1024 11:35:09.551440 DQ12 =18, DQ13 =19, DQ14 =19, DQ15 =22
1025 11:35:09.551546
1026 11:35:09.551636
1027 11:35:09.553973 DramC Write-DBI off
1028 11:35:09.554100 ==
1029 11:35:09.560741 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1030 11:35:09.563924 fsp= 1, odt_onoff= 1, Byte mode= 0
1031 11:35:09.564030 ==
1032 11:35:09.567374 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1033 11:35:09.567476
1034 11:35:09.570985 Begin, DQ Scan Range 919~1175
1035 11:35:09.571093
1036 11:35:09.571184
1037 11:35:09.571269 TX Vref Scan disable
1038 11:35:09.577120 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1039 11:35:09.580212 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1040 11:35:09.583989 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1041 11:35:09.587299 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1042 11:35:09.590231 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1043 11:35:09.593537 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1044 11:35:09.596770 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1045 11:35:09.600428 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1046 11:35:09.603744 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1047 11:35:09.606970 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1048 11:35:09.610295 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1049 11:35:09.613419 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1050 11:35:09.617132 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1051 11:35:09.620309 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1052 11:35:09.627002 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1053 11:35:09.629973 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1054 11:35:09.633435 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1055 11:35:09.636537 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1056 11:35:09.639597 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1057 11:35:09.643452 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1058 11:35:09.646446 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1059 11:35:09.649816 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1060 11:35:09.652949 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1061 11:35:09.656334 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1062 11:35:09.659780 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1063 11:35:09.663199 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1064 11:35:09.665933 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1065 11:35:09.672606 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1066 11:35:09.675997 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1067 11:35:09.679205 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1068 11:35:09.682758 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1069 11:35:09.685631 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1070 11:35:09.689352 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1071 11:35:09.692606 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1072 11:35:09.696147 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1073 11:35:09.699816 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1074 11:35:09.702248 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1075 11:35:09.705888 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1076 11:35:09.708999 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1077 11:35:09.712618 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1078 11:35:09.715432 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1079 11:35:09.719391 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1080 11:35:09.725497 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1081 11:35:09.729038 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1082 11:35:09.731865 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1083 11:35:09.735844 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1084 11:35:09.738907 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1085 11:35:09.741935 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1086 11:35:09.745289 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1087 11:35:09.749245 968 |3 6 8|[0] xxxxxxxx oxxxxxxx [MSB]
1088 11:35:09.751798 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB]
1089 11:35:09.755339 970 |3 6 10|[0] xxxxxxxx oxxooxxx [MSB]
1090 11:35:09.758553 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1091 11:35:09.761904 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1092 11:35:09.765025 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1093 11:35:09.768250 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1094 11:35:09.771689 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1095 11:35:09.775137 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1096 11:35:09.778089 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1097 11:35:09.784567 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1098 11:35:09.787766 979 |3 6 19|[0] xxxoooox oooooooo [MSB]
1099 11:35:09.791323 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1100 11:35:09.794508 981 |3 6 21|[0] xooooooo oooooooo [MSB]
1101 11:35:09.797870 987 |3 6 27|[0] oooooooo xooooooo [MSB]
1102 11:35:09.800900 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1103 11:35:09.804680 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1104 11:35:09.807789 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1105 11:35:09.811005 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1106 11:35:09.814058 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1107 11:35:09.820754 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1108 11:35:09.823911 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1109 11:35:09.827658 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1110 11:35:09.830889 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1111 11:35:09.834046 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1112 11:35:09.837219 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1113 11:35:09.840455 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1114 11:35:09.843550 Byte0, DQ PI dly=988, DQM PI dly= 988
1115 11:35:09.847351 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1116 11:35:09.847427
1117 11:35:09.853870 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1118 11:35:09.853948
1119 11:35:09.856983 Byte1, DQ PI dly=979, DQM PI dly= 979
1120 11:35:09.860025 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1121 11:35:09.860101
1122 11:35:09.863646 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1123 11:35:09.866816
1124 11:35:09.866891 ==
1125 11:35:09.870608 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1126 11:35:09.873401 fsp= 1, odt_onoff= 1, Byte mode= 0
1127 11:35:09.873477 ==
1128 11:35:09.876730 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1129 11:35:09.876807
1130 11:35:09.880372 Begin, DQ Scan Range 955~1019
1131 11:35:09.883364 Write Rank0 MR14 =0x0
1132 11:35:09.891575
1133 11:35:09.891649 CH=0, VrefRange= 0, VrefLevel = 0
1134 11:35:09.898440 TX Bit0 (984~998) 15 991, Bit8 (972~981) 10 976,
1135 11:35:09.901308 TX Bit1 (983~995) 13 989, Bit9 (974~983) 10 978,
1136 11:35:09.908274 TX Bit2 (983~996) 14 989, Bit10 (977~989) 13 983,
1137 11:35:09.911524 TX Bit3 (977~991) 15 984, Bit11 (972~982) 11 977,
1138 11:35:09.914816 TX Bit4 (983~993) 11 988, Bit12 (973~983) 11 978,
1139 11:35:09.921166 TX Bit5 (980~991) 12 985, Bit13 (974~983) 10 978,
1140 11:35:09.924743 TX Bit6 (982~992) 11 987, Bit14 (973~987) 15 980,
1141 11:35:09.927959 TX Bit7 (983~993) 11 988, Bit15 (975~990) 16 982,
1142 11:35:09.931134
1143 11:35:09.931209 Write Rank0 MR14 =0x2
1144 11:35:09.940197
1145 11:35:09.940279 CH=0, VrefRange= 0, VrefLevel = 2
1146 11:35:09.946934 TX Bit0 (984~998) 15 991, Bit8 (972~982) 11 977,
1147 11:35:09.950045 TX Bit1 (982~996) 15 989, Bit9 (973~984) 12 978,
1148 11:35:09.956797 TX Bit2 (983~996) 14 989, Bit10 (976~989) 14 982,
1149 11:35:09.960176 TX Bit3 (977~991) 15 984, Bit11 (972~982) 11 977,
1150 11:35:09.963866 TX Bit4 (983~993) 11 988, Bit12 (973~984) 12 978,
1151 11:35:09.969794 TX Bit5 (979~991) 13 985, Bit13 (973~983) 11 978,
1152 11:35:09.973289 TX Bit6 (980~993) 14 986, Bit14 (973~988) 16 980,
1153 11:35:09.980142 TX Bit7 (983~993) 11 988, Bit15 (975~990) 16 982,
1154 11:35:09.980218
1155 11:35:09.980276 Write Rank0 MR14 =0x4
1156 11:35:09.989520
1157 11:35:09.989594 CH=0, VrefRange= 0, VrefLevel = 4
1158 11:35:09.995615 TX Bit0 (984~998) 15 991, Bit8 (971~983) 13 977,
1159 11:35:09.998952 TX Bit1 (982~997) 16 989, Bit9 (973~984) 12 978,
1160 11:35:10.006124 TX Bit2 (983~998) 16 990, Bit10 (976~990) 15 983,
1161 11:35:10.008581 TX Bit3 (977~991) 15 984, Bit11 (972~983) 12 977,
1162 11:35:10.012111 TX Bit4 (982~994) 13 988, Bit12 (973~985) 13 979,
1163 11:35:10.018432 TX Bit5 (979~992) 14 985, Bit13 (973~984) 12 978,
1164 11:35:10.022265 TX Bit6 (980~994) 15 987, Bit14 (973~988) 16 980,
1165 11:35:10.072961 TX Bit7 (982~994) 13 988, Bit15 (975~991) 17 983,
1166 11:35:10.073082
1167 11:35:10.073595 Write Rank0 MR14 =0x6
1168 11:35:10.073669
1169 11:35:10.073727 CH=0, VrefRange= 0, VrefLevel = 6
1170 11:35:10.074002 TX Bit0 (983~999) 17 991, Bit8 (970~983) 14 976,
1171 11:35:10.074088 TX Bit1 (982~998) 17 990, Bit9 (972~985) 14 978,
1172 11:35:10.074141 TX Bit2 (983~998) 16 990, Bit10 (975~990) 16 982,
1173 11:35:10.074193 TX Bit3 (976~992) 17 984, Bit11 (972~983) 12 977,
1174 11:35:10.074774 TX Bit4 (982~995) 14 988, Bit12 (973~986) 14 979,
1175 11:35:10.075027 TX Bit5 (979~993) 15 986, Bit13 (973~984) 12 978,
1176 11:35:10.075311 TX Bit6 (980~995) 16 987, Bit14 (973~989) 17 981,
1177 11:35:10.099218 TX Bit7 (981~995) 15 988, Bit15 (975~991) 17 983,
1178 11:35:10.099318
1179 11:35:10.099376 Write Rank0 MR14 =0x8
1180 11:35:10.099431
1181 11:35:10.099670 CH=0, VrefRange= 0, VrefLevel = 8
1182 11:35:10.099727 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977,
1183 11:35:10.099779 TX Bit1 (981~998) 18 989, Bit9 (972~986) 15 979,
1184 11:35:10.102847 TX Bit2 (982~999) 18 990, Bit10 (975~991) 17 983,
1185 11:35:10.105953 TX Bit3 (976~992) 17 984, Bit11 (971~984) 14 977,
1186 11:35:10.112850 TX Bit4 (981~996) 16 988, Bit12 (972~987) 16 979,
1187 11:35:10.116253 TX Bit5 (978~993) 16 985, Bit13 (973~985) 13 979,
1188 11:35:10.119120 TX Bit6 (979~996) 18 987, Bit14 (973~989) 17 981,
1189 11:35:10.126145 TX Bit7 (981~997) 17 989, Bit15 (975~992) 18 983,
1190 11:35:10.126223
1191 11:35:10.126281 Write Rank0 MR14 =0xa
1192 11:35:10.135820
1193 11:35:10.138966 CH=0, VrefRange= 0, VrefLevel = 10
1194 11:35:10.142480 TX Bit0 (983~999) 17 991, Bit8 (969~984) 16 976,
1195 11:35:10.145397 TX Bit1 (981~999) 19 990, Bit9 (971~987) 17 979,
1196 11:35:10.152033 TX Bit2 (982~999) 18 990, Bit10 (975~991) 17 983,
1197 11:35:10.155438 TX Bit3 (976~993) 18 984, Bit11 (970~984) 15 977,
1198 11:35:10.158588 TX Bit4 (981~997) 17 989, Bit12 (972~988) 17 980,
1199 11:35:10.165033 TX Bit5 (978~994) 17 986, Bit13 (972~986) 15 979,
1200 11:35:10.168767 TX Bit6 (979~996) 18 987, Bit14 (972~989) 18 980,
1201 11:35:10.175400 TX Bit7 (981~997) 17 989, Bit15 (974~991) 18 982,
1202 11:35:10.175479
1203 11:35:10.175536 Write Rank0 MR14 =0xc
1204 11:35:10.184845
1205 11:35:10.188158 CH=0, VrefRange= 0, VrefLevel = 12
1206 11:35:10.191096 TX Bit0 (983~1000) 18 991, Bit8 (969~985) 17 977,
1207 11:35:10.194350 TX Bit1 (981~999) 19 990, Bit9 (971~988) 18 979,
1208 11:35:10.201243 TX Bit2 (982~1000) 19 991, Bit10 (975~992) 18 983,
1209 11:35:10.204355 TX Bit3 (976~993) 18 984, Bit11 (970~985) 16 977,
1210 11:35:10.207760 TX Bit4 (980~998) 19 989, Bit12 (972~988) 17 980,
1211 11:35:10.214364 TX Bit5 (978~995) 18 986, Bit13 (972~987) 16 979,
1212 11:35:10.217401 TX Bit6 (978~997) 20 987, Bit14 (972~990) 19 981,
1213 11:35:10.223862 TX Bit7 (980~998) 19 989, Bit15 (974~993) 20 983,
1214 11:35:10.223937
1215 11:35:10.223995 Write Rank0 MR14 =0xe
1216 11:35:10.233990
1217 11:35:10.237356 CH=0, VrefRange= 0, VrefLevel = 14
1218 11:35:10.240696 TX Bit0 (982~1000) 19 991, Bit8 (968~986) 19 977,
1219 11:35:10.243872 TX Bit1 (981~999) 19 990, Bit9 (971~988) 18 979,
1220 11:35:10.250295 TX Bit2 (982~1000) 19 991, Bit10 (975~993) 19 984,
1221 11:35:10.254331 TX Bit3 (975~993) 19 984, Bit11 (969~986) 18 977,
1222 11:35:10.257522 TX Bit4 (980~998) 19 989, Bit12 (971~989) 19 980,
1223 11:35:10.263423 TX Bit5 (977~996) 20 986, Bit13 (972~988) 17 980,
1224 11:35:10.267215 TX Bit6 (978~998) 21 988, Bit14 (972~990) 19 981,
1225 11:35:10.273499 TX Bit7 (980~998) 19 989, Bit15 (974~993) 20 983,
1226 11:35:10.273574
1227 11:35:10.273632 Write Rank0 MR14 =0x10
1228 11:35:10.283402
1229 11:35:10.286727 CH=0, VrefRange= 0, VrefLevel = 16
1230 11:35:10.290472 TX Bit0 (982~1001) 20 991, Bit8 (968~987) 20 977,
1231 11:35:10.293099 TX Bit1 (980~1000) 21 990, Bit9 (970~989) 20 979,
1232 11:35:10.299953 TX Bit2 (981~1000) 20 990, Bit10 (974~994) 21 984,
1233 11:35:10.303484 TX Bit3 (975~994) 20 984, Bit11 (969~987) 19 978,
1234 11:35:10.309702 TX Bit4 (979~998) 20 988, Bit12 (971~989) 19 980,
1235 11:35:10.313246 TX Bit5 (977~996) 20 986, Bit13 (971~989) 19 980,
1236 11:35:10.316240 TX Bit6 (977~998) 22 987, Bit14 (971~991) 21 981,
1237 11:35:10.323398 TX Bit7 (979~998) 20 988, Bit15 (974~993) 20 983,
1238 11:35:10.323473
1239 11:35:10.323530 Write Rank0 MR14 =0x12
1240 11:35:10.333006
1241 11:35:10.336363 CH=0, VrefRange= 0, VrefLevel = 18
1242 11:35:10.340193 TX Bit0 (982~1001) 20 991, Bit8 (968~987) 20 977,
1243 11:35:10.343157 TX Bit1 (980~1000) 21 990, Bit9 (970~989) 20 979,
1244 11:35:10.349560 TX Bit2 (981~1001) 21 991, Bit10 (974~994) 21 984,
1245 11:35:10.353027 TX Bit3 (975~995) 21 985, Bit11 (969~988) 20 978,
1246 11:35:10.356224 TX Bit4 (979~999) 21 989, Bit12 (970~990) 21 980,
1247 11:35:10.362631 TX Bit5 (977~997) 21 987, Bit13 (970~989) 20 979,
1248 11:35:10.366181 TX Bit6 (977~998) 22 987, Bit14 (970~991) 22 980,
1249 11:35:10.372332 TX Bit7 (979~999) 21 989, Bit15 (973~994) 22 983,
1250 11:35:10.372407
1251 11:35:10.372464 Write Rank0 MR14 =0x14
1252 11:35:10.382739
1253 11:35:10.386605 CH=0, VrefRange= 0, VrefLevel = 20
1254 11:35:10.389895 TX Bit0 (981~1001) 21 991, Bit8 (967~988) 22 977,
1255 11:35:10.392646 TX Bit1 (979~1000) 22 989, Bit9 (970~989) 20 979,
1256 11:35:10.399454 TX Bit2 (980~1001) 22 990, Bit10 (974~995) 22 984,
1257 11:35:10.402999 TX Bit3 (975~995) 21 985, Bit11 (968~988) 21 978,
1258 11:35:10.405992 TX Bit4 (979~999) 21 989, Bit12 (970~990) 21 980,
1259 11:35:10.412308 TX Bit5 (977~997) 21 987, Bit13 (970~990) 21 980,
1260 11:35:10.416100 TX Bit6 (977~999) 23 988, Bit14 (970~991) 22 980,
1261 11:35:10.422736 TX Bit7 (979~999) 21 989, Bit15 (973~995) 23 984,
1262 11:35:10.422811
1263 11:35:10.422869 Write Rank0 MR14 =0x16
1264 11:35:10.432655
1265 11:35:10.435870 CH=0, VrefRange= 0, VrefLevel = 22
1266 11:35:10.438993 TX Bit0 (981~1002) 22 991, Bit8 (967~988) 22 977,
1267 11:35:10.442590 TX Bit1 (979~1001) 23 990, Bit9 (969~990) 22 979,
1268 11:35:10.449256 TX Bit2 (980~1002) 23 991, Bit10 (974~995) 22 984,
1269 11:35:10.452350 TX Bit3 (975~996) 22 985, Bit11 (968~989) 22 978,
1270 11:35:10.455654 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1271 11:35:10.462444 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
1272 11:35:10.465886 TX Bit6 (977~999) 23 988, Bit14 (970~992) 23 981,
1273 11:35:10.472110 TX Bit7 (978~1000) 23 989, Bit15 (973~995) 23 984,
1274 11:35:10.472190
1275 11:35:10.472248 Write Rank0 MR14 =0x18
1276 11:35:10.482816
1277 11:35:10.486460 CH=0, VrefRange= 0, VrefLevel = 24
1278 11:35:10.489577 TX Bit0 (980~1003) 24 991, Bit8 (967~989) 23 978,
1279 11:35:10.492277 TX Bit1 (978~1002) 25 990, Bit9 (969~990) 22 979,
1280 11:35:10.499274 TX Bit2 (979~1002) 24 990, Bit10 (973~996) 24 984,
1281 11:35:10.502468 TX Bit3 (974~997) 24 985, Bit11 (967~989) 23 978,
1282 11:35:10.508795 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1283 11:35:10.511970 TX Bit5 (976~998) 23 987, Bit13 (969~990) 22 979,
1284 11:35:10.515760 TX Bit6 (977~999) 23 988, Bit14 (970~992) 23 981,
1285 11:35:10.521934 TX Bit7 (978~1000) 23 989, Bit15 (972~995) 24 983,
1286 11:35:10.522065
1287 11:35:10.522125 Write Rank0 MR14 =0x1a
1288 11:35:10.533070
1289 11:35:10.536222 CH=0, VrefRange= 0, VrefLevel = 26
1290 11:35:10.539396 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
1291 11:35:10.542497 TX Bit1 (978~1002) 25 990, Bit9 (968~990) 23 979,
1292 11:35:10.549406 TX Bit2 (979~1003) 25 991, Bit10 (973~997) 25 985,
1293 11:35:10.552634 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
1294 11:35:10.559090 TX Bit4 (978~1000) 23 989, Bit12 (969~991) 23 980,
1295 11:35:10.562436 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
1296 11:35:10.565811 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
1297 11:35:10.572364 TX Bit7 (978~1000) 23 989, Bit15 (973~996) 24 984,
1298 11:35:10.572440
1299 11:35:10.575665 wait MRW command Rank0 MR14 =0x1c fired (1)
1300 11:35:10.578725 Write Rank0 MR14 =0x1c
1301 11:35:10.587200
1302 11:35:10.590416 CH=0, VrefRange= 0, VrefLevel = 28
1303 11:35:10.593965 TX Bit0 (980~1004) 25 992, Bit8 (966~990) 25 978,
1304 11:35:10.596918 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1305 11:35:10.603738 TX Bit2 (978~1004) 27 991, Bit10 (973~997) 25 985,
1306 11:35:10.607431 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1307 11:35:10.613507 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1308 11:35:10.616936 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
1309 11:35:10.620026 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1310 11:35:10.626270 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
1311 11:35:10.626371
1312 11:35:10.626456 Write Rank0 MR14 =0x1e
1313 11:35:10.637627
1314 11:35:10.640618 CH=0, VrefRange= 0, VrefLevel = 30
1315 11:35:10.643962 TX Bit0 (980~1004) 25 992, Bit8 (966~990) 25 978,
1316 11:35:10.647090 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1317 11:35:10.654317 TX Bit2 (978~1004) 27 991, Bit10 (973~997) 25 985,
1318 11:35:10.657514 TX Bit3 (974~997) 24 985, Bit11 (967~990) 24 978,
1319 11:35:10.660353 TX Bit4 (977~1001) 25 989, Bit12 (968~991) 24 979,
1320 11:35:10.667433 TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980,
1321 11:35:10.670344 TX Bit6 (976~1000) 25 988, Bit14 (968~993) 26 980,
1322 11:35:10.677013 TX Bit7 (977~1001) 25 989, Bit15 (973~996) 24 984,
1323 11:35:10.677087
1324 11:35:10.677145 Write Rank0 MR14 =0x20
1325 11:35:10.687671
1326 11:35:10.691110 CH=0, VrefRange= 0, VrefLevel = 32
1327 11:35:10.694397 TX Bit0 (979~1003) 25 991, Bit8 (966~989) 24 977,
1328 11:35:10.697654 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1329 11:35:10.703985 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
1330 11:35:10.707570 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
1331 11:35:10.710891 TX Bit4 (977~1002) 26 989, Bit12 (968~991) 24 979,
1332 11:35:10.717161 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1333 11:35:10.720671 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1334 11:35:10.727195 TX Bit7 (978~1002) 25 990, Bit15 (972~995) 24 983,
1335 11:35:10.727271
1336 11:35:10.727332 Write Rank0 MR14 =0x22
1337 11:35:10.738140
1338 11:35:10.741003 CH=0, VrefRange= 0, VrefLevel = 34
1339 11:35:10.744554 TX Bit0 (979~1003) 25 991, Bit8 (966~989) 24 977,
1340 11:35:10.747592 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1341 11:35:10.754473 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
1342 11:35:10.757778 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
1343 11:35:10.761411 TX Bit4 (977~1002) 26 989, Bit12 (968~991) 24 979,
1344 11:35:10.767673 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1345 11:35:10.771112 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1346 11:35:10.777256 TX Bit7 (978~1002) 25 990, Bit15 (972~995) 24 983,
1347 11:35:10.777331
1348 11:35:10.777388 Write Rank0 MR14 =0x24
1349 11:35:10.787860
1350 11:35:10.791115 CH=0, VrefRange= 0, VrefLevel = 36
1351 11:35:10.794895 TX Bit0 (979~1003) 25 991, Bit8 (966~989) 24 977,
1352 11:35:10.797709 TX Bit1 (978~1002) 25 990, Bit9 (967~990) 24 978,
1353 11:35:10.804649 TX Bit2 (980~1003) 24 991, Bit10 (973~996) 24 984,
1354 11:35:10.807741 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
1355 11:35:10.810853 TX Bit4 (977~1002) 26 989, Bit12 (968~991) 24 979,
1356 11:35:10.817938 TX Bit5 (976~999) 24 987, Bit13 (968~991) 24 979,
1357 11:35:10.820804 TX Bit6 (976~1000) 25 988, Bit14 (969~993) 25 981,
1358 11:35:10.827263 TX Bit7 (978~1002) 25 990, Bit15 (972~995) 24 983,
1359 11:35:10.827340
1360 11:35:10.827398
1361 11:35:10.830514 TX Vref found, early break! 368< 372
1362 11:35:10.834222 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1363 11:35:10.837928 u1DelayCellOfst[0]=6 cells (5 PI)
1364 11:35:10.840689 u1DelayCellOfst[1]=5 cells (4 PI)
1365 11:35:10.843974 u1DelayCellOfst[2]=6 cells (5 PI)
1366 11:35:10.847135 u1DelayCellOfst[3]=0 cells (0 PI)
1367 11:35:10.850856 u1DelayCellOfst[4]=3 cells (3 PI)
1368 11:35:10.853839 u1DelayCellOfst[5]=1 cells (1 PI)
1369 11:35:10.857296 u1DelayCellOfst[6]=2 cells (2 PI)
1370 11:35:10.860437 u1DelayCellOfst[7]=5 cells (4 PI)
1371 11:35:10.863757 Byte0, DQ PI dly=986, DQM PI dly= 988
1372 11:35:10.866815 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1373 11:35:10.866890
1374 11:35:10.870435 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1375 11:35:10.870511
1376 11:35:10.873385 u1DelayCellOfst[8]=0 cells (0 PI)
1377 11:35:10.877063 u1DelayCellOfst[9]=1 cells (1 PI)
1378 11:35:10.880317 u1DelayCellOfst[10]=9 cells (7 PI)
1379 11:35:10.883548 u1DelayCellOfst[11]=1 cells (1 PI)
1380 11:35:10.886937 u1DelayCellOfst[12]=2 cells (2 PI)
1381 11:35:10.890002 u1DelayCellOfst[13]=2 cells (2 PI)
1382 11:35:10.893823 u1DelayCellOfst[14]=5 cells (4 PI)
1383 11:35:10.896836 u1DelayCellOfst[15]=7 cells (6 PI)
1384 11:35:10.899793 Byte1, DQ PI dly=977, DQM PI dly= 980
1385 11:35:10.903150 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1386 11:35:10.903225
1387 11:35:10.906255 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1388 11:35:10.909923
1389 11:35:10.913589 wait MRW command Rank0 MR14 =0x20 fired (1)
1390 11:35:10.913664 Write Rank0 MR14 =0x20
1391 11:35:10.913721
1392 11:35:10.916811 Final TX Range 0 Vref 32
1393 11:35:10.916885
1394 11:35:10.922730 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1395 11:35:10.922806
1396 11:35:10.929341 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1397 11:35:10.936232 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1398 11:35:10.942818 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1399 11:35:10.945781 Write Rank0 MR3 =0xb0
1400 11:35:10.949320 DramC Write-DBI on
1401 11:35:10.949395 ==
1402 11:35:10.952407 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1403 11:35:10.955603 fsp= 1, odt_onoff= 1, Byte mode= 0
1404 11:35:10.955679 ==
1405 11:35:10.962700 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1406 11:35:10.962775
1407 11:35:10.962833 Begin, DQ Scan Range 700~764
1408 11:35:10.962887
1409 11:35:10.962937
1410 11:35:10.965310 TX Vref Scan disable
1411 11:35:10.969340 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1412 11:35:10.972200 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1413 11:35:10.975101 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1414 11:35:10.978582 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1415 11:35:10.981610 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1416 11:35:10.984761 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1417 11:35:10.991615 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1418 11:35:10.994988 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1419 11:35:10.998151 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1420 11:35:11.001248 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1421 11:35:11.004987 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1422 11:35:11.007721 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1423 11:35:11.011218 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1424 11:35:11.014709 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1425 11:35:11.018229 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1426 11:35:11.021286 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1427 11:35:11.024638 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1428 11:35:11.027448 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1429 11:35:11.030842 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1430 11:35:11.034024 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1431 11:35:11.037574 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1432 11:35:11.046356 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1433 11:35:11.049291 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1434 11:35:11.052990 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1435 11:35:11.056136 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1436 11:35:11.059285 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1437 11:35:11.062654 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1438 11:35:11.065817 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1439 11:35:11.069747 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1440 11:35:11.072792 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1441 11:35:11.075731 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1442 11:35:11.079100 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1443 11:35:11.082936 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1444 11:35:11.085989 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
1445 11:35:11.089038 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
1446 11:35:11.095779 Byte0, DQ PI dly=734, DQM PI dly= 734
1447 11:35:11.099268 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
1448 11:35:11.099369
1449 11:35:11.102321 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
1450 11:35:11.102414
1451 11:35:11.105775 Byte1, DQ PI dly=723, DQM PI dly= 723
1452 11:35:11.112093 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
1453 11:35:11.112194
1454 11:35:11.115535 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
1455 11:35:11.115610
1456 11:35:11.122029 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1457 11:35:11.128810 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1458 11:35:11.135289 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1459 11:35:11.138189 Write Rank0 MR3 =0x30
1460 11:35:11.138283 DramC Write-DBI off
1461 11:35:11.138368
1462 11:35:11.141661 [DATLAT]
1463 11:35:11.144683 Freq=1600, CH0 RK0, use_rxtx_scan=0
1464 11:35:11.144773
1465 11:35:11.144859 DATLAT Default: 0xf
1466 11:35:11.148300 7, 0xFFFF, sum=0
1467 11:35:11.148395 8, 0xFFFF, sum=0
1468 11:35:11.151810 9, 0xFFFF, sum=0
1469 11:35:11.151902 10, 0xFFFF, sum=0
1470 11:35:11.154702 11, 0xFFFF, sum=0
1471 11:35:11.154779 12, 0xFFFF, sum=0
1472 11:35:11.158481 13, 0xFFFF, sum=0
1473 11:35:11.158584 14, 0x0, sum=1
1474 11:35:11.161212 15, 0x0, sum=2
1475 11:35:11.161306 16, 0x0, sum=3
1476 11:35:11.161395 17, 0x0, sum=4
1477 11:35:11.167919 pattern=2 first_step=14 total pass=5 best_step=16
1478 11:35:11.167995 ==
1479 11:35:11.171369 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1480 11:35:11.174642 fsp= 1, odt_onoff= 1, Byte mode= 0
1481 11:35:11.174716 ==
1482 11:35:11.181310 Start DQ dly to find pass range UseTestEngine =1
1483 11:35:11.184585 x-axis: bit #, y-axis: DQ dly (-127~63)
1484 11:35:11.184660 RX Vref Scan = 1
1485 11:35:11.292184
1486 11:35:11.292312 RX Vref found, early break!
1487 11:35:11.292373
1488 11:35:11.298724 Final RX Vref 11, apply to both rank0 and 1
1489 11:35:11.298800 ==
1490 11:35:11.302449 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1491 11:35:11.305603 fsp= 1, odt_onoff= 1, Byte mode= 0
1492 11:35:11.305702 ==
1493 11:35:11.305853 DQS Delay:
1494 11:35:11.308778 DQS0 = 0, DQS1 = 0
1495 11:35:11.308855 DQM Delay:
1496 11:35:11.312293 DQM0 = 19, DQM1 = 18
1497 11:35:11.312371 DQ Delay:
1498 11:35:11.315412 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15
1499 11:35:11.318941 DQ4 =21, DQ5 =16, DQ6 =19, DQ7 =21
1500 11:35:11.321902 DQ8 =15, DQ9 =17, DQ10 =24, DQ11 =16
1501 11:35:11.325667 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1502 11:35:11.325742
1503 11:35:11.325801
1504 11:35:11.325855
1505 11:35:11.329256 [DramC_TX_OE_Calibration] TA2
1506 11:35:11.331973 Original DQ_B0 (3 6) =30, OEN = 27
1507 11:35:11.335089 Original DQ_B1 (3 6) =30, OEN = 27
1508 11:35:11.338339 23, 0x0, End_B0=23 End_B1=23
1509 11:35:11.338419 24, 0x0, End_B0=24 End_B1=24
1510 11:35:11.342171 25, 0x0, End_B0=25 End_B1=25
1511 11:35:11.345498 26, 0x0, End_B0=26 End_B1=26
1512 11:35:11.348313 27, 0x0, End_B0=27 End_B1=27
1513 11:35:11.352119 28, 0x0, End_B0=28 End_B1=28
1514 11:35:11.352198 29, 0x0, End_B0=29 End_B1=29
1515 11:35:11.355043 30, 0x0, End_B0=30 End_B1=30
1516 11:35:11.358609 31, 0xFFFF, End_B0=30 End_B1=30
1517 11:35:11.364584 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1518 11:35:11.368535 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1519 11:35:11.368614
1520 11:35:11.371664
1521 11:35:11.371742 Write Rank0 MR23 =0x3f
1522 11:35:11.371819 [DQSOSC]
1523 11:35:11.381139 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
1524 11:35:11.388203 CH0_RK0: MR19=0x202, MR18=0xADAD, DQSOSC=459, MR23=63, INC=11, DEC=17
1525 11:35:11.388282 Write Rank0 MR23 =0x3f
1526 11:35:11.391671 [DQSOSC]
1527 11:35:11.397759 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
1528 11:35:11.401023 CH0 RK0: MR19=202, MR18=AEAE
1529 11:35:11.404167 [RankSwap] Rank num 2, (Multi 1), Rank 1
1530 11:35:11.407399 Write Rank0 MR2 =0xad
1531 11:35:11.407476 [Write Leveling]
1532 11:35:11.410896 delay byte0 byte1 byte2 byte3
1533 11:35:11.410973
1534 11:35:11.411049 10 0 0
1535 11:35:11.414130 11 0 0
1536 11:35:11.414209 12 0 0
1537 11:35:11.417574 13 0 0
1538 11:35:11.417653 14 0 0
1539 11:35:11.421079 15 0 0
1540 11:35:11.421157 16 0 0
1541 11:35:11.421235 17 0 0
1542 11:35:11.424037 18 0 0
1543 11:35:11.424115 19 0 0
1544 11:35:11.427481 20 0 0
1545 11:35:11.427559 21 0 0
1546 11:35:11.427636 22 0 0
1547 11:35:11.430402 23 0 ff
1548 11:35:11.430480 24 0 ff
1549 11:35:11.434094 25 0 ff
1550 11:35:11.434171 26 0 ff
1551 11:35:11.437245 27 0 ff
1552 11:35:11.437321 28 0 ff
1553 11:35:11.440598 29 0 ff
1554 11:35:11.440674 30 0 ff
1555 11:35:11.440733 31 0 ff
1556 11:35:11.444120 32 ff ff
1557 11:35:11.444195 33 ff ff
1558 11:35:11.447199 34 ff ff
1559 11:35:11.447274 35 ff ff
1560 11:35:11.451162 36 ff ff
1561 11:35:11.451237 37 ff ff
1562 11:35:11.453904 38 ff ff
1563 11:35:11.456757 pass bytecount = 0xff (0xff: all bytes pass)
1564 11:35:11.456832
1565 11:35:11.456891 DQS0 dly: 32
1566 11:35:11.460404 DQS1 dly: 23
1567 11:35:11.460478 Write Rank0 MR2 =0x2d
1568 11:35:11.463410 [RankSwap] Rank num 2, (Multi 1), Rank 0
1569 11:35:11.467459 Write Rank1 MR1 =0xd6
1570 11:35:11.467534 [Gating]
1571 11:35:11.467592 ==
1572 11:35:11.473489 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1573 11:35:11.476856 fsp= 1, odt_onoff= 1, Byte mode= 0
1574 11:35:11.476933 ==
1575 11:35:11.480014 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1576 11:35:11.486725 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1577 11:35:11.490171 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1578 11:35:11.493348 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1579 11:35:11.500070 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1580 11:35:11.503401 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1581 11:35:11.506130 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1582 11:35:11.513176 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1583 11:35:11.516164 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1584 11:35:11.519653 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1585 11:35:11.526282 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1586 11:35:11.529155 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
1587 11:35:11.532810 3 2 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1588 11:35:11.539211 3 2 20 |3d3d 404 |(11 11)(11 11) |(1 1)(0 0)| 0
1589 11:35:11.542789 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1590 11:35:11.546208 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1591 11:35:11.548949 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1592 11:35:11.555604 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1593 11:35:11.559001 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1594 11:35:11.562881 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1595 11:35:11.569006 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1596 11:35:11.572099 3 3 20 |1e1e 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1597 11:35:11.575493 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1598 11:35:11.582212 [Byte 0] Lead/lag Transition tap number (1)
1599 11:35:11.585528 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1600 11:35:11.589262 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1601 11:35:11.595512 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1602 11:35:11.598436 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1603 11:35:11.602013 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1604 11:35:11.605125 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1605 11:35:11.611635 3 4 16 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1606 11:35:11.615348 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1607 11:35:11.618650 3 4 24 |3d3d 2d2d |(11 11)(11 11) |(1 1)(1 1)| 0
1608 11:35:11.624629 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1609 11:35:11.628410 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1610 11:35:11.631498 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1611 11:35:11.637778 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1612 11:35:11.641335 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1613 11:35:11.644993 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 11:35:11.651716 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 11:35:11.654730 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1616 11:35:11.657891 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 11:35:11.664414 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 11:35:11.667586 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 11:35:11.670796 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1620 11:35:11.677942 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1621 11:35:11.680612 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1622 11:35:11.684468 [Byte 0] Lead/lag Transition tap number (3)
1623 11:35:11.687225 [Byte 1] Lead/lag falling Transition (3, 6, 12)
1624 11:35:11.694286 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1625 11:35:11.697457 [Byte 1] Lead/lag Transition tap number (2)
1626 11:35:11.700588 3 6 20 |404 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1627 11:35:11.703914 3 6 24 |4646 808 |(0 0)(11 11) |(0 0)(0 0)| 0
1628 11:35:11.707206 [Byte 0]First pass (3, 6, 24)
1629 11:35:11.710597 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1630 11:35:11.713858 [Byte 1]First pass (3, 6, 28)
1631 11:35:11.720771 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1632 11:35:11.723502 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1633 11:35:11.727014 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1634 11:35:11.730993 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1635 11:35:11.733598 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1636 11:35:11.740208 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1637 11:35:11.743248 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1638 11:35:11.746692 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1639 11:35:11.750199 All bytes gating window > 1UI, Early break!
1640 11:35:11.750276
1641 11:35:11.753515 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
1642 11:35:11.756377
1643 11:35:11.759644 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 16)
1644 11:35:11.759721
1645 11:35:11.759797
1646 11:35:11.759868
1647 11:35:11.763306 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
1648 11:35:11.763383
1649 11:35:11.766545 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1650 11:35:11.766644
1651 11:35:11.766720
1652 11:35:11.769313 Write Rank1 MR1 =0x56
1653 11:35:11.769389
1654 11:35:11.772872 best RODT dly(2T, 0.5T) = (2, 3)
1655 11:35:11.772949
1656 11:35:11.776477 best RODT dly(2T, 0.5T) = (2, 3)
1657 11:35:11.776566 ==
1658 11:35:11.779500 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1659 11:35:11.782843 fsp= 1, odt_onoff= 1, Byte mode= 0
1660 11:35:11.782919 ==
1661 11:35:11.789532 Start DQ dly to find pass range UseTestEngine =0
1662 11:35:11.792736 x-axis: bit #, y-axis: DQ dly (-127~63)
1663 11:35:11.792812 RX Vref Scan = 0
1664 11:35:11.795639 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1665 11:35:11.799334 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1666 11:35:11.802371 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1667 11:35:11.805451 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1668 11:35:11.808773 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1669 11:35:11.811984 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1670 11:35:11.815888 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1671 11:35:11.815965 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1672 11:35:11.818602 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1673 11:35:11.821780 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1674 11:35:11.825457 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1675 11:35:11.828980 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1676 11:35:11.831668 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1677 11:35:11.835333 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1678 11:35:11.838552 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1679 11:35:11.841927 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1680 11:35:11.842052 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1681 11:35:11.845210 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1682 11:35:11.848456 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1683 11:35:11.851680 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1684 11:35:11.854893 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1685 11:35:11.858283 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1686 11:35:11.861366 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1687 11:35:11.864517 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1688 11:35:11.864594 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1689 11:35:11.868342 -1, [0] xxxoxxxx xxxxxxxx [MSB]
1690 11:35:11.870993 0, [0] xxxoxxxx xxxxxxxx [MSB]
1691 11:35:11.874776 1, [0] xxxoxoox oxxoxxxx [MSB]
1692 11:35:11.877703 2, [0] xxxoxoox oxxoxxxx [MSB]
1693 11:35:11.881125 3, [0] xxxooooo ooxoxxxx [MSB]
1694 11:35:11.881202 4, [0] ooxooooo ooxoooxx [MSB]
1695 11:35:11.884300 5, [0] ooxooooo ooxoooox [MSB]
1696 11:35:11.887724 6, [0] oooooooo ooxoooox [MSB]
1697 11:35:11.890719 7, [0] oooooooo ooxooooo [MSB]
1698 11:35:11.894577 8, [0] oooooooo ooxooooo [MSB]
1699 11:35:11.898110 9, [0] oooooooo ooxooooo [MSB]
1700 11:35:11.900842 32, [0] oooxoooo oooooooo [MSB]
1701 11:35:11.900918 33, [0] oooxoooo oooooooo [MSB]
1702 11:35:11.904154 34, [0] oooxoxoo oooooooo [MSB]
1703 11:35:11.907453 35, [0] oooxoxoo xooxoooo [MSB]
1704 11:35:11.910627 36, [0] oooxoxoo xxoxxooo [MSB]
1705 11:35:11.913978 37, [0] oooxoxxx xxoxxxxo [MSB]
1706 11:35:11.917608 38, [0] xooxoxxx xxoxxxxo [MSB]
1707 11:35:11.920688 39, [0] xxoxoxxx xxoxxxxo [MSB]
1708 11:35:11.920780 40, [0] xxxxoxxx xxoxxxxo [MSB]
1709 11:35:11.924506 41, [0] xxxxxxxx xxoxxxxx [MSB]
1710 11:35:11.927640 42, [0] xxxxxxxx xxoxxxxx [MSB]
1711 11:35:11.930752 43, [0] xxxxxxxx xxxxxxxx [MSB]
1712 11:35:11.933783 iDelay=43, Bit 0, Center 20 (4 ~ 37) 34
1713 11:35:11.937519 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
1714 11:35:11.940289 iDelay=43, Bit 2, Center 22 (6 ~ 39) 34
1715 11:35:11.944047 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1716 11:35:11.947372 iDelay=43, Bit 4, Center 21 (3 ~ 40) 38
1717 11:35:11.950699 iDelay=43, Bit 5, Center 17 (1 ~ 33) 33
1718 11:35:11.953823 iDelay=43, Bit 6, Center 18 (1 ~ 36) 36
1719 11:35:11.960277 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34
1720 11:35:11.963518 iDelay=43, Bit 8, Center 17 (1 ~ 34) 34
1721 11:35:11.967041 iDelay=43, Bit 9, Center 19 (3 ~ 35) 33
1722 11:35:11.970134 iDelay=43, Bit 10, Center 26 (10 ~ 42) 33
1723 11:35:11.973624 iDelay=43, Bit 11, Center 17 (1 ~ 34) 34
1724 11:35:11.977131 iDelay=43, Bit 12, Center 19 (4 ~ 35) 32
1725 11:35:11.979909 iDelay=43, Bit 13, Center 20 (4 ~ 36) 33
1726 11:35:11.983666 iDelay=43, Bit 14, Center 20 (5 ~ 36) 32
1727 11:35:11.986764 iDelay=43, Bit 15, Center 23 (7 ~ 40) 34
1728 11:35:11.986841 ==
1729 11:35:11.993795 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1730 11:35:11.996431 fsp= 1, odt_onoff= 1, Byte mode= 0
1731 11:35:11.996509 ==
1732 11:35:11.996587 DQS Delay:
1733 11:35:12.000153 DQS0 = 0, DQS1 = 0
1734 11:35:12.000231 DQM Delay:
1735 11:35:12.003566 DQM0 = 19, DQM1 = 20
1736 11:35:12.003644 DQ Delay:
1737 11:35:12.006677 DQ0 =20, DQ1 =21, DQ2 =22, DQ3 =14
1738 11:35:12.010382 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
1739 11:35:12.013230 DQ8 =17, DQ9 =19, DQ10 =26, DQ11 =17
1740 11:35:12.016252 DQ12 =19, DQ13 =20, DQ14 =20, DQ15 =23
1741 11:35:12.016329
1742 11:35:12.016405
1743 11:35:12.020108 DramC Write-DBI off
1744 11:35:12.020184 ==
1745 11:35:12.022942 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1746 11:35:12.026868 fsp= 1, odt_onoff= 1, Byte mode= 0
1747 11:35:12.026946 ==
1748 11:35:12.029930 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1749 11:35:12.030013
1750 11:35:12.032793 Begin, DQ Scan Range 919~1175
1751 11:35:12.032870
1752 11:35:12.032944
1753 11:35:12.036649 TX Vref Scan disable
1754 11:35:12.039578 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1755 11:35:12.042658 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1756 11:35:12.046365 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1757 11:35:12.049414 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1758 11:35:12.052956 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1759 11:35:12.056229 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1760 11:35:12.062426 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1761 11:35:12.065657 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1762 11:35:12.068966 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1763 11:35:12.072132 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1764 11:35:12.076072 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1765 11:35:12.079294 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1766 11:35:12.082304 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1767 11:35:12.085419 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1768 11:35:12.088920 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1769 11:35:12.092142 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1770 11:35:12.095919 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1771 11:35:12.099241 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1772 11:35:12.102052 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1773 11:35:12.108339 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1774 11:35:12.111829 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1775 11:35:12.115744 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1776 11:35:12.118600 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1777 11:35:12.121674 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1778 11:35:12.125050 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1779 11:35:12.128624 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1780 11:35:12.131532 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1781 11:35:12.135003 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1782 11:35:12.138037 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1783 11:35:12.141766 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1784 11:35:12.145037 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1785 11:35:12.148202 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1786 11:35:12.151988 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1787 11:35:12.158146 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1788 11:35:12.161610 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1789 11:35:12.164963 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1790 11:35:12.168282 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1791 11:35:12.171279 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1792 11:35:12.174285 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1793 11:35:12.178203 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1794 11:35:12.181134 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1795 11:35:12.184236 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1796 11:35:12.187434 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1797 11:35:12.191477 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1798 11:35:12.194028 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1799 11:35:12.197912 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1800 11:35:12.200889 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1801 11:35:12.203949 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1802 11:35:12.207210 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1803 11:35:12.210721 968 |3 6 8|[0] xxxxxxxx oxxxxxxx [MSB]
1804 11:35:12.217068 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB]
1805 11:35:12.220747 970 |3 6 10|[0] xxxxxxxx oxxoooxx [MSB]
1806 11:35:12.223942 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1807 11:35:12.227164 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1808 11:35:12.230303 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1809 11:35:12.233980 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1810 11:35:12.236949 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1811 11:35:12.240100 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1812 11:35:12.243377 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1813 11:35:12.247194 978 |3 6 18|[0] xxxoxoox oooooooo [MSB]
1814 11:35:12.250262 979 |3 6 19|[0] xxxooooo oooooooo [MSB]
1815 11:35:12.253989 980 |3 6 20|[0] xoxooooo oooooooo [MSB]
1816 11:35:12.256874 981 |3 6 21|[0] xoxooooo oooooooo [MSB]
1817 11:35:12.264141 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1818 11:35:12.267148 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1819 11:35:12.270739 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1820 11:35:12.274041 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1821 11:35:12.277594 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1822 11:35:12.280625 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1823 11:35:12.284227 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
1824 11:35:12.287142 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1825 11:35:12.290759 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1826 11:35:12.293605 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
1827 11:35:12.297169 999 |3 6 39|[0] oooxoxoo xxxxxxxx [MSB]
1828 11:35:12.300458 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1829 11:35:12.303890 Byte0, DQ PI dly=988, DQM PI dly= 988
1830 11:35:12.310018 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
1831 11:35:12.310130
1832 11:35:12.313568 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
1833 11:35:12.313642
1834 11:35:12.317009 Byte1, DQ PI dly=980, DQM PI dly= 980
1835 11:35:12.322974 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1836 11:35:12.323050
1837 11:35:12.326782 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1838 11:35:12.326857
1839 11:35:12.326915 ==
1840 11:35:12.333059 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1841 11:35:12.333134 fsp= 1, odt_onoff= 1, Byte mode= 0
1842 11:35:12.336439 ==
1843 11:35:12.339628 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1844 11:35:12.339702
1845 11:35:12.342705 Begin, DQ Scan Range 956~1020
1846 11:35:12.342779 Write Rank1 MR14 =0x0
1847 11:35:12.352611
1848 11:35:12.352685 CH=0, VrefRange= 0, VrefLevel = 0
1849 11:35:12.359720 TX Bit0 (984~997) 14 990, Bit8 (971~982) 12 976,
1850 11:35:12.362377 TX Bit1 (983~995) 13 989, Bit9 (973~983) 11 978,
1851 11:35:12.369112 TX Bit2 (984~997) 14 990, Bit10 (976~990) 15 983,
1852 11:35:12.372404 TX Bit3 (978~991) 14 984, Bit11 (972~982) 11 977,
1853 11:35:12.375760 TX Bit4 (983~995) 13 989, Bit12 (973~984) 12 978,
1854 11:35:12.383130 TX Bit5 (981~992) 12 986, Bit13 (973~985) 13 979,
1855 11:35:12.385442 TX Bit6 (980~993) 14 986, Bit14 (974~988) 15 981,
1856 11:35:12.392173 TX Bit7 (982~995) 14 988, Bit15 (976~988) 13 982,
1857 11:35:12.392249
1858 11:35:12.392307 Write Rank1 MR14 =0x2
1859 11:35:12.401126
1860 11:35:12.401201 CH=0, VrefRange= 0, VrefLevel = 2
1861 11:35:12.407677 TX Bit0 (984~998) 15 991, Bit8 (970~983) 14 976,
1862 11:35:12.411114 TX Bit1 (983~996) 14 989, Bit9 (973~984) 12 978,
1863 11:35:12.417750 TX Bit2 (984~998) 15 991, Bit10 (976~990) 15 983,
1864 11:35:12.421031 TX Bit3 (977~991) 15 984, Bit11 (972~983) 12 977,
1865 11:35:12.424287 TX Bit4 (983~996) 14 989, Bit12 (973~985) 13 979,
1866 11:35:12.430803 TX Bit5 (980~993) 14 986, Bit13 (973~986) 14 979,
1867 11:35:12.434165 TX Bit6 (981~994) 14 987, Bit14 (973~988) 16 980,
1868 11:35:12.437208 TX Bit7 (982~997) 16 989, Bit15 (976~989) 14 982,
1869 11:35:12.440391
1870 11:35:12.440467 Write Rank1 MR14 =0x4
1871 11:35:12.449540
1872 11:35:12.449615 CH=0, VrefRange= 0, VrefLevel = 4
1873 11:35:12.456396 TX Bit0 (984~998) 15 991, Bit8 (970~983) 14 976,
1874 11:35:12.459315 TX Bit1 (982~997) 16 989, Bit9 (973~985) 13 979,
1875 11:35:12.466450 TX Bit2 (984~998) 15 991, Bit10 (975~991) 17 983,
1876 11:35:12.469656 TX Bit3 (977~992) 16 984, Bit11 (972~983) 12 977,
1877 11:35:12.472891 TX Bit4 (983~997) 15 990, Bit12 (973~985) 13 979,
1878 11:35:12.479630 TX Bit5 (979~994) 16 986, Bit13 (973~987) 15 980,
1879 11:35:12.482932 TX Bit6 (980~995) 16 987, Bit14 (973~989) 17 981,
1880 11:35:12.486252 TX Bit7 (982~997) 16 989, Bit15 (975~990) 16 982,
1881 11:35:12.486328
1882 11:35:12.492916 wait MRW command Rank1 MR14 =0x6 fired (1)
1883 11:35:12.492993 Write Rank1 MR14 =0x6
1884 11:35:12.502339
1885 11:35:12.502415 CH=0, VrefRange= 0, VrefLevel = 6
1886 11:35:12.509317 TX Bit0 (984~999) 16 991, Bit8 (970~984) 15 977,
1887 11:35:12.512087 TX Bit1 (983~998) 16 990, Bit9 (973~985) 13 979,
1888 11:35:12.519280 TX Bit2 (984~999) 16 991, Bit10 (975~992) 18 983,
1889 11:35:12.522464 TX Bit3 (977~992) 16 984, Bit11 (971~984) 14 977,
1890 11:35:12.525613 TX Bit4 (982~998) 17 990, Bit12 (973~986) 14 979,
1891 11:35:12.531785 TX Bit5 (979~995) 17 987, Bit13 (972~988) 17 980,
1892 11:35:12.535491 TX Bit6 (979~996) 18 987, Bit14 (973~989) 17 981,
1893 11:35:12.538477 TX Bit7 (981~998) 18 989, Bit15 (975~990) 16 982,
1894 11:35:12.541635
1895 11:35:12.541708 Write Rank1 MR14 =0x8
1896 11:35:12.551212
1897 11:35:12.551286 CH=0, VrefRange= 0, VrefLevel = 8
1898 11:35:12.557712 TX Bit0 (984~999) 16 991, Bit8 (969~985) 17 977,
1899 11:35:12.560734 TX Bit1 (982~999) 18 990, Bit9 (972~986) 15 979,
1900 11:35:12.567382 TX Bit2 (984~999) 16 991, Bit10 (975~992) 18 983,
1901 11:35:12.571076 TX Bit3 (977~992) 16 984, Bit11 (971~984) 14 977,
1902 11:35:12.574024 TX Bit4 (981~998) 18 989, Bit12 (972~988) 17 980,
1903 11:35:12.580502 TX Bit5 (979~995) 17 987, Bit13 (972~989) 18 980,
1904 11:35:12.583742 TX Bit6 (979~996) 18 987, Bit14 (972~990) 19 981,
1905 11:35:12.590675 TX Bit7 (981~999) 19 990, Bit15 (975~990) 16 982,
1906 11:35:12.590751
1907 11:35:12.590811 Write Rank1 MR14 =0xa
1908 11:35:12.599986
1909 11:35:12.603413 CH=0, VrefRange= 0, VrefLevel = 10
1910 11:35:12.606467 TX Bit0 (983~1000) 18 991, Bit8 (969~985) 17 977,
1911 11:35:12.609991 TX Bit1 (981~999) 19 990, Bit9 (972~987) 16 979,
1912 11:35:12.616568 TX Bit2 (983~1000) 18 991, Bit10 (975~993) 19 984,
1913 11:35:12.619551 TX Bit3 (977~993) 17 985, Bit11 (970~985) 16 977,
1914 11:35:12.623164 TX Bit4 (981~999) 19 990, Bit12 (972~988) 17 980,
1915 11:35:12.629712 TX Bit5 (978~997) 20 987, Bit13 (972~989) 18 980,
1916 11:35:12.632770 TX Bit6 (978~997) 20 987, Bit14 (972~990) 19 981,
1917 11:35:12.639380 TX Bit7 (981~1000) 20 990, Bit15 (975~991) 17 983,
1918 11:35:12.639458
1919 11:35:12.639517 Write Rank1 MR14 =0xc
1920 11:35:12.649387
1921 11:35:12.652886 CH=0, VrefRange= 0, VrefLevel = 12
1922 11:35:12.655680 TX Bit0 (983~1000) 18 991, Bit8 (968~986) 19 977,
1923 11:35:12.659107 TX Bit1 (981~1000) 20 990, Bit9 (972~988) 17 980,
1924 11:35:12.665309 TX Bit2 (983~1000) 18 991, Bit10 (975~993) 19 984,
1925 11:35:12.669064 TX Bit3 (976~994) 19 985, Bit11 (970~986) 17 978,
1926 11:35:12.672131 TX Bit4 (981~999) 19 990, Bit12 (972~989) 18 980,
1927 11:35:12.678906 TX Bit5 (978~996) 19 987, Bit13 (972~989) 18 980,
1928 11:35:12.681871 TX Bit6 (978~999) 22 988, Bit14 (972~991) 20 981,
1929 11:35:12.688134 TX Bit7 (979~1000) 22 989, Bit15 (975~991) 17 983,
1930 11:35:12.688211
1931 11:35:12.688270 Write Rank1 MR14 =0xe
1932 11:35:12.698540
1933 11:35:12.701764 CH=0, VrefRange= 0, VrefLevel = 14
1934 11:35:12.705584 TX Bit0 (983~1001) 19 992, Bit8 (968~987) 20 977,
1935 11:35:12.708479 TX Bit1 (981~1000) 20 990, Bit9 (971~989) 19 980,
1936 11:35:12.715292 TX Bit2 (983~1001) 19 992, Bit10 (975~994) 20 984,
1937 11:35:12.718378 TX Bit3 (976~994) 19 985, Bit11 (969~987) 19 978,
1938 11:35:12.724879 TX Bit4 (980~1000) 21 990, Bit12 (971~989) 19 980,
1939 11:35:12.728010 TX Bit5 (978~998) 21 988, Bit13 (971~990) 20 980,
1940 11:35:12.731866 TX Bit6 (978~999) 22 988, Bit14 (972~991) 20 981,
1941 11:35:12.738121 TX Bit7 (979~1000) 22 989, Bit15 (974~992) 19 983,
1942 11:35:12.738198
1943 11:35:12.738258 Write Rank1 MR14 =0x10
1944 11:35:12.748141
1945 11:35:12.751837 CH=0, VrefRange= 0, VrefLevel = 16
1946 11:35:12.754979 TX Bit0 (983~1001) 19 992, Bit8 (968~988) 21 978,
1947 11:35:12.758503 TX Bit1 (981~1000) 20 990, Bit9 (971~989) 19 980,
1948 11:35:12.765086 TX Bit2 (982~1001) 20 991, Bit10 (974~995) 22 984,
1949 11:35:12.768322 TX Bit3 (976~995) 20 985, Bit11 (969~988) 20 978,
1950 11:35:12.771665 TX Bit4 (980~1000) 21 990, Bit12 (970~990) 21 980,
1951 11:35:12.778172 TX Bit5 (977~998) 22 987, Bit13 (971~990) 20 980,
1952 11:35:12.781772 TX Bit6 (977~999) 23 988, Bit14 (971~991) 21 981,
1953 11:35:12.788064 TX Bit7 (979~1001) 23 990, Bit15 (974~992) 19 983,
1954 11:35:12.788157
1955 11:35:12.788217 Write Rank1 MR14 =0x12
1956 11:35:12.798533
1957 11:35:12.801165 CH=0, VrefRange= 0, VrefLevel = 18
1958 11:35:12.805013 TX Bit0 (983~1001) 19 992, Bit8 (967~989) 23 978,
1959 11:35:12.808227 TX Bit1 (980~1001) 22 990, Bit9 (970~989) 20 979,
1960 11:35:12.814368 TX Bit2 (982~1001) 20 991, Bit10 (974~996) 23 985,
1961 11:35:12.817755 TX Bit3 (976~996) 21 986, Bit11 (968~988) 21 978,
1962 11:35:12.821545 TX Bit4 (979~1000) 22 989, Bit12 (970~990) 21 980,
1963 11:35:12.827740 TX Bit5 (977~998) 22 987, Bit13 (970~990) 21 980,
1964 11:35:12.831456 TX Bit6 (977~1000) 24 988, Bit14 (971~992) 22 981,
1965 11:35:12.837700 TX Bit7 (979~1001) 23 990, Bit15 (974~994) 21 984,
1966 11:35:12.837776
1967 11:35:12.837834 Write Rank1 MR14 =0x14
1968 11:35:12.848284
1969 11:35:12.851328 CH=0, VrefRange= 0, VrefLevel = 20
1970 11:35:12.854719 TX Bit0 (982~1002) 21 992, Bit8 (967~989) 23 978,
1971 11:35:12.858108 TX Bit1 (979~1001) 23 990, Bit9 (969~989) 21 979,
1972 11:35:12.864391 TX Bit2 (981~1002) 22 991, Bit10 (973~996) 24 984,
1973 11:35:12.867682 TX Bit3 (975~997) 23 986, Bit11 (968~989) 22 978,
1974 11:35:12.874599 TX Bit4 (979~1001) 23 990, Bit12 (970~990) 21 980,
1975 11:35:12.877698 TX Bit5 (977~999) 23 988, Bit13 (969~991) 23 980,
1976 11:35:12.880916 TX Bit6 (977~1000) 24 988, Bit14 (971~992) 22 981,
1977 11:35:12.887450 TX Bit7 (978~1001) 24 989, Bit15 (974~994) 21 984,
1978 11:35:12.887528
1979 11:35:12.887587 Write Rank1 MR14 =0x16
1980 11:35:12.898001
1981 11:35:12.901584 CH=0, VrefRange= 0, VrefLevel = 22
1982 11:35:12.904698 TX Bit0 (981~1003) 23 992, Bit8 (967~989) 23 978,
1983 11:35:12.908141 TX Bit1 (979~1002) 24 990, Bit9 (970~990) 21 980,
1984 11:35:12.914620 TX Bit2 (982~1002) 21 992, Bit10 (974~996) 23 985,
1985 11:35:12.918147 TX Bit3 (975~997) 23 986, Bit11 (967~989) 23 978,
1986 11:35:12.924331 TX Bit4 (978~1002) 25 990, Bit12 (969~991) 23 980,
1987 11:35:12.927874 TX Bit5 (977~999) 23 988, Bit13 (969~991) 23 980,
1988 11:35:12.931197 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
1989 11:35:12.937631 TX Bit7 (978~1002) 25 990, Bit15 (974~995) 22 984,
1990 11:35:12.937708
1991 11:35:12.937766 Write Rank1 MR14 =0x18
1992 11:35:12.947988
1993 11:35:12.951636 CH=0, VrefRange= 0, VrefLevel = 24
1994 11:35:12.954724 TX Bit0 (981~1003) 23 992, Bit8 (966~989) 24 977,
1995 11:35:12.958146 TX Bit1 (979~1002) 24 990, Bit9 (969~990) 22 979,
1996 11:35:12.964931 TX Bit2 (981~1003) 23 992, Bit10 (973~997) 25 985,
1997 11:35:12.967589 TX Bit3 (975~998) 24 986, Bit11 (967~990) 24 978,
1998 11:35:12.974491 TX Bit4 (979~1002) 24 990, Bit12 (969~991) 23 980,
1999 11:35:12.977613 TX Bit5 (977~999) 23 988, Bit13 (969~991) 23 980,
2000 11:35:12.981025 TX Bit6 (977~1001) 25 989, Bit14 (969~993) 25 981,
2001 11:35:12.987836 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
2002 11:35:12.987913
2003 11:35:12.987973 Write Rank1 MR14 =0x1a
2004 11:35:12.998400
2005 11:35:13.001959 CH=0, VrefRange= 0, VrefLevel = 26
2006 11:35:13.005153 TX Bit0 (980~1004) 25 992, Bit8 (967~989) 23 978,
2007 11:35:13.008162 TX Bit1 (979~1003) 25 991, Bit9 (969~990) 22 979,
2008 11:35:13.014832 TX Bit2 (980~1003) 24 991, Bit10 (973~997) 25 985,
2009 11:35:13.018679 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
2010 11:35:13.021753 TX Bit4 (978~1003) 26 990, Bit12 (969~992) 24 980,
2011 11:35:13.028356 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
2012 11:35:13.031543 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
2013 11:35:13.037992 TX Bit7 (977~1003) 27 990, Bit15 (973~996) 24 984,
2014 11:35:13.038091
2015 11:35:13.038173 Write Rank1 MR14 =0x1c
2016 11:35:13.048869
2017 11:35:13.052406 CH=0, VrefRange= 0, VrefLevel = 28
2018 11:35:13.055695 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
2019 11:35:13.059327 TX Bit1 (979~1004) 26 991, Bit9 (969~990) 22 979,
2020 11:35:13.065826 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
2021 11:35:13.068677 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
2022 11:35:13.075364 TX Bit4 (978~1003) 26 990, Bit12 (968~991) 24 979,
2023 11:35:13.078691 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
2024 11:35:13.082141 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2025 11:35:13.088411 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
2026 11:35:13.088499
2027 11:35:13.088559 Write Rank1 MR14 =0x1e
2028 11:35:13.099625
2029 11:35:13.102730 CH=0, VrefRange= 0, VrefLevel = 30
2030 11:35:13.105760 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
2031 11:35:13.109825 TX Bit1 (979~1004) 26 991, Bit9 (969~990) 22 979,
2032 11:35:13.115976 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
2033 11:35:13.119436 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
2034 11:35:13.122737 TX Bit4 (978~1003) 26 990, Bit12 (968~991) 24 979,
2035 11:35:13.129423 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
2036 11:35:13.132353 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2037 11:35:13.139147 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
2038 11:35:13.139224
2039 11:35:13.139284 Write Rank1 MR14 =0x20
2040 11:35:13.149743
2041 11:35:13.153993 CH=0, VrefRange= 0, VrefLevel = 32
2042 11:35:13.156864 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
2043 11:35:13.159963 TX Bit1 (979~1004) 26 991, Bit9 (969~990) 22 979,
2044 11:35:13.166385 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
2045 11:35:13.169648 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
2046 11:35:13.176160 TX Bit4 (978~1003) 26 990, Bit12 (968~991) 24 979,
2047 11:35:13.179205 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
2048 11:35:13.182811 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2049 11:35:13.189101 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
2050 11:35:13.189178
2051 11:35:13.189238 Write Rank1 MR14 =0x22
2052 11:35:13.200485
2053 11:35:13.203892 CH=0, VrefRange= 0, VrefLevel = 34
2054 11:35:13.206982 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
2055 11:35:13.210433 TX Bit1 (979~1004) 26 991, Bit9 (969~990) 22 979,
2056 11:35:13.216867 TX Bit2 (980~1004) 25 992, Bit10 (973~997) 25 985,
2057 11:35:13.220217 TX Bit3 (974~998) 25 986, Bit11 (967~990) 24 978,
2058 11:35:13.223483 TX Bit4 (978~1003) 26 990, Bit12 (968~991) 24 979,
2059 11:35:13.230208 TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979,
2060 11:35:13.233793 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2061 11:35:13.239631 TX Bit7 (978~1003) 26 990, Bit15 (973~996) 24 984,
2062 11:35:13.239708
2063 11:35:13.239766
2064 11:35:13.242944 TX Vref found, early break! 365< 373
2065 11:35:13.246496 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2066 11:35:13.249606 u1DelayCellOfst[0]=9 cells (7 PI)
2067 11:35:13.253323 u1DelayCellOfst[1]=6 cells (5 PI)
2068 11:35:13.256493 u1DelayCellOfst[2]=7 cells (6 PI)
2069 11:35:13.260068 u1DelayCellOfst[3]=0 cells (0 PI)
2070 11:35:13.262862 u1DelayCellOfst[4]=5 cells (4 PI)
2071 11:35:13.265997 u1DelayCellOfst[5]=2 cells (2 PI)
2072 11:35:13.270229 u1DelayCellOfst[6]=3 cells (3 PI)
2073 11:35:13.273020 u1DelayCellOfst[7]=5 cells (4 PI)
2074 11:35:13.276125 Byte0, DQ PI dly=986, DQM PI dly= 989
2075 11:35:13.279237 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2076 11:35:13.279386
2077 11:35:13.282899 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2078 11:35:13.283042
2079 11:35:13.286340 u1DelayCellOfst[8]=0 cells (0 PI)
2080 11:35:13.289272 u1DelayCellOfst[9]=2 cells (2 PI)
2081 11:35:13.292884 u1DelayCellOfst[10]=10 cells (8 PI)
2082 11:35:13.295802 u1DelayCellOfst[11]=1 cells (1 PI)
2083 11:35:13.299530 u1DelayCellOfst[12]=2 cells (2 PI)
2084 11:35:13.302531 u1DelayCellOfst[13]=2 cells (2 PI)
2085 11:35:13.305559 u1DelayCellOfst[14]=5 cells (4 PI)
2086 11:35:13.308756 u1DelayCellOfst[15]=9 cells (7 PI)
2087 11:35:13.312692 Byte1, DQ PI dly=977, DQM PI dly= 981
2088 11:35:13.315812 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2089 11:35:13.315888
2090 11:35:13.322493 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2091 11:35:13.322569
2092 11:35:13.322658 Write Rank1 MR14 =0x1c
2093 11:35:13.322755
2094 11:35:13.325354 Final TX Range 0 Vref 28
2095 11:35:13.325431
2096 11:35:13.332480 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2097 11:35:13.332557
2098 11:35:13.338454 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2099 11:35:13.345447 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2100 11:35:13.351915 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2101 11:35:13.354912 Write Rank1 MR3 =0xb0
2102 11:35:13.354989 DramC Write-DBI on
2103 11:35:13.355047 ==
2104 11:35:13.361693 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2105 11:35:13.365362 fsp= 1, odt_onoff= 1, Byte mode= 0
2106 11:35:13.365440 ==
2107 11:35:13.368469 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2108 11:35:13.368545
2109 11:35:13.372108 Begin, DQ Scan Range 701~765
2110 11:35:13.372183
2111 11:35:13.372242
2112 11:35:13.374888 TX Vref Scan disable
2113 11:35:13.378686 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2114 11:35:13.381882 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2115 11:35:13.384993 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2116 11:35:13.388196 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2117 11:35:13.391714 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2118 11:35:13.394851 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2119 11:35:13.398032 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2120 11:35:13.401343 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2121 11:35:13.404517 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2122 11:35:13.407918 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2123 11:35:13.411164 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2124 11:35:13.414458 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2125 11:35:13.417632 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2126 11:35:13.424262 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2127 11:35:13.427603 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2128 11:35:13.431035 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2129 11:35:13.434319 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2130 11:35:13.437826 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2131 11:35:13.441258 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2132 11:35:13.444240 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2133 11:35:13.447660 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2134 11:35:13.455783 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2135 11:35:13.458163 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2136 11:35:13.461484 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2137 11:35:13.464838 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2138 11:35:13.468459 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2139 11:35:13.471770 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2140 11:35:13.475333 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2141 11:35:13.477970 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2142 11:35:13.481213 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2143 11:35:13.484390 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2144 11:35:13.488180 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2145 11:35:13.491225 748 |2 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
2146 11:35:13.494830 Byte0, DQ PI dly=734, DQM PI dly= 734
2147 11:35:13.501412 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
2148 11:35:13.501489
2149 11:35:13.504395 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
2150 11:35:13.504471
2151 11:35:13.508407 Byte1, DQ PI dly=724, DQM PI dly= 724
2152 11:35:13.511203 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2153 11:35:13.511279
2154 11:35:13.517763 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2155 11:35:13.517839
2156 11:35:13.523978 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2157 11:35:13.530844 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2158 11:35:13.537475 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2159 11:35:13.540731 Write Rank1 MR3 =0x30
2160 11:35:13.540807 DramC Write-DBI off
2161 11:35:13.540865
2162 11:35:13.544515 [DATLAT]
2163 11:35:13.544590 Freq=1600, CH0 RK1, use_rxtx_scan=0
2164 11:35:13.544651
2165 11:35:13.547959 DATLAT Default: 0x10
2166 11:35:13.548038 7, 0xFFFF, sum=0
2167 11:35:13.551043 8, 0xFFFF, sum=0
2168 11:35:13.551121 9, 0xFFFF, sum=0
2169 11:35:13.554275 10, 0xFFFF, sum=0
2170 11:35:13.554352 11, 0xFFFF, sum=0
2171 11:35:13.557574 12, 0xFFFF, sum=0
2172 11:35:13.557650 13, 0xFFFF, sum=0
2173 11:35:13.560777 14, 0x0, sum=1
2174 11:35:13.560854 15, 0x0, sum=2
2175 11:35:13.564068 16, 0x0, sum=3
2176 11:35:13.564144 17, 0x0, sum=4
2177 11:35:13.567789 pattern=2 first_step=14 total pass=5 best_step=16
2178 11:35:13.570940 ==
2179 11:35:13.573819 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2180 11:35:13.577204 fsp= 1, odt_onoff= 1, Byte mode= 0
2181 11:35:13.577280 ==
2182 11:35:13.580973 Start DQ dly to find pass range UseTestEngine =1
2183 11:35:13.583898 x-axis: bit #, y-axis: DQ dly (-127~63)
2184 11:35:13.587047 RX Vref Scan = 0
2185 11:35:13.590271 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2186 11:35:13.593496 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2187 11:35:13.597200 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2188 11:35:13.597277 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2189 11:35:13.600398 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2190 11:35:13.603799 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2191 11:35:13.607062 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2192 11:35:13.610306 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2193 11:35:13.613600 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2194 11:35:13.616684 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2195 11:35:13.620252 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2196 11:35:13.623293 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2197 11:35:13.623371 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2198 11:35:13.626806 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2199 11:35:13.629824 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2200 11:35:13.633509 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2201 11:35:13.636489 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2202 11:35:13.639547 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2203 11:35:13.643212 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2204 11:35:13.646335 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2205 11:35:13.646412 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2206 11:35:13.649766 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2207 11:35:13.653196 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2208 11:35:13.656362 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2209 11:35:13.659463 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2210 11:35:13.662806 -1, [0] xxxoxxxx xxxxxxxx [MSB]
2211 11:35:13.665953 0, [0] xxxoxoxx oxxoxxxx [MSB]
2212 11:35:13.666068 1, [0] xxxoxoox oxxoxxxx [MSB]
2213 11:35:13.669305 2, [0] xxxoxoox ooxoxxxx [MSB]
2214 11:35:13.672683 3, [0] xoxoxoox ooxoooxx [MSB]
2215 11:35:13.676040 4, [0] ooooxooo ooxoooxx [MSB]
2216 11:35:13.679161 5, [0] oooooooo ooxoooox [MSB]
2217 11:35:13.682741 6, [0] oooooooo ooxooooo [MSB]
2218 11:35:13.685626 7, [0] oooooooo ooxooooo [MSB]
2219 11:35:13.685703 8, [0] oooooooo ooxooooo [MSB]
2220 11:35:13.690664 32, [0] oooxoooo oooooooo [MSB]
2221 11:35:13.694039 33, [0] oooxoxoo oooooooo [MSB]
2222 11:35:13.697049 34, [0] oooxoxoo oooxoooo [MSB]
2223 11:35:13.700524 35, [0] oooxoxoo xooxoooo [MSB]
2224 11:35:13.703794 36, [0] oooxoxxo xxoxoooo [MSB]
2225 11:35:13.706866 37, [0] oooxoxxo xxoxxxoo [MSB]
2226 11:35:13.710115 38, [0] oooxoxxx xxoxxxxo [MSB]
2227 11:35:13.710193 39, [0] xooxxxxx xxoxxxxo [MSB]
2228 11:35:13.713848 40, [0] xxoxxxxx xxoxxxxo [MSB]
2229 11:35:13.716960 41, [0] xxxxxxxx xxoxxxxx [MSB]
2230 11:35:13.720176 42, [0] xxxxxxxx xxoxxxxx [MSB]
2231 11:35:13.723331 43, [0] xxxxxxxx xxxxxxxx [MSB]
2232 11:35:13.726621 iDelay=43, Bit 0, Center 21 (4 ~ 38) 35
2233 11:35:13.730221 iDelay=43, Bit 1, Center 21 (3 ~ 39) 37
2234 11:35:13.733403 iDelay=43, Bit 2, Center 22 (4 ~ 40) 37
2235 11:35:13.736597 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
2236 11:35:13.739954 iDelay=43, Bit 4, Center 21 (5 ~ 38) 34
2237 11:35:13.743033 iDelay=43, Bit 5, Center 16 (0 ~ 32) 33
2238 11:35:13.746508 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
2239 11:35:13.752628 iDelay=43, Bit 7, Center 20 (4 ~ 37) 34
2240 11:35:13.756224 iDelay=43, Bit 8, Center 17 (0 ~ 34) 35
2241 11:35:13.759668 iDelay=43, Bit 9, Center 18 (2 ~ 35) 34
2242 11:35:13.762763 iDelay=43, Bit 10, Center 25 (9 ~ 42) 34
2243 11:35:13.765772 iDelay=43, Bit 11, Center 16 (0 ~ 33) 34
2244 11:35:13.769021 iDelay=43, Bit 12, Center 19 (3 ~ 36) 34
2245 11:35:13.772659 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34
2246 11:35:13.775599 iDelay=43, Bit 14, Center 21 (5 ~ 37) 33
2247 11:35:13.778866 iDelay=43, Bit 15, Center 23 (6 ~ 40) 35
2248 11:35:13.778941 ==
2249 11:35:13.785962 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2250 11:35:13.788804 fsp= 1, odt_onoff= 1, Byte mode= 0
2251 11:35:13.788880 ==
2252 11:35:13.788939 DQS Delay:
2253 11:35:13.791946 DQS0 = 0, DQS1 = 0
2254 11:35:13.792022 DQM Delay:
2255 11:35:13.795490 DQM0 = 19, DQM1 = 19
2256 11:35:13.795565 DQ Delay:
2257 11:35:13.798997 DQ0 =21, DQ1 =21, DQ2 =22, DQ3 =14
2258 11:35:13.802277 DQ4 =21, DQ5 =16, DQ6 =18, DQ7 =20
2259 11:35:13.805414 DQ8 =17, DQ9 =18, DQ10 =25, DQ11 =16
2260 11:35:13.808595 DQ12 =19, DQ13 =19, DQ14 =21, DQ15 =23
2261 11:35:13.808671
2262 11:35:13.808729
2263 11:35:13.808783
2264 11:35:13.811724 [DramC_TX_OE_Calibration] TA2
2265 11:35:13.815680 Original DQ_B0 (3 6) =30, OEN = 27
2266 11:35:13.818851 Original DQ_B1 (3 6) =30, OEN = 27
2267 11:35:13.821644 23, 0x0, End_B0=23 End_B1=23
2268 11:35:13.821721 24, 0x0, End_B0=24 End_B1=24
2269 11:35:13.825109 25, 0x0, End_B0=25 End_B1=25
2270 11:35:13.828447 26, 0x0, End_B0=26 End_B1=26
2271 11:35:13.831520 27, 0x0, End_B0=27 End_B1=27
2272 11:35:13.831596 28, 0x0, End_B0=28 End_B1=28
2273 11:35:13.834762 29, 0x0, End_B0=29 End_B1=29
2274 11:35:13.838648 30, 0x0, End_B0=30 End_B1=30
2275 11:35:13.841665 31, 0xFFFF, End_B0=30 End_B1=30
2276 11:35:13.848089 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2277 11:35:13.851426 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2278 11:35:13.851501
2279 11:35:13.851559
2280 11:35:13.855117 Write Rank1 MR23 =0x3f
2281 11:35:13.855193 [DQSOSC]
2282 11:35:13.864938 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0x202, tDQSOscB0 = 456 ps tDQSOscB1 = 456 ps
2283 11:35:13.871335 CH0_RK1: MR19=0x202, MR18=0xB2B2, DQSOSC=456, MR23=63, INC=11, DEC=17
2284 11:35:13.871411 Write Rank1 MR23 =0x3f
2285 11:35:13.871471 [DQSOSC]
2286 11:35:13.881183 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0x202, tDQSOscB0 = 455 ps tDQSOscB1 = 455 ps
2287 11:35:13.884334 CH0 RK1: MR19=202, MR18=B3B3
2288 11:35:13.887829 [RxdqsGatingPostProcess] freq 1600
2289 11:35:13.890690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2290 11:35:13.894534 Rank: 0
2291 11:35:13.894610 best DQS0 dly(2T, 0.5T) = (2, 6)
2292 11:35:13.897784 best DQS1 dly(2T, 0.5T) = (2, 6)
2293 11:35:13.901074 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2294 11:35:13.903964 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2295 11:35:13.907627 Rank: 1
2296 11:35:13.907746 best DQS0 dly(2T, 0.5T) = (2, 6)
2297 11:35:13.910837 best DQS1 dly(2T, 0.5T) = (2, 6)
2298 11:35:13.913948 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2299 11:35:13.917358 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2300 11:35:13.923577 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2301 11:35:13.927002 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2302 11:35:13.930352 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2303 11:35:13.933277 Write Rank0 MR13 =0x59
2304 11:35:13.933352 ==
2305 11:35:13.937141 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2306 11:35:13.940673 fsp= 1, odt_onoff= 1, Byte mode= 0
2307 11:35:13.943769 ==
2308 11:35:13.943845 === u2Vref_new: 0x56 --> 0x3a
2309 11:35:13.946619 === u2Vref_new: 0x58 --> 0x58
2310 11:35:13.949749 === u2Vref_new: 0x5a --> 0x5a
2311 11:35:13.953449 === u2Vref_new: 0x5c --> 0x78
2312 11:35:13.956635 === u2Vref_new: 0x5e --> 0x7a
2313 11:35:13.959978 === u2Vref_new: 0x60 --> 0x90
2314 11:35:13.963028 [CA 0] Center 37 (12~63) winsize 52
2315 11:35:13.966208 [CA 1] Center 36 (10~63) winsize 54
2316 11:35:13.970023 [CA 2] Center 35 (8~63) winsize 56
2317 11:35:13.973171 [CA 3] Center 34 (6~63) winsize 58
2318 11:35:13.976552 [CA 4] Center 34 (5~63) winsize 59
2319 11:35:13.979535 [CA 5] Center 28 (0~57) winsize 58
2320 11:35:13.979611
2321 11:35:13.983522 [CATrainingPosCal] consider 1 rank data
2322 11:35:13.986049 u2DelayCellTimex100 = 744/100 ps
2323 11:35:13.989482 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2324 11:35:13.992745 CA1 delay=36 (10~63),Diff = 8 PI (10 cell)
2325 11:35:13.996550 CA2 delay=35 (8~63),Diff = 7 PI (9 cell)
2326 11:35:13.999883 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2327 11:35:14.002899 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2328 11:35:14.009269 CA5 delay=28 (0~57),Diff = 0 PI (0 cell)
2329 11:35:14.009338
2330 11:35:14.012376 CA PerBit enable=1, Macro0, CA PI delay=28
2331 11:35:14.015848 === u2Vref_new: 0x5e --> 0x7a
2332 11:35:14.015926
2333 11:35:14.015985 Vref(ca) range 1: 30
2334 11:35:14.016041
2335 11:35:14.019066 CS Dly= 11 (42-0-32)
2336 11:35:14.019141 Write Rank0 MR13 =0xd8
2337 11:35:14.022521 Write Rank0 MR13 =0xd8
2338 11:35:14.026469 Write Rank0 MR12 =0x5e
2339 11:35:14.026545 Write Rank1 MR13 =0x59
2340 11:35:14.026603 ==
2341 11:35:14.032736 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2342 11:35:14.035781 fsp= 1, odt_onoff= 1, Byte mode= 0
2343 11:35:14.035857 ==
2344 11:35:14.039348 === u2Vref_new: 0x56 --> 0x3a
2345 11:35:14.042500 === u2Vref_new: 0x58 --> 0x58
2346 11:35:14.045680 === u2Vref_new: 0x5a --> 0x5a
2347 11:35:14.048882 === u2Vref_new: 0x5c --> 0x78
2348 11:35:14.052145 === u2Vref_new: 0x5e --> 0x7a
2349 11:35:14.052221 === u2Vref_new: 0x60 --> 0x90
2350 11:35:14.056228 [CA 0] Center 37 (11~63) winsize 53
2351 11:35:14.059056 [CA 1] Center 36 (10~63) winsize 54
2352 11:35:14.062550 [CA 2] Center 35 (7~63) winsize 57
2353 11:35:14.065653 [CA 3] Center 34 (6~63) winsize 58
2354 11:35:14.069112 [CA 4] Center 34 (5~63) winsize 59
2355 11:35:14.072475 [CA 5] Center 28 (0~56) winsize 57
2356 11:35:14.072550
2357 11:35:14.075655 [CATrainingPosCal] consider 2 rank data
2358 11:35:14.079151 u2DelayCellTimex100 = 744/100 ps
2359 11:35:14.082295 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2360 11:35:14.085677 CA1 delay=36 (10~63),Diff = 8 PI (10 cell)
2361 11:35:14.092766 CA2 delay=35 (8~63),Diff = 7 PI (9 cell)
2362 11:35:14.096538 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2363 11:35:14.098886 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2364 11:35:14.102697 CA5 delay=28 (0~56),Diff = 0 PI (0 cell)
2365 11:35:14.102770
2366 11:35:14.105782 CA PerBit enable=1, Macro0, CA PI delay=28
2367 11:35:14.108742 === u2Vref_new: 0x60 --> 0x90
2368 11:35:14.108817
2369 11:35:14.108875 Vref(ca) range 1: 32
2370 11:35:14.112082
2371 11:35:14.112155 CS Dly= 10 (41-0-32)
2372 11:35:14.115792 Write Rank1 MR13 =0xd8
2373 11:35:14.115898 Write Rank1 MR13 =0xd8
2374 11:35:14.119100 Write Rank1 MR12 =0x60
2375 11:35:14.122053 [RankSwap] Rank num 2, (Multi 1), Rank 0
2376 11:35:14.125074 Write Rank0 MR2 =0xad
2377 11:35:14.125173 [Write Leveling]
2378 11:35:14.128285 delay byte0 byte1 byte2 byte3
2379 11:35:14.128383
2380 11:35:14.132401 10 0 0
2381 11:35:14.132504 11 0 0
2382 11:35:14.132592 12 0 0
2383 11:35:14.135203 13 0 0
2384 11:35:14.135304 14 0 0
2385 11:35:14.138780 15 0 0
2386 11:35:14.138885 16 0 0
2387 11:35:14.138975 17 0 0
2388 11:35:14.141982 18 0 0
2389 11:35:14.142091 19 0 0
2390 11:35:14.145039 20 0 0
2391 11:35:14.145139 21 0 0
2392 11:35:14.148211 22 0 0
2393 11:35:14.148314 23 0 0
2394 11:35:14.148407 24 0 0
2395 11:35:14.151981 25 0 0
2396 11:35:14.152090 26 0 0
2397 11:35:14.155135 27 0 0
2398 11:35:14.155238 28 0 0
2399 11:35:14.158386 29 0 0
2400 11:35:14.158488 30 0 0
2401 11:35:14.158578 31 0 0
2402 11:35:14.161482 32 0 0
2403 11:35:14.161581 33 0 ff
2404 11:35:14.165012 34 0 ff
2405 11:35:14.165112 35 0 ff
2406 11:35:14.168459 36 ff ff
2407 11:35:14.168559 37 ff ff
2408 11:35:14.171137 38 ff ff
2409 11:35:14.171237 39 ff ff
2410 11:35:14.171328 40 ff ff
2411 11:35:14.175095 41 ff ff
2412 11:35:14.175195 42 ff ff
2413 11:35:14.181712 pass bytecount = 0xff (0xff: all bytes pass)
2414 11:35:14.181811
2415 11:35:14.181895 DQS0 dly: 36
2416 11:35:14.181977 DQS1 dly: 33
2417 11:35:14.185182 Write Rank0 MR2 =0x2d
2418 11:35:14.188438 [RankSwap] Rank num 2, (Multi 1), Rank 0
2419 11:35:14.191241 Write Rank0 MR1 =0xd6
2420 11:35:14.191338 [Gating]
2421 11:35:14.191425 ==
2422 11:35:14.197952 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2423 11:35:14.201032 fsp= 1, odt_onoff= 1, Byte mode= 0
2424 11:35:14.201130 ==
2425 11:35:14.204425 3 1 0 |2c2b 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2426 11:35:14.208201 3 1 4 |2c2b a09 |(11 11)(11 11) |(1 1)(0 0)| 0
2427 11:35:14.210928 3 1 8 |2c2b 3636 |(11 11)(0 0) |(1 1)(1 1)| 0
2428 11:35:14.217936 3 1 12 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2429 11:35:14.220792 3 1 16 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2430 11:35:14.224004 [Byte 0] Lead/lag falling Transition (3, 1, 16)
2431 11:35:14.230596 3 1 20 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
2432 11:35:14.233834 3 1 24 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
2433 11:35:14.237026 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2434 11:35:14.243727 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2435 11:35:14.247030 [Byte 1] Lead/lag Transition tap number (1)
2436 11:35:14.250453 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2437 11:35:14.256695 3 2 8 |2c2b 3232 |(11 11)(11 11) |(1 0)(0 0)| 0
2438 11:35:14.260222 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2439 11:35:14.263356 3 2 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2440 11:35:14.270241 3 2 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
2441 11:35:14.273391 [Byte 0] Lead/lag Transition tap number (10)
2442 11:35:14.276577 3 2 24 |303 3434 |(11 11)(11 11) |(0 0)(0 1)| 0
2443 11:35:14.280327 3 2 28 |303 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
2444 11:35:14.286632 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
2445 11:35:14.289975 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2446 11:35:14.293018 3 3 8 |3534 3c3c |(11 11)(10 10) |(0 0)(1 1)| 0
2447 11:35:14.299546 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2448 11:35:14.302787 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2449 11:35:14.305729 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2450 11:35:14.312585 3 3 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2451 11:35:14.316299 3 3 28 |3534 3332 |(11 11)(11 11) |(0 0)(1 1)| 0
2452 11:35:14.318984 3 4 0 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
2453 11:35:14.325425 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
2454 11:35:14.329139 [Byte 1] Lead/lag Transition tap number (1)
2455 11:35:14.332347 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2456 11:35:14.335693 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2457 11:35:14.342499 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2458 11:35:14.345351 3 4 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2459 11:35:14.348855 3 4 24 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2460 11:35:14.355674 3 4 28 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2461 11:35:14.359012 3 5 0 |3d3d 504 |(11 11)(11 11) |(1 1)(1 1)| 0
2462 11:35:14.362015 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2463 11:35:14.368165 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 11:35:14.371788 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 11:35:14.374942 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2466 11:35:14.381213 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2467 11:35:14.384824 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2468 11:35:14.388080 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 11:35:14.394906 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 11:35:14.398020 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2471 11:35:14.401139 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2472 11:35:14.407862 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2473 11:35:14.410995 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2474 11:35:14.414254 [Byte 0] Lead/lag falling Transition (3, 6, 16)
2475 11:35:14.421032 3 6 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2476 11:35:14.424127 [Byte 1] Lead/lag falling Transition (3, 6, 20)
2477 11:35:14.427170 3 6 24 |403 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
2478 11:35:14.430755 [Byte 0] Lead/lag Transition tap number (3)
2479 11:35:14.437437 [Byte 1] Lead/lag Transition tap number (2)
2480 11:35:14.440969 3 6 28 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
2481 11:35:14.443850 [Byte 0]First pass (3, 6, 28)
2482 11:35:14.447194 3 7 0 |4646 1717 |(0 0)(11 11) |(0 0)(0 0)| 0
2483 11:35:14.450377 3 7 4 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2484 11:35:14.453809 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2485 11:35:14.456633 [Byte 1]First pass (3, 7, 8)
2486 11:35:14.460138 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2487 11:35:14.466689 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2488 11:35:14.470273 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2489 11:35:14.473243 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2490 11:35:14.476807 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2491 11:35:14.483134 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2492 11:35:14.486881 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2493 11:35:14.489956 4 0 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2494 11:35:14.492816 All bytes gating window > 1UI, Early break!
2495 11:35:14.492914
2496 11:35:14.496192 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 22)
2497 11:35:14.496293
2498 11:35:14.502560 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24)
2499 11:35:14.502661
2500 11:35:14.502749
2501 11:35:14.502834
2502 11:35:14.505828 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
2503 11:35:14.505930
2504 11:35:14.509207 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24)
2505 11:35:14.509306
2506 11:35:14.509393
2507 11:35:14.512693 Write Rank0 MR1 =0x56
2508 11:35:14.512797
2509 11:35:14.515651 best RODT dly(2T, 0.5T) = (2, 3)
2510 11:35:14.515750
2511 11:35:14.519295 best RODT dly(2T, 0.5T) = (2, 3)
2512 11:35:14.519396 ==
2513 11:35:14.522463 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2514 11:35:14.525647 fsp= 1, odt_onoff= 1, Byte mode= 0
2515 11:35:14.525748 ==
2516 11:35:14.531940 Start DQ dly to find pass range UseTestEngine =0
2517 11:35:14.535729 x-axis: bit #, y-axis: DQ dly (-127~63)
2518 11:35:14.535830 RX Vref Scan = 0
2519 11:35:14.538914 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2520 11:35:14.542268 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2521 11:35:14.545082 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2522 11:35:14.548425 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2523 11:35:14.552031 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2524 11:35:14.555397 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2525 11:35:14.558247 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2526 11:35:14.558354 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2527 11:35:14.561447 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2528 11:35:14.565219 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2529 11:35:14.568169 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2530 11:35:14.571388 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2531 11:35:14.574529 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2532 11:35:14.577909 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2533 11:35:14.581345 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2534 11:35:14.584786 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2535 11:35:14.584889 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2536 11:35:14.588263 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2537 11:35:14.591398 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2538 11:35:14.594629 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2539 11:35:14.598114 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2540 11:35:14.601127 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2541 11:35:14.604801 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2542 11:35:14.604903 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2543 11:35:14.607463 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2544 11:35:14.611435 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2545 11:35:14.614897 0, [0] xxxxxxxx ooxxxxxo [MSB]
2546 11:35:14.618538 1, [0] xxxoxxxx ooxxxxxo [MSB]
2547 11:35:14.621269 2, [0] xxxoxxxx ooxxxxxo [MSB]
2548 11:35:14.624775 3, [0] xoooxxxo oooxxxxo [MSB]
2549 11:35:14.624878 4, [0] xoooxxxo oooxxxxo [MSB]
2550 11:35:14.627681 5, [0] xooooxxo oooooooo [MSB]
2551 11:35:14.630627 6, [0] xooooxxo oooooooo [MSB]
2552 11:35:14.633838 7, [0] xooooooo oooooooo [MSB]
2553 11:35:14.637253 8, [0] xooooooo oooooooo [MSB]
2554 11:35:14.640653 33, [0] oooxoooo ooooooox [MSB]
2555 11:35:14.643558 34, [0] oooxoooo ooooooox [MSB]
2556 11:35:14.643659 35, [0] oooxoooo xoooooox [MSB]
2557 11:35:14.646802 36, [0] oooxoooo xxooooox [MSB]
2558 11:35:14.650490 37, [0] ooxxoooo xxooooox [MSB]
2559 11:35:14.653433 38, [0] ooxxoooo xxooooox [MSB]
2560 11:35:14.656753 39, [0] xxxxxoox xxooxoox [MSB]
2561 11:35:14.660507 40, [0] xxxxxoox xxxoxoox [MSB]
2562 11:35:14.663669 41, [0] xxxxxxxx xxxxxxxx [MSB]
2563 11:35:14.667116 iDelay=41, Bit 0, Center 23 (9 ~ 38) 30
2564 11:35:14.670184 iDelay=41, Bit 1, Center 20 (3 ~ 38) 36
2565 11:35:14.673353 iDelay=41, Bit 2, Center 19 (3 ~ 36) 34
2566 11:35:14.676919 iDelay=41, Bit 3, Center 16 (1 ~ 32) 32
2567 11:35:14.679956 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34
2568 11:35:14.683679 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2569 11:35:14.686702 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2570 11:35:14.689934 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
2571 11:35:14.693139 iDelay=41, Bit 8, Center 17 (0 ~ 34) 35
2572 11:35:14.696280 iDelay=41, Bit 9, Center 17 (0 ~ 35) 36
2573 11:35:14.699562 iDelay=41, Bit 10, Center 21 (3 ~ 39) 37
2574 11:35:14.706328 iDelay=41, Bit 11, Center 22 (5 ~ 40) 36
2575 11:35:14.709773 iDelay=41, Bit 12, Center 21 (5 ~ 38) 34
2576 11:35:14.712666 iDelay=41, Bit 13, Center 22 (5 ~ 40) 36
2577 11:35:14.716573 iDelay=41, Bit 14, Center 22 (5 ~ 40) 36
2578 11:35:14.719376 iDelay=41, Bit 15, Center 14 (-4 ~ 32) 37
2579 11:35:14.719450 ==
2580 11:35:14.726014 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2581 11:35:14.728918 fsp= 1, odt_onoff= 1, Byte mode= 0
2582 11:35:14.729003 ==
2583 11:35:14.729062 DQS Delay:
2584 11:35:14.731972 DQS0 = 0, DQS1 = 0
2585 11:35:14.732045 DQM Delay:
2586 11:35:14.732105 DQM0 = 20, DQM1 = 19
2587 11:35:14.736063 DQ Delay:
2588 11:35:14.739226 DQ0 =23, DQ1 =20, DQ2 =19, DQ3 =16
2589 11:35:14.741969 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
2590 11:35:14.745594 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =22
2591 11:35:14.748830 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =14
2592 11:35:14.748905
2593 11:35:14.748963
2594 11:35:14.749016 DramC Write-DBI off
2595 11:35:14.749067 ==
2596 11:35:14.755082 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2597 11:35:14.758176 fsp= 1, odt_onoff= 1, Byte mode= 0
2598 11:35:14.758251 ==
2599 11:35:14.761881 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2600 11:35:14.761956
2601 11:35:14.764825 Begin, DQ Scan Range 929~1185
2602 11:35:14.764898
2603 11:35:14.764955
2604 11:35:14.768088 TX Vref Scan disable
2605 11:35:14.771397 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2606 11:35:14.774631 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2607 11:35:14.777930 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2608 11:35:14.781397 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2609 11:35:14.784683 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2610 11:35:14.787855 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2611 11:35:14.791306 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2612 11:35:14.794228 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2613 11:35:14.801560 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2614 11:35:14.804313 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2615 11:35:14.807792 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2616 11:35:14.811079 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2617 11:35:14.814195 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2618 11:35:14.817973 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2619 11:35:14.820707 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2620 11:35:14.823954 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2621 11:35:14.827600 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2622 11:35:14.830793 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2623 11:35:14.833877 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2624 11:35:14.837002 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2625 11:35:14.840772 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2626 11:35:14.847093 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2627 11:35:14.850210 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2628 11:35:14.853457 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2629 11:35:14.856619 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2630 11:35:14.860284 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2631 11:35:14.863409 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2632 11:35:14.866561 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2633 11:35:14.869832 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2634 11:35:14.873933 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2635 11:35:14.876672 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2636 11:35:14.879437 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2637 11:35:14.883122 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2638 11:35:14.886153 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2639 11:35:14.889828 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2640 11:35:14.896461 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2641 11:35:14.899303 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2642 11:35:14.902648 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2643 11:35:14.905953 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2644 11:35:14.909480 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2645 11:35:14.912358 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2646 11:35:14.916322 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2647 11:35:14.919377 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2648 11:35:14.921925 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2649 11:35:14.925638 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2650 11:35:14.928712 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2651 11:35:14.931805 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2652 11:35:14.935358 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2653 11:35:14.938482 977 |3 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2654 11:35:14.944881 978 |3 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2655 11:35:14.948893 979 |3 6 19|[0] xxxxxxxx xxxxxxxo [MSB]
2656 11:35:14.952202 980 |3 6 20|[0] xxxxxxxx oxxxxxxo [MSB]
2657 11:35:14.955099 981 |3 6 21|[0] xxxxxxxx ooxxxxxo [MSB]
2658 11:35:14.958144 982 |3 6 22|[0] xxxxxxxx ooxxxxxo [MSB]
2659 11:35:14.961364 983 |3 6 23|[0] xxxxxxxx oooxxxoo [MSB]
2660 11:35:14.965153 984 |3 6 24|[0] xxxxxxxx oooooxoo [MSB]
2661 11:35:14.968342 985 |3 6 25|[0] xxxxxxxo oooooooo [MSB]
2662 11:35:14.974861 996 |3 6 36|[0] oooooooo ooooooox [MSB]
2663 11:35:14.978683 997 |3 6 37|[0] oooooooo ooooooox [MSB]
2664 11:35:14.981632 998 |3 6 38|[0] oooooooo ooooooox [MSB]
2665 11:35:14.984654 999 |3 6 39|[0] oooooooo ooooooox [MSB]
2666 11:35:14.987814 1000 |3 6 40|[0] oooooooo oxooooox [MSB]
2667 11:35:14.991369 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
2668 11:35:14.994935 1002 |3 6 42|[0] oooooooo xxxxxxxx [MSB]
2669 11:35:14.998164 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2670 11:35:15.001383 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2671 11:35:15.004450 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
2672 11:35:15.010925 1006 |3 6 46|[0] ooxxoooo xxxxxxxx [MSB]
2673 11:35:15.014374 1007 |3 6 47|[0] ooxxxoox xxxxxxxx [MSB]
2674 11:35:15.017329 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
2675 11:35:15.020745 Byte0, DQ PI dly=995, DQM PI dly= 995
2676 11:35:15.024458 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 35)
2677 11:35:15.024533
2678 11:35:15.027531 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 35)
2679 11:35:15.031056
2680 11:35:15.033818 Byte1, DQ PI dly=989, DQM PI dly= 989
2681 11:35:15.037222 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2682 11:35:15.037322
2683 11:35:15.040344 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2684 11:35:15.040445
2685 11:35:15.040533 ==
2686 11:35:15.046850 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2687 11:35:15.050184 fsp= 1, odt_onoff= 1, Byte mode= 0
2688 11:35:15.050285 ==
2689 11:35:15.054133 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2690 11:35:15.054231
2691 11:35:15.057294 Begin, DQ Scan Range 965~1029
2692 11:35:15.060140 Write Rank0 MR14 =0x0
2693 11:35:15.066848
2694 11:35:15.066949 CH=1, VrefRange= 0, VrefLevel = 0
2695 11:35:15.073742 TX Bit0 (987~1004) 18 995, Bit8 (984~994) 11 989,
2696 11:35:15.076677 TX Bit1 (986~1003) 18 994, Bit9 (984~993) 10 988,
2697 11:35:15.083654 TX Bit2 (985~999) 15 992, Bit10 (986~998) 13 992,
2698 11:35:15.086797 TX Bit3 (984~996) 13 990, Bit11 (986~997) 12 991,
2699 11:35:15.090036 TX Bit4 (986~1002) 17 994, Bit12 (986~996) 11 991,
2700 11:35:15.096131 TX Bit5 (987~1003) 17 995, Bit13 (987~997) 11 992,
2701 11:35:15.099921 TX Bit6 (986~1003) 18 994, Bit14 (986~994) 9 990,
2702 11:35:15.106116 TX Bit7 (986~1000) 15 993, Bit15 (980~989) 10 984,
2703 11:35:15.106218
2704 11:35:15.106305 Write Rank0 MR14 =0x2
2705 11:35:15.115484
2706 11:35:15.115585 CH=1, VrefRange= 0, VrefLevel = 2
2707 11:35:15.122576 TX Bit0 (986~1005) 20 995, Bit8 (984~995) 12 989,
2708 11:35:15.125882 TX Bit1 (985~1003) 19 994, Bit9 (983~994) 12 988,
2709 11:35:15.131896 TX Bit2 (985~999) 15 992, Bit10 (985~999) 15 992,
2710 11:35:15.135541 TX Bit3 (984~997) 14 990, Bit11 (986~998) 13 992,
2711 11:35:15.138475 TX Bit4 (986~1003) 18 994, Bit12 (985~997) 13 991,
2712 11:35:15.144941 TX Bit5 (987~1004) 18 995, Bit13 (986~999) 14 992,
2713 11:35:15.148681 TX Bit6 (986~1004) 19 995, Bit14 (986~995) 10 990,
2714 11:35:15.155102 TX Bit7 (986~1001) 16 993, Bit15 (980~991) 12 985,
2715 11:35:15.155181
2716 11:35:15.155240 Write Rank0 MR14 =0x4
2717 11:35:15.164647
2718 11:35:15.164723 CH=1, VrefRange= 0, VrefLevel = 4
2719 11:35:15.171137 TX Bit0 (986~1006) 21 996, Bit8 (982~995) 14 988,
2720 11:35:15.174296 TX Bit1 (985~1005) 21 995, Bit9 (982~994) 13 988,
2721 11:35:15.180817 TX Bit2 (984~1000) 17 992, Bit10 (985~1000) 16 992,
2722 11:35:15.184257 TX Bit3 (983~998) 16 990, Bit11 (986~1000) 15 993,
2723 11:35:15.190971 TX Bit4 (985~1004) 20 994, Bit12 (985~999) 15 992,
2724 11:35:15.194183 TX Bit5 (986~1005) 20 995, Bit13 (986~999) 14 992,
2725 11:35:15.197441 TX Bit6 (986~1005) 20 995, Bit14 (985~996) 12 990,
2726 11:35:15.204101 TX Bit7 (985~1002) 18 993, Bit15 (979~992) 14 985,
2727 11:35:15.204179
2728 11:35:15.204237 Write Rank0 MR14 =0x6
2729 11:35:15.213990
2730 11:35:15.214112 CH=1, VrefRange= 0, VrefLevel = 6
2731 11:35:15.220450 TX Bit0 (986~1006) 21 996, Bit8 (982~996) 15 989,
2732 11:35:15.223781 TX Bit1 (985~1005) 21 995, Bit9 (982~995) 14 988,
2733 11:35:15.229913 TX Bit2 (984~1001) 18 992, Bit10 (985~1000) 16 992,
2734 11:35:15.233962 TX Bit3 (983~998) 16 990, Bit11 (986~1000) 15 993,
2735 11:35:15.239844 TX Bit4 (985~1005) 21 995, Bit12 (985~1000) 16 992,
2736 11:35:15.243210 TX Bit5 (986~1005) 20 995, Bit13 (986~1000) 15 993,
2737 11:35:15.246709 TX Bit6 (986~1005) 20 995, Bit14 (986~997) 12 991,
2738 11:35:15.253004 TX Bit7 (985~1004) 20 994, Bit15 (979~993) 15 986,
2739 11:35:15.253081
2740 11:35:15.256216 Write Rank0 MR14 =0x8
2741 11:35:15.263227
2742 11:35:15.263304 CH=1, VrefRange= 0, VrefLevel = 8
2743 11:35:15.269840 TX Bit0 (986~1006) 21 996, Bit8 (981~996) 16 988,
2744 11:35:15.273081 TX Bit1 (985~1006) 22 995, Bit9 (982~995) 14 988,
2745 11:35:15.279821 TX Bit2 (984~1002) 19 993, Bit10 (985~1001) 17 993,
2746 11:35:15.282911 TX Bit3 (983~999) 17 991, Bit11 (985~1000) 16 992,
2747 11:35:15.289327 TX Bit4 (985~1005) 21 995, Bit12 (985~1000) 16 992,
2748 11:35:15.292638 TX Bit5 (986~1006) 21 996, Bit13 (986~1000) 15 993,
2749 11:35:15.296153 TX Bit6 (985~1006) 22 995, Bit14 (985~998) 14 991,
2750 11:35:15.302756 TX Bit7 (985~1004) 20 994, Bit15 (978~993) 16 985,
2751 11:35:15.302835
2752 11:35:15.302895 Write Rank0 MR14 =0xa
2753 11:35:15.312575
2754 11:35:15.315594 CH=1, VrefRange= 0, VrefLevel = 10
2755 11:35:15.319043 TX Bit0 (986~1006) 21 996, Bit8 (980~998) 19 989,
2756 11:35:15.322235 TX Bit1 (985~1006) 22 995, Bit9 (982~996) 15 989,
2757 11:35:15.328880 TX Bit2 (984~1003) 20 993, Bit10 (984~1001) 18 992,
2758 11:35:15.331971 TX Bit3 (983~1000) 18 991, Bit11 (985~1001) 17 993,
2759 11:35:15.338429 TX Bit4 (985~1005) 21 995, Bit12 (984~1001) 18 992,
2760 11:35:15.342120 TX Bit5 (986~1006) 21 996, Bit13 (986~1001) 16 993,
2761 11:35:15.348179 TX Bit6 (985~1006) 22 995, Bit14 (985~999) 15 992,
2762 11:35:15.351936 TX Bit7 (985~1005) 21 995, Bit15 (978~993) 16 985,
2763 11:35:15.352012
2764 11:35:15.355051 Write Rank0 MR14 =0xc
2765 11:35:15.361951
2766 11:35:15.365546 CH=1, VrefRange= 0, VrefLevel = 12
2767 11:35:15.368766 TX Bit0 (985~1006) 22 995, Bit8 (980~998) 19 989,
2768 11:35:15.371692 TX Bit1 (985~1006) 22 995, Bit9 (981~997) 17 989,
2769 11:35:15.378536 TX Bit2 (984~1003) 20 993, Bit10 (985~1001) 17 993,
2770 11:35:15.381322 TX Bit3 (982~1000) 19 991, Bit11 (985~1001) 17 993,
2771 11:35:15.388329 TX Bit4 (985~1006) 22 995, Bit12 (984~1001) 18 992,
2772 11:35:15.391412 TX Bit5 (986~1006) 21 996, Bit13 (985~1001) 17 993,
2773 11:35:15.398041 TX Bit6 (985~1006) 22 995, Bit14 (985~1000) 16 992,
2774 11:35:15.401347 TX Bit7 (985~1005) 21 995, Bit15 (978~994) 17 986,
2775 11:35:15.401423
2776 11:35:15.404449 Write Rank0 MR14 =0xe
2777 11:35:15.411946
2778 11:35:15.414862 CH=1, VrefRange= 0, VrefLevel = 14
2779 11:35:15.418509 TX Bit0 (985~1007) 23 996, Bit8 (980~999) 20 989,
2780 11:35:15.421864 TX Bit1 (984~1006) 23 995, Bit9 (980~998) 19 989,
2781 11:35:15.428123 TX Bit2 (984~1005) 22 994, Bit10 (984~1002) 19 993,
2782 11:35:15.431386 TX Bit3 (982~1001) 20 991, Bit11 (985~1002) 18 993,
2783 11:35:15.438310 TX Bit4 (985~1006) 22 995, Bit12 (984~1002) 19 993,
2784 11:35:15.440974 TX Bit5 (985~1006) 22 995, Bit13 (985~1001) 17 993,
2785 11:35:15.444906 TX Bit6 (985~1006) 22 995, Bit14 (984~1000) 17 992,
2786 11:35:15.451115 TX Bit7 (985~1005) 21 995, Bit15 (978~994) 17 986,
2787 11:35:15.451193
2788 11:35:15.454161 Write Rank0 MR14 =0x10
2789 11:35:15.461740
2790 11:35:15.465190 CH=1, VrefRange= 0, VrefLevel = 16
2791 11:35:15.468497 TX Bit0 (985~1008) 24 996, Bit8 (979~1000) 22 989,
2792 11:35:15.471967 TX Bit1 (984~1007) 24 995, Bit9 (980~998) 19 989,
2793 11:35:15.477990 TX Bit2 (983~1005) 23 994, Bit10 (983~1002) 20 992,
2794 11:35:15.481090 TX Bit3 (981~1002) 22 991, Bit11 (984~1002) 19 993,
2795 11:35:15.487877 TX Bit4 (985~1006) 22 995, Bit12 (984~1002) 19 993,
2796 11:35:15.491206 TX Bit5 (985~1006) 22 995, Bit13 (985~1002) 18 993,
2797 11:35:15.497997 TX Bit6 (985~1006) 22 995, Bit14 (984~1001) 18 992,
2798 11:35:15.501249 TX Bit7 (985~1006) 22 995, Bit15 (977~995) 19 986,
2799 11:35:15.501327
2800 11:35:15.504277 Write Rank0 MR14 =0x12
2801 11:35:15.512170
2802 11:35:15.515132 CH=1, VrefRange= 0, VrefLevel = 18
2803 11:35:15.518324 TX Bit0 (985~1008) 24 996, Bit8 (979~1000) 22 989,
2804 11:35:15.521587 TX Bit1 (984~1007) 24 995, Bit9 (980~1000) 21 990,
2805 11:35:15.528207 TX Bit2 (983~1006) 24 994, Bit10 (982~1002) 21 992,
2806 11:35:15.531427 TX Bit3 (981~1002) 22 991, Bit11 (984~1002) 19 993,
2807 11:35:15.538248 TX Bit4 (985~1006) 22 995, Bit12 (983~1002) 20 992,
2808 11:35:15.541126 TX Bit5 (985~1007) 23 996, Bit13 (985~1002) 18 993,
2809 11:35:15.548085 TX Bit6 (984~1007) 24 995, Bit14 (983~1001) 19 992,
2810 11:35:15.551102 TX Bit7 (985~1006) 22 995, Bit15 (977~995) 19 986,
2811 11:35:15.551179
2812 11:35:15.554633 Write Rank0 MR14 =0x14
2813 11:35:15.562432
2814 11:35:15.566862 CH=1, VrefRange= 0, VrefLevel = 20
2815 11:35:15.569403 TX Bit0 (985~1008) 24 996, Bit8 (979~1001) 23 990,
2816 11:35:15.571520 TX Bit1 (984~1007) 24 995, Bit9 (979~1000) 22 989,
2817 11:35:15.578456 TX Bit2 (983~1006) 24 994, Bit10 (983~1002) 20 992,
2818 11:35:15.581530 TX Bit3 (980~1003) 24 991, Bit11 (984~1003) 20 993,
2819 11:35:15.588067 TX Bit4 (985~1007) 23 996, Bit12 (982~1003) 22 992,
2820 11:35:15.591155 TX Bit5 (985~1007) 23 996, Bit13 (985~1003) 19 994,
2821 11:35:15.598044 TX Bit6 (984~1007) 24 995, Bit14 (983~1002) 20 992,
2822 11:35:15.601060 TX Bit7 (984~1006) 23 995, Bit15 (977~996) 20 986,
2823 11:35:15.601137
2824 11:35:15.604395 Write Rank0 MR14 =0x16
2825 11:35:15.612288
2826 11:35:15.615471 CH=1, VrefRange= 0, VrefLevel = 22
2827 11:35:15.618612 TX Bit0 (985~1009) 25 997, Bit8 (979~1001) 23 990,
2828 11:35:15.621880 TX Bit1 (984~1008) 25 996, Bit9 (979~1000) 22 989,
2829 11:35:15.629058 TX Bit2 (983~1006) 24 994, Bit10 (982~1003) 22 992,
2830 11:35:15.632225 TX Bit3 (980~1004) 25 992, Bit11 (983~1003) 21 993,
2831 11:35:15.638660 TX Bit4 (984~1007) 24 995, Bit12 (983~1003) 21 993,
2832 11:35:15.641804 TX Bit5 (985~1008) 24 996, Bit13 (984~1003) 20 993,
2833 11:35:15.648579 TX Bit6 (984~1007) 24 995, Bit14 (982~1002) 21 992,
2834 11:35:15.651652 TX Bit7 (984~1007) 24 995, Bit15 (977~997) 21 987,
2835 11:35:15.651752
2836 11:35:15.655409 Write Rank0 MR14 =0x18
2837 11:35:15.662810
2838 11:35:15.665821 CH=1, VrefRange= 0, VrefLevel = 24
2839 11:35:15.669308 TX Bit0 (985~1009) 25 997, Bit8 (978~1001) 24 989,
2840 11:35:15.672202 TX Bit1 (984~1008) 25 996, Bit9 (979~1001) 23 990,
2841 11:35:15.679351 TX Bit2 (982~1006) 25 994, Bit10 (981~1004) 24 992,
2842 11:35:15.682712 TX Bit3 (980~1004) 25 992, Bit11 (982~1004) 23 993,
2843 11:35:15.688890 TX Bit4 (984~1008) 25 996, Bit12 (983~1003) 21 993,
2844 11:35:15.692343 TX Bit5 (985~1008) 24 996, Bit13 (984~1003) 20 993,
2845 11:35:15.698590 TX Bit6 (984~1008) 25 996, Bit14 (982~1002) 21 992,
2846 11:35:15.702221 TX Bit7 (984~1007) 24 995, Bit15 (977~997) 21 987,
2847 11:35:15.702323
2848 11:35:15.705564 Write Rank0 MR14 =0x1a
2849 11:35:15.712846
2850 11:35:15.716536 CH=1, VrefRange= 0, VrefLevel = 26
2851 11:35:15.719608 TX Bit0 (985~1010) 26 997, Bit8 (978~1001) 24 989,
2852 11:35:15.722983 TX Bit1 (983~1009) 27 996, Bit9 (978~1001) 24 989,
2853 11:35:15.729561 TX Bit2 (982~1007) 26 994, Bit10 (981~1004) 24 992,
2854 11:35:15.732701 TX Bit3 (979~1005) 27 992, Bit11 (982~1004) 23 993,
2855 11:35:15.739779 TX Bit4 (984~1008) 25 996, Bit12 (982~1004) 23 993,
2856 11:35:15.742568 TX Bit5 (985~1009) 25 997, Bit13 (984~1003) 20 993,
2857 11:35:15.748984 TX Bit6 (984~1009) 26 996, Bit14 (981~1003) 23 992,
2858 11:35:15.752811 TX Bit7 (984~1007) 24 995, Bit15 (976~999) 24 987,
2859 11:35:15.752909
2860 11:35:15.756338 Write Rank0 MR14 =0x1c
2861 11:35:15.763783
2862 11:35:15.767169 CH=1, VrefRange= 0, VrefLevel = 28
2863 11:35:15.770113 TX Bit0 (984~1010) 27 997, Bit8 (978~1001) 24 989,
2864 11:35:15.773452 TX Bit1 (984~1009) 26 996, Bit9 (978~1001) 24 989,
2865 11:35:15.780174 TX Bit2 (982~1006) 25 994, Bit10 (981~1004) 24 992,
2866 11:35:15.783409 TX Bit3 (979~1005) 27 992, Bit11 (982~1004) 23 993,
2867 11:35:15.789752 TX Bit4 (983~1009) 27 996, Bit12 (983~1004) 22 993,
2868 11:35:15.793179 TX Bit5 (985~1009) 25 997, Bit13 (983~1004) 22 993,
2869 11:35:15.800108 TX Bit6 (984~1009) 26 996, Bit14 (980~1003) 24 991,
2870 11:35:15.802913 TX Bit7 (983~1008) 26 995, Bit15 (976~999) 24 987,
2871 11:35:15.803013
2872 11:35:15.806115 Write Rank0 MR14 =0x1e
2873 11:35:15.814114
2874 11:35:15.817490 CH=1, VrefRange= 0, VrefLevel = 30
2875 11:35:15.820893 TX Bit0 (984~1010) 27 997, Bit8 (978~1001) 24 989,
2876 11:35:15.823789 TX Bit1 (984~1009) 26 996, Bit9 (978~1001) 24 989,
2877 11:35:15.830494 TX Bit2 (982~1006) 25 994, Bit10 (981~1004) 24 992,
2878 11:35:15.833643 TX Bit3 (979~1005) 27 992, Bit11 (982~1004) 23 993,
2879 11:35:15.840129 TX Bit4 (983~1009) 27 996, Bit12 (983~1004) 22 993,
2880 11:35:15.844099 TX Bit5 (985~1009) 25 997, Bit13 (983~1004) 22 993,
2881 11:35:15.850117 TX Bit6 (984~1009) 26 996, Bit14 (980~1003) 24 991,
2882 11:35:15.853276 TX Bit7 (983~1008) 26 995, Bit15 (976~999) 24 987,
2883 11:35:15.853376
2884 11:35:15.856375 Write Rank0 MR14 =0x20
2885 11:35:15.864553
2886 11:35:15.868303 CH=1, VrefRange= 0, VrefLevel = 32
2887 11:35:15.871207 TX Bit0 (984~1010) 27 997, Bit8 (978~1001) 24 989,
2888 11:35:15.874387 TX Bit1 (984~1009) 26 996, Bit9 (978~1001) 24 989,
2889 11:35:15.880825 TX Bit2 (982~1006) 25 994, Bit10 (981~1004) 24 992,
2890 11:35:15.884714 TX Bit3 (979~1005) 27 992, Bit11 (982~1004) 23 993,
2891 11:35:15.890704 TX Bit4 (983~1009) 27 996, Bit12 (983~1004) 22 993,
2892 11:35:15.894668 TX Bit5 (985~1009) 25 997, Bit13 (983~1004) 22 993,
2893 11:35:15.900755 TX Bit6 (984~1009) 26 996, Bit14 (980~1003) 24 991,
2894 11:35:15.903951 TX Bit7 (983~1008) 26 995, Bit15 (976~999) 24 987,
2895 11:35:15.904056
2896 11:35:15.907122 Write Rank0 MR14 =0x22
2897 11:35:15.915379
2898 11:35:15.918170 CH=1, VrefRange= 0, VrefLevel = 34
2899 11:35:15.921629 TX Bit0 (984~1010) 27 997, Bit8 (978~1001) 24 989,
2900 11:35:15.924741 TX Bit1 (984~1009) 26 996, Bit9 (978~1001) 24 989,
2901 11:35:15.931045 TX Bit2 (982~1006) 25 994, Bit10 (981~1004) 24 992,
2902 11:35:15.934960 TX Bit3 (979~1005) 27 992, Bit11 (982~1004) 23 993,
2903 11:35:15.941265 TX Bit4 (983~1009) 27 996, Bit12 (983~1004) 22 993,
2904 11:35:15.944363 TX Bit5 (985~1009) 25 997, Bit13 (983~1004) 22 993,
2905 11:35:15.950843 TX Bit6 (984~1009) 26 996, Bit14 (980~1003) 24 991,
2906 11:35:15.953992 TX Bit7 (983~1008) 26 995, Bit15 (976~999) 24 987,
2907 11:35:15.954114
2908 11:35:15.954203
2909 11:35:15.957342 TX Vref found, early break! 372< 376
2910 11:35:15.964698 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2911 11:35:15.964803 u1DelayCellOfst[0]=6 cells (5 PI)
2912 11:35:15.967132 u1DelayCellOfst[1]=5 cells (4 PI)
2913 11:35:15.970805 u1DelayCellOfst[2]=2 cells (2 PI)
2914 11:35:15.974045 u1DelayCellOfst[3]=0 cells (0 PI)
2915 11:35:15.977420 u1DelayCellOfst[4]=5 cells (4 PI)
2916 11:35:15.980601 u1DelayCellOfst[5]=6 cells (5 PI)
2917 11:35:15.983870 u1DelayCellOfst[6]=5 cells (4 PI)
2918 11:35:15.986795 u1DelayCellOfst[7]=3 cells (3 PI)
2919 11:35:15.990243 Byte0, DQ PI dly=992, DQM PI dly= 994
2920 11:35:15.993439 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
2921 11:35:15.993518
2922 11:35:15.999904 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
2923 11:35:16.000054
2924 11:35:16.003711 u1DelayCellOfst[8]=2 cells (2 PI)
2925 11:35:16.006948 u1DelayCellOfst[9]=2 cells (2 PI)
2926 11:35:16.007057 u1DelayCellOfst[10]=6 cells (5 PI)
2927 11:35:16.010256 u1DelayCellOfst[11]=7 cells (6 PI)
2928 11:35:16.013238 u1DelayCellOfst[12]=7 cells (6 PI)
2929 11:35:16.016236 u1DelayCellOfst[13]=7 cells (6 PI)
2930 11:35:16.019925 u1DelayCellOfst[14]=5 cells (4 PI)
2931 11:35:16.022800 u1DelayCellOfst[15]=0 cells (0 PI)
2932 11:35:16.026479 Byte1, DQ PI dly=987, DQM PI dly= 990
2933 11:35:16.032643 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2934 11:35:16.032749
2935 11:35:16.036432 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2936 11:35:16.036532
2937 11:35:16.039922 Write Rank0 MR14 =0x1c
2938 11:35:16.040020
2939 11:35:16.040109 Final TX Range 0 Vref 28
2940 11:35:16.040196
2941 11:35:16.045840 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2942 11:35:16.045944
2943 11:35:16.053039 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2944 11:35:16.059139 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2945 11:35:16.069195 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2946 11:35:16.069300 Write Rank0 MR3 =0xb0
2947 11:35:16.072929 DramC Write-DBI on
2948 11:35:16.073032 ==
2949 11:35:16.075279 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2950 11:35:16.078859 fsp= 1, odt_onoff= 1, Byte mode= 0
2951 11:35:16.078969 ==
2952 11:35:16.085712 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2953 11:35:16.085821
2954 11:35:16.088993 Begin, DQ Scan Range 710~774
2955 11:35:16.089103
2956 11:35:16.089199
2957 11:35:16.089290 TX Vref Scan disable
2958 11:35:16.091529 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2959 11:35:16.095184 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2960 11:35:16.098480 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2961 11:35:16.101685 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2962 11:35:16.108916 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2963 11:35:16.111310 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2964 11:35:16.114940 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2965 11:35:16.118260 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2966 11:35:16.121511 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2967 11:35:16.124542 719 |2 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2968 11:35:16.128219 720 |2 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2969 11:35:16.131277 721 |2 6 17|[0] xxxxxxxx xxxxxxxx [MSB]
2970 11:35:16.134690 722 |2 6 18|[0] xxxxxxxx xxxxxxxx [MSB]
2971 11:35:16.137576 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2972 11:35:16.141382 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
2973 11:35:16.144368 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
2974 11:35:16.147963 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
2975 11:35:16.154268 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
2976 11:35:16.160746 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2977 11:35:16.164016 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2978 11:35:16.167530 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2979 11:35:16.170657 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2980 11:35:16.173751 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
2981 11:35:16.177007 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
2982 11:35:16.180847 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
2983 11:35:16.183905 754 |2 6 50|[0] oooooooo xxxxxxxx [MSB]
2984 11:35:16.187142 755 |2 6 51|[0] xxxxxxxx xxxxxxxx [MSB]
2985 11:35:16.190500 Byte0, DQ PI dly=741, DQM PI dly= 741
2986 11:35:16.196881 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 37)
2987 11:35:16.196988
2988 11:35:16.200345 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 37)
2989 11:35:16.200454
2990 11:35:16.203676 Byte1, DQ PI dly=734, DQM PI dly= 734
2991 11:35:16.206588 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 30)
2992 11:35:16.206693
2993 11:35:16.213383 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 30)
2994 11:35:16.213489
2995 11:35:16.219958 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2996 11:35:16.226320 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2997 11:35:16.233479 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2998 11:35:16.236411 Write Rank0 MR3 =0x30
2999 11:35:16.236516 DramC Write-DBI off
3000 11:35:16.236613
3001 11:35:16.236707 [DATLAT]
3002 11:35:16.239450 Freq=1600, CH1 RK0, use_rxtx_scan=0
3003 11:35:16.239556
3004 11:35:16.242785 DATLAT Default: 0xf
3005 11:35:16.242891 7, 0xFFFF, sum=0
3006 11:35:16.245862 8, 0xFFFF, sum=0
3007 11:35:16.245968 9, 0xFFFF, sum=0
3008 11:35:16.249123 10, 0xFFFF, sum=0
3009 11:35:16.249230 11, 0xFFFF, sum=0
3010 11:35:16.252593 12, 0xFFFF, sum=0
3011 11:35:16.252701 13, 0xFFFF, sum=0
3012 11:35:16.256097 14, 0x0, sum=1
3013 11:35:16.256205 15, 0x0, sum=2
3014 11:35:16.259708 16, 0x0, sum=3
3015 11:35:16.259813 17, 0x0, sum=4
3016 11:35:16.262585 pattern=2 first_step=14 total pass=5 best_step=16
3017 11:35:16.262690 ==
3018 11:35:16.269279 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3019 11:35:16.272335 fsp= 1, odt_onoff= 1, Byte mode= 0
3020 11:35:16.272441 ==
3021 11:35:16.275786 Start DQ dly to find pass range UseTestEngine =1
3022 11:35:16.279016 x-axis: bit #, y-axis: DQ dly (-127~63)
3023 11:35:16.282548 RX Vref Scan = 1
3024 11:35:16.389053
3025 11:35:16.389214 RX Vref found, early break!
3026 11:35:16.389314
3027 11:35:16.395999 Final RX Vref 11, apply to both rank0 and 1
3028 11:35:16.396107 ==
3029 11:35:16.399277 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3030 11:35:16.402122 fsp= 1, odt_onoff= 1, Byte mode= 0
3031 11:35:16.402230 ==
3032 11:35:16.405459 DQS Delay:
3033 11:35:16.405567 DQS0 = 0, DQS1 = 0
3034 11:35:16.405662 DQM Delay:
3035 11:35:16.409040 DQM0 = 20, DQM1 = 19
3036 11:35:16.409145 DQ Delay:
3037 11:35:16.411876 DQ0 =22, DQ1 =20, DQ2 =19, DQ3 =16
3038 11:35:16.415774 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21
3039 11:35:16.418704 DQ8 =17, DQ9 =17, DQ10 =21, DQ11 =21
3040 11:35:16.422125 DQ12 =22, DQ13 =21, DQ14 =22, DQ15 =14
3041 11:35:16.422228
3042 11:35:16.422321
3043 11:35:16.422411
3044 11:35:16.425492 [DramC_TX_OE_Calibration] TA2
3045 11:35:16.428246 Original DQ_B0 (3 6) =30, OEN = 27
3046 11:35:16.432133 Original DQ_B1 (3 6) =30, OEN = 27
3047 11:35:16.435359 23, 0x0, End_B0=23 End_B1=23
3048 11:35:16.438118 24, 0x0, End_B0=24 End_B1=24
3049 11:35:16.438195 25, 0x0, End_B0=25 End_B1=25
3050 11:35:16.441695 26, 0x0, End_B0=26 End_B1=26
3051 11:35:16.444572 27, 0x0, End_B0=27 End_B1=27
3052 11:35:16.448183 28, 0x0, End_B0=28 End_B1=28
3053 11:35:16.451199 29, 0x0, End_B0=29 End_B1=29
3054 11:35:16.451276 30, 0x0, End_B0=30 End_B1=30
3055 11:35:16.454409 31, 0xFFFF, End_B0=30 End_B1=30
3056 11:35:16.461590 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3057 11:35:16.467868 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3058 11:35:16.467944
3059 11:35:16.468002
3060 11:35:16.468056 Write Rank0 MR23 =0x3f
3061 11:35:16.471456 [DQSOSC]
3062 11:35:16.477491 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0x202, tDQSOscB0 = 459 ps tDQSOscB1 = 459 ps
3063 11:35:16.483942 CH1_RK0: MR19=0x202, MR18=0xADAD, DQSOSC=459, MR23=63, INC=11, DEC=17
3064 11:35:16.487320 Write Rank0 MR23 =0x3f
3065 11:35:16.487398 [DQSOSC]
3066 11:35:16.493610 [DQSOSCAuto] RK0, (LSB)MR18= 0xafaf, (MSB)MR19= 0x202, tDQSOscB0 = 458 ps tDQSOscB1 = 458 ps
3067 11:35:16.497118 CH1 RK0: MR19=202, MR18=AFAF
3068 11:35:16.500049 [RankSwap] Rank num 2, (Multi 1), Rank 1
3069 11:35:16.503706 Write Rank0 MR2 =0xad
3070 11:35:16.503780 [Write Leveling]
3071 11:35:16.506656 delay byte0 byte1 byte2 byte3
3072 11:35:16.506765
3073 11:35:16.510530 10 0 0
3074 11:35:16.510638 11 0 0
3075 11:35:16.513882 12 0 0
3076 11:35:16.513987 13 0 0
3077 11:35:16.514125 14 0 0
3078 11:35:16.517185 15 0 0
3079 11:35:16.517293 16 0 0
3080 11:35:16.520519 17 0 0
3081 11:35:16.520627 18 0 0
3082 11:35:16.520726 19 0 0
3083 11:35:16.523043 20 0 0
3084 11:35:16.523151 21 0 0
3085 11:35:16.526966 22 0 0
3086 11:35:16.527073 23 0 0
3087 11:35:16.529621 24 0 0
3088 11:35:16.529727 25 0 0
3089 11:35:16.529824 26 0 0
3090 11:35:16.533248 27 0 0
3091 11:35:16.533354 28 0 0
3092 11:35:16.536621 29 0 ff
3093 11:35:16.536730 30 0 ff
3094 11:35:16.539828 31 0 ff
3095 11:35:16.539936 32 0 ff
3096 11:35:16.543100 33 ff ff
3097 11:35:16.543207 34 ff ff
3098 11:35:16.543318 35 ff ff
3099 11:35:16.546453 36 ff ff
3100 11:35:16.546561 37 ff ff
3101 11:35:16.549408 38 ff ff
3102 11:35:16.549513 39 ff ff
3103 11:35:16.556284 pass bytecount = 0xff (0xff: all bytes pass)
3104 11:35:16.556391
3105 11:35:16.556484 DQS0 dly: 33
3106 11:35:16.556575 DQS1 dly: 29
3107 11:35:16.559580 Write Rank0 MR2 =0x2d
3108 11:35:16.562397 [RankSwap] Rank num 2, (Multi 1), Rank 0
3109 11:35:16.565818 Write Rank1 MR1 =0xd6
3110 11:35:16.565923 [Gating]
3111 11:35:16.566048 ==
3112 11:35:16.572309 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3113 11:35:16.576060 fsp= 1, odt_onoff= 1, Byte mode= 0
3114 11:35:16.576140 ==
3115 11:35:16.579354 3 1 0 |2c2b 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
3116 11:35:16.582690 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3117 11:35:16.588740 3 1 8 |2c2b 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
3118 11:35:16.591972 3 1 12 |2c2b 3535 |(11 11)(10 10) |(0 0)(1 1)| 0
3119 11:35:16.595287 3 1 16 |2c2b 3030 |(11 11)(11 11) |(1 0)(0 0)| 0
3120 11:35:16.601994 3 1 20 |2c2b 3434 |(11 11)(0 0) |(1 0)(1 1)| 0
3121 11:35:16.605139 3 1 24 |2c2b 1414 |(11 11)(11 11) |(1 0)(1 1)| 0
3122 11:35:16.608174 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
3123 11:35:16.614759 3 2 0 |2c2b 3433 |(11 11)(11 11) |(1 0)(1 1)| 0
3124 11:35:16.618014 [Byte 1] Lead/lag falling Transition (3, 2, 0)
3125 11:35:16.621336 3 2 4 |2c2b 3333 |(11 11)(10 10) |(1 0)(1 0)| 0
3126 11:35:16.625080 [Byte 1] Lead/lag Transition tap number (2)
3127 11:35:16.630957 3 2 8 |2c2b 2b2b |(11 11)(11 11) |(1 0)(0 0)| 0
3128 11:35:16.634582 3 2 12 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 0)| 0
3129 11:35:16.638041 3 2 16 |2c2b 302f |(11 11)(11 11) |(0 0)(0 1)| 0
3130 11:35:16.644855 3 2 20 |a0a 3332 |(11 11)(11 11) |(0 0)(1 0)| 0
3131 11:35:16.647852 3 2 24 |3534 3434 |(11 11)(11 11) |(0 0)(1 1)| 0
3132 11:35:16.650612 3 2 28 |3534 3c3b |(11 11)(11 11) |(0 0)(0 0)| 0
3133 11:35:16.657469 3 3 0 |3534 3c3c |(11 11)(11 11) |(0 0)(1 1)| 0
3134 11:35:16.660523 3 3 4 |3534 3c3b |(11 11)(11 11) |(0 0)(0 0)| 0
3135 11:35:16.663928 3 3 8 |3534 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0
3136 11:35:16.670598 3 3 12 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0
3137 11:35:16.673862 3 3 16 |3534 3837 |(11 11)(11 11) |(1 1)(0 0)| 0
3138 11:35:16.676898 3 3 20 |3534 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
3139 11:35:16.683945 3 3 24 |3534 1414 |(11 11)(11 11) |(1 1)(1 1)| 0
3140 11:35:16.686609 [Byte 0] Lead/lag Transition tap number (1)
3141 11:35:16.690344 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3142 11:35:16.697026 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3143 11:35:16.699861 [Byte 1] Lead/lag Transition tap number (1)
3144 11:35:16.703146 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3145 11:35:16.706446 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3146 11:35:16.712810 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3147 11:35:16.716073 3 4 16 |2322 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3148 11:35:16.719481 3 4 20 |505 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3149 11:35:16.726171 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3150 11:35:16.729787 3 4 28 |3d3d 2d2d |(11 11)(11 11) |(1 1)(1 1)| 0
3151 11:35:16.732776 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3152 11:35:16.739568 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3153 11:35:16.742603 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3154 11:35:16.745603 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3155 11:35:16.752432 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3156 11:35:16.755391 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3157 11:35:16.758676 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3158 11:35:16.765542 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3159 11:35:16.768643 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3160 11:35:16.772470 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3161 11:35:16.778369 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3162 11:35:16.782039 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3163 11:35:16.785341 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3164 11:35:16.788454 [Byte 0] Lead/lag Transition tap number (2)
3165 11:35:16.794793 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3166 11:35:16.797993 [Byte 1] Lead/lag Transition tap number (1)
3167 11:35:16.801129 3 6 20 |404 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
3168 11:35:16.808359 3 6 24 |4646 2b2a |(0 0)(11 11) |(0 0)(0 0)| 0
3169 11:35:16.808436 [Byte 0]First pass (3, 6, 24)
3170 11:35:16.814697 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3171 11:35:16.814775 [Byte 1]First pass (3, 6, 28)
3172 11:35:16.821316 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3173 11:35:16.824503 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3174 11:35:16.827647 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3175 11:35:16.831003 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3176 11:35:16.837704 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3177 11:35:16.840688 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3178 11:35:16.844081 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3179 11:35:16.847296 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3180 11:35:16.850878 All bytes gating window > 1UI, Early break!
3181 11:35:16.850953
3182 11:35:16.856988 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3183 11:35:16.857063
3184 11:35:16.860503 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
3185 11:35:16.860581
3186 11:35:16.860639
3187 11:35:16.860693
3188 11:35:16.863979 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3189 11:35:16.864054
3190 11:35:16.867054 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
3191 11:35:16.867130
3192 11:35:16.867189
3193 11:35:16.870706 Write Rank1 MR1 =0x56
3194 11:35:16.870781
3195 11:35:16.873430 best RODT dly(2T, 0.5T) = (2, 3)
3196 11:35:16.873506
3197 11:35:16.876966 best RODT dly(2T, 0.5T) = (2, 3)
3198 11:35:16.877042 ==
3199 11:35:16.880541 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3200 11:35:16.883628 fsp= 1, odt_onoff= 1, Byte mode= 0
3201 11:35:16.886962 ==
3202 11:35:16.890042 Start DQ dly to find pass range UseTestEngine =0
3203 11:35:16.893275 x-axis: bit #, y-axis: DQ dly (-127~63)
3204 11:35:16.893351 RX Vref Scan = 0
3205 11:35:16.896769 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3206 11:35:16.899764 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3207 11:35:16.903273 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3208 11:35:16.906244 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3209 11:35:16.909688 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3210 11:35:16.912945 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3211 11:35:16.916168 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3212 11:35:16.919386 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3213 11:35:16.919463 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3214 11:35:16.922503 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3215 11:35:16.926422 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3216 11:35:16.929534 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3217 11:35:16.932471 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3218 11:35:16.935670 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3219 11:35:16.939345 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3220 11:35:16.942843 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3221 11:35:16.945933 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3222 11:35:16.946016 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3223 11:35:16.949130 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3224 11:35:16.952606 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3225 11:35:16.955636 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3226 11:35:16.958723 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3227 11:35:16.962540 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3228 11:35:16.965333 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3229 11:35:16.968635 -2, [0] xxxxxxxx xxxxxxxo [MSB]
3230 11:35:16.968712 -1, [0] xxxxxxxx xxxxxxxo [MSB]
3231 11:35:16.972426 0, [0] xxxoxxxx xxxxxxxo [MSB]
3232 11:35:16.975615 1, [0] xxxoxxxx xoxxxxxo [MSB]
3233 11:35:16.978692 2, [0] xxooxxxx ooxxxxxo [MSB]
3234 11:35:16.981786 3, [0] xooooxxo oooxxxxo [MSB]
3235 11:35:16.984949 4, [0] xooooxxo oooxxxxo [MSB]
3236 11:35:16.985044 5, [0] xooooxxo oooxxxxo [MSB]
3237 11:35:16.988636 6, [0] oooooooo oooooxoo [MSB]
3238 11:35:16.991752 32, [0] oooxoooo ooooooox [MSB]
3239 11:35:16.995500 33, [0] oooxoooo ooooooox [MSB]
3240 11:35:16.998548 34, [0] oooxoooo ooooooox [MSB]
3241 11:35:17.001431 35, [0] ooxxoooo xoooooox [MSB]
3242 11:35:17.004966 36, [0] ooxxoooo xxooooox [MSB]
3243 11:35:17.005094 37, [0] ooxxoooo xxooooox [MSB]
3244 11:35:17.008310 38, [0] xxxxooox xxooooox [MSB]
3245 11:35:17.011336 39, [0] xxxxxoox xxxoxoox [MSB]
3246 11:35:17.014971 40, [0] xxxxxoox xxxoxoox [MSB]
3247 11:35:17.018800 41, [0] xxxxxxxx xxxxxxxx [MSB]
3248 11:35:17.021211 iDelay=41, Bit 0, Center 21 (6 ~ 37) 32
3249 11:35:17.024267 iDelay=41, Bit 1, Center 20 (3 ~ 37) 35
3250 11:35:17.027647 iDelay=41, Bit 2, Center 18 (2 ~ 34) 33
3251 11:35:17.031077 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32
3252 11:35:17.034659 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
3253 11:35:17.037587 iDelay=41, Bit 5, Center 23 (6 ~ 40) 35
3254 11:35:17.043730 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3255 11:35:17.047608 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
3256 11:35:17.050902 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33
3257 11:35:17.053884 iDelay=41, Bit 9, Center 18 (1 ~ 35) 35
3258 11:35:17.057489 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3259 11:35:17.060219 iDelay=41, Bit 11, Center 23 (6 ~ 40) 35
3260 11:35:17.063885 iDelay=41, Bit 12, Center 22 (6 ~ 38) 33
3261 11:35:17.067104 iDelay=41, Bit 13, Center 23 (7 ~ 40) 34
3262 11:35:17.070421 iDelay=41, Bit 14, Center 23 (6 ~ 40) 35
3263 11:35:17.073797 iDelay=41, Bit 15, Center 14 (-2 ~ 31) 34
3264 11:35:17.073873 ==
3265 11:35:17.080073 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3266 11:35:17.083340 fsp= 1, odt_onoff= 1, Byte mode= 0
3267 11:35:17.083417 ==
3268 11:35:17.083480 DQS Delay:
3269 11:35:17.086836 DQS0 = 0, DQS1 = 0
3270 11:35:17.086910 DQM Delay:
3271 11:35:17.089961 DQM0 = 20, DQM1 = 20
3272 11:35:17.090038 DQ Delay:
3273 11:35:17.093152 DQ0 =21, DQ1 =20, DQ2 =18, DQ3 =15
3274 11:35:17.097188 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3275 11:35:17.100261 DQ8 =18, DQ9 =18, DQ10 =20, DQ11 =23
3276 11:35:17.103261 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =14
3277 11:35:17.103340
3278 11:35:17.103401
3279 11:35:17.106695 DramC Write-DBI off
3280 11:35:17.106772 ==
3281 11:35:17.109977 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3282 11:35:17.113376 fsp= 1, odt_onoff= 1, Byte mode= 0
3283 11:35:17.113454 ==
3284 11:35:17.119498 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3285 11:35:17.119610
3286 11:35:17.119707 Begin, DQ Scan Range 925~1181
3287 11:35:17.122702
3288 11:35:17.122808
3289 11:35:17.122905 TX Vref Scan disable
3290 11:35:17.126244 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3291 11:35:17.129733 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3292 11:35:17.132426 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3293 11:35:17.139376 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3294 11:35:17.142765 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3295 11:35:17.145809 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3296 11:35:17.149469 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3297 11:35:17.152424 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3298 11:35:17.155522 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3299 11:35:17.158810 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3300 11:35:17.162231 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3301 11:35:17.165565 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3302 11:35:17.168581 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3303 11:35:17.171936 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3304 11:35:17.175021 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3305 11:35:17.178384 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3306 11:35:17.185172 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3307 11:35:17.188434 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3308 11:35:17.191759 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3309 11:35:17.194937 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3310 11:35:17.198376 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3311 11:35:17.201932 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3312 11:35:17.204610 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3313 11:35:17.208305 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3314 11:35:17.211606 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3315 11:35:17.215022 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3316 11:35:17.218104 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3317 11:35:17.220976 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3318 11:35:17.224436 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3319 11:35:17.231011 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3320 11:35:17.234476 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3321 11:35:17.237630 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3322 11:35:17.240990 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3323 11:35:17.244042 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3324 11:35:17.247404 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3325 11:35:17.250803 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3326 11:35:17.254143 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3327 11:35:17.256907 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3328 11:35:17.260168 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3329 11:35:17.263974 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3330 11:35:17.266895 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3331 11:35:17.270288 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3332 11:35:17.273863 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3333 11:35:17.276820 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3334 11:35:17.280225 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3335 11:35:17.286889 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3336 11:35:17.290039 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3337 11:35:17.293196 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3338 11:35:17.296529 973 |3 6 13|[0] xxxxxxxx xxxxxxxo [MSB]
3339 11:35:17.299755 974 |3 6 14|[0] xxxxxxxx ooxxxxxo [MSB]
3340 11:35:17.303107 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3341 11:35:17.306603 976 |3 6 16|[0] xxxxxxxx ooxxxxxo [MSB]
3342 11:35:17.309389 977 |3 6 17|[0] xxxxxxxx ooooxxxo [MSB]
3343 11:35:17.313340 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3344 11:35:17.315843 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3345 11:35:17.319898 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3346 11:35:17.322582 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3347 11:35:17.325893 982 |3 6 22|[0] xxxxxxxo oooooooo [MSB]
3348 11:35:17.332623 983 |3 6 23|[0] xooooooo oooooooo [MSB]
3349 11:35:17.335762 992 |3 6 32|[0] oooooooo ooooooox [MSB]
3350 11:35:17.339879 993 |3 6 33|[0] oooooooo oxooooox [MSB]
3351 11:35:17.342294 994 |3 6 34|[0] oooooooo oxooooox [MSB]
3352 11:35:17.345525 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3353 11:35:17.349129 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3354 11:35:17.351993 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3355 11:35:17.355726 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3356 11:35:17.362270 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3357 11:35:17.365648 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3358 11:35:17.368933 1001 |3 6 41|[0] ooxxoooo xxxxxxxx [MSB]
3359 11:35:17.372053 1002 |3 6 42|[0] ooxxoooo xxxxxxxx [MSB]
3360 11:35:17.375979 1003 |3 6 43|[0] ooxxxoxx xxxxxxxx [MSB]
3361 11:35:17.378706 1004 |3 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
3362 11:35:17.381605 Byte0, DQ PI dly=991, DQM PI dly= 991
3363 11:35:17.385457 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
3364 11:35:17.385532
3365 11:35:17.391666 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3366 11:35:17.391755
3367 11:35:17.395257 Byte1, DQ PI dly=984, DQM PI dly= 984
3368 11:35:17.398282 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3369 11:35:17.398357
3370 11:35:17.401338 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3371 11:35:17.404977
3372 11:35:17.405049 ==
3373 11:35:17.408095 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3374 11:35:17.411286 fsp= 1, odt_onoff= 1, Byte mode= 0
3375 11:35:17.411360 ==
3376 11:35:17.414346 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3377 11:35:17.417990
3378 11:35:17.418097 Begin, DQ Scan Range 960~1024
3379 11:35:17.420872 Write Rank1 MR14 =0x0
3380 11:35:17.429041
3381 11:35:17.429118 CH=1, VrefRange= 0, VrefLevel = 0
3382 11:35:17.435893 TX Bit0 (985~998) 14 991, Bit8 (977~990) 14 983,
3383 11:35:17.438897 TX Bit1 (984~997) 14 990, Bit9 (978~987) 10 982,
3384 11:35:17.445707 TX Bit2 (982~996) 15 989, Bit10 (979~992) 14 985,
3385 11:35:17.448341 TX Bit3 (980~992) 13 986, Bit11 (980~992) 13 986,
3386 11:35:17.452115 TX Bit4 (984~998) 15 991, Bit12 (980~992) 13 986,
3387 11:35:17.458303 TX Bit5 (985~998) 14 991, Bit13 (980~993) 14 986,
3388 11:35:17.462458 TX Bit6 (984~998) 15 991, Bit14 (980~992) 13 986,
3389 11:35:17.468526 TX Bit7 (984~998) 15 991, Bit15 (974~984) 11 979,
3390 11:35:17.468622
3391 11:35:17.468682 Write Rank1 MR14 =0x2
3392 11:35:17.477170
3393 11:35:17.477267 CH=1, VrefRange= 0, VrefLevel = 2
3394 11:35:17.483374 TX Bit0 (985~999) 15 992, Bit8 (976~991) 16 983,
3395 11:35:17.486874 TX Bit1 (984~998) 15 991, Bit9 (977~988) 12 982,
3396 11:35:17.493317 TX Bit2 (982~996) 15 989, Bit10 (979~993) 15 986,
3397 11:35:17.496577 TX Bit3 (979~993) 15 986, Bit11 (980~993) 14 986,
3398 11:35:17.500660 TX Bit4 (983~999) 17 991, Bit12 (979~993) 15 986,
3399 11:35:17.506782 TX Bit5 (985~999) 15 992, Bit13 (980~994) 15 987,
3400 11:35:17.509985 TX Bit6 (984~999) 16 991, Bit14 (979~992) 14 985,
3401 11:35:17.516471 TX Bit7 (984~999) 16 991, Bit15 (973~985) 13 979,
3402 11:35:17.516557
3403 11:35:17.516615 Write Rank1 MR14 =0x4
3404 11:35:17.524889
3405 11:35:17.524965 CH=1, VrefRange= 0, VrefLevel = 4
3406 11:35:17.531862 TX Bit0 (985~999) 15 992, Bit8 (975~991) 17 983,
3407 11:35:17.534940 TX Bit1 (983~999) 17 991, Bit9 (977~989) 13 983,
3408 11:35:17.541396 TX Bit2 (981~998) 18 989, Bit10 (979~993) 15 986,
3409 11:35:17.545141 TX Bit3 (979~994) 16 986, Bit11 (980~994) 15 987,
3410 11:35:17.548314 TX Bit4 (983~999) 17 991, Bit12 (979~993) 15 986,
3411 11:35:17.554814 TX Bit5 (985~999) 15 992, Bit13 (980~994) 15 987,
3412 11:35:17.558733 TX Bit6 (983~999) 17 991, Bit14 (979~993) 15 986,
3413 11:35:17.564359 TX Bit7 (984~999) 16 991, Bit15 (973~986) 14 979,
3414 11:35:17.564435
3415 11:35:17.564495 Write Rank1 MR14 =0x6
3416 11:35:17.573352
3417 11:35:17.573427 CH=1, VrefRange= 0, VrefLevel = 6
3418 11:35:17.580086 TX Bit0 (985~1000) 16 992, Bit8 (975~992) 18 983,
3419 11:35:17.583108 TX Bit1 (983~999) 17 991, Bit9 (977~990) 14 983,
3420 11:35:17.589609 TX Bit2 (981~998) 18 989, Bit10 (978~994) 17 986,
3421 11:35:17.593057 TX Bit3 (978~995) 18 986, Bit11 (979~994) 16 986,
3422 11:35:17.596681 TX Bit4 (983~999) 17 991, Bit12 (979~994) 16 986,
3423 11:35:17.603704 TX Bit5 (984~1000) 17 992, Bit13 (979~995) 17 987,
3424 11:35:17.606409 TX Bit6 (983~999) 17 991, Bit14 (979~994) 16 986,
3425 11:35:17.612591 TX Bit7 (984~999) 16 991, Bit15 (972~987) 16 979,
3426 11:35:17.612672
3427 11:35:17.612729 Write Rank1 MR14 =0x8
3428 11:35:17.621973
3429 11:35:17.622088 CH=1, VrefRange= 0, VrefLevel = 8
3430 11:35:17.628616 TX Bit0 (984~1000) 17 992, Bit8 (976~992) 17 984,
3431 11:35:17.631994 TX Bit1 (983~1000) 18 991, Bit9 (975~991) 17 983,
3432 11:35:17.638527 TX Bit2 (981~999) 19 990, Bit10 (979~994) 16 986,
3433 11:35:17.641692 TX Bit3 (978~996) 19 987, Bit11 (979~994) 16 986,
3434 11:35:17.644949 TX Bit4 (983~1000) 18 991, Bit12 (978~994) 17 986,
3435 11:35:17.651595 TX Bit5 (984~1000) 17 992, Bit13 (979~996) 18 987,
3436 11:35:17.654829 TX Bit6 (983~1000) 18 991, Bit14 (979~994) 16 986,
3437 11:35:17.661596 TX Bit7 (984~1000) 17 992, Bit15 (972~987) 16 979,
3438 11:35:17.661677
3439 11:35:17.661734 Write Rank1 MR14 =0xa
3440 11:35:17.671033
3441 11:35:17.674227 CH=1, VrefRange= 0, VrefLevel = 10
3442 11:35:17.677348 TX Bit0 (984~1002) 19 993, Bit8 (975~992) 18 983,
3443 11:35:17.681262 TX Bit1 (982~1001) 20 991, Bit9 (975~991) 17 983,
3444 11:35:17.687729 TX Bit2 (980~999) 20 989, Bit10 (978~995) 18 986,
3445 11:35:17.690691 TX Bit3 (978~997) 20 987, Bit11 (978~995) 18 986,
3446 11:35:17.697315 TX Bit4 (983~1000) 18 991, Bit12 (979~994) 16 986,
3447 11:35:17.700968 TX Bit5 (984~1001) 18 992, Bit13 (979~996) 18 987,
3448 11:35:17.704598 TX Bit6 (983~1001) 19 992, Bit14 (978~995) 18 986,
3449 11:35:17.710046 TX Bit7 (983~1000) 18 991, Bit15 (972~989) 18 980,
3450 11:35:17.710122
3451 11:35:17.710181 Write Rank1 MR14 =0xc
3452 11:35:17.720092
3453 11:35:17.723915 CH=1, VrefRange= 0, VrefLevel = 12
3454 11:35:17.726748 TX Bit0 (984~1002) 19 993, Bit8 (974~993) 20 983,
3455 11:35:17.730115 TX Bit1 (982~1001) 20 991, Bit9 (974~992) 19 983,
3456 11:35:17.736579 TX Bit2 (980~999) 20 989, Bit10 (977~996) 20 986,
3457 11:35:17.740291 TX Bit3 (977~997) 21 987, Bit11 (978~996) 19 987,
3458 11:35:17.746750 TX Bit4 (982~1001) 20 991, Bit12 (978~996) 19 987,
3459 11:35:17.749772 TX Bit5 (984~1002) 19 993, Bit13 (979~997) 19 988,
3460 11:35:17.753327 TX Bit6 (982~1001) 20 991, Bit14 (978~996) 19 987,
3461 11:35:17.759653 TX Bit7 (983~1001) 19 992, Bit15 (971~990) 20 980,
3462 11:35:17.759728
3463 11:35:17.759787 Write Rank1 MR14 =0xe
3464 11:35:17.769529
3465 11:35:17.772702 CH=1, VrefRange= 0, VrefLevel = 14
3466 11:35:17.776259 TX Bit0 (984~1003) 20 993, Bit8 (974~993) 20 983,
3467 11:35:17.779840 TX Bit1 (982~1002) 21 992, Bit9 (974~992) 19 983,
3468 11:35:17.786313 TX Bit2 (980~1000) 21 990, Bit10 (977~996) 20 986,
3469 11:35:17.789717 TX Bit3 (977~998) 22 987, Bit11 (978~997) 20 987,
3470 11:35:17.795913 TX Bit4 (982~1002) 21 992, Bit12 (978~996) 19 987,
3471 11:35:17.799186 TX Bit5 (984~1002) 19 993, Bit13 (978~998) 21 988,
3472 11:35:17.802790 TX Bit6 (982~1002) 21 992, Bit14 (978~996) 19 987,
3473 11:35:17.809088 TX Bit7 (982~1001) 20 991, Bit15 (971~991) 21 981,
3474 11:35:17.809165
3475 11:35:17.809223 Write Rank1 MR14 =0x10
3476 11:35:17.819271
3477 11:35:17.822672 CH=1, VrefRange= 0, VrefLevel = 16
3478 11:35:17.826352 TX Bit0 (984~1004) 21 994, Bit8 (973~994) 22 983,
3479 11:35:17.829079 TX Bit1 (982~1003) 22 992, Bit9 (974~993) 20 983,
3480 11:35:17.835580 TX Bit2 (980~1000) 21 990, Bit10 (977~997) 21 987,
3481 11:35:17.839069 TX Bit3 (977~998) 22 987, Bit11 (977~998) 22 987,
3482 11:35:17.845441 TX Bit4 (981~1002) 22 991, Bit12 (978~997) 20 987,
3483 11:35:17.848827 TX Bit5 (984~1003) 20 993, Bit13 (978~999) 22 988,
3484 11:35:17.852429 TX Bit6 (982~1002) 21 992, Bit14 (978~997) 20 987,
3485 11:35:17.858806 TX Bit7 (982~1002) 21 992, Bit15 (971~991) 21 981,
3486 11:35:17.858888
3487 11:35:17.858948 Write Rank1 MR14 =0x12
3488 11:35:17.869008
3489 11:35:17.872004 CH=1, VrefRange= 0, VrefLevel = 18
3490 11:35:17.875416 TX Bit0 (984~1004) 21 994, Bit8 (973~994) 22 983,
3491 11:35:17.878542 TX Bit1 (982~1003) 22 992, Bit9 (974~993) 20 983,
3492 11:35:17.885557 TX Bit2 (980~1000) 21 990, Bit10 (977~997) 21 987,
3493 11:35:17.888437 TX Bit3 (977~998) 22 987, Bit11 (977~998) 22 987,
3494 11:35:17.894932 TX Bit4 (981~1002) 22 991, Bit12 (978~997) 20 987,
3495 11:35:17.898313 TX Bit5 (984~1003) 20 993, Bit13 (978~999) 22 988,
3496 11:35:17.901740 TX Bit6 (982~1002) 21 992, Bit14 (978~997) 20 987,
3497 11:35:17.908524 TX Bit7 (982~1002) 21 992, Bit15 (971~991) 21 981,
3498 11:35:17.908601
3499 11:35:17.908660 Write Rank1 MR14 =0x14
3500 11:35:17.918976
3501 11:35:17.922079 CH=1, VrefRange= 0, VrefLevel = 20
3502 11:35:17.925972 TX Bit0 (983~1005) 23 994, Bit8 (972~995) 24 983,
3503 11:35:17.928937 TX Bit1 (981~1004) 24 992, Bit9 (973~993) 21 983,
3504 11:35:17.935198 TX Bit2 (978~1001) 24 989, Bit10 (976~999) 24 987,
3505 11:35:17.938233 TX Bit3 (977~999) 23 988, Bit11 (977~999) 23 988,
3506 11:35:17.945158 TX Bit4 (981~1003) 23 992, Bit12 (977~999) 23 988,
3507 11:35:17.948362 TX Bit5 (983~1005) 23 994, Bit13 (977~999) 23 988,
3508 11:35:17.951740 TX Bit6 (981~1004) 24 992, Bit14 (977~999) 23 988,
3509 11:35:17.958315 TX Bit7 (981~1004) 24 992, Bit15 (971~992) 22 981,
3510 11:35:17.958394
3511 11:35:17.958452 Write Rank1 MR14 =0x16
3512 11:35:17.968639
3513 11:35:17.972118 CH=1, VrefRange= 0, VrefLevel = 22
3514 11:35:17.975220 TX Bit0 (983~1005) 23 994, Bit8 (972~995) 24 983,
3515 11:35:17.978562 TX Bit1 (981~1004) 24 992, Bit9 (973~993) 21 983,
3516 11:35:17.984915 TX Bit2 (979~1002) 24 990, Bit10 (976~999) 24 987,
3517 11:35:17.988729 TX Bit3 (977~999) 23 988, Bit11 (976~999) 24 987,
3518 11:35:17.995371 TX Bit4 (981~1004) 24 992, Bit12 (977~999) 23 988,
3519 11:35:17.997997 TX Bit5 (982~1005) 24 993, Bit13 (977~1000) 24 988,
3520 11:35:18.001831 TX Bit6 (980~1004) 25 992, Bit14 (977~999) 23 988,
3521 11:35:18.008289 TX Bit7 (981~1004) 24 992, Bit15 (970~993) 24 981,
3522 11:35:18.008368
3523 11:35:18.008427 Write Rank1 MR14 =0x18
3524 11:35:18.018788
3525 11:35:18.021989 CH=1, VrefRange= 0, VrefLevel = 24
3526 11:35:18.025955 TX Bit0 (983~1006) 24 994, Bit8 (972~996) 25 984,
3527 11:35:18.028840 TX Bit1 (980~1005) 26 992, Bit9 (973~994) 22 983,
3528 11:35:18.035480 TX Bit2 (978~1002) 25 990, Bit10 (976~999) 24 987,
3529 11:35:18.038696 TX Bit3 (976~1000) 25 988, Bit11 (976~1000) 25 988,
3530 11:35:18.044871 TX Bit4 (980~1005) 26 992, Bit12 (977~999) 23 988,
3531 11:35:18.048633 TX Bit5 (982~1005) 24 993, Bit13 (977~1000) 24 988,
3532 11:35:18.052121 TX Bit6 (980~1005) 26 992, Bit14 (976~999) 24 987,
3533 11:35:18.058255 TX Bit7 (981~1005) 25 993, Bit15 (970~993) 24 981,
3534 11:35:18.058334
3535 11:35:18.061748 Write Rank1 MR14 =0x1a
3536 11:35:18.068783
3537 11:35:18.072711 CH=1, VrefRange= 0, VrefLevel = 26
3538 11:35:18.075697 TX Bit0 (982~1006) 25 994, Bit8 (972~997) 26 984,
3539 11:35:18.079238 TX Bit1 (979~1005) 27 992, Bit9 (972~994) 23 983,
3540 11:35:18.085544 TX Bit2 (977~1003) 27 990, Bit10 (975~1000) 26 987,
3541 11:35:18.088684 TX Bit3 (976~1000) 25 988, Bit11 (976~1000) 25 988,
3542 11:35:18.095245 TX Bit4 (980~1005) 26 992, Bit12 (976~1000) 25 988,
3543 11:35:18.098783 TX Bit5 (982~1006) 25 994, Bit13 (977~1000) 24 988,
3544 11:35:18.104835 TX Bit6 (980~1005) 26 992, Bit14 (976~1000) 25 988,
3545 11:35:18.108319 TX Bit7 (980~1005) 26 992, Bit15 (970~993) 24 981,
3546 11:35:18.108435
3547 11:35:18.111334 Write Rank1 MR14 =0x1c
3548 11:35:18.119576
3549 11:35:18.123145 CH=1, VrefRange= 0, VrefLevel = 28
3550 11:35:18.125944 TX Bit0 (982~1006) 25 994, Bit8 (972~997) 26 984,
3551 11:35:18.129595 TX Bit1 (979~1005) 27 992, Bit9 (972~994) 23 983,
3552 11:35:18.136053 TX Bit2 (977~1004) 28 990, Bit10 (974~1000) 27 987,
3553 11:35:18.139236 TX Bit3 (976~1000) 25 988, Bit11 (976~1000) 25 988,
3554 11:35:18.145875 TX Bit4 (979~1006) 28 992, Bit12 (976~1000) 25 988,
3555 11:35:18.149309 TX Bit5 (982~1006) 25 994, Bit13 (976~1000) 25 988,
3556 11:35:18.155900 TX Bit6 (979~1005) 27 992, Bit14 (976~1000) 25 988,
3557 11:35:18.159208 TX Bit7 (980~1006) 27 993, Bit15 (970~994) 25 982,
3558 11:35:18.159285
3559 11:35:18.162107 Write Rank1 MR14 =0x1e
3560 11:35:18.170464
3561 11:35:18.173596 CH=1, VrefRange= 0, VrefLevel = 30
3562 11:35:18.176661 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3563 11:35:18.180152 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3564 11:35:18.186857 TX Bit2 (977~1003) 27 990, Bit10 (974~1000) 27 987,
3565 11:35:18.189927 TX Bit3 (976~1001) 26 988, Bit11 (976~1000) 25 988,
3566 11:35:18.196264 TX Bit4 (979~1006) 28 992, Bit12 (976~1000) 25 988,
3567 11:35:18.200131 TX Bit5 (981~1006) 26 993, Bit13 (977~1000) 24 988,
3568 11:35:18.206358 TX Bit6 (980~1006) 27 993, Bit14 (975~1000) 26 987,
3569 11:35:18.209381 TX Bit7 (979~1006) 28 992, Bit15 (970~994) 25 982,
3570 11:35:18.209456
3571 11:35:18.212852 Write Rank1 MR14 =0x20
3572 11:35:18.220920
3573 11:35:18.224328 CH=1, VrefRange= 0, VrefLevel = 32
3574 11:35:18.227461 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3575 11:35:18.230815 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3576 11:35:18.236940 TX Bit2 (977~1003) 27 990, Bit10 (974~1000) 27 987,
3577 11:35:18.240467 TX Bit3 (976~1001) 26 988, Bit11 (976~1000) 25 988,
3578 11:35:18.246724 TX Bit4 (979~1006) 28 992, Bit12 (976~1000) 25 988,
3579 11:35:18.250151 TX Bit5 (981~1006) 26 993, Bit13 (977~1000) 24 988,
3580 11:35:18.256730 TX Bit6 (980~1006) 27 993, Bit14 (975~1000) 26 987,
3581 11:35:18.260293 TX Bit7 (979~1006) 28 992, Bit15 (970~994) 25 982,
3582 11:35:18.260371
3583 11:35:18.263117 Write Rank1 MR14 =0x22
3584 11:35:18.271649
3585 11:35:18.275220 CH=1, VrefRange= 0, VrefLevel = 34
3586 11:35:18.278194 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3587 11:35:18.281333 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3588 11:35:18.287775 TX Bit2 (977~1003) 27 990, Bit10 (974~1000) 27 987,
3589 11:35:18.290939 TX Bit3 (976~1001) 26 988, Bit11 (976~1000) 25 988,
3590 11:35:18.297481 TX Bit4 (979~1006) 28 992, Bit12 (976~1000) 25 988,
3591 11:35:18.300686 TX Bit5 (981~1006) 26 993, Bit13 (977~1000) 24 988,
3592 11:35:18.307498 TX Bit6 (980~1006) 27 993, Bit14 (975~1000) 26 987,
3593 11:35:18.310563 TX Bit7 (979~1006) 28 992, Bit15 (970~994) 25 982,
3594 11:35:18.310639
3595 11:35:18.313747 Write Rank1 MR14 =0x24
3596 11:35:18.322213
3597 11:35:18.325526 CH=1, VrefRange= 0, VrefLevel = 36
3598 11:35:18.328760 TX Bit0 (982~1006) 25 994, Bit8 (972~996) 25 984,
3599 11:35:18.331928 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3600 11:35:18.338127 TX Bit2 (977~1003) 27 990, Bit10 (974~1000) 27 987,
3601 11:35:18.341515 TX Bit3 (976~1001) 26 988, Bit11 (976~1000) 25 988,
3602 11:35:18.348544 TX Bit4 (979~1006) 28 992, Bit12 (976~1000) 25 988,
3603 11:35:18.351808 TX Bit5 (981~1006) 26 993, Bit13 (977~1000) 24 988,
3604 11:35:18.358003 TX Bit6 (980~1006) 27 993, Bit14 (975~1000) 26 987,
3605 11:35:18.361639 TX Bit7 (979~1006) 28 992, Bit15 (970~994) 25 982,
3606 11:35:18.361719
3607 11:35:18.361778
3608 11:35:18.364641 TX Vref found, early break! 387< 395
3609 11:35:18.371302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3610 11:35:18.371384 u1DelayCellOfst[0]=7 cells (6 PI)
3611 11:35:18.374482 u1DelayCellOfst[1]=6 cells (5 PI)
3612 11:35:18.378324 u1DelayCellOfst[2]=2 cells (2 PI)
3613 11:35:18.381237 u1DelayCellOfst[3]=0 cells (0 PI)
3614 11:35:18.384970 u1DelayCellOfst[4]=5 cells (4 PI)
3615 11:35:18.387681 u1DelayCellOfst[5]=6 cells (5 PI)
3616 11:35:18.390930 u1DelayCellOfst[6]=6 cells (5 PI)
3617 11:35:18.394204 u1DelayCellOfst[7]=5 cells (4 PI)
3618 11:35:18.398016 Byte0, DQ PI dly=988, DQM PI dly= 991
3619 11:35:18.400895 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3620 11:35:18.400973
3621 11:35:18.407103 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3622 11:35:18.407184
3623 11:35:18.410714 u1DelayCellOfst[8]=2 cells (2 PI)
3624 11:35:18.410793 u1DelayCellOfst[9]=1 cells (1 PI)
3625 11:35:18.413936 u1DelayCellOfst[10]=6 cells (5 PI)
3626 11:35:18.417044 u1DelayCellOfst[11]=7 cells (6 PI)
3627 11:35:18.420163 u1DelayCellOfst[12]=7 cells (6 PI)
3628 11:35:18.424186 u1DelayCellOfst[13]=7 cells (6 PI)
3629 11:35:18.427205 u1DelayCellOfst[14]=6 cells (5 PI)
3630 11:35:18.429986 u1DelayCellOfst[15]=0 cells (0 PI)
3631 11:35:18.433587 Byte1, DQ PI dly=982, DQM PI dly= 985
3632 11:35:18.440529 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3633 11:35:18.440643
3634 11:35:18.443361 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3635 11:35:18.443461
3636 11:35:18.446607 Write Rank1 MR14 =0x1e
3637 11:35:18.446713
3638 11:35:18.446804 Final TX Range 0 Vref 30
3639 11:35:18.446916
3640 11:35:18.453071 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3641 11:35:18.453145
3642 11:35:18.459691 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3643 11:35:18.466657 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3644 11:35:18.476773 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3645 11:35:18.476953 Write Rank1 MR3 =0xb0
3646 11:35:18.480247 DramC Write-DBI on
3647 11:35:18.480332 ==
3648 11:35:18.483157 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3649 11:35:18.486290 fsp= 1, odt_onoff= 1, Byte mode= 0
3650 11:35:18.486360 ==
3651 11:35:18.492318 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3652 11:35:18.492396
3653 11:35:18.495916 Begin, DQ Scan Range 705~769
3654 11:35:18.495994
3655 11:35:18.496053
3656 11:35:18.496108 TX Vref Scan disable
3657 11:35:18.499182 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3658 11:35:18.502360 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3659 11:35:18.505590 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3660 11:35:18.509263 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3661 11:35:18.512191 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3662 11:35:18.518851 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3663 11:35:18.521822 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3664 11:35:18.525246 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3665 11:35:18.528713 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3666 11:35:18.531664 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3667 11:35:18.535315 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3668 11:35:18.538274 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3669 11:35:18.541958 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3670 11:35:18.544883 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3671 11:35:18.548514 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3672 11:35:18.551717 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3673 11:35:18.554801 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3674 11:35:18.558499 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3675 11:35:18.561613 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3676 11:35:18.570861 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3677 11:35:18.574245 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3678 11:35:18.577187 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3679 11:35:18.580778 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3680 11:35:18.584705 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3681 11:35:18.587376 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3682 11:35:18.590563 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3683 11:35:18.593812 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3684 11:35:18.597530 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3685 11:35:18.600367 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3686 11:35:18.603988 Byte0, DQ PI dly=737, DQM PI dly= 737
3687 11:35:18.609977 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3688 11:35:18.610102
3689 11:35:18.613280 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3690 11:35:18.613367
3691 11:35:18.616991 Byte1, DQ PI dly=728, DQM PI dly= 728
3692 11:35:18.619736 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3693 11:35:18.619813
3694 11:35:18.626472 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3695 11:35:18.626553
3696 11:35:18.633132 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3697 11:35:18.639844 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3698 11:35:18.646032 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3699 11:35:18.649317 wait MRW command Rank1 MR3 =0x30 fired (1)
3700 11:35:18.652755 Write Rank1 MR3 =0x30
3701 11:35:18.652831 DramC Write-DBI off
3702 11:35:18.652922
3703 11:35:18.656139 [DATLAT]
3704 11:35:18.659147 Freq=1600, CH1 RK1, use_rxtx_scan=0
3705 11:35:18.659223
3706 11:35:18.659282 DATLAT Default: 0x10
3707 11:35:18.662855 7, 0xFFFF, sum=0
3708 11:35:18.662932 8, 0xFFFF, sum=0
3709 11:35:18.665754 9, 0xFFFF, sum=0
3710 11:35:18.665834 10, 0xFFFF, sum=0
3711 11:35:18.668878 11, 0xFFFF, sum=0
3712 11:35:18.668956 12, 0xFFFF, sum=0
3713 11:35:18.672851 13, 0xFFFF, sum=0
3714 11:35:18.672928 14, 0x0, sum=1
3715 11:35:18.675902 15, 0x0, sum=2
3716 11:35:18.675978 16, 0x0, sum=3
3717 11:35:18.676039 17, 0x0, sum=4
3718 11:35:18.682207 pattern=2 first_step=14 total pass=5 best_step=16
3719 11:35:18.682284 ==
3720 11:35:18.685353 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3721 11:35:18.689014 fsp= 1, odt_onoff= 1, Byte mode= 0
3722 11:35:18.689089 ==
3723 11:35:18.695642 Start DQ dly to find pass range UseTestEngine =1
3724 11:35:18.698784 x-axis: bit #, y-axis: DQ dly (-127~63)
3725 11:35:18.698864 RX Vref Scan = 0
3726 11:35:18.702242 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3727 11:35:18.705120 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3728 11:35:18.708368 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3729 11:35:18.711649 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3730 11:35:18.715863 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3731 11:35:18.718153 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3732 11:35:18.721980 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3733 11:35:18.722135 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3734 11:35:18.724588 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3735 11:35:18.728450 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3736 11:35:18.731943 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3737 11:35:18.734622 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3738 11:35:18.737751 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3739 11:35:18.741365 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3740 11:35:18.744446 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3741 11:35:18.747545 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3742 11:35:18.747618 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3743 11:35:18.751389 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3744 11:35:18.754241 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3745 11:35:18.757967 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3746 11:35:18.761204 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3747 11:35:18.764151 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3748 11:35:18.767475 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3749 11:35:18.770849 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3750 11:35:18.770937 -2, [0] xxxxxxxx xxxxxxxo [MSB]
3751 11:35:18.773935 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3752 11:35:18.777727 0, [0] xxxoxxxx xxxxxxxo [MSB]
3753 11:35:18.780369 1, [0] xxxoxxxx ooxxxxxo [MSB]
3754 11:35:18.783873 2, [0] xoooxxxx ooxxxxxo [MSB]
3755 11:35:18.787040 3, [0] xooooxxx ooxxxxxo [MSB]
3756 11:35:18.787126 4, [0] xooooxxo oooxxxxo [MSB]
3757 11:35:18.790206 5, [0] ooooooxo ooooxxxo [MSB]
3758 11:35:18.793364 6, [0] ooooooxo ooooxooo [MSB]
3759 11:35:18.797758 33, [0] oooxoooo ooooooox [MSB]
3760 11:35:18.801838 34, [0] oooxoooo ooooooox [MSB]
3761 11:35:18.804676 35, [0] oooxoooo xxooooox [MSB]
3762 11:35:18.807773 36, [0] ooxxoooo xxooooox [MSB]
3763 11:35:18.811472 37, [0] ooxxoooo xxooooox [MSB]
3764 11:35:18.814175 38, [0] oxxxoooo xxxoooox [MSB]
3765 11:35:18.817880 39, [0] xxxxxoox xxxxxxox [MSB]
3766 11:35:18.818016 40, [0] xxxxxoox xxxxxxxx [MSB]
3767 11:35:18.821072 41, [0] xxxxxxox xxxxxxxx [MSB]
3768 11:35:18.824167 42, [0] xxxxxxxx xxxxxxxx [MSB]
3769 11:35:18.827437 iDelay=42, Bit 0, Center 21 (5 ~ 38) 34
3770 11:35:18.830921 iDelay=42, Bit 1, Center 19 (2 ~ 37) 36
3771 11:35:18.833869 iDelay=42, Bit 2, Center 18 (2 ~ 35) 34
3772 11:35:18.840728 iDelay=42, Bit 3, Center 15 (-1 ~ 32) 34
3773 11:35:18.843731 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36
3774 11:35:18.847309 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3775 11:35:18.850420 iDelay=42, Bit 6, Center 24 (7 ~ 41) 35
3776 11:35:18.853665 iDelay=42, Bit 7, Center 21 (4 ~ 38) 35
3777 11:35:18.856806 iDelay=42, Bit 8, Center 17 (1 ~ 34) 34
3778 11:35:18.860227 iDelay=42, Bit 9, Center 17 (1 ~ 34) 34
3779 11:35:18.863545 iDelay=42, Bit 10, Center 20 (4 ~ 37) 34
3780 11:35:18.866926 iDelay=42, Bit 11, Center 21 (5 ~ 38) 34
3781 11:35:18.870293 iDelay=42, Bit 12, Center 22 (7 ~ 38) 32
3782 11:35:18.873515 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33
3783 11:35:18.879812 iDelay=42, Bit 14, Center 22 (6 ~ 39) 34
3784 11:35:18.883666 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35
3785 11:35:18.883760 ==
3786 11:35:18.886462 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3787 11:35:18.889869 fsp= 1, odt_onoff= 1, Byte mode= 0
3788 11:35:18.889978 ==
3789 11:35:18.893350 DQS Delay:
3790 11:35:18.893433 DQS0 = 0, DQS1 = 0
3791 11:35:18.893492 DQM Delay:
3792 11:35:18.896572 DQM0 = 20, DQM1 = 19
3793 11:35:18.896659 DQ Delay:
3794 11:35:18.899346 DQ0 =21, DQ1 =19, DQ2 =18, DQ3 =15
3795 11:35:18.902494 DQ4 =20, DQ5 =22, DQ6 =24, DQ7 =21
3796 11:35:18.905844 DQ8 =17, DQ9 =17, DQ10 =20, DQ11 =21
3797 11:35:18.909101 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =15
3798 11:35:18.909178
3799 11:35:18.909235
3800 11:35:18.909287
3801 11:35:18.912376 [DramC_TX_OE_Calibration] TA2
3802 11:35:18.915563 Original DQ_B0 (3 6) =30, OEN = 27
3803 11:35:18.918887 Original DQ_B1 (3 6) =30, OEN = 27
3804 11:35:18.922586 23, 0x0, End_B0=23 End_B1=23
3805 11:35:18.926171 24, 0x0, End_B0=24 End_B1=24
3806 11:35:18.928946 25, 0x0, End_B0=25 End_B1=25
3807 11:35:18.929022 26, 0x0, End_B0=26 End_B1=26
3808 11:35:18.932210 27, 0x0, End_B0=27 End_B1=27
3809 11:35:18.936537 28, 0x0, End_B0=28 End_B1=28
3810 11:35:18.938507 29, 0x0, End_B0=29 End_B1=29
3811 11:35:18.938582 30, 0x0, End_B0=30 End_B1=30
3812 11:35:18.942682 31, 0xFFFF, End_B0=30 End_B1=30
3813 11:35:18.948447 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3814 11:35:18.954753 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3815 11:35:18.954834
3816 11:35:18.954893
3817 11:35:18.954947 Write Rank1 MR23 =0x3f
3818 11:35:18.958689 [DQSOSC]
3819 11:35:18.964821 [DQSOSCAuto] RK1, (LSB)MR18= 0xb4b4, (MSB)MR19= 0x202, tDQSOscB0 = 455 ps tDQSOscB1 = 455 ps
3820 11:35:18.971282 CH1_RK1: MR19=0x202, MR18=0xB4B4, DQSOSC=455, MR23=63, INC=11, DEC=17
3821 11:35:18.974549 Write Rank1 MR23 =0x3f
3822 11:35:18.974635 [DQSOSC]
3823 11:35:18.980981 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0x202, tDQSOscB0 = 454 ps tDQSOscB1 = 454 ps
3824 11:35:18.984413 CH1 RK1: MR19=202, MR18=B5B5
3825 11:35:18.987877 [RxdqsGatingPostProcess] freq 1600
3826 11:35:18.994124 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3827 11:35:18.994200 Rank: 0
3828 11:35:18.997917 best DQS0 dly(2T, 0.5T) = (2, 6)
3829 11:35:19.001136 best DQS1 dly(2T, 0.5T) = (2, 6)
3830 11:35:19.004186 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3831 11:35:19.007658 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3832 11:35:19.007951 Rank: 1
3833 11:35:19.011181 best DQS0 dly(2T, 0.5T) = (2, 6)
3834 11:35:19.013979 best DQS1 dly(2T, 0.5T) = (2, 6)
3835 11:35:19.017373 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3836 11:35:19.020857 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3837 11:35:19.023855 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3838 11:35:19.027599 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3839 11:35:19.033713 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3840 11:35:19.034149
3841 11:35:19.034423
3842 11:35:19.036649 [Calibration Summary] Freqency 1600
3843 11:35:19.036725 CH 0, Rank 0
3844 11:35:19.036784 All Pass.
3845 11:35:19.040052
3846 11:35:19.040129 CH 0, Rank 1
3847 11:35:19.040205 All Pass.
3848 11:35:19.040274
3849 11:35:19.043434 CH 1, Rank 0
3850 11:35:19.043512 All Pass.
3851 11:35:19.043571
3852 11:35:19.043625 CH 1, Rank 1
3853 11:35:19.046893 All Pass.
3854 11:35:19.046968
3855 11:35:19.054173 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3856 11:35:19.060413 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3857 11:35:19.066490 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3858 11:35:19.066567 Write Rank0 MR3 =0xb0
3859 11:35:19.073323 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3860 11:35:19.083265 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3861 11:35:19.089784 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3862 11:35:19.089883 Write Rank1 MR3 =0xb0
3863 11:35:19.095961 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3864 11:35:19.102899 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3865 11:35:19.112674 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3866 11:35:19.112771 Write Rank0 MR3 =0xb0
3867 11:35:19.118956 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3868 11:35:19.125777 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3869 11:35:19.132677 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3870 11:35:19.135474 Write Rank1 MR3 =0xb0
3871 11:35:19.139276 DramC Write-DBI on
3872 11:35:19.142656 [GetDramInforAfterCalByMRR] Vendor 6.
3873 11:35:19.145265 [GetDramInforAfterCalByMRR] Revision 505.
3874 11:35:19.145340 MR8 1111
3875 11:35:19.149069 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3876 11:35:19.151865 MR8 1111
3877 11:35:19.155067 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3878 11:35:19.155212 MR8 1111
3879 11:35:19.161636 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3880 11:35:19.161759 MR8 1111
3881 11:35:19.168662 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3882 11:35:19.175201 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3883 11:35:19.178337 Write Rank0 MR13 =0xd0
3884 11:35:19.181740 Write Rank1 MR13 =0xd0
3885 11:35:19.181850 Write Rank0 MR13 =0xd0
3886 11:35:19.184580 Write Rank1 MR13 =0xd0
3887 11:35:19.187810 Save calibration result to emmc
3888 11:35:19.187908
3889 11:35:19.187969
3890 11:35:19.191478 [DramcModeReg_Check] Freq_1600, FSP_1
3891 11:35:19.191564 FSP_1, CH_0, RK0
3892 11:35:19.195065 Write Rank0 MR13 =0xd8
3893 11:35:19.198202 MR12 = 0x5e (global = 0x5e) match
3894 11:35:19.201206 MR14 = 0x20 (global = 0x20) match
3895 11:35:19.201300 FSP_1, CH_0, RK1
3896 11:35:19.204334 Write Rank1 MR13 =0xd8
3897 11:35:19.207817 MR12 = 0x5e (global = 0x5e) match
3898 11:35:19.210871 MR14 = 0x1c (global = 0x1c) match
3899 11:35:19.210947 FSP_1, CH_1, RK0
3900 11:35:19.213979 Write Rank0 MR13 =0xd8
3901 11:35:19.217293 MR12 = 0x5e (global = 0x5e) match
3902 11:35:19.220967 MR14 = 0x1c (global = 0x1c) match
3903 11:35:19.223966 FSP_1, CH_1, RK1
3904 11:35:19.224043 Write Rank1 MR13 =0xd8
3905 11:35:19.227266 MR12 = 0x60 (global = 0x60) match
3906 11:35:19.230451 MR14 = 0x1e (global = 0x1e) match
3907 11:35:19.230528
3908 11:35:19.233853 [MEM_TEST] 02: After DFS, before run time config
3909 11:35:19.246514 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3910 11:35:19.246598
3911 11:35:19.246662 [TA2_TEST]
3912 11:35:19.246719 === TA2 HW
3913 11:35:19.249578 TA2 PAT: XTALK
3914 11:35:19.252629 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3915 11:35:19.259051 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3916 11:35:19.262580 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3917 11:35:19.269174 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3918 11:35:19.269253
3919 11:35:19.269311
3920 11:35:19.269366 Settings after calibration
3921 11:35:19.269419
3922 11:35:19.272331 [DramcRunTimeConfig]
3923 11:35:19.275327 TransferPLLToSPMControl - MODE SW PHYPLL
3924 11:35:19.279290 TX_TRACKING: ON
3925 11:35:19.279368 RX_TRACKING: ON
3926 11:35:19.279428 HW_GATING: ON
3927 11:35:19.282754 HW_GATING DBG: OFF
3928 11:35:19.282833 ddr_geometry:1
3929 11:35:19.285524 ddr_geometry:1
3930 11:35:19.285656 ddr_geometry:1
3931 11:35:19.288567 ddr_geometry:1
3932 11:35:19.288683 ddr_geometry:1
3933 11:35:19.292156 ddr_geometry:1
3934 11:35:19.292234 ddr_geometry:1
3935 11:35:19.292292 ddr_geometry:1
3936 11:35:19.296348 High Freq DUMMY_READ_FOR_TRACKING: ON
3937 11:35:19.298598 ZQCS_ENABLE_LP4: OFF
3938 11:35:19.302352 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3939 11:35:19.306048 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3940 11:35:19.308630 SPM_CONTROL_AFTERK: ON
3941 11:35:19.309087 IMPEDANCE_TRACKING: ON
3942 11:35:19.312116 TEMP_SENSOR: ON
3943 11:35:19.312569 PER_BANK_REFRESH: ON
3944 11:35:19.315003 HW_SAVE_FOR_SR: ON
3945 11:35:19.318500 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 11:35:19.322071 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3947 11:35:19.325298 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3948 11:35:19.325642 Read ODT Tracking: ON
3949 11:35:19.328386 =========================
3950 11:35:19.328730
3951 11:35:19.329019 [TA2_TEST]
3952 11:35:19.331854 === TA2 HW
3953 11:35:19.334717 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3954 11:35:19.340900 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3955 11:35:19.344575 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3956 11:35:19.350748 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3957 11:35:19.350887
3958 11:35:19.354377 [MEM_TEST] 03: After run time config
3959 11:35:19.364020 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3960 11:35:19.366969 [complex_mem_test] start addr:0x40024000, len:131072
3961 11:35:19.572232 1st complex R/W mem test pass
3962 11:35:19.578780 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3963 11:35:19.581911 sync preloader write leveling
3964 11:35:19.584996 sync preloader cbt_mr12
3965 11:35:19.588235 sync preloader cbt_clk_dly
3966 11:35:19.588632 sync preloader cbt_cmd_dly
3967 11:35:19.591708 sync preloader cbt_cs
3968 11:35:19.594764 sync preloader cbt_ca_perbit_delay
3969 11:35:19.598069 sync preloader clk_delay
3970 11:35:19.598437 sync preloader dqs_delay
3971 11:35:19.601270 sync preloader u1Gating2T_Save
3972 11:35:19.604695 sync preloader u1Gating05T_Save
3973 11:35:19.607860 sync preloader u1Gatingfine_tune_Save
3974 11:35:19.611206 sync preloader u1Gatingucpass_count_Save
3975 11:35:19.614384 sync preloader u1TxWindowPerbitVref_Save
3976 11:35:19.617702 sync preloader u1TxCenter_min_Save
3977 11:35:19.620979 sync preloader u1TxCenter_max_Save
3978 11:35:19.624725 sync preloader u1Txwin_center_Save
3979 11:35:19.627590 sync preloader u1Txfirst_pass_Save
3980 11:35:19.630643 sync preloader u1Txlast_pass_Save
3981 11:35:19.634129 sync preloader u1RxDatlat_Save
3982 11:35:19.637411 sync preloader u1RxWinPerbitVref_Save
3983 11:35:19.640494 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3984 11:35:19.643974 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3985 11:35:19.646859 sync preloader delay_cell_unit
3986 11:35:19.653706 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3987 11:35:19.656841 sync preloader write leveling
3988 11:35:19.660646 sync preloader cbt_mr12
3989 11:35:19.660976 sync preloader cbt_clk_dly
3990 11:35:19.663929 sync preloader cbt_cmd_dly
3991 11:35:19.666912 sync preloader cbt_cs
3992 11:35:19.670043 sync preloader cbt_ca_perbit_delay
3993 11:35:19.670376 sync preloader clk_delay
3994 11:35:19.673608 sync preloader dqs_delay
3995 11:35:19.677011 sync preloader u1Gating2T_Save
3996 11:35:19.680205 sync preloader u1Gating05T_Save
3997 11:35:19.683252 sync preloader u1Gatingfine_tune_Save
3998 11:35:19.686825 sync preloader u1Gatingucpass_count_Save
3999 11:35:19.689939 sync preloader u1TxWindowPerbitVref_Save
4000 11:35:19.693110 sync preloader u1TxCenter_min_Save
4001 11:35:19.696416 sync preloader u1TxCenter_max_Save
4002 11:35:19.700024 sync preloader u1Txwin_center_Save
4003 11:35:19.702592 sync preloader u1Txfirst_pass_Save
4004 11:35:19.706003 sync preloader u1Txlast_pass_Save
4005 11:35:19.709294 sync preloader u1RxDatlat_Save
4006 11:35:19.712788 sync preloader u1RxWinPerbitVref_Save
4007 11:35:19.715381 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4008 11:35:19.719360 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4009 11:35:19.722787 sync preloader delay_cell_unit
4010 11:35:19.729031 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4011 11:35:19.732334 sync preloader write leveling
4012 11:35:19.732482 sync preloader cbt_mr12
4013 11:35:19.735654 sync preloader cbt_clk_dly
4014 11:35:19.739149 sync preloader cbt_cmd_dly
4015 11:35:19.742482 sync preloader cbt_cs
4016 11:35:19.745495 sync preloader cbt_ca_perbit_delay
4017 11:35:19.745674 sync preloader clk_delay
4018 11:35:19.748314 sync preloader dqs_delay
4019 11:35:19.751931 sync preloader u1Gating2T_Save
4020 11:35:19.755167 sync preloader u1Gating05T_Save
4021 11:35:19.758175 sync preloader u1Gatingfine_tune_Save
4022 11:35:19.761519 sync preloader u1Gatingucpass_count_Save
4023 11:35:19.765123 sync preloader u1TxWindowPerbitVref_Save
4024 11:35:19.768180 sync preloader u1TxCenter_min_Save
4025 11:35:19.771597 sync preloader u1TxCenter_max_Save
4026 11:35:19.774663 sync preloader u1Txwin_center_Save
4027 11:35:19.778250 sync preloader u1Txfirst_pass_Save
4028 11:35:19.781037 sync preloader u1Txlast_pass_Save
4029 11:35:19.781112 sync preloader u1RxDatlat_Save
4030 11:35:19.784586 sync preloader u1RxWinPerbitVref_Save
4031 11:35:19.791115 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4032 11:35:19.794214 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4033 11:35:19.797973 sync preloader delay_cell_unit
4034 11:35:19.801537 just_for_test_dump_coreboot_params dump all params
4035 11:35:19.804769 dump source = 0x0
4036 11:35:19.804918 dump params frequency:1600
4037 11:35:19.807773 dump params rank number:2
4038 11:35:19.807930
4039 11:35:19.811093 dump params write leveling
4040 11:35:19.814741 write leveling[0][0][0] = 0x20
4041 11:35:19.817786 write leveling[0][0][1] = 0x17
4042 11:35:19.817903 write leveling[0][1][0] = 0x20
4043 11:35:19.820745 write leveling[0][1][1] = 0x17
4044 11:35:19.824210 write leveling[1][0][0] = 0x24
4045 11:35:19.827207 write leveling[1][0][1] = 0x21
4046 11:35:19.830440 write leveling[1][1][0] = 0x21
4047 11:35:19.834339 write leveling[1][1][1] = 0x1d
4048 11:35:19.834505 dump params cbt_cs
4049 11:35:19.837279 cbt_cs[0][0] = 0x7
4050 11:35:19.837468 cbt_cs[0][1] = 0x7
4051 11:35:19.840607 cbt_cs[1][0] = 0xa
4052 11:35:19.840911 cbt_cs[1][1] = 0xa
4053 11:35:19.843773 dump params cbt_mr12
4054 11:35:19.844046 cbt_mr12[0][0] = 0x1e
4055 11:35:19.847044 cbt_mr12[0][1] = 0x1e
4056 11:35:19.850635 cbt_mr12[1][0] = 0x1e
4057 11:35:19.851105 cbt_mr12[1][1] = 0x20
4058 11:35:19.853345 dump params tx window
4059 11:35:19.857340 tx_center_min[0][0][0] = 986
4060 11:35:19.857713 tx_center_max[0][0][0] = 991
4061 11:35:19.860458 tx_center_min[0][0][1] = 977
4062 11:35:19.864019 tx_center_max[0][0][1] = 984
4063 11:35:19.866359 tx_center_min[0][1][0] = 986
4064 11:35:19.870442 tx_center_max[0][1][0] = 993
4065 11:35:19.870797 tx_center_min[0][1][1] = 977
4066 11:35:19.873723 tx_center_max[0][1][1] = 985
4067 11:35:19.876561 tx_center_min[1][0][0] = 992
4068 11:35:19.879998 tx_center_max[1][0][0] = 997
4069 11:35:19.883098 tx_center_min[1][0][1] = 987
4070 11:35:19.883613 tx_center_max[1][0][1] = 993
4071 11:35:19.886076 tx_center_min[1][1][0] = 988
4072 11:35:19.889313 tx_center_max[1][1][0] = 994
4073 11:35:19.893298 tx_center_min[1][1][1] = 982
4074 11:35:19.896490 tx_center_max[1][1][1] = 988
4075 11:35:19.896883 dump params tx window
4076 11:35:19.899385 tx_win_center[0][0][0] = 991
4077 11:35:19.902540 tx_first_pass[0][0][0] = 979
4078 11:35:19.905783 tx_last_pass[0][0][0] = 1003
4079 11:35:19.905988 tx_win_center[0][0][1] = 990
4080 11:35:19.909423 tx_first_pass[0][0][1] = 978
4081 11:35:19.913149 tx_last_pass[0][0][1] = 1002
4082 11:35:19.915282 tx_win_center[0][0][2] = 991
4083 11:35:19.918761 tx_first_pass[0][0][2] = 980
4084 11:35:19.918902 tx_last_pass[0][0][2] = 1003
4085 11:35:19.921892 tx_win_center[0][0][3] = 986
4086 11:35:19.925017 tx_first_pass[0][0][3] = 974
4087 11:35:19.928589 tx_last_pass[0][0][3] = 998
4088 11:35:19.931556 tx_win_center[0][0][4] = 989
4089 11:35:19.931648 tx_first_pass[0][0][4] = 977
4090 11:35:19.935184 tx_last_pass[0][0][4] = 1002
4091 11:35:19.938402 tx_win_center[0][0][5] = 987
4092 11:35:19.941579 tx_first_pass[0][0][5] = 976
4093 11:35:19.944850 tx_last_pass[0][0][5] = 999
4094 11:35:19.944935 tx_win_center[0][0][6] = 988
4095 11:35:19.948030 tx_first_pass[0][0][6] = 976
4096 11:35:19.951933 tx_last_pass[0][0][6] = 1000
4097 11:35:19.954951 tx_win_center[0][0][7] = 990
4098 11:35:19.958443 tx_first_pass[0][0][7] = 978
4099 11:35:19.958516 tx_last_pass[0][0][7] = 1002
4100 11:35:19.961599 tx_win_center[0][0][8] = 977
4101 11:35:19.964890 tx_first_pass[0][0][8] = 966
4102 11:35:19.967994 tx_last_pass[0][0][8] = 989
4103 11:35:19.971394 tx_win_center[0][0][9] = 978
4104 11:35:19.971469 tx_first_pass[0][0][9] = 967
4105 11:35:19.974519 tx_last_pass[0][0][9] = 990
4106 11:35:19.977607 tx_win_center[0][0][10] = 984
4107 11:35:19.980879 tx_first_pass[0][0][10] = 973
4108 11:35:19.984968 tx_last_pass[0][0][10] = 996
4109 11:35:19.985042 tx_win_center[0][0][11] = 978
4110 11:35:19.987670 tx_first_pass[0][0][11] = 967
4111 11:35:19.990775 tx_last_pass[0][0][11] = 990
4112 11:35:19.994210 tx_win_center[0][0][12] = 979
4113 11:35:19.997132 tx_first_pass[0][0][12] = 968
4114 11:35:19.997205 tx_last_pass[0][0][12] = 991
4115 11:35:20.000712 tx_win_center[0][0][13] = 979
4116 11:35:20.004291 tx_first_pass[0][0][13] = 968
4117 11:35:20.007383 tx_last_pass[0][0][13] = 991
4118 11:35:20.010570 tx_win_center[0][0][14] = 981
4119 11:35:20.014031 tx_first_pass[0][0][14] = 969
4120 11:35:20.014107 tx_last_pass[0][0][14] = 993
4121 11:35:20.017397 tx_win_center[0][0][15] = 983
4122 11:35:20.020369 tx_first_pass[0][0][15] = 972
4123 11:35:20.023776 tx_last_pass[0][0][15] = 995
4124 11:35:20.026907 tx_win_center[0][1][0] = 993
4125 11:35:20.026985 tx_first_pass[0][1][0] = 981
4126 11:35:20.030686 tx_last_pass[0][1][0] = 1005
4127 11:35:20.033351 tx_win_center[0][1][1] = 991
4128 11:35:20.037122 tx_first_pass[0][1][1] = 979
4129 11:35:20.040636 tx_last_pass[0][1][1] = 1004
4130 11:35:20.040718 tx_win_center[0][1][2] = 992
4131 11:35:20.043863 tx_first_pass[0][1][2] = 980
4132 11:35:20.046698 tx_last_pass[0][1][2] = 1004
4133 11:35:20.050075 tx_win_center[0][1][3] = 986
4134 11:35:20.053224 tx_first_pass[0][1][3] = 974
4135 11:35:20.053295 tx_last_pass[0][1][3] = 998
4136 11:35:20.056723 tx_win_center[0][1][4] = 990
4137 11:35:20.059956 tx_first_pass[0][1][4] = 978
4138 11:35:20.063593 tx_last_pass[0][1][4] = 1003
4139 11:35:20.066639 tx_win_center[0][1][5] = 988
4140 11:35:20.066709 tx_first_pass[0][1][5] = 976
4141 11:35:20.069569 tx_last_pass[0][1][5] = 1000
4142 11:35:20.072989 tx_win_center[0][1][6] = 989
4143 11:35:20.076536 tx_first_pass[0][1][6] = 977
4144 11:35:20.076630 tx_last_pass[0][1][6] = 1001
4145 11:35:20.079810 tx_win_center[0][1][7] = 990
4146 11:35:20.083296 tx_first_pass[0][1][7] = 978
4147 11:35:20.086018 tx_last_pass[0][1][7] = 1003
4148 11:35:20.089423 tx_win_center[0][1][8] = 977
4149 11:35:20.089500 tx_first_pass[0][1][8] = 966
4150 11:35:20.092710 tx_last_pass[0][1][8] = 989
4151 11:35:20.095589 tx_win_center[0][1][9] = 979
4152 11:35:20.099308 tx_first_pass[0][1][9] = 969
4153 11:35:20.102077 tx_last_pass[0][1][9] = 990
4154 11:35:20.102155 tx_win_center[0][1][10] = 985
4155 11:35:20.105849 tx_first_pass[0][1][10] = 973
4156 11:35:20.109440 tx_last_pass[0][1][10] = 997
4157 11:35:20.112053 tx_win_center[0][1][11] = 978
4158 11:35:20.115794 tx_first_pass[0][1][11] = 967
4159 11:35:20.118887 tx_last_pass[0][1][11] = 990
4160 11:35:20.118964 tx_win_center[0][1][12] = 979
4161 11:35:20.122060 tx_first_pass[0][1][12] = 968
4162 11:35:20.125122 tx_last_pass[0][1][12] = 991
4163 11:35:20.128494 tx_win_center[0][1][13] = 979
4164 11:35:20.132272 tx_first_pass[0][1][13] = 968
4165 11:35:20.132349 tx_last_pass[0][1][13] = 991
4166 11:35:20.134952 tx_win_center[0][1][14] = 981
4167 11:35:20.138542 tx_first_pass[0][1][14] = 970
4168 11:35:20.141521 tx_last_pass[0][1][14] = 992
4169 11:35:20.145188 tx_win_center[0][1][15] = 984
4170 11:35:20.148144 tx_first_pass[0][1][15] = 973
4171 11:35:20.148221 tx_last_pass[0][1][15] = 996
4172 11:35:20.151609 tx_win_center[1][0][0] = 997
4173 11:35:20.154702 tx_first_pass[1][0][0] = 984
4174 11:35:20.158527 tx_last_pass[1][0][0] = 1010
4175 11:35:20.158607 tx_win_center[1][0][1] = 996
4176 11:35:20.161390 tx_first_pass[1][0][1] = 984
4177 11:35:20.164393 tx_last_pass[1][0][1] = 1009
4178 11:35:20.168270 tx_win_center[1][0][2] = 994
4179 11:35:20.172162 tx_first_pass[1][0][2] = 982
4180 11:35:20.172238 tx_last_pass[1][0][2] = 1006
4181 11:35:20.174196 tx_win_center[1][0][3] = 992
4182 11:35:20.177725 tx_first_pass[1][0][3] = 979
4183 11:35:20.180951 tx_last_pass[1][0][3] = 1005
4184 11:35:20.184658 tx_win_center[1][0][4] = 996
4185 11:35:20.184754 tx_first_pass[1][0][4] = 983
4186 11:35:20.187660 tx_last_pass[1][0][4] = 1009
4187 11:35:20.191171 tx_win_center[1][0][5] = 997
4188 11:35:20.194310 tx_first_pass[1][0][5] = 985
4189 11:35:20.197612 tx_last_pass[1][0][5] = 1009
4190 11:35:20.197712 tx_win_center[1][0][6] = 996
4191 11:35:20.200640 tx_first_pass[1][0][6] = 984
4192 11:35:20.203970 tx_last_pass[1][0][6] = 1009
4193 11:35:20.207178 tx_win_center[1][0][7] = 995
4194 11:35:20.210729 tx_first_pass[1][0][7] = 983
4195 11:35:20.210825 tx_last_pass[1][0][7] = 1008
4196 11:35:20.214603 tx_win_center[1][0][8] = 989
4197 11:35:20.217355 tx_first_pass[1][0][8] = 978
4198 11:35:20.220872 tx_last_pass[1][0][8] = 1001
4199 11:35:20.223980 tx_win_center[1][0][9] = 989
4200 11:35:20.224112 tx_first_pass[1][0][9] = 978
4201 11:35:20.227331 tx_last_pass[1][0][9] = 1001
4202 11:35:20.230472 tx_win_center[1][0][10] = 992
4203 11:35:20.234002 tx_first_pass[1][0][10] = 981
4204 11:35:20.236806 tx_last_pass[1][0][10] = 1004
4205 11:35:20.236918 tx_win_center[1][0][11] = 993
4206 11:35:20.240973 tx_first_pass[1][0][11] = 982
4207 11:35:20.244025 tx_last_pass[1][0][11] = 1004
4208 11:35:20.247013 tx_win_center[1][0][12] = 993
4209 11:35:20.249971 tx_first_pass[1][0][12] = 983
4210 11:35:20.253398 tx_last_pass[1][0][12] = 1004
4211 11:35:20.253480 tx_win_center[1][0][13] = 993
4212 11:35:20.256938 tx_first_pass[1][0][13] = 983
4213 11:35:20.260085 tx_last_pass[1][0][13] = 1004
4214 11:35:20.263314 tx_win_center[1][0][14] = 991
4215 11:35:20.266309 tx_first_pass[1][0][14] = 980
4216 11:35:20.266400 tx_last_pass[1][0][14] = 1003
4217 11:35:20.269710 tx_win_center[1][0][15] = 987
4218 11:35:20.272990 tx_first_pass[1][0][15] = 976
4219 11:35:20.276656 tx_last_pass[1][0][15] = 999
4220 11:35:20.279720 tx_win_center[1][1][0] = 994
4221 11:35:20.283208 tx_first_pass[1][1][0] = 982
4222 11:35:20.283305 tx_last_pass[1][1][0] = 1006
4223 11:35:20.286000 tx_win_center[1][1][1] = 993
4224 11:35:20.289611 tx_first_pass[1][1][1] = 980
4225 11:35:20.292869 tx_last_pass[1][1][1] = 1006
4226 11:35:20.292966 tx_win_center[1][1][2] = 990
4227 11:35:20.296444 tx_first_pass[1][1][2] = 977
4228 11:35:20.299849 tx_last_pass[1][1][2] = 1003
4229 11:35:20.302340 tx_win_center[1][1][3] = 988
4230 11:35:20.305705 tx_first_pass[1][1][3] = 976
4231 11:35:20.305799 tx_last_pass[1][1][3] = 1001
4232 11:35:20.309374 tx_win_center[1][1][4] = 992
4233 11:35:20.312799 tx_first_pass[1][1][4] = 979
4234 11:35:20.316267 tx_last_pass[1][1][4] = 1006
4235 11:35:20.319440 tx_win_center[1][1][5] = 993
4236 11:35:20.319511 tx_first_pass[1][1][5] = 981
4237 11:35:20.322225 tx_last_pass[1][1][5] = 1006
4238 11:35:20.325954 tx_win_center[1][1][6] = 993
4239 11:35:20.329254 tx_first_pass[1][1][6] = 980
4240 11:35:20.332488 tx_last_pass[1][1][6] = 1006
4241 11:35:20.332557 tx_win_center[1][1][7] = 992
4242 11:35:20.335699 tx_first_pass[1][1][7] = 979
4243 11:35:20.338649 tx_last_pass[1][1][7] = 1006
4244 11:35:20.341930 tx_win_center[1][1][8] = 984
4245 11:35:20.345677 tx_first_pass[1][1][8] = 972
4246 11:35:20.345743 tx_last_pass[1][1][8] = 996
4247 11:35:20.348833 tx_win_center[1][1][9] = 983
4248 11:35:20.352074 tx_first_pass[1][1][9] = 971
4249 11:35:20.355297 tx_last_pass[1][1][9] = 995
4250 11:35:20.355365 tx_win_center[1][1][10] = 987
4251 11:35:20.358512 tx_first_pass[1][1][10] = 974
4252 11:35:20.361881 tx_last_pass[1][1][10] = 1000
4253 11:35:20.365192 tx_win_center[1][1][11] = 988
4254 11:35:20.368493 tx_first_pass[1][1][11] = 976
4255 11:35:20.371660 tx_last_pass[1][1][11] = 1000
4256 11:35:20.371728 tx_win_center[1][1][12] = 988
4257 11:35:20.374947 tx_first_pass[1][1][12] = 976
4258 11:35:20.377963 tx_last_pass[1][1][12] = 1000
4259 11:35:20.381801 tx_win_center[1][1][13] = 988
4260 11:35:20.385171 tx_first_pass[1][1][13] = 977
4261 11:35:20.388846 tx_last_pass[1][1][13] = 1000
4262 11:35:20.388982 tx_win_center[1][1][14] = 987
4263 11:35:20.391801 tx_first_pass[1][1][14] = 975
4264 11:35:20.395191 tx_last_pass[1][1][14] = 1000
4265 11:35:20.398117 tx_win_center[1][1][15] = 982
4266 11:35:20.401413 tx_first_pass[1][1][15] = 970
4267 11:35:20.401489 tx_last_pass[1][1][15] = 994
4268 11:35:20.405281 dump params rx window
4269 11:35:20.408005 rx_firspass[0][0][0] = 5
4270 11:35:20.408070 rx_lastpass[0][0][0] = 39
4271 11:35:20.411426 rx_firspass[0][0][1] = 5
4272 11:35:20.414767 rx_lastpass[0][0][1] = 36
4273 11:35:20.417526 rx_firspass[0][0][2] = 6
4274 11:35:20.417602 rx_lastpass[0][0][2] = 37
4275 11:35:20.421033 rx_firspass[0][0][3] = 0
4276 11:35:20.424836 rx_lastpass[0][0][3] = 30
4277 11:35:20.424910 rx_firspass[0][0][4] = 5
4278 11:35:20.427557 rx_lastpass[0][0][4] = 36
4279 11:35:20.430869 rx_firspass[0][0][5] = 1
4280 11:35:20.434026 rx_lastpass[0][0][5] = 33
4281 11:35:20.434121 rx_firspass[0][0][6] = 5
4282 11:35:20.437794 rx_lastpass[0][0][6] = 33
4283 11:35:20.440951 rx_firspass[0][0][7] = 7
4284 11:35:20.441027 rx_lastpass[0][0][7] = 36
4285 11:35:20.444363 rx_firspass[0][0][8] = 0
4286 11:35:20.447798 rx_lastpass[0][0][8] = 31
4287 11:35:20.447877 rx_firspass[0][0][9] = 1
4288 11:35:20.450728 rx_lastpass[0][0][9] = 32
4289 11:35:20.454093 rx_firspass[0][0][10] = 9
4290 11:35:20.457141 rx_lastpass[0][0][10] = 39
4291 11:35:20.457209 rx_firspass[0][0][11] = 2
4292 11:35:20.460468 rx_lastpass[0][0][11] = 30
4293 11:35:20.463626 rx_firspass[0][0][12] = 1
4294 11:35:20.467262 rx_lastpass[0][0][12] = 34
4295 11:35:20.467357 rx_firspass[0][0][13] = 2
4296 11:35:20.470166 rx_lastpass[0][0][13] = 33
4297 11:35:20.474088 rx_firspass[0][0][14] = 3
4298 11:35:20.477023 rx_lastpass[0][0][14] = 36
4299 11:35:20.477116 rx_firspass[0][0][15] = 7
4300 11:35:20.479875 rx_lastpass[0][0][15] = 37
4301 11:35:20.483748 rx_firspass[0][1][0] = 4
4302 11:35:20.483816 rx_lastpass[0][1][0] = 38
4303 11:35:20.487229 rx_firspass[0][1][1] = 3
4304 11:35:20.490434 rx_lastpass[0][1][1] = 39
4305 11:35:20.493296 rx_firspass[0][1][2] = 4
4306 11:35:20.493370 rx_lastpass[0][1][2] = 40
4307 11:35:20.496922 rx_firspass[0][1][3] = -3
4308 11:35:20.500080 rx_lastpass[0][1][3] = 31
4309 11:35:20.500145 rx_firspass[0][1][4] = 5
4310 11:35:20.502955 rx_lastpass[0][1][4] = 38
4311 11:35:20.506195 rx_firspass[0][1][5] = 0
4312 11:35:20.510254 rx_lastpass[0][1][5] = 32
4313 11:35:20.510324 rx_firspass[0][1][6] = 1
4314 11:35:20.513049 rx_lastpass[0][1][6] = 35
4315 11:35:20.516513 rx_firspass[0][1][7] = 4
4316 11:35:20.516578 rx_lastpass[0][1][7] = 37
4317 11:35:20.519651 rx_firspass[0][1][8] = 0
4318 11:35:20.522595 rx_lastpass[0][1][8] = 34
4319 11:35:20.525878 rx_firspass[0][1][9] = 2
4320 11:35:20.526013 rx_lastpass[0][1][9] = 35
4321 11:35:20.529418 rx_firspass[0][1][10] = 9
4322 11:35:20.532437 rx_lastpass[0][1][10] = 42
4323 11:35:20.532532 rx_firspass[0][1][11] = 0
4324 11:35:20.536158 rx_lastpass[0][1][11] = 33
4325 11:35:20.539051 rx_firspass[0][1][12] = 3
4326 11:35:20.542973 rx_lastpass[0][1][12] = 36
4327 11:35:20.543088 rx_firspass[0][1][13] = 3
4328 11:35:20.546011 rx_lastpass[0][1][13] = 36
4329 11:35:20.549012 rx_firspass[0][1][14] = 5
4330 11:35:20.552470 rx_lastpass[0][1][14] = 37
4331 11:35:20.552540 rx_firspass[0][1][15] = 6
4332 11:35:20.555818 rx_lastpass[0][1][15] = 40
4333 11:35:20.559104 rx_firspass[1][0][0] = 5
4334 11:35:20.559196 rx_lastpass[1][0][0] = 39
4335 11:35:20.562305 rx_firspass[1][0][1] = 3
4336 11:35:20.565453 rx_lastpass[1][0][1] = 36
4337 11:35:20.568807 rx_firspass[1][0][2] = 4
4338 11:35:20.568913 rx_lastpass[1][0][2] = 36
4339 11:35:20.572380 rx_firspass[1][0][3] = -1
4340 11:35:20.575784 rx_lastpass[1][0][3] = 33
4341 11:35:20.575885 rx_firspass[1][0][4] = 4
4342 11:35:20.579122 rx_lastpass[1][0][4] = 36
4343 11:35:20.581880 rx_firspass[1][0][5] = 6
4344 11:35:20.585506 rx_lastpass[1][0][5] = 38
4345 11:35:20.585602 rx_firspass[1][0][6] = 10
4346 11:35:20.588645 rx_lastpass[1][0][6] = 39
4347 11:35:20.591920 rx_firspass[1][0][7] = 5
4348 11:35:20.591992 rx_lastpass[1][0][7] = 37
4349 11:35:20.594907 rx_firspass[1][0][8] = 0
4350 11:35:20.598141 rx_lastpass[1][0][8] = 33
4351 11:35:20.602305 rx_firspass[1][0][9] = 2
4352 11:35:20.602387 rx_lastpass[1][0][9] = 32
4353 11:35:20.605005 rx_firspass[1][0][10] = 6
4354 11:35:20.608423 rx_lastpass[1][0][10] = 36
4355 11:35:20.608521 rx_firspass[1][0][11] = 7
4356 11:35:20.611325 rx_lastpass[1][0][11] = 36
4357 11:35:20.615043 rx_firspass[1][0][12] = 5
4358 11:35:20.617986 rx_lastpass[1][0][12] = 37
4359 11:35:20.618100 rx_firspass[1][0][13] = 6
4360 11:35:20.621417 rx_lastpass[1][0][13] = 36
4361 11:35:20.624971 rx_firspass[1][0][14] = 7
4362 11:35:20.627961 rx_lastpass[1][0][14] = 37
4363 11:35:20.628057 rx_firspass[1][0][15] = 0
4364 11:35:20.631287 rx_lastpass[1][0][15] = 29
4365 11:35:20.634236 rx_firspass[1][1][0] = 5
4366 11:35:20.637541 rx_lastpass[1][1][0] = 38
4367 11:35:20.637607 rx_firspass[1][1][1] = 2
4368 11:35:20.640795 rx_lastpass[1][1][1] = 37
4369 11:35:20.644338 rx_firspass[1][1][2] = 2
4370 11:35:20.644427 rx_lastpass[1][1][2] = 35
4371 11:35:20.647660 rx_firspass[1][1][3] = -1
4372 11:35:20.650795 rx_lastpass[1][1][3] = 32
4373 11:35:20.654256 rx_firspass[1][1][4] = 3
4374 11:35:20.654333 rx_lastpass[1][1][4] = 38
4375 11:35:20.657314 rx_firspass[1][1][5] = 5
4376 11:35:20.660795 rx_lastpass[1][1][5] = 40
4377 11:35:20.660888 rx_firspass[1][1][6] = 7
4378 11:35:20.663770 rx_lastpass[1][1][6] = 41
4379 11:35:20.666992 rx_firspass[1][1][7] = 4
4380 11:35:20.667084 rx_lastpass[1][1][7] = 38
4381 11:35:20.670738 rx_firspass[1][1][8] = 1
4382 11:35:20.673657 rx_lastpass[1][1][8] = 34
4383 11:35:20.677165 rx_firspass[1][1][9] = 1
4384 11:35:20.677253 rx_lastpass[1][1][9] = 34
4385 11:35:20.679998 rx_firspass[1][1][10] = 4
4386 11:35:20.683572 rx_lastpass[1][1][10] = 37
4387 11:35:20.687410 rx_firspass[1][1][11] = 5
4388 11:35:20.687484 rx_lastpass[1][1][11] = 38
4389 11:35:20.690122 rx_firspass[1][1][12] = 7
4390 11:35:20.693482 rx_lastpass[1][1][12] = 38
4391 11:35:20.693554 rx_firspass[1][1][13] = 6
4392 11:35:20.696506 rx_lastpass[1][1][13] = 38
4393 11:35:20.700355 rx_firspass[1][1][14] = 6
4394 11:35:20.703609 rx_lastpass[1][1][14] = 39
4395 11:35:20.703674 rx_firspass[1][1][15] = -2
4396 11:35:20.706548 rx_lastpass[1][1][15] = 32
4397 11:35:20.710701 dump params clk_delay
4398 11:35:20.710770 clk_delay[0] = 1
4399 11:35:20.713357 clk_delay[1] = 0
4400 11:35:20.713419 dump params dqs_delay
4401 11:35:20.716474 dqs_delay[0][0] = 0
4402 11:35:20.716538 dqs_delay[0][1] = 0
4403 11:35:20.719830 dqs_delay[1][0] = -1
4404 11:35:20.719925 dqs_delay[1][1] = 0
4405 11:35:20.722990 dump params delay_cell_unit = 744
4406 11:35:20.726784 dump source = 0x0
4407 11:35:20.729690 dump params frequency:1200
4408 11:35:20.729769 dump params rank number:2
4409 11:35:20.729826
4410 11:35:20.732809 dump params write leveling
4411 11:35:20.736069 write leveling[0][0][0] = 0x0
4412 11:35:20.739790 write leveling[0][0][1] = 0x0
4413 11:35:20.743203 write leveling[0][1][0] = 0x0
4414 11:35:20.743277 write leveling[0][1][1] = 0x0
4415 11:35:20.746128 write leveling[1][0][0] = 0x0
4416 11:35:20.749254 write leveling[1][0][1] = 0x0
4417 11:35:20.752796 write leveling[1][1][0] = 0x0
4418 11:35:20.756035 write leveling[1][1][1] = 0x0
4419 11:35:20.756108 dump params cbt_cs
4420 11:35:20.759142 cbt_cs[0][0] = 0x0
4421 11:35:20.759244 cbt_cs[0][1] = 0x0
4422 11:35:20.762774 cbt_cs[1][0] = 0x0
4423 11:35:20.762862 cbt_cs[1][1] = 0x0
4424 11:35:20.765685 dump params cbt_mr12
4425 11:35:20.765790 cbt_mr12[0][0] = 0x0
4426 11:35:20.769053 cbt_mr12[0][1] = 0x0
4427 11:35:20.772610 cbt_mr12[1][0] = 0x0
4428 11:35:20.772685 cbt_mr12[1][1] = 0x0
4429 11:35:20.776069 dump params tx window
4430 11:35:20.778962 tx_center_min[0][0][0] = 0
4431 11:35:20.779037 tx_center_max[0][0][0] = 0
4432 11:35:20.782365 tx_center_min[0][0][1] = 0
4433 11:35:20.785589 tx_center_max[0][0][1] = 0
4434 11:35:20.788408 tx_center_min[0][1][0] = 0
4435 11:35:20.788484 tx_center_max[0][1][0] = 0
4436 11:35:20.791787 tx_center_min[0][1][1] = 0
4437 11:35:20.794995 tx_center_max[0][1][1] = 0
4438 11:35:20.798606 tx_center_min[1][0][0] = 0
4439 11:35:20.798691 tx_center_max[1][0][0] = 0
4440 11:35:20.802479 tx_center_min[1][0][1] = 0
4441 11:35:20.804947 tx_center_max[1][0][1] = 0
4442 11:35:20.808019 tx_center_min[1][1][0] = 0
4443 11:35:20.808084 tx_center_max[1][1][0] = 0
4444 11:35:20.811916 tx_center_min[1][1][1] = 0
4445 11:35:20.814536 tx_center_max[1][1][1] = 0
4446 11:35:20.814641 dump params tx window
4447 11:35:20.817805 tx_win_center[0][0][0] = 0
4448 11:35:20.821561 tx_first_pass[0][0][0] = 0
4449 11:35:20.824561 tx_last_pass[0][0][0] = 0
4450 11:35:20.824656 tx_win_center[0][0][1] = 0
4451 11:35:20.827674 tx_first_pass[0][0][1] = 0
4452 11:35:20.830978 tx_last_pass[0][0][1] = 0
4453 11:35:20.834318 tx_win_center[0][0][2] = 0
4454 11:35:20.834410 tx_first_pass[0][0][2] = 0
4455 11:35:20.837703 tx_last_pass[0][0][2] = 0
4456 11:35:20.840861 tx_win_center[0][0][3] = 0
4457 11:35:20.844313 tx_first_pass[0][0][3] = 0
4458 11:35:20.844403 tx_last_pass[0][0][3] = 0
4459 11:35:20.847488 tx_win_center[0][0][4] = 0
4460 11:35:20.850903 tx_first_pass[0][0][4] = 0
4461 11:35:20.853698 tx_last_pass[0][0][4] = 0
4462 11:35:20.853798 tx_win_center[0][0][5] = 0
4463 11:35:20.857377 tx_first_pass[0][0][5] = 0
4464 11:35:20.860658 tx_last_pass[0][0][5] = 0
4465 11:35:20.860747 tx_win_center[0][0][6] = 0
4466 11:35:20.863979 tx_first_pass[0][0][6] = 0
4467 11:35:20.867003 tx_last_pass[0][0][6] = 0
4468 11:35:20.870204 tx_win_center[0][0][7] = 0
4469 11:35:20.870318 tx_first_pass[0][0][7] = 0
4470 11:35:20.873288 tx_last_pass[0][0][7] = 0
4471 11:35:20.876642 tx_win_center[0][0][8] = 0
4472 11:35:20.880106 tx_first_pass[0][0][8] = 0
4473 11:35:20.880181 tx_last_pass[0][0][8] = 0
4474 11:35:20.883625 tx_win_center[0][0][9] = 0
4475 11:35:20.886558 tx_first_pass[0][0][9] = 0
4476 11:35:20.889941 tx_last_pass[0][0][9] = 0
4477 11:35:20.890028 tx_win_center[0][0][10] = 0
4478 11:35:20.893040 tx_first_pass[0][0][10] = 0
4479 11:35:20.896191 tx_last_pass[0][0][10] = 0
4480 11:35:20.899744 tx_win_center[0][0][11] = 0
4481 11:35:20.899841 tx_first_pass[0][0][11] = 0
4482 11:35:20.903353 tx_last_pass[0][0][11] = 0
4483 11:35:20.906567 tx_win_center[0][0][12] = 0
4484 11:35:20.909806 tx_first_pass[0][0][12] = 0
4485 11:35:20.909925 tx_last_pass[0][0][12] = 0
4486 11:35:20.912815 tx_win_center[0][0][13] = 0
4487 11:35:20.916343 tx_first_pass[0][0][13] = 0
4488 11:35:20.919473 tx_last_pass[0][0][13] = 0
4489 11:35:20.922984 tx_win_center[0][0][14] = 0
4490 11:35:20.923063 tx_first_pass[0][0][14] = 0
4491 11:35:20.925896 tx_last_pass[0][0][14] = 0
4492 11:35:20.929053 tx_win_center[0][0][15] = 0
4493 11:35:20.932132 tx_first_pass[0][0][15] = 0
4494 11:35:20.932261 tx_last_pass[0][0][15] = 0
4495 11:35:20.935445 tx_win_center[0][1][0] = 0
4496 11:35:20.939621 tx_first_pass[0][1][0] = 0
4497 11:35:20.942538 tx_last_pass[0][1][0] = 0
4498 11:35:20.942629 tx_win_center[0][1][1] = 0
4499 11:35:20.945720 tx_first_pass[0][1][1] = 0
4500 11:35:20.948690 tx_last_pass[0][1][1] = 0
4501 11:35:20.952159 tx_win_center[0][1][2] = 0
4502 11:35:20.952241 tx_first_pass[0][1][2] = 0
4503 11:35:20.955288 tx_last_pass[0][1][2] = 0
4504 11:35:20.958582 tx_win_center[0][1][3] = 0
4505 11:35:20.962223 tx_first_pass[0][1][3] = 0
4506 11:35:20.962303 tx_last_pass[0][1][3] = 0
4507 11:35:20.965430 tx_win_center[0][1][4] = 0
4508 11:35:20.968696 tx_first_pass[0][1][4] = 0
4509 11:35:20.968796 tx_last_pass[0][1][4] = 0
4510 11:35:20.972185 tx_win_center[0][1][5] = 0
4511 11:35:20.975182 tx_first_pass[0][1][5] = 0
4512 11:35:20.978524 tx_last_pass[0][1][5] = 0
4513 11:35:20.978605 tx_win_center[0][1][6] = 0
4514 11:35:20.981898 tx_first_pass[0][1][6] = 0
4515 11:35:20.984888 tx_last_pass[0][1][6] = 0
4516 11:35:20.988543 tx_win_center[0][1][7] = 0
4517 11:35:20.988632 tx_first_pass[0][1][7] = 0
4518 11:35:20.991734 tx_last_pass[0][1][7] = 0
4519 11:35:20.994581 tx_win_center[0][1][8] = 0
4520 11:35:20.997974 tx_first_pass[0][1][8] = 0
4521 11:35:20.998114 tx_last_pass[0][1][8] = 0
4522 11:35:21.001029 tx_win_center[0][1][9] = 0
4523 11:35:21.004966 tx_first_pass[0][1][9] = 0
4524 11:35:21.005060 tx_last_pass[0][1][9] = 0
4525 11:35:21.008114 tx_win_center[0][1][10] = 0
4526 11:35:21.011395 tx_first_pass[0][1][10] = 0
4527 11:35:21.014527 tx_last_pass[0][1][10] = 0
4528 11:35:21.014622 tx_win_center[0][1][11] = 0
4529 11:35:21.017645 tx_first_pass[0][1][11] = 0
4530 11:35:21.020837 tx_last_pass[0][1][11] = 0
4531 11:35:21.024505 tx_win_center[0][1][12] = 0
4532 11:35:21.027581 tx_first_pass[0][1][12] = 0
4533 11:35:21.027663 tx_last_pass[0][1][12] = 0
4534 11:35:21.030772 tx_win_center[0][1][13] = 0
4535 11:35:21.034021 tx_first_pass[0][1][13] = 0
4536 11:35:21.037223 tx_last_pass[0][1][13] = 0
4537 11:35:21.037305 tx_win_center[0][1][14] = 0
4538 11:35:21.041056 tx_first_pass[0][1][14] = 0
4539 11:35:21.044138 tx_last_pass[0][1][14] = 0
4540 11:35:21.047147 tx_win_center[0][1][15] = 0
4541 11:35:21.047262 tx_first_pass[0][1][15] = 0
4542 11:35:21.050626 tx_last_pass[0][1][15] = 0
4543 11:35:21.054220 tx_win_center[1][0][0] = 0
4544 11:35:21.056826 tx_first_pass[1][0][0] = 0
4545 11:35:21.056906 tx_last_pass[1][0][0] = 0
4546 11:35:21.060151 tx_win_center[1][0][1] = 0
4547 11:35:21.063689 tx_first_pass[1][0][1] = 0
4548 11:35:21.069715 tx_last_pass[1][0][1] = 0
4549 11:35:21.069859 tx_win_center[1][0][2] = 0
4550 11:35:21.070151 tx_first_pass[1][0][2] = 0
4551 11:35:21.073636 tx_last_pass[1][0][2] = 0
4552 11:35:21.077186 tx_win_center[1][0][3] = 0
4553 11:35:21.077295 tx_first_pass[1][0][3] = 0
4554 11:35:21.080243 tx_last_pass[1][0][3] = 0
4555 11:35:21.083229 tx_win_center[1][0][4] = 0
4556 11:35:21.083344 tx_first_pass[1][0][4] = 0
4557 11:35:21.086392 tx_last_pass[1][0][4] = 0
4558 11:35:21.090549 tx_win_center[1][0][5] = 0
4559 11:35:21.093488 tx_first_pass[1][0][5] = 0
4560 11:35:21.093567 tx_last_pass[1][0][5] = 0
4561 11:35:21.096674 tx_win_center[1][0][6] = 0
4562 11:35:21.099766 tx_first_pass[1][0][6] = 0
4563 11:35:21.102907 tx_last_pass[1][0][6] = 0
4564 11:35:21.103050 tx_win_center[1][0][7] = 0
4565 11:35:21.106778 tx_first_pass[1][0][7] = 0
4566 11:35:21.109422 tx_last_pass[1][0][7] = 0
4567 11:35:21.112661 tx_win_center[1][0][8] = 0
4568 11:35:21.112766 tx_first_pass[1][0][8] = 0
4569 11:35:21.116141 tx_last_pass[1][0][8] = 0
4570 11:35:21.119093 tx_win_center[1][0][9] = 0
4571 11:35:21.122779 tx_first_pass[1][0][9] = 0
4572 11:35:21.122856 tx_last_pass[1][0][9] = 0
4573 11:35:21.125700 tx_win_center[1][0][10] = 0
4574 11:35:21.129110 tx_first_pass[1][0][10] = 0
4575 11:35:21.132535 tx_last_pass[1][0][10] = 0
4576 11:35:21.132611 tx_win_center[1][0][11] = 0
4577 11:35:21.136521 tx_first_pass[1][0][11] = 0
4578 11:35:21.138829 tx_last_pass[1][0][11] = 0
4579 11:35:21.142267 tx_win_center[1][0][12] = 0
4580 11:35:21.142347 tx_first_pass[1][0][12] = 0
4581 11:35:21.145945 tx_last_pass[1][0][12] = 0
4582 11:35:21.148795 tx_win_center[1][0][13] = 0
4583 11:35:21.152074 tx_first_pass[1][0][13] = 0
4584 11:35:21.152158 tx_last_pass[1][0][13] = 0
4585 11:35:21.155431 tx_win_center[1][0][14] = 0
4586 11:35:21.158404 tx_first_pass[1][0][14] = 0
4587 11:35:21.162185 tx_last_pass[1][0][14] = 0
4588 11:35:21.162269 tx_win_center[1][0][15] = 0
4589 11:35:21.165352 tx_first_pass[1][0][15] = 0
4590 11:35:21.168631 tx_last_pass[1][0][15] = 0
4591 11:35:21.172034 tx_win_center[1][1][0] = 0
4592 11:35:21.172112 tx_first_pass[1][1][0] = 0
4593 11:35:21.175510 tx_last_pass[1][1][0] = 0
4594 11:35:21.178455 tx_win_center[1][1][1] = 0
4595 11:35:21.181916 tx_first_pass[1][1][1] = 0
4596 11:35:21.181995 tx_last_pass[1][1][1] = 0
4597 11:35:21.185124 tx_win_center[1][1][2] = 0
4598 11:35:21.188277 tx_first_pass[1][1][2] = 0
4599 11:35:21.191877 tx_last_pass[1][1][2] = 0
4600 11:35:21.191954 tx_win_center[1][1][3] = 0
4601 11:35:21.194810 tx_first_pass[1][1][3] = 0
4602 11:35:21.198290 tx_last_pass[1][1][3] = 0
4603 11:35:21.201220 tx_win_center[1][1][4] = 0
4604 11:35:21.201296 tx_first_pass[1][1][4] = 0
4605 11:35:21.204703 tx_last_pass[1][1][4] = 0
4606 11:35:21.207790 tx_win_center[1][1][5] = 0
4607 11:35:21.207868 tx_first_pass[1][1][5] = 0
4608 11:35:21.210900 tx_last_pass[1][1][5] = 0
4609 11:35:21.214386 tx_win_center[1][1][6] = 0
4610 11:35:21.217770 tx_first_pass[1][1][6] = 0
4611 11:35:21.217847 tx_last_pass[1][1][6] = 0
4612 11:35:21.221357 tx_win_center[1][1][7] = 0
4613 11:35:21.224322 tx_first_pass[1][1][7] = 0
4614 11:35:21.227361 tx_last_pass[1][1][7] = 0
4615 11:35:21.227437 tx_win_center[1][1][8] = 0
4616 11:35:21.231170 tx_first_pass[1][1][8] = 0
4617 11:35:21.234163 tx_last_pass[1][1][8] = 0
4618 11:35:21.237118 tx_win_center[1][1][9] = 0
4619 11:35:21.237194 tx_first_pass[1][1][9] = 0
4620 11:35:21.240630 tx_last_pass[1][1][9] = 0
4621 11:35:21.243835 tx_win_center[1][1][10] = 0
4622 11:35:21.247385 tx_first_pass[1][1][10] = 0
4623 11:35:21.247462 tx_last_pass[1][1][10] = 0
4624 11:35:21.250330 tx_win_center[1][1][11] = 0
4625 11:35:21.253365 tx_first_pass[1][1][11] = 0
4626 11:35:21.257195 tx_last_pass[1][1][11] = 0
4627 11:35:21.257277 tx_win_center[1][1][12] = 0
4628 11:35:21.260072 tx_first_pass[1][1][12] = 0
4629 11:35:21.263240 tx_last_pass[1][1][12] = 0
4630 11:35:21.267076 tx_win_center[1][1][13] = 0
4631 11:35:21.267156 tx_first_pass[1][1][13] = 0
4632 11:35:21.270249 tx_last_pass[1][1][13] = 0
4633 11:35:21.273384 tx_win_center[1][1][14] = 0
4634 11:35:21.276662 tx_first_pass[1][1][14] = 0
4635 11:35:21.276740 tx_last_pass[1][1][14] = 0
4636 11:35:21.279894 tx_win_center[1][1][15] = 0
4637 11:35:21.283077 tx_first_pass[1][1][15] = 0
4638 11:35:21.286867 tx_last_pass[1][1][15] = 0
4639 11:35:21.286945 dump params rx window
4640 11:35:21.289955 rx_firspass[0][0][0] = 0
4641 11:35:21.293567 rx_lastpass[0][0][0] = 0
4642 11:35:21.293646 rx_firspass[0][0][1] = 0
4643 11:35:21.296842 rx_lastpass[0][0][1] = 0
4644 11:35:21.299765 rx_firspass[0][0][2] = 0
4645 11:35:21.302983 rx_lastpass[0][0][2] = 0
4646 11:35:21.303059 rx_firspass[0][0][3] = 0
4647 11:35:21.306413 rx_lastpass[0][0][3] = 0
4648 11:35:21.309348 rx_firspass[0][0][4] = 0
4649 11:35:21.309424 rx_lastpass[0][0][4] = 0
4650 11:35:21.312822 rx_firspass[0][0][5] = 0
4651 11:35:21.316719 rx_lastpass[0][0][5] = 0
4652 11:35:21.316796 rx_firspass[0][0][6] = 0
4653 11:35:21.319121 rx_lastpass[0][0][6] = 0
4654 11:35:21.322994 rx_firspass[0][0][7] = 0
4655 11:35:21.325967 rx_lastpass[0][0][7] = 0
4656 11:35:21.326087 rx_firspass[0][0][8] = 0
4657 11:35:21.330342 rx_lastpass[0][0][8] = 0
4658 11:35:21.332109 rx_firspass[0][0][9] = 0
4659 11:35:21.332185 rx_lastpass[0][0][9] = 0
4660 11:35:21.335664 rx_firspass[0][0][10] = 0
4661 11:35:21.339156 rx_lastpass[0][0][10] = 0
4662 11:35:21.339260 rx_firspass[0][0][11] = 0
4663 11:35:21.342550 rx_lastpass[0][0][11] = 0
4664 11:35:21.345551 rx_firspass[0][0][12] = 0
4665 11:35:21.349238 rx_lastpass[0][0][12] = 0
4666 11:35:21.349319 rx_firspass[0][0][13] = 0
4667 11:35:21.352457 rx_lastpass[0][0][13] = 0
4668 11:35:21.355595 rx_firspass[0][0][14] = 0
4669 11:35:21.355685 rx_lastpass[0][0][14] = 0
4670 11:35:21.358834 rx_firspass[0][0][15] = 0
4671 11:35:21.361817 rx_lastpass[0][0][15] = 0
4672 11:35:21.365270 rx_firspass[0][1][0] = 0
4673 11:35:21.365346 rx_lastpass[0][1][0] = 0
4674 11:35:21.368667 rx_firspass[0][1][1] = 0
4675 11:35:21.371696 rx_lastpass[0][1][1] = 0
4676 11:35:21.371773 rx_firspass[0][1][2] = 0
4677 11:35:21.375498 rx_lastpass[0][1][2] = 0
4678 11:35:21.378439 rx_firspass[0][1][3] = 0
4679 11:35:21.381775 rx_lastpass[0][1][3] = 0
4680 11:35:21.381850 rx_firspass[0][1][4] = 0
4681 11:35:21.385229 rx_lastpass[0][1][4] = 0
4682 11:35:21.388022 rx_firspass[0][1][5] = 0
4683 11:35:21.388097 rx_lastpass[0][1][5] = 0
4684 11:35:21.391871 rx_firspass[0][1][6] = 0
4685 11:35:21.394891 rx_lastpass[0][1][6] = 0
4686 11:35:21.394965 rx_firspass[0][1][7] = 0
4687 11:35:21.398251 rx_lastpass[0][1][7] = 0
4688 11:35:21.402164 rx_firspass[0][1][8] = 0
4689 11:35:21.402238 rx_lastpass[0][1][8] = 0
4690 11:35:21.404675 rx_firspass[0][1][9] = 0
4691 11:35:21.407634 rx_lastpass[0][1][9] = 0
4692 11:35:21.410939 rx_firspass[0][1][10] = 0
4693 11:35:21.411013 rx_lastpass[0][1][10] = 0
4694 11:35:21.414621 rx_firspass[0][1][11] = 0
4695 11:35:21.417965 rx_lastpass[0][1][11] = 0
4696 11:35:21.418072 rx_firspass[0][1][12] = 0
4697 11:35:21.421084 rx_lastpass[0][1][12] = 0
4698 11:35:21.424391 rx_firspass[0][1][13] = 0
4699 11:35:21.427359 rx_lastpass[0][1][13] = 0
4700 11:35:21.427433 rx_firspass[0][1][14] = 0
4701 11:35:21.430957 rx_lastpass[0][1][14] = 0
4702 11:35:21.434187 rx_firspass[0][1][15] = 0
4703 11:35:21.437841 rx_lastpass[0][1][15] = 0
4704 11:35:21.437941 rx_firspass[1][0][0] = 0
4705 11:35:21.441033 rx_lastpass[1][0][0] = 0
4706 11:35:21.444189 rx_firspass[1][0][1] = 0
4707 11:35:21.444263 rx_lastpass[1][0][1] = 0
4708 11:35:21.447867 rx_firspass[1][0][2] = 0
4709 11:35:21.450642 rx_lastpass[1][0][2] = 0
4710 11:35:21.450717 rx_firspass[1][0][3] = 0
4711 11:35:21.453842 rx_lastpass[1][0][3] = 0
4712 11:35:21.457038 rx_firspass[1][0][4] = 0
4713 11:35:21.460254 rx_lastpass[1][0][4] = 0
4714 11:35:21.460329 rx_firspass[1][0][5] = 0
4715 11:35:21.463395 rx_lastpass[1][0][5] = 0
4716 11:35:21.466935 rx_firspass[1][0][6] = 0
4717 11:35:21.467009 rx_lastpass[1][0][6] = 0
4718 11:35:21.470197 rx_firspass[1][0][7] = 0
4719 11:35:21.473578 rx_lastpass[1][0][7] = 0
4720 11:35:21.473653 rx_firspass[1][0][8] = 0
4721 11:35:21.477227 rx_lastpass[1][0][8] = 0
4722 11:35:21.479847 rx_firspass[1][0][9] = 0
4723 11:35:21.479945 rx_lastpass[1][0][9] = 0
4724 11:35:21.483032 rx_firspass[1][0][10] = 0
4725 11:35:21.486303 rx_lastpass[1][0][10] = 0
4726 11:35:21.489583 rx_firspass[1][0][11] = 0
4727 11:35:21.489657 rx_lastpass[1][0][11] = 0
4728 11:35:21.493379 rx_firspass[1][0][12] = 0
4729 11:35:21.496976 rx_lastpass[1][0][12] = 0
4730 11:35:21.499766 rx_firspass[1][0][13] = 0
4731 11:35:21.499841 rx_lastpass[1][0][13] = 0
4732 11:35:21.502684 rx_firspass[1][0][14] = 0
4733 11:35:21.506435 rx_lastpass[1][0][14] = 0
4734 11:35:21.506509 rx_firspass[1][0][15] = 0
4735 11:35:21.509658 rx_lastpass[1][0][15] = 0
4736 11:35:21.512686 rx_firspass[1][1][0] = 0
4737 11:35:21.515749 rx_lastpass[1][1][0] = 0
4738 11:35:21.515824 rx_firspass[1][1][1] = 0
4739 11:35:21.519745 rx_lastpass[1][1][1] = 0
4740 11:35:21.522701 rx_firspass[1][1][2] = 0
4741 11:35:21.522775 rx_lastpass[1][1][2] = 0
4742 11:35:21.526019 rx_firspass[1][1][3] = 0
4743 11:35:21.529575 rx_lastpass[1][1][3] = 0
4744 11:35:21.529649 rx_firspass[1][1][4] = 0
4745 11:35:21.532671 rx_lastpass[1][1][4] = 0
4746 11:35:21.535780 rx_firspass[1][1][5] = 0
4747 11:35:21.535855 rx_lastpass[1][1][5] = 0
4748 11:35:21.538894 rx_firspass[1][1][6] = 0
4749 11:35:21.542731 rx_lastpass[1][1][6] = 0
4750 11:35:21.546277 rx_firspass[1][1][7] = 0
4751 11:35:21.546351 rx_lastpass[1][1][7] = 0
4752 11:35:21.548965 rx_firspass[1][1][8] = 0
4753 11:35:21.552486 rx_lastpass[1][1][8] = 0
4754 11:35:21.552560 rx_firspass[1][1][9] = 0
4755 11:35:21.556026 rx_lastpass[1][1][9] = 0
4756 11:35:21.558790 rx_firspass[1][1][10] = 0
4757 11:35:21.558865 rx_lastpass[1][1][10] = 0
4758 11:35:21.561996 rx_firspass[1][1][11] = 0
4759 11:35:21.565361 rx_lastpass[1][1][11] = 0
4760 11:35:21.568395 rx_firspass[1][1][12] = 0
4761 11:35:21.568469 rx_lastpass[1][1][12] = 0
4762 11:35:21.571815 rx_firspass[1][1][13] = 0
4763 11:35:21.575121 rx_lastpass[1][1][13] = 0
4764 11:35:21.578950 rx_firspass[1][1][14] = 0
4765 11:35:21.579024 rx_lastpass[1][1][14] = 0
4766 11:35:21.582068 rx_firspass[1][1][15] = 0
4767 11:35:21.585123 rx_lastpass[1][1][15] = 0
4768 11:35:21.585196 dump params clk_delay
4769 11:35:21.587992 clk_delay[0] = 0
4770 11:35:21.588066 clk_delay[1] = 0
4771 11:35:21.591187 dump params dqs_delay
4772 11:35:21.591262 dqs_delay[0][0] = 0
4773 11:35:21.594631 dqs_delay[0][1] = 0
4774 11:35:21.597885 dqs_delay[1][0] = 0
4775 11:35:21.597960 dqs_delay[1][1] = 0
4776 11:35:21.601067 dump params delay_cell_unit = 744
4777 11:35:21.604938 dump source = 0x0
4778 11:35:21.605013 dump params frequency:800
4779 11:35:21.607989 dump params rank number:2
4780 11:35:21.608064
4781 11:35:21.611678 dump params write leveling
4782 11:35:21.614500 write leveling[0][0][0] = 0x0
4783 11:35:21.614576 write leveling[0][0][1] = 0x0
4784 11:35:21.617644 write leveling[0][1][0] = 0x0
4785 11:35:21.621328 write leveling[0][1][1] = 0x0
4786 11:35:21.624302 write leveling[1][0][0] = 0x0
4787 11:35:21.627582 write leveling[1][0][1] = 0x0
4788 11:35:21.627657 write leveling[1][1][0] = 0x0
4789 11:35:21.631275 write leveling[1][1][1] = 0x0
4790 11:35:21.634322 dump params cbt_cs
4791 11:35:21.634398 cbt_cs[0][0] = 0x0
4792 11:35:21.637450 cbt_cs[0][1] = 0x0
4793 11:35:21.637525 cbt_cs[1][0] = 0x0
4794 11:35:21.640609 cbt_cs[1][1] = 0x0
4795 11:35:21.640684 dump params cbt_mr12
4796 11:35:21.644189 cbt_mr12[0][0] = 0x0
4797 11:35:21.647061 cbt_mr12[0][1] = 0x0
4798 11:35:21.647135 cbt_mr12[1][0] = 0x0
4799 11:35:21.650484 cbt_mr12[1][1] = 0x0
4800 11:35:21.650558 dump params tx window
4801 11:35:21.653736 tx_center_min[0][0][0] = 0
4802 11:35:21.657001 tx_center_max[0][0][0] = 0
4803 11:35:21.660333 tx_center_min[0][0][1] = 0
4804 11:35:21.660419 tx_center_max[0][0][1] = 0
4805 11:35:21.663978 tx_center_min[0][1][0] = 0
4806 11:35:21.666768 tx_center_max[0][1][0] = 0
4807 11:35:21.671233 tx_center_min[0][1][1] = 0
4808 11:35:21.671309 tx_center_max[0][1][1] = 0
4809 11:35:21.673380 tx_center_min[1][0][0] = 0
4810 11:35:21.676690 tx_center_max[1][0][0] = 0
4811 11:35:21.680136 tx_center_min[1][0][1] = 0
4812 11:35:21.680212 tx_center_max[1][0][1] = 0
4813 11:35:21.683413 tx_center_min[1][1][0] = 0
4814 11:35:21.686512 tx_center_max[1][1][0] = 0
4815 11:35:21.689560 tx_center_min[1][1][1] = 0
4816 11:35:21.689636 tx_center_max[1][1][1] = 0
4817 11:35:21.693350 dump params tx window
4818 11:35:21.696552 tx_win_center[0][0][0] = 0
4819 11:35:21.699363 tx_first_pass[0][0][0] = 0
4820 11:35:21.699439 tx_last_pass[0][0][0] = 0
4821 11:35:21.702978 tx_win_center[0][0][1] = 0
4822 11:35:21.705907 tx_first_pass[0][0][1] = 0
4823 11:35:21.705982 tx_last_pass[0][0][1] = 0
4824 11:35:21.709582 tx_win_center[0][0][2] = 0
4825 11:35:21.712642 tx_first_pass[0][0][2] = 0
4826 11:35:21.715950 tx_last_pass[0][0][2] = 0
4827 11:35:21.716026 tx_win_center[0][0][3] = 0
4828 11:35:21.719500 tx_first_pass[0][0][3] = 0
4829 11:35:21.722521 tx_last_pass[0][0][3] = 0
4830 11:35:21.725713 tx_win_center[0][0][4] = 0
4831 11:35:21.725789 tx_first_pass[0][0][4] = 0
4832 11:35:21.728944 tx_last_pass[0][0][4] = 0
4833 11:35:21.733233 tx_win_center[0][0][5] = 0
4834 11:35:21.736015 tx_first_pass[0][0][5] = 0
4835 11:35:21.736090 tx_last_pass[0][0][5] = 0
4836 11:35:21.739233 tx_win_center[0][0][6] = 0
4837 11:35:21.742214 tx_first_pass[0][0][6] = 0
4838 11:35:21.742289 tx_last_pass[0][0][6] = 0
4839 11:35:21.745453 tx_win_center[0][0][7] = 0
4840 11:35:21.748694 tx_first_pass[0][0][7] = 0
4841 11:35:21.752323 tx_last_pass[0][0][7] = 0
4842 11:35:21.752400 tx_win_center[0][0][8] = 0
4843 11:35:21.756033 tx_first_pass[0][0][8] = 0
4844 11:35:21.758719 tx_last_pass[0][0][8] = 0
4845 11:35:21.762176 tx_win_center[0][0][9] = 0
4846 11:35:21.762251 tx_first_pass[0][0][9] = 0
4847 11:35:21.765637 tx_last_pass[0][0][9] = 0
4848 11:35:21.768988 tx_win_center[0][0][10] = 0
4849 11:35:21.771975 tx_first_pass[0][0][10] = 0
4850 11:35:21.772050 tx_last_pass[0][0][10] = 0
4851 11:35:21.775602 tx_win_center[0][0][11] = 0
4852 11:35:21.778478 tx_first_pass[0][0][11] = 0
4853 11:35:21.781516 tx_last_pass[0][0][11] = 0
4854 11:35:21.781591 tx_win_center[0][0][12] = 0
4855 11:35:21.785446 tx_first_pass[0][0][12] = 0
4856 11:35:21.788125 tx_last_pass[0][0][12] = 0
4857 11:35:21.791865 tx_win_center[0][0][13] = 0
4858 11:35:21.791940 tx_first_pass[0][0][13] = 0
4859 11:35:21.794844 tx_last_pass[0][0][13] = 0
4860 11:35:21.798352 tx_win_center[0][0][14] = 0
4861 11:35:21.801259 tx_first_pass[0][0][14] = 0
4862 11:35:21.801334 tx_last_pass[0][0][14] = 0
4863 11:35:21.804765 tx_win_center[0][0][15] = 0
4864 11:35:21.808216 tx_first_pass[0][0][15] = 0
4865 11:35:21.811254 tx_last_pass[0][0][15] = 0
4866 11:35:21.811329 tx_win_center[0][1][0] = 0
4867 11:35:21.814565 tx_first_pass[0][1][0] = 0
4868 11:35:21.817727 tx_last_pass[0][1][0] = 0
4869 11:35:21.821073 tx_win_center[0][1][1] = 0
4870 11:35:21.821147 tx_first_pass[0][1][1] = 0
4871 11:35:21.824663 tx_last_pass[0][1][1] = 0
4872 11:35:21.827649 tx_win_center[0][1][2] = 0
4873 11:35:21.831197 tx_first_pass[0][1][2] = 0
4874 11:35:21.831296 tx_last_pass[0][1][2] = 0
4875 11:35:21.834648 tx_win_center[0][1][3] = 0
4876 11:35:21.837603 tx_first_pass[0][1][3] = 0
4877 11:35:21.840603 tx_last_pass[0][1][3] = 0
4878 11:35:21.840678 tx_win_center[0][1][4] = 0
4879 11:35:21.844298 tx_first_pass[0][1][4] = 0
4880 11:35:21.847925 tx_last_pass[0][1][4] = 0
4881 11:35:21.848000 tx_win_center[0][1][5] = 0
4882 11:35:21.850732 tx_first_pass[0][1][5] = 0
4883 11:35:21.853844 tx_last_pass[0][1][5] = 0
4884 11:35:21.857503 tx_win_center[0][1][6] = 0
4885 11:35:21.857577 tx_first_pass[0][1][6] = 0
4886 11:35:21.860745 tx_last_pass[0][1][6] = 0
4887 11:35:21.864024 tx_win_center[0][1][7] = 0
4888 11:35:21.867647 tx_first_pass[0][1][7] = 0
4889 11:35:21.867722 tx_last_pass[0][1][7] = 0
4890 11:35:21.870491 tx_win_center[0][1][8] = 0
4891 11:35:21.873753 tx_first_pass[0][1][8] = 0
4892 11:35:21.876915 tx_last_pass[0][1][8] = 0
4893 11:35:21.876990 tx_win_center[0][1][9] = 0
4894 11:35:21.879975 tx_first_pass[0][1][9] = 0
4895 11:35:21.883976 tx_last_pass[0][1][9] = 0
4896 11:35:21.887438 tx_win_center[0][1][10] = 0
4897 11:35:21.887512 tx_first_pass[0][1][10] = 0
4898 11:35:21.890580 tx_last_pass[0][1][10] = 0
4899 11:35:21.893198 tx_win_center[0][1][11] = 0
4900 11:35:21.897156 tx_first_pass[0][1][11] = 0
4901 11:35:21.897230 tx_last_pass[0][1][11] = 0
4902 11:35:21.899695 tx_win_center[0][1][12] = 0
4903 11:35:21.903302 tx_first_pass[0][1][12] = 0
4904 11:35:21.906457 tx_last_pass[0][1][12] = 0
4905 11:35:21.906532 tx_win_center[0][1][13] = 0
4906 11:35:21.909527 tx_first_pass[0][1][13] = 0
4907 11:35:21.912840 tx_last_pass[0][1][13] = 0
4908 11:35:21.916207 tx_win_center[0][1][14] = 0
4909 11:35:21.916281 tx_first_pass[0][1][14] = 0
4910 11:35:21.919458 tx_last_pass[0][1][14] = 0
4911 11:35:21.923310 tx_win_center[0][1][15] = 0
4912 11:35:21.925947 tx_first_pass[0][1][15] = 0
4913 11:35:21.926077 tx_last_pass[0][1][15] = 0
4914 11:35:21.929807 tx_win_center[1][0][0] = 0
4915 11:35:21.933308 tx_first_pass[1][0][0] = 0
4916 11:35:21.936024 tx_last_pass[1][0][0] = 0
4917 11:35:21.936098 tx_win_center[1][0][1] = 0
4918 11:35:21.939328 tx_first_pass[1][0][1] = 0
4919 11:35:21.943214 tx_last_pass[1][0][1] = 0
4920 11:35:21.945666 tx_win_center[1][0][2] = 0
4921 11:35:21.945741 tx_first_pass[1][0][2] = 0
4922 11:35:21.948958 tx_last_pass[1][0][2] = 0
4923 11:35:21.952327 tx_win_center[1][0][3] = 0
4924 11:35:21.955555 tx_first_pass[1][0][3] = 0
4925 11:35:21.955629 tx_last_pass[1][0][3] = 0
4926 11:35:21.959018 tx_win_center[1][0][4] = 0
4927 11:35:21.962150 tx_first_pass[1][0][4] = 0
4928 11:35:21.965784 tx_last_pass[1][0][4] = 0
4929 11:35:21.965859 tx_win_center[1][0][5] = 0
4930 11:35:21.968669 tx_first_pass[1][0][5] = 0
4931 11:35:21.971719 tx_last_pass[1][0][5] = 0
4932 11:35:21.971793 tx_win_center[1][0][6] = 0
4933 11:35:21.975192 tx_first_pass[1][0][6] = 0
4934 11:35:21.978330 tx_last_pass[1][0][6] = 0
4935 11:35:21.982338 tx_win_center[1][0][7] = 0
4936 11:35:21.982413 tx_first_pass[1][0][7] = 0
4937 11:35:21.985369 tx_last_pass[1][0][7] = 0
4938 11:35:21.988444 tx_win_center[1][0][8] = 0
4939 11:35:21.991650 tx_first_pass[1][0][8] = 0
4940 11:35:21.991726 tx_last_pass[1][0][8] = 0
4941 11:35:21.994711 tx_win_center[1][0][9] = 0
4942 11:35:21.998371 tx_first_pass[1][0][9] = 0
4943 11:35:22.001589 tx_last_pass[1][0][9] = 0
4944 11:35:22.001663 tx_win_center[1][0][10] = 0
4945 11:35:22.004706 tx_first_pass[1][0][10] = 0
4946 11:35:22.008277 tx_last_pass[1][0][10] = 0
4947 11:35:22.011273 tx_win_center[1][0][11] = 0
4948 11:35:22.011348 tx_first_pass[1][0][11] = 0
4949 11:35:22.015065 tx_last_pass[1][0][11] = 0
4950 11:35:22.018560 tx_win_center[1][0][12] = 0
4951 11:35:22.021312 tx_first_pass[1][0][12] = 0
4952 11:35:22.021388 tx_last_pass[1][0][12] = 0
4953 11:35:22.024442 tx_win_center[1][0][13] = 0
4954 11:35:22.027559 tx_first_pass[1][0][13] = 0
4955 11:35:22.031450 tx_last_pass[1][0][13] = 0
4956 11:35:22.034402 tx_win_center[1][0][14] = 0
4957 11:35:22.034478 tx_first_pass[1][0][14] = 0
4958 11:35:22.038019 tx_last_pass[1][0][14] = 0
4959 11:35:22.040898 tx_win_center[1][0][15] = 0
4960 11:35:22.044061 tx_first_pass[1][0][15] = 0
4961 11:35:22.044136 tx_last_pass[1][0][15] = 0
4962 11:35:22.047697 tx_win_center[1][1][0] = 0
4963 11:35:22.050970 tx_first_pass[1][1][0] = 0
4964 11:35:22.053893 tx_last_pass[1][1][0] = 0
4965 11:35:22.053992 tx_win_center[1][1][1] = 0
4966 11:35:22.057339 tx_first_pass[1][1][1] = 0
4967 11:35:22.060602 tx_last_pass[1][1][1] = 0
4968 11:35:22.060677 tx_win_center[1][1][2] = 0
4969 11:35:22.063716 tx_first_pass[1][1][2] = 0
4970 11:35:22.066958 tx_last_pass[1][1][2] = 0
4971 11:35:22.070297 tx_win_center[1][1][3] = 0
4972 11:35:22.070371 tx_first_pass[1][1][3] = 0
4973 11:35:22.073936 tx_last_pass[1][1][3] = 0
4974 11:35:22.076594 tx_win_center[1][1][4] = 0
4975 11:35:22.080005 tx_first_pass[1][1][4] = 0
4976 11:35:22.080081 tx_last_pass[1][1][4] = 0
4977 11:35:22.083213 tx_win_center[1][1][5] = 0
4978 11:35:22.086666 tx_first_pass[1][1][5] = 0
4979 11:35:22.090636 tx_last_pass[1][1][5] = 0
4980 11:35:22.090711 tx_win_center[1][1][6] = 0
4981 11:35:22.093115 tx_first_pass[1][1][6] = 0
4982 11:35:22.096325 tx_last_pass[1][1][6] = 0
4983 11:35:22.096400 tx_win_center[1][1][7] = 0
4984 11:35:22.100043 tx_first_pass[1][1][7] = 0
4985 11:35:22.103230 tx_last_pass[1][1][7] = 0
4986 11:35:22.106504 tx_win_center[1][1][8] = 0
4987 11:35:22.106580 tx_first_pass[1][1][8] = 0
4988 11:35:22.109575 tx_last_pass[1][1][8] = 0
4989 11:35:22.112965 tx_win_center[1][1][9] = 0
4990 11:35:22.116616 tx_first_pass[1][1][9] = 0
4991 11:35:22.116692 tx_last_pass[1][1][9] = 0
4992 11:35:22.119369 tx_win_center[1][1][10] = 0
4993 11:35:22.122826 tx_first_pass[1][1][10] = 0
4994 11:35:22.126127 tx_last_pass[1][1][10] = 0
4995 11:35:22.126203 tx_win_center[1][1][11] = 0
4996 11:35:22.129254 tx_first_pass[1][1][11] = 0
4997 11:35:22.133034 tx_last_pass[1][1][11] = 0
4998 11:35:22.136112 tx_win_center[1][1][12] = 0
4999 11:35:22.136188 tx_first_pass[1][1][12] = 0
5000 11:35:22.139414 tx_last_pass[1][1][12] = 0
5001 11:35:22.142937 tx_win_center[1][1][13] = 0
5002 11:35:22.145606 tx_first_pass[1][1][13] = 0
5003 11:35:22.145681 tx_last_pass[1][1][13] = 0
5004 11:35:22.149309 tx_win_center[1][1][14] = 0
5005 11:35:22.152525 tx_first_pass[1][1][14] = 0
5006 11:35:22.155899 tx_last_pass[1][1][14] = 0
5007 11:35:22.158795 tx_win_center[1][1][15] = 0
5008 11:35:22.158870 tx_first_pass[1][1][15] = 0
5009 11:35:22.162160 tx_last_pass[1][1][15] = 0
5010 11:35:22.165407 dump params rx window
5011 11:35:22.165483 rx_firspass[0][0][0] = 0
5012 11:35:22.169288 rx_lastpass[0][0][0] = 0
5013 11:35:22.172662 rx_firspass[0][0][1] = 0
5014 11:35:22.172736 rx_lastpass[0][0][1] = 0
5015 11:35:22.175842 rx_firspass[0][0][2] = 0
5016 11:35:22.179537 rx_lastpass[0][0][2] = 0
5017 11:35:22.179612 rx_firspass[0][0][3] = 0
5018 11:35:22.182330 rx_lastpass[0][0][3] = 0
5019 11:35:22.185452 rx_firspass[0][0][4] = 0
5020 11:35:22.188535 rx_lastpass[0][0][4] = 0
5021 11:35:22.188610 rx_firspass[0][0][5] = 0
5022 11:35:22.192094 rx_lastpass[0][0][5] = 0
5023 11:35:22.195840 rx_firspass[0][0][6] = 0
5024 11:35:22.195914 rx_lastpass[0][0][6] = 0
5025 11:35:22.198775 rx_firspass[0][0][7] = 0
5026 11:35:22.201655 rx_lastpass[0][0][7] = 0
5027 11:35:22.201730 rx_firspass[0][0][8] = 0
5028 11:35:22.205084 rx_lastpass[0][0][8] = 0
5029 11:35:22.208600 rx_firspass[0][0][9] = 0
5030 11:35:22.208674 rx_lastpass[0][0][9] = 0
5031 11:35:22.211934 rx_firspass[0][0][10] = 0
5032 11:35:22.215066 rx_lastpass[0][0][10] = 0
5033 11:35:22.218125 rx_firspass[0][0][11] = 0
5034 11:35:22.218200 rx_lastpass[0][0][11] = 0
5035 11:35:22.221330 rx_firspass[0][0][12] = 0
5036 11:35:22.224893 rx_lastpass[0][0][12] = 0
5037 11:35:22.228644 rx_firspass[0][0][13] = 0
5038 11:35:22.228720 rx_lastpass[0][0][13] = 0
5039 11:35:22.231156 rx_firspass[0][0][14] = 0
5040 11:35:22.234825 rx_lastpass[0][0][14] = 0
5041 11:35:22.234901 rx_firspass[0][0][15] = 0
5042 11:35:22.238153 rx_lastpass[0][0][15] = 0
5043 11:35:22.241272 rx_firspass[0][1][0] = 0
5044 11:35:22.244459 rx_lastpass[0][1][0] = 0
5045 11:35:22.244534 rx_firspass[0][1][1] = 0
5046 11:35:22.247599 rx_lastpass[0][1][1] = 0
5047 11:35:22.250837 rx_firspass[0][1][2] = 0
5048 11:35:22.250912 rx_lastpass[0][1][2] = 0
5049 11:35:22.254431 rx_firspass[0][1][3] = 0
5050 11:35:22.257573 rx_lastpass[0][1][3] = 0
5051 11:35:22.257647 rx_firspass[0][1][4] = 0
5052 11:35:22.260820 rx_lastpass[0][1][4] = 0
5053 11:35:22.264018 rx_firspass[0][1][5] = 0
5054 11:35:22.267093 rx_lastpass[0][1][5] = 0
5055 11:35:22.267182 rx_firspass[0][1][6] = 0
5056 11:35:22.270501 rx_lastpass[0][1][6] = 0
5057 11:35:22.273927 rx_firspass[0][1][7] = 0
5058 11:35:22.274002 rx_lastpass[0][1][7] = 0
5059 11:35:22.277282 rx_firspass[0][1][8] = 0
5060 11:35:22.280691 rx_lastpass[0][1][8] = 0
5061 11:35:22.280766 rx_firspass[0][1][9] = 0
5062 11:35:22.283791 rx_lastpass[0][1][9] = 0
5063 11:35:22.287988 rx_firspass[0][1][10] = 0
5064 11:35:22.290407 rx_lastpass[0][1][10] = 0
5065 11:35:22.290482 rx_firspass[0][1][11] = 0
5066 11:35:22.293878 rx_lastpass[0][1][11] = 0
5067 11:35:22.297056 rx_firspass[0][1][12] = 0
5068 11:35:22.297152 rx_lastpass[0][1][12] = 0
5069 11:35:22.300188 rx_firspass[0][1][13] = 0
5070 11:35:22.303364 rx_lastpass[0][1][13] = 0
5071 11:35:22.307373 rx_firspass[0][1][14] = 0
5072 11:35:22.307462 rx_lastpass[0][1][14] = 0
5073 11:35:22.310126 rx_firspass[0][1][15] = 0
5074 11:35:22.313228 rx_lastpass[0][1][15] = 0
5075 11:35:22.313376 rx_firspass[1][0][0] = 0
5076 11:35:22.316625 rx_lastpass[1][0][0] = 0
5077 11:35:22.319818 rx_firspass[1][0][1] = 0
5078 11:35:22.323436 rx_lastpass[1][0][1] = 0
5079 11:35:22.323506 rx_firspass[1][0][2] = 0
5080 11:35:22.326306 rx_lastpass[1][0][2] = 0
5081 11:35:22.330085 rx_firspass[1][0][3] = 0
5082 11:35:22.330156 rx_lastpass[1][0][3] = 0
5083 11:35:22.333264 rx_firspass[1][0][4] = 0
5084 11:35:22.336661 rx_lastpass[1][0][4] = 0
5085 11:35:22.336737 rx_firspass[1][0][5] = 0
5086 11:35:22.339947 rx_lastpass[1][0][5] = 0
5087 11:35:22.342826 rx_firspass[1][0][6] = 0
5088 11:35:22.346160 rx_lastpass[1][0][6] = 0
5089 11:35:22.346236 rx_firspass[1][0][7] = 0
5090 11:35:22.349504 rx_lastpass[1][0][7] = 0
5091 11:35:22.352497 rx_firspass[1][0][8] = 0
5092 11:35:22.352595 rx_lastpass[1][0][8] = 0
5093 11:35:22.355710 rx_firspass[1][0][9] = 0
5094 11:35:22.359362 rx_lastpass[1][0][9] = 0
5095 11:35:22.359438 rx_firspass[1][0][10] = 0
5096 11:35:22.362750 rx_lastpass[1][0][10] = 0
5097 11:35:22.365875 rx_firspass[1][0][11] = 0
5098 11:35:22.369267 rx_lastpass[1][0][11] = 0
5099 11:35:22.369354 rx_firspass[1][0][12] = 0
5100 11:35:22.372680 rx_lastpass[1][0][12] = 0
5101 11:35:22.375810 rx_firspass[1][0][13] = 0
5102 11:35:22.375909 rx_lastpass[1][0][13] = 0
5103 11:35:22.379502 rx_firspass[1][0][14] = 0
5104 11:35:22.382130 rx_lastpass[1][0][14] = 0
5105 11:35:22.385882 rx_firspass[1][0][15] = 0
5106 11:35:22.385961 rx_lastpass[1][0][15] = 0
5107 11:35:22.388939 rx_firspass[1][1][0] = 0
5108 11:35:22.392301 rx_lastpass[1][1][0] = 0
5109 11:35:22.392377 rx_firspass[1][1][1] = 0
5110 11:35:22.395737 rx_lastpass[1][1][1] = 0
5111 11:35:22.398878 rx_firspass[1][1][2] = 0
5112 11:35:22.401880 rx_lastpass[1][1][2] = 0
5113 11:35:22.401978 rx_firspass[1][1][3] = 0
5114 11:35:22.405482 rx_lastpass[1][1][3] = 0
5115 11:35:22.409164 rx_firspass[1][1][4] = 0
5116 11:35:22.409241 rx_lastpass[1][1][4] = 0
5117 11:35:22.412322 rx_firspass[1][1][5] = 0
5118 11:35:22.415030 rx_lastpass[1][1][5] = 0
5119 11:35:22.415107 rx_firspass[1][1][6] = 0
5120 11:35:22.418670 rx_lastpass[1][1][6] = 0
5121 11:35:22.421827 rx_firspass[1][1][7] = 0
5122 11:35:22.421904 rx_lastpass[1][1][7] = 0
5123 11:35:22.425269 rx_firspass[1][1][8] = 0
5124 11:35:22.428182 rx_lastpass[1][1][8] = 0
5125 11:35:22.431837 rx_firspass[1][1][9] = 0
5126 11:35:22.431911 rx_lastpass[1][1][9] = 0
5127 11:35:22.434681 rx_firspass[1][1][10] = 0
5128 11:35:22.438442 rx_lastpass[1][1][10] = 0
5129 11:35:22.438516 rx_firspass[1][1][11] = 0
5130 11:35:22.441737 rx_lastpass[1][1][11] = 0
5131 11:35:22.444428 rx_firspass[1][1][12] = 0
5132 11:35:22.448177 rx_lastpass[1][1][12] = 0
5133 11:35:22.448274 rx_firspass[1][1][13] = 0
5134 11:35:22.451109 rx_lastpass[1][1][13] = 0
5135 11:35:22.454156 rx_firspass[1][1][14] = 0
5136 11:35:22.454230 rx_lastpass[1][1][14] = 0
5137 11:35:22.457497 rx_firspass[1][1][15] = 0
5138 11:35:22.461148 rx_lastpass[1][1][15] = 0
5139 11:35:22.464372 dump params clk_delay
5140 11:35:22.464441 clk_delay[0] = 0
5141 11:35:22.464498 clk_delay[1] = 0
5142 11:35:22.467590 dump params dqs_delay
5143 11:35:22.470722 dqs_delay[0][0] = 0
5144 11:35:22.470796 dqs_delay[0][1] = 0
5145 11:35:22.473943 dqs_delay[1][0] = 0
5146 11:35:22.474076 dqs_delay[1][1] = 0
5147 11:35:22.477215 dump params delay_cell_unit = 744
5148 11:35:22.480354 mt_set_emi_preloader end
5149 11:35:22.484151 [mt_mem_init] dram size: 0x100000000, rank number: 2
5150 11:35:22.490545 [complex_mem_test] start addr:0x40000000, len:20480
5151 11:35:22.526520 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5152 11:35:22.532916 [complex_mem_test] start addr:0x80000000, len:20480
5153 11:35:22.568700 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5154 11:35:22.575232 [complex_mem_test] start addr:0xc0000000, len:20480
5155 11:35:22.610689 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5156 11:35:22.617638 [complex_mem_test] start addr:0x56000000, len:8192
5157 11:35:22.634334 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5158 11:35:22.637461 ddr_geometry:1
5159 11:35:22.640546 [complex_mem_test] start addr:0x80000000, len:8192
5160 11:35:22.657833 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5161 11:35:22.661003 dram_init: dram init end (result: 0)
5162 11:35:22.667820 Successfully loaded DRAM blobs and ran DRAM calibration
5163 11:35:22.677684 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5164 11:35:22.677762 CBMEM:
5165 11:35:22.681028 IMD: root @ 00000000fffff000 254 entries.
5166 11:35:22.684082 IMD: root @ 00000000ffffec00 62 entries.
5167 11:35:22.691048 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5168 11:35:22.697100 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5169 11:35:22.700710 in-header: 03 a1 00 00 08 00 00 00
5170 11:35:22.703926 in-data: 84 60 60 10 00 00 00 00
5171 11:35:22.707051 Chrome EC: clear events_b mask to 0x0000000020004000
5172 11:35:22.713718 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5173 11:35:22.717940 in-header: 03 fd 00 00 00 00 00 00
5174 11:35:22.721144 in-data:
5175 11:35:22.724311 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5176 11:35:22.727646 CBFS @ 21000 size 3d4000
5177 11:35:22.730677 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5178 11:35:22.733917 CBFS: Locating 'fallback/ramstage'
5179 11:35:22.737480 CBFS: Found @ offset 10d40 size d563
5180 11:35:22.759758 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5181 11:35:22.771725 Accumulated console time in romstage 13501 ms
5182 11:35:22.771804
5183 11:35:22.771880
5184 11:35:22.781882 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5185 11:35:22.785672 ARM64: Exception handlers installed.
5186 11:35:22.785751 ARM64: Testing exception
5187 11:35:22.788521 ARM64: Done test exception
5188 11:35:22.791654 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5189 11:35:22.794804 Manufacturer: ef
5190 11:35:22.801926 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5191 11:35:22.805506 WARNING: RO_VPD is uninitialized or empty.
5192 11:35:22.808193 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5193 11:35:22.811425 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5194 11:35:22.821585 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5195 11:35:22.825261 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5196 11:35:22.831676 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5197 11:35:22.831755 Enumerating buses...
5198 11:35:22.839023 Show all devs... Before device enumeration.
5199 11:35:22.839102 Root Device: enabled 1
5200 11:35:22.841859 CPU_CLUSTER: 0: enabled 1
5201 11:35:22.841941 CPU: 00: enabled 1
5202 11:35:22.844640 Compare with tree...
5203 11:35:22.848299 Root Device: enabled 1
5204 11:35:22.848378 CPU_CLUSTER: 0: enabled 1
5205 11:35:22.851891 CPU: 00: enabled 1
5206 11:35:22.855345 Root Device scanning...
5207 11:35:22.855423 root_dev_scan_bus for Root Device
5208 11:35:22.857735 CPU_CLUSTER: 0 enabled
5209 11:35:22.861270 root_dev_scan_bus for Root Device done
5210 11:35:22.868002 scan_bus: scanning of bus Root Device took 10689 usecs
5211 11:35:22.868081 done
5212 11:35:22.871497 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5213 11:35:22.874157 Allocating resources...
5214 11:35:22.874235 Reading resources...
5215 11:35:22.881236 Root Device read_resources bus 0 link: 0
5216 11:35:22.884365 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5217 11:35:22.887368 CPU: 00 missing read_resources
5218 11:35:22.890571 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5219 11:35:22.893734 Root Device read_resources bus 0 link: 0 done
5220 11:35:22.896975 Done reading resources.
5221 11:35:22.900817 Show resources in subtree (Root Device)...After reading.
5222 11:35:22.906961 Root Device child on link 0 CPU_CLUSTER: 0
5223 11:35:22.910494 CPU_CLUSTER: 0 child on link 0 CPU: 00
5224 11:35:22.916782 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5225 11:35:22.920372 CPU: 00
5226 11:35:22.920450 Setting resources...
5227 11:35:22.923511 Root Device assign_resources, bus 0 link: 0
5228 11:35:22.927329 CPU_CLUSTER: 0 missing set_resources
5229 11:35:22.933294 Root Device assign_resources, bus 0 link: 0
5230 11:35:22.933374 Done setting resources.
5231 11:35:22.940296 Show resources in subtree (Root Device)...After assigning values.
5232 11:35:22.942934 Root Device child on link 0 CPU_CLUSTER: 0
5233 11:35:22.946478 CPU_CLUSTER: 0 child on link 0 CPU: 00
5234 11:35:22.956295 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5235 11:35:22.956372 CPU: 00
5236 11:35:22.960205 Done allocating resources.
5237 11:35:22.962892 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5238 11:35:22.966023 Enabling resources...
5239 11:35:22.966119 done.
5240 11:35:22.972630 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5241 11:35:22.972709 Initializing devices...
5242 11:35:22.975747 Root Device init ...
5243 11:35:22.979811 mainboard_init: Starting display init.
5244 11:35:22.982903 ADC[4]: Raw value=75908 ID=0
5245 11:35:23.004829 anx7625_power_on_init: Init interface.
5246 11:35:23.007708 anx7625_disable_pd_protocol: Disabled PD feature.
5247 11:35:23.014110 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5248 11:35:23.060936 anx7625_start_dp_work: Secure OCM version=00
5249 11:35:23.064156 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5250 11:35:23.081416 sp_tx_get_edid_block: EDID Block = 1
5251 11:35:23.199088 Extracted contents:
5252 11:35:23.201942 header: 00 ff ff ff ff ff ff 00
5253 11:35:23.205078 serial number: 06 af 5c 14 00 00 00 00 00 1a
5254 11:35:23.208829 version: 01 04
5255 11:35:23.211962 basic params: 95 1a 0e 78 02
5256 11:35:23.215250 chroma info: 99 85 95 55 56 92 28 22 50 54
5257 11:35:23.218425 established: 00 00 00
5258 11:35:23.225032 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5259 11:35:23.231633 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5260 11:35:23.235053 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5261 11:35:23.242198 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5262 11:35:23.248074 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5263 11:35:23.251571 extensions: 00
5264 11:35:23.251647 checksum: ae
5265 11:35:23.251723
5266 11:35:23.257944 Manufacturer: AUO Model 145c Serial Number 0
5267 11:35:23.258032 Made week 0 of 2016
5268 11:35:23.261237 EDID version: 1.4
5269 11:35:23.261356 Digital display
5270 11:35:23.264254 6 bits per primary color channel
5271 11:35:23.267449 DisplayPort interface
5272 11:35:23.270772 Maximum image size: 26 cm x 14 cm
5273 11:35:23.270848 Gamma: 220%
5274 11:35:23.270924 Check DPMS levels
5275 11:35:23.274053 Supported color formats: RGB 4:4:4
5276 11:35:23.277148 First detailed timing is preferred timing
5277 11:35:23.280491 Established timings supported:
5278 11:35:23.284043 Standard timings supported:
5279 11:35:23.287834 Detailed timings
5280 11:35:23.290955 Hex of detail: ce1d56ea50001a3030204600009010000018
5281 11:35:23.294161 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5282 11:35:23.300790 0556 0586 05a6 0640 hborder 0
5283 11:35:23.303486 0300 0304 030a 031a vborder 0
5284 11:35:23.306848 -hsync -vsync
5285 11:35:23.306952 Did detailed timing
5286 11:35:23.313852 Hex of detail: 0000000f0000000000000000000000000020
5287 11:35:23.316924 Manufacturer-specified data, tag 15
5288 11:35:23.319950 Hex of detail: 000000fe0041554f0a202020202020202020
5289 11:35:23.320028 ASCII string: AUO
5290 11:35:23.326922 Hex of detail: 000000fe004231313658414230312e34200a
5291 11:35:23.329955 ASCII string: B116XAB01.4
5292 11:35:23.330073 Checksum
5293 11:35:23.330134 Checksum: 0xae (valid)
5294 11:35:23.336691 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5295 11:35:23.340149 DSI data_rate: 457800000 bps
5296 11:35:23.346681 anx7625_parse_edid: set default k value to 0x3d for panel
5297 11:35:23.349607 anx7625_parse_edid: pixelclock(76300).
5298 11:35:23.353334 hactive(1366), hsync(32), hfp(48), hbp(154)
5299 11:35:23.356483 vactive(768), vsync(6), vfp(4), vbp(16)
5300 11:35:23.359312 anx7625_dsi_config: config dsi.
5301 11:35:23.366764 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5302 11:35:23.387868 anx7625_dsi_config: success to config DSI
5303 11:35:23.391568 anx7625_dp_start: MIPI phy setup OK.
5304 11:35:23.394432 [SSUSB] Setting up USB HOST controller...
5305 11:35:23.397733 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5306 11:35:23.401571 [SSUSB] phy power-on done.
5307 11:35:23.405299 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5308 11:35:23.408542 in-header: 03 fc 01 00 00 00 00 00
5309 11:35:23.408617 in-data:
5310 11:35:23.414971 handle_proto3_response: EC response with error code: 1
5311 11:35:23.415047 SPM: pcm index = 1
5312 11:35:23.418599 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5313 11:35:23.421988 CBFS @ 21000 size 3d4000
5314 11:35:23.428151 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5315 11:35:23.431680 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5316 11:35:23.434461 CBFS: Found @ offset 1e7c0 size 1026
5317 11:35:23.441237 read SPI 0x3f808 0x1026: 1270 us, 3255 KB/s, 26.040 Mbps
5318 11:35:23.444752 SPM: binary array size = 2988
5319 11:35:23.447624 SPM: version = pcm_allinone_v1.17.2_20180829
5320 11:35:23.451228 SPM binary loaded in 32 msecs
5321 11:35:23.459097 spm_kick_im_to_fetch: ptr = 000000004021eec2
5322 11:35:23.462246 spm_kick_im_to_fetch: len = 2988
5323 11:35:23.462320 SPM: spm_kick_pcm_to_run
5324 11:35:23.465791 SPM: spm_kick_pcm_to_run done
5325 11:35:23.468943 SPM: spm_init done in 52 msecs
5326 11:35:23.472208 Root Device init finished in 494984 usecs
5327 11:35:23.475739 CPU_CLUSTER: 0 init ...
5328 11:35:23.485572 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5329 11:35:23.488590 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5330 11:35:23.491916 CBFS @ 21000 size 3d4000
5331 11:35:23.495148 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5332 11:35:23.498311 CBFS: Locating 'sspm.bin'
5333 11:35:23.501557 CBFS: Found @ offset 208c0 size 41cb
5334 11:35:23.512111 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5335 11:35:23.520108 CPU_CLUSTER: 0 init finished in 42799 usecs
5336 11:35:23.520183 Devices initialized
5337 11:35:23.523289 Show all devs... After init.
5338 11:35:23.526795 Root Device: enabled 1
5339 11:35:23.526869 CPU_CLUSTER: 0: enabled 1
5340 11:35:23.529751 CPU: 00: enabled 1
5341 11:35:23.533485 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5342 11:35:23.539728 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5343 11:35:23.543257 ELOG: NV offset 0x558000 size 0x1000
5344 11:35:23.546818 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5345 11:35:23.553116 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5346 11:35:23.559446 ELOG: Event(17) added with size 13 at 2024-07-17 11:35:07 UTC
5347 11:35:23.563115 out: cmd=0x121: 03 db 21 01 00 00 00 00
5348 11:35:23.566285 in-header: 03 0e 00 00 2c 00 00 00
5349 11:35:23.579163 in-data: c3 4a 00 00 00 00 00 00 02 10 00 00 06 80 00 00 e5 dc 07 00 06 80 00 00 e0 fb 34 00 06 80 00 00 e5 e6 00 00 06 80 00 00 06 e3 01 00
5350 11:35:23.582797 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5351 11:35:23.585905 in-header: 03 19 00 00 08 00 00 00
5352 11:35:23.589408 in-data: a2 e0 47 00 13 00 00 00
5353 11:35:23.589482 Chrome EC: UHEPI supported
5354 11:35:23.595698 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5355 11:35:23.599564 in-header: 03 e1 00 00 08 00 00 00
5356 11:35:23.602784 in-data: 84 20 60 10 00 00 00 00
5357 11:35:23.608905 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5358 11:35:23.615742 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5359 11:35:23.618924 in-header: 03 e1 00 00 08 00 00 00
5360 11:35:23.621971 in-data: 84 20 60 10 00 00 00 00
5361 11:35:23.625157 ELOG: Event(A1) added with size 10 at 2024-07-17 11:35:07 UTC
5362 11:35:23.632161 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5363 11:35:23.638339 ELOG: Event(A0) added with size 9 at 2024-07-17 11:35:07 UTC
5364 11:35:23.641694 elog_add_boot_reason: Logged dev mode boot
5365 11:35:23.645021 Finalize devices...
5366 11:35:23.645096 Devices finalized
5367 11:35:23.651984 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5368 11:35:23.655296 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5369 11:35:23.661717 ELOG: Event(91) added with size 10 at 2024-07-17 11:35:07 UTC
5370 11:35:23.665063 Writing coreboot table at 0xffeda000
5371 11:35:23.668290 0. 0000000000114000-000000000011efff: RAMSTAGE
5372 11:35:23.671530 1. 0000000040000000-000000004023cfff: RAMSTAGE
5373 11:35:23.677920 2. 000000004023d000-00000000545fffff: RAM
5374 11:35:23.681096 3. 0000000054600000-000000005465ffff: BL31
5375 11:35:23.684435 4. 0000000054660000-00000000ffed9fff: RAM
5376 11:35:23.690776 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5377 11:35:23.694454 6. 0000000100000000-000000013fffffff: RAM
5378 11:35:23.694532 Passing 5 GPIOs to payload:
5379 11:35:23.700568 NAME | PORT | POLARITY | VALUE
5380 11:35:23.704294 write protect | 0x00000096 | low | high
5381 11:35:23.710569 EC in RW | 0x000000b1 | high | undefined
5382 11:35:23.714507 EC interrupt | 0x00000097 | low | undefined
5383 11:35:23.720696 TPM interrupt | 0x00000099 | high | undefined
5384 11:35:23.723630 speaker enable | 0x000000af | high | undefined
5385 11:35:23.727395 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5386 11:35:23.730277 in-header: 03 f7 00 00 02 00 00 00
5387 11:35:23.733644 in-data: 04 00
5388 11:35:23.733721 Board ID: 4
5389 11:35:23.737265 ADC[3]: Raw value=213471 ID=1
5390 11:35:23.737365 RAM code: 1
5391 11:35:23.737443 SKU ID: 16
5392 11:35:23.743636 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5393 11:35:23.743715 CBFS @ 21000 size 3d4000
5394 11:35:23.750513 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5395 11:35:23.756705 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum b96b
5396 11:35:23.760027 coreboot table: 940 bytes.
5397 11:35:23.763035 IMD ROOT 0. 00000000fffff000 00001000
5398 11:35:23.766305 IMD SMALL 1. 00000000ffffe000 00001000
5399 11:35:23.770196 CONSOLE 2. 00000000fffde000 00020000
5400 11:35:23.772933 FMAP 3. 00000000fffdd000 0000047c
5401 11:35:23.776436 TIME STAMP 4. 00000000fffdc000 00000910
5402 11:35:23.779624 RAMOOPS 5. 00000000ffedc000 00100000
5403 11:35:23.783356 COREBOOT 6. 00000000ffeda000 00002000
5404 11:35:23.786032 IMD small region:
5405 11:35:23.789772 IMD ROOT 0. 00000000ffffec00 00000400
5406 11:35:23.792830 VBOOT WORK 1. 00000000ffffeb00 00000100
5407 11:35:23.796087 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5408 11:35:23.799142 VPD 3. 00000000ffffea60 0000006c
5409 11:35:23.806202 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5410 11:35:23.812484 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5411 11:35:23.815923 in-header: 03 e1 00 00 08 00 00 00
5412 11:35:23.819139 in-data: 84 20 60 10 00 00 00 00
5413 11:35:23.822124 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5414 11:35:23.825777 CBFS @ 21000 size 3d4000
5415 11:35:23.832107 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5416 11:35:23.832185 CBFS: Locating 'fallback/payload'
5417 11:35:23.842325 CBFS: Found @ offset dc040 size 439a0
5418 11:35:23.930368 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5419 11:35:23.932868 Checking segment from ROM address 0x0000000040003a00
5420 11:35:23.939627 Checking segment from ROM address 0x0000000040003a1c
5421 11:35:23.942880 Loading segment from ROM address 0x0000000040003a00
5422 11:35:23.945984 code (compression=0)
5423 11:35:23.956138 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5424 11:35:23.962345 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5425 11:35:23.965682 it's not compressed!
5426 11:35:23.969229 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5427 11:35:23.975595 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5428 11:35:23.984123 Loading segment from ROM address 0x0000000040003a1c
5429 11:35:23.987135 Entry Point 0x0000000080000000
5430 11:35:23.987211 Loaded segments
5431 11:35:23.994290 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5432 11:35:23.997278 Jumping to boot code at 0000000080000000(00000000ffeda000)
5433 11:35:24.007193 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5434 11:35:24.013611 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5435 11:35:24.013686 CBFS @ 21000 size 3d4000
5436 11:35:24.019739 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5437 11:35:24.023567 CBFS: Locating 'fallback/bl31'
5438 11:35:24.026578 CBFS: Found @ offset 36dc0 size 5820
5439 11:35:24.037808 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5440 11:35:24.040986 Checking segment from ROM address 0x0000000040003a00
5441 11:35:24.047683 Checking segment from ROM address 0x0000000040003a1c
5442 11:35:24.051228 Loading segment from ROM address 0x0000000040003a00
5443 11:35:24.054251 code (compression=1)
5444 11:35:24.064387 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5445 11:35:24.070505 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5446 11:35:24.070581 using LZMA
5447 11:35:24.079680 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5448 11:35:24.086039 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5449 11:35:24.089887 Loading segment from ROM address 0x0000000040003a1c
5450 11:35:24.092606 Entry Point 0x0000000054601000
5451 11:35:24.092681 Loaded segments
5452 11:35:24.095701 NOTICE: MT8183 bl31_setup
5453 11:35:24.103311 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5454 11:35:24.106552 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5455 11:35:24.110327 INFO: [DEVAPC] dump DEVAPC registers:
5456 11:35:24.120412 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5457 11:35:24.126224 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5458 11:35:24.136263 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5459 11:35:24.142577 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5460 11:35:24.152919 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5461 11:35:24.159136 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5462 11:35:24.169653 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5463 11:35:24.175527 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5464 11:35:24.185716 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5465 11:35:24.192400 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5466 11:35:24.201939 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5467 11:35:24.208212 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5468 11:35:24.218259 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5469 11:35:24.224907 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5470 11:35:24.231242 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5471 11:35:24.238279 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5472 11:35:24.247812 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5473 11:35:24.254558 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5474 11:35:24.261000 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5475 11:35:24.267224 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5476 11:35:24.277423 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5477 11:35:24.284106 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5478 11:35:24.287741 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5479 11:35:24.290765 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5480 11:35:24.293951 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5481 11:35:24.296976 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5482 11:35:24.300669 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5483 11:35:24.307193 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5484 11:35:24.310139 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5485 11:35:24.313937 WARNING: region 0:
5486 11:35:24.317134 WARNING: apc:0x168, sa:0x0, ea:0xfff
5487 11:35:24.317211 WARNING: region 1:
5488 11:35:24.320298 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5489 11:35:24.323307 WARNING: region 2:
5490 11:35:24.326767 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5491 11:35:24.329899 WARNING: region 3:
5492 11:35:24.333187 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5493 11:35:24.333264 WARNING: region 4:
5494 11:35:24.336284 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5495 11:35:24.340146 WARNING: region 5:
5496 11:35:24.343701 WARNING: apc:0x0, sa:0x0, ea:0x0
5497 11:35:24.343777 WARNING: region 6:
5498 11:35:24.346469 WARNING: apc:0x0, sa:0x0, ea:0x0
5499 11:35:24.349815 WARNING: region 7:
5500 11:35:24.353526 WARNING: apc:0x0, sa:0x0, ea:0x0
5501 11:35:24.359848 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5502 11:35:24.362722 INFO: SPM: enable SPMC mode
5503 11:35:24.365930 NOTICE: spm_boot_init() start
5504 11:35:24.369310 NOTICE: spm_boot_init() end
5505 11:35:24.372665 INFO: BL31: Initializing runtime services
5506 11:35:24.376010 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5507 11:35:24.382305 INFO: BL31: Preparing for EL3 exit to normal world
5508 11:35:24.385562 INFO: Entry point address = 0x80000000
5509 11:35:24.389158 INFO: SPSR = 0x8
5510 11:35:24.409887
5511 11:35:24.410033
5512 11:35:24.410109
5513 11:35:24.410580 end: 2.2.3 depthcharge-start (duration 00:00:23) [common]
5514 11:35:24.410713 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5515 11:35:24.410811 Setting prompt string to ['jacuzzi:']
5516 11:35:24.410875 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5517 11:35:24.413247 Starting depthcharge on Juniper...
5518 11:35:24.413370
5519 11:35:24.416731 vboot_handoff: creating legacy vboot_handoff structure
5520 11:35:24.416805
5521 11:35:24.419636 ec_init(0): CrosEC protocol v3 supported (544, 544)
5522 11:35:24.423158
5523 11:35:24.423232 Wipe memory regions:
5524 11:35:24.423291
5525 11:35:24.426547 [0x00000040000000, 0x00000054600000)
5526 11:35:24.469139
5527 11:35:24.469218 [0x00000054660000, 0x00000080000000)
5528 11:35:24.561229
5529 11:35:24.561332 [0x000000811994a0, 0x000000ffeda000)
5530 11:35:24.819681
5531 11:35:24.819801 [0x00000100000000, 0x00000140000000)
5532 11:35:24.952027
5533 11:35:24.955787 Initializing XHCI USB controller at 0x11200000.
5534 11:35:24.978744
5535 11:35:24.981711 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5536 11:35:24.981785
5537 11:35:24.981843
5538 11:35:24.982068 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5539 11:35:24.982143 Sending line: 'tftpboot 192.168.201.1 14864601/tftp-deploy-znwinunr/kernel/image.itb 14864601/tftp-deploy-znwinunr/kernel/cmdline '
5541 11:35:25.082577 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5542 11:35:25.082678 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5543 11:35:25.087071 jacuzzi: tftpboot 192.168.201.1 14864601/tftp-deploy-znwinunr/kernel/image.itp-deploy-znwinunr/kernel/cmdline
5544 11:35:25.087145
5545 11:35:25.087203 Waiting for link
5546 11:35:25.492340
5547 11:35:25.492468 R8152: Initializing
5548 11:35:25.492527
5549 11:35:25.495566 Version 9 (ocp_data = 6010)
5550 11:35:25.495641
5551 11:35:25.498863 R8152: Done initializing
5552 11:35:25.498938
5553 11:35:25.498997 Adding net device
5554 11:35:25.884787
5555 11:35:25.884909 done.
5556 11:35:25.884966
5557 11:35:25.885018 MAC: 00:e0:4c:72:3d:a6
5558 11:35:25.885070
5559 11:35:25.887804 Sending DHCP discover... done.
5560 11:35:25.887924
5561 11:35:25.891199 Waiting for reply... done.
5562 11:35:25.891343
5563 11:35:25.894485 Sending DHCP request... done.
5564 11:35:25.894576
5565 11:35:25.903401 Waiting for reply... done.
5566 11:35:25.903508
5567 11:35:25.903604 My ip is 192.168.201.20
5568 11:35:25.903672
5569 11:35:25.906657 The DHCP server ip is 192.168.201.1
5570 11:35:25.906790
5571 11:35:25.913122 TFTP server IP predefined by user: 192.168.201.1
5572 11:35:25.913261
5573 11:35:25.919979 Bootfile predefined by user: 14864601/tftp-deploy-znwinunr/kernel/image.itb
5574 11:35:25.920101
5575 11:35:25.923212 Sending tftp read request... done.
5576 11:35:25.923323
5577 11:35:25.926874 Waiting for the transfer...
5578 11:35:25.926961
5579 11:35:26.181842 00000000 ################################################################
5580 11:35:26.181977
5581 11:35:26.434002 00080000 ################################################################
5582 11:35:26.434138
5583 11:35:26.682817 00100000 ################################################################
5584 11:35:26.682933
5585 11:35:26.929477 00180000 ################################################################
5586 11:35:26.929592
5587 11:35:27.181766 00200000 ################################################################
5588 11:35:27.181883
5589 11:35:27.435862 00280000 ################################################################
5590 11:35:27.435978
5591 11:35:27.702140 00300000 ################################################################
5592 11:35:27.702262
5593 11:35:27.960441 00380000 ################################################################
5594 11:35:27.960572
5595 11:35:28.226623 00400000 ################################################################
5596 11:35:28.226739
5597 11:35:28.485530 00480000 ################################################################
5598 11:35:28.485672
5599 11:35:28.738698 00500000 ################################################################
5600 11:35:28.738822
5601 11:35:28.990311 00580000 ################################################################
5602 11:35:28.990433
5603 11:35:29.243882 00600000 ################################################################
5604 11:35:29.244004
5605 11:35:29.498489 00680000 ################################################################
5606 11:35:29.498602
5607 11:35:29.751522 00700000 ################################################################
5608 11:35:29.751646
5609 11:35:30.001501 00780000 ################################################################
5610 11:35:30.001638
5611 11:35:30.252319 00800000 ################################################################
5612 11:35:30.252446
5613 11:35:30.505762 00880000 ################################################################
5614 11:35:30.505914
5615 11:35:30.755319 00900000 ################################################################
5616 11:35:30.755442
5617 11:35:31.018084 00980000 ################################################################
5618 11:35:31.018211
5619 11:35:31.284472 00a00000 ################################################################
5620 11:35:31.284592
5621 11:35:31.538765 00a80000 ################################################################
5622 11:35:31.538886
5623 11:35:31.807568 00b00000 ################################################################
5624 11:35:31.807705
5625 11:35:32.055422 00b80000 ################################################################
5626 11:35:32.055549
5627 11:35:32.304832 00c00000 ################################################################
5628 11:35:32.304978
5629 11:35:32.566425 00c80000 ################################################################
5630 11:35:32.566552
5631 11:35:32.818996 00d00000 ################################################################
5632 11:35:32.819132
5633 11:35:33.069332 00d80000 ################################################################
5634 11:35:33.069466
5635 11:35:33.322025 00e00000 ################################################################
5636 11:35:33.322160
5637 11:35:33.575174 00e80000 ################################################################
5638 11:35:33.575355
5639 11:35:33.832870 00f00000 ################################################################
5640 11:35:33.833031
5641 11:35:34.094794 00f80000 ################################################################
5642 11:35:34.094951
5643 11:35:34.361128 01000000 ################################################################
5644 11:35:34.361289
5645 11:35:34.624513 01080000 ################################################################
5646 11:35:34.624650
5647 11:35:34.884296 01100000 ################################################################
5648 11:35:34.884459
5649 11:35:35.139131 01180000 ################################################################
5650 11:35:35.139261
5651 11:35:35.390904 01200000 ################################################################
5652 11:35:35.391062
5653 11:35:35.641420 01280000 ################################################################
5654 11:35:35.641587
5655 11:35:35.890014 01300000 ################################################################
5656 11:35:35.890149
5657 11:35:36.140957 01380000 ################################################################
5658 11:35:36.141123
5659 11:35:36.391866 01400000 ################################################################
5660 11:35:36.392001
5661 11:35:36.644874 01480000 ################################################################
5662 11:35:36.645038
5663 11:35:36.898944 01500000 ################################################################
5664 11:35:36.899082
5665 11:35:37.157545 01580000 ################################################################
5666 11:35:37.157685
5667 11:35:37.423692 01600000 ################################################################
5668 11:35:37.423852
5669 11:35:37.685102 01680000 ################################################################
5670 11:35:37.685238
5671 11:35:37.944406 01700000 ################################################################
5672 11:35:37.944534
5673 11:35:38.195073 01780000 ################################################################
5674 11:35:38.195202
5675 11:35:38.451758 01800000 ################################################################
5676 11:35:38.451895
5677 11:35:38.707385 01880000 ################################################################
5678 11:35:38.707547
5679 11:35:38.959851 01900000 ################################################################
5680 11:35:38.960006
5681 11:35:39.215754 01980000 ################################################################
5682 11:35:39.215886
5683 11:35:39.471988 01a00000 ################################################################
5684 11:35:39.472141
5685 11:35:39.732232 01a80000 ################################################################
5686 11:35:39.732389
5687 11:35:39.988585 01b00000 ################################################################
5688 11:35:39.988747
5689 11:35:40.250129 01b80000 ################################################################
5690 11:35:40.250259
5691 11:35:40.514652 01c00000 ################################################################
5692 11:35:40.514767
5693 11:35:40.766759 01c80000 ################################################################
5694 11:35:40.766925
5695 11:35:41.033735 01d00000 ################################################################
5696 11:35:41.033891
5697 11:35:41.288430 01d80000 ################################################################
5698 11:35:41.288588
5699 11:35:41.506284 01e00000 ###################################################### done.
5700 11:35:41.506414
5701 11:35:41.509429 The bootfile was 31898642 bytes long.
5702 11:35:41.509554
5703 11:35:41.512414 Sending tftp read request... done.
5704 11:35:41.512491
5705 11:35:41.512549 Waiting for the transfer...
5706 11:35:41.512603
5707 11:35:41.515783 00000000 # done.
5708 11:35:41.515873
5709 11:35:41.522696 Command line loaded dynamically from TFTP file: 14864601/tftp-deploy-znwinunr/kernel/cmdline
5710 11:35:41.522778
5711 11:35:41.548554 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5712 11:35:41.548672
5713 11:35:41.552051 Loading FIT.
5714 11:35:41.552147
5715 11:35:41.555225 Image ramdisk-1 has 18720610 bytes.
5716 11:35:41.555326
5717 11:35:41.555412 Image fdt-1 has 57695 bytes.
5718 11:35:41.555510
5719 11:35:41.558409 Image kernel-1 has 13118294 bytes.
5720 11:35:41.558514
5721 11:35:41.568444 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5722 11:35:41.568548
5723 11:35:41.581455 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5724 11:35:41.581575
5725 11:35:41.584576 Choosing best match conf-1 for compat google,juniper-sku16.
5726 11:35:41.589585
5727 11:35:41.594548 Connected to device vid:did:rid of 1ae0:0028:00
5728 11:35:41.602665
5729 11:35:41.605640 tpm_get_response: command 0x17b, return code 0x0
5730 11:35:41.605746
5731 11:35:41.609176 tpm_cleanup: add release locality here.
5732 11:35:41.609281
5733 11:35:41.612177 Shutting down all USB controllers.
5734 11:35:41.612285
5735 11:35:41.615357 Removing current net device
5736 11:35:41.615430
5737 11:35:41.618678 Exiting depthcharge with code 4 at timestamp: 34302307
5738 11:35:41.618783
5739 11:35:41.622275 LZMA decompressing kernel-1 to 0x80193568
5740 11:35:41.625580
5741 11:35:41.629080 LZMA decompressing kernel-1 to 0x40000000
5742 11:35:43.491286
5743 11:35:43.491418 jumping to kernel
5744 11:35:43.491879 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
5745 11:35:43.491972 start: 2.2.5 auto-login-action (timeout 00:04:09) [common]
5746 11:35:43.492041 Setting prompt string to ['Linux version [0-9]']
5747 11:35:43.492112 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5748 11:35:43.492218 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5749 11:35:43.566345
5750 11:35:43.569464 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5751 11:35:43.573153 start: 2.2.5.1 login-action (timeout 00:04:09) [common]
5752 11:35:43.573249 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5753 11:35:43.573318 Setting prompt string to []
5754 11:35:43.573392 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5755 11:35:43.573466 Using line separator: #'\n'#
5756 11:35:43.573522 No login prompt set.
5757 11:35:43.573579 Parsing kernel messages
5758 11:35:43.573631 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5759 11:35:43.573733 [login-action] Waiting for messages, (timeout 00:04:09)
5760 11:35:43.573795 Waiting using forced prompt support (timeout 00:02:04)
5761 11:35:43.592382 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
5762 11:35:43.595741 [ 0.000000] random: crng init done
5763 11:35:43.599494 [ 0.000000] Machine model: Google juniper sku16 board
5764 11:35:43.602471 [ 0.000000] efi: UEFI not found.
5765 11:35:43.612286 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5766 11:35:43.618873 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5767 11:35:43.628817 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5768 11:35:43.632145 [ 0.000000] printk: bootconsole [mtk8250] enabled
5769 11:35:43.640236 [ 0.000000] NUMA: No NUMA configuration found
5770 11:35:43.646878 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5771 11:35:43.653657 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5772 11:35:43.653771 [ 0.000000] Zone ranges:
5773 11:35:43.660337 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5774 11:35:43.663060 [ 0.000000] DMA32 empty
5775 11:35:43.670087 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5776 11:35:43.672992 [ 0.000000] Movable zone start for each node
5777 11:35:43.676260 [ 0.000000] Early memory node ranges
5778 11:35:43.682825 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5779 11:35:43.689702 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5780 11:35:43.696135 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5781 11:35:43.702448 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5782 11:35:43.708968 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5783 11:35:43.716272 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5784 11:35:43.737172 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5785 11:35:43.743950 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5786 11:35:43.750146 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5787 11:35:43.753280 [ 0.000000] psci: probing for conduit method from DT.
5788 11:35:43.759716 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5789 11:35:43.763295 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5790 11:35:43.769615 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5791 11:35:43.772907 [ 0.000000] psci: SMC Calling Convention v1.1
5792 11:35:43.779607 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5793 11:35:43.783038 [ 0.000000] Detected VIPT I-cache on CPU0
5794 11:35:43.789059 [ 0.000000] CPU features: detected: GIC system register CPU interface
5795 11:35:43.795502 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5796 11:35:43.802515 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5797 11:35:43.809461 [ 0.000000] CPU features: detected: ARM erratum 845719
5798 11:35:43.812385 [ 0.000000] alternatives: applying boot alternatives
5799 11:35:43.818500 [ 0.000000] Fallback order for Node 0: 0
5800 11:35:43.825591 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5801 11:35:43.829140 [ 0.000000] Policy zone: Normal
5802 11:35:43.854552 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5803 11:35:43.867672 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5804 11:35:43.874649 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5805 11:35:43.884440 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5806 11:35:43.890628 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5807 11:35:43.893900 <6>[ 0.000000] software IO TLB: area num 8.
5808 11:35:43.920685 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5809 11:35:43.978887 <6>[ 0.000000] Memory: 3896788K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 261676K reserved, 32768K cma-reserved)
5810 11:35:43.985838 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5811 11:35:43.992084 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5812 11:35:43.995547 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5813 11:35:44.001863 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5814 11:35:44.008087 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5815 11:35:44.014545 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5816 11:35:44.021230 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5817 11:35:44.027725 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5818 11:35:44.034480 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5819 11:35:44.044554 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5820 11:35:44.048042 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5821 11:35:44.054190 <6>[ 0.000000] GICv3: 640 SPIs implemented
5822 11:35:44.057303 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5823 11:35:44.060634 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5824 11:35:44.067570 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5825 11:35:44.073764 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5826 11:35:44.087268 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5827 11:35:44.097646 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5828 11:35:44.106797 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5829 11:35:44.115389 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5830 11:35:44.128908 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5831 11:35:44.135224 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5832 11:35:44.142929 <6>[ 0.009464] Console: colour dummy device 80x25
5833 11:35:44.145853 <6>[ 0.014502] printk: console [tty1] enabled
5834 11:35:44.159445 <6>[ 0.018893] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5835 11:35:44.161902 <6>[ 0.029359] pid_max: default: 32768 minimum: 301
5836 11:35:44.168452 <6>[ 0.034239] LSM: Security Framework initializing
5837 11:35:44.175336 <6>[ 0.039154] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5838 11:35:44.181725 <6>[ 0.046776] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5839 11:35:44.188718 <4>[ 0.055660] cacheinfo: Unable to detect cache hierarchy for CPU 0
5840 11:35:44.198857 <6>[ 0.062285] cblist_init_generic: Setting adjustable number of callback queues.
5841 11:35:44.205501 <6>[ 0.069731] cblist_init_generic: Setting shift to 3 and lim to 1.
5842 11:35:44.212106 <6>[ 0.076083] cblist_init_generic: Setting adjustable number of callback queues.
5843 11:35:44.218399 <6>[ 0.083528] cblist_init_generic: Setting shift to 3 and lim to 1.
5844 11:35:44.221546 <6>[ 0.089927] rcu: Hierarchical SRCU implementation.
5845 11:35:44.228553 <6>[ 0.094953] rcu: Max phase no-delay instances is 1000.
5846 11:35:44.235894 <6>[ 0.102854] EFI services will not be available.
5847 11:35:44.238825 <6>[ 0.107802] smp: Bringing up secondary CPUs ...
5848 11:35:44.249704 <6>[ 0.113078] Detected VIPT I-cache on CPU1
5849 11:35:44.255942 <4>[ 0.113126] cacheinfo: Unable to detect cache hierarchy for CPU 1
5850 11:35:44.262721 <6>[ 0.113133] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5851 11:35:44.269893 <6>[ 0.113165] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5852 11:35:44.273155 <6>[ 0.113648] Detected VIPT I-cache on CPU2
5853 11:35:44.279283 <4>[ 0.113682] cacheinfo: Unable to detect cache hierarchy for CPU 2
5854 11:35:44.285710 <6>[ 0.113686] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5855 11:35:44.291991 <6>[ 0.113698] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5856 11:35:44.298915 <6>[ 0.114144] Detected VIPT I-cache on CPU3
5857 11:35:44.305298 <4>[ 0.114174] cacheinfo: Unable to detect cache hierarchy for CPU 3
5858 11:35:44.311776 <6>[ 0.114178] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5859 11:35:44.318529 <6>[ 0.114190] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5860 11:35:44.322517 <6>[ 0.114764] CPU features: detected: Spectre-v2
5861 11:35:44.328311 <6>[ 0.114774] CPU features: detected: Spectre-BHB
5862 11:35:44.331506 <6>[ 0.114778] CPU features: detected: ARM erratum 858921
5863 11:35:44.338099 <6>[ 0.114783] Detected VIPT I-cache on CPU4
5864 11:35:44.341323 <4>[ 0.114831] cacheinfo: Unable to detect cache hierarchy for CPU 4
5865 11:35:44.351165 <6>[ 0.114839] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5866 11:35:44.358165 <6>[ 0.114847] arch_timer: Enabling local workaround for ARM erratum 858921
5867 11:35:44.361937 <6>[ 0.114857] arch_timer: CPU4: Trapping CNTVCT access
5868 11:35:44.367855 <6>[ 0.114865] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5869 11:35:44.374353 <6>[ 0.115352] Detected VIPT I-cache on CPU5
5870 11:35:44.381434 <4>[ 0.115392] cacheinfo: Unable to detect cache hierarchy for CPU 5
5871 11:35:44.387391 <6>[ 0.115398] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5872 11:35:44.394446 <6>[ 0.115405] arch_timer: Enabling local workaround for ARM erratum 858921
5873 11:35:44.400721 <6>[ 0.115411] arch_timer: CPU5: Trapping CNTVCT access
5874 11:35:44.407673 <6>[ 0.115416] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5875 11:35:44.410448 <6>[ 0.115853] Detected VIPT I-cache on CPU6
5876 11:35:44.417166 <4>[ 0.115897] cacheinfo: Unable to detect cache hierarchy for CPU 6
5877 11:35:44.423818 <6>[ 0.115903] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5878 11:35:44.430073 <6>[ 0.115910] arch_timer: Enabling local workaround for ARM erratum 858921
5879 11:35:44.436845 <6>[ 0.115916] arch_timer: CPU6: Trapping CNTVCT access
5880 11:35:44.443391 <6>[ 0.115921] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5881 11:35:44.446566 <6>[ 0.116452] Detected VIPT I-cache on CPU7
5882 11:35:44.453675 <4>[ 0.116496] cacheinfo: Unable to detect cache hierarchy for CPU 7
5883 11:35:44.460130 <6>[ 0.116503] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5884 11:35:44.466484 <6>[ 0.116510] arch_timer: Enabling local workaround for ARM erratum 858921
5885 11:35:44.473190 <6>[ 0.116516] arch_timer: CPU7: Trapping CNTVCT access
5886 11:35:44.479860 <6>[ 0.116521] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5887 11:35:44.482935 <6>[ 0.116589] smp: Brought up 1 node, 8 CPUs
5888 11:35:44.489620 <6>[ 0.355464] SMP: Total of 8 processors activated.
5889 11:35:44.492575 <6>[ 0.360401] CPU features: detected: 32-bit EL0 Support
5890 11:35:44.499439 <6>[ 0.365772] CPU features: detected: 32-bit EL1 Support
5891 11:35:44.505834 <6>[ 0.371139] CPU features: detected: CRC32 instructions
5892 11:35:44.509257 <6>[ 0.376566] CPU: All CPU(s) started at EL2
5893 11:35:44.515619 <6>[ 0.380903] alternatives: applying system-wide alternatives
5894 11:35:44.518821 <6>[ 0.388913] devtmpfs: initialized
5895 11:35:44.537307 <6>[ 0.397858] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5896 11:35:44.544055 <6>[ 0.407807] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5897 11:35:44.550365 <6>[ 0.415531] pinctrl core: initialized pinctrl subsystem
5898 11:35:44.554085 <6>[ 0.422649] DMI not present or invalid.
5899 11:35:44.560182 <6>[ 0.427019] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5900 11:35:44.570272 <6>[ 0.433927] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5901 11:35:44.576924 <6>[ 0.441456] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5902 11:35:44.586352 <6>[ 0.449707] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5903 11:35:44.593387 <6>[ 0.457883] audit: initializing netlink subsys (disabled)
5904 11:35:44.599764 <5>[ 0.463588] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5905 11:35:44.606151 <6>[ 0.464567] thermal_sys: Registered thermal governor 'step_wise'
5906 11:35:44.613191 <6>[ 0.471556] thermal_sys: Registered thermal governor 'power_allocator'
5907 11:35:44.616270 <6>[ 0.477854] cpuidle: using governor menu
5908 11:35:44.623070 <6>[ 0.488816] NET: Registered PF_QIPCRTR protocol family
5909 11:35:44.629907 <6>[ 0.494313] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5910 11:35:44.635719 <6>[ 0.501412] ASID allocator initialised with 32768 entries
5911 11:35:44.639072 <6>[ 0.508179] Serial: AMBA PL011 UART driver
5912 11:35:44.652439 <4>[ 0.519517] Trying to register duplicate clock ID: 113
5913 11:35:44.712165 <6>[ 0.576066] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5914 11:35:44.726468 <6>[ 0.590461] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5915 11:35:44.729908 <6>[ 0.600239] KASLR enabled
5916 11:35:44.744584 <6>[ 0.608207] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5917 11:35:44.751014 <6>[ 0.615209] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5918 11:35:44.757683 <6>[ 0.621684] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5919 11:35:44.764588 <6>[ 0.628676] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5920 11:35:44.770789 <6>[ 0.635149] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5921 11:35:44.777035 <6>[ 0.642140] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5922 11:35:44.784250 <6>[ 0.648613] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5923 11:35:44.790402 <6>[ 0.655602] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5924 11:35:44.793647 <6>[ 0.663171] ACPI: Interpreter disabled.
5925 11:35:44.804270 <6>[ 0.671139] iommu: Default domain type: Translated
5926 11:35:44.810402 <6>[ 0.676247] iommu: DMA domain TLB invalidation policy: strict mode
5927 11:35:44.814088 <5>[ 0.682877] SCSI subsystem initialized
5928 11:35:44.820087 <6>[ 0.687291] usbcore: registered new interface driver usbfs
5929 11:35:44.827751 <6>[ 0.693019] usbcore: registered new interface driver hub
5930 11:35:44.833619 <6>[ 0.698559] usbcore: registered new device driver usb
5931 11:35:44.837034 <6>[ 0.704863] pps_core: LinuxPPS API ver. 1 registered
5932 11:35:44.846640 <6>[ 0.710048] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5933 11:35:44.853529 <6>[ 0.719374] PTP clock support registered
5934 11:35:44.856701 <6>[ 0.723627] EDAC MC: Ver: 3.0.0
5935 11:35:44.859422 <6>[ 0.729255] FPGA manager framework
5936 11:35:44.866355 <6>[ 0.732938] Advanced Linux Sound Architecture Driver Initialized.
5937 11:35:44.869270 <6>[ 0.739700] vgaarb: loaded
5938 11:35:44.876280 <6>[ 0.742829] clocksource: Switched to clocksource arch_sys_counter
5939 11:35:44.882662 <5>[ 0.749260] VFS: Disk quotas dquot_6.6.0
5940 11:35:44.889140 <6>[ 0.753435] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5941 11:35:44.892220 <6>[ 0.760611] pnp: PnP ACPI: disabled
5942 11:35:44.900676 <6>[ 0.767503] NET: Registered PF_INET protocol family
5943 11:35:44.907309 <6>[ 0.772735] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5944 11:35:44.918825 <6>[ 0.782646] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5945 11:35:44.928557 <6>[ 0.791401] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5946 11:35:44.935191 <6>[ 0.799351] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5947 11:35:44.941799 <6>[ 0.807585] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5948 11:35:44.952411 <6>[ 0.815679] TCP: Hash tables configured (established 32768 bind 32768)
5949 11:35:44.958448 <6>[ 0.822506] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5950 11:35:44.964956 <6>[ 0.829481] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5951 11:35:44.971911 <6>[ 0.836960] NET: Registered PF_UNIX/PF_LOCAL protocol family
5952 11:35:44.978521 <6>[ 0.843058] RPC: Registered named UNIX socket transport module.
5953 11:35:44.981338 <6>[ 0.849202] RPC: Registered udp transport module.
5954 11:35:44.987806 <6>[ 0.854127] RPC: Registered tcp transport module.
5955 11:35:44.994648 <6>[ 0.859050] RPC: Registered tcp NFSv4.1 backchannel transport module.
5956 11:35:44.998028 <6>[ 0.865702] PCI: CLS 0 bytes, default 64
5957 11:35:45.001168 <6>[ 0.869989] Unpacking initramfs...
5958 11:35:45.016219 <6>[ 0.879557] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5959 11:35:45.025808 <6>[ 0.888180] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5960 11:35:45.028983 <6>[ 0.897034] kvm [1]: IPA Size Limit: 40 bits
5961 11:35:45.037004 <6>[ 0.903361] kvm [1]: vgic-v2@c420000
5962 11:35:45.039940 <6>[ 0.907178] kvm [1]: GIC system register CPU interface enabled
5963 11:35:45.047903 <6>[ 0.914905] kvm [1]: vgic interrupt IRQ18
5964 11:35:45.051707 <6>[ 0.919268] kvm [1]: Hyp mode initialized successfully
5965 11:35:45.058547 <5>[ 0.925629] Initialise system trusted keyrings
5966 11:35:45.065366 <6>[ 0.930481] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5967 11:35:45.073407 <6>[ 0.940411] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5968 11:35:45.079960 <5>[ 0.946853] NFS: Registering the id_resolver key type
5969 11:35:45.083462 <5>[ 0.952154] Key type id_resolver registered
5970 11:35:45.090043 <5>[ 0.956568] Key type id_legacy registered
5971 11:35:45.096368 <6>[ 0.960881] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5972 11:35:45.102945 <6>[ 0.967806] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5973 11:35:45.109333 <6>[ 0.975560] 9p: Installing v9fs 9p2000 file system support
5974 11:35:45.137919 <5>[ 1.004543] Key type asymmetric registered
5975 11:35:45.141583 <5>[ 1.008888] Asymmetric key parser 'x509' registered
5976 11:35:45.150671 <6>[ 1.014046] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5977 11:35:45.154032 <6>[ 1.021655] io scheduler mq-deadline registered
5978 11:35:45.157154 <6>[ 1.026410] io scheduler kyber registered
5979 11:35:45.180239 <6>[ 1.047171] EINJ: ACPI disabled.
5980 11:35:45.186701 <4>[ 1.050930] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5981 11:35:45.227758 <6>[ 1.091774] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5982 11:35:45.234137 <6>[ 1.100288] printk: console [ttyS0] disabled
5983 11:35:45.261638 <6>[ 1.124941] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5984 11:35:45.268020 <6>[ 1.134417] printk: console [ttyS0] enabled
5985 11:35:45.271124 <6>[ 1.134417] printk: console [ttyS0] enabled
5986 11:35:45.277727 <6>[ 1.143337] printk: bootconsole [mtk8250] disabled
5987 11:35:45.280902 <6>[ 1.143337] printk: bootconsole [mtk8250] disabled
5988 11:35:45.290998 <3>[ 1.153873] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5989 11:35:45.297512 <3>[ 1.162257] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5990 11:35:45.326734 <6>[ 1.190671] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5991 11:35:45.333470 <6>[ 1.200332] serial serial0: tty port ttyS1 registered
5992 11:35:45.340346 <6>[ 1.206931] SuperH (H)SCI(F) driver initialized
5993 11:35:45.343769 <6>[ 1.212432] msm_serial: driver initialized
5994 11:35:45.359251 <6>[ 1.222754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5995 11:35:45.368796 <6>[ 1.231363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5996 11:35:45.375471 <6>[ 1.239939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5997 11:35:45.385529 <6>[ 1.248511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5998 11:35:45.395546 <6>[ 1.257167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5999 11:35:45.402107 <6>[ 1.265829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6000 11:35:45.411743 <6>[ 1.274571] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6001 11:35:45.418339 <6>[ 1.283310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6002 11:35:45.428086 <6>[ 1.291876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6003 11:35:45.437778 <6>[ 1.300674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6004 11:35:45.445742 <4>[ 1.313089] cacheinfo: Unable to detect cache hierarchy for CPU 0
6005 11:35:45.455470 <6>[ 1.322467] loop: module loaded
6006 11:35:45.467178 <6>[ 1.334448] vsim1: Bringing 1800000uV into 2700000-2700000uV
6007 11:35:45.485639 <6>[ 1.352558] megasas: 07.719.03.00-rc1
6008 11:35:45.494256 <6>[ 1.361374] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6009 11:35:45.506357 <6>[ 1.370209] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6010 11:35:45.520023 <6>[ 1.387085] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6011 11:35:45.576832 <6>[ 1.437406] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d
6012 11:35:45.625952 <6>[ 1.492705] Freeing initrd memory: 18280K
6013 11:35:45.640764 <4>[ 1.504581] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6014 11:35:45.647825 <4>[ 1.513811] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6015 11:35:45.654220 <4>[ 1.520509] Hardware name: Google juniper sku16 board (DT)
6016 11:35:45.657426 <4>[ 1.526247] Call trace:
6017 11:35:45.660683 <4>[ 1.528946] dump_backtrace.part.0+0xe0/0xf0
6018 11:35:45.664430 <4>[ 1.533484] show_stack+0x18/0x30
6019 11:35:45.667522 <4>[ 1.537056] dump_stack_lvl+0x64/0x80
6020 11:35:45.674289 <4>[ 1.540976] dump_stack+0x18/0x34
6021 11:35:45.677254 <4>[ 1.544545] sysfs_warn_dup+0x64/0x80
6022 11:35:45.680864 <4>[ 1.548467] sysfs_do_create_link_sd+0xf0/0x100
6023 11:35:45.684056 <4>[ 1.553255] sysfs_create_link+0x20/0x40
6024 11:35:45.690668 <4>[ 1.557434] bus_add_device+0x64/0x120
6025 11:35:45.694045 <4>[ 1.561440] device_add+0x354/0x7ec
6026 11:35:45.697480 <4>[ 1.565186] of_device_add+0x44/0x60
6027 11:35:45.704480 <4>[ 1.569020] of_platform_device_create_pdata+0x90/0x124
6028 11:35:45.707064 <4>[ 1.574502] of_platform_bus_create+0x154/0x380
6029 11:35:45.710283 <4>[ 1.579287] of_platform_populate+0x50/0xfc
6030 11:35:45.717345 <4>[ 1.583726] parse_mtd_partitions+0x1d8/0x4e0
6031 11:35:45.720436 <4>[ 1.588342] mtd_device_parse_register+0xec/0x2e0
6032 11:35:45.723977 <4>[ 1.593304] spi_nor_probe+0x280/0x2f4
6033 11:35:45.730557 <4>[ 1.597309] spi_mem_probe+0x6c/0xc0
6034 11:35:45.733882 <4>[ 1.601140] spi_probe+0x84/0xe4
6035 11:35:45.737582 <4>[ 1.604626] really_probe+0xbc/0x2dc
6036 11:35:45.740554 <4>[ 1.608456] __driver_probe_device+0x78/0x114
6037 11:35:45.746887 <4>[ 1.613068] driver_probe_device+0xd8/0x15c
6038 11:35:45.750552 <4>[ 1.617505] __device_attach_driver+0xb8/0x134
6039 11:35:45.753779 <4>[ 1.622203] bus_for_each_drv+0x7c/0xd4
6040 11:35:45.756833 <4>[ 1.626296] __device_attach+0x9c/0x1a0
6041 11:35:45.764018 <4>[ 1.630386] device_initial_probe+0x14/0x20
6042 11:35:45.766846 <4>[ 1.634824] bus_probe_device+0x98/0xa0
6043 11:35:45.770425 <4>[ 1.638913] device_add+0x3c0/0x7ec
6044 11:35:45.773324 <4>[ 1.642658] __spi_add_device+0x78/0x120
6045 11:35:45.780263 <4>[ 1.646836] spi_add_device+0x44/0x80
6046 11:35:45.783459 <4>[ 1.650754] spi_register_controller+0x704/0xb20
6047 11:35:45.790095 <4>[ 1.655626] devm_spi_register_controller+0x4c/0xac
6048 11:35:45.793560 <4>[ 1.660760] mtk_spi_probe+0x4f4/0x684
6049 11:35:45.796916 <4>[ 1.664765] platform_probe+0x68/0xc0
6050 11:35:45.800044 <4>[ 1.668684] really_probe+0xbc/0x2dc
6051 11:35:45.806630 <4>[ 1.672514] __driver_probe_device+0x78/0x114
6052 11:35:45.810168 <4>[ 1.677126] driver_probe_device+0xd8/0x15c
6053 11:35:45.813107 <4>[ 1.681563] __driver_attach+0x94/0x19c
6054 11:35:45.816236 <4>[ 1.685652] bus_for_each_dev+0x74/0xd0
6055 11:35:45.822804 <4>[ 1.689744] driver_attach+0x24/0x30
6056 11:35:45.826151 <4>[ 1.693574] bus_add_driver+0x154/0x20c
6057 11:35:45.829826 <4>[ 1.697664] driver_register+0x78/0x130
6058 11:35:45.836225 <4>[ 1.701754] __platform_driver_register+0x28/0x34
6059 11:35:45.839531 <4>[ 1.706713] mtk_spi_driver_init+0x1c/0x28
6060 11:35:45.843288 <4>[ 1.711068] do_one_initcall+0x64/0x1dc
6061 11:35:45.846508 <4>[ 1.715158] kernel_init_freeable+0x218/0x284
6062 11:35:45.852789 <4>[ 1.719773] kernel_init+0x24/0x12c
6063 11:35:45.856328 <4>[ 1.723519] ret_from_fork+0x10/0x20
6064 11:35:45.865711 <6>[ 1.732416] tun: Universal TUN/TAP device driver, 1.6
6065 11:35:45.868968 <6>[ 1.738703] thunder_xcv, ver 1.0
6066 11:35:45.875713 <6>[ 1.742221] thunder_bgx, ver 1.0
6067 11:35:45.875791 <6>[ 1.745727] nicpf, ver 1.0
6068 11:35:45.886766 <6>[ 1.750102] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6069 11:35:45.889904 <6>[ 1.757587] hns3: Copyright (c) 2017 Huawei Corporation.
6070 11:35:45.896725 <6>[ 1.763184] hclge is initializing
6071 11:35:45.900180 <6>[ 1.766765] e1000: Intel(R) PRO/1000 Network Driver
6072 11:35:45.906269 <6>[ 1.771901] e1000: Copyright (c) 1999-2006 Intel Corporation.
6073 11:35:45.909542 <6>[ 1.777922] e1000e: Intel(R) PRO/1000 Network Driver
6074 11:35:45.916248 <6>[ 1.783144] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6075 11:35:45.922882 <6>[ 1.789337] igb: Intel(R) Gigabit Ethernet Network Driver
6076 11:35:45.929625 <6>[ 1.794992] igb: Copyright (c) 2007-2014 Intel Corporation.
6077 11:35:45.936558 <6>[ 1.800837] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6078 11:35:45.942748 <6>[ 1.807360] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6079 11:35:45.946315 <6>[ 1.813915] sky2: driver version 1.30
6080 11:35:45.953109 <6>[ 1.819178] usbcore: registered new device driver r8152-cfgselector
6081 11:35:45.959581 <6>[ 1.825720] usbcore: registered new interface driver r8152
6082 11:35:45.966399 <6>[ 1.831553] VFIO - User Level meta-driver version: 0.3
6083 11:35:45.972588 <6>[ 1.839349] mtu3 11201000.usb: uwk - reg:0x420, version:101
6084 11:35:45.979583 <4>[ 1.845226] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6085 11:35:45.985871 <6>[ 1.852501] mtu3 11201000.usb: dr_mode: 1, drd: auto
6086 11:35:45.992514 <6>[ 1.857729] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6087 11:35:45.995635 <6>[ 1.863918] mtu3 11201000.usb: usb3-drd: 0
6088 11:35:46.005849 <6>[ 1.869495] mtu3 11201000.usb: xHCI platform device register success...
6089 11:35:46.012763 <4>[ 1.878120] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6090 11:35:46.018990 <6>[ 1.886064] xhci-mtk 11200000.usb: xHCI Host Controller
6091 11:35:46.026095 <6>[ 1.891569] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6092 11:35:46.032263 <6>[ 1.899287] xhci-mtk 11200000.usb: USB3 root hub has no ports
6093 11:35:46.042801 <6>[ 1.905295] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6094 11:35:46.049238 <6>[ 1.914720] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6095 11:35:46.056532 <6>[ 1.920796] xhci-mtk 11200000.usb: xHCI Host Controller
6096 11:35:46.062163 <6>[ 1.926285] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6097 11:35:46.068811 <6>[ 1.933942] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6098 11:35:46.072467 <6>[ 1.940763] hub 1-0:1.0: USB hub found
6099 11:35:46.078594 <6>[ 1.944791] hub 1-0:1.0: 1 port detected
6100 11:35:46.084927 <6>[ 1.950164] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6101 11:35:46.091695 <6>[ 1.958792] hub 2-0:1.0: USB hub found
6102 11:35:46.098476 <3>[ 1.962828] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6103 11:35:46.104984 <6>[ 1.970705] usbcore: registered new interface driver usb-storage
6104 11:35:46.111785 <6>[ 1.977302] usbcore: registered new device driver onboard-usb-hub
6105 11:35:46.123694 <4>[ 1.986931] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6106 11:35:46.132153 <6>[ 1.999169] mt6397-rtc mt6358-rtc: registered as rtc0
6107 11:35:46.142261 <6>[ 2.004651] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-17T11:35:30 UTC (1721216130)
6108 11:35:46.149312 <6>[ 2.014533] i2c_dev: i2c /dev entries driver
6109 11:35:46.158465 <6>[ 2.020964] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6110 11:35:46.165283 <6>[ 2.029283] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6111 11:35:46.171434 <6>[ 2.038186] i2c 4-0058: Fixed dependency cycle(s) with /panel
6112 11:35:46.177925 <6>[ 2.044217] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6113 11:35:46.196682 <6>[ 2.063639] cpu cpu0: EM: created perf domain
6114 11:35:46.206631 <6>[ 2.069146] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6115 11:35:46.213211 <6>[ 2.080428] cpu cpu4: EM: created perf domain
6116 11:35:46.220367 <6>[ 2.087174] sdhci: Secure Digital Host Controller Interface driver
6117 11:35:46.227186 <6>[ 2.093628] sdhci: Copyright(c) Pierre Ossman
6118 11:35:46.233659 <6>[ 2.099026] Synopsys Designware Multimedia Card Interface Driver
6119 11:35:46.240156 <6>[ 2.099536] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6120 11:35:46.243718 <6>[ 2.106092] sdhci-pltfm: SDHCI platform and OF driver helper
6121 11:35:46.252433 <6>[ 2.119314] ledtrig-cpu: registered to indicate activity on CPUs
6122 11:35:46.260000 <6>[ 2.127086] usbcore: registered new interface driver usbhid
6123 11:35:46.263524 <6>[ 2.132930] usbhid: USB HID core driver
6124 11:35:46.274257 <6>[ 2.137217] spi_master spi2: will run message pump with realtime priority
6125 11:35:46.277979 <4>[ 2.137229] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6126 11:35:46.288115 <4>[ 2.151509] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6127 11:35:46.301557 <6>[ 2.155052] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6128 11:35:46.315211 <6>[ 2.174030] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6129 11:35:46.321372 <4>[ 2.184540] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6130 11:35:46.327808 <6>[ 2.194880] cros-ec-spi spi2.0: Chrome EC device registered
6131 11:35:46.339412 <4>[ 2.202748] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6132 11:35:46.350690 <4>[ 2.214161] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6133 11:35:46.357268 <4>[ 2.223038] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6134 11:35:46.369491 <6>[ 2.233032] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6135 11:35:46.383548 <6>[ 2.250315] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
6136 11:35:46.391172 <6>[ 2.257960] mmc0: new HS400 MMC card at address 0001
6137 11:35:46.397818 <6>[ 2.263945] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6138 11:35:46.406262 <6>[ 2.272876] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6139 11:35:46.414562 <6>[ 2.281373] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6140 11:35:46.424108 <6>[ 2.286036] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6141 11:35:46.427902 <6>[ 2.287932] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6142 11:35:46.440823 <6>[ 2.299489] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6143 11:35:46.447358 <6>[ 2.301521] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6144 11:35:46.457678 <6>[ 2.303038] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6145 11:35:46.467890 <6>[ 2.303264] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6146 11:35:46.474339 <6>[ 2.312950] NET: Registered PF_PACKET protocol family
6147 11:35:46.478110 <6>[ 2.345408] 9pnet: Installing 9P2000 support
6148 11:35:46.484077 <5>[ 2.350182] Key type dns_resolver registered
6149 11:35:46.487413 <6>[ 2.355415] registered taskstats version 1
6150 11:35:46.493805 <5>[ 2.359875] Loading compiled-in X.509 certificates
6151 11:35:46.511320 <6>[ 2.374846] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6152 11:35:46.541100 <3>[ 2.404842] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6153 11:35:46.571899 <6>[ 2.432487] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6154 11:35:46.582585 <6>[ 2.446333] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6155 11:35:46.592378 <6>[ 2.454918] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6156 11:35:46.599738 <6>[ 2.463450] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6157 11:35:46.608638 <6>[ 2.471974] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6158 11:35:46.615444 <6>[ 2.480499] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6159 11:35:46.625510 <6>[ 2.489023] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6160 11:35:46.635598 <6>[ 2.497544] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6161 11:35:46.641953 <6>[ 2.506748] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6162 11:35:46.648525 <6>[ 2.514294] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6163 11:35:46.655340 <6>[ 2.521608] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6164 11:35:46.665539 <6>[ 2.528922] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6165 11:35:46.668843 <6>[ 2.530733] hub 1-1:1.0: USB hub found
6166 11:35:46.675154 <6>[ 2.536429] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6167 11:35:46.678860 <6>[ 2.540111] hub 1-1:1.0: 3 ports detected
6168 11:35:46.685096 <6>[ 2.548027] panfrost 13040000.gpu: clock rate = 511999970
6169 11:35:46.695214 <6>[ 2.556284] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6170 11:35:46.701255 <6>[ 2.566683] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6171 11:35:46.711277 <6>[ 2.574713] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6172 11:35:46.724781 <6>[ 2.583149] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6173 11:35:46.731221 <6>[ 2.595225] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6174 11:35:46.743040 <6>[ 2.606611] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6175 11:35:46.752951 <6>[ 2.615874] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6176 11:35:46.763342 <6>[ 2.625050] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6177 11:35:46.772650 <6>[ 2.634180] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6178 11:35:46.779141 <6>[ 2.643309] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6179 11:35:46.788789 <6>[ 2.652610] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6180 11:35:46.799220 <6>[ 2.661914] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6181 11:35:46.808880 <6>[ 2.671389] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6182 11:35:46.818644 <6>[ 2.680864] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6183 11:35:46.828336 <6>[ 2.689990] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6184 11:35:46.898687 <6>[ 2.762457] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6185 11:35:46.909026 <6>[ 2.771351] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6186 11:35:46.918966 <6>[ 2.782814] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6187 11:35:46.975744 <6>[ 2.838987] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6188 11:35:47.621564 <6>[ 3.023293] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6189 11:35:47.631495 <4>[ 3.126557] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6190 11:35:47.637806 <4>[ 3.126575] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6191 11:35:47.644501 <6>[ 3.163839] r8152 1-1.2:1.0 eth0: v1.12.13
6192 11:35:47.651243 <6>[ 3.242861] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6193 11:35:47.657860 <6>[ 3.468572] Console: switching to colour frame buffer device 170x48
6194 11:35:47.667737 <6>[ 3.530438] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6195 11:35:47.688012 <6>[ 3.548493] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6196 11:35:47.706771 <6>[ 3.566490] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6197 11:35:47.715949 <6>[ 3.579064] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6198 11:35:47.722708 <6>[ 3.587949] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6199 11:35:47.735967 <6>[ 3.595922] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6200 11:35:47.753639 <6>[ 3.614101] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6201 11:35:49.004443 <6>[ 4.871611] r8152 1-1.2:1.0 eth0: carrier on
6202 11:35:49.051857 <5>[ 4.894854] Sending DHCP requests ., OK
6203 11:35:49.058422 <6>[ 4.923139] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.20
6204 11:35:49.061590 <6>[ 4.931592] IP-Config: Complete:
6205 11:35:49.074725 <6>[ 4.935190] device=eth0, hwaddr=00:e0:4c:72:3d:a6, ipaddr=192.168.201.20, mask=255.255.255.0, gw=192.168.201.1
6206 11:35:49.085163 <6>[ 4.946095] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4, domain=lava-rack, nis-domain=(none)
6207 11:35:49.096827 <6>[ 4.960438] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6208 11:35:49.105362 <6>[ 4.960448] nameserver0=192.168.201.1
6209 11:35:49.113278 <6>[ 4.980309] clk: Disabling unused clocks
6210 11:35:49.118239 <6>[ 4.988273] ALSA device list:
6211 11:35:49.126954 <6>[ 4.994169] No soundcards found.
6212 11:35:49.136057 <6>[ 5.003198] Freeing unused kernel memory: 8512K
6213 11:35:49.143236 <6>[ 5.010327] Run /init as init process
6214 11:35:49.155786 Loading, please wait...
6215 11:35:49.187891 Starting systemd-udevd version 252.22-1~deb12u1
6216 11:35:49.542158 <3>[ 5.409241] mtk-scp 10500000.scp: invalid resource
6217 11:35:49.552064 <6>[ 5.409506] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6218 11:35:49.562075 <6>[ 5.414393] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6219 11:35:49.565143 <3>[ 5.427646] thermal_sys: Failed to find 'trips' node
6220 11:35:49.572036 <4>[ 5.436949] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6221 11:35:49.581851 <3>[ 5.437998] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6222 11:35:49.591886 <3>[ 5.445333] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6223 11:35:49.598751 <3>[ 5.452611] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6224 11:35:49.605236 <6>[ 5.455331] remoteproc remoteproc0: scp is available
6225 11:35:49.611917 <4>[ 5.455355] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6226 11:35:49.621428 <4>[ 5.455487] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6227 11:35:49.624644 <6>[ 5.455496] remoteproc remoteproc0: powering up scp
6228 11:35:49.635398 <4>[ 5.455524] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6229 11:35:49.642117 <3>[ 5.455529] remoteproc remoteproc0: request_firmware failed: -2
6230 11:35:49.648165 <3>[ 5.462614] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6231 11:35:49.662432 <3>[ 5.462622] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6232 11:35:49.672172 <4>[ 5.471381] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6233 11:35:49.682123 <6>[ 5.472646] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6234 11:35:49.688578 <3>[ 5.476314] elan_i2c 2-0015: Error applying setting, reverse things back
6235 11:35:49.695445 <3>[ 5.487741] thermal_sys: Failed to find 'trips' node
6236 11:35:49.697930 <6>[ 5.503004] mc: Linux media interface: v0.10
6237 11:35:49.705010 <3>[ 5.507591] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6238 11:35:49.711202 <6>[ 5.551183] videodev: Linux video capture interface: v2.00
6239 11:35:49.718627 <3>[ 5.553065] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6240 11:35:49.727825 <3>[ 5.554472] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6241 11:35:49.737910 <3>[ 5.554497] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6242 11:35:49.744855 <3>[ 5.554505] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6243 11:35:49.754163 <3>[ 5.562006] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6244 11:35:49.761154 <6>[ 5.564898] cs_system_cfg: CoreSight Configuration manager initialised
6245 11:35:49.767361 <4>[ 5.565198] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6246 11:35:49.777602 <3>[ 5.569710] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6247 11:35:49.787813 <6>[ 5.571605] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6248 11:35:49.797767 <4>[ 5.578877] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6249 11:35:49.808548 <3>[ 5.582874] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6250 11:35:49.821939 <6>[ 5.591786] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6251 11:35:49.831919 <3>[ 5.600016] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6252 11:35:49.845790 <6>[ 5.609920] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6253 11:35:49.855112 <3>[ 5.617060] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6254 11:35:49.868732 <3>[ 5.625753] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6255 11:35:49.879688 <3>[ 5.632416] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6256 11:35:49.889982 <6>[ 5.658296] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6257 11:35:49.953921 <3>[ 5.814420] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6258 11:35:49.963901 <6>[ 5.827364] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6259 11:35:49.970219 <5>[ 5.828748] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6260 11:35:49.977155 <3>[ 5.829306] debugfs: File 'Playback' in directory 'dapm' already present!
6261 11:35:49.988123 <3>[ 5.829318] debugfs: File 'Capture' in directory 'dapm' already present!
6262 11:35:49.998849 <6>[ 5.831039] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6263 11:35:50.004973 <6>[ 5.835537] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6264 11:35:50.013009 <6>[ 5.851232] Bluetooth: Core ver 2.22
6265 11:35:50.020242 <6>[ 5.852163] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6266 11:35:50.026431 <6>[ 5.853283] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6267 11:35:50.033513 <5>[ 5.856616] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6268 11:35:50.043366 <5>[ 5.857096] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6269 11:35:50.049433 <4>[ 5.857192] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6270 11:35:50.056298 <6>[ 5.857199] cfg80211: failed to load regulatory.db
6271 11:35:50.063166 <6>[ 5.859474] NET: Registered PF_BLUETOOTH protocol family
6272 11:35:50.069628 <6>[ 5.877898] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6273 11:35:50.076240 <6>[ 5.880581] Bluetooth: HCI device and connection manager initialized
6274 11:35:50.083249 <6>[ 5.883989] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6275 11:35:50.089264 <6>[ 5.884774] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video2
6276 11:35:50.102736 <6>[ 5.884853] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6277 11:35:50.109145 <6>[ 5.885010] usbcore: registered new interface driver uvcvideo
6278 11:35:50.115520 <6>[ 5.891845] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6279 11:35:50.123327 <6>[ 5.892089] Bluetooth: HCI socket layer initialized
6280 11:35:50.126718 <6>[ 5.892096] Bluetooth: L2CAP socket layer initialized
6281 11:35:50.133382 <6>[ 5.892228] Bluetooth: SCO socket layer initialized
6282 11:35:50.140915 <6>[ 5.898585] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video3 (81,3)
6283 11:35:50.147687 <6>[ 5.905171] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6284 11:35:50.154526 Begin: Loading e<6>[ 5.929123] Bluetooth: HCI UART driver ver 2.3
6285 11:35:50.163994 ssential drivers<6>[ 5.934653] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6286 11:35:50.164105 ... done.
6287 11:35:50.170325 Begi<6>[ 5.941275] Bluetooth: HCI UART protocol H4 registered
6288 11:35:50.177286 n: Running /scri<6>[ 5.941310] Bluetooth: HCI UART protocol LL registered
6289 11:35:50.186973 pts/init-premoun<6>[ 5.947968] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6290 11:35:50.187069 t ... done.
6291 11:35:50.193849 Beg<6>[ 5.954108] Bluetooth: HCI UART protocol Three-wire (H5) registered
6292 11:35:50.204511 in: Mounting roo<6>[ 5.961907] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6293 11:35:50.216898 t file system ..<6>[ 5.969004] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6294 11:35:50.226968 . Begin: Running<6>[ 5.969018] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6295 11:35:50.236646 /scripts/nfs-to<6>[ 5.969365] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6296 11:35:50.239878 p ... done.
6297 11:35:50.246722 Beg<6>[ 5.973794] Bluetooth: HCI UART protocol Broadcom registered
6298 11:35:50.256750 in: Running /scr<4>[ 5.988181] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6299 11:35:50.259570 <4>[ 5.988181] Fallback method does not support PEC.
6300 11:35:50.269814 ipts/nfs-premount ... Waiting up to 60 secs for <6>[ 5.988240] Bluetooth: HCI UART protocol QCA registered
6301 11:35:50.273342 any ethernet to become available
6302 11:35:50.279330 Device /sys/cl<6>[ 5.989850] Bluetooth: hci0: setting up ROME/QCA6390
6303 11:35:50.283197 ass/net/eth0 found
6304 11:35:50.283289 done.
6305 11:35:50.292563 Begin: Waiting up to <3>[ 5.995699] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6306 11:35:50.302278 180 secs for any network device to become availa<6>[ 5.998650] Bluetooth: HCI UART protocol Marvell registered
6307 11:35:50.302369 ble ... done.
6308 11:35:50.314486 <3>[ 6.009663] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6309 11:35:50.326475 <6>[ 6.117524] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6310 11:35:50.341609 <3>[ 6.202173] Bluetooth: hci0: Frame reassembly failed (-84)
6311 11:35:50.344288 IP-Config: eth0 hardware address 00:e0:4c:72:3d:a6 mtu 1500 DHCP
6312 11:35:50.359624 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6313 11:35:50.366444 address: 192.168.201.20 broadcast: 192.168.201.255 netmask: 255.255.255.0
6314 11:35:50.373148 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6315 11:35:50.379586 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-4
6316 11:35:50.386150 domain : lava-rack
6317 11:35:50.389692 rootserver: 192.168.201.1 rootpath:
6318 11:35:50.392874 filename :
6319 11:35:50.427494 done.
6320 11:35:50.435300 Begin: Running /scripts/nfs-bottom ... done.
6321 11:35:50.450707 Begin: Running /scripts/init-bottom ... done.
6322 11:35:50.604725 <6>[ 6.471398] Bluetooth: hci0: QCA Product ID :0x00000008
6323 11:35:50.613906 <6>[ 6.480823] Bluetooth: hci0: QCA SOC Version :0x00000044
6324 11:35:50.623152 <6>[ 6.490036] Bluetooth: hci0: QCA ROM Version :0x00000302
6325 11:35:50.632824 <6>[ 6.499742] Bluetooth: hci0: QCA Patch Version:0x00000111
6326 11:35:50.643112 <6>[ 6.509741] Bluetooth: hci0: QCA controller version 0x00440302
6327 11:35:50.655851 <6>[ 6.519289] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6328 11:35:50.669212 <4>[ 6.532526] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6329 11:35:50.681364 <3>[ 6.544735] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6330 11:35:50.689465 <3>[ 6.555840] Bluetooth: hci0: QCA Failed to download patch (-2)
6331 11:35:50.708819 <6>[ 6.572445] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6332 11:35:50.791311 <4>[ 6.654882] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6333 11:35:50.810403 <4>[ 6.674008] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6334 11:35:50.826545 <4>[ 6.689623] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6335 11:35:50.836281 <4>[ 6.702852] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6336 11:35:51.801156 <6>[ 7.667836] NET: Registered PF_INET6 protocol family
6337 11:35:51.813353 <6>[ 7.680283] Segment Routing with IPv6
6338 11:35:51.821558 <6>[ 7.688428] In-situ OAM (IOAM) with IPv6
6339 11:35:51.998128 <30>[ 7.835592] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6340 11:35:52.015485 <30>[ 7.882379] systemd[1]: Detected architecture arm64.
6341 11:35:52.024957
6342 11:35:52.028552 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6343 11:35:52.028622
6344 11:35:52.052429 <30>[ 7.919242] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6345 11:35:52.780099 <3>[ 8.646878] Bluetooth: hci0: command 0x1002 tx timeout
6346 11:35:52.787120 <3>[ 8.647063] Bluetooth: hci0: Opcode 0x1002 failed: -110
6347 11:35:52.997936 <30>[ 8.861671] systemd[1]: Queued start job for default target graphical.target.
6348 11:35:53.042164 <30>[ 8.905790] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6349 11:35:53.054263 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6350 11:35:53.073486 <30>[ 8.937253] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6351 11:35:53.087647 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6352 11:35:53.107243 <30>[ 8.970392] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6353 11:35:53.121384 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6354 11:35:53.140885 <30>[ 9.004474] systemd[1]: Created slice user.slice - User and Session Slice.
6355 11:35:53.153202 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6356 11:35:53.175461 <30>[ 9.035595] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6357 11:35:53.188372 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6358 11:35:53.211430 <30>[ 9.071292] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6359 11:35:53.223142 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6360 11:35:53.249325 <30>[ 9.103235] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6361 11:35:53.269502 <30>[ 9.132998] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6362 11:35:53.278144 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6363 11:35:53.295321 <30>[ 9.159025] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6364 11:35:53.308367 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6365 11:35:53.327667 <30>[ 9.191073] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6366 11:35:53.341715 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6367 11:35:53.356609 <30>[ 9.223506] systemd[1]: Reached target paths.target - Path Units.
6368 11:35:53.371659 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6369 11:35:53.387535 <30>[ 9.251048] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6370 11:35:53.399919 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6371 11:35:53.416689 <30>[ 9.283389] systemd[1]: Reached target slices.target - Slice Units.
6372 11:35:53.431738 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6373 11:35:53.443983 <30>[ 9.311075] systemd[1]: Reached target swap.target - Swaps.
6374 11:35:53.454717 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6375 11:35:53.475702 <30>[ 9.339111] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6376 11:35:53.489515 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6377 11:35:53.508281 <30>[ 9.372035] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6378 11:35:53.522381 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6379 11:35:53.543693 <30>[ 9.406776] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6380 11:35:53.556571 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6381 11:35:53.576585 <30>[ 9.440398] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6382 11:35:53.591050 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6383 11:35:53.608505 <30>[ 9.471764] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6384 11:35:53.620698 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6385 11:35:53.641216 <30>[ 9.504822] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6386 11:35:53.654956 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6387 11:35:53.674016 <30>[ 9.537701] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6388 11:35:53.687200 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6389 11:35:53.703934 <30>[ 9.567666] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6390 11:35:53.717316 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6391 11:35:53.756486 <30>[ 9.620130] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6392 11:35:53.766969 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6393 11:35:53.791393 <30>[ 9.654799] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6394 11:35:53.803873 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6395 11:35:53.827343 <30>[ 9.690785] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6396 11:35:53.838770 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6397 11:35:53.866897 <30>[ 9.723758] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6398 11:35:53.891506 <30>[ 9.754767] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6399 11:35:53.905888 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6400 11:35:53.929837 <30>[ 9.793175] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6401 11:35:53.942150 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6402 11:35:53.988348 <30>[ 9.852036] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6403 11:35:54.000872 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6404 11:35:54.027341 <30>[ 9.890770] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6405 11:35:54.043124 Startin<6>[ 9.904186] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6406 11:35:54.046276 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6407 11:35:54.071009 <30>[ 9.934172] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6408 11:35:54.085206 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6409 11:35:54.107689 <30>[ 9.971318] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6410 11:35:54.121130 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6411 11:35:54.158144 <6>[ 10.025276] fuse: init (API version 7.37)
6412 11:35:54.176396 <30>[ 10.039795] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6413 11:35:54.188521 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6414 11:35:54.217598 <30>[ 10.080932] systemd[1]: Starting systemd-journald.service - Journal Service...
6415 11:35:54.227355 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6416 11:35:54.254844 <30>[ 10.118212] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6417 11:35:54.265483 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6418 11:35:54.290664 <30>[ 10.150740] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6419 11:35:54.301112 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6420 11:35:54.348573 <30>[ 10.211667] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6421 11:35:54.362646 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6422 11:35:54.383543 <30>[ 10.247308] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6423 11:35:54.395538 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6424 11:35:54.417387 <30>[ 10.280632] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6425 11:35:54.423908 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6426 11:35:54.445030 <30>[ 10.307632] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6427 11:35:54.451377 <3>[ 10.308194] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6428 11:35:54.469899 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 10.332000] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6429 11:35:54.470018 File System.
6430 11:35:54.487884 <3>[ 10.351174] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6431 11:35:54.495405 <30>[ 10.352051] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6432 11:35:54.504927 <3>[ 10.366259] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6433 11:35:54.525575 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 10.387904] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6434 11:35:54.525679 File System.
6435 11:35:54.540709 <3>[ 10.403227] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6436 11:35:54.551631 <30>[ 10.412694] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6437 11:35:54.557811 <3>[ 10.420086] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6438 11:35:54.571663 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6439 11:35:54.578502 <3>[ 10.441494] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6440 11:35:54.586709 <30>[ 10.452628] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6441 11:35:54.600340 <30>[ 10.462510] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6442 11:35:54.609951 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6443 11:35:54.628468 <30>[ 10.491795] systemd[1]: Started systemd-journald.service - Journal Service.
6444 11:35:54.640116 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6445 11:35:54.665066 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6446 11:35:54.686626 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6447 11:35:54.710695 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6448 11:35:54.735140 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6449 11:35:54.758953 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6450 11:35:54.777541 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6451 11:35:54.798111 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6452 11:35:54.817169 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6453 11:35:54.838946 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6454 11:35:54.894195 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System..<4>[ 10.749392] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6455 11:35:54.894312 .
6456 11:35:54.904850 <3>[ 10.768258] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6457 11:35:54.921517 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6458 11:35:54.949406 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6459 11:35:54.976375 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6460 11:35:55.002999 Starting [0;1;39msystemd-sysctl.se…c<46>[ 10.866285] systemd-journald[319]: Received client request to flush runtime journal.
6461 11:35:55.009610 e[0m - Apply Kernel Variables...
6462 11:35:55.034698 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6463 11:35:55.064744 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6464 11:35:55.084969 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6465 11:35:55.105191 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6466 11:35:55.126885 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6467 11:35:55.146191 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6468 11:35:56.119075 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6469 11:35:56.156597 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6470 11:35:56.473244 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6471 11:35:56.562845 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6472 11:35:56.584521 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6473 11:35:56.603839 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6474 11:35:56.649071 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6475 11:35:56.673909 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6476 11:35:56.907742 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6477 11:35:56.924341 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6478 11:35:57.004861 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6479 11:35:57.174219 <4>[ 13.040600] power_supply_show_property: 4 callbacks suppressed
6480 11:35:57.184045 <3>[ 13.040611] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6481 11:35:57.199151 Starting [0;1;39msystemd-timesyncd… - Network Time S<3>[ 13.061864] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6482 11:35:57.202023 ynchronization...
6483 11:35:57.222644 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6484 11:35:57.241092 <3>[ 13.104004] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6485 11:35:57.256377 <3>[ 13.119326] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6486 11:35:57.264387 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6487 11:35:57.274318 <3>[ 13.137470] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6488 11:35:57.290550 <3>[ 13.153912] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6489 11:35:57.306923 <3>[ 13.170207] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6490 11:35:57.321902 <3>[ 13.185051] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6491 11:35:57.338235 <3>[ 13.200962] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6492 11:35:57.352593 <3>[ 13.215748] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6493 11:35:57.434173 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6494 11:35:57.491816 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6495 11:35:57.512142 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6496 11:35:57.528674 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6497 11:35:57.544265 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6498 11:35:57.592467 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6499 11:35:57.612859 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6500 11:35:57.637039 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6501 11:35:57.659721 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6502 11:35:57.679258 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6503 11:35:57.700681 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6504 11:35:57.716296 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6505 11:35:57.736221 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6506 11:35:57.757788 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6507 11:35:57.779724 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6508 11:35:57.796743 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6509 11:35:57.824569 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6510 11:35:57.846993 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6511 11:35:57.864645 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6512 11:35:57.882349 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6513 11:35:57.900431 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6514 11:35:57.917063 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6515 11:35:57.958979 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6516 11:35:57.995088 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6517 11:35:58.070027 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6518 11:35:58.095471 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6519 11:35:58.118435 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6520 11:35:58.288973 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6521 11:35:58.349119 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6522 11:35:58.377569 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6523 11:35:58.402154 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6524 11:35:58.420710 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6525 11:35:58.440989 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6526 11:35:58.476533 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6527 11:35:58.502890 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6528 11:35:58.527697 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6529 11:35:58.545353 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6530 11:35:58.593759 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6531 11:35:58.644748 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6532 11:35:58.735529
6533 11:35:58.738806 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6534 11:35:58.738885
6535 11:35:58.741946 debian-bookworm-arm64 login: root (automatic login)
6536 11:35:58.742070
6537 11:35:58.978611 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
6538 11:35:58.978755
6539 11:35:58.985128 The programs included with the Debian GNU/Linux system are free software;
6540 11:35:58.992030 the exact distribution terms for each program are described in the
6541 11:35:58.995352 individual files in /usr/share/doc/*/copyright.
6542 11:35:58.995472
6543 11:35:59.002162 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6544 11:35:59.005195 permitted by applicable law.
6545 11:35:59.058779 Matched prompt #10: / #
6547 11:35:59.059116 Setting prompt string to ['/ #']
6548 11:35:59.059241 end: 2.2.5.1 login-action (duration 00:00:15) [common]
6550 11:35:59.059514 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
6551 11:35:59.059627 start: 2.2.6 expect-shell-connection (timeout 00:03:53) [common]
6552 11:35:59.059714 Setting prompt string to ['/ #']
6553 11:35:59.059795 Forcing a shell prompt, looking for ['/ #']
6554 11:35:59.059877 Sending line: ''
6556 11:35:59.110289 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6557 11:35:59.110391 Waiting using forced prompt support (timeout 00:02:30)
6558 11:35:59.116117 / #
6559 11:35:59.116436 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6560 11:35:59.116556 start: 2.2.7 export-device-env (timeout 00:03:53) [common]
6561 11:35:59.116657 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx'"
6563 11:35:59.222460 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864601/extract-nfsrootfs-fztzidxx'
6564 11:35:59.222798 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
6566 11:35:59.328844 / # export NFS_SERVER_IP='192.168.201.1'
6567 11:35:59.329141 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6568 11:35:59.329245 end: 2.2 depthcharge-retry (duration 00:01:07) [common]
6569 11:35:59.329343 end: 2 depthcharge-action (duration 00:01:07) [common]
6570 11:35:59.329440 start: 3 lava-test-retry (timeout 00:30:00) [common]
6571 11:35:59.329534 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
6572 11:35:59.329616 Using namespace: common
6573 11:35:59.329695 Sending line: '#'
6575 11:35:59.430175 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
6576 11:35:59.435421 / # #
6577 11:35:59.435691 Using /lava-14864601
6578 11:35:59.435760 Sending line: 'export SHELL=/bin/sh'
6580 11:35:59.541008 / # export SHELL=/bin/sh
6581 11:35:59.541275 Sending line: '. /lava-14864601/environment'
6583 11:35:59.647383 / # . /lava-14864601/environment
6584 11:35:59.652966 Sending line: '/lava-14864601/bin/lava-test-runner /lava-14864601/0'
6586 11:35:59.753506 Test shell timeout: 10s (minimum of the action and connection timeout)
6587 11:35:59.759131 / # /lava-14864601/bin/lava-test-runner /lava-14864601/0
6588 11:35:59.965330 + export TESTRUN_ID=0_lc-compliance
6589 11:35:59.968804 + cd /lava-14864601/0/tests/0_lc-compliance
6590 11:35:59.968898 + cat uuid
6591 11:35:59.972963 + UUID=14864601_1.6.2.3.1
6592 11:35:59.976695 + set +x
6593 11:35:59.979821 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14864601_1.6.2.3.1>
6594 11:35:59.980087 Received signal: <STARTRUN> 0_lc-compliance 14864601_1.6.2.3.1
6595 11:35:59.980167 Starting test lava.0_lc-compliance (14864601_1.6.2.3.1)
6596 11:35:59.980268 Skipping test definition patterns.
6597 11:35:59.982902 + /usr/bin/lc-compliance-parser.sh
6598 11:36:01.630645 [0:00:17.351097000] [427] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
6599 11:36:01.637409 Using camera /base/soc/usb@11201000/usb@11200000/hub@1-1.3:1.0-04f2:b567
6600 11:36:01.685727 [0:00:17.406997616] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6601 11:36:01.694601 [==========] Running 120 tests from 1 test suite.
6602 11:36:01.753550 [0:00:17.474205077] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6603 11:36:01.756610 [----------] Global test environment set-up.
6604 11:36:01.805674 [----------] 120 tests from CaptureTests/SingleStream
6605 11:36:01.819264 [0:00:17.540494154] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6606 11:36:01.861469 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
6607 11:36:01.883986 [0:00:17.605321000] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6608 11:36:01.910908 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
6609 11:36:01.911215 Received signal: <TESTSET> START CaptureTests/SingleStream
6610 11:36:01.911293 Starting test_set CaptureTests/SingleStream
6611 11:36:01.914069 Camera needs 4 requests, can't test only 1
6612 11:36:01.975198 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6613 11:36:02.035964
6614 11:36:02.102337 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (66 ms)
6615 11:36:02.174218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
6616 11:36:02.174525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
6618 11:36:02.186535 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
6619 11:36:02.233854 Camera needs 4 requests, can't test only 2
6620 11:36:02.294358 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6621 11:36:02.347976
6622 11:36:02.411137 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (65 ms)
6623 11:36:02.473177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
6624 11:36:02.473468 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
6626 11:36:02.483977 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
6627 11:36:02.520938 Camera needs 4 requests, can't test only 3
6628 11:36:02.530905 [0:00:18.250242923] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6629 11:36:02.579718 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6630 11:36:02.636321
6631 11:36:02.695658 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (65 ms)
6632 11:36:02.755925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
6633 11:36:02.756231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
6635 11:36:02.767102 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
6636 11:36:02.804022 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (490 ms)
6637 11:36:02.860288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
6638 11:36:02.860603 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
6640 11:36:02.875186 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
6641 11:36:03.040551 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (711 ms)
6642 11:36:03.115051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
6643 11:36:03.115368 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
6645 11:36:03.126767 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
6646 11:36:03.141616 [0:00:18.862669923] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6647 11:36:03.817209 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (776 ms)
6648 11:36:03.862259 [0:00:19.583107154] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6649 11:36:03.881148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
6650 11:36:03.881454 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
6652 11:36:03.892166 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
6653 11:36:05.259211 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1440 ms)
6654 11:36:05.303164 [0:00:21.023761693] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6655 11:36:05.327703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
6656 11:36:05.328012 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
6658 11:36:05.339719 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
6659 11:36:09.070020 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (3811 ms)
6660 11:36:09.113858 [0:00:24.834851385] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6661 11:36:09.139798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
6662 11:36:09.140099 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
6664 11:36:09.151961 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
6665 11:36:14.973330 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (5903 ms)
6666 11:36:15.017006 [0:00:30.738265232] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6667 11:36:15.045057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
6668 11:36:15.045345 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
6670 11:36:15.056864 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
6671 11:36:20.073973 <6>[ 35.943297] vaux18: disabling
6672 11:36:20.077715 <6>[ 35.947042] vio28: disabling
6673 11:36:24.267249 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (9293 ms)
6674 11:36:24.311360 [0:00:40.032307232] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6675 11:36:24.336373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
6676 11:36:24.336672 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
6678 11:36:24.346635 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
6679 11:36:24.374958 [0:00:40.095327848] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6680 11:36:24.388608 Camera needs 4 requests, can't test only 1
6681 11:36:24.437530 [0:00:40.158285232] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6682 11:36:24.447973 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6683 11:36:24.502891 [0:00:40.223330925] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6684 11:36:24.503006
6685 11:36:24.557920 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (63 ms)
6686 11:36:24.616525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
6687 11:36:24.616824 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
6689 11:36:24.628015 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
6690 11:36:24.665955 Camera needs 4 requests, can't test only 2
6691 11:36:24.719892 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6692 11:36:24.779253
6693 11:36:24.851274 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (62 ms)
6694 11:36:24.907000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
6695 11:36:24.907272 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
6697 11:36:24.919796 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
6698 11:36:24.963254 Camera needs 4 requests, can't test only 3
6699 11:36:25.032256 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6700 11:36:25.094891
6701 11:36:25.157800 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (64 ms)
6702 11:36:25.223779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
6703 11:36:25.224087 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
6705 11:36:25.233657 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
6706 11:36:26.030985 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (1573 ms)
6707 11:36:26.075666 [0:00:41.796292463] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6708 11:36:26.107054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
6709 11:36:26.107337 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
6711 11:36:26.117959 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
6712 11:36:27.251198 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (1219 ms)
6713 11:36:27.295367 [0:00:43.015594771] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6714 11:36:27.318440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
6715 11:36:27.318701 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
6717 11:36:27.330323 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
6718 11:36:28.973450 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1718 ms)
6719 11:36:29.013837 [0:00:44.734715387] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6720 11:36:29.035894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
6721 11:36:29.036158 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
6723 11:36:29.048211 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
6724 11:36:31.485773 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (2515 ms)
6725 11:36:31.529309 [0:00:47.250011694] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6726 11:36:31.557572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
6727 11:36:31.557837 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
6729 11:36:31.569626 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
6730 11:36:35.297900 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (3812 ms)
6731 11:36:35.341766 [0:00:51.061981618] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6732 11:36:35.366707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
6733 11:36:35.367046 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
6735 11:36:35.379448 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
6736 11:36:41.202419 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (5904 ms)
6737 11:36:41.247896 [0:00:56.967288310] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6738 11:36:41.284758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
6739 11:36:41.285044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
6741 11:36:41.297827 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
6742 11:36:50.498397 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (9295 ms)
6743 11:36:50.544578 [0:01:06.264399080] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6744 11:36:50.570791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
6745 11:36:50.571051 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
6747 11:36:50.582234 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
6748 11:36:50.605980 [0:01:06.325994619] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6749 11:36:50.624256 Camera needs 4 requests, can't test only 1
6750 11:36:50.669989 [0:01:06.390076619] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6751 11:36:50.686744 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6752 11:36:50.738229 [0:01:06.458096542] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6753 11:36:50.746876
6754 11:36:50.814686 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (63 ms)
6755 11:36:50.880951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
6756 11:36:50.881265 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
6758 11:36:50.895538 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
6759 11:36:50.939573 Camera needs 4 requests, can't test only 2
6760 11:36:50.999476 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6761 11:36:51.062753
6762 11:36:51.121604 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (62 ms)
6763 11:36:51.194455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
6764 11:36:51.194979 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
6766 11:36:51.207727 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
6767 11:36:51.252010 Camera needs 4 requests, can't test only 3
6768 11:36:51.320723 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6769 11:36:51.386813
6770 11:36:51.450809 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (68 ms)
6771 11:36:51.520762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
6772 11:36:51.521040 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
6774 11:36:51.533169 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
6775 11:36:52.262816 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (1569 ms)
6776 11:36:52.307193 [0:01:08.027193849] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6777 11:36:52.330126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
6778 11:36:52.330396 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
6780 11:36:52.343127 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
6781 11:36:53.489283 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (1222 ms)
6782 11:36:53.530993 [0:01:09.250569926] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6783 11:36:53.567270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
6784 11:36:53.567923 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
6786 11:36:53.583385 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
6787 11:36:55.210706 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1720 ms)
6788 11:36:55.252265 [0:01:10.971828080] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6789 11:36:55.294464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
6790 11:36:55.295113 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
6792 11:36:55.310040 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
6793 11:36:57.727895 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (2517 ms)
6794 11:36:57.769301 [0:01:13.489549696] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6795 11:36:57.795595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
6796 11:36:57.795870 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
6798 11:36:57.808950 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
6799 11:37:01.539066 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (3813 ms)
6800 11:37:01.583458 [0:01:17.303331081] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6801 11:37:01.616661 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
6803 11:37:01.620047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
6804 11:37:01.630119 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
6805 11:37:07.450337 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (5908 ms)
6806 11:37:07.491997 [0:01:23.211282466] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6807 11:37:07.517678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
6808 11:37:07.517937 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
6810 11:37:07.528634 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
6811 11:37:16.750247 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (9298 ms)
6812 11:37:16.791327 [0:01:32.510808082] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6813 11:37:16.812746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
6814 11:37:16.813002 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
6816 11:37:16.822938 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
6817 11:37:16.854260 [0:01:32.573606312] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6818 11:37:16.864277 Camera needs 4 requests, can't test only 1
6819 11:37:16.919452 [0:01:32.638645928] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6820 11:37:16.922439 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6821 11:37:16.984618 [0:01:32.704407928] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6822 11:37:16.984715
6823 11:37:17.044786 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (62 ms)
6824 11:37:17.101234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
6825 11:37:17.101504 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
6827 11:37:17.112252 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
6828 11:37:17.155547 Camera needs 4 requests, can't test only 2
6829 11:37:17.218096 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6830 11:37:17.275455
6831 11:37:17.336235 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (62 ms)
6832 11:37:17.398981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
6833 11:37:17.399271 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
6835 11:37:17.411081 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
6836 11:37:17.449256 Camera needs 4 requests, can't test only 3
6837 11:37:17.501653 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6838 11:37:17.550442
6839 11:37:17.603327 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (66 ms)
6840 11:37:17.668813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
6841 11:37:17.669086 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
6843 11:37:17.679387 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
6844 11:37:18.510373 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (1571 ms)
6845 11:37:18.554410 [0:01:34.274090697] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6846 11:37:18.588966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
6847 11:37:18.589223 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
6849 11:37:18.601576 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
6850 11:37:19.729178 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (1218 ms)
6851 11:37:19.773929 [0:01:35.493102543] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6852 11:37:19.799124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
6853 11:37:19.799378 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
6855 11:37:19.813000 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
6856 11:37:21.447879 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1718 ms)
6857 11:37:21.494836 [0:01:37.213780390] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6858 11:37:21.523698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
6859 11:37:21.523976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
6861 11:37:21.538383 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
6862 11:37:23.966943 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (2517 ms)
6863 11:37:24.011223 [0:01:39.730151774] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6864 11:37:24.067052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
6865 11:37:24.067708 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
6867 11:37:24.084734 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
6868 11:37:27.779153 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (3811 ms)
6869 11:37:27.823755 [0:01:43.542397313] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6870 11:37:27.868220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
6871 11:37:27.868646 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
6873 11:37:27.884646 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
6874 11:37:33.683205 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (5903 ms)
6875 11:37:33.728024 [0:01:49.447105544] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6876 11:37:33.784332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
6877 11:37:33.785017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
6879 11:37:33.801374 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
6880 11:37:42.979900 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (9296 ms)
6881 11:37:43.024736 [0:01:58.743027160] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6882 11:37:43.077161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
6883 11:37:43.077800 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
6885 11:37:43.090510 [0:01:58.807917083] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6886 11:37:43.093180 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
6887 11:37:43.152411 [0:01:58.870944391] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6888 11:37:43.155744 Camera needs 4 requests, can't test only 1
6889 11:37:43.218772 [0:01:58.937029545] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6890 11:37:43.229498 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6891 11:37:43.308091
6892 11:37:43.386372 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (63 ms)
6893 11:37:43.483012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
6894 11:37:43.483748 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
6896 11:37:43.498514 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
6897 11:37:43.548448 Camera needs 4 requests, can't test only 2
6898 11:37:43.618925 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6899 11:37:43.686384
6900 11:37:43.759093 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (62 ms)
6901 11:37:43.841191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
6902 11:37:43.841892 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
6904 11:37:43.855824 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
6905 11:37:43.911558 Camera needs 4 requests, can't test only 3
6906 11:37:43.984985 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6907 11:37:44.050943
6908 11:37:44.128688 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (66 ms)
6909 11:37:44.215446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
6910 11:37:44.216273 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
6912 11:37:44.229975 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
6913 11:37:46.485856 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (3313 ms)
6914 11:37:46.531565 [0:02:02.249772468] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6915 11:37:46.568582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
6916 11:37:46.569350 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
6918 11:37:46.583709 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
6919 11:37:50.053165 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (3567 ms)
6920 11:37:50.097717 [0:02:05.816683391] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6921 11:37:50.119673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
6922 11:37:50.120024 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
6924 11:37:50.133747 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
6925 11:37:55.117970 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (5064 ms)
6926 11:37:55.163622 [0:02:10.882003699] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6927 11:37:55.183100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
6928 11:37:55.183354 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
6930 11:37:55.194693 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
6931 11:38:02.571302 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (7452 ms)
6932 11:38:02.615777 [0:02:18.334528007] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6933 11:38:02.637455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
6934 11:38:02.637734 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
6936 11:38:02.649167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
6937 11:38:13.917995 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (11342 ms)
6938 11:38:13.961923 [0:02:29.680261470] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6939 11:38:13.991267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
6940 11:38:13.991574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
6942 11:38:14.004937 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
6943 11:38:31.539374 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (17621 ms)
6944 11:38:31.586208 [0:02:47.304222702] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6945 11:38:31.610907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
6946 11:38:31.611184 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
6948 11:38:31.623311 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
6949 11:38:59.340101 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (27802 ms)
6950 11:38:59.384631 [0:03:15.101745165] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6951 11:38:59.404262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
6952 11:38:59.404523 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
6954 11:38:59.418064 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
6955 11:38:59.449945 [0:03:15.166955165] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6956 11:38:59.452614 Camera needs 4 requests, can't test only 1
6957 11:38:59.515668 [0:03:15.232346857] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6958 11:38:59.518498 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6959 11:38:59.564139
6960 11:38:59.577777 [0:03:15.294937703] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6961 11:38:59.619914 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (62 ms)
6962 11:38:59.679608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
6963 11:38:59.679908 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
6965 11:38:59.686787 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
6966 11:38:59.727576 Camera needs 4 requests, can't test only 2
6967 11:38:59.794113 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6968 11:38:59.856922
6969 11:38:59.920894 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (66 ms)
6970 11:38:59.983389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
6971 11:38:59.983702 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
6973 11:38:59.991473 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
6974 11:39:00.030082 Camera needs 4 requests, can't test only 3
6975 11:39:00.093690 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6976 11:39:00.158088
6977 11:39:00.221496 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (63 ms)
6978 11:39:00.289593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
6979 11:39:00.289894 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
6981 11:39:00.297002 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
6982 11:39:02.854524 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (3318 ms)
6983 11:39:02.896817 [0:03:18.613745703] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6984 11:39:02.922181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
6985 11:39:02.922430 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
6987 11:39:02.932693 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
6988 11:39:06.422783 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (3567 ms)
6989 11:39:06.464386 [0:03:22.181446088] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6990 11:39:06.490847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
6991 11:39:06.491113 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
6993 11:39:06.499216 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
6994 11:39:11.489705 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (5066 ms)
6995 11:39:11.530717 [0:03:27.247723473] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6996 11:39:11.555615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
6997 11:39:11.555927 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
6999 11:39:11.562801 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
7000 11:39:18.945028 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (7453 ms)
7001 11:39:18.986096 [0:03:34.702678550] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7002 11:39:19.026363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
7003 11:39:19.026789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
7005 11:39:19.038772 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
7006 11:39:30.286854 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (11342 ms)
7007 11:39:30.329069 [0:03:46.045370628] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7008 11:39:30.357986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
7009 11:39:30.358319 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
7011 11:39:30.366174 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
7012 11:39:47.900125 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (17612 ms)
7013 11:39:47.946128 [0:04:03.662007091] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7014 11:39:47.976946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
7015 11:39:47.977221 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
7017 11:39:47.985919 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
7018 11:40:15.694708 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (27791 ms)
7019 11:40:15.739726 [0:04:31.455443631] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7020 11:40:15.785080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
7021 11:40:15.785346 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
7023 11:40:15.793900 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
7024 11:40:15.806960 [0:04:31.522556631] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7025 11:40:15.846108 Camera needs 4 requests, can't test only 1
7026 11:40:15.876288 [0:04:31.591549785] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7027 11:40:15.915739 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7028 11:40:15.942070 [0:04:31.657684862] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7029 11:40:15.988028
7030 11:40:16.067841 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (65 ms)
7031 11:40:16.142659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
7032 11:40:16.142953 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
7034 11:40:16.153516 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
7035 11:40:16.195751 Camera needs 4 requests, can't test only 2
7036 11:40:16.250898 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7037 11:40:16.301204
7038 11:40:16.360162 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (68 ms)
7039 11:40:16.421162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
7040 11:40:16.421448 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
7042 11:40:16.430116 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
7043 11:40:16.468368 Camera needs 4 requests, can't test only 3
7044 11:40:16.522259 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7045 11:40:16.572488
7046 11:40:16.636160 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (67 ms)
7047 11:40:16.703394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
7048 11:40:16.703687 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
7050 11:40:16.713443 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
7051 11:40:19.207857 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (3308 ms)
7052 11:40:19.251874 [0:04:34.966721016] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7053 11:40:19.295908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
7054 11:40:19.296576 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
7056 11:40:19.307873 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
7057 11:40:22.773863 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (3565 ms)
7058 11:40:22.816770 [0:04:38.531852939] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7059 11:40:22.864363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
7060 11:40:22.864987 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
7062 11:40:22.878755 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
7063 11:40:27.836896 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (5063 ms)
7064 11:40:27.878109 [0:04:43.593348016] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7065 11:40:27.915712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
7066 11:40:27.916016 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
7068 11:40:27.926655 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
7069 11:40:35.286946 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (7449 ms)
7070 11:40:35.328982 [0:04:51.043991709] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7071 11:40:35.363778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
7072 11:40:35.364599 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
7074 11:40:35.375022 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
7075 11:40:46.624788 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (11337 ms)
7076 11:40:46.668037 [0:05:02.382572710] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7077 11:40:46.710370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
7078 11:40:46.710662 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
7080 11:40:46.725137 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
7081 11:41:04.239811 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (17614 ms)
7082 11:41:04.281741 [0:05:19.996124480] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7083 11:41:04.310905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
7084 11:41:04.311163 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
7086 11:41:04.322950 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
7087 11:41:32.029255 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (27788 ms)
7088 11:41:32.071138 [0:05:47.784601482] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7089 11:41:32.125136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
7090 11:41:32.125823 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
7092 11:41:32.136007 [0:05:47.847431789] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7093 11:41:32.141413 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
7094 11:41:32.184503 Camera needs 4 requests, can't test only 1
7095 11:41:32.194203 [0:05:47.909692097] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7096 11:41:32.257349 [0:05:47.970695558] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7097 11:41:32.260726 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7098 11:41:32.334636
7099 11:41:32.415365 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (61 ms)
7100 11:41:32.498606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
7101 11:41:32.499365 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
7103 11:41:32.509727 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
7104 11:41:32.555186 Camera needs 4 requests, can't test only 2
7105 11:41:32.624575 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7106 11:41:32.696775
7107 11:41:32.783002 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (63 ms)
7108 11:41:32.865421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
7109 11:41:32.865727 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
7111 11:41:32.877903 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
7112 11:41:32.918963 Camera needs 4 requests, can't test only 3
7113 11:41:32.993263 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7114 11:41:33.068693
7115 11:41:33.134774 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (61 ms)
7116 11:41:33.199987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
7117 11:41:33.200286 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
7119 11:41:33.207896 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
7120 11:41:35.537062 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (3321 ms)
7121 11:41:35.579319 [0:05:51.292748328] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7122 11:41:35.618166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
7123 11:41:35.618448 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
7125 11:41:35.627854 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
7126 11:41:39.105163 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (3568 ms)
7127 11:41:39.146791 [0:05:54.860709713] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7128 11:41:39.180222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
7129 11:41:39.180535 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
7131 11:41:39.190742 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
7132 11:41:44.166551 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (5061 ms)
7133 11:41:44.208019 [0:05:59.921419098] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7134 11:41:44.244158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
7135 11:41:44.244417 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
7137 11:41:44.257047 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
7138 11:41:51.616164 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (7448 ms)
7139 11:41:51.658221 [0:06:07.371061560] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7140 11:41:51.696560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
7141 11:41:51.696818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
7143 11:41:51.704782 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
7144 11:42:02.951347 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (11335 ms)
7145 11:42:02.992497 [0:06:18.705662637] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7146 11:42:03.026363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
7147 11:42:03.026626 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
7149 11:42:03.034807 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
7150 11:42:20.563572 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (17611 ms)
7151 11:42:20.605184 [0:06:36.317173177] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7152 11:42:20.660007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
7153 11:42:20.660647 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
7155 11:42:20.672236 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
7156 11:42:48.350798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (27786 ms)
7157 11:42:48.392761 [0:07:04.104791255] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7158 11:42:48.425488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
7159 11:42:48.425789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
7161 11:42:48.434645 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
7162 11:42:48.872916 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (525 ms)
7163 11:42:48.936001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
7164 11:42:48.936333 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
7166 11:42:48.948344 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
7167 11:42:49.137834 [0:07:04.850065794] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7168 11:42:49.720358 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (846 ms)
7169 11:42:49.794057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
7170 11:42:49.794359 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
7172 11:42:49.806375 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
7173 11:42:49.885309 [0:07:05.597157102] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7174 11:42:50.568826 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (848 ms)
7175 11:42:50.633473 [0:07:06.345670563] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7176 11:42:50.637301 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
7178 11:42:50.640401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
7179 11:42:50.643797 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
7180 11:42:51.512723 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (944 ms)
7181 11:42:51.557000 [0:07:07.268995025] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7182 11:42:51.588313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
7183 11:42:51.588616 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
7185 11:42:51.602319 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
7186 11:42:52.734920 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (1222 ms)
7187 11:42:52.779186 [0:07:08.491253409] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7188 11:42:52.800965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
7189 11:42:52.801282 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
7191 11:42:52.813077 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
7192 11:42:54.455174 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1720 ms)
7193 11:42:54.499799 [0:07:10.211559486] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7194 11:42:54.518739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
7195 11:42:54.519017 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
7197 11:42:54.531626 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
7198 11:42:56.973068 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (2517 ms)
7199 11:42:57.018343 [0:07:12.730226179] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7200 11:42:57.041370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
7201 11:42:57.041654 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
7203 11:42:57.053272 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
7204 11:43:00.785492 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (3811 ms)
7205 11:43:00.829364 [0:07:16.541145333] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7206 11:43:00.855267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
7207 11:43:00.855561 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
7209 11:43:00.867483 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
7210 11:43:06.689807 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (5904 ms)
7211 11:43:06.736163 [0:07:22.448235026] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7212 11:43:06.755282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
7213 11:43:06.755611 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
7215 11:43:06.770612 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
7216 11:43:15.989614 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (9298 ms)
7217 11:43:16.034618 [0:07:31.745739718] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7218 11:43:16.077514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
7219 11:43:16.078200 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
7221 11:43:16.093142 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
7222 11:43:16.518244 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (525 ms)
7223 11:43:16.599691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
7224 11:43:16.600482 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
7226 11:43:16.611766 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
7227 11:43:16.781826 [0:07:32.493012488] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7228 11:43:17.366690 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (848 ms)
7229 11:43:17.433178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
7230 11:43:17.433468 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
7232 11:43:17.441495 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
7233 11:43:17.534341 [0:07:33.246032103] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7234 11:43:18.218171 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (851 ms)
7235 11:43:18.284970 [0:07:33.996566257] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7236 11:43:18.291596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
7237 11:43:18.291877 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
7239 11:43:18.298325 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
7240 11:43:19.165118 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (946 ms)
7241 11:43:19.206804 [0:07:34.918497565] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7242 11:43:19.236921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
7243 11:43:19.237175 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
7245 11:43:19.244947 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
7246 11:43:20.385341 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (1220 ms)
7247 11:43:20.427217 [0:07:36.138449565] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7248 11:43:20.459753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
7249 11:43:20.460106 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
7251 11:43:20.468917 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
7252 11:43:22.106128 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1720 ms)
7253 11:43:22.148762 [0:07:37.859712796] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7254 11:43:22.198550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
7255 11:43:22.199217 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
7257 11:43:22.211827 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
7258 11:43:24.621801 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (2515 ms)
7259 11:43:24.663764 [0:07:40.375074104] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7260 11:43:24.699972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
7261 11:43:24.700240 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
7263 11:43:24.710435 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
7264 11:43:28.435694 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (3813 ms)
7265 11:43:28.477101 [0:07:44.187666950] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7266 11:43:28.522933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
7267 11:43:28.523646 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
7269 11:43:28.533868 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
7270 11:43:34.340144 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (5904 ms)
7271 11:43:34.380614 [0:07:50.091223181] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7272 11:43:34.421691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
7273 11:43:34.421973 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
7275 11:43:34.434096 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
7276 11:43:43.635528 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (9295 ms)
7277 11:43:43.676747 [0:07:59.387239951] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7278 11:43:43.714643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
7279 11:43:43.714906 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
7281 11:43:43.723939 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
7282 11:43:44.162344 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (527 ms)
7283 11:43:44.227795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
7284 11:43:44.228064 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
7286 11:43:44.238909 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
7287 11:43:44.426245 [0:08:00.136694951] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7288 11:43:45.011640 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (848 ms)
7289 11:43:45.088637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
7290 11:43:45.088914 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
7292 11:43:45.098153 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
7293 11:43:45.175962 [0:08:00.886731874] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7294 11:43:45.861933 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (850 ms)
7295 11:43:45.923985 [0:08:01.634661951] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7296 11:43:45.947327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
7297 11:43:45.947974 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
7299 11:43:45.960377 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
7300 11:43:46.803715 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (941 ms)
7301 11:43:46.844629 [0:08:02.555374643] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7302 11:43:46.889830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
7303 11:43:46.890564 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
7305 11:43:46.901298 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
7306 11:43:48.023111 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (1219 ms)
7307 11:43:48.064994 [0:08:03.775319105] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7308 11:43:48.107899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
7309 11:43:48.108563 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
7311 11:43:48.120568 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
7312 11:43:49.742968 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1720 ms)
7313 11:43:49.784092 [0:08:05.494533720] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7314 11:43:49.833461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
7315 11:43:49.834125 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
7317 11:43:49.844489 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
7318 11:43:52.258453 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (2514 ms)
7319 11:43:52.299005 [0:08:08.009368259] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7320 11:43:52.336265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
7321 11:43:52.336565 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
7323 11:43:52.343595 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
7324 11:43:56.068266 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (3810 ms)
7325 11:43:56.109371 [0:08:11.819661490] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7326 11:43:56.143607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
7327 11:43:56.144234 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
7329 11:43:56.153352 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
7330 11:44:01.971509 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (5902 ms)
7331 11:44:02.012529 [0:08:17.722431721] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7332 11:44:02.056318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
7333 11:44:02.056589 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
7335 11:44:02.067822 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
7336 11:44:11.265751 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (9294 ms)
7337 11:44:11.307282 [0:08:27.017499491] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7338 11:44:11.345114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
7339 11:44:11.345408 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
7341 11:44:11.355645 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
7342 11:44:11.787023 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (524 ms)
7343 11:44:11.858942 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
7345 11:44:11.862219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
7346 11:44:11.873463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
7347 11:44:12.051410 [0:08:27.761926414] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7348 11:44:12.636658 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (846 ms)
7349 11:44:12.718777 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
7351 11:44:12.721736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
7352 11:44:12.732527 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
7353 11:44:12.798613 [0:08:28.508620568] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7354 11:44:13.483443 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (846 ms)
7355 11:44:13.545715 [0:08:29.256040491] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7356 11:44:13.561650 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
7358 11:44:13.564728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
7359 11:44:13.575525 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
7360 11:44:14.424340 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (940 ms)
7361 11:44:14.465704 [0:08:30.175744876] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7362 11:44:14.504557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
7363 11:44:14.504820 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
7365 11:44:14.516025 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
7366 11:44:15.647564 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (1223 ms)
7367 11:44:15.688727 [0:08:31.399119030] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7368 11:44:15.729878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
7369 11:44:15.730175 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
7371 11:44:15.746374 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
7372 11:44:17.368214 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1719 ms)
7373 11:44:17.409189 [0:08:33.119254184] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7374 11:44:17.446595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
7375 11:44:17.446854 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
7377 11:44:17.453962 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
7378 11:44:19.887202 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (2518 ms)
7379 11:44:19.929987 [0:08:35.640076107] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7380 11:44:19.974566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
7381 11:44:19.974853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
7383 11:44:19.985837 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
7384 11:44:23.701932 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (3814 ms)
7385 11:44:23.745314 [0:08:39.455256723] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7386 11:44:23.784062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
7387 11:44:23.784365 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
7389 11:44:23.794163 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
7390 11:44:29.610217 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (5908 ms)
7391 11:44:29.653816 [0:08:45.363723723] [427] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7392 11:44:29.696530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
7393 11:44:29.696808 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
7395 11:44:29.706065 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
7396 11:44:38.909541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (9298 ms)
7397 11:44:39.001100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
7398 11:44:39.001388 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
7400 11:44:39.010197 [----------] 120 tests from CaptureTests/SingleStream (517253 ms total)
7401 11:44:39.065806
7402 11:44:39.136703 [----------] Global test environment tear-down
7403 11:44:39.203955 [==========] 120 tests from 1 test suite ran. (517253 ms total)
7404 11:44:39.265380 <LAVA_SIGNAL_TESTSET STOP>
7405 11:44:39.265674 Received signal: <TESTSET> STOP
7406 11:44:39.265740 Closing test_set CaptureTests/SingleStream
7407 11:44:39.268605 + set +x
7408 11:44:39.271867 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14864601_1.6.2.3.1>
7409 11:44:39.272109 Received signal: <ENDRUN> 0_lc-compliance 14864601_1.6.2.3.1
7410 11:44:39.272183 Ending use of test pattern.
7411 11:44:39.272239 Ending test lava.0_lc-compliance (14864601_1.6.2.3.1), duration 519.29
7413 11:44:39.275515 <LAVA_TEST_RUNNER EXIT>
7414 11:44:39.275793 ok: lava_test_shell seems to have completed
7415 11:44:39.277447 Capture/Raw_1:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_2:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_3:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_5:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_8:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_13:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_21:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_34:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_55:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_89:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
7416 11:44:39.277642 end: 3.1 lava-test-shell (duration 00:08:40) [common]
7417 11:44:39.277723 end: 3 lava-test-retry (duration 00:08:40) [common]
7418 11:44:39.277801 start: 4 finalize (timeout 00:10:00) [common]
7419 11:44:39.277881 start: 4.1 power-off (timeout 00:00:30) [common]
7420 11:44:39.278055 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-4', '--port=1', '--command=off']
7421 11:44:41.347839 >> Command sent successfully.
7422 11:44:41.351707 Returned 0 in 2 seconds
7423 11:44:41.351867 end: 4.1 power-off (duration 00:00:02) [common]
7425 11:44:41.352154 start: 4.2 read-feedback (timeout 00:09:58) [common]
7426 11:44:41.352325 Listened to connection for namespace 'common' for up to 1s
7427 11:44:42.353400 Finalising connection for namespace 'common'
7428 11:44:42.353549 Disconnecting from shell: Finalise
7429 11:44:42.353616 / #
7430 11:44:42.453881 end: 4.2 read-feedback (duration 00:00:01) [common]
7431 11:44:42.454089 end: 4 finalize (duration 00:00:03) [common]
7432 11:44:42.454197 Cleaning after the job
7433 11:44:42.454290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/ramdisk
7434 11:44:42.456676 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/kernel
7435 11:44:42.467956 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/dtb
7436 11:44:42.468139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/nfsrootfs
7437 11:44:42.510231 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864601/tftp-deploy-znwinunr/modules
7438 11:44:42.515969 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864601
7439 11:44:42.781341 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864601
7440 11:44:42.781509 Job finished correctly