Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 11:35:04.733773 lava-dispatcher, installed at version: 2024.05
2 11:35:04.733984 start: 0 validate
3 11:35:04.734112 Start time: 2024-07-17 11:35:04.734104+00:00 (UTC)
4 11:35:04.734249 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:35:04.734390 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:35:04.994288 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:35:04.994507 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:35:05.251843 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:35:05.252035 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:35:05.501305 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:35:05.501505 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:35:05.763676 validate duration: 1.03
14 11:35:05.764007 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:35:05.764135 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:35:05.764243 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:35:05.764435 Not decompressing ramdisk as can be used compressed.
18 11:35:05.764549 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:35:05.764639 saving as /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/ramdisk/rootfs.cpio.gz
20 11:35:05.764726 total size: 28105535 (26 MB)
21 11:35:05.766102 progress 0 % (0 MB)
22 11:35:05.773583 progress 5 % (1 MB)
23 11:35:05.781096 progress 10 % (2 MB)
24 11:35:05.788604 progress 15 % (4 MB)
25 11:35:05.796185 progress 20 % (5 MB)
26 11:35:05.803632 progress 25 % (6 MB)
27 11:35:05.811126 progress 30 % (8 MB)
28 11:35:05.818826 progress 35 % (9 MB)
29 11:35:05.826448 progress 40 % (10 MB)
30 11:35:05.833861 progress 45 % (12 MB)
31 11:35:05.841530 progress 50 % (13 MB)
32 11:35:05.849039 progress 55 % (14 MB)
33 11:35:05.856467 progress 60 % (16 MB)
34 11:35:05.863658 progress 65 % (17 MB)
35 11:35:05.871175 progress 70 % (18 MB)
36 11:35:05.878708 progress 75 % (20 MB)
37 11:35:05.886191 progress 80 % (21 MB)
38 11:35:05.893660 progress 85 % (22 MB)
39 11:35:05.901133 progress 90 % (24 MB)
40 11:35:05.908650 progress 95 % (25 MB)
41 11:35:05.915910 progress 100 % (26 MB)
42 11:35:05.916183 26 MB downloaded in 0.15 s (176.98 MB/s)
43 11:35:05.916394 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:35:05.916750 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:35:05.916857 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:35:05.916966 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:35:05.917135 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:35:05.917223 saving as /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/kernel/Image
50 11:35:05.917349 total size: 54813184 (52 MB)
51 11:35:05.917432 No compression specified
52 11:35:05.918877 progress 0 % (0 MB)
53 11:35:05.933131 progress 5 % (2 MB)
54 11:35:05.947848 progress 10 % (5 MB)
55 11:35:05.961768 progress 15 % (7 MB)
56 11:35:05.975427 progress 20 % (10 MB)
57 11:35:05.989390 progress 25 % (13 MB)
58 11:35:06.003202 progress 30 % (15 MB)
59 11:35:06.016963 progress 35 % (18 MB)
60 11:35:06.030937 progress 40 % (20 MB)
61 11:35:06.044964 progress 45 % (23 MB)
62 11:35:06.058586 progress 50 % (26 MB)
63 11:35:06.072707 progress 55 % (28 MB)
64 11:35:06.086918 progress 60 % (31 MB)
65 11:35:06.101117 progress 65 % (34 MB)
66 11:35:06.115340 progress 70 % (36 MB)
67 11:35:06.129023 progress 75 % (39 MB)
68 11:35:06.142790 progress 80 % (41 MB)
69 11:35:06.156629 progress 85 % (44 MB)
70 11:35:06.171200 progress 90 % (47 MB)
71 11:35:06.185133 progress 95 % (49 MB)
72 11:35:06.198961 progress 100 % (52 MB)
73 11:35:06.199209 52 MB downloaded in 0.28 s (185.46 MB/s)
74 11:35:06.199361 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:35:06.199567 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:35:06.199646 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:35:06.199720 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:35:06.199857 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:35:06.199990 saving as /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/dtb/mt8192-asurada-spherion-r0.dtb
81 11:35:06.200072 total size: 47258 (0 MB)
82 11:35:06.200155 No compression specified
83 11:35:06.201672 progress 69 % (0 MB)
84 11:35:06.201961 progress 100 % (0 MB)
85 11:35:06.202167 0 MB downloaded in 0.00 s (21.54 MB/s)
86 11:35:06.202328 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:35:06.202660 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:35:06.202768 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:35:06.202872 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:35:06.203012 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:35:06.203098 saving as /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/modules/modules.tar
93 11:35:06.203180 total size: 8610184 (8 MB)
94 11:35:06.203263 Using unxz to decompress xz
95 11:35:06.205086 progress 0 % (0 MB)
96 11:35:06.226298 progress 5 % (0 MB)
97 11:35:06.250839 progress 10 % (0 MB)
98 11:35:06.274634 progress 15 % (1 MB)
99 11:35:06.298894 progress 20 % (1 MB)
100 11:35:06.322543 progress 25 % (2 MB)
101 11:35:06.346037 progress 30 % (2 MB)
102 11:35:06.368572 progress 35 % (2 MB)
103 11:35:06.394409 progress 40 % (3 MB)
104 11:35:06.418610 progress 45 % (3 MB)
105 11:35:06.442550 progress 50 % (4 MB)
106 11:35:06.466955 progress 55 % (4 MB)
107 11:35:06.491201 progress 60 % (4 MB)
108 11:35:06.514302 progress 65 % (5 MB)
109 11:35:06.539309 progress 70 % (5 MB)
110 11:35:06.566064 progress 75 % (6 MB)
111 11:35:06.593415 progress 80 % (6 MB)
112 11:35:06.616930 progress 85 % (7 MB)
113 11:35:06.640403 progress 90 % (7 MB)
114 11:35:06.663592 progress 95 % (7 MB)
115 11:35:06.686071 progress 100 % (8 MB)
116 11:35:06.691534 8 MB downloaded in 0.49 s (16.81 MB/s)
117 11:35:06.691743 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:35:06.692087 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:35:06.692198 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:35:06.692304 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:35:06.692407 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:35:06.692509 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:35:06.692720 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5
125 11:35:06.692874 makedir: /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin
126 11:35:06.692993 makedir: /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/tests
127 11:35:06.693109 makedir: /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/results
128 11:35:06.693233 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-add-keys
129 11:35:06.693434 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-add-sources
130 11:35:06.693586 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-background-process-start
131 11:35:06.693745 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-background-process-stop
132 11:35:06.693903 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-common-functions
133 11:35:06.694053 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-echo-ipv4
134 11:35:06.694198 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-install-packages
135 11:35:06.694440 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-installed-packages
136 11:35:06.694588 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-os-build
137 11:35:06.694740 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-probe-channel
138 11:35:06.694881 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-probe-ip
139 11:35:06.695029 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-target-ip
140 11:35:06.695173 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-target-mac
141 11:35:06.695317 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-target-storage
142 11:35:06.695466 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-case
143 11:35:06.695614 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-event
144 11:35:06.695765 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-feedback
145 11:35:06.695910 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-raise
146 11:35:06.696052 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-reference
147 11:35:06.696197 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-runner
148 11:35:06.696340 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-set
149 11:35:06.696486 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-test-shell
150 11:35:06.696636 Updating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-install-packages (oe)
151 11:35:06.696813 Updating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/bin/lava-installed-packages (oe)
152 11:35:06.696958 Creating /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/environment
153 11:35:06.697074 LAVA metadata
154 11:35:06.697167 - LAVA_JOB_ID=14864607
155 11:35:06.697296 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:35:06.697422 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:35:06.697511 skipped lava-vland-overlay
158 11:35:06.697609 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:35:06.697718 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:35:06.697797 skipped lava-multinode-overlay
161 11:35:06.697890 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:35:06.697988 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:35:06.698083 Loading test definitions
164 11:35:06.698193 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:35:06.698282 Using /lava-14864607 at stage 0
166 11:35:06.698686 uuid=14864607_1.5.2.3.1 testdef=None
167 11:35:06.698798 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:35:06.698901 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:35:06.699517 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:35:06.699843 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:35:06.700669 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:35:06.701007 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:35:06.701856 runner path: /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14864607_1.5.2.3.1
176 11:35:06.702038 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:35:06.702352 Creating lava-test-runner.conf files
179 11:35:06.702473 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864607/lava-overlay-5hc7gsl5/lava-14864607/0 for stage 0
180 11:35:06.702586 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:35:06.702708 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:35:06.702812 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:35:06.711265 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:35:06.711385 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:35:06.711465 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:35:06.711543 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:35:06.711619 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:35:07.500614 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:35:07.500756 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:35:07.500830 extracting modules file /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864607/extract-overlay-ramdisk-ozoj0tnq/ramdisk
191 11:35:07.731101 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:35:07.731246 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:35:07.731330 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864607/compress-overlay-nz_f4094/overlay-1.5.2.4.tar.gz to ramdisk
194 11:35:07.731390 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864607/compress-overlay-nz_f4094/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864607/extract-overlay-ramdisk-ozoj0tnq/ramdisk
195 11:35:07.737834 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:35:07.737944 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:35:07.738024 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:35:07.738098 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:35:07.738163 Building ramdisk /var/lib/lava/dispatcher/tmp/14864607/extract-overlay-ramdisk-ozoj0tnq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864607/extract-overlay-ramdisk-ozoj0tnq/ramdisk
200 11:35:08.330983 >> 275513 blocks
201 11:35:12.615860 rename /var/lib/lava/dispatcher/tmp/14864607/extract-overlay-ramdisk-ozoj0tnq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/ramdisk/ramdisk.cpio.gz
202 11:35:12.616027 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:35:12.616113 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:35:12.616190 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:35:12.616265 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/kernel/Image']
206 11:35:26.617575 Returned 0 in 14 seconds
207 11:35:26.617738 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/kernel/image.itb
208 11:35:27.232119 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:35:27.232248 output: Created: Wed Jul 17 12:35:27 2024
210 11:35:27.232336 output: Image 0 (kernel-1)
211 11:35:27.232403 output: Description:
212 11:35:27.232453 output: Created: Wed Jul 17 12:35:27 2024
213 11:35:27.232502 output: Type: Kernel Image
214 11:35:27.232550 output: Compression: lzma compressed
215 11:35:27.232601 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:35:27.232648 output: Architecture: AArch64
217 11:35:27.232695 output: OS: Linux
218 11:35:27.232741 output: Load Address: 0x00000000
219 11:35:27.232788 output: Entry Point: 0x00000000
220 11:35:27.232834 output: Hash algo: crc32
221 11:35:27.232881 output: Hash value: 83448d17
222 11:35:27.232927 output: Image 1 (fdt-1)
223 11:35:27.232973 output: Description: mt8192-asurada-spherion-r0
224 11:35:27.233019 output: Created: Wed Jul 17 12:35:27 2024
225 11:35:27.233065 output: Type: Flat Device Tree
226 11:35:27.233111 output: Compression: uncompressed
227 11:35:27.233158 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:35:27.233205 output: Architecture: AArch64
229 11:35:27.233285 output: Hash algo: crc32
230 11:35:27.233345 output: Hash value: 0f8e4d2e
231 11:35:27.233391 output: Image 2 (ramdisk-1)
232 11:35:27.233436 output: Description: unavailable
233 11:35:27.233482 output: Created: Wed Jul 17 12:35:27 2024
234 11:35:27.233527 output: Type: RAMDisk Image
235 11:35:27.233573 output: Compression: uncompressed
236 11:35:27.233620 output: Data Size: 41210643 Bytes = 40244.77 KiB = 39.30 MiB
237 11:35:27.233665 output: Architecture: AArch64
238 11:35:27.233710 output: OS: Linux
239 11:35:27.233755 output: Load Address: unavailable
240 11:35:27.233800 output: Entry Point: unavailable
241 11:35:27.233846 output: Hash algo: crc32
242 11:35:27.233890 output: Hash value: ecab1aee
243 11:35:27.233936 output: Default Configuration: 'conf-1'
244 11:35:27.233981 output: Configuration 0 (conf-1)
245 11:35:27.234026 output: Description: mt8192-asurada-spherion-r0
246 11:35:27.234072 output: Kernel: kernel-1
247 11:35:27.234117 output: Init Ramdisk: ramdisk-1
248 11:35:27.234162 output: FDT: fdt-1
249 11:35:27.234208 output: Loadables: kernel-1
250 11:35:27.234254 output:
251 11:35:27.234347 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:35:27.234416 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:35:27.234487 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 11:35:27.234558 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:35:27.234613 No LXC device requested
256 11:35:27.234688 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:35:27.234759 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:35:27.234824 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:35:27.234877 Checking files for TFTP limit of 4294967296 bytes.
260 11:35:27.235229 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:35:27.235314 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:35:27.235389 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:35:27.235472 substitutions:
264 11:35:27.235529 - {DTB}: 14864607/tftp-deploy-3gvh_9_g/dtb/mt8192-asurada-spherion-r0.dtb
265 11:35:27.235582 - {INITRD}: 14864607/tftp-deploy-3gvh_9_g/ramdisk/ramdisk.cpio.gz
266 11:35:27.235632 - {KERNEL}: 14864607/tftp-deploy-3gvh_9_g/kernel/Image
267 11:35:27.235680 - {LAVA_MAC}: None
268 11:35:27.235728 - {PRESEED_CONFIG}: None
269 11:35:27.235776 - {PRESEED_LOCAL}: None
270 11:35:27.235824 - {RAMDISK}: 14864607/tftp-deploy-3gvh_9_g/ramdisk/ramdisk.cpio.gz
271 11:35:27.235881 - {ROOT_PART}: None
272 11:35:27.235930 - {ROOT}: None
273 11:35:27.235977 - {SERVER_IP}: 192.168.201.1
274 11:35:27.236024 - {TEE}: None
275 11:35:27.236071 Parsed boot commands:
276 11:35:27.236116 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:35:27.236252 Parsed boot commands: tftpboot 192.168.201.1 14864607/tftp-deploy-3gvh_9_g/kernel/image.itb 14864607/tftp-deploy-3gvh_9_g/kernel/cmdline
278 11:35:27.236329 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:35:27.236399 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:35:27.236468 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:35:27.236535 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:35:27.236589 Not connected, no need to disconnect.
283 11:35:27.236652 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:35:27.236719 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:35:27.236771 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:35:27.239700 Setting prompt string to ['lava-test: # ']
287 11:35:27.239989 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:35:27.240079 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:35:27.240163 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:35:27.240237 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:35:27.240446 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 11:35:36.467512 >> Command sent successfully.
293 11:35:36.481386 Returned 0 in 9 seconds
294 11:35:36.482023 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:35:36.483148 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:35:36.483645 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:35:36.484036 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:35:36.484380 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:35:36.484768 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:35:36.486510 [Enter `^Ec?' for help]
302 11:35:37.861338
303 11:35:37.861857
304 11:35:37.862311 F0: 102B 0000
305 11:35:37.862645
306 11:35:37.862956 F3: 1001 0000 [0200]
307 11:35:37.863263
308 11:35:37.864286 F3: 1001 0000
309 11:35:37.864710
310 11:35:37.865082 F7: 102D 0000
311 11:35:37.865590
312 11:35:37.865948 F1: 0000 0000
313 11:35:37.867885
314 11:35:37.868296 V0: 0000 0000 [0001]
315 11:35:37.868613
316 11:35:37.868909 00: 0007 8000
317 11:35:37.869204
318 11:35:37.872250 01: 0000 0000
319 11:35:37.872675
320 11:35:37.873013 BP: 0C00 0209 [0000]
321 11:35:37.873553
322 11:35:37.875894 G0: 1182 0000
323 11:35:37.876486
324 11:35:37.876973 EC: 0000 0021 [4000]
325 11:35:37.877477
326 11:35:37.878650 S7: 0000 0000 [0000]
327 11:35:37.879067
328 11:35:37.879390 CC: 0000 0000 [0001]
329 11:35:37.879689
330 11:35:37.882337 T0: 0000 0040 [010F]
331 11:35:37.882758
332 11:35:37.883206 Jump to BL
333 11:35:37.883690
334 11:35:37.907586
335 11:35:37.908067
336 11:35:37.914322 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:35:37.917723 ARM64: Exception handlers installed.
338 11:35:37.921361 ARM64: Testing exception
339 11:35:37.925111 ARM64: Done test exception
340 11:35:37.932477 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:35:37.942925 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:35:37.950376 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:35:37.958374 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:35:37.964824 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:35:37.972548 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:35:37.984816 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:35:37.992459 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:35:38.011795 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:35:38.014918 WDT: Last reset was cold boot
350 11:35:38.019165 SPI1(PAD0) initialized at 2873684 Hz
351 11:35:38.022308 SPI5(PAD0) initialized at 992727 Hz
352 11:35:38.022866 VBOOT: Loading verstage.
353 11:35:38.030050 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:35:38.034088 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:35:38.036466 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:35:38.040047 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:35:38.048307 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:35:38.055251 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:35:38.066223 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:35:38.066653
361 11:35:38.066976
362 11:35:38.077621 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:35:38.081288 ARM64: Exception handlers installed.
364 11:35:38.081714 ARM64: Testing exception
365 11:35:38.084453 ARM64: Done test exception
366 11:35:38.088298 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:35:38.091797 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:35:38.107352 Probing TPM: . done!
369 11:35:38.107778 TPM ready after 0 ms
370 11:35:38.113952 Connected to device vid:did:rid of 1ae0:0028:00
371 11:35:38.121031 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 11:35:38.176611 Initialized TPM device CR50 revision 0
373 11:35:38.187071 tlcl_send_startup: Startup return code is 0
374 11:35:38.187629 TPM: setup succeeded
375 11:35:38.198741 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:35:38.207818 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:35:38.217358 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:35:38.226197 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:35:38.229569 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:35:38.232805 in-header: 03 07 00 00 08 00 00 00
381 11:35:38.236733 in-data: aa e4 47 04 13 02 00 00
382 11:35:38.239766 Chrome EC: UHEPI supported
383 11:35:38.246417 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:35:38.249321 in-header: 03 a9 00 00 08 00 00 00
385 11:35:38.253202 in-data: 84 60 60 08 00 00 00 00
386 11:35:38.253669 Phase 1
387 11:35:38.256356 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:35:38.262666 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:35:38.269669 VB2:vb2_check_recovery() Recovery was requested manually
390 11:35:38.272721 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:35:38.276235 Recovery requested (1009000e)
392 11:35:38.284293 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:35:38.289594 tlcl_extend: response is 0
394 11:35:38.298071 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:35:38.303706 tlcl_extend: response is 0
396 11:35:38.310469 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:35:38.330712 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:35:38.336857 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:35:38.337273
400 11:35:38.337573
401 11:35:38.348208 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:35:38.350466 ARM64: Exception handlers installed.
403 11:35:38.354166 ARM64: Testing exception
404 11:35:38.354544 ARM64: Done test exception
405 11:35:38.376490 pmic_efuse_setting: Set efuses in 11 msecs
406 11:35:38.379840 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:35:38.386116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:35:38.389512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:35:38.395911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:35:38.399991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:35:38.406314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:35:38.409547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:35:38.413676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:35:38.419204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:35:38.422756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:35:38.429970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:35:38.432940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:35:38.435965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:35:38.442814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:35:38.449953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:35:38.452831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:35:38.459439 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:35:38.466403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:35:38.472790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:35:38.475984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:35:38.482721 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:35:38.489511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:35:38.492751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:35:38.499325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:35:38.505748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:35:38.509429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:35:38.515792 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:35:38.519224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:35:38.525971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:35:38.529467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:35:38.536526 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:35:38.539139 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:35:38.545769 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:35:38.549935 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:35:38.556305 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:35:38.559098 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:35:38.565857 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:35:38.569740 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:35:38.575999 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:35:38.579852 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:35:38.584336 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:35:38.587931 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:35:38.594418 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:35:38.599361 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:35:38.601771 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:35:38.605138 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:35:38.612740 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:35:38.615845 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:35:38.619182 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:35:38.622474 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:35:38.625600 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:35:38.632776 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:35:38.638730 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:35:38.649121 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:35:38.652519 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:35:38.659001 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:35:38.668758 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:35:38.672846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:35:38.679703 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:35:38.682884 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:35:38.689025 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
467 11:35:38.695935 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:35:38.700042 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:35:38.702039 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:35:38.714206 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:35:38.723077 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 11:35:38.733545 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 11:35:38.743053 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 11:35:38.751229 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:35:38.761337 [RTC]rtc_get_frequency_meter,154: input=16, output=786
476 11:35:38.771714 [RTC]rtc_get_frequency_meter,154: input=17, output=809
477 11:35:38.773984 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:35:38.780941 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:35:38.784196 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:35:38.787783 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:35:38.794064 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:35:38.797866 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:35:38.801222 ADC[4]: Raw value=670800 ID=5
484 11:35:38.801768 ADC[3]: Raw value=212549 ID=1
485 11:35:38.804358 RAM Code: 0x51
486 11:35:38.807561 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:35:38.815610 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:35:38.822012 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:35:38.828479 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:35:38.830689 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:35:38.834381 in-header: 03 07 00 00 08 00 00 00
492 11:35:38.837933 in-data: aa e4 47 04 13 02 00 00
493 11:35:38.841202 Chrome EC: UHEPI supported
494 11:35:38.847964 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:35:38.850934 in-header: 03 a9 00 00 08 00 00 00
496 11:35:38.854057 in-data: 84 60 60 08 00 00 00 00
497 11:35:38.857628 MRC: failed to locate region type 0.
498 11:35:38.864171 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:35:38.868034 DRAM-K: Running full calibration
500 11:35:38.871117 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:35:38.874449 header.status = 0x0
502 11:35:38.878011 header.version = 0x6 (expected: 0x6)
503 11:35:38.881153 header.size = 0xd00 (expected: 0xd00)
504 11:35:38.881749 header.flags = 0x0
505 11:35:38.887864 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:35:38.906261 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 11:35:38.912847 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:35:38.916858 dram_init: ddr_geometry: 0
509 11:35:38.919921 [EMI] MDL number = 0
510 11:35:38.920342 [EMI] Get MDL freq = 0
511 11:35:38.922804 dram_init: ddr_type: 0
512 11:35:38.923276 is_discrete_lpddr4: 1
513 11:35:38.926770 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:35:38.927240
515 11:35:38.927563
516 11:35:38.930444 [Bian_co] ETT version 0.0.0.1
517 11:35:38.937363 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:35:38.937827
519 11:35:38.939235 dramc_set_vcore_voltage set vcore to 650000
520 11:35:38.942790 Read voltage for 800, 4
521 11:35:38.943259 Vio18 = 0
522 11:35:38.943588 Vcore = 650000
523 11:35:38.945815 Vdram = 0
524 11:35:38.946307 Vddq = 0
525 11:35:38.946633 Vmddr = 0
526 11:35:38.949525 dram_init: config_dvfs: 1
527 11:35:38.952974 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:35:38.959204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:35:38.962731 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:35:38.965829 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:35:38.970783 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:35:38.972497 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:35:38.975717 MEM_TYPE=3, freq_sel=18
534 11:35:38.979107 sv_algorithm_assistance_LP4_1600
535 11:35:38.982337 ============ PULL DRAM RESETB DOWN ============
536 11:35:38.989276 ========== PULL DRAM RESETB DOWN end =========
537 11:35:38.993283 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:35:38.995672 ===================================
539 11:35:38.999545 LPDDR4 DRAM CONFIGURATION
540 11:35:39.002375 ===================================
541 11:35:39.002756 EX_ROW_EN[0] = 0x0
542 11:35:39.005676 EX_ROW_EN[1] = 0x0
543 11:35:39.006094 LP4Y_EN = 0x0
544 11:35:39.009096 WORK_FSP = 0x0
545 11:35:39.009508 WL = 0x2
546 11:35:39.012230 RL = 0x2
547 11:35:39.012607 BL = 0x2
548 11:35:39.015711 RPST = 0x0
549 11:35:39.016090 RD_PRE = 0x0
550 11:35:39.019062 WR_PRE = 0x1
551 11:35:39.019447 WR_PST = 0x0
552 11:35:39.022500 DBI_WR = 0x0
553 11:35:39.025827 DBI_RD = 0x0
554 11:35:39.026208 OTF = 0x1
555 11:35:39.029512 ===================================
556 11:35:39.032409 ===================================
557 11:35:39.032877 ANA top config
558 11:35:39.036531 ===================================
559 11:35:39.039274 DLL_ASYNC_EN = 0
560 11:35:39.042876 ALL_SLAVE_EN = 1
561 11:35:39.045870 NEW_RANK_MODE = 1
562 11:35:39.048939 DLL_IDLE_MODE = 1
563 11:35:39.049339 LP45_APHY_COMB_EN = 1
564 11:35:39.052571 TX_ODT_DIS = 1
565 11:35:39.055998 NEW_8X_MODE = 1
566 11:35:39.059104 ===================================
567 11:35:39.062170 ===================================
568 11:35:39.065687 data_rate = 1600
569 11:35:39.069626 CKR = 1
570 11:35:39.070101 DQ_P2S_RATIO = 8
571 11:35:39.072847 ===================================
572 11:35:39.075516 CA_P2S_RATIO = 8
573 11:35:39.079239 DQ_CA_OPEN = 0
574 11:35:39.082567 DQ_SEMI_OPEN = 0
575 11:35:39.085915 CA_SEMI_OPEN = 0
576 11:35:39.089024 CA_FULL_RATE = 0
577 11:35:39.089472 DQ_CKDIV4_EN = 1
578 11:35:39.093305 CA_CKDIV4_EN = 1
579 11:35:39.095570 CA_PREDIV_EN = 0
580 11:35:39.099162 PH8_DLY = 0
581 11:35:39.102786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:35:39.103247 DQ_AAMCK_DIV = 4
583 11:35:39.105894 CA_AAMCK_DIV = 4
584 11:35:39.109373 CA_ADMCK_DIV = 4
585 11:35:39.112545 DQ_TRACK_CA_EN = 0
586 11:35:39.116431 CA_PICK = 800
587 11:35:39.118788 CA_MCKIO = 800
588 11:35:39.122705 MCKIO_SEMI = 0
589 11:35:39.123125 PLL_FREQ = 3068
590 11:35:39.125687 DQ_UI_PI_RATIO = 32
591 11:35:39.129609 CA_UI_PI_RATIO = 0
592 11:35:39.132687 ===================================
593 11:35:39.135503 ===================================
594 11:35:39.138980 memory_type:LPDDR4
595 11:35:39.142382 GP_NUM : 10
596 11:35:39.142851 SRAM_EN : 1
597 11:35:39.145862 MD32_EN : 0
598 11:35:39.149392 ===================================
599 11:35:39.149900 [ANA_INIT] >>>>>>>>>>>>>>
600 11:35:39.152602 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:35:39.156045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:35:39.158922 ===================================
603 11:35:39.161842 data_rate = 1600,PCW = 0X7600
604 11:35:39.165431 ===================================
605 11:35:39.168538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:35:39.176169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:35:39.178720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:35:39.185880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:35:39.189215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:35:39.192203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:35:39.192583 [ANA_INIT] flow start
612 11:35:39.195518 [ANA_INIT] PLL >>>>>>>>
613 11:35:39.198828 [ANA_INIT] PLL <<<<<<<<
614 11:35:39.202386 [ANA_INIT] MIDPI >>>>>>>>
615 11:35:39.202806 [ANA_INIT] MIDPI <<<<<<<<
616 11:35:39.205646 [ANA_INIT] DLL >>>>>>>>
617 11:35:39.206056 [ANA_INIT] flow end
618 11:35:39.212376 ============ LP4 DIFF to SE enter ============
619 11:35:39.216214 ============ LP4 DIFF to SE exit ============
620 11:35:39.218623 [ANA_INIT] <<<<<<<<<<<<<
621 11:35:39.222247 [Flow] Enable top DCM control >>>>>
622 11:35:39.225628 [Flow] Enable top DCM control <<<<<
623 11:35:39.228891 Enable DLL master slave shuffle
624 11:35:39.232539 ==============================================================
625 11:35:39.235924 Gating Mode config
626 11:35:39.239321 ==============================================================
627 11:35:39.243086 Config description:
628 11:35:39.253190 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:35:39.256859 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:35:39.263879 SELPH_MODE 0: By rank 1: By Phase
631 11:35:39.267387 ==============================================================
632 11:35:39.270851 GAT_TRACK_EN = 1
633 11:35:39.275126 RX_GATING_MODE = 2
634 11:35:39.278416 RX_GATING_TRACK_MODE = 2
635 11:35:39.284769 SELPH_MODE = 1
636 11:35:39.285146 PICG_EARLY_EN = 1
637 11:35:39.286298 VALID_LAT_VALUE = 1
638 11:35:39.293019 ==============================================================
639 11:35:39.296744 Enter into Gating configuration >>>>
640 11:35:39.299461 Exit from Gating configuration <<<<
641 11:35:39.302608 Enter into DVFS_PRE_config >>>>>
642 11:35:39.312184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:35:39.316313 Exit from DVFS_PRE_config <<<<<
644 11:35:39.319047 Enter into PICG configuration >>>>
645 11:35:39.322083 Exit from PICG configuration <<<<
646 11:35:39.325841 [RX_INPUT] configuration >>>>>
647 11:35:39.329080 [RX_INPUT] configuration <<<<<
648 11:35:39.333061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:35:39.339128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:35:39.345760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:35:39.353274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:35:39.355899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:35:39.362294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:35:39.365907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:35:39.372755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:35:39.375907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:35:39.379170 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:35:39.382445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:35:39.388857 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:35:39.392444 ===================================
661 11:35:39.392891 LPDDR4 DRAM CONFIGURATION
662 11:35:39.395483 ===================================
663 11:35:39.399371 EX_ROW_EN[0] = 0x0
664 11:35:39.402529 EX_ROW_EN[1] = 0x0
665 11:35:39.403033 LP4Y_EN = 0x0
666 11:35:39.405327 WORK_FSP = 0x0
667 11:35:39.405864 WL = 0x2
668 11:35:39.408916 RL = 0x2
669 11:35:39.409349 BL = 0x2
670 11:35:39.412067 RPST = 0x0
671 11:35:39.412447 RD_PRE = 0x0
672 11:35:39.415696 WR_PRE = 0x1
673 11:35:39.416081 WR_PST = 0x0
674 11:35:39.419254 DBI_WR = 0x0
675 11:35:39.419637 DBI_RD = 0x0
676 11:35:39.422152 OTF = 0x1
677 11:35:39.425587 ===================================
678 11:35:39.428740 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:35:39.431895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:35:39.438656 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:35:39.442953 ===================================
682 11:35:39.443339 LPDDR4 DRAM CONFIGURATION
683 11:35:39.446249 ===================================
684 11:35:39.449182 EX_ROW_EN[0] = 0x10
685 11:35:39.452944 EX_ROW_EN[1] = 0x0
686 11:35:39.453419 LP4Y_EN = 0x0
687 11:35:39.455696 WORK_FSP = 0x0
688 11:35:39.456082 WL = 0x2
689 11:35:39.459193 RL = 0x2
690 11:35:39.459628 BL = 0x2
691 11:35:39.461993 RPST = 0x0
692 11:35:39.462377 RD_PRE = 0x0
693 11:35:39.465298 WR_PRE = 0x1
694 11:35:39.465679 WR_PST = 0x0
695 11:35:39.468921 DBI_WR = 0x0
696 11:35:39.469364 DBI_RD = 0x0
697 11:35:39.472385 OTF = 0x1
698 11:35:39.475367 ===================================
699 11:35:39.482094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:35:39.485421 nWR fixed to 40
701 11:35:39.485813 [ModeRegInit_LP4] CH0 RK0
702 11:35:39.488518 [ModeRegInit_LP4] CH0 RK1
703 11:35:39.491992 [ModeRegInit_LP4] CH1 RK0
704 11:35:39.495649 [ModeRegInit_LP4] CH1 RK1
705 11:35:39.496082 match AC timing 12
706 11:35:39.498307 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:35:39.505364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:35:39.508831 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:35:39.511930 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:35:39.518738 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:35:39.519127 [EMI DOE] emi_dcm 0
712 11:35:39.525465 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:35:39.525948 ==
714 11:35:39.528396 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:35:39.532154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:35:39.532545 ==
717 11:35:39.538876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:35:39.541947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:35:39.552547 [CA 0] Center 37 (7~68) winsize 62
720 11:35:39.555390 [CA 1] Center 37 (7~68) winsize 62
721 11:35:39.558847 [CA 2] Center 35 (5~66) winsize 62
722 11:35:39.562472 [CA 3] Center 35 (4~66) winsize 63
723 11:35:39.565367 [CA 4] Center 34 (3~65) winsize 63
724 11:35:39.568875 [CA 5] Center 34 (3~65) winsize 63
725 11:35:39.569369
726 11:35:39.572112 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:35:39.572534
728 11:35:39.576314 [CATrainingPosCal] consider 1 rank data
729 11:35:39.579677 u2DelayCellTimex100 = 270/100 ps
730 11:35:39.582742 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 11:35:39.585775 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 11:35:39.588960 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 11:35:39.595552 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 11:35:39.598889 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
735 11:35:39.602873 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
736 11:35:39.603104
737 11:35:39.605895 CA PerBit enable=1, Macro0, CA PI delay=34
738 11:35:39.606158
739 11:35:39.608789 [CBTSetCACLKResult] CA Dly = 34
740 11:35:39.609034 CS Dly: 6 (0~37)
741 11:35:39.609190 ==
742 11:35:39.612090 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:35:39.619055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:35:39.619463 ==
745 11:35:39.622817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:35:39.629100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:35:39.638483 [CA 0] Center 37 (7~68) winsize 62
748 11:35:39.641191 [CA 1] Center 37 (6~68) winsize 63
749 11:35:39.644967 [CA 2] Center 35 (4~66) winsize 63
750 11:35:39.648519 [CA 3] Center 35 (4~66) winsize 63
751 11:35:39.651164 [CA 4] Center 33 (3~64) winsize 62
752 11:35:39.654540 [CA 5] Center 34 (3~65) winsize 63
753 11:35:39.655044
754 11:35:39.657752 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 11:35:39.658352
756 11:35:39.661137 [CATrainingPosCal] consider 2 rank data
757 11:35:39.664184 u2DelayCellTimex100 = 270/100 ps
758 11:35:39.667602 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:35:39.671700 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:35:39.677852 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:35:39.680912 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 11:35:39.684873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:35:39.688214 CA5 delay=34 (3~65),Diff = 1 PI (7 cell)
764 11:35:39.688695
765 11:35:39.691305 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:35:39.691692
767 11:35:39.694197 [CBTSetCACLKResult] CA Dly = 33
768 11:35:39.694587 CS Dly: 6 (0~37)
769 11:35:39.697539
770 11:35:39.700830 ----->DramcWriteLeveling(PI) begin...
771 11:35:39.701275 ==
772 11:35:39.704265 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:35:39.707755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:35:39.708247 ==
775 11:35:39.711373 Write leveling (Byte 0): 27 => 27
776 11:35:39.714925 Write leveling (Byte 1): 28 => 28
777 11:35:39.718308 DramcWriteLeveling(PI) end<-----
778 11:35:39.718773
779 11:35:39.719082 ==
780 11:35:39.720901 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:35:39.724873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:35:39.725296 ==
783 11:35:39.727939 [Gating] SW mode calibration
784 11:35:39.733974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:35:39.741043 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:35:39.744300 0 6 0 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 0)
787 11:35:39.748173 0 6 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
788 11:35:39.751244 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:35:39.757698 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:35:39.760815 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:35:39.764364 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:35:39.770830 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:35:39.775093 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:35:39.777925 0 7 0 | B1->B0 | 2525 2828 | 0 0 | (1 1) (0 0)
795 11:35:39.784568 0 7 4 | B1->B0 | 3838 3d3d | 0 1 | (0 0) (0 0)
796 11:35:39.787820 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:35:39.791312 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:35:39.798160 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:35:39.800914 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:35:39.805347 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:35:39.810738 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:35:39.814429 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 11:35:39.818239 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
804 11:35:39.825053 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:35:39.828600 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:35:39.831791 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:35:39.834986 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:35:39.841268 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:35:39.845590 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:35:39.847924 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:35:39.854802 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:35:39.859238 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:35:39.862034 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:35:39.868412 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:35:39.871485 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:35:39.875274 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:35:39.881795 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 11:35:39.885751 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
819 11:35:39.887749 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 11:35:39.891416 Total UI for P1: 0, mck2ui 16
821 11:35:39.894526 best dqsien dly found for B0: ( 0, 10, 2)
822 11:35:39.898077 Total UI for P1: 0, mck2ui 16
823 11:35:39.902088 best dqsien dly found for B1: ( 0, 10, 2)
824 11:35:39.904694 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 11:35:39.908292 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 11:35:39.908797
827 11:35:39.911896 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 11:35:39.918055 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 11:35:39.918527 [Gating] SW calibration Done
830 11:35:39.918860 ==
831 11:35:39.921176 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:35:39.928260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:35:39.928770 ==
834 11:35:39.929104 RX Vref Scan: 0
835 11:35:39.929483
836 11:35:39.932313 RX Vref 0 -> 0, step: 1
837 11:35:39.932801
838 11:35:39.935021 RX Delay -130 -> 252, step: 16
839 11:35:39.938033 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 11:35:39.941395 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:35:39.945554 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 11:35:39.952281 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:35:39.955047 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 11:35:39.957898 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:35:39.961714 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
846 11:35:39.964935 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
847 11:35:39.971374 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:35:39.975266 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 11:35:39.978602 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:35:39.981753 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:35:39.985084 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:35:39.991230 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 11:35:39.994627 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:35:39.997854 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:35:39.998279 ==
856 11:35:40.001439 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:35:40.004937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:35:40.005355 ==
859 11:35:40.007547 DQS Delay:
860 11:35:40.007928 DQS0 = 0, DQS1 = 0
861 11:35:40.011621 DQM Delay:
862 11:35:40.012003 DQM0 = 84, DQM1 = 74
863 11:35:40.012298 DQ Delay:
864 11:35:40.014680 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 11:35:40.018176 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
866 11:35:40.021298 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 11:35:40.025139 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 11:35:40.025606
869 11:35:40.025902
870 11:35:40.028087 ==
871 11:35:40.031345 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:35:40.034680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:35:40.035070 ==
874 11:35:40.035364
875 11:35:40.035634
876 11:35:40.037782 TX Vref Scan disable
877 11:35:40.038288 == TX Byte 0 ==
878 11:35:40.044532 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 11:35:40.048152 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 11:35:40.048629 == TX Byte 1 ==
881 11:35:40.054910 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 11:35:40.057632 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 11:35:40.058059 ==
884 11:35:40.060835 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:35:40.064458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:35:40.064903 ==
887 11:35:40.078069 TX Vref=22, minBit 2, minWin=27, winSum=445
888 11:35:40.080729 TX Vref=24, minBit 4, minWin=27, winSum=450
889 11:35:40.084462 TX Vref=26, minBit 4, minWin=27, winSum=451
890 11:35:40.088312 TX Vref=28, minBit 0, minWin=28, winSum=451
891 11:35:40.090707 TX Vref=30, minBit 2, minWin=28, winSum=457
892 11:35:40.094506 TX Vref=32, minBit 0, minWin=28, winSum=452
893 11:35:40.101385 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
894 11:35:40.101769
895 11:35:40.103860 Final TX Range 1 Vref 30
896 11:35:40.104244
897 11:35:40.104535 ==
898 11:35:40.107551 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:35:40.111195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:35:40.111578 ==
901 11:35:40.114149
902 11:35:40.114686
903 11:35:40.115121 TX Vref Scan disable
904 11:35:40.117342 == TX Byte 0 ==
905 11:35:40.120958 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 11:35:40.124143 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 11:35:40.128093 == TX Byte 1 ==
908 11:35:40.130752 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
909 11:35:40.134320 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
910 11:35:40.137144
911 11:35:40.137552 [DATLAT]
912 11:35:40.137849 Freq=800, CH0 RK0
913 11:35:40.138124
914 11:35:40.140476 DATLAT Default: 0xa
915 11:35:40.140860 0, 0xFFFF, sum = 0
916 11:35:40.143915 1, 0xFFFF, sum = 0
917 11:35:40.144334 2, 0xFFFF, sum = 0
918 11:35:40.147482 3, 0xFFFF, sum = 0
919 11:35:40.147879 4, 0xFFFF, sum = 0
920 11:35:40.150986 5, 0xFFFF, sum = 0
921 11:35:40.151381 6, 0xFFFF, sum = 0
922 11:35:40.154239 7, 0xFFFF, sum = 0
923 11:35:40.154517 8, 0x0, sum = 1
924 11:35:40.158462 9, 0x0, sum = 2
925 11:35:40.158730 10, 0x0, sum = 3
926 11:35:40.160997 11, 0x0, sum = 4
927 11:35:40.161213 best_step = 9
928 11:35:40.161406
929 11:35:40.161555 ==
930 11:35:40.164057 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:35:40.170243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:35:40.170412 ==
933 11:35:40.170525 RX Vref Scan: 1
934 11:35:40.170625
935 11:35:40.173621 Set Vref Range= 32 -> 127
936 11:35:40.173759
937 11:35:40.177179 RX Vref 32 -> 127, step: 1
938 11:35:40.177354
939 11:35:40.177467 RX Delay -111 -> 252, step: 8
940 11:35:40.180156
941 11:35:40.180267 Set Vref, RX VrefLevel [Byte0]: 32
942 11:35:40.183565 [Byte1]: 32
943 11:35:40.187657
944 11:35:40.187747 Set Vref, RX VrefLevel [Byte0]: 33
945 11:35:40.191582 [Byte1]: 33
946 11:35:40.196857
947 11:35:40.197321 Set Vref, RX VrefLevel [Byte0]: 34
948 11:35:40.200021 [Byte1]: 34
949 11:35:40.203527
950 11:35:40.203826 Set Vref, RX VrefLevel [Byte0]: 35
951 11:35:40.206879 [Byte1]: 35
952 11:35:40.211860
953 11:35:40.212221 Set Vref, RX VrefLevel [Byte0]: 36
954 11:35:40.215036 [Byte1]: 36
955 11:35:40.219167
956 11:35:40.219545 Set Vref, RX VrefLevel [Byte0]: 37
957 11:35:40.223122 [Byte1]: 37
958 11:35:40.227098
959 11:35:40.227621 Set Vref, RX VrefLevel [Byte0]: 38
960 11:35:40.230505 [Byte1]: 38
961 11:35:40.234892
962 11:35:40.235240 Set Vref, RX VrefLevel [Byte0]: 39
963 11:35:40.237257 [Byte1]: 39
964 11:35:40.242052
965 11:35:40.242472 Set Vref, RX VrefLevel [Byte0]: 40
966 11:35:40.245168 [Byte1]: 40
967 11:35:40.249946
968 11:35:40.250414 Set Vref, RX VrefLevel [Byte0]: 41
969 11:35:40.253456 [Byte1]: 41
970 11:35:40.257408
971 11:35:40.257919 Set Vref, RX VrefLevel [Byte0]: 42
972 11:35:40.260720 [Byte1]: 42
973 11:35:40.265315
974 11:35:40.265740 Set Vref, RX VrefLevel [Byte0]: 43
975 11:35:40.267838 [Byte1]: 43
976 11:35:40.273308
977 11:35:40.273734 Set Vref, RX VrefLevel [Byte0]: 44
978 11:35:40.275851 [Byte1]: 44
979 11:35:40.279855
980 11:35:40.280284 Set Vref, RX VrefLevel [Byte0]: 45
981 11:35:40.283654 [Byte1]: 45
982 11:35:40.288133
983 11:35:40.288626 Set Vref, RX VrefLevel [Byte0]: 46
984 11:35:40.291260 [Byte1]: 46
985 11:35:40.295706
986 11:35:40.296172 Set Vref, RX VrefLevel [Byte0]: 47
987 11:35:40.298802 [Byte1]: 47
988 11:35:40.303633
989 11:35:40.304138 Set Vref, RX VrefLevel [Byte0]: 48
990 11:35:40.306434 [Byte1]: 48
991 11:35:40.310447
992 11:35:40.310911 Set Vref, RX VrefLevel [Byte0]: 49
993 11:35:40.313934 [Byte1]: 49
994 11:35:40.318349
995 11:35:40.318773 Set Vref, RX VrefLevel [Byte0]: 50
996 11:35:40.321795 [Byte1]: 50
997 11:35:40.326098
998 11:35:40.326567 Set Vref, RX VrefLevel [Byte0]: 51
999 11:35:40.328932 [Byte1]: 51
1000 11:35:40.333772
1001 11:35:40.334239 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:35:40.336712 [Byte1]: 52
1003 11:35:40.341643
1004 11:35:40.342198 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:35:40.344971 [Byte1]: 53
1006 11:35:40.348900
1007 11:35:40.349420 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:35:40.352155 [Byte1]: 54
1009 11:35:40.356586
1010 11:35:40.357011 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:35:40.360222 [Byte1]: 55
1012 11:35:40.364367
1013 11:35:40.364796 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:35:40.367272 [Byte1]: 56
1015 11:35:40.371572
1016 11:35:40.371994 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:35:40.376133 [Byte1]: 57
1018 11:35:40.379846
1019 11:35:40.380267 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:35:40.382524 [Byte1]: 58
1021 11:35:40.387041
1022 11:35:40.387473 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:35:40.390775 [Byte1]: 59
1024 11:35:40.395027
1025 11:35:40.395522 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:35:40.398077 [Byte1]: 60
1027 11:35:40.402369
1028 11:35:40.402790 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:35:40.405821 [Byte1]: 61
1030 11:35:40.410252
1031 11:35:40.410725 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:35:40.413291 [Byte1]: 62
1033 11:35:40.418358
1034 11:35:40.418856 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:35:40.420725 [Byte1]: 63
1036 11:35:40.425191
1037 11:35:40.425690 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:35:40.428991 [Byte1]: 64
1039 11:35:40.434200
1040 11:35:40.434670 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:35:40.436013 [Byte1]: 65
1042 11:35:40.440573
1043 11:35:40.441001 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:35:40.443820 [Byte1]: 66
1045 11:35:40.447820
1046 11:35:40.448251 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:35:40.451701 [Byte1]: 67
1048 11:35:40.456023
1049 11:35:40.456683 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:35:40.459190 [Byte1]: 68
1051 11:35:40.463288
1052 11:35:40.463663 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:35:40.467562 [Byte1]: 69
1054 11:35:40.470896
1055 11:35:40.471279 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:35:40.475302 [Byte1]: 70
1057 11:35:40.479351
1058 11:35:40.479746 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:35:40.482108 [Byte1]: 71
1060 11:35:40.487486
1061 11:35:40.487848 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:35:40.489759 [Byte1]: 72
1063 11:35:40.494273
1064 11:35:40.494660 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:35:40.497404 [Byte1]: 73
1066 11:35:40.502655
1067 11:35:40.503045 Final RX Vref Byte 0 = 54 to rank0
1068 11:35:40.505396 Final RX Vref Byte 1 = 56 to rank0
1069 11:35:40.508809 Final RX Vref Byte 0 = 54 to rank1
1070 11:35:40.511621 Final RX Vref Byte 1 = 56 to rank1==
1071 11:35:40.515293 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 11:35:40.522352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 11:35:40.522741 ==
1074 11:35:40.523036 DQS Delay:
1075 11:35:40.523305 DQS0 = 0, DQS1 = 0
1076 11:35:40.525525 DQM Delay:
1077 11:35:40.525947 DQM0 = 83, DQM1 = 73
1078 11:35:40.528647 DQ Delay:
1079 11:35:40.531985 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 11:35:40.532440 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1081 11:35:40.534687 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 11:35:40.538022 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1083 11:35:40.541446
1084 11:35:40.542061
1085 11:35:40.548153 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1086 11:35:40.551995 CH0 RK0: MR19=606, MR18=3535
1087 11:35:40.558228 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1088 11:35:40.558641
1089 11:35:40.561333 ----->DramcWriteLeveling(PI) begin...
1090 11:35:40.561715 ==
1091 11:35:40.564973 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 11:35:40.568216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 11:35:40.568599 ==
1094 11:35:40.572160 Write leveling (Byte 0): 29 => 29
1095 11:35:40.574896 Write leveling (Byte 1): 28 => 28
1096 11:35:40.578095 DramcWriteLeveling(PI) end<-----
1097 11:35:40.578475
1098 11:35:40.578767 ==
1099 11:35:40.581718 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 11:35:40.584606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 11:35:40.584987 ==
1102 11:35:40.588774 [Gating] SW mode calibration
1103 11:35:40.595442 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 11:35:40.602150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 11:35:40.605488 0 6 0 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
1106 11:35:40.608866 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1107 11:35:40.614709 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 11:35:40.618417 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 11:35:40.621626 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 11:35:40.627925 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 11:35:40.631884 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 11:35:40.635392 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 11:35:40.641866 0 7 0 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1114 11:35:40.645151 0 7 4 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (1 1)
1115 11:35:40.648315 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 11:35:40.654912 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 11:35:40.658239 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 11:35:40.661816 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 11:35:40.668043 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 11:35:40.671371 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 11:35:40.674904 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:35:40.681553 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1123 11:35:40.684903 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 11:35:40.689098 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 11:35:40.691879 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 11:35:40.698451 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 11:35:40.701593 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 11:35:40.705133 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 11:35:40.711536 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:35:40.715087 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:35:40.719170 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:35:40.724717 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:35:40.727774 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:35:40.731584 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:35:40.738066 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:35:40.741494 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:35:40.744328 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1138 11:35:40.751352 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1139 11:35:40.754833 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 11:35:40.758163 Total UI for P1: 0, mck2ui 16
1141 11:35:40.761023 best dqsien dly found for B0: ( 0, 10, 2)
1142 11:35:40.764373 Total UI for P1: 0, mck2ui 16
1143 11:35:40.767916 best dqsien dly found for B1: ( 0, 10, 2)
1144 11:35:40.771227 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1145 11:35:40.774918 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1146 11:35:40.775194
1147 11:35:40.777693 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1148 11:35:40.781756 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1149 11:35:40.784617 [Gating] SW calibration Done
1150 11:35:40.784907 ==
1151 11:35:40.829572 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 11:35:40.830334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 11:35:40.830699 ==
1154 11:35:40.831077 RX Vref Scan: 0
1155 11:35:40.831442
1156 11:35:40.831794 RX Vref 0 -> 0, step: 1
1157 11:35:40.832146
1158 11:35:40.832568 RX Delay -130 -> 252, step: 16
1159 11:35:40.832893 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1160 11:35:40.833268 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1161 11:35:40.833706 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1162 11:35:40.834215 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1163 11:35:40.834540 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1164 11:35:40.834884 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1165 11:35:40.835225 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1166 11:35:40.844104 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1167 11:35:40.844778 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1168 11:35:40.845493 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1169 11:35:40.847013 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1170 11:35:40.849891 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1171 11:35:40.850282 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1172 11:35:40.856359 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1173 11:35:40.860095 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1174 11:35:40.863577 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1175 11:35:40.863973 ==
1176 11:35:40.866578 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 11:35:40.869601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1178 11:35:40.873532 ==
1179 11:35:40.873910 DQS Delay:
1180 11:35:40.874410 DQS0 = 0, DQS1 = 0
1181 11:35:40.876893 DQM Delay:
1182 11:35:40.877318 DQM0 = 81, DQM1 = 72
1183 11:35:40.877623 DQ Delay:
1184 11:35:40.880108 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1185 11:35:40.883477 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1186 11:35:40.887172 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1187 11:35:40.890129 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1188 11:35:40.890507
1189 11:35:40.890859
1190 11:35:40.893414 ==
1191 11:35:40.896482 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 11:35:40.900112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1193 11:35:40.900493 ==
1194 11:35:40.900788
1195 11:35:40.901056
1196 11:35:40.903225 TX Vref Scan disable
1197 11:35:40.903614 == TX Byte 0 ==
1198 11:35:40.909549 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1199 11:35:40.912835 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1200 11:35:40.913297 == TX Byte 1 ==
1201 11:35:40.919762 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1202 11:35:40.923161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1203 11:35:40.923542 ==
1204 11:35:40.926471 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 11:35:40.930200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 11:35:40.930629 ==
1207 11:35:40.942886 TX Vref=22, minBit 6, minWin=27, winSum=446
1208 11:35:40.945986 TX Vref=24, minBit 2, minWin=28, winSum=457
1209 11:35:40.949584 TX Vref=26, minBit 2, minWin=28, winSum=457
1210 11:35:40.953265 TX Vref=28, minBit 2, minWin=28, winSum=455
1211 11:35:40.956160 TX Vref=30, minBit 2, minWin=28, winSum=456
1212 11:35:40.960593 TX Vref=32, minBit 2, minWin=28, winSum=458
1213 11:35:40.966686 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 32
1214 11:35:40.967069
1215 11:35:40.970174 Final TX Range 1 Vref 32
1216 11:35:40.970556
1217 11:35:40.970847 ==
1218 11:35:40.972899 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 11:35:40.976524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 11:35:40.976924 ==
1221 11:35:40.977418
1222 11:35:40.979846
1223 11:35:40.980243 TX Vref Scan disable
1224 11:35:40.983175 == TX Byte 0 ==
1225 11:35:40.986450 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1226 11:35:40.990370 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1227 11:35:40.992821 == TX Byte 1 ==
1228 11:35:40.996384 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1229 11:35:40.999660 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1230 11:35:41.000041
1231 11:35:41.003006 [DATLAT]
1232 11:35:41.003381 Freq=800, CH0 RK1
1233 11:35:41.003725
1234 11:35:41.006722 DATLAT Default: 0x9
1235 11:35:41.007154 0, 0xFFFF, sum = 0
1236 11:35:41.009901 1, 0xFFFF, sum = 0
1237 11:35:41.010330 2, 0xFFFF, sum = 0
1238 11:35:41.013552 3, 0xFFFF, sum = 0
1239 11:35:41.013937 4, 0xFFFF, sum = 0
1240 11:35:41.016726 5, 0xFFFF, sum = 0
1241 11:35:41.017112 6, 0xFFFF, sum = 0
1242 11:35:41.019687 7, 0xFFFF, sum = 0
1243 11:35:41.020070 8, 0x0, sum = 1
1244 11:35:41.022953 9, 0x0, sum = 2
1245 11:35:41.023336 10, 0x0, sum = 3
1246 11:35:41.026354 11, 0x0, sum = 4
1247 11:35:41.026788 best_step = 9
1248 11:35:41.027080
1249 11:35:41.027347 ==
1250 11:35:41.030085 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 11:35:41.033735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 11:35:41.036498 ==
1253 11:35:41.036878 RX Vref Scan: 0
1254 11:35:41.037171
1255 11:35:41.039805 RX Vref 0 -> 0, step: 1
1256 11:35:41.040182
1257 11:35:41.043499 RX Delay -111 -> 252, step: 8
1258 11:35:41.046668 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1259 11:35:41.050716 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1260 11:35:41.053470 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1261 11:35:41.059989 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1262 11:35:41.063409 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1263 11:35:41.066407 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1264 11:35:41.069858 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1265 11:35:41.073587 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1266 11:35:41.079616 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1267 11:35:41.083417 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1268 11:35:41.086439 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1269 11:35:41.089867 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1270 11:35:41.093041 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1271 11:35:41.099970 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1272 11:35:41.104192 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1273 11:35:41.107058 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1274 11:35:41.107474 ==
1275 11:35:41.111263 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 11:35:41.113841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 11:35:41.114234 ==
1278 11:35:41.116137 DQS Delay:
1279 11:35:41.116554 DQS0 = 0, DQS1 = 0
1280 11:35:41.119916 DQM Delay:
1281 11:35:41.120366 DQM0 = 86, DQM1 = 73
1282 11:35:41.120664 DQ Delay:
1283 11:35:41.123405 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80
1284 11:35:41.127461 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1285 11:35:41.131308 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1286 11:35:41.135186 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1287 11:35:41.135700
1288 11:35:41.136136
1289 11:35:41.142915 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1290 11:35:41.146424 CH0 RK1: MR19=606, MR18=4C4C
1291 11:35:41.152865 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1292 11:35:41.153382 [RxdqsGatingPostProcess] freq 800
1293 11:35:41.161324 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1294 11:35:41.163894 Pre-setting of DQS Precalculation
1295 11:35:41.166323 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1296 11:35:41.166762 ==
1297 11:35:41.170022 Dram Type= 6, Freq= 0, CH_1, rank 0
1298 11:35:41.176091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 11:35:41.176495 ==
1300 11:35:41.179907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1301 11:35:41.186125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1302 11:35:41.196194 [CA 0] Center 37 (6~68) winsize 63
1303 11:35:41.199175 [CA 1] Center 37 (6~68) winsize 63
1304 11:35:41.202551 [CA 2] Center 34 (4~65) winsize 62
1305 11:35:41.206143 [CA 3] Center 34 (4~65) winsize 62
1306 11:35:41.208935 [CA 4] Center 33 (2~64) winsize 63
1307 11:35:41.212173 [CA 5] Center 33 (3~64) winsize 62
1308 11:35:41.212639
1309 11:35:41.216391 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1310 11:35:41.216882
1311 11:35:41.218852 [CATrainingPosCal] consider 1 rank data
1312 11:35:41.222180 u2DelayCellTimex100 = 270/100 ps
1313 11:35:41.225692 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1314 11:35:41.229642 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1315 11:35:41.236345 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 11:35:41.238850 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1317 11:35:41.243323 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1318 11:35:41.245220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1319 11:35:41.245474
1320 11:35:41.249096 CA PerBit enable=1, Macro0, CA PI delay=33
1321 11:35:41.249291
1322 11:35:41.253158 [CBTSetCACLKResult] CA Dly = 33
1323 11:35:41.253347 CS Dly: 4 (0~35)
1324 11:35:41.253476 ==
1325 11:35:41.255390 Dram Type= 6, Freq= 0, CH_1, rank 1
1326 11:35:41.261939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 11:35:41.262155 ==
1328 11:35:41.265453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1329 11:35:41.271726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1330 11:35:41.281914 [CA 0] Center 37 (6~68) winsize 63
1331 11:35:41.285455 [CA 1] Center 37 (6~68) winsize 63
1332 11:35:41.288518 [CA 2] Center 34 (4~65) winsize 62
1333 11:35:41.292332 [CA 3] Center 34 (4~65) winsize 62
1334 11:35:41.294740 [CA 4] Center 33 (3~64) winsize 62
1335 11:35:41.298155 [CA 5] Center 33 (2~64) winsize 63
1336 11:35:41.298573
1337 11:35:41.301790 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1338 11:35:41.302376
1339 11:35:41.305180 [CATrainingPosCal] consider 2 rank data
1340 11:35:41.308740 u2DelayCellTimex100 = 270/100 ps
1341 11:35:41.312369 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1342 11:35:41.314806 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1343 11:35:41.322534 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 11:35:41.324629 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1345 11:35:41.328539 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1346 11:35:41.331670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1347 11:35:41.332183
1348 11:35:41.334854 CA PerBit enable=1, Macro0, CA PI delay=33
1349 11:35:41.335442
1350 11:35:41.338340 [CBTSetCACLKResult] CA Dly = 33
1351 11:35:41.338940 CS Dly: 5 (0~37)
1352 11:35:41.339336
1353 11:35:41.342845 ----->DramcWriteLeveling(PI) begin...
1354 11:35:41.344751 ==
1355 11:35:41.345356 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 11:35:41.351449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 11:35:41.351916 ==
1358 11:35:41.354495 Write leveling (Byte 0): 25 => 25
1359 11:35:41.358346 Write leveling (Byte 1): 25 => 25
1360 11:35:41.361615 DramcWriteLeveling(PI) end<-----
1361 11:35:41.362089
1362 11:35:41.362416 ==
1363 11:35:41.364816 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 11:35:41.369055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 11:35:41.369514 ==
1366 11:35:41.372139 [Gating] SW mode calibration
1367 11:35:41.378127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1368 11:35:41.381183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1369 11:35:41.388388 0 6 0 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
1370 11:35:41.391314 0 6 4 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
1371 11:35:41.395554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 11:35:41.401708 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 11:35:41.404735 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 11:35:41.408060 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 11:35:41.415458 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 11:35:41.418470 0 6 28 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1377 11:35:41.422843 0 7 0 | B1->B0 | 2f2f 3d3d | 0 1 | (0 0) (0 0)
1378 11:35:41.428279 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1379 11:35:41.432035 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 11:35:41.435123 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 11:35:41.441398 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 11:35:41.444423 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 11:35:41.448548 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 11:35:41.451747 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1385 11:35:41.458565 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1386 11:35:41.461792 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 11:35:41.464966 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 11:35:41.473474 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 11:35:41.475291 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 11:35:41.478043 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 11:35:41.484800 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:35:41.488057 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:35:41.491817 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:35:41.497903 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:35:41.501063 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:35:41.505172 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:35:41.511455 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:35:41.514736 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:35:41.518367 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:35:41.525600 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1401 11:35:41.529032 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 11:35:41.532305 Total UI for P1: 0, mck2ui 16
1403 11:35:41.535332 best dqsien dly found for B0: ( 0, 9, 28)
1404 11:35:41.538771 Total UI for P1: 0, mck2ui 16
1405 11:35:41.541307 best dqsien dly found for B1: ( 0, 9, 28)
1406 11:35:41.544527 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1407 11:35:41.548575 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1408 11:35:41.548998
1409 11:35:41.551547 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1410 11:35:41.554704 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1411 11:35:41.558025 [Gating] SW calibration Done
1412 11:35:41.558449 ==
1413 11:35:41.561654 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 11:35:41.565295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 11:35:41.565682 ==
1416 11:35:41.568343 RX Vref Scan: 0
1417 11:35:41.568720
1418 11:35:41.571545 RX Vref 0 -> 0, step: 1
1419 11:35:41.571924
1420 11:35:41.572219 RX Delay -130 -> 252, step: 16
1421 11:35:41.578671 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1422 11:35:41.581325 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1423 11:35:41.584803 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1424 11:35:41.588197 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1425 11:35:41.591178 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1426 11:35:41.597826 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1427 11:35:41.601531 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1428 11:35:41.604630 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1429 11:35:41.607707 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1430 11:35:41.611802 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1431 11:35:41.617801 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1432 11:35:41.621523 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1433 11:35:41.624748 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1434 11:35:41.628066 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1435 11:35:41.634379 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1436 11:35:41.638714 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1437 11:35:41.639230 ==
1438 11:35:41.641330 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:35:41.644539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 11:35:41.644922 ==
1441 11:35:41.645215 DQS Delay:
1442 11:35:41.647690 DQS0 = 0, DQS1 = 0
1443 11:35:41.648067 DQM Delay:
1444 11:35:41.651523 DQM0 = 81, DQM1 = 71
1445 11:35:41.651926 DQ Delay:
1446 11:35:41.654548 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1447 11:35:41.657830 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1448 11:35:41.661772 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1449 11:35:41.664412 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1450 11:35:41.664917
1451 11:35:41.665390
1452 11:35:41.665807 ==
1453 11:35:41.668014 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 11:35:41.671635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1455 11:35:41.674907 ==
1456 11:35:41.675292
1457 11:35:41.675584
1458 11:35:41.675950 TX Vref Scan disable
1459 11:35:41.677801 == TX Byte 0 ==
1460 11:35:41.681554 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1461 11:35:41.684541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1462 11:35:41.688126 == TX Byte 1 ==
1463 11:35:41.691636 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 11:35:41.695173 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 11:35:41.698009 ==
1466 11:35:41.698458 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 11:35:41.705355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1468 11:35:41.705891 ==
1469 11:35:41.717329 TX Vref=22, minBit 3, minWin=27, winSum=446
1470 11:35:41.719981 TX Vref=24, minBit 3, minWin=27, winSum=448
1471 11:35:41.723546 TX Vref=26, minBit 3, minWin=27, winSum=454
1472 11:35:41.726757 TX Vref=28, minBit 0, minWin=28, winSum=460
1473 11:35:41.730561 TX Vref=30, minBit 0, minWin=28, winSum=457
1474 11:35:41.732804 TX Vref=32, minBit 9, minWin=27, winSum=457
1475 11:35:41.739664 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 28
1476 11:35:41.740053
1477 11:35:41.743361 Final TX Range 1 Vref 28
1478 11:35:41.743912
1479 11:35:41.744288 ==
1480 11:35:41.746311 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 11:35:41.750377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 11:35:41.750854 ==
1483 11:35:41.751163
1484 11:35:41.753190
1485 11:35:41.753630 TX Vref Scan disable
1486 11:35:41.756580 == TX Byte 0 ==
1487 11:35:41.760021 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1488 11:35:41.763283 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1489 11:35:41.767362 == TX Byte 1 ==
1490 11:35:41.769800 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 11:35:41.773160 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 11:35:41.773589
1493 11:35:41.776481 [DATLAT]
1494 11:35:41.776877 Freq=800, CH1 RK0
1495 11:35:41.777170
1496 11:35:41.779631 DATLAT Default: 0xa
1497 11:35:41.780011 0, 0xFFFF, sum = 0
1498 11:35:41.783455 1, 0xFFFF, sum = 0
1499 11:35:41.783842 2, 0xFFFF, sum = 0
1500 11:35:41.787515 3, 0xFFFF, sum = 0
1501 11:35:41.787951 4, 0xFFFF, sum = 0
1502 11:35:41.789691 5, 0xFFFF, sum = 0
1503 11:35:41.790080 6, 0xFFFF, sum = 0
1504 11:35:41.793267 7, 0xFFFF, sum = 0
1505 11:35:41.793668 8, 0x0, sum = 1
1506 11:35:41.796752 9, 0x0, sum = 2
1507 11:35:41.797141 10, 0x0, sum = 3
1508 11:35:41.800017 11, 0x0, sum = 4
1509 11:35:41.800472 best_step = 9
1510 11:35:41.800775
1511 11:35:41.801048 ==
1512 11:35:41.803503 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:35:41.806617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 11:35:41.810291 ==
1515 11:35:41.810763 RX Vref Scan: 1
1516 11:35:41.811186
1517 11:35:41.813708 Set Vref Range= 32 -> 127
1518 11:35:41.814091
1519 11:35:41.817356 RX Vref 32 -> 127, step: 1
1520 11:35:41.817812
1521 11:35:41.818113 RX Delay -111 -> 252, step: 8
1522 11:35:41.818392
1523 11:35:41.819614 Set Vref, RX VrefLevel [Byte0]: 32
1524 11:35:41.823193 [Byte1]: 32
1525 11:35:41.827544
1526 11:35:41.828029 Set Vref, RX VrefLevel [Byte0]: 33
1527 11:35:41.830189 [Byte1]: 33
1528 11:35:41.835100
1529 11:35:41.835559 Set Vref, RX VrefLevel [Byte0]: 34
1530 11:35:41.837945 [Byte1]: 34
1531 11:35:41.842611
1532 11:35:41.842992 Set Vref, RX VrefLevel [Byte0]: 35
1533 11:35:41.845739 [Byte1]: 35
1534 11:35:41.850131
1535 11:35:41.850559 Set Vref, RX VrefLevel [Byte0]: 36
1536 11:35:41.854181 [Byte1]: 36
1537 11:35:41.858306
1538 11:35:41.858690 Set Vref, RX VrefLevel [Byte0]: 37
1539 11:35:41.861157 [Byte1]: 37
1540 11:35:41.865905
1541 11:35:41.866362 Set Vref, RX VrefLevel [Byte0]: 38
1542 11:35:41.868659 [Byte1]: 38
1543 11:35:41.873282
1544 11:35:41.873804 Set Vref, RX VrefLevel [Byte0]: 39
1545 11:35:41.876668 [Byte1]: 39
1546 11:35:41.881124
1547 11:35:41.881664 Set Vref, RX VrefLevel [Byte0]: 40
1548 11:35:41.885113 [Byte1]: 40
1549 11:35:41.888942
1550 11:35:41.889450 Set Vref, RX VrefLevel [Byte0]: 41
1551 11:35:41.892033 [Byte1]: 41
1552 11:35:41.896084
1553 11:35:41.896508 Set Vref, RX VrefLevel [Byte0]: 42
1554 11:35:41.900694 [Byte1]: 42
1555 11:35:41.904014
1556 11:35:41.904439 Set Vref, RX VrefLevel [Byte0]: 43
1557 11:35:41.907001 [Byte1]: 43
1558 11:35:41.911495
1559 11:35:41.911919 Set Vref, RX VrefLevel [Byte0]: 44
1560 11:35:41.914991 [Byte1]: 44
1561 11:35:41.920079
1562 11:35:41.920535 Set Vref, RX VrefLevel [Byte0]: 45
1563 11:35:41.922208 [Byte1]: 45
1564 11:35:41.926448
1565 11:35:41.926828 Set Vref, RX VrefLevel [Byte0]: 46
1566 11:35:41.930143 [Byte1]: 46
1567 11:35:41.934467
1568 11:35:41.934897 Set Vref, RX VrefLevel [Byte0]: 47
1569 11:35:41.939134 [Byte1]: 47
1570 11:35:41.942146
1571 11:35:41.942528 Set Vref, RX VrefLevel [Byte0]: 48
1572 11:35:41.945470 [Byte1]: 48
1573 11:35:41.949690
1574 11:35:41.950072 Set Vref, RX VrefLevel [Byte0]: 49
1575 11:35:41.952871 [Byte1]: 49
1576 11:35:41.957270
1577 11:35:41.957786 Set Vref, RX VrefLevel [Byte0]: 50
1578 11:35:41.961124 [Byte1]: 50
1579 11:35:41.965393
1580 11:35:41.965774 Set Vref, RX VrefLevel [Byte0]: 51
1581 11:35:41.968423 [Byte1]: 51
1582 11:35:41.972377
1583 11:35:41.972798 Set Vref, RX VrefLevel [Byte0]: 52
1584 11:35:41.975990 [Byte1]: 52
1585 11:35:41.980410
1586 11:35:41.980878 Set Vref, RX VrefLevel [Byte0]: 53
1587 11:35:41.984009 [Byte1]: 53
1588 11:35:41.987593
1589 11:35:41.988081 Set Vref, RX VrefLevel [Byte0]: 54
1590 11:35:41.990831 [Byte1]: 54
1591 11:35:41.996142
1592 11:35:41.996548 Set Vref, RX VrefLevel [Byte0]: 55
1593 11:35:42.001752 [Byte1]: 55
1594 11:35:42.002139
1595 11:35:42.005392 Set Vref, RX VrefLevel [Byte0]: 56
1596 11:35:42.008558 [Byte1]: 56
1597 11:35:42.008958
1598 11:35:42.011769 Set Vref, RX VrefLevel [Byte0]: 57
1599 11:35:42.015363 [Byte1]: 57
1600 11:35:42.018167
1601 11:35:42.018554 Set Vref, RX VrefLevel [Byte0]: 58
1602 11:35:42.021662 [Byte1]: 58
1603 11:35:42.026164
1604 11:35:42.026621 Set Vref, RX VrefLevel [Byte0]: 59
1605 11:35:42.029183 [Byte1]: 59
1606 11:35:42.033849
1607 11:35:42.034232 Set Vref, RX VrefLevel [Byte0]: 60
1608 11:35:42.036831 [Byte1]: 60
1609 11:35:42.041595
1610 11:35:42.041981 Set Vref, RX VrefLevel [Byte0]: 61
1611 11:35:42.045781 [Byte1]: 61
1612 11:35:42.049743
1613 11:35:42.050206 Set Vref, RX VrefLevel [Byte0]: 62
1614 11:35:42.052571 [Byte1]: 62
1615 11:35:42.056698
1616 11:35:42.057215 Set Vref, RX VrefLevel [Byte0]: 63
1617 11:35:42.060307 [Byte1]: 63
1618 11:35:42.065365
1619 11:35:42.065870 Set Vref, RX VrefLevel [Byte0]: 64
1620 11:35:42.067736 [Byte1]: 64
1621 11:35:42.071814
1622 11:35:42.072236 Set Vref, RX VrefLevel [Byte0]: 65
1623 11:35:42.075358 [Byte1]: 65
1624 11:35:42.080697
1625 11:35:42.081167 Set Vref, RX VrefLevel [Byte0]: 66
1626 11:35:42.083237 [Byte1]: 66
1627 11:35:42.087595
1628 11:35:42.088061 Set Vref, RX VrefLevel [Byte0]: 67
1629 11:35:42.090511 [Byte1]: 67
1630 11:35:42.096036
1631 11:35:42.096579 Set Vref, RX VrefLevel [Byte0]: 68
1632 11:35:42.098844 [Byte1]: 68
1633 11:35:42.102760
1634 11:35:42.103269 Set Vref, RX VrefLevel [Byte0]: 69
1635 11:35:42.106534 [Byte1]: 69
1636 11:35:42.110248
1637 11:35:42.110746 Set Vref, RX VrefLevel [Byte0]: 70
1638 11:35:42.113656 [Byte1]: 70
1639 11:35:42.117772
1640 11:35:42.118197 Set Vref, RX VrefLevel [Byte0]: 71
1641 11:35:42.121220 [Byte1]: 71
1642 11:35:42.125463
1643 11:35:42.125921 Set Vref, RX VrefLevel [Byte0]: 72
1644 11:35:42.128848 [Byte1]: 72
1645 11:35:42.133398
1646 11:35:42.133859 Set Vref, RX VrefLevel [Byte0]: 73
1647 11:35:42.137219 [Byte1]: 73
1648 11:35:42.140823
1649 11:35:42.141297 Set Vref, RX VrefLevel [Byte0]: 74
1650 11:35:42.144308 [Byte1]: 74
1651 11:35:42.149087
1652 11:35:42.149631 Set Vref, RX VrefLevel [Byte0]: 75
1653 11:35:42.151895 [Byte1]: 75
1654 11:35:42.155729
1655 11:35:42.156155 Final RX Vref Byte 0 = 59 to rank0
1656 11:35:42.160327 Final RX Vref Byte 1 = 54 to rank0
1657 11:35:42.162771 Final RX Vref Byte 0 = 59 to rank1
1658 11:35:42.166105 Final RX Vref Byte 1 = 54 to rank1==
1659 11:35:42.169486 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 11:35:42.176682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1661 11:35:42.177173 ==
1662 11:35:42.177563 DQS Delay:
1663 11:35:42.177869 DQS0 = 0, DQS1 = 0
1664 11:35:42.179597 DQM Delay:
1665 11:35:42.180039 DQM0 = 81, DQM1 = 75
1666 11:35:42.182645 DQ Delay:
1667 11:35:42.186700 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1668 11:35:42.187131 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1669 11:35:42.190144 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1670 11:35:42.192792 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1671 11:35:42.196679
1672 11:35:42.197104
1673 11:35:42.202515 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1674 11:35:42.206447 CH1 RK0: MR19=606, MR18=5252
1675 11:35:42.212943 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1676 11:35:42.213508
1677 11:35:42.216662 ----->DramcWriteLeveling(PI) begin...
1678 11:35:42.217051 ==
1679 11:35:42.219378 Dram Type= 6, Freq= 0, CH_1, rank 1
1680 11:35:42.223565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1681 11:35:42.224034 ==
1682 11:35:42.226657 Write leveling (Byte 0): 26 => 26
1683 11:35:42.229443 Write leveling (Byte 1): 26 => 26
1684 11:35:42.232954 DramcWriteLeveling(PI) end<-----
1685 11:35:42.233388
1686 11:35:42.233695 ==
1687 11:35:42.237017 Dram Type= 6, Freq= 0, CH_1, rank 1
1688 11:35:42.239642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1689 11:35:42.240032 ==
1690 11:35:42.242458 [Gating] SW mode calibration
1691 11:35:42.249132 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1692 11:35:42.256134 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1693 11:35:42.259525 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
1694 11:35:42.263213 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 11:35:42.269813 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 11:35:42.273196 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 11:35:42.276448 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 11:35:42.282697 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 11:35:42.285784 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 11:35:42.290764 0 6 28 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1701 11:35:42.296127 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1702 11:35:42.299255 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 11:35:42.302389 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 11:35:42.310220 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 11:35:42.312336 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 11:35:42.315751 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 11:35:42.318972 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 11:35:42.326115 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1709 11:35:42.328900 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 11:35:42.332474 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 11:35:42.339105 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 11:35:42.342385 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 11:35:42.346077 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 11:35:42.352419 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 11:35:42.355729 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:35:42.359440 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:35:42.366146 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:35:42.369304 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:35:42.372492 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:35:42.379182 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:35:42.382669 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:35:42.386376 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 11:35:42.394236 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 11:35:42.395471 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1725 11:35:42.399000 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1726 11:35:42.402539 Total UI for P1: 0, mck2ui 16
1727 11:35:42.405708 best dqsien dly found for B0: ( 0, 9, 28)
1728 11:35:42.412714 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 11:35:42.413115 Total UI for P1: 0, mck2ui 16
1730 11:35:42.418724 best dqsien dly found for B1: ( 0, 9, 30)
1731 11:35:42.422442 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1732 11:35:42.425565 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1733 11:35:42.426028
1734 11:35:42.429434 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1735 11:35:42.432321 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1736 11:35:42.435570 [Gating] SW calibration Done
1737 11:35:42.436032 ==
1738 11:35:42.438722 Dram Type= 6, Freq= 0, CH_1, rank 1
1739 11:35:42.442295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 11:35:42.442700 ==
1741 11:35:42.445796 RX Vref Scan: 0
1742 11:35:42.446177
1743 11:35:42.446473 RX Vref 0 -> 0, step: 1
1744 11:35:42.446751
1745 11:35:42.449419 RX Delay -130 -> 252, step: 16
1746 11:35:42.452405 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1747 11:35:42.459257 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1748 11:35:42.462005 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1749 11:35:42.465557 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1750 11:35:42.469566 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1751 11:35:42.472593 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1752 11:35:42.479032 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1753 11:35:42.483227 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1754 11:35:42.485922 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1755 11:35:42.489537 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1756 11:35:42.492411 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1757 11:35:42.499463 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1758 11:35:42.502886 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1759 11:35:42.505767 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1760 11:35:42.509252 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1761 11:35:42.512519 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1762 11:35:42.515245 ==
1763 11:35:42.518902 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 11:35:42.523216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 11:35:42.523727 ==
1766 11:35:42.524060 DQS Delay:
1767 11:35:42.526264 DQS0 = 0, DQS1 = 0
1768 11:35:42.526692 DQM Delay:
1769 11:35:42.529472 DQM0 = 87, DQM1 = 74
1770 11:35:42.529992 DQ Delay:
1771 11:35:42.532648 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1772 11:35:42.535739 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1773 11:35:42.538814 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1774 11:35:42.542071 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1775 11:35:42.542495
1776 11:35:42.542868
1777 11:35:42.543170 ==
1778 11:35:42.545360 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 11:35:42.549749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1780 11:35:42.550179 ==
1781 11:35:42.550506
1782 11:35:42.550851
1783 11:35:42.551935 TX Vref Scan disable
1784 11:35:42.555466 == TX Byte 0 ==
1785 11:35:42.558630 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1786 11:35:42.562510 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1787 11:35:42.565592 == TX Byte 1 ==
1788 11:35:42.568690 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1789 11:35:42.572170 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1790 11:35:42.572670 ==
1791 11:35:42.575974 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 11:35:42.579133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 11:35:42.582016 ==
1794 11:35:42.593600 TX Vref=22, minBit 0, minWin=27, winSum=447
1795 11:35:42.596590 TX Vref=24, minBit 0, minWin=27, winSum=451
1796 11:35:42.599995 TX Vref=26, minBit 8, minWin=27, winSum=457
1797 11:35:42.603222 TX Vref=28, minBit 0, minWin=28, winSum=460
1798 11:35:42.607059 TX Vref=30, minBit 5, minWin=28, winSum=456
1799 11:35:42.610032 TX Vref=32, minBit 0, minWin=28, winSum=455
1800 11:35:42.617468 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 28
1801 11:35:42.618005
1802 11:35:42.620071 Final TX Range 1 Vref 28
1803 11:35:42.620501
1804 11:35:42.620923 ==
1805 11:35:42.623262 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 11:35:42.626569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 11:35:42.627053 ==
1808 11:35:42.627483
1809 11:35:42.629479
1810 11:35:42.629910 TX Vref Scan disable
1811 11:35:42.633712 == TX Byte 0 ==
1812 11:35:42.636233 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1813 11:35:42.639777 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1814 11:35:42.643241 == TX Byte 1 ==
1815 11:35:42.646256 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1816 11:35:42.649528 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1817 11:35:42.653303
1818 11:35:42.653732 [DATLAT]
1819 11:35:42.654192 Freq=800, CH1 RK1
1820 11:35:42.654680
1821 11:35:42.656181 DATLAT Default: 0x9
1822 11:35:42.656618 0, 0xFFFF, sum = 0
1823 11:35:42.659621 1, 0xFFFF, sum = 0
1824 11:35:42.660046 2, 0xFFFF, sum = 0
1825 11:35:42.662790 3, 0xFFFF, sum = 0
1826 11:35:42.663218 4, 0xFFFF, sum = 0
1827 11:35:42.667116 5, 0xFFFF, sum = 0
1828 11:35:42.667540 6, 0xFFFF, sum = 0
1829 11:35:42.669546 7, 0xFFFF, sum = 0
1830 11:35:42.669975 8, 0x0, sum = 1
1831 11:35:42.673334 9, 0x0, sum = 2
1832 11:35:42.673761 10, 0x0, sum = 3
1833 11:35:42.676227 11, 0x0, sum = 4
1834 11:35:42.676613 best_step = 9
1835 11:35:42.676996
1836 11:35:42.677317 ==
1837 11:35:42.679590 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 11:35:42.686575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1839 11:35:42.686959 ==
1840 11:35:42.687254 RX Vref Scan: 0
1841 11:35:42.687525
1842 11:35:42.689377 RX Vref 0 -> 0, step: 1
1843 11:35:42.689759
1844 11:35:42.692612 RX Delay -111 -> 252, step: 8
1845 11:35:42.696146 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1846 11:35:42.699703 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1847 11:35:42.705823 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1848 11:35:42.710048 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1849 11:35:42.713161 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1850 11:35:42.716123 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1851 11:35:42.719351 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1852 11:35:42.726606 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1853 11:35:42.730255 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1854 11:35:42.732728 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1855 11:35:42.737013 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1856 11:35:42.739751 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1857 11:35:42.746112 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1858 11:35:42.749375 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1859 11:35:42.753512 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1860 11:35:42.755912 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1861 11:35:42.756292 ==
1862 11:35:42.759978 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:35:42.762880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 11:35:42.766418 ==
1865 11:35:42.766806 DQS Delay:
1866 11:35:42.767106 DQS0 = 0, DQS1 = 0
1867 11:35:42.769483 DQM Delay:
1868 11:35:42.769997 DQM0 = 84, DQM1 = 75
1869 11:35:42.772747 DQ Delay:
1870 11:35:42.776543 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1871 11:35:42.777024 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1872 11:35:42.779852 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1873 11:35:42.783309 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1874 11:35:42.786385
1875 11:35:42.786769
1876 11:35:42.792669 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1877 11:35:42.796395 CH1 RK1: MR19=606, MR18=3F3F
1878 11:35:42.803144 CH1_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1879 11:35:42.806278 [RxdqsGatingPostProcess] freq 800
1880 11:35:42.810382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1881 11:35:42.812843 Pre-setting of DQS Precalculation
1882 11:35:42.816486 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1883 11:35:42.825995 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1884 11:35:42.832880 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1885 11:35:42.833314
1886 11:35:42.833624
1887 11:35:42.835960 [Calibration Summary] 1600 Mbps
1888 11:35:42.836345 CH 0, Rank 0
1889 11:35:42.839460 SW Impedance : PASS
1890 11:35:42.839838 DUTY Scan : NO K
1891 11:35:42.842635 ZQ Calibration : PASS
1892 11:35:42.846481 Jitter Meter : NO K
1893 11:35:42.846858 CBT Training : PASS
1894 11:35:42.849537 Write leveling : PASS
1895 11:35:42.853011 RX DQS gating : PASS
1896 11:35:42.853547 RX DQ/DQS(RDDQC) : PASS
1897 11:35:42.856042 TX DQ/DQS : PASS
1898 11:35:42.859800 RX DATLAT : PASS
1899 11:35:42.860175 RX DQ/DQS(Engine): PASS
1900 11:35:42.862534 TX OE : NO K
1901 11:35:42.862910 All Pass.
1902 11:35:42.863262
1903 11:35:42.865996 CH 0, Rank 1
1904 11:35:42.866373 SW Impedance : PASS
1905 11:35:42.869459 DUTY Scan : NO K
1906 11:35:42.872443 ZQ Calibration : PASS
1907 11:35:42.872822 Jitter Meter : NO K
1908 11:35:42.875805 CBT Training : PASS
1909 11:35:42.876248 Write leveling : PASS
1910 11:35:42.879625 RX DQS gating : PASS
1911 11:35:42.882911 RX DQ/DQS(RDDQC) : PASS
1912 11:35:42.883287 TX DQ/DQS : PASS
1913 11:35:42.886166 RX DATLAT : PASS
1914 11:35:42.889142 RX DQ/DQS(Engine): PASS
1915 11:35:42.889610 TX OE : NO K
1916 11:35:42.892645 All Pass.
1917 11:35:42.893094
1918 11:35:42.893450 CH 1, Rank 0
1919 11:35:42.896185 SW Impedance : PASS
1920 11:35:42.896564 DUTY Scan : NO K
1921 11:35:42.899370 ZQ Calibration : PASS
1922 11:35:42.903534 Jitter Meter : NO K
1923 11:35:42.903914 CBT Training : PASS
1924 11:35:42.906640 Write leveling : PASS
1925 11:35:42.909833 RX DQS gating : PASS
1926 11:35:42.910215 RX DQ/DQS(RDDQC) : PASS
1927 11:35:42.912464 TX DQ/DQS : PASS
1928 11:35:42.915834 RX DATLAT : PASS
1929 11:35:42.916312 RX DQ/DQS(Engine): PASS
1930 11:35:42.919452 TX OE : NO K
1931 11:35:42.919882 All Pass.
1932 11:35:42.920182
1933 11:35:42.922846 CH 1, Rank 1
1934 11:35:42.923224 SW Impedance : PASS
1935 11:35:42.925773 DUTY Scan : NO K
1936 11:35:42.926158 ZQ Calibration : PASS
1937 11:35:42.929174 Jitter Meter : NO K
1938 11:35:42.933214 CBT Training : PASS
1939 11:35:42.933689 Write leveling : PASS
1940 11:35:42.936651 RX DQS gating : PASS
1941 11:35:42.939503 RX DQ/DQS(RDDQC) : PASS
1942 11:35:42.939885 TX DQ/DQS : PASS
1943 11:35:42.943051 RX DATLAT : PASS
1944 11:35:42.946618 RX DQ/DQS(Engine): PASS
1945 11:35:42.947049 TX OE : NO K
1946 11:35:42.949326 All Pass.
1947 11:35:42.949715
1948 11:35:42.950008 DramC Write-DBI off
1949 11:35:42.953195 PER_BANK_REFRESH: Hybrid Mode
1950 11:35:42.953665 TX_TRACKING: ON
1951 11:35:42.955941 [GetDramInforAfterCalByMRR] Vendor 6.
1952 11:35:42.963414 [GetDramInforAfterCalByMRR] Revision 606.
1953 11:35:42.965898 [GetDramInforAfterCalByMRR] Revision 2 0.
1954 11:35:42.966285 MR0 0x3939
1955 11:35:42.966587 MR8 0x1111
1956 11:35:42.969698 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1957 11:35:42.970078
1958 11:35:42.972846 MR0 0x3939
1959 11:35:42.973250 MR8 0x1111
1960 11:35:42.975884 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 11:35:42.976266
1962 11:35:42.985749 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1963 11:35:42.988892 [FAST_K] Save calibration result to emmc
1964 11:35:42.992699 [FAST_K] Save calibration result to emmc
1965 11:35:42.995670 dram_init: config_dvfs: 1
1966 11:35:42.998805 dramc_set_vcore_voltage set vcore to 662500
1967 11:35:43.003088 Read voltage for 1200, 2
1968 11:35:43.003407 Vio18 = 0
1969 11:35:43.003616 Vcore = 662500
1970 11:35:43.005644 Vdram = 0
1971 11:35:43.005908 Vddq = 0
1972 11:35:43.006160 Vmddr = 0
1973 11:35:43.012232 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1974 11:35:43.015418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1975 11:35:43.019575 MEM_TYPE=3, freq_sel=15
1976 11:35:43.025478 sv_algorithm_assistance_LP4_1600
1977 11:35:43.026101 ============ PULL DRAM RESETB DOWN ============
1978 11:35:43.029499 ========== PULL DRAM RESETB DOWN end =========
1979 11:35:43.037560 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1980 11:35:43.039414 ===================================
1981 11:35:43.039800 LPDDR4 DRAM CONFIGURATION
1982 11:35:43.043669 ===================================
1983 11:35:43.045932 EX_ROW_EN[0] = 0x0
1984 11:35:43.049489 EX_ROW_EN[1] = 0x0
1985 11:35:43.049783 LP4Y_EN = 0x0
1986 11:35:43.052989 WORK_FSP = 0x0
1987 11:35:43.053447 WL = 0x4
1988 11:35:43.056429 RL = 0x4
1989 11:35:43.056959 BL = 0x2
1990 11:35:43.059164 RPST = 0x0
1991 11:35:43.059679 RD_PRE = 0x0
1992 11:35:43.062381 WR_PRE = 0x1
1993 11:35:43.062886 WR_PST = 0x0
1994 11:35:43.065793 DBI_WR = 0x0
1995 11:35:43.066430 DBI_RD = 0x0
1996 11:35:43.069551 OTF = 0x1
1997 11:35:43.072909 ===================================
1998 11:35:43.076389 ===================================
1999 11:35:43.076865 ANA top config
2000 11:35:43.079399 ===================================
2001 11:35:43.082195 DLL_ASYNC_EN = 0
2002 11:35:43.085781 ALL_SLAVE_EN = 0
2003 11:35:43.086221 NEW_RANK_MODE = 1
2004 11:35:43.089118 DLL_IDLE_MODE = 1
2005 11:35:43.092426 LP45_APHY_COMB_EN = 1
2006 11:35:43.095974 TX_ODT_DIS = 1
2007 11:35:43.099111 NEW_8X_MODE = 1
2008 11:35:43.102841 ===================================
2009 11:35:43.105608 ===================================
2010 11:35:43.106063 data_rate = 2400
2011 11:35:43.109445 CKR = 1
2012 11:35:43.113197 DQ_P2S_RATIO = 8
2013 11:35:43.115523 ===================================
2014 11:35:43.119120 CA_P2S_RATIO = 8
2015 11:35:43.122554 DQ_CA_OPEN = 0
2016 11:35:43.126510 DQ_SEMI_OPEN = 0
2017 11:35:43.127078 CA_SEMI_OPEN = 0
2018 11:35:43.128895 CA_FULL_RATE = 0
2019 11:35:43.133004 DQ_CKDIV4_EN = 0
2020 11:35:43.135935 CA_CKDIV4_EN = 0
2021 11:35:43.139338 CA_PREDIV_EN = 0
2022 11:35:43.142417 PH8_DLY = 17
2023 11:35:43.142937 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2024 11:35:43.145715 DQ_AAMCK_DIV = 4
2025 11:35:43.149488 CA_AAMCK_DIV = 4
2026 11:35:43.152509 CA_ADMCK_DIV = 4
2027 11:35:43.155606 DQ_TRACK_CA_EN = 0
2028 11:35:43.159243 CA_PICK = 1200
2029 11:35:43.162533 CA_MCKIO = 1200
2030 11:35:43.163046 MCKIO_SEMI = 0
2031 11:35:43.165935 PLL_FREQ = 2366
2032 11:35:43.168927 DQ_UI_PI_RATIO = 32
2033 11:35:43.172642 CA_UI_PI_RATIO = 0
2034 11:35:43.175368 ===================================
2035 11:35:43.179751 ===================================
2036 11:35:43.182744 memory_type:LPDDR4
2037 11:35:43.183185 GP_NUM : 10
2038 11:35:43.186061 SRAM_EN : 1
2039 11:35:43.186485 MD32_EN : 0
2040 11:35:43.188863 ===================================
2041 11:35:43.193128 [ANA_INIT] >>>>>>>>>>>>>>
2042 11:35:43.196257 <<<<<< [CONFIGURE PHASE]: ANA_TX
2043 11:35:43.199106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2044 11:35:43.203210 ===================================
2045 11:35:43.205787 data_rate = 2400,PCW = 0X5b00
2046 11:35:43.209203 ===================================
2047 11:35:43.213001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2048 11:35:43.219017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2049 11:35:43.222106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2050 11:35:43.229116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2051 11:35:43.232395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2052 11:35:43.235481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2053 11:35:43.235914 [ANA_INIT] flow start
2054 11:35:43.239061 [ANA_INIT] PLL >>>>>>>>
2055 11:35:43.242385 [ANA_INIT] PLL <<<<<<<<
2056 11:35:43.242811 [ANA_INIT] MIDPI >>>>>>>>
2057 11:35:43.245758 [ANA_INIT] MIDPI <<<<<<<<
2058 11:35:43.248681 [ANA_INIT] DLL >>>>>>>>
2059 11:35:43.249099 [ANA_INIT] DLL <<<<<<<<
2060 11:35:43.252017 [ANA_INIT] flow end
2061 11:35:43.255399 ============ LP4 DIFF to SE enter ============
2062 11:35:43.258581 ============ LP4 DIFF to SE exit ============
2063 11:35:43.262013 [ANA_INIT] <<<<<<<<<<<<<
2064 11:35:43.266027 [Flow] Enable top DCM control >>>>>
2065 11:35:43.269929 [Flow] Enable top DCM control <<<<<
2066 11:35:43.273194 Enable DLL master slave shuffle
2067 11:35:43.279119 ==============================================================
2068 11:35:43.279632 Gating Mode config
2069 11:35:43.285986 ==============================================================
2070 11:35:43.286405 Config description:
2071 11:35:43.295503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2072 11:35:43.301831 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2073 11:35:43.309074 SELPH_MODE 0: By rank 1: By Phase
2074 11:35:43.312291 ==============================================================
2075 11:35:43.315614 GAT_TRACK_EN = 1
2076 11:35:43.318979 RX_GATING_MODE = 2
2077 11:35:43.322857 RX_GATING_TRACK_MODE = 2
2078 11:35:43.325526 SELPH_MODE = 1
2079 11:35:43.328976 PICG_EARLY_EN = 1
2080 11:35:43.332144 VALID_LAT_VALUE = 1
2081 11:35:43.339313 ==============================================================
2082 11:35:43.342270 Enter into Gating configuration >>>>
2083 11:35:43.345761 Exit from Gating configuration <<<<
2084 11:35:43.346285 Enter into DVFS_PRE_config >>>>>
2085 11:35:43.359694 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2086 11:35:43.362324 Exit from DVFS_PRE_config <<<<<
2087 11:35:43.365560 Enter into PICG configuration >>>>
2088 11:35:43.368619 Exit from PICG configuration <<<<
2089 11:35:43.369045 [RX_INPUT] configuration >>>>>
2090 11:35:43.372026 [RX_INPUT] configuration <<<<<
2091 11:35:43.378864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2092 11:35:43.381915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2093 11:35:43.389090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 11:35:43.395438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 11:35:43.402282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 11:35:43.408829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 11:35:43.411898 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2098 11:35:43.415421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2099 11:35:43.422716 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2100 11:35:43.425583 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2101 11:35:43.428842 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2102 11:35:43.432168 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2103 11:35:43.435717 ===================================
2104 11:35:43.439580 LPDDR4 DRAM CONFIGURATION
2105 11:35:43.441928 ===================================
2106 11:35:43.445166 EX_ROW_EN[0] = 0x0
2107 11:35:43.445614 EX_ROW_EN[1] = 0x0
2108 11:35:43.449196 LP4Y_EN = 0x0
2109 11:35:43.449742 WORK_FSP = 0x0
2110 11:35:43.451967 WL = 0x4
2111 11:35:43.452392 RL = 0x4
2112 11:35:43.455076 BL = 0x2
2113 11:35:43.455501 RPST = 0x0
2114 11:35:43.459198 RD_PRE = 0x0
2115 11:35:43.459625 WR_PRE = 0x1
2116 11:35:43.461911 WR_PST = 0x0
2117 11:35:43.462331 DBI_WR = 0x0
2118 11:35:43.465813 DBI_RD = 0x0
2119 11:35:43.466284 OTF = 0x1
2120 11:35:43.468728 ===================================
2121 11:35:43.475115 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2122 11:35:43.478451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2123 11:35:43.481779 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 11:35:43.485090 ===================================
2125 11:35:43.488369 LPDDR4 DRAM CONFIGURATION
2126 11:35:43.491629 ===================================
2127 11:35:43.495043 EX_ROW_EN[0] = 0x10
2128 11:35:43.495466 EX_ROW_EN[1] = 0x0
2129 11:35:43.499070 LP4Y_EN = 0x0
2130 11:35:43.499566 WORK_FSP = 0x0
2131 11:35:43.503147 WL = 0x4
2132 11:35:43.503701 RL = 0x4
2133 11:35:43.505038 BL = 0x2
2134 11:35:43.505519 RPST = 0x0
2135 11:35:43.508671 RD_PRE = 0x0
2136 11:35:43.509093 WR_PRE = 0x1
2137 11:35:43.511751 WR_PST = 0x0
2138 11:35:43.512172 DBI_WR = 0x0
2139 11:35:43.515252 DBI_RD = 0x0
2140 11:35:43.515746 OTF = 0x1
2141 11:35:43.518833 ===================================
2142 11:35:43.524977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2143 11:35:43.525514 ==
2144 11:35:43.528371 Dram Type= 6, Freq= 0, CH_0, rank 0
2145 11:35:43.535256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2146 11:35:43.535726 ==
2147 11:35:43.536057 [Duty_Offset_Calibration]
2148 11:35:43.537943 B0:0 B1:2 CA:1
2149 11:35:43.538367
2150 11:35:43.541791 [DutyScan_Calibration_Flow] k_type=0
2151 11:35:43.550355
2152 11:35:43.550826 ==CLK 0==
2153 11:35:43.554108 Final CLK duty delay cell = 0
2154 11:35:43.556729 [0] MAX Duty = 5093%(X100), DQS PI = 12
2155 11:35:43.560921 [0] MIN Duty = 4938%(X100), DQS PI = 54
2156 11:35:43.561498 [0] AVG Duty = 5015%(X100)
2157 11:35:43.563946
2158 11:35:43.566763 CH0 CLK Duty spec in!! Max-Min= 155%
2159 11:35:43.570074 [DutyScan_Calibration_Flow] ====Done====
2160 11:35:43.570571
2161 11:35:43.573417 [DutyScan_Calibration_Flow] k_type=1
2162 11:35:43.589532
2163 11:35:43.589996 ==DQS 0 ==
2164 11:35:43.593091 Final DQS duty delay cell = 0
2165 11:35:43.596418 [0] MAX Duty = 5125%(X100), DQS PI = 32
2166 11:35:43.599582 [0] MIN Duty = 5031%(X100), DQS PI = 6
2167 11:35:43.600004 [0] AVG Duty = 5078%(X100)
2168 11:35:43.603348
2169 11:35:43.603882 ==DQS 1 ==
2170 11:35:43.606185 Final DQS duty delay cell = 0
2171 11:35:43.609301 [0] MAX Duty = 5031%(X100), DQS PI = 50
2172 11:35:43.613061 [0] MIN Duty = 4906%(X100), DQS PI = 14
2173 11:35:43.613657 [0] AVG Duty = 4968%(X100)
2174 11:35:43.616144
2175 11:35:43.619381 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2176 11:35:43.619940
2177 11:35:43.623740 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2178 11:35:43.626191 [DutyScan_Calibration_Flow] ====Done====
2179 11:35:43.626617
2180 11:35:43.629412 [DutyScan_Calibration_Flow] k_type=3
2181 11:35:43.646660
2182 11:35:43.647130 ==DQM 0 ==
2183 11:35:43.650609 Final DQM duty delay cell = 0
2184 11:35:43.653884 [0] MAX Duty = 5187%(X100), DQS PI = 22
2185 11:35:43.657778 [0] MIN Duty = 4969%(X100), DQS PI = 40
2186 11:35:43.658203 [0] AVG Duty = 5078%(X100)
2187 11:35:43.660204
2188 11:35:43.660627 ==DQM 1 ==
2189 11:35:43.663645 Final DQM duty delay cell = 4
2190 11:35:43.667534 [4] MAX Duty = 5187%(X100), DQS PI = 54
2191 11:35:43.670551 [4] MIN Duty = 5000%(X100), DQS PI = 18
2192 11:35:43.671026 [4] AVG Duty = 5093%(X100)
2193 11:35:43.675215
2194 11:35:43.676832 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2195 11:35:43.677286
2196 11:35:43.680189 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2197 11:35:43.683288 [DutyScan_Calibration_Flow] ====Done====
2198 11:35:43.683769
2199 11:35:43.687023 [DutyScan_Calibration_Flow] k_type=2
2200 11:35:43.701572
2201 11:35:43.702106 ==DQ 0 ==
2202 11:35:43.705395 Final DQ duty delay cell = -4
2203 11:35:43.708045 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2204 11:35:43.711597 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2205 11:35:43.715144 [-4] AVG Duty = 4937%(X100)
2206 11:35:43.715579
2207 11:35:43.715910 ==DQ 1 ==
2208 11:35:43.718247 Final DQ duty delay cell = -4
2209 11:35:43.721877 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2210 11:35:43.724824 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2211 11:35:43.728016 [-4] AVG Duty = 4984%(X100)
2212 11:35:43.728436
2213 11:35:43.731561 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2214 11:35:43.732073
2215 11:35:43.734999 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2216 11:35:43.739030 [DutyScan_Calibration_Flow] ====Done====
2217 11:35:43.739452 ==
2218 11:35:43.741567 Dram Type= 6, Freq= 0, CH_1, rank 0
2219 11:35:43.744925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2220 11:35:43.745405 ==
2221 11:35:43.748796 [Duty_Offset_Calibration]
2222 11:35:43.749353 B0:0 B1:5 CA:-5
2223 11:35:43.749696
2224 11:35:43.751456 [DutyScan_Calibration_Flow] k_type=0
2225 11:35:43.762631
2226 11:35:43.763099 ==CLK 0==
2227 11:35:43.766088 Final CLK duty delay cell = 0
2228 11:35:43.769569 [0] MAX Duty = 5094%(X100), DQS PI = 24
2229 11:35:43.772481 [0] MIN Duty = 4875%(X100), DQS PI = 46
2230 11:35:43.772904 [0] AVG Duty = 4984%(X100)
2231 11:35:43.776287
2232 11:35:43.779119 CH1 CLK Duty spec in!! Max-Min= 219%
2233 11:35:43.782411 [DutyScan_Calibration_Flow] ====Done====
2234 11:35:43.782836
2235 11:35:43.785757 [DutyScan_Calibration_Flow] k_type=1
2236 11:35:43.801457
2237 11:35:43.801961 ==DQS 0 ==
2238 11:35:43.804101 Final DQS duty delay cell = 0
2239 11:35:43.807687 [0] MAX Duty = 5125%(X100), DQS PI = 16
2240 11:35:43.810419 [0] MIN Duty = 4875%(X100), DQS PI = 40
2241 11:35:43.814069 [0] AVG Duty = 5000%(X100)
2242 11:35:43.814536
2243 11:35:43.814882 ==DQS 1 ==
2244 11:35:43.817288 Final DQS duty delay cell = -4
2245 11:35:43.820826 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2246 11:35:43.823726 [-4] MIN Duty = 4876%(X100), DQS PI = 44
2247 11:35:43.826963 [-4] AVG Duty = 4938%(X100)
2248 11:35:43.827383
2249 11:35:43.830984 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2250 11:35:43.831409
2251 11:35:43.833906 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2252 11:35:43.837765 [DutyScan_Calibration_Flow] ====Done====
2253 11:35:43.838185
2254 11:35:43.840163 [DutyScan_Calibration_Flow] k_type=3
2255 11:35:43.855777
2256 11:35:43.856246 ==DQM 0 ==
2257 11:35:43.859342 Final DQM duty delay cell = -4
2258 11:35:43.863381 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2259 11:35:43.867146 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2260 11:35:43.869804 [-4] AVG Duty = 4984%(X100)
2261 11:35:43.870221
2262 11:35:43.870544 ==DQM 1 ==
2263 11:35:43.872815 Final DQM duty delay cell = -4
2264 11:35:43.875945 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2265 11:35:43.879422 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2266 11:35:43.883010 [-4] AVG Duty = 4968%(X100)
2267 11:35:43.883433
2268 11:35:43.886107 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2269 11:35:43.886531
2270 11:35:43.890185 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2271 11:35:43.892682 [DutyScan_Calibration_Flow] ====Done====
2272 11:35:43.893204
2273 11:35:43.895915 [DutyScan_Calibration_Flow] k_type=2
2274 11:35:43.913810
2275 11:35:43.914295 ==DQ 0 ==
2276 11:35:43.917140 Final DQ duty delay cell = 0
2277 11:35:43.919735 [0] MAX Duty = 5062%(X100), DQS PI = 0
2278 11:35:43.923072 [0] MIN Duty = 4938%(X100), DQS PI = 44
2279 11:35:43.923512 [0] AVG Duty = 5000%(X100)
2280 11:35:43.923945
2281 11:35:43.926446 ==DQ 1 ==
2282 11:35:43.930306 Final DQ duty delay cell = 0
2283 11:35:43.933211 [0] MAX Duty = 5031%(X100), DQS PI = 8
2284 11:35:43.936334 [0] MIN Duty = 4907%(X100), DQS PI = 0
2285 11:35:43.937073 [0] AVG Duty = 4969%(X100)
2286 11:35:43.937526
2287 11:35:43.939777 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2288 11:35:43.940306
2289 11:35:43.942985 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2290 11:35:43.949715 [DutyScan_Calibration_Flow] ====Done====
2291 11:35:43.953158 nWR fixed to 30
2292 11:35:43.953785 [ModeRegInit_LP4] CH0 RK0
2293 11:35:43.956565 [ModeRegInit_LP4] CH0 RK1
2294 11:35:43.960392 [ModeRegInit_LP4] CH1 RK0
2295 11:35:43.960958 [ModeRegInit_LP4] CH1 RK1
2296 11:35:43.962976 match AC timing 6
2297 11:35:43.966810 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2298 11:35:43.969751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2299 11:35:43.976502 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2300 11:35:43.980156 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2301 11:35:43.986173 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2302 11:35:43.986581 ==
2303 11:35:43.989574 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 11:35:43.992678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2305 11:35:43.993065 ==
2306 11:35:43.999699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2307 11:35:44.003237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2308 11:35:44.012605 [CA 0] Center 39 (9~70) winsize 62
2309 11:35:44.016589 [CA 1] Center 39 (8~70) winsize 63
2310 11:35:44.019069 [CA 2] Center 36 (5~67) winsize 63
2311 11:35:44.022339 [CA 3] Center 35 (4~66) winsize 63
2312 11:35:44.026504 [CA 4] Center 34 (3~65) winsize 63
2313 11:35:44.029042 [CA 5] Center 33 (3~64) winsize 62
2314 11:35:44.029265
2315 11:35:44.032024 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2316 11:35:44.032223
2317 11:35:44.035842 [CATrainingPosCal] consider 1 rank data
2318 11:35:44.039346 u2DelayCellTimex100 = 270/100 ps
2319 11:35:44.042620 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2320 11:35:44.045906 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2321 11:35:44.052713 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2322 11:35:44.056351 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2323 11:35:44.059996 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2324 11:35:44.062495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2325 11:35:44.062869
2326 11:35:44.066514 CA PerBit enable=1, Macro0, CA PI delay=33
2327 11:35:44.066905
2328 11:35:44.069168 [CBTSetCACLKResult] CA Dly = 33
2329 11:35:44.069580 CS Dly: 7 (0~38)
2330 11:35:44.069870 ==
2331 11:35:44.072617 Dram Type= 6, Freq= 0, CH_0, rank 1
2332 11:35:44.079012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2333 11:35:44.079396 ==
2334 11:35:44.082841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2335 11:35:44.089997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2336 11:35:44.097910 [CA 0] Center 39 (8~70) winsize 63
2337 11:35:44.102073 [CA 1] Center 39 (8~70) winsize 63
2338 11:35:44.106275 [CA 2] Center 35 (5~66) winsize 62
2339 11:35:44.108119 [CA 3] Center 35 (4~66) winsize 63
2340 11:35:44.112117 [CA 4] Center 33 (3~64) winsize 62
2341 11:35:44.114876 [CA 5] Center 34 (3~65) winsize 63
2342 11:35:44.115254
2343 11:35:44.118339 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2344 11:35:44.118719
2345 11:35:44.121917 [CATrainingPosCal] consider 2 rank data
2346 11:35:44.124499 u2DelayCellTimex100 = 270/100 ps
2347 11:35:44.128018 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2348 11:35:44.131197 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2349 11:35:44.138763 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2350 11:35:44.141612 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2351 11:35:44.145049 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2352 11:35:44.147961 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2353 11:35:44.148339
2354 11:35:44.151275 CA PerBit enable=1, Macro0, CA PI delay=33
2355 11:35:44.151655
2356 11:35:44.155495 [CBTSetCACLKResult] CA Dly = 33
2357 11:35:44.155875 CS Dly: 7 (0~39)
2358 11:35:44.156166
2359 11:35:44.158227 ----->DramcWriteLeveling(PI) begin...
2360 11:35:44.158611 ==
2361 11:35:44.161652 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 11:35:44.168155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2363 11:35:44.168548 ==
2364 11:35:44.171399 Write leveling (Byte 0): 27 => 27
2365 11:35:44.174793 Write leveling (Byte 1): 27 => 27
2366 11:35:44.175067 DramcWriteLeveling(PI) end<-----
2367 11:35:44.178225
2368 11:35:44.178493 ==
2369 11:35:44.182242 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 11:35:44.185120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 11:35:44.185466 ==
2372 11:35:44.188383 [Gating] SW mode calibration
2373 11:35:44.194573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2374 11:35:44.197878 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2375 11:35:44.205804 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 11:35:44.208818 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 11:35:44.212667 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 11:35:44.217669 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 11:35:44.221139 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2380 11:35:44.224655 0 11 20 | B1->B0 | 2d2d 2828 | 0 0 | (0 1) (0 0)
2381 11:35:44.231284 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 11:35:44.234871 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 11:35:44.238314 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 11:35:44.244553 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 11:35:44.248302 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 11:35:44.251156 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 11:35:44.257774 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2388 11:35:44.261209 0 12 20 | B1->B0 | 3838 4040 | 0 1 | (0 0) (0 0)
2389 11:35:44.264933 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 11:35:44.271419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 11:35:44.274883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 11:35:44.277809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 11:35:44.284313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 11:35:44.287657 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 11:35:44.290834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 11:35:44.294422 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2397 11:35:44.301557 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 11:35:44.305040 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 11:35:44.308394 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 11:35:44.314918 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 11:35:44.317985 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 11:35:44.321357 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 11:35:44.328140 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:35:44.332555 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:35:44.334675 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:35:44.342578 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:35:44.344868 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:35:44.348131 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:35:44.354809 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 11:35:44.357951 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 11:35:44.361085 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2412 11:35:44.368137 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2413 11:35:44.371953 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 11:35:44.374922 Total UI for P1: 0, mck2ui 16
2415 11:35:44.379069 best dqsien dly found for B0: ( 0, 15, 18)
2416 11:35:44.381140 Total UI for P1: 0, mck2ui 16
2417 11:35:44.384662 best dqsien dly found for B1: ( 0, 15, 18)
2418 11:35:44.388660 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2419 11:35:44.391674 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2420 11:35:44.392098
2421 11:35:44.394726 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2422 11:35:44.397908 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2423 11:35:44.401511 [Gating] SW calibration Done
2424 11:35:44.402014 ==
2425 11:35:44.405922 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 11:35:44.408343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 11:35:44.408766 ==
2428 11:35:44.411702 RX Vref Scan: 0
2429 11:35:44.412327
2430 11:35:44.415393 RX Vref 0 -> 0, step: 1
2431 11:35:44.416010
2432 11:35:44.416360 RX Delay -40 -> 252, step: 8
2433 11:35:44.421533 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2434 11:35:44.425829 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2435 11:35:44.429514 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2436 11:35:44.431770 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2437 11:35:44.435585 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2438 11:35:44.441342 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2439 11:35:44.444992 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2440 11:35:44.447989 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2441 11:35:44.451345 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2442 11:35:44.455193 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2443 11:35:44.459841 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2444 11:35:44.465268 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2445 11:35:44.469024 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2446 11:35:44.471784 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2447 11:35:44.475023 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2448 11:35:44.481786 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2449 11:35:44.482252 ==
2450 11:35:44.484941 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 11:35:44.488513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 11:35:44.488939 ==
2453 11:35:44.489303 DQS Delay:
2454 11:35:44.491331 DQS0 = 0, DQS1 = 0
2455 11:35:44.491749 DQM Delay:
2456 11:35:44.494646 DQM0 = 115, DQM1 = 106
2457 11:35:44.495065 DQ Delay:
2458 11:35:44.498683 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2459 11:35:44.502338 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2460 11:35:44.504778 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2461 11:35:44.507977 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2462 11:35:44.508400
2463 11:35:44.508723
2464 11:35:44.509021 ==
2465 11:35:44.512485 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 11:35:44.518341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 11:35:44.518912 ==
2468 11:35:44.519252
2469 11:35:44.519549
2470 11:35:44.519831 TX Vref Scan disable
2471 11:35:44.521939 == TX Byte 0 ==
2472 11:35:44.525363 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2473 11:35:44.532419 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2474 11:35:44.532889 == TX Byte 1 ==
2475 11:35:44.534822 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2476 11:35:44.542161 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2477 11:35:44.542707 ==
2478 11:35:44.544966 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 11:35:44.548050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 11:35:44.548576 ==
2481 11:35:44.559762 TX Vref=22, minBit 10, minWin=25, winSum=422
2482 11:35:44.562950 TX Vref=24, minBit 8, minWin=25, winSum=422
2483 11:35:44.565846 TX Vref=26, minBit 8, minWin=26, winSum=434
2484 11:35:44.569343 TX Vref=28, minBit 8, minWin=26, winSum=433
2485 11:35:44.572357 TX Vref=30, minBit 9, minWin=25, winSum=429
2486 11:35:44.580104 TX Vref=32, minBit 5, minWin=26, winSum=436
2487 11:35:44.582554 [TxChooseVref] Worse bit 5, Min win 26, Win sum 436, Final Vref 32
2488 11:35:44.583110
2489 11:35:44.586199 Final TX Range 1 Vref 32
2490 11:35:44.586752
2491 11:35:44.587240 ==
2492 11:35:44.590695 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 11:35:44.592139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 11:35:44.592305 ==
2495 11:35:44.595593
2496 11:35:44.595755
2497 11:35:44.595882 TX Vref Scan disable
2498 11:35:44.599078 == TX Byte 0 ==
2499 11:35:44.602726 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2500 11:35:44.605706 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2501 11:35:44.609330 == TX Byte 1 ==
2502 11:35:44.612675 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2503 11:35:44.616074 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2504 11:35:44.618968
2505 11:35:44.619272 [DATLAT]
2506 11:35:44.619499 Freq=1200, CH0 RK0
2507 11:35:44.619756
2508 11:35:44.622681 DATLAT Default: 0xd
2509 11:35:44.623083 0, 0xFFFF, sum = 0
2510 11:35:44.625738 1, 0xFFFF, sum = 0
2511 11:35:44.626123 2, 0xFFFF, sum = 0
2512 11:35:44.629271 3, 0xFFFF, sum = 0
2513 11:35:44.629711 4, 0xFFFF, sum = 0
2514 11:35:44.633345 5, 0xFFFF, sum = 0
2515 11:35:44.635641 6, 0xFFFF, sum = 0
2516 11:35:44.636025 7, 0xFFFF, sum = 0
2517 11:35:44.639394 8, 0xFFFF, sum = 0
2518 11:35:44.639864 9, 0xFFFF, sum = 0
2519 11:35:44.643188 10, 0xFFFF, sum = 0
2520 11:35:44.643695 11, 0x0, sum = 1
2521 11:35:44.644001 12, 0x0, sum = 2
2522 11:35:44.646195 13, 0x0, sum = 3
2523 11:35:44.646627 14, 0x0, sum = 4
2524 11:35:44.649103 best_step = 12
2525 11:35:44.649508
2526 11:35:44.649817 ==
2527 11:35:44.653362 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 11:35:44.656922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 11:35:44.657401 ==
2530 11:35:44.659444 RX Vref Scan: 1
2531 11:35:44.659820
2532 11:35:44.660114 Set Vref Range= 32 -> 127
2533 11:35:44.662823
2534 11:35:44.663332 RX Vref 32 -> 127, step: 1
2535 11:35:44.663658
2536 11:35:44.665694 RX Delay -21 -> 252, step: 4
2537 11:35:44.666072
2538 11:35:44.669666 Set Vref, RX VrefLevel [Byte0]: 32
2539 11:35:44.673067 [Byte1]: 32
2540 11:35:44.675719
2541 11:35:44.676097 Set Vref, RX VrefLevel [Byte0]: 33
2542 11:35:44.679207 [Byte1]: 33
2543 11:35:44.683943
2544 11:35:44.684324 Set Vref, RX VrefLevel [Byte0]: 34
2545 11:35:44.686977 [Byte1]: 34
2546 11:35:44.691780
2547 11:35:44.692161 Set Vref, RX VrefLevel [Byte0]: 35
2548 11:35:44.694876 [Byte1]: 35
2549 11:35:44.700139
2550 11:35:44.700645 Set Vref, RX VrefLevel [Byte0]: 36
2551 11:35:44.703980 [Byte1]: 36
2552 11:35:44.708248
2553 11:35:44.708681 Set Vref, RX VrefLevel [Byte0]: 37
2554 11:35:44.711302 [Byte1]: 37
2555 11:35:44.715775
2556 11:35:44.716260 Set Vref, RX VrefLevel [Byte0]: 38
2557 11:35:44.718606 [Byte1]: 38
2558 11:35:44.723766
2559 11:35:44.724256 Set Vref, RX VrefLevel [Byte0]: 39
2560 11:35:44.727634 [Byte1]: 39
2561 11:35:44.731081
2562 11:35:44.731501 Set Vref, RX VrefLevel [Byte0]: 40
2563 11:35:44.734774 [Byte1]: 40
2564 11:35:44.739015
2565 11:35:44.739482 Set Vref, RX VrefLevel [Byte0]: 41
2566 11:35:44.743092 [Byte1]: 41
2567 11:35:44.747080
2568 11:35:44.747520 Set Vref, RX VrefLevel [Byte0]: 42
2569 11:35:44.750423 [Byte1]: 42
2570 11:35:44.755405
2571 11:35:44.755828 Set Vref, RX VrefLevel [Byte0]: 43
2572 11:35:44.758217 [Byte1]: 43
2573 11:35:44.763011
2574 11:35:44.763502 Set Vref, RX VrefLevel [Byte0]: 44
2575 11:35:44.766280 [Byte1]: 44
2576 11:35:44.770987
2577 11:35:44.771469 Set Vref, RX VrefLevel [Byte0]: 45
2578 11:35:44.773993 [Byte1]: 45
2579 11:35:44.778742
2580 11:35:44.779159 Set Vref, RX VrefLevel [Byte0]: 46
2581 11:35:44.782496 [Byte1]: 46
2582 11:35:44.786725
2583 11:35:44.787164 Set Vref, RX VrefLevel [Byte0]: 47
2584 11:35:44.789736 [Byte1]: 47
2585 11:35:44.794731
2586 11:35:44.795148 Set Vref, RX VrefLevel [Byte0]: 48
2587 11:35:44.798171 [Byte1]: 48
2588 11:35:44.802986
2589 11:35:44.803446 Set Vref, RX VrefLevel [Byte0]: 49
2590 11:35:44.805602 [Byte1]: 49
2591 11:35:44.810670
2592 11:35:44.811090 Set Vref, RX VrefLevel [Byte0]: 50
2593 11:35:44.814251 [Byte1]: 50
2594 11:35:44.818602
2595 11:35:44.819065 Set Vref, RX VrefLevel [Byte0]: 51
2596 11:35:44.822026 [Byte1]: 51
2597 11:35:44.826951
2598 11:35:44.827414 Set Vref, RX VrefLevel [Byte0]: 52
2599 11:35:44.829712 [Byte1]: 52
2600 11:35:44.834788
2601 11:35:44.835253 Set Vref, RX VrefLevel [Byte0]: 53
2602 11:35:44.838717 [Byte1]: 53
2603 11:35:44.843163
2604 11:35:44.843659 Set Vref, RX VrefLevel [Byte0]: 54
2605 11:35:44.846113 [Byte1]: 54
2606 11:35:44.850125
2607 11:35:44.850548 Set Vref, RX VrefLevel [Byte0]: 55
2608 11:35:44.854006 [Byte1]: 55
2609 11:35:44.858044
2610 11:35:44.858552 Set Vref, RX VrefLevel [Byte0]: 56
2611 11:35:44.861489 [Byte1]: 56
2612 11:35:44.865872
2613 11:35:44.866352 Set Vref, RX VrefLevel [Byte0]: 57
2614 11:35:44.869903 [Byte1]: 57
2615 11:35:44.874316
2616 11:35:44.874796 Set Vref, RX VrefLevel [Byte0]: 58
2617 11:35:44.877907 [Byte1]: 58
2618 11:35:44.881921
2619 11:35:44.882404 Set Vref, RX VrefLevel [Byte0]: 59
2620 11:35:44.885405 [Byte1]: 59
2621 11:35:44.889509
2622 11:35:44.889941 Set Vref, RX VrefLevel [Byte0]: 60
2623 11:35:44.892931 [Byte1]: 60
2624 11:35:44.897781
2625 11:35:44.898265 Set Vref, RX VrefLevel [Byte0]: 61
2626 11:35:44.901167 [Byte1]: 61
2627 11:35:44.905962
2628 11:35:44.906456 Set Vref, RX VrefLevel [Byte0]: 62
2629 11:35:44.909022 [Byte1]: 62
2630 11:35:44.913675
2631 11:35:44.914186 Set Vref, RX VrefLevel [Byte0]: 63
2632 11:35:44.916954 [Byte1]: 63
2633 11:35:44.921477
2634 11:35:44.921954 Set Vref, RX VrefLevel [Byte0]: 64
2635 11:35:44.925024 [Byte1]: 64
2636 11:35:44.929285
2637 11:35:44.929762 Set Vref, RX VrefLevel [Byte0]: 65
2638 11:35:44.933040 [Byte1]: 65
2639 11:35:44.937460
2640 11:35:44.937986 Set Vref, RX VrefLevel [Byte0]: 66
2641 11:35:44.940278 [Byte1]: 66
2642 11:35:44.945076
2643 11:35:44.945558 Final RX Vref Byte 0 = 47 to rank0
2644 11:35:44.948423 Final RX Vref Byte 1 = 52 to rank0
2645 11:35:44.951646 Final RX Vref Byte 0 = 47 to rank1
2646 11:35:44.955117 Final RX Vref Byte 1 = 52 to rank1==
2647 11:35:44.958232 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 11:35:44.965779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2649 11:35:44.966216 ==
2650 11:35:44.966642 DQS Delay:
2651 11:35:44.967042 DQS0 = 0, DQS1 = 0
2652 11:35:44.969056 DQM Delay:
2653 11:35:44.969565 DQM0 = 113, DQM1 = 105
2654 11:35:44.971700 DQ Delay:
2655 11:35:44.975872 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2656 11:35:44.979334 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2657 11:35:44.981770 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2658 11:35:44.985560 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2659 11:35:44.985991
2660 11:35:44.986419
2661 11:35:44.991970 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2662 11:35:44.995850 CH0 RK0: MR19=404, MR18=909
2663 11:35:45.001956 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2664 11:35:45.002433
2665 11:35:45.006701 ----->DramcWriteLeveling(PI) begin...
2666 11:35:45.007182 ==
2667 11:35:45.008586 Dram Type= 6, Freq= 0, CH_0, rank 1
2668 11:35:45.011839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2669 11:35:45.012321 ==
2670 11:35:45.015482 Write leveling (Byte 0): 27 => 27
2671 11:35:45.019135 Write leveling (Byte 1): 24 => 24
2672 11:35:45.022378 DramcWriteLeveling(PI) end<-----
2673 11:35:45.022835
2674 11:35:45.023264 ==
2675 11:35:45.025273 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 11:35:45.028695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 11:35:45.031884 ==
2678 11:35:45.032319 [Gating] SW mode calibration
2679 11:35:45.041844 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2680 11:35:45.044900 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2681 11:35:45.048563 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 11:35:45.054996 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 11:35:45.058451 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 11:35:45.061578 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 11:35:45.068310 0 11 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2686 11:35:45.071912 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
2687 11:35:45.075089 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 11:35:45.082004 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 11:35:45.085262 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 11:35:45.089288 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 11:35:45.095928 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 11:35:45.098431 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 11:35:45.102551 0 12 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2694 11:35:45.105183 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (1 1) (0 0)
2695 11:35:45.111988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 11:35:45.115173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 11:35:45.118671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 11:35:45.125467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 11:35:45.128448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 11:35:45.131767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 11:35:45.138486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2702 11:35:45.142382 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2703 11:35:45.145792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2704 11:35:45.151625 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 11:35:45.155704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 11:35:45.158071 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 11:35:45.164765 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:35:45.169367 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:35:45.171613 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:35:45.178433 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:35:45.182455 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:35:45.185290 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:35:45.191715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 11:35:45.194877 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 11:35:45.198258 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 11:35:45.204812 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 11:35:45.208150 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2718 11:35:45.211948 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2719 11:35:45.214818 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 11:35:45.218860 Total UI for P1: 0, mck2ui 16
2721 11:35:45.221326 best dqsien dly found for B0: ( 0, 15, 18)
2722 11:35:45.225161 Total UI for P1: 0, mck2ui 16
2723 11:35:45.228603 best dqsien dly found for B1: ( 0, 15, 18)
2724 11:35:45.231996 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2725 11:35:45.238586 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2726 11:35:45.238961
2727 11:35:45.241956 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2728 11:35:45.244747 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2729 11:35:45.248148 [Gating] SW calibration Done
2730 11:35:45.248592 ==
2731 11:35:45.252053 Dram Type= 6, Freq= 0, CH_0, rank 1
2732 11:35:45.255191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 11:35:45.255571 ==
2734 11:35:45.255864 RX Vref Scan: 0
2735 11:35:45.256134
2736 11:35:45.258815 RX Vref 0 -> 0, step: 1
2737 11:35:45.259199
2738 11:35:45.262056 RX Delay -40 -> 252, step: 8
2739 11:35:45.265480 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2740 11:35:45.269044 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2741 11:35:45.275491 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2742 11:35:45.279319 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2743 11:35:45.281996 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2744 11:35:45.284985 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2745 11:35:45.288983 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2746 11:35:45.295422 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2747 11:35:45.298564 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2748 11:35:45.302064 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2749 11:35:45.305892 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2750 11:35:45.308837 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2751 11:35:45.311881 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2752 11:35:45.318681 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2753 11:35:45.322712 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2754 11:35:45.325933 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2755 11:35:45.326433 ==
2756 11:35:45.328572 Dram Type= 6, Freq= 0, CH_0, rank 1
2757 11:35:45.332478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2758 11:35:45.332904 ==
2759 11:35:45.335153 DQS Delay:
2760 11:35:45.335588 DQS0 = 0, DQS1 = 0
2761 11:35:45.339044 DQM Delay:
2762 11:35:45.339538 DQM0 = 114, DQM1 = 105
2763 11:35:45.342625 DQ Delay:
2764 11:35:45.345401 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2765 11:35:45.348920 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2766 11:35:45.351968 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2767 11:35:45.355327 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2768 11:35:45.355748
2769 11:35:45.356075
2770 11:35:45.356481 ==
2771 11:35:45.359081 Dram Type= 6, Freq= 0, CH_0, rank 1
2772 11:35:45.361850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2773 11:35:45.362276 ==
2774 11:35:45.362608
2775 11:35:45.362907
2776 11:35:45.366675 TX Vref Scan disable
2777 11:35:45.368586 == TX Byte 0 ==
2778 11:35:45.372076 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2779 11:35:45.375475 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2780 11:35:45.379223 == TX Byte 1 ==
2781 11:35:45.382133 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2782 11:35:45.385586 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2783 11:35:45.386084 ==
2784 11:35:45.388988 Dram Type= 6, Freq= 0, CH_0, rank 1
2785 11:35:45.392421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2786 11:35:45.392922 ==
2787 11:35:45.405328 TX Vref=22, minBit 8, minWin=25, winSum=419
2788 11:35:45.408645 TX Vref=24, minBit 8, minWin=25, winSum=420
2789 11:35:45.411878 TX Vref=26, minBit 8, minWin=25, winSum=425
2790 11:35:45.415792 TX Vref=28, minBit 8, minWin=25, winSum=428
2791 11:35:45.419782 TX Vref=30, minBit 8, minWin=26, winSum=429
2792 11:35:45.421750 TX Vref=32, minBit 8, minWin=25, winSum=431
2793 11:35:45.428917 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
2794 11:35:45.429466
2795 11:35:45.432115 Final TX Range 1 Vref 30
2796 11:35:45.432539
2797 11:35:45.432863 ==
2798 11:35:45.436093 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 11:35:45.438699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 11:35:45.439127 ==
2801 11:35:45.439456
2802 11:35:45.442214
2803 11:35:45.442703 TX Vref Scan disable
2804 11:35:45.445032 == TX Byte 0 ==
2805 11:35:45.449954 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2806 11:35:45.451867 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2807 11:35:45.455034 == TX Byte 1 ==
2808 11:35:45.458685 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2809 11:35:45.463136 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2810 11:35:45.463630
2811 11:35:45.465462 [DATLAT]
2812 11:35:45.465885 Freq=1200, CH0 RK1
2813 11:35:45.466291
2814 11:35:45.469099 DATLAT Default: 0xc
2815 11:35:45.469755 0, 0xFFFF, sum = 0
2816 11:35:45.472015 1, 0xFFFF, sum = 0
2817 11:35:45.472682 2, 0xFFFF, sum = 0
2818 11:35:45.475158 3, 0xFFFF, sum = 0
2819 11:35:45.475588 4, 0xFFFF, sum = 0
2820 11:35:45.478426 5, 0xFFFF, sum = 0
2821 11:35:45.478857 6, 0xFFFF, sum = 0
2822 11:35:45.482494 7, 0xFFFF, sum = 0
2823 11:35:45.482998 8, 0xFFFF, sum = 0
2824 11:35:45.485552 9, 0xFFFF, sum = 0
2825 11:35:45.488624 10, 0xFFFF, sum = 0
2826 11:35:45.489051 11, 0x0, sum = 1
2827 11:35:45.489449 12, 0x0, sum = 2
2828 11:35:45.492552 13, 0x0, sum = 3
2829 11:35:45.493054 14, 0x0, sum = 4
2830 11:35:45.495446 best_step = 12
2831 11:35:45.495867
2832 11:35:45.496192 ==
2833 11:35:45.498647 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 11:35:45.502230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 11:35:45.502720 ==
2836 11:35:45.504996 RX Vref Scan: 0
2837 11:35:45.505459
2838 11:35:45.505787 RX Vref 0 -> 0, step: 1
2839 11:35:45.506087
2840 11:35:45.508753 RX Delay -21 -> 252, step: 4
2841 11:35:45.515983 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2842 11:35:45.518794 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2843 11:35:45.522008 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
2844 11:35:45.526048 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2845 11:35:45.529752 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2846 11:35:45.535781 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2847 11:35:45.538920 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2848 11:35:45.542158 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2849 11:35:45.546002 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2850 11:35:45.549463 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2851 11:35:45.555775 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2852 11:35:45.559109 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2853 11:35:45.562372 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2854 11:35:45.566014 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
2855 11:35:45.568820 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2856 11:35:45.575359 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2857 11:35:45.575826 ==
2858 11:35:45.578833 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 11:35:45.581857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2860 11:35:45.582284 ==
2861 11:35:45.582695 DQS Delay:
2862 11:35:45.585411 DQS0 = 0, DQS1 = 0
2863 11:35:45.585897 DQM Delay:
2864 11:35:45.588368 DQM0 = 114, DQM1 = 106
2865 11:35:45.588791 DQ Delay:
2866 11:35:45.591812 DQ0 =110, DQ1 =116, DQ2 =110, DQ3 =108
2867 11:35:45.594982 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2868 11:35:45.598464 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2869 11:35:45.601821 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2870 11:35:45.602291
2871 11:35:45.602619
2872 11:35:45.611737 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2873 11:35:45.614941 CH0 RK1: MR19=404, MR18=1010
2874 11:35:45.621877 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2875 11:35:45.622365 [RxdqsGatingPostProcess] freq 1200
2876 11:35:45.628346 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2877 11:35:45.631491 Pre-setting of DQS Precalculation
2878 11:35:45.638442 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2879 11:35:45.639034 ==
2880 11:35:45.641308 Dram Type= 6, Freq= 0, CH_1, rank 0
2881 11:35:45.645005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2882 11:35:45.645626 ==
2883 11:35:45.651389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2884 11:35:45.655304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2885 11:35:45.664556 [CA 0] Center 37 (7~68) winsize 62
2886 11:35:45.667875 [CA 1] Center 37 (6~68) winsize 63
2887 11:35:45.671541 [CA 2] Center 34 (4~65) winsize 62
2888 11:35:45.674693 [CA 3] Center 33 (3~64) winsize 62
2889 11:35:45.677580 [CA 4] Center 32 (2~63) winsize 62
2890 11:35:45.680964 [CA 5] Center 32 (2~63) winsize 62
2891 11:35:45.681537
2892 11:35:45.683993 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2893 11:35:45.684512
2894 11:35:45.688213 [CATrainingPosCal] consider 1 rank data
2895 11:35:45.691229 u2DelayCellTimex100 = 270/100 ps
2896 11:35:45.694078 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2897 11:35:45.697527 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2898 11:35:45.701279 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2899 11:35:45.707646 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2900 11:35:45.711110 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2901 11:35:45.714328 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2902 11:35:45.714818
2903 11:35:45.717492 CA PerBit enable=1, Macro0, CA PI delay=32
2904 11:35:45.717915
2905 11:35:45.721457 [CBTSetCACLKResult] CA Dly = 32
2906 11:35:45.722017 CS Dly: 6 (0~37)
2907 11:35:45.722357 ==
2908 11:35:45.724643 Dram Type= 6, Freq= 0, CH_1, rank 1
2909 11:35:45.730615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2910 11:35:45.731064 ==
2911 11:35:45.734422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2912 11:35:45.740796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2913 11:35:45.750316 [CA 0] Center 37 (7~68) winsize 62
2914 11:35:45.752700 [CA 1] Center 37 (6~68) winsize 63
2915 11:35:45.756119 [CA 2] Center 33 (3~64) winsize 62
2916 11:35:45.759806 [CA 3] Center 33 (3~64) winsize 62
2917 11:35:45.763100 [CA 4] Center 32 (2~63) winsize 62
2918 11:35:45.765753 [CA 5] Center 31 (1~62) winsize 62
2919 11:35:45.766198
2920 11:35:45.768836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2921 11:35:45.769299
2922 11:35:45.772601 [CATrainingPosCal] consider 2 rank data
2923 11:35:45.775716 u2DelayCellTimex100 = 270/100 ps
2924 11:35:45.779592 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2925 11:35:45.783346 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2926 11:35:45.789392 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2927 11:35:45.793386 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2928 11:35:45.796118 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2929 11:35:45.799287 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2930 11:35:45.799713
2931 11:35:45.802653 CA PerBit enable=1, Macro0, CA PI delay=32
2932 11:35:45.803149
2933 11:35:45.805716 [CBTSetCACLKResult] CA Dly = 32
2934 11:35:45.806138 CS Dly: 6 (0~37)
2935 11:35:45.806469
2936 11:35:45.809422 ----->DramcWriteLeveling(PI) begin...
2937 11:35:45.812495 ==
2938 11:35:45.816246 Dram Type= 6, Freq= 0, CH_1, rank 0
2939 11:35:45.819716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2940 11:35:45.820145 ==
2941 11:35:45.823087 Write leveling (Byte 0): 22 => 22
2942 11:35:45.825923 Write leveling (Byte 1): 22 => 22
2943 11:35:45.830192 DramcWriteLeveling(PI) end<-----
2944 11:35:45.830661
2945 11:35:45.831224 ==
2946 11:35:45.832504 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 11:35:45.835986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 11:35:45.836456 ==
2949 11:35:45.839129 [Gating] SW mode calibration
2950 11:35:45.846458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2951 11:35:45.849739 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2952 11:35:45.856472 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 11:35:45.859438 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 11:35:45.863207 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 11:35:45.869307 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 11:35:45.872613 0 11 16 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
2957 11:35:45.876024 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2958 11:35:45.882496 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 11:35:45.886804 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 11:35:45.889907 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 11:35:45.896153 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 11:35:45.899558 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 11:35:45.903207 0 12 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2964 11:35:45.909476 0 12 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2965 11:35:45.912940 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 11:35:45.916439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:35:45.920339 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 11:35:45.926713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:35:45.929143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:35:45.932806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:35:45.939257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:35:45.943292 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2973 11:35:45.946394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:35:45.952747 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:35:45.956278 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:35:45.959436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:35:45.966192 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:35:45.969778 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:35:45.972521 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:35:45.979563 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:35:45.983295 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:35:45.986195 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:35:45.993019 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:35:45.996298 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:35:45.999786 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:35:46.005946 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:35:46.009200 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2988 11:35:46.012575 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2989 11:35:46.016864 Total UI for P1: 0, mck2ui 16
2990 11:35:46.019515 best dqsien dly found for B0: ( 0, 15, 12)
2991 11:35:46.022374 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2992 11:35:46.030317 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 11:35:46.032505 Total UI for P1: 0, mck2ui 16
2994 11:35:46.036097 best dqsien dly found for B1: ( 0, 15, 18)
2995 11:35:46.039588 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
2996 11:35:46.042621 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2997 11:35:46.043039
2998 11:35:46.046095 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
2999 11:35:46.049018 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3000 11:35:46.052482 [Gating] SW calibration Done
3001 11:35:46.052902 ==
3002 11:35:46.056294 Dram Type= 6, Freq= 0, CH_1, rank 0
3003 11:35:46.059152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3004 11:35:46.059581 ==
3005 11:35:46.062668 RX Vref Scan: 0
3006 11:35:46.063089
3007 11:35:46.065996 RX Vref 0 -> 0, step: 1
3008 11:35:46.066418
3009 11:35:46.066742 RX Delay -40 -> 252, step: 8
3010 11:35:46.072441 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3011 11:35:46.075804 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3012 11:35:46.080812 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3013 11:35:46.082379 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3014 11:35:46.086140 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3015 11:35:46.093333 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3016 11:35:46.095869 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3017 11:35:46.099862 iDelay=208, Bit 7, Center 111 (32 ~ 191) 160
3018 11:35:46.102147 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3019 11:35:46.105781 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3020 11:35:46.112446 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3021 11:35:46.116346 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3022 11:35:46.119819 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3023 11:35:46.122378 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3024 11:35:46.125413 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3025 11:35:46.132437 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3026 11:35:46.132909 ==
3027 11:35:46.135606 Dram Type= 6, Freq= 0, CH_1, rank 0
3028 11:35:46.139453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3029 11:35:46.139901 ==
3030 11:35:46.140227 DQS Delay:
3031 11:35:46.142379 DQS0 = 0, DQS1 = 0
3032 11:35:46.142793 DQM Delay:
3033 11:35:46.146130 DQM0 = 115, DQM1 = 107
3034 11:35:46.146588 DQ Delay:
3035 11:35:46.149059 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3036 11:35:46.152373 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =111
3037 11:35:46.155742 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3038 11:35:46.159039 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3039 11:35:46.159464
3040 11:35:46.159809
3041 11:35:46.160109 ==
3042 11:35:46.162636 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 11:35:46.169363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3044 11:35:46.169830 ==
3045 11:35:46.170161
3046 11:35:46.170461
3047 11:35:46.170805 TX Vref Scan disable
3048 11:35:46.173121 == TX Byte 0 ==
3049 11:35:46.176052 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3050 11:35:46.182569 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3051 11:35:46.182997 == TX Byte 1 ==
3052 11:35:46.186474 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3053 11:35:46.192724 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3054 11:35:46.193155 ==
3055 11:35:46.195706 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 11:35:46.199574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3057 11:35:46.200002 ==
3058 11:35:46.210063 TX Vref=22, minBit 5, minWin=25, winSum=412
3059 11:35:46.214109 TX Vref=24, minBit 9, minWin=25, winSum=425
3060 11:35:46.216814 TX Vref=26, minBit 0, minWin=26, winSum=427
3061 11:35:46.220122 TX Vref=28, minBit 1, minWin=26, winSum=431
3062 11:35:46.223466 TX Vref=30, minBit 9, minWin=25, winSum=431
3063 11:35:46.230949 TX Vref=32, minBit 9, minWin=25, winSum=427
3064 11:35:46.234062 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3065 11:35:46.234491
3066 11:35:46.237292 Final TX Range 1 Vref 28
3067 11:35:46.237749
3068 11:35:46.238080 ==
3069 11:35:46.239827 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 11:35:46.243283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 11:35:46.247007 ==
3072 11:35:46.247464
3073 11:35:46.247795
3074 11:35:46.248098 TX Vref Scan disable
3075 11:35:46.251514 == TX Byte 0 ==
3076 11:35:46.253017 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3077 11:35:46.259798 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3078 11:35:46.260225 == TX Byte 1 ==
3079 11:35:46.263719 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3080 11:35:46.269972 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3081 11:35:46.270413
3082 11:35:46.270738 [DATLAT]
3083 11:35:46.271038 Freq=1200, CH1 RK0
3084 11:35:46.271364
3085 11:35:46.273152 DATLAT Default: 0xd
3086 11:35:46.276126 0, 0xFFFF, sum = 0
3087 11:35:46.276573 1, 0xFFFF, sum = 0
3088 11:35:46.279871 2, 0xFFFF, sum = 0
3089 11:35:46.280395 3, 0xFFFF, sum = 0
3090 11:35:46.282759 4, 0xFFFF, sum = 0
3091 11:35:46.283182 5, 0xFFFF, sum = 0
3092 11:35:46.285956 6, 0xFFFF, sum = 0
3093 11:35:46.286453 7, 0xFFFF, sum = 0
3094 11:35:46.289639 8, 0xFFFF, sum = 0
3095 11:35:46.290198 9, 0xFFFF, sum = 0
3096 11:35:46.293135 10, 0xFFFF, sum = 0
3097 11:35:46.293792 11, 0x0, sum = 1
3098 11:35:46.295893 12, 0x0, sum = 2
3099 11:35:46.296398 13, 0x0, sum = 3
3100 11:35:46.299430 14, 0x0, sum = 4
3101 11:35:46.299967 best_step = 12
3102 11:35:46.300288
3103 11:35:46.300659 ==
3104 11:35:46.302654 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:35:46.305808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 11:35:46.309817 ==
3107 11:35:46.310227 RX Vref Scan: 1
3108 11:35:46.310520
3109 11:35:46.312423 Set Vref Range= 32 -> 127
3110 11:35:46.312895
3111 11:35:46.316119 RX Vref 32 -> 127, step: 1
3112 11:35:46.316477
3113 11:35:46.316761 RX Delay -29 -> 252, step: 4
3114 11:35:46.317032
3115 11:35:46.319519 Set Vref, RX VrefLevel [Byte0]: 32
3116 11:35:46.322339 [Byte1]: 32
3117 11:35:46.326614
3118 11:35:46.327026 Set Vref, RX VrefLevel [Byte0]: 33
3119 11:35:46.330261 [Byte1]: 33
3120 11:35:46.334778
3121 11:35:46.335374 Set Vref, RX VrefLevel [Byte0]: 34
3122 11:35:46.338810 [Byte1]: 34
3123 11:35:46.342429
3124 11:35:46.342884 Set Vref, RX VrefLevel [Byte0]: 35
3125 11:35:46.346258 [Byte1]: 35
3126 11:35:46.350272
3127 11:35:46.350915 Set Vref, RX VrefLevel [Byte0]: 36
3128 11:35:46.353744 [Byte1]: 36
3129 11:35:46.358668
3130 11:35:46.359049 Set Vref, RX VrefLevel [Byte0]: 37
3131 11:35:46.361995 [Byte1]: 37
3132 11:35:46.366675
3133 11:35:46.367053 Set Vref, RX VrefLevel [Byte0]: 38
3134 11:35:46.369530 [Byte1]: 38
3135 11:35:46.374228
3136 11:35:46.374626 Set Vref, RX VrefLevel [Byte0]: 39
3137 11:35:46.377348 [Byte1]: 39
3138 11:35:46.382830
3139 11:35:46.383255 Set Vref, RX VrefLevel [Byte0]: 40
3140 11:35:46.385768 [Byte1]: 40
3141 11:35:46.390649
3142 11:35:46.391038 Set Vref, RX VrefLevel [Byte0]: 41
3143 11:35:46.393363 [Byte1]: 41
3144 11:35:46.398179
3145 11:35:46.398556 Set Vref, RX VrefLevel [Byte0]: 42
3146 11:35:46.401295 [Byte1]: 42
3147 11:35:46.406071
3148 11:35:46.406493 Set Vref, RX VrefLevel [Byte0]: 43
3149 11:35:46.409334 [Byte1]: 43
3150 11:35:46.415564
3151 11:35:46.415973 Set Vref, RX VrefLevel [Byte0]: 44
3152 11:35:46.417542 [Byte1]: 44
3153 11:35:46.422314
3154 11:35:46.422785 Set Vref, RX VrefLevel [Byte0]: 45
3155 11:35:46.425697 [Byte1]: 45
3156 11:35:46.430187
3157 11:35:46.430604 Set Vref, RX VrefLevel [Byte0]: 46
3158 11:35:46.433802 [Byte1]: 46
3159 11:35:46.438385
3160 11:35:46.438852 Set Vref, RX VrefLevel [Byte0]: 47
3161 11:35:46.441407 [Byte1]: 47
3162 11:35:46.445996
3163 11:35:46.446494 Set Vref, RX VrefLevel [Byte0]: 48
3164 11:35:46.449594 [Byte1]: 48
3165 11:35:46.453986
3166 11:35:46.454402 Set Vref, RX VrefLevel [Byte0]: 49
3167 11:35:46.457150 [Byte1]: 49
3168 11:35:46.462461
3169 11:35:46.462935 Set Vref, RX VrefLevel [Byte0]: 50
3170 11:35:46.465188 [Byte1]: 50
3171 11:35:46.469631
3172 11:35:46.470108 Set Vref, RX VrefLevel [Byte0]: 51
3173 11:35:46.473176 [Byte1]: 51
3174 11:35:46.477999
3175 11:35:46.478465 Set Vref, RX VrefLevel [Byte0]: 52
3176 11:35:46.481374 [Byte1]: 52
3177 11:35:46.485753
3178 11:35:46.486170 Set Vref, RX VrefLevel [Byte0]: 53
3179 11:35:46.488989 [Byte1]: 53
3180 11:35:46.494057
3181 11:35:46.494472 Set Vref, RX VrefLevel [Byte0]: 54
3182 11:35:46.496924 [Byte1]: 54
3183 11:35:46.501961
3184 11:35:46.502377 Set Vref, RX VrefLevel [Byte0]: 55
3185 11:35:46.505121 [Byte1]: 55
3186 11:35:46.509651
3187 11:35:46.510073 Set Vref, RX VrefLevel [Byte0]: 56
3188 11:35:46.513151 [Byte1]: 56
3189 11:35:46.517690
3190 11:35:46.518198 Set Vref, RX VrefLevel [Byte0]: 57
3191 11:35:46.520829 [Byte1]: 57
3192 11:35:46.525342
3193 11:35:46.525768 Set Vref, RX VrefLevel [Byte0]: 58
3194 11:35:46.528850 [Byte1]: 58
3195 11:35:46.533750
3196 11:35:46.534222 Set Vref, RX VrefLevel [Byte0]: 59
3197 11:35:46.536913 [Byte1]: 59
3198 11:35:46.541221
3199 11:35:46.541692 Set Vref, RX VrefLevel [Byte0]: 60
3200 11:35:46.544588 [Byte1]: 60
3201 11:35:46.550094
3202 11:35:46.550511 Set Vref, RX VrefLevel [Byte0]: 61
3203 11:35:46.552913 [Byte1]: 61
3204 11:35:46.557746
3205 11:35:46.558166 Set Vref, RX VrefLevel [Byte0]: 62
3206 11:35:46.560706 [Byte1]: 62
3207 11:35:46.565219
3208 11:35:46.565727 Set Vref, RX VrefLevel [Byte0]: 63
3209 11:35:46.569404 [Byte1]: 63
3210 11:35:46.573187
3211 11:35:46.573705 Set Vref, RX VrefLevel [Byte0]: 64
3212 11:35:46.576605 [Byte1]: 64
3213 11:35:46.581497
3214 11:35:46.581942 Set Vref, RX VrefLevel [Byte0]: 65
3215 11:35:46.585185 [Byte1]: 65
3216 11:35:46.589266
3217 11:35:46.589690 Final RX Vref Byte 0 = 51 to rank0
3218 11:35:46.592648 Final RX Vref Byte 1 = 50 to rank0
3219 11:35:46.596462 Final RX Vref Byte 0 = 51 to rank1
3220 11:35:46.599206 Final RX Vref Byte 1 = 50 to rank1==
3221 11:35:46.602305 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:35:46.609058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3223 11:35:46.609623 ==
3224 11:35:46.609959 DQS Delay:
3225 11:35:46.610261 DQS0 = 0, DQS1 = 0
3226 11:35:46.612415 DQM Delay:
3227 11:35:46.612831 DQM0 = 115, DQM1 = 105
3228 11:35:46.616106 DQ Delay:
3229 11:35:46.619222 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3230 11:35:46.622561 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3231 11:35:46.627316 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3232 11:35:46.629039 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3233 11:35:46.629605
3234 11:35:46.629945
3235 11:35:46.635767 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3236 11:35:46.639005 CH1 RK0: MR19=404, MR18=1919
3237 11:35:46.646270 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3238 11:35:46.646746
3239 11:35:46.648856 ----->DramcWriteLeveling(PI) begin...
3240 11:35:46.649360 ==
3241 11:35:46.652683 Dram Type= 6, Freq= 0, CH_1, rank 1
3242 11:35:46.659572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3243 11:35:46.660063 ==
3244 11:35:46.661787 Write leveling (Byte 0): 21 => 21
3245 11:35:46.662256 Write leveling (Byte 1): 21 => 21
3246 11:35:46.665563 DramcWriteLeveling(PI) end<-----
3247 11:35:46.666069
3248 11:35:46.666394 ==
3249 11:35:46.668591 Dram Type= 6, Freq= 0, CH_1, rank 1
3250 11:35:46.675153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3251 11:35:46.675578 ==
3252 11:35:46.679252 [Gating] SW mode calibration
3253 11:35:46.685839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3254 11:35:46.688780 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3255 11:35:46.695068 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 11:35:46.698440 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3257 11:35:46.701699 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3258 11:35:46.708308 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
3259 11:35:46.711775 0 11 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
3260 11:35:46.714706 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 11:35:46.721874 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 11:35:46.725767 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 11:35:46.728192 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 11:35:46.735061 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 11:35:46.738773 0 12 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3266 11:35:46.742467 0 12 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
3267 11:35:46.748251 0 12 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3268 11:35:46.751443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 11:35:46.754635 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 11:35:46.761837 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 11:35:46.766134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 11:35:46.767714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 11:35:46.774520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 11:35:46.778477 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3275 11:35:46.780976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3276 11:35:46.784957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3277 11:35:46.791298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 11:35:46.794298 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 11:35:46.797851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 11:35:46.804964 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 11:35:46.807568 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 11:35:46.811019 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 11:35:46.817863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 11:35:46.820692 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:35:46.824243 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:35:46.831243 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:35:46.834126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:35:46.837740 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:35:46.844843 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 11:35:46.847627 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3291 11:35:46.851296 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3292 11:35:46.854135 Total UI for P1: 0, mck2ui 16
3293 11:35:46.857353 best dqsien dly found for B0: ( 0, 15, 12)
3294 11:35:46.864176 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 11:35:46.864642 Total UI for P1: 0, mck2ui 16
3296 11:35:46.870646 best dqsien dly found for B1: ( 0, 15, 14)
3297 11:35:46.874344 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3298 11:35:46.877139 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3299 11:35:46.877715
3300 11:35:46.881398 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3301 11:35:46.883943 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3302 11:35:46.887347 [Gating] SW calibration Done
3303 11:35:46.887763 ==
3304 11:35:46.890563 Dram Type= 6, Freq= 0, CH_1, rank 1
3305 11:35:46.894012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3306 11:35:46.894431 ==
3307 11:35:46.896935 RX Vref Scan: 0
3308 11:35:46.897372
3309 11:35:46.900354 RX Vref 0 -> 0, step: 1
3310 11:35:46.900768
3311 11:35:46.901087 RX Delay -40 -> 252, step: 8
3312 11:35:46.906914 iDelay=200, Bit 0, Center 119 (56 ~ 183) 128
3313 11:35:46.910057 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3314 11:35:46.913617 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3315 11:35:46.917014 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3316 11:35:46.920015 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3317 11:35:46.927615 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3318 11:35:46.930209 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3319 11:35:46.933580 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3320 11:35:46.937157 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3321 11:35:46.940293 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3322 11:35:46.947788 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3323 11:35:46.950278 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3324 11:35:46.954054 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3325 11:35:46.957136 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3326 11:35:46.960077 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3327 11:35:46.966535 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3328 11:35:46.966952 ==
3329 11:35:46.970480 Dram Type= 6, Freq= 0, CH_1, rank 1
3330 11:35:46.973213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3331 11:35:46.973782 ==
3332 11:35:46.974110 DQS Delay:
3333 11:35:46.976707 DQS0 = 0, DQS1 = 0
3334 11:35:46.977180 DQM Delay:
3335 11:35:46.979915 DQM0 = 116, DQM1 = 105
3336 11:35:46.980408 DQ Delay:
3337 11:35:46.983023 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3338 11:35:46.986449 DQ4 =119, DQ5 =123, DQ6 =127, DQ7 =111
3339 11:35:46.990660 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
3340 11:35:46.993336 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3341 11:35:46.993904
3342 11:35:46.994415
3343 11:35:46.996600 ==
3344 11:35:46.997112 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 11:35:47.002976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 11:35:47.003416 ==
3347 11:35:47.003737
3348 11:35:47.004046
3349 11:35:47.006488 TX Vref Scan disable
3350 11:35:47.006901 == TX Byte 0 ==
3351 11:35:47.010996 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3352 11:35:47.016484 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3353 11:35:47.016967 == TX Byte 1 ==
3354 11:35:47.020278 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3355 11:35:47.026757 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3356 11:35:47.027219 ==
3357 11:35:47.031352 Dram Type= 6, Freq= 0, CH_1, rank 1
3358 11:35:47.032635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3359 11:35:47.033051 ==
3360 11:35:47.044889 TX Vref=22, minBit 9, minWin=25, winSum=421
3361 11:35:47.048074 TX Vref=24, minBit 9, minWin=25, winSum=427
3362 11:35:47.051456 TX Vref=26, minBit 9, minWin=25, winSum=426
3363 11:35:47.054464 TX Vref=28, minBit 8, minWin=26, winSum=431
3364 11:35:47.058956 TX Vref=30, minBit 9, minWin=26, winSum=434
3365 11:35:47.064662 TX Vref=32, minBit 9, minWin=26, winSum=434
3366 11:35:47.067999 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3367 11:35:47.068416
3368 11:35:47.071311 Final TX Range 1 Vref 30
3369 11:35:47.071730
3370 11:35:47.072047 ==
3371 11:35:47.075039 Dram Type= 6, Freq= 0, CH_1, rank 1
3372 11:35:47.078065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3373 11:35:47.078484 ==
3374 11:35:47.078855
3375 11:35:47.081209
3376 11:35:47.081691 TX Vref Scan disable
3377 11:35:47.085169 == TX Byte 0 ==
3378 11:35:47.088297 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3379 11:35:47.091227 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3380 11:35:47.094324 == TX Byte 1 ==
3381 11:35:47.097915 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3382 11:35:47.102385 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3383 11:35:47.104379
3384 11:35:47.104753 [DATLAT]
3385 11:35:47.105060 Freq=1200, CH1 RK1
3386 11:35:47.105336
3387 11:35:47.108265 DATLAT Default: 0xc
3388 11:35:47.108551 0, 0xFFFF, sum = 0
3389 11:35:47.111994 1, 0xFFFF, sum = 0
3390 11:35:47.112389 2, 0xFFFF, sum = 0
3391 11:35:47.114988 3, 0xFFFF, sum = 0
3392 11:35:47.115282 4, 0xFFFF, sum = 0
3393 11:35:47.117677 5, 0xFFFF, sum = 0
3394 11:35:47.117969 6, 0xFFFF, sum = 0
3395 11:35:47.121690 7, 0xFFFF, sum = 0
3396 11:35:47.124671 8, 0xFFFF, sum = 0
3397 11:35:47.124966 9, 0xFFFF, sum = 0
3398 11:35:47.127790 10, 0xFFFF, sum = 0
3399 11:35:47.128081 11, 0x0, sum = 1
3400 11:35:47.131039 12, 0x0, sum = 2
3401 11:35:47.131347 13, 0x0, sum = 3
3402 11:35:47.131577 14, 0x0, sum = 4
3403 11:35:47.134203 best_step = 12
3404 11:35:47.134486
3405 11:35:47.134705 ==
3406 11:35:47.138003 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 11:35:47.141346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3408 11:35:47.141637 ==
3409 11:35:47.144328 RX Vref Scan: 0
3410 11:35:47.144615
3411 11:35:47.144837 RX Vref 0 -> 0, step: 1
3412 11:35:47.147308
3413 11:35:47.147593 RX Delay -29 -> 252, step: 4
3414 11:35:47.155833 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3415 11:35:47.159052 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3416 11:35:47.162175 iDelay=195, Bit 2, Center 106 (35 ~ 178) 144
3417 11:35:47.165000 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3418 11:35:47.167788 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3419 11:35:47.174389 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3420 11:35:47.178616 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3421 11:35:47.181628 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3422 11:35:47.184974 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3423 11:35:47.187898 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3424 11:35:47.194877 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3425 11:35:47.198306 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3426 11:35:47.200905 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3427 11:35:47.204174 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3428 11:35:47.207712 iDelay=195, Bit 14, Center 112 (43 ~ 182) 140
3429 11:35:47.214451 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3430 11:35:47.214807 ==
3431 11:35:47.217943 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:35:47.220988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3433 11:35:47.221508 ==
3434 11:35:47.221893 DQS Delay:
3435 11:35:47.225812 DQS0 = 0, DQS1 = 0
3436 11:35:47.226269 DQM Delay:
3437 11:35:47.227850 DQM0 = 114, DQM1 = 103
3438 11:35:47.228228 DQ Delay:
3439 11:35:47.230893 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =110
3440 11:35:47.234376 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3441 11:35:47.238274 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3442 11:35:47.241553 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3443 11:35:47.241937
3444 11:35:47.242346
3445 11:35:47.250724 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3446 11:35:47.254059 CH1 RK1: MR19=404, MR18=707
3447 11:35:47.261149 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3448 11:35:47.261627 [RxdqsGatingPostProcess] freq 1200
3449 11:35:47.267415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3450 11:35:47.270758 Pre-setting of DQS Precalculation
3451 11:35:47.273988 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3452 11:35:47.284585 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3453 11:35:47.290847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3454 11:35:47.291232
3455 11:35:47.291528
3456 11:35:47.293875 [Calibration Summary] 2400 Mbps
3457 11:35:47.294257 CH 0, Rank 0
3458 11:35:47.297855 SW Impedance : PASS
3459 11:35:47.301203 DUTY Scan : NO K
3460 11:35:47.301653 ZQ Calibration : PASS
3461 11:35:47.304024 Jitter Meter : NO K
3462 11:35:47.304412 CBT Training : PASS
3463 11:35:47.308031 Write leveling : PASS
3464 11:35:47.310267 RX DQS gating : PASS
3465 11:35:47.310689 RX DQ/DQS(RDDQC) : PASS
3466 11:35:47.314102 TX DQ/DQS : PASS
3467 11:35:47.317729 RX DATLAT : PASS
3468 11:35:47.318196 RX DQ/DQS(Engine): PASS
3469 11:35:47.320205 TX OE : NO K
3470 11:35:47.320625 All Pass.
3471 11:35:47.320947
3472 11:35:47.324626 CH 0, Rank 1
3473 11:35:47.325075 SW Impedance : PASS
3474 11:35:47.327084 DUTY Scan : NO K
3475 11:35:47.330437 ZQ Calibration : PASS
3476 11:35:47.330983 Jitter Meter : NO K
3477 11:35:47.333948 CBT Training : PASS
3478 11:35:47.337607 Write leveling : PASS
3479 11:35:47.338069 RX DQS gating : PASS
3480 11:35:47.340664 RX DQ/DQS(RDDQC) : PASS
3481 11:35:47.343872 TX DQ/DQS : PASS
3482 11:35:47.344290 RX DATLAT : PASS
3483 11:35:47.347020 RX DQ/DQS(Engine): PASS
3484 11:35:47.347509 TX OE : NO K
3485 11:35:47.350229 All Pass.
3486 11:35:47.350697
3487 11:35:47.351197 CH 1, Rank 0
3488 11:35:47.353880 SW Impedance : PASS
3489 11:35:47.354371 DUTY Scan : NO K
3490 11:35:47.357331 ZQ Calibration : PASS
3491 11:35:47.361074 Jitter Meter : NO K
3492 11:35:47.361585 CBT Training : PASS
3493 11:35:47.363794 Write leveling : PASS
3494 11:35:47.367436 RX DQS gating : PASS
3495 11:35:47.367897 RX DQ/DQS(RDDQC) : PASS
3496 11:35:47.370284 TX DQ/DQS : PASS
3497 11:35:47.373706 RX DATLAT : PASS
3498 11:35:47.374192 RX DQ/DQS(Engine): PASS
3499 11:35:47.376837 TX OE : NO K
3500 11:35:47.377334 All Pass.
3501 11:35:47.377770
3502 11:35:47.380199 CH 1, Rank 1
3503 11:35:47.380659 SW Impedance : PASS
3504 11:35:47.384085 DUTY Scan : NO K
3505 11:35:47.387682 ZQ Calibration : PASS
3506 11:35:47.388104 Jitter Meter : NO K
3507 11:35:47.390392 CBT Training : PASS
3508 11:35:47.393561 Write leveling : PASS
3509 11:35:47.394087 RX DQS gating : PASS
3510 11:35:47.397050 RX DQ/DQS(RDDQC) : PASS
3511 11:35:47.400504 TX DQ/DQS : PASS
3512 11:35:47.401071 RX DATLAT : PASS
3513 11:35:47.403859 RX DQ/DQS(Engine): PASS
3514 11:35:47.404426 TX OE : NO K
3515 11:35:47.406830 All Pass.
3516 11:35:47.407416
3517 11:35:47.407898 DramC Write-DBI off
3518 11:35:47.410681 PER_BANK_REFRESH: Hybrid Mode
3519 11:35:47.413616 TX_TRACKING: ON
3520 11:35:47.420456 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3521 11:35:47.423604 [FAST_K] Save calibration result to emmc
3522 11:35:47.429930 dramc_set_vcore_voltage set vcore to 650000
3523 11:35:47.430363 Read voltage for 600, 5
3524 11:35:47.430664 Vio18 = 0
3525 11:35:47.433542 Vcore = 650000
3526 11:35:47.433926 Vdram = 0
3527 11:35:47.434307 Vddq = 0
3528 11:35:47.436584 Vmddr = 0
3529 11:35:47.440292 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3530 11:35:47.446761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3531 11:35:47.447431 MEM_TYPE=3, freq_sel=19
3532 11:35:47.450010 sv_algorithm_assistance_LP4_1600
3533 11:35:47.456457 ============ PULL DRAM RESETB DOWN ============
3534 11:35:47.459875 ========== PULL DRAM RESETB DOWN end =========
3535 11:35:47.463366 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3536 11:35:47.466665 ===================================
3537 11:35:47.469703 LPDDR4 DRAM CONFIGURATION
3538 11:35:47.473077 ===================================
3539 11:35:47.476923 EX_ROW_EN[0] = 0x0
3540 11:35:47.477470 EX_ROW_EN[1] = 0x0
3541 11:35:47.479780 LP4Y_EN = 0x0
3542 11:35:47.480265 WORK_FSP = 0x0
3543 11:35:47.483514 WL = 0x2
3544 11:35:47.483932 RL = 0x2
3545 11:35:47.487419 BL = 0x2
3546 11:35:47.487884 RPST = 0x0
3547 11:35:47.489761 RD_PRE = 0x0
3548 11:35:47.490281 WR_PRE = 0x1
3549 11:35:47.493722 WR_PST = 0x0
3550 11:35:47.494240 DBI_WR = 0x0
3551 11:35:47.496513 DBI_RD = 0x0
3552 11:35:47.497331 OTF = 0x1
3553 11:35:47.499828 ===================================
3554 11:35:47.503640 ===================================
3555 11:35:47.506436 ANA top config
3556 11:35:47.509791 ===================================
3557 11:35:47.513011 DLL_ASYNC_EN = 0
3558 11:35:47.513512 ALL_SLAVE_EN = 1
3559 11:35:47.516756 NEW_RANK_MODE = 1
3560 11:35:47.520005 DLL_IDLE_MODE = 1
3561 11:35:47.523668 LP45_APHY_COMB_EN = 1
3562 11:35:47.524257 TX_ODT_DIS = 1
3563 11:35:47.526791 NEW_8X_MODE = 1
3564 11:35:47.530220 ===================================
3565 11:35:47.532833 ===================================
3566 11:35:47.536551 data_rate = 1200
3567 11:35:47.539774 CKR = 1
3568 11:35:47.543298 DQ_P2S_RATIO = 8
3569 11:35:47.546026 ===================================
3570 11:35:47.549581 CA_P2S_RATIO = 8
3571 11:35:47.550061 DQ_CA_OPEN = 0
3572 11:35:47.552963 DQ_SEMI_OPEN = 0
3573 11:35:47.555956 CA_SEMI_OPEN = 0
3574 11:35:47.559659 CA_FULL_RATE = 0
3575 11:35:47.562792 DQ_CKDIV4_EN = 1
3576 11:35:47.566289 CA_CKDIV4_EN = 1
3577 11:35:47.566738 CA_PREDIV_EN = 0
3578 11:35:47.569157 PH8_DLY = 0
3579 11:35:47.573068 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3580 11:35:47.576727 DQ_AAMCK_DIV = 4
3581 11:35:47.580051 CA_AAMCK_DIV = 4
3582 11:35:47.582899 CA_ADMCK_DIV = 4
3583 11:35:47.583278 DQ_TRACK_CA_EN = 0
3584 11:35:47.586825 CA_PICK = 600
3585 11:35:47.589892 CA_MCKIO = 600
3586 11:35:47.593067 MCKIO_SEMI = 0
3587 11:35:47.596021 PLL_FREQ = 2288
3588 11:35:47.599222 DQ_UI_PI_RATIO = 32
3589 11:35:47.603220 CA_UI_PI_RATIO = 0
3590 11:35:47.605864 ===================================
3591 11:35:47.609942 ===================================
3592 11:35:47.610411 memory_type:LPDDR4
3593 11:35:47.612685 GP_NUM : 10
3594 11:35:47.616072 SRAM_EN : 1
3595 11:35:47.616452 MD32_EN : 0
3596 11:35:47.619432 ===================================
3597 11:35:47.623185 [ANA_INIT] >>>>>>>>>>>>>>
3598 11:35:47.625933 <<<<<< [CONFIGURE PHASE]: ANA_TX
3599 11:35:47.629012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3600 11:35:47.632259 ===================================
3601 11:35:47.635638 data_rate = 1200,PCW = 0X5800
3602 11:35:47.639079 ===================================
3603 11:35:47.642412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3604 11:35:47.646726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3605 11:35:47.653066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3606 11:35:47.656072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3607 11:35:47.659136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3608 11:35:47.662303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3609 11:35:47.665825 [ANA_INIT] flow start
3610 11:35:47.668750 [ANA_INIT] PLL >>>>>>>>
3611 11:35:47.669136 [ANA_INIT] PLL <<<<<<<<
3612 11:35:47.672194 [ANA_INIT] MIDPI >>>>>>>>
3613 11:35:47.675831 [ANA_INIT] MIDPI <<<<<<<<
3614 11:35:47.678928 [ANA_INIT] DLL >>>>>>>>
3615 11:35:47.679314 [ANA_INIT] flow end
3616 11:35:47.682265 ============ LP4 DIFF to SE enter ============
3617 11:35:47.688849 ============ LP4 DIFF to SE exit ============
3618 11:35:47.689341 [ANA_INIT] <<<<<<<<<<<<<
3619 11:35:47.692294 [Flow] Enable top DCM control >>>>>
3620 11:35:47.695512 [Flow] Enable top DCM control <<<<<
3621 11:35:47.698665 Enable DLL master slave shuffle
3622 11:35:47.705552 ==============================================================
3623 11:35:47.705932 Gating Mode config
3624 11:35:47.712579 ==============================================================
3625 11:35:47.715342 Config description:
3626 11:35:47.721820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3627 11:35:47.728547 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3628 11:35:47.735393 SELPH_MODE 0: By rank 1: By Phase
3629 11:35:47.742004 ==============================================================
3630 11:35:47.742470 GAT_TRACK_EN = 1
3631 11:35:47.745325 RX_GATING_MODE = 2
3632 11:35:47.748939 RX_GATING_TRACK_MODE = 2
3633 11:35:47.751805 SELPH_MODE = 1
3634 11:35:47.755157 PICG_EARLY_EN = 1
3635 11:35:47.759327 VALID_LAT_VALUE = 1
3636 11:35:47.765814 ==============================================================
3637 11:35:47.769103 Enter into Gating configuration >>>>
3638 11:35:47.772675 Exit from Gating configuration <<<<
3639 11:35:47.773059 Enter into DVFS_PRE_config >>>>>
3640 11:35:47.785612 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3641 11:35:47.789103 Exit from DVFS_PRE_config <<<<<
3642 11:35:47.792507 Enter into PICG configuration >>>>
3643 11:35:47.795625 Exit from PICG configuration <<<<
3644 11:35:47.795841 [RX_INPUT] configuration >>>>>
3645 11:35:47.799609 [RX_INPUT] configuration <<<<<
3646 11:35:47.805221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3647 11:35:47.808329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3648 11:35:47.815464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3649 11:35:47.821759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3650 11:35:47.828824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3651 11:35:47.835579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3652 11:35:47.838838 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3653 11:35:47.841379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3654 11:35:47.848589 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3655 11:35:47.852055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3656 11:35:47.856209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3657 11:35:47.862135 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3658 11:35:47.865540 ===================================
3659 11:35:47.865963 LPDDR4 DRAM CONFIGURATION
3660 11:35:47.869301 ===================================
3661 11:35:47.871502 EX_ROW_EN[0] = 0x0
3662 11:35:47.871876 EX_ROW_EN[1] = 0x0
3663 11:35:47.875565 LP4Y_EN = 0x0
3664 11:35:47.875943 WORK_FSP = 0x0
3665 11:35:47.878468 WL = 0x2
3666 11:35:47.878863 RL = 0x2
3667 11:35:47.883150 BL = 0x2
3668 11:35:47.885690 RPST = 0x0
3669 11:35:47.886063 RD_PRE = 0x0
3670 11:35:47.889437 WR_PRE = 0x1
3671 11:35:47.889813 WR_PST = 0x0
3672 11:35:47.891847 DBI_WR = 0x0
3673 11:35:47.892222 DBI_RD = 0x0
3674 11:35:47.894963 OTF = 0x1
3675 11:35:47.898172 ===================================
3676 11:35:47.901530 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3677 11:35:47.904874 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3678 11:35:47.908593 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3679 11:35:47.911487 ===================================
3680 11:35:47.915637 LPDDR4 DRAM CONFIGURATION
3681 11:35:47.917990 ===================================
3682 11:35:47.921561 EX_ROW_EN[0] = 0x10
3683 11:35:47.921993 EX_ROW_EN[1] = 0x0
3684 11:35:47.925015 LP4Y_EN = 0x0
3685 11:35:47.925541 WORK_FSP = 0x0
3686 11:35:47.928372 WL = 0x2
3687 11:35:47.928798 RL = 0x2
3688 11:35:47.930959 BL = 0x2
3689 11:35:47.931339 RPST = 0x0
3690 11:35:47.934692 RD_PRE = 0x0
3691 11:35:47.938233 WR_PRE = 0x1
3692 11:35:47.938609 WR_PST = 0x0
3693 11:35:47.941694 DBI_WR = 0x0
3694 11:35:47.942125 DBI_RD = 0x0
3695 11:35:47.944411 OTF = 0x1
3696 11:35:47.948240 ===================================
3697 11:35:47.950922 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3698 11:35:47.957089 nWR fixed to 30
3699 11:35:47.960203 [ModeRegInit_LP4] CH0 RK0
3700 11:35:47.960598 [ModeRegInit_LP4] CH0 RK1
3701 11:35:47.963456 [ModeRegInit_LP4] CH1 RK0
3702 11:35:47.966777 [ModeRegInit_LP4] CH1 RK1
3703 11:35:47.967168 match AC timing 16
3704 11:35:47.973212 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3705 11:35:47.976476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3706 11:35:47.980323 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3707 11:35:47.986851 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3708 11:35:47.989571 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3709 11:35:47.989955 ==
3710 11:35:47.993571 Dram Type= 6, Freq= 0, CH_0, rank 0
3711 11:35:47.996738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3712 11:35:47.997118 ==
3713 11:35:48.003319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3714 11:35:48.009521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3715 11:35:48.012668 [CA 0] Center 35 (5~66) winsize 62
3716 11:35:48.016527 [CA 1] Center 35 (5~66) winsize 62
3717 11:35:48.020061 [CA 2] Center 34 (4~65) winsize 62
3718 11:35:48.022988 [CA 3] Center 34 (4~65) winsize 62
3719 11:35:48.026960 [CA 4] Center 33 (3~64) winsize 62
3720 11:35:48.029568 [CA 5] Center 33 (3~64) winsize 62
3721 11:35:48.030019
3722 11:35:48.032334 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3723 11:35:48.032724
3724 11:35:48.035948 [CATrainingPosCal] consider 1 rank data
3725 11:35:48.039567 u2DelayCellTimex100 = 270/100 ps
3726 11:35:48.042353 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3727 11:35:48.045818 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3728 11:35:48.049119 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3729 11:35:48.052099 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3730 11:35:48.059148 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3731 11:35:48.062282 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3732 11:35:48.062710
3733 11:35:48.066045 CA PerBit enable=1, Macro0, CA PI delay=33
3734 11:35:48.066426
3735 11:35:48.068849 [CBTSetCACLKResult] CA Dly = 33
3736 11:35:48.069246 CS Dly: 4 (0~35)
3737 11:35:48.069548 ==
3738 11:35:48.072573 Dram Type= 6, Freq= 0, CH_0, rank 1
3739 11:35:48.080384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3740 11:35:48.080771 ==
3741 11:35:48.083024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3742 11:35:48.088794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3743 11:35:48.092503 [CA 0] Center 36 (6~66) winsize 61
3744 11:35:48.095344 [CA 1] Center 35 (5~66) winsize 62
3745 11:35:48.098531 [CA 2] Center 34 (4~65) winsize 62
3746 11:35:48.102116 [CA 3] Center 34 (4~65) winsize 62
3747 11:35:48.105135 [CA 4] Center 33 (3~64) winsize 62
3748 11:35:48.108764 [CA 5] Center 33 (3~64) winsize 62
3749 11:35:48.109143
3750 11:35:48.112001 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3751 11:35:48.112379
3752 11:35:48.115302 [CATrainingPosCal] consider 2 rank data
3753 11:35:48.118641 u2DelayCellTimex100 = 270/100 ps
3754 11:35:48.122249 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3755 11:35:48.125044 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3756 11:35:48.132179 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3757 11:35:48.135000 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3758 11:35:48.138367 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3759 11:35:48.141387 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3760 11:35:48.141549
3761 11:35:48.144421 CA PerBit enable=1, Macro0, CA PI delay=33
3762 11:35:48.144565
3763 11:35:48.147784 [CBTSetCACLKResult] CA Dly = 33
3764 11:35:48.147902 CS Dly: 4 (0~36)
3765 11:35:48.147980
3766 11:35:48.155065 ----->DramcWriteLeveling(PI) begin...
3767 11:35:48.155141 ==
3768 11:35:48.157591 Dram Type= 6, Freq= 0, CH_0, rank 0
3769 11:35:48.161682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3770 11:35:48.161757 ==
3771 11:35:48.164464 Write leveling (Byte 0): 31 => 31
3772 11:35:48.167926 Write leveling (Byte 1): 29 => 29
3773 11:35:48.170980 DramcWriteLeveling(PI) end<-----
3774 11:35:48.171053
3775 11:35:48.171110 ==
3776 11:35:48.174303 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 11:35:48.177298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 11:35:48.177373 ==
3779 11:35:48.180994 [Gating] SW mode calibration
3780 11:35:48.187490 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3781 11:35:48.194132 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3782 11:35:48.197924 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3783 11:35:48.200992 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3784 11:35:48.207909 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
3785 11:35:48.211012 0 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
3786 11:35:48.213964 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3787 11:35:48.220902 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 11:35:48.224190 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 11:35:48.227642 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 11:35:48.234058 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 11:35:48.237991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 11:35:48.241135 0 6 8 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
3793 11:35:48.247253 0 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3794 11:35:48.250983 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3795 11:35:48.254527 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 11:35:48.261274 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 11:35:48.264021 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 11:35:48.267451 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 11:35:48.273941 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 11:35:48.276893 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 11:35:48.280137 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3802 11:35:48.288280 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 11:35:48.290081 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 11:35:48.293376 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 11:35:48.300691 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 11:35:48.304049 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 11:35:48.306798 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 11:35:48.313792 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 11:35:48.316565 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 11:35:48.320012 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:35:48.326758 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:35:48.330245 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:35:48.333674 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:35:48.339813 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:35:48.343232 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 11:35:48.347275 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 11:35:48.352588 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3818 11:35:48.353003 Total UI for P1: 0, mck2ui 16
3819 11:35:48.356385 best dqsien dly found for B0: ( 0, 9, 10)
3820 11:35:48.363191 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 11:35:48.368075 Total UI for P1: 0, mck2ui 16
3822 11:35:48.369636 best dqsien dly found for B1: ( 0, 9, 12)
3823 11:35:48.372456 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3824 11:35:48.376574 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3825 11:35:48.376952
3826 11:35:48.379181 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3827 11:35:48.383249 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3828 11:35:48.386198 [Gating] SW calibration Done
3829 11:35:48.386584 ==
3830 11:35:48.389119 Dram Type= 6, Freq= 0, CH_0, rank 0
3831 11:35:48.393262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3832 11:35:48.395927 ==
3833 11:35:48.396307 RX Vref Scan: 0
3834 11:35:48.396592
3835 11:35:48.399206 RX Vref 0 -> 0, step: 1
3836 11:35:48.399576
3837 11:35:48.402337 RX Delay -230 -> 252, step: 16
3838 11:35:48.406354 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3839 11:35:48.409305 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3840 11:35:48.412744 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3841 11:35:48.415957 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3842 11:35:48.422884 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3843 11:35:48.425864 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3844 11:35:48.429033 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3845 11:35:48.432886 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3846 11:35:48.438944 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3847 11:35:48.442469 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3848 11:35:48.445782 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3849 11:35:48.449447 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3850 11:35:48.455636 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3851 11:35:48.459659 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3852 11:35:48.461862 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3853 11:35:48.465913 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3854 11:35:48.466368 ==
3855 11:35:48.469553 Dram Type= 6, Freq= 0, CH_0, rank 0
3856 11:35:48.475266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3857 11:35:48.475802 ==
3858 11:35:48.476237 DQS Delay:
3859 11:35:48.478263 DQS0 = 0, DQS1 = 0
3860 11:35:48.478719 DQM Delay:
3861 11:35:48.482105 DQM0 = 38, DQM1 = 33
3862 11:35:48.482545 DQ Delay:
3863 11:35:48.485179 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3864 11:35:48.488613 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3865 11:35:48.492167 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3866 11:35:48.496303 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3867 11:35:48.496750
3868 11:35:48.497076
3869 11:35:48.497400 ==
3870 11:35:48.498639 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 11:35:48.502035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 11:35:48.502549 ==
3873 11:35:48.502882
3874 11:35:48.503177
3875 11:35:48.505060 TX Vref Scan disable
3876 11:35:48.508639 == TX Byte 0 ==
3877 11:35:48.511974 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3878 11:35:48.514934 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3879 11:35:48.519071 == TX Byte 1 ==
3880 11:35:48.521861 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3881 11:35:48.525144 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3882 11:35:48.525622 ==
3883 11:35:48.528435 Dram Type= 6, Freq= 0, CH_0, rank 0
3884 11:35:48.535913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3885 11:35:48.536418 ==
3886 11:35:48.536743
3887 11:35:48.537044
3888 11:35:48.537369 TX Vref Scan disable
3889 11:35:48.539468 == TX Byte 0 ==
3890 11:35:48.542102 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3891 11:35:48.548661 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3892 11:35:48.549050 == TX Byte 1 ==
3893 11:35:48.551974 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3894 11:35:48.558880 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3895 11:35:48.559272
3896 11:35:48.559566 [DATLAT]
3897 11:35:48.559835 Freq=600, CH0 RK0
3898 11:35:48.560096
3899 11:35:48.561908 DATLAT Default: 0x9
3900 11:35:48.562289 0, 0xFFFF, sum = 0
3901 11:35:48.564947 1, 0xFFFF, sum = 0
3902 11:35:48.568934 2, 0xFFFF, sum = 0
3903 11:35:48.569463 3, 0xFFFF, sum = 0
3904 11:35:48.571851 4, 0xFFFF, sum = 0
3905 11:35:48.572273 5, 0xFFFF, sum = 0
3906 11:35:48.575236 6, 0xFFFF, sum = 0
3907 11:35:48.575765 7, 0x0, sum = 1
3908 11:35:48.576153 8, 0x0, sum = 2
3909 11:35:48.578147 9, 0x0, sum = 3
3910 11:35:48.578540 10, 0x0, sum = 4
3911 11:35:48.581591 best_step = 8
3912 11:35:48.582203
3913 11:35:48.582818 ==
3914 11:35:48.585607 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 11:35:48.588400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3916 11:35:48.588787 ==
3917 11:35:48.592166 RX Vref Scan: 1
3918 11:35:48.592634
3919 11:35:48.592933 RX Vref 0 -> 0, step: 1
3920 11:35:48.593209
3921 11:35:48.595111 RX Delay -195 -> 252, step: 8
3922 11:35:48.595491
3923 11:35:48.598258 Set Vref, RX VrefLevel [Byte0]: 47
3924 11:35:48.601128 [Byte1]: 52
3925 11:35:48.605738
3926 11:35:48.606395 Final RX Vref Byte 0 = 47 to rank0
3927 11:35:48.609069 Final RX Vref Byte 1 = 52 to rank0
3928 11:35:48.612062 Final RX Vref Byte 0 = 47 to rank1
3929 11:35:48.615559 Final RX Vref Byte 1 = 52 to rank1==
3930 11:35:48.618864 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 11:35:48.625343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3932 11:35:48.625733 ==
3933 11:35:48.626029 DQS Delay:
3934 11:35:48.630127 DQS0 = 0, DQS1 = 0
3935 11:35:48.630515 DQM Delay:
3936 11:35:48.630810 DQM0 = 41, DQM1 = 30
3937 11:35:48.632450 DQ Delay:
3938 11:35:48.636251 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =36
3939 11:35:48.639301 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
3940 11:35:48.641889 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3941 11:35:48.645416 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3942 11:35:48.645796
3943 11:35:48.646091
3944 11:35:48.652616 [DQSOSCAuto] RK0, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
3945 11:35:48.655903 CH0 RK0: MR19=808, MR18=6161
3946 11:35:48.662193 CH0_RK0: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
3947 11:35:48.662575
3948 11:35:48.665278 ----->DramcWriteLeveling(PI) begin...
3949 11:35:48.665672 ==
3950 11:35:48.668868 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 11:35:48.672587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3952 11:35:48.673015 ==
3953 11:35:48.675567 Write leveling (Byte 0): 29 => 29
3954 11:35:48.678842 Write leveling (Byte 1): 28 => 28
3955 11:35:48.681915 DramcWriteLeveling(PI) end<-----
3956 11:35:48.682413
3957 11:35:48.682722 ==
3958 11:35:48.685743 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 11:35:48.688270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3960 11:35:48.688656 ==
3961 11:35:48.691889 [Gating] SW mode calibration
3962 11:35:48.698408 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3963 11:35:48.704928 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3964 11:35:48.709834 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 11:35:48.715422 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3966 11:35:48.718376 0 5 8 | B1->B0 | 3232 3232 | 1 1 | (1 0) (1 1)
3967 11:35:48.721510 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
3968 11:35:48.728236 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 11:35:48.731827 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 11:35:48.735405 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 11:35:48.741885 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 11:35:48.745031 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 11:35:48.748291 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3974 11:35:48.755035 0 6 8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
3975 11:35:48.758152 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 11:35:48.761522 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 11:35:48.768136 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 11:35:48.771205 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 11:35:48.774319 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 11:35:48.781834 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 11:35:48.784370 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 11:35:48.788185 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3983 11:35:48.794476 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:35:48.798587 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:35:48.801126 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:35:48.808018 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:35:48.811532 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:35:48.813994 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:35:48.818126 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:35:48.824817 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:35:48.827760 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:35:48.831165 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:35:48.837856 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:35:48.840878 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:35:48.844292 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:35:48.850448 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:35:48.853772 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:35:48.857354 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:35:48.860897 Total UI for P1: 0, mck2ui 16
4000 11:35:48.863569 best dqsien dly found for B0: ( 0, 9, 6)
4001 11:35:48.867455 Total UI for P1: 0, mck2ui 16
4002 11:35:48.871158 best dqsien dly found for B1: ( 0, 9, 6)
4003 11:35:48.873671 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4004 11:35:48.877743 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4005 11:35:48.878235
4006 11:35:48.884485 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4007 11:35:48.887418 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4008 11:35:48.891240 [Gating] SW calibration Done
4009 11:35:48.891736 ==
4010 11:35:48.893427 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 11:35:48.897338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4012 11:35:48.897728 ==
4013 11:35:48.898028 RX Vref Scan: 0
4014 11:35:48.898303
4015 11:35:48.900902 RX Vref 0 -> 0, step: 1
4016 11:35:48.901325
4017 11:35:48.903710 RX Delay -230 -> 252, step: 16
4018 11:35:48.907461 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4019 11:35:48.910248 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4020 11:35:48.916977 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4021 11:35:48.920729 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4022 11:35:48.924491 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4023 11:35:48.927013 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4024 11:35:48.933416 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4025 11:35:48.937082 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4026 11:35:48.940615 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4027 11:35:48.944262 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4028 11:35:48.949845 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4029 11:35:48.953063 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4030 11:35:48.957084 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4031 11:35:48.960164 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4032 11:35:48.966869 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4033 11:35:48.969929 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4034 11:35:48.970352 ==
4035 11:35:48.972902 Dram Type= 6, Freq= 0, CH_0, rank 1
4036 11:35:48.976258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4037 11:35:48.976684 ==
4038 11:35:48.980496 DQS Delay:
4039 11:35:48.980991 DQS0 = 0, DQS1 = 0
4040 11:35:48.981482 DQM Delay:
4041 11:35:48.982807 DQM0 = 40, DQM1 = 33
4042 11:35:48.983224 DQ Delay:
4043 11:35:48.986440 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4044 11:35:48.989680 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4045 11:35:48.993096 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4046 11:35:48.996519 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4047 11:35:48.997009
4048 11:35:48.997404
4049 11:35:48.997711 ==
4050 11:35:49.000017 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 11:35:49.005712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 11:35:49.006172 ==
4053 11:35:49.006492
4054 11:35:49.006786
4055 11:35:49.007100 TX Vref Scan disable
4056 11:35:49.009380 == TX Byte 0 ==
4057 11:35:49.013719 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4058 11:35:49.019820 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4059 11:35:49.020311 == TX Byte 1 ==
4060 11:35:49.023240 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4061 11:35:49.029306 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4062 11:35:49.029804 ==
4063 11:35:49.032885 Dram Type= 6, Freq= 0, CH_0, rank 1
4064 11:35:49.036644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4065 11:35:49.037137 ==
4066 11:35:49.037525
4067 11:35:49.037827
4068 11:35:49.039506 TX Vref Scan disable
4069 11:35:49.043245 == TX Byte 0 ==
4070 11:35:49.046067 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4071 11:35:49.049462 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4072 11:35:49.053445 == TX Byte 1 ==
4073 11:35:49.056015 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4074 11:35:49.059215 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4075 11:35:49.059634
4076 11:35:49.059972 [DATLAT]
4077 11:35:49.062348 Freq=600, CH0 RK1
4078 11:35:49.062765
4079 11:35:49.066282 DATLAT Default: 0x8
4080 11:35:49.066775 0, 0xFFFF, sum = 0
4081 11:35:49.069197 1, 0xFFFF, sum = 0
4082 11:35:49.069684 2, 0xFFFF, sum = 0
4083 11:35:49.072235 3, 0xFFFF, sum = 0
4084 11:35:49.072596 4, 0xFFFF, sum = 0
4085 11:35:49.075836 5, 0xFFFF, sum = 0
4086 11:35:49.076258 6, 0xFFFF, sum = 0
4087 11:35:49.079812 7, 0x0, sum = 1
4088 11:35:49.080310 8, 0x0, sum = 2
4089 11:35:49.082515 9, 0x0, sum = 3
4090 11:35:49.082960 10, 0x0, sum = 4
4091 11:35:49.083296 best_step = 8
4092 11:35:49.083602
4093 11:35:49.085367 ==
4094 11:35:49.085784 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 11:35:49.092847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 11:35:49.093354 ==
4097 11:35:49.093689 RX Vref Scan: 0
4098 11:35:49.093991
4099 11:35:49.095600 RX Vref 0 -> 0, step: 1
4100 11:35:49.096014
4101 11:35:49.099096 RX Delay -195 -> 252, step: 8
4102 11:35:49.105634 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4103 11:35:49.109394 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4104 11:35:49.112151 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4105 11:35:49.115750 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4106 11:35:49.118526 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4107 11:35:49.125612 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4108 11:35:49.129286 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4109 11:35:49.132351 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4110 11:35:49.135867 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4111 11:35:49.142191 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4112 11:35:49.145584 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4113 11:35:49.148515 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4114 11:35:49.152598 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4115 11:35:49.159010 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4116 11:35:49.163131 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4117 11:35:49.165034 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4118 11:35:49.165587 ==
4119 11:35:49.168624 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 11:35:49.171937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 11:35:49.172460 ==
4122 11:35:49.174898 DQS Delay:
4123 11:35:49.175312 DQS0 = 0, DQS1 = 0
4124 11:35:49.178030 DQM Delay:
4125 11:35:49.178449 DQM0 = 41, DQM1 = 32
4126 11:35:49.178774 DQ Delay:
4127 11:35:49.181670 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4128 11:35:49.186241 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4129 11:35:49.188114 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4130 11:35:49.191890 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4131 11:35:49.192379
4132 11:35:49.192736
4133 11:35:49.201143 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4134 11:35:49.204901 CH0 RK1: MR19=808, MR18=6B6B
4135 11:35:49.211288 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4136 11:35:49.214610 [RxdqsGatingPostProcess] freq 600
4137 11:35:49.218385 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4138 11:35:49.221611 Pre-setting of DQS Precalculation
4139 11:35:49.227802 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4140 11:35:49.228291 ==
4141 11:35:49.231737 Dram Type= 6, Freq= 0, CH_1, rank 0
4142 11:35:49.235907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4143 11:35:49.236485 ==
4144 11:35:49.241005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4145 11:35:49.245348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4146 11:35:49.248468 [CA 0] Center 35 (5~66) winsize 62
4147 11:35:49.251665 [CA 1] Center 35 (5~65) winsize 61
4148 11:35:49.255569 [CA 2] Center 33 (3~64) winsize 62
4149 11:35:49.258250 [CA 3] Center 33 (3~64) winsize 62
4150 11:35:49.261645 [CA 4] Center 33 (2~64) winsize 63
4151 11:35:49.264470 [CA 5] Center 33 (2~64) winsize 63
4152 11:35:49.264952
4153 11:35:49.267902 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4154 11:35:49.268379
4155 11:35:49.271928 [CATrainingPosCal] consider 1 rank data
4156 11:35:49.274905 u2DelayCellTimex100 = 270/100 ps
4157 11:35:49.278334 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4158 11:35:49.284952 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4159 11:35:49.288750 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4160 11:35:49.291266 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4161 11:35:49.294715 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4162 11:35:49.298505 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4163 11:35:49.298922
4164 11:35:49.301221 CA PerBit enable=1, Macro0, CA PI delay=33
4165 11:35:49.301696
4166 11:35:49.304545 [CBTSetCACLKResult] CA Dly = 33
4167 11:35:49.308852 CS Dly: 4 (0~35)
4168 11:35:49.309379 ==
4169 11:35:49.311639 Dram Type= 6, Freq= 0, CH_1, rank 1
4170 11:35:49.314596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4171 11:35:49.315049 ==
4172 11:35:49.321284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4173 11:35:49.324428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4174 11:35:49.328829 [CA 0] Center 35 (5~66) winsize 62
4175 11:35:49.332925 [CA 1] Center 34 (4~65) winsize 62
4176 11:35:49.335459 [CA 2] Center 33 (3~64) winsize 62
4177 11:35:49.338948 [CA 3] Center 33 (3~64) winsize 62
4178 11:35:49.342200 [CA 4] Center 32 (2~63) winsize 62
4179 11:35:49.345485 [CA 5] Center 32 (2~63) winsize 62
4180 11:35:49.345978
4181 11:35:49.348590 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4182 11:35:49.349005
4183 11:35:49.351573 [CATrainingPosCal] consider 2 rank data
4184 11:35:49.355377 u2DelayCellTimex100 = 270/100 ps
4185 11:35:49.358059 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4186 11:35:49.365440 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4187 11:35:49.367987 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4188 11:35:49.371807 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4189 11:35:49.374804 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4190 11:35:49.377898 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4191 11:35:49.378315
4192 11:35:49.381755 CA PerBit enable=1, Macro0, CA PI delay=32
4193 11:35:49.382251
4194 11:35:49.385364 [CBTSetCACLKResult] CA Dly = 32
4195 11:35:49.385853 CS Dly: 4 (0~36)
4196 11:35:49.388422
4197 11:35:49.391796 ----->DramcWriteLeveling(PI) begin...
4198 11:35:49.392293 ==
4199 11:35:49.394756 Dram Type= 6, Freq= 0, CH_1, rank 0
4200 11:35:49.398874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4201 11:35:49.399298 ==
4202 11:35:49.401390 Write leveling (Byte 0): 26 => 26
4203 11:35:49.405873 Write leveling (Byte 1): 29 => 29
4204 11:35:49.409202 DramcWriteLeveling(PI) end<-----
4205 11:35:49.409712
4206 11:35:49.410042 ==
4207 11:35:49.411182 Dram Type= 6, Freq= 0, CH_1, rank 0
4208 11:35:49.414461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4209 11:35:49.415010 ==
4210 11:35:49.417930 [Gating] SW mode calibration
4211 11:35:49.424944 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 11:35:49.431691 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4213 11:35:49.434481 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 11:35:49.437952 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
4215 11:35:49.444542 0 5 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
4216 11:35:49.447741 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 11:35:49.451484 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 11:35:49.457477 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:35:49.461143 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:35:49.463955 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:35:49.471070 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:35:49.473894 0 6 4 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
4223 11:35:49.477699 0 6 8 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4224 11:35:49.484132 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 11:35:49.487695 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 11:35:49.491023 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:35:49.497206 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:35:49.500292 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:35:49.504839 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:35:49.510442 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4231 11:35:49.514054 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4232 11:35:49.517136 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:35:49.523522 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:35:49.527109 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:35:49.530465 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:35:49.534347 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:35:49.540256 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:35:49.543914 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:35:49.547450 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:35:49.553894 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:35:49.557381 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:35:49.560178 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:35:49.567167 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:35:49.571206 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:35:49.573410 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:35:49.580578 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:35:49.583439 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4248 11:35:49.586965 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:35:49.589400 Total UI for P1: 0, mck2ui 16
4250 11:35:49.593804 best dqsien dly found for B0: ( 0, 9, 8)
4251 11:35:49.596419 Total UI for P1: 0, mck2ui 16
4252 11:35:49.599663 best dqsien dly found for B1: ( 0, 9, 8)
4253 11:35:49.602868 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4254 11:35:49.606122 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4255 11:35:49.606403
4256 11:35:49.613151 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4257 11:35:49.617115 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4258 11:35:49.620158 [Gating] SW calibration Done
4259 11:35:49.620560 ==
4260 11:35:49.623212 Dram Type= 6, Freq= 0, CH_1, rank 0
4261 11:35:49.626304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4262 11:35:49.626692 ==
4263 11:35:49.626989 RX Vref Scan: 0
4264 11:35:49.627268
4265 11:35:49.629937 RX Vref 0 -> 0, step: 1
4266 11:35:49.630359
4267 11:35:49.632800 RX Delay -230 -> 252, step: 16
4268 11:35:49.636909 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4269 11:35:49.639458 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4270 11:35:49.647071 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4271 11:35:49.649202 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4272 11:35:49.652614 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4273 11:35:49.656605 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4274 11:35:49.662889 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4275 11:35:49.667913 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4276 11:35:49.669637 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4277 11:35:49.673361 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4278 11:35:49.679178 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4279 11:35:49.682861 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4280 11:35:49.686537 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4281 11:35:49.689129 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4282 11:35:49.696077 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4283 11:35:49.698998 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4284 11:35:49.699368 ==
4285 11:35:49.702276 Dram Type= 6, Freq= 0, CH_1, rank 0
4286 11:35:49.706415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4287 11:35:49.706888 ==
4288 11:35:49.709393 DQS Delay:
4289 11:35:49.709776 DQS0 = 0, DQS1 = 0
4290 11:35:49.710074 DQM Delay:
4291 11:35:49.712726 DQM0 = 39, DQM1 = 31
4292 11:35:49.713106 DQ Delay:
4293 11:35:49.715957 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4294 11:35:49.720114 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4295 11:35:49.723155 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4296 11:35:49.725794 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4297 11:35:49.726177
4298 11:35:49.726512
4299 11:35:49.726792 ==
4300 11:35:49.728722 Dram Type= 6, Freq= 0, CH_1, rank 0
4301 11:35:49.732025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4302 11:35:49.735899 ==
4303 11:35:49.736281
4304 11:35:49.736597
4305 11:35:49.737164 TX Vref Scan disable
4306 11:35:49.738905 == TX Byte 0 ==
4307 11:35:49.742165 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4308 11:35:49.748518 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4309 11:35:49.749064 == TX Byte 1 ==
4310 11:35:49.753462 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4311 11:35:49.758957 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4312 11:35:49.759311 ==
4313 11:35:49.762220 Dram Type= 6, Freq= 0, CH_1, rank 0
4314 11:35:49.765649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4315 11:35:49.765918 ==
4316 11:35:49.766147
4317 11:35:49.766363
4318 11:35:49.768654 TX Vref Scan disable
4319 11:35:49.772017 == TX Byte 0 ==
4320 11:35:49.774784 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4321 11:35:49.778703 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4322 11:35:49.781756 == TX Byte 1 ==
4323 11:35:49.785898 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4324 11:35:49.788023 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4325 11:35:49.788234
4326 11:35:49.788409 [DATLAT]
4327 11:35:49.791999 Freq=600, CH1 RK0
4328 11:35:49.792208
4329 11:35:49.795109 DATLAT Default: 0x9
4330 11:35:49.795300 0, 0xFFFF, sum = 0
4331 11:35:49.798722 1, 0xFFFF, sum = 0
4332 11:35:49.798915 2, 0xFFFF, sum = 0
4333 11:35:49.801402 3, 0xFFFF, sum = 0
4334 11:35:49.801595 4, 0xFFFF, sum = 0
4335 11:35:49.804869 5, 0xFFFF, sum = 0
4336 11:35:49.805328 6, 0xFFFF, sum = 0
4337 11:35:49.808201 7, 0x0, sum = 1
4338 11:35:49.808433 8, 0x0, sum = 2
4339 11:35:49.811587 9, 0x0, sum = 3
4340 11:35:49.812064 10, 0x0, sum = 4
4341 11:35:49.812494 best_step = 8
4342 11:35:49.812809
4343 11:35:49.814866 ==
4344 11:35:49.815400 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 11:35:49.822099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4346 11:35:49.822456 ==
4347 11:35:49.822739 RX Vref Scan: 1
4348 11:35:49.823009
4349 11:35:49.825804 RX Vref 0 -> 0, step: 1
4350 11:35:49.826220
4351 11:35:49.828455 RX Delay -195 -> 252, step: 8
4352 11:35:49.829045
4353 11:35:49.831598 Set Vref, RX VrefLevel [Byte0]: 51
4354 11:35:49.834892 [Byte1]: 50
4355 11:35:49.835428
4356 11:35:49.838497 Final RX Vref Byte 0 = 51 to rank0
4357 11:35:49.842137 Final RX Vref Byte 1 = 50 to rank0
4358 11:35:49.844785 Final RX Vref Byte 0 = 51 to rank1
4359 11:35:49.848261 Final RX Vref Byte 1 = 50 to rank1==
4360 11:35:49.852485 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 11:35:49.855475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 11:35:49.855855 ==
4363 11:35:49.858568 DQS Delay:
4364 11:35:49.859041 DQS0 = 0, DQS1 = 0
4365 11:35:49.861363 DQM Delay:
4366 11:35:49.861736 DQM0 = 37, DQM1 = 30
4367 11:35:49.862028 DQ Delay:
4368 11:35:49.865492 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4369 11:35:49.869785 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4370 11:35:49.871628 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4371 11:35:49.875918 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4372 11:35:49.876297
4373 11:35:49.876588
4374 11:35:49.884894 [DQSOSCAuto] RK0, (LSB)MR18= 0x8080, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4375 11:35:49.887948 CH1 RK0: MR19=808, MR18=8080
4376 11:35:49.894690 CH1_RK0: MR19=0x808, MR18=0x8080, DQSOSC=386, MR23=63, INC=176, DEC=117
4377 11:35:49.895146
4378 11:35:49.898985 ----->DramcWriteLeveling(PI) begin...
4379 11:35:49.899368 ==
4380 11:35:49.902732 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 11:35:49.904614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 11:35:49.904994 ==
4383 11:35:49.907913 Write leveling (Byte 0): 27 => 27
4384 11:35:49.911433 Write leveling (Byte 1): 27 => 27
4385 11:35:49.914704 DramcWriteLeveling(PI) end<-----
4386 11:35:49.915153
4387 11:35:49.915442 ==
4388 11:35:49.917828 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 11:35:49.921469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4390 11:35:49.921857 ==
4391 11:35:49.925094 [Gating] SW mode calibration
4392 11:35:49.931512 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4393 11:35:49.938355 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4394 11:35:49.940913 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4395 11:35:49.944452 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4396 11:35:49.952562 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4397 11:35:49.954886 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:35:49.957413 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:35:49.964053 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 11:35:49.967712 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 11:35:49.971114 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 11:35:49.977771 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 11:35:49.981139 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4404 11:35:49.983949 0 6 8 | B1->B0 | 3131 4242 | 0 1 | (0 0) (0 0)
4405 11:35:49.991159 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4406 11:35:49.994225 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:35:49.997337 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 11:35:50.004593 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 11:35:50.007427 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 11:35:50.011425 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 11:35:50.017288 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4412 11:35:50.021017 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4413 11:35:50.024914 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:35:50.031613 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:35:50.034435 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:35:50.037341 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:35:50.044247 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:35:50.047911 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:35:50.051232 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:35:50.057283 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:35:50.060525 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:35:50.063812 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:35:50.066929 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:35:50.073756 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:35:50.077460 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:35:50.080600 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:35:50.088284 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4428 11:35:50.089923 Total UI for P1: 0, mck2ui 16
4429 11:35:50.093871 best dqsien dly found for B0: ( 0, 9, 2)
4430 11:35:50.096976 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:35:50.100468 Total UI for P1: 0, mck2ui 16
4432 11:35:50.103610 best dqsien dly found for B1: ( 0, 9, 4)
4433 11:35:50.107497 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4434 11:35:50.110213 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4435 11:35:50.110633
4436 11:35:50.113222 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4437 11:35:50.116719 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4438 11:35:50.120106 [Gating] SW calibration Done
4439 11:35:50.120523 ==
4440 11:35:50.123722 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 11:35:50.130323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4442 11:35:50.130886 ==
4443 11:35:50.131328 RX Vref Scan: 0
4444 11:35:50.131729
4445 11:35:50.133194 RX Vref 0 -> 0, step: 1
4446 11:35:50.133724
4447 11:35:50.136540 RX Delay -230 -> 252, step: 16
4448 11:35:50.139575 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4449 11:35:50.143529 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4450 11:35:50.146565 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4451 11:35:50.153122 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4452 11:35:50.156224 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4453 11:35:50.159806 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4454 11:35:50.163166 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4455 11:35:50.169549 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4456 11:35:50.173637 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4457 11:35:50.176579 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4458 11:35:50.179444 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4459 11:35:50.183257 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4460 11:35:50.190675 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4461 11:35:50.193394 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4462 11:35:50.196735 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4463 11:35:50.202899 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4464 11:35:50.203439 ==
4465 11:35:50.206090 Dram Type= 6, Freq= 0, CH_1, rank 1
4466 11:35:50.209387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4467 11:35:50.209953 ==
4468 11:35:50.210375 DQS Delay:
4469 11:35:50.212968 DQS0 = 0, DQS1 = 0
4470 11:35:50.213605 DQM Delay:
4471 11:35:50.215887 DQM0 = 39, DQM1 = 34
4472 11:35:50.216316 DQ Delay:
4473 11:35:50.219121 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4474 11:35:50.222301 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4475 11:35:50.225836 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4476 11:35:50.229018 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4477 11:35:50.229503
4478 11:35:50.229927
4479 11:35:50.230356 ==
4480 11:35:50.232184 Dram Type= 6, Freq= 0, CH_1, rank 1
4481 11:35:50.235652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4482 11:35:50.236086 ==
4483 11:35:50.236510
4484 11:35:50.237133
4485 11:35:50.239119 TX Vref Scan disable
4486 11:35:50.242377 == TX Byte 0 ==
4487 11:35:50.247330 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4488 11:35:50.248748 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4489 11:35:50.253774 == TX Byte 1 ==
4490 11:35:50.255351 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4491 11:35:50.259235 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4492 11:35:50.259790 ==
4493 11:35:50.261838 Dram Type= 6, Freq= 0, CH_1, rank 1
4494 11:35:50.268856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4495 11:35:50.269431 ==
4496 11:35:50.269769
4497 11:35:50.270081
4498 11:35:50.270470 TX Vref Scan disable
4499 11:35:50.273971 == TX Byte 0 ==
4500 11:35:50.276923 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4501 11:35:50.283333 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4502 11:35:50.283850 == TX Byte 1 ==
4503 11:35:50.287188 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4504 11:35:50.294181 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4505 11:35:50.294674
4506 11:35:50.295105 [DATLAT]
4507 11:35:50.295506 Freq=600, CH1 RK1
4508 11:35:50.295948
4509 11:35:50.296700 DATLAT Default: 0x8
4510 11:35:50.297041 0, 0xFFFF, sum = 0
4511 11:35:50.299396 1, 0xFFFF, sum = 0
4512 11:35:50.302721 2, 0xFFFF, sum = 0
4513 11:35:50.303158 3, 0xFFFF, sum = 0
4514 11:35:50.305996 4, 0xFFFF, sum = 0
4515 11:35:50.306432 5, 0xFFFF, sum = 0
4516 11:35:50.309163 6, 0xFFFF, sum = 0
4517 11:35:50.309687 7, 0x0, sum = 1
4518 11:35:50.313042 8, 0x0, sum = 2
4519 11:35:50.313736 9, 0x0, sum = 3
4520 11:35:50.314175 10, 0x0, sum = 4
4521 11:35:50.315928 best_step = 8
4522 11:35:50.316365
4523 11:35:50.316706 ==
4524 11:35:50.319480 Dram Type= 6, Freq= 0, CH_1, rank 1
4525 11:35:50.322332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4526 11:35:50.322761 ==
4527 11:35:50.325716 RX Vref Scan: 0
4528 11:35:50.326132
4529 11:35:50.326456 RX Vref 0 -> 0, step: 1
4530 11:35:50.326754
4531 11:35:50.328843 RX Delay -195 -> 252, step: 8
4532 11:35:50.336733 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4533 11:35:50.340600 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4534 11:35:50.343366 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4535 11:35:50.347273 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4536 11:35:50.353752 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4537 11:35:50.356805 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4538 11:35:50.360748 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4539 11:35:50.363005 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4540 11:35:50.366630 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4541 11:35:50.374070 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4542 11:35:50.376623 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4543 11:35:50.379631 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4544 11:35:50.383555 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4545 11:35:50.389594 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4546 11:35:50.393516 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4547 11:35:50.396839 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4548 11:35:50.397470 ==
4549 11:35:50.399437 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 11:35:50.406258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 11:35:50.406778 ==
4552 11:35:50.407210 DQS Delay:
4553 11:35:50.407608 DQS0 = 0, DQS1 = 0
4554 11:35:50.410265 DQM Delay:
4555 11:35:50.410766 DQM0 = 36, DQM1 = 28
4556 11:35:50.413289 DQ Delay:
4557 11:35:50.416181 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4558 11:35:50.416609 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4559 11:35:50.419920 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4560 11:35:50.426479 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =36
4561 11:35:50.426903
4562 11:35:50.427401
4563 11:35:50.432788 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4564 11:35:50.436635 CH1 RK1: MR19=808, MR18=6565
4565 11:35:50.442881 CH1_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4566 11:35:50.446713 [RxdqsGatingPostProcess] freq 600
4567 11:35:50.450247 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4568 11:35:50.453473 Pre-setting of DQS Precalculation
4569 11:35:50.459825 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4570 11:35:50.465787 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4571 11:35:50.472477 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4572 11:35:50.472971
4573 11:35:50.473356
4574 11:35:50.476762 [Calibration Summary] 1200 Mbps
4575 11:35:50.477180 CH 0, Rank 0
4576 11:35:50.478830 SW Impedance : PASS
4577 11:35:50.482882 DUTY Scan : NO K
4578 11:35:50.483532 ZQ Calibration : PASS
4579 11:35:50.486680 Jitter Meter : NO K
4580 11:35:50.489793 CBT Training : PASS
4581 11:35:50.490211 Write leveling : PASS
4582 11:35:50.492576 RX DQS gating : PASS
4583 11:35:50.496100 RX DQ/DQS(RDDQC) : PASS
4584 11:35:50.496600 TX DQ/DQS : PASS
4585 11:35:50.499647 RX DATLAT : PASS
4586 11:35:50.500145 RX DQ/DQS(Engine): PASS
4587 11:35:50.503455 TX OE : NO K
4588 11:35:50.503960 All Pass.
4589 11:35:50.504285
4590 11:35:50.505441 CH 0, Rank 1
4591 11:35:50.509203 SW Impedance : PASS
4592 11:35:50.509747 DUTY Scan : NO K
4593 11:35:50.512411 ZQ Calibration : PASS
4594 11:35:50.512899 Jitter Meter : NO K
4595 11:35:50.516053 CBT Training : PASS
4596 11:35:50.518953 Write leveling : PASS
4597 11:35:50.519384 RX DQS gating : PASS
4598 11:35:50.522503 RX DQ/DQS(RDDQC) : PASS
4599 11:35:50.525463 TX DQ/DQS : PASS
4600 11:35:50.525960 RX DATLAT : PASS
4601 11:35:50.529466 RX DQ/DQS(Engine): PASS
4602 11:35:50.532286 TX OE : NO K
4603 11:35:50.532771 All Pass.
4604 11:35:50.533194
4605 11:35:50.533718 CH 1, Rank 0
4606 11:35:50.536178 SW Impedance : PASS
4607 11:35:50.539063 DUTY Scan : NO K
4608 11:35:50.539563 ZQ Calibration : PASS
4609 11:35:50.542372 Jitter Meter : NO K
4610 11:35:50.545598 CBT Training : PASS
4611 11:35:50.546091 Write leveling : PASS
4612 11:35:50.549354 RX DQS gating : PASS
4613 11:35:50.552180 RX DQ/DQS(RDDQC) : PASS
4614 11:35:50.552668 TX DQ/DQS : PASS
4615 11:35:50.555662 RX DATLAT : PASS
4616 11:35:50.558901 RX DQ/DQS(Engine): PASS
4617 11:35:50.559400 TX OE : NO K
4618 11:35:50.559735 All Pass.
4619 11:35:50.560031
4620 11:35:50.561815 CH 1, Rank 1
4621 11:35:50.566413 SW Impedance : PASS
4622 11:35:50.566906 DUTY Scan : NO K
4623 11:35:50.568761 ZQ Calibration : PASS
4624 11:35:50.569179 Jitter Meter : NO K
4625 11:35:50.571956 CBT Training : PASS
4626 11:35:50.574988 Write leveling : PASS
4627 11:35:50.575406 RX DQS gating : PASS
4628 11:35:50.578461 RX DQ/DQS(RDDQC) : PASS
4629 11:35:50.581884 TX DQ/DQS : PASS
4630 11:35:50.582302 RX DATLAT : PASS
4631 11:35:50.584888 RX DQ/DQS(Engine): PASS
4632 11:35:50.588002 TX OE : NO K
4633 11:35:50.588419 All Pass.
4634 11:35:50.588752
4635 11:35:50.591675 DramC Write-DBI off
4636 11:35:50.592174 PER_BANK_REFRESH: Hybrid Mode
4637 11:35:50.594685 TX_TRACKING: ON
4638 11:35:50.604750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4639 11:35:50.608355 [FAST_K] Save calibration result to emmc
4640 11:35:50.611844 dramc_set_vcore_voltage set vcore to 662500
4641 11:35:50.612342 Read voltage for 933, 3
4642 11:35:50.614958 Vio18 = 0
4643 11:35:50.615449 Vcore = 662500
4644 11:35:50.615777 Vdram = 0
4645 11:35:50.617865 Vddq = 0
4646 11:35:50.618281 Vmddr = 0
4647 11:35:50.621640 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4648 11:35:50.628174 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4649 11:35:50.631456 MEM_TYPE=3, freq_sel=17
4650 11:35:50.635334 sv_algorithm_assistance_LP4_1600
4651 11:35:50.638339 ============ PULL DRAM RESETB DOWN ============
4652 11:35:50.641728 ========== PULL DRAM RESETB DOWN end =========
4653 11:35:50.648549 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4654 11:35:50.651512 ===================================
4655 11:35:50.651932 LPDDR4 DRAM CONFIGURATION
4656 11:35:50.654900 ===================================
4657 11:35:50.658579 EX_ROW_EN[0] = 0x0
4658 11:35:50.659072 EX_ROW_EN[1] = 0x0
4659 11:35:50.661878 LP4Y_EN = 0x0
4660 11:35:50.662375 WORK_FSP = 0x0
4661 11:35:50.664764 WL = 0x3
4662 11:35:50.669684 RL = 0x3
4663 11:35:50.670239 BL = 0x2
4664 11:35:50.671484 RPST = 0x0
4665 11:35:50.671924 RD_PRE = 0x0
4666 11:35:50.674577 WR_PRE = 0x1
4667 11:35:50.675011 WR_PST = 0x0
4668 11:35:50.677486 DBI_WR = 0x0
4669 11:35:50.677919 DBI_RD = 0x0
4670 11:35:50.682007 OTF = 0x1
4671 11:35:50.684847 ===================================
4672 11:35:50.687858 ===================================
4673 11:35:50.688287 ANA top config
4674 11:35:50.692747 ===================================
4675 11:35:50.694419 DLL_ASYNC_EN = 0
4676 11:35:50.697826 ALL_SLAVE_EN = 1
4677 11:35:50.698288 NEW_RANK_MODE = 1
4678 11:35:50.701142 DLL_IDLE_MODE = 1
4679 11:35:50.704114 LP45_APHY_COMB_EN = 1
4680 11:35:50.707992 TX_ODT_DIS = 1
4681 11:35:50.710957 NEW_8X_MODE = 1
4682 11:35:50.714092 ===================================
4683 11:35:50.717817 ===================================
4684 11:35:50.718248 data_rate = 1866
4685 11:35:50.721278 CKR = 1
4686 11:35:50.725365 DQ_P2S_RATIO = 8
4687 11:35:50.728251 ===================================
4688 11:35:50.731412 CA_P2S_RATIO = 8
4689 11:35:50.734542 DQ_CA_OPEN = 0
4690 11:35:50.737346 DQ_SEMI_OPEN = 0
4691 11:35:50.737854 CA_SEMI_OPEN = 0
4692 11:35:50.741178 CA_FULL_RATE = 0
4693 11:35:50.745330 DQ_CKDIV4_EN = 1
4694 11:35:50.747096 CA_CKDIV4_EN = 1
4695 11:35:50.750661 CA_PREDIV_EN = 0
4696 11:35:50.753849 PH8_DLY = 0
4697 11:35:50.754362 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4698 11:35:50.757494 DQ_AAMCK_DIV = 4
4699 11:35:50.760478 CA_AAMCK_DIV = 4
4700 11:35:50.763472 CA_ADMCK_DIV = 4
4701 11:35:50.766970 DQ_TRACK_CA_EN = 0
4702 11:35:50.770188 CA_PICK = 933
4703 11:35:50.773776 CA_MCKIO = 933
4704 11:35:50.774194 MCKIO_SEMI = 0
4705 11:35:50.777387 PLL_FREQ = 3732
4706 11:35:50.779925 DQ_UI_PI_RATIO = 32
4707 11:35:50.783792 CA_UI_PI_RATIO = 0
4708 11:35:50.786620 ===================================
4709 11:35:50.789890 ===================================
4710 11:35:50.793645 memory_type:LPDDR4
4711 11:35:50.794065 GP_NUM : 10
4712 11:35:50.796719 SRAM_EN : 1
4713 11:35:50.800284 MD32_EN : 0
4714 11:35:50.803917 ===================================
4715 11:35:50.804421 [ANA_INIT] >>>>>>>>>>>>>>
4716 11:35:50.806508 <<<<<< [CONFIGURE PHASE]: ANA_TX
4717 11:35:50.810052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4718 11:35:50.813917 ===================================
4719 11:35:50.816893 data_rate = 1866,PCW = 0X8f00
4720 11:35:50.819838 ===================================
4721 11:35:50.823714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4722 11:35:50.830211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4723 11:35:50.832983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4724 11:35:50.840236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4725 11:35:50.842792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4726 11:35:50.846226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4727 11:35:50.846663 [ANA_INIT] flow start
4728 11:35:50.850389 [ANA_INIT] PLL >>>>>>>>
4729 11:35:50.852767 [ANA_INIT] PLL <<<<<<<<
4730 11:35:50.856698 [ANA_INIT] MIDPI >>>>>>>>
4731 11:35:50.857088 [ANA_INIT] MIDPI <<<<<<<<
4732 11:35:50.859610 [ANA_INIT] DLL >>>>>>>>
4733 11:35:50.863149 [ANA_INIT] flow end
4734 11:35:50.866114 ============ LP4 DIFF to SE enter ============
4735 11:35:50.869320 ============ LP4 DIFF to SE exit ============
4736 11:35:50.873144 [ANA_INIT] <<<<<<<<<<<<<
4737 11:35:50.876242 [Flow] Enable top DCM control >>>>>
4738 11:35:50.879448 [Flow] Enable top DCM control <<<<<
4739 11:35:50.882699 Enable DLL master slave shuffle
4740 11:35:50.886132 ==============================================================
4741 11:35:50.888943 Gating Mode config
4742 11:35:50.896617 ==============================================================
4743 11:35:50.897116 Config description:
4744 11:35:50.906577 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4745 11:35:50.912918 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4746 11:35:50.915947 SELPH_MODE 0: By rank 1: By Phase
4747 11:35:50.922713 ==============================================================
4748 11:35:50.925535 GAT_TRACK_EN = 1
4749 11:35:50.929827 RX_GATING_MODE = 2
4750 11:35:50.932444 RX_GATING_TRACK_MODE = 2
4751 11:35:50.936205 SELPH_MODE = 1
4752 11:35:50.939582 PICG_EARLY_EN = 1
4753 11:35:50.943080 VALID_LAT_VALUE = 1
4754 11:35:50.945691 ==============================================================
4755 11:35:50.949447 Enter into Gating configuration >>>>
4756 11:35:50.952924 Exit from Gating configuration <<<<
4757 11:35:50.956386 Enter into DVFS_PRE_config >>>>>
4758 11:35:50.969012 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4759 11:35:50.969527 Exit from DVFS_PRE_config <<<<<
4760 11:35:50.972415 Enter into PICG configuration >>>>
4761 11:35:50.975741 Exit from PICG configuration <<<<
4762 11:35:50.979084 [RX_INPUT] configuration >>>>>
4763 11:35:50.981546 [RX_INPUT] configuration <<<<<
4764 11:35:50.988438 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4765 11:35:50.991626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4766 11:35:50.998184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4767 11:35:51.005289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4768 11:35:51.012375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4769 11:35:51.019259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4770 11:35:51.021504 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4771 11:35:51.025272 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4772 11:35:51.028079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4773 11:35:51.035317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4774 11:35:51.038523 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4775 11:35:51.042071 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4776 11:35:51.044720 ===================================
4777 11:35:51.048007 LPDDR4 DRAM CONFIGURATION
4778 11:35:51.052670 ===================================
4779 11:35:51.054571 EX_ROW_EN[0] = 0x0
4780 11:35:51.055203 EX_ROW_EN[1] = 0x0
4781 11:35:51.058110 LP4Y_EN = 0x0
4782 11:35:51.058645 WORK_FSP = 0x0
4783 11:35:51.061337 WL = 0x3
4784 11:35:51.061843 RL = 0x3
4785 11:35:51.064612 BL = 0x2
4786 11:35:51.065110 RPST = 0x0
4787 11:35:51.068007 RD_PRE = 0x0
4788 11:35:51.068522 WR_PRE = 0x1
4789 11:35:51.071567 WR_PST = 0x0
4790 11:35:51.072070 DBI_WR = 0x0
4791 11:35:51.075050 DBI_RD = 0x0
4792 11:35:51.075534 OTF = 0x1
4793 11:35:51.078125 ===================================
4794 11:35:51.084656 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4795 11:35:51.087997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4796 11:35:51.092130 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4797 11:35:51.094198 ===================================
4798 11:35:51.097872 LPDDR4 DRAM CONFIGURATION
4799 11:35:51.101106 ===================================
4800 11:35:51.104011 EX_ROW_EN[0] = 0x10
4801 11:35:51.104442 EX_ROW_EN[1] = 0x0
4802 11:35:51.107499 LP4Y_EN = 0x0
4803 11:35:51.108009 WORK_FSP = 0x0
4804 11:35:51.110655 WL = 0x3
4805 11:35:51.111087 RL = 0x3
4806 11:35:51.114543 BL = 0x2
4807 11:35:51.115067 RPST = 0x0
4808 11:35:51.117744 RD_PRE = 0x0
4809 11:35:51.118192 WR_PRE = 0x1
4810 11:35:51.121278 WR_PST = 0x0
4811 11:35:51.121717 DBI_WR = 0x0
4812 11:35:51.124143 DBI_RD = 0x0
4813 11:35:51.124580 OTF = 0x1
4814 11:35:51.127952 ===================================
4815 11:35:51.134486 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4816 11:35:51.138950 nWR fixed to 30
4817 11:35:51.142418 [ModeRegInit_LP4] CH0 RK0
4818 11:35:51.142848 [ModeRegInit_LP4] CH0 RK1
4819 11:35:51.145893 [ModeRegInit_LP4] CH1 RK0
4820 11:35:51.148757 [ModeRegInit_LP4] CH1 RK1
4821 11:35:51.149327 match AC timing 8
4822 11:35:51.155827 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4823 11:35:51.159012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4824 11:35:51.163151 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4825 11:35:51.168689 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4826 11:35:51.171798 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4827 11:35:51.172184 ==
4828 11:35:51.175226 Dram Type= 6, Freq= 0, CH_0, rank 0
4829 11:35:51.178623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4830 11:35:51.179058 ==
4831 11:35:51.186169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4832 11:35:51.191814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4833 11:35:51.195012 [CA 0] Center 38 (8~69) winsize 62
4834 11:35:51.199823 [CA 1] Center 38 (8~69) winsize 62
4835 11:35:51.201635 [CA 2] Center 36 (5~67) winsize 63
4836 11:35:51.205282 [CA 3] Center 35 (5~66) winsize 62
4837 11:35:51.209032 [CA 4] Center 34 (4~65) winsize 62
4838 11:35:51.212338 [CA 5] Center 34 (4~65) winsize 62
4839 11:35:51.212856
4840 11:35:51.215045 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4841 11:35:51.215474
4842 11:35:51.218397 [CATrainingPosCal] consider 1 rank data
4843 11:35:51.221635 u2DelayCellTimex100 = 270/100 ps
4844 11:35:51.224892 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4845 11:35:51.228337 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4846 11:35:51.231597 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4847 11:35:51.235585 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4848 11:35:51.238985 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4849 11:35:51.245108 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4850 11:35:51.245632
4851 11:35:51.248293 CA PerBit enable=1, Macro0, CA PI delay=34
4852 11:35:51.248710
4853 11:35:51.251850 [CBTSetCACLKResult] CA Dly = 34
4854 11:35:51.252342 CS Dly: 7 (0~38)
4855 11:35:51.252687 ==
4856 11:35:51.255126 Dram Type= 6, Freq= 0, CH_0, rank 1
4857 11:35:51.257833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4858 11:35:51.261453 ==
4859 11:35:51.266149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4860 11:35:51.272925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4861 11:35:51.275212 [CA 0] Center 38 (8~69) winsize 62
4862 11:35:51.278063 [CA 1] Center 38 (7~69) winsize 63
4863 11:35:51.281489 [CA 2] Center 36 (5~67) winsize 63
4864 11:35:51.284701 [CA 3] Center 35 (5~66) winsize 62
4865 11:35:51.288455 [CA 4] Center 34 (4~65) winsize 62
4866 11:35:51.291621 [CA 5] Center 34 (4~65) winsize 62
4867 11:35:51.292046
4868 11:35:51.294876 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4869 11:35:51.295373
4870 11:35:51.298570 [CATrainingPosCal] consider 2 rank data
4871 11:35:51.302545 u2DelayCellTimex100 = 270/100 ps
4872 11:35:51.305121 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4873 11:35:51.308409 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4874 11:35:51.311178 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4875 11:35:51.314656 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4876 11:35:51.317690 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4877 11:35:51.324690 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4878 11:35:51.325415
4879 11:35:51.328090 CA PerBit enable=1, Macro0, CA PI delay=34
4880 11:35:51.328522
4881 11:35:51.330864 [CBTSetCACLKResult] CA Dly = 34
4882 11:35:51.331300 CS Dly: 7 (0~39)
4883 11:35:51.331728
4884 11:35:51.335208 ----->DramcWriteLeveling(PI) begin...
4885 11:35:51.335734 ==
4886 11:35:51.337806 Dram Type= 6, Freq= 0, CH_0, rank 0
4887 11:35:51.344478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4888 11:35:51.344972 ==
4889 11:35:51.347869 Write leveling (Byte 0): 26 => 26
4890 11:35:51.348305 Write leveling (Byte 1): 26 => 26
4891 11:35:51.351124 DramcWriteLeveling(PI) end<-----
4892 11:35:51.351633
4893 11:35:51.354486 ==
4894 11:35:51.354995 Dram Type= 6, Freq= 0, CH_0, rank 0
4895 11:35:51.360911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4896 11:35:51.361373 ==
4897 11:35:51.364883 [Gating] SW mode calibration
4898 11:35:51.371070 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4899 11:35:51.374920 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4900 11:35:51.381337 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4901 11:35:51.384383 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4902 11:35:51.387828 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4903 11:35:51.394640 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4904 11:35:51.397629 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 11:35:51.401300 0 10 20 | B1->B0 | 3434 3030 | 0 0 | (1 1) (1 1)
4906 11:35:51.407612 0 10 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
4907 11:35:51.411150 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4908 11:35:51.414392 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4909 11:35:51.421219 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4910 11:35:51.423971 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 11:35:51.427328 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 11:35:51.433807 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 11:35:51.437371 0 11 20 | B1->B0 | 2828 3131 | 0 0 | (1 1) (0 0)
4914 11:35:51.441216 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4915 11:35:51.447112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4916 11:35:51.450449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4917 11:35:51.454108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4918 11:35:51.460181 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 11:35:51.463663 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 11:35:51.467683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 11:35:51.473755 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4922 11:35:51.476912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4923 11:35:51.481056 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4924 11:35:51.487388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 11:35:51.490528 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 11:35:51.493999 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 11:35:51.497142 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 11:35:51.503494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 11:35:51.507354 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 11:35:51.510437 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 11:35:51.516727 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:35:51.520941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:35:51.523965 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:35:51.530485 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:35:51.533706 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:35:51.536654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 11:35:51.543284 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4938 11:35:51.547479 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 11:35:51.549567 Total UI for P1: 0, mck2ui 16
4940 11:35:51.554091 best dqsien dly found for B0: ( 0, 14, 20)
4941 11:35:51.557130 Total UI for P1: 0, mck2ui 16
4942 11:35:51.559418 best dqsien dly found for B1: ( 0, 14, 20)
4943 11:35:51.563575 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4944 11:35:51.566680 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4945 11:35:51.567175
4946 11:35:51.569827 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4947 11:35:51.573307 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4948 11:35:51.576940 [Gating] SW calibration Done
4949 11:35:51.577487 ==
4950 11:35:51.579523 Dram Type= 6, Freq= 0, CH_0, rank 0
4951 11:35:51.586027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4952 11:35:51.586513 ==
4953 11:35:51.586842 RX Vref Scan: 0
4954 11:35:51.587144
4955 11:35:51.589526 RX Vref 0 -> 0, step: 1
4956 11:35:51.589947
4957 11:35:51.592562 RX Delay -80 -> 252, step: 8
4958 11:35:51.596436 iDelay=208, Bit 0, Center 87 (-16 ~ 191) 208
4959 11:35:51.599701 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4960 11:35:51.602841 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4961 11:35:51.606249 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
4962 11:35:51.613038 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4963 11:35:51.616440 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4964 11:35:51.619043 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4965 11:35:51.622865 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4966 11:35:51.626144 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4967 11:35:51.629896 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4968 11:35:51.636478 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4969 11:35:51.639343 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4970 11:35:51.642752 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4971 11:35:51.645904 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4972 11:35:51.649925 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
4973 11:35:51.656474 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4974 11:35:51.656976 ==
4975 11:35:51.659783 Dram Type= 6, Freq= 0, CH_0, rank 0
4976 11:35:51.662774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4977 11:35:51.663198 ==
4978 11:35:51.663524 DQS Delay:
4979 11:35:51.665781 DQS0 = 0, DQS1 = 0
4980 11:35:51.666198 DQM Delay:
4981 11:35:51.669343 DQM0 = 95, DQM1 = 86
4982 11:35:51.669766 DQ Delay:
4983 11:35:51.672445 DQ0 =87, DQ1 =95, DQ2 =91, DQ3 =87
4984 11:35:51.675505 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
4985 11:35:51.678997 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
4986 11:35:51.681981 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
4987 11:35:51.682434
4988 11:35:51.682768
4989 11:35:51.683068 ==
4990 11:35:51.686836 Dram Type= 6, Freq= 0, CH_0, rank 0
4991 11:35:51.688702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4992 11:35:51.692234 ==
4993 11:35:51.692450
4994 11:35:51.692618
4995 11:35:51.692773 TX Vref Scan disable
4996 11:35:51.695517 == TX Byte 0 ==
4997 11:35:51.698768 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
4998 11:35:51.701898 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
4999 11:35:51.705648 == TX Byte 1 ==
5000 11:35:51.708751 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5001 11:35:51.712004 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5002 11:35:51.715401 ==
5003 11:35:51.715725 Dram Type= 6, Freq= 0, CH_0, rank 0
5004 11:35:51.721985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5005 11:35:51.722345 ==
5006 11:35:51.722579
5007 11:35:51.722774
5008 11:35:51.725148 TX Vref Scan disable
5009 11:35:51.725540 == TX Byte 0 ==
5010 11:35:51.732267 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5011 11:35:51.735642 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5012 11:35:51.736139 == TX Byte 1 ==
5013 11:35:51.742227 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5014 11:35:51.746509 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5015 11:35:51.746933
5016 11:35:51.747258 [DATLAT]
5017 11:35:51.748487 Freq=933, CH0 RK0
5018 11:35:51.748906
5019 11:35:51.749265 DATLAT Default: 0xd
5020 11:35:51.751896 0, 0xFFFF, sum = 0
5021 11:35:51.752393 1, 0xFFFF, sum = 0
5022 11:35:51.755357 2, 0xFFFF, sum = 0
5023 11:35:51.755860 3, 0xFFFF, sum = 0
5024 11:35:51.758138 4, 0xFFFF, sum = 0
5025 11:35:51.758563 5, 0xFFFF, sum = 0
5026 11:35:51.762898 6, 0xFFFF, sum = 0
5027 11:35:51.763409 7, 0xFFFF, sum = 0
5028 11:35:51.765004 8, 0xFFFF, sum = 0
5029 11:35:51.769304 9, 0xFFFF, sum = 0
5030 11:35:51.769809 10, 0x0, sum = 1
5031 11:35:51.770142 11, 0x0, sum = 2
5032 11:35:51.771342 12, 0x0, sum = 3
5033 11:35:51.771764 13, 0x0, sum = 4
5034 11:35:51.774778 best_step = 11
5035 11:35:51.775229
5036 11:35:51.775554 ==
5037 11:35:51.778975 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 11:35:51.781605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5039 11:35:51.782114 ==
5040 11:35:51.785966 RX Vref Scan: 1
5041 11:35:51.786463
5042 11:35:51.786791 RX Vref 0 -> 0, step: 1
5043 11:35:51.787090
5044 11:35:51.788279 RX Delay -69 -> 252, step: 4
5045 11:35:51.788697
5046 11:35:51.791452 Set Vref, RX VrefLevel [Byte0]: 47
5047 11:35:51.794856 [Byte1]: 52
5048 11:35:51.799184
5049 11:35:51.799699 Final RX Vref Byte 0 = 47 to rank0
5050 11:35:51.802901 Final RX Vref Byte 1 = 52 to rank0
5051 11:35:51.805487 Final RX Vref Byte 0 = 47 to rank1
5052 11:35:51.809477 Final RX Vref Byte 1 = 52 to rank1==
5053 11:35:51.812755 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 11:35:51.818729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5055 11:35:51.819215 ==
5056 11:35:51.819558 DQS Delay:
5057 11:35:51.819862 DQS0 = 0, DQS1 = 0
5058 11:35:51.822459 DQM Delay:
5059 11:35:51.822878 DQM0 = 97, DQM1 = 87
5060 11:35:51.825519 DQ Delay:
5061 11:35:51.829001 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5062 11:35:51.832953 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5063 11:35:51.835276 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5064 11:35:51.838955 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5065 11:35:51.839487
5066 11:35:51.839817
5067 11:35:51.845742 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5068 11:35:51.848820 CH0 RK0: MR19=505, MR18=2424
5069 11:35:51.856386 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5070 11:35:51.856886
5071 11:35:51.859102 ----->DramcWriteLeveling(PI) begin...
5072 11:35:51.859530 ==
5073 11:35:51.862287 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 11:35:51.865289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5075 11:35:51.865717 ==
5076 11:35:51.868540 Write leveling (Byte 0): 27 => 27
5077 11:35:51.872505 Write leveling (Byte 1): 27 => 27
5078 11:35:51.875546 DramcWriteLeveling(PI) end<-----
5079 11:35:51.876040
5080 11:35:51.876367 ==
5081 11:35:51.878634 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 11:35:51.882093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5083 11:35:51.885695 ==
5084 11:35:51.886190 [Gating] SW mode calibration
5085 11:35:51.891675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5086 11:35:51.898577 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5087 11:35:51.902211 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 11:35:51.909411 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 11:35:51.911766 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 11:35:51.915664 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 11:35:51.921409 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5092 11:35:51.925854 0 10 20 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 1)
5093 11:35:51.927932 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5094 11:35:51.934467 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 11:35:51.938744 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 11:35:51.941537 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 11:35:51.948123 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 11:35:51.951378 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 11:35:51.954787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 11:35:51.962101 0 11 20 | B1->B0 | 2b2b 3332 | 0 1 | (0 0) (0 0)
5101 11:35:51.964367 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5102 11:35:51.968129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 11:35:51.974464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 11:35:51.977671 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 11:35:51.980915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 11:35:51.988309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 11:35:51.991253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 11:35:51.994188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 11:35:52.000970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:35:52.004545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:35:52.007527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:35:52.014459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:35:52.017852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:35:52.020583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:35:52.027615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:35:52.031519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:35:52.034151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:35:52.040504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:35:52.044521 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:35:52.047205 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:35:52.054177 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:35:52.057140 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:35:52.060472 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:35:52.063929 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5125 11:35:52.070418 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:35:52.074718 Total UI for P1: 0, mck2ui 16
5127 11:35:52.077349 best dqsien dly found for B0: ( 0, 14, 22)
5128 11:35:52.079992 Total UI for P1: 0, mck2ui 16
5129 11:35:52.084531 best dqsien dly found for B1: ( 0, 14, 20)
5130 11:35:52.087813 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5131 11:35:52.090915 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5132 11:35:52.091335
5133 11:35:52.094387 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5134 11:35:52.097139 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5135 11:35:52.100478 [Gating] SW calibration Done
5136 11:35:52.100897 ==
5137 11:35:52.103600 Dram Type= 6, Freq= 0, CH_0, rank 1
5138 11:35:52.107318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5139 11:35:52.107803 ==
5140 11:35:52.110271 RX Vref Scan: 0
5141 11:35:52.110878
5142 11:35:52.113203 RX Vref 0 -> 0, step: 1
5143 11:35:52.113701
5144 11:35:52.114126 RX Delay -80 -> 252, step: 8
5145 11:35:52.119820 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5146 11:35:52.123272 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5147 11:35:52.126411 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5148 11:35:52.130138 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5149 11:35:52.133858 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5150 11:35:52.137365 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5151 11:35:52.143567 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5152 11:35:52.147481 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5153 11:35:52.149785 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5154 11:35:52.153291 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5155 11:35:52.156402 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5156 11:35:52.163729 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5157 11:35:52.167204 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5158 11:35:52.169959 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5159 11:35:52.174519 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5160 11:35:52.176578 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5161 11:35:52.176969 ==
5162 11:35:52.180644 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 11:35:52.186623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 11:35:52.187092 ==
5165 11:35:52.187389 DQS Delay:
5166 11:35:52.190177 DQS0 = 0, DQS1 = 0
5167 11:35:52.190676 DQM Delay:
5168 11:35:52.190999 DQM0 = 95, DQM1 = 86
5169 11:35:52.192939 DQ Delay:
5170 11:35:52.196643 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5171 11:35:52.199667 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5172 11:35:52.203419 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5173 11:35:52.206712 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5174 11:35:52.207209
5175 11:35:52.207542
5176 11:35:52.207841 ==
5177 11:35:52.209329 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 11:35:52.212955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5179 11:35:52.213558 ==
5180 11:35:52.213898
5181 11:35:52.214195
5182 11:35:52.216594 TX Vref Scan disable
5183 11:35:52.217087 == TX Byte 0 ==
5184 11:35:52.222500 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5185 11:35:52.226705 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5186 11:35:52.229562 == TX Byte 1 ==
5187 11:35:52.232819 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5188 11:35:52.235719 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5189 11:35:52.236259 ==
5190 11:35:52.239144 Dram Type= 6, Freq= 0, CH_0, rank 1
5191 11:35:52.242269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5192 11:35:52.242434 ==
5193 11:35:52.245816
5194 11:35:52.245980
5195 11:35:52.246173 TX Vref Scan disable
5196 11:35:52.249565 == TX Byte 0 ==
5197 11:35:52.252323 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5198 11:35:52.258876 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5199 11:35:52.259077 == TX Byte 1 ==
5200 11:35:52.262508 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5201 11:35:52.269542 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5202 11:35:52.269993
5203 11:35:52.270295 [DATLAT]
5204 11:35:52.270570 Freq=933, CH0 RK1
5205 11:35:52.270836
5206 11:35:52.272464 DATLAT Default: 0xb
5207 11:35:52.272843 0, 0xFFFF, sum = 0
5208 11:35:52.275777 1, 0xFFFF, sum = 0
5209 11:35:52.276163 2, 0xFFFF, sum = 0
5210 11:35:52.279505 3, 0xFFFF, sum = 0
5211 11:35:52.279934 4, 0xFFFF, sum = 0
5212 11:35:52.282669 5, 0xFFFF, sum = 0
5213 11:35:52.286130 6, 0xFFFF, sum = 0
5214 11:35:52.286557 7, 0xFFFF, sum = 0
5215 11:35:52.289328 8, 0xFFFF, sum = 0
5216 11:35:52.289756 9, 0xFFFF, sum = 0
5217 11:35:52.292130 10, 0x0, sum = 1
5218 11:35:52.292555 11, 0x0, sum = 2
5219 11:35:52.292901 12, 0x0, sum = 3
5220 11:35:52.296199 13, 0x0, sum = 4
5221 11:35:52.296626 best_step = 11
5222 11:35:52.296953
5223 11:35:52.299018 ==
5224 11:35:52.302420 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 11:35:52.306502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 11:35:52.306926 ==
5227 11:35:52.307338 RX Vref Scan: 0
5228 11:35:52.307650
5229 11:35:52.309743 RX Vref 0 -> 0, step: 1
5230 11:35:52.310162
5231 11:35:52.312614 RX Delay -69 -> 252, step: 4
5232 11:35:52.315632 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5233 11:35:52.322528 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5234 11:35:52.325720 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5235 11:35:52.329108 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5236 11:35:52.332043 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5237 11:35:52.335107 iDelay=199, Bit 5, Center 90 (-1 ~ 182) 184
5238 11:35:52.338694 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5239 11:35:52.345346 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5240 11:35:52.348581 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5241 11:35:52.351786 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5242 11:35:52.355348 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5243 11:35:52.358801 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5244 11:35:52.364889 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5245 11:35:52.368108 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5246 11:35:52.371642 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5247 11:35:52.374630 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5248 11:35:52.375042 ==
5249 11:35:52.378543 Dram Type= 6, Freq= 0, CH_0, rank 1
5250 11:35:52.384955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5251 11:35:52.385384 ==
5252 11:35:52.385686 DQS Delay:
5253 11:35:52.385960 DQS0 = 0, DQS1 = 0
5254 11:35:52.388519 DQM Delay:
5255 11:35:52.388896 DQM0 = 97, DQM1 = 86
5256 11:35:52.391516 DQ Delay:
5257 11:35:52.394902 DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =92
5258 11:35:52.398555 DQ4 =102, DQ5 =90, DQ6 =102, DQ7 =106
5259 11:35:52.401424 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5260 11:35:52.404994 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5261 11:35:52.405411
5262 11:35:52.405705
5263 11:35:52.411293 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5264 11:35:52.414643 CH0 RK1: MR19=505, MR18=2C2C
5265 11:35:52.421339 CH0_RK1: MR19=0x505, MR18=0x2C2C, DQSOSC=408, MR23=63, INC=65, DEC=43
5266 11:35:52.424487 [RxdqsGatingPostProcess] freq 933
5267 11:35:52.427384 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5268 11:35:52.431198 Pre-setting of DQS Precalculation
5269 11:35:52.437766 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5270 11:35:52.437841 ==
5271 11:35:52.441120 Dram Type= 6, Freq= 0, CH_1, rank 0
5272 11:35:52.443987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5273 11:35:52.444062 ==
5274 11:35:52.450589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5275 11:35:52.456982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5276 11:35:52.460934 [CA 0] Center 37 (7~68) winsize 62
5277 11:35:52.464130 [CA 1] Center 37 (6~68) winsize 63
5278 11:35:52.467511 [CA 2] Center 34 (4~65) winsize 62
5279 11:35:52.470421 [CA 3] Center 34 (4~65) winsize 62
5280 11:35:52.474125 [CA 4] Center 32 (2~63) winsize 62
5281 11:35:52.477146 [CA 5] Center 33 (2~64) winsize 63
5282 11:35:52.477221
5283 11:35:52.480564 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5284 11:35:52.480638
5285 11:35:52.483638 [CATrainingPosCal] consider 1 rank data
5286 11:35:52.488066 u2DelayCellTimex100 = 270/100 ps
5287 11:35:52.490684 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5288 11:35:52.493698 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5289 11:35:52.497567 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5290 11:35:52.500313 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5291 11:35:52.503525 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5292 11:35:52.506965 CA5 delay=33 (2~64),Diff = 1 PI (6 cell)
5293 11:35:52.507040
5294 11:35:52.513300 CA PerBit enable=1, Macro0, CA PI delay=32
5295 11:35:52.513397
5296 11:35:52.516712 [CBTSetCACLKResult] CA Dly = 32
5297 11:35:52.516785 CS Dly: 5 (0~36)
5298 11:35:52.516843 ==
5299 11:35:52.519876 Dram Type= 6, Freq= 0, CH_1, rank 1
5300 11:35:52.523152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5301 11:35:52.523226 ==
5302 11:35:52.530114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5303 11:35:52.536629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5304 11:35:52.540231 [CA 0] Center 37 (6~68) winsize 63
5305 11:35:52.543238 [CA 1] Center 37 (6~68) winsize 63
5306 11:35:52.546396 [CA 2] Center 34 (4~65) winsize 62
5307 11:35:52.549687 [CA 3] Center 33 (3~64) winsize 62
5308 11:35:52.553088 [CA 4] Center 32 (2~63) winsize 62
5309 11:35:52.556591 [CA 5] Center 32 (2~63) winsize 62
5310 11:35:52.556688
5311 11:35:52.559596 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5312 11:35:52.559699
5313 11:35:52.562790 [CATrainingPosCal] consider 2 rank data
5314 11:35:52.566791 u2DelayCellTimex100 = 270/100 ps
5315 11:35:52.569433 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5316 11:35:52.572617 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5317 11:35:52.576802 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5318 11:35:52.579011 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5319 11:35:52.585623 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5320 11:35:52.589141 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5321 11:35:52.589233
5322 11:35:52.592619 CA PerBit enable=1, Macro0, CA PI delay=32
5323 11:35:52.592703
5324 11:35:52.595820 [CBTSetCACLKResult] CA Dly = 32
5325 11:35:52.595882 CS Dly: 5 (0~37)
5326 11:35:52.595933
5327 11:35:52.599773 ----->DramcWriteLeveling(PI) begin...
5328 11:35:52.599865 ==
5329 11:35:52.602406 Dram Type= 6, Freq= 0, CH_1, rank 0
5330 11:35:52.608826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 11:35:52.608902 ==
5332 11:35:52.612766 Write leveling (Byte 0): 25 => 25
5333 11:35:52.615427 Write leveling (Byte 1): 25 => 25
5334 11:35:52.615489 DramcWriteLeveling(PI) end<-----
5335 11:35:52.618976
5336 11:35:52.619090 ==
5337 11:35:52.622433 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 11:35:52.626219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 11:35:52.626285 ==
5340 11:35:52.629418 [Gating] SW mode calibration
5341 11:35:52.635095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 11:35:52.638676 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5343 11:35:52.645119 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 11:35:52.648455 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 11:35:52.651951 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 11:35:52.658428 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:35:52.662326 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5348 11:35:52.665315 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5349 11:35:52.672198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 11:35:52.675442 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 11:35:52.678490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 11:35:52.685330 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 11:35:52.688262 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:35:52.692243 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:35:52.698644 0 11 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
5356 11:35:52.702145 0 11 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
5357 11:35:52.704669 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5358 11:35:52.711889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 11:35:52.714666 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 11:35:52.718290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 11:35:52.725137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:35:52.728347 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:35:52.731370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5364 11:35:52.738061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 11:35:52.741149 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:35:52.744557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:35:52.750910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:35:52.754280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:35:52.757919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:35:52.764732 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:35:52.767401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:35:52.770753 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:35:52.777589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:35:52.780852 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:35:52.785163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:35:52.790862 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:35:52.793933 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:35:52.797589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:35:52.804222 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:35:52.808380 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 11:35:52.810830 Total UI for P1: 0, mck2ui 16
5382 11:35:52.814188 best dqsien dly found for B0: ( 0, 14, 18)
5383 11:35:52.817449 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:35:52.820587 Total UI for P1: 0, mck2ui 16
5385 11:35:52.824075 best dqsien dly found for B1: ( 0, 14, 20)
5386 11:35:52.827510 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5387 11:35:52.830407 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5388 11:35:52.830494
5389 11:35:52.837176 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5390 11:35:52.840740 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5391 11:35:52.843927 [Gating] SW calibration Done
5392 11:35:52.844015 ==
5393 11:35:52.847131 Dram Type= 6, Freq= 0, CH_1, rank 0
5394 11:35:52.850184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5395 11:35:52.850248 ==
5396 11:35:52.850301 RX Vref Scan: 0
5397 11:35:52.850366
5398 11:35:52.853768 RX Vref 0 -> 0, step: 1
5399 11:35:52.853828
5400 11:35:52.857451 RX Delay -80 -> 252, step: 8
5401 11:35:52.860159 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5402 11:35:52.863467 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5403 11:35:52.870023 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5404 11:35:52.873459 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5405 11:35:52.877707 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5406 11:35:52.880196 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5407 11:35:52.883350 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5408 11:35:52.886734 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5409 11:35:52.890528 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5410 11:35:52.897066 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5411 11:35:52.900004 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5412 11:35:52.903506 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5413 11:35:52.906691 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5414 11:35:52.909890 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5415 11:35:52.916726 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5416 11:35:52.920311 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5417 11:35:52.920386 ==
5418 11:35:52.923407 Dram Type= 6, Freq= 0, CH_1, rank 0
5419 11:35:52.926635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5420 11:35:52.926709 ==
5421 11:35:52.930756 DQS Delay:
5422 11:35:52.930830 DQS0 = 0, DQS1 = 0
5423 11:35:52.930888 DQM Delay:
5424 11:35:52.933175 DQM0 = 95, DQM1 = 86
5425 11:35:52.933255 DQ Delay:
5426 11:35:52.936564 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5427 11:35:52.939688 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5428 11:35:52.943260 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5429 11:35:52.946650 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5430 11:35:52.946724
5431 11:35:52.946780
5432 11:35:52.946832 ==
5433 11:35:52.949812 Dram Type= 6, Freq= 0, CH_1, rank 0
5434 11:35:52.956306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5435 11:35:52.956380 ==
5436 11:35:52.956437
5437 11:35:52.956489
5438 11:35:52.956538 TX Vref Scan disable
5439 11:35:52.959666 == TX Byte 0 ==
5440 11:35:52.963546 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5441 11:35:52.966742 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5442 11:35:52.970207 == TX Byte 1 ==
5443 11:35:52.973109 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5444 11:35:52.979870 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5445 11:35:52.979944 ==
5446 11:35:52.983113 Dram Type= 6, Freq= 0, CH_1, rank 0
5447 11:35:52.986613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5448 11:35:52.986687 ==
5449 11:35:52.986744
5450 11:35:52.986796
5451 11:35:52.990266 TX Vref Scan disable
5452 11:35:52.990340 == TX Byte 0 ==
5453 11:35:52.996577 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5454 11:35:53.000241 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5455 11:35:53.000316 == TX Byte 1 ==
5456 11:35:53.006468 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5457 11:35:53.009515 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5458 11:35:53.009593
5459 11:35:53.009650 [DATLAT]
5460 11:35:53.012694 Freq=933, CH1 RK0
5461 11:35:53.012768
5462 11:35:53.012825 DATLAT Default: 0xd
5463 11:35:53.016445 0, 0xFFFF, sum = 0
5464 11:35:53.016520 1, 0xFFFF, sum = 0
5465 11:35:53.019569 2, 0xFFFF, sum = 0
5466 11:35:53.019644 3, 0xFFFF, sum = 0
5467 11:35:53.022591 4, 0xFFFF, sum = 0
5468 11:35:53.026267 5, 0xFFFF, sum = 0
5469 11:35:53.026342 6, 0xFFFF, sum = 0
5470 11:35:53.029499 7, 0xFFFF, sum = 0
5471 11:35:53.029579 8, 0xFFFF, sum = 0
5472 11:35:53.032959 9, 0xFFFF, sum = 0
5473 11:35:53.033034 10, 0x0, sum = 1
5474 11:35:53.036522 11, 0x0, sum = 2
5475 11:35:53.036597 12, 0x0, sum = 3
5476 11:35:53.036655 13, 0x0, sum = 4
5477 11:35:53.039523 best_step = 11
5478 11:35:53.039597
5479 11:35:53.039653 ==
5480 11:35:53.043271 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 11:35:53.045877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 11:35:53.045952 ==
5483 11:35:53.049389 RX Vref Scan: 1
5484 11:35:53.049463
5485 11:35:53.052983 RX Vref 0 -> 0, step: 1
5486 11:35:53.053055
5487 11:35:53.053112 RX Delay -69 -> 252, step: 4
5488 11:35:53.053165
5489 11:35:53.055644 Set Vref, RX VrefLevel [Byte0]: 51
5490 11:35:53.059292 [Byte1]: 50
5491 11:35:53.063968
5492 11:35:53.064041 Final RX Vref Byte 0 = 51 to rank0
5493 11:35:53.067521 Final RX Vref Byte 1 = 50 to rank0
5494 11:35:53.070331 Final RX Vref Byte 0 = 51 to rank1
5495 11:35:53.073720 Final RX Vref Byte 1 = 50 to rank1==
5496 11:35:53.077213 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 11:35:53.084170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 11:35:53.084244 ==
5499 11:35:53.084302 DQS Delay:
5500 11:35:53.084354 DQS0 = 0, DQS1 = 0
5501 11:35:53.086820 DQM Delay:
5502 11:35:53.086893 DQM0 = 94, DQM1 = 88
5503 11:35:53.090265 DQ Delay:
5504 11:35:53.093516 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
5505 11:35:53.097213 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5506 11:35:53.100468 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5507 11:35:53.103527 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5508 11:35:53.103601
5509 11:35:53.103657
5510 11:35:53.110530 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5511 11:35:53.113538 CH1 RK0: MR19=505, MR18=3333
5512 11:35:53.120361 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5513 11:35:53.120436
5514 11:35:53.123817 ----->DramcWriteLeveling(PI) begin...
5515 11:35:53.123892 ==
5516 11:35:53.127803 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 11:35:53.130550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5518 11:35:53.130628 ==
5519 11:35:53.133188 Write leveling (Byte 0): 27 => 27
5520 11:35:53.136895 Write leveling (Byte 1): 21 => 21
5521 11:35:53.139745 DramcWriteLeveling(PI) end<-----
5522 11:35:53.139820
5523 11:35:53.139877 ==
5524 11:35:53.143464 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 11:35:53.146912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 11:35:53.146988 ==
5527 11:35:53.149898 [Gating] SW mode calibration
5528 11:35:53.156470 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5529 11:35:53.163119 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5530 11:35:53.166466 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 11:35:53.173259 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 11:35:53.176793 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5533 11:35:53.179697 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5534 11:35:53.187218 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
5535 11:35:53.190206 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5536 11:35:53.193253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5537 11:35:53.199603 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 11:35:53.203467 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 11:35:53.206341 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 11:35:53.212861 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 11:35:53.216058 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 11:35:53.219116 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5543 11:35:53.226996 0 11 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5544 11:35:53.229697 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5545 11:35:53.233055 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 11:35:53.239812 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 11:35:53.242731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 11:35:53.245978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 11:35:53.249101 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 11:35:53.255772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5551 11:35:53.259142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 11:35:53.262818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5553 11:35:53.269747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 11:35:53.272470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 11:35:53.276228 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 11:35:53.283019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 11:35:53.286086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 11:35:53.288943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 11:35:53.295484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 11:35:53.299229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 11:35:53.302310 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:35:53.308570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:35:53.312745 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:35:53.315338 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:35:53.322729 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:35:53.325218 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5567 11:35:53.328634 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5568 11:35:53.335589 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 11:35:53.338979 Total UI for P1: 0, mck2ui 16
5570 11:35:53.341963 best dqsien dly found for B0: ( 0, 14, 18)
5571 11:35:53.345884 Total UI for P1: 0, mck2ui 16
5572 11:35:53.348372 best dqsien dly found for B1: ( 0, 14, 18)
5573 11:35:53.351612 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5574 11:35:53.355382 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5575 11:35:53.355457
5576 11:35:53.358183 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5577 11:35:53.361433 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5578 11:35:53.365065 [Gating] SW calibration Done
5579 11:35:53.365138 ==
5580 11:35:53.369357 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 11:35:53.371461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5582 11:35:53.371536 ==
5583 11:35:53.375047 RX Vref Scan: 0
5584 11:35:53.375121
5585 11:35:53.378344 RX Vref 0 -> 0, step: 1
5586 11:35:53.378418
5587 11:35:53.378475 RX Delay -80 -> 252, step: 8
5588 11:35:53.385159 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5589 11:35:53.387991 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5590 11:35:53.392324 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5591 11:35:53.394729 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5592 11:35:53.398546 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5593 11:35:53.401547 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5594 11:35:53.408465 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5595 11:35:53.411841 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5596 11:35:53.414804 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5597 11:35:53.418407 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5598 11:35:53.421414 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5599 11:35:53.427874 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5600 11:35:53.431938 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5601 11:35:53.434534 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5602 11:35:53.438282 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5603 11:35:53.442307 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5604 11:35:53.442382 ==
5605 11:35:53.444672 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 11:35:53.451270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 11:35:53.451345 ==
5608 11:35:53.451404 DQS Delay:
5609 11:35:53.454194 DQS0 = 0, DQS1 = 0
5610 11:35:53.454268 DQM Delay:
5611 11:35:53.454326 DQM0 = 94, DQM1 = 86
5612 11:35:53.458151 DQ Delay:
5613 11:35:53.461337 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =87
5614 11:35:53.464233 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5615 11:35:53.467942 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5616 11:35:53.471271 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5617 11:35:53.471345
5618 11:35:53.471402
5619 11:35:53.471455 ==
5620 11:35:53.474569 Dram Type= 6, Freq= 0, CH_1, rank 1
5621 11:35:53.477499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5622 11:35:53.477574 ==
5623 11:35:53.477632
5624 11:35:53.477686
5625 11:35:53.481473 TX Vref Scan disable
5626 11:35:53.484285 == TX Byte 0 ==
5627 11:35:53.487611 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5628 11:35:53.490503 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5629 11:35:53.493966 == TX Byte 1 ==
5630 11:35:53.497969 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5631 11:35:53.500693 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5632 11:35:53.500768 ==
5633 11:35:53.504160 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 11:35:53.507196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 11:35:53.510413 ==
5636 11:35:53.510487
5637 11:35:53.510544
5638 11:35:53.510597 TX Vref Scan disable
5639 11:35:53.514523 == TX Byte 0 ==
5640 11:35:53.517709 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5641 11:35:53.523904 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5642 11:35:53.523979 == TX Byte 1 ==
5643 11:35:53.528620 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5644 11:35:53.534794 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5645 11:35:53.534869
5646 11:35:53.534927 [DATLAT]
5647 11:35:53.534980 Freq=933, CH1 RK1
5648 11:35:53.535032
5649 11:35:53.538059 DATLAT Default: 0xb
5650 11:35:53.538133 0, 0xFFFF, sum = 0
5651 11:35:53.540830 1, 0xFFFF, sum = 0
5652 11:35:53.540906 2, 0xFFFF, sum = 0
5653 11:35:53.545218 3, 0xFFFF, sum = 0
5654 11:35:53.547725 4, 0xFFFF, sum = 0
5655 11:35:53.547812 5, 0xFFFF, sum = 0
5656 11:35:53.550935 6, 0xFFFF, sum = 0
5657 11:35:53.551010 7, 0xFFFF, sum = 0
5658 11:35:53.553861 8, 0xFFFF, sum = 0
5659 11:35:53.553937 9, 0xFFFF, sum = 0
5660 11:35:53.557243 10, 0x0, sum = 1
5661 11:35:53.557318 11, 0x0, sum = 2
5662 11:35:53.560889 12, 0x0, sum = 3
5663 11:35:53.560964 13, 0x0, sum = 4
5664 11:35:53.561024 best_step = 11
5665 11:35:53.561088
5666 11:35:53.563920 ==
5667 11:35:53.567318 Dram Type= 6, Freq= 0, CH_1, rank 1
5668 11:35:53.571535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5669 11:35:53.571610 ==
5670 11:35:53.571667 RX Vref Scan: 0
5671 11:35:53.571721
5672 11:35:53.573839 RX Vref 0 -> 0, step: 1
5673 11:35:53.573913
5674 11:35:53.576988 RX Delay -77 -> 252, step: 4
5675 11:35:53.584000 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5676 11:35:53.586971 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5677 11:35:53.590499 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5678 11:35:53.593732 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5679 11:35:53.597099 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5680 11:35:53.600757 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5681 11:35:53.607266 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5682 11:35:53.611348 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5683 11:35:53.613812 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5684 11:35:53.616677 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5685 11:35:53.620107 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5686 11:35:53.626793 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5687 11:35:53.630206 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5688 11:35:53.633463 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5689 11:35:53.636886 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5690 11:35:53.639811 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5691 11:35:53.639885 ==
5692 11:35:53.643270 Dram Type= 6, Freq= 0, CH_1, rank 1
5693 11:35:53.649987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5694 11:35:53.650062 ==
5695 11:35:53.650120 DQS Delay:
5696 11:35:53.650173 DQS0 = 0, DQS1 = 0
5697 11:35:53.653743 DQM Delay:
5698 11:35:53.653817 DQM0 = 96, DQM1 = 87
5699 11:35:53.657856 DQ Delay:
5700 11:35:53.659916 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5701 11:35:53.663508 DQ4 =98, DQ5 =108, DQ6 =104, DQ7 =94
5702 11:35:53.663583 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =78
5703 11:35:53.670186 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5704 11:35:53.670261
5705 11:35:53.670318
5706 11:35:53.677467 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5707 11:35:53.680006 CH1 RK1: MR19=505, MR18=2222
5708 11:35:53.686533 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5709 11:35:53.689544 [RxdqsGatingPostProcess] freq 933
5710 11:35:53.693434 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5711 11:35:53.696609 Pre-setting of DQS Precalculation
5712 11:35:53.703577 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5713 11:35:53.709448 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5714 11:35:53.718341 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5715 11:35:53.718415
5716 11:35:53.718473
5717 11:35:53.720852 [Calibration Summary] 1866 Mbps
5718 11:35:53.720926 CH 0, Rank 0
5719 11:35:53.723842 SW Impedance : PASS
5720 11:35:53.726229 DUTY Scan : NO K
5721 11:35:53.726304 ZQ Calibration : PASS
5722 11:35:53.729413 Jitter Meter : NO K
5723 11:35:53.732757 CBT Training : PASS
5724 11:35:53.732831 Write leveling : PASS
5725 11:35:53.736572 RX DQS gating : PASS
5726 11:35:53.739567 RX DQ/DQS(RDDQC) : PASS
5727 11:35:53.739641 TX DQ/DQS : PASS
5728 11:35:53.742569 RX DATLAT : PASS
5729 11:35:53.747339 RX DQ/DQS(Engine): PASS
5730 11:35:53.747413 TX OE : NO K
5731 11:35:53.747472 All Pass.
5732 11:35:53.749748
5733 11:35:53.749821 CH 0, Rank 1
5734 11:35:53.752924 SW Impedance : PASS
5735 11:35:53.752999 DUTY Scan : NO K
5736 11:35:53.755731 ZQ Calibration : PASS
5737 11:35:53.755806 Jitter Meter : NO K
5738 11:35:53.759698 CBT Training : PASS
5739 11:35:53.762997 Write leveling : PASS
5740 11:35:53.763071 RX DQS gating : PASS
5741 11:35:53.766940 RX DQ/DQS(RDDQC) : PASS
5742 11:35:53.769478 TX DQ/DQS : PASS
5743 11:35:53.769553 RX DATLAT : PASS
5744 11:35:53.772968 RX DQ/DQS(Engine): PASS
5745 11:35:53.776017 TX OE : NO K
5746 11:35:53.776091 All Pass.
5747 11:35:53.776148
5748 11:35:53.776201 CH 1, Rank 0
5749 11:35:53.779480 SW Impedance : PASS
5750 11:35:53.782411 DUTY Scan : NO K
5751 11:35:53.782485 ZQ Calibration : PASS
5752 11:35:53.785622 Jitter Meter : NO K
5753 11:35:53.789457 CBT Training : PASS
5754 11:35:53.789532 Write leveling : PASS
5755 11:35:53.792598 RX DQS gating : PASS
5756 11:35:53.795766 RX DQ/DQS(RDDQC) : PASS
5757 11:35:53.795840 TX DQ/DQS : PASS
5758 11:35:53.799125 RX DATLAT : PASS
5759 11:35:53.803069 RX DQ/DQS(Engine): PASS
5760 11:35:53.803143 TX OE : NO K
5761 11:35:53.803201 All Pass.
5762 11:35:53.805838
5763 11:35:53.805912 CH 1, Rank 1
5764 11:35:53.808994 SW Impedance : PASS
5765 11:35:53.809068 DUTY Scan : NO K
5766 11:35:53.812396 ZQ Calibration : PASS
5767 11:35:53.812469 Jitter Meter : NO K
5768 11:35:53.816508 CBT Training : PASS
5769 11:35:53.819430 Write leveling : PASS
5770 11:35:53.819504 RX DQS gating : PASS
5771 11:35:53.822465 RX DQ/DQS(RDDQC) : PASS
5772 11:35:53.825874 TX DQ/DQS : PASS
5773 11:35:53.825949 RX DATLAT : PASS
5774 11:35:53.829094 RX DQ/DQS(Engine): PASS
5775 11:35:53.833081 TX OE : NO K
5776 11:35:53.833156 All Pass.
5777 11:35:53.833215
5778 11:35:53.835716 DramC Write-DBI off
5779 11:35:53.835790 PER_BANK_REFRESH: Hybrid Mode
5780 11:35:53.839087 TX_TRACKING: ON
5781 11:35:53.848507 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5782 11:35:53.853000 [FAST_K] Save calibration result to emmc
5783 11:35:53.856767 dramc_set_vcore_voltage set vcore to 650000
5784 11:35:53.856845 Read voltage for 400, 6
5785 11:35:53.858826 Vio18 = 0
5786 11:35:53.858900 Vcore = 650000
5787 11:35:53.858957 Vdram = 0
5788 11:35:53.862052 Vddq = 0
5789 11:35:53.862126 Vmddr = 0
5790 11:35:53.865413 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5791 11:35:53.871940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5792 11:35:53.875403 MEM_TYPE=3, freq_sel=20
5793 11:35:53.878416 sv_algorithm_assistance_LP4_800
5794 11:35:53.882183 ============ PULL DRAM RESETB DOWN ============
5795 11:35:53.885337 ========== PULL DRAM RESETB DOWN end =========
5796 11:35:53.891975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5797 11:35:53.895030 ===================================
5798 11:35:53.895105 LPDDR4 DRAM CONFIGURATION
5799 11:35:53.898298 ===================================
5800 11:35:53.901670 EX_ROW_EN[0] = 0x0
5801 11:35:53.901744 EX_ROW_EN[1] = 0x0
5802 11:35:53.905552 LP4Y_EN = 0x0
5803 11:35:53.905626 WORK_FSP = 0x0
5804 11:35:53.908271 WL = 0x2
5805 11:35:53.912787 RL = 0x2
5806 11:35:53.912861 BL = 0x2
5807 11:35:53.915267 RPST = 0x0
5808 11:35:53.915341 RD_PRE = 0x0
5809 11:35:53.918580 WR_PRE = 0x1
5810 11:35:53.918654 WR_PST = 0x0
5811 11:35:53.921492 DBI_WR = 0x0
5812 11:35:53.921590 DBI_RD = 0x0
5813 11:35:53.925050 OTF = 0x1
5814 11:35:53.928244 ===================================
5815 11:35:53.933007 ===================================
5816 11:35:53.933082 ANA top config
5817 11:35:53.935239 ===================================
5818 11:35:53.938141 DLL_ASYNC_EN = 0
5819 11:35:53.942085 ALL_SLAVE_EN = 1
5820 11:35:53.942160 NEW_RANK_MODE = 1
5821 11:35:53.944783 DLL_IDLE_MODE = 1
5822 11:35:53.948157 LP45_APHY_COMB_EN = 1
5823 11:35:53.951653 TX_ODT_DIS = 1
5824 11:35:53.954765 NEW_8X_MODE = 1
5825 11:35:53.954841 ===================================
5826 11:35:53.958197 ===================================
5827 11:35:53.961831 data_rate = 800
5828 11:35:53.964985 CKR = 1
5829 11:35:53.968299 DQ_P2S_RATIO = 4
5830 11:35:53.972105 ===================================
5831 11:35:53.974956 CA_P2S_RATIO = 4
5832 11:35:53.979047 DQ_CA_OPEN = 0
5833 11:35:53.981255 DQ_SEMI_OPEN = 1
5834 11:35:53.981329 CA_SEMI_OPEN = 1
5835 11:35:53.984513 CA_FULL_RATE = 0
5836 11:35:53.988499 DQ_CKDIV4_EN = 0
5837 11:35:53.991366 CA_CKDIV4_EN = 1
5838 11:35:53.994483 CA_PREDIV_EN = 0
5839 11:35:53.998103 PH8_DLY = 0
5840 11:35:53.998177 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5841 11:35:54.001703 DQ_AAMCK_DIV = 0
5842 11:35:54.004364 CA_AAMCK_DIV = 0
5843 11:35:54.007692 CA_ADMCK_DIV = 4
5844 11:35:54.011637 DQ_TRACK_CA_EN = 0
5845 11:35:54.014536 CA_PICK = 800
5846 11:35:54.014610 CA_MCKIO = 400
5847 11:35:54.017841 MCKIO_SEMI = 400
5848 11:35:54.020866 PLL_FREQ = 3016
5849 11:35:54.024359 DQ_UI_PI_RATIO = 32
5850 11:35:54.027553 CA_UI_PI_RATIO = 32
5851 11:35:54.031579 ===================================
5852 11:35:54.034507 ===================================
5853 11:35:54.037679 memory_type:LPDDR4
5854 11:35:54.037752 GP_NUM : 10
5855 11:35:54.040755 SRAM_EN : 1
5856 11:35:54.044524 MD32_EN : 0
5857 11:35:54.047623 ===================================
5858 11:35:54.047696 [ANA_INIT] >>>>>>>>>>>>>>
5859 11:35:54.051264 <<<<<< [CONFIGURE PHASE]: ANA_TX
5860 11:35:54.054093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5861 11:35:54.057715 ===================================
5862 11:35:54.061088 data_rate = 800,PCW = 0X7400
5863 11:35:54.064238 ===================================
5864 11:35:54.067674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5865 11:35:54.074252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5866 11:35:54.083726 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5867 11:35:54.087213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5868 11:35:54.094351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5869 11:35:54.097495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5870 11:35:54.097570 [ANA_INIT] flow start
5871 11:35:54.100855 [ANA_INIT] PLL >>>>>>>>
5872 11:35:54.104270 [ANA_INIT] PLL <<<<<<<<
5873 11:35:54.104344 [ANA_INIT] MIDPI >>>>>>>>
5874 11:35:54.108234 [ANA_INIT] MIDPI <<<<<<<<
5875 11:35:54.110423 [ANA_INIT] DLL >>>>>>>>
5876 11:35:54.110497 [ANA_INIT] flow end
5877 11:35:54.114347 ============ LP4 DIFF to SE enter ============
5878 11:35:54.120103 ============ LP4 DIFF to SE exit ============
5879 11:35:54.120177 [ANA_INIT] <<<<<<<<<<<<<
5880 11:35:54.123703 [Flow] Enable top DCM control >>>>>
5881 11:35:54.127119 [Flow] Enable top DCM control <<<<<
5882 11:35:54.130109 Enable DLL master slave shuffle
5883 11:35:54.136654 ==============================================================
5884 11:35:54.140777 Gating Mode config
5885 11:35:54.144087 ==============================================================
5886 11:35:54.146525 Config description:
5887 11:35:54.156884 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5888 11:35:54.162987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5889 11:35:54.166608 SELPH_MODE 0: By rank 1: By Phase
5890 11:35:54.173862 ==============================================================
5891 11:35:54.177692 GAT_TRACK_EN = 0
5892 11:35:54.179775 RX_GATING_MODE = 2
5893 11:35:54.183176 RX_GATING_TRACK_MODE = 2
5894 11:35:54.186488 SELPH_MODE = 1
5895 11:35:54.186562 PICG_EARLY_EN = 1
5896 11:35:54.189837 VALID_LAT_VALUE = 1
5897 11:35:54.197202 ==============================================================
5898 11:35:54.199630 Enter into Gating configuration >>>>
5899 11:35:54.203484 Exit from Gating configuration <<<<
5900 11:35:54.206852 Enter into DVFS_PRE_config >>>>>
5901 11:35:54.216520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5902 11:35:54.219843 Exit from DVFS_PRE_config <<<<<
5903 11:35:54.222601 Enter into PICG configuration >>>>
5904 11:35:54.226616 Exit from PICG configuration <<<<
5905 11:35:54.229474 [RX_INPUT] configuration >>>>>
5906 11:35:54.233114 [RX_INPUT] configuration <<<<<
5907 11:35:54.235909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5908 11:35:54.242564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5909 11:35:54.249460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5910 11:35:54.255883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5911 11:35:54.262571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5912 11:35:54.269182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5913 11:35:54.273164 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5914 11:35:54.275704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5915 11:35:54.278794 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5916 11:35:54.282427 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5917 11:35:54.288801 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5918 11:35:54.292474 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5919 11:35:54.295702 ===================================
5920 11:35:54.299076 LPDDR4 DRAM CONFIGURATION
5921 11:35:54.302443 ===================================
5922 11:35:54.302518 EX_ROW_EN[0] = 0x0
5923 11:35:54.305954 EX_ROW_EN[1] = 0x0
5924 11:35:54.306028 LP4Y_EN = 0x0
5925 11:35:54.309139 WORK_FSP = 0x0
5926 11:35:54.309214 WL = 0x2
5927 11:35:54.312057 RL = 0x2
5928 11:35:54.315476 BL = 0x2
5929 11:35:54.315550 RPST = 0x0
5930 11:35:54.318936 RD_PRE = 0x0
5931 11:35:54.319011 WR_PRE = 0x1
5932 11:35:54.322173 WR_PST = 0x0
5933 11:35:54.322250 DBI_WR = 0x0
5934 11:35:54.325692 DBI_RD = 0x0
5935 11:35:54.325772 OTF = 0x1
5936 11:35:54.328871 ===================================
5937 11:35:54.332149 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5938 11:35:54.338832 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5939 11:35:54.342019 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5940 11:35:54.345168 ===================================
5941 11:35:54.348142 LPDDR4 DRAM CONFIGURATION
5942 11:35:54.351776 ===================================
5943 11:35:54.351850 EX_ROW_EN[0] = 0x10
5944 11:35:54.355350 EX_ROW_EN[1] = 0x0
5945 11:35:54.355428 LP4Y_EN = 0x0
5946 11:35:54.358428 WORK_FSP = 0x0
5947 11:35:54.358502 WL = 0x2
5948 11:35:54.361598 RL = 0x2
5949 11:35:54.361673 BL = 0x2
5950 11:35:54.365076 RPST = 0x0
5951 11:35:54.368665 RD_PRE = 0x0
5952 11:35:54.368738 WR_PRE = 0x1
5953 11:35:54.371441 WR_PST = 0x0
5954 11:35:54.371505 DBI_WR = 0x0
5955 11:35:54.374727 DBI_RD = 0x0
5956 11:35:54.374794 OTF = 0x1
5957 11:35:54.378088 ===================================
5958 11:35:54.384898 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5959 11:35:54.388555 nWR fixed to 30
5960 11:35:54.392038 [ModeRegInit_LP4] CH0 RK0
5961 11:35:54.392108 [ModeRegInit_LP4] CH0 RK1
5962 11:35:54.395182 [ModeRegInit_LP4] CH1 RK0
5963 11:35:54.399186 [ModeRegInit_LP4] CH1 RK1
5964 11:35:54.399255 match AC timing 18
5965 11:35:54.405602 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5966 11:35:54.408654 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5967 11:35:54.413620 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5968 11:35:54.418583 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5969 11:35:54.421813 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5970 11:35:54.421888 ==
5971 11:35:54.425804 Dram Type= 6, Freq= 0, CH_0, rank 0
5972 11:35:54.428654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5973 11:35:54.428730 ==
5974 11:35:54.435738 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5975 11:35:54.441740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5976 11:35:54.445530 [CA 0] Center 36 (8~64) winsize 57
5977 11:35:54.449100 [CA 1] Center 36 (8~64) winsize 57
5978 11:35:54.451618 [CA 2] Center 36 (8~64) winsize 57
5979 11:35:54.455157 [CA 3] Center 36 (8~64) winsize 57
5980 11:35:54.455232 [CA 4] Center 36 (8~64) winsize 57
5981 11:35:54.458217 [CA 5] Center 36 (8~64) winsize 57
5982 11:35:54.458292
5983 11:35:54.464805 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5984 11:35:54.464880
5985 11:35:54.468534 [CATrainingPosCal] consider 1 rank data
5986 11:35:54.471589 u2DelayCellTimex100 = 270/100 ps
5987 11:35:54.475894 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5988 11:35:54.478491 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5989 11:35:54.482054 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 11:35:54.485463 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 11:35:54.488431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 11:35:54.491491 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 11:35:54.491566
5994 11:35:54.494391 CA PerBit enable=1, Macro0, CA PI delay=36
5995 11:35:54.494466
5996 11:35:54.498040 [CBTSetCACLKResult] CA Dly = 36
5997 11:35:54.501016 CS Dly: 1 (0~32)
5998 11:35:54.501090 ==
5999 11:35:54.504363 Dram Type= 6, Freq= 0, CH_0, rank 1
6000 11:35:54.508410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6001 11:35:54.508486 ==
6002 11:35:54.514603 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6003 11:35:54.521009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6004 11:35:54.524142 [CA 0] Center 36 (8~64) winsize 57
6005 11:35:54.524216 [CA 1] Center 36 (8~64) winsize 57
6006 11:35:54.527489 [CA 2] Center 36 (8~64) winsize 57
6007 11:35:54.530859 [CA 3] Center 36 (8~64) winsize 57
6008 11:35:54.534465 [CA 4] Center 36 (8~64) winsize 57
6009 11:35:54.537210 [CA 5] Center 36 (8~64) winsize 57
6010 11:35:54.537307
6011 11:35:54.541160 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6012 11:35:54.541269
6013 11:35:54.547362 [CATrainingPosCal] consider 2 rank data
6014 11:35:54.547436 u2DelayCellTimex100 = 270/100 ps
6015 11:35:54.554319 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 11:35:54.557447 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 11:35:54.560874 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 11:35:54.564575 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 11:35:54.567420 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 11:35:54.570869 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 11:35:54.570943
6022 11:35:54.575201 CA PerBit enable=1, Macro0, CA PI delay=36
6023 11:35:54.575276
6024 11:35:54.578284 [CBTSetCACLKResult] CA Dly = 36
6025 11:35:54.580913 CS Dly: 1 (0~32)
6026 11:35:54.580986
6027 11:35:54.584317 ----->DramcWriteLeveling(PI) begin...
6028 11:35:54.584392 ==
6029 11:35:54.587307 Dram Type= 6, Freq= 0, CH_0, rank 0
6030 11:35:54.590678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6031 11:35:54.590753 ==
6032 11:35:54.594451 Write leveling (Byte 0): 32 => 0
6033 11:35:54.597002 Write leveling (Byte 1): 32 => 0
6034 11:35:54.600730 DramcWriteLeveling(PI) end<-----
6035 11:35:54.600803
6036 11:35:54.600861 ==
6037 11:35:54.604219 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 11:35:54.607225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 11:35:54.607300 ==
6040 11:35:54.610614 [Gating] SW mode calibration
6041 11:35:54.616741 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6042 11:35:54.623249 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6043 11:35:54.626791 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6044 11:35:54.631130 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6045 11:35:54.636728 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6046 11:35:54.640105 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6047 11:35:54.643400 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6048 11:35:54.650248 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6049 11:35:54.653160 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6050 11:35:54.657124 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6051 11:35:54.663159 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6052 11:35:54.663232 Total UI for P1: 0, mck2ui 16
6053 11:35:54.669461 best dqsien dly found for B0: ( 0, 10, 16)
6054 11:35:54.669532 Total UI for P1: 0, mck2ui 16
6055 11:35:54.676532 best dqsien dly found for B1: ( 0, 10, 24)
6056 11:35:54.680483 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6057 11:35:54.682857 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6058 11:35:54.682920
6059 11:35:54.686620 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6060 11:35:54.689671 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6061 11:35:54.693007 [Gating] SW calibration Done
6062 11:35:54.693070 ==
6063 11:35:54.696575 Dram Type= 6, Freq= 0, CH_0, rank 0
6064 11:35:54.699818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6065 11:35:54.699883 ==
6066 11:35:54.702938 RX Vref Scan: 0
6067 11:35:54.703002
6068 11:35:54.703058 RX Vref 0 -> 0, step: 1
6069 11:35:54.706063
6070 11:35:54.706127 RX Delay -410 -> 252, step: 16
6071 11:35:54.713257 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6072 11:35:54.715942 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6073 11:35:54.719259 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6074 11:35:54.722737 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6075 11:35:54.729432 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6076 11:35:54.732291 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6077 11:35:54.735689 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6078 11:35:54.739735 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6079 11:35:54.745482 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6080 11:35:54.748831 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6081 11:35:54.752279 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6082 11:35:54.758959 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6083 11:35:54.763193 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6084 11:35:54.766452 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6085 11:35:54.768728 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6086 11:35:54.775502 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6087 11:35:54.775566 ==
6088 11:35:54.779096 Dram Type= 6, Freq= 0, CH_0, rank 0
6089 11:35:54.782363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6090 11:35:54.782423 ==
6091 11:35:54.782478 DQS Delay:
6092 11:35:54.785336 DQS0 = 51, DQS1 = 59
6093 11:35:54.785395 DQM Delay:
6094 11:35:54.788818 DQM0 = 13, DQM1 = 16
6095 11:35:54.788875 DQ Delay:
6096 11:35:54.792205 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6097 11:35:54.795330 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6098 11:35:54.798602 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6099 11:35:54.801572 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6100 11:35:54.801631
6101 11:35:54.801682
6102 11:35:54.801731 ==
6103 11:35:54.805453 Dram Type= 6, Freq= 0, CH_0, rank 0
6104 11:35:54.808345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6105 11:35:54.808411 ==
6106 11:35:54.808469
6107 11:35:54.808518
6108 11:35:54.812339 TX Vref Scan disable
6109 11:35:54.815716 == TX Byte 0 ==
6110 11:35:54.818811 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6111 11:35:54.822060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6112 11:35:54.825141 == TX Byte 1 ==
6113 11:35:54.828738 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6114 11:35:54.832351 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6115 11:35:54.832415 ==
6116 11:35:54.835733 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 11:35:54.838618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 11:35:54.842273 ==
6119 11:35:54.842331
6120 11:35:54.842387
6121 11:35:54.842437 TX Vref Scan disable
6122 11:35:54.845307 == TX Byte 0 ==
6123 11:35:54.848114 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 11:35:54.852197 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 11:35:54.855649 == TX Byte 1 ==
6126 11:35:54.858328 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 11:35:54.861742 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 11:35:54.861803
6129 11:35:54.865263 [DATLAT]
6130 11:35:54.865331 Freq=400, CH0 RK0
6131 11:35:54.865387
6132 11:35:54.868312 DATLAT Default: 0xf
6133 11:35:54.868370 0, 0xFFFF, sum = 0
6134 11:35:54.872130 1, 0xFFFF, sum = 0
6135 11:35:54.872196 2, 0xFFFF, sum = 0
6136 11:35:54.875460 3, 0xFFFF, sum = 0
6137 11:35:54.875526 4, 0xFFFF, sum = 0
6138 11:35:54.878394 5, 0xFFFF, sum = 0
6139 11:35:54.878461 6, 0xFFFF, sum = 0
6140 11:35:54.882301 7, 0xFFFF, sum = 0
6141 11:35:54.882364 8, 0xFFFF, sum = 0
6142 11:35:54.885387 9, 0xFFFF, sum = 0
6143 11:35:54.885450 10, 0xFFFF, sum = 0
6144 11:35:54.888049 11, 0xFFFF, sum = 0
6145 11:35:54.888112 12, 0x0, sum = 1
6146 11:35:54.892669 13, 0x0, sum = 2
6147 11:35:54.892731 14, 0x0, sum = 3
6148 11:35:54.894993 15, 0x0, sum = 4
6149 11:35:54.895055 best_step = 13
6150 11:35:54.895105
6151 11:35:54.895154 ==
6152 11:35:54.898146 Dram Type= 6, Freq= 0, CH_0, rank 0
6153 11:35:54.904686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6154 11:35:54.904750 ==
6155 11:35:54.904803 RX Vref Scan: 1
6156 11:35:54.904855
6157 11:35:54.908451 RX Vref 0 -> 0, step: 1
6158 11:35:54.908507
6159 11:35:54.912209 RX Delay -359 -> 252, step: 8
6160 11:35:54.912269
6161 11:35:54.914574 Set Vref, RX VrefLevel [Byte0]: 47
6162 11:35:54.918034 [Byte1]: 52
6163 11:35:54.918097
6164 11:35:54.921545 Final RX Vref Byte 0 = 47 to rank0
6165 11:35:54.924581 Final RX Vref Byte 1 = 52 to rank0
6166 11:35:54.927819 Final RX Vref Byte 0 = 47 to rank1
6167 11:35:54.931917 Final RX Vref Byte 1 = 52 to rank1==
6168 11:35:54.934685 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 11:35:54.938178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 11:35:54.941969 ==
6171 11:35:54.942032 DQS Delay:
6172 11:35:54.942084 DQS0 = 52, DQS1 = 64
6173 11:35:54.944759 DQM Delay:
6174 11:35:54.944814 DQM0 = 9, DQM1 = 13
6175 11:35:54.948179 DQ Delay:
6176 11:35:54.948237 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6177 11:35:54.951430 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6178 11:35:54.955065 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6179 11:35:54.957753 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6180 11:35:54.957816
6181 11:35:54.957867
6182 11:35:54.967951 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6183 11:35:54.970907 CH0 RK0: MR19=C0C, MR18=A0A0
6184 11:35:54.978106 CH0_RK0: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6185 11:35:54.978177 ==
6186 11:35:54.980943 Dram Type= 6, Freq= 0, CH_0, rank 1
6187 11:35:54.984312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 11:35:54.984375 ==
6189 11:35:54.987524 [Gating] SW mode calibration
6190 11:35:54.994993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6191 11:35:54.998505 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6192 11:35:55.004968 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6193 11:35:55.007743 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6194 11:35:55.011130 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6195 11:35:55.018067 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6196 11:35:55.021351 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6197 11:35:55.024092 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6198 11:35:55.031247 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6199 11:35:55.034297 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6200 11:35:55.037546 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6201 11:35:55.040640 Total UI for P1: 0, mck2ui 16
6202 11:35:55.044620 best dqsien dly found for B0: ( 0, 10, 16)
6203 11:35:55.047404 Total UI for P1: 0, mck2ui 16
6204 11:35:55.050735 best dqsien dly found for B1: ( 0, 10, 16)
6205 11:35:55.053995 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6206 11:35:55.057684 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6207 11:35:55.057752
6208 11:35:55.064345 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6209 11:35:55.067208 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6210 11:35:55.071425 [Gating] SW calibration Done
6211 11:35:55.071493 ==
6212 11:35:55.074106 Dram Type= 6, Freq= 0, CH_0, rank 1
6213 11:35:55.077347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6214 11:35:55.077421 ==
6215 11:35:55.077479 RX Vref Scan: 0
6216 11:35:55.080234
6217 11:35:55.080295 RX Vref 0 -> 0, step: 1
6218 11:35:55.080348
6219 11:35:55.083874 RX Delay -410 -> 252, step: 16
6220 11:35:55.086847 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6221 11:35:55.093642 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6222 11:35:55.097063 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6223 11:35:55.100346 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6224 11:35:55.104519 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6225 11:35:55.110827 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6226 11:35:55.114027 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6227 11:35:55.117113 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6228 11:35:55.120051 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6229 11:35:55.126543 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6230 11:35:55.130670 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6231 11:35:55.134035 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6232 11:35:55.137423 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6233 11:35:55.143478 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6234 11:35:55.146706 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6235 11:35:55.150010 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6236 11:35:55.150084 ==
6237 11:35:55.153438 Dram Type= 6, Freq= 0, CH_0, rank 1
6238 11:35:55.160409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6239 11:35:55.160485 ==
6240 11:35:55.160542 DQS Delay:
6241 11:35:55.162996 DQS0 = 51, DQS1 = 59
6242 11:35:55.163069 DQM Delay:
6243 11:35:55.163126 DQM0 = 14, DQM1 = 14
6244 11:35:55.167566 DQ Delay:
6245 11:35:55.169856 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6246 11:35:55.173006 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6247 11:35:55.173080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6248 11:35:55.176649 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6249 11:35:55.179567
6250 11:35:55.179633
6251 11:35:55.179693 ==
6252 11:35:55.183199 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 11:35:55.186984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6254 11:35:55.187049 ==
6255 11:35:55.187107
6256 11:35:55.187160
6257 11:35:55.189716 TX Vref Scan disable
6258 11:35:55.189777 == TX Byte 0 ==
6259 11:35:55.192988 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6260 11:35:55.200181 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6261 11:35:55.200252 == TX Byte 1 ==
6262 11:35:55.202798 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6263 11:35:55.209460 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6264 11:35:55.209531 ==
6265 11:35:55.212923 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 11:35:55.218546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 11:35:55.218616 ==
6268 11:35:55.218673
6269 11:35:55.218725
6270 11:35:55.220001 TX Vref Scan disable
6271 11:35:55.220061 == TX Byte 0 ==
6272 11:35:55.222868 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6273 11:35:55.229967 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6274 11:35:55.230040 == TX Byte 1 ==
6275 11:35:55.232934 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6276 11:35:55.239650 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6277 11:35:55.239730
6278 11:35:55.239788 [DATLAT]
6279 11:35:55.239842 Freq=400, CH0 RK1
6280 11:35:55.242816
6281 11:35:55.242884 DATLAT Default: 0xd
6282 11:35:55.245913 0, 0xFFFF, sum = 0
6283 11:35:55.245977 1, 0xFFFF, sum = 0
6284 11:35:55.250179 2, 0xFFFF, sum = 0
6285 11:35:55.250244 3, 0xFFFF, sum = 0
6286 11:35:55.252603 4, 0xFFFF, sum = 0
6287 11:35:55.252665 5, 0xFFFF, sum = 0
6288 11:35:55.256354 6, 0xFFFF, sum = 0
6289 11:35:55.256416 7, 0xFFFF, sum = 0
6290 11:35:55.259517 8, 0xFFFF, sum = 0
6291 11:35:55.259580 9, 0xFFFF, sum = 0
6292 11:35:55.262889 10, 0xFFFF, sum = 0
6293 11:35:55.262951 11, 0xFFFF, sum = 0
6294 11:35:55.265570 12, 0x0, sum = 1
6295 11:35:55.265636 13, 0x0, sum = 2
6296 11:35:55.269753 14, 0x0, sum = 3
6297 11:35:55.269815 15, 0x0, sum = 4
6298 11:35:55.273048 best_step = 13
6299 11:35:55.273113
6300 11:35:55.273165 ==
6301 11:35:55.275936 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 11:35:55.279030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6303 11:35:55.279091 ==
6304 11:35:55.282493 RX Vref Scan: 0
6305 11:35:55.282556
6306 11:35:55.282607 RX Vref 0 -> 0, step: 1
6307 11:35:55.282657
6308 11:35:55.285682 RX Delay -359 -> 252, step: 8
6309 11:35:55.294027 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6310 11:35:55.297088 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6311 11:35:55.300212 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6312 11:35:55.303660 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6313 11:35:55.310612 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6314 11:35:55.313937 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6315 11:35:55.316655 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6316 11:35:55.321203 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6317 11:35:55.327361 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6318 11:35:55.330214 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6319 11:35:55.333394 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6320 11:35:55.339891 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6321 11:35:55.344196 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6322 11:35:55.347290 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6323 11:35:55.350105 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6324 11:35:55.356744 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6325 11:35:55.356811 ==
6326 11:35:55.360219 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 11:35:55.363103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 11:35:55.363163 ==
6329 11:35:55.363219 DQS Delay:
6330 11:35:55.367550 DQS0 = 52, DQS1 = 64
6331 11:35:55.367609 DQM Delay:
6332 11:35:55.370741 DQM0 = 9, DQM1 = 14
6333 11:35:55.370797 DQ Delay:
6334 11:35:55.373631 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6335 11:35:55.376531 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6336 11:35:55.379575 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6337 11:35:55.383594 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6338 11:35:55.383667
6339 11:35:55.383723
6340 11:35:55.390060 [DQSOSCAuto] RK1, (LSB)MR18= 0xcbcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6341 11:35:55.393250 CH0 RK1: MR19=C0C, MR18=CBCB
6342 11:35:55.400400 CH0_RK1: MR19=0xC0C, MR18=0xCBCB, DQSOSC=384, MR23=63, INC=400, DEC=267
6343 11:35:55.403752 [RxdqsGatingPostProcess] freq 400
6344 11:35:55.409488 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6345 11:35:55.412784 Pre-setting of DQS Precalculation
6346 11:35:55.416201 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6347 11:35:55.416264 ==
6348 11:35:55.419728 Dram Type= 6, Freq= 0, CH_1, rank 0
6349 11:35:55.422590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 11:35:55.422654 ==
6351 11:35:55.429430 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6352 11:35:55.436262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6353 11:35:55.439059 [CA 0] Center 36 (8~64) winsize 57
6354 11:35:55.442597 [CA 1] Center 36 (8~64) winsize 57
6355 11:35:55.445944 [CA 2] Center 36 (8~64) winsize 57
6356 11:35:55.449690 [CA 3] Center 36 (8~64) winsize 57
6357 11:35:55.452501 [CA 4] Center 36 (8~64) winsize 57
6358 11:35:55.455632 [CA 5] Center 36 (8~64) winsize 57
6359 11:35:55.455745
6360 11:35:55.458882 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6361 11:35:55.458953
6362 11:35:55.463941 [CATrainingPosCal] consider 1 rank data
6363 11:35:55.465730 u2DelayCellTimex100 = 270/100 ps
6364 11:35:55.468789 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 11:35:55.472138 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 11:35:55.475887 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 11:35:55.478889 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 11:35:55.483099 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 11:35:55.485724 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 11:35:55.485798
6371 11:35:55.489269 CA PerBit enable=1, Macro0, CA PI delay=36
6372 11:35:55.489343
6373 11:35:55.492475 [CBTSetCACLKResult] CA Dly = 36
6374 11:35:55.495337 CS Dly: 1 (0~32)
6375 11:35:55.495410 ==
6376 11:35:55.500211 Dram Type= 6, Freq= 0, CH_1, rank 1
6377 11:35:55.502266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6378 11:35:55.502340 ==
6379 11:35:55.508691 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6380 11:35:55.514984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6381 11:35:55.518120 [CA 0] Center 36 (8~64) winsize 57
6382 11:35:55.521586 [CA 1] Center 36 (8~64) winsize 57
6383 11:35:55.525610 [CA 2] Center 36 (8~64) winsize 57
6384 11:35:55.525685 [CA 3] Center 36 (8~64) winsize 57
6385 11:35:55.528660 [CA 4] Center 36 (8~64) winsize 57
6386 11:35:55.532753 [CA 5] Center 36 (8~64) winsize 57
6387 11:35:55.532828
6388 11:35:55.538257 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6389 11:35:55.538331
6390 11:35:55.541455 [CATrainingPosCal] consider 2 rank data
6391 11:35:55.545490 u2DelayCellTimex100 = 270/100 ps
6392 11:35:55.548745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 11:35:55.552213 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 11:35:55.555111 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 11:35:55.559005 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 11:35:55.561498 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 11:35:55.564733 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 11:35:55.564807
6399 11:35:55.568715 CA PerBit enable=1, Macro0, CA PI delay=36
6400 11:35:55.568804
6401 11:35:55.571620 [CBTSetCACLKResult] CA Dly = 36
6402 11:35:55.574865 CS Dly: 1 (0~32)
6403 11:35:55.574938
6404 11:35:55.578048 ----->DramcWriteLeveling(PI) begin...
6405 11:35:55.578142 ==
6406 11:35:55.581538 Dram Type= 6, Freq= 0, CH_1, rank 0
6407 11:35:55.585118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6408 11:35:55.585194 ==
6409 11:35:55.588048 Write leveling (Byte 0): 32 => 0
6410 11:35:55.591641 Write leveling (Byte 1): 32 => 0
6411 11:35:55.594436 DramcWriteLeveling(PI) end<-----
6412 11:35:55.594510
6413 11:35:55.594567 ==
6414 11:35:55.598350 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 11:35:55.601364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 11:35:55.601438 ==
6417 11:35:55.604632 [Gating] SW mode calibration
6418 11:35:55.611133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 11:35:55.618324 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6420 11:35:55.620915 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:35:55.624460 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 11:35:55.630810 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:35:55.634778 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6424 11:35:55.638017 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:35:55.644169 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:35:55.647587 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:35:55.650681 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6428 11:35:55.657137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:35:55.660407 Total UI for P1: 0, mck2ui 16
6430 11:35:55.663789 best dqsien dly found for B0: ( 0, 10, 16)
6431 11:35:55.667341 Total UI for P1: 0, mck2ui 16
6432 11:35:55.670473 best dqsien dly found for B1: ( 0, 10, 16)
6433 11:35:55.674272 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6434 11:35:55.677443 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6435 11:35:55.677517
6436 11:35:55.680353 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6437 11:35:55.684771 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6438 11:35:55.686900 [Gating] SW calibration Done
6439 11:35:55.686973 ==
6440 11:35:55.690757 Dram Type= 6, Freq= 0, CH_1, rank 0
6441 11:35:55.694156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6442 11:35:55.694230 ==
6443 11:35:55.696955 RX Vref Scan: 0
6444 11:35:55.697028
6445 11:35:55.700357 RX Vref 0 -> 0, step: 1
6446 11:35:55.700432
6447 11:35:55.700494 RX Delay -410 -> 252, step: 16
6448 11:35:55.707112 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6449 11:35:55.710104 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6450 11:35:55.713841 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6451 11:35:55.720885 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6452 11:35:55.723801 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6453 11:35:55.727415 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6454 11:35:55.730260 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6455 11:35:55.737114 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6456 11:35:55.740130 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6457 11:35:55.743503 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6458 11:35:55.746648 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6459 11:35:55.753531 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6460 11:35:55.756895 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6461 11:35:55.760058 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6462 11:35:55.763090 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6463 11:35:55.769360 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6464 11:35:55.769435 ==
6465 11:35:55.773126 Dram Type= 6, Freq= 0, CH_1, rank 0
6466 11:35:55.777117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6467 11:35:55.777192 ==
6468 11:35:55.777259 DQS Delay:
6469 11:35:55.779703 DQS0 = 43, DQS1 = 59
6470 11:35:55.779777 DQM Delay:
6471 11:35:55.783202 DQM0 = 6, DQM1 = 15
6472 11:35:55.783276 DQ Delay:
6473 11:35:55.786452 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6474 11:35:55.789353 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6475 11:35:55.793195 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 11:35:55.796646 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6477 11:35:55.796720
6478 11:35:55.796777
6479 11:35:55.796830 ==
6480 11:35:55.799472 Dram Type= 6, Freq= 0, CH_1, rank 0
6481 11:35:55.802762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6482 11:35:55.802836 ==
6483 11:35:55.802894
6484 11:35:55.806503
6485 11:35:55.806576 TX Vref Scan disable
6486 11:35:55.810221 == TX Byte 0 ==
6487 11:35:55.813417 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6488 11:35:55.816047 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6489 11:35:55.818951 == TX Byte 1 ==
6490 11:35:55.822316 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6491 11:35:55.825958 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6492 11:35:55.826032 ==
6493 11:35:55.829367 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 11:35:55.835630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 11:35:55.835719 ==
6496 11:35:55.835777
6497 11:35:55.835828
6498 11:35:55.835885 TX Vref Scan disable
6499 11:35:55.838832 == TX Byte 0 ==
6500 11:35:55.842376 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 11:35:55.845685 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 11:35:55.848790 == TX Byte 1 ==
6503 11:35:55.852385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 11:35:55.855567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 11:35:55.858999
6506 11:35:55.859066 [DATLAT]
6507 11:35:55.859119 Freq=400, CH1 RK0
6508 11:35:55.859170
6509 11:35:55.862814 DATLAT Default: 0xf
6510 11:35:55.862878 0, 0xFFFF, sum = 0
6511 11:35:55.865142 1, 0xFFFF, sum = 0
6512 11:35:55.865203 2, 0xFFFF, sum = 0
6513 11:35:55.868518 3, 0xFFFF, sum = 0
6514 11:35:55.868576 4, 0xFFFF, sum = 0
6515 11:35:55.872308 5, 0xFFFF, sum = 0
6516 11:35:55.872368 6, 0xFFFF, sum = 0
6517 11:35:55.875554 7, 0xFFFF, sum = 0
6518 11:35:55.878669 8, 0xFFFF, sum = 0
6519 11:35:55.878732 9, 0xFFFF, sum = 0
6520 11:35:55.882168 10, 0xFFFF, sum = 0
6521 11:35:55.882229 11, 0xFFFF, sum = 0
6522 11:35:55.885144 12, 0x0, sum = 1
6523 11:35:55.885201 13, 0x0, sum = 2
6524 11:35:55.889076 14, 0x0, sum = 3
6525 11:35:55.889137 15, 0x0, sum = 4
6526 11:35:55.889187 best_step = 13
6527 11:35:55.889246
6528 11:35:55.891786 ==
6529 11:35:55.895730 Dram Type= 6, Freq= 0, CH_1, rank 0
6530 11:35:55.899407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6531 11:35:55.899467 ==
6532 11:35:55.899523 RX Vref Scan: 1
6533 11:35:55.899574
6534 11:35:55.901674 RX Vref 0 -> 0, step: 1
6535 11:35:55.901730
6536 11:35:55.905252 RX Delay -359 -> 252, step: 8
6537 11:35:55.905343
6538 11:35:55.908596 Set Vref, RX VrefLevel [Byte0]: 51
6539 11:35:55.912153 [Byte1]: 50
6540 11:35:55.915673
6541 11:35:55.915746 Final RX Vref Byte 0 = 51 to rank0
6542 11:35:55.919015 Final RX Vref Byte 1 = 50 to rank0
6543 11:35:55.922451 Final RX Vref Byte 0 = 51 to rank1
6544 11:35:55.925886 Final RX Vref Byte 1 = 50 to rank1==
6545 11:35:55.928622 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 11:35:55.935495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 11:35:55.935569 ==
6548 11:35:55.935627 DQS Delay:
6549 11:35:55.939514 DQS0 = 48, DQS1 = 64
6550 11:35:55.939587 DQM Delay:
6551 11:35:55.939644 DQM0 = 8, DQM1 = 15
6552 11:35:55.942443 DQ Delay:
6553 11:35:55.945720 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6554 11:35:55.945794 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6555 11:35:55.948830 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6556 11:35:55.952070 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6557 11:35:55.952144
6558 11:35:55.952202
6559 11:35:55.962197 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5e5, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6560 11:35:55.965927 CH1 RK0: MR19=C0C, MR18=E5E5
6561 11:35:55.972497 CH1_RK0: MR19=0xC0C, MR18=0xE5E5, DQSOSC=381, MR23=63, INC=406, DEC=271
6562 11:35:55.972571 ==
6563 11:35:55.975714 Dram Type= 6, Freq= 0, CH_1, rank 1
6564 11:35:55.978585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 11:35:55.978660 ==
6566 11:35:55.982290 [Gating] SW mode calibration
6567 11:35:55.988992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6568 11:35:55.992023 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6569 11:35:55.998908 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6570 11:35:56.001658 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6571 11:35:56.004971 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6572 11:35:56.012479 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6573 11:35:56.014940 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6574 11:35:56.018753 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6575 11:35:56.025618 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6576 11:35:56.028652 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6577 11:35:56.031579 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6578 11:35:56.034984 Total UI for P1: 0, mck2ui 16
6579 11:35:56.038443 best dqsien dly found for B0: ( 0, 10, 16)
6580 11:35:56.041705 Total UI for P1: 0, mck2ui 16
6581 11:35:56.044853 best dqsien dly found for B1: ( 0, 10, 16)
6582 11:35:56.047855 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6583 11:35:56.056004 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6584 11:35:56.056077
6585 11:35:56.058572 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6586 11:35:56.061283 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6587 11:35:56.064280 [Gating] SW calibration Done
6588 11:35:56.064354 ==
6589 11:35:56.067748 Dram Type= 6, Freq= 0, CH_1, rank 1
6590 11:35:56.070953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6591 11:35:56.071028 ==
6592 11:35:56.074484 RX Vref Scan: 0
6593 11:35:56.074583
6594 11:35:56.074650 RX Vref 0 -> 0, step: 1
6595 11:35:56.074705
6596 11:35:56.077839 RX Delay -410 -> 252, step: 16
6597 11:35:56.084257 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6598 11:35:56.087734 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6599 11:35:56.091474 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6600 11:35:56.094571 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6601 11:35:56.101212 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6602 11:35:56.104493 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6603 11:35:56.107875 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6604 11:35:56.112083 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6605 11:35:56.117921 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6606 11:35:56.120730 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6607 11:35:56.123874 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6608 11:35:56.127406 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6609 11:35:56.133878 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6610 11:35:56.137713 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6611 11:35:56.140542 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6612 11:35:56.144027 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6613 11:35:56.147847 ==
6614 11:35:56.147921 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 11:35:56.153844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6616 11:35:56.153919 ==
6617 11:35:56.153977 DQS Delay:
6618 11:35:56.157498 DQS0 = 35, DQS1 = 59
6619 11:35:56.157572 DQM Delay:
6620 11:35:56.160990 DQM0 = 3, DQM1 = 18
6621 11:35:56.161063 DQ Delay:
6622 11:35:56.163826 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6623 11:35:56.167568 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6624 11:35:56.167642 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6625 11:35:56.173813 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6626 11:35:56.173888
6627 11:35:56.173945
6628 11:35:56.173997 ==
6629 11:35:56.177242 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 11:35:56.180367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6631 11:35:56.180442 ==
6632 11:35:56.180498
6633 11:35:56.180550
6634 11:35:56.183788 TX Vref Scan disable
6635 11:35:56.183862 == TX Byte 0 ==
6636 11:35:56.187580 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6637 11:35:56.193575 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6638 11:35:56.193650 == TX Byte 1 ==
6639 11:35:56.196956 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6640 11:35:56.203171 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6641 11:35:56.203245 ==
6642 11:35:56.206885 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 11:35:56.210198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 11:35:56.210273 ==
6645 11:35:56.210330
6646 11:35:56.210383
6647 11:35:56.213559 TX Vref Scan disable
6648 11:35:56.213633 == TX Byte 0 ==
6649 11:35:56.220526 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6650 11:35:56.223015 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6651 11:35:56.223090 == TX Byte 1 ==
6652 11:35:56.230718 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6653 11:35:56.233992 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6654 11:35:56.234067
6655 11:35:56.234123 [DATLAT]
6656 11:35:56.236435 Freq=400, CH1 RK1
6657 11:35:56.236508
6658 11:35:56.236565 DATLAT Default: 0xd
6659 11:35:56.240297 0, 0xFFFF, sum = 0
6660 11:35:56.240372 1, 0xFFFF, sum = 0
6661 11:35:56.243806 2, 0xFFFF, sum = 0
6662 11:35:56.243882 3, 0xFFFF, sum = 0
6663 11:35:56.246629 4, 0xFFFF, sum = 0
6664 11:35:56.246704 5, 0xFFFF, sum = 0
6665 11:35:56.249866 6, 0xFFFF, sum = 0
6666 11:35:56.249942 7, 0xFFFF, sum = 0
6667 11:35:56.252846 8, 0xFFFF, sum = 0
6668 11:35:56.252922 9, 0xFFFF, sum = 0
6669 11:35:56.256503 10, 0xFFFF, sum = 0
6670 11:35:56.256578 11, 0xFFFF, sum = 0
6671 11:35:56.259594 12, 0x0, sum = 1
6672 11:35:56.259669 13, 0x0, sum = 2
6673 11:35:56.262802 14, 0x0, sum = 3
6674 11:35:56.262877 15, 0x0, sum = 4
6675 11:35:56.266918 best_step = 13
6676 11:35:56.266992
6677 11:35:56.267049 ==
6678 11:35:56.269547 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 11:35:56.273691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6680 11:35:56.273766 ==
6681 11:35:56.276347 RX Vref Scan: 0
6682 11:35:56.276421
6683 11:35:56.276479 RX Vref 0 -> 0, step: 1
6684 11:35:56.276532
6685 11:35:56.279682 RX Delay -359 -> 252, step: 8
6686 11:35:56.287580 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6687 11:35:56.290834 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6688 11:35:56.294581 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6689 11:35:56.297795 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6690 11:35:56.305128 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6691 11:35:56.308668 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6692 11:35:56.311265 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6693 11:35:56.314214 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6694 11:35:56.321074 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6695 11:35:56.325126 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6696 11:35:56.327918 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6697 11:35:56.334475 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6698 11:35:56.337533 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6699 11:35:56.340694 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6700 11:35:56.344231 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6701 11:35:56.351054 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6702 11:35:56.351121 ==
6703 11:35:56.354662 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 11:35:56.357397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 11:35:56.357482 ==
6706 11:35:56.357561 DQS Delay:
6707 11:35:56.360516 DQS0 = 48, DQS1 = 64
6708 11:35:56.360579 DQM Delay:
6709 11:35:56.363953 DQM0 = 9, DQM1 = 15
6710 11:35:56.364010 DQ Delay:
6711 11:35:56.367638 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6712 11:35:56.371528 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6713 11:35:56.373385 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6714 11:35:56.377201 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6715 11:35:56.377299
6716 11:35:56.377351
6717 11:35:56.383448 [DQSOSCAuto] RK1, (LSB)MR18= 0xafaf, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6718 11:35:56.387417 CH1 RK1: MR19=C0C, MR18=AFAF
6719 11:35:56.393320 CH1_RK1: MR19=0xC0C, MR18=0xAFAF, DQSOSC=388, MR23=63, INC=392, DEC=261
6720 11:35:56.396978 [RxdqsGatingPostProcess] freq 400
6721 11:35:56.403247 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6722 11:35:56.406684 Pre-setting of DQS Precalculation
6723 11:35:56.410316 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6724 11:35:56.417072 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6725 11:35:56.423499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6726 11:35:56.423570
6727 11:35:56.423625
6728 11:35:56.426958 [Calibration Summary] 800 Mbps
6729 11:35:56.429870 CH 0, Rank 0
6730 11:35:56.429930 SW Impedance : PASS
6731 11:35:56.433134 DUTY Scan : NO K
6732 11:35:56.436624 ZQ Calibration : PASS
6733 11:35:56.436690 Jitter Meter : NO K
6734 11:35:56.439901 CBT Training : PASS
6735 11:35:56.443133 Write leveling : PASS
6736 11:35:56.443193 RX DQS gating : PASS
6737 11:35:56.446638 RX DQ/DQS(RDDQC) : PASS
6738 11:35:56.446698 TX DQ/DQS : PASS
6739 11:35:56.450479 RX DATLAT : PASS
6740 11:35:56.453500 RX DQ/DQS(Engine): PASS
6741 11:35:56.453562 TX OE : NO K
6742 11:35:56.456498 All Pass.
6743 11:35:56.456556
6744 11:35:56.456611 CH 0, Rank 1
6745 11:35:56.460217 SW Impedance : PASS
6746 11:35:56.460274 DUTY Scan : NO K
6747 11:35:56.463762 ZQ Calibration : PASS
6748 11:35:56.466765 Jitter Meter : NO K
6749 11:35:56.466828 CBT Training : PASS
6750 11:35:56.469999 Write leveling : NO K
6751 11:35:56.474341 RX DQS gating : PASS
6752 11:35:56.474401 RX DQ/DQS(RDDQC) : PASS
6753 11:35:56.476125 TX DQ/DQS : PASS
6754 11:35:56.479893 RX DATLAT : PASS
6755 11:35:56.479951 RX DQ/DQS(Engine): PASS
6756 11:35:56.482955 TX OE : NO K
6757 11:35:56.483013 All Pass.
6758 11:35:56.483063
6759 11:35:56.486408 CH 1, Rank 0
6760 11:35:56.486466 SW Impedance : PASS
6761 11:35:56.489622 DUTY Scan : NO K
6762 11:35:56.492977 ZQ Calibration : PASS
6763 11:35:56.493095 Jitter Meter : NO K
6764 11:35:56.496201 CBT Training : PASS
6765 11:35:56.499330 Write leveling : PASS
6766 11:35:56.499404 RX DQS gating : PASS
6767 11:35:56.503040 RX DQ/DQS(RDDQC) : PASS
6768 11:35:56.505911 TX DQ/DQS : PASS
6769 11:35:56.505986 RX DATLAT : PASS
6770 11:35:56.509963 RX DQ/DQS(Engine): PASS
6771 11:35:56.512447 TX OE : NO K
6772 11:35:56.512535 All Pass.
6773 11:35:56.512615
6774 11:35:56.512698 CH 1, Rank 1
6775 11:35:56.516135 SW Impedance : PASS
6776 11:35:56.520248 DUTY Scan : NO K
6777 11:35:56.520309 ZQ Calibration : PASS
6778 11:35:56.522811 Jitter Meter : NO K
6779 11:35:56.522874 CBT Training : PASS
6780 11:35:56.525783 Write leveling : NO K
6781 11:35:56.529217 RX DQS gating : PASS
6782 11:35:56.529319 RX DQ/DQS(RDDQC) : PASS
6783 11:35:56.532322 TX DQ/DQS : PASS
6784 11:35:56.536257 RX DATLAT : PASS
6785 11:35:56.536358 RX DQ/DQS(Engine): PASS
6786 11:35:56.539677 TX OE : NO K
6787 11:35:56.539749 All Pass.
6788 11:35:56.539805
6789 11:35:56.543048 DramC Write-DBI off
6790 11:35:56.545868 PER_BANK_REFRESH: Hybrid Mode
6791 11:35:56.545929 TX_TRACKING: ON
6792 11:35:56.555900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6793 11:35:56.558768 [FAST_K] Save calibration result to emmc
6794 11:35:56.562475 dramc_set_vcore_voltage set vcore to 725000
6795 11:35:56.565554 Read voltage for 1600, 0
6796 11:35:56.565633 Vio18 = 0
6797 11:35:56.569087 Vcore = 725000
6798 11:35:56.569172 Vdram = 0
6799 11:35:56.569287 Vddq = 0
6800 11:35:56.569375 Vmddr = 0
6801 11:35:56.575830 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6802 11:35:56.582341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6803 11:35:56.582413 MEM_TYPE=3, freq_sel=13
6804 11:35:56.585394 sv_algorithm_assistance_LP4_3733
6805 11:35:56.588796 ============ PULL DRAM RESETB DOWN ============
6806 11:35:56.594874 ========== PULL DRAM RESETB DOWN end =========
6807 11:35:56.598248 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6808 11:35:56.601803 ===================================
6809 11:35:56.605159 LPDDR4 DRAM CONFIGURATION
6810 11:35:56.608102 ===================================
6811 11:35:56.608172 EX_ROW_EN[0] = 0x0
6812 11:35:56.611415 EX_ROW_EN[1] = 0x0
6813 11:35:56.611480 LP4Y_EN = 0x0
6814 11:35:56.614894 WORK_FSP = 0x1
6815 11:35:56.614962 WL = 0x5
6816 11:35:56.618800 RL = 0x5
6817 11:35:56.621554 BL = 0x2
6818 11:35:56.621617 RPST = 0x0
6819 11:35:56.624895 RD_PRE = 0x0
6820 11:35:56.624970 WR_PRE = 0x1
6821 11:35:56.628332 WR_PST = 0x1
6822 11:35:56.628406 DBI_WR = 0x0
6823 11:35:56.631833 DBI_RD = 0x0
6824 11:35:56.631907 OTF = 0x1
6825 11:35:56.635266 ===================================
6826 11:35:56.638556 ===================================
6827 11:35:56.641898 ANA top config
6828 11:35:56.645017 ===================================
6829 11:35:56.645091 DLL_ASYNC_EN = 0
6830 11:35:56.648720 ALL_SLAVE_EN = 0
6831 11:35:56.651439 NEW_RANK_MODE = 1
6832 11:35:56.654607 DLL_IDLE_MODE = 1
6833 11:35:56.654681 LP45_APHY_COMB_EN = 1
6834 11:35:56.658310 TX_ODT_DIS = 0
6835 11:35:56.661205 NEW_8X_MODE = 1
6836 11:35:56.664561 ===================================
6837 11:35:56.668298 ===================================
6838 11:35:56.671570 data_rate = 3200
6839 11:35:56.675150 CKR = 1
6840 11:35:56.678163 DQ_P2S_RATIO = 8
6841 11:35:56.681092 ===================================
6842 11:35:56.681184 CA_P2S_RATIO = 8
6843 11:35:56.684429 DQ_CA_OPEN = 0
6844 11:35:56.688088 DQ_SEMI_OPEN = 0
6845 11:35:56.691156 CA_SEMI_OPEN = 0
6846 11:35:56.695012 CA_FULL_RATE = 0
6847 11:35:56.698399 DQ_CKDIV4_EN = 0
6848 11:35:56.698497 CA_CKDIV4_EN = 0
6849 11:35:56.701722 CA_PREDIV_EN = 0
6850 11:35:56.704347 PH8_DLY = 12
6851 11:35:56.707458 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6852 11:35:56.711039 DQ_AAMCK_DIV = 4
6853 11:35:56.714917 CA_AAMCK_DIV = 4
6854 11:35:56.715006 CA_ADMCK_DIV = 4
6855 11:35:56.718578 DQ_TRACK_CA_EN = 0
6856 11:35:56.721113 CA_PICK = 1600
6857 11:35:56.724662 CA_MCKIO = 1600
6858 11:35:56.727939 MCKIO_SEMI = 0
6859 11:35:56.731218 PLL_FREQ = 3068
6860 11:35:56.734275 DQ_UI_PI_RATIO = 32
6861 11:35:56.737642 CA_UI_PI_RATIO = 0
6862 11:35:56.737710 ===================================
6863 11:35:56.741240 ===================================
6864 11:35:56.743937 memory_type:LPDDR4
6865 11:35:56.748402 GP_NUM : 10
6866 11:35:56.748464 SRAM_EN : 1
6867 11:35:56.751521 MD32_EN : 0
6868 11:35:56.754485 ===================================
6869 11:35:56.757439 [ANA_INIT] >>>>>>>>>>>>>>
6870 11:35:56.761063 <<<<<< [CONFIGURE PHASE]: ANA_TX
6871 11:35:56.764149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6872 11:35:56.767834 ===================================
6873 11:35:56.770686 data_rate = 3200,PCW = 0X7600
6874 11:35:56.770744 ===================================
6875 11:35:56.777219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6876 11:35:56.780625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6877 11:35:56.787773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6878 11:35:56.790741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6879 11:35:56.794107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6880 11:35:56.797456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6881 11:35:56.800929 [ANA_INIT] flow start
6882 11:35:56.803474 [ANA_INIT] PLL >>>>>>>>
6883 11:35:56.803534 [ANA_INIT] PLL <<<<<<<<
6884 11:35:56.807794 [ANA_INIT] MIDPI >>>>>>>>
6885 11:35:56.809958 [ANA_INIT] MIDPI <<<<<<<<
6886 11:35:56.810018 [ANA_INIT] DLL >>>>>>>>
6887 11:35:56.813429 [ANA_INIT] DLL <<<<<<<<
6888 11:35:56.816933 [ANA_INIT] flow end
6889 11:35:56.819760 ============ LP4 DIFF to SE enter ============
6890 11:35:56.823955 ============ LP4 DIFF to SE exit ============
6891 11:35:56.826890 [ANA_INIT] <<<<<<<<<<<<<
6892 11:35:56.830486 [Flow] Enable top DCM control >>>>>
6893 11:35:56.833057 [Flow] Enable top DCM control <<<<<
6894 11:35:56.836641 Enable DLL master slave shuffle
6895 11:35:56.842851 ==============================================================
6896 11:35:56.842921 Gating Mode config
6897 11:35:56.850535 ==============================================================
6898 11:35:56.850606 Config description:
6899 11:35:56.859692 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6900 11:35:56.866487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6901 11:35:56.872858 SELPH_MODE 0: By rank 1: By Phase
6902 11:35:56.876871 ==============================================================
6903 11:35:56.879932 GAT_TRACK_EN = 1
6904 11:35:56.883356 RX_GATING_MODE = 2
6905 11:35:56.886629 RX_GATING_TRACK_MODE = 2
6906 11:35:56.890347 SELPH_MODE = 1
6907 11:35:56.892947 PICG_EARLY_EN = 1
6908 11:35:56.896604 VALID_LAT_VALUE = 1
6909 11:35:56.899891 ==============================================================
6910 11:35:56.902957 Enter into Gating configuration >>>>
6911 11:35:56.906095 Exit from Gating configuration <<<<
6912 11:35:56.910170 Enter into DVFS_PRE_config >>>>>
6913 11:35:56.923070 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6914 11:35:56.926356 Exit from DVFS_PRE_config <<<<<
6915 11:35:56.929760 Enter into PICG configuration >>>>
6916 11:35:56.929821 Exit from PICG configuration <<<<
6917 11:35:56.932583 [RX_INPUT] configuration >>>>>
6918 11:35:56.936171 [RX_INPUT] configuration <<<<<
6919 11:35:56.943057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6920 11:35:56.945807 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6921 11:35:56.953121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6922 11:35:56.959761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6923 11:35:56.966202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6924 11:35:56.972372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6925 11:35:56.975637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6926 11:35:56.979310 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6927 11:35:56.985755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6928 11:35:56.989419 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6929 11:35:56.992820 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6930 11:35:56.996001 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6931 11:35:56.998978 ===================================
6932 11:35:57.002185 LPDDR4 DRAM CONFIGURATION
6933 11:35:57.005876 ===================================
6934 11:35:57.009590 EX_ROW_EN[0] = 0x0
6935 11:35:57.009665 EX_ROW_EN[1] = 0x0
6936 11:35:57.012634 LP4Y_EN = 0x0
6937 11:35:57.012708 WORK_FSP = 0x1
6938 11:35:57.015957 WL = 0x5
6939 11:35:57.016032 RL = 0x5
6940 11:35:57.018737 BL = 0x2
6941 11:35:57.018812 RPST = 0x0
6942 11:35:57.022101 RD_PRE = 0x0
6943 11:35:57.022176 WR_PRE = 0x1
6944 11:35:57.025479 WR_PST = 0x1
6945 11:35:57.025552 DBI_WR = 0x0
6946 11:35:57.028906 DBI_RD = 0x0
6947 11:35:57.032220 OTF = 0x1
6948 11:35:57.035665 ===================================
6949 11:35:57.038870 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6950 11:35:57.042308 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6951 11:35:57.045423 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6952 11:35:57.049084 ===================================
6953 11:35:57.052647 LPDDR4 DRAM CONFIGURATION
6954 11:35:57.055639 ===================================
6955 11:35:57.059851 EX_ROW_EN[0] = 0x10
6956 11:35:57.059925 EX_ROW_EN[1] = 0x0
6957 11:35:57.061956 LP4Y_EN = 0x0
6958 11:35:57.062029 WORK_FSP = 0x1
6959 11:35:57.065196 WL = 0x5
6960 11:35:57.065319 RL = 0x5
6961 11:35:57.068774 BL = 0x2
6962 11:35:57.068848 RPST = 0x0
6963 11:35:57.072582 RD_PRE = 0x0
6964 11:35:57.072656 WR_PRE = 0x1
6965 11:35:57.075302 WR_PST = 0x1
6966 11:35:57.075376 DBI_WR = 0x0
6967 11:35:57.079017 DBI_RD = 0x0
6968 11:35:57.079091 OTF = 0x1
6969 11:35:57.082153 ===================================
6970 11:35:57.088688 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6971 11:35:57.088767 ==
6972 11:35:57.092208 Dram Type= 6, Freq= 0, CH_0, rank 0
6973 11:35:57.098930 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6974 11:35:57.099005 ==
6975 11:35:57.099063 [Duty_Offset_Calibration]
6976 11:35:57.102021 B0:0 B1:2 CA:1
6977 11:35:57.102095
6978 11:35:57.105082 [DutyScan_Calibration_Flow] k_type=0
6979 11:35:57.114683
6980 11:35:57.114756 ==CLK 0==
6981 11:35:57.117905 Final CLK duty delay cell = 0
6982 11:35:57.121013 [0] MAX Duty = 5156%(X100), DQS PI = 22
6983 11:35:57.124823 [0] MIN Duty = 4907%(X100), DQS PI = 54
6984 11:35:57.127449 [0] AVG Duty = 5031%(X100)
6985 11:35:57.127523
6986 11:35:57.131876 CH0 CLK Duty spec in!! Max-Min= 249%
6987 11:35:57.134835 [DutyScan_Calibration_Flow] ====Done====
6988 11:35:57.134909
6989 11:35:57.137904 [DutyScan_Calibration_Flow] k_type=1
6990 11:35:57.154714
6991 11:35:57.154788 ==DQS 0 ==
6992 11:35:57.157485 Final DQS duty delay cell = 0
6993 11:35:57.161059 [0] MAX Duty = 5156%(X100), DQS PI = 34
6994 11:35:57.164828 [0] MIN Duty = 5031%(X100), DQS PI = 8
6995 11:35:57.164903 [0] AVG Duty = 5093%(X100)
6996 11:35:57.167702
6997 11:35:57.167807 ==DQS 1 ==
6998 11:35:57.170976 Final DQS duty delay cell = 0
6999 11:35:57.174350 [0] MAX Duty = 5031%(X100), DQS PI = 2
7000 11:35:57.177704 [0] MIN Duty = 4876%(X100), DQS PI = 16
7001 11:35:57.177778 [0] AVG Duty = 4953%(X100)
7002 11:35:57.181180
7003 11:35:57.184370 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7004 11:35:57.184444
7005 11:35:57.187739 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7006 11:35:57.191442 [DutyScan_Calibration_Flow] ====Done====
7007 11:35:57.191516
7008 11:35:57.194311 [DutyScan_Calibration_Flow] k_type=3
7009 11:35:57.211262
7010 11:35:57.211336 ==DQM 0 ==
7011 11:35:57.214880 Final DQM duty delay cell = 0
7012 11:35:57.218495 [0] MAX Duty = 5187%(X100), DQS PI = 24
7013 11:35:57.221518 [0] MIN Duty = 4907%(X100), DQS PI = 56
7014 11:35:57.224700 [0] AVG Duty = 5047%(X100)
7015 11:35:57.224775
7016 11:35:57.224832 ==DQM 1 ==
7017 11:35:57.228529 Final DQM duty delay cell = 0
7018 11:35:57.231959 [0] MAX Duty = 5031%(X100), DQS PI = 50
7019 11:35:57.234735 [0] MIN Duty = 4782%(X100), DQS PI = 14
7020 11:35:57.238331 [0] AVG Duty = 4906%(X100)
7021 11:35:57.238405
7022 11:35:57.241187 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7023 11:35:57.241268
7024 11:35:57.248354 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7025 11:35:57.248608 [DutyScan_Calibration_Flow] ====Done====
7026 11:35:57.248669
7027 11:35:57.251044 [DutyScan_Calibration_Flow] k_type=2
7028 11:35:57.268107
7029 11:35:57.268181 ==DQ 0 ==
7030 11:35:57.271339 Final DQ duty delay cell = 0
7031 11:35:57.274817 [0] MAX Duty = 5218%(X100), DQS PI = 18
7032 11:35:57.278451 [0] MIN Duty = 4938%(X100), DQS PI = 54
7033 11:35:57.278525 [0] AVG Duty = 5078%(X100)
7034 11:35:57.281459
7035 11:35:57.281533 ==DQ 1 ==
7036 11:35:57.285120 Final DQ duty delay cell = -4
7037 11:35:57.288439 [-4] MAX Duty = 5094%(X100), DQS PI = 6
7038 11:35:57.291403 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7039 11:35:57.294224 [-4] AVG Duty = 4969%(X100)
7040 11:35:57.294299
7041 11:35:57.298090 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7042 11:35:57.298164
7043 11:35:57.301335 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7044 11:35:57.304925 [DutyScan_Calibration_Flow] ====Done====
7045 11:35:57.304999 ==
7046 11:35:57.308496 Dram Type= 6, Freq= 0, CH_1, rank 0
7047 11:35:57.311187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7048 11:35:57.311261 ==
7049 11:35:57.314333 [Duty_Offset_Calibration]
7050 11:35:57.314407 B0:0 B1:4 CA:-5
7051 11:35:57.314464
7052 11:35:57.319024 [DutyScan_Calibration_Flow] k_type=0
7053 11:35:57.328623
7054 11:35:57.328696 ==CLK 0==
7055 11:35:57.332010 Final CLK duty delay cell = 0
7056 11:35:57.335288 [0] MAX Duty = 5156%(X100), DQS PI = 18
7057 11:35:57.338957 [0] MIN Duty = 4906%(X100), DQS PI = 50
7058 11:35:57.339032 [0] AVG Duty = 5031%(X100)
7059 11:35:57.342272
7060 11:35:57.345146 CH1 CLK Duty spec in!! Max-Min= 250%
7061 11:35:57.348667 [DutyScan_Calibration_Flow] ====Done====
7062 11:35:57.348741
7063 11:35:57.351679 [DutyScan_Calibration_Flow] k_type=1
7064 11:35:57.367624
7065 11:35:57.367698 ==DQS 0 ==
7066 11:35:57.371390 Final DQS duty delay cell = 0
7067 11:35:57.373826 [0] MAX Duty = 5187%(X100), DQS PI = 20
7068 11:35:57.377552 [0] MIN Duty = 4876%(X100), DQS PI = 42
7069 11:35:57.380557 [0] AVG Duty = 5031%(X100)
7070 11:35:57.380630
7071 11:35:57.380687 ==DQS 1 ==
7072 11:35:57.383977 Final DQS duty delay cell = -4
7073 11:35:57.387986 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7074 11:35:57.390812 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7075 11:35:57.394141 [-4] AVG Duty = 4922%(X100)
7076 11:35:57.394216
7077 11:35:57.397472 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7078 11:35:57.397546
7079 11:35:57.401045 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7080 11:35:57.405019 [DutyScan_Calibration_Flow] ====Done====
7081 11:35:57.405087
7082 11:35:57.406755 [DutyScan_Calibration_Flow] k_type=3
7083 11:35:57.423286
7084 11:35:57.423360 ==DQM 0 ==
7085 11:35:57.426824 Final DQM duty delay cell = -4
7086 11:35:57.430439 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7087 11:35:57.433626 [-4] MIN Duty = 4782%(X100), DQS PI = 42
7088 11:35:57.436493 [-4] AVG Duty = 4922%(X100)
7089 11:35:57.436566
7090 11:35:57.436623 ==DQM 1 ==
7091 11:35:57.440200 Final DQM duty delay cell = -4
7092 11:35:57.443219 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7093 11:35:57.446179 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7094 11:35:57.450257 [-4] AVG Duty = 4969%(X100)
7095 11:35:57.450320
7096 11:35:57.453394 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7097 11:35:57.453458
7098 11:35:57.456235 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7099 11:35:57.459754 [DutyScan_Calibration_Flow] ====Done====
7100 11:35:57.459821
7101 11:35:57.462864 [DutyScan_Calibration_Flow] k_type=2
7102 11:35:57.480983
7103 11:35:57.481049 ==DQ 0 ==
7104 11:35:57.484017 Final DQ duty delay cell = 0
7105 11:35:57.487545 [0] MAX Duty = 5093%(X100), DQS PI = 20
7106 11:35:57.490543 [0] MIN Duty = 4938%(X100), DQS PI = 46
7107 11:35:57.490603 [0] AVG Duty = 5015%(X100)
7108 11:35:57.494322
7109 11:35:57.494387 ==DQ 1 ==
7110 11:35:57.498101 Final DQ duty delay cell = 0
7111 11:35:57.501032 [0] MAX Duty = 5031%(X100), DQS PI = 2
7112 11:35:57.504113 [0] MIN Duty = 4876%(X100), DQS PI = 28
7113 11:35:57.504173 [0] AVG Duty = 4953%(X100)
7114 11:35:57.507539
7115 11:35:57.510678 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7116 11:35:57.510740
7117 11:35:57.513879 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7118 11:35:57.517135 [DutyScan_Calibration_Flow] ====Done====
7119 11:35:57.521333 nWR fixed to 30
7120 11:35:57.521396 [ModeRegInit_LP4] CH0 RK0
7121 11:35:57.525026 [ModeRegInit_LP4] CH0 RK1
7122 11:35:57.526964 [ModeRegInit_LP4] CH1 RK0
7123 11:35:57.530579 [ModeRegInit_LP4] CH1 RK1
7124 11:35:57.530639 match AC timing 4
7125 11:35:57.536928 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7126 11:35:57.540266 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7127 11:35:57.543964 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7128 11:35:57.550922 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7129 11:35:57.554053 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7130 11:35:57.554117 [MiockJmeterHQA]
7131 11:35:57.554170
7132 11:35:57.556929 [DramcMiockJmeter] u1RxGatingPI = 0
7133 11:35:57.560177 0 : 4254, 4029
7134 11:35:57.560241 4 : 4252, 4027
7135 11:35:57.563741 8 : 4363, 4137
7136 11:35:57.563801 12 : 4252, 4027
7137 11:35:57.563853 16 : 4252, 4027
7138 11:35:57.567827 20 : 4363, 4137
7139 11:35:57.567889 24 : 4362, 4137
7140 11:35:57.570067 28 : 4252, 4027
7141 11:35:57.570127 32 : 4253, 4027
7142 11:35:57.574397 36 : 4252, 4027
7143 11:35:57.574460 40 : 4360, 4138
7144 11:35:57.576938 44 : 4253, 4027
7145 11:35:57.576998 48 : 4361, 4137
7146 11:35:57.577049 52 : 4252, 4029
7147 11:35:57.579964 56 : 4250, 4026
7148 11:35:57.580024 60 : 4250, 4027
7149 11:35:57.583619 64 : 4253, 4029
7150 11:35:57.583681 68 : 4250, 4026
7151 11:35:57.587005 72 : 4250, 4026
7152 11:35:57.587068 76 : 4363, 4140
7153 11:35:57.590245 80 : 4249, 4027
7154 11:35:57.590308 84 : 4252, 4030
7155 11:35:57.590361 88 : 4250, 4027
7156 11:35:57.593629 92 : 4360, 4137
7157 11:35:57.593686 96 : 4250, 4027
7158 11:35:57.597194 100 : 4360, 2099
7159 11:35:57.597272 104 : 4360, 0
7160 11:35:57.599822 108 : 4252, 0
7161 11:35:57.599881 112 : 4252, 0
7162 11:35:57.599932 116 : 4250, 0
7163 11:35:57.603225 120 : 4250, 0
7164 11:35:57.603287 124 : 4363, 0
7165 11:35:57.603338 128 : 4250, 0
7166 11:35:57.606493 132 : 4250, 0
7167 11:35:57.606549 136 : 4361, 0
7168 11:35:57.609776 140 : 4360, 0
7169 11:35:57.609836 144 : 4249, 0
7170 11:35:57.609886 148 : 4250, 0
7171 11:35:57.612973 152 : 4250, 0
7172 11:35:57.613036 156 : 4249, 0
7173 11:35:57.616268 160 : 4250, 0
7174 11:35:57.616327 164 : 4253, 0
7175 11:35:57.616377 168 : 4250, 0
7176 11:35:57.620277 172 : 4250, 0
7177 11:35:57.620382 176 : 4250, 0
7178 11:35:57.623109 180 : 4252, 0
7179 11:35:57.623185 184 : 4250, 0
7180 11:35:57.623244 188 : 4361, 0
7181 11:35:57.626459 192 : 4360, 0
7182 11:35:57.626535 196 : 4249, 0
7183 11:35:57.629683 200 : 4250, 0
7184 11:35:57.629759 204 : 4253, 0
7185 11:35:57.629818 208 : 4249, 0
7186 11:35:57.633206 212 : 4250, 0
7187 11:35:57.633321 216 : 4253, 0
7188 11:35:57.636523 220 : 4250, 428
7189 11:35:57.636598 224 : 4361, 4074
7190 11:35:57.636657 228 : 4252, 4029
7191 11:35:57.640114 232 : 4249, 4027
7192 11:35:57.640189 236 : 4250, 4026
7193 11:35:57.643089 240 : 4252, 4029
7194 11:35:57.643165 244 : 4250, 4027
7195 11:35:57.646406 248 : 4250, 4027
7196 11:35:57.646482 252 : 4250, 4026
7197 11:35:57.650254 256 : 4253, 4029
7198 11:35:57.650330 260 : 4250, 4026
7199 11:35:57.653150 264 : 4360, 4137
7200 11:35:57.653271 268 : 4360, 4137
7201 11:35:57.656047 272 : 4250, 4027
7202 11:35:57.656123 276 : 4363, 4140
7203 11:35:57.659418 280 : 4360, 4137
7204 11:35:57.659493 284 : 4250, 4027
7205 11:35:57.659553 288 : 4250, 4026
7206 11:35:57.663646 292 : 4252, 4029
7207 11:35:57.663722 296 : 4250, 4027
7208 11:35:57.665994 300 : 4249, 4027
7209 11:35:57.666070 304 : 4250, 4026
7210 11:35:57.669542 308 : 4253, 4029
7211 11:35:57.669617 312 : 4250, 4027
7212 11:35:57.673511 316 : 4360, 4137
7213 11:35:57.673587 320 : 4360, 4137
7214 11:35:57.675881 324 : 4247, 4025
7215 11:35:57.675957 328 : 4363, 4140
7216 11:35:57.679569 332 : 4360, 4137
7217 11:35:57.679645 336 : 4249, 3921
7218 11:35:57.682720 340 : 4250, 1871
7219 11:35:57.682821
7220 11:35:57.682882 MIOCK jitter meter ch=0
7221 11:35:57.682936
7222 11:35:57.686258 1T = (340-100) = 240 dly cells
7223 11:35:57.692708 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7224 11:35:57.692783 ==
7225 11:35:57.696148 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 11:35:57.699015 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7227 11:35:57.699090 ==
7228 11:35:57.705840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7229 11:35:57.708994 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7230 11:35:57.712268 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7231 11:35:57.719455 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7232 11:35:57.728476 [CA 0] Center 41 (11~72) winsize 62
7233 11:35:57.731755 [CA 1] Center 41 (11~72) winsize 62
7234 11:35:57.734548 [CA 2] Center 37 (7~67) winsize 61
7235 11:35:57.737667 [CA 3] Center 37 (7~67) winsize 61
7236 11:35:57.741733 [CA 4] Center 35 (5~66) winsize 62
7237 11:35:57.745507 [CA 5] Center 35 (5~65) winsize 61
7238 11:35:57.745582
7239 11:35:57.747699 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7240 11:35:57.747773
7241 11:35:57.751300 [CATrainingPosCal] consider 1 rank data
7242 11:35:57.754799 u2DelayCellTimex100 = 271/100 ps
7243 11:35:57.757643 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7244 11:35:57.764482 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7245 11:35:57.767902 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7246 11:35:57.770817 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7247 11:35:57.773938 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7248 11:35:57.777507 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7249 11:35:57.777582
7250 11:35:57.781669 CA PerBit enable=1, Macro0, CA PI delay=35
7251 11:35:57.781767
7252 11:35:57.783923 [CBTSetCACLKResult] CA Dly = 35
7253 11:35:57.787520 CS Dly: 11 (0~42)
7254 11:35:57.791028 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7255 11:35:57.794392 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7256 11:35:57.794466 ==
7257 11:35:57.797361 Dram Type= 6, Freq= 0, CH_0, rank 1
7258 11:35:57.803975 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7259 11:35:57.804070 ==
7260 11:35:57.807220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7261 11:35:57.814455 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7262 11:35:57.817435 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7263 11:35:57.823383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7264 11:35:57.830633 [CA 0] Center 42 (12~73) winsize 62
7265 11:35:57.833819 [CA 1] Center 41 (11~72) winsize 62
7266 11:35:57.837338 [CA 2] Center 38 (9~68) winsize 60
7267 11:35:57.840386 [CA 3] Center 37 (7~67) winsize 61
7268 11:35:57.844581 [CA 4] Center 35 (5~65) winsize 61
7269 11:35:57.847621 [CA 5] Center 35 (5~66) winsize 62
7270 11:35:57.847696
7271 11:35:57.850281 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7272 11:35:57.850356
7273 11:35:57.853701 [CATrainingPosCal] consider 2 rank data
7274 11:35:57.857190 u2DelayCellTimex100 = 271/100 ps
7275 11:35:57.863811 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7276 11:35:57.867228 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7277 11:35:57.870577 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7278 11:35:57.873473 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7279 11:35:57.876824 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7280 11:35:57.880204 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7281 11:35:57.880280
7282 11:35:57.883700 CA PerBit enable=1, Macro0, CA PI delay=35
7283 11:35:57.883769
7284 11:35:57.886882 [CBTSetCACLKResult] CA Dly = 35
7285 11:35:57.890328 CS Dly: 11 (0~43)
7286 11:35:57.893180 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7287 11:35:57.897576 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7288 11:35:57.897651
7289 11:35:57.899890 ----->DramcWriteLeveling(PI) begin...
7290 11:35:57.899965 ==
7291 11:35:57.903245 Dram Type= 6, Freq= 0, CH_0, rank 0
7292 11:35:57.910076 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7293 11:35:57.910151 ==
7294 11:35:57.913701 Write leveling (Byte 0): 30 => 30
7295 11:35:57.913775 Write leveling (Byte 1): 27 => 27
7296 11:35:57.917829 DramcWriteLeveling(PI) end<-----
7297 11:35:57.917903
7298 11:35:57.920866 ==
7299 11:35:57.920943 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 11:35:57.926970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7301 11:35:57.927045 ==
7302 11:35:57.930316 [Gating] SW mode calibration
7303 11:35:57.937031 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7304 11:35:57.940019 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7305 11:35:57.946422 0 12 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7306 11:35:57.949667 0 12 4 | B1->B0 | 2424 3333 | 1 1 | (1 1) (0 0)
7307 11:35:57.953766 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7308 11:35:57.959726 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7309 11:35:57.962914 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 11:35:57.967014 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 11:35:57.972912 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 11:35:57.976874 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7313 11:35:57.979710 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
7314 11:35:57.987084 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
7315 11:35:57.991028 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7316 11:35:57.993127 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7317 11:35:57.999586 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 11:35:58.003835 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 11:35:58.006498 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 11:35:58.013749 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 11:35:58.016093 0 14 0 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7322 11:35:58.019435 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7323 11:35:58.026292 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7324 11:35:58.029084 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7325 11:35:58.033144 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 11:35:58.039172 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 11:35:58.042778 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 11:35:58.045757 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7329 11:35:58.052147 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 11:35:58.055660 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7331 11:35:58.058814 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7332 11:35:58.065822 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7333 11:35:58.068636 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7334 11:35:58.072275 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 11:35:58.078856 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 11:35:58.082097 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 11:35:58.085493 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 11:35:58.091940 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 11:35:58.096886 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 11:35:58.098648 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 11:35:58.101932 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 11:35:58.108800 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:35:58.111762 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:35:58.115354 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7345 11:35:58.121802 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7346 11:35:58.124961 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7347 11:35:58.128611 Total UI for P1: 0, mck2ui 16
7348 11:35:58.132541 best dqsien dly found for B0: ( 1, 0, 30)
7349 11:35:58.135496 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7350 11:35:58.142364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 11:35:58.142435 Total UI for P1: 0, mck2ui 16
7352 11:35:58.148405 best dqsien dly found for B1: ( 1, 1, 4)
7353 11:35:58.152019 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7354 11:35:58.155430 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7355 11:35:58.155499
7356 11:35:58.158789 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7357 11:35:58.162464 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7358 11:35:58.165451 [Gating] SW calibration Done
7359 11:35:58.165512 ==
7360 11:35:58.168690 Dram Type= 6, Freq= 0, CH_0, rank 0
7361 11:35:58.172369 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7362 11:35:58.172435 ==
7363 11:35:58.174959 RX Vref Scan: 0
7364 11:35:58.175023
7365 11:35:58.175074 RX Vref 0 -> 0, step: 1
7366 11:35:58.175123
7367 11:35:58.178627 RX Delay 0 -> 252, step: 8
7368 11:35:58.181684 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7369 11:35:58.188551 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7370 11:35:58.191436 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7371 11:35:58.195197 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7372 11:35:58.198388 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7373 11:35:58.201394 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7374 11:35:58.208449 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7375 11:35:58.212127 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7376 11:35:58.215210 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7377 11:35:58.218450 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7378 11:35:58.221842 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7379 11:35:58.228339 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7380 11:35:58.231351 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7381 11:35:58.234409 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7382 11:35:58.238701 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7383 11:35:58.244581 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7384 11:35:58.244683 ==
7385 11:35:58.247746 Dram Type= 6, Freq= 0, CH_0, rank 0
7386 11:35:58.251818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7387 11:35:58.251919 ==
7388 11:35:58.252001 DQS Delay:
7389 11:35:58.254768 DQS0 = 0, DQS1 = 0
7390 11:35:58.254856 DQM Delay:
7391 11:35:58.258855 DQM0 = 130, DQM1 = 124
7392 11:35:58.258926 DQ Delay:
7393 11:35:58.261591 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7394 11:35:58.264700 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7395 11:35:58.268072 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7396 11:35:58.270979 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7397 11:35:58.271040
7398 11:35:58.271092
7399 11:35:58.275068 ==
7400 11:35:58.275134 Dram Type= 6, Freq= 0, CH_0, rank 0
7401 11:35:58.281369 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7402 11:35:58.281432 ==
7403 11:35:58.281483
7404 11:35:58.281532
7405 11:35:58.284428 TX Vref Scan disable
7406 11:35:58.284487 == TX Byte 0 ==
7407 11:35:58.287697 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7408 11:35:58.294314 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7409 11:35:58.294377 == TX Byte 1 ==
7410 11:35:58.297461 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7411 11:35:58.304336 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7412 11:35:58.304399 ==
7413 11:35:58.307454 Dram Type= 6, Freq= 0, CH_0, rank 0
7414 11:35:58.310692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7415 11:35:58.310755 ==
7416 11:35:58.323842
7417 11:35:58.326960 TX Vref early break, caculate TX vref
7418 11:35:58.331175 TX Vref=16, minBit 9, minWin=22, winSum=376
7419 11:35:58.333833 TX Vref=18, minBit 8, minWin=22, winSum=382
7420 11:35:58.337494 TX Vref=20, minBit 8, minWin=23, winSum=388
7421 11:35:58.340760 TX Vref=22, minBit 8, minWin=23, winSum=401
7422 11:35:58.343530 TX Vref=24, minBit 8, minWin=24, winSum=407
7423 11:35:58.350205 TX Vref=26, minBit 8, minWin=24, winSum=411
7424 11:35:58.353881 TX Vref=28, minBit 8, minWin=24, winSum=416
7425 11:35:58.356782 TX Vref=30, minBit 0, minWin=25, winSum=407
7426 11:35:58.359808 TX Vref=32, minBit 8, minWin=23, winSum=401
7427 11:35:58.363157 TX Vref=34, minBit 8, minWin=23, winSum=393
7428 11:35:58.370038 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 30
7429 11:35:58.370114
7430 11:35:58.373148 Final TX Range 0 Vref 30
7431 11:35:58.373252
7432 11:35:58.373312 ==
7433 11:35:58.377630 Dram Type= 6, Freq= 0, CH_0, rank 0
7434 11:35:58.379873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7435 11:35:58.379948 ==
7436 11:35:58.380005
7437 11:35:58.380059
7438 11:35:58.383414 TX Vref Scan disable
7439 11:35:58.389838 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7440 11:35:58.389913 == TX Byte 0 ==
7441 11:35:58.393534 u2DelayCellOfst[0]=14 cells (4 PI)
7442 11:35:58.396422 u2DelayCellOfst[1]=18 cells (5 PI)
7443 11:35:58.399917 u2DelayCellOfst[2]=14 cells (4 PI)
7444 11:35:58.403395 u2DelayCellOfst[3]=10 cells (3 PI)
7445 11:35:58.406725 u2DelayCellOfst[4]=10 cells (3 PI)
7446 11:35:58.409704 u2DelayCellOfst[5]=0 cells (0 PI)
7447 11:35:58.413341 u2DelayCellOfst[6]=18 cells (5 PI)
7448 11:35:58.416729 u2DelayCellOfst[7]=18 cells (5 PI)
7449 11:35:58.420316 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7450 11:35:58.423096 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7451 11:35:58.426776 == TX Byte 1 ==
7452 11:35:58.429869 u2DelayCellOfst[8]=0 cells (0 PI)
7453 11:35:58.429943 u2DelayCellOfst[9]=0 cells (0 PI)
7454 11:35:58.432909 u2DelayCellOfst[10]=10 cells (3 PI)
7455 11:35:58.436058 u2DelayCellOfst[11]=3 cells (1 PI)
7456 11:35:58.440008 u2DelayCellOfst[12]=14 cells (4 PI)
7457 11:35:58.443186 u2DelayCellOfst[13]=18 cells (5 PI)
7458 11:35:58.446415 u2DelayCellOfst[14]=18 cells (5 PI)
7459 11:35:58.449464 u2DelayCellOfst[15]=14 cells (4 PI)
7460 11:35:58.453775 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7461 11:35:58.459341 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7462 11:35:58.459416 DramC Write-DBI on
7463 11:35:58.459473 ==
7464 11:35:58.463349 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 11:35:58.469885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7466 11:35:58.469960 ==
7467 11:35:58.470017
7468 11:35:58.470070
7469 11:35:58.470120 TX Vref Scan disable
7470 11:35:58.473463 == TX Byte 0 ==
7471 11:35:58.476868 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7472 11:35:58.480219 == TX Byte 1 ==
7473 11:35:58.483593 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7474 11:35:58.487394 DramC Write-DBI off
7475 11:35:58.487467
7476 11:35:58.487526 [DATLAT]
7477 11:35:58.487580 Freq=1600, CH0 RK0
7478 11:35:58.487631
7479 11:35:58.489863 DATLAT Default: 0xf
7480 11:35:58.489938 0, 0xFFFF, sum = 0
7481 11:35:58.493023 1, 0xFFFF, sum = 0
7482 11:35:58.496243 2, 0xFFFF, sum = 0
7483 11:35:58.496318 3, 0xFFFF, sum = 0
7484 11:35:58.500061 4, 0xFFFF, sum = 0
7485 11:35:58.500137 5, 0xFFFF, sum = 0
7486 11:35:58.503267 6, 0xFFFF, sum = 0
7487 11:35:58.503343 7, 0xFFFF, sum = 0
7488 11:35:58.506810 8, 0xFFFF, sum = 0
7489 11:35:58.506886 9, 0xFFFF, sum = 0
7490 11:35:58.509977 10, 0xFFFF, sum = 0
7491 11:35:58.510053 11, 0xFFFF, sum = 0
7492 11:35:58.513454 12, 0xBFF, sum = 0
7493 11:35:58.513529 13, 0x0, sum = 1
7494 11:35:58.516607 14, 0x0, sum = 2
7495 11:35:58.516682 15, 0x0, sum = 3
7496 11:35:58.520174 16, 0x0, sum = 4
7497 11:35:58.520249 best_step = 14
7498 11:35:58.520306
7499 11:35:58.520359 ==
7500 11:35:58.523135 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 11:35:58.526214 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7502 11:35:58.526289 ==
7503 11:35:58.529627 RX Vref Scan: 1
7504 11:35:58.529701
7505 11:35:58.532826 Set Vref Range= 24 -> 127
7506 11:35:58.532900
7507 11:35:58.532957 RX Vref 24 -> 127, step: 1
7508 11:35:58.536027
7509 11:35:58.536099 RX Delay 11 -> 252, step: 4
7510 11:35:58.536164
7511 11:35:58.539376 Set Vref, RX VrefLevel [Byte0]: 24
7512 11:35:58.543224 [Byte1]: 24
7513 11:35:58.546675
7514 11:35:58.546742 Set Vref, RX VrefLevel [Byte0]: 25
7515 11:35:58.549922 [Byte1]: 25
7516 11:35:58.557179
7517 11:35:58.557300 Set Vref, RX VrefLevel [Byte0]: 26
7518 11:35:58.557839 [Byte1]: 26
7519 11:35:58.561867
7520 11:35:58.561936 Set Vref, RX VrefLevel [Byte0]: 27
7521 11:35:58.564884 [Byte1]: 27
7522 11:35:58.569493
7523 11:35:58.569555 Set Vref, RX VrefLevel [Byte0]: 28
7524 11:35:58.572600 [Byte1]: 28
7525 11:35:58.577527
7526 11:35:58.577592 Set Vref, RX VrefLevel [Byte0]: 29
7527 11:35:58.580484 [Byte1]: 29
7528 11:35:58.585389
7529 11:35:58.585482 Set Vref, RX VrefLevel [Byte0]: 30
7530 11:35:58.587844 [Byte1]: 30
7531 11:35:58.592237
7532 11:35:58.592301 Set Vref, RX VrefLevel [Byte0]: 31
7533 11:35:58.596168 [Byte1]: 31
7534 11:35:58.600513
7535 11:35:58.600588 Set Vref, RX VrefLevel [Byte0]: 32
7536 11:35:58.603490 [Byte1]: 32
7537 11:35:58.607871
7538 11:35:58.607944 Set Vref, RX VrefLevel [Byte0]: 33
7539 11:35:58.610690 [Byte1]: 33
7540 11:35:58.614904
7541 11:35:58.614978 Set Vref, RX VrefLevel [Byte0]: 34
7542 11:35:58.618356 [Byte1]: 34
7543 11:35:58.622871
7544 11:35:58.622945 Set Vref, RX VrefLevel [Byte0]: 35
7545 11:35:58.627168 [Byte1]: 35
7546 11:35:58.630456
7547 11:35:58.630563 Set Vref, RX VrefLevel [Byte0]: 36
7548 11:35:58.633418 [Byte1]: 36
7549 11:35:58.637757
7550 11:35:58.637831 Set Vref, RX VrefLevel [Byte0]: 37
7551 11:35:58.642016 [Byte1]: 37
7552 11:35:58.645420
7553 11:35:58.645494 Set Vref, RX VrefLevel [Byte0]: 38
7554 11:35:58.649164 [Byte1]: 38
7555 11:35:58.653190
7556 11:35:58.653292 Set Vref, RX VrefLevel [Byte0]: 39
7557 11:35:58.656453 [Byte1]: 39
7558 11:35:58.661056
7559 11:35:58.661135 Set Vref, RX VrefLevel [Byte0]: 40
7560 11:35:58.664804 [Byte1]: 40
7561 11:35:58.668584
7562 11:35:58.668658 Set Vref, RX VrefLevel [Byte0]: 41
7563 11:35:58.671906 [Byte1]: 41
7564 11:35:58.676140
7565 11:35:58.676214 Set Vref, RX VrefLevel [Byte0]: 42
7566 11:35:58.679788 [Byte1]: 42
7567 11:35:58.683881
7568 11:35:58.683955 Set Vref, RX VrefLevel [Byte0]: 43
7569 11:35:58.686752 [Byte1]: 43
7570 11:35:58.691583
7571 11:35:58.691657 Set Vref, RX VrefLevel [Byte0]: 44
7572 11:35:58.694545 [Byte1]: 44
7573 11:35:58.699551
7574 11:35:58.699625 Set Vref, RX VrefLevel [Byte0]: 45
7575 11:35:58.702127 [Byte1]: 45
7576 11:35:58.706396
7577 11:35:58.706470 Set Vref, RX VrefLevel [Byte0]: 46
7578 11:35:58.710891 [Byte1]: 46
7579 11:35:58.714314
7580 11:35:58.714388 Set Vref, RX VrefLevel [Byte0]: 47
7581 11:35:58.717540 [Byte1]: 47
7582 11:35:58.721857
7583 11:35:58.721931 Set Vref, RX VrefLevel [Byte0]: 48
7584 11:35:58.725261 [Byte1]: 48
7585 11:35:58.730423
7586 11:35:58.730495 Set Vref, RX VrefLevel [Byte0]: 49
7587 11:35:58.732598 [Byte1]: 49
7588 11:35:58.737649
7589 11:35:58.737716 Set Vref, RX VrefLevel [Byte0]: 50
7590 11:35:58.740455 [Byte1]: 50
7591 11:35:58.744548
7592 11:35:58.744609 Set Vref, RX VrefLevel [Byte0]: 51
7593 11:35:58.747907 [Byte1]: 51
7594 11:35:58.752299
7595 11:35:58.752362 Set Vref, RX VrefLevel [Byte0]: 52
7596 11:35:58.755593 [Byte1]: 52
7597 11:35:58.759752
7598 11:35:58.759815 Set Vref, RX VrefLevel [Byte0]: 53
7599 11:35:58.763322 [Byte1]: 53
7600 11:35:58.767217
7601 11:35:58.767275 Set Vref, RX VrefLevel [Byte0]: 54
7602 11:35:58.771300 [Byte1]: 54
7603 11:35:58.775140
7604 11:35:58.775198 Set Vref, RX VrefLevel [Byte0]: 55
7605 11:35:58.778169 [Byte1]: 55
7606 11:35:58.782607
7607 11:35:58.782672 Set Vref, RX VrefLevel [Byte0]: 56
7608 11:35:58.785571 [Byte1]: 56
7609 11:35:58.790067
7610 11:35:58.790128 Set Vref, RX VrefLevel [Byte0]: 57
7611 11:35:58.793603 [Byte1]: 57
7612 11:35:58.797812
7613 11:35:58.797872 Set Vref, RX VrefLevel [Byte0]: 58
7614 11:35:58.801429 [Byte1]: 58
7615 11:35:58.805448
7616 11:35:58.805522 Set Vref, RX VrefLevel [Byte0]: 59
7617 11:35:58.809027 [Byte1]: 59
7618 11:35:58.813082
7619 11:35:58.813156 Set Vref, RX VrefLevel [Byte0]: 60
7620 11:35:58.816635 [Byte1]: 60
7621 11:35:58.820598
7622 11:35:58.820671 Set Vref, RX VrefLevel [Byte0]: 61
7623 11:35:58.824372 [Byte1]: 61
7624 11:35:58.828514
7625 11:35:58.828589 Set Vref, RX VrefLevel [Byte0]: 62
7626 11:35:58.831638 [Byte1]: 62
7627 11:35:58.835657
7628 11:35:58.835731 Set Vref, RX VrefLevel [Byte0]: 63
7629 11:35:58.840086 [Byte1]: 63
7630 11:35:58.844079
7631 11:35:58.844152 Set Vref, RX VrefLevel [Byte0]: 64
7632 11:35:58.847028 [Byte1]: 64
7633 11:35:58.851476
7634 11:35:58.851549 Set Vref, RX VrefLevel [Byte0]: 65
7635 11:35:58.854661 [Byte1]: 65
7636 11:35:58.858923
7637 11:35:58.858997 Set Vref, RX VrefLevel [Byte0]: 66
7638 11:35:58.862317 [Byte1]: 66
7639 11:35:58.866387
7640 11:35:58.866461 Set Vref, RX VrefLevel [Byte0]: 67
7641 11:35:58.869907 [Byte1]: 67
7642 11:35:58.874152
7643 11:35:58.874227 Set Vref, RX VrefLevel [Byte0]: 68
7644 11:35:58.877134 [Byte1]: 68
7645 11:35:58.881670
7646 11:35:58.881745 Set Vref, RX VrefLevel [Byte0]: 69
7647 11:35:58.885104 [Byte1]: 69
7648 11:35:58.889183
7649 11:35:58.889277 Set Vref, RX VrefLevel [Byte0]: 70
7650 11:35:58.892228 [Byte1]: 70
7651 11:35:58.896790
7652 11:35:58.896887 Set Vref, RX VrefLevel [Byte0]: 71
7653 11:35:58.900750 [Byte1]: 71
7654 11:35:58.904341
7655 11:35:58.904414 Set Vref, RX VrefLevel [Byte0]: 72
7656 11:35:58.907974 [Byte1]: 72
7657 11:35:58.911767
7658 11:35:58.911841 Set Vref, RX VrefLevel [Byte0]: 73
7659 11:35:58.915356 [Byte1]: 73
7660 11:35:58.919402
7661 11:35:58.919474 Final RX Vref Byte 0 = 52 to rank0
7662 11:35:58.923288 Final RX Vref Byte 1 = 56 to rank0
7663 11:35:58.926120 Final RX Vref Byte 0 = 52 to rank1
7664 11:35:58.930247 Final RX Vref Byte 1 = 56 to rank1==
7665 11:35:58.932855 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 11:35:58.939344 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7667 11:35:58.939419 ==
7668 11:35:58.939476 DQS Delay:
7669 11:35:58.942860 DQS0 = 0, DQS1 = 0
7670 11:35:58.942934 DQM Delay:
7671 11:35:58.942991 DQM0 = 126, DQM1 = 121
7672 11:35:58.945783 DQ Delay:
7673 11:35:58.949347 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7674 11:35:58.952479 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7675 11:35:58.956108 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7676 11:35:58.959207 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7677 11:35:58.959280
7678 11:35:58.959337
7679 11:35:58.959389
7680 11:35:58.962436 [DramC_TX_OE_Calibration] TA2
7681 11:35:58.965965 Original DQ_B0 (3 6) =30, OEN = 27
7682 11:35:58.969650 Original DQ_B1 (3 6) =30, OEN = 27
7683 11:35:58.973041 24, 0x0, End_B0=24 End_B1=24
7684 11:35:58.973150 25, 0x0, End_B0=25 End_B1=25
7685 11:35:58.975891 26, 0x0, End_B0=26 End_B1=26
7686 11:35:58.979079 27, 0x0, End_B0=27 End_B1=27
7687 11:35:58.982834 28, 0x0, End_B0=28 End_B1=28
7688 11:35:58.986136 29, 0x0, End_B0=29 End_B1=29
7689 11:35:58.986210 30, 0x0, End_B0=30 End_B1=30
7690 11:35:58.989132 31, 0x4141, End_B0=30 End_B1=30
7691 11:35:58.992445 Byte0 end_step=30 best_step=27
7692 11:35:58.995793 Byte1 end_step=30 best_step=27
7693 11:35:58.999068 Byte0 TX OE(2T, 0.5T) = (3, 3)
7694 11:35:59.002373 Byte1 TX OE(2T, 0.5T) = (3, 3)
7695 11:35:59.002446
7696 11:35:59.002502
7697 11:35:59.009452 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7698 11:35:59.011956 CH0 RK0: MR19=303, MR18=1C1C
7699 11:35:59.019062 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7700 11:35:59.019139
7701 11:35:59.022808 ----->DramcWriteLeveling(PI) begin...
7702 11:35:59.022882 ==
7703 11:35:59.025831 Dram Type= 6, Freq= 0, CH_0, rank 1
7704 11:35:59.028885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7705 11:35:59.028959 ==
7706 11:35:59.032633 Write leveling (Byte 0): 31 => 31
7707 11:35:59.035402 Write leveling (Byte 1): 28 => 28
7708 11:35:59.040095 DramcWriteLeveling(PI) end<-----
7709 11:35:59.040169
7710 11:35:59.040236 ==
7711 11:35:59.042436 Dram Type= 6, Freq= 0, CH_0, rank 1
7712 11:35:59.045188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7713 11:35:59.045279 ==
7714 11:35:59.049175 [Gating] SW mode calibration
7715 11:35:59.055544 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7716 11:35:59.062644 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7717 11:35:59.065914 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7718 11:35:59.072069 0 12 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7719 11:35:59.075044 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 11:35:59.078554 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 11:35:59.085882 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 11:35:59.088684 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 11:35:59.091663 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7724 11:35:59.098272 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7725 11:35:59.101850 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
7726 11:35:59.105221 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7727 11:35:59.111601 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 11:35:59.114907 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 11:35:59.118288 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 11:35:59.125806 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 11:35:59.128001 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 11:35:59.132033 0 13 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7733 11:35:59.134888 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7734 11:35:59.141300 0 14 4 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
7735 11:35:59.145120 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 11:35:59.148009 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 11:35:59.154642 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 11:35:59.158504 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 11:35:59.161214 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 11:35:59.167932 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7741 11:35:59.171281 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7742 11:35:59.174636 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7743 11:35:59.181463 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 11:35:59.185003 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 11:35:59.187651 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 11:35:59.194917 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:35:59.197630 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:35:59.200979 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:35:59.207553 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:35:59.211161 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 11:35:59.214331 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 11:35:59.221148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 11:35:59.224560 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 11:35:59.227887 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 11:35:59.234321 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 11:35:59.237931 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7757 11:35:59.241167 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7758 11:35:59.248283 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7759 11:35:59.248358 Total UI for P1: 0, mck2ui 16
7760 11:35:59.253821 best dqsien dly found for B0: ( 1, 0, 30)
7761 11:35:59.257325 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7762 11:35:59.261434 Total UI for P1: 0, mck2ui 16
7763 11:35:59.264161 best dqsien dly found for B1: ( 1, 1, 2)
7764 11:35:59.267438 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7765 11:35:59.270951 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7766 11:35:59.271024
7767 11:35:59.274112 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7768 11:35:59.277612 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7769 11:35:59.280669 [Gating] SW calibration Done
7770 11:35:59.280742 ==
7771 11:35:59.284153 Dram Type= 6, Freq= 0, CH_0, rank 1
7772 11:35:59.286987 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7773 11:35:59.287060 ==
7774 11:35:59.290692 RX Vref Scan: 0
7775 11:35:59.290789
7776 11:35:59.293783 RX Vref 0 -> 0, step: 1
7777 11:35:59.293885
7778 11:35:59.293971 RX Delay 0 -> 252, step: 8
7779 11:35:59.300599 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7780 11:35:59.304147 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7781 11:35:59.307320 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7782 11:35:59.310511 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7783 11:35:59.313922 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7784 11:35:59.320304 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7785 11:35:59.323422 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7786 11:35:59.326876 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7787 11:35:59.330905 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7788 11:35:59.333871 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7789 11:35:59.340335 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7790 11:35:59.344100 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7791 11:35:59.348608 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7792 11:35:59.350233 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7793 11:35:59.357455 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7794 11:35:59.360173 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7795 11:35:59.360248 ==
7796 11:35:59.363469 Dram Type= 6, Freq= 0, CH_0, rank 1
7797 11:35:59.366760 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7798 11:35:59.366835 ==
7799 11:35:59.366893 DQS Delay:
7800 11:35:59.370492 DQS0 = 0, DQS1 = 0
7801 11:35:59.370566 DQM Delay:
7802 11:35:59.373217 DQM0 = 130, DQM1 = 124
7803 11:35:59.373330 DQ Delay:
7804 11:35:59.377063 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7805 11:35:59.380768 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7806 11:35:59.383433 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7807 11:35:59.390028 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7808 11:35:59.390102
7809 11:35:59.390158
7810 11:35:59.390211 ==
7811 11:35:59.393988 Dram Type= 6, Freq= 0, CH_0, rank 1
7812 11:35:59.397723 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7813 11:35:59.397802 ==
7814 11:35:59.397861
7815 11:35:59.397913
7816 11:35:59.399769 TX Vref Scan disable
7817 11:35:59.399844 == TX Byte 0 ==
7818 11:35:59.406690 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7819 11:35:59.409928 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7820 11:35:59.410003 == TX Byte 1 ==
7821 11:35:59.416417 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7822 11:35:59.420245 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7823 11:35:59.420320 ==
7824 11:35:59.423203 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 11:35:59.426414 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 11:35:59.426489 ==
7827 11:35:59.441171
7828 11:35:59.444614 TX Vref early break, caculate TX vref
7829 11:35:59.447789 TX Vref=16, minBit 1, minWin=22, winSum=377
7830 11:35:59.451219 TX Vref=18, minBit 1, minWin=23, winSum=387
7831 11:35:59.454225 TX Vref=20, minBit 1, minWin=24, winSum=398
7832 11:35:59.457691 TX Vref=22, minBit 1, minWin=24, winSum=401
7833 11:35:59.461032 TX Vref=24, minBit 8, minWin=24, winSum=409
7834 11:35:59.467659 TX Vref=26, minBit 9, minWin=25, winSum=419
7835 11:35:59.471080 TX Vref=28, minBit 8, minWin=25, winSum=419
7836 11:35:59.474292 TX Vref=30, minBit 8, minWin=24, winSum=409
7837 11:35:59.477991 TX Vref=32, minBit 0, minWin=25, winSum=407
7838 11:35:59.481398 TX Vref=34, minBit 0, minWin=24, winSum=400
7839 11:35:59.485179 TX Vref=36, minBit 1, minWin=23, winSum=390
7840 11:35:59.491133 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 26
7841 11:35:59.491203
7842 11:35:59.494225 Final TX Range 0 Vref 26
7843 11:35:59.494285
7844 11:35:59.494335 ==
7845 11:35:59.497524 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 11:35:59.501323 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 11:35:59.501387 ==
7848 11:35:59.501438
7849 11:35:59.504202
7850 11:35:59.504260 TX Vref Scan disable
7851 11:35:59.511037 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7852 11:35:59.511102 == TX Byte 0 ==
7853 11:35:59.514642 u2DelayCellOfst[0]=14 cells (4 PI)
7854 11:35:59.517132 u2DelayCellOfst[1]=18 cells (5 PI)
7855 11:35:59.521186 u2DelayCellOfst[2]=14 cells (4 PI)
7856 11:35:59.524458 u2DelayCellOfst[3]=14 cells (4 PI)
7857 11:35:59.527644 u2DelayCellOfst[4]=10 cells (3 PI)
7858 11:35:59.530810 u2DelayCellOfst[5]=0 cells (0 PI)
7859 11:35:59.534386 u2DelayCellOfst[6]=18 cells (5 PI)
7860 11:35:59.537110 u2DelayCellOfst[7]=18 cells (5 PI)
7861 11:35:59.541162 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7862 11:35:59.543868 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7863 11:35:59.546851 == TX Byte 1 ==
7864 11:35:59.550395 u2DelayCellOfst[8]=3 cells (1 PI)
7865 11:35:59.553398 u2DelayCellOfst[9]=0 cells (0 PI)
7866 11:35:59.556659 u2DelayCellOfst[10]=10 cells (3 PI)
7867 11:35:59.560197 u2DelayCellOfst[11]=3 cells (1 PI)
7868 11:35:59.563611 u2DelayCellOfst[12]=14 cells (4 PI)
7869 11:35:59.563678 u2DelayCellOfst[13]=14 cells (4 PI)
7870 11:35:59.566858 u2DelayCellOfst[14]=18 cells (5 PI)
7871 11:35:59.570816 u2DelayCellOfst[15]=14 cells (4 PI)
7872 11:35:59.576622 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7873 11:35:59.580473 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7874 11:35:59.580546 DramC Write-DBI on
7875 11:35:59.583599 ==
7876 11:35:59.586936 Dram Type= 6, Freq= 0, CH_0, rank 1
7877 11:35:59.590421 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7878 11:35:59.590492 ==
7879 11:35:59.590547
7880 11:35:59.590598
7881 11:35:59.593987 TX Vref Scan disable
7882 11:35:59.594052 == TX Byte 0 ==
7883 11:35:59.600976 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7884 11:35:59.601044 == TX Byte 1 ==
7885 11:35:59.603298 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7886 11:35:59.606998 DramC Write-DBI off
7887 11:35:59.607061
7888 11:35:59.607113 [DATLAT]
7889 11:35:59.609953 Freq=1600, CH0 RK1
7890 11:35:59.610011
7891 11:35:59.610061 DATLAT Default: 0xe
7892 11:35:59.613737 0, 0xFFFF, sum = 0
7893 11:35:59.613800 1, 0xFFFF, sum = 0
7894 11:35:59.616632 2, 0xFFFF, sum = 0
7895 11:35:59.616699 3, 0xFFFF, sum = 0
7896 11:35:59.621107 4, 0xFFFF, sum = 0
7897 11:35:59.621168 5, 0xFFFF, sum = 0
7898 11:35:59.623380 6, 0xFFFF, sum = 0
7899 11:35:59.626584 7, 0xFFFF, sum = 0
7900 11:35:59.626646 8, 0xFFFF, sum = 0
7901 11:35:59.629716 9, 0xFFFF, sum = 0
7902 11:35:59.629775 10, 0xFFFF, sum = 0
7903 11:35:59.632983 11, 0xFFFF, sum = 0
7904 11:35:59.633046 12, 0x8FFF, sum = 0
7905 11:35:59.636593 13, 0x0, sum = 1
7906 11:35:59.636652 14, 0x0, sum = 2
7907 11:35:59.640208 15, 0x0, sum = 3
7908 11:35:59.640271 16, 0x0, sum = 4
7909 11:35:59.642937 best_step = 14
7910 11:35:59.643001
7911 11:35:59.643054 ==
7912 11:35:59.646489 Dram Type= 6, Freq= 0, CH_0, rank 1
7913 11:35:59.649623 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7914 11:35:59.649690 ==
7915 11:35:59.649742 RX Vref Scan: 0
7916 11:35:59.649791
7917 11:35:59.652866 RX Vref 0 -> 0, step: 1
7918 11:35:59.652926
7919 11:35:59.656062 RX Delay 11 -> 252, step: 4
7920 11:35:59.659436 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7921 11:35:59.666266 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7922 11:35:59.669414 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7923 11:35:59.672493 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7924 11:35:59.676068 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7925 11:35:59.679898 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7926 11:35:59.685390 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7927 11:35:59.689235 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7928 11:35:59.692010 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7929 11:35:59.695489 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7930 11:35:59.700602 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7931 11:35:59.705203 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7932 11:35:59.709400 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7933 11:35:59.712409 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7934 11:35:59.715589 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7935 11:35:59.721735 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7936 11:35:59.721812 ==
7937 11:35:59.725455 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 11:35:59.728483 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 11:35:59.728545 ==
7940 11:35:59.728604 DQS Delay:
7941 11:35:59.732317 DQS0 = 0, DQS1 = 0
7942 11:35:59.732378 DQM Delay:
7943 11:35:59.735266 DQM0 = 128, DQM1 = 120
7944 11:35:59.735326 DQ Delay:
7945 11:35:59.738403 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7946 11:35:59.742228 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7947 11:35:59.745470 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7948 11:35:59.748558 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7949 11:35:59.748633
7950 11:35:59.748689
7951 11:35:59.751868
7952 11:35:59.751941 [DramC_TX_OE_Calibration] TA2
7953 11:35:59.755758 Original DQ_B0 (3 6) =30, OEN = 27
7954 11:35:59.758255 Original DQ_B1 (3 6) =30, OEN = 27
7955 11:35:59.761954 24, 0x0, End_B0=24 End_B1=24
7956 11:35:59.765501 25, 0x0, End_B0=25 End_B1=25
7957 11:35:59.768258 26, 0x0, End_B0=26 End_B1=26
7958 11:35:59.768332 27, 0x0, End_B0=27 End_B1=27
7959 11:35:59.771742 28, 0x0, End_B0=28 End_B1=28
7960 11:35:59.775209 29, 0x0, End_B0=29 End_B1=29
7961 11:35:59.778843 30, 0x0, End_B0=30 End_B1=30
7962 11:35:59.781652 31, 0x4141, End_B0=30 End_B1=30
7963 11:35:59.781728 Byte0 end_step=30 best_step=27
7964 11:35:59.784762 Byte1 end_step=30 best_step=27
7965 11:35:59.788071 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 11:35:59.791385 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 11:35:59.791478
7968 11:35:59.791563
7969 11:35:59.801149 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
7970 11:35:59.801252 CH0 RK1: MR19=303, MR18=2626
7971 11:35:59.807871 CH0_RK1: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
7972 11:35:59.811436 [RxdqsGatingPostProcess] freq 1600
7973 11:35:59.818149 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7974 11:35:59.821653 Pre-setting of DQS Precalculation
7975 11:35:59.824296 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7976 11:35:59.824388 ==
7977 11:35:59.827805 Dram Type= 6, Freq= 0, CH_1, rank 0
7978 11:35:59.831152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7979 11:35:59.834524 ==
7980 11:35:59.837902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7981 11:35:59.841214 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7982 11:35:59.847331 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7983 11:35:59.853882 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7984 11:35:59.861627 [CA 0] Center 41 (11~71) winsize 61
7985 11:35:59.864203 [CA 1] Center 41 (11~72) winsize 62
7986 11:35:59.867284 [CA 2] Center 37 (8~67) winsize 60
7987 11:35:59.870348 [CA 3] Center 36 (6~66) winsize 61
7988 11:35:59.875111 [CA 4] Center 34 (4~64) winsize 61
7989 11:35:59.877518 [CA 5] Center 34 (4~64) winsize 61
7990 11:35:59.877583
7991 11:35:59.880725 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7992 11:35:59.880813
7993 11:35:59.884425 [CATrainingPosCal] consider 1 rank data
7994 11:35:59.887895 u2DelayCellTimex100 = 271/100 ps
7995 11:35:59.891206 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
7996 11:35:59.897522 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
7997 11:35:59.901418 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7998 11:35:59.904121 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
7999 11:35:59.907377 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8000 11:35:59.910353 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8001 11:35:59.910419
8002 11:35:59.913891 CA PerBit enable=1, Macro0, CA PI delay=34
8003 11:35:59.913954
8004 11:35:59.916816 [CBTSetCACLKResult] CA Dly = 34
8005 11:35:59.920475 CS Dly: 8 (0~39)
8006 11:35:59.924098 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8007 11:35:59.928082 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8008 11:35:59.928172 ==
8009 11:35:59.930232 Dram Type= 6, Freq= 0, CH_1, rank 1
8010 11:35:59.936735 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8011 11:35:59.936825 ==
8012 11:35:59.940215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8013 11:35:59.944022 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8014 11:35:59.950263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8015 11:35:59.956754 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8016 11:35:59.963314 [CA 0] Center 40 (10~70) winsize 61
8017 11:35:59.966591 [CA 1] Center 39 (9~70) winsize 62
8018 11:35:59.969764 [CA 2] Center 35 (6~65) winsize 60
8019 11:35:59.973449 [CA 3] Center 35 (6~64) winsize 59
8020 11:35:59.976223 [CA 4] Center 32 (3~62) winsize 60
8021 11:35:59.979507 [CA 5] Center 32 (3~62) winsize 60
8022 11:35:59.979595
8023 11:35:59.984491 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8024 11:35:59.984580
8025 11:35:59.986545 [CATrainingPosCal] consider 2 rank data
8026 11:35:59.989948 u2DelayCellTimex100 = 271/100 ps
8027 11:35:59.993223 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8028 11:35:59.999684 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8029 11:36:00.003184 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8030 11:36:00.006813 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8031 11:36:00.010046 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8032 11:36:00.012881 CA5 delay=33 (4~62),Diff = 0 PI (0 cell)
8033 11:36:00.012983
8034 11:36:00.016472 CA PerBit enable=1, Macro0, CA PI delay=33
8035 11:36:00.016561
8036 11:36:00.020141 [CBTSetCACLKResult] CA Dly = 33
8037 11:36:00.023611 CS Dly: 9 (0~41)
8038 11:36:00.026039 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8039 11:36:00.029698 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8040 11:36:00.029790
8041 11:36:00.032299 ----->DramcWriteLeveling(PI) begin...
8042 11:36:00.032363 ==
8043 11:36:00.035737 Dram Type= 6, Freq= 0, CH_1, rank 0
8044 11:36:00.042202 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8045 11:36:00.042296 ==
8046 11:36:00.045354 Write leveling (Byte 0): 24 => 24
8047 11:36:00.049025 Write leveling (Byte 1): 22 => 22
8048 11:36:00.049114 DramcWriteLeveling(PI) end<-----
8049 11:36:00.049195
8050 11:36:00.052264 ==
8051 11:36:00.055476 Dram Type= 6, Freq= 0, CH_1, rank 0
8052 11:36:00.059398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8053 11:36:00.059492 ==
8054 11:36:00.061963 [Gating] SW mode calibration
8055 11:36:00.068533 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 11:36:00.072035 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8057 11:36:00.078838 0 12 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8058 11:36:00.082605 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8059 11:36:00.085211 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:36:00.092113 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:36:00.095698 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:36:00.099422 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:36:00.105289 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8064 11:36:00.108672 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8065 11:36:00.111688 0 13 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8066 11:36:00.118681 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8067 11:36:00.121844 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:36:00.125477 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:36:00.132157 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:36:00.135624 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:36:00.138533 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8072 11:36:00.145261 0 13 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8073 11:36:00.148691 0 14 0 | B1->B0 | 3838 4646 | 1 0 | (1 1) (0 0)
8074 11:36:00.151440 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:36:00.157992 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:36:00.161519 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:36:00.164627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:36:00.171514 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:36:00.175173 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:36:00.177974 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8081 11:36:00.185131 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 11:36:00.188037 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 11:36:00.191199 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:36:00.198334 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:36:00.200794 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:36:00.204053 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:36:00.211587 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:36:00.214791 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:36:00.218188 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:36:00.224484 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:36:00.227722 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:36:00.231313 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:36:00.237854 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:36:00.240808 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:36:00.244709 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 11:36:00.251018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 11:36:00.251112 Total UI for P1: 0, mck2ui 16
8098 11:36:00.254064 best dqsien dly found for B0: ( 1, 0, 24)
8099 11:36:00.260513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 11:36:00.264641 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 11:36:00.267079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:36:00.270445 Total UI for P1: 0, mck2ui 16
8103 11:36:00.273592 best dqsien dly found for B1: ( 1, 1, 0)
8104 11:36:00.277597 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8105 11:36:00.280343 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8106 11:36:00.284055
8107 11:36:00.287242 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8108 11:36:00.290377 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8109 11:36:00.294367 [Gating] SW calibration Done
8110 11:36:00.294437 ==
8111 11:36:00.296855 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 11:36:00.300129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 11:36:00.300217 ==
8114 11:36:00.300298 RX Vref Scan: 0
8115 11:36:00.303636
8116 11:36:00.303722 RX Vref 0 -> 0, step: 1
8117 11:36:00.303803
8118 11:36:00.306717 RX Delay 0 -> 252, step: 8
8119 11:36:00.310575 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 11:36:00.314623 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8121 11:36:00.320380 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8122 11:36:00.323638 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8123 11:36:00.326753 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8124 11:36:00.330303 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8125 11:36:00.333330 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8126 11:36:00.339880 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8127 11:36:00.343319 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8128 11:36:00.347290 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8129 11:36:00.349981 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8130 11:36:00.353361 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8131 11:36:00.360182 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8132 11:36:00.363655 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8133 11:36:00.366555 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 11:36:00.369457 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 11:36:00.369546 ==
8136 11:36:00.373098 Dram Type= 6, Freq= 0, CH_1, rank 0
8137 11:36:00.380080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8138 11:36:00.380173 ==
8139 11:36:00.380254 DQS Delay:
8140 11:36:00.382873 DQS0 = 0, DQS1 = 0
8141 11:36:00.382963 DQM Delay:
8142 11:36:00.386315 DQM0 = 130, DQM1 = 126
8143 11:36:00.386379 DQ Delay:
8144 11:36:00.389932 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8145 11:36:00.393376 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8146 11:36:00.396589 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8147 11:36:00.399590 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8148 11:36:00.399677
8149 11:36:00.399757
8150 11:36:00.399836 ==
8151 11:36:00.404159 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 11:36:00.409592 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 11:36:00.409681 ==
8154 11:36:00.409740
8155 11:36:00.409791
8156 11:36:00.409840 TX Vref Scan disable
8157 11:36:00.413362 == TX Byte 0 ==
8158 11:36:00.416083 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8159 11:36:00.419330 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8160 11:36:00.422673 == TX Byte 1 ==
8161 11:36:00.426357 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8162 11:36:00.432461 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8163 11:36:00.432531 ==
8164 11:36:00.436246 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 11:36:00.439330 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 11:36:00.439420 ==
8167 11:36:00.451365
8168 11:36:00.455231 TX Vref early break, caculate TX vref
8169 11:36:00.458421 TX Vref=16, minBit 0, minWin=22, winSum=373
8170 11:36:00.461995 TX Vref=18, minBit 0, minWin=23, winSum=382
8171 11:36:00.464710 TX Vref=20, minBit 3, minWin=23, winSum=389
8172 11:36:00.467919 TX Vref=22, minBit 0, minWin=24, winSum=404
8173 11:36:00.471262 TX Vref=24, minBit 0, minWin=25, winSum=408
8174 11:36:00.477706 TX Vref=26, minBit 0, minWin=25, winSum=414
8175 11:36:00.481682 TX Vref=28, minBit 3, minWin=24, winSum=414
8176 11:36:00.484403 TX Vref=30, minBit 3, minWin=24, winSum=408
8177 11:36:00.488444 TX Vref=32, minBit 3, minWin=24, winSum=400
8178 11:36:00.490959 TX Vref=34, minBit 7, minWin=23, winSum=391
8179 11:36:00.498199 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8180 11:36:00.498268
8181 11:36:00.501120 Final TX Range 0 Vref 26
8182 11:36:00.501207
8183 11:36:00.501275 ==
8184 11:36:00.504823 Dram Type= 6, Freq= 0, CH_1, rank 0
8185 11:36:00.507486 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8186 11:36:00.507576 ==
8187 11:36:00.507659
8188 11:36:00.507736
8189 11:36:00.510804 TX Vref Scan disable
8190 11:36:00.517841 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8191 11:36:00.517910 == TX Byte 0 ==
8192 11:36:00.520841 u2DelayCellOfst[0]=14 cells (4 PI)
8193 11:36:00.524539 u2DelayCellOfst[1]=10 cells (3 PI)
8194 11:36:00.528280 u2DelayCellOfst[2]=0 cells (0 PI)
8195 11:36:00.531135 u2DelayCellOfst[3]=7 cells (2 PI)
8196 11:36:00.534468 u2DelayCellOfst[4]=7 cells (2 PI)
8197 11:36:00.537587 u2DelayCellOfst[5]=14 cells (4 PI)
8198 11:36:00.541040 u2DelayCellOfst[6]=14 cells (4 PI)
8199 11:36:00.541130 u2DelayCellOfst[7]=7 cells (2 PI)
8200 11:36:00.547816 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8201 11:36:00.550979 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8202 11:36:00.554194 == TX Byte 1 ==
8203 11:36:00.554260 u2DelayCellOfst[8]=0 cells (0 PI)
8204 11:36:00.557856 u2DelayCellOfst[9]=3 cells (1 PI)
8205 11:36:00.560774 u2DelayCellOfst[10]=10 cells (3 PI)
8206 11:36:00.564173 u2DelayCellOfst[11]=3 cells (1 PI)
8207 11:36:00.567213 u2DelayCellOfst[12]=18 cells (5 PI)
8208 11:36:00.570401 u2DelayCellOfst[13]=18 cells (5 PI)
8209 11:36:00.574260 u2DelayCellOfst[14]=21 cells (6 PI)
8210 11:36:00.577117 u2DelayCellOfst[15]=18 cells (5 PI)
8211 11:36:00.580830 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8212 11:36:00.586925 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8213 11:36:00.587017 DramC Write-DBI on
8214 11:36:00.587099 ==
8215 11:36:00.590612 Dram Type= 6, Freq= 0, CH_1, rank 0
8216 11:36:00.593769 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8217 11:36:00.596870 ==
8218 11:36:00.596932
8219 11:36:00.596982
8220 11:36:00.597037 TX Vref Scan disable
8221 11:36:00.601196 == TX Byte 0 ==
8222 11:36:00.604064 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8223 11:36:00.607377 == TX Byte 1 ==
8224 11:36:00.611393 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8225 11:36:00.613628 DramC Write-DBI off
8226 11:36:00.613694
8227 11:36:00.613749 [DATLAT]
8228 11:36:00.613801 Freq=1600, CH1 RK0
8229 11:36:00.613852
8230 11:36:00.616974 DATLAT Default: 0xf
8231 11:36:00.620047 0, 0xFFFF, sum = 0
8232 11:36:00.620137 1, 0xFFFF, sum = 0
8233 11:36:00.624164 2, 0xFFFF, sum = 0
8234 11:36:00.624253 3, 0xFFFF, sum = 0
8235 11:36:00.627388 4, 0xFFFF, sum = 0
8236 11:36:00.627476 5, 0xFFFF, sum = 0
8237 11:36:00.630216 6, 0xFFFF, sum = 0
8238 11:36:00.630304 7, 0xFFFF, sum = 0
8239 11:36:00.633538 8, 0xFFFF, sum = 0
8240 11:36:00.633602 9, 0xFFFF, sum = 0
8241 11:36:00.636573 10, 0xFFFF, sum = 0
8242 11:36:00.636659 11, 0xFFFF, sum = 0
8243 11:36:00.640661 12, 0x8F7F, sum = 0
8244 11:36:00.640748 13, 0x0, sum = 1
8245 11:36:00.643564 14, 0x0, sum = 2
8246 11:36:00.643655 15, 0x0, sum = 3
8247 11:36:00.647135 16, 0x0, sum = 4
8248 11:36:00.647201 best_step = 14
8249 11:36:00.647253
8250 11:36:00.647303 ==
8251 11:36:00.649917 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 11:36:00.653332 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8253 11:36:00.656988 ==
8254 11:36:00.657074 RX Vref Scan: 1
8255 11:36:00.657154
8256 11:36:00.660523 Set Vref Range= 24 -> 127
8257 11:36:00.660584
8258 11:36:00.663436 RX Vref 24 -> 127, step: 1
8259 11:36:00.663496
8260 11:36:00.663549 RX Delay 3 -> 252, step: 4
8261 11:36:00.663600
8262 11:36:00.666863 Set Vref, RX VrefLevel [Byte0]: 24
8263 11:36:00.669827 [Byte1]: 24
8264 11:36:00.674907
8265 11:36:00.674967 Set Vref, RX VrefLevel [Byte0]: 25
8266 11:36:00.677699 [Byte1]: 25
8267 11:36:00.681453
8268 11:36:00.681515 Set Vref, RX VrefLevel [Byte0]: 26
8269 11:36:00.685222 [Byte1]: 26
8270 11:36:00.689223
8271 11:36:00.689324 Set Vref, RX VrefLevel [Byte0]: 27
8272 11:36:00.692616 [Byte1]: 27
8273 11:36:00.697076
8274 11:36:00.697162 Set Vref, RX VrefLevel [Byte0]: 28
8275 11:36:00.700201 [Byte1]: 28
8276 11:36:00.704422
8277 11:36:00.704507 Set Vref, RX VrefLevel [Byte0]: 29
8278 11:36:00.707480 [Byte1]: 29
8279 11:36:00.712390
8280 11:36:00.712452 Set Vref, RX VrefLevel [Byte0]: 30
8281 11:36:00.715465 [Byte1]: 30
8282 11:36:00.719894
8283 11:36:00.719983 Set Vref, RX VrefLevel [Byte0]: 31
8284 11:36:00.726940 [Byte1]: 31
8285 11:36:00.727033
8286 11:36:00.729899 Set Vref, RX VrefLevel [Byte0]: 32
8287 11:36:00.732965 [Byte1]: 32
8288 11:36:00.733052
8289 11:36:00.735918 Set Vref, RX VrefLevel [Byte0]: 33
8290 11:36:00.739630 [Byte1]: 33
8291 11:36:00.742782
8292 11:36:00.742876 Set Vref, RX VrefLevel [Byte0]: 34
8293 11:36:00.746242 [Byte1]: 34
8294 11:36:00.751699
8295 11:36:00.751794 Set Vref, RX VrefLevel [Byte0]: 35
8296 11:36:00.753943 [Byte1]: 35
8297 11:36:00.758409
8298 11:36:00.758487 Set Vref, RX VrefLevel [Byte0]: 36
8299 11:36:00.761183 [Byte1]: 36
8300 11:36:00.765742
8301 11:36:00.765805 Set Vref, RX VrefLevel [Byte0]: 37
8302 11:36:00.768589 [Byte1]: 37
8303 11:36:00.773716
8304 11:36:00.773811 Set Vref, RX VrefLevel [Byte0]: 38
8305 11:36:00.776678 [Byte1]: 38
8306 11:36:00.781081
8307 11:36:00.781155 Set Vref, RX VrefLevel [Byte0]: 39
8308 11:36:00.783997 [Byte1]: 39
8309 11:36:00.788475
8310 11:36:00.791866 Set Vref, RX VrefLevel [Byte0]: 40
8311 11:36:00.791940 [Byte1]: 40
8312 11:36:00.796374
8313 11:36:00.796447 Set Vref, RX VrefLevel [Byte0]: 41
8314 11:36:00.799665 [Byte1]: 41
8315 11:36:00.804791
8316 11:36:00.804888 Set Vref, RX VrefLevel [Byte0]: 42
8317 11:36:00.807129 [Byte1]: 42
8318 11:36:00.811961
8319 11:36:00.812034 Set Vref, RX VrefLevel [Byte0]: 43
8320 11:36:00.815509 [Byte1]: 43
8321 11:36:00.819268
8322 11:36:00.819341 Set Vref, RX VrefLevel [Byte0]: 44
8323 11:36:00.822377 [Byte1]: 44
8324 11:36:00.827485
8325 11:36:00.827558 Set Vref, RX VrefLevel [Byte0]: 45
8326 11:36:00.830067 [Byte1]: 45
8327 11:36:00.834455
8328 11:36:00.834528 Set Vref, RX VrefLevel [Byte0]: 46
8329 11:36:00.838074 [Byte1]: 46
8330 11:36:00.842388
8331 11:36:00.842461 Set Vref, RX VrefLevel [Byte0]: 47
8332 11:36:00.846949 [Byte1]: 47
8333 11:36:00.850038
8334 11:36:00.850111 Set Vref, RX VrefLevel [Byte0]: 48
8335 11:36:00.852845 [Byte1]: 48
8336 11:36:00.857239
8337 11:36:00.857312 Set Vref, RX VrefLevel [Byte0]: 49
8338 11:36:00.861479 [Byte1]: 49
8339 11:36:00.864831
8340 11:36:00.864903 Set Vref, RX VrefLevel [Byte0]: 50
8341 11:36:00.868164 [Byte1]: 50
8342 11:36:00.873418
8343 11:36:00.873490 Set Vref, RX VrefLevel [Byte0]: 51
8344 11:36:00.875899 [Byte1]: 51
8345 11:36:00.880526
8346 11:36:00.880599 Set Vref, RX VrefLevel [Byte0]: 52
8347 11:36:00.883856 [Byte1]: 52
8348 11:36:00.888053
8349 11:36:00.888126 Set Vref, RX VrefLevel [Byte0]: 53
8350 11:36:00.891501 [Byte1]: 53
8351 11:36:00.896072
8352 11:36:00.896148 Set Vref, RX VrefLevel [Byte0]: 54
8353 11:36:00.899012 [Byte1]: 54
8354 11:36:00.903268
8355 11:36:00.903341 Set Vref, RX VrefLevel [Byte0]: 55
8356 11:36:00.906632 [Byte1]: 55
8357 11:36:00.911442
8358 11:36:00.911581 Set Vref, RX VrefLevel [Byte0]: 56
8359 11:36:00.914316 [Byte1]: 56
8360 11:36:00.919476
8361 11:36:00.919550 Set Vref, RX VrefLevel [Byte0]: 57
8362 11:36:00.922154 [Byte1]: 57
8363 11:36:00.926353
8364 11:36:00.926453 Set Vref, RX VrefLevel [Byte0]: 58
8365 11:36:00.930223 [Byte1]: 58
8366 11:36:00.934158
8367 11:36:00.934254 Set Vref, RX VrefLevel [Byte0]: 59
8368 11:36:00.937432 [Byte1]: 59
8369 11:36:00.941548
8370 11:36:00.941644 Set Vref, RX VrefLevel [Byte0]: 60
8371 11:36:00.945752 [Byte1]: 60
8372 11:36:00.950482
8373 11:36:00.950573 Set Vref, RX VrefLevel [Byte0]: 61
8374 11:36:00.952686 [Byte1]: 61
8375 11:36:00.956999
8376 11:36:00.957088 Set Vref, RX VrefLevel [Byte0]: 62
8377 11:36:00.959861 [Byte1]: 62
8378 11:36:00.964829
8379 11:36:00.964918 Set Vref, RX VrefLevel [Byte0]: 63
8380 11:36:00.968105 [Byte1]: 63
8381 11:36:00.972134
8382 11:36:00.972220 Set Vref, RX VrefLevel [Byte0]: 64
8383 11:36:00.975639 [Byte1]: 64
8384 11:36:00.980110
8385 11:36:00.980195 Set Vref, RX VrefLevel [Byte0]: 65
8386 11:36:00.983008 [Byte1]: 65
8387 11:36:00.987547
8388 11:36:00.987637 Set Vref, RX VrefLevel [Byte0]: 66
8389 11:36:00.990829 [Byte1]: 66
8390 11:36:00.995233
8391 11:36:00.995325 Set Vref, RX VrefLevel [Byte0]: 67
8392 11:36:00.999247 [Byte1]: 67
8393 11:36:01.003339
8394 11:36:01.003428 Set Vref, RX VrefLevel [Byte0]: 68
8395 11:36:01.006288 [Byte1]: 68
8396 11:36:01.010218
8397 11:36:01.010306 Set Vref, RX VrefLevel [Byte0]: 69
8398 11:36:01.013940 [Byte1]: 69
8399 11:36:01.017891
8400 11:36:01.017982 Set Vref, RX VrefLevel [Byte0]: 70
8401 11:36:01.021367 [Byte1]: 70
8402 11:36:01.026011
8403 11:36:01.026082 Set Vref, RX VrefLevel [Byte0]: 71
8404 11:36:01.029444 [Byte1]: 71
8405 11:36:01.033351
8406 11:36:01.033419 Final RX Vref Byte 0 = 61 to rank0
8407 11:36:01.036899 Final RX Vref Byte 1 = 53 to rank0
8408 11:36:01.040136 Final RX Vref Byte 0 = 61 to rank1
8409 11:36:01.043474 Final RX Vref Byte 1 = 53 to rank1==
8410 11:36:01.046646 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 11:36:01.054169 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8412 11:36:01.054270 ==
8413 11:36:01.054355 DQS Delay:
8414 11:36:01.054437 DQS0 = 0, DQS1 = 0
8415 11:36:01.056680 DQM Delay:
8416 11:36:01.056767 DQM0 = 128, DQM1 = 124
8417 11:36:01.060349 DQ Delay:
8418 11:36:01.063425 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8419 11:36:01.066662 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8420 11:36:01.069734 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8421 11:36:01.073347 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8422 11:36:01.073421
8423 11:36:01.073488
8424 11:36:01.073567
8425 11:36:01.076539 [DramC_TX_OE_Calibration] TA2
8426 11:36:01.079709 Original DQ_B0 (3 6) =30, OEN = 27
8427 11:36:01.083135 Original DQ_B1 (3 6) =30, OEN = 27
8428 11:36:01.086466 24, 0x0, End_B0=24 End_B1=24
8429 11:36:01.086532 25, 0x0, End_B0=25 End_B1=25
8430 11:36:01.089728 26, 0x0, End_B0=26 End_B1=26
8431 11:36:01.093185 27, 0x0, End_B0=27 End_B1=27
8432 11:36:01.096588 28, 0x0, End_B0=28 End_B1=28
8433 11:36:01.099803 29, 0x0, End_B0=29 End_B1=29
8434 11:36:01.099896 30, 0x0, End_B0=30 End_B1=30
8435 11:36:01.103104 31, 0x4141, End_B0=30 End_B1=30
8436 11:36:01.106128 Byte0 end_step=30 best_step=27
8437 11:36:01.109376 Byte1 end_step=30 best_step=27
8438 11:36:01.113859 Byte0 TX OE(2T, 0.5T) = (3, 3)
8439 11:36:01.116439 Byte1 TX OE(2T, 0.5T) = (3, 3)
8440 11:36:01.116506
8441 11:36:01.116561
8442 11:36:01.123273 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8443 11:36:01.126156 CH1 RK0: MR19=303, MR18=2929
8444 11:36:01.132547 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8445 11:36:01.132638
8446 11:36:01.136537 ----->DramcWriteLeveling(PI) begin...
8447 11:36:01.136628 ==
8448 11:36:01.139778 Dram Type= 6, Freq= 0, CH_1, rank 1
8449 11:36:01.143150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8450 11:36:01.143225 ==
8451 11:36:01.146062 Write leveling (Byte 0): 23 => 23
8452 11:36:01.149281 Write leveling (Byte 1): 21 => 21
8453 11:36:01.153489 DramcWriteLeveling(PI) end<-----
8454 11:36:01.153563
8455 11:36:01.153619 ==
8456 11:36:01.156144 Dram Type= 6, Freq= 0, CH_1, rank 1
8457 11:36:01.159695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8458 11:36:01.159769 ==
8459 11:36:01.162717 [Gating] SW mode calibration
8460 11:36:01.169038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8461 11:36:01.176043 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8462 11:36:01.179225 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 11:36:01.185805 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 11:36:01.189115 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 11:36:01.193177 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 11:36:01.199281 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 11:36:01.202215 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8468 11:36:01.205509 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8469 11:36:01.212416 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8470 11:36:01.215431 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8471 11:36:01.219181 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 11:36:01.226294 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 11:36:01.228707 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 11:36:01.232362 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 11:36:01.238702 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8476 11:36:01.242123 0 13 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8477 11:36:01.245740 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8478 11:36:01.249714 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8479 11:36:01.255867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 11:36:01.259041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 11:36:01.262444 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 11:36:01.268710 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 11:36:01.271925 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 11:36:01.274926 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8485 11:36:01.281788 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8486 11:36:01.284827 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8487 11:36:01.288721 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:36:01.294820 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:36:01.298339 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:36:01.301754 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:36:01.307973 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:36:01.311695 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:36:01.315120 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:36:01.321486 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 11:36:01.324789 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 11:36:01.328326 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 11:36:01.334865 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 11:36:01.338445 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 11:36:01.341383 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8500 11:36:01.348694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8501 11:36:01.351468 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8502 11:36:01.354564 Total UI for P1: 0, mck2ui 16
8503 11:36:01.358060 best dqsien dly found for B0: ( 1, 0, 22)
8504 11:36:01.361519 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8505 11:36:01.368321 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8506 11:36:01.368412 Total UI for P1: 0, mck2ui 16
8507 11:36:01.375716 best dqsien dly found for B1: ( 1, 0, 30)
8508 11:36:01.378306 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8509 11:36:01.381185 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8510 11:36:01.381278
8511 11:36:01.384666 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8512 11:36:01.387653 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8513 11:36:01.391214 [Gating] SW calibration Done
8514 11:36:01.391279 ==
8515 11:36:01.394625 Dram Type= 6, Freq= 0, CH_1, rank 1
8516 11:36:01.397413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8517 11:36:01.397480 ==
8518 11:36:01.400700 RX Vref Scan: 0
8519 11:36:01.400762
8520 11:36:01.400818 RX Vref 0 -> 0, step: 1
8521 11:36:01.400871
8522 11:36:01.404484 RX Delay 0 -> 252, step: 8
8523 11:36:01.407502 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8524 11:36:01.414509 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8525 11:36:01.417299 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8526 11:36:01.421421 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8527 11:36:01.424700 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8528 11:36:01.427202 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8529 11:36:01.434633 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8530 11:36:01.437122 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8531 11:36:01.440420 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8532 11:36:01.444597 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8533 11:36:01.447385 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8534 11:36:01.453635 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8535 11:36:01.457191 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8536 11:36:01.460520 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8537 11:36:01.463595 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8538 11:36:01.470755 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8539 11:36:01.470826 ==
8540 11:36:01.473999 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 11:36:01.477665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 11:36:01.477730 ==
8543 11:36:01.477784 DQS Delay:
8544 11:36:01.481518 DQS0 = 0, DQS1 = 0
8545 11:36:01.481584 DQM Delay:
8546 11:36:01.483636 DQM0 = 130, DQM1 = 125
8547 11:36:01.483714 DQ Delay:
8548 11:36:01.486702 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8549 11:36:01.490253 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =127
8550 11:36:01.493555 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8551 11:36:01.497482 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8552 11:36:01.497556
8553 11:36:01.497612
8554 11:36:01.500195 ==
8555 11:36:01.503273 Dram Type= 6, Freq= 0, CH_1, rank 1
8556 11:36:01.506784 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8557 11:36:01.506858 ==
8558 11:36:01.506916
8559 11:36:01.506968
8560 11:36:01.510458 TX Vref Scan disable
8561 11:36:01.510533 == TX Byte 0 ==
8562 11:36:01.513537 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8563 11:36:01.520382 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8564 11:36:01.520457 == TX Byte 1 ==
8565 11:36:01.523876 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8566 11:36:01.529938 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8567 11:36:01.530013 ==
8568 11:36:01.533532 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 11:36:01.536418 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 11:36:01.536493 ==
8571 11:36:01.550745
8572 11:36:01.553737 TX Vref early break, caculate TX vref
8573 11:36:01.557083 TX Vref=16, minBit 5, minWin=21, winSum=376
8574 11:36:01.561166 TX Vref=18, minBit 1, minWin=22, winSum=387
8575 11:36:01.563586 TX Vref=20, minBit 0, minWin=23, winSum=394
8576 11:36:01.567524 TX Vref=22, minBit 0, minWin=24, winSum=404
8577 11:36:01.570296 TX Vref=24, minBit 0, minWin=24, winSum=412
8578 11:36:01.576747 TX Vref=26, minBit 0, minWin=24, winSum=418
8579 11:36:01.580411 TX Vref=28, minBit 0, minWin=23, winSum=418
8580 11:36:01.585007 TX Vref=30, minBit 0, minWin=23, winSum=413
8581 11:36:01.587142 TX Vref=32, minBit 0, minWin=22, winSum=403
8582 11:36:01.590135 TX Vref=34, minBit 0, minWin=23, winSum=398
8583 11:36:01.593390 TX Vref=36, minBit 0, minWin=22, winSum=393
8584 11:36:01.600669 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
8585 11:36:01.600742
8586 11:36:01.603996 Final TX Range 0 Vref 26
8587 11:36:01.604068
8588 11:36:01.604126 ==
8589 11:36:01.606520 Dram Type= 6, Freq= 0, CH_1, rank 1
8590 11:36:01.610008 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8591 11:36:01.610075 ==
8592 11:36:01.610131
8593 11:36:01.613262
8594 11:36:01.613327 TX Vref Scan disable
8595 11:36:01.619783 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8596 11:36:01.619855 == TX Byte 0 ==
8597 11:36:01.623587 u2DelayCellOfst[0]=18 cells (5 PI)
8598 11:36:01.626373 u2DelayCellOfst[1]=14 cells (4 PI)
8599 11:36:01.630517 u2DelayCellOfst[2]=0 cells (0 PI)
8600 11:36:01.633266 u2DelayCellOfst[3]=10 cells (3 PI)
8601 11:36:01.636644 u2DelayCellOfst[4]=10 cells (3 PI)
8602 11:36:01.639736 u2DelayCellOfst[5]=18 cells (5 PI)
8603 11:36:01.643821 u2DelayCellOfst[6]=18 cells (5 PI)
8604 11:36:01.646351 u2DelayCellOfst[7]=7 cells (2 PI)
8605 11:36:01.649931 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8606 11:36:01.653426 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8607 11:36:01.656826 == TX Byte 1 ==
8608 11:36:01.659598 u2DelayCellOfst[8]=0 cells (0 PI)
8609 11:36:01.663312 u2DelayCellOfst[9]=3 cells (1 PI)
8610 11:36:01.666437 u2DelayCellOfst[10]=10 cells (3 PI)
8611 11:36:01.669688 u2DelayCellOfst[11]=3 cells (1 PI)
8612 11:36:01.669757 u2DelayCellOfst[12]=14 cells (4 PI)
8613 11:36:01.673105 u2DelayCellOfst[13]=18 cells (5 PI)
8614 11:36:01.676276 u2DelayCellOfst[14]=18 cells (5 PI)
8615 11:36:01.679499 u2DelayCellOfst[15]=14 cells (4 PI)
8616 11:36:01.686915 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8617 11:36:01.689720 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8618 11:36:01.689785 DramC Write-DBI on
8619 11:36:01.692794 ==
8620 11:36:01.692859 Dram Type= 6, Freq= 0, CH_1, rank 1
8621 11:36:01.699350 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8622 11:36:01.699415 ==
8623 11:36:01.699473
8624 11:36:01.699526
8625 11:36:01.702682 TX Vref Scan disable
8626 11:36:01.702748 == TX Byte 0 ==
8627 11:36:01.709329 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8628 11:36:01.709402 == TX Byte 1 ==
8629 11:36:01.713345 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8630 11:36:01.716358 DramC Write-DBI off
8631 11:36:01.716427
8632 11:36:01.716483 [DATLAT]
8633 11:36:01.719139 Freq=1600, CH1 RK1
8634 11:36:01.719202
8635 11:36:01.719258 DATLAT Default: 0xe
8636 11:36:01.722364 0, 0xFFFF, sum = 0
8637 11:36:01.722424 1, 0xFFFF, sum = 0
8638 11:36:01.725619 2, 0xFFFF, sum = 0
8639 11:36:01.725684 3, 0xFFFF, sum = 0
8640 11:36:01.729147 4, 0xFFFF, sum = 0
8641 11:36:01.729257 5, 0xFFFF, sum = 0
8642 11:36:01.732939 6, 0xFFFF, sum = 0
8643 11:36:01.732998 7, 0xFFFF, sum = 0
8644 11:36:01.735560 8, 0xFFFF, sum = 0
8645 11:36:01.739790 9, 0xFFFF, sum = 0
8646 11:36:01.739849 10, 0xFFFF, sum = 0
8647 11:36:01.742297 11, 0xFFFF, sum = 0
8648 11:36:01.742359 12, 0xF5F, sum = 0
8649 11:36:01.746189 13, 0x0, sum = 1
8650 11:36:01.746256 14, 0x0, sum = 2
8651 11:36:01.746310 15, 0x0, sum = 3
8652 11:36:01.749618 16, 0x0, sum = 4
8653 11:36:01.749676 best_step = 14
8654 11:36:01.749727
8655 11:36:01.753234 ==
8656 11:36:01.753292 Dram Type= 6, Freq= 0, CH_1, rank 1
8657 11:36:01.759103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8658 11:36:01.759163 ==
8659 11:36:01.759213 RX Vref Scan: 0
8660 11:36:01.759266
8661 11:36:01.762389 RX Vref 0 -> 0, step: 1
8662 11:36:01.762453
8663 11:36:01.765594 RX Delay 3 -> 252, step: 4
8664 11:36:01.769261 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8665 11:36:01.772017 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8666 11:36:01.779313 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8667 11:36:01.781928 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8668 11:36:01.785855 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8669 11:36:01.790538 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8670 11:36:01.792138 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8671 11:36:01.799035 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8672 11:36:01.801854 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8673 11:36:01.805374 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8674 11:36:01.809513 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8675 11:36:01.811971 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8676 11:36:01.818966 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8677 11:36:01.821939 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8678 11:36:01.825455 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8679 11:36:01.828263 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8680 11:36:01.828337 ==
8681 11:36:01.831853 Dram Type= 6, Freq= 0, CH_1, rank 1
8682 11:36:01.838461 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8683 11:36:01.838537 ==
8684 11:36:01.838595 DQS Delay:
8685 11:36:01.841991 DQS0 = 0, DQS1 = 0
8686 11:36:01.842065 DQM Delay:
8687 11:36:01.845190 DQM0 = 127, DQM1 = 123
8688 11:36:01.845312 DQ Delay:
8689 11:36:01.848195 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8690 11:36:01.851643 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8691 11:36:01.854631 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114
8692 11:36:01.858583 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8693 11:36:01.858658
8694 11:36:01.858714
8695 11:36:01.858766
8696 11:36:01.862034 [DramC_TX_OE_Calibration] TA2
8697 11:36:01.865020 Original DQ_B0 (3 6) =30, OEN = 27
8698 11:36:01.867890 Original DQ_B1 (3 6) =30, OEN = 27
8699 11:36:01.871389 24, 0x0, End_B0=24 End_B1=24
8700 11:36:01.874691 25, 0x0, End_B0=25 End_B1=25
8701 11:36:01.874767 26, 0x0, End_B0=26 End_B1=26
8702 11:36:01.878926 27, 0x0, End_B0=27 End_B1=27
8703 11:36:01.881703 28, 0x0, End_B0=28 End_B1=28
8704 11:36:01.884461 29, 0x0, End_B0=29 End_B1=29
8705 11:36:01.887907 30, 0x0, End_B0=30 End_B1=30
8706 11:36:01.887981 31, 0x4141, End_B0=30 End_B1=30
8707 11:36:01.892711 Byte0 end_step=30 best_step=27
8708 11:36:01.895167 Byte1 end_step=30 best_step=27
8709 11:36:01.899516 Byte0 TX OE(2T, 0.5T) = (3, 3)
8710 11:36:01.900937 Byte1 TX OE(2T, 0.5T) = (3, 3)
8711 11:36:01.901010
8712 11:36:01.901067
8713 11:36:01.908030 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8714 11:36:01.911615 CH1 RK1: MR19=303, MR18=1C1C
8715 11:36:01.917293 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8716 11:36:01.920952 [RxdqsGatingPostProcess] freq 1600
8717 11:36:01.927355 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8718 11:36:01.930850 Pre-setting of DQS Precalculation
8719 11:36:01.934325 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8720 11:36:01.940459 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8721 11:36:01.947181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8722 11:36:01.947256
8723 11:36:01.947313
8724 11:36:01.951784 [Calibration Summary] 3200 Mbps
8725 11:36:01.954203 CH 0, Rank 0
8726 11:36:01.954277 SW Impedance : PASS
8727 11:36:01.957814 DUTY Scan : NO K
8728 11:36:01.961985 ZQ Calibration : PASS
8729 11:36:01.962059 Jitter Meter : NO K
8730 11:36:01.963845 CBT Training : PASS
8731 11:36:01.967037 Write leveling : PASS
8732 11:36:01.967111 RX DQS gating : PASS
8733 11:36:01.970447 RX DQ/DQS(RDDQC) : PASS
8734 11:36:01.973929 TX DQ/DQS : PASS
8735 11:36:01.974004 RX DATLAT : PASS
8736 11:36:01.977240 RX DQ/DQS(Engine): PASS
8737 11:36:01.980689 TX OE : PASS
8738 11:36:01.980763 All Pass.
8739 11:36:01.980820
8740 11:36:01.980873 CH 0, Rank 1
8741 11:36:01.983906 SW Impedance : PASS
8742 11:36:01.986918 DUTY Scan : NO K
8743 11:36:01.986991 ZQ Calibration : PASS
8744 11:36:01.990057 Jitter Meter : NO K
8745 11:36:01.993576 CBT Training : PASS
8746 11:36:01.993649 Write leveling : PASS
8747 11:36:01.997163 RX DQS gating : PASS
8748 11:36:01.997244 RX DQ/DQS(RDDQC) : PASS
8749 11:36:01.999874 TX DQ/DQS : PASS
8750 11:36:02.003138 RX DATLAT : PASS
8751 11:36:02.003211 RX DQ/DQS(Engine): PASS
8752 11:36:02.007007 TX OE : PASS
8753 11:36:02.007082 All Pass.
8754 11:36:02.007139
8755 11:36:02.010203 CH 1, Rank 0
8756 11:36:02.010277 SW Impedance : PASS
8757 11:36:02.013284 DUTY Scan : NO K
8758 11:36:02.016610 ZQ Calibration : PASS
8759 11:36:02.016683 Jitter Meter : NO K
8760 11:36:02.020107 CBT Training : PASS
8761 11:36:02.023156 Write leveling : PASS
8762 11:36:02.023230 RX DQS gating : PASS
8763 11:36:02.026767 RX DQ/DQS(RDDQC) : PASS
8764 11:36:02.029567 TX DQ/DQS : PASS
8765 11:36:02.029641 RX DATLAT : PASS
8766 11:36:02.033178 RX DQ/DQS(Engine): PASS
8767 11:36:02.036273 TX OE : PASS
8768 11:36:02.036347 All Pass.
8769 11:36:02.036403
8770 11:36:02.036456 CH 1, Rank 1
8771 11:36:02.039825 SW Impedance : PASS
8772 11:36:02.043264 DUTY Scan : NO K
8773 11:36:02.043339 ZQ Calibration : PASS
8774 11:36:02.046643 Jitter Meter : NO K
8775 11:36:02.049799 CBT Training : PASS
8776 11:36:02.049873 Write leveling : PASS
8777 11:36:02.053151 RX DQS gating : PASS
8778 11:36:02.056232 RX DQ/DQS(RDDQC) : PASS
8779 11:36:02.056305 TX DQ/DQS : PASS
8780 11:36:02.059677 RX DATLAT : PASS
8781 11:36:02.062962 RX DQ/DQS(Engine): PASS
8782 11:36:02.063036 TX OE : PASS
8783 11:36:02.063093 All Pass.
8784 11:36:02.063145
8785 11:36:02.066475 DramC Write-DBI on
8786 11:36:02.069171 PER_BANK_REFRESH: Hybrid Mode
8787 11:36:02.069251 TX_TRACKING: ON
8788 11:36:02.079787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8789 11:36:02.085908 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8790 11:36:02.096038 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8791 11:36:02.099450 [FAST_K] Save calibration result to emmc
8792 11:36:02.103435 sync common calibartion params.
8793 11:36:02.103509 sync cbt_mode0:0, 1:0
8794 11:36:02.105564 dram_init: ddr_geometry: 0
8795 11:36:02.109116 dram_init: ddr_geometry: 0
8796 11:36:02.109190 dram_init: ddr_geometry: 0
8797 11:36:02.112341 0:dram_rank_size:80000000
8798 11:36:02.115369 1:dram_rank_size:80000000
8799 11:36:02.119442 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8800 11:36:02.122161 DFS_SHUFFLE_HW_MODE: ON
8801 11:36:02.125320 dramc_set_vcore_voltage set vcore to 725000
8802 11:36:02.128851 Read voltage for 1600, 0
8803 11:36:02.128930 Vio18 = 0
8804 11:36:02.133214 Vcore = 725000
8805 11:36:02.133298 Vdram = 0
8806 11:36:02.133359 Vddq = 0
8807 11:36:02.133416 Vmddr = 0
8808 11:36:02.135262 switch to 3200 Mbps bootup
8809 11:36:02.138763 [DramcRunTimeConfig]
8810 11:36:02.138850 PHYPLL
8811 11:36:02.142253 DPM_CONTROL_AFTERK: ON
8812 11:36:02.142339 PER_BANK_REFRESH: ON
8813 11:36:02.145194 REFRESH_OVERHEAD_REDUCTION: ON
8814 11:36:02.148753 CMD_PICG_NEW_MODE: OFF
8815 11:36:02.148843 XRTWTW_NEW_MODE: ON
8816 11:36:02.152221 XRTRTR_NEW_MODE: ON
8817 11:36:02.152317 TX_TRACKING: ON
8818 11:36:02.155461 RDSEL_TRACKING: OFF
8819 11:36:02.158867 DQS Precalculation for DVFS: ON
8820 11:36:02.158981 RX_TRACKING: OFF
8821 11:36:02.159075 HW_GATING DBG: ON
8822 11:36:02.162409 ZQCS_ENABLE_LP4: ON
8823 11:36:02.166159 RX_PICG_NEW_MODE: ON
8824 11:36:02.166297 TX_PICG_NEW_MODE: ON
8825 11:36:02.168753 ENABLE_RX_DCM_DPHY: ON
8826 11:36:02.172297 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8827 11:36:02.175632 DUMMY_READ_FOR_TRACKING: OFF
8828 11:36:02.175826 !!! SPM_CONTROL_AFTERK: OFF
8829 11:36:02.178785 !!! SPM could not control APHY
8830 11:36:02.181827 IMPEDANCE_TRACKING: ON
8831 11:36:02.182151 TEMP_SENSOR: ON
8832 11:36:02.185357 HW_SAVE_FOR_SR: OFF
8833 11:36:02.189055 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8834 11:36:02.192950 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8835 11:36:02.193336 Read ODT Tracking: ON
8836 11:36:02.195533 Refresh Rate DeBounce: ON
8837 11:36:02.198710 DFS_NO_QUEUE_FLUSH: ON
8838 11:36:02.201831 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8839 11:36:02.202176 ENABLE_DFS_RUNTIME_MRW: OFF
8840 11:36:02.206043 DDR_RESERVE_NEW_MODE: ON
8841 11:36:02.208248 MR_CBT_SWITCH_FREQ: ON
8842 11:36:02.208583 =========================
8843 11:36:02.228719 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8844 11:36:02.231527 dram_init: ddr_geometry: 0
8845 11:36:02.250360 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8846 11:36:02.253295 dram_init: dram init end (result: 0)
8847 11:36:02.260026 DRAM-K: Full calibration passed in 23382 msecs
8848 11:36:02.263395 MRC: failed to locate region type 0.
8849 11:36:02.263752 DRAM rank0 size:0x80000000,
8850 11:36:02.266636 DRAM rank1 size=0x80000000
8851 11:36:02.277335 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8852 11:36:02.283020 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8853 11:36:02.289293 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8854 11:36:02.296200 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8855 11:36:02.299953 DRAM rank0 size:0x80000000,
8856 11:36:02.302695 DRAM rank1 size=0x80000000
8857 11:36:02.303101 CBMEM:
8858 11:36:02.306431 IMD: root @ 0xfffff000 254 entries.
8859 11:36:02.309658 IMD: root @ 0xffffec00 62 entries.
8860 11:36:02.314549 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8861 11:36:02.315965 WARNING: RO_VPD is uninitialized or empty.
8862 11:36:02.322545 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8863 11:36:02.329460 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8864 11:36:02.342644 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8865 11:36:02.353594 BS: romstage times (exec / console): total (unknown) / 22927 ms
8866 11:36:02.353998
8867 11:36:02.354297
8868 11:36:02.363762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8869 11:36:02.366810 ARM64: Exception handlers installed.
8870 11:36:02.370295 ARM64: Testing exception
8871 11:36:02.373816 ARM64: Done test exception
8872 11:36:02.374198 Enumerating buses...
8873 11:36:02.377335 Show all devs... Before device enumeration.
8874 11:36:02.379967 Root Device: enabled 1
8875 11:36:02.383817 CPU_CLUSTER: 0: enabled 1
8876 11:36:02.384249 CPU: 00: enabled 1
8877 11:36:02.386584 Compare with tree...
8878 11:36:02.387200 Root Device: enabled 1
8879 11:36:02.390209 CPU_CLUSTER: 0: enabled 1
8880 11:36:02.393304 CPU: 00: enabled 1
8881 11:36:02.393688 Root Device scanning...
8882 11:36:02.397071 scan_static_bus for Root Device
8883 11:36:02.400177 CPU_CLUSTER: 0 enabled
8884 11:36:02.404078 scan_static_bus for Root Device done
8885 11:36:02.406554 scan_bus: bus Root Device finished in 8 msecs
8886 11:36:02.406939 done
8887 11:36:02.413860 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8888 11:36:02.416329 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8889 11:36:02.423326 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8890 11:36:02.426513 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8891 11:36:02.429628 Allocating resources...
8892 11:36:02.432908 Reading resources...
8893 11:36:02.436371 Root Device read_resources bus 0 link: 0
8894 11:36:02.440076 DRAM rank0 size:0x80000000,
8895 11:36:02.440568 DRAM rank1 size=0x80000000
8896 11:36:02.443161 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8897 11:36:02.446706 CPU: 00 missing read_resources
8898 11:36:02.452454 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8899 11:36:02.456300 Root Device read_resources bus 0 link: 0 done
8900 11:36:02.456751 Done reading resources.
8901 11:36:02.462982 Show resources in subtree (Root Device)...After reading.
8902 11:36:02.465764 Root Device child on link 0 CPU_CLUSTER: 0
8903 11:36:02.469172 CPU_CLUSTER: 0 child on link 0 CPU: 00
8904 11:36:02.479029 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8905 11:36:02.479431 CPU: 00
8906 11:36:02.483393 Root Device assign_resources, bus 0 link: 0
8907 11:36:02.485917 CPU_CLUSTER: 0 missing set_resources
8908 11:36:02.493101 Root Device assign_resources, bus 0 link: 0 done
8909 11:36:02.493508 Done setting resources.
8910 11:36:02.498805 Show resources in subtree (Root Device)...After assigning values.
8911 11:36:02.502865 Root Device child on link 0 CPU_CLUSTER: 0
8912 11:36:02.505979 CPU_CLUSTER: 0 child on link 0 CPU: 00
8913 11:36:02.514937 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8914 11:36:02.515013 CPU: 00
8915 11:36:02.519130 Done allocating resources.
8916 11:36:02.525595 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8917 11:36:02.525670 Enabling resources...
8918 11:36:02.525728 done.
8919 11:36:02.531995 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8920 11:36:02.532073 Initializing devices...
8921 11:36:02.535198 Root Device init
8922 11:36:02.538945 init hardware done!
8923 11:36:02.539019 0x00000018: ctrlr->caps
8924 11:36:02.541753 52.000 MHz: ctrlr->f_max
8925 11:36:02.544769 0.400 MHz: ctrlr->f_min
8926 11:36:02.544844 0x40ff8080: ctrlr->voltages
8927 11:36:02.548112 sclk: 390625
8928 11:36:02.548187 Bus Width = 1
8929 11:36:02.548244 sclk: 390625
8930 11:36:02.551534 Bus Width = 1
8931 11:36:02.551607 Early init status = 3
8932 11:36:02.558597 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8933 11:36:02.561882 in-header: 03 fc 00 00 01 00 00 00
8934 11:36:02.565286 in-data: 00
8935 11:36:02.568203 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8936 11:36:02.571637 in-header: 03 fd 00 00 00 00 00 00
8937 11:36:02.575996 in-data:
8938 11:36:02.578796 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8939 11:36:02.581769 in-header: 03 fc 00 00 01 00 00 00
8940 11:36:02.585702 in-data: 00
8941 11:36:02.589757 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8942 11:36:02.593184 in-header: 03 fd 00 00 00 00 00 00
8943 11:36:02.597179 in-data:
8944 11:36:02.599582 [SSUSB] Setting up USB HOST controller...
8945 11:36:02.603236 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8946 11:36:02.607141 [SSUSB] phy power-on done.
8947 11:36:02.611030 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8948 11:36:02.616870 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8949 11:36:02.619827 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8950 11:36:02.626540 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8951 11:36:02.633387 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8952 11:36:02.639806 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8953 11:36:02.646833 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8954 11:36:02.653238 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8955 11:36:02.656299 SPM: binary array size = 0x9dc
8956 11:36:02.659614 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8957 11:36:02.666273 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8958 11:36:02.672678 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8959 11:36:02.679783 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8960 11:36:02.682557 configure_display: Starting display init
8961 11:36:02.716435 anx7625_power_on_init: Init interface.
8962 11:36:02.720220 anx7625_disable_pd_protocol: Disabled PD feature.
8963 11:36:02.723024 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8964 11:36:02.751313 anx7625_start_dp_work: Secure OCM version=00
8965 11:36:02.753960 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8966 11:36:02.768663 sp_tx_get_edid_block: EDID Block = 1
8967 11:36:02.871550 Extracted contents:
8968 11:36:02.874447 header: 00 ff ff ff ff ff ff 00
8969 11:36:02.877874 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8970 11:36:02.881061 version: 01 04
8971 11:36:02.884750 basic params: 95 1f 11 78 0a
8972 11:36:02.887780 chroma info: 76 90 94 55 54 90 27 21 50 54
8973 11:36:02.891268 established: 00 00 00
8974 11:36:02.897559 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8975 11:36:02.904578 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8976 11:36:02.907400 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8977 11:36:02.913991 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8978 11:36:02.921286 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8979 11:36:02.924179 extensions: 00
8980 11:36:02.924266 checksum: fb
8981 11:36:02.924346
8982 11:36:02.930631 Manufacturer: IVO Model 57d Serial Number 0
8983 11:36:02.930696 Made week 0 of 2020
8984 11:36:02.934119 EDID version: 1.4
8985 11:36:02.934185 Digital display
8986 11:36:02.937541 6 bits per primary color channel
8987 11:36:02.937606 DisplayPort interface
8988 11:36:02.940945 Maximum image size: 31 cm x 17 cm
8989 11:36:02.943918 Gamma: 220%
8990 11:36:02.944004 Check DPMS levels
8991 11:36:02.947435 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8992 11:36:02.955138 First detailed timing is preferred timing
8993 11:36:02.955229 Established timings supported:
8994 11:36:02.957808 Standard timings supported:
8995 11:36:02.960728 Detailed timings
8996 11:36:02.964764 Hex of detail: 383680a07038204018303c0035ae10000019
8997 11:36:02.970518 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
8998 11:36:02.974259 0780 0798 07c8 0820 hborder 0
8999 11:36:02.977193 0438 043b 0447 0458 vborder 0
9000 11:36:02.980839 -hsync -vsync
9001 11:36:02.980912 Did detailed timing
9002 11:36:02.987218 Hex of detail: 000000000000000000000000000000000000
9003 11:36:02.990546 Manufacturer-specified data, tag 0
9004 11:36:02.994329 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9005 11:36:02.996892 ASCII string: InfoVision
9006 11:36:03.001340 Hex of detail: 000000fe00523134304e574635205248200a
9007 11:36:03.003747 ASCII string: R140NWF5 RH
9008 11:36:03.003844 Checksum
9009 11:36:03.007114 Checksum: 0xfb (valid)
9010 11:36:03.010184 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9011 11:36:03.013876 DSI data_rate: 832800000 bps
9012 11:36:03.020191 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9013 11:36:03.023612 anx7625_parse_edid: pixelclock(138800).
9014 11:36:03.027532 hactive(1920), hsync(48), hfp(24), hbp(88)
9015 11:36:03.030324 vactive(1080), vsync(12), vfp(3), vbp(17)
9016 11:36:03.033109 anx7625_dsi_config: config dsi.
9017 11:36:03.040347 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9018 11:36:03.054079 anx7625_dsi_config: success to config DSI
9019 11:36:03.057012 anx7625_dp_start: MIPI phy setup OK.
9020 11:36:03.060174 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9021 11:36:03.063480 mtk_ddp_mode_set invalid vrefresh 60
9022 11:36:03.066822 main_disp_path_setup
9023 11:36:03.066919 ovl_layer_smi_id_en
9024 11:36:03.070369 ovl_layer_smi_id_en
9025 11:36:03.070436 ccorr_config
9026 11:36:03.070495 aal_config
9027 11:36:03.073650 gamma_config
9028 11:36:03.073727 postmask_config
9029 11:36:03.076755 dither_config
9030 11:36:03.080749 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9031 11:36:03.086778 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9032 11:36:03.090238 Root Device init finished in 551 msecs
9033 11:36:03.093833 CPU_CLUSTER: 0 init
9034 11:36:03.100048 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9035 11:36:03.103027 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9036 11:36:03.106739 APU_MBOX 0x190000b0 = 0x10001
9037 11:36:03.109592 APU_MBOX 0x190001b0 = 0x10001
9038 11:36:03.113122 APU_MBOX 0x190005b0 = 0x10001
9039 11:36:03.116347 APU_MBOX 0x190006b0 = 0x10001
9040 11:36:03.119715 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9041 11:36:03.132667 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9042 11:36:03.145488 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9043 11:36:03.151688 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9044 11:36:03.163071 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9045 11:36:03.172006 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9046 11:36:03.176130 CPU_CLUSTER: 0 init finished in 81 msecs
9047 11:36:03.179414 Devices initialized
9048 11:36:03.182533 Show all devs... After init.
9049 11:36:03.182598 Root Device: enabled 1
9050 11:36:03.185897 CPU_CLUSTER: 0: enabled 1
9051 11:36:03.188973 CPU: 00: enabled 1
9052 11:36:03.192459 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9053 11:36:03.196096 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9054 11:36:03.199088 ELOG: NV offset 0x57f000 size 0x1000
9055 11:36:03.206127 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9056 11:36:03.212340 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9057 11:36:03.215832 ELOG: Event(17) added with size 13 at 2024-07-17 11:36:03 UTC
9058 11:36:03.220017 out: cmd=0x121: 03 db 21 01 00 00 00 00
9059 11:36:03.223176 in-header: 03 a9 00 00 2c 00 00 00
9060 11:36:03.236337 in-data: 99 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9061 11:36:03.242738 ELOG: Event(A1) added with size 10 at 2024-07-17 11:36:03 UTC
9062 11:36:03.249773 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9063 11:36:03.256367 ELOG: Event(A0) added with size 9 at 2024-07-17 11:36:03 UTC
9064 11:36:03.259527 elog_add_boot_reason: Logged dev mode boot
9065 11:36:03.262881 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9066 11:36:03.266804 Finalize devices...
9067 11:36:03.266870 Devices finalized
9068 11:36:03.273871 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9069 11:36:03.275961 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9070 11:36:03.279172 in-header: 03 07 00 00 08 00 00 00
9071 11:36:03.282818 in-data: aa e4 47 04 13 02 00 00
9072 11:36:03.286002 Chrome EC: UHEPI supported
9073 11:36:03.292498 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9074 11:36:03.295893 in-header: 03 a9 00 00 08 00 00 00
9075 11:36:03.299285 in-data: 84 60 60 08 00 00 00 00
9076 11:36:03.302461 ELOG: Event(91) added with size 10 at 2024-07-17 11:36:03 UTC
9077 11:36:03.309051 Chrome EC: clear events_b mask to 0x0000000020004000
9078 11:36:03.316274 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9079 11:36:03.319530 in-header: 03 fd 00 00 00 00 00 00
9080 11:36:03.319595 in-data:
9081 11:36:03.326254 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9082 11:36:03.329222 Writing coreboot table at 0xffe64000
9083 11:36:03.332533 0. 000000000010a000-0000000000113fff: RAMSTAGE
9084 11:36:03.335807 1. 0000000040000000-00000000400fffff: RAM
9085 11:36:03.339014 2. 0000000040100000-000000004032afff: RAMSTAGE
9086 11:36:03.342493 3. 000000004032b000-00000000545fffff: RAM
9087 11:36:03.350247 4. 0000000054600000-000000005465ffff: BL31
9088 11:36:03.352654 5. 0000000054660000-00000000ffe63fff: RAM
9089 11:36:03.356099 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9090 11:36:03.362630 7. 0000000100000000-000000013fffffff: RAM
9091 11:36:03.362704 Passing 5 GPIOs to payload:
9092 11:36:03.368830 NAME | PORT | POLARITY | VALUE
9093 11:36:03.372474 EC in RW | 0x000000aa | low | undefined
9094 11:36:03.378954 EC interrupt | 0x00000005 | low | undefined
9095 11:36:03.382422 TPM interrupt | 0x000000ab | high | undefined
9096 11:36:03.385209 SD card detect | 0x00000011 | high | undefined
9097 11:36:03.392545 speaker enable | 0x00000093 | high | undefined
9098 11:36:03.396191 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9099 11:36:03.399185 in-header: 03 f8 00 00 02 00 00 00
9100 11:36:03.401983 in-data: 03 00
9101 11:36:03.402056 ADC[4]: Raw value=668958 ID=5
9102 11:36:03.405578 ADC[3]: Raw value=212549 ID=1
9103 11:36:03.408540 RAM Code: 0x51
9104 11:36:03.408614 ADC[6]: Raw value=74410 ID=0
9105 11:36:03.412243 ADC[5]: Raw value=211812 ID=1
9106 11:36:03.415221 SKU Code: 0x1
9107 11:36:03.418433 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7f2d
9108 11:36:03.422065 coreboot table: 964 bytes.
9109 11:36:03.425601 IMD ROOT 0. 0xfffff000 0x00001000
9110 11:36:03.428340 IMD SMALL 1. 0xffffe000 0x00001000
9111 11:36:03.431952 RO MCACHE 2. 0xffffc000 0x00001104
9112 11:36:03.435218 CONSOLE 3. 0xfff7c000 0x00080000
9113 11:36:03.438109 FMAP 4. 0xfff7b000 0x00000452
9114 11:36:03.441501 TIME STAMP 5. 0xfff7a000 0x00000910
9115 11:36:03.444986 VBOOT WORK 6. 0xfff66000 0x00014000
9116 11:36:03.448649 RAMOOPS 7. 0xffe66000 0x00100000
9117 11:36:03.452223 COREBOOT 8. 0xffe64000 0x00002000
9118 11:36:03.455128 IMD small region:
9119 11:36:03.458864 IMD ROOT 0. 0xffffec00 0x00000400
9120 11:36:03.461318 VPD 1. 0xffffeb80 0x0000006c
9121 11:36:03.465397 MMC STATUS 2. 0xffffeb60 0x00000004
9122 11:36:03.467961 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9123 11:36:03.474798 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9124 11:36:03.516033 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9125 11:36:03.519007 Checking segment from ROM address 0x40100000
9126 11:36:03.521957 Checking segment from ROM address 0x4010001c
9127 11:36:03.529314 Loading segment from ROM address 0x40100000
9128 11:36:03.529388 code (compression=0)
9129 11:36:03.539075 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9130 11:36:03.545541 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9131 11:36:03.545617 it's not compressed!
9132 11:36:03.551999 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9133 11:36:03.558658 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9134 11:36:03.575619 Loading segment from ROM address 0x4010001c
9135 11:36:03.575695 Entry Point 0x80000000
9136 11:36:03.578980 Loaded segments
9137 11:36:03.582568 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9138 11:36:03.589486 Jumping to boot code at 0x80000000(0xffe64000)
9139 11:36:03.595926 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9140 11:36:03.602275 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9141 11:36:03.610526 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9142 11:36:03.613678 Checking segment from ROM address 0x40100000
9143 11:36:03.617453 Checking segment from ROM address 0x4010001c
9144 11:36:03.623191 Loading segment from ROM address 0x40100000
9145 11:36:03.623265 code (compression=1)
9146 11:36:03.630093 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9147 11:36:03.640495 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9148 11:36:03.640570 using LZMA
9149 11:36:03.648314 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9150 11:36:03.655064 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9151 11:36:03.658358 Loading segment from ROM address 0x4010001c
9152 11:36:03.658432 Entry Point 0x54601000
9153 11:36:03.662363 Loaded segments
9154 11:36:03.664952 NOTICE: MT8192 bl31_setup
9155 11:36:03.671996 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9156 11:36:03.676118 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9157 11:36:03.678916 WARNING: region 0:
9158 11:36:03.682669 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9159 11:36:03.682759 WARNING: region 1:
9160 11:36:03.688421 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9161 11:36:03.691798 WARNING: region 2:
9162 11:36:03.696256 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9163 11:36:03.699279 WARNING: region 3:
9164 11:36:03.702450 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9165 11:36:03.705652 WARNING: region 4:
9166 11:36:03.712279 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9167 11:36:03.712353 WARNING: region 5:
9168 11:36:03.716060 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 11:36:03.718644 WARNING: region 6:
9170 11:36:03.722769 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9171 11:36:03.725375 WARNING: region 7:
9172 11:36:03.729049 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9173 11:36:03.735544 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9174 11:36:03.738456 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9175 11:36:03.742685 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9176 11:36:03.748402 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9177 11:36:03.751943 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9178 11:36:03.756512 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9179 11:36:03.762182 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9180 11:36:03.764909 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9181 11:36:03.771647 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9182 11:36:03.774952 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9183 11:36:03.778606 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9184 11:36:03.784991 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9185 11:36:03.788501 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9186 11:36:03.791665 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9187 11:36:03.798257 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9188 11:36:03.801492 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9189 11:36:03.808186 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9190 11:36:03.811417 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9191 11:36:03.814895 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9192 11:36:03.822033 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9193 11:36:03.825005 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9194 11:36:03.831501 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9195 11:36:03.835220 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9196 11:36:03.838798 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9197 11:36:03.844572 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9198 11:36:03.848660 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9199 11:36:03.855305 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9200 11:36:03.858516 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9201 11:36:03.861519 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9202 11:36:03.869123 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9203 11:36:03.872024 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9204 11:36:03.878776 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9205 11:36:03.881338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9206 11:36:03.885361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9207 11:36:03.888665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9208 11:36:03.894946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9209 11:36:03.898144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9210 11:36:03.901135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9211 11:36:03.904848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9212 11:36:03.908168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9213 11:36:03.914436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9214 11:36:03.917658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9215 11:36:03.921522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9216 11:36:03.927865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9217 11:36:03.931184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9218 11:36:03.934594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9219 11:36:03.937842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9220 11:36:03.944608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9221 11:36:03.947513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9222 11:36:03.951473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9223 11:36:03.957864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9224 11:36:03.960796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9225 11:36:03.967921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9226 11:36:03.971351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9227 11:36:03.978809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9228 11:36:03.981494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9229 11:36:03.984642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9230 11:36:03.990910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9231 11:36:03.994436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9232 11:36:04.001154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9233 11:36:04.004396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9234 11:36:04.010764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9235 11:36:04.013849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9236 11:36:04.021405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9237 11:36:04.024118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9238 11:36:04.027450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9239 11:36:04.034039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9240 11:36:04.037379 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9241 11:36:04.043917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9242 11:36:04.047556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9243 11:36:04.053932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9244 11:36:04.057536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9245 11:36:04.060876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9246 11:36:04.067669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9247 11:36:04.070812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9248 11:36:04.077325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9249 11:36:04.081883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9250 11:36:04.087173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9251 11:36:04.090565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9252 11:36:04.098225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9253 11:36:04.100674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9254 11:36:04.103730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9255 11:36:04.110312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9256 11:36:04.113712 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9257 11:36:04.121066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9258 11:36:04.124263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9259 11:36:04.130818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9260 11:36:04.133463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9261 11:36:04.136762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9262 11:36:04.143330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9263 11:36:04.147569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9264 11:36:04.153426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9265 11:36:04.156588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9266 11:36:04.163689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9267 11:36:04.166417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9268 11:36:04.173351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9269 11:36:04.177793 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9270 11:36:04.179813 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9271 11:36:04.183182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9272 11:36:04.190143 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9273 11:36:04.193427 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9274 11:36:04.196819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9275 11:36:04.203734 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9276 11:36:04.206518 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9277 11:36:04.212993 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9278 11:36:04.216159 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9279 11:36:04.220005 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9280 11:36:04.226297 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9281 11:36:04.229991 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9282 11:36:04.236589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9283 11:36:04.239465 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9284 11:36:04.243336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9285 11:36:04.249373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9286 11:36:04.252626 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9287 11:36:04.259403 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9288 11:36:04.263310 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9289 11:36:04.265906 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9290 11:36:04.273330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9291 11:36:04.275736 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9292 11:36:04.279189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9293 11:36:04.282780 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9294 11:36:04.289502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9295 11:36:04.292894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9296 11:36:04.296050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9297 11:36:04.302338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9298 11:36:04.306002 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9299 11:36:04.309644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9300 11:36:04.315572 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9301 11:36:04.318854 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9302 11:36:04.325409 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9303 11:36:04.329031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9304 11:36:04.332676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9305 11:36:04.338843 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9306 11:36:04.342388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9307 11:36:04.348694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9308 11:36:04.352144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9309 11:36:04.355564 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9310 11:36:04.362543 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9311 11:36:04.365418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9312 11:36:04.368571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9313 11:36:04.375469 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9314 11:36:04.378503 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9315 11:36:04.385468 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9316 11:36:04.389109 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9317 11:36:04.391994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9318 11:36:04.398750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9319 11:36:04.401726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9320 11:36:04.408699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9321 11:36:04.412082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9322 11:36:04.415416 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9323 11:36:04.422040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9324 11:36:04.425054 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9325 11:36:04.428676 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9326 11:36:04.435418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9327 11:36:04.438892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9328 11:36:04.445036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9329 11:36:04.448589 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9330 11:36:04.452476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9331 11:36:04.458789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9332 11:36:04.462526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9333 11:36:04.468356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9334 11:36:04.471835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9335 11:36:04.475820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9336 11:36:04.482180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9337 11:36:04.485321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9338 11:36:04.492131 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9339 11:36:04.496314 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9340 11:36:04.499029 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9341 11:36:04.505418 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9342 11:36:04.509095 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9343 11:36:04.514992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9344 11:36:04.518508 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9345 11:36:04.522037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9346 11:36:04.528354 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9347 11:36:04.531595 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9348 11:36:04.535207 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9349 11:36:04.541681 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9350 11:36:04.545466 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9351 11:36:04.551345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9352 11:36:04.554574 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9353 11:36:04.558493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9354 11:36:04.564748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9355 11:36:04.568237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9356 11:36:04.574952 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9357 11:36:04.578490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9358 11:36:04.581271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9359 11:36:04.588195 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9360 11:36:04.591955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9361 11:36:04.597936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9362 11:36:04.601188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9363 11:36:04.604850 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9364 11:36:04.611180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9365 11:36:04.614953 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9366 11:36:04.621515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9367 11:36:04.624941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9368 11:36:04.627860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9369 11:36:04.635094 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9370 11:36:04.638224 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9371 11:36:04.644633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9372 11:36:04.647778 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9373 11:36:04.654599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9374 11:36:04.658487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9375 11:36:04.661598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9376 11:36:04.667889 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9377 11:36:04.670862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9378 11:36:04.677678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9379 11:36:04.680779 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9380 11:36:04.684351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9381 11:36:04.691183 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9382 11:36:04.694077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9383 11:36:04.701335 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9384 11:36:04.704278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9385 11:36:04.710894 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9386 11:36:04.713910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9387 11:36:04.717213 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9388 11:36:04.724227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9389 11:36:04.727450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9390 11:36:04.733887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9391 11:36:04.737642 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9392 11:36:04.745722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9393 11:36:04.747540 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9394 11:36:04.750394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9395 11:36:04.757078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9396 11:36:04.760332 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9397 11:36:04.767096 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9398 11:36:04.770574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9399 11:36:04.773821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9400 11:36:04.780124 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9401 11:36:04.783885 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9402 11:36:04.790428 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9403 11:36:04.793500 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9404 11:36:04.796768 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9405 11:36:04.800536 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9406 11:36:04.803473 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9407 11:36:04.810132 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9408 11:36:04.813549 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9409 11:36:04.820599 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9410 11:36:04.823277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9411 11:36:04.827329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9412 11:36:04.833567 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9413 11:36:04.836767 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9414 11:36:04.840440 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9415 11:36:04.847441 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9416 11:36:04.850154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9417 11:36:04.853381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9418 11:36:04.860060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9419 11:36:04.864149 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9420 11:36:04.870004 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9421 11:36:04.873681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9422 11:36:04.876841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9423 11:36:04.883141 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9424 11:36:04.886469 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9425 11:36:04.890731 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9426 11:36:04.896753 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9427 11:36:04.899713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9428 11:36:04.906560 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9429 11:36:04.909894 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9430 11:36:04.913181 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9431 11:36:04.919938 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9432 11:36:04.923044 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9433 11:36:04.926970 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9434 11:36:04.933373 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9435 11:36:04.936574 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9436 11:36:04.940106 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9437 11:36:04.946130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9438 11:36:04.949537 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9439 11:36:04.956119 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9440 11:36:04.959652 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9441 11:36:04.963342 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9442 11:36:04.966375 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9443 11:36:04.972849 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9444 11:36:04.976942 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9445 11:36:04.980180 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9446 11:36:04.982783 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9447 11:36:04.989176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9448 11:36:04.992671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9449 11:36:04.996362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9450 11:36:04.999313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9451 11:36:05.005862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9452 11:36:05.009022 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9453 11:36:05.012394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9454 11:36:05.018911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9455 11:36:05.022116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9456 11:36:05.026265 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9457 11:36:05.032345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9458 11:36:05.035861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9459 11:36:05.042592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9460 11:36:05.045499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9461 11:36:05.052316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9462 11:36:05.055491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9463 11:36:05.058496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9464 11:36:05.065910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9465 11:36:05.068764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9466 11:36:05.072287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9467 11:36:05.078651 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9468 11:36:05.082214 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9469 11:36:05.088829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9470 11:36:05.092631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9471 11:36:05.095275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9472 11:36:05.102094 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9473 11:36:05.105083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9474 11:36:05.111647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9475 11:36:05.115318 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9476 11:36:05.122503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9477 11:36:05.124667 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9478 11:36:05.128447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9479 11:36:05.134967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9480 11:36:05.138203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9481 11:36:05.144781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9482 11:36:05.147911 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9483 11:36:05.155057 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9484 11:36:05.158797 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9485 11:36:05.161220 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9486 11:36:05.168330 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9487 11:36:05.171352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9488 11:36:05.177806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9489 11:36:05.181396 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9490 11:36:05.184896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9491 11:36:05.191064 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9492 11:36:05.194336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9493 11:36:05.200737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9494 11:36:05.204424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9495 11:36:05.208123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9496 11:36:05.214778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9497 11:36:05.217617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9498 11:36:05.224125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9499 11:36:05.227167 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9500 11:36:05.233960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9501 11:36:05.237786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9502 11:36:05.240723 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9503 11:36:05.247152 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9504 11:36:05.250178 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9505 11:36:05.257138 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9506 11:36:05.260372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9507 11:36:05.267117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9508 11:36:05.270356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9509 11:36:05.273763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9510 11:36:05.280219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9511 11:36:05.283838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9512 11:36:05.290124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9513 11:36:05.294765 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9514 11:36:05.296951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9515 11:36:05.303507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9516 11:36:05.307115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9517 11:36:05.313098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9518 11:36:05.316432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9519 11:36:05.320004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9520 11:36:05.326381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9521 11:36:05.329547 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9522 11:36:05.336473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9523 11:36:05.339564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9524 11:36:05.346806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9525 11:36:05.350443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9526 11:36:05.353729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9527 11:36:05.359786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9528 11:36:05.362673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9529 11:36:05.369572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9530 11:36:05.372989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9531 11:36:05.379913 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9532 11:36:05.382981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9533 11:36:05.386268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9534 11:36:05.392549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9535 11:36:05.396139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9536 11:36:05.403911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9537 11:36:05.406177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9538 11:36:05.413454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9539 11:36:05.415529 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9540 11:36:05.422594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9541 11:36:05.425552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9542 11:36:05.428920 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9543 11:36:05.436000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9544 11:36:05.439315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9545 11:36:05.445693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9546 11:36:05.448912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9547 11:36:05.455296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9548 11:36:05.458700 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9549 11:36:05.465453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9550 11:36:05.468967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9551 11:36:05.471624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9552 11:36:05.479088 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9553 11:36:05.481772 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9554 11:36:05.488976 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9555 11:36:05.492119 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9556 11:36:05.498986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9557 11:36:05.501978 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9558 11:36:05.504852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9559 11:36:05.513107 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9560 11:36:05.514779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9561 11:36:05.521495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9562 11:36:05.524836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9563 11:36:05.531512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9564 11:36:05.535128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9565 11:36:05.542223 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9566 11:36:05.544464 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9567 11:36:05.548258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9568 11:36:05.554697 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9569 11:36:05.557788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9570 11:36:05.565293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9571 11:36:05.567727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9572 11:36:05.574884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9573 11:36:05.577818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9574 11:36:05.581944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9575 11:36:05.588683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9576 11:36:05.591723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9577 11:36:05.598534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9578 11:36:05.601087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9579 11:36:05.607863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9580 11:36:05.611770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9581 11:36:05.614836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9582 11:36:05.621727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9583 11:36:05.624652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9584 11:36:05.631573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9585 11:36:05.634268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9586 11:36:05.640798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9587 11:36:05.644612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9588 11:36:05.650693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9589 11:36:05.653840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9590 11:36:05.660849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9591 11:36:05.663959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9592 11:36:05.670945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9593 11:36:05.674474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9594 11:36:05.680552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9595 11:36:05.684214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9596 11:36:05.690300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9597 11:36:05.694002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9598 11:36:05.700258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9599 11:36:05.703828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9600 11:36:05.711150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9601 11:36:05.713678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9602 11:36:05.720131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9603 11:36:05.723511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9604 11:36:05.730435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9605 11:36:05.734768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9606 11:36:05.740013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9607 11:36:05.743217 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9608 11:36:05.746656 INFO: [APUAPC] vio 0
9609 11:36:05.750401 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9610 11:36:05.757118 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9611 11:36:05.760296 INFO: [APUAPC] D0_APC_0: 0x400510
9612 11:36:05.763305 INFO: [APUAPC] D0_APC_1: 0x0
9613 11:36:05.766919 INFO: [APUAPC] D0_APC_2: 0x1540
9614 11:36:05.766995 INFO: [APUAPC] D0_APC_3: 0x0
9615 11:36:05.770213 INFO: [APUAPC] D1_APC_0: 0xffffffff
9616 11:36:05.773080 INFO: [APUAPC] D1_APC_1: 0xffffffff
9617 11:36:05.776401 INFO: [APUAPC] D1_APC_2: 0x3fffff
9618 11:36:05.780009 INFO: [APUAPC] D1_APC_3: 0x0
9619 11:36:05.783824 INFO: [APUAPC] D2_APC_0: 0xffffffff
9620 11:36:05.787280 INFO: [APUAPC] D2_APC_1: 0xffffffff
9621 11:36:05.789568 INFO: [APUAPC] D2_APC_2: 0x3fffff
9622 11:36:05.793144 INFO: [APUAPC] D2_APC_3: 0x0
9623 11:36:05.796651 INFO: [APUAPC] D3_APC_0: 0xffffffff
9624 11:36:05.799805 INFO: [APUAPC] D3_APC_1: 0xffffffff
9625 11:36:05.802976 INFO: [APUAPC] D3_APC_2: 0x3fffff
9626 11:36:05.806292 INFO: [APUAPC] D3_APC_3: 0x0
9627 11:36:05.809652 INFO: [APUAPC] D4_APC_0: 0xffffffff
9628 11:36:05.812754 INFO: [APUAPC] D4_APC_1: 0xffffffff
9629 11:36:05.816559 INFO: [APUAPC] D4_APC_2: 0x3fffff
9630 11:36:05.819700 INFO: [APUAPC] D4_APC_3: 0x0
9631 11:36:05.822991 INFO: [APUAPC] D5_APC_0: 0xffffffff
9632 11:36:05.826461 INFO: [APUAPC] D5_APC_1: 0xffffffff
9633 11:36:05.829702 INFO: [APUAPC] D5_APC_2: 0x3fffff
9634 11:36:05.832893 INFO: [APUAPC] D5_APC_3: 0x0
9635 11:36:05.835985 INFO: [APUAPC] D6_APC_0: 0xffffffff
9636 11:36:05.839920 INFO: [APUAPC] D6_APC_1: 0xffffffff
9637 11:36:05.842642 INFO: [APUAPC] D6_APC_2: 0x3fffff
9638 11:36:05.846202 INFO: [APUAPC] D6_APC_3: 0x0
9639 11:36:05.849361 INFO: [APUAPC] D7_APC_0: 0xffffffff
9640 11:36:05.852417 INFO: [APUAPC] D7_APC_1: 0xffffffff
9641 11:36:05.855708 INFO: [APUAPC] D7_APC_2: 0x3fffff
9642 11:36:05.859478 INFO: [APUAPC] D7_APC_3: 0x0
9643 11:36:05.862794 INFO: [APUAPC] D8_APC_0: 0xffffffff
9644 11:36:05.866186 INFO: [APUAPC] D8_APC_1: 0xffffffff
9645 11:36:05.868815 INFO: [APUAPC] D8_APC_2: 0x3fffff
9646 11:36:05.872152 INFO: [APUAPC] D8_APC_3: 0x0
9647 11:36:05.875510 INFO: [APUAPC] D9_APC_0: 0xffffffff
9648 11:36:05.879395 INFO: [APUAPC] D9_APC_1: 0xffffffff
9649 11:36:05.882288 INFO: [APUAPC] D9_APC_2: 0x3fffff
9650 11:36:05.885396 INFO: [APUAPC] D9_APC_3: 0x0
9651 11:36:05.889144 INFO: [APUAPC] D10_APC_0: 0xffffffff
9652 11:36:05.892653 INFO: [APUAPC] D10_APC_1: 0xffffffff
9653 11:36:05.895734 INFO: [APUAPC] D10_APC_2: 0x3fffff
9654 11:36:05.899025 INFO: [APUAPC] D10_APC_3: 0x0
9655 11:36:05.902799 INFO: [APUAPC] D11_APC_0: 0xffffffff
9656 11:36:05.905832 INFO: [APUAPC] D11_APC_1: 0xffffffff
9657 11:36:05.908712 INFO: [APUAPC] D11_APC_2: 0x3fffff
9658 11:36:05.912324 INFO: [APUAPC] D11_APC_3: 0x0
9659 11:36:05.915323 INFO: [APUAPC] D12_APC_0: 0xffffffff
9660 11:36:05.918453 INFO: [APUAPC] D12_APC_1: 0xffffffff
9661 11:36:05.922230 INFO: [APUAPC] D12_APC_2: 0x3fffff
9662 11:36:05.925330 INFO: [APUAPC] D12_APC_3: 0x0
9663 11:36:05.928575 INFO: [APUAPC] D13_APC_0: 0xffffffff
9664 11:36:05.932254 INFO: [APUAPC] D13_APC_1: 0xffffffff
9665 11:36:05.935243 INFO: [APUAPC] D13_APC_2: 0x3fffff
9666 11:36:05.938662 INFO: [APUAPC] D13_APC_3: 0x0
9667 11:36:05.942509 INFO: [APUAPC] D14_APC_0: 0xffffffff
9668 11:36:05.946134 INFO: [APUAPC] D14_APC_1: 0xffffffff
9669 11:36:05.948967 INFO: [APUAPC] D14_APC_2: 0x3fffff
9670 11:36:05.951546 INFO: [APUAPC] D14_APC_3: 0x0
9671 11:36:05.955449 INFO: [APUAPC] D15_APC_0: 0xffffffff
9672 11:36:05.958882 INFO: [APUAPC] D15_APC_1: 0xffffffff
9673 11:36:05.962056 INFO: [APUAPC] D15_APC_2: 0x3fffff
9674 11:36:05.964874 INFO: [APUAPC] D15_APC_3: 0x0
9675 11:36:05.968562 INFO: [APUAPC] APC_CON: 0x4
9676 11:36:05.971401 INFO: [NOCDAPC] D0_APC_0: 0x0
9677 11:36:05.974820 INFO: [NOCDAPC] D0_APC_1: 0x0
9678 11:36:05.978022 INFO: [NOCDAPC] D1_APC_0: 0x0
9679 11:36:05.978086 INFO: [NOCDAPC] D1_APC_1: 0xfff
9680 11:36:05.982101 INFO: [NOCDAPC] D2_APC_0: 0x0
9681 11:36:05.984924 INFO: [NOCDAPC] D2_APC_1: 0xfff
9682 11:36:05.988987 INFO: [NOCDAPC] D3_APC_0: 0x0
9683 11:36:05.991352 INFO: [NOCDAPC] D3_APC_1: 0xfff
9684 11:36:05.994614 INFO: [NOCDAPC] D4_APC_0: 0x0
9685 11:36:05.997806 INFO: [NOCDAPC] D4_APC_1: 0xfff
9686 11:36:06.001896 INFO: [NOCDAPC] D5_APC_0: 0x0
9687 11:36:06.004594 INFO: [NOCDAPC] D5_APC_1: 0xfff
9688 11:36:06.008099 INFO: [NOCDAPC] D6_APC_0: 0x0
9689 11:36:06.011799 INFO: [NOCDAPC] D6_APC_1: 0xfff
9690 11:36:06.011868 INFO: [NOCDAPC] D7_APC_0: 0x0
9691 11:36:06.015722 INFO: [NOCDAPC] D7_APC_1: 0xfff
9692 11:36:06.018198 INFO: [NOCDAPC] D8_APC_0: 0x0
9693 11:36:06.021434 INFO: [NOCDAPC] D8_APC_1: 0xfff
9694 11:36:06.024878 INFO: [NOCDAPC] D9_APC_0: 0x0
9695 11:36:06.028034 INFO: [NOCDAPC] D9_APC_1: 0xfff
9696 11:36:06.031423 INFO: [NOCDAPC] D10_APC_0: 0x0
9697 11:36:06.034833 INFO: [NOCDAPC] D10_APC_1: 0xfff
9698 11:36:06.037672 INFO: [NOCDAPC] D11_APC_0: 0x0
9699 11:36:06.041567 INFO: [NOCDAPC] D11_APC_1: 0xfff
9700 11:36:06.044727 INFO: [NOCDAPC] D12_APC_0: 0x0
9701 11:36:06.048272 INFO: [NOCDAPC] D12_APC_1: 0xfff
9702 11:36:06.051500 INFO: [NOCDAPC] D13_APC_0: 0x0
9703 11:36:06.051568 INFO: [NOCDAPC] D13_APC_1: 0xfff
9704 11:36:06.054857 INFO: [NOCDAPC] D14_APC_0: 0x0
9705 11:36:06.059059 INFO: [NOCDAPC] D14_APC_1: 0xfff
9706 11:36:06.061507 INFO: [NOCDAPC] D15_APC_0: 0x0
9707 11:36:06.064519 INFO: [NOCDAPC] D15_APC_1: 0xfff
9708 11:36:06.068188 INFO: [NOCDAPC] APC_CON: 0x4
9709 11:36:06.071081 INFO: [APUAPC] set_apusys_apc done
9710 11:36:06.074584 INFO: [DEVAPC] devapc_init done
9711 11:36:06.077986 INFO: GICv3 without legacy support detected.
9712 11:36:06.081546 INFO: ARM GICv3 driver initialized in EL3
9713 11:36:06.087812 INFO: Maximum SPI INTID supported: 639
9714 11:36:06.091393 INFO: BL31: Initializing runtime services
9715 11:36:06.098296 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9716 11:36:06.098364 INFO: SPM: enable CPC mode
9717 11:36:06.104479 INFO: mcdi ready for mcusys-off-idle and system suspend
9718 11:36:06.107485 INFO: BL31: Preparing for EL3 exit to normal world
9719 11:36:06.111167 INFO: Entry point address = 0x80000000
9720 11:36:06.114623 INFO: SPSR = 0x8
9721 11:36:06.120169
9722 11:36:06.120284
9723 11:36:06.120343
9724 11:36:06.123810 Starting depthcharge on Spherion...
9725 11:36:06.123897
9726 11:36:06.123976 Wipe memory regions:
9727 11:36:06.124053
9728 11:36:06.124826 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9729 11:36:06.124942 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9730 11:36:06.125043 Setting prompt string to ['asurada:']
9731 11:36:06.125135 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9732 11:36:06.127249 [0x00000040000000, 0x00000054600000)
9733 11:36:06.249197
9734 11:36:06.249351 [0x00000054660000, 0x00000080000000)
9735 11:36:06.509534
9736 11:36:06.509661 [0x000000821a7280, 0x000000ffe64000)
9737 11:36:07.254742
9738 11:36:07.254864 [0x00000100000000, 0x00000140000000)
9739 11:36:07.635224
9740 11:36:07.639239 Initializing XHCI USB controller at 0x11200000.
9741 11:36:08.677436
9742 11:36:08.680542 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9743 11:36:08.680951
9744 11:36:08.681436
9745 11:36:08.682129 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9746 11:36:08.682509 Sending line: 'tftpboot 192.168.201.1 14864607/tftp-deploy-3gvh_9_g/kernel/image.itb 14864607/tftp-deploy-3gvh_9_g/kernel/cmdline '
9748 11:36:08.783796 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9749 11:36:08.784309 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:18)
9750 11:36:08.789281 asurada: tftpboot 192.168.201.1 14864607/tftp-deploy-3gvh_9_g/kernel/image.itp-deploy-3gvh_9_g/kernel/cmdline
9751 11:36:08.789693
9752 11:36:08.790010 Waiting for link
9753 11:36:08.946609
9754 11:36:08.947076 R8152: Initializing
9755 11:36:08.947384
9756 11:36:08.950382 Version 9 (ocp_data = 6010)
9757 11:36:08.950740
9758 11:36:08.954238 R8152: Done initializing
9759 11:36:08.954607
9760 11:36:08.954913 Adding net device
9761 11:36:10.955412
9762 11:36:10.955540 done.
9763 11:36:10.955600
9764 11:36:10.955652 MAC: 00:e0:4c:68:03:bd
9765 11:36:10.955703
9766 11:36:10.957036 Sending DHCP discover... done.
9767 11:36:10.957105
9768 11:36:10.961056 Waiting for reply... done.
9769 11:36:10.961125
9770 11:36:10.964016 Sending DHCP request... done.
9771 11:36:10.964078
9772 11:36:10.964130 Waiting for reply... done.
9773 11:36:10.964180
9774 11:36:10.967198 My ip is 192.168.201.16
9775 11:36:10.967261
9776 11:36:10.970576 The DHCP server ip is 192.168.201.1
9777 11:36:10.970637
9778 11:36:10.973895 TFTP server IP predefined by user: 192.168.201.1
9779 11:36:10.973961
9780 11:36:10.980430 Bootfile predefined by user: 14864607/tftp-deploy-3gvh_9_g/kernel/image.itb
9781 11:36:10.980507
9782 11:36:10.983929 Sending tftp read request... done.
9783 11:36:10.983993
9784 11:36:10.986879 Waiting for the transfer...
9785 11:36:10.986954
9786 11:36:11.254361 00000000 ################################################################
9787 11:36:11.254481
9788 11:36:11.522682 00080000 ################################################################
9789 11:36:11.522816
9790 11:36:11.782415 00100000 ################################################################
9791 11:36:11.782563
9792 11:36:12.027685 00180000 ################################################################
9793 11:36:12.027808
9794 11:36:12.276868 00200000 ################################################################
9795 11:36:12.276987
9796 11:36:12.525588 00280000 ################################################################
9797 11:36:12.525710
9798 11:36:12.777001 00300000 ################################################################
9799 11:36:12.777123
9800 11:36:13.035101 00380000 ################################################################
9801 11:36:13.035222
9802 11:36:13.283204 00400000 ################################################################
9803 11:36:13.283339
9804 11:36:13.531396 00480000 ################################################################
9805 11:36:13.531546
9806 11:36:13.779569 00500000 ################################################################
9807 11:36:13.779708
9808 11:36:14.027367 00580000 ################################################################
9809 11:36:14.027488
9810 11:36:14.276535 00600000 ################################################################
9811 11:36:14.276654
9812 11:36:14.524785 00680000 ################################################################
9813 11:36:14.524902
9814 11:36:14.776094 00700000 ################################################################
9815 11:36:14.776211
9816 11:36:15.027348 00780000 ################################################################
9817 11:36:15.027467
9818 11:36:15.275227 00800000 ################################################################
9819 11:36:15.275346
9820 11:36:15.522146 00880000 ################################################################
9821 11:36:15.522267
9822 11:36:15.775616 00900000 ################################################################
9823 11:36:15.775729
9824 11:36:16.023622 00980000 ################################################################
9825 11:36:16.023760
9826 11:36:16.273723 00a00000 ################################################################
9827 11:36:16.273841
9828 11:36:16.536210 00a80000 ################################################################
9829 11:36:16.536326
9830 11:36:16.819030 00b00000 ################################################################
9831 11:36:16.819145
9832 11:36:17.085711 00b80000 ################################################################
9833 11:36:17.085864
9834 11:36:17.347274 00c00000 ################################################################
9835 11:36:17.347386
9836 11:36:17.597823 00c80000 ################################################################
9837 11:36:17.597942
9838 11:36:17.846229 00d00000 ################################################################
9839 11:36:17.846341
9840 11:36:18.108742 00d80000 ################################################################
9841 11:36:18.108853
9842 11:36:18.360036 00e00000 ################################################################
9843 11:36:18.360148
9844 11:36:18.617892 00e80000 ################################################################
9845 11:36:18.618055
9846 11:36:18.868874 00f00000 ################################################################
9847 11:36:18.868987
9848 11:36:19.118577 00f80000 ################################################################
9849 11:36:19.118703
9850 11:36:19.369117 01000000 ################################################################
9851 11:36:19.369291
9852 11:36:19.620075 01080000 ################################################################
9853 11:36:19.620210
9854 11:36:19.867769 01100000 ################################################################
9855 11:36:19.867908
9856 11:36:20.124632 01180000 ################################################################
9857 11:36:20.124766
9858 11:36:20.375212 01200000 ################################################################
9859 11:36:20.375322
9860 11:36:20.626782 01280000 ################################################################
9861 11:36:20.626897
9862 11:36:20.877637 01300000 ################################################################
9863 11:36:20.877774
9864 11:36:21.152354 01380000 ################################################################
9865 11:36:21.152481
9866 11:36:21.413117 01400000 ################################################################
9867 11:36:21.413237
9868 11:36:21.660754 01480000 ################################################################
9869 11:36:21.660876
9870 11:36:21.908460 01500000 ################################################################
9871 11:36:21.908608
9872 11:36:22.157411 01580000 ################################################################
9873 11:36:22.157534
9874 11:36:22.405924 01600000 ################################################################
9875 11:36:22.406055
9876 11:36:22.651709 01680000 ################################################################
9877 11:36:22.651918
9878 11:36:22.898423 01700000 ################################################################
9879 11:36:22.898542
9880 11:36:23.164349 01780000 ################################################################
9881 11:36:23.164471
9882 11:36:23.421400 01800000 ################################################################
9883 11:36:23.421524
9884 11:36:23.668089 01880000 ################################################################
9885 11:36:23.668222
9886 11:36:23.915865 01900000 ################################################################
9887 11:36:23.915988
9888 11:36:24.193346 01980000 ################################################################
9889 11:36:24.193479
9890 11:36:24.457735 01a00000 ################################################################
9891 11:36:24.457856
9892 11:36:24.730526 01a80000 ################################################################
9893 11:36:24.730647
9894 11:36:24.993561 01b00000 ################################################################
9895 11:36:24.993685
9896 11:36:25.247318 01b80000 ################################################################
9897 11:36:25.247433
9898 11:36:25.512488 01c00000 ################################################################
9899 11:36:25.512608
9900 11:36:25.763025 01c80000 ################################################################
9901 11:36:25.763143
9902 11:36:26.010635 01d00000 ################################################################
9903 11:36:26.010783
9904 11:36:26.258380 01d80000 ################################################################
9905 11:36:26.258495
9906 11:36:26.504958 01e00000 ################################################################
9907 11:36:26.505069
9908 11:36:26.751673 01e80000 ################################################################
9909 11:36:26.751787
9910 11:36:26.997406 01f00000 ################################################################
9911 11:36:26.997528
9912 11:36:27.248120 01f80000 ################################################################
9913 11:36:27.248241
9914 11:36:27.516971 02000000 ################################################################
9915 11:36:27.517107
9916 11:36:27.774138 02080000 ################################################################
9917 11:36:27.774264
9918 11:36:28.025046 02100000 ################################################################
9919 11:36:28.025169
9920 11:36:28.274947 02180000 ################################################################
9921 11:36:28.275074
9922 11:36:28.526405 02200000 ################################################################
9923 11:36:28.526528
9924 11:36:28.777475 02280000 ################################################################
9925 11:36:28.777598
9926 11:36:29.026224 02300000 ################################################################
9927 11:36:29.026350
9928 11:36:29.275470 02380000 ################################################################
9929 11:36:29.275596
9930 11:36:29.518389 02400000 ################################################################
9931 11:36:29.518509
9932 11:36:29.765933 02480000 ################################################################
9933 11:36:29.766053
9934 11:36:30.016114 02500000 ################################################################
9935 11:36:30.016234
9936 11:36:30.269129 02580000 ################################################################
9937 11:36:30.269295
9938 11:36:30.515112 02600000 ################################################################
9939 11:36:30.515228
9940 11:36:30.781914 02680000 ################################################################
9941 11:36:30.782030
9942 11:36:31.028057 02700000 ################################################################
9943 11:36:31.028172
9944 11:36:31.282144 02780000 ################################################################
9945 11:36:31.282260
9946 11:36:31.536111 02800000 ################################################################
9947 11:36:31.536252
9948 11:36:31.785038 02880000 ################################################################
9949 11:36:31.785150
9950 11:36:32.041136 02900000 ################################################################
9951 11:36:32.041260
9952 11:36:32.295641 02980000 ################################################################
9953 11:36:32.295757
9954 11:36:32.562567 02a00000 ################################################################
9955 11:36:32.562679
9956 11:36:32.813793 02a80000 ################################################################
9957 11:36:32.813904
9958 11:36:33.059573 02b00000 ################################################################
9959 11:36:33.059684
9960 11:36:33.305503 02b80000 ################################################################
9961 11:36:33.305632
9962 11:36:33.553669 02c00000 ################################################################
9963 11:36:33.553798
9964 11:36:33.801640 02c80000 ################################################################
9965 11:36:33.801759
9966 11:36:34.071199 02d00000 ################################################################
9967 11:36:34.071322
9968 11:36:34.324018 02d80000 ################################################################
9969 11:36:34.324177
9970 11:36:34.569720 02e00000 ################################################################
9971 11:36:34.569907
9972 11:36:34.824256 02e80000 ################################################################
9973 11:36:34.824409
9974 11:36:35.089598 02f00000 ################################################################
9975 11:36:35.089715
9976 11:36:35.341637 02f80000 ################################################################
9977 11:36:35.341755
9978 11:36:35.591297 03000000 ################################################################
9979 11:36:35.591424
9980 11:36:35.847224 03080000 ################################################################
9981 11:36:35.847346
9982 11:36:36.093170 03100000 ################################################################
9983 11:36:36.093341
9984 11:36:36.341853 03180000 ################################################################
9985 11:36:36.341973
9986 11:36:36.590063 03200000 ################################################################
9987 11:36:36.590192
9988 11:36:36.839631 03280000 ################################################################
9989 11:36:36.839753
9990 11:36:37.089589 03300000 ################################################################
9991 11:36:37.089711
9992 11:36:37.272604 03380000 ############################################## done.
9993 11:36:37.272722
9994 11:36:37.275399 The bootfile was 54378222 bytes long.
9995 11:36:37.275476
9996 11:36:37.278652 Sending tftp read request... done.
9997 11:36:37.278729
9998 11:36:37.278788 Waiting for the transfer...
9999 11:36:37.278842
10000 11:36:37.282515 00000000 # done.
10001 11:36:37.282594
10002 11:36:37.288742 Command line loaded dynamically from TFTP file: 14864607/tftp-deploy-3gvh_9_g/kernel/cmdline
10003 11:36:37.288819
10004 11:36:37.302403 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10005 11:36:37.302484
10006 11:36:37.305089 Loading FIT.
10007 11:36:37.305188
10008 11:36:37.308443 Image ramdisk-1 has 41210643 bytes.
10009 11:36:37.308518
10010 11:36:37.311838 Image fdt-1 has 47258 bytes.
10011 11:36:37.311913
10012 11:36:37.311972 Image kernel-1 has 13118294 bytes.
10013 11:36:37.315241
10014 11:36:37.321910 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10015 11:36:37.321987
10016 11:36:37.341215 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10017 11:36:37.341333
10018 11:36:37.345556 Choosing best match conf-1 for compat google,spherion-rev3.
10019 11:36:37.349706
10020 11:36:37.354602 Connected to device vid:did:rid of 1ae0:0028:00
10021 11:36:37.360791
10022 11:36:37.364021 tpm_get_response: command 0x17b, return code 0x0
10023 11:36:37.364097
10024 11:36:37.369367 ec_init: CrosEC protocol v3 supported (256, 248)
10025 11:36:37.372792
10026 11:36:37.376032 tpm_cleanup: add release locality here.
10027 11:36:37.376108
10028 11:36:37.376167 Shutting down all USB controllers.
10029 11:36:37.379842
10030 11:36:37.379939 Removing current net device
10031 11:36:37.380026
10032 11:36:37.386551 Exiting depthcharge with code 4 at timestamp: 59475874
10033 11:36:37.386631
10034 11:36:37.389433 LZMA decompressing kernel-1 to 0x821a6718
10035 11:36:37.389500
10036 11:36:37.393756 LZMA decompressing kernel-1 to 0x40000000
10037 11:36:39.008279
10038 11:36:39.008836 jumping to kernel
10039 11:36:39.011146 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10040 11:36:39.011704 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10041 11:36:39.012179 Setting prompt string to ['Linux version [0-9]']
10042 11:36:39.012660 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 11:36:39.013152 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10044 11:36:39.058661
10045 11:36:39.061951 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10046 11:36:39.065985 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10047 11:36:39.066435 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10048 11:36:39.066775 Setting prompt string to []
10049 11:36:39.067166 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10050 11:36:39.067520 Using line separator: #'\n'#
10051 11:36:39.067799 No login prompt set.
10052 11:36:39.068098 Parsing kernel messages
10053 11:36:39.068376 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10054 11:36:39.068888 [login-action] Waiting for messages, (timeout 00:03:48)
10055 11:36:39.069205 Waiting using forced prompt support (timeout 00:01:54)
10056 11:36:39.085060 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10057 11:36:39.088678 [ 0.000000] random: crng init done
10058 11:36:39.091672 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10059 11:36:39.095542 [ 0.000000] efi: UEFI not found.
10060 11:36:39.105082 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10061 11:36:39.111334 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10062 11:36:39.121378 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10063 11:36:39.132223 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10064 11:36:39.139871 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10065 11:36:39.141621 [ 0.000000] printk: bootconsole [mtk8250] enabled
10066 11:36:39.149967 [ 0.000000] NUMA: No NUMA configuration found
10067 11:36:39.156446 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10068 11:36:39.163282 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10069 11:36:39.163683 [ 0.000000] Zone ranges:
10070 11:36:39.169596 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10071 11:36:39.173140 [ 0.000000] DMA32 empty
10072 11:36:39.180188 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10073 11:36:39.182939 [ 0.000000] Movable zone start for each node
10074 11:36:39.186273 [ 0.000000] Early memory node ranges
10075 11:36:39.192805 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10076 11:36:39.199526 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10077 11:36:39.205812 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10078 11:36:39.213347 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10079 11:36:39.219648 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10080 11:36:39.226116 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10081 11:36:39.257725 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10082 11:36:39.262808 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10083 11:36:39.269920 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10084 11:36:39.273026 [ 0.000000] psci: probing for conduit method from DT.
10085 11:36:39.280835 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10086 11:36:39.283152 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10087 11:36:39.289422 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10088 11:36:39.293110 [ 0.000000] psci: SMC Calling Convention v1.2
10089 11:36:39.299641 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10090 11:36:39.302881 [ 0.000000] Detected VIPT I-cache on CPU0
10091 11:36:39.309276 [ 0.000000] CPU features: detected: GIC system register CPU interface
10092 11:36:39.316525 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10093 11:36:39.322719 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10094 11:36:39.329664 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10095 11:36:39.335895 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10096 11:36:39.346435 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10097 11:36:39.349267 [ 0.000000] alternatives: applying boot alternatives
10098 11:36:39.356135 [ 0.000000] Fallback order for Node 0: 0
10099 11:36:39.362983 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10100 11:36:39.365939 [ 0.000000] Policy zone: Normal
10101 11:36:39.378782 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10102 11:36:39.388329 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10103 11:36:39.399584 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10104 11:36:39.409081 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10105 11:36:39.415091 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10106 11:36:39.418481 <6>[ 0.000000] software IO TLB: area num 8.
10107 11:36:39.476252 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10108 11:36:39.556508 <6>[ 0.000000] Memory: 3809396K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 349068K reserved, 32768K cma-reserved)
10109 11:36:39.563062 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10110 11:36:39.570373 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10111 11:36:39.572515 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10112 11:36:39.579667 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10113 11:36:39.586043 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10114 11:36:39.588954 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10115 11:36:39.598765 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10116 11:36:39.606522 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10117 11:36:39.612499 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10118 11:36:39.618783 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10119 11:36:39.622092 <6>[ 0.000000] GICv3: 608 SPIs implemented
10120 11:36:39.625306 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10121 11:36:39.631946 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10122 11:36:39.635199 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10123 11:36:39.642001 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10124 11:36:39.655448 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10125 11:36:39.668604 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10126 11:36:39.675867 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10127 11:36:39.682586 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10128 11:36:39.695669 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10129 11:36:39.702356 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10130 11:36:39.709100 <6>[ 0.009171] Console: colour dummy device 80x25
10131 11:36:39.719034 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10132 11:36:39.725527 <6>[ 0.024339] pid_max: default: 32768 minimum: 301
10133 11:36:39.729065 <6>[ 0.029241] LSM: Security Framework initializing
10134 11:36:39.735641 <6>[ 0.034154] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10135 11:36:39.745536 <6>[ 0.041762] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10136 11:36:39.752093 <6>[ 0.050865] cblist_init_generic: Setting adjustable number of callback queues.
10137 11:36:39.758863 <6>[ 0.058305] cblist_init_generic: Setting shift to 3 and lim to 1.
10138 11:36:39.765283 <6>[ 0.064644] cblist_init_generic: Setting adjustable number of callback queues.
10139 11:36:39.771889 <6>[ 0.072115] cblist_init_generic: Setting shift to 3 and lim to 1.
10140 11:36:39.779226 <6>[ 0.078515] rcu: Hierarchical SRCU implementation.
10141 11:36:39.784985 <6>[ 0.083529] rcu: Max phase no-delay instances is 1000.
10142 11:36:39.789080 <6>[ 0.090541] EFI services will not be available.
10143 11:36:39.795272 <6>[ 0.095529] smp: Bringing up secondary CPUs ...
10144 11:36:39.802897 <6>[ 0.100547] Detected VIPT I-cache on CPU1
10145 11:36:39.810040 <6>[ 0.100606] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10146 11:36:39.816147 <6>[ 0.100630] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10147 11:36:39.819221 <6>[ 0.100961] Detected VIPT I-cache on CPU2
10148 11:36:39.829653 <6>[ 0.101014] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10149 11:36:39.835686 <6>[ 0.101031] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10150 11:36:39.839586 <6>[ 0.101291] Detected VIPT I-cache on CPU3
10151 11:36:39.845561 <6>[ 0.101338] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10152 11:36:39.852049 <6>[ 0.101353] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10153 11:36:39.859625 <6>[ 0.101660] CPU features: detected: Spectre-v4
10154 11:36:39.862706 <6>[ 0.101667] CPU features: detected: Spectre-BHB
10155 11:36:39.865548 <6>[ 0.101673] Detected PIPT I-cache on CPU4
10156 11:36:39.872411 <6>[ 0.101732] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10157 11:36:39.878318 <6>[ 0.101750] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10158 11:36:39.885375 <6>[ 0.102038] Detected PIPT I-cache on CPU5
10159 11:36:39.892121 <6>[ 0.102100] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10160 11:36:39.898353 <6>[ 0.102116] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10161 11:36:39.902318 <6>[ 0.102393] Detected PIPT I-cache on CPU6
10162 11:36:39.908343 <6>[ 0.102455] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10163 11:36:39.918431 <6>[ 0.102471] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10164 11:36:39.921454 <6>[ 0.102772] Detected PIPT I-cache on CPU7
10165 11:36:39.928518 <6>[ 0.102835] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10166 11:36:39.934505 <6>[ 0.102851] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10167 11:36:39.938082 <6>[ 0.102898] smp: Brought up 1 node, 8 CPUs
10168 11:36:39.944799 <6>[ 0.244336] SMP: Total of 8 processors activated.
10169 11:36:39.948448 <6>[ 0.249257] CPU features: detected: 32-bit EL0 Support
10170 11:36:39.957918 <6>[ 0.254653] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10171 11:36:39.964466 <6>[ 0.263507] CPU features: detected: Common not Private translations
10172 11:36:39.971301 <6>[ 0.269983] CPU features: detected: CRC32 instructions
10173 11:36:39.977948 <6>[ 0.275335] CPU features: detected: RCpc load-acquire (LDAPR)
10174 11:36:39.981153 <6>[ 0.281295] CPU features: detected: LSE atomic instructions
10175 11:36:39.987650 <6>[ 0.287077] CPU features: detected: Privileged Access Never
10176 11:36:39.994382 <6>[ 0.292856] CPU features: detected: RAS Extension Support
10177 11:36:40.000785 <6>[ 0.298499] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10178 11:36:40.003965 <6>[ 0.305721] CPU: All CPU(s) started at EL2
10179 11:36:40.010501 <6>[ 0.310037] alternatives: applying system-wide alternatives
10180 11:36:40.019818 <6>[ 0.319996] devtmpfs: initialized
10181 11:36:40.032243 <6>[ 0.328122] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10182 11:36:40.042161 <6>[ 0.338082] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10183 11:36:40.047845 <6>[ 0.346346] pinctrl core: initialized pinctrl subsystem
10184 11:36:40.051617 <6>[ 0.352994] DMI not present or invalid.
10185 11:36:40.058482 <6>[ 0.357395] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10186 11:36:40.068586 <6>[ 0.364268] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10187 11:36:40.074734 <6>[ 0.371714] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10188 11:36:40.084349 <6>[ 0.379800] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10189 11:36:40.087619 <6>[ 0.387956] audit: initializing netlink subsys (disabled)
10190 11:36:40.097758 <5>[ 0.393653] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10191 11:36:40.103914 <6>[ 0.394351] thermal_sys: Registered thermal governor 'step_wise'
10192 11:36:40.110791 <6>[ 0.401620] thermal_sys: Registered thermal governor 'power_allocator'
10193 11:36:40.114471 <6>[ 0.407872] cpuidle: using governor menu
10194 11:36:40.117706 <6>[ 0.418822] NET: Registered PF_QIPCRTR protocol family
10195 11:36:40.127115 <6>[ 0.424309] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10196 11:36:40.131208 <6>[ 0.431411] ASID allocator initialised with 32768 entries
10197 11:36:40.138055 <6>[ 0.437960] Serial: AMBA PL011 UART driver
10198 11:36:40.147616 <4>[ 0.447284] Trying to register duplicate clock ID: 134
10199 11:36:40.205308 <6>[ 0.508482] KASLR enabled
10200 11:36:40.219456 <6>[ 0.516098] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10201 11:36:40.225804 <6>[ 0.523116] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10202 11:36:40.232668 <6>[ 0.529600] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10203 11:36:40.239718 <6>[ 0.536606] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10204 11:36:40.246232 <6>[ 0.543095] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10205 11:36:40.252497 <6>[ 0.550102] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10206 11:36:40.258893 <6>[ 0.556587] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10207 11:36:40.265434 <6>[ 0.563588] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10208 11:36:40.268545 <6>[ 0.571034] ACPI: Interpreter disabled.
10209 11:36:40.278957 <6>[ 0.577454] iommu: Default domain type: Translated
10210 11:36:40.284000 <6>[ 0.582617] iommu: DMA domain TLB invalidation policy: strict mode
10211 11:36:40.287562 <5>[ 0.589272] SCSI subsystem initialized
10212 11:36:40.293985 <6>[ 0.593534] usbcore: registered new interface driver usbfs
10213 11:36:40.300338 <6>[ 0.599265] usbcore: registered new interface driver hub
10214 11:36:40.303991 <6>[ 0.604813] usbcore: registered new device driver usb
10215 11:36:40.312658 <6>[ 0.610938] pps_core: LinuxPPS API ver. 1 registered
10216 11:36:40.321860 <6>[ 0.616133] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10217 11:36:40.323746 <6>[ 0.625473] PTP clock support registered
10218 11:36:40.327107 <6>[ 0.629715] EDAC MC: Ver: 3.0.0
10219 11:36:40.334494 <6>[ 0.634888] FPGA manager framework
10220 11:36:40.341348 <6>[ 0.638567] Advanced Linux Sound Architecture Driver Initialized.
10221 11:36:40.344393 <6>[ 0.645353] vgaarb: loaded
10222 11:36:40.351679 <6>[ 0.648530] clocksource: Switched to clocksource arch_sys_counter
10223 11:36:40.354445 <5>[ 0.654984] VFS: Disk quotas dquot_6.6.0
10224 11:36:40.361456 <6>[ 0.659173] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10225 11:36:40.364140 <6>[ 0.666361] pnp: PnP ACPI: disabled
10226 11:36:40.373002 <6>[ 0.673110] NET: Registered PF_INET protocol family
10227 11:36:40.379422 <6>[ 0.678507] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10228 11:36:40.392202 <6>[ 0.688549] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10229 11:36:40.402082 <6>[ 0.697334] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10230 11:36:40.408595 <6>[ 0.705301] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10231 11:36:40.414649 <6>[ 0.713706] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10232 11:36:40.425417 <6>[ 0.722352] TCP: Hash tables configured (established 32768 bind 32768)
10233 11:36:40.432590 <6>[ 0.729214] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10234 11:36:40.439492 <6>[ 0.736231] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10235 11:36:40.444959 <6>[ 0.743754] NET: Registered PF_UNIX/PF_LOCAL protocol family
10236 11:36:40.451934 <6>[ 0.749833] RPC: Registered named UNIX socket transport module.
10237 11:36:40.454817 <6>[ 0.755978] RPC: Registered udp transport module.
10238 11:36:40.462142 <6>[ 0.760908] RPC: Registered tcp transport module.
10239 11:36:40.468929 <6>[ 0.765839] RPC: Registered tcp NFSv4.1 backchannel transport module.
10240 11:36:40.472497 <6>[ 0.772500] PCI: CLS 0 bytes, default 64
10241 11:36:40.474940 <6>[ 0.776836] Unpacking initramfs...
10242 11:36:40.492229 <6>[ 0.789046] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10243 11:36:40.502204 <6>[ 0.797689] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10244 11:36:40.505239 <6>[ 0.806523] kvm [1]: IPA Size Limit: 40 bits
10245 11:36:40.511850 <6>[ 0.811051] kvm [1]: GICv3: no GICV resource entry
10246 11:36:40.515303 <6>[ 0.816072] kvm [1]: disabling GICv2 emulation
10247 11:36:40.522219 <6>[ 0.820759] kvm [1]: GIC system register CPU interface enabled
10248 11:36:40.528565 <6>[ 0.828612] kvm [1]: vgic interrupt IRQ18
10249 11:36:40.531678 <6>[ 0.832980] kvm [1]: VHE mode initialized successfully
10250 11:36:40.539837 <5>[ 0.839439] Initialise system trusted keyrings
10251 11:36:40.545959 <6>[ 0.844211] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10252 11:36:40.554036 <6>[ 0.854154] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10253 11:36:40.560562 <5>[ 0.860563] NFS: Registering the id_resolver key type
10254 11:36:40.564005 <5>[ 0.865862] Key type id_resolver registered
10255 11:36:40.571241 <5>[ 0.870279] Key type id_legacy registered
10256 11:36:40.578069 <6>[ 0.874574] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10257 11:36:40.583832 <6>[ 0.881496] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10258 11:36:40.589879 <6>[ 0.889218] 9p: Installing v9fs 9p2000 file system support
10259 11:36:40.626400 <5>[ 0.926819] Key type asymmetric registered
10260 11:36:40.630327 <5>[ 0.931150] Asymmetric key parser 'x509' registered
10261 11:36:40.639644 <6>[ 0.936285] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10262 11:36:40.643321 <6>[ 0.943897] io scheduler mq-deadline registered
10263 11:36:40.647608 <6>[ 0.948678] io scheduler kyber registered
10264 11:36:40.665387 <6>[ 0.965631] EINJ: ACPI disabled.
10265 11:36:40.698476 <4>[ 0.991616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10266 11:36:40.708088 <4>[ 1.002247] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10267 11:36:40.722475 <6>[ 1.022969] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10268 11:36:40.730410 <6>[ 1.030989] printk: console [ttyS0] disabled
10269 11:36:40.758535 <6>[ 1.055622] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10270 11:36:40.765467 <6>[ 1.065093] printk: console [ttyS0] enabled
10271 11:36:40.768492 <6>[ 1.065093] printk: console [ttyS0] enabled
10272 11:36:40.775462 <6>[ 1.073988] printk: bootconsole [mtk8250] disabled
10273 11:36:40.778346 <6>[ 1.073988] printk: bootconsole [mtk8250] disabled
10274 11:36:40.785535 <6>[ 1.085314] SuperH (H)SCI(F) driver initialized
10275 11:36:40.788870 <6>[ 1.090607] msm_serial: driver initialized
10276 11:36:40.802631 <6>[ 1.099607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10277 11:36:40.812628 <6>[ 1.108157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10278 11:36:40.819359 <6>[ 1.116699] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10279 11:36:40.829186 <6>[ 1.125327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10280 11:36:40.835846 <6>[ 1.134033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10281 11:36:40.845772 <6>[ 1.142758] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10282 11:36:40.856006 <6>[ 1.151299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10283 11:36:40.862503 <6>[ 1.160103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10284 11:36:40.872659 <6>[ 1.168647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10285 11:36:40.883802 <6>[ 1.184317] loop: module loaded
10286 11:36:40.891887 <6>[ 1.190285] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10287 11:36:40.914020 <4>[ 1.213684] mtk-pmic-keys: Failed to locate of_node [id: -1]
10288 11:36:40.920209 <6>[ 1.220674] megasas: 07.719.03.00-rc1
10289 11:36:40.930159 <6>[ 1.230535] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10290 11:36:40.939758 <6>[ 1.239913] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10291 11:36:40.956663 <6>[ 1.256597] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10292 11:36:41.012984 <6>[ 1.306590] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10293 11:36:42.212834 <6>[ 2.511871] Freeing initrd memory: 40240K
10294 11:36:42.223462 <6>[ 2.523682] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10295 11:36:42.235271 <6>[ 2.534578] tun: Universal TUN/TAP device driver, 1.6
10296 11:36:42.237622 <6>[ 2.540658] thunder_xcv, ver 1.0
10297 11:36:42.240888 <6>[ 2.544151] thunder_bgx, ver 1.0
10298 11:36:42.244756 <6>[ 2.547648] nicpf, ver 1.0
10299 11:36:42.254918 <6>[ 2.551665] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10300 11:36:42.258456 <6>[ 2.559142] hns3: Copyright (c) 2017 Huawei Corporation.
10301 11:36:42.264775 <6>[ 2.564730] hclge is initializing
10302 11:36:42.268557 <6>[ 2.568302] e1000: Intel(R) PRO/1000 Network Driver
10303 11:36:42.274751 <6>[ 2.573432] e1000: Copyright (c) 1999-2006 Intel Corporation.
10304 11:36:42.278183 <6>[ 2.579445] e1000e: Intel(R) PRO/1000 Network Driver
10305 11:36:42.284609 <6>[ 2.584661] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10306 11:36:42.291701 <6>[ 2.590850] igb: Intel(R) Gigabit Ethernet Network Driver
10307 11:36:42.298504 <6>[ 2.596500] igb: Copyright (c) 2007-2014 Intel Corporation.
10308 11:36:42.304249 <6>[ 2.602337] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10309 11:36:42.310950 <6>[ 2.608854] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10310 11:36:42.315026 <6>[ 2.615312] sky2: driver version 1.30
10311 11:36:42.320970 <6>[ 2.620242] usbcore: registered new device driver r8152-cfgselector
10312 11:36:42.327709 <6>[ 2.626781] usbcore: registered new interface driver r8152
10313 11:36:42.334909 <6>[ 2.632607] VFIO - User Level meta-driver version: 0.3
10314 11:36:42.341034 <6>[ 2.640836] usbcore: registered new interface driver usb-storage
10315 11:36:42.347130 <6>[ 2.647279] usbcore: registered new device driver onboard-usb-hub
10316 11:36:42.356405 <6>[ 2.656449] mt6397-rtc mt6359-rtc: registered as rtc0
10317 11:36:42.366215 <6>[ 2.661917] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:36:42 UTC (1721216202)
10318 11:36:42.369794 <6>[ 2.671484] i2c_dev: i2c /dev entries driver
10319 11:36:42.384008 <4>[ 2.683631] cpu cpu0: supply cpu not found, using dummy regulator
10320 11:36:42.390686 <4>[ 2.690086] cpu cpu1: supply cpu not found, using dummy regulator
10321 11:36:42.397132 <4>[ 2.696495] cpu cpu2: supply cpu not found, using dummy regulator
10322 11:36:42.403390 <4>[ 2.702899] cpu cpu3: supply cpu not found, using dummy regulator
10323 11:36:42.410572 <4>[ 2.709293] cpu cpu4: supply cpu not found, using dummy regulator
10324 11:36:42.417023 <4>[ 2.715686] cpu cpu5: supply cpu not found, using dummy regulator
10325 11:36:42.423751 <4>[ 2.722102] cpu cpu6: supply cpu not found, using dummy regulator
10326 11:36:42.429642 <4>[ 2.728502] cpu cpu7: supply cpu not found, using dummy regulator
10327 11:36:42.450234 <6>[ 2.750125] cpu cpu0: EM: created perf domain
10328 11:36:42.453061 <6>[ 2.755053] cpu cpu4: EM: created perf domain
10329 11:36:42.460549 <6>[ 2.760609] sdhci: Secure Digital Host Controller Interface driver
10330 11:36:42.467291 <6>[ 2.767037] sdhci: Copyright(c) Pierre Ossman
10331 11:36:42.473526 <6>[ 2.771952] Synopsys Designware Multimedia Card Interface Driver
10332 11:36:42.480817 <6>[ 2.778554] sdhci-pltfm: SDHCI platform and OF driver helper
10333 11:36:42.483765 <6>[ 2.778728] mmc0: CQHCI version 5.10
10334 11:36:42.490202 <6>[ 2.788637] ledtrig-cpu: registered to indicate activity on CPUs
10335 11:36:42.496754 <6>[ 2.795670] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10336 11:36:42.503434 <6>[ 2.802710] usbcore: registered new interface driver usbhid
10337 11:36:42.506666 <6>[ 2.808531] usbhid: USB HID core driver
10338 11:36:42.513298 <6>[ 2.812729] spi_master spi0: will run message pump with realtime priority
10339 11:36:42.561211 <6>[ 2.854657] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10340 11:36:42.581330 <6>[ 2.871282] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10341 11:36:42.584855 <6>[ 2.883571] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10342 11:36:42.591995 <6>[ 2.886195] cros-ec-spi spi0.0: Chrome EC device registered
10343 11:36:42.595756 <6>[ 2.896757] mmc0: Command Queue Engine enabled
10344 11:36:42.602389 <6>[ 2.901526] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10345 11:36:42.609672 <6>[ 2.909301] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10346 11:36:42.619410 <6>[ 2.909519] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10347 11:36:42.626100 <6>[ 2.918317] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10348 11:36:42.628963 <6>[ 2.924352] NET: Registered PF_PACKET protocol family
10349 11:36:42.635828 <6>[ 2.930767] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10350 11:36:42.639634 <6>[ 2.934735] 9pnet: Installing 9P2000 support
10351 11:36:42.645676 <6>[ 2.940478] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10352 11:36:42.649500 <5>[ 2.944411] Key type dns_resolver registered
10353 11:36:42.655965 <6>[ 2.950213] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10354 11:36:42.658713 <6>[ 2.954703] registered taskstats version 1
10355 11:36:42.665723 <5>[ 2.965008] Loading compiled-in X.509 certificates
10356 11:36:42.692206 <4>[ 2.985676] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10357 11:36:42.702431 <4>[ 2.996410] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10358 11:36:42.716900 <6>[ 3.017035] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10359 11:36:42.723903 <6>[ 3.023935] xhci-mtk 11200000.usb: xHCI Host Controller
10360 11:36:42.731087 <6>[ 3.029473] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10361 11:36:42.740875 <6>[ 3.037352] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10362 11:36:42.747744 <6>[ 3.046795] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10363 11:36:42.754251 <6>[ 3.052885] xhci-mtk 11200000.usb: xHCI Host Controller
10364 11:36:42.760402 <6>[ 3.058373] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10365 11:36:42.767478 <6>[ 3.066143] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10366 11:36:42.775550 <6>[ 3.074084] hub 1-0:1.0: USB hub found
10367 11:36:42.777728 <6>[ 3.078138] hub 1-0:1.0: 1 port detected
10368 11:36:42.787615 <6>[ 3.082462] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10369 11:36:42.790274 <6>[ 3.091346] hub 2-0:1.0: USB hub found
10370 11:36:42.794073 <6>[ 3.095388] hub 2-0:1.0: 1 port detected
10371 11:36:42.803386 <6>[ 3.102979] mtk-msdc 11f70000.mmc: Got CD GPIO
10372 11:36:42.817116 <6>[ 3.113828] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10373 11:36:42.826809 <6>[ 3.122213] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10374 11:36:42.833618 <6>[ 3.130555] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10375 11:36:42.843930 <6>[ 3.138901] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10376 11:36:42.850346 <6>[ 3.147241] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10377 11:36:42.860021 <6>[ 3.155579] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10378 11:36:42.866759 <6>[ 3.163918] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10379 11:36:42.877147 <6>[ 3.172256] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10380 11:36:42.882864 <6>[ 3.180596] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10381 11:36:42.893457 <6>[ 3.188933] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10382 11:36:42.900159 <6>[ 3.197272] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10383 11:36:42.910371 <6>[ 3.205617] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10384 11:36:42.916193 <6>[ 3.213954] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10385 11:36:42.927166 <6>[ 3.222292] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10386 11:36:42.932808 <6>[ 3.230631] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10387 11:36:42.939833 <6>[ 3.239294] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10388 11:36:42.947015 <6>[ 3.246417] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10389 11:36:42.952727 <6>[ 3.253195] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10390 11:36:42.964099 <6>[ 3.259933] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10391 11:36:42.969672 <6>[ 3.266837] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10392 11:36:42.977003 <6>[ 3.273717] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10393 11:36:42.986216 <6>[ 3.282850] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10394 11:36:42.996610 <6>[ 3.291972] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10395 11:36:43.006417 <6>[ 3.301265] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10396 11:36:43.016393 <6>[ 3.310732] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10397 11:36:43.025826 <6>[ 3.320199] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10398 11:36:43.032698 <6>[ 3.329324] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10399 11:36:43.042007 <6>[ 3.338792] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10400 11:36:43.052485 <6>[ 3.347912] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10401 11:36:43.062118 <6>[ 3.357206] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10402 11:36:43.073148 <6>[ 3.367365] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10403 11:36:43.081768 <6>[ 3.378904] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10404 11:36:43.207892 <6>[ 3.504807] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10405 11:36:43.362359 <6>[ 3.662677] hub 1-1:1.0: USB hub found
10406 11:36:43.365985 <6>[ 3.667206] hub 1-1:1.0: 4 ports detected
10407 11:36:43.376370 <6>[ 3.676487] hub 1-1:1.0: USB hub found
10408 11:36:43.379569 <6>[ 3.680889] hub 1-1:1.0: 4 ports detected
10409 11:36:43.488295 <6>[ 3.785115] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10410 11:36:43.513987 <6>[ 3.814133] hub 2-1:1.0: USB hub found
10411 11:36:43.517460 <6>[ 3.818595] hub 2-1:1.0: 3 ports detected
10412 11:36:43.528342 <6>[ 3.828494] hub 2-1:1.0: USB hub found
10413 11:36:43.531807 <6>[ 3.832935] hub 2-1:1.0: 3 ports detected
10414 11:36:43.699300 <6>[ 3.996791] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10415 11:36:43.832332 <6>[ 4.132560] hub 1-1.4:1.0: USB hub found
10416 11:36:43.835377 <6>[ 4.137221] hub 1-1.4:1.0: 2 ports detected
10417 11:36:43.848227 <6>[ 4.148477] hub 1-1.4:1.0: USB hub found
10418 11:36:43.851284 <6>[ 4.153053] hub 1-1.4:1.0: 2 ports detected
10419 11:36:43.911367 <6>[ 4.209029] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10420 11:36:44.020548 <6>[ 4.317476] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10421 11:36:44.055833 <4>[ 4.352909] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10422 11:36:44.065743 <4>[ 4.362004] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10423 11:36:44.109455 <6>[ 4.410128] r8152 2-1.3:1.0 eth0: v1.12.13
10424 11:36:44.147492 <6>[ 4.444735] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10425 11:36:44.344243 <6>[ 4.640854] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10426 11:36:45.849781 <6>[ 6.150675] r8152 2-1.3:1.0 eth0: carrier on
10427 11:36:48.544207 <5>[ 6.172609] Sending DHCP requests .., OK
10428 11:36:48.550371 <6>[ 8.848882] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10429 11:36:48.553479 <6>[ 8.857161] IP-Config: Complete:
10430 11:36:48.567118 <6>[ 8.860658] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10431 11:36:48.573473 <6>[ 8.871379] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10432 11:36:48.580230 <6>[ 8.879997] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10433 11:36:48.586634 <6>[ 8.880006] nameserver0=192.168.201.1
10434 11:36:48.590028 <6>[ 8.892185] clk: Disabling unused clocks
10435 11:36:48.593283 <6>[ 8.897663] ALSA device list:
10436 11:36:48.600312 <6>[ 8.900940] No soundcards found.
10437 11:36:48.607308 <6>[ 8.908357] Freeing unused kernel memory: 8512K
10438 11:36:48.611020 <6>[ 8.913244] Run /init as init process
10439 11:36:48.640914 <6>[ 8.941508] NET: Registered PF_INET6 protocol family
10440 11:36:48.647028 <6>[ 8.948094] Segment Routing with IPv6
10441 11:36:48.651274 <6>[ 8.952069] In-situ OAM (IOAM) with IPv6
10442 11:36:48.690484 <30>[ 8.964721] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10443 11:36:48.696723 <30>[ 8.997914] systemd[1]: Detected architecture arm64.
10444 11:36:48.697035
10445 11:36:48.704012 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10446 11:36:48.704325
10447 11:36:48.715938 <30>[ 9.016878] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10448 11:36:48.829495 <30>[ 9.126976] systemd[1]: Queued start job for default target graphical.target.
10449 11:36:48.873218 <30>[ 9.170731] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10450 11:36:48.880857 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10451 11:36:48.899801 <30>[ 9.197308] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10452 11:36:48.910023 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10453 11:36:48.929115 <30>[ 9.226432] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10454 11:36:48.938738 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10455 11:36:48.956567 <30>[ 9.253412] systemd[1]: Created slice user.slice - User and Session Slice.
10456 11:36:48.962614 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10457 11:36:48.982731 <30>[ 9.276887] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10458 11:36:48.990071 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10459 11:36:49.010981 <30>[ 9.304981] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10460 11:36:49.017665 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10461 11:36:49.045720 <30>[ 9.333234] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10462 11:36:49.056009 <30>[ 9.353123] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10463 11:36:49.061998 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10464 11:36:49.080257 <30>[ 9.377210] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10465 11:36:49.089891 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10466 11:36:49.107963 <30>[ 9.405325] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10467 11:36:49.118590 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10468 11:36:49.132313 <30>[ 9.433338] systemd[1]: Reached target paths.target - Path Units.
10469 11:36:49.142571 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10470 11:36:49.159790 <30>[ 9.457291] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10471 11:36:49.166693 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10472 11:36:49.180281 <30>[ 9.480821] systemd[1]: Reached target slices.target - Slice Units.
10473 11:36:49.190523 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10474 11:36:49.204639 <30>[ 9.505322] systemd[1]: Reached target swap.target - Swaps.
10475 11:36:49.211624 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10476 11:36:49.232167 <30>[ 9.529329] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10477 11:36:49.242001 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10478 11:36:49.259909 <30>[ 9.557778] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10479 11:36:49.270059 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10480 11:36:49.289071 <30>[ 9.586955] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10481 11:36:49.298783 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10482 11:36:49.315741 <30>[ 9.613456] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10483 11:36:49.325731 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10484 11:36:49.343397 <30>[ 9.641429] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10485 11:36:49.350120 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10486 11:36:49.368558 <30>[ 9.665493] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10487 11:36:49.377350 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10488 11:36:49.397061 <30>[ 9.694240] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10489 11:36:49.406090 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10490 11:36:49.424444 <30>[ 9.721957] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10491 11:36:49.434020 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10492 11:36:49.487693 <30>[ 9.785073] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10493 11:36:49.494070 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10494 11:36:49.506774 <30>[ 9.804605] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10495 11:36:49.513271 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10496 11:36:49.535318 <30>[ 9.833309] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10497 11:36:49.542696 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10498 11:36:49.569635 <30>[ 9.861022] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10499 11:36:49.583398 <30>[ 9.881236] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10500 11:36:49.593096 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10501 11:36:49.616657 <30>[ 9.914160] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10502 11:36:49.622983 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10503 11:36:49.647764 <30>[ 9.945868] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10504 11:36:49.657573 Startin<6>[ 9.955281] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10505 11:36:49.664567 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10506 11:36:49.685525 <30>[ 9.983571] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10507 11:36:49.691997 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10508 11:36:49.715674 <30>[ 10.012993] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10509 11:36:49.725061 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10510 11:36:49.748072 <30>[ 10.046059] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10511 11:36:49.754669 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10512 11:36:49.784016 <30>[ 10.082090] systemd[1]: Starting systemd-journald.service - Journal Service...
10513 11:36:49.791093 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10514 11:36:49.817185 <30>[ 10.114770] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10515 11:36:49.823876 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10516 11:36:49.851219 <30>[ 10.145935] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10517 11:36:49.858256 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10518 11:36:49.884121 <30>[ 10.182125] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10519 11:36:49.894108 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10520 11:36:49.917149 <30>[ 10.214450] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10521 11:36:49.922995 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10522 11:36:49.950505 <30>[ 10.247316] systemd[1]: Started systemd-journald.service - Journal Service.
10523 11:36:49.955915 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10524 11:36:49.984432 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10525 11:36:50.005401 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10526 11:36:50.024561 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10527 11:36:50.045826 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10528 11:36:50.071078 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10529 11:36:50.091576 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10530 11:36:50.110734 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10531 11:36:50.135392 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10532 11:36:50.158432 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10533 11:36:50.176605 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10534 11:36:50.196777 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10535 11:36:50.217637 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10536 11:36:50.224159 See 'systemctl status systemd-remount-fs.service' for details.
10537 11:36:50.234092 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10538 11:36:50.254166 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10539 11:36:50.303418 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10540 11:36:50.323629 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10541 11:36:50.345879 <46>[ 10.643275] systemd-journald[185]: Received client request to flush runtime journal.
10542 11:36:50.352473 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10543 11:36:50.376628 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10544 11:36:50.404159 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10545 11:36:50.429458 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10546 11:36:50.449117 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10547 11:36:50.468269 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10548 11:36:50.488440 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10549 11:36:50.508359 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10550 11:36:50.560245 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10551 11:36:50.585519 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10552 11:36:50.604283 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10553 11:36:50.623502 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10554 11:36:50.664606 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10555 11:36:50.689819 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10556 11:36:50.714116 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10557 11:36:50.766560 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10558 11:36:50.794819 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10559 11:36:50.816334 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10560 11:36:50.839781 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10561 11:36:50.909414 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10562 11:36:50.939699 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10563 11:36:51.039096 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10564 11:36:51.055717 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10565 11:36:51.076417 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10566 11:36:51.091352 <6>[ 11.389565] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10567 11:36:51.101616 <6>[ 11.398631] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10568 11:36:51.112565 [[0;32m OK [<6>[ 11.406662] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10569 11:36:51.118188 0m] Started [0;<6>[ 11.407944] remoteproc remoteproc0: scp is available
10570 11:36:51.124582 <6>[ 11.416597] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10571 11:36:51.131735 1;39mfstrim.time<6>[ 11.432124] remoteproc remoteproc0: powering up scp
10572 11:36:51.141019 r[0m - Discard <6>[ 11.438619] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10573 11:36:51.151176 unused blocks on<3>[ 11.442270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10574 11:36:51.151254 ce a week.
10575 11:36:51.161488 <6>[ 11.445724] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10576 11:36:51.164199 <6>[ 11.448359] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10577 11:36:51.174153 <6>[ 11.463358] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10578 11:36:51.182477 <3>[ 11.466550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10579 11:36:51.190901 <4>[ 11.481771] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10580 11:36:51.194516 <4>[ 11.481771] Fallback method does not support PEC.
10581 11:36:51.205023 <3>[ 11.488279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 11:36:51.210799 <3>[ 11.488463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10583 11:36:51.217602 <6>[ 11.499120] mc: Linux media interface: v0.10
10584 11:36:51.223917 <6>[ 11.506232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10585 11:36:51.233517 <3>[ 11.510031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10586 11:36:51.240068 <3>[ 11.510042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 11:36:51.246654 <6>[ 11.518120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10588 11:36:51.257204 <3>[ 11.522644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10589 11:36:51.266425 <4>[ 11.530917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10590 11:36:51.273886 <4>[ 11.536661] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10591 11:36:51.279937 <6>[ 11.536746] videodev: Linux video capture interface: v2.00
10592 11:36:51.287313 <4>[ 11.538703] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10593 11:36:51.294135 <3>[ 11.538719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10594 11:36:51.304133 <3>[ 11.547155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 11:36:51.311214 <6>[ 11.555392] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10596 11:36:51.316678 <3>[ 11.567561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 11:36:51.326607 <6>[ 11.571814] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10598 11:36:51.333798 <6>[ 11.573844] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10599 11:36:51.341284 <6>[ 11.573851] remoteproc remoteproc0: remote processor scp is now up
10600 11:36:51.347390 <6>[ 11.573854] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10601 11:36:51.357785 <3>[ 11.579233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10602 11:36:51.364032 <6>[ 11.586755] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10603 11:36:51.370881 <6>[ 11.588249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10604 11:36:51.377027 <6>[ 11.588262] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10605 11:36:51.387394 <6>[ 11.588265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10606 11:36:51.394250 <6>[ 11.588267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10607 11:36:51.404669 <3>[ 11.592277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 11:36:51.411377 <3>[ 11.592500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 11:36:51.421101 <3>[ 11.592509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 11:36:51.427605 <3>[ 11.599586] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 11:36:51.435093 <6>[ 11.600647] pci_bus 0000:00: root bus resource [bus 00-ff]
10612 11:36:51.444496 <3>[ 11.608662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 11:36:51.450581 <3>[ 11.608668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 11:36:51.457325 <6>[ 11.616741] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10615 11:36:51.467358 <6>[ 11.618131] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10616 11:36:51.475317 <6>[ 11.619951] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10617 11:36:51.483931 <3>[ 11.624817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10618 11:36:51.493633 <6>[ 11.632719] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10619 11:36:51.500353 <3>[ 11.641247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10620 11:36:51.511171 <3>[ 11.645540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 11:36:51.517006 <3>[ 11.646233] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10622 11:36:51.523543 <6>[ 11.647686] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10623 11:36:51.533397 <6>[ 11.648644] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10624 11:36:51.543215 <6>[ 11.665275] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10625 11:36:51.549640 <6>[ 11.669652] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10626 11:36:51.557088 <6>[ 11.669714] pci 0000:00:00.0: supports D1 D2
10627 11:36:51.563341 <6>[ 11.678228] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10628 11:36:51.569799 <6>[ 11.685382] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10629 11:36:51.579387 <6>[ 11.686279] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10630 11:36:51.590098 <3>[ 11.709166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 11:36:51.593008 <6>[ 11.710775] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10632 11:36:51.599559 <6>[ 11.719803] Bluetooth: Core ver 2.22
10633 11:36:51.606837 <6>[ 11.726778] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10634 11:36:51.612554 <6>[ 11.735648] NET: Registered PF_BLUETOOTH protocol family
10635 11:36:51.619168 <6>[ 11.741288] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10636 11:36:51.625854 <6>[ 11.749371] Bluetooth: HCI device and connection manager initialized
10637 11:36:51.633179 <6>[ 11.757457] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10638 11:36:51.639146 <6>[ 11.758689] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10639 11:36:51.652724 <6>[ 11.759880] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10640 11:36:51.658802 <6>[ 11.759979] usbcore: registered new interface driver uvcvideo
10641 11:36:51.662597 <6>[ 11.764927] Bluetooth: HCI socket layer initialized
10642 11:36:51.669491 <6>[ 11.773114] pci 0000:01:00.0: supports D1 D2
10643 11:36:51.672172 <6>[ 11.781204] Bluetooth: L2CAP socket layer initialized
10644 11:36:51.678695 <6>[ 11.789273] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10645 11:36:51.685344 <6>[ 11.789971] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10646 11:36:51.692162 <6>[ 11.799191] Bluetooth: SCO socket layer initialized
10647 11:36:51.698964 <6>[ 11.800700] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10648 11:36:51.704906 <6>[ 11.800725] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10649 11:36:51.715265 <6>[ 11.800729] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10650 11:36:51.722666 <6>[ 11.800736] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10651 11:36:51.731904 <6>[ 11.800749] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10652 11:36:51.738660 <6>[ 11.800761] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10653 11:36:51.745255 <6>[ 11.800773] pci 0000:00:00.0: PCI bridge to [bus 01]
10654 11:36:51.751544 <6>[ 11.800778] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10655 11:36:51.758427 <6>[ 11.807368] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10656 11:36:51.764833 <6>[ 11.886183] usbcore: registered new interface driver btusb
10657 11:36:51.774465 <4>[ 11.887281] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10658 11:36:51.781434 <3>[ 11.887296] Bluetooth: hci0: Failed to load firmware file (-2)
10659 11:36:51.787824 <3>[ 11.887303] Bluetooth: hci0: Failed to set up firmware (-2)
10660 11:36:51.798095 <4>[ 11.887309] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10661 11:36:51.804419 <6>[ 11.896757] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10662 11:36:51.811094 [[0;32m OK [<6>[ 12.110452] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10663 11:36:51.817587 0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10664 11:36:51.827074 <5>[ 12.125433] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10665 11:36:51.837505 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10666 11:36:51.850481 <5>[ 12.147863] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10667 11:36:51.856583 <5>[ 12.154886] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10668 11:36:51.866404 <4>[ 12.163298] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10669 11:36:51.873087 <3>[ 12.164058] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10670 11:36:51.879818 <6>[ 12.172167] cfg80211: failed to load regulatory.db
10671 11:36:51.887257 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10672 11:36:51.919754 <3>[ 12.218196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 11:36:51.926528 <6>[ 12.226831] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10674 11:36:51.933089 <6>[ 12.234484] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10675 11:36:51.950233 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration..<3>[ 12.247787] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10676 11:36:51.950317 .
10677 11:36:51.956613 <6>[ 12.258241] mt7921e 0000:01:00.0: ASIC revision: 79610010
10678 11:36:51.968979 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10679 11:36:51.982744 <3>[ 12.279970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 11:36:52.031710 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10681 11:36:52.062389 <6>[ 12.360587] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10682 11:36:52.065906 <6>[ 12.360587]
10683 11:36:52.104227 Startin<3>[ 12.397852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10684 11:36:52.106427 g [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10685 11:36:52.132769 [[0;32m OK [<3>[ 12.428122] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 11:36:52.139497 0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10687 11:36:52.154598 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10688 11:36:52.219539 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10689 11:36:52.241790 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10690 11:36:52.263083 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10691 11:36:52.279660 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10692 11:36:52.299410 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10693 11:36:52.333579 <6>[ 12.630892] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10694 11:36:52.361382 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10695 11:36:52.386969 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10696 11:36:52.412490 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10697 11:36:52.432683 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10698 11:36:52.475273 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10699 11:36:52.496666 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10700 11:36:52.516772 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10701 11:36:52.531803 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10702 11:36:52.552003 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10703 11:36:52.622774 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10704 11:36:52.647780 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10705 11:36:52.670246 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10706 11:36:52.711371 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10707 11:36:52.761080
10708 11:36:52.764347 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10709 11:36:52.764423
10710 11:36:52.768702 debian-bookworm-arm64 login: root (automatic login)
10711 11:36:52.768776
10712 11:36:52.783086 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
10713 11:36:52.783161
10714 11:36:52.789165 The programs included with the Debian GNU/Linux system are free software;
10715 11:36:52.796187 the exact distribution terms for each program are described in the
10716 11:36:52.799450 individual files in /usr/share/doc/*/copyright.
10717 11:36:52.799525
10718 11:36:52.805585 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10719 11:36:52.809576 permitted by applicable law.
10720 11:36:52.809939 Matched prompt #10: / #
10722 11:36:52.810123 Setting prompt string to ['/ #']
10723 11:36:52.810209 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10725 11:36:52.810379 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10726 11:36:52.810459 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10727 11:36:52.810517 Setting prompt string to ['/ #']
10728 11:36:52.810569 Forcing a shell prompt, looking for ['/ #']
10729 11:36:52.810621 Sending line: ''
10731 11:36:52.860910 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10732 11:36:52.860997 Waiting using forced prompt support (timeout 00:02:30)
10733 11:36:52.866239 / #
10734 11:36:52.866498 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10735 11:36:52.866584 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10736 11:36:52.866668 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10737 11:36:52.866743 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10738 11:36:52.866820 end: 2 depthcharge-action (duration 00:01:26) [common]
10739 11:36:52.866898 start: 3 lava-test-retry (timeout 00:08:13) [common]
10740 11:36:52.866983 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10741 11:36:52.867051 Using namespace: common
10742 11:36:52.867112 Sending line: '#'
10744 11:36:52.967518 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10745 11:36:52.973002 / # #
10746 11:36:52.973255 Using /lava-14864607
10747 11:36:52.973320 Sending line: 'export SHELL=/bin/sh'
10749 11:36:53.079864 / # export SHELL=/bin/sh
10750 11:36:53.080107 Sending line: '. /lava-14864607/environment'
10752 11:36:53.185200 / # . /lava-14864607/environment
10753 11:36:53.185504 Sending line: '/lava-14864607/bin/lava-test-runner /lava-14864607/0'
10755 11:36:53.285942 Test shell timeout: 10s (minimum of the action and connection timeout)
10756 11:36:53.286192 / # <6>[ 13.504522] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10757 11:36:53.291230 /lava-14864607/bin/lava-test-runner /lava-14864607/0
10758 11:36:53.333386 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10759 11:36:53.333478 + cd /lava-14864607/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10760 11:36:53.333538 + cat uuid
10761 11:36:53.333594 + UUID=14864607_1.5.2.3.1
10762 11:36:53.333647 + set +x
10763 11:36:53.336002 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14864607_1.5.2.3.1>
10764 11:36:53.336258 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14864607_1.5.2.3.1
10765 11:36:53.336325 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14864607_1.5.2.3.1)
10766 11:36:53.336401 Skipping test definition patterns.
10767 11:36:53.340085 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10768 11:36:53.345963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10769 11:36:53.346039 device: /dev/video2
10770 11:36:53.346263 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10772 11:36:53.366514 <4>[ 13.664427] use of bytesused == 0 is deprecated and will be removed in the future,
10773 11:36:53.369725 <4>[ 13.672281] use the actual size instead.
10774 11:36:53.384679 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10775 11:36:53.394964 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10776 11:36:53.401005
10777 11:36:53.415091 Compliance test for mtk-vcodec-enc device /dev/video2:
10778 11:36:53.420962
10779 11:36:53.430593 Driver Info:
10780 11:36:53.442300 Driver name : mtk-vcodec-enc
10781 11:36:53.455158 Card type : MT8192 video encoder
10782 11:36:53.466395 Bus info : platform:17020000.vcodec
10783 11:36:53.473631 Driver version : 6.1.96
10784 11:36:53.483205 Capabilities : 0x84204000
10785 11:36:53.495182 Video Memory-to-Memory Multiplanar
10786 11:36:53.508126 Streaming
10787 11:36:53.517883 Extended Pix Format
10788 11:36:53.527639 Device Capabilities
10789 11:36:53.538590 Device Caps : 0x04204000
10790 11:36:53.552885 Video Memory-to-Memory Multiplanar
10791 11:36:53.562849 Streaming
10792 11:36:53.574089 Extended Pix Format
10793 11:36:53.583709 Detected Stateful Encoder
10794 11:36:53.592921
10795 11:36:53.605131 Required ioctls:
10796 11:36:53.621028 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10797 11:36:53.621103 test VIDIOC_QUERYCAP: OK
10798 11:36:53.621333 Received signal: <TESTSET> START Required-ioctls
10799 11:36:53.621398 Starting test_set Required-ioctls
10800 11:36:53.645392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10801 11:36:53.645636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10803 11:36:53.648473 test invalid ioctls: OK
10804 11:36:53.669406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10805 11:36:53.669487
10806 11:36:53.669734 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10808 11:36:53.679715 Allow for multiple opens:
10809 11:36:53.686106 <LAVA_SIGNAL_TESTSET STOP>
10810 11:36:53.686347 Received signal: <TESTSET> STOP
10811 11:36:53.686410 Closing test_set Required-ioctls
10812 11:36:53.693918 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10813 11:36:53.694159 Received signal: <TESTSET> START Allow-for-multiple-opens
10814 11:36:53.694221 Starting test_set Allow-for-multiple-opens
10815 11:36:53.697193 test second /dev/video2 open: OK
10816 11:36:53.719156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10817 11:36:53.719400 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10819 11:36:53.721376 test VIDIOC_QUERYCAP: OK
10820 11:36:53.742228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10821 11:36:53.742476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10823 11:36:53.746137 test VIDIOC_G/S_PRIORITY: OK
10824 11:36:53.771069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10825 11:36:53.771329 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10827 11:36:53.774049 test for unlimited opens: OK
10828 11:36:53.795430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10829 11:36:53.795501
10830 11:36:53.795723 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10832 11:36:53.807226 Debug ioctls:
10833 11:36:53.816586 <LAVA_SIGNAL_TESTSET STOP>
10834 11:36:53.816843 Received signal: <TESTSET> STOP
10835 11:36:53.816912 Closing test_set Allow-for-multiple-opens
10836 11:36:53.827996 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10837 11:36:53.828258 Received signal: <TESTSET> START Debug-ioctls
10838 11:36:53.828350 Starting test_set Debug-ioctls
10839 11:36:53.830967 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10840 11:36:53.851701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10841 11:36:53.851959 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10843 11:36:53.858315 test VIDIOC_LOG_STATUS: OK (Not Supported)
10844 11:36:53.877950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10845 11:36:53.878019
10846 11:36:53.878239 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10848 11:36:53.888021 Input ioctls:
10849 11:36:53.894112 <LAVA_SIGNAL_TESTSET STOP>
10850 11:36:53.894346 Received signal: <TESTSET> STOP
10851 11:36:53.894406 Closing test_set Debug-ioctls
10852 11:36:53.903001 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10853 11:36:53.903239 Received signal: <TESTSET> START Input-ioctls
10854 11:36:53.903298 Starting test_set Input-ioctls
10855 11:36:53.906055 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10856 11:36:53.932007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10857 11:36:53.932245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10859 11:36:53.934915 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10860 11:36:53.950069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10861 11:36:53.950312 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10863 11:36:53.956418 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10864 11:36:53.974908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10865 11:36:53.975150 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10867 11:36:53.982023 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10868 11:36:53.998082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10869 11:36:53.998324 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10871 11:36:54.004057 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
10872 11:36:54.023686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10873 11:36:54.023926 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10875 11:36:54.026895 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10876 11:36:54.049411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10877 11:36:54.049654 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
10879 11:36:54.052169 Inputs: 0 Audio Inputs: 0 Tuners: 0
10880 11:36:54.059392
10881 11:36:54.079629 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
10882 11:36:54.100179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
10883 11:36:54.100592 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
10885 11:36:54.106831 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10886 11:36:54.124601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10887 11:36:54.125217 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10889 11:36:54.130253 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
10890 11:36:54.154035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
10891 11:36:54.154664 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
10893 11:36:54.160599 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
10894 11:36:54.178387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
10895 11:36:54.179005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
10897 11:36:54.185330 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
10898 11:36:54.201188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
10899 11:36:54.201608
10900 11:36:54.202145 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
10902 11:36:54.220738 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
10903 11:36:54.249028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
10904 11:36:54.249706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
10906 11:36:54.254829 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
10907 11:36:54.276124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
10908 11:36:54.276742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
10910 11:36:54.279208 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
10911 11:36:54.295893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
10912 11:36:54.296514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
10914 11:36:54.299406 test VIDIOC_G/S_EDID: OK (Not Supported)
10915 11:36:54.319227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
10916 11:36:54.319633
10917 11:36:54.320159 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
10919 11:36:54.329343 Control ioctls:
10920 11:36:54.337277 <LAVA_SIGNAL_TESTSET STOP>
10921 11:36:54.337969 Received signal: <TESTSET> STOP
10922 11:36:54.338459 Closing test_set Input-ioctls
10923 11:36:54.346637 <LAVA_SIGNAL_TESTSET START Control-ioctls>
10924 11:36:54.347498 Received signal: <TESTSET> START Control-ioctls
10925 11:36:54.347901 Starting test_set Control-ioctls
10926 11:36:54.350042 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
10927 11:36:54.375273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
10928 11:36:54.375715 test VIDIOC_QUERYCTRL: OK
10929 11:36:54.376258 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
10931 11:36:54.400026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
10932 11:36:54.400741 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
10934 11:36:54.402944 test VIDIOC_G/S_CTRL: OK
10935 11:36:54.425641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
10936 11:36:54.426268 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
10938 11:36:54.429199 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
10939 11:36:54.448312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
10940 11:36:54.449082 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
10942 11:36:54.454716 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
10943 11:36:54.463304 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
10944 11:36:54.491574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
10945 11:36:54.492238 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
10947 11:36:54.495313 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
10948 11:36:54.513936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
10949 11:36:54.514586 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
10951 11:36:54.516484 Standard Controls: 16 Private Controls: 0
10952 11:36:54.522528
10953 11:36:54.533098 Format ioctls:
10954 11:36:54.538962 <LAVA_SIGNAL_TESTSET STOP>
10955 11:36:54.539569 Received signal: <TESTSET> STOP
10956 11:36:54.539876 Closing test_set Control-ioctls
10957 11:36:54.549290 <LAVA_SIGNAL_TESTSET START Format-ioctls>
10958 11:36:54.549902 Received signal: <TESTSET> START Format-ioctls
10959 11:36:54.550214 Starting test_set Format-ioctls
10960 11:36:54.551697 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
10961 11:36:54.576863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
10962 11:36:54.577518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
10964 11:36:54.580265 test VIDIOC_G/S_PARM: OK
10965 11:36:54.596414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
10966 11:36:54.597028 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
10968 11:36:54.599740 test VIDIOC_G_FBUF: OK (Not Supported)
10969 11:36:54.621802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
10970 11:36:54.622412 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
10972 11:36:54.625109 test VIDIOC_G_FMT: OK
10973 11:36:54.646340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
10974 11:36:54.646951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
10976 11:36:54.649848 test VIDIOC_TRY_FMT: OK
10977 11:36:54.672314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
10978 11:36:54.672926 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
10980 11:36:54.677507 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
10981 11:36:54.683066 test VIDIOC_S_FMT: FAIL
10982 11:36:54.708216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
10983 11:36:54.708826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
10985 11:36:54.711586 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
10986 11:36:54.731354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
10987 11:36:54.731970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
10989 11:36:54.735612 test Cropping: OK
10990 11:36:54.759169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
10991 11:36:54.759779 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
10993 11:36:54.762346 test Composing: OK (Not Supported)
10994 11:36:54.782975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
10995 11:36:54.783622 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
10997 11:36:54.786953 test Scaling: OK (Not Supported)
10998 11:36:54.805595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
10999 11:36:54.805979
11000 11:36:54.806501 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11002 11:36:54.817497 Codec ioctls:
11003 11:36:54.825099 <LAVA_SIGNAL_TESTSET STOP>
11004 11:36:54.825738 Received signal: <TESTSET> STOP
11005 11:36:54.826049 Closing test_set Format-ioctls
11006 11:36:54.834990 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11007 11:36:54.835607 Received signal: <TESTSET> START Codec-ioctls
11008 11:36:54.835927 Starting test_set Codec-ioctls
11009 11:36:54.838478 test VIDIOC_(TRY_)ENCODER_CMD: OK
11010 11:36:54.858742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11011 11:36:54.859522 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11013 11:36:54.865033 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11014 11:36:54.881715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11015 11:36:54.882335 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11017 11:36:54.889092 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11018 11:36:54.905954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11019 11:36:54.906465
11020 11:36:54.907119 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11022 11:36:54.916379 Buffer ioctls:
11023 11:36:54.923519 <LAVA_SIGNAL_TESTSET STOP>
11024 11:36:54.924291 Received signal: <TESTSET> STOP
11025 11:36:54.924728 Closing test_set Codec-ioctls
11026 11:36:54.933048 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11027 11:36:54.933691 Received signal: <TESTSET> START Buffer-ioctls
11028 11:36:54.933999 Starting test_set Buffer-ioctls
11029 11:36:54.935438 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11030 11:36:54.965020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11031 11:36:54.965678 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11033 11:36:54.968666 test CREATE_BUFS maximum buffers: OK
11034 11:36:54.984424 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11036 11:36:54.987192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11037 11:36:54.987538 test VIDIOC_EXPBUF: OK
11038 11:36:55.012052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11039 11:36:55.012662 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11041 11:36:55.014924 test Requests: OK (Not Supported)
11042 11:36:55.035840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11043 11:36:55.036225
11044 11:36:55.036756 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11046 11:36:55.049629 Test input 0:
11047 11:36:55.058820
11048 11:36:55.068732 Streaming ioctls:
11049 11:36:55.075045 <LAVA_SIGNAL_TESTSET STOP>
11050 11:36:55.075653 Received signal: <TESTSET> STOP
11051 11:36:55.075962 Closing test_set Buffer-ioctls
11052 11:36:55.083919 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11053 11:36:55.084530 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11054 11:36:55.084841 Starting test_set Streaming-ioctls_Test-input-0
11055 11:36:55.087918 test read/write: OK (Not Supported)
11056 11:36:55.113713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11057 11:36:55.114511 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11059 11:36:55.120089 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11060 11:36:55.126535 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11061 11:36:55.134391 test blocking wait: FAIL
11062 11:36:55.157342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11063 11:36:55.158037 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11065 11:36:55.164149 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11066 11:36:55.167891 test MMAP (select): FAIL
11067 11:36:55.202748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11068 11:36:55.203375 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11070 11:36:55.209143 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11071 11:36:55.216352 test MMAP (epoll): FAIL
11072 11:36:55.239180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11073 11:36:55.239800 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11075 11:36:55.246235 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11076 11:36:55.254706 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11077 11:36:55.264954 test USERPTR (select): FAIL
11078 11:36:55.289783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11079 11:36:55.290401 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11081 11:36:55.296571 test DMABUF: Cannot test, specify --expbuf-device
11082 11:36:55.299655
11083 11:36:55.319336 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11084 11:36:55.320824 <LAVA_TEST_RUNNER EXIT>
11085 11:36:55.321442 ok: lava_test_shell seems to have completed
11086 11:36:55.321776 Marking unfinished test run as failed
11088 11:36:55.325734 device-presence: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video2-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls
result: fail
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls
result: pass
VIDIOC_G_FMT:
set: Format-ioctls
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls
result: pass
VIDIOC_S_FMT:
set: Format-ioctls
result: fail
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls
result: pass
Cropping:
set: Format-ioctls
result: pass
Composing:
set: Format-ioctls
result: pass
Scaling:
set: Format-ioctls
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls
result: pass
Requests:
set: Buffer-ioctls
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: fail
11089 11:36:55.326632 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11090 11:36:55.327179 end: 3 lava-test-retry (duration 00:00:02) [common]
11091 11:36:55.327732 start: 4 finalize (timeout 00:08:10) [common]
11092 11:36:55.328179 start: 4.1 power-off (timeout 00:00:30) [common]
11093 11:36:55.328770 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11094 11:36:57.437505 >> Command sent successfully.
11095 11:36:57.453997 Returned 0 in 2 seconds
11096 11:36:57.454695 end: 4.1 power-off (duration 00:00:02) [common]
11098 11:36:57.456155 start: 4.2 read-feedback (timeout 00:08:08) [common]
11099 11:36:57.456974 Listened to connection for namespace 'common' for up to 1s
11100 11:36:58.457425 Finalising connection for namespace 'common'
11101 11:36:58.457935 Disconnecting from shell: Finalise
11102 11:36:58.458271 / #
11103 11:36:58.558939 end: 4.2 read-feedback (duration 00:00:01) [common]
11104 11:36:58.559446 end: 4 finalize (duration 00:00:03) [common]
11105 11:36:58.559950 Cleaning after the job
11106 11:36:58.560394 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/ramdisk
11107 11:36:58.576079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/kernel
11108 11:36:58.607359 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/dtb
11109 11:36:58.607694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864607/tftp-deploy-3gvh_9_g/modules
11110 11:36:58.615431 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864607
11111 11:36:58.682695 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864607
11112 11:36:58.682876 Job finished correctly