Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 1
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 87
1 11:36:39.931540 lava-dispatcher, installed at version: 2024.05
2 11:36:39.931764 start: 0 validate
3 11:36:39.931903 Start time: 2024-07-17 11:36:39.931889+00:00 (UTC)
4 11:36:39.932049 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:36:39.932237 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:36:40.193047 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:36:40.193223 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:36:40.450513 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:36:40.450726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 11:36:40.708450 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:36:40.708616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:36:40.958514 validate duration: 1.03
14 11:36:40.958788 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:36:40.958892 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:36:40.958982 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:36:40.959148 Not decompressing ramdisk as can be used compressed.
18 11:36:40.959238 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:36:40.959307 saving as /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/ramdisk/rootfs.cpio.gz
20 11:36:40.959371 total size: 28105535 (26 MB)
21 11:36:40.960425 progress 0 % (0 MB)
22 11:36:40.968274 progress 5 % (1 MB)
23 11:36:40.976231 progress 10 % (2 MB)
24 11:36:40.983858 progress 15 % (4 MB)
25 11:36:40.991450 progress 20 % (5 MB)
26 11:36:40.999141 progress 25 % (6 MB)
27 11:36:41.006750 progress 30 % (8 MB)
28 11:36:41.014322 progress 35 % (9 MB)
29 11:36:41.021860 progress 40 % (10 MB)
30 11:36:41.029186 progress 45 % (12 MB)
31 11:36:41.036740 progress 50 % (13 MB)
32 11:36:41.044254 progress 55 % (14 MB)
33 11:36:41.051874 progress 60 % (16 MB)
34 11:36:41.059417 progress 65 % (17 MB)
35 11:36:41.067047 progress 70 % (18 MB)
36 11:36:41.074593 progress 75 % (20 MB)
37 11:36:41.082105 progress 80 % (21 MB)
38 11:36:41.089647 progress 85 % (22 MB)
39 11:36:41.097073 progress 90 % (24 MB)
40 11:36:41.104559 progress 95 % (25 MB)
41 11:36:41.112093 progress 100 % (26 MB)
42 11:36:41.112350 26 MB downloaded in 0.15 s (175.22 MB/s)
43 11:36:41.112523 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:36:41.112766 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:36:41.112853 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:36:41.112938 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:36:41.113087 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:36:41.113157 saving as /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/kernel/Image
50 11:36:41.113216 total size: 54813184 (52 MB)
51 11:36:41.113276 No compression specified
52 11:36:41.114369 progress 0 % (0 MB)
53 11:36:41.128898 progress 5 % (2 MB)
54 11:36:41.143550 progress 10 % (5 MB)
55 11:36:41.157982 progress 15 % (7 MB)
56 11:36:41.172754 progress 20 % (10 MB)
57 11:36:41.188614 progress 25 % (13 MB)
58 11:36:41.204256 progress 30 % (15 MB)
59 11:36:41.219481 progress 35 % (18 MB)
60 11:36:41.234193 progress 40 % (20 MB)
61 11:36:41.248754 progress 45 % (23 MB)
62 11:36:41.263512 progress 50 % (26 MB)
63 11:36:41.278334 progress 55 % (28 MB)
64 11:36:41.292758 progress 60 % (31 MB)
65 11:36:41.307377 progress 65 % (34 MB)
66 11:36:41.321781 progress 70 % (36 MB)
67 11:36:41.336396 progress 75 % (39 MB)
68 11:36:41.350965 progress 80 % (41 MB)
69 11:36:41.365428 progress 85 % (44 MB)
70 11:36:41.379956 progress 90 % (47 MB)
71 11:36:41.394506 progress 95 % (49 MB)
72 11:36:41.408844 progress 100 % (52 MB)
73 11:36:41.409104 52 MB downloaded in 0.30 s (176.67 MB/s)
74 11:36:41.409261 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:36:41.409489 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:36:41.409577 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:36:41.409661 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:36:41.409801 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 11:36:41.409870 saving as /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 11:36:41.409930 total size: 57695 (0 MB)
82 11:36:41.409988 No compression specified
83 11:36:41.411051 progress 56 % (0 MB)
84 11:36:41.411331 progress 100 % (0 MB)
85 11:36:41.411550 0 MB downloaded in 0.00 s (34.03 MB/s)
86 11:36:41.411674 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:36:41.411896 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:36:41.411978 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:36:41.412065 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:36:41.412185 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:36:41.412252 saving as /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/modules/modules.tar
93 11:36:41.412311 total size: 8610184 (8 MB)
94 11:36:41.412370 Using unxz to decompress xz
95 11:36:41.413758 progress 0 % (0 MB)
96 11:36:41.436225 progress 5 % (0 MB)
97 11:36:41.463046 progress 10 % (0 MB)
98 11:36:41.490128 progress 15 % (1 MB)
99 11:36:41.516916 progress 20 % (1 MB)
100 11:36:41.542814 progress 25 % (2 MB)
101 11:36:41.569029 progress 30 % (2 MB)
102 11:36:41.594533 progress 35 % (2 MB)
103 11:36:41.624843 progress 40 % (3 MB)
104 11:36:41.652726 progress 45 % (3 MB)
105 11:36:41.681368 progress 50 % (4 MB)
106 11:36:41.709924 progress 55 % (4 MB)
107 11:36:41.737609 progress 60 % (4 MB)
108 11:36:41.763420 progress 65 % (5 MB)
109 11:36:41.791594 progress 70 % (5 MB)
110 11:36:41.821717 progress 75 % (6 MB)
111 11:36:41.852154 progress 80 % (6 MB)
112 11:36:41.878500 progress 85 % (7 MB)
113 11:36:41.904479 progress 90 % (7 MB)
114 11:36:41.930506 progress 95 % (7 MB)
115 11:36:41.955700 progress 100 % (8 MB)
116 11:36:41.961707 8 MB downloaded in 0.55 s (14.95 MB/s)
117 11:36:41.961887 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:36:41.962125 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:36:41.962213 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:36:41.962300 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:36:41.962382 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:36:41.962460 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:36:41.962647 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79
125 11:36:41.962779 makedir: /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin
126 11:36:41.962883 makedir: /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/tests
127 11:36:41.962980 makedir: /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/results
128 11:36:41.963078 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-add-keys
129 11:36:41.963220 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-add-sources
130 11:36:41.963351 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-background-process-start
131 11:36:41.963505 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-background-process-stop
132 11:36:41.963660 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-common-functions
133 11:36:41.963790 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-echo-ipv4
134 11:36:41.963925 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-install-packages
135 11:36:41.964053 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-installed-packages
136 11:36:41.964180 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-os-build
137 11:36:41.964304 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-probe-channel
138 11:36:41.964448 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-probe-ip
139 11:36:41.964620 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-target-ip
140 11:36:41.964789 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-target-mac
141 11:36:41.964939 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-target-storage
142 11:36:41.965071 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-case
143 11:36:41.965203 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-event
144 11:36:41.965330 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-feedback
145 11:36:41.965455 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-raise
146 11:36:41.965582 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-reference
147 11:36:41.965705 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-runner
148 11:36:41.965828 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-set
149 11:36:41.965955 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-test-shell
150 11:36:41.966087 Updating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-install-packages (oe)
151 11:36:41.966239 Updating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/bin/lava-installed-packages (oe)
152 11:36:41.966369 Creating /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/environment
153 11:36:41.966472 LAVA metadata
154 11:36:41.966544 - LAVA_JOB_ID=14864642
155 11:36:41.966605 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:36:41.966704 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:36:41.966766 skipped lava-vland-overlay
158 11:36:41.966845 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:36:41.966924 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:36:41.966986 skipped lava-multinode-overlay
161 11:36:41.967060 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:36:41.967136 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:36:41.967207 Loading test definitions
164 11:36:41.967292 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:36:41.967363 Using /lava-14864642 at stage 0
166 11:36:41.967699 uuid=14864642_1.5.2.3.1 testdef=None
167 11:36:41.967788 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:36:41.967872 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:36:41.968414 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:36:41.968725 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:36:41.969354 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:36:41.969584 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:36:41.970186 runner path: /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/0/tests/0_v4l2-compliance-uvc test_uuid 14864642_1.5.2.3.1
176 11:36:41.970343 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:36:41.970555 Creating lava-test-runner.conf files
179 11:36:41.970617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864642/lava-overlay-60qlua79/lava-14864642/0 for stage 0
180 11:36:41.970708 - 0_v4l2-compliance-uvc
181 11:36:41.970805 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:36:41.970888 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:36:41.978025 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:36:41.978142 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:36:41.978228 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:36:41.978317 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:36:41.978399 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:36:42.856061 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:36:42.856217 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:36:42.856303 extracting modules file /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864642/extract-overlay-ramdisk-486g1obs/ramdisk
191 11:36:43.117840 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:36:43.117989 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:36:43.118083 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864642/compress-overlay-ueux6627/overlay-1.5.2.4.tar.gz to ramdisk
194 11:36:43.118150 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864642/compress-overlay-ueux6627/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864642/extract-overlay-ramdisk-486g1obs/ramdisk
195 11:36:43.125779 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:36:43.125892 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:36:43.126033 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:36:43.126166 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:36:43.126273 Building ramdisk /var/lib/lava/dispatcher/tmp/14864642/extract-overlay-ramdisk-486g1obs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864642/extract-overlay-ramdisk-486g1obs/ramdisk
200 11:36:43.741871 >> 275512 blocks
201 11:36:48.542046 rename /var/lib/lava/dispatcher/tmp/14864642/extract-overlay-ramdisk-486g1obs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/ramdisk/ramdisk.cpio.gz
202 11:36:48.542211 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:36:48.542309 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 11:36:48.542414 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 11:36:48.542521 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/kernel/Image']
206 11:37:03.675812 Returned 0 in 15 seconds
207 11:37:03.676038 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/kernel/image.itb
208 11:37:04.324269 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:37:04.324401 output: Created: Wed Jul 17 12:37:04 2024
210 11:37:04.324469 output: Image 0 (kernel-1)
211 11:37:04.324531 output: Description:
212 11:37:04.324589 output: Created: Wed Jul 17 12:37:04 2024
213 11:37:04.324646 output: Type: Kernel Image
214 11:37:04.324702 output: Compression: lzma compressed
215 11:37:04.324760 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:37:04.324819 output: Architecture: AArch64
217 11:37:04.324874 output: OS: Linux
218 11:37:04.324928 output: Load Address: 0x00000000
219 11:37:04.324982 output: Entry Point: 0x00000000
220 11:37:04.325037 output: Hash algo: crc32
221 11:37:04.325091 output: Hash value: 83448d17
222 11:37:04.325146 output: Image 1 (fdt-1)
223 11:37:04.325199 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 11:37:04.325254 output: Created: Wed Jul 17 12:37:04 2024
225 11:37:04.325307 output: Type: Flat Device Tree
226 11:37:04.325360 output: Compression: uncompressed
227 11:37:04.325414 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 11:37:04.325468 output: Architecture: AArch64
229 11:37:04.325523 output: Hash algo: crc32
230 11:37:04.325576 output: Hash value: a9713552
231 11:37:04.325629 output: Image 2 (ramdisk-1)
232 11:37:04.325682 output: Description: unavailable
233 11:37:04.325735 output: Created: Wed Jul 17 12:37:04 2024
234 11:37:04.325788 output: Type: RAMDisk Image
235 11:37:04.325841 output: Compression: uncompressed
236 11:37:04.325895 output: Data Size: 41201711 Bytes = 40236.05 KiB = 39.29 MiB
237 11:37:04.325948 output: Architecture: AArch64
238 11:37:04.326001 output: OS: Linux
239 11:37:04.326054 output: Load Address: unavailable
240 11:37:04.326107 output: Entry Point: unavailable
241 11:37:04.326160 output: Hash algo: crc32
242 11:37:04.326213 output: Hash value: f0aa7d4e
243 11:37:04.326265 output: Default Configuration: 'conf-1'
244 11:37:04.326318 output: Configuration 0 (conf-1)
245 11:37:04.326372 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 11:37:04.326425 output: Kernel: kernel-1
247 11:37:04.326478 output: Init Ramdisk: ramdisk-1
248 11:37:04.326531 output: FDT: fdt-1
249 11:37:04.326584 output: Loadables: kernel-1
250 11:37:04.326637 output:
251 11:37:04.326745 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 11:37:04.326828 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 11:37:04.326909 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 11:37:04.326992 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 11:37:04.327056 No LXC device requested
256 11:37:04.327133 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:37:04.327213 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 11:37:04.327289 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:37:04.327349 Checking files for TFTP limit of 4294967296 bytes.
260 11:37:04.327774 end: 1 tftp-deploy (duration 00:00:23) [common]
261 11:37:04.327873 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:37:04.327960 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:37:04.328059 substitutions:
264 11:37:04.328127 - {DTB}: 14864642/tftp-deploy-7mqfe8wa/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 11:37:04.328191 - {INITRD}: 14864642/tftp-deploy-7mqfe8wa/ramdisk/ramdisk.cpio.gz
266 11:37:04.328251 - {KERNEL}: 14864642/tftp-deploy-7mqfe8wa/kernel/Image
267 11:37:04.328309 - {LAVA_MAC}: None
268 11:37:04.328367 - {PRESEED_CONFIG}: None
269 11:37:04.328422 - {PRESEED_LOCAL}: None
270 11:37:04.328479 - {RAMDISK}: 14864642/tftp-deploy-7mqfe8wa/ramdisk/ramdisk.cpio.gz
271 11:37:04.328540 - {ROOT_PART}: None
272 11:37:04.328596 - {ROOT}: None
273 11:37:04.328651 - {SERVER_IP}: 192.168.201.1
274 11:37:04.328706 - {TEE}: None
275 11:37:04.328761 Parsed boot commands:
276 11:37:04.328814 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:37:04.328968 Parsed boot commands: tftpboot 192.168.201.1 14864642/tftp-deploy-7mqfe8wa/kernel/image.itb 14864642/tftp-deploy-7mqfe8wa/kernel/cmdline
278 11:37:04.329057 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:37:04.329138 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:37:04.329219 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:37:04.329298 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:37:04.329359 Not connected, no need to disconnect.
283 11:37:04.329432 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:37:04.329508 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:37:04.329572 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
286 11:37:04.332551 Setting prompt string to ['lava-test: # ']
287 11:37:04.332894 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:37:04.332998 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:37:04.333099 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:37:04.333188 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:37:04.333392 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=reboot']
292 11:37:13.500694 >> Command sent successfully.
293 11:37:13.504389 Returned 0 in 9 seconds
294 11:37:13.504561 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:37:13.504790 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:37:13.504883 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:37:13.504963 Setting prompt string to 'Starting depthcharge on Juniper...'
299 11:37:13.505025 Changing prompt to 'Starting depthcharge on Juniper...'
300 11:37:13.505092 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
301 11:37:13.505462 [Enter `^Ec?' for help]
302 11:37:20.146402 [DL] 00000000 00000000 010701
303 11:37:20.151657
304 11:37:20.151748
305 11:37:20.151813 F0: 102B 0000
306 11:37:20.151879
307 11:37:20.154994 F3: 1006 0033 [0200]
308 11:37:20.155102
309 11:37:20.155171 F3: 4001 00E0 [0200]
310 11:37:20.155230
311 11:37:20.155288 F3: 0000 0000
312 11:37:20.158022
313 11:37:20.158108 V0: 0000 0000 [0001]
314 11:37:20.158174
315 11:37:20.158231 00: 1027 0002
316 11:37:20.161495
317 11:37:20.161560 01: 0000 0000
318 11:37:20.161620
319 11:37:20.161675 BP: 0C00 0251 [0000]
320 11:37:20.161729
321 11:37:20.164821 G0: 1182 0000
322 11:37:20.164904
323 11:37:20.164968 EC: 0004 0000 [0001]
324 11:37:20.165028
325 11:37:20.168141 S7: 0000 0000 [0000]
326 11:37:20.168224
327 11:37:20.171369 CC: 0000 0000 [0001]
328 11:37:20.171451
329 11:37:20.171542 T0: 0000 00DB [000F]
330 11:37:20.171604
331 11:37:20.171662 Jump to BL
332 11:37:20.174449
333 11:37:20.207615
334 11:37:20.207745
335 11:37:20.217530 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
336 11:37:20.220560 ARM64: Exception handlers installed.
337 11:37:20.220648 ARM64: Testing exception
338 11:37:20.223847 ARM64: Done test exception
339 11:37:20.227397 WDT: Last reset was cold boot
340 11:37:20.231033 SPI0(PAD0) initialized at 992727 Hz
341 11:37:20.234117 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
342 11:37:20.234204 Manufacturer: ef
343 11:37:20.240814 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
344 11:37:20.254433 Probing TPM: . done!
345 11:37:20.254548 TPM ready after 0 ms
346 11:37:20.260999 Connected to device vid:did:rid of 1ae0:0028:00
347 11:37:20.270726 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-afa1dd1
348 11:37:20.300881 Initialized TPM device CR50 revision 0
349 11:37:20.312924 tlcl_send_startup: Startup return code is 0
350 11:37:20.313035 TPM: setup succeeded
351 11:37:20.320902 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
352 11:37:20.324092 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
353 11:37:20.327371 in-header: 03 19 00 00 08 00 00 00
354 11:37:20.330764 in-data: a2 e0 47 00 13 00 00 00
355 11:37:20.333937 Chrome EC: UHEPI supported
356 11:37:20.340749 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
357 11:37:20.343906 in-header: 03 a1 00 00 08 00 00 00
358 11:37:20.347217 in-data: 84 60 60 10 00 00 00 00
359 11:37:20.347305 Phase 1
360 11:37:20.350638 FMAP: area GBB found @ 3f5000 (12032 bytes)
361 11:37:20.357104 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
362 11:37:20.363475 VB2:vb2_check_recovery() Recovery was requested manually
363 11:37:20.366844 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
364 11:37:20.370617 Recovery requested (1009000e)
365 11:37:20.379651 tlcl_extend: response is 0
366 11:37:20.387892 tlcl_extend: response is 0
367 11:37:20.412646
368 11:37:20.412753
369 11:37:20.422724 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
370 11:37:20.426123 ARM64: Exception handlers installed.
371 11:37:20.426211 ARM64: Testing exception
372 11:37:20.429194 ARM64: Done test exception
373 11:37:20.444834 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x926b, sec=0x203a
374 11:37:20.451596 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
375 11:37:20.454867 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
376 11:37:20.463124 [RTC]rtc_get_frequency_meter,134: input=0xf, output=863
377 11:37:20.470299 [RTC]rtc_get_frequency_meter,134: input=0x7, output=732
378 11:37:20.477118 [RTC]rtc_get_frequency_meter,134: input=0xb, output=798
379 11:37:20.483975 [RTC]rtc_get_frequency_meter,134: input=0x9, output=765
380 11:37:20.490886 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
381 11:37:20.497926 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
382 11:37:20.504622 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
383 11:37:20.511313 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x926b
384 11:37:20.514623 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
385 11:37:20.517788 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
386 11:37:20.524358 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
387 11:37:20.527432 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
388 11:37:20.531007 in-header: 03 19 00 00 08 00 00 00
389 11:37:20.534259 in-data: a2 e0 47 00 13 00 00 00
390 11:37:20.534338 Chrome EC: UHEPI supported
391 11:37:20.540915 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
392 11:37:20.544212 in-header: 03 a1 00 00 08 00 00 00
393 11:37:20.547231 in-data: 84 60 60 10 00 00 00 00
394 11:37:20.550760 Skip loading cached calibration data
395 11:37:20.557228 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
396 11:37:20.560565 in-header: 03 a1 00 00 08 00 00 00
397 11:37:20.563639 in-data: 84 60 60 10 00 00 00 00
398 11:37:20.570494 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
399 11:37:20.573468 in-header: 03 a1 00 00 08 00 00 00
400 11:37:20.577075 in-data: 84 60 60 10 00 00 00 00
401 11:37:20.580176 ADC[3]: Raw value=216116 ID=1
402 11:37:20.583549 Manufacturer: ef
403 11:37:20.586936 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
404 11:37:20.593339 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
405 11:37:20.593427 CBFS @ 21000 size 3d4000
406 11:37:20.599725 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
407 11:37:20.603079 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
408 11:37:20.606533 CBFS: Found @ offset 3c700 size 44
409 11:37:20.609848 DRAM-K: Full Calibration
410 11:37:20.613015 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:37:20.616314 CBFS @ 21000 size 3d4000
412 11:37:20.622925 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
413 11:37:20.623012 CBFS: Locating 'fallback/dram'
414 11:37:20.629419 CBFS: Found @ offset 24b00 size 12268
415 11:37:20.656099 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
416 11:37:20.659016 ddr_geometry: 1, config: 0x0
417 11:37:20.662399 header.status = 0x0
418 11:37:20.665750 header.magic = 0x44524d4b (expected: 0x44524d4b)
419 11:37:20.668920 header.version = 0x5 (expected: 0x5)
420 11:37:20.672067 header.size = 0x8f0 (expected: 0x8f0)
421 11:37:20.675341 header.config = 0x0
422 11:37:20.675426 header.flags = 0x0
423 11:37:20.678707 header.checksum = 0x0
424 11:37:20.685238 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
425 11:37:20.688704 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
426 11:37:20.695040 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
427 11:37:20.695127 ddr_geometry:1
428 11:37:20.698438 [EMI] new MDL number = 1
429 11:37:20.698522 dram_cbt_mode_extern: 0
430 11:37:20.701472 dram_cbt_mode [RK0]: 0, [RK1]: 0
431 11:37:20.708681 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
432 11:37:20.708765
433 11:37:20.708830
434 11:37:20.712074 [Bianco] ETT version 0.0.0.1
435 11:37:20.715142 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
436 11:37:20.715226
437 11:37:20.718452 vSetVcoreByFreq with vcore:762500, freq=1600
438 11:37:20.718536
439 11:37:20.721763 [DramcInit]
440 11:37:20.725050 AutoRefreshCKEOff AutoREF OFF
441 11:37:20.725139 DDRPhyPLLSetting-CKEOFF
442 11:37:20.728439 DDRPhyPLLSetting-CKEON
443 11:37:20.728523
444 11:37:20.728588 Enable WDQS
445 11:37:20.733245 [ModeRegInit_LP4] CH0 RK0
446 11:37:20.736588 Write Rank0 MR13 =0x18
447 11:37:20.736673 Write Rank0 MR12 =0x5d
448 11:37:20.739569 Write Rank0 MR1 =0x56
449 11:37:20.743218 Write Rank0 MR2 =0x1a
450 11:37:20.743309 Write Rank0 MR11 =0x0
451 11:37:20.746133 Write Rank0 MR22 =0x38
452 11:37:20.749529 Write Rank0 MR14 =0x5d
453 11:37:20.749614 Write Rank0 MR3 =0x30
454 11:37:20.752590 Write Rank0 MR13 =0x58
455 11:37:20.752674 Write Rank0 MR12 =0x5d
456 11:37:20.755955 Write Rank0 MR1 =0x56
457 11:37:20.759357 Write Rank0 MR2 =0x2d
458 11:37:20.759440 Write Rank0 MR11 =0x23
459 11:37:20.762396 Write Rank0 MR22 =0x34
460 11:37:20.765862 Write Rank0 MR14 =0x10
461 11:37:20.765946 Write Rank0 MR3 =0x30
462 11:37:20.769201 Write Rank0 MR13 =0xd8
463 11:37:20.769285 [ModeRegInit_LP4] CH0 RK1
464 11:37:20.772500 Write Rank1 MR13 =0x18
465 11:37:20.775796 Write Rank1 MR12 =0x5d
466 11:37:20.775883 Write Rank1 MR1 =0x56
467 11:37:20.778780 Write Rank1 MR2 =0x1a
468 11:37:20.782116 Write Rank1 MR11 =0x0
469 11:37:20.782201 Write Rank1 MR22 =0x38
470 11:37:20.785406 Write Rank1 MR14 =0x5d
471 11:37:20.785490 Write Rank1 MR3 =0x30
472 11:37:20.788570 Write Rank1 MR13 =0x58
473 11:37:20.791836 Write Rank1 MR12 =0x5d
474 11:37:20.791919 Write Rank1 MR1 =0x56
475 11:37:20.795264 Write Rank1 MR2 =0x2d
476 11:37:20.798386 Write Rank1 MR11 =0x23
477 11:37:20.798482 Write Rank1 MR22 =0x34
478 11:37:20.801712 Write Rank1 MR14 =0x10
479 11:37:20.801801 Write Rank1 MR3 =0x30
480 11:37:20.804873 Write Rank1 MR13 =0xd8
481 11:37:20.808268 [ModeRegInit_LP4] CH1 RK0
482 11:37:20.808349 Write Rank0 MR13 =0x18
483 11:37:20.811687 Write Rank0 MR12 =0x5d
484 11:37:20.814836 Write Rank0 MR1 =0x56
485 11:37:20.814916 Write Rank0 MR2 =0x1a
486 11:37:20.817955 Write Rank0 MR11 =0x0
487 11:37:20.818030 Write Rank0 MR22 =0x38
488 11:37:20.821289 Write Rank0 MR14 =0x5d
489 11:37:20.824596 Write Rank0 MR3 =0x30
490 11:37:20.824670 Write Rank0 MR13 =0x58
491 11:37:20.827980 Write Rank0 MR12 =0x5d
492 11:37:20.831144 Write Rank0 MR1 =0x56
493 11:37:20.831218 Write Rank0 MR2 =0x2d
494 11:37:20.834613 Write Rank0 MR11 =0x23
495 11:37:20.834730 Write Rank0 MR22 =0x34
496 11:37:20.837789 Write Rank0 MR14 =0x10
497 11:37:20.841159 Write Rank0 MR3 =0x30
498 11:37:20.841271 Write Rank0 MR13 =0xd8
499 11:37:20.844180 [ModeRegInit_LP4] CH1 RK1
500 11:37:20.847717 Write Rank1 MR13 =0x18
501 11:37:20.847828 Write Rank1 MR12 =0x5d
502 11:37:20.850941 Write Rank1 MR1 =0x56
503 11:37:20.851053 Write Rank1 MR2 =0x1a
504 11:37:20.854227 Write Rank1 MR11 =0x0
505 11:37:20.857347 Write Rank1 MR22 =0x38
506 11:37:20.857433 Write Rank1 MR14 =0x5d
507 11:37:20.860711 Write Rank1 MR3 =0x30
508 11:37:20.863777 Write Rank1 MR13 =0x58
509 11:37:20.863855 Write Rank1 MR12 =0x5d
510 11:37:20.867101 Write Rank1 MR1 =0x56
511 11:37:20.867181 Write Rank1 MR2 =0x2d
512 11:37:20.870476 Write Rank1 MR11 =0x23
513 11:37:20.873965 Write Rank1 MR22 =0x34
514 11:37:20.874082 Write Rank1 MR14 =0x10
515 11:37:20.877153 Write Rank1 MR3 =0x30
516 11:37:20.880459 Write Rank1 MR13 =0xd8
517 11:37:20.880563 match AC timing 3
518 11:37:20.890397 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
519 11:37:20.890515 [MiockJmeterHQA]
520 11:37:20.896686 vSetVcoreByFreq with vcore:762500, freq=1600
521 11:37:21.001191
522 11:37:21.001328 MIOCK jitter meter ch=0
523 11:37:21.001399
524 11:37:21.004452 1T = (102-18) = 84 dly cells
525 11:37:21.010979 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
526 11:37:21.014196 vSetVcoreByFreq with vcore:725000, freq=1200
527 11:37:21.114853
528 11:37:21.114990 MIOCK jitter meter ch=0
529 11:37:21.115060
530 11:37:21.118056 1T = (97-17) = 80 dly cells
531 11:37:21.124644 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
532 11:37:21.127668 vSetVcoreByFreq with vcore:725000, freq=800
533 11:37:21.227955
534 11:37:21.228093 MIOCK jitter meter ch=0
535 11:37:21.228177
536 11:37:21.231299 1T = (97-17) = 80 dly cells
537 11:37:21.237727 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
538 11:37:21.241171 vSetVcoreByFreq with vcore:762500, freq=1600
539 11:37:21.244274 vSetVcoreByFreq with vcore:762500, freq=1600
540 11:37:21.244353
541 11:37:21.244425 K DRVP
542 11:37:21.247655 1. OCD DRVP=0 CALOUT=0
543 11:37:21.250743 1. OCD DRVP=1 CALOUT=0
544 11:37:21.250828 1. OCD DRVP=2 CALOUT=0
545 11:37:21.253922 1. OCD DRVP=3 CALOUT=0
546 11:37:21.257410 1. OCD DRVP=4 CALOUT=0
547 11:37:21.257488 1. OCD DRVP=5 CALOUT=0
548 11:37:21.260513 1. OCD DRVP=6 CALOUT=0
549 11:37:21.263811 1. OCD DRVP=7 CALOUT=0
550 11:37:21.263888 1. OCD DRVP=8 CALOUT=1
551 11:37:21.263952
552 11:37:21.267068 1. OCD DRVP calibration OK! DRVP=8
553 11:37:21.267143
554 11:37:21.267203
555 11:37:21.267262
556 11:37:21.270298 K ODTN
557 11:37:21.270378 3. OCD ODTN=0 ,CALOUT=1
558 11:37:21.273639 3. OCD ODTN=1 ,CALOUT=1
559 11:37:21.277041 3. OCD ODTN=2 ,CALOUT=1
560 11:37:21.277121 3. OCD ODTN=3 ,CALOUT=1
561 11:37:21.280481 3. OCD ODTN=4 ,CALOUT=1
562 11:37:21.280562 3. OCD ODTN=5 ,CALOUT=1
563 11:37:21.283533 3. OCD ODTN=6 ,CALOUT=1
564 11:37:21.286904 3. OCD ODTN=7 ,CALOUT=0
565 11:37:21.286982
566 11:37:21.290315 3. OCD ODTN calibration OK! ODTN=7
567 11:37:21.290392
568 11:37:21.293527 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
569 11:37:21.296696 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
570 11:37:21.303158 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
571 11:37:21.303268
572 11:37:21.303361 K DRVP
573 11:37:21.306598 1. OCD DRVP=0 CALOUT=0
574 11:37:21.306699 1. OCD DRVP=1 CALOUT=0
575 11:37:21.309924 1. OCD DRVP=2 CALOUT=0
576 11:37:21.312893 1. OCD DRVP=3 CALOUT=0
577 11:37:21.312976 1. OCD DRVP=4 CALOUT=0
578 11:37:21.316469 1. OCD DRVP=5 CALOUT=0
579 11:37:21.316547 1. OCD DRVP=6 CALOUT=0
580 11:37:21.319619 1. OCD DRVP=7 CALOUT=0
581 11:37:21.322969 1. OCD DRVP=8 CALOUT=0
582 11:37:21.323043 1. OCD DRVP=9 CALOUT=0
583 11:37:21.326263 1. OCD DRVP=10 CALOUT=1
584 11:37:21.326342
585 11:37:21.329570 1. OCD DRVP calibration OK! DRVP=10
586 11:37:21.329650
587 11:37:21.329712
588 11:37:21.329771
589 11:37:21.329828 K ODTN
590 11:37:21.332659 3. OCD ODTN=0 ,CALOUT=1
591 11:37:21.336011 3. OCD ODTN=1 ,CALOUT=1
592 11:37:21.336087 3. OCD ODTN=2 ,CALOUT=1
593 11:37:21.339228 3. OCD ODTN=3 ,CALOUT=1
594 11:37:21.342575 3. OCD ODTN=4 ,CALOUT=1
595 11:37:21.342657 3. OCD ODTN=5 ,CALOUT=1
596 11:37:21.345852 3. OCD ODTN=6 ,CALOUT=1
597 11:37:21.348995 3. OCD ODTN=7 ,CALOUT=1
598 11:37:21.349089 3. OCD ODTN=8 ,CALOUT=1
599 11:37:21.352318 3. OCD ODTN=9 ,CALOUT=1
600 11:37:21.355620 3. OCD ODTN=10 ,CALOUT=1
601 11:37:21.355714 3. OCD ODTN=11 ,CALOUT=1
602 11:37:21.358717 3. OCD ODTN=12 ,CALOUT=1
603 11:37:21.362168 3. OCD ODTN=13 ,CALOUT=1
604 11:37:21.362255 3. OCD ODTN=14 ,CALOUT=1
605 11:37:21.365560 3. OCD ODTN=15 ,CALOUT=0
606 11:37:21.365646
607 11:37:21.368669 3. OCD ODTN calibration OK! ODTN=15
608 11:37:21.368756
609 11:37:21.371929 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
610 11:37:21.375172 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
611 11:37:21.381706 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
612 11:37:21.381800
613 11:37:21.381868 [DramcInit]
614 11:37:21.384997 AutoRefreshCKEOff AutoREF OFF
615 11:37:21.388510 DDRPhyPLLSetting-CKEOFF
616 11:37:21.391593 DDRPhyPLLSetting-CKEON
617 11:37:21.391677
618 11:37:21.391742 Enable WDQS
619 11:37:21.391801 ==
620 11:37:21.398327 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
621 11:37:21.401557 fsp= 1, odt_onoff= 1, Byte mode= 0
622 11:37:21.401644 ==
623 11:37:21.401710 [Duty_Offset_Calibration]
624 11:37:21.401771
625 11:37:21.404613 ===========================
626 11:37:21.408003 B0:1 B1:-1 CA:0
627 11:37:21.427364 ==
628 11:37:21.430845 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
629 11:37:21.434156 fsp= 1, odt_onoff= 1, Byte mode= 0
630 11:37:21.434242 ==
631 11:37:21.437222 [Duty_Offset_Calibration]
632 11:37:21.437306
633 11:37:21.440577 ===========================
634 11:37:21.440663 B0:0 B1:0 CA:0
635 11:37:21.472920 [ModeRegInit_LP4] CH0 RK0
636 11:37:21.476091 Write Rank0 MR13 =0x18
637 11:37:21.476188 Write Rank0 MR12 =0x5d
638 11:37:21.479394 Write Rank0 MR1 =0x56
639 11:37:21.482744 Write Rank0 MR2 =0x1a
640 11:37:21.482830 Write Rank0 MR11 =0x0
641 11:37:21.486224 Write Rank0 MR22 =0x38
642 11:37:21.489182 Write Rank0 MR14 =0x5d
643 11:37:21.489266 Write Rank0 MR3 =0x30
644 11:37:21.492603 Write Rank0 MR13 =0x58
645 11:37:21.492707 Write Rank0 MR12 =0x5d
646 11:37:21.496058 Write Rank0 MR1 =0x56
647 11:37:21.499126 Write Rank0 MR2 =0x2d
648 11:37:21.499236 Write Rank0 MR11 =0x23
649 11:37:21.502539 Write Rank0 MR22 =0x34
650 11:37:21.505610 Write Rank0 MR14 =0x10
651 11:37:21.505694 Write Rank0 MR3 =0x30
652 11:37:21.508853 Write Rank0 MR13 =0xd8
653 11:37:21.508937 [ModeRegInit_LP4] CH0 RK1
654 11:37:21.512316 Write Rank1 MR13 =0x18
655 11:37:21.515719 Write Rank1 MR12 =0x5d
656 11:37:21.515803 Write Rank1 MR1 =0x56
657 11:37:21.518897 Write Rank1 MR2 =0x1a
658 11:37:21.522285 Write Rank1 MR11 =0x0
659 11:37:21.522369 Write Rank1 MR22 =0x38
660 11:37:21.525446 Write Rank1 MR14 =0x5d
661 11:37:21.525530 Write Rank1 MR3 =0x30
662 11:37:21.528455 Write Rank1 MR13 =0x58
663 11:37:21.531930 Write Rank1 MR12 =0x5d
664 11:37:21.532042 Write Rank1 MR1 =0x56
665 11:37:21.535166 Write Rank1 MR2 =0x2d
666 11:37:21.538338 Write Rank1 MR11 =0x23
667 11:37:21.538424 Write Rank1 MR22 =0x34
668 11:37:21.541966 Write Rank1 MR14 =0x10
669 11:37:21.542052 Write Rank1 MR3 =0x30
670 11:37:21.545414 Write Rank1 MR13 =0xd8
671 11:37:21.548430 [ModeRegInit_LP4] CH1 RK0
672 11:37:21.548514 Write Rank0 MR13 =0x18
673 11:37:21.551383 Write Rank0 MR12 =0x5d
674 11:37:21.555082 Write Rank0 MR1 =0x56
675 11:37:21.555166 Write Rank0 MR2 =0x1a
676 11:37:21.557940 Write Rank0 MR11 =0x0
677 11:37:21.558023 Write Rank0 MR22 =0x38
678 11:37:21.561560 Write Rank0 MR14 =0x5d
679 11:37:21.564703 Write Rank0 MR3 =0x30
680 11:37:21.564787 Write Rank0 MR13 =0x58
681 11:37:21.567947 Write Rank0 MR12 =0x5d
682 11:37:21.571051 Write Rank0 MR1 =0x56
683 11:37:21.571135 Write Rank0 MR2 =0x2d
684 11:37:21.574301 Write Rank0 MR11 =0x23
685 11:37:21.574413 Write Rank0 MR22 =0x34
686 11:37:21.577633 Write Rank0 MR14 =0x10
687 11:37:21.581085 Write Rank0 MR3 =0x30
688 11:37:21.581170 Write Rank0 MR13 =0xd8
689 11:37:21.584206 [ModeRegInit_LP4] CH1 RK1
690 11:37:21.587558 Write Rank1 MR13 =0x18
691 11:37:21.587644 Write Rank1 MR12 =0x5d
692 11:37:21.590946 Write Rank1 MR1 =0x56
693 11:37:21.591029 Write Rank1 MR2 =0x1a
694 11:37:21.594006 Write Rank1 MR11 =0x0
695 11:37:21.597346 Write Rank1 MR22 =0x38
696 11:37:21.597430 Write Rank1 MR14 =0x5d
697 11:37:21.600779 Write Rank1 MR3 =0x30
698 11:37:21.604140 Write Rank1 MR13 =0x58
699 11:37:21.604223 Write Rank1 MR12 =0x5d
700 11:37:21.607108 Write Rank1 MR1 =0x56
701 11:37:21.607192 Write Rank1 MR2 =0x2d
702 11:37:21.610540 Write Rank1 MR11 =0x23
703 11:37:21.613887 Write Rank1 MR22 =0x34
704 11:37:21.613971 Write Rank1 MR14 =0x10
705 11:37:21.617126 Write Rank1 MR3 =0x30
706 11:37:21.620229 Write Rank1 MR13 =0xd8
707 11:37:21.620313 match AC timing 3
708 11:37:21.630036 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
709 11:37:21.633275 DramC Write-DBI off
710 11:37:21.633364 DramC Read-DBI off
711 11:37:21.636769 Write Rank0 MR13 =0x59
712 11:37:21.636854 ==
713 11:37:21.639934 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
714 11:37:21.643220 fsp= 1, odt_onoff= 1, Byte mode= 0
715 11:37:21.643303 ==
716 11:37:21.646679 === u2Vref_new: 0x56 --> 0x2d
717 11:37:21.649681 === u2Vref_new: 0x58 --> 0x38
718 11:37:21.653135 === u2Vref_new: 0x5a --> 0x39
719 11:37:21.656428 === u2Vref_new: 0x5c --> 0x3c
720 11:37:21.659386 === u2Vref_new: 0x5e --> 0x3d
721 11:37:21.662862 === u2Vref_new: 0x60 --> 0xa0
722 11:37:21.665892 [CA 0] Center 34 (6~63) winsize 58
723 11:37:21.669285 [CA 1] Center 35 (7~63) winsize 57
724 11:37:21.672526 [CA 2] Center 28 (-1~58) winsize 60
725 11:37:21.675880 [CA 3] Center 23 (-4~51) winsize 56
726 11:37:21.679163 [CA 4] Center 24 (-4~53) winsize 58
727 11:37:21.682258 [CA 5] Center 30 (1~59) winsize 59
728 11:37:21.682364
729 11:37:21.685535 [CATrainingPosCal] consider 1 rank data
730 11:37:21.688851 u2DelayCellTimex100 = 744/100 ps
731 11:37:21.692342 CA0 delay=34 (6~63),Diff = 11 PI (14 cell)
732 11:37:21.695648 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
733 11:37:21.698686 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
734 11:37:21.702149 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
735 11:37:21.708654 CA4 delay=24 (-4~53),Diff = 1 PI (1 cell)
736 11:37:21.712064 CA5 delay=30 (1~59),Diff = 7 PI (9 cell)
737 11:37:21.712147
738 11:37:21.715084 CA PerBit enable=1, Macro0, CA PI delay=23
739 11:37:21.718406 === u2Vref_new: 0x5c --> 0x3c
740 11:37:21.718490
741 11:37:21.718556 Vref(ca) range 1: 28
742 11:37:21.718617
743 11:37:21.721846 CS Dly= 8 (39-0-32)
744 11:37:21.724889 Write Rank0 MR13 =0xd8
745 11:37:21.724973 Write Rank0 MR13 =0xd8
746 11:37:21.728147 Write Rank0 MR12 =0x5c
747 11:37:21.728231 Write Rank1 MR13 =0x59
748 11:37:21.731505 ==
749 11:37:21.734772 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
750 11:37:21.738111 fsp= 1, odt_onoff= 1, Byte mode= 0
751 11:37:21.738200 ==
752 11:37:21.741208 === u2Vref_new: 0x56 --> 0x2d
753 11:37:21.744583 === u2Vref_new: 0x58 --> 0x38
754 11:37:21.748009 === u2Vref_new: 0x5a --> 0x39
755 11:37:21.751201 === u2Vref_new: 0x5c --> 0x3c
756 11:37:21.754175 === u2Vref_new: 0x5e --> 0x3d
757 11:37:21.757516 === u2Vref_new: 0x60 --> 0xa0
758 11:37:21.760844 [CA 0] Center 35 (7~63) winsize 57
759 11:37:21.764204 [CA 1] Center 35 (7~63) winsize 57
760 11:37:21.767610 [CA 2] Center 28 (-1~58) winsize 60
761 11:37:21.770702 [CA 3] Center 23 (-5~51) winsize 57
762 11:37:21.773962 [CA 4] Center 24 (-4~52) winsize 57
763 11:37:21.777342 [CA 5] Center 29 (0~59) winsize 60
764 11:37:21.777426
765 11:37:21.780532 [CATrainingPosCal] consider 2 rank data
766 11:37:21.783830 u2DelayCellTimex100 = 744/100 ps
767 11:37:21.786925 CA0 delay=35 (7~63),Diff = 12 PI (15 cell)
768 11:37:21.790583 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
769 11:37:21.793688 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
770 11:37:21.797180 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
771 11:37:21.800254 CA4 delay=24 (-4~52),Diff = 1 PI (1 cell)
772 11:37:21.803360 CA5 delay=30 (1~59),Diff = 7 PI (9 cell)
773 11:37:21.803478
774 11:37:21.809860 CA PerBit enable=1, Macro0, CA PI delay=23
775 11:37:21.809945 === u2Vref_new: 0x5e --> 0x3d
776 11:37:21.810012
777 11:37:21.813242 Vref(ca) range 1: 30
778 11:37:21.813326
779 11:37:21.816619 CS Dly= 5 (36-0-32)
780 11:37:21.816702 Write Rank1 MR13 =0xd8
781 11:37:21.819917 Write Rank1 MR13 =0xd8
782 11:37:21.823236 Write Rank1 MR12 =0x5e
783 11:37:21.826579 [RankSwap] Rank num 2, (Multi 1), Rank 0
784 11:37:21.826663 Write Rank0 MR2 =0xad
785 11:37:21.829577 [Write Leveling]
786 11:37:21.832996 delay byte0 byte1 byte2 byte3
787 11:37:21.833080
788 11:37:21.833145 10 0 0
789 11:37:21.836052 11 0 0
790 11:37:21.836136 12 0 0
791 11:37:21.836202 13 0 0
792 11:37:21.839370 14 0 0
793 11:37:21.839491 15 0 0
794 11:37:21.842554 16 0 0
795 11:37:21.842642 17 0 0
796 11:37:21.846082 18 0 0
797 11:37:21.846168 19 0 0
798 11:37:21.846232 20 0 0
799 11:37:21.849212 21 0 0
800 11:37:21.849294 22 0 0
801 11:37:21.852634 23 0 0
802 11:37:21.852712 24 0 0
803 11:37:21.852786 25 0 0
804 11:37:21.855916 26 0 0
805 11:37:21.855990 27 0 ff
806 11:37:21.858991 28 0 ff
807 11:37:21.859071 29 0 ff
808 11:37:21.862367 30 0 ff
809 11:37:21.862438 31 ff ff
810 11:37:21.865548 32 ff ff
811 11:37:21.865631 33 ff ff
812 11:37:21.868875 34 ff ff
813 11:37:21.868973 35 ff ff
814 11:37:21.872183 36 ff ff
815 11:37:21.872262 37 ff ff
816 11:37:21.875557 pass bytecount = 0xff (0xff: all bytes pass)
817 11:37:21.875633
818 11:37:21.878707 DQS0 dly: 31
819 11:37:21.878786 DQS1 dly: 27
820 11:37:21.881850 Write Rank0 MR2 =0x2d
821 11:37:21.885264 [RankSwap] Rank num 2, (Multi 1), Rank 0
822 11:37:21.885356 Write Rank0 MR1 =0xd6
823 11:37:21.888611 [Gating]
824 11:37:21.888687 ==
825 11:37:21.891856 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
826 11:37:21.895074 fsp= 1, odt_onoff= 1, Byte mode= 0
827 11:37:21.895161 ==
828 11:37:21.901904 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
829 11:37:21.904982 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
830 11:37:21.908330 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(0 0)| 0
831 11:37:21.914659 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
832 11:37:21.918222 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
833 11:37:21.921200 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
834 11:37:21.928004 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
835 11:37:21.931052 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
836 11:37:21.934453 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
837 11:37:21.940958 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
838 11:37:21.944475 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
839 11:37:21.947529 3 2 12 |201 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
840 11:37:21.950873 3 2 16 |3534 303 |(11 11)(11 11) |(0 0)(0 0)| 0
841 11:37:21.957414 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
842 11:37:21.960822 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
843 11:37:21.967268 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
844 11:37:21.970278 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
845 11:37:21.973708 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
846 11:37:21.976866 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
847 11:37:21.983360 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
848 11:37:21.986835 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
849 11:37:21.990241 [Byte 0] Lead/lag Transition tap number (1)
850 11:37:21.996756 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
851 11:37:21.999709 [Byte 1] Lead/lag falling Transition (3, 3, 20)
852 11:37:22.003131 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
853 11:37:22.009599 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
854 11:37:22.012960 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
855 11:37:22.016250 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
856 11:37:22.022886 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
857 11:37:22.025957 3 4 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
858 11:37:22.029221 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
859 11:37:22.035926 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
860 11:37:22.039057 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 11:37:22.042455 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 11:37:22.049002 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 11:37:22.052365 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 11:37:22.055545 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 11:37:22.061941 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 11:37:22.065409 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
867 11:37:22.068709 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
868 11:37:22.075056 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
869 11:37:22.078422 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
870 11:37:22.081681 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
871 11:37:22.088289 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
872 11:37:22.092107 [Byte 0] Lead/lag falling Transition (3, 6, 4)
873 11:37:22.094790 [Byte 1] Lead/lag falling Transition (3, 6, 4)
874 11:37:22.098347 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
875 11:37:22.104508 [Byte 0] Lead/lag Transition tap number (2)
876 11:37:22.107914 3 6 12 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
877 11:37:22.111396 [Byte 1] Lead/lag Transition tap number (3)
878 11:37:22.114612 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
879 11:37:22.117887 [Byte 0]First pass (3, 6, 16)
880 11:37:22.120896 3 6 20 |4646 606 |(0 0)(1 1) |(0 0)(0 0)| 0
881 11:37:22.127596 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 11:37:22.127734 [Byte 1]First pass (3, 6, 24)
883 11:37:22.134098 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 11:37:22.137415 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 11:37:22.140807 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 11:37:22.143869 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
887 11:37:22.150334 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
888 11:37:22.153752 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
889 11:37:22.156962 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
890 11:37:22.160320 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
891 11:37:22.163720 All bytes gating window > 1UI, Early break!
892 11:37:22.163804
893 11:37:22.170063 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 8)
894 11:37:22.170150
895 11:37:22.173557 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
896 11:37:22.173641
897 11:37:22.173706
898 11:37:22.173765
899 11:37:22.176613 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
900 11:37:22.176697
901 11:37:22.180411 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
902 11:37:22.180496
903 11:37:22.180561
904 11:37:22.183094 Write Rank0 MR1 =0x56
905 11:37:22.183177
906 11:37:22.186631 best RODT dly(2T, 0.5T) = (2, 3)
907 11:37:22.186715
908 11:37:22.189936 best RODT dly(2T, 0.5T) = (2, 3)
909 11:37:22.190019 ==
910 11:37:22.193147 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
911 11:37:22.196502 fsp= 1, odt_onoff= 1, Byte mode= 0
912 11:37:22.199818 ==
913 11:37:22.202841 Start DQ dly to find pass range UseTestEngine =0
914 11:37:22.206129 x-axis: bit #, y-axis: DQ dly (-127~63)
915 11:37:22.206214 RX Vref Scan = 0
916 11:37:22.209499 -26, [0] xxxxxxxx xxxxxxxx [MSB]
917 11:37:22.212523 -25, [0] xxxxxxxx xxxxxxxx [MSB]
918 11:37:22.216206 -24, [0] xxxxxxxx xxxxxxxx [MSB]
919 11:37:22.219408 -23, [0] xxxxxxxx xxxxxxxx [MSB]
920 11:37:22.222400 -22, [0] xxxxxxxx xxxxxxxx [MSB]
921 11:37:22.225742 -21, [0] xxxxxxxx xxxxxxxx [MSB]
922 11:37:22.228956 -20, [0] xxxxxxxx xxxxxxxx [MSB]
923 11:37:22.232296 -19, [0] xxxxxxxx xxxxxxxx [MSB]
924 11:37:22.232382 -18, [0] xxxxxxxx xxxxxxxx [MSB]
925 11:37:22.235746 -17, [0] xxxxxxxx xxxxxxxx [MSB]
926 11:37:22.238773 -16, [0] xxxxxxxx xxxxxxxx [MSB]
927 11:37:22.242065 -15, [0] xxxxxxxx xxxxxxxx [MSB]
928 11:37:22.245443 -14, [0] xxxxxxxx xxxxxxxx [MSB]
929 11:37:22.248761 -13, [0] xxxxxxxx xxxxxxxx [MSB]
930 11:37:22.252177 -12, [0] xxxxxxxx xxxxxxxx [MSB]
931 11:37:22.255270 -11, [0] xxxxxxxx xxxxxxxx [MSB]
932 11:37:22.258516 -10, [0] xxxxxxxx xxxxxxxx [MSB]
933 11:37:22.258607 -9, [0] xxxxxxxx xxxxxxxx [MSB]
934 11:37:22.261885 -8, [0] xxxxxxxx xxxxxxxx [MSB]
935 11:37:22.265099 -7, [0] xxxxxxxx xxxxxxxx [MSB]
936 11:37:22.268104 -6, [0] xxxxxxxx xxxxxxxx [MSB]
937 11:37:22.271609 -5, [0] xxxxxxxx xxxxxxxx [MSB]
938 11:37:22.275001 -4, [0] xxxxxxxx xxxxxxxx [MSB]
939 11:37:22.278109 -3, [0] xxxxxxxx oxxxxxxx [MSB]
940 11:37:22.281552 -2, [0] xxxoxxxx oxxoxxxx [MSB]
941 11:37:22.281676 -1, [0] xxxoxxxx oxxoxxxx [MSB]
942 11:37:22.284878 0, [0] xxxoxxxx ooxoxoxx [MSB]
943 11:37:22.288074 1, [0] xxxoxoxx ooxoooxx [MSB]
944 11:37:22.291571 2, [0] xxxoxoox ooxoooox [MSB]
945 11:37:22.294753 3, [0] xxxoxoox ooxoooox [MSB]
946 11:37:22.297762 4, [0] xxxoxoox ooxoooox [MSB]
947 11:37:22.297877 5, [0] xxxooooo ooxooooo [MSB]
948 11:37:22.301182 6, [0] oxoooooo ooxooooo [MSB]
949 11:37:22.304418 32, [0] oooxoooo oooooooo [MSB]
950 11:37:22.307554 33, [0] oooxoooo xooooooo [MSB]
951 11:37:22.311130 34, [0] oooxoooo xooxoooo [MSB]
952 11:37:22.314272 35, [0] oooxoooo xxoxxooo [MSB]
953 11:37:22.317479 36, [0] oooxoxoo xxoxxoxo [MSB]
954 11:37:22.320912 37, [0] oooxoxxo xxoxxxxo [MSB]
955 11:37:22.320999 38, [0] oooxoxxx xxoxxxxo [MSB]
956 11:37:22.324067 39, [0] oooxoxxx xxoxxxxx [MSB]
957 11:37:22.327287 40, [0] oooxoxxx xxoxxxxx [MSB]
958 11:37:22.330687 41, [0] xxxxxxxx xxoxxxxx [MSB]
959 11:37:22.333707 42, [0] xxxxxxxx xxxxxxxx [MSB]
960 11:37:22.336981 iDelay=42, Bit 0, Center 23 (6 ~ 40) 35
961 11:37:22.340468 iDelay=42, Bit 1, Center 23 (7 ~ 40) 34
962 11:37:22.343666 iDelay=42, Bit 2, Center 23 (6 ~ 40) 35
963 11:37:22.347092 iDelay=42, Bit 3, Center 14 (-2 ~ 31) 34
964 11:37:22.350130 iDelay=42, Bit 4, Center 22 (5 ~ 40) 36
965 11:37:22.353753 iDelay=42, Bit 5, Center 18 (1 ~ 35) 35
966 11:37:22.356679 iDelay=42, Bit 6, Center 19 (2 ~ 36) 35
967 11:37:22.363473 iDelay=42, Bit 7, Center 21 (5 ~ 37) 33
968 11:37:22.366703 iDelay=42, Bit 8, Center 14 (-3 ~ 32) 36
969 11:37:22.369722 iDelay=42, Bit 9, Center 17 (0 ~ 34) 35
970 11:37:22.373204 iDelay=42, Bit 10, Center 24 (7 ~ 41) 35
971 11:37:22.376546 iDelay=42, Bit 11, Center 15 (-2 ~ 33) 36
972 11:37:22.379628 iDelay=42, Bit 12, Center 17 (1 ~ 34) 34
973 11:37:22.383033 iDelay=42, Bit 13, Center 18 (0 ~ 36) 37
974 11:37:22.386225 iDelay=42, Bit 14, Center 18 (2 ~ 35) 34
975 11:37:22.389652 iDelay=42, Bit 15, Center 21 (5 ~ 38) 34
976 11:37:22.389752 ==
977 11:37:22.396302 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
978 11:37:22.399490 fsp= 1, odt_onoff= 1, Byte mode= 0
979 11:37:22.399570 ==
980 11:37:22.399635 DQS Delay:
981 11:37:22.402524 DQS0 = 0, DQS1 = 0
982 11:37:22.402623 DQM Delay:
983 11:37:22.405866 DQM0 = 20, DQM1 = 18
984 11:37:22.405968 DQ Delay:
985 11:37:22.409330 DQ0 =23, DQ1 =23, DQ2 =23, DQ3 =14
986 11:37:22.412411 DQ4 =22, DQ5 =18, DQ6 =19, DQ7 =21
987 11:37:22.415716 DQ8 =14, DQ9 =17, DQ10 =24, DQ11 =15
988 11:37:22.419043 DQ12 =17, DQ13 =18, DQ14 =18, DQ15 =21
989 11:37:22.419144
990 11:37:22.419235
991 11:37:22.422477 DramC Write-DBI off
992 11:37:22.422574 ==
993 11:37:22.425633 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
994 11:37:22.428809 fsp= 1, odt_onoff= 1, Byte mode= 0
995 11:37:22.428882 ==
996 11:37:22.435398 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
997 11:37:22.435516
998 11:37:22.435614 Begin, DQ Scan Range 923~1179
999 11:37:22.438645
1000 11:37:22.438753
1001 11:37:22.438854 TX Vref Scan disable
1002 11:37:22.441974 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1003 11:37:22.445403 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1004 11:37:22.448437 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1005 11:37:22.454979 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1006 11:37:22.458282 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1007 11:37:22.461688 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1008 11:37:22.464776 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1009 11:37:22.468159 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1010 11:37:22.471266 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1011 11:37:22.474701 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1012 11:37:22.477694 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1013 11:37:22.481098 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1014 11:37:22.484302 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1015 11:37:22.487537 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1016 11:37:22.490935 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1017 11:37:22.494269 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1018 11:37:22.500929 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1019 11:37:22.503918 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1020 11:37:22.507530 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1021 11:37:22.510424 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1022 11:37:22.513927 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1023 11:37:22.517359 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1024 11:37:22.520279 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1025 11:37:22.523566 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1026 11:37:22.527043 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1027 11:37:22.530275 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1028 11:37:22.533563 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1029 11:37:22.536659 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1030 11:37:22.540136 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1031 11:37:22.546754 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1032 11:37:22.549967 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1033 11:37:22.553219 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1034 11:37:22.556636 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1035 11:37:22.559693 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1036 11:37:22.563000 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1037 11:37:22.566647 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1038 11:37:22.569797 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1039 11:37:22.572894 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1040 11:37:22.576174 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1041 11:37:22.579416 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1042 11:37:22.582581 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1043 11:37:22.585908 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1044 11:37:22.589182 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1045 11:37:22.592712 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1046 11:37:22.599000 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1047 11:37:22.602231 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1048 11:37:22.605521 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1049 11:37:22.608913 970 |3 6 10|[0] xxxxxxxx ooxoxxxx [MSB]
1050 11:37:22.612182 971 |3 6 11|[0] xxxxxxxx ooxooxxx [MSB]
1051 11:37:22.615225 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1052 11:37:22.618590 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1053 11:37:22.622196 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1054 11:37:22.625328 975 |3 6 15|[0] xxxxxxxx ooxooooo [MSB]
1055 11:37:22.628419 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1056 11:37:22.631749 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1057 11:37:22.635070 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1058 11:37:22.642835 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1059 11:37:22.646242 991 |3 6 31|[0] oooooooo xooxxxoo [MSB]
1060 11:37:22.649246 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1061 11:37:22.652668 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1062 11:37:22.655982 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1063 11:37:22.659262 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1064 11:37:22.662378 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1065 11:37:22.665669 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1066 11:37:22.669014 998 |3 6 38|[0] xoxxxxxx xxxxxxxx [MSB]
1067 11:37:22.672322 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1068 11:37:22.675672 Byte0, DQ PI dly=986, DQM PI dly= 986
1069 11:37:22.682071 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1070 11:37:22.682177
1071 11:37:22.685450 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1072 11:37:22.685528
1073 11:37:22.688803 Byte1, DQ PI dly=981, DQM PI dly= 981
1074 11:37:22.691919 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1075 11:37:22.691996
1076 11:37:22.698380 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1077 11:37:22.698482
1078 11:37:22.698573 ==
1079 11:37:22.701770 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1080 11:37:22.704946 fsp= 1, odt_onoff= 1, Byte mode= 0
1081 11:37:22.705043 ==
1082 11:37:22.711529 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1083 11:37:22.711628
1084 11:37:22.714928 Begin, DQ Scan Range 957~1021
1085 11:37:22.715025 Write Rank0 MR14 =0x0
1086 11:37:22.723407
1087 11:37:22.723507 CH=0, VrefRange= 0, VrefLevel = 0
1088 11:37:22.729839 TX Bit0 (983~994) 12 988, Bit8 (971~985) 15 978,
1089 11:37:22.733113 TX Bit1 (980~994) 15 987, Bit9 (974~987) 14 980,
1090 11:37:22.739691 TX Bit2 (982~994) 13 988, Bit10 (978~991) 14 984,
1091 11:37:22.742777 TX Bit3 (976~990) 15 983, Bit11 (972~983) 12 977,
1092 11:37:22.746199 TX Bit4 (980~993) 14 986, Bit12 (975~985) 11 980,
1093 11:37:22.752780 TX Bit5 (978~991) 14 984, Bit13 (975~985) 11 980,
1094 11:37:22.756246 TX Bit6 (978~992) 15 985, Bit14 (975~989) 15 982,
1095 11:37:22.762508 TX Bit7 (979~993) 15 986, Bit15 (977~991) 15 984,
1096 11:37:22.762665
1097 11:37:22.762762 Write Rank0 MR14 =0x2
1098 11:37:22.771274
1099 11:37:22.771418 CH=0, VrefRange= 0, VrefLevel = 2
1100 11:37:22.777916 TX Bit0 (982~994) 13 988, Bit8 (970~986) 17 978,
1101 11:37:22.781047 TX Bit1 (980~994) 15 987, Bit9 (973~988) 16 980,
1102 11:37:22.787691 TX Bit2 (981~995) 15 988, Bit10 (977~991) 15 984,
1103 11:37:22.791103 TX Bit3 (976~991) 16 983, Bit11 (972~985) 14 978,
1104 11:37:22.794206 TX Bit4 (979~993) 15 986, Bit12 (975~986) 12 980,
1105 11:37:22.800780 TX Bit5 (977~991) 15 984, Bit13 (975~985) 11 980,
1106 11:37:22.804286 TX Bit6 (978~992) 15 985, Bit14 (975~990) 16 982,
1107 11:37:22.810518 TX Bit7 (979~993) 15 986, Bit15 (977~992) 16 984,
1108 11:37:22.810651
1109 11:37:22.810776 Write Rank0 MR14 =0x4
1110 11:37:22.819051
1111 11:37:22.819214 CH=0, VrefRange= 0, VrefLevel = 4
1112 11:37:22.825564 TX Bit0 (981~994) 14 987, Bit8 (970~988) 19 979,
1113 11:37:22.829026 TX Bit1 (979~995) 17 987, Bit9 (973~989) 17 981,
1114 11:37:22.835705 TX Bit2 (981~995) 15 988, Bit10 (977~992) 16 984,
1115 11:37:22.838729 TX Bit3 (976~991) 16 983, Bit11 (971~986) 16 978,
1116 11:37:22.842096 TX Bit4 (979~994) 16 986, Bit12 (975~988) 14 981,
1117 11:37:22.848561 TX Bit5 (977~992) 16 984, Bit13 (975~987) 13 981,
1118 11:37:22.852153 TX Bit6 (978~992) 15 985, Bit14 (975~990) 16 982,
1119 11:37:22.858311 TX Bit7 (979~994) 16 986, Bit15 (977~992) 16 984,
1120 11:37:22.858476
1121 11:37:22.858620 Write Rank0 MR14 =0x6
1122 11:37:22.867567
1123 11:37:22.867724 CH=0, VrefRange= 0, VrefLevel = 6
1124 11:37:22.874081 TX Bit0 (981~996) 16 988, Bit8 (970~988) 19 979,
1125 11:37:22.877149 TX Bit1 (979~996) 18 987, Bit9 (972~989) 18 980,
1126 11:37:22.883648 TX Bit2 (980~997) 18 988, Bit10 (977~994) 18 985,
1127 11:37:22.887920 TX Bit3 (975~991) 17 983, Bit11 (970~987) 18 978,
1128 11:37:22.890360 TX Bit4 (979~994) 16 986, Bit12 (974~988) 15 981,
1129 11:37:22.897026 TX Bit5 (977~992) 16 984, Bit13 (974~988) 15 981,
1130 11:37:22.900431 TX Bit6 (978~993) 16 985, Bit14 (975~991) 17 983,
1131 11:37:22.954057 TX Bit7 (979~995) 17 987, Bit15 (977~994) 18 985,
1132 11:37:22.954218
1133 11:37:22.954323 Write Rank0 MR14 =0x8
1134 11:37:22.954420
1135 11:37:22.954707 CH=0, VrefRange= 0, VrefLevel = 8
1136 11:37:22.954807 TX Bit0 (981~997) 17 989, Bit8 (969~989) 21 979,
1137 11:37:22.954901 TX Bit1 (978~996) 19 987, Bit9 (971~989) 19 980,
1138 11:37:22.955011 TX Bit2 (979~997) 19 988, Bit10 (977~995) 19 986,
1139 11:37:22.955102 TX Bit3 (975~992) 18 983, Bit11 (970~988) 19 979,
1140 11:37:22.955383 TX Bit4 (978~995) 18 986, Bit12 (974~989) 16 981,
1141 11:37:22.955487 TX Bit5 (977~993) 17 985, Bit13 (974~989) 16 981,
1142 11:37:22.955589 TX Bit6 (977~994) 18 985, Bit14 (975~991) 17 983,
1143 11:37:22.955845 TX Bit7 (979~996) 18 987, Bit15 (976~995) 20 985,
1144 11:37:22.955909
1145 11:37:22.989898 Write Rank0 MR14 =0xa
1146 11:37:22.990060
1147 11:37:22.990170 CH=0, VrefRange= 0, VrefLevel = 10
1148 11:37:22.990463 TX Bit0 (980~997) 18 988, Bit8 (969~989) 21 979,
1149 11:37:22.990547 TX Bit1 (978~997) 20 987, Bit9 (971~990) 20 980,
1150 11:37:22.990620 TX Bit2 (979~998) 20 988, Bit10 (977~995) 19 986,
1151 11:37:22.990687 TX Bit3 (975~992) 18 983, Bit11 (970~988) 19 979,
1152 11:37:22.991047 TX Bit4 (978~996) 19 987, Bit12 (973~989) 17 981,
1153 11:37:22.994049 TX Bit5 (977~993) 17 985, Bit13 (973~989) 17 981,
1154 11:37:22.997280 TX Bit6 (977~995) 19 986, Bit14 (974~991) 18 982,
1155 11:37:23.003428 TX Bit7 (978~996) 19 987, Bit15 (976~996) 21 986,
1156 11:37:23.003540
1157 11:37:23.003634 Write Rank0 MR14 =0xc
1158 11:37:23.012576
1159 11:37:23.015974 CH=0, VrefRange= 0, VrefLevel = 12
1160 11:37:23.019274 TX Bit0 (980~998) 19 989, Bit8 (969~989) 21 979,
1161 11:37:23.022405 TX Bit1 (978~998) 21 988, Bit9 (971~990) 20 980,
1162 11:37:23.028903 TX Bit2 (979~999) 21 989, Bit10 (976~996) 21 986,
1163 11:37:23.032276 TX Bit3 (975~992) 18 983, Bit11 (970~989) 20 979,
1164 11:37:23.035441 TX Bit4 (978~996) 19 987, Bit12 (972~989) 18 980,
1165 11:37:23.042306 TX Bit5 (976~994) 19 985, Bit13 (973~989) 17 981,
1166 11:37:23.045421 TX Bit6 (977~996) 20 986, Bit14 (974~992) 19 983,
1167 11:37:23.051856 TX Bit7 (978~998) 21 988, Bit15 (976~996) 21 986,
1168 11:37:23.051962
1169 11:37:23.052046 Write Rank0 MR14 =0xe
1170 11:37:23.061152
1171 11:37:23.064620 CH=0, VrefRange= 0, VrefLevel = 14
1172 11:37:23.068013 TX Bit0 (979~999) 21 989, Bit8 (969~989) 21 979,
1173 11:37:23.071048 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
1174 11:37:23.077778 TX Bit2 (979~999) 21 989, Bit10 (976~997) 22 986,
1175 11:37:23.080766 TX Bit3 (974~993) 20 983, Bit11 (969~989) 21 979,
1176 11:37:23.084163 TX Bit4 (978~997) 20 987, Bit12 (972~990) 19 981,
1177 11:37:23.090659 TX Bit5 (977~994) 18 985, Bit13 (972~990) 19 981,
1178 11:37:23.094005 TX Bit6 (977~996) 20 986, Bit14 (973~993) 21 983,
1179 11:37:23.100556 TX Bit7 (978~999) 22 988, Bit15 (975~996) 22 985,
1180 11:37:23.100663
1181 11:37:23.100751 Write Rank0 MR14 =0x10
1182 11:37:23.110417
1183 11:37:23.113257 CH=0, VrefRange= 0, VrefLevel = 16
1184 11:37:23.116656 TX Bit0 (979~999) 21 989, Bit8 (969~990) 22 979,
1185 11:37:23.119680 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1186 11:37:23.126298 TX Bit2 (979~999) 21 989, Bit10 (976~997) 22 986,
1187 11:37:23.129507 TX Bit3 (974~993) 20 983, Bit11 (969~989) 21 979,
1188 11:37:23.132947 TX Bit4 (978~998) 21 988, Bit12 (971~990) 20 980,
1189 11:37:23.139477 TX Bit5 (976~995) 20 985, Bit13 (971~990) 20 980,
1190 11:37:23.142518 TX Bit6 (976~997) 22 986, Bit14 (972~993) 22 982,
1191 11:37:23.149189 TX Bit7 (978~999) 22 988, Bit15 (975~997) 23 986,
1192 11:37:23.149299
1193 11:37:23.149395 Write Rank0 MR14 =0x12
1194 11:37:23.159104
1195 11:37:23.162230 CH=0, VrefRange= 0, VrefLevel = 18
1196 11:37:23.165488 TX Bit0 (979~999) 21 989, Bit8 (968~990) 23 979,
1197 11:37:23.168553 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1198 11:37:23.175264 TX Bit2 (978~1000) 23 989, Bit10 (975~997) 23 986,
1199 11:37:23.178368 TX Bit3 (974~993) 20 983, Bit11 (969~990) 22 979,
1200 11:37:23.181800 TX Bit4 (977~998) 22 987, Bit12 (971~991) 21 981,
1201 11:37:23.188279 TX Bit5 (976~996) 21 986, Bit13 (971~991) 21 981,
1202 11:37:23.191730 TX Bit6 (977~998) 22 987, Bit14 (972~993) 22 982,
1203 11:37:23.198213 TX Bit7 (978~999) 22 988, Bit15 (975~997) 23 986,
1204 11:37:23.198342
1205 11:37:23.198433 Write Rank0 MR14 =0x14
1206 11:37:23.207973
1207 11:37:23.211116 CH=0, VrefRange= 0, VrefLevel = 20
1208 11:37:23.214578 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1209 11:37:23.217706 TX Bit1 (977~999) 23 988, Bit9 (969~992) 24 980,
1210 11:37:23.224045 TX Bit2 (978~1000) 23 989, Bit10 (975~998) 24 986,
1211 11:37:23.227489 TX Bit3 (974~994) 21 984, Bit11 (969~990) 22 979,
1212 11:37:23.230794 TX Bit4 (977~999) 23 988, Bit12 (971~991) 21 981,
1213 11:37:23.237230 TX Bit5 (976~997) 22 986, Bit13 (971~991) 21 981,
1214 11:37:23.240492 TX Bit6 (976~999) 24 987, Bit14 (971~995) 25 983,
1215 11:37:23.247218 TX Bit7 (977~1000) 24 988, Bit15 (974~997) 24 985,
1216 11:37:23.247373
1217 11:37:23.247446 Write Rank0 MR14 =0x16
1218 11:37:23.256974
1219 11:37:23.260468 CH=0, VrefRange= 0, VrefLevel = 22
1220 11:37:23.263451 TX Bit0 (979~1000) 22 989, Bit8 (968~991) 24 979,
1221 11:37:23.266930 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1222 11:37:23.273598 TX Bit2 (978~1000) 23 989, Bit10 (975~998) 24 986,
1223 11:37:23.276755 TX Bit3 (973~994) 22 983, Bit11 (969~990) 22 979,
1224 11:37:23.283010 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
1225 11:37:23.286533 TX Bit5 (975~997) 23 986, Bit13 (971~991) 21 981,
1226 11:37:23.289632 TX Bit6 (976~999) 24 987, Bit14 (972~995) 24 983,
1227 11:37:23.296291 TX Bit7 (977~1000) 24 988, Bit15 (974~998) 25 986,
1228 11:37:23.296416
1229 11:37:23.296536 Write Rank0 MR14 =0x18
1230 11:37:23.306231
1231 11:37:23.309455 CH=0, VrefRange= 0, VrefLevel = 24
1232 11:37:23.312730 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1233 11:37:23.316153 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1234 11:37:23.322351 TX Bit2 (978~1000) 23 989, Bit10 (974~998) 25 986,
1235 11:37:23.325760 TX Bit3 (973~995) 23 984, Bit11 (969~991) 23 980,
1236 11:37:23.332537 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
1237 11:37:23.335545 TX Bit5 (975~998) 24 986, Bit13 (970~992) 23 981,
1238 11:37:23.338941 TX Bit6 (976~999) 24 987, Bit14 (971~996) 26 983,
1239 11:37:23.345430 TX Bit7 (977~1000) 24 988, Bit15 (974~998) 25 986,
1240 11:37:23.345558
1241 11:37:23.345681 Write Rank0 MR14 =0x1a
1242 11:37:23.355720
1243 11:37:23.358747 CH=0, VrefRange= 0, VrefLevel = 26
1244 11:37:23.362073 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1245 11:37:23.365266 TX Bit1 (977~1000) 24 988, Bit9 (969~993) 25 981,
1246 11:37:23.371915 TX Bit2 (978~1001) 24 989, Bit10 (974~999) 26 986,
1247 11:37:23.375316 TX Bit3 (973~995) 23 984, Bit11 (968~991) 24 979,
1248 11:37:23.381736 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1249 11:37:23.385060 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1250 11:37:23.388259 TX Bit6 (975~1000) 26 987, Bit14 (970~996) 27 983,
1251 11:37:23.394873 TX Bit7 (977~1000) 24 988, Bit15 (973~998) 26 985,
1252 11:37:23.394991
1253 11:37:23.395104 Write Rank0 MR14 =0x1c
1254 11:37:23.405467
1255 11:37:23.408598 CH=0, VrefRange= 0, VrefLevel = 28
1256 11:37:23.411976 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1257 11:37:23.415316 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1258 11:37:23.421566 TX Bit2 (977~1002) 26 989, Bit10 (974~998) 25 986,
1259 11:37:23.425185 TX Bit3 (972~995) 24 983, Bit11 (968~992) 25 980,
1260 11:37:23.431557 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1261 11:37:23.434796 TX Bit5 (975~999) 25 987, Bit13 (970~993) 24 981,
1262 11:37:23.437906 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1263 11:37:23.444668 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
1264 11:37:23.444779
1265 11:37:23.444876 Write Rank0 MR14 =0x1e
1266 11:37:23.454934
1267 11:37:23.458121 CH=0, VrefRange= 0, VrefLevel = 30
1268 11:37:23.461530 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1269 11:37:23.464955 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1270 11:37:23.471114 TX Bit2 (977~1002) 26 989, Bit10 (974~998) 25 986,
1271 11:37:23.474621 TX Bit3 (972~995) 24 983, Bit11 (968~992) 25 980,
1272 11:37:23.481186 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1273 11:37:23.484293 TX Bit5 (975~999) 25 987, Bit13 (970~993) 24 981,
1274 11:37:23.487644 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1275 11:37:23.493994 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
1276 11:37:23.494126
1277 11:37:23.494227 Write Rank0 MR14 =0x20
1278 11:37:23.504577
1279 11:37:23.507673 CH=0, VrefRange= 0, VrefLevel = 32
1280 11:37:23.511024 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1281 11:37:23.514412 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1282 11:37:23.520726 TX Bit2 (977~1002) 26 989, Bit10 (974~998) 25 986,
1283 11:37:23.524285 TX Bit3 (972~995) 24 983, Bit11 (968~992) 25 980,
1284 11:37:23.530517 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1285 11:37:23.533905 TX Bit5 (975~999) 25 987, Bit13 (970~993) 24 981,
1286 11:37:23.537162 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1287 11:37:23.543568 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
1288 11:37:23.543650
1289 11:37:23.543727 Write Rank0 MR14 =0x22
1290 11:37:23.554369
1291 11:37:23.557779 CH=0, VrefRange= 0, VrefLevel = 34
1292 11:37:23.560918 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1293 11:37:23.564393 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1294 11:37:23.570653 TX Bit2 (977~1002) 26 989, Bit10 (974~998) 25 986,
1295 11:37:23.574133 TX Bit3 (972~995) 24 983, Bit11 (968~992) 25 980,
1296 11:37:23.580364 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1297 11:37:23.583893 TX Bit5 (975~999) 25 987, Bit13 (970~993) 24 981,
1298 11:37:23.586939 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1299 11:37:23.593518 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
1300 11:37:23.593624
1301 11:37:23.593716 Write Rank0 MR14 =0x24
1302 11:37:23.604056
1303 11:37:23.607359 CH=0, VrefRange= 0, VrefLevel = 36
1304 11:37:23.610464 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1305 11:37:23.614019 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1306 11:37:23.620353 TX Bit2 (977~1002) 26 989, Bit10 (974~998) 25 986,
1307 11:37:23.623435 TX Bit3 (972~995) 24 983, Bit11 (968~992) 25 980,
1308 11:37:23.630073 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1309 11:37:23.633506 TX Bit5 (975~999) 25 987, Bit13 (970~993) 24 981,
1310 11:37:23.636896 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1311 11:37:23.643325 TX Bit7 (977~1001) 25 989, Bit15 (974~998) 25 986,
1312 11:37:23.643434
1313 11:37:23.643540
1314 11:37:23.646379 TX Vref found, early break! 374< 377
1315 11:37:23.649951 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1316 11:37:23.653164 u1DelayCellOfst[0]=9 cells (7 PI)
1317 11:37:23.656391 u1DelayCellOfst[1]=7 cells (6 PI)
1318 11:37:23.659704 u1DelayCellOfst[2]=7 cells (6 PI)
1319 11:37:23.662714 u1DelayCellOfst[3]=0 cells (0 PI)
1320 11:37:23.666192 u1DelayCellOfst[4]=6 cells (5 PI)
1321 11:37:23.669479 u1DelayCellOfst[5]=5 cells (4 PI)
1322 11:37:23.672725 u1DelayCellOfst[6]=5 cells (4 PI)
1323 11:37:23.676025 u1DelayCellOfst[7]=7 cells (6 PI)
1324 11:37:23.679106 Byte0, DQ PI dly=983, DQM PI dly= 986
1325 11:37:23.682588 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1326 11:37:23.682699
1327 11:37:23.685969 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1328 11:37:23.686081
1329 11:37:23.689113 u1DelayCellOfst[8]=0 cells (0 PI)
1330 11:37:23.692295 u1DelayCellOfst[9]=2 cells (2 PI)
1331 11:37:23.695863 u1DelayCellOfst[10]=9 cells (7 PI)
1332 11:37:23.698985 u1DelayCellOfst[11]=1 cells (1 PI)
1333 11:37:23.702020 u1DelayCellOfst[12]=2 cells (2 PI)
1334 11:37:23.705473 u1DelayCellOfst[13]=2 cells (2 PI)
1335 11:37:23.708798 u1DelayCellOfst[14]=5 cells (4 PI)
1336 11:37:23.712061 u1DelayCellOfst[15]=9 cells (7 PI)
1337 11:37:23.715353 Byte1, DQ PI dly=979, DQM PI dly= 982
1338 11:37:23.718470 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1339 11:37:23.718573
1340 11:37:23.725034 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1341 11:37:23.725146
1342 11:37:23.725241 Write Rank0 MR14 =0x1c
1343 11:37:23.725339
1344 11:37:23.728620 Final TX Range 0 Vref 28
1345 11:37:23.728739
1346 11:37:23.734976 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1347 11:37:23.735087
1348 11:37:23.741607 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1349 11:37:23.747928 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1350 11:37:23.754773 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1351 11:37:23.757820 Write Rank0 MR3 =0xb0
1352 11:37:23.761210 DramC Write-DBI on
1353 11:37:23.761317 ==
1354 11:37:23.764252 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1355 11:37:23.767801 fsp= 1, odt_onoff= 1, Byte mode= 0
1356 11:37:23.767910 ==
1357 11:37:23.774059 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1358 11:37:23.774182
1359 11:37:23.774279 Begin, DQ Scan Range 702~766
1360 11:37:23.774376
1361 11:37:23.774469
1362 11:37:23.777614 TX Vref Scan disable
1363 11:37:23.780713 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1364 11:37:23.783899 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1365 11:37:23.787260 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1366 11:37:23.790331 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1367 11:37:23.793923 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1368 11:37:23.797038 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1369 11:37:23.800277 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1370 11:37:23.806860 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1371 11:37:23.810256 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1372 11:37:23.813511 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1373 11:37:23.816772 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1374 11:37:23.819908 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1375 11:37:23.823484 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1376 11:37:23.826394 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1377 11:37:23.829817 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1378 11:37:23.832986 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1379 11:37:23.836551 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1380 11:37:23.839875 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1381 11:37:23.848389 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1382 11:37:23.851747 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1383 11:37:23.854802 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1384 11:37:23.858337 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1385 11:37:23.861277 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1386 11:37:23.864682 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1387 11:37:23.868054 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1388 11:37:23.871212 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1389 11:37:23.874682 Byte0, DQ PI dly=732, DQM PI dly= 732
1390 11:37:23.877729 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1391 11:37:23.881058
1392 11:37:23.884462 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1393 11:37:23.884570
1394 11:37:23.887764 Byte1, DQ PI dly=725, DQM PI dly= 725
1395 11:37:23.891095 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1396 11:37:23.891195
1397 11:37:23.897283 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1398 11:37:23.897400
1399 11:37:23.904341 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1400 11:37:23.910416 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1401 11:37:23.917104 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1402 11:37:23.920301 Write Rank0 MR3 =0x30
1403 11:37:23.920405 DramC Write-DBI off
1404 11:37:23.920496
1405 11:37:23.920585 [DATLAT]
1406 11:37:23.923749 Freq=1600, CH0 RK0, use_rxtx_scan=0
1407 11:37:23.923828
1408 11:37:23.926860 DATLAT Default: 0xf
1409 11:37:23.926954 7, 0xFFFF, sum=0
1410 11:37:23.930292 8, 0xFFFF, sum=0
1411 11:37:23.930395 9, 0xFFFF, sum=0
1412 11:37:23.933405 10, 0xFFFF, sum=0
1413 11:37:23.933511 11, 0xFFFF, sum=0
1414 11:37:23.936730 12, 0xFFFF, sum=0
1415 11:37:23.936836 13, 0xFFFF, sum=0
1416 11:37:23.940011 14, 0x0, sum=1
1417 11:37:23.940125 15, 0x0, sum=2
1418 11:37:23.943281 16, 0x0, sum=3
1419 11:37:23.943392 17, 0x0, sum=4
1420 11:37:23.946417 pattern=2 first_step=14 total pass=5 best_step=16
1421 11:37:23.949765 ==
1422 11:37:23.952953 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1423 11:37:23.956530 fsp= 1, odt_onoff= 1, Byte mode= 0
1424 11:37:23.956633 ==
1425 11:37:23.959919 Start DQ dly to find pass range UseTestEngine =1
1426 11:37:23.962841 x-axis: bit #, y-axis: DQ dly (-127~63)
1427 11:37:23.966138 RX Vref Scan = 1
1428 11:37:24.073090
1429 11:37:24.073259 RX Vref found, early break!
1430 11:37:24.073358
1431 11:37:24.079640 Final RX Vref 11, apply to both rank0 and 1
1432 11:37:24.079755 ==
1433 11:37:24.083077 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1434 11:37:24.086198 fsp= 1, odt_onoff= 1, Byte mode= 0
1435 11:37:24.086298 ==
1436 11:37:24.089406 DQS Delay:
1437 11:37:24.089509 DQS0 = 0, DQS1 = 0
1438 11:37:24.089604 DQM Delay:
1439 11:37:24.092945 DQM0 = 19, DQM1 = 17
1440 11:37:24.093053 DQ Delay:
1441 11:37:24.096128 DQ0 =22, DQ1 =22, DQ2 =24, DQ3 =14
1442 11:37:24.099189 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =20
1443 11:37:24.102759 DQ8 =13, DQ9 =17, DQ10 =23, DQ11 =15
1444 11:37:24.105824 DQ12 =17, DQ13 =16, DQ14 =18, DQ15 =20
1445 11:37:24.105965
1446 11:37:24.106081
1447 11:37:24.106201
1448 11:37:24.109303 [DramC_TX_OE_Calibration] TA2
1449 11:37:24.112471 Original DQ_B0 (3 6) =30, OEN = 27
1450 11:37:24.115930 Original DQ_B1 (3 6) =30, OEN = 27
1451 11:37:24.119073 23, 0x0, End_B0=23 End_B1=23
1452 11:37:24.122570 24, 0x0, End_B0=24 End_B1=24
1453 11:37:24.122724 25, 0x0, End_B0=25 End_B1=25
1454 11:37:24.125678 26, 0x0, End_B0=26 End_B1=26
1455 11:37:24.128831 27, 0x0, End_B0=27 End_B1=27
1456 11:37:24.132316 28, 0x0, End_B0=28 End_B1=28
1457 11:37:24.135529 29, 0x0, End_B0=29 End_B1=29
1458 11:37:24.135641 30, 0x0, End_B0=30 End_B1=30
1459 11:37:24.138731 31, 0xFFFF, End_B0=30 End_B1=30
1460 11:37:24.145249 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1461 11:37:24.151690 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1462 11:37:24.151803
1463 11:37:24.151870
1464 11:37:24.151931 Write Rank0 MR23 =0x3f
1465 11:37:24.154995 [DQSOSC]
1466 11:37:24.161408 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c1, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
1467 11:37:24.168270 CH0_RK0: MR19=0x202, MR18=0xC1C1, DQSOSC=446, MR23=63, INC=12, DEC=18
1468 11:37:24.171437 Write Rank0 MR23 =0x3f
1469 11:37:24.171551 [DQSOSC]
1470 11:37:24.177793 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
1471 11:37:24.181077 CH0 RK0: MR19=202, MR18=C0C0
1472 11:37:24.184294 [RankSwap] Rank num 2, (Multi 1), Rank 1
1473 11:37:24.187817 Write Rank0 MR2 =0xad
1474 11:37:24.187932 [Write Leveling]
1475 11:37:24.190849 delay byte0 byte1 byte2 byte3
1476 11:37:24.190966
1477 11:37:24.194180 10 0 0
1478 11:37:24.194293 11 0 0
1479 11:37:24.197738 12 0 0
1480 11:37:24.197833 13 0 0
1481 11:37:24.197902 14 0 0
1482 11:37:24.200919 15 0 0
1483 11:37:24.201009 16 0 0
1484 11:37:24.204056 17 0 0
1485 11:37:24.204160 18 0 0
1486 11:37:24.204262 19 0 0
1487 11:37:24.207261 20 0 0
1488 11:37:24.207367 21 0 0
1489 11:37:24.210751 22 0 0
1490 11:37:24.210857 23 0 ff
1491 11:37:24.213831 24 0 ff
1492 11:37:24.213934 25 0 ff
1493 11:37:24.217167 26 0 ff
1494 11:37:24.217286 27 ff ff
1495 11:37:24.217385 28 ff ff
1496 11:37:24.220645 29 ff ff
1497 11:37:24.220761 30 ff ff
1498 11:37:24.223767 31 ff ff
1499 11:37:24.223853 32 ff ff
1500 11:37:24.226984 33 ff ff
1501 11:37:24.230230 pass bytecount = 0xff (0xff: all bytes pass)
1502 11:37:24.230331
1503 11:37:24.233464 DQS0 dly: 27
1504 11:37:24.233564 DQS1 dly: 23
1505 11:37:24.233659 Write Rank0 MR2 =0x2d
1506 11:37:24.240270 [RankSwap] Rank num 2, (Multi 1), Rank 0
1507 11:37:24.240378 Write Rank1 MR1 =0xd6
1508 11:37:24.240473 [Gating]
1509 11:37:24.243263 ==
1510 11:37:24.246505 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1511 11:37:24.249870 fsp= 1, odt_onoff= 1, Byte mode= 0
1512 11:37:24.249972 ==
1513 11:37:24.253419 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1514 11:37:24.259803 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1515 11:37:24.263044 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1516 11:37:24.266203 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1517 11:37:24.272920 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1518 11:37:24.276246 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1519 11:37:24.279339 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1520 11:37:24.285919 [Byte 0] Lead/lag falling Transition (3, 1, 24)
1521 11:37:24.289352 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1522 11:37:24.292405 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1523 11:37:24.299071 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1524 11:37:24.302249 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1525 11:37:24.305417 3 2 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1526 11:37:24.311941 3 2 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1527 11:37:24.315446 [Byte 0] Lead/lag Transition tap number (7)
1528 11:37:24.318523 3 2 20 |201 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
1529 11:37:24.325080 3 2 24 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1530 11:37:24.328420 3 2 28 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1531 11:37:24.331850 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1532 11:37:24.334976 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1533 11:37:24.341434 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1534 11:37:24.344758 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1535 11:37:24.348310 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1536 11:37:24.354666 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1537 11:37:24.357868 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1538 11:37:24.361312 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1539 11:37:24.367844 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1540 11:37:24.370965 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1541 11:37:24.374265 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1542 11:37:24.381058 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1543 11:37:24.384223 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1544 11:37:24.387217 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1545 11:37:24.393893 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1546 11:37:24.397406 3 4 24 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1547 11:37:24.400425 3 4 28 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1548 11:37:24.407257 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1549 11:37:24.410261 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1550 11:37:24.413503 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1551 11:37:24.420049 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1552 11:37:24.423596 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1553 11:37:24.426672 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1554 11:37:24.433367 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1555 11:37:24.436606 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1556 11:37:24.439877 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 11:37:24.446305 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 11:37:24.449465 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1559 11:37:24.453213 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1560 11:37:24.459699 [Byte 0] Lead/lag falling Transition (3, 6, 12)
1561 11:37:24.462791 [Byte 1] Lead/lag falling Transition (3, 6, 12)
1562 11:37:24.466019 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1563 11:37:24.469325 [Byte 0] Lead/lag Transition tap number (2)
1564 11:37:24.475977 [Byte 1] Lead/lag Transition tap number (2)
1565 11:37:24.479118 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1566 11:37:24.482268 3 6 24 |4646 605 |(0 0)(11 11) |(0 0)(0 0)| 0
1567 11:37:24.485660 [Byte 0]First pass (3, 6, 24)
1568 11:37:24.489045 3 6 28 |4646 2a2a |(0 0)(1 1) |(0 0)(0 0)| 0
1569 11:37:24.492348 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1570 11:37:24.495522 [Byte 1]First pass (3, 7, 0)
1571 11:37:24.498813 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1572 11:37:24.505308 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1573 11:37:24.508666 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1574 11:37:24.511762 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1575 11:37:24.515252 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1576 11:37:24.521540 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1577 11:37:24.525059 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1578 11:37:24.528270 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1579 11:37:24.531369 All bytes gating window > 1UI, Early break!
1580 11:37:24.531463
1581 11:37:24.534842 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
1582 11:37:24.534928
1583 11:37:24.541164 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 16)
1584 11:37:24.541250
1585 11:37:24.541357
1586 11:37:24.541424
1587 11:37:24.544743 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1588 11:37:24.544827
1589 11:37:24.548061 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1590 11:37:24.548144
1591 11:37:24.548208
1592 11:37:24.551022 Write Rank1 MR1 =0x56
1593 11:37:24.551104
1594 11:37:24.554569 best RODT dly(2T, 0.5T) = (2, 3)
1595 11:37:24.554651
1596 11:37:24.557880 best RODT dly(2T, 0.5T) = (2, 3)
1597 11:37:24.557964 ==
1598 11:37:24.560951 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1599 11:37:24.564422 fsp= 1, odt_onoff= 1, Byte mode= 0
1600 11:37:24.564506 ==
1601 11:37:24.570695 Start DQ dly to find pass range UseTestEngine =0
1602 11:37:24.574090 x-axis: bit #, y-axis: DQ dly (-127~63)
1603 11:37:24.574174 RX Vref Scan = 0
1604 11:37:24.577560 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1605 11:37:24.580548 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1606 11:37:24.584102 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1607 11:37:24.587373 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1608 11:37:24.590454 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1609 11:37:24.593663 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1610 11:37:24.597006 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1611 11:37:24.597092 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1612 11:37:24.600359 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1613 11:37:24.603407 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1614 11:37:24.606893 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1615 11:37:24.610200 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1616 11:37:24.613413 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1617 11:37:24.616718 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1618 11:37:24.619944 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1619 11:37:24.623397 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1620 11:37:24.623508 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1621 11:37:24.626498 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1622 11:37:24.629677 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1623 11:37:24.632888 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1624 11:37:24.636347 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1625 11:37:24.639409 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1626 11:37:24.643013 -4, [0] xxxxxxxx oxxxxxxx [MSB]
1627 11:37:24.646128 -3, [0] xxxoxxxx oxxoxxxx [MSB]
1628 11:37:24.646214 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1629 11:37:24.649349 -1, [0] xxxoxxxx ooxoooxx [MSB]
1630 11:37:24.652762 0, [0] xxxoxoxx ooxoooxx [MSB]
1631 11:37:24.655927 1, [0] xxxoxoox ooxoooxx [MSB]
1632 11:37:24.659168 2, [0] xxxoxoox ooxoooox [MSB]
1633 11:37:24.662399 3, [0] xxxooooo ooxoooox [MSB]
1634 11:37:24.662485 4, [0] xxxooooo ooxoooox [MSB]
1635 11:37:24.665849 5, [0] ooxooooo ooxooooo [MSB]
1636 11:37:24.669038 6, [0] oooooooo ooxooooo [MSB]
1637 11:37:24.672356 32, [0] oooxoooo oooooooo [MSB]
1638 11:37:24.675773 33, [0] oooxoooo xooooooo [MSB]
1639 11:37:24.678798 34, [0] oooxoooo xooooooo [MSB]
1640 11:37:24.682400 35, [0] oooxoooo xxoxoooo [MSB]
1641 11:37:24.685451 36, [0] oooxoxxo xxoxxxxo [MSB]
1642 11:37:24.685537 37, [0] oooxoxxx xxoxxxxo [MSB]
1643 11:37:24.688712 38, [0] oooxoxxx xxoxxxxo [MSB]
1644 11:37:24.692259 39, [0] ooxxxxxx xxoxxxxx [MSB]
1645 11:37:24.695207 40, [0] xoxxxxxx xxoxxxxx [MSB]
1646 11:37:24.698541 41, [0] xxxxxxxx xxoxxxxx [MSB]
1647 11:37:24.701886 42, [0] xxxxxxxx xxoxxxxx [MSB]
1648 11:37:24.705161 43, [0] xxxxxxxx xxxxxxxx [MSB]
1649 11:37:24.708338 iDelay=43, Bit 0, Center 22 (5 ~ 39) 35
1650 11:37:24.711686 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36
1651 11:37:24.714809 iDelay=43, Bit 2, Center 22 (6 ~ 38) 33
1652 11:37:24.718182 iDelay=43, Bit 3, Center 14 (-3 ~ 31) 35
1653 11:37:24.721543 iDelay=43, Bit 4, Center 20 (3 ~ 38) 36
1654 11:37:24.724527 iDelay=43, Bit 5, Center 17 (0 ~ 35) 36
1655 11:37:24.728018 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
1656 11:37:24.731327 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34
1657 11:37:24.734583 iDelay=43, Bit 8, Center 14 (-4 ~ 32) 37
1658 11:37:24.737750 iDelay=43, Bit 9, Center 16 (-1 ~ 34) 36
1659 11:37:24.744387 iDelay=43, Bit 10, Center 24 (7 ~ 42) 36
1660 11:37:24.747869 iDelay=43, Bit 11, Center 15 (-3 ~ 34) 38
1661 11:37:24.751016 iDelay=43, Bit 12, Center 17 (-1 ~ 35) 37
1662 11:37:24.754115 iDelay=43, Bit 13, Center 17 (-1 ~ 35) 37
1663 11:37:24.757597 iDelay=43, Bit 14, Center 18 (2 ~ 35) 34
1664 11:37:24.760965 iDelay=43, Bit 15, Center 21 (5 ~ 38) 34
1665 11:37:24.761051 ==
1666 11:37:24.767576 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1667 11:37:24.770605 fsp= 1, odt_onoff= 1, Byte mode= 0
1668 11:37:24.770689 ==
1669 11:37:24.770756 DQS Delay:
1670 11:37:24.773957 DQS0 = 0, DQS1 = 0
1671 11:37:24.774042 DQM Delay:
1672 11:37:24.777095 DQM0 = 19, DQM1 = 17
1673 11:37:24.777180 DQ Delay:
1674 11:37:24.780352 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1675 11:37:24.783826 DQ4 =20, DQ5 =17, DQ6 =18, DQ7 =19
1676 11:37:24.786863 DQ8 =14, DQ9 =16, DQ10 =24, DQ11 =15
1677 11:37:24.790123 DQ12 =17, DQ13 =17, DQ14 =18, DQ15 =21
1678 11:37:24.790207
1679 11:37:24.790273
1680 11:37:24.790333 DramC Write-DBI off
1681 11:37:24.793462 ==
1682 11:37:24.796736 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1683 11:37:24.800092 fsp= 1, odt_onoff= 1, Byte mode= 0
1684 11:37:24.800178 ==
1685 11:37:24.803479 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1686 11:37:24.803565
1687 11:37:24.806783 Begin, DQ Scan Range 919~1175
1688 11:37:24.806867
1689 11:37:24.806933
1690 11:37:24.809799 TX Vref Scan disable
1691 11:37:24.813245 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1692 11:37:24.816541 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1693 11:37:24.819846 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1694 11:37:24.823009 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1695 11:37:24.826305 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1696 11:37:24.829683 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1697 11:37:24.836032 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1698 11:37:24.839220 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1699 11:37:24.842640 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1700 11:37:24.845761 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1701 11:37:24.848985 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1702 11:37:24.852489 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1703 11:37:24.855535 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1704 11:37:24.859047 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1705 11:37:24.862162 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1706 11:37:24.865594 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1707 11:37:24.868909 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1708 11:37:24.872016 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1709 11:37:24.878536 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1710 11:37:24.881968 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1711 11:37:24.885237 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1712 11:37:24.888341 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1713 11:37:24.891695 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1714 11:37:24.894991 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1715 11:37:24.898283 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1716 11:37:24.901460 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1717 11:37:24.904819 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1718 11:37:24.908197 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1719 11:37:24.911120 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1720 11:37:24.914785 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1721 11:37:24.917848 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1722 11:37:24.924632 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1723 11:37:24.927708 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1724 11:37:24.930950 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1725 11:37:24.934401 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1726 11:37:24.937370 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1727 11:37:24.940937 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1728 11:37:24.944032 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1729 11:37:24.947364 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1730 11:37:24.950548 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1731 11:37:24.953879 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1732 11:37:24.957127 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1733 11:37:24.960596 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1734 11:37:24.963718 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1735 11:37:24.967107 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1736 11:37:24.973429 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1737 11:37:24.976968 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1738 11:37:24.980015 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1739 11:37:24.983538 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1740 11:37:24.986594 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1741 11:37:24.989863 969 |3 6 9|[0] xxxxxxxx oxxoxxxx [MSB]
1742 11:37:24.993111 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1743 11:37:24.996578 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1744 11:37:24.999762 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1745 11:37:25.002982 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1746 11:37:25.006468 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1747 11:37:25.009420 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1748 11:37:25.012842 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1749 11:37:25.016128 977 |3 6 17|[0] xxxoxoox oooooooo [MSB]
1750 11:37:25.023903 987 |3 6 27|[0] oooooooo oooxoooo [MSB]
1751 11:37:25.027245 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1752 11:37:25.030444 989 |3 6 29|[0] oooooooo xxoxoooo [MSB]
1753 11:37:25.033495 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1754 11:37:25.036844 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1755 11:37:25.040153 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1756 11:37:25.043296 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1757 11:37:25.046795 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1758 11:37:25.050210 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1759 11:37:25.053368 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1760 11:37:25.056533 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1761 11:37:25.059899 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1762 11:37:25.063078 Byte0, DQ PI dly=985, DQM PI dly= 985
1763 11:37:25.069949 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1764 11:37:25.070053
1765 11:37:25.072974 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1766 11:37:25.073080
1767 11:37:25.076406 Byte1, DQ PI dly=979, DQM PI dly= 979
1768 11:37:25.082909 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1769 11:37:25.083018
1770 11:37:25.086017 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1771 11:37:25.086122
1772 11:37:25.086215 ==
1773 11:37:25.092460 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1774 11:37:25.095859 fsp= 1, odt_onoff= 1, Byte mode= 0
1775 11:37:25.095941 ==
1776 11:37:25.099254 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1777 11:37:25.099355
1778 11:37:25.102166 Begin, DQ Scan Range 955~1019
1779 11:37:25.102269 Write Rank1 MR14 =0x0
1780 11:37:25.111362
1781 11:37:25.111473 CH=0, VrefRange= 0, VrefLevel = 0
1782 11:37:25.117879 TX Bit0 (981~992) 12 986, Bit8 (970~983) 14 976,
1783 11:37:25.120989 TX Bit1 (979~992) 14 985, Bit9 (974~983) 10 978,
1784 11:37:25.127791 TX Bit2 (981~992) 12 986, Bit10 (977~990) 14 983,
1785 11:37:25.131190 TX Bit3 (975~989) 15 982, Bit11 (972~981) 10 976,
1786 11:37:25.134391 TX Bit4 (979~992) 14 985, Bit12 (974~983) 10 978,
1787 11:37:25.140627 TX Bit5 (978~988) 11 983, Bit13 (973~984) 12 978,
1788 11:37:25.143953 TX Bit6 (978~991) 14 984, Bit14 (973~989) 17 981,
1789 11:37:25.150559 TX Bit7 (979~992) 14 985, Bit15 (976~990) 15 983,
1790 11:37:25.150678
1791 11:37:25.150782 Write Rank1 MR14 =0x2
1792 11:37:25.159520
1793 11:37:25.159613 CH=0, VrefRange= 0, VrefLevel = 2
1794 11:37:25.165988 TX Bit0 (980~993) 14 986, Bit8 (969~983) 15 976,
1795 11:37:25.169012 TX Bit1 (979~993) 15 986, Bit9 (973~983) 11 978,
1796 11:37:25.175903 TX Bit2 (981~992) 12 986, Bit10 (976~990) 15 983,
1797 11:37:25.179135 TX Bit3 (975~990) 16 982, Bit11 (972~982) 11 977,
1798 11:37:25.182243 TX Bit4 (979~992) 14 985, Bit12 (974~983) 10 978,
1799 11:37:25.188796 TX Bit5 (978~989) 12 983, Bit13 (973~985) 13 979,
1800 11:37:25.192216 TX Bit6 (978~991) 14 984, Bit14 (973~990) 18 981,
1801 11:37:25.198501 TX Bit7 (979~993) 15 986, Bit15 (976~990) 15 983,
1802 11:37:25.198597
1803 11:37:25.198670 Write Rank1 MR14 =0x4
1804 11:37:25.207427
1805 11:37:25.207565 CH=0, VrefRange= 0, VrefLevel = 4
1806 11:37:25.213797 TX Bit0 (980~993) 14 986, Bit8 (969~984) 16 976,
1807 11:37:25.217402 TX Bit1 (979~994) 16 986, Bit9 (972~984) 13 978,
1808 11:37:25.223722 TX Bit2 (980~993) 14 986, Bit10 (976~991) 16 983,
1809 11:37:25.226913 TX Bit3 (974~990) 17 982, Bit11 (971~983) 13 977,
1810 11:37:25.230439 TX Bit4 (978~993) 16 985, Bit12 (974~984) 11 979,
1811 11:37:25.236941 TX Bit5 (977~990) 14 983, Bit13 (972~985) 14 978,
1812 11:37:25.240267 TX Bit6 (977~992) 16 984, Bit14 (972~990) 19 981,
1813 11:37:25.246615 TX Bit7 (979~994) 16 986, Bit15 (976~990) 15 983,
1814 11:37:25.246722
1815 11:37:25.246819 Write Rank1 MR14 =0x6
1816 11:37:25.255709
1817 11:37:25.255790 CH=0, VrefRange= 0, VrefLevel = 6
1818 11:37:25.262264 TX Bit0 (979~994) 16 986, Bit8 (969~984) 16 976,
1819 11:37:25.265685 TX Bit1 (978~995) 18 986, Bit9 (972~985) 14 978,
1820 11:37:25.272352 TX Bit2 (979~994) 16 986, Bit10 (976~991) 16 983,
1821 11:37:25.275522 TX Bit3 (974~991) 18 982, Bit11 (970~983) 14 976,
1822 11:37:25.278598 TX Bit4 (978~994) 17 986, Bit12 (972~985) 14 978,
1823 11:37:25.285149 TX Bit5 (977~990) 14 983, Bit13 (972~986) 15 979,
1824 11:37:25.288568 TX Bit6 (977~992) 16 984, Bit14 (972~990) 19 981,
1825 11:37:25.295119 TX Bit7 (978~994) 17 986, Bit15 (976~991) 16 983,
1826 11:37:25.295227
1827 11:37:25.295320 Write Rank1 MR14 =0x8
1828 11:37:25.303943
1829 11:37:25.304031 CH=0, VrefRange= 0, VrefLevel = 8
1830 11:37:25.310612 TX Bit0 (979~995) 17 987, Bit8 (968~985) 18 976,
1831 11:37:25.313637 TX Bit1 (978~995) 18 986, Bit9 (971~985) 15 978,
1832 11:37:25.320496 TX Bit2 (979~994) 16 986, Bit10 (976~992) 17 984,
1833 11:37:25.323537 TX Bit3 (974~991) 18 982, Bit11 (970~984) 15 977,
1834 11:37:25.326809 TX Bit4 (978~994) 17 986, Bit12 (972~985) 14 978,
1835 11:37:25.333277 TX Bit5 (977~991) 15 984, Bit13 (971~987) 17 979,
1836 11:37:25.336734 TX Bit6 (977~993) 17 985, Bit14 (972~990) 19 981,
1837 11:37:25.343303 TX Bit7 (979~995) 17 987, Bit15 (975~991) 17 983,
1838 11:37:25.343411
1839 11:37:25.343527 Write Rank1 MR14 =0xa
1840 11:37:25.352436
1841 11:37:25.355663 CH=0, VrefRange= 0, VrefLevel = 10
1842 11:37:25.359056 TX Bit0 (979~996) 18 987, Bit8 (969~985) 17 977,
1843 11:37:25.362160 TX Bit1 (978~996) 19 987, Bit9 (971~985) 15 978,
1844 11:37:25.368906 TX Bit2 (979~995) 17 987, Bit10 (975~992) 18 983,
1845 11:37:25.371993 TX Bit3 (973~991) 19 982, Bit11 (970~984) 15 977,
1846 11:37:25.375439 TX Bit4 (978~995) 18 986, Bit12 (972~985) 14 978,
1847 11:37:25.382051 TX Bit5 (977~992) 16 984, Bit13 (972~988) 17 980,
1848 11:37:25.385502 TX Bit6 (977~993) 17 985, Bit14 (971~991) 21 981,
1849 11:37:25.391856 TX Bit7 (978~996) 19 987, Bit15 (975~992) 18 983,
1850 11:37:25.391940
1851 11:37:25.392006 Write Rank1 MR14 =0xc
1852 11:37:25.401272
1853 11:37:25.404318 CH=0, VrefRange= 0, VrefLevel = 12
1854 11:37:25.407758 TX Bit0 (978~997) 20 987, Bit8 (968~986) 19 977,
1855 11:37:25.410942 TX Bit1 (978~997) 20 987, Bit9 (971~986) 16 978,
1856 11:37:25.417699 TX Bit2 (979~996) 18 987, Bit10 (975~992) 18 983,
1857 11:37:25.420767 TX Bit3 (973~991) 19 982, Bit11 (969~985) 17 977,
1858 11:37:25.424151 TX Bit4 (978~995) 18 986, Bit12 (971~986) 16 978,
1859 11:37:25.430658 TX Bit5 (976~992) 17 984, Bit13 (970~989) 20 979,
1860 11:37:25.433831 TX Bit6 (977~994) 18 985, Bit14 (970~991) 22 980,
1861 11:37:25.440376 TX Bit7 (978~997) 20 987, Bit15 (975~992) 18 983,
1862 11:37:25.440490
1863 11:37:25.440587 Write Rank1 MR14 =0xe
1864 11:37:25.450168
1865 11:37:25.453353 CH=0, VrefRange= 0, VrefLevel = 14
1866 11:37:25.456516 TX Bit0 (978~998) 21 988, Bit8 (968~986) 19 977,
1867 11:37:25.459675 TX Bit1 (978~998) 21 988, Bit9 (970~987) 18 978,
1868 11:37:25.466799 TX Bit2 (979~997) 19 988, Bit10 (975~993) 19 984,
1869 11:37:25.469641 TX Bit3 (972~992) 21 982, Bit11 (969~985) 17 977,
1870 11:37:25.472789 TX Bit4 (978~997) 20 987, Bit12 (970~988) 19 979,
1871 11:37:25.479450 TX Bit5 (976~993) 18 984, Bit13 (970~989) 20 979,
1872 11:37:25.483014 TX Bit6 (977~995) 19 986, Bit14 (970~991) 22 980,
1873 11:37:25.489179 TX Bit7 (978~998) 21 988, Bit15 (975~992) 18 983,
1874 11:37:25.489293
1875 11:37:25.489392 Write Rank1 MR14 =0x10
1876 11:37:25.499110
1877 11:37:25.502198 CH=0, VrefRange= 0, VrefLevel = 16
1878 11:37:25.505356 TX Bit0 (978~998) 21 988, Bit8 (968~988) 21 978,
1879 11:37:25.508892 TX Bit1 (978~998) 21 988, Bit9 (970~988) 19 979,
1880 11:37:25.515388 TX Bit2 (978~998) 21 988, Bit10 (975~993) 19 984,
1881 11:37:25.518617 TX Bit3 (972~992) 21 982, Bit11 (968~986) 19 977,
1882 11:37:25.521887 TX Bit4 (978~997) 20 987, Bit12 (970~989) 20 979,
1883 11:37:25.528504 TX Bit5 (976~993) 18 984, Bit13 (970~990) 21 980,
1884 11:37:25.531854 TX Bit6 (976~995) 20 985, Bit14 (970~992) 23 981,
1885 11:37:25.538142 TX Bit7 (978~998) 21 988, Bit15 (975~993) 19 984,
1886 11:37:25.538255
1887 11:37:25.538351 Write Rank1 MR14 =0x12
1888 11:37:25.548218
1889 11:37:25.551288 CH=0, VrefRange= 0, VrefLevel = 18
1890 11:37:25.554817 TX Bit0 (978~999) 22 988, Bit8 (968~988) 21 978,
1891 11:37:25.557955 TX Bit1 (978~999) 22 988, Bit9 (969~989) 21 979,
1892 11:37:25.564564 TX Bit2 (979~998) 20 988, Bit10 (975~994) 20 984,
1893 11:37:25.567596 TX Bit3 (972~992) 21 982, Bit11 (968~987) 20 977,
1894 11:37:25.571131 TX Bit4 (977~998) 22 987, Bit12 (970~989) 20 979,
1895 11:37:25.577511 TX Bit5 (976~994) 19 985, Bit13 (969~990) 22 979,
1896 11:37:25.580713 TX Bit6 (976~996) 21 986, Bit14 (970~992) 23 981,
1897 11:37:25.587222 TX Bit7 (978~998) 21 988, Bit15 (975~993) 19 984,
1898 11:37:25.587329
1899 11:37:25.587429 Write Rank1 MR14 =0x14
1900 11:37:25.597102
1901 11:37:25.600442 CH=0, VrefRange= 0, VrefLevel = 20
1902 11:37:25.603702 TX Bit0 (978~999) 22 988, Bit8 (967~988) 22 977,
1903 11:37:25.606862 TX Bit1 (978~999) 22 988, Bit9 (969~990) 22 979,
1904 11:37:25.613733 TX Bit2 (978~999) 22 988, Bit10 (974~994) 21 984,
1905 11:37:25.616785 TX Bit3 (971~993) 23 982, Bit11 (968~987) 20 977,
1906 11:37:25.620064 TX Bit4 (977~998) 22 987, Bit12 (969~990) 22 979,
1907 11:37:25.626688 TX Bit5 (975~994) 20 984, Bit13 (969~991) 23 980,
1908 11:37:25.629821 TX Bit6 (976~997) 22 986, Bit14 (969~992) 24 980,
1909 11:37:25.636299 TX Bit7 (978~999) 22 988, Bit15 (974~994) 21 984,
1910 11:37:25.636406
1911 11:37:25.636498 Write Rank1 MR14 =0x16
1912 11:37:25.646572
1913 11:37:25.649753 CH=0, VrefRange= 0, VrefLevel = 22
1914 11:37:25.652906 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
1915 11:37:25.656220 TX Bit1 (977~999) 23 988, Bit9 (969~990) 22 979,
1916 11:37:25.662902 TX Bit2 (978~999) 22 988, Bit10 (974~996) 23 985,
1917 11:37:25.666031 TX Bit3 (971~993) 23 982, Bit11 (968~988) 21 978,
1918 11:37:25.669536 TX Bit4 (977~999) 23 988, Bit12 (969~990) 22 979,
1919 11:37:25.676105 TX Bit5 (975~995) 21 985, Bit13 (969~991) 23 980,
1920 11:37:25.679343 TX Bit6 (976~998) 23 987, Bit14 (969~993) 25 981,
1921 11:37:25.685570 TX Bit7 (977~999) 23 988, Bit15 (974~995) 22 984,
1922 11:37:25.685681
1923 11:37:25.685777 Write Rank1 MR14 =0x18
1924 11:37:25.695935
1925 11:37:25.699303 CH=0, VrefRange= 0, VrefLevel = 24
1926 11:37:25.702526 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
1927 11:37:25.705631 TX Bit1 (977~1000) 24 988, Bit9 (969~990) 22 979,
1928 11:37:25.712273 TX Bit2 (978~999) 22 988, Bit10 (973~997) 25 985,
1929 11:37:25.715373 TX Bit3 (970~994) 25 982, Bit11 (968~989) 22 978,
1930 11:37:25.718634 TX Bit4 (977~999) 23 988, Bit12 (969~990) 22 979,
1931 11:37:25.725240 TX Bit5 (975~996) 22 985, Bit13 (969~991) 23 980,
1932 11:37:25.728530 TX Bit6 (976~998) 23 987, Bit14 (969~993) 25 981,
1933 11:37:25.735096 TX Bit7 (977~999) 23 988, Bit15 (973~996) 24 984,
1934 11:37:25.735175
1935 11:37:25.735245 Write Rank1 MR14 =0x1a
1936 11:37:25.745188
1937 11:37:25.748375 CH=0, VrefRange= 0, VrefLevel = 26
1938 11:37:25.751834 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
1939 11:37:25.755068 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1940 11:37:25.761563 TX Bit2 (978~1000) 23 989, Bit10 (973~997) 25 985,
1941 11:37:25.765041 TX Bit3 (970~994) 25 982, Bit11 (967~990) 24 978,
1942 11:37:25.771277 TX Bit4 (977~999) 23 988, Bit12 (968~991) 24 979,
1943 11:37:25.774466 TX Bit5 (974~996) 23 985, Bit13 (968~992) 25 980,
1944 11:37:25.777934 TX Bit6 (975~999) 25 987, Bit14 (969~993) 25 981,
1945 11:37:25.784465 TX Bit7 (977~1000) 24 988, Bit15 (973~996) 24 984,
1946 11:37:25.784541
1947 11:37:25.784605 Write Rank1 MR14 =0x1c
1948 11:37:25.794926
1949 11:37:25.798433 CH=0, VrefRange= 0, VrefLevel = 28
1950 11:37:25.801520 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
1951 11:37:25.804628 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1952 11:37:25.811371 TX Bit2 (978~1000) 23 989, Bit10 (973~997) 25 985,
1953 11:37:25.814478 TX Bit3 (970~995) 26 982, Bit11 (967~990) 24 978,
1954 11:37:25.821054 TX Bit4 (976~1000) 25 988, Bit12 (969~991) 23 980,
1955 11:37:25.824404 TX Bit5 (974~997) 24 985, Bit13 (968~992) 25 980,
1956 11:37:25.827765 TX Bit6 (975~999) 25 987, Bit14 (968~993) 26 980,
1957 11:37:25.834044 TX Bit7 (977~1000) 24 988, Bit15 (973~997) 25 985,
1958 11:37:25.834151
1959 11:37:25.834244 Write Rank1 MR14 =0x1e
1960 11:37:25.844689
1961 11:37:25.848090 CH=0, VrefRange= 0, VrefLevel = 30
1962 11:37:25.851365 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1963 11:37:25.854499 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1964 11:37:25.861072 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
1965 11:37:25.864337 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1966 11:37:25.870794 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
1967 11:37:25.874419 TX Bit5 (974~998) 25 986, Bit13 (968~991) 24 979,
1968 11:37:25.877540 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
1969 11:37:25.884193 TX Bit7 (976~1001) 26 988, Bit15 (973~997) 25 985,
1970 11:37:25.884299
1971 11:37:25.884393 Write Rank1 MR14 =0x20
1972 11:37:25.894805
1973 11:37:25.898310 CH=0, VrefRange= 0, VrefLevel = 32
1974 11:37:25.901411 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1975 11:37:25.904522 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1976 11:37:25.911348 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
1977 11:37:25.914468 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1978 11:37:25.921024 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
1979 11:37:25.924289 TX Bit5 (974~998) 25 986, Bit13 (968~991) 24 979,
1980 11:37:25.927385 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
1981 11:37:25.934067 TX Bit7 (976~1001) 26 988, Bit15 (973~997) 25 985,
1982 11:37:25.934177
1983 11:37:25.934274 Write Rank1 MR14 =0x22
1984 11:37:25.944819
1985 11:37:25.947775 CH=0, VrefRange= 0, VrefLevel = 34
1986 11:37:25.951302 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1987 11:37:25.954604 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1988 11:37:25.960988 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
1989 11:37:25.964266 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1990 11:37:25.970790 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
1991 11:37:25.974199 TX Bit5 (974~998) 25 986, Bit13 (968~991) 24 979,
1992 11:37:25.977452 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
1993 11:37:25.983919 TX Bit7 (976~1001) 26 988, Bit15 (973~997) 25 985,
1994 11:37:25.984028
1995 11:37:25.987227 wait MRW command Rank1 MR14 =0x24 fired (1)
1996 11:37:25.990195 Write Rank1 MR14 =0x24
1997 11:37:25.998303
1998 11:37:26.001528 CH=0, VrefRange= 0, VrefLevel = 36
1999 11:37:26.005072 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
2000 11:37:26.008037 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
2001 11:37:26.014630 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2002 11:37:26.018054 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
2003 11:37:26.024703 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
2004 11:37:26.027745 TX Bit5 (974~998) 25 986, Bit13 (968~991) 24 979,
2005 11:37:26.031271 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
2006 11:37:26.037569 TX Bit7 (976~1001) 26 988, Bit15 (973~997) 25 985,
2007 11:37:26.037674
2008 11:37:26.037780 Write Rank1 MR14 =0x26
2009 11:37:26.048263
2010 11:37:26.051537 CH=0, VrefRange= 0, VrefLevel = 38
2011 11:37:26.054685 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
2012 11:37:26.057982 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
2013 11:37:26.064566 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
2014 11:37:26.067965 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
2015 11:37:26.074195 TX Bit4 (977~1000) 24 988, Bit12 (968~991) 24 979,
2016 11:37:26.077676 TX Bit5 (974~998) 25 986, Bit13 (968~991) 24 979,
2017 11:37:26.080979 TX Bit6 (976~999) 24 987, Bit14 (969~993) 25 981,
2018 11:37:26.087530 TX Bit7 (976~1001) 26 988, Bit15 (973~997) 25 985,
2019 11:37:26.087616
2020 11:37:26.087682
2021 11:37:26.090549 TX Vref found, early break! 365< 373
2022 11:37:26.093968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2023 11:37:26.097427 u1DelayCellOfst[0]=9 cells (7 PI)
2024 11:37:26.100626 u1DelayCellOfst[1]=7 cells (6 PI)
2025 11:37:26.103977 u1DelayCellOfst[2]=9 cells (7 PI)
2026 11:37:26.107004 u1DelayCellOfst[3]=0 cells (0 PI)
2027 11:37:26.110362 u1DelayCellOfst[4]=7 cells (6 PI)
2028 11:37:26.113637 u1DelayCellOfst[5]=5 cells (4 PI)
2029 11:37:26.116936 u1DelayCellOfst[6]=6 cells (5 PI)
2030 11:37:26.120352 u1DelayCellOfst[7]=7 cells (6 PI)
2031 11:37:26.123382 Byte0, DQ PI dly=982, DQM PI dly= 985
2032 11:37:26.126886 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2033 11:37:26.126994
2034 11:37:26.129954 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2035 11:37:26.130040
2036 11:37:26.133510 u1DelayCellOfst[8]=0 cells (0 PI)
2037 11:37:26.136575 u1DelayCellOfst[9]=0 cells (0 PI)
2038 11:37:26.140084 u1DelayCellOfst[10]=7 cells (6 PI)
2039 11:37:26.143156 u1DelayCellOfst[11]=0 cells (0 PI)
2040 11:37:26.146352 u1DelayCellOfst[12]=0 cells (0 PI)
2041 11:37:26.149841 u1DelayCellOfst[13]=0 cells (0 PI)
2042 11:37:26.152953 u1DelayCellOfst[14]=2 cells (2 PI)
2043 11:37:26.156560 u1DelayCellOfst[15]=7 cells (6 PI)
2044 11:37:26.159826 Byte1, DQ PI dly=979, DQM PI dly= 982
2045 11:37:26.162882 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2046 11:37:26.163029
2047 11:37:26.169260 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2048 11:37:26.169396
2049 11:37:26.169500 Write Rank1 MR14 =0x1e
2050 11:37:26.169593
2051 11:37:26.172642 Final TX Range 0 Vref 30
2052 11:37:26.172731
2053 11:37:26.179265 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2054 11:37:26.179375
2055 11:37:26.185952 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2056 11:37:26.192475 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2057 11:37:26.199071 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2058 11:37:26.202068 Write Rank1 MR3 =0xb0
2059 11:37:26.205488 DramC Write-DBI on
2060 11:37:26.205576 ==
2061 11:37:26.208594 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2062 11:37:26.212064 fsp= 1, odt_onoff= 1, Byte mode= 0
2063 11:37:26.212144 ==
2064 11:37:26.215293 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2065 11:37:26.218399
2066 11:37:26.218531 Begin, DQ Scan Range 702~766
2067 11:37:26.218631
2068 11:37:26.218760
2069 11:37:26.221718 TX Vref Scan disable
2070 11:37:26.225091 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2071 11:37:26.228483 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2072 11:37:26.231683 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2073 11:37:26.235205 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2074 11:37:26.238242 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2075 11:37:26.241483 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2076 11:37:26.244563 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2077 11:37:26.251159 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2078 11:37:26.254619 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2079 11:37:26.257800 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2080 11:37:26.261072 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2081 11:37:26.264264 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2082 11:37:26.267314 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2083 11:37:26.270817 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2084 11:37:26.274141 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2085 11:37:26.277333 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2086 11:37:26.280511 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2087 11:37:26.288696 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2088 11:37:26.292060 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2089 11:37:26.295282 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2090 11:37:26.298782 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2091 11:37:26.301892 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2092 11:37:26.305388 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2093 11:37:26.308415 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2094 11:37:26.311771 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2095 11:37:26.314822 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2096 11:37:26.318350 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2097 11:37:26.321434 Byte0, DQ PI dly=731, DQM PI dly= 731
2098 11:37:26.328166 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2099 11:37:26.328268
2100 11:37:26.331283 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2101 11:37:26.331387
2102 11:37:26.334624 Byte1, DQ PI dly=723, DQM PI dly= 723
2103 11:37:26.337697 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2104 11:37:26.337795
2105 11:37:26.344245 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2106 11:37:26.344325
2107 11:37:26.350923 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2108 11:37:26.357462 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2109 11:37:26.364099 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2110 11:37:26.367489 Write Rank1 MR3 =0x30
2111 11:37:26.367573 DramC Write-DBI off
2112 11:37:26.367640
2113 11:37:26.370521 [DATLAT]
2114 11:37:26.374124 Freq=1600, CH0 RK1, use_rxtx_scan=0
2115 11:37:26.374228
2116 11:37:26.374321 DATLAT Default: 0x10
2117 11:37:26.377252 7, 0xFFFF, sum=0
2118 11:37:26.377333 8, 0xFFFF, sum=0
2119 11:37:26.380631 9, 0xFFFF, sum=0
2120 11:37:26.380702 10, 0xFFFF, sum=0
2121 11:37:26.383803 11, 0xFFFF, sum=0
2122 11:37:26.383874 12, 0xFFFF, sum=0
2123 11:37:26.387019 13, 0xFFFF, sum=0
2124 11:37:26.387090 14, 0x0, sum=1
2125 11:37:26.387150 15, 0x0, sum=2
2126 11:37:26.390124 16, 0x0, sum=3
2127 11:37:26.390192 17, 0x0, sum=4
2128 11:37:26.396858 pattern=2 first_step=14 total pass=5 best_step=16
2129 11:37:26.396964 ==
2130 11:37:26.400253 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2131 11:37:26.403386 fsp= 1, odt_onoff= 1, Byte mode= 0
2132 11:37:26.403499 ==
2133 11:37:26.409982 Start DQ dly to find pass range UseTestEngine =1
2134 11:37:26.413624 x-axis: bit #, y-axis: DQ dly (-127~63)
2135 11:37:26.413728 RX Vref Scan = 0
2136 11:37:26.416736 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2137 11:37:26.420175 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2138 11:37:26.423367 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2139 11:37:26.426541 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2140 11:37:26.426643 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2141 11:37:26.430074 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2142 11:37:26.433154 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2143 11:37:26.436633 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2144 11:37:26.439908 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2145 11:37:26.443076 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2146 11:37:26.446293 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2147 11:37:26.449738 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2148 11:37:26.452901 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2149 11:37:26.456012 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2150 11:37:26.456117 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2151 11:37:26.459470 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2152 11:37:26.462829 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2153 11:37:26.465920 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2154 11:37:26.469350 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2155 11:37:26.472502 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2156 11:37:26.475791 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2157 11:37:26.479243 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2158 11:37:26.479348 -4, [0] xxxxxxxx oxxxxxxx [MSB]
2159 11:37:26.482311 -3, [0] xxxxxxxx oxxoxxxx [MSB]
2160 11:37:26.485787 -2, [0] xxxoxxxx ooxoxoxx [MSB]
2161 11:37:26.489003 -1, [0] xxxoxxxx ooxoxoxx [MSB]
2162 11:37:26.492195 0, [0] xxxoxoxx ooxoooxx [MSB]
2163 11:37:26.495422 1, [0] xxxoxoox ooxoooxx [MSB]
2164 11:37:26.498778 2, [0] xxxoxoox ooxoooox [MSB]
2165 11:37:26.498856 3, [0] xxxoxooo ooxoooox [MSB]
2166 11:37:26.502034 4, [0] ooxoxooo ooxooooo [MSB]
2167 11:37:26.505363 5, [0] ooxooooo oooooooo [MSB]
2168 11:37:26.509211 32, [0] oooxoooo oooooooo [MSB]
2169 11:37:26.512718 33, [0] oooxoooo xooxoooo [MSB]
2170 11:37:26.516128 34, [0] oooxoooo xooxoooo [MSB]
2171 11:37:26.519167 35, [0] oooxoxoo xxoxxxoo [MSB]
2172 11:37:26.522669 36, [0] oooxoxxo xxoxxxoo [MSB]
2173 11:37:26.525789 37, [0] oooxoxxo xxoxxxxo [MSB]
2174 11:37:26.528955 38, [0] oooxoxxx xxoxxxxx [MSB]
2175 11:37:26.529057 39, [0] oxoxxxxx xxoxxxxx [MSB]
2176 11:37:26.532490 40, [0] xxoxxxxx xxoxxxxx [MSB]
2177 11:37:26.535617 41, [0] xxxxxxxx xxxxxxxx [MSB]
2178 11:37:26.538688 iDelay=41, Bit 0, Center 21 (4 ~ 39) 36
2179 11:37:26.542186 iDelay=41, Bit 1, Center 21 (4 ~ 38) 35
2180 11:37:26.545611 iDelay=41, Bit 2, Center 23 (6 ~ 40) 35
2181 11:37:26.551888 iDelay=41, Bit 3, Center 14 (-2 ~ 31) 34
2182 11:37:26.555052 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34
2183 11:37:26.558494 iDelay=41, Bit 5, Center 17 (0 ~ 34) 35
2184 11:37:26.561631 iDelay=41, Bit 6, Center 18 (1 ~ 35) 35
2185 11:37:26.565044 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
2186 11:37:26.568553 iDelay=41, Bit 8, Center 14 (-4 ~ 32) 37
2187 11:37:26.571411 iDelay=41, Bit 9, Center 16 (-2 ~ 34) 37
2188 11:37:26.574949 iDelay=41, Bit 10, Center 22 (5 ~ 40) 36
2189 11:37:26.578161 iDelay=41, Bit 11, Center 14 (-3 ~ 32) 36
2190 11:37:26.581590 iDelay=41, Bit 12, Center 17 (0 ~ 34) 35
2191 11:37:26.588076 iDelay=41, Bit 13, Center 16 (-2 ~ 34) 37
2192 11:37:26.591328 iDelay=41, Bit 14, Center 19 (2 ~ 36) 35
2193 11:37:26.594612 iDelay=41, Bit 15, Center 20 (4 ~ 37) 34
2194 11:37:26.594713 ==
2195 11:37:26.597767 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2196 11:37:26.600863 fsp= 1, odt_onoff= 1, Byte mode= 0
2197 11:37:26.600967 ==
2198 11:37:26.604449 DQS Delay:
2199 11:37:26.604550 DQS0 = 0, DQS1 = 0
2200 11:37:26.607733 DQM Delay:
2201 11:37:26.607833 DQM0 = 19, DQM1 = 17
2202 11:37:26.607931 DQ Delay:
2203 11:37:26.611015 DQ0 =21, DQ1 =21, DQ2 =23, DQ3 =14
2204 11:37:26.614334 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
2205 11:37:26.617318 DQ8 =14, DQ9 =16, DQ10 =22, DQ11 =14
2206 11:37:26.620622 DQ12 =17, DQ13 =16, DQ14 =19, DQ15 =20
2207 11:37:26.620751
2208 11:37:26.620844
2209 11:37:26.623806
2210 11:37:26.623935 [DramC_TX_OE_Calibration] TA2
2211 11:37:26.627155 Original DQ_B0 (3 6) =30, OEN = 27
2212 11:37:26.630410 Original DQ_B1 (3 6) =30, OEN = 27
2213 11:37:26.633985 23, 0x0, End_B0=23 End_B1=23
2214 11:37:26.637071 24, 0x0, End_B0=24 End_B1=24
2215 11:37:26.640187 25, 0x0, End_B0=25 End_B1=25
2216 11:37:26.640336 26, 0x0, End_B0=26 End_B1=26
2217 11:37:26.643765 27, 0x0, End_B0=27 End_B1=27
2218 11:37:26.646698 28, 0x0, End_B0=28 End_B1=28
2219 11:37:26.650221 29, 0x0, End_B0=29 End_B1=29
2220 11:37:26.653610 30, 0x0, End_B0=30 End_B1=30
2221 11:37:26.653845 31, 0xFFFF, End_B0=30 End_B1=30
2222 11:37:26.660054 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2223 11:37:26.666651 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2224 11:37:26.666931
2225 11:37:26.667201
2226 11:37:26.670304 Write Rank1 MR23 =0x3f
2227 11:37:26.670697 [DQSOSC]
2228 11:37:26.676928 [DQSOSCAuto] RK1, (LSB)MR18= 0xa5a5, (MSB)MR19= 0x202, tDQSOscB0 = 465 ps tDQSOscB1 = 465 ps
2229 11:37:26.682962 CH0_RK1: MR19=0x202, MR18=0xA5A5, DQSOSC=465, MR23=63, INC=11, DEC=17
2230 11:37:26.686430 Write Rank1 MR23 =0x3f
2231 11:37:26.686907 [DQSOSC]
2232 11:37:26.693208 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0x202, tDQSOscB0 = 464 ps tDQSOscB1 = 464 ps
2233 11:37:26.696272 CH0 RK1: MR19=202, MR18=A6A6
2234 11:37:26.699975 [RxdqsGatingPostProcess] freq 1600
2235 11:37:26.706267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2236 11:37:26.706747 Rank: 0
2237 11:37:26.709460 best DQS0 dly(2T, 0.5T) = (2, 6)
2238 11:37:26.712500 best DQS1 dly(2T, 0.5T) = (2, 6)
2239 11:37:26.715851 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2240 11:37:26.719162 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2241 11:37:26.719609 Rank: 1
2242 11:37:26.722459 best DQS0 dly(2T, 0.5T) = (2, 6)
2243 11:37:26.725678 best DQS1 dly(2T, 0.5T) = (2, 6)
2244 11:37:26.728789 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2245 11:37:26.732363 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2246 11:37:26.735524 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2247 11:37:26.738764 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2248 11:37:26.745494 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2249 11:37:26.746066 Write Rank0 MR13 =0x59
2250 11:37:26.748585 ==
2251 11:37:26.751921 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2252 11:37:26.755393 fsp= 1, odt_onoff= 1, Byte mode= 0
2253 11:37:26.755800 ==
2254 11:37:26.758541 === u2Vref_new: 0x56 --> 0x3a
2255 11:37:26.761737 === u2Vref_new: 0x58 --> 0x58
2256 11:37:26.765087 === u2Vref_new: 0x5a --> 0x5a
2257 11:37:26.768237 === u2Vref_new: 0x5c --> 0x78
2258 11:37:26.771654 === u2Vref_new: 0x5e --> 0x7a
2259 11:37:26.774684 === u2Vref_new: 0x60 --> 0x90
2260 11:37:26.778088 [CA 0] Center 37 (12~63) winsize 52
2261 11:37:26.781594 [CA 1] Center 37 (11~63) winsize 53
2262 11:37:26.784633 [CA 2] Center 34 (6~63) winsize 58
2263 11:37:26.788014 [CA 3] Center 34 (6~63) winsize 58
2264 11:37:26.791019 [CA 4] Center 34 (5~63) winsize 59
2265 11:37:26.794670 [CA 5] Center 28 (-1~58) winsize 60
2266 11:37:26.795175
2267 11:37:26.797627 [CATrainingPosCal] consider 1 rank data
2268 11:37:26.800840 u2DelayCellTimex100 = 744/100 ps
2269 11:37:26.804193 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2270 11:37:26.807483 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2271 11:37:26.810909 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2272 11:37:26.813938 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2273 11:37:26.817457 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2274 11:37:26.820550 CA5 delay=28 (-1~58),Diff = 0 PI (0 cell)
2275 11:37:26.821121
2276 11:37:26.827144 CA PerBit enable=1, Macro0, CA PI delay=28
2277 11:37:26.827718 === u2Vref_new: 0x5c --> 0x78
2278 11:37:26.828162
2279 11:37:26.830476 Vref(ca) range 1: 28
2280 11:37:26.830935
2281 11:37:26.833580 CS Dly= 12 (43-0-32)
2282 11:37:26.834091 Write Rank0 MR13 =0xd8
2283 11:37:26.837060 Write Rank0 MR13 =0xd8
2284 11:37:26.840297 Write Rank0 MR12 =0x5c
2285 11:37:26.840823 Write Rank1 MR13 =0x59
2286 11:37:26.841348 ==
2287 11:37:26.846940 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2288 11:37:26.850217 fsp= 1, odt_onoff= 1, Byte mode= 0
2289 11:37:26.850570 ==
2290 11:37:26.853337 === u2Vref_new: 0x56 --> 0x3a
2291 11:37:26.856703 === u2Vref_new: 0x58 --> 0x58
2292 11:37:26.859856 === u2Vref_new: 0x5a --> 0x5a
2293 11:37:26.860113 === u2Vref_new: 0x5c --> 0x78
2294 11:37:26.863369 === u2Vref_new: 0x5e --> 0x7a
2295 11:37:26.866589 === u2Vref_new: 0x60 --> 0x90
2296 11:37:26.869942 [CA 0] Center 37 (12~63) winsize 52
2297 11:37:26.873233 [CA 1] Center 37 (12~63) winsize 52
2298 11:37:26.876701 [CA 2] Center 34 (5~63) winsize 59
2299 11:37:26.879772 [CA 3] Center 34 (6~63) winsize 58
2300 11:37:26.883040 [CA 4] Center 33 (4~63) winsize 60
2301 11:37:26.886468 [CA 5] Center 29 (0~58) winsize 59
2302 11:37:26.886731
2303 11:37:26.889541 [CATrainingPosCal] consider 2 rank data
2304 11:37:26.892948 u2DelayCellTimex100 = 744/100 ps
2305 11:37:26.896431 CA0 delay=37 (12~63),Diff = 8 PI (10 cell)
2306 11:37:26.899685 CA1 delay=37 (12~63),Diff = 8 PI (10 cell)
2307 11:37:26.905996 CA2 delay=34 (6~63),Diff = 5 PI (6 cell)
2308 11:37:26.909339 CA3 delay=34 (6~63),Diff = 5 PI (6 cell)
2309 11:37:26.912765 CA4 delay=34 (5~63),Diff = 5 PI (6 cell)
2310 11:37:26.915916 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2311 11:37:26.916448
2312 11:37:26.919369 CA PerBit enable=1, Macro0, CA PI delay=29
2313 11:37:26.922619 === u2Vref_new: 0x5e --> 0x7a
2314 11:37:26.923004
2315 11:37:26.925663 Vref(ca) range 1: 30
2316 11:37:26.926158
2317 11:37:26.926566 CS Dly= 11 (42-0-32)
2318 11:37:26.929189 Write Rank1 MR13 =0xd8
2319 11:37:26.929545 Write Rank1 MR13 =0xd8
2320 11:37:26.932490 Write Rank1 MR12 =0x5e
2321 11:37:26.935551 [RankSwap] Rank num 2, (Multi 1), Rank 0
2322 11:37:26.938918 Write Rank0 MR2 =0xad
2323 11:37:26.939439 [Write Leveling]
2324 11:37:26.942286 delay byte0 byte1 byte2 byte3
2325 11:37:26.942830
2326 11:37:26.945427 10 0 0
2327 11:37:26.945785 11 0 0
2328 11:37:26.946060 12 0 0
2329 11:37:26.948833 13 0 0
2330 11:37:26.949310 14 0 0
2331 11:37:26.952032 15 0 0
2332 11:37:26.952390 16 0 0
2333 11:37:26.955243 17 0 0
2334 11:37:26.955643 18 0 0
2335 11:37:26.955923 19 0 0
2336 11:37:26.958809 20 0 0
2337 11:37:26.959166 21 0 0
2338 11:37:26.961844 22 0 0
2339 11:37:26.962202 23 0 0
2340 11:37:26.964956 24 0 0
2341 11:37:26.965312 25 0 0
2342 11:37:26.965642 26 0 0
2343 11:37:26.968376 27 0 0
2344 11:37:26.968734 28 0 0
2345 11:37:26.971565 29 0 ff
2346 11:37:26.971923 30 0 ff
2347 11:37:26.974822 31 0 ff
2348 11:37:26.975177 32 0 ff
2349 11:37:26.975544 33 0 ff
2350 11:37:26.978374 34 0 ff
2351 11:37:26.978870 35 0 ff
2352 11:37:26.981394 36 ff ff
2353 11:37:26.981480 37 ff ff
2354 11:37:26.984487 38 ff ff
2355 11:37:26.984572 39 ff ff
2356 11:37:26.987817 40 ff ff
2357 11:37:26.987902 41 ff ff
2358 11:37:26.990888 42 ff ff
2359 11:37:26.994313 pass bytecount = 0xff (0xff: all bytes pass)
2360 11:37:26.994400
2361 11:37:26.994466 DQS0 dly: 36
2362 11:37:26.997780 DQS1 dly: 29
2363 11:37:26.997864 Write Rank0 MR2 =0x2d
2364 11:37:27.001009 [RankSwap] Rank num 2, (Multi 1), Rank 0
2365 11:37:27.004085 Write Rank0 MR1 =0xd6
2366 11:37:27.004168 [Gating]
2367 11:37:27.004233 ==
2368 11:37:27.010677 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2369 11:37:27.013951 fsp= 1, odt_onoff= 1, Byte mode= 0
2370 11:37:27.014035 ==
2371 11:37:27.017101 3 1 0 |2c2b 3737 |(11 11)(11 11) |(1 1)(1 1)| 0
2372 11:37:27.023791 3 1 4 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2373 11:37:27.027307 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2374 11:37:27.030384 3 1 12 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
2375 11:37:27.037045 3 1 16 |2c2b 3635 |(11 11)(11 11) |(1 0)(1 1)| 0
2376 11:37:27.040106 3 1 20 |2c2b 201 |(11 11)(11 11) |(1 0)(1 1)| 0
2377 11:37:27.043287 3 1 24 |2c2b 2121 |(11 11)(11 11) |(1 0)(1 1)| 0
2378 11:37:27.046778 [Byte 1] Lead/lag Transition tap number (1)
2379 11:37:27.053169 3 1 28 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0
2380 11:37:27.056596 3 2 0 |2c2b 2b2a |(11 11)(11 11) |(1 0)(1 1)| 0
2381 11:37:27.059948 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2382 11:37:27.066449 3 2 8 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 1)| 0
2383 11:37:27.069585 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2384 11:37:27.072970 3 2 16 |302 3434 |(11 1)(11 11) |(0 0)(0 1)| 0
2385 11:37:27.079574 3 2 20 |909 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
2386 11:37:27.082567 3 2 24 |3534 706 |(11 11)(11 11) |(0 0)(1 1)| 0
2387 11:37:27.086099 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2388 11:37:27.092380 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2389 11:37:27.095953 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2390 11:37:27.099033 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2391 11:37:27.105614 3 3 12 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
2392 11:37:27.108795 3 3 16 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2393 11:37:27.112178 3 3 20 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2394 11:37:27.118901 [Byte 0] Lead/lag falling Transition (3, 3, 20)
2395 11:37:27.122033 3 3 24 |3534 202 |(11 11)(11 11) |(0 1)(1 1)| 0
2396 11:37:27.125152 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2397 11:37:27.131605 [Byte 1] Lead/lag falling Transition (3, 3, 28)
2398 11:37:27.135117 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2399 11:37:27.138135 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2400 11:37:27.141583 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2401 11:37:27.148292 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2402 11:37:27.151346 3 4 16 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2403 11:37:27.154861 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2404 11:37:27.161127 3 4 24 |3d3d 1211 |(11 11)(11 11) |(1 1)(1 1)| 0
2405 11:37:27.164385 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2406 11:37:27.167653 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2407 11:37:27.174449 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2408 11:37:27.177649 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2409 11:37:27.180966 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2410 11:37:27.187513 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2411 11:37:27.190710 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2412 11:37:27.193874 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2413 11:37:27.200588 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2414 11:37:27.203879 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2415 11:37:27.206948 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2416 11:37:27.213440 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2417 11:37:27.216964 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2418 11:37:27.220137 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2419 11:37:27.226912 [Byte 0] Lead/lag Transition tap number (2)
2420 11:37:27.230048 [Byte 1] Lead/lag falling Transition (3, 6, 12)
2421 11:37:27.233216 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2422 11:37:27.236685 [Byte 1] Lead/lag Transition tap number (2)
2423 11:37:27.243132 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
2424 11:37:27.243254 [Byte 0]First pass (3, 6, 20)
2425 11:37:27.249585 3 6 24 |4646 1212 |(0 0)(11 11) |(0 0)(0 0)| 0
2426 11:37:27.253112 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2427 11:37:27.256191 [Byte 1]First pass (3, 6, 28)
2428 11:37:27.259639 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2429 11:37:27.262966 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2430 11:37:27.265971 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2431 11:37:27.272557 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2432 11:37:27.275852 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2433 11:37:27.279344 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2434 11:37:27.282442 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2435 11:37:27.289097 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2436 11:37:27.292375 All bytes gating window > 1UI, Early break!
2437 11:37:27.292461
2438 11:37:27.295663 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2439 11:37:27.295777
2440 11:37:27.298866 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 16)
2441 11:37:27.298981
2442 11:37:27.299077
2443 11:37:27.299167
2444 11:37:27.302358 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2445 11:37:27.302485
2446 11:37:27.308570 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
2447 11:37:27.308681
2448 11:37:27.308778
2449 11:37:27.308877 Write Rank0 MR1 =0x56
2450 11:37:27.308966
2451 11:37:27.311972 best RODT dly(2T, 0.5T) = (2, 3)
2452 11:37:27.312087
2453 11:37:27.315067 best RODT dly(2T, 0.5T) = (2, 3)
2454 11:37:27.315182 ==
2455 11:37:27.321663 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2456 11:37:27.324960 fsp= 1, odt_onoff= 1, Byte mode= 0
2457 11:37:27.325075 ==
2458 11:37:27.328379 Start DQ dly to find pass range UseTestEngine =0
2459 11:37:27.331376 x-axis: bit #, y-axis: DQ dly (-127~63)
2460 11:37:27.334996 RX Vref Scan = 0
2461 11:37:27.338060 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2462 11:37:27.341611 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2463 11:37:27.341717 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2464 11:37:27.344634 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2465 11:37:27.347973 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2466 11:37:27.351370 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2467 11:37:27.354532 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2468 11:37:27.357664 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2469 11:37:27.361097 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2470 11:37:27.364256 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2471 11:37:27.367476 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2472 11:37:27.370759 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2473 11:37:27.370879 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2474 11:37:27.374168 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2475 11:37:27.377247 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2476 11:37:27.380601 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2477 11:37:27.383958 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2478 11:37:27.387230 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2479 11:37:27.390291 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2480 11:37:27.393921 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2481 11:37:27.394040 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2482 11:37:27.396854 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2483 11:37:27.400287 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2484 11:37:27.403475 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2485 11:37:27.406978 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2486 11:37:27.410231 -1, [0] xxxoxxxx ooxxxxxo [MSB]
2487 11:37:27.413329 0, [0] xxxoxxxx ooxxxxxo [MSB]
2488 11:37:27.413458 1, [0] xxxoxxxx ooxxxxxo [MSB]
2489 11:37:27.416542 2, [0] xxooxxxo oooxxxxo [MSB]
2490 11:37:27.419747 3, [0] xxooxxxo oooooxoo [MSB]
2491 11:37:27.423188 4, [0] xooooxxo oooooooo [MSB]
2492 11:37:27.426445 5, [0] oooooxoo oooooooo [MSB]
2493 11:37:27.429582 6, [0] oooooxoo oooooooo [MSB]
2494 11:37:27.432891 32, [0] oooooooo ooooooox [MSB]
2495 11:37:27.433024 33, [0] oooooooo ooooooox [MSB]
2496 11:37:27.436368 34, [0] oooooooo ooooooox [MSB]
2497 11:37:27.439443 35, [0] ooxooooo oxooooox [MSB]
2498 11:37:27.443090 36, [0] ooxxoooo oxooooox [MSB]
2499 11:37:27.446186 37, [0] ooxxoooo xxooooox [MSB]
2500 11:37:27.449244 38, [0] ooxxoooo xxooooox [MSB]
2501 11:37:27.452676 39, [0] oxxxooox xxxxooox [MSB]
2502 11:37:27.455850 40, [0] oxxxxoox xxxxxoox [MSB]
2503 11:37:27.456015 41, [0] xxxxxoxx xxxxxxxx [MSB]
2504 11:37:27.459438 42, [0] xxxxxoxx xxxxxxxx [MSB]
2505 11:37:27.462451 43, [0] xxxxxxxx xxxxxxxx [MSB]
2506 11:37:27.465881 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
2507 11:37:27.469069 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
2508 11:37:27.472625 iDelay=43, Bit 2, Center 18 (2 ~ 34) 33
2509 11:37:27.478808 iDelay=43, Bit 3, Center 17 (-1 ~ 35) 37
2510 11:37:27.482268 iDelay=43, Bit 4, Center 21 (4 ~ 39) 36
2511 11:37:27.485295 iDelay=43, Bit 5, Center 24 (7 ~ 42) 36
2512 11:37:27.488641 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
2513 11:37:27.491864 iDelay=43, Bit 7, Center 20 (2 ~ 38) 37
2514 11:37:27.495334 iDelay=43, Bit 8, Center 17 (-1 ~ 36) 38
2515 11:37:27.498513 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
2516 11:37:27.501750 iDelay=43, Bit 10, Center 20 (2 ~ 38) 37
2517 11:37:27.505235 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
2518 11:37:27.508468 iDelay=43, Bit 12, Center 21 (3 ~ 39) 37
2519 11:37:27.511577 iDelay=43, Bit 13, Center 22 (4 ~ 40) 37
2520 11:37:27.518094 iDelay=43, Bit 14, Center 21 (3 ~ 40) 38
2521 11:37:27.521286 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
2522 11:37:27.521399 ==
2523 11:37:27.524552 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2524 11:37:27.527930 fsp= 1, odt_onoff= 1, Byte mode= 0
2525 11:37:27.528034 ==
2526 11:37:27.531218 DQS Delay:
2527 11:37:27.531327 DQS0 = 0, DQS1 = 0
2528 11:37:27.534374 DQM Delay:
2529 11:37:27.534481 DQM0 = 20, DQM1 = 18
2530 11:37:27.534546 DQ Delay:
2531 11:37:27.537891 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =17
2532 11:37:27.541057 DQ4 =21, DQ5 =24, DQ6 =22, DQ7 =20
2533 11:37:27.544297 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =20
2534 11:37:27.547774 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =13
2535 11:37:27.547881
2536 11:37:27.547974
2537 11:37:27.550719 DramC Write-DBI off
2538 11:37:27.550821 ==
2539 11:37:27.557569 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2540 11:37:27.560563 fsp= 1, odt_onoff= 1, Byte mode= 0
2541 11:37:27.560672 ==
2542 11:37:27.564072 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2543 11:37:27.564174
2544 11:37:27.567291 Begin, DQ Scan Range 925~1181
2545 11:37:27.567394
2546 11:37:27.567497
2547 11:37:27.570269 TX Vref Scan disable
2548 11:37:27.573862 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2549 11:37:27.577027 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2550 11:37:27.580193 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2551 11:37:27.583465 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2552 11:37:27.586977 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2553 11:37:27.589994 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2554 11:37:27.593503 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2555 11:37:27.596577 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2556 11:37:27.599908 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2557 11:37:27.603073 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2558 11:37:27.606534 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2559 11:37:27.609678 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2560 11:37:27.616265 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2561 11:37:27.619424 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2562 11:37:27.623046 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2563 11:37:27.626140 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2564 11:37:27.629233 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2565 11:37:27.632789 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2566 11:37:27.635873 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2567 11:37:27.639238 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2568 11:37:27.642615 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2569 11:37:27.645897 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2570 11:37:27.649000 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2571 11:37:27.652584 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2572 11:37:27.655673 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2573 11:37:27.662081 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2574 11:37:27.665570 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2575 11:37:27.668992 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2576 11:37:27.672088 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2577 11:37:27.675161 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2578 11:37:27.678636 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2579 11:37:27.681654 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2580 11:37:27.684993 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2581 11:37:27.688347 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2582 11:37:27.691415 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2583 11:37:27.694925 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2584 11:37:27.698286 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2585 11:37:27.701411 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2586 11:37:27.704773 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2587 11:37:27.711062 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2588 11:37:27.714464 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2589 11:37:27.717891 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2590 11:37:27.721110 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2591 11:37:27.724292 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2592 11:37:27.727714 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2593 11:37:27.731071 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2594 11:37:27.734052 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2595 11:37:27.737625 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2596 11:37:27.740720 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2597 11:37:27.744100 974 |3 6 14|[0] xxxxxxxx ooxxxxxo [MSB]
2598 11:37:27.747257 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
2599 11:37:27.750652 976 |3 6 16|[0] xxxxxxxx oooxxxxo [MSB]
2600 11:37:27.753639 977 |3 6 17|[0] xxxxxxxx oooxoxoo [MSB]
2601 11:37:27.760549 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2602 11:37:27.763623 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2603 11:37:27.766940 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2604 11:37:27.770296 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2605 11:37:27.773656 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2606 11:37:27.776686 983 |3 6 23|[0] xooooxoo oooooooo [MSB]
2607 11:37:27.780091 991 |3 6 31|[0] oooooooo ooooooox [MSB]
2608 11:37:27.783204 992 |3 6 32|[0] oooooooo oxooooox [MSB]
2609 11:37:27.786438 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2610 11:37:27.792982 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2611 11:37:27.796471 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2612 11:37:27.799695 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2613 11:37:27.803012 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2614 11:37:27.805989 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2615 11:37:27.809579 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2616 11:37:27.812714 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2617 11:37:27.816180 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2618 11:37:27.819533 1002 |3 6 42|[0] ooxxoooo xxxxxxxx [MSB]
2619 11:37:27.822950 1003 |3 6 43|[0] ooxxoooo xxxxxxxx [MSB]
2620 11:37:27.825967 1004 |3 6 44|[0] ooxxxoox xxxxxxxx [MSB]
2621 11:37:27.832424 1005 |3 6 45|[0] ooxxxoxx xxxxxxxx [MSB]
2622 11:37:27.835775 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
2623 11:37:27.838816 Byte0, DQ PI dly=992, DQM PI dly= 992
2624 11:37:27.842396 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
2625 11:37:27.842506
2626 11:37:27.845447 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
2627 11:37:27.845567
2628 11:37:27.848989 Byte1, DQ PI dly=983, DQM PI dly= 983
2629 11:37:27.855411 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2630 11:37:27.855532
2631 11:37:27.858644 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2632 11:37:27.858724
2633 11:37:27.858787 ==
2634 11:37:27.865270 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2635 11:37:27.868490 fsp= 1, odt_onoff= 1, Byte mode= 0
2636 11:37:27.868600 ==
2637 11:37:27.871596 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2638 11:37:27.871677
2639 11:37:27.874874 Begin, DQ Scan Range 959~1023
2640 11:37:27.878362 Write Rank0 MR14 =0x0
2641 11:37:27.885505
2642 11:37:27.885609 CH=1, VrefRange= 0, VrefLevel = 0
2643 11:37:27.891813 TX Bit0 (985~1000) 16 992, Bit8 (977~990) 14 983,
2644 11:37:27.895030 TX Bit1 (984~1000) 17 992, Bit9 (977~988) 12 982,
2645 11:37:27.901689 TX Bit2 (983~998) 16 990, Bit10 (978~991) 14 984,
2646 11:37:27.904980 TX Bit3 (980~995) 16 987, Bit11 (980~991) 12 985,
2647 11:37:27.908345 TX Bit4 (984~998) 15 991, Bit12 (979~991) 13 985,
2648 11:37:27.914821 TX Bit5 (985~1000) 16 992, Bit13 (980~992) 13 986,
2649 11:37:27.917955 TX Bit6 (985~999) 15 992, Bit14 (979~991) 13 985,
2650 11:37:27.924617 TX Bit7 (985~999) 15 992, Bit15 (975~983) 9 979,
2651 11:37:27.924857
2652 11:37:27.925056 Write Rank0 MR14 =0x2
2653 11:37:27.934057
2654 11:37:27.934168 CH=1, VrefRange= 0, VrefLevel = 2
2655 11:37:27.940761 TX Bit0 (985~1001) 17 993, Bit8 (976~990) 15 983,
2656 11:37:27.943915 TX Bit1 (984~1000) 17 992, Bit9 (976~989) 14 982,
2657 11:37:27.950543 TX Bit2 (982~998) 17 990, Bit10 (978~992) 15 985,
2658 11:37:27.953609 TX Bit3 (979~996) 18 987, Bit11 (979~992) 14 985,
2659 11:37:27.957027 TX Bit4 (984~999) 16 991, Bit12 (979~992) 14 985,
2660 11:37:27.963597 TX Bit5 (985~1000) 16 992, Bit13 (980~993) 14 986,
2661 11:37:27.966671 TX Bit6 (985~999) 15 992, Bit14 (979~991) 13 985,
2662 11:37:27.973301 TX Bit7 (984~999) 16 991, Bit15 (974~984) 11 979,
2663 11:37:27.973386
2664 11:37:27.973452 Write Rank0 MR14 =0x4
2665 11:37:27.983176
2666 11:37:27.983255 CH=1, VrefRange= 0, VrefLevel = 4
2667 11:37:27.989509 TX Bit0 (985~1002) 18 993, Bit8 (976~991) 16 983,
2668 11:37:27.992849 TX Bit1 (984~1001) 18 992, Bit9 (976~989) 14 982,
2669 11:37:27.999439 TX Bit2 (982~999) 18 990, Bit10 (977~992) 16 984,
2670 11:37:28.002548 TX Bit3 (979~996) 18 987, Bit11 (979~992) 14 985,
2671 11:37:28.009225 TX Bit4 (984~1000) 17 992, Bit12 (978~992) 15 985,
2672 11:37:28.012532 TX Bit5 (985~1001) 17 993, Bit13 (979~993) 15 986,
2673 11:37:28.015701 TX Bit6 (984~1000) 17 992, Bit14 (979~992) 14 985,
2674 11:37:28.022426 TX Bit7 (984~1000) 17 992, Bit15 (973~984) 12 978,
2675 11:37:28.022506
2676 11:37:28.022578 Write Rank0 MR14 =0x6
2677 11:37:28.032351
2678 11:37:28.035426 CH=1, VrefRange= 0, VrefLevel = 6
2679 11:37:28.038830 TX Bit0 (985~1002) 18 993, Bit8 (976~991) 16 983,
2680 11:37:28.042000 TX Bit1 (983~1001) 19 992, Bit9 (976~990) 15 983,
2681 11:37:28.048514 TX Bit2 (982~999) 18 990, Bit10 (977~993) 17 985,
2682 11:37:28.051967 TX Bit3 (978~997) 20 987, Bit11 (978~993) 16 985,
2683 11:37:28.058432 TX Bit4 (984~1000) 17 992, Bit12 (978~993) 16 985,
2684 11:37:28.061556 TX Bit5 (985~1002) 18 993, Bit13 (979~994) 16 986,
2685 11:37:28.065004 TX Bit6 (984~1000) 17 992, Bit14 (979~993) 15 986,
2686 11:37:28.071306 TX Bit7 (984~1000) 17 992, Bit15 (972~985) 14 978,
2687 11:37:28.071409
2688 11:37:28.071500 Write Rank0 MR14 =0x8
2689 11:37:28.081688
2690 11:37:28.081767 CH=1, VrefRange= 0, VrefLevel = 8
2691 11:37:28.088139 TX Bit0 (984~1003) 20 993, Bit8 (975~991) 17 983,
2692 11:37:28.091539 TX Bit1 (984~1002) 19 993, Bit9 (975~990) 16 982,
2693 11:37:28.098288 TX Bit2 (981~999) 19 990, Bit10 (977~993) 17 985,
2694 11:37:28.101310 TX Bit3 (978~997) 20 987, Bit11 (978~994) 17 986,
2695 11:37:28.104733 TX Bit4 (983~1001) 19 992, Bit12 (978~993) 16 985,
2696 11:37:28.111094 TX Bit5 (984~1003) 20 993, Bit13 (979~995) 17 987,
2697 11:37:28.114515 TX Bit6 (984~1001) 18 992, Bit14 (978~993) 16 985,
2698 11:37:28.120876 TX Bit7 (983~1000) 18 991, Bit15 (972~986) 15 979,
2699 11:37:28.120957
2700 11:37:28.121023 Write Rank0 MR14 =0xa
2701 11:37:28.131379
2702 11:37:28.134498 CH=1, VrefRange= 0, VrefLevel = 10
2703 11:37:28.137870 TX Bit0 (985~1004) 20 994, Bit8 (975~992) 18 983,
2704 11:37:28.141404 TX Bit1 (983~1002) 20 992, Bit9 (975~991) 17 983,
2705 11:37:28.147783 TX Bit2 (981~1000) 20 990, Bit10 (977~994) 18 985,
2706 11:37:28.151073 TX Bit3 (979~998) 20 988, Bit11 (978~994) 17 986,
2707 11:37:28.157560 TX Bit4 (983~1001) 19 992, Bit12 (978~994) 17 986,
2708 11:37:28.160973 TX Bit5 (985~1004) 20 994, Bit13 (979~995) 17 987,
2709 11:37:28.163913 TX Bit6 (984~1001) 18 992, Bit14 (978~993) 16 985,
2710 11:37:28.170319 TX Bit7 (984~1001) 18 992, Bit15 (972~987) 16 979,
2711 11:37:28.170400
2712 11:37:28.170465 Write Rank0 MR14 =0xc
2713 11:37:28.181324
2714 11:37:28.184249 CH=1, VrefRange= 0, VrefLevel = 12
2715 11:37:28.187703 TX Bit0 (984~1005) 22 994, Bit8 (974~992) 19 983,
2716 11:37:28.190950 TX Bit1 (983~1003) 21 993, Bit9 (975~991) 17 983,
2717 11:37:28.197445 TX Bit2 (980~1001) 22 990, Bit10 (977~995) 19 986,
2718 11:37:28.200584 TX Bit3 (978~998) 21 988, Bit11 (978~994) 17 986,
2719 11:37:28.207551 TX Bit4 (982~1002) 21 992, Bit12 (978~995) 18 986,
2720 11:37:28.210398 TX Bit5 (985~1004) 20 994, Bit13 (978~996) 19 987,
2721 11:37:28.213793 TX Bit6 (983~1002) 20 992, Bit14 (978~994) 17 986,
2722 11:37:28.220243 TX Bit7 (984~1002) 19 993, Bit15 (971~989) 19 980,
2723 11:37:28.220325
2724 11:37:28.220392 Write Rank0 MR14 =0xe
2725 11:37:28.230841
2726 11:37:28.234352 CH=1, VrefRange= 0, VrefLevel = 14
2727 11:37:28.237682 TX Bit0 (984~1005) 22 994, Bit8 (974~992) 19 983,
2728 11:37:28.240741 TX Bit1 (982~1004) 23 993, Bit9 (974~991) 18 982,
2729 11:37:28.247348 TX Bit2 (980~1000) 21 990, Bit10 (976~995) 20 985,
2730 11:37:28.250752 TX Bit3 (978~999) 22 988, Bit11 (978~995) 18 986,
2731 11:37:28.257413 TX Bit4 (982~1003) 22 992, Bit12 (977~995) 19 986,
2732 11:37:28.260424 TX Bit5 (984~1005) 22 994, Bit13 (977~996) 20 986,
2733 11:37:28.263930 TX Bit6 (983~1003) 21 993, Bit14 (977~995) 19 986,
2734 11:37:28.270261 TX Bit7 (984~1002) 19 993, Bit15 (971~989) 19 980,
2735 11:37:28.270459
2736 11:37:28.273540 Write Rank0 MR14 =0x10
2737 11:37:28.281075
2738 11:37:28.284657 CH=1, VrefRange= 0, VrefLevel = 16
2739 11:37:28.287708 TX Bit0 (984~1005) 22 994, Bit8 (973~993) 21 983,
2740 11:37:28.291038 TX Bit1 (982~1005) 24 993, Bit9 (974~991) 18 982,
2741 11:37:28.297373 TX Bit2 (980~1002) 23 991, Bit10 (976~996) 21 986,
2742 11:37:28.300759 TX Bit3 (978~999) 22 988, Bit11 (977~997) 21 987,
2743 11:37:28.307493 TX Bit4 (982~1003) 22 992, Bit12 (977~997) 21 987,
2744 11:37:28.310566 TX Bit5 (984~1005) 22 994, Bit13 (978~997) 20 987,
2745 11:37:28.314006 TX Bit6 (983~1003) 21 993, Bit14 (977~996) 20 986,
2746 11:37:28.320427 TX Bit7 (983~1003) 21 993, Bit15 (970~990) 21 980,
2747 11:37:28.320807
2748 11:37:28.323810 Write Rank0 MR14 =0x12
2749 11:37:28.331450
2750 11:37:28.334626 CH=1, VrefRange= 0, VrefLevel = 18
2751 11:37:28.338010 TX Bit0 (983~1006) 24 994, Bit8 (973~994) 22 983,
2752 11:37:28.341313 TX Bit1 (982~1005) 24 993, Bit9 (974~992) 19 983,
2753 11:37:28.347794 TX Bit2 (979~1002) 24 990, Bit10 (976~997) 22 986,
2754 11:37:28.350821 TX Bit3 (978~999) 22 988, Bit11 (977~997) 21 987,
2755 11:37:28.357363 TX Bit4 (981~1004) 24 992, Bit12 (977~997) 21 987,
2756 11:37:28.361090 TX Bit5 (983~1005) 23 994, Bit13 (978~998) 21 988,
2757 11:37:28.363962 TX Bit6 (982~1004) 23 993, Bit14 (977~996) 20 986,
2758 11:37:28.370781 TX Bit7 (982~1004) 23 993, Bit15 (971~990) 20 980,
2759 11:37:28.371286
2760 11:37:28.371767 Write Rank0 MR14 =0x14
2761 11:37:28.381408
2762 11:37:28.384904 CH=1, VrefRange= 0, VrefLevel = 20
2763 11:37:28.387997 TX Bit0 (983~1006) 24 994, Bit8 (973~994) 22 983,
2764 11:37:28.391162 TX Bit1 (982~1005) 24 993, Bit9 (973~992) 20 982,
2765 11:37:28.398068 TX Bit2 (979~1003) 25 991, Bit10 (976~997) 22 986,
2766 11:37:28.401238 TX Bit3 (978~999) 22 988, Bit11 (977~997) 21 987,
2767 11:37:28.407597 TX Bit4 (981~1005) 25 993, Bit12 (977~997) 21 987,
2768 11:37:28.410863 TX Bit5 (983~1006) 24 994, Bit13 (978~998) 21 988,
2769 11:37:28.414305 TX Bit6 (982~1005) 24 993, Bit14 (977~997) 21 987,
2770 11:37:28.420776 TX Bit7 (982~1004) 23 993, Bit15 (970~990) 21 980,
2771 11:37:28.421236
2772 11:37:28.421666 Write Rank0 MR14 =0x16
2773 11:37:28.431565
2774 11:37:28.434753 CH=1, VrefRange= 0, VrefLevel = 22
2775 11:37:28.438242 TX Bit0 (984~1006) 23 995, Bit8 (972~994) 23 983,
2776 11:37:28.441413 TX Bit1 (982~1005) 24 993, Bit9 (972~992) 21 982,
2777 11:37:28.448120 TX Bit2 (979~1004) 26 991, Bit10 (975~998) 24 986,
2778 11:37:28.451248 TX Bit3 (977~1000) 24 988, Bit11 (977~998) 22 987,
2779 11:37:28.457772 TX Bit4 (981~1005) 25 993, Bit12 (977~998) 22 987,
2780 11:37:28.460813 TX Bit5 (983~1006) 24 994, Bit13 (977~998) 22 987,
2781 11:37:28.464328 TX Bit6 (982~1005) 24 993, Bit14 (976~998) 23 987,
2782 11:37:28.470767 TX Bit7 (981~1005) 25 993, Bit15 (970~991) 22 980,
2783 11:37:28.471385
2784 11:37:28.473917 Write Rank0 MR14 =0x18
2785 11:37:28.481724
2786 11:37:28.485266 CH=1, VrefRange= 0, VrefLevel = 24
2787 11:37:28.488305 TX Bit0 (983~1006) 24 994, Bit8 (972~996) 25 984,
2788 11:37:28.491743 TX Bit1 (981~1005) 25 993, Bit9 (972~993) 22 982,
2789 11:37:28.498075 TX Bit2 (979~1004) 26 991, Bit10 (975~998) 24 986,
2790 11:37:28.501584 TX Bit3 (977~1000) 24 988, Bit11 (977~998) 22 987,
2791 11:37:28.508157 TX Bit4 (980~1005) 26 992, Bit12 (977~998) 22 987,
2792 11:37:28.511499 TX Bit5 (983~1006) 24 994, Bit13 (977~999) 23 988,
2793 11:37:28.514572 TX Bit6 (982~1005) 24 993, Bit14 (976~998) 23 987,
2794 11:37:28.521510 TX Bit7 (981~1005) 25 993, Bit15 (970~991) 22 980,
2795 11:37:28.521881
2796 11:37:28.524163 Write Rank0 MR14 =0x1a
2797 11:37:28.532076
2798 11:37:28.535383 CH=1, VrefRange= 0, VrefLevel = 26
2799 11:37:28.538511 TX Bit0 (983~1006) 24 994, Bit8 (972~997) 26 984,
2800 11:37:28.541585 TX Bit1 (981~1006) 26 993, Bit9 (971~993) 23 982,
2801 11:37:28.548284 TX Bit2 (978~1005) 28 991, Bit10 (974~998) 25 986,
2802 11:37:28.551559 TX Bit3 (977~1000) 24 988, Bit11 (976~999) 24 987,
2803 11:37:28.558041 TX Bit4 (980~1005) 26 992, Bit12 (976~998) 23 987,
2804 11:37:28.561612 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2805 11:37:28.564781 TX Bit6 (981~1006) 26 993, Bit14 (976~998) 23 987,
2806 11:37:28.571099 TX Bit7 (981~1005) 25 993, Bit15 (969~991) 23 980,
2807 11:37:28.571578
2808 11:37:28.574507 Write Rank0 MR14 =0x1c
2809 11:37:28.582301
2810 11:37:28.585432 CH=1, VrefRange= 0, VrefLevel = 28
2811 11:37:28.588624 TX Bit0 (983~1006) 24 994, Bit8 (971~996) 26 983,
2812 11:37:28.592224 TX Bit1 (980~1006) 27 993, Bit9 (971~994) 24 982,
2813 11:37:28.598714 TX Bit2 (978~1005) 28 991, Bit10 (974~999) 26 986,
2814 11:37:28.601971 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2815 11:37:28.608321 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2816 11:37:28.611814 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2817 11:37:28.614757 TX Bit6 (980~1006) 27 993, Bit14 (976~999) 24 987,
2818 11:37:28.621534 TX Bit7 (981~1006) 26 993, Bit15 (969~992) 24 980,
2819 11:37:28.621980
2820 11:37:28.624938 Write Rank0 MR14 =0x1e
2821 11:37:28.632706
2822 11:37:28.635732 CH=1, VrefRange= 0, VrefLevel = 30
2823 11:37:28.639210 TX Bit0 (983~1007) 25 995, Bit8 (971~996) 26 983,
2824 11:37:28.642283 TX Bit1 (980~1006) 27 993, Bit9 (970~994) 25 982,
2825 11:37:28.649060 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2826 11:37:28.652279 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2827 11:37:28.658882 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2828 11:37:28.661565 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2829 11:37:28.665064 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
2830 11:37:28.671579 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
2831 11:37:28.671665
2832 11:37:28.674646 Write Rank0 MR14 =0x20
2833 11:37:28.682694
2834 11:37:28.685836 CH=1, VrefRange= 0, VrefLevel = 32
2835 11:37:28.688966 TX Bit0 (983~1007) 25 995, Bit8 (971~996) 26 983,
2836 11:37:28.692296 TX Bit1 (980~1006) 27 993, Bit9 (970~994) 25 982,
2837 11:37:28.699139 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2838 11:37:28.702237 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2839 11:37:28.708637 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2840 11:37:28.711965 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2841 11:37:28.715285 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
2842 11:37:28.721890 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
2843 11:37:28.721976
2844 11:37:28.725143 Write Rank0 MR14 =0x22
2845 11:37:28.732958
2846 11:37:28.736371 CH=1, VrefRange= 0, VrefLevel = 34
2847 11:37:28.739537 TX Bit0 (983~1007) 25 995, Bit8 (971~996) 26 983,
2848 11:37:28.742720 TX Bit1 (980~1006) 27 993, Bit9 (970~994) 25 982,
2849 11:37:28.749550 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2850 11:37:28.752708 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2851 11:37:28.759011 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2852 11:37:28.762538 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2853 11:37:28.765761 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
2854 11:37:28.772173 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
2855 11:37:28.772282
2856 11:37:28.775305 Write Rank0 MR14 =0x24
2857 11:37:28.783474
2858 11:37:28.786488 CH=1, VrefRange= 0, VrefLevel = 36
2859 11:37:28.789702 TX Bit0 (983~1007) 25 995, Bit8 (971~996) 26 983,
2860 11:37:28.793106 TX Bit1 (980~1006) 27 993, Bit9 (970~994) 25 982,
2861 11:37:28.799766 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2862 11:37:28.802831 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2863 11:37:28.809308 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2864 11:37:28.812588 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2865 11:37:28.815938 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
2866 11:37:28.822665 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
2867 11:37:28.822749
2868 11:37:28.825551 Write Rank0 MR14 =0x26
2869 11:37:28.833684
2870 11:37:28.837077 CH=1, VrefRange= 0, VrefLevel = 38
2871 11:37:28.840352 TX Bit0 (983~1007) 25 995, Bit8 (971~996) 26 983,
2872 11:37:28.843511 TX Bit1 (980~1006) 27 993, Bit9 (970~994) 25 982,
2873 11:37:28.850081 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
2874 11:37:28.853578 TX Bit3 (977~1001) 25 989, Bit11 (976~999) 24 987,
2875 11:37:28.859886 TX Bit4 (980~1006) 27 993, Bit12 (976~999) 24 987,
2876 11:37:28.863374 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
2877 11:37:28.866513 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
2878 11:37:28.873027 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
2879 11:37:28.873112
2880 11:37:28.873177
2881 11:37:28.876482 TX Vref found, early break! 381< 387
2882 11:37:28.879460 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2883 11:37:28.882740 u1DelayCellOfst[0]=7 cells (6 PI)
2884 11:37:28.886090 u1DelayCellOfst[1]=5 cells (4 PI)
2885 11:37:28.889666 u1DelayCellOfst[2]=2 cells (2 PI)
2886 11:37:28.892741 u1DelayCellOfst[3]=0 cells (0 PI)
2887 11:37:28.895876 u1DelayCellOfst[4]=5 cells (4 PI)
2888 11:37:28.899387 u1DelayCellOfst[5]=6 cells (5 PI)
2889 11:37:28.902617 u1DelayCellOfst[6]=5 cells (4 PI)
2890 11:37:28.905470 u1DelayCellOfst[7]=5 cells (4 PI)
2891 11:37:28.908980 Byte0, DQ PI dly=989, DQM PI dly= 992
2892 11:37:28.912306 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2893 11:37:28.912392
2894 11:37:28.915377 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2895 11:37:28.918993
2896 11:37:28.919076 u1DelayCellOfst[8]=3 cells (3 PI)
2897 11:37:28.922020 u1DelayCellOfst[9]=2 cells (2 PI)
2898 11:37:28.925315 u1DelayCellOfst[10]=9 cells (7 PI)
2899 11:37:28.928595 u1DelayCellOfst[11]=9 cells (7 PI)
2900 11:37:28.931963 u1DelayCellOfst[12]=9 cells (7 PI)
2901 11:37:28.935425 u1DelayCellOfst[13]=9 cells (7 PI)
2902 11:37:28.938650 u1DelayCellOfst[14]=9 cells (7 PI)
2903 11:37:28.941798 u1DelayCellOfst[15]=0 cells (0 PI)
2904 11:37:28.944946 Byte1, DQ PI dly=980, DQM PI dly= 983
2905 11:37:28.948231 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2906 11:37:28.948342
2907 11:37:28.954670 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2908 11:37:28.954792
2909 11:37:28.954899 Write Rank0 MR14 =0x1e
2910 11:37:28.958310
2911 11:37:28.958396 Final TX Range 0 Vref 30
2912 11:37:28.958462
2913 11:37:28.964853 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2914 11:37:28.964955
2915 11:37:28.971154 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2916 11:37:28.977797 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2917 11:37:28.987742 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2918 11:37:28.990988 wait MRW command Rank0 MR3 =0xb0 fired (1)
2919 11:37:28.991209 Write Rank0 MR3 =0xb0
2920 11:37:28.994130 DramC Write-DBI on
2921 11:37:28.994366 ==
2922 11:37:28.997622 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2923 11:37:29.000798 fsp= 1, odt_onoff= 1, Byte mode= 0
2924 11:37:29.000995 ==
2925 11:37:29.007451 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2926 11:37:29.007917
2927 11:37:29.010712 Begin, DQ Scan Range 703~767
2928 11:37:29.011103
2929 11:37:29.011388
2930 11:37:29.011728 TX Vref Scan disable
2931 11:37:29.014151 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2932 11:37:29.017288 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2933 11:37:29.024068 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2934 11:37:29.027168 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2935 11:37:29.030654 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2936 11:37:29.033550 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2937 11:37:29.036958 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2938 11:37:29.040556 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2939 11:37:29.043394 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2940 11:37:29.046634 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2941 11:37:29.050536 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2942 11:37:29.053322 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2943 11:37:29.056618 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2944 11:37:29.059791 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2945 11:37:29.063101 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2946 11:37:29.066463 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2947 11:37:29.069572 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2948 11:37:29.073211 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2949 11:37:29.079732 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2950 11:37:29.082819 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2951 11:37:29.086056 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2952 11:37:29.093221 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2953 11:37:29.096133 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2954 11:37:29.099765 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2955 11:37:29.102665 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2956 11:37:29.105971 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2957 11:37:29.109482 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2958 11:37:29.112707 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2959 11:37:29.115777 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2960 11:37:29.119199 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2961 11:37:29.122444 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2962 11:37:29.125751 Byte0, DQ PI dly=737, DQM PI dly= 737
2963 11:37:29.132045 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
2964 11:37:29.132484
2965 11:37:29.135323 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
2966 11:37:29.135820
2967 11:37:29.138795 Byte1, DQ PI dly=728, DQM PI dly= 728
2968 11:37:29.142174 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2969 11:37:29.142558
2970 11:37:29.148707 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2971 11:37:29.149101
2972 11:37:29.154970 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2973 11:37:29.161698 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2974 11:37:29.168289 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2975 11:37:29.171845 Write Rank0 MR3 =0x30
2976 11:37:29.172315 DramC Write-DBI off
2977 11:37:29.172642
2978 11:37:29.174822 [DATLAT]
2979 11:37:29.177964 Freq=1600, CH1 RK0, use_rxtx_scan=0
2980 11:37:29.178456
2981 11:37:29.178874 DATLAT Default: 0xf
2982 11:37:29.181127 7, 0xFFFF, sum=0
2983 11:37:29.181591 8, 0xFFFF, sum=0
2984 11:37:29.184804 9, 0xFFFF, sum=0
2985 11:37:29.185159 10, 0xFFFF, sum=0
2986 11:37:29.188197 11, 0xFFFF, sum=0
2987 11:37:29.188685 12, 0xFFFF, sum=0
2988 11:37:29.191122 13, 0xFFFF, sum=0
2989 11:37:29.191514 14, 0x0, sum=1
2990 11:37:29.191804 15, 0x0, sum=2
2991 11:37:29.194131 16, 0x0, sum=3
2992 11:37:29.194598 17, 0x0, sum=4
2993 11:37:29.201054 pattern=2 first_step=14 total pass=5 best_step=16
2994 11:37:29.201505 ==
2995 11:37:29.204147 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2996 11:37:29.207541 fsp= 1, odt_onoff= 1, Byte mode= 0
2997 11:37:29.207894 ==
2998 11:37:29.214045 Start DQ dly to find pass range UseTestEngine =1
2999 11:37:29.217102 x-axis: bit #, y-axis: DQ dly (-127~63)
3000 11:37:29.217618 RX Vref Scan = 1
3001 11:37:29.325189
3002 11:37:29.325579 RX Vref found, early break!
3003 11:37:29.325858
3004 11:37:29.331551 Final RX Vref 11, apply to both rank0 and 1
3005 11:37:29.331915 ==
3006 11:37:29.334868 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3007 11:37:29.338188 fsp= 1, odt_onoff= 1, Byte mode= 0
3008 11:37:29.338541 ==
3009 11:37:29.341215 DQS Delay:
3010 11:37:29.341568 DQS0 = 0, DQS1 = 0
3011 11:37:29.341841 DQM Delay:
3012 11:37:29.344435 DQM0 = 20, DQM1 = 18
3013 11:37:29.344787 DQ Delay:
3014 11:37:29.347895 DQ0 =21, DQ1 =21, DQ2 =17, DQ3 =16
3015 11:37:29.351398 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3016 11:37:29.354519 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =20
3017 11:37:29.357839 DQ12 =21, DQ13 =21, DQ14 =21, DQ15 =13
3018 11:37:29.358240
3019 11:37:29.358565
3020 11:37:29.358899
3021 11:37:29.360931 [DramC_TX_OE_Calibration] TA2
3022 11:37:29.364420 Original DQ_B0 (3 6) =30, OEN = 27
3023 11:37:29.367282 Original DQ_B1 (3 6) =30, OEN = 27
3024 11:37:29.370746 23, 0x0, End_B0=23 End_B1=23
3025 11:37:29.373983 24, 0x0, End_B0=24 End_B1=24
3026 11:37:29.374381 25, 0x0, End_B0=25 End_B1=25
3027 11:37:29.377140 26, 0x0, End_B0=26 End_B1=26
3028 11:37:29.380696 27, 0x0, End_B0=27 End_B1=27
3029 11:37:29.383738 28, 0x0, End_B0=28 End_B1=28
3030 11:37:29.387209 29, 0x0, End_B0=29 End_B1=29
3031 11:37:29.387664 30, 0x0, End_B0=30 End_B1=30
3032 11:37:29.390325 31, 0xFFFF, End_B0=30 End_B1=30
3033 11:37:29.396893 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3034 11:37:29.403357 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3035 11:37:29.403755
3036 11:37:29.404034
3037 11:37:29.404290 Write Rank0 MR23 =0x3f
3038 11:37:29.407289 [DQSOSC]
3039 11:37:29.413636 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3040 11:37:29.419789 CH1_RK0: MR19=0x202, MR18=0xB7B7, DQSOSC=453, MR23=63, INC=11, DEC=17
3041 11:37:29.423116 Write Rank0 MR23 =0x3f
3042 11:37:29.423526 [DQSOSC]
3043 11:37:29.429884 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3044 11:37:29.433206 CH1 RK0: MR19=202, MR18=B7B7
3045 11:37:29.436238 [RankSwap] Rank num 2, (Multi 1), Rank 1
3046 11:37:29.439593 Write Rank0 MR2 =0xad
3047 11:37:29.440040 [Write Leveling]
3048 11:37:29.442664 delay byte0 byte1 byte2 byte3
3049 11:37:29.443062
3050 11:37:29.446242 10 0 0
3051 11:37:29.446696 11 0 0
3052 11:37:29.449480 12 0 0
3053 11:37:29.449876 13 0 0
3054 11:37:29.450161 14 0 0
3055 11:37:29.452654 15 0 0
3056 11:37:29.453196 16 0 0
3057 11:37:29.456169 17 0 0
3058 11:37:29.456533 18 0 0
3059 11:37:29.456814 19 0 0
3060 11:37:29.459223 20 0 0
3061 11:37:29.459615 21 0 0
3062 11:37:29.462569 22 0 0
3063 11:37:29.462931 23 0 0
3064 11:37:29.465706 24 0 0
3065 11:37:29.466066 25 0 0
3066 11:37:29.466346 26 0 0
3067 11:37:29.468914 27 0 0
3068 11:37:29.469273 28 0 ff
3069 11:37:29.472556 29 0 ff
3070 11:37:29.472916 30 0 ff
3071 11:37:29.475736 31 0 ff
3072 11:37:29.476097 32 0 ff
3073 11:37:29.479144 33 0 ff
3074 11:37:29.479540 34 0 ff
3075 11:37:29.479827 35 ff ff
3076 11:37:29.482171 36 0 ff
3077 11:37:29.482536 37 ff ff
3078 11:37:29.485221 38 ff ff
3079 11:37:29.485584 39 ff ff
3080 11:37:29.488687 40 ff ff
3081 11:37:29.489046 41 ff ff
3082 11:37:29.491789 42 ff ff
3083 11:37:29.492149 43 ff ff
3084 11:37:29.495225 pass bytecount = 0xff (0xff: all bytes pass)
3085 11:37:29.495653
3086 11:37:29.498286 DQS0 dly: 37
3087 11:37:29.498650 DQS1 dly: 28
3088 11:37:29.501831 Write Rank0 MR2 =0x2d
3089 11:37:29.504984 [RankSwap] Rank num 2, (Multi 1), Rank 0
3090 11:37:29.508514 Write Rank1 MR1 =0xd6
3091 11:37:29.509088 [Gating]
3092 11:37:29.509509 ==
3093 11:37:29.511438 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3094 11:37:29.514922 fsp= 1, odt_onoff= 1, Byte mode= 0
3095 11:37:29.515276 ==
3096 11:37:29.521325 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3097 11:37:29.524489 3 1 4 |2c2b 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
3098 11:37:29.527897 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3099 11:37:29.534350 3 1 12 |2c2b 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
3100 11:37:29.537620 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
3101 11:37:29.540927 3 1 20 |2c2b 909 |(11 11)(1 1) |(1 0)(1 1)| 0
3102 11:37:29.547380 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
3103 11:37:29.550786 3 1 28 |2c2b 3535 |(11 11)(0 0) |(1 0)(1 1)| 0
3104 11:37:29.554110 [Byte 1] Lead/lag falling Transition (3, 1, 28)
3105 11:37:29.560525 3 2 0 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 1)| 0
3106 11:37:29.563950 [Byte 1] Lead/lag Transition tap number (2)
3107 11:37:29.566854 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
3108 11:37:29.570241 3 2 8 |2c2b 1d1d |(11 11)(11 11) |(1 0)(0 1)| 0
3109 11:37:29.576876 3 2 12 |2c2b 505 |(11 11)(11 11) |(1 0)(0 1)| 0
3110 11:37:29.580211 3 2 16 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
3111 11:37:29.583235 3 2 20 |201 3434 |(11 1)(11 11) |(0 0)(0 1)| 0
3112 11:37:29.590127 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
3113 11:37:29.593229 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3114 11:37:29.596756 3 3 0 |3534 3e3d |(11 11)(11 11) |(0 0)(1 1)| 0
3115 11:37:29.603083 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3116 11:37:29.606047 3 3 8 |3534 3c3b |(11 11)(11 11) |(0 0)(1 1)| 0
3117 11:37:29.609618 [Byte 1] Lead/lag Transition tap number (1)
3118 11:37:29.616133 3 3 12 |3534 1a19 |(11 11)(11 11) |(1 1)(0 0)| 0
3119 11:37:29.619498 3 3 16 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3120 11:37:29.622607 3 3 20 |3534 3c3c |(11 11)(11 11) |(1 1)(0 0)| 0
3121 11:37:29.629309 3 3 24 |3534 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
3122 11:37:29.632486 [Byte 0] Lead/lag falling Transition (3, 3, 24)
3123 11:37:29.635860 3 3 28 |3534 f0f |(11 11)(11 11) |(0 1)(1 1)| 0
3124 11:37:29.642386 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3125 11:37:29.645401 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3126 11:37:29.648846 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3127 11:37:29.655319 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3128 11:37:29.658810 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3129 11:37:29.661969 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3130 11:37:29.668538 3 4 24 |3d3d 1e1e |(11 11)(11 11) |(1 1)(1 1)| 0
3131 11:37:29.671548 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3132 11:37:29.674991 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3133 11:37:29.678425 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3134 11:37:29.684814 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3135 11:37:29.688222 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3136 11:37:29.691314 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3137 11:37:29.697863 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3138 11:37:29.700995 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3139 11:37:29.707416 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3140 11:37:29.710860 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3141 11:37:29.714266 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3142 11:37:29.717251 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3143 11:37:29.723725 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3144 11:37:29.727148 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3145 11:37:29.730376 [Byte 0] Lead/lag Transition tap number (2)
3146 11:37:29.737019 [Byte 1] Lead/lag falling Transition (3, 6, 12)
3147 11:37:29.739941 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3148 11:37:29.743492 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3149 11:37:29.746905 [Byte 1] Lead/lag Transition tap number (3)
3150 11:37:29.753106 3 6 24 |1a1a 2c2c |(11 11)(11 11) |(0 0)(0 0)| 0
3151 11:37:29.756428 3 6 28 |4646 4646 |(0 0)(10 0) |(0 0)(0 0)| 0
3152 11:37:29.759866 [Byte 0]First pass (3, 6, 28)
3153 11:37:29.763124 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3154 11:37:29.766179 [Byte 1]First pass (3, 7, 0)
3155 11:37:29.769381 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3156 11:37:29.772820 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3157 11:37:29.776097 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3158 11:37:29.782795 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3159 11:37:29.785913 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3160 11:37:29.789388 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3161 11:37:29.792587 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3162 11:37:29.799042 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3163 11:37:29.802310 All bytes gating window > 1UI, Early break!
3164 11:37:29.802417
3165 11:37:29.805760 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3166 11:37:29.805864
3167 11:37:29.808833 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
3168 11:37:29.808932
3169 11:37:29.809023
3170 11:37:29.809110
3171 11:37:29.812264 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3172 11:37:29.815347
3173 11:37:29.818708 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
3174 11:37:29.818811
3175 11:37:29.818905
3176 11:37:29.818998 Write Rank1 MR1 =0x56
3177 11:37:29.819086
3178 11:37:29.822150 best RODT dly(2T, 0.5T) = (2, 3)
3179 11:37:29.822249
3180 11:37:29.825239 best RODT dly(2T, 0.5T) = (2, 3)
3181 11:37:29.825341 ==
3182 11:37:29.831913 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3183 11:37:29.835020 fsp= 1, odt_onoff= 1, Byte mode= 0
3184 11:37:29.835123 ==
3185 11:37:29.838443 Start DQ dly to find pass range UseTestEngine =0
3186 11:37:29.841511 x-axis: bit #, y-axis: DQ dly (-127~63)
3187 11:37:29.844955 RX Vref Scan = 0
3188 11:37:29.848105 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3189 11:37:29.851317 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3190 11:37:29.854660 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3191 11:37:29.854757 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3192 11:37:29.857909 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3193 11:37:29.861077 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3194 11:37:29.864521 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3195 11:37:29.867925 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3196 11:37:29.871072 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3197 11:37:29.874429 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3198 11:37:29.877605 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3199 11:37:29.880862 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3200 11:37:29.880946 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3201 11:37:29.884147 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3202 11:37:29.887240 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3203 11:37:29.890797 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3204 11:37:29.893888 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3205 11:37:29.897338 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3206 11:37:29.900383 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3207 11:37:29.903958 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3208 11:37:29.907225 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3209 11:37:29.907347 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3210 11:37:29.910294 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3211 11:37:29.913728 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3212 11:37:29.916931 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3213 11:37:29.920404 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3214 11:37:29.923376 0, [0] xxxoxxxx ooxxxxxo [MSB]
3215 11:37:29.926791 1, [0] xxxoxxxx ooxxxxxo [MSB]
3216 11:37:29.926876 2, [0] xxxoxxxx ooxxoxxo [MSB]
3217 11:37:29.930167 3, [0] xxooxxxo oooxoxxo [MSB]
3218 11:37:29.933362 4, [0] oooooxxo oooooooo [MSB]
3219 11:37:29.936561 32, [0] oooooooo ooooooox [MSB]
3220 11:37:29.940016 33, [0] oooooooo ooooooox [MSB]
3221 11:37:29.942910 34, [0] oooooooo oxooooox [MSB]
3222 11:37:29.946245 35, [0] ooxxoooo oxooooox [MSB]
3223 11:37:29.946349 36, [0] ooxxoooo xxooooox [MSB]
3224 11:37:29.949705 37, [0] ooxxoooo xxooooox [MSB]
3225 11:37:29.953067 38, [0] ooxxoooo xxooooox [MSB]
3226 11:37:29.956107 39, [0] oxxxooox xxooooox [MSB]
3227 11:37:29.959312 40, [0] oxxxooox xxxxooox [MSB]
3228 11:37:29.962785 41, [0] xxxxxoxx xxxxxoox [MSB]
3229 11:37:29.966034 42, [0] xxxxxoxx xxxxxxxx [MSB]
3230 11:37:29.969380 43, [0] xxxxxxxx xxxxxxxx [MSB]
3231 11:37:29.972341 iDelay=43, Bit 0, Center 22 (4 ~ 40) 37
3232 11:37:29.975895 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
3233 11:37:29.978971 iDelay=43, Bit 2, Center 18 (3 ~ 34) 32
3234 11:37:29.982471 iDelay=43, Bit 3, Center 16 (-2 ~ 34) 37
3235 11:37:29.985619 iDelay=43, Bit 4, Center 22 (4 ~ 40) 37
3236 11:37:29.989073 iDelay=43, Bit 5, Center 23 (5 ~ 42) 38
3237 11:37:29.992402 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
3238 11:37:29.995358 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
3239 11:37:29.998694 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
3240 11:37:30.001785 iDelay=43, Bit 9, Center 15 (-2 ~ 33) 36
3241 11:37:30.008527 iDelay=43, Bit 10, Center 21 (3 ~ 39) 37
3242 11:37:30.011744 iDelay=43, Bit 11, Center 21 (4 ~ 39) 36
3243 11:37:30.014866 iDelay=43, Bit 12, Center 21 (2 ~ 40) 39
3244 11:37:30.018353 iDelay=43, Bit 13, Center 22 (4 ~ 41) 38
3245 11:37:30.021415 iDelay=43, Bit 14, Center 22 (4 ~ 41) 38
3246 11:37:30.024767 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
3247 11:37:30.024868 ==
3248 11:37:30.031475 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3249 11:37:30.034492 fsp= 1, odt_onoff= 1, Byte mode= 0
3250 11:37:30.034596 ==
3251 11:37:30.034688 DQS Delay:
3252 11:37:30.038032 DQS0 = 0, DQS1 = 0
3253 11:37:30.038134 DQM Delay:
3254 11:37:30.041164 DQM0 = 20, DQM1 = 19
3255 11:37:30.041263 DQ Delay:
3256 11:37:30.044346 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3257 11:37:30.047629 DQ4 =22, DQ5 =23, DQ6 =22, DQ7 =20
3258 11:37:30.051041 DQ8 =17, DQ9 =15, DQ10 =21, DQ11 =21
3259 11:37:30.054547 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =13
3260 11:37:30.054635
3261 11:37:30.054699
3262 11:37:30.054759 DramC Write-DBI off
3263 11:37:30.057671 ==
3264 11:37:30.060790 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3265 11:37:30.064408 fsp= 1, odt_onoff= 1, Byte mode= 0
3266 11:37:30.064492 ==
3267 11:37:30.067393 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3268 11:37:30.067484
3269 11:37:30.070630 Begin, DQ Scan Range 924~1180
3270 11:37:30.070713
3271 11:37:30.070777
3272 11:37:30.073988 TX Vref Scan disable
3273 11:37:30.077387 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3274 11:37:30.080583 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3275 11:37:30.083623 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3276 11:37:30.086982 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3277 11:37:30.090391 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3278 11:37:30.093679 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3279 11:37:30.100111 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3280 11:37:30.103417 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3281 11:37:30.106687 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3282 11:37:30.109760 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3283 11:37:30.112955 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3284 11:37:30.116383 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3285 11:37:30.119765 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3286 11:37:30.122907 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3287 11:37:30.126263 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3288 11:37:30.129283 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3289 11:37:30.132528 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3290 11:37:30.135941 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3291 11:37:30.139306 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3292 11:37:30.145976 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3293 11:37:30.149064 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3294 11:37:30.152388 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3295 11:37:30.155380 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3296 11:37:30.158853 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3297 11:37:30.162044 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3298 11:37:30.165475 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3299 11:37:30.168562 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3300 11:37:30.172205 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3301 11:37:30.175259 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3302 11:37:30.178576 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3303 11:37:30.181578 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3304 11:37:30.188348 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3305 11:37:30.191459 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3306 11:37:30.194856 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3307 11:37:30.198325 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3308 11:37:30.201360 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3309 11:37:30.204535 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3310 11:37:30.207935 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3311 11:37:30.211273 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3312 11:37:30.214771 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3313 11:37:30.217856 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3314 11:37:30.221174 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3315 11:37:30.224379 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3316 11:37:30.227752 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3317 11:37:30.230875 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3318 11:37:30.234392 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3319 11:37:30.237419 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3320 11:37:30.244115 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3321 11:37:30.247413 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3322 11:37:30.250430 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3323 11:37:30.253979 974 |3 6 14|[0] xxxxxxxx xoxxxxxo [MSB]
3324 11:37:30.257170 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3325 11:37:30.260445 976 |3 6 16|[0] xxxxxxxx oooxxxxo [MSB]
3326 11:37:30.263491 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3327 11:37:30.267109 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3328 11:37:30.270017 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3329 11:37:30.273599 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3330 11:37:30.276684 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3331 11:37:30.279924 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3332 11:37:30.283217 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3333 11:37:30.290979 991 |3 6 31|[0] oooooooo ooooooox [MSB]
3334 11:37:30.294166 992 |3 6 32|[0] oooooooo oxooooox [MSB]
3335 11:37:30.297502 993 |3 6 33|[0] oooooooo xxooooox [MSB]
3336 11:37:30.300783 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3337 11:37:30.304181 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3338 11:37:30.307061 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3339 11:37:30.310210 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3340 11:37:30.313710 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3341 11:37:30.317053 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3342 11:37:30.320238 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3343 11:37:30.323345 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3344 11:37:30.330082 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3345 11:37:30.333519 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
3346 11:37:30.336632 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
3347 11:37:30.339691 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
3348 11:37:30.343080 1006 |3 6 46|[0] xxxxxoxx xxxxxxxx [MSB]
3349 11:37:30.346306 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3350 11:37:30.349658 Byte0, DQ PI dly=993, DQM PI dly= 993
3351 11:37:30.353278 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
3352 11:37:30.353383
3353 11:37:30.359658 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
3354 11:37:30.359753
3355 11:37:30.362832 Byte1, DQ PI dly=983, DQM PI dly= 983
3356 11:37:30.365989 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3357 11:37:30.366080
3358 11:37:30.372458 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3359 11:37:30.372551
3360 11:37:30.372636 ==
3361 11:37:30.375915 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3362 11:37:30.379057 fsp= 1, odt_onoff= 1, Byte mode= 0
3363 11:37:30.379146 ==
3364 11:37:30.385577 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3365 11:37:30.385677
3366 11:37:30.385763 Begin, DQ Scan Range 959~1023
3367 11:37:30.388912 Write Rank1 MR14 =0x0
3368 11:37:30.397864
3369 11:37:30.397975 CH=1, VrefRange= 0, VrefLevel = 0
3370 11:37:30.404444 TX Bit0 (986~1002) 17 994, Bit8 (978~988) 11 983,
3371 11:37:30.407645 TX Bit1 (985~1000) 16 992, Bit9 (976~987) 12 981,
3372 11:37:30.414166 TX Bit2 (984~999) 16 991, Bit10 (977~992) 16 984,
3373 11:37:30.417351 TX Bit3 (982~994) 13 988, Bit11 (978~992) 15 985,
3374 11:37:30.420743 TX Bit4 (985~1000) 16 992, Bit12 (980~991) 12 985,
3375 11:37:30.427142 TX Bit5 (986~1002) 17 994, Bit13 (979~993) 15 986,
3376 11:37:30.430441 TX Bit6 (986~1000) 15 993, Bit14 (979~991) 13 985,
3377 11:37:30.437063 TX Bit7 (985~999) 15 992, Bit15 (974~984) 11 979,
3378 11:37:30.437154
3379 11:37:30.437247 Write Rank1 MR14 =0x2
3380 11:37:30.446866
3381 11:37:30.446952 CH=1, VrefRange= 0, VrefLevel = 2
3382 11:37:30.453732 TX Bit0 (986~1003) 18 994, Bit8 (977~989) 13 983,
3383 11:37:30.457070 TX Bit1 (985~1001) 17 993, Bit9 (976~988) 13 982,
3384 11:37:30.463592 TX Bit2 (984~999) 16 991, Bit10 (978~993) 16 985,
3385 11:37:30.466731 TX Bit3 (981~996) 16 988, Bit11 (978~993) 16 985,
3386 11:37:30.470154 TX Bit4 (985~1001) 17 993, Bit12 (979~991) 13 985,
3387 11:37:30.476740 TX Bit5 (986~1003) 18 994, Bit13 (979~993) 15 986,
3388 11:37:30.479773 TX Bit6 (985~1001) 17 993, Bit14 (978~991) 14 984,
3389 11:37:30.486394 TX Bit7 (985~999) 15 992, Bit15 (973~985) 13 979,
3390 11:37:30.486482
3391 11:37:30.486568 Write Rank1 MR14 =0x4
3392 11:37:30.496661
3393 11:37:30.496748 CH=1, VrefRange= 0, VrefLevel = 4
3394 11:37:30.503156 TX Bit0 (986~1004) 19 995, Bit8 (977~990) 14 983,
3395 11:37:30.506523 TX Bit1 (985~1001) 17 993, Bit9 (975~989) 15 982,
3396 11:37:30.512867 TX Bit2 (983~999) 17 991, Bit10 (977~994) 18 985,
3397 11:37:30.516066 TX Bit3 (981~997) 17 989, Bit11 (978~993) 16 985,
3398 11:37:30.519661 TX Bit4 (985~1002) 18 993, Bit12 (979~991) 13 985,
3399 11:37:30.526119 TX Bit5 (985~1004) 20 994, Bit13 (979~994) 16 986,
3400 11:37:30.529301 TX Bit6 (985~1002) 18 993, Bit14 (978~992) 15 985,
3401 11:37:30.535936 TX Bit7 (985~1000) 16 992, Bit15 (972~986) 15 979,
3402 11:37:30.536024
3403 11:37:30.536109 Write Rank1 MR14 =0x6
3404 11:37:30.546542
3405 11:37:30.546629 CH=1, VrefRange= 0, VrefLevel = 6
3406 11:37:30.552917 TX Bit0 (986~1005) 20 995, Bit8 (976~990) 15 983,
3407 11:37:30.556181 TX Bit1 (985~1002) 18 993, Bit9 (975~989) 15 982,
3408 11:37:30.562600 TX Bit2 (983~1000) 18 991, Bit10 (977~994) 18 985,
3409 11:37:30.566202 TX Bit3 (981~997) 17 989, Bit11 (978~994) 17 986,
3410 11:37:30.572744 TX Bit4 (985~1003) 19 994, Bit12 (978~992) 15 985,
3411 11:37:30.575976 TX Bit5 (985~1004) 20 994, Bit13 (978~994) 17 986,
3412 11:37:30.579124 TX Bit6 (985~1002) 18 993, Bit14 (978~992) 15 985,
3413 11:37:30.585718 TX Bit7 (985~1001) 17 993, Bit15 (972~986) 15 979,
3414 11:37:30.585804
3415 11:37:30.585869 Write Rank1 MR14 =0x8
3416 11:37:30.596270
3417 11:37:30.596391 CH=1, VrefRange= 0, VrefLevel = 8
3418 11:37:30.602872 TX Bit0 (986~1005) 20 995, Bit8 (976~990) 15 983,
3419 11:37:30.606012 TX Bit1 (985~1002) 18 993, Bit9 (975~989) 15 982,
3420 11:37:30.612586 TX Bit2 (983~1000) 18 991, Bit10 (977~994) 18 985,
3421 11:37:30.615981 TX Bit3 (981~997) 17 989, Bit11 (978~994) 17 986,
3422 11:37:30.622577 TX Bit4 (985~1003) 19 994, Bit12 (978~992) 15 985,
3423 11:37:30.625658 TX Bit5 (985~1004) 20 994, Bit13 (978~994) 17 986,
3424 11:37:30.628805 TX Bit6 (985~1002) 18 993, Bit14 (978~992) 15 985,
3425 11:37:30.635432 TX Bit7 (985~1001) 17 993, Bit15 (972~986) 15 979,
3426 11:37:30.635531
3427 11:37:30.635596 Write Rank1 MR14 =0xa
3428 11:37:30.646336
3429 11:37:30.649427 CH=1, VrefRange= 0, VrefLevel = 10
3430 11:37:30.652777 TX Bit0 (985~1006) 22 995, Bit8 (975~991) 17 983,
3431 11:37:30.656077 TX Bit1 (984~1004) 21 994, Bit9 (974~990) 17 982,
3432 11:37:30.662612 TX Bit2 (983~1001) 19 992, Bit10 (976~996) 21 986,
3433 11:37:30.665862 TX Bit3 (979~998) 20 988, Bit11 (978~996) 19 987,
3434 11:37:30.672193 TX Bit4 (984~1004) 21 994, Bit12 (977~993) 17 985,
3435 11:37:30.675668 TX Bit5 (985~1005) 21 995, Bit13 (977~996) 20 986,
3436 11:37:30.678785 TX Bit6 (985~1004) 20 994, Bit14 (978~993) 16 985,
3437 11:37:30.685470 TX Bit7 (984~1002) 19 993, Bit15 (971~989) 19 980,
3438 11:37:30.685565
3439 11:37:30.688634 Write Rank1 MR14 =0xc
3440 11:37:30.696495
3441 11:37:30.699429 CH=1, VrefRange= 0, VrefLevel = 12
3442 11:37:30.702908 TX Bit0 (985~1006) 22 995, Bit8 (976~991) 16 983,
3443 11:37:30.706372 TX Bit1 (984~1005) 22 994, Bit9 (973~991) 19 982,
3444 11:37:30.712773 TX Bit2 (982~1002) 21 992, Bit10 (976~997) 22 986,
3445 11:37:30.715963 TX Bit3 (979~998) 20 988, Bit11 (977~997) 21 987,
3446 11:37:30.722324 TX Bit4 (983~1005) 23 994, Bit12 (977~993) 17 985,
3447 11:37:30.725660 TX Bit5 (985~1006) 22 995, Bit13 (977~997) 21 987,
3448 11:37:30.728959 TX Bit6 (984~1005) 22 994, Bit14 (977~994) 18 985,
3449 11:37:30.735562 TX Bit7 (984~1003) 20 993, Bit15 (971~989) 19 980,
3450 11:37:30.735650
3451 11:37:30.735734 Write Rank1 MR14 =0xe
3452 11:37:30.746548
3453 11:37:30.749611 CH=1, VrefRange= 0, VrefLevel = 14
3454 11:37:30.753058 TX Bit0 (985~1006) 22 995, Bit8 (976~991) 16 983,
3455 11:37:30.756095 TX Bit1 (984~1005) 22 994, Bit9 (973~991) 19 982,
3456 11:37:30.762809 TX Bit2 (981~1003) 23 992, Bit10 (976~998) 23 987,
3457 11:37:30.766237 TX Bit3 (979~999) 21 989, Bit11 (977~997) 21 987,
3458 11:37:30.772459 TX Bit4 (983~1005) 23 994, Bit12 (977~994) 18 985,
3459 11:37:30.775863 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
3460 11:37:30.779031 TX Bit6 (984~1005) 22 994, Bit14 (977~995) 19 986,
3461 11:37:30.785741 TX Bit7 (984~1004) 21 994, Bit15 (970~990) 21 980,
3462 11:37:30.785830
3463 11:37:30.785915 Write Rank1 MR14 =0x10
3464 11:37:30.796815
3465 11:37:30.799988 CH=1, VrefRange= 0, VrefLevel = 16
3466 11:37:30.803312 TX Bit0 (985~1006) 22 995, Bit8 (975~992) 18 983,
3467 11:37:30.806685 TX Bit1 (984~1005) 22 994, Bit9 (972~991) 20 981,
3468 11:37:30.812948 TX Bit2 (981~1004) 24 992, Bit10 (976~998) 23 987,
3469 11:37:30.816431 TX Bit3 (978~999) 22 988, Bit11 (977~998) 22 987,
3470 11:37:30.822850 TX Bit4 (983~1005) 23 994, Bit12 (977~995) 19 986,
3471 11:37:30.826288 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
3472 11:37:30.829288 TX Bit6 (984~1005) 22 994, Bit14 (977~996) 20 986,
3473 11:37:30.836048 TX Bit7 (984~1005) 22 994, Bit15 (970~990) 21 980,
3474 11:37:30.836136
3475 11:37:30.836222 Write Rank1 MR14 =0x12
3476 11:37:30.847061
3477 11:37:30.850227 CH=1, VrefRange= 0, VrefLevel = 18
3478 11:37:30.853560 TX Bit0 (985~1007) 23 996, Bit8 (974~992) 19 983,
3479 11:37:30.856886 TX Bit1 (983~1005) 23 994, Bit9 (972~992) 21 982,
3480 11:37:30.863143 TX Bit2 (981~1004) 24 992, Bit10 (975~998) 24 986,
3481 11:37:30.866705 TX Bit3 (978~1000) 23 989, Bit11 (976~998) 23 987,
3482 11:37:30.873408 TX Bit4 (983~1006) 24 994, Bit12 (977~996) 20 986,
3483 11:37:30.876226 TX Bit5 (984~1006) 23 995, Bit13 (977~998) 22 987,
3484 11:37:30.879725 TX Bit6 (983~1006) 24 994, Bit14 (977~997) 21 987,
3485 11:37:30.886210 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
3486 11:37:30.886324
3487 11:37:30.889499 Write Rank1 MR14 =0x14
3488 11:37:30.897447
3489 11:37:30.900533 CH=1, VrefRange= 0, VrefLevel = 20
3490 11:37:30.904274 TX Bit0 (985~1007) 23 996, Bit8 (973~992) 20 982,
3491 11:37:30.907210 TX Bit1 (983~1006) 24 994, Bit9 (972~992) 21 982,
3492 11:37:30.913946 TX Bit2 (981~1005) 25 993, Bit10 (975~998) 24 986,
3493 11:37:30.917083 TX Bit3 (979~1000) 22 989, Bit11 (976~999) 24 987,
3494 11:37:30.923530 TX Bit4 (983~1006) 24 994, Bit12 (977~997) 21 987,
3495 11:37:30.926984 TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988,
3496 11:37:30.930005 TX Bit6 (983~1006) 24 994, Bit14 (976~997) 22 986,
3497 11:37:30.936961 TX Bit7 (983~1005) 23 994, Bit15 (970~991) 22 980,
3498 11:37:30.937046
3499 11:37:30.939812 Write Rank1 MR14 =0x16
3500 11:37:30.947870
3501 11:37:30.951000 CH=1, VrefRange= 0, VrefLevel = 22
3502 11:37:30.954468 TX Bit0 (984~1007) 24 995, Bit8 (973~993) 21 983,
3503 11:37:30.957543 TX Bit1 (983~1006) 24 994, Bit9 (971~992) 22 981,
3504 11:37:30.964003 TX Bit2 (980~1005) 26 992, Bit10 (975~999) 25 987,
3505 11:37:30.967324 TX Bit3 (978~1001) 24 989, Bit11 (976~999) 24 987,
3506 11:37:30.973972 TX Bit4 (982~1006) 25 994, Bit12 (976~997) 22 986,
3507 11:37:30.977234 TX Bit5 (984~1007) 24 995, Bit13 (976~999) 24 987,
3508 11:37:30.980707 TX Bit6 (983~1006) 24 994, Bit14 (976~998) 23 987,
3509 11:37:30.987185 TX Bit7 (983~1006) 24 994, Bit15 (969~991) 23 980,
3510 11:37:30.987299
3511 11:37:30.990277 Write Rank1 MR14 =0x18
3512 11:37:30.998514
3513 11:37:31.001432 CH=1, VrefRange= 0, VrefLevel = 24
3514 11:37:31.004736 TX Bit0 (984~1007) 24 995, Bit8 (973~994) 22 983,
3515 11:37:31.007858 TX Bit1 (982~1006) 25 994, Bit9 (971~993) 23 982,
3516 11:37:31.014680 TX Bit2 (980~1005) 26 992, Bit10 (974~999) 26 986,
3517 11:37:31.017931 TX Bit3 (978~1001) 24 989, Bit11 (976~999) 24 987,
3518 11:37:31.024605 TX Bit4 (982~1006) 25 994, Bit12 (976~997) 22 986,
3519 11:37:31.027714 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3520 11:37:31.031275 TX Bit6 (982~1006) 25 994, Bit14 (976~998) 23 987,
3521 11:37:31.037699 TX Bit7 (983~1006) 24 994, Bit15 (969~992) 24 980,
3522 11:37:31.037809
3523 11:37:31.040763 Write Rank1 MR14 =0x1a
3524 11:37:31.048896
3525 11:37:31.052073 CH=1, VrefRange= 0, VrefLevel = 26
3526 11:37:31.055583 TX Bit0 (984~1008) 25 996, Bit8 (972~994) 23 983,
3527 11:37:31.058652 TX Bit1 (983~1007) 25 995, Bit9 (971~993) 23 982,
3528 11:37:31.065260 TX Bit2 (979~1005) 27 992, Bit10 (974~999) 26 986,
3529 11:37:31.068723 TX Bit3 (978~1002) 25 990, Bit11 (975~999) 25 987,
3530 11:37:31.075272 TX Bit4 (982~1007) 26 994, Bit12 (976~998) 23 987,
3531 11:37:31.078506 TX Bit5 (983~1007) 25 995, Bit13 (976~999) 24 987,
3532 11:37:31.081730 TX Bit6 (982~1007) 26 994, Bit14 (976~998) 23 987,
3533 11:37:31.088068 TX Bit7 (982~1006) 25 994, Bit15 (969~992) 24 980,
3534 11:37:31.088171
3535 11:37:31.091473 Write Rank1 MR14 =0x1c
3536 11:37:31.099578
3537 11:37:31.102845 CH=1, VrefRange= 0, VrefLevel = 28
3538 11:37:31.105983 TX Bit0 (983~1008) 26 995, Bit8 (972~995) 24 983,
3539 11:37:31.109371 TX Bit1 (982~1007) 26 994, Bit9 (971~994) 24 982,
3540 11:37:31.115799 TX Bit2 (979~1006) 28 992, Bit10 (975~999) 25 987,
3541 11:37:31.119099 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3542 11:37:31.125692 TX Bit4 (982~1007) 26 994, Bit12 (976~998) 23 987,
3543 11:37:31.129143 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
3544 11:37:31.132078 TX Bit6 (983~1007) 25 995, Bit14 (975~998) 24 986,
3545 11:37:31.138893 TX Bit7 (982~1007) 26 994, Bit15 (969~992) 24 980,
3546 11:37:31.138977
3547 11:37:31.142182 Write Rank1 MR14 =0x1e
3548 11:37:31.150054
3549 11:37:31.153603 CH=1, VrefRange= 0, VrefLevel = 30
3550 11:37:31.156642 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984,
3551 11:37:31.159760 TX Bit1 (982~1007) 26 994, Bit9 (971~995) 25 983,
3552 11:37:31.166464 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
3553 11:37:31.169544 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3554 11:37:31.176179 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
3555 11:37:31.179588 TX Bit5 (983~1008) 26 995, Bit13 (976~999) 24 987,
3556 11:37:31.182613 TX Bit6 (982~1007) 26 994, Bit14 (975~998) 24 986,
3557 11:37:31.189400 TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981,
3558 11:37:31.189504
3559 11:37:31.192554 Write Rank1 MR14 =0x20
3560 11:37:31.200704
3561 11:37:31.204054 CH=1, VrefRange= 0, VrefLevel = 32
3562 11:37:31.207292 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984,
3563 11:37:31.210643 TX Bit1 (982~1007) 26 994, Bit9 (971~995) 25 983,
3564 11:37:31.217308 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
3565 11:37:31.220422 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3566 11:37:31.226802 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
3567 11:37:31.230244 TX Bit5 (983~1008) 26 995, Bit13 (976~999) 24 987,
3568 11:37:31.233570 TX Bit6 (982~1007) 26 994, Bit14 (975~998) 24 986,
3569 11:37:31.240143 TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981,
3570 11:37:31.240256
3571 11:37:31.243206 Write Rank1 MR14 =0x22
3572 11:37:31.251557
3573 11:37:31.254786 CH=1, VrefRange= 0, VrefLevel = 34
3574 11:37:31.258062 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984,
3575 11:37:31.261281 TX Bit1 (982~1007) 26 994, Bit9 (971~995) 25 983,
3576 11:37:31.267608 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
3577 11:37:31.271078 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3578 11:37:31.277703 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
3579 11:37:31.280775 TX Bit5 (983~1008) 26 995, Bit13 (976~999) 24 987,
3580 11:37:31.284261 TX Bit6 (982~1007) 26 994, Bit14 (975~998) 24 986,
3581 11:37:31.290827 TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981,
3582 11:37:31.290911
3583 11:37:31.293923 Write Rank1 MR14 =0x24
3584 11:37:31.301850
3585 11:37:31.305037 CH=1, VrefRange= 0, VrefLevel = 36
3586 11:37:31.308603 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984,
3587 11:37:31.311603 TX Bit1 (982~1007) 26 994, Bit9 (971~995) 25 983,
3588 11:37:31.318206 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
3589 11:37:31.321253 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3590 11:37:31.328008 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
3591 11:37:31.331130 TX Bit5 (983~1008) 26 995, Bit13 (976~999) 24 987,
3592 11:37:31.334453 TX Bit6 (982~1007) 26 994, Bit14 (975~998) 24 986,
3593 11:37:31.341029 TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981,
3594 11:37:31.341117
3595 11:37:31.344376 Write Rank1 MR14 =0x26
3596 11:37:31.352360
3597 11:37:31.355447 CH=1, VrefRange= 0, VrefLevel = 38
3598 11:37:31.358749 TX Bit0 (984~1008) 25 996, Bit8 (972~996) 25 984,
3599 11:37:31.362075 TX Bit1 (982~1007) 26 994, Bit9 (971~995) 25 983,
3600 11:37:31.368704 TX Bit2 (979~1006) 28 992, Bit10 (975~998) 24 986,
3601 11:37:31.371968 TX Bit3 (978~1003) 26 990, Bit11 (975~999) 25 987,
3602 11:37:31.378537 TX Bit4 (982~1006) 25 994, Bit12 (975~999) 25 987,
3603 11:37:31.381883 TX Bit5 (983~1008) 26 995, Bit13 (976~999) 24 987,
3604 11:37:31.385174 TX Bit6 (982~1007) 26 994, Bit14 (975~998) 24 986,
3605 11:37:31.391693 TX Bit7 (982~1007) 26 994, Bit15 (969~993) 25 981,
3606 11:37:31.391803
3607 11:37:31.391897
3608 11:37:31.394910 TX Vref found, early break! 375< 384
3609 11:37:31.398051 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3610 11:37:31.401647 u1DelayCellOfst[0]=7 cells (6 PI)
3611 11:37:31.404768 u1DelayCellOfst[1]=5 cells (4 PI)
3612 11:37:31.408167 u1DelayCellOfst[2]=2 cells (2 PI)
3613 11:37:31.411102 u1DelayCellOfst[3]=0 cells (0 PI)
3614 11:37:31.414610 u1DelayCellOfst[4]=5 cells (4 PI)
3615 11:37:31.417711 u1DelayCellOfst[5]=6 cells (5 PI)
3616 11:37:31.421004 u1DelayCellOfst[6]=5 cells (4 PI)
3617 11:37:31.424398 u1DelayCellOfst[7]=5 cells (4 PI)
3618 11:37:31.427414 Byte0, DQ PI dly=990, DQM PI dly= 993
3619 11:37:31.430653 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
3620 11:37:31.430737
3621 11:37:31.434068 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
3622 11:37:31.437560
3623 11:37:31.437643 u1DelayCellOfst[8]=3 cells (3 PI)
3624 11:37:31.440788 u1DelayCellOfst[9]=2 cells (2 PI)
3625 11:37:31.443873 u1DelayCellOfst[10]=6 cells (5 PI)
3626 11:37:31.447286 u1DelayCellOfst[11]=7 cells (6 PI)
3627 11:37:31.450451 u1DelayCellOfst[12]=7 cells (6 PI)
3628 11:37:31.453688 u1DelayCellOfst[13]=7 cells (6 PI)
3629 11:37:31.457065 u1DelayCellOfst[14]=6 cells (5 PI)
3630 11:37:31.460385 u1DelayCellOfst[15]=0 cells (0 PI)
3631 11:37:31.463538 Byte1, DQ PI dly=981, DQM PI dly= 984
3632 11:37:31.466709 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3633 11:37:31.466794
3634 11:37:31.473422 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3635 11:37:31.473507
3636 11:37:31.473573 Write Rank1 MR14 =0x1e
3637 11:37:31.473632
3638 11:37:31.476624 Final TX Range 0 Vref 30
3639 11:37:31.476708
3640 11:37:31.483071 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3641 11:37:31.483155
3642 11:37:31.489825 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3643 11:37:31.496392 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3644 11:37:31.506304 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3645 11:37:31.506390 Write Rank1 MR3 =0xb0
3646 11:37:31.509311 DramC Write-DBI on
3647 11:37:31.509394 ==
3648 11:37:31.512659 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3649 11:37:31.516124 fsp= 1, odt_onoff= 1, Byte mode= 0
3650 11:37:31.516243 ==
3651 11:37:31.522673 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3652 11:37:31.522757
3653 11:37:31.522821 Begin, DQ Scan Range 704~768
3654 11:37:31.522881
3655 11:37:31.525726
3656 11:37:31.525808 TX Vref Scan disable
3657 11:37:31.529041 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3658 11:37:31.532229 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3659 11:37:31.535674 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3660 11:37:31.538842 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3661 11:37:31.541968 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3662 11:37:31.545506 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3663 11:37:31.551992 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3664 11:37:31.555073 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3665 11:37:31.558647 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3666 11:37:31.561834 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3667 11:37:31.565279 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3668 11:37:31.568349 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3669 11:37:31.571609 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3670 11:37:31.574717 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3671 11:37:31.578247 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3672 11:37:31.581345 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3673 11:37:31.584680 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3674 11:37:31.588117 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3675 11:37:31.591187 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3676 11:37:31.594445 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3677 11:37:31.601141 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3678 11:37:31.604270 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3679 11:37:31.607603 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3680 11:37:31.614184 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3681 11:37:31.617323 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3682 11:37:31.620526 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3683 11:37:31.624065 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3684 11:37:31.627162 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3685 11:37:31.630273 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3686 11:37:31.633742 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3687 11:37:31.637124 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3688 11:37:31.640303 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3689 11:37:31.643418 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3690 11:37:31.646666 Byte0, DQ PI dly=738, DQM PI dly= 738
3691 11:37:31.653372 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
3692 11:37:31.653457
3693 11:37:31.656837 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
3694 11:37:31.656921
3695 11:37:31.659983 Byte1, DQ PI dly=727, DQM PI dly= 727
3696 11:37:31.663033 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23)
3697 11:37:31.663149
3698 11:37:31.669796 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23)
3699 11:37:31.669880
3700 11:37:31.676269 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3701 11:37:31.682864 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3702 11:37:31.689501 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3703 11:37:31.692716 Write Rank1 MR3 =0x30
3704 11:37:31.692800 DramC Write-DBI off
3705 11:37:31.692865
3706 11:37:31.696010 [DATLAT]
3707 11:37:31.699104 Freq=1600, CH1 RK1, use_rxtx_scan=0
3708 11:37:31.699214
3709 11:37:31.699307 DATLAT Default: 0x10
3710 11:37:31.702673 7, 0xFFFF, sum=0
3711 11:37:31.702757 8, 0xFFFF, sum=0
3712 11:37:31.705828 9, 0xFFFF, sum=0
3713 11:37:31.705912 10, 0xFFFF, sum=0
3714 11:37:31.709028 11, 0xFFFF, sum=0
3715 11:37:31.709112 12, 0xFFFF, sum=0
3716 11:37:31.712405 13, 0xFFFF, sum=0
3717 11:37:31.712489 14, 0x0, sum=1
3718 11:37:31.712555 15, 0x0, sum=2
3719 11:37:31.715494 16, 0x0, sum=3
3720 11:37:31.715579 17, 0x0, sum=4
3721 11:37:31.722152 pattern=2 first_step=14 total pass=5 best_step=16
3722 11:37:31.722237 ==
3723 11:37:31.725289 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3724 11:37:31.728712 fsp= 1, odt_onoff= 1, Byte mode= 0
3725 11:37:31.728795 ==
3726 11:37:31.735045 Start DQ dly to find pass range UseTestEngine =1
3727 11:37:31.738287 x-axis: bit #, y-axis: DQ dly (-127~63)
3728 11:37:31.738371 RX Vref Scan = 0
3729 11:37:31.741752 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3730 11:37:31.744735 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3731 11:37:31.748304 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3732 11:37:31.751450 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3733 11:37:31.754723 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3734 11:37:31.757996 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3735 11:37:31.758080 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3736 11:37:31.761163 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3737 11:37:31.764697 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3738 11:37:31.767739 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3739 11:37:31.771232 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3740 11:37:31.774438 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3741 11:37:31.777835 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3742 11:37:31.780884 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3743 11:37:31.784245 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3744 11:37:31.784329 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3745 11:37:31.787368 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3746 11:37:31.790840 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3747 11:37:31.793918 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3748 11:37:31.797361 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3749 11:37:31.800452 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3750 11:37:31.803949 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3751 11:37:31.807040 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3752 11:37:31.807136 -3, [0] xxxxxxxx xoxxxxxo [MSB]
3753 11:37:31.810358 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3754 11:37:31.813818 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3755 11:37:31.816759 0, [0] xxxoxxxx ooxxxxxo [MSB]
3756 11:37:31.820087 1, [0] xxxoxxxx ooxxxxxo [MSB]
3757 11:37:31.823700 2, [0] xxxoxxxx ooxxxxxo [MSB]
3758 11:37:31.826546 3, [0] ooooxxxo ooooooxo [MSB]
3759 11:37:31.826630 4, [0] oooooxxo oooooooo [MSB]
3760 11:37:31.829917 5, [0] ooooooxo oooooooo [MSB]
3761 11:37:31.834442 32, [0] oooooooo ooooooox [MSB]
3762 11:37:31.837772 33, [0] oooooooo ooooooox [MSB]
3763 11:37:31.841477 34, [0] oooxoooo oxooooox [MSB]
3764 11:37:31.844554 35, [0] ooxxoooo oxooooox [MSB]
3765 11:37:31.847554 36, [0] ooxxoooo xxooooox [MSB]
3766 11:37:31.851028 37, [0] ooxxoooo xxooooox [MSB]
3767 11:37:31.854282 38, [0] ooxxoooo xxooxoox [MSB]
3768 11:37:31.854395 39, [0] ooxxooox xxxxxoox [MSB]
3769 11:37:31.857372 40, [0] oxxxxoox xxxxxxox [MSB]
3770 11:37:31.860755 41, [0] xxxxxxxx xxxxxxxx [MSB]
3771 11:37:31.863931 iDelay=41, Bit 0, Center 21 (3 ~ 40) 38
3772 11:37:31.867437 iDelay=41, Bit 1, Center 21 (3 ~ 39) 37
3773 11:37:31.870659 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3774 11:37:31.877313 iDelay=41, Bit 3, Center 15 (-2 ~ 33) 36
3775 11:37:31.880334 iDelay=41, Bit 4, Center 21 (4 ~ 39) 36
3776 11:37:31.883820 iDelay=41, Bit 5, Center 22 (5 ~ 40) 36
3777 11:37:31.886930 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3778 11:37:31.890195 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
3779 11:37:31.893440 iDelay=41, Bit 8, Center 17 (-1 ~ 35) 37
3780 11:37:31.896903 iDelay=41, Bit 9, Center 15 (-3 ~ 33) 37
3781 11:37:31.899977 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3782 11:37:31.903391 iDelay=41, Bit 11, Center 20 (3 ~ 38) 36
3783 11:37:31.906522 iDelay=41, Bit 12, Center 20 (3 ~ 37) 35
3784 11:37:31.909939 iDelay=41, Bit 13, Center 21 (3 ~ 39) 37
3785 11:37:31.916357 iDelay=41, Bit 14, Center 22 (4 ~ 40) 37
3786 11:37:31.919952 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
3787 11:37:31.920036 ==
3788 11:37:31.923005 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3789 11:37:31.926271 fsp= 1, odt_onoff= 1, Byte mode= 0
3790 11:37:31.926356 ==
3791 11:37:31.929728 DQS Delay:
3792 11:37:31.929814 DQS0 = 0, DQS1 = 0
3793 11:37:31.933006 DQM Delay:
3794 11:37:31.933088 DQM0 = 20, DQM1 = 18
3795 11:37:31.933153 DQ Delay:
3796 11:37:31.935956 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =15
3797 11:37:31.939498 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3798 11:37:31.942632 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =20
3799 11:37:31.945762 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =13
3800 11:37:31.945844
3801 11:37:31.945908
3802 11:37:31.949174
3803 11:37:31.949257 [DramC_TX_OE_Calibration] TA2
3804 11:37:31.952632 Original DQ_B0 (3 6) =30, OEN = 27
3805 11:37:31.955847 Original DQ_B1 (3 6) =30, OEN = 27
3806 11:37:31.958888 23, 0x0, End_B0=23 End_B1=23
3807 11:37:31.962429 24, 0x0, End_B0=24 End_B1=24
3808 11:37:31.965499 25, 0x0, End_B0=25 End_B1=25
3809 11:37:31.965584 26, 0x0, End_B0=26 End_B1=26
3810 11:37:31.968951 27, 0x0, End_B0=27 End_B1=27
3811 11:37:31.972205 28, 0x0, End_B0=28 End_B1=28
3812 11:37:31.975610 29, 0x0, End_B0=29 End_B1=29
3813 11:37:31.978665 30, 0x0, End_B0=30 End_B1=30
3814 11:37:31.978779 31, 0xFFFF, End_B0=30 End_B1=30
3815 11:37:31.985370 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3816 11:37:31.991706 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3817 11:37:31.991807
3818 11:37:31.991874
3819 11:37:31.994905 Write Rank1 MR23 =0x3f
3820 11:37:31.995008 [DQSOSC]
3821 11:37:32.001286 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3822 11:37:32.007991 CH1_RK1: MR19=0x202, MR18=0xB7B7, DQSOSC=453, MR23=63, INC=11, DEC=17
3823 11:37:32.011381 Write Rank1 MR23 =0x3f
3824 11:37:32.011477 [DQSOSC]
3825 11:37:32.017834 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3826 11:37:32.021246 CH1 RK1: MR19=202, MR18=B7B7
3827 11:37:32.024325 [RxdqsGatingPostProcess] freq 1600
3828 11:37:32.031007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3829 11:37:32.031090 Rank: 0
3830 11:37:32.034341 best DQS0 dly(2T, 0.5T) = (2, 6)
3831 11:37:32.037429 best DQS1 dly(2T, 0.5T) = (2, 6)
3832 11:37:32.040708 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3833 11:37:32.044011 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3834 11:37:32.044094 Rank: 1
3835 11:37:32.047250 best DQS0 dly(2T, 0.5T) = (2, 6)
3836 11:37:32.050758 best DQS1 dly(2T, 0.5T) = (2, 6)
3837 11:37:32.053831 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3838 11:37:32.057288 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3839 11:37:32.060269 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3840 11:37:32.063510 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3841 11:37:32.070096 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3842 11:37:32.070179
3843 11:37:32.070243
3844 11:37:32.073642 [Calibration Summary] Freqency 1600
3845 11:37:32.073724 CH 0, Rank 0
3846 11:37:32.076629 All Pass.
3847 11:37:32.076712
3848 11:37:32.076776 CH 0, Rank 1
3849 11:37:32.076836 All Pass.
3850 11:37:32.076892
3851 11:37:32.079817 CH 1, Rank 0
3852 11:37:32.079900 All Pass.
3853 11:37:32.079965
3854 11:37:32.080023 CH 1, Rank 1
3855 11:37:32.083435 All Pass.
3856 11:37:32.083529
3857 11:37:32.089746 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3858 11:37:32.096245 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3859 11:37:32.103029 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3860 11:37:32.106342 Write Rank0 MR3 =0xb0
3861 11:37:32.112601 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3862 11:37:32.119423 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3863 11:37:32.126035 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3864 11:37:32.129084 Write Rank1 MR3 =0xb0
3865 11:37:32.132269 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3866 11:37:32.142236 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3867 11:37:32.148678 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3868 11:37:32.148762 Write Rank0 MR3 =0xb0
3869 11:37:32.155244 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3870 11:37:32.161903 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3871 11:37:32.171600 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3872 11:37:32.171685 Write Rank1 MR3 =0xb0
3873 11:37:32.174944 DramC Write-DBI on
3874 11:37:32.178281 [GetDramInforAfterCalByMRR] Vendor 6.
3875 11:37:32.181637 [GetDramInforAfterCalByMRR] Revision 505.
3876 11:37:32.181720 MR8 1111
3877 11:37:32.188001 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3878 11:37:32.188093 MR8 1111
3879 11:37:32.191435 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3880 11:37:32.194744 MR8 1111
3881 11:37:32.197990 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3882 11:37:32.198074 MR8 1111
3883 11:37:32.204682 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3884 11:37:32.214369 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3885 11:37:32.214454 Write Rank0 MR13 =0xd0
3886 11:37:32.217571 Write Rank1 MR13 =0xd0
3887 11:37:32.217656 Write Rank0 MR13 =0xd0
3888 11:37:32.220960 Write Rank1 MR13 =0xd0
3889 11:37:32.224076 Save calibration result to emmc
3890 11:37:32.224158
3891 11:37:32.224225
3892 11:37:32.227360 [DramcModeReg_Check] Freq_1600, FSP_1
3893 11:37:32.230834 FSP_1, CH_0, RK0
3894 11:37:32.230917 Write Rank0 MR13 =0xd8
3895 11:37:32.233920 MR12 = 0x5c (global = 0x5c) match
3896 11:37:32.237496 MR14 = 0x1c (global = 0x1c) match
3897 11:37:32.240565 FSP_1, CH_0, RK1
3898 11:37:32.240647 Write Rank1 MR13 =0xd8
3899 11:37:32.243734 MR12 = 0x5e (global = 0x5e) match
3900 11:37:32.247026 MR14 = 0x1e (global = 0x1e) match
3901 11:37:32.250255 FSP_1, CH_1, RK0
3902 11:37:32.250338 Write Rank0 MR13 =0xd8
3903 11:37:32.253624 MR12 = 0x5c (global = 0x5c) match
3904 11:37:32.257068 MR14 = 0x1e (global = 0x1e) match
3905 11:37:32.259974 FSP_1, CH_1, RK1
3906 11:37:32.260083 Write Rank1 MR13 =0xd8
3907 11:37:32.263380 MR12 = 0x5e (global = 0x5e) match
3908 11:37:32.266572 MR14 = 0x1e (global = 0x1e) match
3909 11:37:32.266655
3910 11:37:32.273119 [MEM_TEST] 02: After DFS, before run time config
3911 11:37:32.283117 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3912 11:37:32.283229
3913 11:37:32.283326 [TA2_TEST]
3914 11:37:32.283415 === TA2 HW
3915 11:37:32.286329 TA2 PAT: XTALK
3916 11:37:32.289674 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3917 11:37:32.296099 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3918 11:37:32.299674 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3919 11:37:32.306083 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3920 11:37:32.306188
3921 11:37:32.306281
3922 11:37:32.306373 Settings after calibration
3923 11:37:32.306462
3924 11:37:32.309286 [DramcRunTimeConfig]
3925 11:37:32.312681 TransferPLLToSPMControl - MODE SW PHYPLL
3926 11:37:32.316109 TX_TRACKING: ON
3927 11:37:32.316194 RX_TRACKING: ON
3928 11:37:32.316291 HW_GATING: ON
3929 11:37:32.319071 HW_GATING DBG: OFF
3930 11:37:32.319185 ddr_geometry:1
3931 11:37:32.322551 ddr_geometry:1
3932 11:37:32.322637 ddr_geometry:1
3933 11:37:32.325688 ddr_geometry:1
3934 11:37:32.325791 ddr_geometry:1
3935 11:37:32.325883 ddr_geometry:1
3936 11:37:32.329159 ddr_geometry:1
3937 11:37:32.329260 ddr_geometry:1
3938 11:37:32.332444 High Freq DUMMY_READ_FOR_TRACKING: ON
3939 11:37:32.335550 ZQCS_ENABLE_LP4: OFF
3940 11:37:32.338700 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3941 11:37:32.342149 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3942 11:37:32.342246 SPM_CONTROL_AFTERK: ON
3943 11:37:32.345295 IMPEDANCE_TRACKING: ON
3944 11:37:32.348756 TEMP_SENSOR: ON
3945 11:37:32.348828 PER_BANK_REFRESH: ON
3946 11:37:32.351764 HW_SAVE_FOR_SR: ON
3947 11:37:32.355044 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 11:37:32.358271 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3949 11:37:32.361701 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3950 11:37:32.361803 Read ODT Tracking: ON
3951 11:37:32.365041 =========================
3952 11:37:32.365144
3953 11:37:32.365236 [TA2_TEST]
3954 11:37:32.368261 === TA2 HW
3955 11:37:32.371356 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3956 11:37:32.378014 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3957 11:37:32.381371 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3958 11:37:32.387825 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3959 11:37:32.387928
3960 11:37:32.391019 [MEM_TEST] 03: After run time config
3961 11:37:32.400812 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3962 11:37:32.404011 [complex_mem_test] start addr:0x40024000, len:131072
3963 11:37:32.608604 1st complex R/W mem test pass
3964 11:37:32.614720 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3965 11:37:32.618103 sync preloader write leveling
3966 11:37:32.621347 sync preloader cbt_mr12
3967 11:37:32.624746 sync preloader cbt_clk_dly
3968 11:37:32.624849 sync preloader cbt_cmd_dly
3969 11:37:32.628185 sync preloader cbt_cs
3970 11:37:32.631212 sync preloader cbt_ca_perbit_delay
3971 11:37:32.634780 sync preloader clk_delay
3972 11:37:32.634851 sync preloader dqs_delay
3973 11:37:32.638114 sync preloader u1Gating2T_Save
3974 11:37:32.641248 sync preloader u1Gating05T_Save
3975 11:37:32.644367 sync preloader u1Gatingfine_tune_Save
3976 11:37:32.647870 sync preloader u1Gatingucpass_count_Save
3977 11:37:32.651054 sync preloader u1TxWindowPerbitVref_Save
3978 11:37:32.654370 sync preloader u1TxCenter_min_Save
3979 11:37:32.657473 sync preloader u1TxCenter_max_Save
3980 11:37:32.660678 sync preloader u1Txwin_center_Save
3981 11:37:32.664196 sync preloader u1Txfirst_pass_Save
3982 11:37:32.667273 sync preloader u1Txlast_pass_Save
3983 11:37:32.670714 sync preloader u1RxDatlat_Save
3984 11:37:32.673874 sync preloader u1RxWinPerbitVref_Save
3985 11:37:32.676970 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3986 11:37:32.680308 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3987 11:37:32.683792 sync preloader delay_cell_unit
3988 11:37:32.690314 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3989 11:37:32.693431 sync preloader write leveling
3990 11:37:32.696884 sync preloader cbt_mr12
3991 11:37:32.696986 sync preloader cbt_clk_dly
3992 11:37:32.699961 sync preloader cbt_cmd_dly
3993 11:37:32.703480 sync preloader cbt_cs
3994 11:37:32.706593 sync preloader cbt_ca_perbit_delay
3995 11:37:32.706692 sync preloader clk_delay
3996 11:37:32.710084 sync preloader dqs_delay
3997 11:37:32.713285 sync preloader u1Gating2T_Save
3998 11:37:32.716411 sync preloader u1Gating05T_Save
3999 11:37:32.719574 sync preloader u1Gatingfine_tune_Save
4000 11:37:32.723145 sync preloader u1Gatingucpass_count_Save
4001 11:37:32.726372 sync preloader u1TxWindowPerbitVref_Save
4002 11:37:32.729587 sync preloader u1TxCenter_min_Save
4003 11:37:32.732626 sync preloader u1TxCenter_max_Save
4004 11:37:32.736103 sync preloader u1Txwin_center_Save
4005 11:37:32.739244 sync preloader u1Txfirst_pass_Save
4006 11:37:32.742735 sync preloader u1Txlast_pass_Save
4007 11:37:32.745992 sync preloader u1RxDatlat_Save
4008 11:37:32.749337 sync preloader u1RxWinPerbitVref_Save
4009 11:37:32.752297 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4010 11:37:32.755645 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4011 11:37:32.759101 sync preloader delay_cell_unit
4012 11:37:32.765585 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4013 11:37:32.768879 sync preloader write leveling
4014 11:37:32.772145 sync preloader cbt_mr12
4015 11:37:32.772256 sync preloader cbt_clk_dly
4016 11:37:32.775464 sync preloader cbt_cmd_dly
4017 11:37:32.778769 sync preloader cbt_cs
4018 11:37:32.781921 sync preloader cbt_ca_perbit_delay
4019 11:37:32.782022 sync preloader clk_delay
4020 11:37:32.785067 sync preloader dqs_delay
4021 11:37:32.788596 sync preloader u1Gating2T_Save
4022 11:37:32.791711 sync preloader u1Gating05T_Save
4023 11:37:32.794867 sync preloader u1Gatingfine_tune_Save
4024 11:37:32.798457 sync preloader u1Gatingucpass_count_Save
4025 11:37:32.801440 sync preloader u1TxWindowPerbitVref_Save
4026 11:37:32.804937 sync preloader u1TxCenter_min_Save
4027 11:37:32.808029 sync preloader u1TxCenter_max_Save
4028 11:37:32.811607 sync preloader u1Txwin_center_Save
4029 11:37:32.814734 sync preloader u1Txfirst_pass_Save
4030 11:37:32.817755 sync preloader u1Txlast_pass_Save
4031 11:37:32.817826 sync preloader u1RxDatlat_Save
4032 11:37:32.821363 sync preloader u1RxWinPerbitVref_Save
4033 11:37:32.827964 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4034 11:37:32.831193 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4035 11:37:32.834342 sync preloader delay_cell_unit
4036 11:37:32.837881 just_for_test_dump_coreboot_params dump all params
4037 11:37:32.840746 dump source = 0x0
4038 11:37:32.840846 dump params frequency:1600
4039 11:37:32.844284 dump params rank number:2
4040 11:37:32.844358
4041 11:37:32.847341 dump params write leveling
4042 11:37:32.850603 write leveling[0][0][0] = 0x1f
4043 11:37:32.854102 write leveling[0][0][1] = 0x1b
4044 11:37:32.854176 write leveling[0][1][0] = 0x1b
4045 11:37:32.857327 write leveling[0][1][1] = 0x17
4046 11:37:32.860564 write leveling[1][0][0] = 0x24
4047 11:37:32.863590 write leveling[1][0][1] = 0x1d
4048 11:37:32.867009 write leveling[1][1][0] = 0x25
4049 11:37:32.870161 write leveling[1][1][1] = 0x1c
4050 11:37:32.870264 dump params cbt_cs
4051 11:37:32.873694 cbt_cs[0][0] = 0x6
4052 11:37:32.873799 cbt_cs[0][1] = 0x6
4053 11:37:32.876810 cbt_cs[1][0] = 0xb
4054 11:37:32.876882 cbt_cs[1][1] = 0xb
4055 11:37:32.880251 dump params cbt_mr12
4056 11:37:32.883363 cbt_mr12[0][0] = 0x1c
4057 11:37:32.883469 cbt_mr12[0][1] = 0x1e
4058 11:37:32.886631 cbt_mr12[1][0] = 0x1c
4059 11:37:32.886728 cbt_mr12[1][1] = 0x1e
4060 11:37:32.889838 dump params tx window
4061 11:37:32.893251 tx_center_min[0][0][0] = 983
4062 11:37:32.896240 tx_center_max[0][0][0] = 990
4063 11:37:32.896316 tx_center_min[0][0][1] = 979
4064 11:37:32.899665 tx_center_max[0][0][1] = 986
4065 11:37:32.902796 tx_center_min[0][1][0] = 982
4066 11:37:32.906315 tx_center_max[0][1][0] = 989
4067 11:37:32.909423 tx_center_min[0][1][1] = 979
4068 11:37:32.909520 tx_center_max[0][1][1] = 985
4069 11:37:32.912641 tx_center_min[1][0][0] = 989
4070 11:37:32.916028 tx_center_max[1][0][0] = 995
4071 11:37:32.919461 tx_center_min[1][0][1] = 980
4072 11:37:32.922519 tx_center_max[1][0][1] = 987
4073 11:37:32.922620 tx_center_min[1][1][0] = 990
4074 11:37:32.926033 tx_center_max[1][1][0] = 996
4075 11:37:32.929079 tx_center_min[1][1][1] = 981
4076 11:37:32.932554 tx_center_max[1][1][1] = 987
4077 11:37:32.932700 dump params tx window
4078 11:37:32.935732 tx_win_center[0][0][0] = 990
4079 11:37:32.938917 tx_first_pass[0][0][0] = 978
4080 11:37:32.942280 tx_last_pass[0][0][0] = 1002
4081 11:37:32.945488 tx_win_center[0][0][1] = 989
4082 11:37:32.945600 tx_first_pass[0][0][1] = 977
4083 11:37:32.948831 tx_last_pass[0][0][1] = 1001
4084 11:37:32.952080 tx_win_center[0][0][2] = 989
4085 11:37:32.955566 tx_first_pass[0][0][2] = 977
4086 11:37:32.958595 tx_last_pass[0][0][2] = 1002
4087 11:37:32.958706 tx_win_center[0][0][3] = 983
4088 11:37:32.962126 tx_first_pass[0][0][3] = 972
4089 11:37:32.965408 tx_last_pass[0][0][3] = 995
4090 11:37:32.968506 tx_win_center[0][0][4] = 988
4091 11:37:32.971667 tx_first_pass[0][0][4] = 977
4092 11:37:32.971774 tx_last_pass[0][0][4] = 1000
4093 11:37:32.975004 tx_win_center[0][0][5] = 987
4094 11:37:32.978268 tx_first_pass[0][0][5] = 975
4095 11:37:32.981747 tx_last_pass[0][0][5] = 999
4096 11:37:32.981863 tx_win_center[0][0][6] = 987
4097 11:37:32.984924 tx_first_pass[0][0][6] = 976
4098 11:37:32.988356 tx_last_pass[0][0][6] = 999
4099 11:37:32.991711 tx_win_center[0][0][7] = 989
4100 11:37:32.994730 tx_first_pass[0][0][7] = 977
4101 11:37:32.994831 tx_last_pass[0][0][7] = 1001
4102 11:37:32.998045 tx_win_center[0][0][8] = 979
4103 11:37:33.001418 tx_first_pass[0][0][8] = 968
4104 11:37:33.004669 tx_last_pass[0][0][8] = 991
4105 11:37:33.007796 tx_win_center[0][0][9] = 981
4106 11:37:33.007879 tx_first_pass[0][0][9] = 969
4107 11:37:33.011105 tx_last_pass[0][0][9] = 993
4108 11:37:33.014281 tx_win_center[0][0][10] = 986
4109 11:37:33.017716 tx_first_pass[0][0][10] = 974
4110 11:37:33.021049 tx_last_pass[0][0][10] = 998
4111 11:37:33.021133 tx_win_center[0][0][11] = 980
4112 11:37:33.024096 tx_first_pass[0][0][11] = 968
4113 11:37:33.027554 tx_last_pass[0][0][11] = 992
4114 11:37:33.030724 tx_win_center[0][0][12] = 981
4115 11:37:33.034134 tx_first_pass[0][0][12] = 970
4116 11:37:33.037275 tx_last_pass[0][0][12] = 993
4117 11:37:33.037387 tx_win_center[0][0][13] = 981
4118 11:37:33.040497 tx_first_pass[0][0][13] = 970
4119 11:37:33.043909 tx_last_pass[0][0][13] = 993
4120 11:37:33.046995 tx_win_center[0][0][14] = 983
4121 11:37:33.050260 tx_first_pass[0][0][14] = 970
4122 11:37:33.050361 tx_last_pass[0][0][14] = 996
4123 11:37:33.053712 tx_win_center[0][0][15] = 986
4124 11:37:33.056750 tx_first_pass[0][0][15] = 974
4125 11:37:33.060227 tx_last_pass[0][0][15] = 998
4126 11:37:33.063258 tx_win_center[0][1][0] = 989
4127 11:37:33.063368 tx_first_pass[0][1][0] = 978
4128 11:37:33.066853 tx_last_pass[0][1][0] = 1001
4129 11:37:33.070146 tx_win_center[0][1][1] = 988
4130 11:37:33.073242 tx_first_pass[0][1][1] = 977
4131 11:37:33.076382 tx_last_pass[0][1][1] = 1000
4132 11:37:33.076488 tx_win_center[0][1][2] = 989
4133 11:37:33.079864 tx_first_pass[0][1][2] = 978
4134 11:37:33.082929 tx_last_pass[0][1][2] = 1001
4135 11:37:33.086230 tx_win_center[0][1][3] = 982
4136 11:37:33.089803 tx_first_pass[0][1][3] = 970
4137 11:37:33.089888 tx_last_pass[0][1][3] = 994
4138 11:37:33.092927 tx_win_center[0][1][4] = 988
4139 11:37:33.096127 tx_first_pass[0][1][4] = 977
4140 11:37:33.099568 tx_last_pass[0][1][4] = 1000
4141 11:37:33.102903 tx_win_center[0][1][5] = 986
4142 11:37:33.102986 tx_first_pass[0][1][5] = 974
4143 11:37:33.106033 tx_last_pass[0][1][5] = 998
4144 11:37:33.109384 tx_win_center[0][1][6] = 987
4145 11:37:33.112467 tx_first_pass[0][1][6] = 976
4146 11:37:33.116114 tx_last_pass[0][1][6] = 999
4147 11:37:33.116219 tx_win_center[0][1][7] = 988
4148 11:37:33.119181 tx_first_pass[0][1][7] = 976
4149 11:37:33.122313 tx_last_pass[0][1][7] = 1001
4150 11:37:33.125456 tx_win_center[0][1][8] = 979
4151 11:37:33.128976 tx_first_pass[0][1][8] = 967
4152 11:37:33.129078 tx_last_pass[0][1][8] = 991
4153 11:37:33.132100 tx_win_center[0][1][9] = 979
4154 11:37:33.135581 tx_first_pass[0][1][9] = 968
4155 11:37:33.138880 tx_last_pass[0][1][9] = 991
4156 11:37:33.138987 tx_win_center[0][1][10] = 985
4157 11:37:33.142044 tx_first_pass[0][1][10] = 973
4158 11:37:33.145068 tx_last_pass[0][1][10] = 997
4159 11:37:33.148610 tx_win_center[0][1][11] = 979
4160 11:37:33.151747 tx_first_pass[0][1][11] = 967
4161 11:37:33.155232 tx_last_pass[0][1][11] = 991
4162 11:37:33.155336 tx_win_center[0][1][12] = 979
4163 11:37:33.158417 tx_first_pass[0][1][12] = 968
4164 11:37:33.161560 tx_last_pass[0][1][12] = 991
4165 11:37:33.165070 tx_win_center[0][1][13] = 979
4166 11:37:33.168207 tx_first_pass[0][1][13] = 968
4167 11:37:33.168285 tx_last_pass[0][1][13] = 991
4168 11:37:33.171631 tx_win_center[0][1][14] = 981
4169 11:37:33.174857 tx_first_pass[0][1][14] = 969
4170 11:37:33.178103 tx_last_pass[0][1][14] = 993
4171 11:37:33.181174 tx_win_center[0][1][15] = 985
4172 11:37:33.184678 tx_first_pass[0][1][15] = 973
4173 11:37:33.184780 tx_last_pass[0][1][15] = 997
4174 11:37:33.187999 tx_win_center[1][0][0] = 995
4175 11:37:33.191212 tx_first_pass[1][0][0] = 983
4176 11:37:33.194219 tx_last_pass[1][0][0] = 1007
4177 11:37:33.197723 tx_win_center[1][0][1] = 993
4178 11:37:33.197809 tx_first_pass[1][0][1] = 980
4179 11:37:33.201066 tx_last_pass[1][0][1] = 1006
4180 11:37:33.204230 tx_win_center[1][0][2] = 991
4181 11:37:33.207308 tx_first_pass[1][0][2] = 978
4182 11:37:33.210964 tx_last_pass[1][0][2] = 1005
4183 11:37:33.211047 tx_win_center[1][0][3] = 989
4184 11:37:33.214079 tx_first_pass[1][0][3] = 977
4185 11:37:33.217256 tx_last_pass[1][0][3] = 1001
4186 11:37:33.220575 tx_win_center[1][0][4] = 993
4187 11:37:33.223906 tx_first_pass[1][0][4] = 980
4188 11:37:33.223989 tx_last_pass[1][0][4] = 1006
4189 11:37:33.227096 tx_win_center[1][0][5] = 994
4190 11:37:33.230396 tx_first_pass[1][0][5] = 982
4191 11:37:33.233733 tx_last_pass[1][0][5] = 1006
4192 11:37:33.236882 tx_win_center[1][0][6] = 993
4193 11:37:33.236984 tx_first_pass[1][0][6] = 980
4194 11:37:33.240312 tx_last_pass[1][0][6] = 1006
4195 11:37:33.243208 tx_win_center[1][0][7] = 993
4196 11:37:33.246505 tx_first_pass[1][0][7] = 980
4197 11:37:33.250089 tx_last_pass[1][0][7] = 1006
4198 11:37:33.250186 tx_win_center[1][0][8] = 983
4199 11:37:33.253239 tx_first_pass[1][0][8] = 971
4200 11:37:33.256332 tx_last_pass[1][0][8] = 996
4201 11:37:33.259836 tx_win_center[1][0][9] = 982
4202 11:37:33.262981 tx_first_pass[1][0][9] = 970
4203 11:37:33.263055 tx_last_pass[1][0][9] = 994
4204 11:37:33.266469 tx_win_center[1][0][10] = 987
4205 11:37:33.269600 tx_first_pass[1][0][10] = 975
4206 11:37:33.272991 tx_last_pass[1][0][10] = 999
4207 11:37:33.276083 tx_win_center[1][0][11] = 987
4208 11:37:33.276155 tx_first_pass[1][0][11] = 976
4209 11:37:33.279203 tx_last_pass[1][0][11] = 999
4210 11:37:33.282679 tx_win_center[1][0][12] = 987
4211 11:37:33.286085 tx_first_pass[1][0][12] = 976
4212 11:37:33.289245 tx_last_pass[1][0][12] = 999
4213 11:37:33.289311 tx_win_center[1][0][13] = 987
4214 11:37:33.292464 tx_first_pass[1][0][13] = 976
4215 11:37:33.295788 tx_last_pass[1][0][13] = 999
4216 11:37:33.299037 tx_win_center[1][0][14] = 987
4217 11:37:33.302101 tx_first_pass[1][0][14] = 975
4218 11:37:33.305575 tx_last_pass[1][0][14] = 999
4219 11:37:33.305676 tx_win_center[1][0][15] = 980
4220 11:37:33.309031 tx_first_pass[1][0][15] = 969
4221 11:37:33.311987 tx_last_pass[1][0][15] = 992
4222 11:37:33.315310 tx_win_center[1][1][0] = 996
4223 11:37:33.318834 tx_first_pass[1][1][0] = 984
4224 11:37:33.318926 tx_last_pass[1][1][0] = 1008
4225 11:37:33.321827 tx_win_center[1][1][1] = 994
4226 11:37:33.325160 tx_first_pass[1][1][1] = 982
4227 11:37:33.328675 tx_last_pass[1][1][1] = 1007
4228 11:37:33.331665 tx_win_center[1][1][2] = 992
4229 11:37:33.331733 tx_first_pass[1][1][2] = 979
4230 11:37:33.334909 tx_last_pass[1][1][2] = 1006
4231 11:37:33.338264 tx_win_center[1][1][3] = 990
4232 11:37:33.341562 tx_first_pass[1][1][3] = 978
4233 11:37:33.344963 tx_last_pass[1][1][3] = 1003
4234 11:37:33.345064 tx_win_center[1][1][4] = 994
4235 11:37:33.348125 tx_first_pass[1][1][4] = 982
4236 11:37:33.351269 tx_last_pass[1][1][4] = 1006
4237 11:37:33.354496 tx_win_center[1][1][5] = 995
4238 11:37:33.358119 tx_first_pass[1][1][5] = 983
4239 11:37:33.358188 tx_last_pass[1][1][5] = 1008
4240 11:37:33.361260 tx_win_center[1][1][6] = 994
4241 11:37:33.364407 tx_first_pass[1][1][6] = 982
4242 11:37:33.367903 tx_last_pass[1][1][6] = 1007
4243 11:37:33.370985 tx_win_center[1][1][7] = 994
4244 11:37:33.371078 tx_first_pass[1][1][7] = 982
4245 11:37:33.374210 tx_last_pass[1][1][7] = 1007
4246 11:37:33.377690 tx_win_center[1][1][8] = 984
4247 11:37:33.380730 tx_first_pass[1][1][8] = 972
4248 11:37:33.383887 tx_last_pass[1][1][8] = 996
4249 11:37:33.383983 tx_win_center[1][1][9] = 983
4250 11:37:33.387328 tx_first_pass[1][1][9] = 971
4251 11:37:33.390493 tx_last_pass[1][1][9] = 995
4252 11:37:33.393875 tx_win_center[1][1][10] = 986
4253 11:37:33.396960 tx_first_pass[1][1][10] = 975
4254 11:37:33.397054 tx_last_pass[1][1][10] = 998
4255 11:37:33.400310 tx_win_center[1][1][11] = 987
4256 11:37:33.403739 tx_first_pass[1][1][11] = 975
4257 11:37:33.407110 tx_last_pass[1][1][11] = 999
4258 11:37:33.410165 tx_win_center[1][1][12] = 987
4259 11:37:33.410237 tx_first_pass[1][1][12] = 975
4260 11:37:33.413618 tx_last_pass[1][1][12] = 999
4261 11:37:33.416811 tx_win_center[1][1][13] = 987
4262 11:37:33.419922 tx_first_pass[1][1][13] = 976
4263 11:37:33.423415 tx_last_pass[1][1][13] = 999
4264 11:37:33.426668 tx_win_center[1][1][14] = 986
4265 11:37:33.426769 tx_first_pass[1][1][14] = 975
4266 11:37:33.430096 tx_last_pass[1][1][14] = 998
4267 11:37:33.433142 tx_win_center[1][1][15] = 981
4268 11:37:33.436278 tx_first_pass[1][1][15] = 969
4269 11:37:33.439838 tx_last_pass[1][1][15] = 993
4270 11:37:33.439934 dump params rx window
4271 11:37:33.442865 rx_firspass[0][0][0] = 7
4272 11:37:33.446054 rx_lastpass[0][0][0] = 36
4273 11:37:33.446147 rx_firspass[0][0][1] = 8
4274 11:37:33.449673 rx_lastpass[0][0][1] = 36
4275 11:37:33.452717 rx_firspass[0][0][2] = 5
4276 11:37:33.452788 rx_lastpass[0][0][2] = 39
4277 11:37:33.456184 rx_firspass[0][0][3] = -3
4278 11:37:33.459434 rx_lastpass[0][0][3] = 30
4279 11:37:33.462556 rx_firspass[0][0][4] = 6
4280 11:37:33.462625 rx_lastpass[0][0][4] = 36
4281 11:37:33.465958 rx_firspass[0][0][5] = 3
4282 11:37:33.469056 rx_lastpass[0][0][5] = 33
4283 11:37:33.469154 rx_firspass[0][0][6] = 3
4284 11:37:33.472631 rx_lastpass[0][0][6] = 33
4285 11:37:33.475712 rx_firspass[0][0][7] = 4
4286 11:37:33.479257 rx_lastpass[0][0][7] = 36
4287 11:37:33.479353 rx_firspass[0][0][8] = -2
4288 11:37:33.482292 rx_lastpass[0][0][8] = 30
4289 11:37:33.485433 rx_firspass[0][0][9] = 2
4290 11:37:33.485501 rx_lastpass[0][0][9] = 32
4291 11:37:33.488873 rx_firspass[0][0][10] = 8
4292 11:37:33.492014 rx_lastpass[0][0][10] = 37
4293 11:37:33.495213 rx_firspass[0][0][11] = 0
4294 11:37:33.495287 rx_lastpass[0][0][11] = 30
4295 11:37:33.498750 rx_firspass[0][0][12] = 3
4296 11:37:33.502021 rx_lastpass[0][0][12] = 31
4297 11:37:33.505337 rx_firspass[0][0][13] = 1
4298 11:37:33.505436 rx_lastpass[0][0][13] = 31
4299 11:37:33.508536 rx_firspass[0][0][14] = 0
4300 11:37:33.511595 rx_lastpass[0][0][14] = 35
4301 11:37:33.514999 rx_firspass[0][0][15] = 3
4302 11:37:33.515098 rx_lastpass[0][0][15] = 36
4303 11:37:33.518485 rx_firspass[0][1][0] = 4
4304 11:37:33.521439 rx_lastpass[0][1][0] = 39
4305 11:37:33.521535 rx_firspass[0][1][1] = 4
4306 11:37:33.524729 rx_lastpass[0][1][1] = 38
4307 11:37:33.528021 rx_firspass[0][1][2] = 6
4308 11:37:33.531304 rx_lastpass[0][1][2] = 40
4309 11:37:33.531400 rx_firspass[0][1][3] = -2
4310 11:37:33.534716 rx_lastpass[0][1][3] = 31
4311 11:37:33.538068 rx_firspass[0][1][4] = 5
4312 11:37:33.538169 rx_lastpass[0][1][4] = 38
4313 11:37:33.541106 rx_firspass[0][1][5] = 0
4314 11:37:33.544323 rx_lastpass[0][1][5] = 34
4315 11:37:33.547859 rx_firspass[0][1][6] = 1
4316 11:37:33.547931 rx_lastpass[0][1][6] = 35
4317 11:37:33.551072 rx_firspass[0][1][7] = 3
4318 11:37:33.554236 rx_lastpass[0][1][7] = 37
4319 11:37:33.554331 rx_firspass[0][1][8] = -4
4320 11:37:33.557528 rx_lastpass[0][1][8] = 32
4321 11:37:33.560932 rx_firspass[0][1][9] = -2
4322 11:37:33.564250 rx_lastpass[0][1][9] = 34
4323 11:37:33.564318 rx_firspass[0][1][10] = 5
4324 11:37:33.567242 rx_lastpass[0][1][10] = 40
4325 11:37:33.570485 rx_firspass[0][1][11] = -3
4326 11:37:33.573985 rx_lastpass[0][1][11] = 32
4327 11:37:33.574064 rx_firspass[0][1][12] = 0
4328 11:37:33.577062 rx_lastpass[0][1][12] = 34
4329 11:37:33.580583 rx_firspass[0][1][13] = -2
4330 11:37:33.583637 rx_lastpass[0][1][13] = 34
4331 11:37:33.583705 rx_firspass[0][1][14] = 2
4332 11:37:33.587130 rx_lastpass[0][1][14] = 36
4333 11:37:33.590274 rx_firspass[0][1][15] = 4
4334 11:37:33.593413 rx_lastpass[0][1][15] = 37
4335 11:37:33.593508 rx_firspass[1][0][0] = 5
4336 11:37:33.596848 rx_lastpass[1][0][0] = 36
4337 11:37:33.599949 rx_firspass[1][0][1] = 4
4338 11:37:33.600020 rx_lastpass[1][0][1] = 37
4339 11:37:33.603435 rx_firspass[1][0][2] = 1
4340 11:37:33.606496 rx_lastpass[1][0][2] = 35
4341 11:37:33.606587 rx_firspass[1][0][3] = 0
4342 11:37:33.609750 rx_lastpass[1][0][3] = 31
4343 11:37:33.613072 rx_firspass[1][0][4] = 5
4344 11:37:33.616581 rx_lastpass[1][0][4] = 35
4345 11:37:33.616667 rx_firspass[1][0][5] = 9
4346 11:37:33.619918 rx_lastpass[1][0][5] = 38
4347 11:37:33.622851 rx_firspass[1][0][6] = 6
4348 11:37:33.622936 rx_lastpass[1][0][6] = 38
4349 11:37:33.626144 rx_firspass[1][0][7] = 5
4350 11:37:33.629614 rx_lastpass[1][0][7] = 35
4351 11:37:33.632863 rx_firspass[1][0][8] = 0
4352 11:37:33.632955 rx_lastpass[1][0][8] = 33
4353 11:37:33.635978 rx_firspass[1][0][9] = -1
4354 11:37:33.639397 rx_lastpass[1][0][9] = 32
4355 11:37:33.639559 rx_firspass[1][0][10] = 2
4356 11:37:33.642480 rx_lastpass[1][0][10] = 36
4357 11:37:33.645688 rx_firspass[1][0][11] = 4
4358 11:37:33.648958 rx_lastpass[1][0][11] = 36
4359 11:37:33.649104 rx_firspass[1][0][12] = 5
4360 11:37:33.652466 rx_lastpass[1][0][12] = 35
4361 11:37:33.655502 rx_firspass[1][0][13] = 6
4362 11:37:33.658997 rx_lastpass[1][0][13] = 36
4363 11:37:33.659138 rx_firspass[1][0][14] = 5
4364 11:37:33.662334 rx_lastpass[1][0][14] = 37
4365 11:37:33.665380 rx_firspass[1][0][15] = -4
4366 11:37:33.668872 rx_lastpass[1][0][15] = 29
4367 11:37:33.668993 rx_firspass[1][1][0] = 3
4368 11:37:33.671943 rx_lastpass[1][1][0] = 40
4369 11:37:33.675269 rx_firspass[1][1][1] = 3
4370 11:37:33.675388 rx_lastpass[1][1][1] = 39
4371 11:37:33.678660 rx_firspass[1][1][2] = 3
4372 11:37:33.681882 rx_lastpass[1][1][2] = 34
4373 11:37:33.685366 rx_firspass[1][1][3] = -2
4374 11:37:33.685489 rx_lastpass[1][1][3] = 33
4375 11:37:33.688443 rx_firspass[1][1][4] = 4
4376 11:37:33.691894 rx_lastpass[1][1][4] = 39
4377 11:37:33.692065 rx_firspass[1][1][5] = 5
4378 11:37:33.694871 rx_lastpass[1][1][5] = 40
4379 11:37:33.698462 rx_firspass[1][1][6] = 6
4380 11:37:33.701621 rx_lastpass[1][1][6] = 40
4381 11:37:33.701773 rx_firspass[1][1][7] = 3
4382 11:37:33.705028 rx_lastpass[1][1][7] = 38
4383 11:37:33.708188 rx_firspass[1][1][8] = -1
4384 11:37:33.708350 rx_lastpass[1][1][8] = 35
4385 11:37:33.711402 rx_firspass[1][1][9] = -3
4386 11:37:33.714855 rx_lastpass[1][1][9] = 33
4387 11:37:33.718029 rx_firspass[1][1][10] = 3
4388 11:37:33.718159 rx_lastpass[1][1][10] = 38
4389 11:37:33.721453 rx_firspass[1][1][11] = 3
4390 11:37:33.724592 rx_lastpass[1][1][11] = 38
4391 11:37:33.727798 rx_firspass[1][1][12] = 3
4392 11:37:33.727930 rx_lastpass[1][1][12] = 37
4393 11:37:33.730785 rx_firspass[1][1][13] = 3
4394 11:37:33.734076 rx_lastpass[1][1][13] = 39
4395 11:37:33.737585 rx_firspass[1][1][14] = 4
4396 11:37:33.737672 rx_lastpass[1][1][14] = 40
4397 11:37:33.740536 rx_firspass[1][1][15] = -4
4398 11:37:33.744087 rx_lastpass[1][1][15] = 31
4399 11:37:33.744174 dump params clk_delay
4400 11:37:33.747414 clk_delay[0] = -1
4401 11:37:33.747519 clk_delay[1] = 0
4402 11:37:33.750639 dump params dqs_delay
4403 11:37:33.753926 dqs_delay[0][0] = -1
4404 11:37:33.754044 dqs_delay[0][1] = 0
4405 11:37:33.757088 dqs_delay[1][0] = 0
4406 11:37:33.757173 dqs_delay[1][1] = -1
4407 11:37:33.760639 dump params delay_cell_unit = 744
4408 11:37:33.763797 dump source = 0x0
4409 11:37:33.763882 dump params frequency:1200
4410 11:37:33.767011 dump params rank number:2
4411 11:37:33.767098
4412 11:37:33.770347 dump params write leveling
4413 11:37:33.773606 write leveling[0][0][0] = 0x0
4414 11:37:33.776718 write leveling[0][0][1] = 0x0
4415 11:37:33.776828 write leveling[0][1][0] = 0x0
4416 11:37:33.780049 write leveling[0][1][1] = 0x0
4417 11:37:33.783338 write leveling[1][0][0] = 0x0
4418 11:37:33.786438 write leveling[1][0][1] = 0x0
4419 11:37:33.789993 write leveling[1][1][0] = 0x0
4420 11:37:33.790074 write leveling[1][1][1] = 0x0
4421 11:37:33.793043 dump params cbt_cs
4422 11:37:33.796576 cbt_cs[0][0] = 0x0
4423 11:37:33.796657 cbt_cs[0][1] = 0x0
4424 11:37:33.799607 cbt_cs[1][0] = 0x0
4425 11:37:33.799693 cbt_cs[1][1] = 0x0
4426 11:37:33.802763 dump params cbt_mr12
4427 11:37:33.802873 cbt_mr12[0][0] = 0x0
4428 11:37:33.806344 cbt_mr12[0][1] = 0x0
4429 11:37:33.806432 cbt_mr12[1][0] = 0x0
4430 11:37:33.809561 cbt_mr12[1][1] = 0x0
4431 11:37:33.812710 dump params tx window
4432 11:37:33.812805 tx_center_min[0][0][0] = 0
4433 11:37:33.816117 tx_center_max[0][0][0] = 0
4434 11:37:33.819350 tx_center_min[0][0][1] = 0
4435 11:37:33.822416 tx_center_max[0][0][1] = 0
4436 11:37:33.822497 tx_center_min[0][1][0] = 0
4437 11:37:33.825950 tx_center_max[0][1][0] = 0
4438 11:37:33.829037 tx_center_min[0][1][1] = 0
4439 11:37:33.832308 tx_center_max[0][1][1] = 0
4440 11:37:33.832397 tx_center_min[1][0][0] = 0
4441 11:37:33.835912 tx_center_max[1][0][0] = 0
4442 11:37:33.839137 tx_center_min[1][0][1] = 0
4443 11:37:33.842415 tx_center_max[1][0][1] = 0
4444 11:37:33.842505 tx_center_min[1][1][0] = 0
4445 11:37:33.845617 tx_center_max[1][1][0] = 0
4446 11:37:33.848896 tx_center_min[1][1][1] = 0
4447 11:37:33.851885 tx_center_max[1][1][1] = 0
4448 11:37:33.851972 dump params tx window
4449 11:37:33.855504 tx_win_center[0][0][0] = 0
4450 11:37:33.858769 tx_first_pass[0][0][0] = 0
4451 11:37:33.858854 tx_last_pass[0][0][0] = 0
4452 11:37:33.861817 tx_win_center[0][0][1] = 0
4453 11:37:33.865266 tx_first_pass[0][0][1] = 0
4454 11:37:33.868468 tx_last_pass[0][0][1] = 0
4455 11:37:33.868547 tx_win_center[0][0][2] = 0
4456 11:37:33.871655 tx_first_pass[0][0][2] = 0
4457 11:37:33.875021 tx_last_pass[0][0][2] = 0
4458 11:37:33.878217 tx_win_center[0][0][3] = 0
4459 11:37:33.878298 tx_first_pass[0][0][3] = 0
4460 11:37:33.881485 tx_last_pass[0][0][3] = 0
4461 11:37:33.884698 tx_win_center[0][0][4] = 0
4462 11:37:33.887913 tx_first_pass[0][0][4] = 0
4463 11:37:33.887999 tx_last_pass[0][0][4] = 0
4464 11:37:33.891208 tx_win_center[0][0][5] = 0
4465 11:37:33.894440 tx_first_pass[0][0][5] = 0
4466 11:37:33.894519 tx_last_pass[0][0][5] = 0
4467 11:37:33.897703 tx_win_center[0][0][6] = 0
4468 11:37:33.901086 tx_first_pass[0][0][6] = 0
4469 11:37:33.904498 tx_last_pass[0][0][6] = 0
4470 11:37:33.904576 tx_win_center[0][0][7] = 0
4471 11:37:33.907709 tx_first_pass[0][0][7] = 0
4472 11:37:33.910713 tx_last_pass[0][0][7] = 0
4473 11:37:33.914253 tx_win_center[0][0][8] = 0
4474 11:37:33.914330 tx_first_pass[0][0][8] = 0
4475 11:37:33.917396 tx_last_pass[0][0][8] = 0
4476 11:37:33.920816 tx_win_center[0][0][9] = 0
4477 11:37:33.924059 tx_first_pass[0][0][9] = 0
4478 11:37:33.924153 tx_last_pass[0][0][9] = 0
4479 11:37:33.927093 tx_win_center[0][0][10] = 0
4480 11:37:33.930570 tx_first_pass[0][0][10] = 0
4481 11:37:33.933653 tx_last_pass[0][0][10] = 0
4482 11:37:33.933733 tx_win_center[0][0][11] = 0
4483 11:37:33.937236 tx_first_pass[0][0][11] = 0
4484 11:37:33.940284 tx_last_pass[0][0][11] = 0
4485 11:37:33.943655 tx_win_center[0][0][12] = 0
4486 11:37:33.943733 tx_first_pass[0][0][12] = 0
4487 11:37:33.946892 tx_last_pass[0][0][12] = 0
4488 11:37:33.950530 tx_win_center[0][0][13] = 0
4489 11:37:33.953463 tx_first_pass[0][0][13] = 0
4490 11:37:33.953555 tx_last_pass[0][0][13] = 0
4491 11:37:33.956524 tx_win_center[0][0][14] = 0
4492 11:37:33.959757 tx_first_pass[0][0][14] = 0
4493 11:37:33.963179 tx_last_pass[0][0][14] = 0
4494 11:37:33.966527 tx_win_center[0][0][15] = 0
4495 11:37:33.966625 tx_first_pass[0][0][15] = 0
4496 11:37:33.970027 tx_last_pass[0][0][15] = 0
4497 11:37:33.973160 tx_win_center[0][1][0] = 0
4498 11:37:33.976266 tx_first_pass[0][1][0] = 0
4499 11:37:33.976345 tx_last_pass[0][1][0] = 0
4500 11:37:33.979702 tx_win_center[0][1][1] = 0
4501 11:37:33.982971 tx_first_pass[0][1][1] = 0
4502 11:37:33.983055 tx_last_pass[0][1][1] = 0
4503 11:37:33.985978 tx_win_center[0][1][2] = 0
4504 11:37:33.989520 tx_first_pass[0][1][2] = 0
4505 11:37:33.992656 tx_last_pass[0][1][2] = 0
4506 11:37:33.992754 tx_win_center[0][1][3] = 0
4507 11:37:33.995986 tx_first_pass[0][1][3] = 0
4508 11:37:33.999111 tx_last_pass[0][1][3] = 0
4509 11:37:34.002576 tx_win_center[0][1][4] = 0
4510 11:37:34.002656 tx_first_pass[0][1][4] = 0
4511 11:37:34.005854 tx_last_pass[0][1][4] = 0
4512 11:37:34.008919 tx_win_center[0][1][5] = 0
4513 11:37:34.012291 tx_first_pass[0][1][5] = 0
4514 11:37:34.012379 tx_last_pass[0][1][5] = 0
4515 11:37:34.015476 tx_win_center[0][1][6] = 0
4516 11:37:34.018961 tx_first_pass[0][1][6] = 0
4517 11:37:34.022083 tx_last_pass[0][1][6] = 0
4518 11:37:34.022161 tx_win_center[0][1][7] = 0
4519 11:37:34.025541 tx_first_pass[0][1][7] = 0
4520 11:37:34.028649 tx_last_pass[0][1][7] = 0
4521 11:37:34.028725 tx_win_center[0][1][8] = 0
4522 11:37:34.031968 tx_first_pass[0][1][8] = 0
4523 11:37:34.035047 tx_last_pass[0][1][8] = 0
4524 11:37:34.038447 tx_win_center[0][1][9] = 0
4525 11:37:34.038525 tx_first_pass[0][1][9] = 0
4526 11:37:34.041554 tx_last_pass[0][1][9] = 0
4527 11:37:34.045092 tx_win_center[0][1][10] = 0
4528 11:37:34.048209 tx_first_pass[0][1][10] = 0
4529 11:37:34.048313 tx_last_pass[0][1][10] = 0
4530 11:37:34.051384 tx_win_center[0][1][11] = 0
4531 11:37:34.054717 tx_first_pass[0][1][11] = 0
4532 11:37:34.058015 tx_last_pass[0][1][11] = 0
4533 11:37:34.061243 tx_win_center[0][1][12] = 0
4534 11:37:34.061330 tx_first_pass[0][1][12] = 0
4535 11:37:34.064474 tx_last_pass[0][1][12] = 0
4536 11:37:34.067818 tx_win_center[0][1][13] = 0
4537 11:37:34.071252 tx_first_pass[0][1][13] = 0
4538 11:37:34.071358 tx_last_pass[0][1][13] = 0
4539 11:37:34.074570 tx_win_center[0][1][14] = 0
4540 11:37:34.078040 tx_first_pass[0][1][14] = 0
4541 11:37:34.081040 tx_last_pass[0][1][14] = 0
4542 11:37:34.081120 tx_win_center[0][1][15] = 0
4543 11:37:34.084498 tx_first_pass[0][1][15] = 0
4544 11:37:34.087640 tx_last_pass[0][1][15] = 0
4545 11:37:34.090987 tx_win_center[1][0][0] = 0
4546 11:37:34.091067 tx_first_pass[1][0][0] = 0
4547 11:37:34.094170 tx_last_pass[1][0][0] = 0
4548 11:37:34.097339 tx_win_center[1][0][1] = 0
4549 11:37:34.100521 tx_first_pass[1][0][1] = 0
4550 11:37:34.100602 tx_last_pass[1][0][1] = 0
4551 11:37:34.103830 tx_win_center[1][0][2] = 0
4552 11:37:34.107316 tx_first_pass[1][0][2] = 0
4553 11:37:34.110377 tx_last_pass[1][0][2] = 0
4554 11:37:34.110458 tx_win_center[1][0][3] = 0
4555 11:37:34.113675 tx_first_pass[1][0][3] = 0
4556 11:37:34.117188 tx_last_pass[1][0][3] = 0
4557 11:37:34.120182 tx_win_center[1][0][4] = 0
4558 11:37:34.120270 tx_first_pass[1][0][4] = 0
4559 11:37:34.123715 tx_last_pass[1][0][4] = 0
4560 11:37:34.126890 tx_win_center[1][0][5] = 0
4561 11:37:34.126968 tx_first_pass[1][0][5] = 0
4562 11:37:34.129954 tx_last_pass[1][0][5] = 0
4563 11:37:34.133288 tx_win_center[1][0][6] = 0
4564 11:37:34.136658 tx_first_pass[1][0][6] = 0
4565 11:37:34.136739 tx_last_pass[1][0][6] = 0
4566 11:37:34.139815 tx_win_center[1][0][7] = 0
4567 11:37:34.143272 tx_first_pass[1][0][7] = 0
4568 11:37:34.146365 tx_last_pass[1][0][7] = 0
4569 11:37:34.146451 tx_win_center[1][0][8] = 0
4570 11:37:34.149908 tx_first_pass[1][0][8] = 0
4571 11:37:34.153246 tx_last_pass[1][0][8] = 0
4572 11:37:34.156365 tx_win_center[1][0][9] = 0
4573 11:37:34.156443 tx_first_pass[1][0][9] = 0
4574 11:37:34.159411 tx_last_pass[1][0][9] = 0
4575 11:37:34.162808 tx_win_center[1][0][10] = 0
4576 11:37:34.166293 tx_first_pass[1][0][10] = 0
4577 11:37:34.166370 tx_last_pass[1][0][10] = 0
4578 11:37:34.169575 tx_win_center[1][0][11] = 0
4579 11:37:34.172480 tx_first_pass[1][0][11] = 0
4580 11:37:34.176084 tx_last_pass[1][0][11] = 0
4581 11:37:34.176172 tx_win_center[1][0][12] = 0
4582 11:37:34.179520 tx_first_pass[1][0][12] = 0
4583 11:37:34.182712 tx_last_pass[1][0][12] = 0
4584 11:37:34.185865 tx_win_center[1][0][13] = 0
4585 11:37:34.185948 tx_first_pass[1][0][13] = 0
4586 11:37:34.189285 tx_last_pass[1][0][13] = 0
4587 11:37:34.192398 tx_win_center[1][0][14] = 0
4588 11:37:34.195929 tx_first_pass[1][0][14] = 0
4589 11:37:34.196013 tx_last_pass[1][0][14] = 0
4590 11:37:34.198930 tx_win_center[1][0][15] = 0
4591 11:37:34.202300 tx_first_pass[1][0][15] = 0
4592 11:37:34.205380 tx_last_pass[1][0][15] = 0
4593 11:37:34.208881 tx_win_center[1][1][0] = 0
4594 11:37:34.208965 tx_first_pass[1][1][0] = 0
4595 11:37:34.212169 tx_last_pass[1][1][0] = 0
4596 11:37:34.215285 tx_win_center[1][1][1] = 0
4597 11:37:34.215379 tx_first_pass[1][1][1] = 0
4598 11:37:34.218514 tx_last_pass[1][1][1] = 0
4599 11:37:34.221746 tx_win_center[1][1][2] = 0
4600 11:37:34.224890 tx_first_pass[1][1][2] = 0
4601 11:37:34.224977 tx_last_pass[1][1][2] = 0
4602 11:37:34.228359 tx_win_center[1][1][3] = 0
4603 11:37:34.231496 tx_first_pass[1][1][3] = 0
4604 11:37:34.234868 tx_last_pass[1][1][3] = 0
4605 11:37:34.234952 tx_win_center[1][1][4] = 0
4606 11:37:34.238086 tx_first_pass[1][1][4] = 0
4607 11:37:34.241533 tx_last_pass[1][1][4] = 0
4608 11:37:34.244708 tx_win_center[1][1][5] = 0
4609 11:37:34.244792 tx_first_pass[1][1][5] = 0
4610 11:37:34.247921 tx_last_pass[1][1][5] = 0
4611 11:37:34.251360 tx_win_center[1][1][6] = 0
4612 11:37:34.254567 tx_first_pass[1][1][6] = 0
4613 11:37:34.254650 tx_last_pass[1][1][6] = 0
4614 11:37:34.257984 tx_win_center[1][1][7] = 0
4615 11:37:34.261218 tx_first_pass[1][1][7] = 0
4616 11:37:34.261301 tx_last_pass[1][1][7] = 0
4617 11:37:34.264402 tx_win_center[1][1][8] = 0
4618 11:37:34.267787 tx_first_pass[1][1][8] = 0
4619 11:37:34.270960 tx_last_pass[1][1][8] = 0
4620 11:37:34.271044 tx_win_center[1][1][9] = 0
4621 11:37:34.274401 tx_first_pass[1][1][9] = 0
4622 11:37:34.277319 tx_last_pass[1][1][9] = 0
4623 11:37:34.280693 tx_win_center[1][1][10] = 0
4624 11:37:34.280783 tx_first_pass[1][1][10] = 0
4625 11:37:34.284092 tx_last_pass[1][1][10] = 0
4626 11:37:34.287175 tx_win_center[1][1][11] = 0
4627 11:37:34.290734 tx_first_pass[1][1][11] = 0
4628 11:37:34.290817 tx_last_pass[1][1][11] = 0
4629 11:37:34.293913 tx_win_center[1][1][12] = 0
4630 11:37:34.297396 tx_first_pass[1][1][12] = 0
4631 11:37:34.300493 tx_last_pass[1][1][12] = 0
4632 11:37:34.303640 tx_win_center[1][1][13] = 0
4633 11:37:34.303762 tx_first_pass[1][1][13] = 0
4634 11:37:34.306918 tx_last_pass[1][1][13] = 0
4635 11:37:34.310120 tx_win_center[1][1][14] = 0
4636 11:37:34.313544 tx_first_pass[1][1][14] = 0
4637 11:37:34.313652 tx_last_pass[1][1][14] = 0
4638 11:37:34.316637 tx_win_center[1][1][15] = 0
4639 11:37:34.320030 tx_first_pass[1][1][15] = 0
4640 11:37:34.323193 tx_last_pass[1][1][15] = 0
4641 11:37:34.323276 dump params rx window
4642 11:37:34.326605 rx_firspass[0][0][0] = 0
4643 11:37:34.329887 rx_lastpass[0][0][0] = 0
4644 11:37:34.329977 rx_firspass[0][0][1] = 0
4645 11:37:34.332966 rx_lastpass[0][0][1] = 0
4646 11:37:34.336599 rx_firspass[0][0][2] = 0
4647 11:37:34.336696 rx_lastpass[0][0][2] = 0
4648 11:37:34.339856 rx_firspass[0][0][3] = 0
4649 11:37:34.343213 rx_lastpass[0][0][3] = 0
4650 11:37:34.343353 rx_firspass[0][0][4] = 0
4651 11:37:34.346160 rx_lastpass[0][0][4] = 0
4652 11:37:34.349766 rx_firspass[0][0][5] = 0
4653 11:37:34.352953 rx_lastpass[0][0][5] = 0
4654 11:37:34.353107 rx_firspass[0][0][6] = 0
4655 11:37:34.356167 rx_lastpass[0][0][6] = 0
4656 11:37:34.359492 rx_firspass[0][0][7] = 0
4657 11:37:34.359665 rx_lastpass[0][0][7] = 0
4658 11:37:34.362685 rx_firspass[0][0][8] = 0
4659 11:37:34.366139 rx_lastpass[0][0][8] = 0
4660 11:37:34.366343 rx_firspass[0][0][9] = 0
4661 11:37:34.369535 rx_lastpass[0][0][9] = 0
4662 11:37:34.372833 rx_firspass[0][0][10] = 0
4663 11:37:34.375935 rx_lastpass[0][0][10] = 0
4664 11:37:34.376255 rx_firspass[0][0][11] = 0
4665 11:37:34.379335 rx_lastpass[0][0][11] = 0
4666 11:37:34.382323 rx_firspass[0][0][12] = 0
4667 11:37:34.385824 rx_lastpass[0][0][12] = 0
4668 11:37:34.386213 rx_firspass[0][0][13] = 0
4669 11:37:34.389050 rx_lastpass[0][0][13] = 0
4670 11:37:34.392430 rx_firspass[0][0][14] = 0
4671 11:37:34.392819 rx_lastpass[0][0][14] = 0
4672 11:37:34.395604 rx_firspass[0][0][15] = 0
4673 11:37:34.398932 rx_lastpass[0][0][15] = 0
4674 11:37:34.402034 rx_firspass[0][1][0] = 0
4675 11:37:34.402420 rx_lastpass[0][1][0] = 0
4676 11:37:34.405626 rx_firspass[0][1][1] = 0
4677 11:37:34.408873 rx_lastpass[0][1][1] = 0
4678 11:37:34.409258 rx_firspass[0][1][2] = 0
4679 11:37:34.412088 rx_lastpass[0][1][2] = 0
4680 11:37:34.415157 rx_firspass[0][1][3] = 0
4681 11:37:34.415586 rx_lastpass[0][1][3] = 0
4682 11:37:34.418257 rx_firspass[0][1][4] = 0
4683 11:37:34.421457 rx_lastpass[0][1][4] = 0
4684 11:37:34.424859 rx_firspass[0][1][5] = 0
4685 11:37:34.425254 rx_lastpass[0][1][5] = 0
4686 11:37:34.428388 rx_firspass[0][1][6] = 0
4687 11:37:34.431366 rx_lastpass[0][1][6] = 0
4688 11:37:34.431908 rx_firspass[0][1][7] = 0
4689 11:37:34.434660 rx_lastpass[0][1][7] = 0
4690 11:37:34.438056 rx_firspass[0][1][8] = 0
4691 11:37:34.438552 rx_lastpass[0][1][8] = 0
4692 11:37:34.441283 rx_firspass[0][1][9] = 0
4693 11:37:34.444705 rx_lastpass[0][1][9] = 0
4694 11:37:34.448013 rx_firspass[0][1][10] = 0
4695 11:37:34.448488 rx_lastpass[0][1][10] = 0
4696 11:37:34.451093 rx_firspass[0][1][11] = 0
4697 11:37:34.454489 rx_lastpass[0][1][11] = 0
4698 11:37:34.454940 rx_firspass[0][1][12] = 0
4699 11:37:34.457756 rx_lastpass[0][1][12] = 0
4700 11:37:34.460914 rx_firspass[0][1][13] = 0
4701 11:37:34.464324 rx_lastpass[0][1][13] = 0
4702 11:37:34.464819 rx_firspass[0][1][14] = 0
4703 11:37:34.467336 rx_lastpass[0][1][14] = 0
4704 11:37:34.470709 rx_firspass[0][1][15] = 0
4705 11:37:34.474053 rx_lastpass[0][1][15] = 0
4706 11:37:34.474519 rx_firspass[1][0][0] = 0
4707 11:37:34.477198 rx_lastpass[1][0][0] = 0
4708 11:37:34.480706 rx_firspass[1][0][1] = 0
4709 11:37:34.481151 rx_lastpass[1][0][1] = 0
4710 11:37:34.483694 rx_firspass[1][0][2] = 0
4711 11:37:34.487210 rx_lastpass[1][0][2] = 0
4712 11:37:34.487670 rx_firspass[1][0][3] = 0
4713 11:37:34.490372 rx_lastpass[1][0][3] = 0
4714 11:37:34.493816 rx_firspass[1][0][4] = 0
4715 11:37:34.497225 rx_lastpass[1][0][4] = 0
4716 11:37:34.497578 rx_firspass[1][0][5] = 0
4717 11:37:34.500288 rx_lastpass[1][0][5] = 0
4718 11:37:34.503597 rx_firspass[1][0][6] = 0
4719 11:37:34.503953 rx_lastpass[1][0][6] = 0
4720 11:37:34.506694 rx_firspass[1][0][7] = 0
4721 11:37:34.510139 rx_lastpass[1][0][7] = 0
4722 11:37:34.510495 rx_firspass[1][0][8] = 0
4723 11:37:34.513367 rx_lastpass[1][0][8] = 0
4724 11:37:34.516376 rx_firspass[1][0][9] = 0
4725 11:37:34.516760 rx_lastpass[1][0][9] = 0
4726 11:37:34.519899 rx_firspass[1][0][10] = 0
4727 11:37:34.522976 rx_lastpass[1][0][10] = 0
4728 11:37:34.526204 rx_firspass[1][0][11] = 0
4729 11:37:34.526558 rx_lastpass[1][0][11] = 0
4730 11:37:34.529605 rx_firspass[1][0][12] = 0
4731 11:37:34.532868 rx_lastpass[1][0][12] = 0
4732 11:37:34.536368 rx_firspass[1][0][13] = 0
4733 11:37:34.536724 rx_lastpass[1][0][13] = 0
4734 11:37:34.539513 rx_firspass[1][0][14] = 0
4735 11:37:34.542841 rx_lastpass[1][0][14] = 0
4736 11:37:34.543201 rx_firspass[1][0][15] = 0
4737 11:37:34.546205 rx_lastpass[1][0][15] = 0
4738 11:37:34.549400 rx_firspass[1][1][0] = 0
4739 11:37:34.552544 rx_lastpass[1][1][0] = 0
4740 11:37:34.552899 rx_firspass[1][1][1] = 0
4741 11:37:34.555931 rx_lastpass[1][1][1] = 0
4742 11:37:34.558975 rx_firspass[1][1][2] = 0
4743 11:37:34.559330 rx_lastpass[1][1][2] = 0
4744 11:37:34.562548 rx_firspass[1][1][3] = 0
4745 11:37:34.565604 rx_lastpass[1][1][3] = 0
4746 11:37:34.565959 rx_firspass[1][1][4] = 0
4747 11:37:34.569143 rx_lastpass[1][1][4] = 0
4748 11:37:34.572355 rx_firspass[1][1][5] = 0
4749 11:37:34.575689 rx_lastpass[1][1][5] = 0
4750 11:37:34.576204 rx_firspass[1][1][6] = 0
4751 11:37:34.578829 rx_lastpass[1][1][6] = 0
4752 11:37:34.582014 rx_firspass[1][1][7] = 0
4753 11:37:34.582363 rx_lastpass[1][1][7] = 0
4754 11:37:34.585514 rx_firspass[1][1][8] = 0
4755 11:37:34.588697 rx_lastpass[1][1][8] = 0
4756 11:37:34.589137 rx_firspass[1][1][9] = 0
4757 11:37:34.592189 rx_lastpass[1][1][9] = 0
4758 11:37:34.595346 rx_firspass[1][1][10] = 0
4759 11:37:34.598328 rx_lastpass[1][1][10] = 0
4760 11:37:34.598753 rx_firspass[1][1][11] = 0
4761 11:37:34.601813 rx_lastpass[1][1][11] = 0
4762 11:37:34.604957 rx_firspass[1][1][12] = 0
4763 11:37:34.605304 rx_lastpass[1][1][12] = 0
4764 11:37:34.608398 rx_firspass[1][1][13] = 0
4765 11:37:34.611667 rx_lastpass[1][1][13] = 0
4766 11:37:34.614666 rx_firspass[1][1][14] = 0
4767 11:37:34.614963 rx_lastpass[1][1][14] = 0
4768 11:37:34.617992 rx_firspass[1][1][15] = 0
4769 11:37:34.621488 rx_lastpass[1][1][15] = 0
4770 11:37:34.621983 dump params clk_delay
4771 11:37:34.624711 clk_delay[0] = 0
4772 11:37:34.625056 clk_delay[1] = 0
4773 11:37:34.628114 dump params dqs_delay
4774 11:37:34.631139 dqs_delay[0][0] = 0
4775 11:37:34.631527 dqs_delay[0][1] = 0
4776 11:37:34.634466 dqs_delay[1][0] = 0
4777 11:37:34.634940 dqs_delay[1][1] = 0
4778 11:37:34.638133 dump params delay_cell_unit = 744
4779 11:37:34.641428 dump source = 0x0
4780 11:37:34.641818 dump params frequency:800
4781 11:37:34.644203 dump params rank number:2
4782 11:37:34.644557
4783 11:37:34.647615 dump params write leveling
4784 11:37:34.650887 write leveling[0][0][0] = 0x0
4785 11:37:34.651243 write leveling[0][0][1] = 0x0
4786 11:37:34.653832 write leveling[0][1][0] = 0x0
4787 11:37:34.657152 write leveling[0][1][1] = 0x0
4788 11:37:34.660544 write leveling[1][0][0] = 0x0
4789 11:37:34.663611 write leveling[1][0][1] = 0x0
4790 11:37:34.666939 write leveling[1][1][0] = 0x0
4791 11:37:34.667171 write leveling[1][1][1] = 0x0
4792 11:37:34.670210 dump params cbt_cs
4793 11:37:34.670405 cbt_cs[0][0] = 0x0
4794 11:37:34.673603 cbt_cs[0][1] = 0x0
4795 11:37:34.673783 cbt_cs[1][0] = 0x0
4796 11:37:34.676996 cbt_cs[1][1] = 0x0
4797 11:37:34.680086 dump params cbt_mr12
4798 11:37:34.680261 cbt_mr12[0][0] = 0x0
4799 11:37:34.683200 cbt_mr12[0][1] = 0x0
4800 11:37:34.683326 cbt_mr12[1][0] = 0x0
4801 11:37:34.686661 cbt_mr12[1][1] = 0x0
4802 11:37:34.686754 dump params tx window
4803 11:37:34.689812 tx_center_min[0][0][0] = 0
4804 11:37:34.693049 tx_center_max[0][0][0] = 0
4805 11:37:34.696394 tx_center_min[0][0][1] = 0
4806 11:37:34.696480 tx_center_max[0][0][1] = 0
4807 11:37:34.699450 tx_center_min[0][1][0] = 0
4808 11:37:34.702945 tx_center_max[0][1][0] = 0
4809 11:37:34.706149 tx_center_min[0][1][1] = 0
4810 11:37:34.706250 tx_center_max[0][1][1] = 0
4811 11:37:34.709598 tx_center_min[1][0][0] = 0
4812 11:37:34.712746 tx_center_max[1][0][0] = 0
4813 11:37:34.716215 tx_center_min[1][0][1] = 0
4814 11:37:34.716287 tx_center_max[1][0][1] = 0
4815 11:37:34.719249 tx_center_min[1][1][0] = 0
4816 11:37:34.722403 tx_center_max[1][1][0] = 0
4817 11:37:34.725782 tx_center_min[1][1][1] = 0
4818 11:37:34.729092 tx_center_max[1][1][1] = 0
4819 11:37:34.729179 dump params tx window
4820 11:37:34.732584 tx_win_center[0][0][0] = 0
4821 11:37:34.735535 tx_first_pass[0][0][0] = 0
4822 11:37:34.735647 tx_last_pass[0][0][0] = 0
4823 11:37:34.738834 tx_win_center[0][0][1] = 0
4824 11:37:34.742390 tx_first_pass[0][0][1] = 0
4825 11:37:34.745385 tx_last_pass[0][0][1] = 0
4826 11:37:34.745506 tx_win_center[0][0][2] = 0
4827 11:37:34.748678 tx_first_pass[0][0][2] = 0
4828 11:37:34.751784 tx_last_pass[0][0][2] = 0
4829 11:37:34.755305 tx_win_center[0][0][3] = 0
4830 11:37:34.755525 tx_first_pass[0][0][3] = 0
4831 11:37:34.758406 tx_last_pass[0][0][3] = 0
4832 11:37:34.761904 tx_win_center[0][0][4] = 0
4833 11:37:34.762141 tx_first_pass[0][0][4] = 0
4834 11:37:34.765252 tx_last_pass[0][0][4] = 0
4835 11:37:34.768530 tx_win_center[0][0][5] = 0
4836 11:37:34.771910 tx_first_pass[0][0][5] = 0
4837 11:37:34.772367 tx_last_pass[0][0][5] = 0
4838 11:37:34.775271 tx_win_center[0][0][6] = 0
4839 11:37:34.778440 tx_first_pass[0][0][6] = 0
4840 11:37:34.781684 tx_last_pass[0][0][6] = 0
4841 11:37:34.782205 tx_win_center[0][0][7] = 0
4842 11:37:34.785067 tx_first_pass[0][0][7] = 0
4843 11:37:34.788365 tx_last_pass[0][0][7] = 0
4844 11:37:34.791411 tx_win_center[0][0][8] = 0
4845 11:37:34.791971 tx_first_pass[0][0][8] = 0
4846 11:37:34.794591 tx_last_pass[0][0][8] = 0
4847 11:37:34.798033 tx_win_center[0][0][9] = 0
4848 11:37:34.801443 tx_first_pass[0][0][9] = 0
4849 11:37:34.802068 tx_last_pass[0][0][9] = 0
4850 11:37:34.804546 tx_win_center[0][0][10] = 0
4851 11:37:34.807982 tx_first_pass[0][0][10] = 0
4852 11:37:34.811090 tx_last_pass[0][0][10] = 0
4853 11:37:34.811790 tx_win_center[0][0][11] = 0
4854 11:37:34.814305 tx_first_pass[0][0][11] = 0
4855 11:37:34.817425 tx_last_pass[0][0][11] = 0
4856 11:37:34.820801 tx_win_center[0][0][12] = 0
4857 11:37:34.821310 tx_first_pass[0][0][12] = 0
4858 11:37:34.824007 tx_last_pass[0][0][12] = 0
4859 11:37:34.827336 tx_win_center[0][0][13] = 0
4860 11:37:34.830761 tx_first_pass[0][0][13] = 0
4861 11:37:34.831091 tx_last_pass[0][0][13] = 0
4862 11:37:34.833476 tx_win_center[0][0][14] = 0
4863 11:37:34.836805 tx_first_pass[0][0][14] = 0
4864 11:37:34.840356 tx_last_pass[0][0][14] = 0
4865 11:37:34.840590 tx_win_center[0][0][15] = 0
4866 11:37:34.843528 tx_first_pass[0][0][15] = 0
4867 11:37:34.846828 tx_last_pass[0][0][15] = 0
4868 11:37:34.849840 tx_win_center[0][1][0] = 0
4869 11:37:34.853387 tx_first_pass[0][1][0] = 0
4870 11:37:34.853558 tx_last_pass[0][1][0] = 0
4871 11:37:34.856395 tx_win_center[0][1][1] = 0
4872 11:37:34.859842 tx_first_pass[0][1][1] = 0
4873 11:37:34.859970 tx_last_pass[0][1][1] = 0
4874 11:37:34.863269 tx_win_center[0][1][2] = 0
4875 11:37:34.866442 tx_first_pass[0][1][2] = 0
4876 11:37:34.869561 tx_last_pass[0][1][2] = 0
4877 11:37:34.869689 tx_win_center[0][1][3] = 0
4878 11:37:34.873002 tx_first_pass[0][1][3] = 0
4879 11:37:34.876255 tx_last_pass[0][1][3] = 0
4880 11:37:34.879313 tx_win_center[0][1][4] = 0
4881 11:37:34.879459 tx_first_pass[0][1][4] = 0
4882 11:37:34.882786 tx_last_pass[0][1][4] = 0
4883 11:37:34.885912 tx_win_center[0][1][5] = 0
4884 11:37:34.889332 tx_first_pass[0][1][5] = 0
4885 11:37:34.889475 tx_last_pass[0][1][5] = 0
4886 11:37:34.892366 tx_win_center[0][1][6] = 0
4887 11:37:34.895828 tx_first_pass[0][1][6] = 0
4888 11:37:34.895964 tx_last_pass[0][1][6] = 0
4889 11:37:34.899212 tx_win_center[0][1][7] = 0
4890 11:37:34.902390 tx_first_pass[0][1][7] = 0
4891 11:37:34.905709 tx_last_pass[0][1][7] = 0
4892 11:37:34.905847 tx_win_center[0][1][8] = 0
4893 11:37:34.908839 tx_first_pass[0][1][8] = 0
4894 11:37:34.912246 tx_last_pass[0][1][8] = 0
4895 11:37:34.915343 tx_win_center[0][1][9] = 0
4896 11:37:34.915462 tx_first_pass[0][1][9] = 0
4897 11:37:34.918813 tx_last_pass[0][1][9] = 0
4898 11:37:34.922005 tx_win_center[0][1][10] = 0
4899 11:37:34.925392 tx_first_pass[0][1][10] = 0
4900 11:37:34.925503 tx_last_pass[0][1][10] = 0
4901 11:37:34.928471 tx_win_center[0][1][11] = 0
4902 11:37:34.931936 tx_first_pass[0][1][11] = 0
4903 11:37:34.934979 tx_last_pass[0][1][11] = 0
4904 11:37:34.935090 tx_win_center[0][1][12] = 0
4905 11:37:34.938294 tx_first_pass[0][1][12] = 0
4906 11:37:34.941660 tx_last_pass[0][1][12] = 0
4907 11:37:34.944736 tx_win_center[0][1][13] = 0
4908 11:37:34.947978 tx_first_pass[0][1][13] = 0
4909 11:37:34.948083 tx_last_pass[0][1][13] = 0
4910 11:37:34.951472 tx_win_center[0][1][14] = 0
4911 11:37:34.954693 tx_first_pass[0][1][14] = 0
4912 11:37:34.957801 tx_last_pass[0][1][14] = 0
4913 11:37:34.957906 tx_win_center[0][1][15] = 0
4914 11:37:34.961186 tx_first_pass[0][1][15] = 0
4915 11:37:34.964641 tx_last_pass[0][1][15] = 0
4916 11:37:34.967914 tx_win_center[1][0][0] = 0
4917 11:37:34.968017 tx_first_pass[1][0][0] = 0
4918 11:37:34.970912 tx_last_pass[1][0][0] = 0
4919 11:37:34.974430 tx_win_center[1][0][1] = 0
4920 11:37:34.977533 tx_first_pass[1][0][1] = 0
4921 11:37:34.977642 tx_last_pass[1][0][1] = 0
4922 11:37:34.981103 tx_win_center[1][0][2] = 0
4923 11:37:34.984174 tx_first_pass[1][0][2] = 0
4924 11:37:34.984281 tx_last_pass[1][0][2] = 0
4925 11:37:34.987475 tx_win_center[1][0][3] = 0
4926 11:37:34.990845 tx_first_pass[1][0][3] = 0
4927 11:37:34.993964 tx_last_pass[1][0][3] = 0
4928 11:37:34.994067 tx_win_center[1][0][4] = 0
4929 11:37:34.997173 tx_first_pass[1][0][4] = 0
4930 11:37:35.000616 tx_last_pass[1][0][4] = 0
4931 11:37:35.003753 tx_win_center[1][0][5] = 0
4932 11:37:35.003855 tx_first_pass[1][0][5] = 0
4933 11:37:35.007239 tx_last_pass[1][0][5] = 0
4934 11:37:35.010221 tx_win_center[1][0][6] = 0
4935 11:37:35.013658 tx_first_pass[1][0][6] = 0
4936 11:37:35.013766 tx_last_pass[1][0][6] = 0
4937 11:37:35.016827 tx_win_center[1][0][7] = 0
4938 11:37:35.020240 tx_first_pass[1][0][7] = 0
4939 11:37:35.023494 tx_last_pass[1][0][7] = 0
4940 11:37:35.023599 tx_win_center[1][0][8] = 0
4941 11:37:35.026762 tx_first_pass[1][0][8] = 0
4942 11:37:35.030031 tx_last_pass[1][0][8] = 0
4943 11:37:35.030137 tx_win_center[1][0][9] = 0
4944 11:37:35.033281 tx_first_pass[1][0][9] = 0
4945 11:37:35.036523 tx_last_pass[1][0][9] = 0
4946 11:37:35.039777 tx_win_center[1][0][10] = 0
4947 11:37:35.043137 tx_first_pass[1][0][10] = 0
4948 11:37:35.043214 tx_last_pass[1][0][10] = 0
4949 11:37:35.046335 tx_win_center[1][0][11] = 0
4950 11:37:35.049669 tx_first_pass[1][0][11] = 0
4951 11:37:35.052852 tx_last_pass[1][0][11] = 0
4952 11:37:35.052926 tx_win_center[1][0][12] = 0
4953 11:37:35.056212 tx_first_pass[1][0][12] = 0
4954 11:37:35.059411 tx_last_pass[1][0][12] = 0
4955 11:37:35.062795 tx_win_center[1][0][13] = 0
4956 11:37:35.062883 tx_first_pass[1][0][13] = 0
4957 11:37:35.065896 tx_last_pass[1][0][13] = 0
4958 11:37:35.069369 tx_win_center[1][0][14] = 0
4959 11:37:35.072701 tx_first_pass[1][0][14] = 0
4960 11:37:35.072786 tx_last_pass[1][0][14] = 0
4961 11:37:35.075771 tx_win_center[1][0][15] = 0
4962 11:37:35.079341 tx_first_pass[1][0][15] = 0
4963 11:37:35.082513 tx_last_pass[1][0][15] = 0
4964 11:37:35.082598 tx_win_center[1][1][0] = 0
4965 11:37:35.085560 tx_first_pass[1][1][0] = 0
4966 11:37:35.088898 tx_last_pass[1][1][0] = 0
4967 11:37:35.092448 tx_win_center[1][1][1] = 0
4968 11:37:35.092534 tx_first_pass[1][1][1] = 0
4969 11:37:35.095565 tx_last_pass[1][1][1] = 0
4970 11:37:35.098687 tx_win_center[1][1][2] = 0
4971 11:37:35.102091 tx_first_pass[1][1][2] = 0
4972 11:37:35.102175 tx_last_pass[1][1][2] = 0
4973 11:37:35.105270 tx_win_center[1][1][3] = 0
4974 11:37:35.108740 tx_first_pass[1][1][3] = 0
4975 11:37:35.112002 tx_last_pass[1][1][3] = 0
4976 11:37:35.112088 tx_win_center[1][1][4] = 0
4977 11:37:35.115248 tx_first_pass[1][1][4] = 0
4978 11:37:35.118389 tx_last_pass[1][1][4] = 0
4979 11:37:35.121971 tx_win_center[1][1][5] = 0
4980 11:37:35.122056 tx_first_pass[1][1][5] = 0
4981 11:37:35.124981 tx_last_pass[1][1][5] = 0
4982 11:37:35.128317 tx_win_center[1][1][6] = 0
4983 11:37:35.128403 tx_first_pass[1][1][6] = 0
4984 11:37:35.131570 tx_last_pass[1][1][6] = 0
4985 11:37:35.134667 tx_win_center[1][1][7] = 0
4986 11:37:35.138127 tx_first_pass[1][1][7] = 0
4987 11:37:35.138201 tx_last_pass[1][1][7] = 0
4988 11:37:35.141426 tx_win_center[1][1][8] = 0
4989 11:37:35.144516 tx_first_pass[1][1][8] = 0
4990 11:37:35.147669 tx_last_pass[1][1][8] = 0
4991 11:37:35.147744 tx_win_center[1][1][9] = 0
4992 11:37:35.151268 tx_first_pass[1][1][9] = 0
4993 11:37:35.154330 tx_last_pass[1][1][9] = 0
4994 11:37:35.157828 tx_win_center[1][1][10] = 0
4995 11:37:35.157900 tx_first_pass[1][1][10] = 0
4996 11:37:35.161015 tx_last_pass[1][1][10] = 0
4997 11:37:35.164104 tx_win_center[1][1][11] = 0
4998 11:37:35.167401 tx_first_pass[1][1][11] = 0
4999 11:37:35.167499 tx_last_pass[1][1][11] = 0
5000 11:37:35.170620 tx_win_center[1][1][12] = 0
5001 11:37:35.173771 tx_first_pass[1][1][12] = 0
5002 11:37:35.177428 tx_last_pass[1][1][12] = 0
5003 11:37:35.177508 tx_win_center[1][1][13] = 0
5004 11:37:35.180442 tx_first_pass[1][1][13] = 0
5005 11:37:35.183826 tx_last_pass[1][1][13] = 0
5006 11:37:35.187215 tx_win_center[1][1][14] = 0
5007 11:37:35.190335 tx_first_pass[1][1][14] = 0
5008 11:37:35.190438 tx_last_pass[1][1][14] = 0
5009 11:37:35.193598 tx_win_center[1][1][15] = 0
5010 11:37:35.196953 tx_first_pass[1][1][15] = 0
5011 11:37:35.200043 tx_last_pass[1][1][15] = 0
5012 11:37:35.200115 dump params rx window
5013 11:37:35.203350 rx_firspass[0][0][0] = 0
5014 11:37:35.206792 rx_lastpass[0][0][0] = 0
5015 11:37:35.206865 rx_firspass[0][0][1] = 0
5016 11:37:35.209917 rx_lastpass[0][0][1] = 0
5017 11:37:35.213361 rx_firspass[0][0][2] = 0
5018 11:37:35.213435 rx_lastpass[0][0][2] = 0
5019 11:37:35.216373 rx_firspass[0][0][3] = 0
5020 11:37:35.219770 rx_lastpass[0][0][3] = 0
5021 11:37:35.219841 rx_firspass[0][0][4] = 0
5022 11:37:35.222917 rx_lastpass[0][0][4] = 0
5023 11:37:35.226071 rx_firspass[0][0][5] = 0
5024 11:37:35.229470 rx_lastpass[0][0][5] = 0
5025 11:37:35.229567 rx_firspass[0][0][6] = 0
5026 11:37:35.232821 rx_lastpass[0][0][6] = 0
5027 11:37:35.235993 rx_firspass[0][0][7] = 0
5028 11:37:35.236067 rx_lastpass[0][0][7] = 0
5029 11:37:35.239431 rx_firspass[0][0][8] = 0
5030 11:37:35.242635 rx_lastpass[0][0][8] = 0
5031 11:37:35.242704 rx_firspass[0][0][9] = 0
5032 11:37:35.245942 rx_lastpass[0][0][9] = 0
5033 11:37:35.249104 rx_firspass[0][0][10] = 0
5034 11:37:35.252278 rx_lastpass[0][0][10] = 0
5035 11:37:35.252349 rx_firspass[0][0][11] = 0
5036 11:37:35.255463 rx_lastpass[0][0][11] = 0
5037 11:37:35.259176 rx_firspass[0][0][12] = 0
5038 11:37:35.262219 rx_lastpass[0][0][12] = 0
5039 11:37:35.262294 rx_firspass[0][0][13] = 0
5040 11:37:35.265553 rx_lastpass[0][0][13] = 0
5041 11:37:35.268671 rx_firspass[0][0][14] = 0
5042 11:37:35.268771 rx_lastpass[0][0][14] = 0
5043 11:37:35.272116 rx_firspass[0][0][15] = 0
5044 11:37:35.275535 rx_lastpass[0][0][15] = 0
5045 11:37:35.278465 rx_firspass[0][1][0] = 0
5046 11:37:35.278545 rx_lastpass[0][1][0] = 0
5047 11:37:35.281962 rx_firspass[0][1][1] = 0
5048 11:37:35.285136 rx_lastpass[0][1][1] = 0
5049 11:37:35.285236 rx_firspass[0][1][2] = 0
5050 11:37:35.288475 rx_lastpass[0][1][2] = 0
5051 11:37:35.291724 rx_firspass[0][1][3] = 0
5052 11:37:35.291797 rx_lastpass[0][1][3] = 0
5053 11:37:35.294839 rx_firspass[0][1][4] = 0
5054 11:37:35.298444 rx_lastpass[0][1][4] = 0
5055 11:37:35.301634 rx_firspass[0][1][5] = 0
5056 11:37:35.301707 rx_lastpass[0][1][5] = 0
5057 11:37:35.304972 rx_firspass[0][1][6] = 0
5058 11:37:35.308134 rx_lastpass[0][1][6] = 0
5059 11:37:35.308207 rx_firspass[0][1][7] = 0
5060 11:37:35.311347 rx_lastpass[0][1][7] = 0
5061 11:37:35.314795 rx_firspass[0][1][8] = 0
5062 11:37:35.314898 rx_lastpass[0][1][8] = 0
5063 11:37:35.317772 rx_firspass[0][1][9] = 0
5064 11:37:35.321305 rx_lastpass[0][1][9] = 0
5065 11:37:35.324360 rx_firspass[0][1][10] = 0
5066 11:37:35.324433 rx_lastpass[0][1][10] = 0
5067 11:37:35.327561 rx_firspass[0][1][11] = 0
5068 11:37:35.331067 rx_lastpass[0][1][11] = 0
5069 11:37:35.331166 rx_firspass[0][1][12] = 0
5070 11:37:35.334479 rx_lastpass[0][1][12] = 0
5071 11:37:35.337395 rx_firspass[0][1][13] = 0
5072 11:37:35.340859 rx_lastpass[0][1][13] = 0
5073 11:37:35.340947 rx_firspass[0][1][14] = 0
5074 11:37:35.344309 rx_lastpass[0][1][14] = 0
5075 11:37:35.347477 rx_firspass[0][1][15] = 0
5076 11:37:35.347581 rx_lastpass[0][1][15] = 0
5077 11:37:35.350653 rx_firspass[1][0][0] = 0
5078 11:37:35.353927 rx_lastpass[1][0][0] = 0
5079 11:37:35.357443 rx_firspass[1][0][1] = 0
5080 11:37:35.357524 rx_lastpass[1][0][1] = 0
5081 11:37:35.360388 rx_firspass[1][0][2] = 0
5082 11:37:35.363708 rx_lastpass[1][0][2] = 0
5083 11:37:35.363810 rx_firspass[1][0][3] = 0
5084 11:37:35.367160 rx_lastpass[1][0][3] = 0
5085 11:37:35.370289 rx_firspass[1][0][4] = 0
5086 11:37:35.370391 rx_lastpass[1][0][4] = 0
5087 11:37:35.373601 rx_firspass[1][0][5] = 0
5088 11:37:35.376874 rx_lastpass[1][0][5] = 0
5089 11:37:35.380269 rx_firspass[1][0][6] = 0
5090 11:37:35.380354 rx_lastpass[1][0][6] = 0
5091 11:37:35.383243 rx_firspass[1][0][7] = 0
5092 11:37:35.386594 rx_lastpass[1][0][7] = 0
5093 11:37:35.386679 rx_firspass[1][0][8] = 0
5094 11:37:35.390001 rx_lastpass[1][0][8] = 0
5095 11:37:35.393218 rx_firspass[1][0][9] = 0
5096 11:37:35.393303 rx_lastpass[1][0][9] = 0
5097 11:37:35.396395 rx_firspass[1][0][10] = 0
5098 11:37:35.399568 rx_lastpass[1][0][10] = 0
5099 11:37:35.402898 rx_firspass[1][0][11] = 0
5100 11:37:35.402983 rx_lastpass[1][0][11] = 0
5101 11:37:35.406238 rx_firspass[1][0][12] = 0
5102 11:37:35.409516 rx_lastpass[1][0][12] = 0
5103 11:37:35.409600 rx_firspass[1][0][13] = 0
5104 11:37:35.412992 rx_lastpass[1][0][13] = 0
5105 11:37:35.416072 rx_firspass[1][0][14] = 0
5106 11:37:35.419432 rx_lastpass[1][0][14] = 0
5107 11:37:35.419528 rx_firspass[1][0][15] = 0
5108 11:37:35.422827 rx_lastpass[1][0][15] = 0
5109 11:37:35.425837 rx_firspass[1][1][0] = 0
5110 11:37:35.429045 rx_lastpass[1][1][0] = 0
5111 11:37:35.429130 rx_firspass[1][1][1] = 0
5112 11:37:35.432615 rx_lastpass[1][1][1] = 0
5113 11:37:35.435679 rx_firspass[1][1][2] = 0
5114 11:37:35.435764 rx_lastpass[1][1][2] = 0
5115 11:37:35.439055 rx_firspass[1][1][3] = 0
5116 11:37:35.442461 rx_lastpass[1][1][3] = 0
5117 11:37:35.442565 rx_firspass[1][1][4] = 0
5118 11:37:35.445648 rx_lastpass[1][1][4] = 0
5119 11:37:35.448738 rx_firspass[1][1][5] = 0
5120 11:37:35.448822 rx_lastpass[1][1][5] = 0
5121 11:37:35.452270 rx_firspass[1][1][6] = 0
5122 11:37:35.455366 rx_lastpass[1][1][6] = 0
5123 11:37:35.458733 rx_firspass[1][1][7] = 0
5124 11:37:35.458819 rx_lastpass[1][1][7] = 0
5125 11:37:35.461765 rx_firspass[1][1][8] = 0
5126 11:37:35.465286 rx_lastpass[1][1][8] = 0
5127 11:37:35.465373 rx_firspass[1][1][9] = 0
5128 11:37:35.468502 rx_lastpass[1][1][9] = 0
5129 11:37:35.471650 rx_firspass[1][1][10] = 0
5130 11:37:35.474955 rx_lastpass[1][1][10] = 0
5131 11:37:35.475086 rx_firspass[1][1][11] = 0
5132 11:37:35.478415 rx_lastpass[1][1][11] = 0
5133 11:37:35.481542 rx_firspass[1][1][12] = 0
5134 11:37:35.481688 rx_lastpass[1][1][12] = 0
5135 11:37:35.484785 rx_firspass[1][1][13] = 0
5136 11:37:35.488270 rx_lastpass[1][1][13] = 0
5137 11:37:35.491370 rx_firspass[1][1][14] = 0
5138 11:37:35.491558 rx_lastpass[1][1][14] = 0
5139 11:37:35.494836 rx_firspass[1][1][15] = 0
5140 11:37:35.498143 rx_lastpass[1][1][15] = 0
5141 11:37:35.498362 dump params clk_delay
5142 11:37:35.501279 clk_delay[0] = 0
5143 11:37:35.501512 clk_delay[1] = 0
5144 11:37:35.504805 dump params dqs_delay
5145 11:37:35.505102 dqs_delay[0][0] = 0
5146 11:37:35.507944 dqs_delay[0][1] = 0
5147 11:37:35.511144 dqs_delay[1][0] = 0
5148 11:37:35.511508 dqs_delay[1][1] = 0
5149 11:37:35.514747 dump params delay_cell_unit = 744
5150 11:37:35.517786 mt_set_emi_preloader end
5151 11:37:35.521232 [mt_mem_init] dram size: 0x100000000, rank number: 2
5152 11:37:35.527661 [complex_mem_test] start addr:0x40000000, len:20480
5153 11:37:35.563103 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5154 11:37:35.569356 [complex_mem_test] start addr:0x80000000, len:20480
5155 11:37:35.605465 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5156 11:37:35.611873 [complex_mem_test] start addr:0xc0000000, len:20480
5157 11:37:35.647759 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5158 11:37:35.654064 [complex_mem_test] start addr:0x56000000, len:8192
5159 11:37:35.670700 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5160 11:37:35.674107 ddr_geometry:1
5161 11:37:35.677229 [complex_mem_test] start addr:0x80000000, len:8192
5162 11:37:35.694486 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5163 11:37:35.697959 dram_init: dram init end (result: 0)
5164 11:37:35.704591 Successfully loaded DRAM blobs and ran DRAM calibration
5165 11:37:35.714190 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5166 11:37:35.714728 CBMEM:
5167 11:37:35.717355 IMD: root @ 00000000fffff000 254 entries.
5168 11:37:35.720607 IMD: root @ 00000000ffffec00 62 entries.
5169 11:37:35.727329 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5170 11:37:35.733891 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5171 11:37:35.737379 in-header: 03 a1 00 00 08 00 00 00
5172 11:37:35.740566 in-data: 84 60 60 10 00 00 00 00
5173 11:37:35.743985 Chrome EC: clear events_b mask to 0x0000000020004000
5174 11:37:35.750562 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5175 11:37:35.754189 in-header: 03 fd 00 00 00 00 00 00
5176 11:37:35.757214 in-data:
5177 11:37:35.760732 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5178 11:37:35.763759 CBFS @ 21000 size 3d4000
5179 11:37:35.767264 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5180 11:37:35.770180 CBFS: Locating 'fallback/ramstage'
5181 11:37:35.773503 CBFS: Found @ offset 10d40 size d563
5182 11:37:35.796538 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5183 11:37:35.808480 Accumulated console time in romstage 13635 ms
5184 11:37:35.808863
5185 11:37:35.809156
5186 11:37:35.818439 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5187 11:37:35.821880 ARM64: Exception handlers installed.
5188 11:37:35.822403 ARM64: Testing exception
5189 11:37:35.825189 ARM64: Done test exception
5190 11:37:35.828236 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5191 11:37:35.831731 Manufacturer: ef
5192 11:37:35.838242 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5193 11:37:35.841410 WARNING: RO_VPD is uninitialized or empty.
5194 11:37:35.844504 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5195 11:37:35.847934 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5196 11:37:35.858315 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5197 11:37:35.861645 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5198 11:37:35.868338 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5199 11:37:35.868736 Enumerating buses...
5200 11:37:35.874700 Show all devs... Before device enumeration.
5201 11:37:35.875095 Root Device: enabled 1
5202 11:37:35.878010 CPU_CLUSTER: 0: enabled 1
5203 11:37:35.881117 CPU: 00: enabled 1
5204 11:37:35.881509 Compare with tree...
5205 11:37:35.884666 Root Device: enabled 1
5206 11:37:35.885057 CPU_CLUSTER: 0: enabled 1
5207 11:37:35.887561 CPU: 00: enabled 1
5208 11:37:35.890922 Root Device scanning...
5209 11:37:35.894158 root_dev_scan_bus for Root Device
5210 11:37:35.894592 CPU_CLUSTER: 0 enabled
5211 11:37:35.897519 root_dev_scan_bus for Root Device done
5212 11:37:35.903873 scan_bus: scanning of bus Root Device took 10690 usecs
5213 11:37:35.904247 done
5214 11:37:35.907388 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5215 11:37:35.910854 Allocating resources...
5216 11:37:35.913913 Reading resources...
5217 11:37:35.917084 Root Device read_resources bus 0 link: 0
5218 11:37:35.920299 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5219 11:37:35.923631 CPU: 00 missing read_resources
5220 11:37:35.926985 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5221 11:37:35.930423 Root Device read_resources bus 0 link: 0 done
5222 11:37:35.933491 Done reading resources.
5223 11:37:35.939956 Show resources in subtree (Root Device)...After reading.
5224 11:37:35.943333 Root Device child on link 0 CPU_CLUSTER: 0
5225 11:37:35.946590 CPU_CLUSTER: 0 child on link 0 CPU: 00
5226 11:37:35.953130 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5227 11:37:35.956223 CPU: 00
5228 11:37:35.956687 Setting resources...
5229 11:37:35.963092 Root Device assign_resources, bus 0 link: 0
5230 11:37:35.966303 CPU_CLUSTER: 0 missing set_resources
5231 11:37:35.969751 Root Device assign_resources, bus 0 link: 0
5232 11:37:35.970239 Done setting resources.
5233 11:37:35.976057 Show resources in subtree (Root Device)...After assigning values.
5234 11:37:35.979503 Root Device child on link 0 CPU_CLUSTER: 0
5235 11:37:35.982585 CPU_CLUSTER: 0 child on link 0 CPU: 00
5236 11:37:35.992576 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5237 11:37:35.992940 CPU: 00
5238 11:37:35.995734 Done allocating resources.
5239 11:37:36.002409 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5240 11:37:36.002807 Enabling resources...
5241 11:37:36.003198 done.
5242 11:37:36.009030 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5243 11:37:36.009427 Initializing devices...
5244 11:37:36.012032 Root Device init ...
5245 11:37:36.015570 mainboard_init: Starting display init.
5246 11:37:36.018754 ADC[4]: Raw value=76192 ID=0
5247 11:37:36.041172 anx7625_power_on_init: Init interface.
5248 11:37:36.044284 anx7625_disable_pd_protocol: Disabled PD feature.
5249 11:37:36.050527 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5250 11:37:36.107826 anx7625_start_dp_work: Secure OCM version=00
5251 11:37:36.111432 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5252 11:37:36.128676 sp_tx_get_edid_block: EDID Block = 1
5253 11:37:36.245741 Extracted contents:
5254 11:37:36.248960 header: 00 ff ff ff ff ff ff 00
5255 11:37:36.252355 serial number: 06 af 5c 14 00 00 00 00 00 1a
5256 11:37:36.255563 version: 01 04
5257 11:37:36.258830 basic params: 95 1a 0e 78 02
5258 11:37:36.262308 chroma info: 99 85 95 55 56 92 28 22 50 54
5259 11:37:36.265536 established: 00 00 00
5260 11:37:36.272199 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5261 11:37:36.278492 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5262 11:37:36.281893 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5263 11:37:36.288053 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5264 11:37:36.294563 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5265 11:37:36.297795 extensions: 00
5266 11:37:36.298341 checksum: ae
5267 11:37:36.298836
5268 11:37:36.304435 Manufacturer: AUO Model 145c Serial Number 0
5269 11:37:36.304973 Made week 0 of 2016
5270 11:37:36.307591 EDID version: 1.4
5271 11:37:36.308121 Digital display
5272 11:37:36.310969 6 bits per primary color channel
5273 11:37:36.314222 DisplayPort interface
5274 11:37:36.317468 Maximum image size: 26 cm x 14 cm
5275 11:37:36.317989 Gamma: 220%
5276 11:37:36.318464 Check DPMS levels
5277 11:37:36.320808 Supported color formats: RGB 4:4:4
5278 11:37:36.327347 First detailed timing is preferred timing
5279 11:37:36.327820 Established timings supported:
5280 11:37:36.330811 Standard timings supported:
5281 11:37:36.333970 Detailed timings
5282 11:37:36.336862 Hex of detail: ce1d56ea50001a3030204600009010000018
5283 11:37:36.343546 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5284 11:37:36.346901 0556 0586 05a6 0640 hborder 0
5285 11:37:36.350128 0300 0304 030a 031a vborder 0
5286 11:37:36.353504 -hsync -vsync
5287 11:37:36.353782 Did detailed timing
5288 11:37:36.360028 Hex of detail: 0000000f0000000000000000000000000020
5289 11:37:36.363062 Manufacturer-specified data, tag 15
5290 11:37:36.366507 Hex of detail: 000000fe0041554f0a202020202020202020
5291 11:37:36.369690 ASCII string: AUO
5292 11:37:36.372921 Hex of detail: 000000fe004231313658414230312e34200a
5293 11:37:36.376468 ASCII string: B116XAB01.4
5294 11:37:36.376755 Checksum
5295 11:37:36.379477 Checksum: 0xae (valid)
5296 11:37:36.382937 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5297 11:37:36.386082 DSI data_rate: 457800000 bps
5298 11:37:36.392679 anx7625_parse_edid: set default k value to 0x3d for panel
5299 11:37:36.395820 anx7625_parse_edid: pixelclock(76300).
5300 11:37:36.399503 hactive(1366), hsync(32), hfp(48), hbp(154)
5301 11:37:36.402723 vactive(768), vsync(6), vfp(4), vbp(16)
5302 11:37:36.405704 anx7625_dsi_config: config dsi.
5303 11:37:36.414246 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5304 11:37:36.434765 anx7625_dsi_config: success to config DSI
5305 11:37:36.438064 anx7625_dp_start: MIPI phy setup OK.
5306 11:37:36.441502 [SSUSB] Setting up USB HOST controller...
5307 11:37:36.444353 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5308 11:37:36.448026 [SSUSB] phy power-on done.
5309 11:37:36.451435 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5310 11:37:36.454879 in-header: 03 fc 01 00 00 00 00 00
5311 11:37:36.455270 in-data:
5312 11:37:36.461498 handle_proto3_response: EC response with error code: 1
5313 11:37:36.461855 SPM: pcm index = 1
5314 11:37:36.467833 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5315 11:37:36.468214 CBFS @ 21000 size 3d4000
5316 11:37:36.474481 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5317 11:37:36.477949 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5318 11:37:36.481102 CBFS: Found @ offset 1e7c0 size 1026
5319 11:37:36.487718 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5320 11:37:36.490810 SPM: binary array size = 2988
5321 11:37:36.494293 SPM: version = pcm_allinone_v1.17.2_20180829
5322 11:37:36.497406 SPM binary loaded in 32 msecs
5323 11:37:36.505736 spm_kick_im_to_fetch: ptr = 000000004021eec2
5324 11:37:36.509306 spm_kick_im_to_fetch: len = 2988
5325 11:37:36.509740 SPM: spm_kick_pcm_to_run
5326 11:37:36.512442 SPM: spm_kick_pcm_to_run done
5327 11:37:36.515789 SPM: spm_init done in 52 msecs
5328 11:37:36.519544 Root Device init finished in 505257 usecs
5329 11:37:36.522652 CPU_CLUSTER: 0 init ...
5330 11:37:36.532161 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5331 11:37:36.535681 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5332 11:37:36.538784 CBFS @ 21000 size 3d4000
5333 11:37:36.542022 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5334 11:37:36.545310 CBFS: Locating 'sspm.bin'
5335 11:37:36.548776 CBFS: Found @ offset 208c0 size 41cb
5336 11:37:36.559178 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5337 11:37:36.566800 CPU_CLUSTER: 0 init finished in 42799 usecs
5338 11:37:36.567199 Devices initialized
5339 11:37:36.570372 Show all devs... After init.
5340 11:37:36.573466 Root Device: enabled 1
5341 11:37:36.573878 CPU_CLUSTER: 0: enabled 1
5342 11:37:36.576844 CPU: 00: enabled 1
5343 11:37:36.579977 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5344 11:37:36.586598 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5345 11:37:36.590088 ELOG: NV offset 0x558000 size 0x1000
5346 11:37:36.593374 read SPI 0x558000 0x1000: 1264 us, 3240 KB/s, 25.920 Mbps
5347 11:37:36.599571 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5348 11:37:36.606520 ELOG: Event(17) added with size 13 at 2024-07-17 11:37:36 UTC
5349 11:37:36.609589 out: cmd=0x121: 03 db 21 01 00 00 00 00
5350 11:37:36.612763 in-header: 03 f4 00 00 2c 00 00 00
5351 11:37:36.625947 in-data: 6d 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 40 04 01 00 06 80 00 00 b9 38 02 00 06 80 00 00 ac 21 01 00 06 80 00 00 07 ed 01 00
5352 11:37:36.628949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5353 11:37:36.632179 in-header: 03 19 00 00 08 00 00 00
5354 11:37:36.635785 in-data: a2 e0 47 00 13 00 00 00
5355 11:37:36.638671 Chrome EC: UHEPI supported
5356 11:37:36.645769 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5357 11:37:36.648602 in-header: 03 e1 00 00 08 00 00 00
5358 11:37:36.651898 in-data: 84 20 60 10 00 00 00 00
5359 11:37:36.655284 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5360 11:37:36.661660 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5361 11:37:36.664953 in-header: 03 e1 00 00 08 00 00 00
5362 11:37:36.668013 in-data: 84 20 60 10 00 00 00 00
5363 11:37:36.674683 ELOG: Event(A1) added with size 10 at 2024-07-17 11:37:36 UTC
5364 11:37:36.681220 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5365 11:37:36.684365 ELOG: Event(A0) added with size 9 at 2024-07-17 11:37:36 UTC
5366 11:37:36.690930 elog_add_boot_reason: Logged dev mode boot
5367 11:37:36.691309 Finalize devices...
5368 11:37:36.694272 Devices finalized
5369 11:37:36.697590 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5370 11:37:36.704161 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5371 11:37:36.707270 ELOG: Event(91) added with size 10 at 2024-07-17 11:37:36 UTC
5372 11:37:36.710690 Writing coreboot table at 0xffeda000
5373 11:37:36.717022 0. 0000000000114000-000000000011efff: RAMSTAGE
5374 11:37:36.720298 1. 0000000040000000-000000004023cfff: RAMSTAGE
5375 11:37:36.723556 2. 000000004023d000-00000000545fffff: RAM
5376 11:37:36.726921 3. 0000000054600000-000000005465ffff: BL31
5377 11:37:36.730257 4. 0000000054660000-00000000ffed9fff: RAM
5378 11:37:36.736733 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5379 11:37:36.739909 6. 0000000100000000-000000013fffffff: RAM
5380 11:37:36.743614 Passing 5 GPIOs to payload:
5381 11:37:36.746644 NAME | PORT | POLARITY | VALUE
5382 11:37:36.752865 write protect | 0x00000096 | low | high
5383 11:37:36.756092 EC in RW | 0x000000b1 | high | undefined
5384 11:37:36.762938 EC interrupt | 0x00000097 | low | undefined
5385 11:37:36.766116 TPM interrupt | 0x00000099 | high | undefined
5386 11:37:36.769382 speaker enable | 0x000000af | high | undefined
5387 11:37:36.772768 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5388 11:37:36.775999 in-header: 03 f7 00 00 02 00 00 00
5389 11:37:36.779423 in-data: 04 00
5390 11:37:36.779813 Board ID: 4
5391 11:37:36.782703 ADC[3]: Raw value=215048 ID=1
5392 11:37:36.783079 RAM code: 1
5393 11:37:36.785608 SKU ID: 16
5394 11:37:36.789280 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5395 11:37:36.792377 CBFS @ 21000 size 3d4000
5396 11:37:36.795777 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5397 11:37:36.802237 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 42c1
5398 11:37:36.805334 coreboot table: 940 bytes.
5399 11:37:36.808626 IMD ROOT 0. 00000000fffff000 00001000
5400 11:37:36.811951 IMD SMALL 1. 00000000ffffe000 00001000
5401 11:37:36.815208 CONSOLE 2. 00000000fffde000 00020000
5402 11:37:36.818463 FMAP 3. 00000000fffdd000 0000047c
5403 11:37:36.824886 TIME STAMP 4. 00000000fffdc000 00000910
5404 11:37:36.828208 RAMOOPS 5. 00000000ffedc000 00100000
5405 11:37:36.831443 COREBOOT 6. 00000000ffeda000 00002000
5406 11:37:36.831980 IMD small region:
5407 11:37:36.834712 IMD ROOT 0. 00000000ffffec00 00000400
5408 11:37:36.841346 VBOOT WORK 1. 00000000ffffeb00 00000100
5409 11:37:36.844667 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5410 11:37:36.847761 VPD 3. 00000000ffffea60 0000006c
5411 11:37:36.851223 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5412 11:37:36.857581 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5413 11:37:36.861036 in-header: 03 e1 00 00 08 00 00 00
5414 11:37:36.864013 in-data: 84 20 60 10 00 00 00 00
5415 11:37:36.870719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5416 11:37:36.870822 CBFS @ 21000 size 3d4000
5417 11:37:36.877071 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5418 11:37:36.880545 CBFS: Locating 'fallback/payload'
5419 11:37:36.888466 CBFS: Found @ offset dc040 size 439a0
5420 11:37:36.976348 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5421 11:37:36.979419 Checking segment from ROM address 0x0000000040003a00
5422 11:37:36.986094 Checking segment from ROM address 0x0000000040003a1c
5423 11:37:36.989554 Loading segment from ROM address 0x0000000040003a00
5424 11:37:36.992628 code (compression=0)
5425 11:37:37.002443 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5426 11:37:37.009166 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5427 11:37:37.012028 it's not compressed!
5428 11:37:37.015371 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5429 11:37:37.021881 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5430 11:37:37.030712 Loading segment from ROM address 0x0000000040003a1c
5431 11:37:37.033820 Entry Point 0x0000000080000000
5432 11:37:37.033905 Loaded segments
5433 11:37:37.040825 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5434 11:37:37.043642 Jumping to boot code at 0000000080000000(00000000ffeda000)
5435 11:37:37.053423 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5436 11:37:37.060143 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5437 11:37:37.060231 CBFS @ 21000 size 3d4000
5438 11:37:37.066611 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5439 11:37:37.069821 CBFS: Locating 'fallback/bl31'
5440 11:37:37.073003 CBFS: Found @ offset 36dc0 size 5820
5441 11:37:37.084291 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5442 11:37:37.087700 Checking segment from ROM address 0x0000000040003a00
5443 11:37:37.094014 Checking segment from ROM address 0x0000000040003a1c
5444 11:37:37.097479 Loading segment from ROM address 0x0000000040003a00
5445 11:37:37.100663 code (compression=1)
5446 11:37:37.110719 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5447 11:37:37.116945 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5448 11:37:37.117085 using LZMA
5449 11:37:37.126398 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5450 11:37:37.132813 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5451 11:37:37.136083 Loading segment from ROM address 0x0000000040003a1c
5452 11:37:37.139292 Entry Point 0x0000000054601000
5453 11:37:37.139426 Loaded segments
5454 11:37:37.142463 NOTICE: MT8183 bl31_setup
5455 11:37:37.149821 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5456 11:37:37.153291 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5457 11:37:37.156564 INFO: [DEVAPC] dump DEVAPC registers:
5458 11:37:37.166107 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5459 11:37:37.172890 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5460 11:37:37.182617 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5461 11:37:37.189187 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5462 11:37:37.199038 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5463 11:37:37.205566 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5464 11:37:37.215442 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5465 11:37:37.221827 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5466 11:37:37.231784 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5467 11:37:37.238414 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5468 11:37:37.248361 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5469 11:37:37.254613 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5470 11:37:37.264652 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5471 11:37:37.271027 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5472 11:37:37.277789 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5473 11:37:37.287387 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5474 11:37:37.294306 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5475 11:37:37.300898 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5476 11:37:37.307172 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5477 11:37:37.313878 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5478 11:37:37.323527 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5479 11:37:37.330311 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5480 11:37:37.333631 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5481 11:37:37.336638 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5482 11:37:37.340181 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5483 11:37:37.343223 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5484 11:37:37.346676 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5485 11:37:37.353209 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5486 11:37:37.356445 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5487 11:37:37.359549 WARNING: region 0:
5488 11:37:37.363005 WARNING: apc:0x168, sa:0x0, ea:0xfff
5489 11:37:37.366237 WARNING: region 1:
5490 11:37:37.369806 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5491 11:37:37.369890 WARNING: region 2:
5492 11:37:37.372749 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5493 11:37:37.376012 WARNING: region 3:
5494 11:37:37.379548 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5495 11:37:37.379649 WARNING: region 4:
5496 11:37:37.385811 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5497 11:37:37.385891 WARNING: region 5:
5498 11:37:37.388915 WARNING: apc:0x0, sa:0x0, ea:0x0
5499 11:37:37.392322 WARNING: region 6:
5500 11:37:37.395771 WARNING: apc:0x0, sa:0x0, ea:0x0
5501 11:37:37.395842 WARNING: region 7:
5502 11:37:37.399019 WARNING: apc:0x0, sa:0x0, ea:0x0
5503 11:37:37.405703 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5504 11:37:37.408813 INFO: SPM: enable SPMC mode
5505 11:37:37.412050 NOTICE: spm_boot_init() start
5506 11:37:37.415248 NOTICE: spm_boot_init() end
5507 11:37:37.418575 INFO: BL31: Initializing runtime services
5508 11:37:37.425208 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5509 11:37:37.428562 INFO: BL31: Preparing for EL3 exit to normal world
5510 11:37:37.431599 INFO: Entry point address = 0x80000000
5511 11:37:37.434763 INFO: SPSR = 0x8
5512 11:37:37.456630
5513 11:37:37.456765
5514 11:37:37.456865
5515 11:37:37.459704 Starting depthcharge on Juniper...
5516 11:37:37.459779
5517 11:37:37.460296 end: 2.2.3 depthcharge-start (duration 00:00:24) [common]
5518 11:37:37.460397 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5519 11:37:37.460482 Setting prompt string to ['jacuzzi:']
5520 11:37:37.460554 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5521 11:37:37.463035 vboot_handoff: creating legacy vboot_handoff structure
5522 11:37:37.463109
5523 11:37:37.466052 ec_init(0): CrosEC protocol v3 supported (544, 544)
5524 11:37:37.469725
5525 11:37:37.469830 Wipe memory regions:
5526 11:37:37.469923
5527 11:37:37.472833 [0x00000040000000, 0x00000054600000)
5528 11:37:37.516054
5529 11:37:37.516190 [0x00000054660000, 0x00000080000000)
5530 11:37:37.607800
5531 11:37:37.607927 [0x000000811994a0, 0x000000ffeda000)
5532 11:37:37.867824
5533 11:37:37.868272 [0x00000100000000, 0x00000140000000)
5534 11:37:38.000516
5535 11:37:38.003389 Initializing XHCI USB controller at 0x11200000.
5536 11:37:38.026762
5537 11:37:38.029862 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5538 11:37:38.029967
5539 11:37:38.030065
5540 11:37:38.030368 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5541 11:37:38.030490 Sending line: 'tftpboot 192.168.201.1 14864642/tftp-deploy-7mqfe8wa/kernel/image.itb 14864642/tftp-deploy-7mqfe8wa/kernel/cmdline '
5543 11:37:38.130966 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5544 11:37:38.131058 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5545 11:37:38.135088 jacuzzi: tftpboot 192.168.201.1 14864642/tftp-deploy-7mqfe8wa/kernel/image.itp-deploy-7mqfe8wa/kernel/cmdline
5546 11:37:38.135198
5547 11:37:38.135291 Waiting for link
5548 11:37:38.541006
5549 11:37:38.541534 R8152: Initializing
5550 11:37:38.541933
5551 11:37:38.544007 Version 9 (ocp_data = 6010)
5552 11:37:38.544333
5553 11:37:38.547255 R8152: Done initializing
5554 11:37:38.547683
5555 11:37:38.547963 Adding net device
5556 11:37:38.933085
5557 11:37:38.933646 done.
5558 11:37:38.934149
5559 11:37:38.934556 MAC: 00:e0:4c:78:85:cb
5560 11:37:38.934978
5561 11:37:38.936320 Sending DHCP discover... done.
5562 11:37:38.936733
5563 11:37:38.939719 Waiting for reply... done.
5564 11:37:38.940339
5565 11:37:38.942581 Sending DHCP request... done.
5566 11:37:38.942904
5567 11:37:38.947320 Waiting for reply... done.
5568 11:37:38.947549
5569 11:37:38.947681 My ip is 192.168.201.22
5570 11:37:38.947802
5571 11:37:38.950507 The DHCP server ip is 192.168.201.1
5572 11:37:38.950686
5573 11:37:38.957164 TFTP server IP predefined by user: 192.168.201.1
5574 11:37:38.957371
5575 11:37:38.963838 Bootfile predefined by user: 14864642/tftp-deploy-7mqfe8wa/kernel/image.itb
5576 11:37:38.964146
5577 11:37:38.967003 Sending tftp read request... done.
5578 11:37:38.967320
5579 11:37:38.973199 Waiting for the transfer...
5580 11:37:38.973691
5581 11:37:39.234635 00000000 ################################################################
5582 11:37:39.234803
5583 11:37:39.492688 00080000 ################################################################
5584 11:37:39.492809
5585 11:37:39.756489 00100000 ################################################################
5586 11:37:39.756651
5587 11:37:40.011864 00180000 ################################################################
5588 11:37:40.012002
5589 11:37:40.281171 00200000 ################################################################
5590 11:37:40.281305
5591 11:37:40.539661 00280000 ################################################################
5592 11:37:40.539823
5593 11:37:40.794402 00300000 ################################################################
5594 11:37:40.794568
5595 11:37:41.061289 00380000 ################################################################
5596 11:37:41.061446
5597 11:37:41.338989 00400000 ################################################################
5598 11:37:41.339129
5599 11:37:41.600134 00480000 ################################################################
5600 11:37:41.600267
5601 11:37:41.860165 00500000 ################################################################
5602 11:37:41.860332
5603 11:37:42.115865 00580000 ################################################################
5604 11:37:42.116022
5605 11:37:42.375728 00600000 ################################################################
5606 11:37:42.375883
5607 11:37:42.641820 00680000 ################################################################
5608 11:37:42.641961
5609 11:37:42.909936 00700000 ################################################################
5610 11:37:42.910075
5611 11:37:43.187754 00780000 ################################################################
5612 11:37:43.187889
5613 11:37:43.458335 00800000 ################################################################
5614 11:37:43.458484
5615 11:37:43.724920 00880000 ################################################################
5616 11:37:43.725063
5617 11:37:43.997533 00900000 ################################################################
5618 11:37:43.997673
5619 11:37:44.256946 00980000 ################################################################
5620 11:37:44.257086
5621 11:37:44.514203 00a00000 ################################################################
5622 11:37:44.514351
5623 11:37:44.779753 00a80000 ################################################################
5624 11:37:44.779900
5625 11:37:45.044497 00b00000 ################################################################
5626 11:37:45.044634
5627 11:37:45.322589 00b80000 ################################################################
5628 11:37:45.322725
5629 11:37:45.585989 00c00000 ################################################################
5630 11:37:45.586125
5631 11:37:45.841262 00c80000 ################################################################
5632 11:37:45.841404
5633 11:37:46.101271 00d00000 ################################################################
5634 11:37:46.101438
5635 11:37:46.367328 00d80000 ################################################################
5636 11:37:46.367501
5637 11:37:46.621137 00e00000 ################################################################
5638 11:37:46.621273
5639 11:37:46.888845 00e80000 ################################################################
5640 11:37:46.888980
5641 11:37:47.168624 00f00000 ################################################################
5642 11:37:47.168769
5643 11:37:47.440506 00f80000 ################################################################
5644 11:37:47.440645
5645 11:37:47.710595 01000000 ################################################################
5646 11:37:47.710722
5647 11:37:47.979336 01080000 ################################################################
5648 11:37:47.979482
5649 11:37:48.237180 01100000 ################################################################
5650 11:37:48.237327
5651 11:37:48.509286 01180000 ################################################################
5652 11:37:48.509443
5653 11:37:48.768746 01200000 ################################################################
5654 11:37:48.768880
5655 11:37:49.026811 01280000 ################################################################
5656 11:37:49.026930
5657 11:37:49.276002 01300000 ################################################################
5658 11:37:49.276140
5659 11:37:49.533011 01380000 ################################################################
5660 11:37:49.533168
5661 11:37:49.790013 01400000 ################################################################
5662 11:37:49.790137
5663 11:37:50.063718 01480000 ################################################################
5664 11:37:50.063840
5665 11:37:50.340613 01500000 ################################################################
5666 11:37:50.340755
5667 11:37:50.613575 01580000 ################################################################
5668 11:37:50.613717
5669 11:37:50.883132 01600000 ################################################################
5670 11:37:50.883275
5671 11:37:51.138266 01680000 ################################################################
5672 11:37:51.138402
5673 11:37:51.392331 01700000 ################################################################
5674 11:37:51.392469
5675 11:37:51.645785 01780000 ################################################################
5676 11:37:51.645923
5677 11:37:51.905307 01800000 ################################################################
5678 11:37:51.905446
5679 11:37:52.179550 01880000 ################################################################
5680 11:37:52.179720
5681 11:37:52.466742 01900000 ################################################################
5682 11:37:52.466883
5683 11:37:52.753425 01980000 ################################################################
5684 11:37:52.753544
5685 11:37:53.042153 01a00000 ################################################################
5686 11:37:53.042280
5687 11:37:53.305885 01a80000 ################################################################
5688 11:37:53.306043
5689 11:37:53.581211 01b00000 ################################################################
5690 11:37:53.581365
5691 11:37:53.862277 01b80000 ################################################################
5692 11:37:53.862401
5693 11:37:54.130459 01c00000 ################################################################
5694 11:37:54.130589
5695 11:37:54.401869 01c80000 ################################################################
5696 11:37:54.401999
5697 11:37:54.663391 01d00000 ################################################################
5698 11:37:54.663527
5699 11:37:54.918341 01d80000 ################################################################
5700 11:37:54.918474
5701 11:37:55.172013 01e00000 ################################################################
5702 11:37:55.172132
5703 11:37:55.426967 01e80000 ################################################################
5704 11:37:55.427102
5705 11:37:55.686733 01f00000 ################################################################
5706 11:37:55.686874
5707 11:37:55.952519 01f80000 ################################################################
5708 11:37:55.952652
5709 11:37:56.210503 02000000 ################################################################
5710 11:37:56.210679
5711 11:37:56.464752 02080000 ################################################################
5712 11:37:56.464895
5713 11:37:56.722567 02100000 ################################################################
5714 11:37:56.722731
5715 11:37:56.980328 02180000 ################################################################
5716 11:37:56.980466
5717 11:37:57.257736 02200000 ################################################################
5718 11:37:57.257857
5719 11:37:57.512066 02280000 ################################################################
5720 11:37:57.512200
5721 11:37:57.769825 02300000 ################################################################
5722 11:37:57.769957
5723 11:37:58.032053 02380000 ################################################################
5724 11:37:58.032221
5725 11:37:58.295875 02400000 ################################################################
5726 11:37:58.296051
5727 11:37:58.560615 02480000 ################################################################
5728 11:37:58.560766
5729 11:37:58.821266 02500000 ################################################################
5730 11:37:58.821421
5731 11:37:59.071480 02580000 ################################################################
5732 11:37:59.071619
5733 11:37:59.324590 02600000 ################################################################
5734 11:37:59.324763
5735 11:37:59.585707 02680000 ################################################################
5736 11:37:59.585868
5737 11:37:59.853244 02700000 ################################################################
5738 11:37:59.853410
5739 11:38:00.127330 02780000 ################################################################
5740 11:38:00.127497
5741 11:38:00.399914 02800000 ################################################################
5742 11:38:00.400054
5743 11:38:00.663567 02880000 ################################################################
5744 11:38:00.663710
5745 11:38:00.925503 02900000 ################################################################
5746 11:38:00.925636
5747 11:38:01.197831 02980000 ################################################################
5748 11:38:01.197968
5749 11:38:01.465853 02a00000 ################################################################
5750 11:38:01.466041
5751 11:38:01.731016 02a80000 ################################################################
5752 11:38:01.731181
5753 11:38:01.989254 02b00000 ################################################################
5754 11:38:01.989413
5755 11:38:02.249356 02b80000 ################################################################
5756 11:38:02.249522
5757 11:38:02.514671 02c00000 ################################################################
5758 11:38:02.514808
5759 11:38:02.791758 02c80000 ################################################################
5760 11:38:02.791924
5761 11:38:03.054281 02d00000 ################################################################
5762 11:38:03.054440
5763 11:38:03.326467 02d80000 ################################################################
5764 11:38:03.326614
5765 11:38:03.594048 02e00000 ################################################################
5766 11:38:03.594208
5767 11:38:03.855856 02e80000 ################################################################
5768 11:38:03.856017
5769 11:38:04.121639 02f00000 ################################################################
5770 11:38:04.121805
5771 11:38:04.377723 02f80000 ################################################################
5772 11:38:04.377886
5773 11:38:04.631448 03000000 ################################################################
5774 11:38:04.631625
5775 11:38:04.898661 03080000 ################################################################
5776 11:38:04.898804
5777 11:38:05.162655 03100000 ################################################################
5778 11:38:05.162812
5779 11:38:05.416156 03180000 ################################################################
5780 11:38:05.416319
5781 11:38:05.680085 03200000 ################################################################
5782 11:38:05.680247
5783 11:38:05.931239 03280000 ################################################################
5784 11:38:05.931403
5785 11:38:06.198275 03300000 ################################################################
5786 11:38:06.198433
5787 11:38:06.379126 03380000 ############################################### done.
5788 11:38:06.379274
5789 11:38:06.382406 The bootfile was 54379742 bytes long.
5790 11:38:06.382511
5791 11:38:06.385675 Sending tftp read request... done.
5792 11:38:06.385775
5793 11:38:06.389099 Waiting for the transfer...
5794 11:38:06.389205
5795 11:38:06.389310 00000000 # done.
5796 11:38:06.389404
5797 11:38:06.399199 Command line loaded dynamically from TFTP file: 14864642/tftp-deploy-7mqfe8wa/kernel/cmdline
5798 11:38:06.399307
5799 11:38:06.415261 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5800 11:38:06.415372
5801 11:38:06.415478 Loading FIT.
5802 11:38:06.415547
5803 11:38:06.418713 Image ramdisk-1 has 41201711 bytes.
5804 11:38:06.418790
5805 11:38:06.421752 Image fdt-1 has 57695 bytes.
5806 11:38:06.421869
5807 11:38:06.425062 Image kernel-1 has 13118294 bytes.
5808 11:38:06.425164
5809 11:38:06.431704 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5810 11:38:06.434783
5811 11:38:06.444577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5812 11:38:06.444685
5813 11:38:06.451435 Choosing best match conf-1 for compat google,juniper-sku16.
5814 11:38:06.454507
5815 11:38:06.458662 Connected to device vid:did:rid of 1ae0:0028:00
5816 11:38:06.466120
5817 11:38:06.469133 tpm_get_response: command 0x17b, return code 0x0
5818 11:38:06.469234
5819 11:38:06.472469 tpm_cleanup: add release locality here.
5820 11:38:06.472544
5821 11:38:06.475591 Shutting down all USB controllers.
5822 11:38:06.475668
5823 11:38:06.479178 Removing current net device
5824 11:38:06.479275
5825 11:38:06.482462 Exiting depthcharge with code 4 at timestamp: 46298138
5826 11:38:06.485573
5827 11:38:06.488889 LZMA decompressing kernel-1 to 0x80193568
5828 11:38:06.488992
5829 11:38:06.492063 LZMA decompressing kernel-1 to 0x40000000
5830 11:38:08.355059
5831 11:38:08.355223 jumping to kernel
5832 11:38:08.355795 end: 2.2.4 bootloader-commands (duration 00:00:31) [common]
5833 11:38:08.355907 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
5834 11:38:08.355985 Setting prompt string to ['Linux version [0-9]']
5835 11:38:08.356058 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5836 11:38:08.356138 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5837 11:38:08.429954
5838 11:38:08.433176 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5839 11:38:08.436529 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
5840 11:38:08.436657 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5841 11:38:08.436763 Setting prompt string to []
5842 11:38:08.436878 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5843 11:38:08.436957 Using line separator: #'\n'#
5844 11:38:08.437021 No login prompt set.
5845 11:38:08.437088 Parsing kernel messages
5846 11:38:08.437145 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5847 11:38:08.437273 [login-action] Waiting for messages, (timeout 00:03:56)
5848 11:38:08.437368 Waiting using forced prompt support (timeout 00:01:58)
5849 11:38:08.455885 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
5850 11:38:08.459360 [ 0.000000] random: crng init done
5851 11:38:08.462718 [ 0.000000] Machine model: Google juniper sku16 board
5852 11:38:08.465784 [ 0.000000] efi: UEFI not found.
5853 11:38:08.475692 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5854 11:38:08.482350 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5855 11:38:08.492229 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5856 11:38:08.495233 [ 0.000000] printk: bootconsole [mtk8250] enabled
5857 11:38:08.503895 [ 0.000000] NUMA: No NUMA configuration found
5858 11:38:08.510232 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5859 11:38:08.516795 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5860 11:38:08.516906 [ 0.000000] Zone ranges:
5861 11:38:08.523414 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5862 11:38:08.526667 [ 0.000000] DMA32 empty
5863 11:38:08.533372 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5864 11:38:08.536768 [ 0.000000] Movable zone start for each node
5865 11:38:08.540023 [ 0.000000] Early memory node ranges
5866 11:38:08.546324 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5867 11:38:08.553152 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5868 11:38:08.559731 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5869 11:38:08.566038 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5870 11:38:08.572458 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5871 11:38:08.579141 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5872 11:38:08.600344 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5873 11:38:08.606890 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5874 11:38:08.613435 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5875 11:38:08.616618 [ 0.000000] psci: probing for conduit method from DT.
5876 11:38:08.623116 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5877 11:38:08.626538 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5878 11:38:08.632877 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5879 11:38:08.636451 [ 0.000000] psci: SMC Calling Convention v1.1
5880 11:38:08.642737 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5881 11:38:08.646158 [ 0.000000] Detected VIPT I-cache on CPU0
5882 11:38:08.652727 [ 0.000000] CPU features: detected: GIC system register CPU interface
5883 11:38:08.659480 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5884 11:38:08.665636 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5885 11:38:08.672101 [ 0.000000] CPU features: detected: ARM erratum 845719
5886 11:38:08.675282 [ 0.000000] alternatives: applying boot alternatives
5887 11:38:08.681927 [ 0.000000] Fallback order for Node 0: 0
5888 11:38:08.688664 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5889 11:38:08.691786 [ 0.000000] Policy zone: Normal
5890 11:38:08.708236 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5891 11:38:08.721155 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5892 11:38:08.731294 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5893 11:38:08.737846 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5894 11:38:08.744423 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
5895 11:38:08.750856 <6>[ 0.000000] software IO TLB: area num 8.
5896 11:38:08.775382 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5897 11:38:08.833420 <6>[ 0.000000] Memory: 3874840K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 283624K reserved, 32768K cma-reserved)
5898 11:38:08.839925 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5899 11:38:08.846528 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5900 11:38:08.849561 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5901 11:38:08.856226 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5902 11:38:08.862459 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5903 11:38:08.869087 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5904 11:38:08.875975 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5905 11:38:08.882166 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5906 11:38:08.889041 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5907 11:38:08.898641 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5908 11:38:08.905261 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5909 11:38:08.908531 <6>[ 0.000000] GICv3: 640 SPIs implemented
5910 11:38:08.911853 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5911 11:38:08.918211 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5912 11:38:08.921575 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5913 11:38:08.928156 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5914 11:38:08.941071 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5915 11:38:08.954133 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5916 11:38:08.960854 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5917 11:38:08.970434 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5918 11:38:08.983420 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5919 11:38:08.990109 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5920 11:38:08.997484 <6>[ 0.009473] Console: colour dummy device 80x25
5921 11:38:09.000369 <6>[ 0.014504] printk: console [tty1] enabled
5922 11:38:09.013836 <6>[ 0.018897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5923 11:38:09.016814 <6>[ 0.029361] pid_max: default: 32768 minimum: 301
5924 11:38:09.023438 <6>[ 0.034242] LSM: Security Framework initializing
5925 11:38:09.030065 <6>[ 0.039157] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5926 11:38:09.036437 <6>[ 0.046780] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5927 11:38:09.043320 <4>[ 0.055665] cacheinfo: Unable to detect cache hierarchy for CPU 0
5928 11:38:09.053165 <6>[ 0.062292] cblist_init_generic: Setting adjustable number of callback queues.
5929 11:38:09.059795 <6>[ 0.069737] cblist_init_generic: Setting shift to 3 and lim to 1.
5930 11:38:09.066273 <6>[ 0.076090] cblist_init_generic: Setting adjustable number of callback queues.
5931 11:38:09.072842 <6>[ 0.083535] cblist_init_generic: Setting shift to 3 and lim to 1.
5932 11:38:09.079217 <6>[ 0.089934] rcu: Hierarchical SRCU implementation.
5933 11:38:09.082525 <6>[ 0.094960] rcu: Max phase no-delay instances is 1000.
5934 11:38:09.090465 <6>[ 0.102879] EFI services will not be available.
5935 11:38:09.093666 <6>[ 0.107827] smp: Bringing up secondary CPUs ...
5936 11:38:09.104048 <6>[ 0.113056] Detected VIPT I-cache on CPU1
5937 11:38:09.110836 <4>[ 0.113103] cacheinfo: Unable to detect cache hierarchy for CPU 1
5938 11:38:09.117353 <6>[ 0.113111] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5939 11:38:09.123875 <6>[ 0.113144] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5940 11:38:09.127220 <6>[ 0.113625] Detected VIPT I-cache on CPU2
5941 11:38:09.133815 <4>[ 0.113658] cacheinfo: Unable to detect cache hierarchy for CPU 2
5942 11:38:09.140160 <6>[ 0.113663] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5943 11:38:09.146700 <6>[ 0.113675] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5944 11:38:09.153270 <6>[ 0.114120] Detected VIPT I-cache on CPU3
5945 11:38:09.160066 <4>[ 0.114150] cacheinfo: Unable to detect cache hierarchy for CPU 3
5946 11:38:09.166467 <6>[ 0.114155] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5947 11:38:09.173280 <6>[ 0.114166] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5948 11:38:09.176263 <6>[ 0.114740] CPU features: detected: Spectre-v2
5949 11:38:09.182862 <6>[ 0.114751] CPU features: detected: Spectre-BHB
5950 11:38:09.186362 <6>[ 0.114754] CPU features: detected: ARM erratum 858921
5951 11:38:09.192859 <6>[ 0.114760] Detected VIPT I-cache on CPU4
5952 11:38:09.199416 <4>[ 0.114808] cacheinfo: Unable to detect cache hierarchy for CPU 4
5953 11:38:09.206562 <6>[ 0.114816] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5954 11:38:09.212478 <6>[ 0.114824] arch_timer: Enabling local workaround for ARM erratum 858921
5955 11:38:09.215956 <6>[ 0.114834] arch_timer: CPU4: Trapping CNTVCT access
5956 11:38:09.225673 <6>[ 0.114842] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5957 11:38:09.229042 <6>[ 0.115328] Detected VIPT I-cache on CPU5
5958 11:38:09.235411 <4>[ 0.115367] cacheinfo: Unable to detect cache hierarchy for CPU 5
5959 11:38:09.241910 <6>[ 0.115373] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5960 11:38:09.248702 <6>[ 0.115380] arch_timer: Enabling local workaround for ARM erratum 858921
5961 11:38:09.255112 <6>[ 0.115386] arch_timer: CPU5: Trapping CNTVCT access
5962 11:38:09.261815 <6>[ 0.115391] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5963 11:38:09.265158 <6>[ 0.115828] Detected VIPT I-cache on CPU6
5964 11:38:09.271519 <4>[ 0.115873] cacheinfo: Unable to detect cache hierarchy for CPU 6
5965 11:38:09.278218 <6>[ 0.115878] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5966 11:38:09.285053 <6>[ 0.115885] arch_timer: Enabling local workaround for ARM erratum 858921
5967 11:38:09.291131 <6>[ 0.115891] arch_timer: CPU6: Trapping CNTVCT access
5968 11:38:09.297853 <6>[ 0.115897] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5969 11:38:09.300714 <6>[ 0.116428] Detected VIPT I-cache on CPU7
5970 11:38:09.307346 <4>[ 0.116472] cacheinfo: Unable to detect cache hierarchy for CPU 7
5971 11:38:09.314044 <6>[ 0.116478] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5972 11:38:09.323812 <6>[ 0.116485] arch_timer: Enabling local workaround for ARM erratum 858921
5973 11:38:09.326972 <6>[ 0.116491] arch_timer: CPU7: Trapping CNTVCT access
5974 11:38:09.333699 <6>[ 0.116497] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5975 11:38:09.337163 <6>[ 0.116544] smp: Brought up 1 node, 8 CPUs
5976 11:38:09.343443 <6>[ 0.355450] SMP: Total of 8 processors activated.
5977 11:38:09.350032 <6>[ 0.360386] CPU features: detected: 32-bit EL0 Support
5978 11:38:09.353352 <6>[ 0.365765] CPU features: detected: 32-bit EL1 Support
5979 11:38:09.359753 <6>[ 0.371133] CPU features: detected: CRC32 instructions
5980 11:38:09.362944 <6>[ 0.376557] CPU: All CPU(s) started at EL2
5981 11:38:09.369307 <6>[ 0.380895] alternatives: applying system-wide alternatives
5982 11:38:09.377041 <6>[ 0.388967] devtmpfs: initialized
5983 11:38:09.392559 <6>[ 0.397899] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5984 11:38:09.399102 <6>[ 0.407846] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5985 11:38:09.405580 <6>[ 0.415570] pinctrl core: initialized pinctrl subsystem
5986 11:38:09.408684 <6>[ 0.422683] DMI not present or invalid.
5987 11:38:09.415429 <6>[ 0.427048] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5988 11:38:09.425345 <6>[ 0.433945] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5989 11:38:09.431938 <6>[ 0.441476] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5990 11:38:09.441830 <6>[ 0.449727] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5991 11:38:09.448454 <6>[ 0.457905] audit: initializing netlink subsys (disabled)
5992 11:38:09.454645 <5>[ 0.463612] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5993 11:38:09.461605 <6>[ 0.464591] thermal_sys: Registered thermal governor 'step_wise'
5994 11:38:09.467933 <6>[ 0.471579] thermal_sys: Registered thermal governor 'power_allocator'
5995 11:38:09.471213 <6>[ 0.477878] cpuidle: using governor menu
5996 11:38:09.477720 <6>[ 0.488843] NET: Registered PF_QIPCRTR protocol family
5997 11:38:09.484318 <6>[ 0.494330] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5998 11:38:09.490392 <6>[ 0.501428] ASID allocator initialised with 32768 entries
5999 11:38:09.497197 <6>[ 0.508198] Serial: AMBA PL011 UART driver
6000 11:38:09.507362 <4>[ 0.519542] Trying to register duplicate clock ID: 113
6001 11:38:09.567512 <6>[ 0.576017] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6002 11:38:09.581724 <6>[ 0.590410] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6003 11:38:09.584846 <6>[ 0.600183] KASLR enabled
6004 11:38:09.599729 <6>[ 0.608145] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6005 11:38:09.606501 <6>[ 0.615148] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6006 11:38:09.612407 <6>[ 0.621623] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6007 11:38:09.619305 <6>[ 0.628615] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6008 11:38:09.625916 <6>[ 0.635088] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6009 11:38:09.632309 <6>[ 0.642079] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6010 11:38:09.638975 <6>[ 0.648554] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6011 11:38:09.645398 <6>[ 0.655544] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6012 11:38:09.648902 <6>[ 0.663110] ACPI: Interpreter disabled.
6013 11:38:09.659134 <6>[ 0.671092] iommu: Default domain type: Translated
6014 11:38:09.665743 <6>[ 0.676201] iommu: DMA domain TLB invalidation policy: strict mode
6015 11:38:09.669071 <5>[ 0.682829] SCSI subsystem initialized
6016 11:38:09.675489 <6>[ 0.687241] usbcore: registered new interface driver usbfs
6017 11:38:09.682048 <6>[ 0.692967] usbcore: registered new interface driver hub
6018 11:38:09.685417 <6>[ 0.698508] usbcore: registered new device driver usb
6019 11:38:09.692884 <6>[ 0.704818] pps_core: LinuxPPS API ver. 1 registered
6020 11:38:09.702444 <6>[ 0.710002] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6021 11:38:09.705928 <6>[ 0.719327] PTP clock support registered
6022 11:38:09.709535 <6>[ 0.723579] EDAC MC: Ver: 3.0.0
6023 11:38:09.717319 <6>[ 0.729226] FPGA manager framework
6024 11:38:09.723912 <6>[ 0.732910] Advanced Linux Sound Architecture Driver Initialized.
6025 11:38:09.726854 <6>[ 0.739668] vgaarb: loaded
6026 11:38:09.733589 <6>[ 0.742787] clocksource: Switched to clocksource arch_sys_counter
6027 11:38:09.736881 <5>[ 0.749218] VFS: Disk quotas dquot_6.6.0
6028 11:38:09.743519 <6>[ 0.753394] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6029 11:38:09.746511 <6>[ 0.760567] pnp: PnP ACPI: disabled
6030 11:38:09.755519 <6>[ 0.767460] NET: Registered PF_INET protocol family
6031 11:38:09.762160 <6>[ 0.772691] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6032 11:38:09.774002 <6>[ 0.782604] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6033 11:38:09.783718 <6>[ 0.791358] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6034 11:38:09.790365 <6>[ 0.799310] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6035 11:38:09.796807 <6>[ 0.807542] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6036 11:38:09.806882 <6>[ 0.815635] TCP: Hash tables configured (established 32768 bind 32768)
6037 11:38:09.813719 <6>[ 0.822464] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6038 11:38:09.819977 <6>[ 0.829436] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6039 11:38:09.826761 <6>[ 0.836916] NET: Registered PF_UNIX/PF_LOCAL protocol family
6040 11:38:09.833372 <6>[ 0.843012] RPC: Registered named UNIX socket transport module.
6041 11:38:09.836448 <6>[ 0.849154] RPC: Registered udp transport module.
6042 11:38:09.843048 <6>[ 0.854080] RPC: Registered tcp transport module.
6043 11:38:09.849492 <6>[ 0.859004] RPC: Registered tcp NFSv4.1 backchannel transport module.
6044 11:38:09.852805 <6>[ 0.865657] PCI: CLS 0 bytes, default 64
6045 11:38:09.856108 <6>[ 0.869950] Unpacking initramfs...
6046 11:38:09.871015 <6>[ 0.879436] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6047 11:38:09.880443 <6>[ 0.888064] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6048 11:38:09.883611 <6>[ 0.896920] kvm [1]: IPA Size Limit: 40 bits
6049 11:38:09.891227 <6>[ 0.903244] kvm [1]: vgic-v2@c420000
6050 11:38:09.894660 <6>[ 0.907062] kvm [1]: GIC system register CPU interface enabled
6051 11:38:09.902931 <6>[ 0.914848] kvm [1]: vgic interrupt IRQ18
6052 11:38:09.906094 <6>[ 0.919215] kvm [1]: Hyp mode initialized successfully
6053 11:38:09.913807 <5>[ 0.925582] Initialise system trusted keyrings
6054 11:38:09.920198 <6>[ 0.930442] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6055 11:38:09.928442 <6>[ 0.940399] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6056 11:38:09.934867 <5>[ 0.946873] NFS: Registering the id_resolver key type
6057 11:38:09.938064 <5>[ 0.952179] Key type id_resolver registered
6058 11:38:09.944818 <5>[ 0.956595] Key type id_legacy registered
6059 11:38:09.951290 <6>[ 0.960902] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6060 11:38:09.957646 <6>[ 0.967824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6061 11:38:09.964083 <6>[ 0.975583] 9p: Installing v9fs 9p2000 file system support
6062 11:38:09.992376 <5>[ 1.004684] Key type asymmetric registered
6063 11:38:09.995861 <5>[ 1.009030] Asymmetric key parser 'x509' registered
6064 11:38:10.005520 <6>[ 1.014200] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6065 11:38:10.008897 <6>[ 1.021818] io scheduler mq-deadline registered
6066 11:38:10.015049 <6>[ 1.026575] io scheduler kyber registered
6067 11:38:10.035002 <6>[ 1.047378] EINJ: ACPI disabled.
6068 11:38:10.041414 <4>[ 1.051126] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6069 11:38:10.079905 <6>[ 1.091800] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6070 11:38:10.088514 <6>[ 1.100276] printk: console [ttyS0] disabled
6071 11:38:10.115953 <6>[ 1.124928] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6072 11:38:10.122958 <6>[ 1.134403] printk: console [ttyS0] enabled
6073 11:38:10.125761 <6>[ 1.134403] printk: console [ttyS0] enabled
6074 11:38:10.132384 <6>[ 1.143323] printk: bootconsole [mtk8250] disabled
6075 11:38:10.135663 <6>[ 1.143323] printk: bootconsole [mtk8250] disabled
6076 11:38:10.145136 <3>[ 1.153860] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6077 11:38:10.152071 <3>[ 1.162243] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6078 11:38:10.181788 <6>[ 1.190663] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6079 11:38:10.188114 <6>[ 1.200324] serial serial0: tty port ttyS1 registered
6080 11:38:10.194443 <6>[ 1.206877] SuperH (H)SCI(F) driver initialized
6081 11:38:10.197783 <6>[ 1.212360] msm_serial: driver initialized
6082 11:38:10.213600 <6>[ 1.222645] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6083 11:38:10.223594 <6>[ 1.231247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6084 11:38:10.230156 <6>[ 1.239822] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6085 11:38:10.240010 <6>[ 1.248390] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6086 11:38:10.249780 <6>[ 1.257046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6087 11:38:10.256016 <6>[ 1.265705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6088 11:38:10.266493 <6>[ 1.274443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6089 11:38:10.276017 <6>[ 1.283181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6090 11:38:10.281958 <6>[ 1.291743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6091 11:38:10.291806 <6>[ 1.300541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6092 11:38:10.300758 <4>[ 1.312970] cacheinfo: Unable to detect cache hierarchy for CPU 0
6093 11:38:10.310037 <6>[ 1.322383] loop: module loaded
6094 11:38:10.321898 <6>[ 1.334337] vsim1: Bringing 1800000uV into 2700000-2700000uV
6095 11:38:10.340136 <6>[ 1.352500] megasas: 07.719.03.00-rc1
6096 11:38:10.348747 <6>[ 1.361249] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6097 11:38:10.361446 <6>[ 1.370179] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6098 11:38:10.374486 <6>[ 1.386776] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6099 11:38:10.434558 <6>[ 1.440457] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-a
6100 11:38:11.184957 <6>[ 2.197259] Freeing initrd memory: 40232K
6101 11:38:11.200303 <4>[ 2.209195] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6102 11:38:11.206591 <4>[ 2.218425] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.96-cip24 #1
6103 11:38:11.213077 <4>[ 2.225123] Hardware name: Google juniper sku16 board (DT)
6104 11:38:11.216439 <4>[ 2.230862] Call trace:
6105 11:38:11.219880 <4>[ 2.233562] dump_backtrace.part.0+0xe0/0xf0
6106 11:38:11.222863 <4>[ 2.238099] show_stack+0x18/0x30
6107 11:38:11.229457 <4>[ 2.241673] dump_stack_lvl+0x64/0x80
6108 11:38:11.232946 <4>[ 2.245593] dump_stack+0x18/0x34
6109 11:38:11.236071 <4>[ 2.249162] sysfs_warn_dup+0x64/0x80
6110 11:38:11.239378 <4>[ 2.253084] sysfs_do_create_link_sd+0xf0/0x100
6111 11:38:11.246159 <4>[ 2.257872] sysfs_create_link+0x20/0x40
6112 11:38:11.249469 <4>[ 2.262051] bus_add_device+0x64/0x120
6113 11:38:11.252843 <4>[ 2.266056] device_add+0x354/0x7ec
6114 11:38:11.255743 <4>[ 2.269802] of_device_add+0x44/0x60
6115 11:38:11.262538 <4>[ 2.273635] of_platform_device_create_pdata+0x90/0x124
6116 11:38:11.265681 <4>[ 2.279117] of_platform_bus_create+0x154/0x380
6117 11:38:11.272424 <4>[ 2.283903] of_platform_populate+0x50/0xfc
6118 11:38:11.275671 <4>[ 2.288343] parse_mtd_partitions+0x1d8/0x4e0
6119 11:38:11.282155 <4>[ 2.292958] mtd_device_parse_register+0xec/0x2e0
6120 11:38:11.285568 <4>[ 2.297919] spi_nor_probe+0x280/0x2f4
6121 11:38:11.288648 <4>[ 2.301924] spi_mem_probe+0x6c/0xc0
6122 11:38:11.291713 <4>[ 2.305756] spi_probe+0x84/0xe4
6123 11:38:11.295077 <4>[ 2.309241] really_probe+0xbc/0x2dc
6124 11:38:11.301883 <4>[ 2.313071] __driver_probe_device+0x78/0x114
6125 11:38:11.305131 <4>[ 2.317683] driver_probe_device+0xd8/0x15c
6126 11:38:11.308175 <4>[ 2.322120] __device_attach_driver+0xb8/0x134
6127 11:38:11.315010 <4>[ 2.326819] bus_for_each_drv+0x7c/0xd4
6128 11:38:11.318163 <4>[ 2.330912] __device_attach+0x9c/0x1a0
6129 11:38:11.321360 <4>[ 2.335003] device_initial_probe+0x14/0x20
6130 11:38:11.324646 <4>[ 2.339440] bus_probe_device+0x98/0xa0
6131 11:38:11.331168 <4>[ 2.343530] device_add+0x3c0/0x7ec
6132 11:38:11.334498 <4>[ 2.347275] __spi_add_device+0x78/0x120
6133 11:38:11.337715 <4>[ 2.351454] spi_add_device+0x44/0x80
6134 11:38:11.344505 <4>[ 2.355371] spi_register_controller+0x704/0xb20
6135 11:38:11.347671 <4>[ 2.360243] devm_spi_register_controller+0x4c/0xac
6136 11:38:11.350790 <4>[ 2.365376] mtk_spi_probe+0x4f4/0x684
6137 11:38:11.357558 <4>[ 2.369381] platform_probe+0x68/0xc0
6138 11:38:11.360690 <4>[ 2.373299] really_probe+0xbc/0x2dc
6139 11:38:11.363912 <4>[ 2.377129] __driver_probe_device+0x78/0x114
6140 11:38:11.370442 <4>[ 2.381740] driver_probe_device+0xd8/0x15c
6141 11:38:11.373966 <4>[ 2.386178] __driver_attach+0x94/0x19c
6142 11:38:11.376958 <4>[ 2.390268] bus_for_each_dev+0x74/0xd0
6143 11:38:11.380570 <4>[ 2.394360] driver_attach+0x24/0x30
6144 11:38:11.383814 <4>[ 2.398190] bus_add_driver+0x154/0x20c
6145 11:38:11.390034 <4>[ 2.402280] driver_register+0x78/0x130
6146 11:38:11.393408 <4>[ 2.406371] __platform_driver_register+0x28/0x34
6147 11:38:11.399946 <4>[ 2.411330] mtk_spi_driver_init+0x1c/0x28
6148 11:38:11.403407 <4>[ 2.415687] do_one_initcall+0x64/0x1dc
6149 11:38:11.406819 <4>[ 2.419777] kernel_init_freeable+0x218/0x284
6150 11:38:11.410052 <4>[ 2.424392] kernel_init+0x24/0x12c
6151 11:38:11.413136 <4>[ 2.428136] ret_from_fork+0x10/0x20
6152 11:38:11.424812 <6>[ 2.437048] tun: Universal TUN/TAP device driver, 1.6
6153 11:38:11.428330 <6>[ 2.443358] thunder_xcv, ver 1.0
6154 11:38:11.434847 <6>[ 2.446878] thunder_bgx, ver 1.0
6155 11:38:11.434957 <6>[ 2.450376] nicpf, ver 1.0
6156 11:38:11.445697 <6>[ 2.454750] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6157 11:38:11.449152 <6>[ 2.462234] hns3: Copyright (c) 2017 Huawei Corporation.
6158 11:38:11.455449 <6>[ 2.467837] hclge is initializing
6159 11:38:11.458724 <6>[ 2.471423] e1000: Intel(R) PRO/1000 Network Driver
6160 11:38:11.465164 <6>[ 2.476559] e1000: Copyright (c) 1999-2006 Intel Corporation.
6161 11:38:11.471679 <6>[ 2.482581] e1000e: Intel(R) PRO/1000 Network Driver
6162 11:38:11.478415 <6>[ 2.487803] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6163 11:38:11.481989 <6>[ 2.493996] igb: Intel(R) Gigabit Ethernet Network Driver
6164 11:38:11.488127 <6>[ 2.499651] igb: Copyright (c) 2007-2014 Intel Corporation.
6165 11:38:11.494647 <6>[ 2.505494] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6166 11:38:11.501349 <6>[ 2.512018] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6167 11:38:11.504355 <6>[ 2.518574] sky2: driver version 1.30
6168 11:38:11.511476 <6>[ 2.523838] usbcore: registered new device driver r8152-cfgselector
6169 11:38:11.518179 <6>[ 2.530379] usbcore: registered new interface driver r8152
6170 11:38:11.524303 <6>[ 2.536208] VFIO - User Level meta-driver version: 0.3
6171 11:38:11.531651 <6>[ 2.544005] mtu3 11201000.usb: uwk - reg:0x420, version:101
6172 11:38:11.541340 <4>[ 2.549878] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6173 11:38:11.544708 <6>[ 2.557149] mtu3 11201000.usb: dr_mode: 1, drd: auto
6174 11:38:11.551478 <6>[ 2.562374] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6175 11:38:11.554393 <6>[ 2.568560] mtu3 11201000.usb: usb3-drd: 0
6176 11:38:11.564953 <6>[ 2.574124] mtu3 11201000.usb: xHCI platform device register success...
6177 11:38:11.571658 <4>[ 2.582758] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6178 11:38:11.578500 <6>[ 2.590696] xhci-mtk 11200000.usb: xHCI Host Controller
6179 11:38:11.588369 <6>[ 2.596200] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6180 11:38:11.591335 <6>[ 2.603920] xhci-mtk 11200000.usb: USB3 root hub has no ports
6181 11:38:11.601135 <6>[ 2.609928] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6182 11:38:11.607582 <6>[ 2.619354] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6183 11:38:11.614496 <6>[ 2.625430] xhci-mtk 11200000.usb: xHCI Host Controller
6184 11:38:11.620935 <6>[ 2.630921] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6185 11:38:11.627569 <6>[ 2.638579] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6186 11:38:11.630505 <6>[ 2.645397] hub 1-0:1.0: USB hub found
6187 11:38:11.636986 <6>[ 2.649425] hub 1-0:1.0: 1 port detected
6188 11:38:11.647002 <6>[ 2.654769] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6189 11:38:11.650050 <6>[ 2.663404] hub 2-0:1.0: USB hub found
6190 11:38:11.656706 <3>[ 2.667440] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6191 11:38:11.663107 <6>[ 2.675330] usbcore: registered new interface driver usb-storage
6192 11:38:11.669539 <6>[ 2.681916] usbcore: registered new device driver onboard-usb-hub
6193 11:38:11.681647 <4>[ 2.690886] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6194 11:38:11.690776 <6>[ 2.703130] mt6397-rtc mt6358-rtc: registered as rtc0
6195 11:38:11.700863 <6>[ 2.708613] mt6397-rtc mt6358-rtc: setting system clock to 2024-07-17T11:38:11 UTC (1721216291)
6196 11:38:11.707279 <6>[ 2.718492] i2c_dev: i2c /dev entries driver
6197 11:38:11.716810 <6>[ 2.724940] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6198 11:38:11.723240 <6>[ 2.733260] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6199 11:38:11.729958 <6>[ 2.742164] i2c 4-0058: Fixed dependency cycle(s) with /panel
6200 11:38:11.736613 <6>[ 2.748197] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6201 11:38:11.755292 <6>[ 2.767700] cpu cpu0: EM: created perf domain
6202 11:38:11.768516 <6>[ 2.773231] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6203 11:38:11.771689 <6>[ 2.784518] cpu cpu4: EM: created perf domain
6204 11:38:11.779599 <6>[ 2.791686] sdhci: Secure Digital Host Controller Interface driver
6205 11:38:11.785950 <6>[ 2.798142] sdhci: Copyright(c) Pierre Ossman
6206 11:38:11.792709 <6>[ 2.803548] Synopsys Designware Multimedia Card Interface Driver
6207 11:38:11.798760 <6>[ 2.804058] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6208 11:38:11.805526 <6>[ 2.810606] sdhci-pltfm: SDHCI platform and OF driver helper
6209 11:38:11.812038 <6>[ 2.823303] ledtrig-cpu: registered to indicate activity on CPUs
6210 11:38:11.818749 <6>[ 2.831013] usbcore: registered new interface driver usbhid
6211 11:38:11.825124 <6>[ 2.836853] usbhid: USB HID core driver
6212 11:38:11.832410 <6>[ 2.841181] spi_master spi2: will run message pump with realtime priority
6213 11:38:11.839346 <4>[ 2.841562] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6214 11:38:11.845823 <4>[ 2.855581] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6215 11:38:11.858857 <6>[ 2.862142] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6216 11:38:11.876175 <6>[ 2.878620] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6217 11:38:11.882778 <4>[ 2.890404] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6218 11:38:11.889255 <6>[ 2.893735] cros-ec-spi spi2.0: Chrome EC device registered
6219 11:38:11.900336 <4>[ 2.909520] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6220 11:38:11.913346 <4>[ 2.922180] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6221 11:38:11.919727 <6>[ 2.929117] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6222 11:38:11.926262 <4>[ 2.931146] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6223 11:38:11.929741 <6>[ 2.937829] mmc0: new HS400 MMC card at address 0001
6224 11:38:11.936139 <6>[ 2.948379] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6225 11:38:11.948648 <6>[ 2.957307] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6226 11:38:11.951615 <6>[ 2.958591] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6227 11:38:11.960099 <6>[ 2.972277] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6228 11:38:11.969817 <6>[ 2.977138] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6229 11:38:11.976403 <6>[ 2.986965] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6230 11:38:11.986094 <6>[ 2.990375] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6231 11:38:11.993176 <6>[ 3.003592] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6232 11:38:11.999194 <6>[ 3.004737] NET: Registered PF_PACKET protocol family
6233 11:38:12.009110 <6>[ 3.007860] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6234 11:38:12.018564 <6>[ 3.007981] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6235 11:38:12.025488 <6>[ 3.037742] 9pnet: Installing 9P2000 support
6236 11:38:12.028884 <5>[ 3.042496] Key type dns_resolver registered
6237 11:38:12.035572 <6>[ 3.047696] registered taskstats version 1
6238 11:38:12.038626 <5>[ 3.052064] Loading compiled-in X.509 certificates
6239 11:38:12.061814 <6>[ 3.070821] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6240 11:38:12.083133 <3>[ 3.092227] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6241 11:38:12.114170 <6>[ 3.119907] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6242 11:38:12.124252 <6>[ 3.133328] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6243 11:38:12.134181 <6>[ 3.141911] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6244 11:38:12.140617 <6>[ 3.150445] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6245 11:38:12.150181 <6>[ 3.158972] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6246 11:38:12.160051 <6>[ 3.167496] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6247 11:38:12.166979 <6>[ 3.176020] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6248 11:38:12.176516 <6>[ 3.184543] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6249 11:38:12.182968 <6>[ 3.193631] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6250 11:38:12.189916 <6>[ 3.201013] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6251 11:38:12.196098 <6>[ 3.208237] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6252 11:38:12.206739 <6>[ 3.215419] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6253 11:38:12.213069 <6>[ 3.222752] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6254 11:38:12.216458 <6>[ 3.225795] hub 1-1:1.0: USB hub found
6255 11:38:12.222641 <6>[ 3.230935] panfrost 13040000.gpu: clock rate = 511999970
6256 11:38:12.226178 <6>[ 3.233825] hub 1-1:1.0: 3 ports detected
6257 11:38:12.236006 <6>[ 3.239114] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6258 11:38:12.245588 <6>[ 3.253555] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6259 11:38:12.252234 <6>[ 3.261582] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6260 11:38:12.265272 <6>[ 3.270014] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6261 11:38:12.271527 <6>[ 3.282093] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6262 11:38:12.282489 <6>[ 3.291500] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6263 11:38:12.292248 <6>[ 3.300386] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6264 11:38:12.302082 <6>[ 3.309557] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6265 11:38:12.312161 <6>[ 3.318687] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6266 11:38:12.318596 <6>[ 3.327816] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6267 11:38:12.328485 <6>[ 3.337117] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6268 11:38:12.338709 <6>[ 3.346417] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6269 11:38:12.348036 <6>[ 3.355891] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6270 11:38:12.357985 <6>[ 3.365365] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6271 11:38:12.367404 <6>[ 3.374496] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6272 11:38:12.437707 <6>[ 3.446534] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6273 11:38:12.447389 <6>[ 3.455477] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6274 11:38:12.458710 <6>[ 3.467594] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6275 11:38:12.537682 <6>[ 3.546826] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6276 11:38:13.143851 <6>[ 3.743268] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6277 11:38:13.153991 <4>[ 3.859872] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6278 11:38:13.160244 <4>[ 3.859890] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6279 11:38:13.166719 <6>[ 3.896754] r8152 1-1.2:1.0 eth0: v1.12.13
6280 11:38:13.173268 <6>[ 3.974842] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6281 11:38:13.179884 <6>[ 4.136420] Console: switching to colour frame buffer device 170x48
6282 11:38:13.189450 <6>[ 4.196984] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6283 11:38:13.207493 <6>[ 4.213357] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6284 11:38:13.224288 <6>[ 4.230069] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6285 11:38:13.234425 <6>[ 4.243517] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6286 11:38:13.240936 <6>[ 4.251681] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6287 11:38:13.254124 <6>[ 4.255781] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6288 11:38:13.268576 <6>[ 4.274520] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6289 11:38:14.550706 <6>[ 5.562970] r8152 1-1.2:1.0 eth0: carrier on
6290 11:38:14.586630 <5>[ 5.582960] Sending DHCP requests ., OK
6291 11:38:14.593352 <6>[ 5.603041] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.22
6292 11:38:14.596395 <6>[ 5.611473] IP-Config: Complete:
6293 11:38:14.609572 <6>[ 5.615043] device=eth0, hwaddr=00:e0:4c:78:85:cb, ipaddr=192.168.201.22, mask=255.255.255.0, gw=192.168.201.1
6294 11:38:14.619379 <6>[ 5.625943] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2, domain=lava-rack, nis-domain=(none)
6295 11:38:14.631196 <6>[ 5.640295] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6296 11:38:14.639790 <6>[ 5.640305] nameserver0=192.168.201.1
6297 11:38:14.647973 <6>[ 5.660162] clk: Disabling unused clocks
6298 11:38:14.652753 <6>[ 5.668167] ALSA device list:
6299 11:38:14.661934 <6>[ 5.674231] No soundcards found.
6300 11:38:14.670843 <6>[ 5.683148] Freeing unused kernel memory: 8512K
6301 11:38:14.677949 <6>[ 5.690217] Run /init as init process
6302 11:38:14.707531 <6>[ 5.719723] NET: Registered PF_INET6 protocol family
6303 11:38:14.714698 <6>[ 5.726705] Segment Routing with IPv6
6304 11:38:14.717599 <6>[ 5.731420] In-situ OAM (IOAM) with IPv6
6305 11:38:14.762285 <30>[ 5.745300] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6306 11:38:14.769075 <30>[ 5.781392] systemd[1]: Detected architecture arm64.
6307 11:38:14.769187
6308 11:38:14.776127 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6309 11:38:14.776210
6310 11:38:14.791164 <30>[ 5.803275] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6311 11:38:14.938250 <30>[ 5.947394] systemd[1]: Queued start job for default target graphical.target.
6312 11:38:14.967879 <30>[ 5.976958] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6313 11:38:14.977599 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6314 11:38:14.994566 <30>[ 6.003666] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6315 11:38:15.004585 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6316 11:38:15.023555 <30>[ 6.032648] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6317 11:38:15.035363 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6318 11:38:15.055269 <30>[ 6.063832] systemd[1]: Created slice user.slice - User and Session Slice.
6319 11:38:15.065056 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6320 11:38:15.085637 <30>[ 6.091319] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6321 11:38:15.097469 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6322 11:38:15.117485 <30>[ 6.123234] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6323 11:38:15.129409 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6324 11:38:15.156475 <30>[ 6.155370] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6325 11:38:15.174819 <30>[ 6.183722] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6326 11:38:15.182331 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6327 11:38:15.202050 <30>[ 6.211033] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6328 11:38:15.214268 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6329 11:38:15.230325 <30>[ 6.239036] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6330 11:38:15.244527 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6331 11:38:15.259114 <30>[ 6.271106] systemd[1]: Reached target paths.target - Path Units.
6332 11:38:15.273517 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6333 11:38:15.289842 <30>[ 6.299010] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6334 11:38:15.302622 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6335 11:38:15.318088 <30>[ 6.326954] systemd[1]: Reached target slices.target - Slice Units.
6336 11:38:15.329457 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6337 11:38:15.342637 <30>[ 6.355024] systemd[1]: Reached target swap.target - Swaps.
6338 11:38:15.353282 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6339 11:38:15.374150 <30>[ 6.383054] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6340 11:38:15.387798 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6341 11:38:15.407040 <30>[ 6.415495] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6342 11:38:15.420874 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6343 11:38:15.440009 <30>[ 6.448646] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6344 11:38:15.453427 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6345 11:38:15.471205 <30>[ 6.479736] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6346 11:38:15.485260 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6347 11:38:15.503124 <30>[ 6.511653] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6348 11:38:15.515380 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6349 11:38:15.535173 <30>[ 6.543785] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6350 11:38:15.548821 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6351 11:38:15.567031 <30>[ 6.575723] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6352 11:38:15.580009 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6353 11:38:15.598687 <30>[ 6.607457] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6354 11:38:15.611636 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6355 11:38:15.654876 <30>[ 6.663221] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6356 11:38:15.665170 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6357 11:38:15.686276 <30>[ 6.694832] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6358 11:38:15.696798 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6359 11:38:15.718179 <30>[ 6.726645] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6360 11:38:15.730591 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6361 11:38:15.753970 <30>[ 6.756044] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6362 11:38:15.807251 <30>[ 6.815925] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6363 11:38:15.820689 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6364 11:38:15.844462 <30>[ 6.852891] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6365 11:38:15.857959 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6366 11:38:15.879799 <30>[ 6.888495] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6367 11:38:15.891197 <6>[ 6.897835] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6368 11:38:15.902135 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6369 11:38:15.943060 <30>[ 6.951482] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6370 11:38:15.953750 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6371 11:38:15.976264 <30>[ 6.984630] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6372 11:38:15.990562 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6373 11:38:16.011965 <30>[ 7.020814] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6374 11:38:16.023538 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6375 11:38:16.059266 <30>[ 7.067767] systemd[1]: Starting systemd-journald.service - Journal Service...
6376 11:38:16.070044 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6377 11:38:16.090816 <30>[ 7.099143] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6378 11:38:16.101433 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6379 11:38:16.141833 <30>[ 7.147718] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6380 11:38:16.153263 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6381 11:38:16.175207 <30>[ 7.184004] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6382 11:38:16.187721 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6383 11:38:16.209039 <30>[ 7.217970] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6384 11:38:16.220226 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6385 11:38:16.241908 <30>[ 7.250860] systemd[1]: Started systemd-journald.service - Journal Service.
6386 11:38:16.251669 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6387 11:38:16.276494 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6388 11:38:16.299039 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6389 11:38:16.322727 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6390 11:38:16.343877 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6391 11:38:16.368981 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6392 11:38:16.388345 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6393 11:38:16.409148 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6394 11:38:16.428942 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6395 11:38:16.448586 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6396 11:38:16.467926 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6397 11:38:16.488065 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6398 11:38:16.509533 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
6399 11:38:16.527049 See 'systemctl status systemd-remount-fs.service' for details.
6400 11:38:16.549151 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6401 11:38:16.602988 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6402 11:38:16.628578 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6403 11:38:16.651723 <46>[ 7.660623] systemd-journald[205]: Received client request to flush runtime journal.
6404 11:38:16.662799 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6405 11:38:16.688588 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6406 11:38:16.715862 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6407 11:38:16.741158 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6408 11:38:16.760360 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6409 11:38:16.779832 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6410 11:38:16.800046 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6411 11:38:16.819921 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6412 11:38:16.839656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6413 11:38:16.895317 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6414 11:38:16.930152 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6415 11:38:16.947294 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6416 11:38:16.970196 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6417 11:38:17.022852 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6418 11:38:17.049164 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6419 11:38:17.074104 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6420 11:38:17.100221 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6421 11:38:17.121367 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6422 11:38:17.138789 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6423 11:38:17.177354 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6424 11:38:17.195655 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6425 11:38:17.215187 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6426 11:38:17.297542 <6>[ 8.306229] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6427 11:38:17.314280 <4>[ 8.319894] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6428 11:38:17.327531 <6>[ 8.332756] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6429 11:38:17.342850 <6>[ 8.348292] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6430 11:38:17.349391 <4>[ 8.353756] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6431 11:38:17.359268 <3>[ 8.359566] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6432 11:38:17.366724 <3>[ 8.362068] mtk-scp 10500000.scp: invalid resource
6433 11:38:17.373528 <6>[ 8.362207] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6434 11:38:17.380064 <6>[ 8.376832] remoteproc remoteproc0: scp is available
6435 11:38:17.386518 <4>[ 8.376859] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6436 11:38:17.392991 <3>[ 8.378614] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6437 11:38:17.402638 <4>[ 8.383790] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6438 11:38:17.412368 <3>[ 8.391254] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6439 11:38:17.419287 <6>[ 8.396478] remoteproc remoteproc0: powering up scp
6440 11:38:17.425869 <3>[ 8.403797] elan_i2c 2-0015: Error applying setting, reverse things back
6441 11:38:17.432204 <4>[ 8.410591] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6442 11:38:17.442000 <3>[ 8.420151] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6443 11:38:17.448477 <3>[ 8.429986] remoteproc remoteproc0: request_firmware failed: -2
6444 11:38:17.458748 <3>[ 8.435126] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6445 11:38:17.466021 <6>[ 8.442112] mc: Linux media interface: v0.10
6446 11:38:17.475586 <3>[ 8.450516] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6447 11:38:17.488789 <3>[ 8.458641] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6448 11:38:17.495194 <5>[ 8.475914] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6449 11:38:17.505020 <3>[ 8.487200] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6450 11:38:17.512297 <5>[ 8.504024] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6451 11:38:17.518582 <3>[ 8.504391] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6452 11:38:17.528684 <6>[ 8.506643] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6453 11:38:17.534941 <6>[ 8.508441] cs_system_cfg: CoreSight Configuration manager initialised
6454 11:38:17.541609 <6>[ 8.512240] videodev: Linux video capture interface: v2.00
6455 11:38:17.548233 <5>[ 8.512826] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6456 11:38:17.558567 <4>[ 8.512909] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6457 11:38:17.565399 <6>[ 8.512917] cfg80211: failed to load regulatory.db
6458 11:38:17.575293 <3>[ 8.520758] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6459 11:38:17.581713 <6>[ 8.531158] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6460 11:38:17.591430 <3>[ 8.536011] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6461 11:38:17.601680 <3>[ 8.536022] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6462 11:38:17.607903 <3>[ 8.536095] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6463 11:38:17.617559 <6>[ 8.569817] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6464 11:38:17.620771 <6>[ 8.575349] Bluetooth: Core ver 2.22
6465 11:38:17.627625 <6>[ 8.575414] NET: Registered PF_BLUETOOTH protocol family
6466 11:38:17.634383 <6>[ 8.575417] Bluetooth: HCI device and connection manager initialized
6467 11:38:17.637379 <6>[ 8.575433] Bluetooth: HCI socket layer initialized
6468 11:38:17.643951 <6>[ 8.575439] Bluetooth: L2CAP socket layer initialized
6469 11:38:17.650399 <6>[ 8.575451] Bluetooth: SCO socket layer initialized
6470 11:38:17.653834 <6>[ 8.583207] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6471 11:38:17.663566 <6>[ 8.590869] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6472 11:38:17.670113 <6>[ 8.600437] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6473 11:38:17.677136 <6>[ 8.617242] Bluetooth: HCI UART driver ver 2.3
6474 11:38:17.683980 <6>[ 8.617824] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6475 11:38:17.696694 <6>[ 8.618168] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6476 11:38:17.703029 <6>[ 8.618239] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video2
6477 11:38:17.709619 <6>[ 8.618732] usbcore: registered new interface driver uvcvideo
6478 11:38:17.716261 <6>[ 8.626107] Bluetooth: HCI UART protocol H4 registered
6479 11:38:17.726247 <6>[ 8.634135] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6480 11:38:17.735933 <6>[ 8.634379] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video3 (81,3)
6481 11:38:17.749053 <3>[ 8.638172] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6482 11:38:17.752578 <6>[ 8.643522] Bluetooth: HCI UART protocol LL registered
6483 11:38:17.763006 <6>[ 8.643581] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6484 11:38:17.772464 <6>[ 8.643758] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6485 11:38:17.779376 <6>[ 8.650051] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6486 11:38:17.789684 <6>[ 8.650191] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6487 11:38:17.796046 <3>[ 8.650931] debugfs: File 'Playback' in directory 'dapm' already present!
6488 11:38:17.802621 <3>[ 8.650937] debugfs: File 'Capture' in directory 'dapm' already present!
6489 11:38:17.815761 <6>[ 8.652626] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6490 11:38:17.822023 <3>[ 8.654031] thermal_sys: Failed to find 'trips' node
6491 11:38:17.828389 <3>[ 8.654037] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6492 11:38:17.838226 <3>[ 8.654042] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6493 11:38:17.844807 <4>[ 8.654046] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6494 11:38:17.851896 <3>[ 8.655499] thermal_sys: Failed to find 'trips' node
6495 11:38:17.862109 <6>[ 8.659237] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6496 11:38:17.871660 <6>[ 8.659249] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6497 11:38:17.881345 <6>[ 8.659574] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6498 11:38:17.892391 <6>[ 8.660686] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6499 11:38:17.899106 <6>[ 8.660698] Bluetooth: HCI UART protocol Three-wire (H5) registered
6500 11:38:17.906246 <6>[ 8.661026] Bluetooth: HCI UART protocol Broadcom registered
6501 11:38:17.913328 <6>[ 8.661056] Bluetooth: HCI UART protocol QCA registered
6502 11:38:17.920422 <6>[ 8.661068] Bluetooth: HCI UART protocol Marvell registered
6503 11:38:17.927700 <6>[ 8.662002] Bluetooth: hci0: setting up ROME/QCA6390
6504 11:38:17.934170 <3>[ 8.665664] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6505 11:38:17.944105 <3>[ 8.665673] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6506 11:38:17.954048 <4>[ 8.665677] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6507 11:38:17.963867 <6>[ 8.807357] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6508 11:38:17.970536 <3>[ 8.877954] Bluetooth: hci0: Frame reassembly failed (-84)
6509 11:38:17.980297 <4>[ 8.888362] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6510 11:38:17.983325 <4>[ 8.888362] Fallback method does not support PEC.
6511 11:38:17.994389 <3>[ 8.911402] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6512 11:38:18.004486 <3>[ 8.919418] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6513 11:38:18.014018 <3>[ 8.928449] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6514 11:38:18.020745 <3>[ 8.936249] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 11:38:18.030898 <3>[ 8.942849] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6516 11:38:18.074024 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slic<3>[ 9.081155] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6517 11:38:18.074131 e /system/systemd-backlight.
6518 11:38:18.089613 <3>[ 9.098125] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6519 11:38:18.106813 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<3>[ 9.113702] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6520 11:38:18.106901 t.
6521 11:38:18.122033 <3>[ 9.130644] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6522 11:38:18.139022 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/r<3>[ 9.146104] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6523 11:38:18.139110 fkill Watch.
6524 11:38:18.156199 <6>[ 9.168029] Bluetooth: hci0: QCA Product ID :0x00000008
6525 11:38:18.163754 <6>[ 9.175089] Bluetooth: hci0: QCA SOC Version :0x00000044
6526 11:38:18.170739 <6>[ 9.182082] Bluetooth: hci0: QCA ROM Version :0x00000302
6527 11:38:18.177154 <6>[ 9.189019] Bluetooth: hci0: QCA Patch Version:0x00000111
6528 11:38:18.183786 <6>[ 9.195928] Bluetooth: hci0: QCA controller version 0x00440302
6529 11:38:18.194693 <6>[ 9.203239] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6530 11:38:18.204764 <4>[ 9.211357] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6531 11:38:18.214889 <3>[ 9.221898] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6532 11:38:18.221021 <3>[ 9.231105] Bluetooth: hci0: QCA Failed to download patch (-2)
6533 11:38:18.230799 <6>[ 9.237332] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6534 11:38:18.246912 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6535 11:38:18.274346 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6536 11:38:18.296249 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6537 11:38:18.313895 <4>[ 9.322252] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6538 11:38:18.331351 <4>[ 9.340299] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6539 11:38:18.345544 [[0;32m OK [0m] Started [0;1;39msystemd-net<4>[ 9.355244] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6540 11:38:18.348896 workd.service[0m - Network Configuration.
6541 11:38:18.355449 <4>[ 9.367709] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6542 11:38:18.368597 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6543 11:38:18.386477 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6544 11:38:18.402074 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6545 11:38:18.418265 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6546 11:38:18.438006 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6547 11:38:18.460341 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6548 11:38:18.475687 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6549 11:38:18.492454 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6550 11:38:18.511201 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6551 11:38:18.526795 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6552 11:38:18.566196 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6553 11:38:18.590344 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6554 11:38:18.613671 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6555 11:38:18.638547 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6556 11:38:18.657588 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6557 11:38:18.686339 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6558 11:38:18.704684 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6559 11:38:18.779202 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6560 11:38:18.830110 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6561 11:38:18.848398 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6562 11:38:18.865001 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6563 11:38:18.885425 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6564 11:38:18.903132 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6565 11:38:18.958858 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6566 11:38:18.993313 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6567 11:38:19.038728
6568 11:38:19.041946 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6569 11:38:19.042429
6570 11:38:19.044857 debian-bookworm-arm64 login: root (automatic login)
6571 11:38:19.045261
6572 11:38:19.069480 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
6573 11:38:19.069924
6574 11:38:19.076137 The programs included with the Debian GNU/Linux system are free software;
6575 11:38:19.082594 the exact distribution terms for each program are described in the
6576 11:38:19.086102 individual files in /usr/share/doc/*/copyright.
6577 11:38:19.086492
6578 11:38:19.092218 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6579 11:38:19.095566 permitted by applicable law.
6580 11:38:19.096817 Matched prompt #10: / #
6582 11:38:19.097708 Setting prompt string to ['/ #']
6583 11:38:19.098109 end: 2.2.5.1 login-action (duration 00:00:11) [common]
6585 11:38:19.098979 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
6586 11:38:19.099382 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
6587 11:38:19.099717 Setting prompt string to ['/ #']
6588 11:38:19.099997 Forcing a shell prompt, looking for ['/ #']
6589 11:38:19.100271 Sending line: ''
6591 11:38:19.151349 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6592 11:38:19.151720 Waiting using forced prompt support (timeout 00:02:30)
6593 11:38:19.156850 / #
6594 11:38:19.157569 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6595 11:38:19.158028 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
6596 11:38:19.158462 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6597 11:38:19.158859 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
6598 11:38:19.159268 end: 2 depthcharge-action (duration 00:01:15) [common]
6599 11:38:19.159703 start: 3 lava-test-retry (timeout 00:08:22) [common]
6600 11:38:19.160111 start: 3.1 lava-test-shell (timeout 00:08:22) [common]
6601 11:38:19.160441 Using namespace: common
6602 11:38:19.160766 Sending line: '#'
6604 11:38:19.261897 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6605 11:38:19.267267 / # #
6606 11:38:19.268026 Using /lava-14864642
6607 11:38:19.268354 Sending line: 'export SHELL=/bin/sh'
6609 11:38:19.375235 / # export SHELL=/bin/sh
6610 11:38:19.375937 Sending line: '. /lava-14864642/environment'
6612 11:38:19.482503 / # . /lava-14864642/environment
6613 11:38:19.483186 Sending line: '/lava-14864642/bin/lava-test-runner /lava-14864642/0'
6615 11:38:19.584390 Test shell timeout: 10s (minimum of the action and connection timeout)
6616 11:38:19.589779 / # /lava-14864642/bin/lava-test-runner /lava-14864642/0
6617 11:38:19.615889 + export TESTRUN_ID=0_v4l2-compliance-uvc
6618 11:38:19.619019 + cd /lava-14864642/0/tests/0_v4l2-compliance-uvc
6619 11:38:19.619144 + cat uuid
6620 11:38:19.621942 + UUID=14864642_1.5.2.3.1
6621 11:38:19.622080 + set +x
6622 11:38:19.628477 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14864642_1.5.2.3.1>
6623 11:38:19.628830 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14864642_1.5.2.3.1
6624 11:38:19.628976 Starting test lava.0_v4l2-compliance-uvc (14864642_1.5.2.3.1)
6625 11:38:19.629158 Skipping test definition patterns.
6626 11:38:19.631745 + /usr/bin/v4l2-parser.sh -d uvcvideo
6627 11:38:19.638574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
6628 11:38:19.638984 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
6630 11:38:19.641818 device: /dev/video0
6631 11:38:26.476791 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
6632 11:38:26.491711 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
6633 11:38:26.503206
6634 11:38:26.520651 Compliance test for uvcvideo device /dev/video0:
6635 11:38:26.531566
6636 11:38:26.546039 Driver Info:
6637 11:38:26.559864 Driver name : uvcvideo
6638 11:38:26.578119 Card type : HD WebCam: HD WebCam
6639 11:38:26.593373 Bus info : usb-11200000.usb-1.3
6640 11:38:26.603698 Driver version : 6.1.96
6641 11:38:26.618411 Capabilities : 0x84a00001
6642 11:38:26.638943 Metadata Capture
6643 11:38:26.652020 Streaming
6644 11:38:26.667125 Extended Pix Format
6645 11:38:26.682092 Device Capabilities
6646 11:38:26.696688 Device Caps : 0x04200001
6647 11:38:26.716543 Streaming
6648 11:38:26.730829 Extended Pix Format
6649 11:38:26.746415 Media Driver Info:
6650 11:38:26.759329 Driver name : uvcvideo
6651 11:38:26.777410 Model : HD WebCam: HD WebCam
6652 11:38:26.787495 Serial :
6653 11:38:26.806162 Bus info : usb-11200000.usb-1.3
6654 11:38:26.816876 Media version : 6.1.96
6655 11:38:26.835089 Hardware revision: 0x00003269 (12905)
6656 11:38:26.845881 Driver version : 6.1.96
6657 11:38:26.861426 Interface Info:
6658 11:38:26.878665 <LAVA_SIGNAL_TESTSET START Interface-Info>
6659 11:38:26.878953 Received signal: <TESTSET> START Interface-Info
6660 11:38:26.879035 Starting test_set Interface-Info
6661 11:38:26.881935 ID : 0x03000002
6662 11:38:26.894042 Type : V4L Video
6663 11:38:26.909383 Entity Info:
6664 11:38:26.917351 <LAVA_SIGNAL_TESTSET STOP>
6665 11:38:26.917612 Received signal: <TESTSET> STOP
6666 11:38:26.917688 Closing test_set Interface-Info
6667 11:38:26.928117 <LAVA_SIGNAL_TESTSET START Entity-Info>
6668 11:38:26.928372 Received signal: <TESTSET> START Entity-Info
6669 11:38:26.928444 Starting test_set Entity-Info
6670 11:38:26.931000 ID : 0x00000001 (1)
6671 11:38:26.946470 Name : HD WebCam: HD WebCam
6672 11:38:26.958107 Function : V4L2 I/O
6673 11:38:26.971184 Flags : default
6674 11:38:26.985805 Pad 0x01000007 : 0: Sink
6675 11:38:27.008597 Link 0x02000013: from remote pad 0x100000a of entity 'Extension 4' (Video Pixel Formatter): Data, Enabled, Immutable
6676 11:38:27.012600
6677 11:38:27.024535 Required ioctls:
6678 11:38:27.034141 <LAVA_SIGNAL_TESTSET STOP>
6679 11:38:27.034398 Received signal: <TESTSET> STOP
6680 11:38:27.034468 Closing test_set Entity-Info
6681 11:38:27.045551 <LAVA_SIGNAL_TESTSET START Required-ioctls>
6682 11:38:27.045836 Received signal: <TESTSET> START Required-ioctls
6683 11:38:27.045922 Starting test_set Required-ioctls
6684 11:38:27.048592 test MC information (see 'Media Driver Info' above): OK
6685 11:38:27.080560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
6686 11:38:27.080823 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
6688 11:38:27.083927 test VIDIOC_QUERYCAP: OK
6689 11:38:27.109276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6690 11:38:27.109532 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6692 11:38:27.112752 test invalid ioctls: OK
6693 11:38:27.135320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
6694 11:38:27.135407
6695 11:38:27.135654 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
6697 11:38:27.150681 Allow for multiple opens:
6698 11:38:27.161270 <LAVA_SIGNAL_TESTSET STOP>
6699 11:38:27.161533 Received signal: <TESTSET> STOP
6700 11:38:27.161604 Closing test_set Required-ioctls
6701 11:38:27.172115 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
6702 11:38:27.172371 Received signal: <TESTSET> START Allow-for-multiple-opens
6703 11:38:27.172441 Starting test_set Allow-for-multiple-opens
6704 11:38:27.175086 test second /dev/video0 open: OK
6705 11:38:27.202472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
6706 11:38:27.202735 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
6708 11:38:27.205871 test VIDIOC_QUERYCAP: OK
6709 11:38:27.237515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6710 11:38:27.237772 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6712 11:38:27.240794 test VIDIOC_G/S_PRIORITY: OK
6713 11:38:27.270387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
6714 11:38:27.270672 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
6716 11:38:27.273445 test for unlimited opens: OK
6717 11:38:27.301671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
6718 11:38:27.301785
6719 11:38:27.302063 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
6721 11:38:27.316126 Debug ioctls:
6722 11:38:27.325511 <LAVA_SIGNAL_TESTSET STOP>
6723 11:38:27.325766 Received signal: <TESTSET> STOP
6724 11:38:27.325841 Closing test_set Allow-for-multiple-opens
6725 11:38:27.336218 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
6726 11:38:27.336472 Received signal: <TESTSET> START Debug-ioctls
6727 11:38:27.336548 Starting test_set Debug-ioctls
6728 11:38:27.339710 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
6729 11:38:27.368969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
6730 11:38:27.369230 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
6732 11:38:27.375380 test VIDIOC_LOG_STATUS: OK (Not Supported)
6733 11:38:27.399865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
6734 11:38:27.399977
6735 11:38:27.400235 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
6737 11:38:27.416169 Input ioctls:
6738 11:38:27.424363 <LAVA_SIGNAL_TESTSET STOP>
6739 11:38:27.424617 Received signal: <TESTSET> STOP
6740 11:38:27.424690 Closing test_set Debug-ioctls
6741 11:38:27.433877 <LAVA_SIGNAL_TESTSET START Input-ioctls>
6742 11:38:27.434131 Received signal: <TESTSET> START Input-ioctls
6743 11:38:27.434206 Starting test_set Input-ioctls
6744 11:38:27.437210 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
6745 11:38:27.463260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
6746 11:38:27.463474 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
6748 11:38:27.466332 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6749 11:38:27.491101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6750 11:38:27.491356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6752 11:38:27.497420 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
6753 11:38:27.520873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
6754 11:38:27.521133 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
6756 11:38:27.527180 test VIDIOC_ENUMAUDIO: OK (Not Supported)
6757 11:38:27.550711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
6758 11:38:27.550991 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
6760 11:38:27.553965 test VIDIOC_G/S/ENUMINPUT: OK
6761 11:38:27.579682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
6762 11:38:27.579947 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
6764 11:38:27.586317 test VIDIOC_G/S_AUDIO: OK (Not Supported)
6765 11:38:27.610418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
6766 11:38:27.610677 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
6768 11:38:27.613272 Inputs: 1 Audio Inputs: 0 Tuners: 0
6769 11:38:27.627423
6770 11:38:27.647650 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
6771 11:38:27.675129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
6772 11:38:27.675392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
6774 11:38:27.681720 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6775 11:38:27.706366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6776 11:38:27.706626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6778 11:38:27.712985 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
6779 11:38:27.735402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
6780 11:38:27.735672 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
6782 11:38:27.741932 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
6783 11:38:27.766421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
6784 11:38:27.766680 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
6786 11:38:27.773283 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
6787 11:38:27.798615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
6788 11:38:27.798871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
6790 11:38:27.802623
6791 11:38:27.825629 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
6792 11:38:27.854022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
6793 11:38:27.854280 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
6795 11:38:27.860434 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
6796 11:38:27.888822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
6797 11:38:27.889101 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
6799 11:38:27.892032 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
6800 11:38:27.914278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
6801 11:38:27.914554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
6803 11:38:27.920840 test VIDIOC_G/S_EDID: OK (Not Supported)
6804 11:38:27.945544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
6805 11:38:27.945632
6806 11:38:27.945867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
6808 11:38:27.962200 Control ioctls (Input 0):
6809 11:38:27.971697 <LAVA_SIGNAL_TESTSET STOP>
6810 11:38:27.971978 Received signal: <TESTSET> STOP
6811 11:38:27.972052 Closing test_set Input-ioctls
6812 11:38:27.983197 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
6813 11:38:27.983477 Received signal: <TESTSET> START Control-ioctls-Input-0
6814 11:38:27.983586 Starting test_set Control-ioctls-Input-0
6815 11:38:27.986281 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
6816 11:38:28.016650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
6817 11:38:28.016745 test VIDIOC_QUERYCTRL: OK
6818 11:38:28.016980 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
6820 11:38:28.041075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
6821 11:38:28.041334 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
6823 11:38:28.044231 test VIDIOC_G/S_CTRL: OK
6824 11:38:28.075133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
6825 11:38:28.075401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
6827 11:38:28.078416 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
6828 11:38:28.106060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
6829 11:38:28.106321 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
6831 11:38:28.112753 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
6832 11:38:28.142524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
6833 11:38:28.142790 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
6835 11:38:28.145624 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
6836 11:38:28.170205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
6837 11:38:28.170481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
6839 11:38:28.176412 Standard Controls: 15 Private Controls: 0
6840 11:38:28.183901
6841 11:38:28.198889 Format ioctls (Input 0):
6842 11:38:28.209221 <LAVA_SIGNAL_TESTSET STOP>
6843 11:38:28.209480 Received signal: <TESTSET> STOP
6844 11:38:28.209551 Closing test_set Control-ioctls-Input-0
6845 11:38:28.220588 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
6846 11:38:28.220841 Received signal: <TESTSET> START Format-ioctls-Input-0
6847 11:38:28.220912 Starting test_set Format-ioctls-Input-0
6848 11:38:28.223813 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
6849 11:38:28.253369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
6850 11:38:28.253637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
6852 11:38:28.256380 test VIDIOC_G/S_PARM: OK
6853 11:38:28.280510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
6854 11:38:28.280771 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
6856 11:38:28.283785 test VIDIOC_G_FBUF: OK (Not Supported)
6857 11:38:28.311881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
6858 11:38:28.312139 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
6860 11:38:28.314896 test VIDIOC_G_FMT: OK
6861 11:38:28.345188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
6862 11:38:28.345447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
6864 11:38:28.348586 test VIDIOC_TRY_FMT: OK
6865 11:38:28.374885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
6866 11:38:28.375142 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
6868 11:38:28.381201 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
6869 11:38:28.390155 test VIDIOC_S_FMT: OK
6870 11:38:28.418045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
6871 11:38:28.418308 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
6873 11:38:28.421000 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
6874 11:38:28.447163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
6875 11:38:28.447417 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
6877 11:38:28.450020 test Cropping: OK (Not Supported)
6878 11:38:28.480999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
6879 11:38:28.481258 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
6881 11:38:28.484134 test Composing: OK (Not Supported)
6882 11:38:28.513770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
6883 11:38:28.514030 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
6885 11:38:28.516373 test Scaling: OK (Not Supported)
6886 11:38:28.544883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
6887 11:38:28.544971
6888 11:38:28.545203 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
6890 11:38:28.559725 Codec ioctls (Input 0):
6891 11:38:28.569658 <LAVA_SIGNAL_TESTSET STOP>
6892 11:38:28.569911 Received signal: <TESTSET> STOP
6893 11:38:28.569983 Closing test_set Format-ioctls-Input-0
6894 11:38:28.581330 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
6895 11:38:28.581583 Received signal: <TESTSET> START Codec-ioctls-Input-0
6896 11:38:28.581654 Starting test_set Codec-ioctls-Input-0
6897 11:38:28.584433 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
6898 11:38:28.616149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
6899 11:38:28.616409 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
6901 11:38:28.622744 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
6902 11:38:28.647227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
6903 11:38:28.647476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
6905 11:38:28.653629 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
6906 11:38:28.678914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
6907 11:38:28.679005
6908 11:38:28.679240 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
6910 11:38:28.693707 Buffer ioctls (Input 0):
6911 11:38:28.703758 <LAVA_SIGNAL_TESTSET STOP>
6912 11:38:28.704009 Received signal: <TESTSET> STOP
6913 11:38:28.704076 Closing test_set Codec-ioctls-Input-0
6914 11:38:28.714966 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
6915 11:38:28.715219 Received signal: <TESTSET> START Buffer-ioctls-Input-0
6916 11:38:28.715289 Starting test_set Buffer-ioctls-Input-0
6917 11:38:28.718376 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
6918 11:38:28.750163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
6919 11:38:28.750418 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
6921 11:38:28.753186 test CREATE_BUFS maximum buffers: OK
6922 11:38:28.784585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
6923 11:38:28.784681 test VIDIOC_EXPBUF: OK
6924 11:38:28.784917 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
6926 11:38:28.811771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
6927 11:38:28.812029 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
6929 11:38:28.815226 test Requests: OK (Not Supported)
6930 11:38:28.841668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
6931 11:38:28.841755
6932 11:38:28.841989 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
6934 11:38:28.856205 Test input 0:
6935 11:38:28.868828
6936 11:38:28.882744 Streaming ioctls:
6937 11:38:28.892912 <LAVA_SIGNAL_TESTSET STOP>
6938 11:38:28.893170 Received signal: <TESTSET> STOP
6939 11:38:28.893242 Closing test_set Buffer-ioctls-Input-0
6940 11:38:28.903817 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
6941 11:38:28.904070 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
6942 11:38:28.904139 Starting test_set Streaming-ioctls_Test-input-0
6943 11:38:28.907021 test read/write: OK (Not Supported)
6944 11:38:28.935404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
6945 11:38:28.935667 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
6947 11:38:28.938707 test blocking wait: OK
6948 11:38:28.967048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
6949 11:38:28.967302 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
6951 11:38:28.973388 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6952 11:38:28.983100 test MMAP (no poll): FAIL
6953 11:38:29.011893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
6954 11:38:29.012153 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
6956 11:38:29.018231 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6957 11:38:29.029518 test MMAP (select): FAIL
6958 11:38:29.058316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
6959 11:38:29.058572 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
6961 11:38:29.064799 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6962 11:38:29.072585 test MMAP (epoll): FAIL
6963 11:38:29.102883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
6964 11:38:29.102974
6965 11:38:29.103209 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
6967 11:38:29.336056
6968 11:38:29.347633 test USERPTR (no poll): OK
6969 11:38:29.378514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
6970 11:38:29.378654
6971 11:38:29.378910 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
6973 11:38:29.614827
6974 11:38:29.627999 test USERPTR (select): OK
6975 11:38:29.654949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
6976 11:38:29.655763 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
6978 11:38:29.661294 test DMABUF: Cannot test, specify --expbuf-device
6979 11:38:29.666600
6980 11:38:29.687655 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 1
6981 11:38:29.695048 <LAVA_TEST_RUNNER EXIT>
6982 11:38:29.695863 ok: lava_test_shell seems to have completed
6983 11:38:29.696383 Marking unfinished test run as failed
6985 11:38:29.704820 device-presence: pass
MC-information-see-Media-Driver-Info-above:
set: Required-ioctls
result: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video0-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls-Input-0
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls-Input-0
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls-Input-0
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_S_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls-Input-0
result: pass
Cropping:
set: Format-ioctls-Input-0
result: pass
Composing:
set: Format-ioctls-Input-0
result: pass
Scaling:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls-Input-0
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls-Input-0
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls-Input-0
result: pass
Requests:
set: Buffer-ioctls-Input-0
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: pass
MMAP-no-poll:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-no-poll:
set: Streaming-ioctls_Test-input-0
result: pass
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: pass
6986 11:38:29.705665 end: 3.1 lava-test-shell (duration 00:00:11) [common]
6987 11:38:29.706273 end: 3 lava-test-retry (duration 00:00:11) [common]
6988 11:38:29.706844 start: 4 finalize (timeout 00:08:11) [common]
6989 11:38:29.707495 start: 4.1 power-off (timeout 00:00:30) [common]
6990 11:38:29.708208 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=off']
6991 11:38:31.785244 >> Command sent successfully.
6992 11:38:31.789136 Returned 0 in 2 seconds
6993 11:38:31.789327 end: 4.1 power-off (duration 00:00:02) [common]
6995 11:38:31.789603 start: 4.2 read-feedback (timeout 00:08:09) [common]
6996 11:38:31.789789 Listened to connection for namespace 'common' for up to 1s
6997 11:38:32.790785 Finalising connection for namespace 'common'
6998 11:38:32.790951 Disconnecting from shell: Finalise
6999 11:38:32.791032 / #
7000 11:38:32.891298 end: 4.2 read-feedback (duration 00:00:01) [common]
7001 11:38:32.891480 end: 4 finalize (duration 00:00:03) [common]
7002 11:38:32.891601 Cleaning after the job
7003 11:38:32.891719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/ramdisk
7004 11:38:32.896646 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/kernel
7005 11:38:32.911658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/dtb
7006 11:38:32.911897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864642/tftp-deploy-7mqfe8wa/modules
7007 11:38:32.918207 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864642
7008 11:38:32.991404 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864642
7009 11:38:32.991943 Job finished correctly