Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 11:35:47.237970 lava-dispatcher, installed at version: 2024.05
2 11:35:47.238258 start: 0 validate
3 11:35:47.238409 Start time: 2024-07-17 11:35:47.238403+00:00 (UTC)
4 11:35:47.238578 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:35:47.238775 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:35:47.521066 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:35:47.521225 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:35:47.778479 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:35:47.778649 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:35:48.035741 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:35:48.035886 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:35:48.295092 validate duration: 1.06
14 11:35:48.295338 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:35:48.295431 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:35:48.295516 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:35:48.295664 Not decompressing ramdisk as can be used compressed.
18 11:35:48.295753 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 11:35:48.295814 saving as /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/ramdisk/rootfs.cpio.gz
20 11:35:48.295871 total size: 28105535 (26 MB)
21 11:35:48.296786 progress 0 % (0 MB)
22 11:35:48.304240 progress 5 % (1 MB)
23 11:35:48.311524 progress 10 % (2 MB)
24 11:35:48.318739 progress 15 % (4 MB)
25 11:35:48.325751 progress 20 % (5 MB)
26 11:35:48.332980 progress 25 % (6 MB)
27 11:35:48.340858 progress 30 % (8 MB)
28 11:35:48.348489 progress 35 % (9 MB)
29 11:35:48.355928 progress 40 % (10 MB)
30 11:35:48.363368 progress 45 % (12 MB)
31 11:35:48.371311 progress 50 % (13 MB)
32 11:35:48.378602 progress 55 % (14 MB)
33 11:35:48.385580 progress 60 % (16 MB)
34 11:35:48.392594 progress 65 % (17 MB)
35 11:35:48.399625 progress 70 % (18 MB)
36 11:35:48.406673 progress 75 % (20 MB)
37 11:35:48.413696 progress 80 % (21 MB)
38 11:35:48.420649 progress 85 % (22 MB)
39 11:35:48.427477 progress 90 % (24 MB)
40 11:35:48.434330 progress 95 % (25 MB)
41 11:35:48.441210 progress 100 % (26 MB)
42 11:35:48.441414 26 MB downloaded in 0.15 s (184.17 MB/s)
43 11:35:48.441570 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:35:48.441797 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:35:48.441881 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:35:48.441959 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:35:48.442105 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:35:48.442168 saving as /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/kernel/Image
50 11:35:48.442222 total size: 54813184 (52 MB)
51 11:35:48.442279 No compression specified
52 11:35:48.443245 progress 0 % (0 MB)
53 11:35:48.456720 progress 5 % (2 MB)
54 11:35:48.470426 progress 10 % (5 MB)
55 11:35:48.483734 progress 15 % (7 MB)
56 11:35:48.497136 progress 20 % (10 MB)
57 11:35:48.510687 progress 25 % (13 MB)
58 11:35:48.524009 progress 30 % (15 MB)
59 11:35:48.537296 progress 35 % (18 MB)
60 11:35:48.550637 progress 40 % (20 MB)
61 11:35:48.563857 progress 45 % (23 MB)
62 11:35:48.577339 progress 50 % (26 MB)
63 11:35:48.590774 progress 55 % (28 MB)
64 11:35:48.604032 progress 60 % (31 MB)
65 11:35:48.617407 progress 65 % (34 MB)
66 11:35:48.630596 progress 70 % (36 MB)
67 11:35:48.644015 progress 75 % (39 MB)
68 11:35:48.657562 progress 80 % (41 MB)
69 11:35:48.671038 progress 85 % (44 MB)
70 11:35:48.684587 progress 90 % (47 MB)
71 11:35:48.698282 progress 95 % (49 MB)
72 11:35:48.711439 progress 100 % (52 MB)
73 11:35:48.711662 52 MB downloaded in 0.27 s (194.01 MB/s)
74 11:35:48.711810 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:35:48.712018 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:35:48.712098 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:35:48.712172 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:35:48.712303 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:35:48.712368 saving as /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/dtb/mt8192-asurada-spherion-r0.dtb
81 11:35:48.712420 total size: 47258 (0 MB)
82 11:35:48.712471 No compression specified
83 11:35:48.713508 progress 69 % (0 MB)
84 11:35:48.713793 progress 100 % (0 MB)
85 11:35:48.713936 0 MB downloaded in 0.00 s (29.77 MB/s)
86 11:35:48.714094 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:35:48.714296 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:35:48.714370 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:35:48.714443 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:35:48.714550 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:35:48.714611 saving as /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/modules/modules.tar
93 11:35:48.714663 total size: 8610184 (8 MB)
94 11:35:48.714715 Using unxz to decompress xz
95 11:35:48.715968 progress 0 % (0 MB)
96 11:35:48.736047 progress 5 % (0 MB)
97 11:35:48.759884 progress 10 % (0 MB)
98 11:35:48.783343 progress 15 % (1 MB)
99 11:35:48.807006 progress 20 % (1 MB)
100 11:35:48.829763 progress 25 % (2 MB)
101 11:35:48.852460 progress 30 % (2 MB)
102 11:35:48.874151 progress 35 % (2 MB)
103 11:35:48.900595 progress 40 % (3 MB)
104 11:35:48.925481 progress 45 % (3 MB)
105 11:35:48.950016 progress 50 % (4 MB)
106 11:35:48.973951 progress 55 % (4 MB)
107 11:35:48.997832 progress 60 % (4 MB)
108 11:35:49.021278 progress 65 % (5 MB)
109 11:35:49.047870 progress 70 % (5 MB)
110 11:35:49.074546 progress 75 % (6 MB)
111 11:35:49.101337 progress 80 % (6 MB)
112 11:35:49.124756 progress 85 % (7 MB)
113 11:35:49.147656 progress 90 % (7 MB)
114 11:35:49.170657 progress 95 % (7 MB)
115 11:35:49.193002 progress 100 % (8 MB)
116 11:35:49.198325 8 MB downloaded in 0.48 s (16.98 MB/s)
117 11:35:49.198470 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:35:49.198678 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:35:49.198757 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:35:49.198833 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:35:49.198904 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:35:49.198975 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:35:49.199143 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n
125 11:35:49.199312 makedir: /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin
126 11:35:49.199434 makedir: /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/tests
127 11:35:49.199555 makedir: /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/results
128 11:35:49.199670 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-add-keys
129 11:35:49.199843 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-add-sources
130 11:35:49.199992 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-background-process-start
131 11:35:49.200126 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-background-process-stop
132 11:35:49.200254 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-common-functions
133 11:35:49.200372 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-echo-ipv4
134 11:35:49.200487 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-install-packages
135 11:35:49.200603 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-installed-packages
136 11:35:49.200716 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-os-build
137 11:35:49.200852 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-probe-channel
138 11:35:49.200967 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-probe-ip
139 11:35:49.201081 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-target-ip
140 11:35:49.201198 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-target-mac
141 11:35:49.201312 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-target-storage
142 11:35:49.201429 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-case
143 11:35:49.201542 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-event
144 11:35:49.201654 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-feedback
145 11:35:49.201767 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-raise
146 11:35:49.201878 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-reference
147 11:35:49.201993 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-runner
148 11:35:49.202129 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-set
149 11:35:49.202273 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-test-shell
150 11:35:49.202403 Updating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-install-packages (oe)
151 11:35:49.202545 Updating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/bin/lava-installed-packages (oe)
152 11:35:49.202664 Creating /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/environment
153 11:35:49.202754 LAVA metadata
154 11:35:49.202820 - LAVA_JOB_ID=14864641
155 11:35:49.202876 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:35:49.202965 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:35:49.203026 skipped lava-vland-overlay
158 11:35:49.203093 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:35:49.203182 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:35:49.203256 skipped lava-multinode-overlay
161 11:35:49.203322 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:35:49.203392 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:35:49.203457 Loading test definitions
164 11:35:49.203533 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:35:49.203609 Using /lava-14864641 at stage 0
166 11:35:49.203903 uuid=14864641_1.5.2.3.1 testdef=None
167 11:35:49.203984 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:35:49.204057 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:35:49.204476 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:35:49.204670 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:35:49.205214 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:35:49.205416 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:35:49.205944 runner path: /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/0/tests/0_v4l2-compliance-uvc test_uuid 14864641_1.5.2.3.1
176 11:35:49.206162 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:35:49.206351 Creating lava-test-runner.conf files
179 11:35:49.206408 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864641/lava-overlay-v9nmim3n/lava-14864641/0 for stage 0
180 11:35:49.206486 - 0_v4l2-compliance-uvc
181 11:35:49.206573 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:35:49.206648 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:35:49.213101 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:35:49.213194 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:35:49.213280 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:35:49.213359 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:35:49.213435 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:35:50.000036 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:35:50.000196 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:35:50.000303 extracting modules file /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864641/extract-overlay-ramdisk-9ut59y6c/ramdisk
191 11:35:50.252889 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:35:50.253014 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:35:50.253106 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864641/compress-overlay-5lw0duhd/overlay-1.5.2.4.tar.gz to ramdisk
194 11:35:50.253165 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864641/compress-overlay-5lw0duhd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864641/extract-overlay-ramdisk-9ut59y6c/ramdisk
195 11:35:50.259682 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:35:50.259774 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:35:50.259856 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:35:50.259933 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:35:50.259995 Building ramdisk /var/lib/lava/dispatcher/tmp/14864641/extract-overlay-ramdisk-9ut59y6c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864641/extract-overlay-ramdisk-9ut59y6c/ramdisk
200 11:35:50.870737 >> 275512 blocks
201 11:35:55.116443 rename /var/lib/lava/dispatcher/tmp/14864641/extract-overlay-ramdisk-9ut59y6c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/ramdisk/ramdisk.cpio.gz
202 11:35:55.116625 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:35:55.116769 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:35:55.116895 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:35:55.117017 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/kernel/Image']
206 11:36:08.911703 Returned 0 in 13 seconds
207 11:36:08.911852 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/kernel/image.itb
208 11:36:09.521439 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:36:09.521570 output: Created: Wed Jul 17 12:36:09 2024
210 11:36:09.521632 output: Image 0 (kernel-1)
211 11:36:09.521686 output: Description:
212 11:36:09.521737 output: Created: Wed Jul 17 12:36:09 2024
213 11:36:09.521787 output: Type: Kernel Image
214 11:36:09.521835 output: Compression: lzma compressed
215 11:36:09.521901 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:36:09.521977 output: Architecture: AArch64
217 11:36:09.522080 output: OS: Linux
218 11:36:09.522130 output: Load Address: 0x00000000
219 11:36:09.522178 output: Entry Point: 0x00000000
220 11:36:09.522226 output: Hash algo: crc32
221 11:36:09.522273 output: Hash value: 83448d17
222 11:36:09.522320 output: Image 1 (fdt-1)
223 11:36:09.522367 output: Description: mt8192-asurada-spherion-r0
224 11:36:09.522413 output: Created: Wed Jul 17 12:36:09 2024
225 11:36:09.522460 output: Type: Flat Device Tree
226 11:36:09.522506 output: Compression: uncompressed
227 11:36:09.522553 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:36:09.522599 output: Architecture: AArch64
229 11:36:09.522645 output: Hash algo: crc32
230 11:36:09.522691 output: Hash value: 0f8e4d2e
231 11:36:09.522737 output: Image 2 (ramdisk-1)
232 11:36:09.522783 output: Description: unavailable
233 11:36:09.522829 output: Created: Wed Jul 17 12:36:09 2024
234 11:36:09.522876 output: Type: RAMDisk Image
235 11:36:09.522923 output: Compression: uncompressed
236 11:36:09.522970 output: Data Size: 41207950 Bytes = 40242.14 KiB = 39.30 MiB
237 11:36:09.523016 output: Architecture: AArch64
238 11:36:09.523062 output: OS: Linux
239 11:36:09.523108 output: Load Address: unavailable
240 11:36:09.523154 output: Entry Point: unavailable
241 11:36:09.523200 output: Hash algo: crc32
242 11:36:09.523256 output: Hash value: 852c1f6d
243 11:36:09.523303 output: Default Configuration: 'conf-1'
244 11:36:09.523350 output: Configuration 0 (conf-1)
245 11:36:09.523396 output: Description: mt8192-asurada-spherion-r0
246 11:36:09.523442 output: Kernel: kernel-1
247 11:36:09.523488 output: Init Ramdisk: ramdisk-1
248 11:36:09.523536 output: FDT: fdt-1
249 11:36:09.523582 output: Loadables: kernel-1
250 11:36:09.523661 output:
251 11:36:09.523759 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:36:09.523831 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:36:09.523912 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:36:09.524011 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:36:09.524101 No LXC device requested
256 11:36:09.524175 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:36:09.524246 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:36:09.524314 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:36:09.524368 Checking files for TFTP limit of 4294967296 bytes.
260 11:36:09.524726 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:36:09.524811 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:36:09.524888 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:36:09.524971 substitutions:
264 11:36:09.525029 - {DTB}: 14864641/tftp-deploy-ttb4uouz/dtb/mt8192-asurada-spherion-r0.dtb
265 11:36:09.525083 - {INITRD}: 14864641/tftp-deploy-ttb4uouz/ramdisk/ramdisk.cpio.gz
266 11:36:09.525134 - {KERNEL}: 14864641/tftp-deploy-ttb4uouz/kernel/Image
267 11:36:09.525184 - {LAVA_MAC}: None
268 11:36:09.525234 - {PRESEED_CONFIG}: None
269 11:36:09.525282 - {PRESEED_LOCAL}: None
270 11:36:09.525329 - {RAMDISK}: 14864641/tftp-deploy-ttb4uouz/ramdisk/ramdisk.cpio.gz
271 11:36:09.525412 - {ROOT_PART}: None
272 11:36:09.525461 - {ROOT}: None
273 11:36:09.525509 - {SERVER_IP}: 192.168.201.1
274 11:36:09.525557 - {TEE}: None
275 11:36:09.525618 Parsed boot commands:
276 11:36:09.525677 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:36:09.525815 Parsed boot commands: tftpboot 192.168.201.1 14864641/tftp-deploy-ttb4uouz/kernel/image.itb 14864641/tftp-deploy-ttb4uouz/kernel/cmdline
278 11:36:09.525924 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:36:09.526037 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:36:09.526139 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:36:09.526237 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:36:09.526317 Not connected, no need to disconnect.
283 11:36:09.526410 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:36:09.526505 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:36:09.526586 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 11:36:09.529493 Setting prompt string to ['lava-test: # ']
287 11:36:09.529818 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:36:09.529928 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:36:09.530027 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:36:09.530121 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:36:09.530319 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 11:36:18.647786 >> Command sent successfully.
293 11:36:18.651070 Returned 0 in 9 seconds
294 11:36:18.651221 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:36:18.651455 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:36:18.651558 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:36:18.651643 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:36:18.651731 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:36:18.651829 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:36:18.652354 [Enter `^Ec?' for help]
302 11:36:20.263464
303 11:36:20.263580
304 11:36:20.263669 F0: 102B 0000
305 11:36:20.263760
306 11:36:20.263843 F3: 1001 0000 [0200]
307 11:36:20.267995
308 11:36:20.268070 F3: 1001 0000
309 11:36:20.268128
310 11:36:20.268181 F7: 102D 0000
311 11:36:20.268232
312 11:36:20.268281 F1: 0000 0000
313 11:36:20.271818
314 11:36:20.271891 V0: 0000 0000 [0001]
315 11:36:20.271949
316 11:36:20.272002 00: 0007 8000
317 11:36:20.272055
318 11:36:20.275190 01: 0000 0000
319 11:36:20.275265
320 11:36:20.275323 BP: 0C00 0209 [0000]
321 11:36:20.275375
322 11:36:20.278544 G0: 1182 0000
323 11:36:20.278621
324 11:36:20.278684 EC: 0000 0021 [4000]
325 11:36:20.278739
326 11:36:20.282243 S7: 0000 0000 [0000]
327 11:36:20.282321
328 11:36:20.282379 CC: 0000 0000 [0001]
329 11:36:20.282433
330 11:36:20.286061 T0: 0000 0040 [010F]
331 11:36:20.286135
332 11:36:20.286193 Jump to BL
333 11:36:20.286247
334 11:36:20.311084
335 11:36:20.311169
336 11:36:20.318299 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:36:20.321834 ARM64: Exception handlers installed.
338 11:36:20.325013 ARM64: Testing exception
339 11:36:20.328565 ARM64: Done test exception
340 11:36:20.335415 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:36:20.345897 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:36:20.352470 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:36:20.362946 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:36:20.369192 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:36:20.375630 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:36:20.387439 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:36:20.393746 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:36:20.413559 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:36:20.417035 WDT: Last reset was cold boot
350 11:36:20.420419 SPI1(PAD0) initialized at 2873684 Hz
351 11:36:20.423553 SPI5(PAD0) initialized at 992727 Hz
352 11:36:20.426998 VBOOT: Loading verstage.
353 11:36:20.433485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:36:20.437189 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:36:20.440302 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:36:20.443477 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:36:20.451230 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:36:20.457571 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:36:20.468903 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:36:20.469001
361 11:36:20.469085
362 11:36:20.478678 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:36:20.482330 ARM64: Exception handlers installed.
364 11:36:20.485077 ARM64: Testing exception
365 11:36:20.485151 ARM64: Done test exception
366 11:36:20.492107 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:36:20.495294 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:36:20.509693 Probing TPM: . done!
369 11:36:20.509768 TPM ready after 0 ms
370 11:36:20.516450 Connected to device vid:did:rid of 1ae0:0028:00
371 11:36:20.523017 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 11:36:20.563599 Initialized TPM device CR50 revision 0
373 11:36:20.574903 tlcl_send_startup: Startup return code is 0
374 11:36:20.574987 TPM: setup succeeded
375 11:36:20.586549 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:36:20.595256 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:36:20.605954 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:36:20.614457 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:36:20.617684 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:36:20.621534 in-header: 03 07 00 00 08 00 00 00
381 11:36:20.624140 in-data: aa e4 47 04 13 02 00 00
382 11:36:20.628156 Chrome EC: UHEPI supported
383 11:36:20.634599 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:36:20.637944 in-header: 03 a9 00 00 08 00 00 00
385 11:36:20.641298 in-data: 84 60 60 08 00 00 00 00
386 11:36:20.641373 Phase 1
387 11:36:20.644639 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:36:20.651151 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:36:20.657848 VB2:vb2_check_recovery() Recovery was requested manually
390 11:36:20.661019 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:36:20.664851 Recovery requested (1009000e)
392 11:36:20.673099 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:36:20.678216 tlcl_extend: response is 0
394 11:36:20.688780 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:36:20.692508 tlcl_extend: response is 0
396 11:36:20.698723 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:36:20.719557 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:36:20.726459 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:36:20.726539
400 11:36:20.726616
401 11:36:20.736936 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:36:20.740395 ARM64: Exception handlers installed.
403 11:36:20.740473 ARM64: Testing exception
404 11:36:20.743451 ARM64: Done test exception
405 11:36:20.764956 pmic_efuse_setting: Set efuses in 11 msecs
406 11:36:20.768308 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:36:20.774785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:36:20.777945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:36:20.784895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:36:20.788062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:36:20.791565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:36:20.798098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:36:20.801394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:36:20.808013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:36:20.811330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:36:20.817857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:36:20.821591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:36:20.824514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:36:20.831650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:36:20.838238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:36:20.841543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:36:20.848364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:36:20.855268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:36:20.858283 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:36:20.865213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:36:20.871702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:36:20.874913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:36:20.881460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:36:20.888085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:36:20.891765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:36:20.898386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:36:20.905100 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:36:20.908307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:36:20.914843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:36:20.918991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:36:20.921588 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:36:20.928793 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:36:20.931922 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:36:20.938793 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:36:20.945164 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:36:20.948476 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:36:20.955075 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:36:20.958240 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:36:20.962196 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:36:20.969310 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:36:20.972825 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:36:20.976289 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:36:20.982589 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:36:20.986130 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:36:20.989533 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:36:20.992855 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:36:20.999552 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:36:21.002885 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:36:21.006146 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:36:21.012718 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:36:21.016003 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:36:21.019322 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:36:21.026227 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:36:21.036254 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:36:21.039772 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:36:21.049912 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:36:21.056075 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:36:21.063446 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:36:21.066128 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:36:21.070183 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:36:21.077394 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x15
467 11:36:21.083878 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:36:21.087537 [RTC]rtc_osc_init,62: osc32con val = 0xde71
469 11:36:21.090806 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:36:21.101789 [RTC]rtc_get_frequency_meter,154: input=15, output=761
471 11:36:21.111242 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 11:36:21.120947 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 11:36:21.130825 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 11:36:21.139760 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 11:36:21.149153 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 11:36:21.158996 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 11:36:21.162263 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:36:21.169401 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:36:21.172870 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:36:21.176030 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:36:21.182719 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:36:21.186034 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:36:21.189763 ADC[4]: Raw value=905465 ID=7
484 11:36:21.189851 ADC[3]: Raw value=213441 ID=1
485 11:36:21.192985 RAM Code: 0x71
486 11:36:21.196218 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:36:21.202596 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:36:21.209763 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:36:21.216278 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:36:21.219351 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:36:21.223152 in-header: 03 07 00 00 08 00 00 00
492 11:36:21.226336 in-data: aa e4 47 04 13 02 00 00
493 11:36:21.229380 Chrome EC: UHEPI supported
494 11:36:21.236114 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:36:21.239674 in-header: 03 a9 00 00 08 00 00 00
496 11:36:21.242988 in-data: 84 60 60 08 00 00 00 00
497 11:36:21.246093 MRC: failed to locate region type 0.
498 11:36:21.252912 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:36:21.256366 DRAM-K: Running full calibration
500 11:36:21.262690 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:36:21.262758 header.status = 0x0
502 11:36:21.266142 header.version = 0x6 (expected: 0x6)
503 11:36:21.269807 header.size = 0xd00 (expected: 0xd00)
504 11:36:21.272711 header.flags = 0x0
505 11:36:21.279404 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:36:21.296676 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 11:36:21.303113 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:36:21.306374 dram_init: ddr_geometry: 2
509 11:36:21.310060 [EMI] MDL number = 2
510 11:36:21.310150 [EMI] Get MDL freq = 0
511 11:36:21.313280 dram_init: ddr_type: 0
512 11:36:21.313346 is_discrete_lpddr4: 1
513 11:36:21.316677 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:36:21.316771
515 11:36:21.316901
516 11:36:21.320109 [Bian_co] ETT version 0.0.0.1
517 11:36:21.326617 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:36:21.326714
519 11:36:21.329773 dramc_set_vcore_voltage set vcore to 650000
520 11:36:21.329862 Read voltage for 800, 4
521 11:36:21.333506 Vio18 = 0
522 11:36:21.333595 Vcore = 650000
523 11:36:21.333674 Vdram = 0
524 11:36:21.336897 Vddq = 0
525 11:36:21.336986 Vmddr = 0
526 11:36:21.340380 dram_init: config_dvfs: 1
527 11:36:21.343466 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:36:21.350099 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:36:21.353700 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 11:36:21.357064 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 11:36:21.360301 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 11:36:21.363904 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 11:36:21.367841 MEM_TYPE=3, freq_sel=18
534 11:36:21.370975 sv_algorithm_assistance_LP4_1600
535 11:36:21.374530 ============ PULL DRAM RESETB DOWN ============
536 11:36:21.378251 ========== PULL DRAM RESETB DOWN end =========
537 11:36:21.381829 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:36:21.385607 ===================================
539 11:36:21.389302 LPDDR4 DRAM CONFIGURATION
540 11:36:21.393064 ===================================
541 11:36:21.393167 EX_ROW_EN[0] = 0x0
542 11:36:21.396887 EX_ROW_EN[1] = 0x0
543 11:36:21.396986 LP4Y_EN = 0x0
544 11:36:21.400916 WORK_FSP = 0x0
545 11:36:21.401005 WL = 0x2
546 11:36:21.403738 RL = 0x2
547 11:36:21.403832 BL = 0x2
548 11:36:21.407182 RPST = 0x0
549 11:36:21.407277 RD_PRE = 0x0
550 11:36:21.410536 WR_PRE = 0x1
551 11:36:21.410628 WR_PST = 0x0
552 11:36:21.414241 DBI_WR = 0x0
553 11:36:21.414316 DBI_RD = 0x0
554 11:36:21.417242 OTF = 0x1
555 11:36:21.420793 ===================================
556 11:36:21.423892 ===================================
557 11:36:21.423983 ANA top config
558 11:36:21.427378 ===================================
559 11:36:21.430565 DLL_ASYNC_EN = 0
560 11:36:21.433807 ALL_SLAVE_EN = 1
561 11:36:21.433884 NEW_RANK_MODE = 1
562 11:36:21.437276 DLL_IDLE_MODE = 1
563 11:36:21.440954 LP45_APHY_COMB_EN = 1
564 11:36:21.444322 TX_ODT_DIS = 1
565 11:36:21.447641 NEW_8X_MODE = 1
566 11:36:21.447717 ===================================
567 11:36:21.450825 ===================================
568 11:36:21.454046 data_rate = 1600
569 11:36:21.457326 CKR = 1
570 11:36:21.460515 DQ_P2S_RATIO = 8
571 11:36:21.464318 ===================================
572 11:36:21.467661 CA_P2S_RATIO = 8
573 11:36:21.471021 DQ_CA_OPEN = 0
574 11:36:21.471100 DQ_SEMI_OPEN = 0
575 11:36:21.474141 CA_SEMI_OPEN = 0
576 11:36:21.477293 CA_FULL_RATE = 0
577 11:36:21.480655 DQ_CKDIV4_EN = 1
578 11:36:21.484060 CA_CKDIV4_EN = 1
579 11:36:21.487213 CA_PREDIV_EN = 0
580 11:36:21.487281 PH8_DLY = 0
581 11:36:21.490835 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:36:21.494209 DQ_AAMCK_DIV = 4
583 11:36:21.497756 CA_AAMCK_DIV = 4
584 11:36:21.500533 CA_ADMCK_DIV = 4
585 11:36:21.504237 DQ_TRACK_CA_EN = 0
586 11:36:21.504326 CA_PICK = 800
587 11:36:21.507586 CA_MCKIO = 800
588 11:36:21.510615 MCKIO_SEMI = 0
589 11:36:21.513966 PLL_FREQ = 3068
590 11:36:21.517497 DQ_UI_PI_RATIO = 32
591 11:36:21.520506 CA_UI_PI_RATIO = 0
592 11:36:21.524390 ===================================
593 11:36:21.527429 ===================================
594 11:36:21.527504 memory_type:LPDDR4
595 11:36:21.530767 GP_NUM : 10
596 11:36:21.534043 SRAM_EN : 1
597 11:36:21.534131 MD32_EN : 0
598 11:36:21.537406 ===================================
599 11:36:21.540569 [ANA_INIT] >>>>>>>>>>>>>>
600 11:36:21.543952 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:36:21.547651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:36:21.550974 ===================================
603 11:36:21.554210 data_rate = 1600,PCW = 0X7600
604 11:36:21.557307 ===================================
605 11:36:21.560699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:36:21.563952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:36:21.571009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:36:21.574315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:36:21.577761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:36:21.580861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:36:21.584080 [ANA_INIT] flow start
612 11:36:21.587902 [ANA_INIT] PLL >>>>>>>>
613 11:36:21.588000 [ANA_INIT] PLL <<<<<<<<
614 11:36:21.591212 [ANA_INIT] MIDPI >>>>>>>>
615 11:36:21.594501 [ANA_INIT] MIDPI <<<<<<<<
616 11:36:21.594588 [ANA_INIT] DLL >>>>>>>>
617 11:36:21.597868 [ANA_INIT] flow end
618 11:36:21.600771 ============ LP4 DIFF to SE enter ============
619 11:36:21.604495 ============ LP4 DIFF to SE exit ============
620 11:36:21.607584 [ANA_INIT] <<<<<<<<<<<<<
621 11:36:21.611192 [Flow] Enable top DCM control >>>>>
622 11:36:21.614466 [Flow] Enable top DCM control <<<<<
623 11:36:21.617695 Enable DLL master slave shuffle
624 11:36:21.624650 ==============================================================
625 11:36:21.624745 Gating Mode config
626 11:36:21.631194 ==============================================================
627 11:36:21.631262 Config description:
628 11:36:21.641284 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:36:21.647676 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:36:21.654678 SELPH_MODE 0: By rank 1: By Phase
631 11:36:21.658014 ==============================================================
632 11:36:21.661185 GAT_TRACK_EN = 1
633 11:36:21.664569 RX_GATING_MODE = 2
634 11:36:21.667850 RX_GATING_TRACK_MODE = 2
635 11:36:21.671086 SELPH_MODE = 1
636 11:36:21.674542 PICG_EARLY_EN = 1
637 11:36:21.677631 VALID_LAT_VALUE = 1
638 11:36:21.681070 ==============================================================
639 11:36:21.684412 Enter into Gating configuration >>>>
640 11:36:21.688201 Exit from Gating configuration <<<<
641 11:36:21.691311 Enter into DVFS_PRE_config >>>>>
642 11:36:21.704752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:36:21.708378 Exit from DVFS_PRE_config <<<<<
644 11:36:21.711145 Enter into PICG configuration >>>>
645 11:36:21.711213 Exit from PICG configuration <<<<
646 11:36:21.714451 [RX_INPUT] configuration >>>>>
647 11:36:21.718092 [RX_INPUT] configuration <<<<<
648 11:36:21.725113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:36:21.727924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:36:21.734614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:36:21.741719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:36:21.748480 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:36:21.754916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:36:21.758549 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:36:21.761299 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:36:21.764701 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:36:21.771413 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:36:21.774972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:36:21.778230 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:36:21.781630 ===================================
661 11:36:21.784808 LPDDR4 DRAM CONFIGURATION
662 11:36:21.788671 ===================================
663 11:36:21.788746 EX_ROW_EN[0] = 0x0
664 11:36:21.791317 EX_ROW_EN[1] = 0x0
665 11:36:21.795236 LP4Y_EN = 0x0
666 11:36:21.795315 WORK_FSP = 0x0
667 11:36:21.798464 WL = 0x2
668 11:36:21.798538 RL = 0x2
669 11:36:21.801982 BL = 0x2
670 11:36:21.802124 RPST = 0x0
671 11:36:21.805311 RD_PRE = 0x0
672 11:36:21.805409 WR_PRE = 0x1
673 11:36:21.808631 WR_PST = 0x0
674 11:36:21.808728 DBI_WR = 0x0
675 11:36:21.811878 DBI_RD = 0x0
676 11:36:21.811970 OTF = 0x1
677 11:36:21.815028 ===================================
678 11:36:21.818547 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:36:21.825241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:36:21.828104 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:36:21.832074 ===================================
682 11:36:21.834957 LPDDR4 DRAM CONFIGURATION
683 11:36:21.838417 ===================================
684 11:36:21.838522 EX_ROW_EN[0] = 0x10
685 11:36:21.841682 EX_ROW_EN[1] = 0x0
686 11:36:21.841756 LP4Y_EN = 0x0
687 11:36:21.844922 WORK_FSP = 0x0
688 11:36:21.844991 WL = 0x2
689 11:36:21.847903 RL = 0x2
690 11:36:21.848019 BL = 0x2
691 11:36:21.851777 RPST = 0x0
692 11:36:21.854545 RD_PRE = 0x0
693 11:36:21.854645 WR_PRE = 0x1
694 11:36:21.857976 WR_PST = 0x0
695 11:36:21.858120 DBI_WR = 0x0
696 11:36:21.861830 DBI_RD = 0x0
697 11:36:21.861963 OTF = 0x1
698 11:36:21.864617 ===================================
699 11:36:21.871340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:36:21.875172 nWR fixed to 40
701 11:36:21.878284 [ModeRegInit_LP4] CH0 RK0
702 11:36:21.878368 [ModeRegInit_LP4] CH0 RK1
703 11:36:21.882068 [ModeRegInit_LP4] CH1 RK0
704 11:36:21.885083 [ModeRegInit_LP4] CH1 RK1
705 11:36:21.885181 match AC timing 13
706 11:36:21.891804 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:36:21.895638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:36:21.898494 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:36:21.905564 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:36:21.908413 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:36:21.908501 [EMI DOE] emi_dcm 0
712 11:36:21.915428 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:36:21.915551 ==
714 11:36:21.918908 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:36:21.922286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:36:21.922408 ==
717 11:36:21.928789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:36:21.932048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:36:21.942531 [CA 0] Center 36 (6~67) winsize 62
720 11:36:21.946169 [CA 1] Center 36 (6~67) winsize 62
721 11:36:21.949871 [CA 2] Center 34 (4~65) winsize 62
722 11:36:21.953854 [CA 3] Center 34 (4~64) winsize 61
723 11:36:21.957028 [CA 4] Center 32 (2~63) winsize 62
724 11:36:21.960714 [CA 5] Center 32 (2~62) winsize 61
725 11:36:21.960809
726 11:36:21.964423 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:36:21.964493
728 11:36:21.967636 [CATrainingPosCal] consider 1 rank data
729 11:36:21.970997 u2DelayCellTimex100 = 270/100 ps
730 11:36:21.974300 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 11:36:21.977871 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 11:36:21.981107 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 11:36:21.984254 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 11:36:21.987474 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
735 11:36:21.990808 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 11:36:21.990883
737 11:36:21.997525 CA PerBit enable=1, Macro0, CA PI delay=32
738 11:36:21.997599
739 11:36:21.997657 [CBTSetCACLKResult] CA Dly = 32
740 11:36:22.001253 CS Dly: 5 (0~36)
741 11:36:22.001351 ==
742 11:36:22.004308 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:36:22.007497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:36:22.007592 ==
745 11:36:22.014055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:36:22.021225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:36:22.028833 [CA 0] Center 36 (6~67) winsize 62
748 11:36:22.032320 [CA 1] Center 36 (6~67) winsize 62
749 11:36:22.035475 [CA 2] Center 34 (4~65) winsize 62
750 11:36:22.038796 [CA 3] Center 34 (3~65) winsize 63
751 11:36:22.042132 [CA 4] Center 32 (2~63) winsize 62
752 11:36:22.045803 [CA 5] Center 32 (2~63) winsize 62
753 11:36:22.045875
754 11:36:22.049071 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:36:22.049142
756 11:36:22.052228 [CATrainingPosCal] consider 2 rank data
757 11:36:22.055351 u2DelayCellTimex100 = 270/100 ps
758 11:36:22.058647 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 11:36:22.062429 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 11:36:22.069160 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 11:36:22.072534 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 11:36:22.075692 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 11:36:22.078672 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 11:36:22.078749
765 11:36:22.082616 CA PerBit enable=1, Macro0, CA PI delay=32
766 11:36:22.082693
767 11:36:22.085846 [CBTSetCACLKResult] CA Dly = 32
768 11:36:22.085923 CS Dly: 5 (0~37)
769 11:36:22.086039
770 11:36:22.089072 ----->DramcWriteLeveling(PI) begin...
771 11:36:22.092236 ==
772 11:36:22.095532 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:36:22.098844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:36:22.098919 ==
775 11:36:22.102107 Write leveling (Byte 0): 32 => 32
776 11:36:22.105921 Write leveling (Byte 1): 31 => 31
777 11:36:22.109203 DramcWriteLeveling(PI) end<-----
778 11:36:22.109273
779 11:36:22.109330 ==
780 11:36:22.112461 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:36:22.115720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:36:22.115785 ==
783 11:36:22.118722 [Gating] SW mode calibration
784 11:36:22.125693 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:36:22.128907 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:36:22.135761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:36:22.139053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:36:22.142018 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 11:36:22.148940 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:36:22.152150 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:36:22.155492 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:36:22.162281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:36:22.165591 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:36:22.169389 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:36:22.175892 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:36:22.179124 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:36:22.182416 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:36:22.189192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:36:22.192651 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:36:22.195952 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:36:22.199205 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:36:22.205949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:36:22.208907 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
804 11:36:22.212401 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 11:36:22.219635 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:36:22.222909 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:36:22.225779 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:36:22.232735 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:36:22.236201 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:36:22.239562 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:36:22.245830 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:36:22.249386 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
813 11:36:22.252746 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
814 11:36:22.259164 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:36:22.262852 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:36:22.265909 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:36:22.269503 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:36:22.275816 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:36:22.279114 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
820 11:36:22.282947 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
821 11:36:22.289375 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 11:36:22.292949 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:36:22.296050 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:36:22.303028 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:36:22.306129 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:36:22.309356 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:36:22.316481 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:36:22.319843 0 11 8 | B1->B0 | 2f2f 3e3e | 0 0 | (1 1) (0 0)
829 11:36:22.323059 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 11:36:22.329595 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:36:22.332687 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:36:22.336247 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:36:22.343124 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:36:22.346301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:36:22.349594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:36:22.352919 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 11:36:22.359473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 11:36:22.363562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:36:22.366485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:36:22.373319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:36:22.376358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:36:22.379977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:36:22.386449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:36:22.390157 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:36:22.393409 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:36:22.400066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:36:22.403484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:36:22.406997 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:36:22.413139 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:36:22.416498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:36:22.420158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:36:22.423274 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:36:22.426688 Total UI for P1: 0, mck2ui 16
854 11:36:22.430619 best dqsien dly found for B0: ( 0, 14, 4)
855 11:36:22.436892 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:36:22.436961 Total UI for P1: 0, mck2ui 16
857 11:36:22.443327 best dqsien dly found for B1: ( 0, 14, 8)
858 11:36:22.447081 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:36:22.450556 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:36:22.450627
861 11:36:22.453712 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:36:22.456966 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:36:22.460331 [Gating] SW calibration Done
864 11:36:22.460404 ==
865 11:36:22.463800 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:36:22.467026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:36:22.467094 ==
868 11:36:22.470264 RX Vref Scan: 0
869 11:36:22.470327
870 11:36:22.470383 RX Vref 0 -> 0, step: 1
871 11:36:22.470435
872 11:36:22.473478 RX Delay -130 -> 252, step: 16
873 11:36:22.476821 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 11:36:22.483395 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 11:36:22.487108 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 11:36:22.490377 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 11:36:22.493562 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 11:36:22.497199 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 11:36:22.503573 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 11:36:22.506800 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 11:36:22.510317 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
882 11:36:22.513536 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 11:36:22.517361 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 11:36:22.521062 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 11:36:22.527243 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
886 11:36:22.530330 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 11:36:22.533846 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 11:36:22.537207 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 11:36:22.537278 ==
890 11:36:22.540226 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:36:22.546817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:36:22.546889 ==
893 11:36:22.546947 DQS Delay:
894 11:36:22.550173 DQS0 = 0, DQS1 = 0
895 11:36:22.550246 DQM Delay:
896 11:36:22.550302 DQM0 = 88, DQM1 = 80
897 11:36:22.553417 DQ Delay:
898 11:36:22.556975 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 11:36:22.560296 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 11:36:22.563733 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
901 11:36:22.566906 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
902 11:36:22.566973
903 11:36:22.567029
904 11:36:22.567080 ==
905 11:36:22.570244 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:36:22.573821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:36:22.573880 ==
908 11:36:22.573932
909 11:36:22.573988
910 11:36:22.576866 TX Vref Scan disable
911 11:36:22.576923 == TX Byte 0 ==
912 11:36:22.583597 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 11:36:22.586936 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 11:36:22.587002 == TX Byte 1 ==
915 11:36:22.593444 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:36:22.597280 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:36:22.597345 ==
918 11:36:22.600621 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:36:22.603815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:36:22.603888 ==
921 11:36:22.617535 TX Vref=22, minBit 9, minWin=27, winSum=449
922 11:36:22.621024 TX Vref=24, minBit 8, minWin=27, winSum=451
923 11:36:22.624115 TX Vref=26, minBit 8, minWin=27, winSum=453
924 11:36:22.627798 TX Vref=28, minBit 0, minWin=28, winSum=458
925 11:36:22.631098 TX Vref=30, minBit 5, minWin=28, winSum=459
926 11:36:22.634371 TX Vref=32, minBit 5, minWin=28, winSum=456
927 11:36:22.640870 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
928 11:36:22.640946
929 11:36:22.644356 Final TX Range 1 Vref 30
930 11:36:22.644422
931 11:36:22.644481 ==
932 11:36:22.647686 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:36:22.651295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:36:22.651401 ==
935 11:36:22.651517
936 11:36:22.653939
937 11:36:22.654060 TX Vref Scan disable
938 11:36:22.657441 == TX Byte 0 ==
939 11:36:22.661552 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 11:36:22.664955 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 11:36:22.667804 == TX Byte 1 ==
942 11:36:22.671015 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 11:36:22.674152 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 11:36:22.674242
945 11:36:22.677482 [DATLAT]
946 11:36:22.677577 Freq=800, CH0 RK0
947 11:36:22.677659
948 11:36:22.680802 DATLAT Default: 0xa
949 11:36:22.680900 0, 0xFFFF, sum = 0
950 11:36:22.684238 1, 0xFFFF, sum = 0
951 11:36:22.684314 2, 0xFFFF, sum = 0
952 11:36:22.687483 3, 0xFFFF, sum = 0
953 11:36:22.687558 4, 0xFFFF, sum = 0
954 11:36:22.690882 5, 0xFFFF, sum = 0
955 11:36:22.690958 6, 0xFFFF, sum = 0
956 11:36:22.694718 7, 0xFFFF, sum = 0
957 11:36:22.694794 8, 0xFFFF, sum = 0
958 11:36:22.697869 9, 0x0, sum = 1
959 11:36:22.697946 10, 0x0, sum = 2
960 11:36:22.701214 11, 0x0, sum = 3
961 11:36:22.701290 12, 0x0, sum = 4
962 11:36:22.704350 best_step = 10
963 11:36:22.704424
964 11:36:22.704482 ==
965 11:36:22.707639 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:36:22.711096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:36:22.711172 ==
968 11:36:22.714997 RX Vref Scan: 1
969 11:36:22.715085
970 11:36:22.715143 Set Vref Range= 32 -> 127
971 11:36:22.715198
972 11:36:22.718465 RX Vref 32 -> 127, step: 1
973 11:36:22.718552
974 11:36:22.721104 RX Delay -79 -> 252, step: 8
975 11:36:22.721179
976 11:36:22.724747 Set Vref, RX VrefLevel [Byte0]: 32
977 11:36:22.727663 [Byte1]: 32
978 11:36:22.727750
979 11:36:22.731106 Set Vref, RX VrefLevel [Byte0]: 33
980 11:36:22.734682 [Byte1]: 33
981 11:36:22.734757
982 11:36:22.737933 Set Vref, RX VrefLevel [Byte0]: 34
983 11:36:22.741411 [Byte1]: 34
984 11:36:22.745352
985 11:36:22.745440 Set Vref, RX VrefLevel [Byte0]: 35
986 11:36:22.748895 [Byte1]: 35
987 11:36:22.752548
988 11:36:22.752622 Set Vref, RX VrefLevel [Byte0]: 36
989 11:36:22.756101 [Byte1]: 36
990 11:36:22.760189
991 11:36:22.760264 Set Vref, RX VrefLevel [Byte0]: 37
992 11:36:22.763419 [Byte1]: 37
993 11:36:22.768106
994 11:36:22.768180 Set Vref, RX VrefLevel [Byte0]: 38
995 11:36:22.771109 [Byte1]: 38
996 11:36:22.775400
997 11:36:22.775474 Set Vref, RX VrefLevel [Byte0]: 39
998 11:36:22.778820 [Byte1]: 39
999 11:36:22.783406
1000 11:36:22.783493 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:36:22.786569 [Byte1]: 40
1002 11:36:22.790760
1003 11:36:22.790834 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:36:22.793873 [Byte1]: 41
1005 11:36:22.798805
1006 11:36:22.798879 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:36:22.801614 [Byte1]: 42
1008 11:36:22.805452
1009 11:36:22.805528 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:36:22.809015 [Byte1]: 43
1011 11:36:22.813368
1012 11:36:22.813457 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:36:22.816680 [Byte1]: 44
1014 11:36:22.820612
1015 11:36:22.820687 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:36:22.824376 [Byte1]: 45
1017 11:36:22.828218
1018 11:36:22.828292 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:36:22.831570 [Byte1]: 46
1020 11:36:22.835956
1021 11:36:22.836031 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:36:22.838991 [Byte1]: 47
1023 11:36:22.843173
1024 11:36:22.843248 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:36:22.847039 [Byte1]: 48
1026 11:36:22.851147
1027 11:36:22.851221 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:36:22.854077 [Byte1]: 49
1029 11:36:22.858523
1030 11:36:22.858597 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:36:22.861670 [Byte1]: 50
1032 11:36:22.866279
1033 11:36:22.866353 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:36:22.869351 [Byte1]: 51
1035 11:36:22.873920
1036 11:36:22.874018 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:36:22.876654 [Byte1]: 52
1038 11:36:22.881093
1039 11:36:22.881167 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:36:22.884407 [Byte1]: 53
1041 11:36:22.888910
1042 11:36:22.888984 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:36:22.892053 [Byte1]: 54
1044 11:36:22.895972
1045 11:36:22.896047 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:36:22.899740 [Byte1]: 55
1047 11:36:22.903650
1048 11:36:22.903725 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:36:22.907134 [Byte1]: 56
1050 11:36:22.911219
1051 11:36:22.911342 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:36:22.914917 [Byte1]: 57
1053 11:36:22.919190
1054 11:36:22.919285 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:36:22.922186 [Byte1]: 58
1056 11:36:22.926551
1057 11:36:22.926629 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:36:22.929843 [Byte1]: 59
1059 11:36:22.934203
1060 11:36:22.934277 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:36:22.937588 [Byte1]: 60
1062 11:36:22.941509
1063 11:36:22.941594 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:36:22.944789 [Byte1]: 61
1065 11:36:22.949178
1066 11:36:22.949245 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:36:22.952210 [Byte1]: 62
1068 11:36:22.956911
1069 11:36:22.956981 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:36:22.960116 [Byte1]: 63
1071 11:36:22.964184
1072 11:36:22.964252 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:36:22.968093 [Byte1]: 64
1074 11:36:22.971847
1075 11:36:22.975169 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:36:22.975250 [Byte1]: 65
1077 11:36:22.979627
1078 11:36:22.979696 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:36:22.982928 [Byte1]: 66
1080 11:36:22.986838
1081 11:36:22.986904 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:36:22.990084 [Byte1]: 67
1083 11:36:22.994080
1084 11:36:22.994153 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:36:22.997823 [Byte1]: 68
1086 11:36:23.001981
1087 11:36:23.002067 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:36:23.008460 [Byte1]: 69
1089 11:36:23.008526
1090 11:36:23.011984 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:36:23.015132 [Byte1]: 70
1092 11:36:23.015202
1093 11:36:23.018515 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:36:23.021659 [Byte1]: 71
1095 11:36:23.021732
1096 11:36:23.024976 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:36:23.028409 [Byte1]: 72
1098 11:36:23.032275
1099 11:36:23.032338 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:36:23.035245 [Byte1]: 73
1101 11:36:23.039421
1102 11:36:23.039485 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:36:23.042986 [Byte1]: 74
1104 11:36:23.047113
1105 11:36:23.047176 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:36:23.050381 [Byte1]: 75
1107 11:36:23.054459
1108 11:36:23.054534 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:36:23.058081 [Byte1]: 76
1110 11:36:23.062266
1111 11:36:23.062343 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:36:23.065697 [Byte1]: 77
1113 11:36:23.069621
1114 11:36:23.069712 Set Vref, RX VrefLevel [Byte0]: 78
1115 11:36:23.073411 [Byte1]: 78
1116 11:36:23.077578
1117 11:36:23.077643 Final RX Vref Byte 0 = 59 to rank0
1118 11:36:23.080464 Final RX Vref Byte 1 = 63 to rank0
1119 11:36:23.084084 Final RX Vref Byte 0 = 59 to rank1
1120 11:36:23.088124 Final RX Vref Byte 1 = 63 to rank1==
1121 11:36:23.090897 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 11:36:23.097657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 11:36:23.097733 ==
1124 11:36:23.097792 DQS Delay:
1125 11:36:23.097845 DQS0 = 0, DQS1 = 0
1126 11:36:23.100884 DQM Delay:
1127 11:36:23.100979 DQM0 = 92, DQM1 = 85
1128 11:36:23.104403 DQ Delay:
1129 11:36:23.104466 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 11:36:23.107495 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1131 11:36:23.110957 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1132 11:36:23.117456 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 11:36:23.117525
1134 11:36:23.117589
1135 11:36:23.123998 [DQSOSCAuto] RK0, (LSB)MR18= 0x5146, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1136 11:36:23.127424 CH0 RK0: MR19=606, MR18=5146
1137 11:36:23.134050 CH0_RK0: MR19=0x606, MR18=0x5146, DQSOSC=389, MR23=63, INC=97, DEC=65
1138 11:36:23.134134
1139 11:36:23.137384 ----->DramcWriteLeveling(PI) begin...
1140 11:36:23.137452 ==
1141 11:36:23.140708 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:36:23.143961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:36:23.144029 ==
1144 11:36:23.147177 Write leveling (Byte 0): 33 => 33
1145 11:36:23.151095 Write leveling (Byte 1): 29 => 29
1146 11:36:23.154381 DramcWriteLeveling(PI) end<-----
1147 11:36:23.154519
1148 11:36:23.154622 ==
1149 11:36:23.157571 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 11:36:23.161293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 11:36:23.161363 ==
1152 11:36:23.163874 [Gating] SW mode calibration
1153 11:36:23.170815 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 11:36:23.177900 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 11:36:23.221539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 11:36:23.221809 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 11:36:23.221913 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 11:36:23.222041 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:36:23.222100 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:36:23.222335 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:36:23.222571 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:36:23.222640 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:36:23.222708 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:36:23.223291 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:36:23.243917 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:36:23.244223 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:36:23.244318 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:36:23.244413 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:36:23.244505 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:36:23.247879 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:36:23.251107 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:36:23.254925 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:36:23.260898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1174 11:36:23.264277 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:36:23.267982 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:36:23.274779 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:36:23.277861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:36:23.281129 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:36:23.287976 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:36:23.291359 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:36:23.294639 0 9 8 | B1->B0 | 2f2f 302f | 1 1 | (1 1) (0 0)
1182 11:36:23.297979 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:36:23.304796 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:36:23.308086 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:36:23.311267 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:36:23.318099 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:36:23.321428 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:36:23.324724 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1189 11:36:23.331306 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 0)
1190 11:36:23.335225 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:36:23.338108 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:36:23.344746 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:36:23.348089 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:36:23.352037 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:36:23.358384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:36:23.361564 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1197 11:36:23.364924 0 11 8 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
1198 11:36:23.368267 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:36:23.374701 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:36:23.378825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:36:23.381931 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:36:23.388659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:36:23.391833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:36:23.395158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:36:23.402003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 11:36:23.405023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:36:23.408777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:36:23.415134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:36:23.418607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:36:23.421996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:36:23.425546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:36:23.432127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:36:23.435199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:36:23.438476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:36:23.444997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:36:23.449045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:36:23.451723 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:36:23.458950 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:36:23.461911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:36:23.465240 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:36:23.471897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 11:36:23.475085 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:36:23.478465 Total UI for P1: 0, mck2ui 16
1224 11:36:23.482328 best dqsien dly found for B0: ( 0, 14, 8)
1225 11:36:23.485175 Total UI for P1: 0, mck2ui 16
1226 11:36:23.488399 best dqsien dly found for B1: ( 0, 14, 8)
1227 11:36:23.492146 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:36:23.495454 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 11:36:23.495517
1230 11:36:23.498825 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:36:23.502214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 11:36:23.505505 [Gating] SW calibration Done
1233 11:36:23.505591 ==
1234 11:36:23.508680 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:36:23.512200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 11:36:23.512264 ==
1237 11:36:23.515949 RX Vref Scan: 0
1238 11:36:23.516044
1239 11:36:23.518860 RX Vref 0 -> 0, step: 1
1240 11:36:23.518921
1241 11:36:23.518976 RX Delay -130 -> 252, step: 16
1242 11:36:23.525967 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 11:36:23.528768 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 11:36:23.532119 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 11:36:23.535472 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 11:36:23.539194 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 11:36:23.545839 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 11:36:23.549128 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 11:36:23.552586 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 11:36:23.555853 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 11:36:23.559095 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1252 11:36:23.565775 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 11:36:23.569021 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 11:36:23.572191 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 11:36:23.576043 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 11:36:23.578778 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 11:36:23.585576 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1258 11:36:23.585663 ==
1259 11:36:23.588815 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:36:23.592615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:36:23.592678 ==
1262 11:36:23.592732 DQS Delay:
1263 11:36:23.595761 DQS0 = 0, DQS1 = 0
1264 11:36:23.595853 DQM Delay:
1265 11:36:23.599138 DQM0 = 91, DQM1 = 81
1266 11:36:23.599210 DQ Delay:
1267 11:36:23.601974 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1268 11:36:23.605319 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 11:36:23.609121 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1270 11:36:23.612469 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1271 11:36:23.612532
1272 11:36:23.612585
1273 11:36:23.612635 ==
1274 11:36:23.615721 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:36:23.619172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:36:23.619238 ==
1277 11:36:23.619291
1278 11:36:23.622282
1279 11:36:23.622344 TX Vref Scan disable
1280 11:36:23.625604 == TX Byte 0 ==
1281 11:36:23.629316 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 11:36:23.632359 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 11:36:23.635386 == TX Byte 1 ==
1284 11:36:23.639256 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 11:36:23.642243 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 11:36:23.642321 ==
1287 11:36:23.645348 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 11:36:23.652223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 11:36:23.652287 ==
1290 11:36:23.664719 TX Vref=22, minBit 8, minWin=27, winSum=446
1291 11:36:23.667672 TX Vref=24, minBit 10, minWin=27, winSum=451
1292 11:36:23.671268 TX Vref=26, minBit 4, minWin=28, winSum=456
1293 11:36:23.674293 TX Vref=28, minBit 12, minWin=27, winSum=458
1294 11:36:23.677858 TX Vref=30, minBit 2, minWin=28, winSum=456
1295 11:36:23.684691 TX Vref=32, minBit 1, minWin=28, winSum=453
1296 11:36:23.688173 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 26
1297 11:36:23.688242
1298 11:36:23.691408 Final TX Range 1 Vref 26
1299 11:36:23.691469
1300 11:36:23.691521 ==
1301 11:36:23.694684 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 11:36:23.697912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 11:36:23.698002 ==
1304 11:36:23.698081
1305 11:36:23.701095
1306 11:36:23.701161 TX Vref Scan disable
1307 11:36:23.704507 == TX Byte 0 ==
1308 11:36:23.707599 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 11:36:23.711565 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 11:36:23.714857 == TX Byte 1 ==
1311 11:36:23.717613 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1312 11:36:23.720955 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1313 11:36:23.725019
1314 11:36:23.725089 [DATLAT]
1315 11:36:23.725144 Freq=800, CH0 RK1
1316 11:36:23.725195
1317 11:36:23.728170 DATLAT Default: 0xa
1318 11:36:23.728230 0, 0xFFFF, sum = 0
1319 11:36:23.731285 1, 0xFFFF, sum = 0
1320 11:36:23.731350 2, 0xFFFF, sum = 0
1321 11:36:23.734347 3, 0xFFFF, sum = 0
1322 11:36:23.734413 4, 0xFFFF, sum = 0
1323 11:36:23.737721 5, 0xFFFF, sum = 0
1324 11:36:23.737782 6, 0xFFFF, sum = 0
1325 11:36:23.741387 7, 0xFFFF, sum = 0
1326 11:36:23.741452 8, 0xFFFF, sum = 0
1327 11:36:23.744825 9, 0x0, sum = 1
1328 11:36:23.744887 10, 0x0, sum = 2
1329 11:36:23.747952 11, 0x0, sum = 3
1330 11:36:23.748012 12, 0x0, sum = 4
1331 11:36:23.751406 best_step = 10
1332 11:36:23.751497
1333 11:36:23.751562 ==
1334 11:36:23.754523 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:36:23.758274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:36:23.758334 ==
1337 11:36:23.761000 RX Vref Scan: 0
1338 11:36:23.761057
1339 11:36:23.761107 RX Vref 0 -> 0, step: 1
1340 11:36:23.761155
1341 11:36:23.764694 RX Delay -79 -> 252, step: 8
1342 11:36:23.771116 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 11:36:23.774974 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 11:36:23.777989 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 11:36:23.781068 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1346 11:36:23.784957 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1347 11:36:23.791081 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 11:36:23.794569 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 11:36:23.798184 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 11:36:23.801457 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 11:36:23.804884 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 11:36:23.811162 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1353 11:36:23.815010 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 11:36:23.817677 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1355 11:36:23.821613 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1356 11:36:23.824808 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 11:36:23.831435 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 11:36:23.831499 ==
1359 11:36:23.834715 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:36:23.837798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:36:23.837861 ==
1362 11:36:23.837914 DQS Delay:
1363 11:36:23.841382 DQS0 = 0, DQS1 = 0
1364 11:36:23.841440 DQM Delay:
1365 11:36:23.844513 DQM0 = 93, DQM1 = 84
1366 11:36:23.844579 DQ Delay:
1367 11:36:23.847835 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1368 11:36:23.851132 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1369 11:36:23.854397 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
1370 11:36:23.858040 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1371 11:36:23.858107
1372 11:36:23.858161
1373 11:36:23.864378 [DQSOSCAuto] RK1, (LSB)MR18= 0x4818, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1374 11:36:23.868267 CH0 RK1: MR19=606, MR18=4818
1375 11:36:23.874672 CH0_RK1: MR19=0x606, MR18=0x4818, DQSOSC=391, MR23=63, INC=96, DEC=64
1376 11:36:23.877907 [RxdqsGatingPostProcess] freq 800
1377 11:36:23.884507 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 11:36:23.884577 Pre-setting of DQS Precalculation
1379 11:36:23.891434 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 11:36:23.891503 ==
1381 11:36:23.894608 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 11:36:23.897895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:36:23.897997 ==
1384 11:36:23.904720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 11:36:23.911361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 11:36:23.919454 [CA 0] Center 36 (6~67) winsize 62
1387 11:36:23.923101 [CA 1] Center 37 (6~68) winsize 63
1388 11:36:23.926484 [CA 2] Center 35 (5~66) winsize 62
1389 11:36:23.929688 [CA 3] Center 34 (4~65) winsize 62
1390 11:36:23.932982 [CA 4] Center 34 (4~65) winsize 62
1391 11:36:23.936362 [CA 5] Center 34 (4~64) winsize 61
1392 11:36:23.936424
1393 11:36:23.939632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 11:36:23.939717
1395 11:36:23.943064 [CATrainingPosCal] consider 1 rank data
1396 11:36:23.946130 u2DelayCellTimex100 = 270/100 ps
1397 11:36:23.950031 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 11:36:23.952898 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1399 11:36:23.959550 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1400 11:36:23.962696 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 11:36:23.966426 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 11:36:23.969638 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 11:36:23.969764
1404 11:36:23.972699 CA PerBit enable=1, Macro0, CA PI delay=34
1405 11:36:23.972806
1406 11:36:23.975946 [CBTSetCACLKResult] CA Dly = 34
1407 11:36:23.976039 CS Dly: 6 (0~37)
1408 11:36:23.979843 ==
1409 11:36:23.979940 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 11:36:23.986319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:36:23.986393 ==
1412 11:36:23.989581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 11:36:23.996434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 11:36:24.005688 [CA 0] Center 36 (6~67) winsize 62
1415 11:36:24.008840 [CA 1] Center 36 (6~67) winsize 62
1416 11:36:24.012650 [CA 2] Center 35 (4~66) winsize 63
1417 11:36:24.015910 [CA 3] Center 34 (4~65) winsize 62
1418 11:36:24.018995 [CA 4] Center 34 (4~65) winsize 62
1419 11:36:24.022534 [CA 5] Center 34 (4~65) winsize 62
1420 11:36:24.022602
1421 11:36:24.026017 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 11:36:24.026081
1423 11:36:24.029017 [CATrainingPosCal] consider 2 rank data
1424 11:36:24.032207 u2DelayCellTimex100 = 270/100 ps
1425 11:36:24.035230 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 11:36:24.039052 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 11:36:24.045797 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1428 11:36:24.049034 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 11:36:24.052290 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 11:36:24.055434 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 11:36:24.055505
1432 11:36:24.059017 CA PerBit enable=1, Macro0, CA PI delay=34
1433 11:36:24.059082
1434 11:36:24.062039 [CBTSetCACLKResult] CA Dly = 34
1435 11:36:24.062131 CS Dly: 6 (0~38)
1436 11:36:24.062220
1437 11:36:24.065377 ----->DramcWriteLeveling(PI) begin...
1438 11:36:24.069400 ==
1439 11:36:24.069470 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:36:24.076056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:36:24.076122 ==
1442 11:36:24.079206 Write leveling (Byte 0): 26 => 26
1443 11:36:24.083001 Write leveling (Byte 1): 26 => 26
1444 11:36:24.083066 DramcWriteLeveling(PI) end<-----
1445 11:36:24.085753
1446 11:36:24.085906 ==
1447 11:36:24.089288 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:36:24.092176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:36:24.092270 ==
1450 11:36:24.095853 [Gating] SW mode calibration
1451 11:36:24.102379 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 11:36:24.106027 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 11:36:24.112496 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 11:36:24.116154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 11:36:24.119369 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:36:24.125770 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:36:24.129454 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:36:24.132416 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:36:24.139179 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:36:24.142777 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:36:24.146349 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:36:24.149826 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:36:24.156368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:36:24.159549 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:36:24.162950 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:36:24.169200 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:36:24.172425 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:36:24.176215 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:36:24.182837 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1470 11:36:24.185916 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1471 11:36:24.189212 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:36:24.196136 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:36:24.199832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:36:24.202754 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:36:24.209664 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:36:24.212885 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:36:24.216111 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:36:24.222942 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1479 11:36:24.226679 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1480 11:36:24.230108 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:36:24.233237 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:36:24.239559 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:36:24.243543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:36:24.246651 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:36:24.253213 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1486 11:36:24.256268 0 10 4 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 1)
1487 11:36:24.260386 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1488 11:36:24.266201 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:36:24.269404 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:36:24.272924 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:36:24.279438 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:36:24.283465 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:36:24.286085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:36:24.293319 0 11 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
1495 11:36:24.296780 0 11 8 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1496 11:36:24.299318 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:36:24.306376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:36:24.309728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:36:24.313252 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:36:24.316362 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:36:24.323418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:36:24.326083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1503 11:36:24.329805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:36:24.336557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:36:24.339935 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:36:24.343059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:36:24.349754 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:36:24.353078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:36:24.356408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:36:24.363170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:36:24.366386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:36:24.369898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:36:24.376471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:36:24.379615 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:36:24.383102 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:36:24.390372 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:36:24.393481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 11:36:24.396830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1519 11:36:24.399852 Total UI for P1: 0, mck2ui 16
1520 11:36:24.403136 best dqsien dly found for B1: ( 0, 14, 0)
1521 11:36:24.406485 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 11:36:24.409757 Total UI for P1: 0, mck2ui 16
1523 11:36:24.413876 best dqsien dly found for B0: ( 0, 14, 4)
1524 11:36:24.416862 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 11:36:24.420058 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1526 11:36:24.423209
1527 11:36:24.427177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 11:36:24.430121 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1529 11:36:24.430213 [Gating] SW calibration Done
1530 11:36:24.433205 ==
1531 11:36:24.436483 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 11:36:24.440248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 11:36:24.440313 ==
1534 11:36:24.440375 RX Vref Scan: 0
1535 11:36:24.440429
1536 11:36:24.443744 RX Vref 0 -> 0, step: 1
1537 11:36:24.443807
1538 11:36:24.446777 RX Delay -130 -> 252, step: 16
1539 11:36:24.450111 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 11:36:24.453442 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 11:36:24.456727 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1542 11:36:24.463637 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 11:36:24.466732 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 11:36:24.470076 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 11:36:24.473155 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1546 11:36:24.477172 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 11:36:24.483381 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1548 11:36:24.486654 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1549 11:36:24.490046 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 11:36:24.493886 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 11:36:24.497119 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 11:36:24.503746 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 11:36:24.506942 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 11:36:24.510399 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 11:36:24.510473 ==
1556 11:36:24.514158 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:36:24.517290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:36:24.517362 ==
1559 11:36:24.520466 DQS Delay:
1560 11:36:24.520556 DQS0 = 0, DQS1 = 0
1561 11:36:24.523848 DQM Delay:
1562 11:36:24.523914 DQM0 = 94, DQM1 = 89
1563 11:36:24.523970 DQ Delay:
1564 11:36:24.527221 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1565 11:36:24.530334 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1566 11:36:24.533630 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1567 11:36:24.537924 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 11:36:24.538021
1569 11:36:24.538108
1570 11:36:24.540913 ==
1571 11:36:24.540984 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 11:36:24.547217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 11:36:24.547310 ==
1574 11:36:24.547399
1575 11:36:24.547478
1576 11:36:24.550357 TX Vref Scan disable
1577 11:36:24.550424 == TX Byte 0 ==
1578 11:36:24.553525 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 11:36:24.560575 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 11:36:24.560644 == TX Byte 1 ==
1581 11:36:24.563859 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1582 11:36:24.570804 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1583 11:36:24.570879 ==
1584 11:36:24.573907 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:36:24.577267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:36:24.577332 ==
1587 11:36:24.590423 TX Vref=22, minBit 1, minWin=26, winSum=432
1588 11:36:24.593471 TX Vref=24, minBit 1, minWin=26, winSum=441
1589 11:36:24.597130 TX Vref=26, minBit 3, minWin=26, winSum=442
1590 11:36:24.600068 TX Vref=28, minBit 1, minWin=27, winSum=447
1591 11:36:24.603519 TX Vref=30, minBit 1, minWin=27, winSum=447
1592 11:36:24.607038 TX Vref=32, minBit 1, minWin=27, winSum=446
1593 11:36:24.613261 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1594 11:36:24.613339
1595 11:36:24.616772 Final TX Range 1 Vref 28
1596 11:36:24.616843
1597 11:36:24.616906 ==
1598 11:36:24.620668 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 11:36:24.623689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 11:36:24.623759 ==
1601 11:36:24.623823
1602 11:36:24.623877
1603 11:36:24.626919 TX Vref Scan disable
1604 11:36:24.630067 == TX Byte 0 ==
1605 11:36:24.633354 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 11:36:24.636946 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 11:36:24.640204 == TX Byte 1 ==
1608 11:36:24.643377 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1609 11:36:24.646704 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1610 11:36:24.646768
1611 11:36:24.650532 [DATLAT]
1612 11:36:24.650604 Freq=800, CH1 RK0
1613 11:36:24.650689
1614 11:36:24.653599 DATLAT Default: 0xa
1615 11:36:24.653659 0, 0xFFFF, sum = 0
1616 11:36:24.657073 1, 0xFFFF, sum = 0
1617 11:36:24.657147 2, 0xFFFF, sum = 0
1618 11:36:24.659921 3, 0xFFFF, sum = 0
1619 11:36:24.660018 4, 0xFFFF, sum = 0
1620 11:36:24.663716 5, 0xFFFF, sum = 0
1621 11:36:24.663785 6, 0xFFFF, sum = 0
1622 11:36:24.666872 7, 0xFFFF, sum = 0
1623 11:36:24.666935 8, 0xFFFF, sum = 0
1624 11:36:24.669912 9, 0x0, sum = 1
1625 11:36:24.670018 10, 0x0, sum = 2
1626 11:36:24.673863 11, 0x0, sum = 3
1627 11:36:24.673958 12, 0x0, sum = 4
1628 11:36:24.677072 best_step = 10
1629 11:36:24.677134
1630 11:36:24.677193 ==
1631 11:36:24.680538 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 11:36:24.683727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 11:36:24.683789 ==
1634 11:36:24.687073 RX Vref Scan: 1
1635 11:36:24.687135
1636 11:36:24.687188 Set Vref Range= 32 -> 127
1637 11:36:24.687245
1638 11:36:24.689866 RX Vref 32 -> 127, step: 1
1639 11:36:24.689950
1640 11:36:24.693545 RX Delay -63 -> 252, step: 8
1641 11:36:24.693608
1642 11:36:24.696543 Set Vref, RX VrefLevel [Byte0]: 32
1643 11:36:24.700514 [Byte1]: 32
1644 11:36:24.700592
1645 11:36:24.703413 Set Vref, RX VrefLevel [Byte0]: 33
1646 11:36:24.707172 [Byte1]: 33
1647 11:36:24.707248
1648 11:36:24.710416 Set Vref, RX VrefLevel [Byte0]: 34
1649 11:36:24.713437 [Byte1]: 34
1650 11:36:24.717803
1651 11:36:24.717878 Set Vref, RX VrefLevel [Byte0]: 35
1652 11:36:24.720675 [Byte1]: 35
1653 11:36:24.724930
1654 11:36:24.725006 Set Vref, RX VrefLevel [Byte0]: 36
1655 11:36:24.728442 [Byte1]: 36
1656 11:36:24.732605
1657 11:36:24.732680 Set Vref, RX VrefLevel [Byte0]: 37
1658 11:36:24.735521 [Byte1]: 37
1659 11:36:24.740246
1660 11:36:24.740321 Set Vref, RX VrefLevel [Byte0]: 38
1661 11:36:24.743486 [Byte1]: 38
1662 11:36:24.747394
1663 11:36:24.747460 Set Vref, RX VrefLevel [Byte0]: 39
1664 11:36:24.750596 [Byte1]: 39
1665 11:36:24.754798
1666 11:36:24.754866 Set Vref, RX VrefLevel [Byte0]: 40
1667 11:36:24.758636 [Byte1]: 40
1668 11:36:24.762831
1669 11:36:24.762907 Set Vref, RX VrefLevel [Byte0]: 41
1670 11:36:24.765917 [Byte1]: 41
1671 11:36:24.769959
1672 11:36:24.770048 Set Vref, RX VrefLevel [Byte0]: 42
1673 11:36:24.773337 [Byte1]: 42
1674 11:36:24.777447
1675 11:36:24.777518 Set Vref, RX VrefLevel [Byte0]: 43
1676 11:36:24.780649 [Byte1]: 43
1677 11:36:24.785259
1678 11:36:24.785354 Set Vref, RX VrefLevel [Byte0]: 44
1679 11:36:24.788564 [Byte1]: 44
1680 11:36:24.792451
1681 11:36:24.792513 Set Vref, RX VrefLevel [Byte0]: 45
1682 11:36:24.795766 [Byte1]: 45
1683 11:36:24.800370
1684 11:36:24.800441 Set Vref, RX VrefLevel [Byte0]: 46
1685 11:36:24.804067 [Byte1]: 46
1686 11:36:24.807257
1687 11:36:24.807322 Set Vref, RX VrefLevel [Byte0]: 47
1688 11:36:24.811405 [Byte1]: 47
1689 11:36:24.815211
1690 11:36:24.815290 Set Vref, RX VrefLevel [Byte0]: 48
1691 11:36:24.818165 [Byte1]: 48
1692 11:36:24.822704
1693 11:36:24.822799 Set Vref, RX VrefLevel [Byte0]: 49
1694 11:36:24.825787 [Byte1]: 49
1695 11:36:24.830284
1696 11:36:24.830382 Set Vref, RX VrefLevel [Byte0]: 50
1697 11:36:24.833255 [Byte1]: 50
1698 11:36:24.837307
1699 11:36:24.837396 Set Vref, RX VrefLevel [Byte0]: 51
1700 11:36:24.840959 [Byte1]: 51
1701 11:36:24.845360
1702 11:36:24.845434 Set Vref, RX VrefLevel [Byte0]: 52
1703 11:36:24.848710 [Byte1]: 52
1704 11:36:24.852358
1705 11:36:24.852419 Set Vref, RX VrefLevel [Byte0]: 53
1706 11:36:24.855788 [Byte1]: 53
1707 11:36:24.860199
1708 11:36:24.860262 Set Vref, RX VrefLevel [Byte0]: 54
1709 11:36:24.862990 [Byte1]: 54
1710 11:36:24.867400
1711 11:36:24.867466 Set Vref, RX VrefLevel [Byte0]: 55
1712 11:36:24.870723 [Byte1]: 55
1713 11:36:24.875200
1714 11:36:24.875263 Set Vref, RX VrefLevel [Byte0]: 56
1715 11:36:24.878383 [Byte1]: 56
1716 11:36:24.882644
1717 11:36:24.882706 Set Vref, RX VrefLevel [Byte0]: 57
1718 11:36:24.885946 [Byte1]: 57
1719 11:36:24.889656
1720 11:36:24.889718 Set Vref, RX VrefLevel [Byte0]: 58
1721 11:36:24.893198 [Byte1]: 58
1722 11:36:24.897316
1723 11:36:24.897378 Set Vref, RX VrefLevel [Byte0]: 59
1724 11:36:24.900604 [Byte1]: 59
1725 11:36:24.904982
1726 11:36:24.905098 Set Vref, RX VrefLevel [Byte0]: 60
1727 11:36:24.908190 [Byte1]: 60
1728 11:36:24.912299
1729 11:36:24.912364 Set Vref, RX VrefLevel [Byte0]: 61
1730 11:36:24.915498 [Byte1]: 61
1731 11:36:24.919795
1732 11:36:24.919879 Set Vref, RX VrefLevel [Byte0]: 62
1733 11:36:24.923624 [Byte1]: 62
1734 11:36:24.927759
1735 11:36:24.927831 Set Vref, RX VrefLevel [Byte0]: 63
1736 11:36:24.931044 [Byte1]: 63
1737 11:36:24.935001
1738 11:36:24.935064 Set Vref, RX VrefLevel [Byte0]: 64
1739 11:36:24.938417 [Byte1]: 64
1740 11:36:24.942670
1741 11:36:24.942731 Set Vref, RX VrefLevel [Byte0]: 65
1742 11:36:24.945623 [Byte1]: 65
1743 11:36:24.949879
1744 11:36:24.949945 Set Vref, RX VrefLevel [Byte0]: 66
1745 11:36:24.953095 [Byte1]: 66
1746 11:36:24.957571
1747 11:36:24.957640 Set Vref, RX VrefLevel [Byte0]: 67
1748 11:36:24.960592 [Byte1]: 67
1749 11:36:24.964821
1750 11:36:24.964920 Set Vref, RX VrefLevel [Byte0]: 68
1751 11:36:24.968469 [Byte1]: 68
1752 11:36:24.972520
1753 11:36:24.972614 Set Vref, RX VrefLevel [Byte0]: 69
1754 11:36:24.975925 [Byte1]: 69
1755 11:36:24.979904
1756 11:36:24.979964 Set Vref, RX VrefLevel [Byte0]: 70
1757 11:36:24.983010 [Byte1]: 70
1758 11:36:24.987657
1759 11:36:24.987724 Set Vref, RX VrefLevel [Byte0]: 71
1760 11:36:24.991226 [Byte1]: 71
1761 11:36:24.994909
1762 11:36:24.995017 Set Vref, RX VrefLevel [Byte0]: 72
1763 11:36:24.998213 [Byte1]: 72
1764 11:36:25.002279
1765 11:36:25.002364 Set Vref, RX VrefLevel [Byte0]: 73
1766 11:36:25.005421 [Byte1]: 73
1767 11:36:25.009988
1768 11:36:25.010072 Set Vref, RX VrefLevel [Byte0]: 74
1769 11:36:25.013500 [Byte1]: 74
1770 11:36:25.017291
1771 11:36:25.017371 Final RX Vref Byte 0 = 57 to rank0
1772 11:36:25.021223 Final RX Vref Byte 1 = 54 to rank0
1773 11:36:25.024372 Final RX Vref Byte 0 = 57 to rank1
1774 11:36:25.027866 Final RX Vref Byte 1 = 54 to rank1==
1775 11:36:25.030937 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 11:36:25.034024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 11:36:25.037833 ==
1778 11:36:25.037933 DQS Delay:
1779 11:36:25.038024 DQS0 = 0, DQS1 = 0
1780 11:36:25.040622 DQM Delay:
1781 11:36:25.040715 DQM0 = 95, DQM1 = 89
1782 11:36:25.044056 DQ Delay:
1783 11:36:25.044121 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1784 11:36:25.047572 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1785 11:36:25.050627 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1786 11:36:25.054524 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1787 11:36:25.057496
1788 11:36:25.057571
1789 11:36:25.064138 [DQSOSCAuto] RK0, (LSB)MR18= 0x324e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1790 11:36:25.067558 CH1 RK0: MR19=606, MR18=324E
1791 11:36:25.073970 CH1_RK0: MR19=0x606, MR18=0x324E, DQSOSC=390, MR23=63, INC=97, DEC=64
1792 11:36:25.074061
1793 11:36:25.077085 ----->DramcWriteLeveling(PI) begin...
1794 11:36:25.077151 ==
1795 11:36:25.080789 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 11:36:25.083954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 11:36:25.084045 ==
1798 11:36:25.087699 Write leveling (Byte 0): 29 => 29
1799 11:36:25.090997 Write leveling (Byte 1): 30 => 30
1800 11:36:25.094437 DramcWriteLeveling(PI) end<-----
1801 11:36:25.094510
1802 11:36:25.094565 ==
1803 11:36:25.097605 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 11:36:25.100972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 11:36:25.101034 ==
1806 11:36:25.104125 [Gating] SW mode calibration
1807 11:36:25.111133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 11:36:25.117600 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 11:36:25.121437 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 11:36:25.124088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:36:25.131278 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:36:25.133999 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:36:25.137531 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:36:25.144502 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:36:25.147602 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:36:25.150814 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:36:25.157495 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:36:25.160816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:36:25.164707 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:36:25.168079 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:36:25.174102 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:36:25.177527 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:36:25.181018 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:36:25.187832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:36:25.191220 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:36:25.194523 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1827 11:36:25.201317 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:36:25.204618 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:36:25.207993 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:36:25.214581 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:36:25.217861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:36:25.220941 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:36:25.227977 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:36:25.231349 0 9 4 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1835 11:36:25.234508 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1836 11:36:25.237637 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:36:25.244810 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:36:25.248160 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:36:25.251835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:36:25.257931 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:36:25.261296 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1842 11:36:25.264641 0 10 4 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
1843 11:36:25.271400 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1844 11:36:25.275052 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:36:25.278183 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:36:25.285128 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:36:25.287875 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:36:25.291329 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:36:25.298387 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1850 11:36:25.301458 0 11 4 | B1->B0 | 3636 3030 | 0 0 | (0 0) (0 0)
1851 11:36:25.304770 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1852 11:36:25.311526 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:36:25.314961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:36:25.318422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:36:25.321623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:36:25.328023 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:36:25.331194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:36:25.334825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1859 11:36:25.341252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:36:25.344684 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:36:25.347945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:36:25.354684 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:36:25.358267 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:36:25.361414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:36:25.367930 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:36:25.371744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:36:25.375152 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:36:25.381391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:36:25.385038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:36:25.387931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:36:25.395153 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:36:25.398263 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:36:25.401586 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:36:25.408493 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1875 11:36:25.411257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1876 11:36:25.414880 Total UI for P1: 0, mck2ui 16
1877 11:36:25.418332 best dqsien dly found for B1: ( 0, 14, 4)
1878 11:36:25.421571 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 11:36:25.424911 Total UI for P1: 0, mck2ui 16
1880 11:36:25.428679 best dqsien dly found for B0: ( 0, 14, 6)
1881 11:36:25.431334 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1882 11:36:25.434663 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 11:36:25.434727
1884 11:36:25.438469 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1885 11:36:25.441852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 11:36:25.444843 [Gating] SW calibration Done
1887 11:36:25.444914 ==
1888 11:36:25.448198 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 11:36:25.454909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 11:36:25.454978 ==
1891 11:36:25.455032 RX Vref Scan: 0
1892 11:36:25.455083
1893 11:36:25.458097 RX Vref 0 -> 0, step: 1
1894 11:36:25.458168
1895 11:36:25.461540 RX Delay -130 -> 252, step: 16
1896 11:36:25.464538 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1897 11:36:25.467988 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1898 11:36:25.471188 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1899 11:36:25.474974 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1900 11:36:25.481189 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1901 11:36:25.484911 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1902 11:36:25.488094 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1903 11:36:25.491695 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1904 11:36:25.494980 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1905 11:36:25.501547 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1906 11:36:25.504630 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1907 11:36:25.507928 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1908 11:36:25.511443 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1909 11:36:25.514783 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1910 11:36:25.521586 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1911 11:36:25.524739 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1912 11:36:25.524816 ==
1913 11:36:25.528412 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 11:36:25.531644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 11:36:25.531713 ==
1916 11:36:25.534865 DQS Delay:
1917 11:36:25.534925 DQS0 = 0, DQS1 = 0
1918 11:36:25.534977 DQM Delay:
1919 11:36:25.538170 DQM0 = 91, DQM1 = 88
1920 11:36:25.538228 DQ Delay:
1921 11:36:25.541276 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1922 11:36:25.545283 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1923 11:36:25.548454 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1924 11:36:25.551473 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1925 11:36:25.551534
1926 11:36:25.551586
1927 11:36:25.551643 ==
1928 11:36:25.555419 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 11:36:25.558111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 11:36:25.561860 ==
1931 11:36:25.561925
1932 11:36:25.561979
1933 11:36:25.562081 TX Vref Scan disable
1934 11:36:25.565227 == TX Byte 0 ==
1935 11:36:25.568541 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1936 11:36:25.571719 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1937 11:36:25.574937 == TX Byte 1 ==
1938 11:36:25.578182 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1939 11:36:25.581714 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1940 11:36:25.584856 ==
1941 11:36:25.588020 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 11:36:25.591553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 11:36:25.591643 ==
1944 11:36:25.604046 TX Vref=22, minBit 0, minWin=27, winSum=441
1945 11:36:25.607404 TX Vref=24, minBit 2, minWin=27, winSum=449
1946 11:36:25.610572 TX Vref=26, minBit 2, minWin=27, winSum=451
1947 11:36:25.613860 TX Vref=28, minBit 2, minWin=27, winSum=449
1948 11:36:25.617478 TX Vref=30, minBit 2, minWin=27, winSum=454
1949 11:36:25.620586 TX Vref=32, minBit 2, minWin=27, winSum=451
1950 11:36:25.627637 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
1951 11:36:25.627711
1952 11:36:25.630688 Final TX Range 1 Vref 30
1953 11:36:25.630754
1954 11:36:25.630810 ==
1955 11:36:25.634108 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 11:36:25.637400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 11:36:25.637464 ==
1958 11:36:25.637519
1959 11:36:25.637570
1960 11:36:25.640761 TX Vref Scan disable
1961 11:36:25.644405 == TX Byte 0 ==
1962 11:36:25.647630 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1963 11:36:25.650999 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1964 11:36:25.654196 == TX Byte 1 ==
1965 11:36:25.657259 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1966 11:36:25.660592 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1967 11:36:25.660656
1968 11:36:25.664482 [DATLAT]
1969 11:36:25.664545 Freq=800, CH1 RK1
1970 11:36:25.664599
1971 11:36:25.667587 DATLAT Default: 0xa
1972 11:36:25.667657 0, 0xFFFF, sum = 0
1973 11:36:25.670805 1, 0xFFFF, sum = 0
1974 11:36:25.670873 2, 0xFFFF, sum = 0
1975 11:36:25.674208 3, 0xFFFF, sum = 0
1976 11:36:25.674267 4, 0xFFFF, sum = 0
1977 11:36:25.677417 5, 0xFFFF, sum = 0
1978 11:36:25.677482 6, 0xFFFF, sum = 0
1979 11:36:25.680764 7, 0xFFFF, sum = 0
1980 11:36:25.680822 8, 0xFFFF, sum = 0
1981 11:36:25.684771 9, 0x0, sum = 1
1982 11:36:25.684831 10, 0x0, sum = 2
1983 11:36:25.688046 11, 0x0, sum = 3
1984 11:36:25.688104 12, 0x0, sum = 4
1985 11:36:25.690717 best_step = 10
1986 11:36:25.690773
1987 11:36:25.690828 ==
1988 11:36:25.694440 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 11:36:25.697663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 11:36:25.697721 ==
1991 11:36:25.700735 RX Vref Scan: 0
1992 11:36:25.700792
1993 11:36:25.700848 RX Vref 0 -> 0, step: 1
1994 11:36:25.700898
1995 11:36:25.704152 RX Delay -79 -> 252, step: 8
1996 11:36:25.710626 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1997 11:36:25.714416 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1998 11:36:25.717758 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1999 11:36:25.721000 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2000 11:36:25.724254 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2001 11:36:25.727441 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2002 11:36:25.734342 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2003 11:36:25.737733 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2004 11:36:25.741083 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2005 11:36:25.744293 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2006 11:36:25.748344 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2007 11:36:25.751116 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2008 11:36:25.757508 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2009 11:36:25.760915 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2010 11:36:25.764481 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2011 11:36:25.768008 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2012 11:36:25.768105 ==
2013 11:36:25.770959 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:36:25.778068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:36:25.778143 ==
2016 11:36:25.778200 DQS Delay:
2017 11:36:25.778252 DQS0 = 0, DQS1 = 0
2018 11:36:25.780736 DQM Delay:
2019 11:36:25.780794 DQM0 = 97, DQM1 = 90
2020 11:36:25.784893 DQ Delay:
2021 11:36:25.788099 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2022 11:36:25.791470 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2023 11:36:25.794611 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2024 11:36:25.798068 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2025 11:36:25.798128
2026 11:36:25.798180
2027 11:36:25.804311 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2028 11:36:25.807752 CH1 RK1: MR19=606, MR18=4D16
2029 11:36:25.814399 CH1_RK1: MR19=0x606, MR18=0x4D16, DQSOSC=390, MR23=63, INC=97, DEC=64
2030 11:36:25.818149 [RxdqsGatingPostProcess] freq 800
2031 11:36:25.821496 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 11:36:25.824901 Pre-setting of DQS Precalculation
2033 11:36:25.831470 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 11:36:25.838089 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 11:36:25.844561 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 11:36:25.844634
2037 11:36:25.844689
2038 11:36:25.847742 [Calibration Summary] 1600 Mbps
2039 11:36:25.847806 CH 0, Rank 0
2040 11:36:25.851547 SW Impedance : PASS
2041 11:36:25.854481 DUTY Scan : NO K
2042 11:36:25.854542 ZQ Calibration : PASS
2043 11:36:25.858152 Jitter Meter : NO K
2044 11:36:25.858217 CBT Training : PASS
2045 11:36:25.861439 Write leveling : PASS
2046 11:36:25.864854 RX DQS gating : PASS
2047 11:36:25.864919 RX DQ/DQS(RDDQC) : PASS
2048 11:36:25.867743 TX DQ/DQS : PASS
2049 11:36:25.871863 RX DATLAT : PASS
2050 11:36:25.871929 RX DQ/DQS(Engine): PASS
2051 11:36:25.874514 TX OE : NO K
2052 11:36:25.874573 All Pass.
2053 11:36:25.874625
2054 11:36:25.878298 CH 0, Rank 1
2055 11:36:25.878361 SW Impedance : PASS
2056 11:36:25.881769 DUTY Scan : NO K
2057 11:36:25.885263 ZQ Calibration : PASS
2058 11:36:25.885331 Jitter Meter : NO K
2059 11:36:25.888177 CBT Training : PASS
2060 11:36:25.891273 Write leveling : PASS
2061 11:36:25.891333 RX DQS gating : PASS
2062 11:36:25.894610 RX DQ/DQS(RDDQC) : PASS
2063 11:36:25.894673 TX DQ/DQS : PASS
2064 11:36:25.898207 RX DATLAT : PASS
2065 11:36:25.901644 RX DQ/DQS(Engine): PASS
2066 11:36:25.901706 TX OE : NO K
2067 11:36:25.904909 All Pass.
2068 11:36:25.904969
2069 11:36:25.905023 CH 1, Rank 0
2070 11:36:25.908179 SW Impedance : PASS
2071 11:36:25.908240 DUTY Scan : NO K
2072 11:36:25.911690 ZQ Calibration : PASS
2073 11:36:25.915147 Jitter Meter : NO K
2074 11:36:25.915206 CBT Training : PASS
2075 11:36:25.918546 Write leveling : PASS
2076 11:36:25.921252 RX DQS gating : PASS
2077 11:36:25.921311 RX DQ/DQS(RDDQC) : PASS
2078 11:36:25.925204 TX DQ/DQS : PASS
2079 11:36:25.928419 RX DATLAT : PASS
2080 11:36:25.928480 RX DQ/DQS(Engine): PASS
2081 11:36:25.931342 TX OE : NO K
2082 11:36:25.931403 All Pass.
2083 11:36:25.931453
2084 11:36:25.935254 CH 1, Rank 1
2085 11:36:25.935313 SW Impedance : PASS
2086 11:36:25.937889 DUTY Scan : NO K
2087 11:36:25.941757 ZQ Calibration : PASS
2088 11:36:25.941821 Jitter Meter : NO K
2089 11:36:25.945248 CBT Training : PASS
2090 11:36:25.945309 Write leveling : PASS
2091 11:36:25.948342 RX DQS gating : PASS
2092 11:36:25.951626 RX DQ/DQS(RDDQC) : PASS
2093 11:36:25.951683 TX DQ/DQS : PASS
2094 11:36:25.954589 RX DATLAT : PASS
2095 11:36:25.957735 RX DQ/DQS(Engine): PASS
2096 11:36:25.957797 TX OE : NO K
2097 11:36:25.961155 All Pass.
2098 11:36:25.961217
2099 11:36:25.961269 DramC Write-DBI off
2100 11:36:25.964576 PER_BANK_REFRESH: Hybrid Mode
2101 11:36:25.968197 TX_TRACKING: ON
2102 11:36:25.971091 [GetDramInforAfterCalByMRR] Vendor 6.
2103 11:36:25.974775 [GetDramInforAfterCalByMRR] Revision 606.
2104 11:36:25.977953 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 11:36:25.978074 MR0 0x3b3b
2106 11:36:25.978130 MR8 0x5151
2107 11:36:25.981274 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 11:36:25.985507
2109 11:36:25.985571 MR0 0x3b3b
2110 11:36:25.985627 MR8 0x5151
2111 11:36:25.987936 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 11:36:25.987997
2113 11:36:25.997856 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 11:36:26.001347 [FAST_K] Save calibration result to emmc
2115 11:36:26.004821 [FAST_K] Save calibration result to emmc
2116 11:36:26.008320 dram_init: config_dvfs: 1
2117 11:36:26.011240 dramc_set_vcore_voltage set vcore to 662500
2118 11:36:26.015038 Read voltage for 1200, 2
2119 11:36:26.015105 Vio18 = 0
2120 11:36:26.015160 Vcore = 662500
2121 11:36:26.018533 Vdram = 0
2122 11:36:26.018622 Vddq = 0
2123 11:36:26.018706 Vmddr = 0
2124 11:36:26.025252 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 11:36:26.028582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 11:36:26.031786 MEM_TYPE=3, freq_sel=15
2127 11:36:26.035380 sv_algorithm_assistance_LP4_1600
2128 11:36:26.038375 ============ PULL DRAM RESETB DOWN ============
2129 11:36:26.041729 ========== PULL DRAM RESETB DOWN end =========
2130 11:36:26.048354 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 11:36:26.051712 ===================================
2132 11:36:26.051783 LPDDR4 DRAM CONFIGURATION
2133 11:36:26.054918 ===================================
2134 11:36:26.058159 EX_ROW_EN[0] = 0x0
2135 11:36:26.062017 EX_ROW_EN[1] = 0x0
2136 11:36:26.062138 LP4Y_EN = 0x0
2137 11:36:26.065471 WORK_FSP = 0x0
2138 11:36:26.065562 WL = 0x4
2139 11:36:26.068551 RL = 0x4
2140 11:36:26.068615 BL = 0x2
2141 11:36:26.071465 RPST = 0x0
2142 11:36:26.071552 RD_PRE = 0x0
2143 11:36:26.075342 WR_PRE = 0x1
2144 11:36:26.075406 WR_PST = 0x0
2145 11:36:26.078409 DBI_WR = 0x0
2146 11:36:26.078475 DBI_RD = 0x0
2147 11:36:26.081929 OTF = 0x1
2148 11:36:26.085547 ===================================
2149 11:36:26.088893 ===================================
2150 11:36:26.088985 ANA top config
2151 11:36:26.091977 ===================================
2152 11:36:26.095159 DLL_ASYNC_EN = 0
2153 11:36:26.098349 ALL_SLAVE_EN = 0
2154 11:36:26.098418 NEW_RANK_MODE = 1
2155 11:36:26.101918 DLL_IDLE_MODE = 1
2156 11:36:26.105289 LP45_APHY_COMB_EN = 1
2157 11:36:26.108626 TX_ODT_DIS = 1
2158 11:36:26.108722 NEW_8X_MODE = 1
2159 11:36:26.111685 ===================================
2160 11:36:26.115591 ===================================
2161 11:36:26.118904 data_rate = 2400
2162 11:36:26.122118 CKR = 1
2163 11:36:26.125700 DQ_P2S_RATIO = 8
2164 11:36:26.128532 ===================================
2165 11:36:26.132126 CA_P2S_RATIO = 8
2166 11:36:26.135339 DQ_CA_OPEN = 0
2167 11:36:26.135408 DQ_SEMI_OPEN = 0
2168 11:36:26.138456 CA_SEMI_OPEN = 0
2169 11:36:26.141937 CA_FULL_RATE = 0
2170 11:36:26.145205 DQ_CKDIV4_EN = 0
2171 11:36:26.148520 CA_CKDIV4_EN = 0
2172 11:36:26.148591 CA_PREDIV_EN = 0
2173 11:36:26.152433 PH8_DLY = 17
2174 11:36:26.155456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 11:36:26.159061 DQ_AAMCK_DIV = 4
2176 11:36:26.162281 CA_AAMCK_DIV = 4
2177 11:36:26.165532 CA_ADMCK_DIV = 4
2178 11:36:26.165593 DQ_TRACK_CA_EN = 0
2179 11:36:26.168821 CA_PICK = 1200
2180 11:36:26.172288 CA_MCKIO = 1200
2181 11:36:26.175562 MCKIO_SEMI = 0
2182 11:36:26.179062 PLL_FREQ = 2366
2183 11:36:26.182492 DQ_UI_PI_RATIO = 32
2184 11:36:26.185568 CA_UI_PI_RATIO = 0
2185 11:36:26.188599 ===================================
2186 11:36:26.192362 ===================================
2187 11:36:26.192433 memory_type:LPDDR4
2188 11:36:26.195260 GP_NUM : 10
2189 11:36:26.199259 SRAM_EN : 1
2190 11:36:26.199329 MD32_EN : 0
2191 11:36:26.201993 ===================================
2192 11:36:26.205179 [ANA_INIT] >>>>>>>>>>>>>>
2193 11:36:26.208673 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 11:36:26.212207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 11:36:26.215158 ===================================
2196 11:36:26.218648 data_rate = 2400,PCW = 0X5b00
2197 11:36:26.222300 ===================================
2198 11:36:26.225649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 11:36:26.228969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 11:36:26.235416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 11:36:26.238880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 11:36:26.242085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 11:36:26.245242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 11:36:26.248736 [ANA_INIT] flow start
2205 11:36:26.251980 [ANA_INIT] PLL >>>>>>>>
2206 11:36:26.252049 [ANA_INIT] PLL <<<<<<<<
2207 11:36:26.255852 [ANA_INIT] MIDPI >>>>>>>>
2208 11:36:26.258917 [ANA_INIT] MIDPI <<<<<<<<
2209 11:36:26.259006 [ANA_INIT] DLL >>>>>>>>
2210 11:36:26.262165 [ANA_INIT] DLL <<<<<<<<
2211 11:36:26.265491 [ANA_INIT] flow end
2212 11:36:26.268627 ============ LP4 DIFF to SE enter ============
2213 11:36:26.271921 ============ LP4 DIFF to SE exit ============
2214 11:36:26.275813 [ANA_INIT] <<<<<<<<<<<<<
2215 11:36:26.279256 [Flow] Enable top DCM control >>>>>
2216 11:36:26.281908 [Flow] Enable top DCM control <<<<<
2217 11:36:26.285500 Enable DLL master slave shuffle
2218 11:36:26.288635 ==============================================================
2219 11:36:26.291951 Gating Mode config
2220 11:36:26.298860 ==============================================================
2221 11:36:26.298938 Config description:
2222 11:36:26.308708 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 11:36:26.315581 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 11:36:26.318851 SELPH_MODE 0: By rank 1: By Phase
2225 11:36:26.325998 ==============================================================
2226 11:36:26.329004 GAT_TRACK_EN = 1
2227 11:36:26.332306 RX_GATING_MODE = 2
2228 11:36:26.335576 RX_GATING_TRACK_MODE = 2
2229 11:36:26.338730 SELPH_MODE = 1
2230 11:36:26.342984 PICG_EARLY_EN = 1
2231 11:36:26.343050 VALID_LAT_VALUE = 1
2232 11:36:26.348830 ==============================================================
2233 11:36:26.352709 Enter into Gating configuration >>>>
2234 11:36:26.356223 Exit from Gating configuration <<<<
2235 11:36:26.359133 Enter into DVFS_PRE_config >>>>>
2236 11:36:26.368981 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 11:36:26.372256 Exit from DVFS_PRE_config <<<<<
2238 11:36:26.375755 Enter into PICG configuration >>>>
2239 11:36:26.378856 Exit from PICG configuration <<<<
2240 11:36:26.382901 [RX_INPUT] configuration >>>>>
2241 11:36:26.385645 [RX_INPUT] configuration <<<<<
2242 11:36:26.389116 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 11:36:26.395635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 11:36:26.402411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 11:36:26.409255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 11:36:26.416149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 11:36:26.419019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 11:36:26.426036 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 11:36:26.429340 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 11:36:26.432882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 11:36:26.436278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 11:36:26.439464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 11:36:26.445900 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 11:36:26.449295 ===================================
2255 11:36:26.452543 LPDDR4 DRAM CONFIGURATION
2256 11:36:26.455857 ===================================
2257 11:36:26.455917 EX_ROW_EN[0] = 0x0
2258 11:36:26.459167 EX_ROW_EN[1] = 0x0
2259 11:36:26.459230 LP4Y_EN = 0x0
2260 11:36:26.463129 WORK_FSP = 0x0
2261 11:36:26.463191 WL = 0x4
2262 11:36:26.466144 RL = 0x4
2263 11:36:26.466202 BL = 0x2
2264 11:36:26.469349 RPST = 0x0
2265 11:36:26.469406 RD_PRE = 0x0
2266 11:36:26.472824 WR_PRE = 0x1
2267 11:36:26.472889 WR_PST = 0x0
2268 11:36:26.475872 DBI_WR = 0x0
2269 11:36:26.475937 DBI_RD = 0x0
2270 11:36:26.479282 OTF = 0x1
2271 11:36:26.482580 ===================================
2272 11:36:26.486145 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 11:36:26.489301 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 11:36:26.495816 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 11:36:26.499627 ===================================
2276 11:36:26.499691 LPDDR4 DRAM CONFIGURATION
2277 11:36:26.503012 ===================================
2278 11:36:26.505973 EX_ROW_EN[0] = 0x10
2279 11:36:26.509549 EX_ROW_EN[1] = 0x0
2280 11:36:26.509615 LP4Y_EN = 0x0
2281 11:36:26.512829 WORK_FSP = 0x0
2282 11:36:26.512901 WL = 0x4
2283 11:36:26.515844 RL = 0x4
2284 11:36:26.515908 BL = 0x2
2285 11:36:26.519093 RPST = 0x0
2286 11:36:26.519160 RD_PRE = 0x0
2287 11:36:26.522504 WR_PRE = 0x1
2288 11:36:26.522571 WR_PST = 0x0
2289 11:36:26.526152 DBI_WR = 0x0
2290 11:36:26.526254 DBI_RD = 0x0
2291 11:36:26.529192 OTF = 0x1
2292 11:36:26.532367 ===================================
2293 11:36:26.539232 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 11:36:26.539302 ==
2295 11:36:26.542820 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 11:36:26.546169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 11:36:26.546233 ==
2298 11:36:26.549230 [Duty_Offset_Calibration]
2299 11:36:26.549296 B0:2 B1:1 CA:1
2300 11:36:26.549351
2301 11:36:26.552462 [DutyScan_Calibration_Flow] k_type=0
2302 11:36:26.562435
2303 11:36:26.562499 ==CLK 0==
2304 11:36:26.566486 Final CLK duty delay cell = 0
2305 11:36:26.569142 [0] MAX Duty = 5218%(X100), DQS PI = 24
2306 11:36:26.572515 [0] MIN Duty = 4844%(X100), DQS PI = 48
2307 11:36:26.572580 [0] AVG Duty = 5031%(X100)
2308 11:36:26.576467
2309 11:36:26.576530 CH0 CLK Duty spec in!! Max-Min= 374%
2310 11:36:26.582925 [DutyScan_Calibration_Flow] ====Done====
2311 11:36:26.582989
2312 11:36:26.585690 [DutyScan_Calibration_Flow] k_type=1
2313 11:36:26.601034
2314 11:36:26.601107 ==DQS 0 ==
2315 11:36:26.604657 Final DQS duty delay cell = -4
2316 11:36:26.608122 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2317 11:36:26.611258 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2318 11:36:26.614955 [-4] AVG Duty = 4953%(X100)
2319 11:36:26.615028
2320 11:36:26.615142 ==DQS 1 ==
2321 11:36:26.618182 Final DQS duty delay cell = 0
2322 11:36:26.621372 [0] MAX Duty = 5156%(X100), DQS PI = 62
2323 11:36:26.624854 [0] MIN Duty = 5000%(X100), DQS PI = 32
2324 11:36:26.627932 [0] AVG Duty = 5078%(X100)
2325 11:36:26.627999
2326 11:36:26.631726 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2327 11:36:26.631799
2328 11:36:26.634537 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2329 11:36:26.637820 [DutyScan_Calibration_Flow] ====Done====
2330 11:36:26.637889
2331 11:36:26.641482 [DutyScan_Calibration_Flow] k_type=3
2332 11:36:26.657889
2333 11:36:26.657961 ==DQM 0 ==
2334 11:36:26.661685 Final DQM duty delay cell = 0
2335 11:36:26.664840 [0] MAX Duty = 5156%(X100), DQS PI = 30
2336 11:36:26.668232 [0] MIN Duty = 4875%(X100), DQS PI = 52
2337 11:36:26.672060 [0] AVG Duty = 5015%(X100)
2338 11:36:26.672119
2339 11:36:26.672175 ==DQM 1 ==
2340 11:36:26.674432 Final DQM duty delay cell = 0
2341 11:36:26.677730 [0] MAX Duty = 5093%(X100), DQS PI = 0
2342 11:36:26.681243 [0] MIN Duty = 5031%(X100), DQS PI = 14
2343 11:36:26.681301 [0] AVG Duty = 5062%(X100)
2344 11:36:26.684545
2345 11:36:26.687904 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2346 11:36:26.687962
2347 11:36:26.691195 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2348 11:36:26.695068 [DutyScan_Calibration_Flow] ====Done====
2349 11:36:26.695124
2350 11:36:26.698452 [DutyScan_Calibration_Flow] k_type=2
2351 11:36:26.714466
2352 11:36:26.714533 ==DQ 0 ==
2353 11:36:26.718172 Final DQ duty delay cell = 0
2354 11:36:26.721298 [0] MAX Duty = 5031%(X100), DQS PI = 26
2355 11:36:26.724514 [0] MIN Duty = 4844%(X100), DQS PI = 62
2356 11:36:26.724577 [0] AVG Duty = 4937%(X100)
2357 11:36:26.728315
2358 11:36:26.728375 ==DQ 1 ==
2359 11:36:26.731198 Final DQ duty delay cell = 0
2360 11:36:26.734603 [0] MAX Duty = 5093%(X100), DQS PI = 26
2361 11:36:26.737986 [0] MIN Duty = 4907%(X100), DQS PI = 36
2362 11:36:26.738089 [0] AVG Duty = 5000%(X100)
2363 11:36:26.738142
2364 11:36:26.741078 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2365 11:36:26.744486
2366 11:36:26.748088 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2367 11:36:26.751208 [DutyScan_Calibration_Flow] ====Done====
2368 11:36:26.751286 ==
2369 11:36:26.755212 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 11:36:26.758403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 11:36:26.758464 ==
2372 11:36:26.761661 [Duty_Offset_Calibration]
2373 11:36:26.761724 B0:1 B1:0 CA:0
2374 11:36:26.761775
2375 11:36:26.764502 [DutyScan_Calibration_Flow] k_type=0
2376 11:36:26.773875
2377 11:36:26.773939 ==CLK 0==
2378 11:36:26.776902 Final CLK duty delay cell = -4
2379 11:36:26.780214 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2380 11:36:26.784283 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2381 11:36:26.786906 [-4] AVG Duty = 4953%(X100)
2382 11:36:26.786973
2383 11:36:26.790791 CH1 CLK Duty spec in!! Max-Min= 156%
2384 11:36:26.793508 [DutyScan_Calibration_Flow] ====Done====
2385 11:36:26.793575
2386 11:36:26.797561 [DutyScan_Calibration_Flow] k_type=1
2387 11:36:26.813668
2388 11:36:26.813735 ==DQS 0 ==
2389 11:36:26.816772 Final DQS duty delay cell = 0
2390 11:36:26.819968 [0] MAX Duty = 5062%(X100), DQS PI = 22
2391 11:36:26.823356 [0] MIN Duty = 4844%(X100), DQS PI = 0
2392 11:36:26.823425 [0] AVG Duty = 4953%(X100)
2393 11:36:26.827021
2394 11:36:26.827081 ==DQS 1 ==
2395 11:36:26.830152 Final DQS duty delay cell = 0
2396 11:36:26.833446 [0] MAX Duty = 5187%(X100), DQS PI = 18
2397 11:36:26.836779 [0] MIN Duty = 4969%(X100), DQS PI = 10
2398 11:36:26.836838 [0] AVG Duty = 5078%(X100)
2399 11:36:26.840097
2400 11:36:26.843231 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2401 11:36:26.843295
2402 11:36:26.846516 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2403 11:36:26.849847 [DutyScan_Calibration_Flow] ====Done====
2404 11:36:26.849915
2405 11:36:26.853688 [DutyScan_Calibration_Flow] k_type=3
2406 11:36:26.869983
2407 11:36:26.870100 ==DQM 0 ==
2408 11:36:26.873139 Final DQM duty delay cell = 0
2409 11:36:26.876469 [0] MAX Duty = 5156%(X100), DQS PI = 10
2410 11:36:26.880325 [0] MIN Duty = 5000%(X100), DQS PI = 0
2411 11:36:26.880396 [0] AVG Duty = 5078%(X100)
2412 11:36:26.883386
2413 11:36:26.883451 ==DQM 1 ==
2414 11:36:26.886799 Final DQM duty delay cell = 0
2415 11:36:26.889921 [0] MAX Duty = 5031%(X100), DQS PI = 24
2416 11:36:26.893161 [0] MIN Duty = 4907%(X100), DQS PI = 36
2417 11:36:26.896721 [0] AVG Duty = 4969%(X100)
2418 11:36:26.896794
2419 11:36:26.900065 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2420 11:36:26.900136
2421 11:36:26.903485 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 11:36:26.906771 [DutyScan_Calibration_Flow] ====Done====
2423 11:36:26.906837
2424 11:36:26.910060 [DutyScan_Calibration_Flow] k_type=2
2425 11:36:26.925761
2426 11:36:26.925839 ==DQ 0 ==
2427 11:36:26.929494 Final DQ duty delay cell = -4
2428 11:36:26.932593 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2429 11:36:26.936487 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2430 11:36:26.936553 [-4] AVG Duty = 4984%(X100)
2431 11:36:26.939843
2432 11:36:26.939907 ==DQ 1 ==
2433 11:36:26.942391 Final DQ duty delay cell = 0
2434 11:36:26.945727 [0] MAX Duty = 5125%(X100), DQS PI = 20
2435 11:36:26.949184 [0] MIN Duty = 4938%(X100), DQS PI = 34
2436 11:36:26.949256 [0] AVG Duty = 5031%(X100)
2437 11:36:26.949312
2438 11:36:26.956008 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2439 11:36:26.956080
2440 11:36:26.959791 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2441 11:36:26.963011 [DutyScan_Calibration_Flow] ====Done====
2442 11:36:26.966225 nWR fixed to 30
2443 11:36:26.966293 [ModeRegInit_LP4] CH0 RK0
2444 11:36:26.969452 [ModeRegInit_LP4] CH0 RK1
2445 11:36:26.972887 [ModeRegInit_LP4] CH1 RK0
2446 11:36:26.972951 [ModeRegInit_LP4] CH1 RK1
2447 11:36:26.976390 match AC timing 7
2448 11:36:26.979563 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 11:36:26.982743 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 11:36:26.989271 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 11:36:26.992630 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 11:36:26.999716 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 11:36:26.999782 ==
2454 11:36:27.002789 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 11:36:27.006181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 11:36:27.006242 ==
2457 11:36:27.012531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 11:36:27.016443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2459 11:36:27.025939 [CA 0] Center 39 (8~70) winsize 63
2460 11:36:27.029701 [CA 1] Center 39 (8~70) winsize 63
2461 11:36:27.033035 [CA 2] Center 35 (5~66) winsize 62
2462 11:36:27.036088 [CA 3] Center 34 (4~65) winsize 62
2463 11:36:27.039438 [CA 4] Center 33 (3~64) winsize 62
2464 11:36:27.042721 [CA 5] Center 32 (3~62) winsize 60
2465 11:36:27.042787
2466 11:36:27.046664 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2467 11:36:27.046728
2468 11:36:27.049269 [CATrainingPosCal] consider 1 rank data
2469 11:36:27.052584 u2DelayCellTimex100 = 270/100 ps
2470 11:36:27.056597 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 11:36:27.059865 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2472 11:36:27.065937 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2473 11:36:27.069661 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2474 11:36:27.072848 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2475 11:36:27.076223 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2476 11:36:27.076291
2477 11:36:27.079367 CA PerBit enable=1, Macro0, CA PI delay=32
2478 11:36:27.079449
2479 11:36:27.083059 [CBTSetCACLKResult] CA Dly = 32
2480 11:36:27.083128 CS Dly: 6 (0~37)
2481 11:36:27.083184 ==
2482 11:36:27.086561 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 11:36:27.092945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 11:36:27.093033 ==
2485 11:36:27.096244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 11:36:27.102756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 11:36:27.111908 [CA 0] Center 38 (8~69) winsize 62
2488 11:36:27.115254 [CA 1] Center 38 (8~69) winsize 62
2489 11:36:27.118474 [CA 2] Center 35 (5~66) winsize 62
2490 11:36:27.121930 [CA 3] Center 34 (4~65) winsize 62
2491 11:36:27.125262 [CA 4] Center 33 (3~64) winsize 62
2492 11:36:27.129291 [CA 5] Center 32 (3~62) winsize 60
2493 11:36:27.129358
2494 11:36:27.132115 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 11:36:27.132179
2496 11:36:27.135234 [CATrainingPosCal] consider 2 rank data
2497 11:36:27.138865 u2DelayCellTimex100 = 270/100 ps
2498 11:36:27.142186 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 11:36:27.145136 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2500 11:36:27.152243 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2501 11:36:27.155089 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 11:36:27.158446 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2503 11:36:27.162091 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 11:36:27.162158
2505 11:36:27.165479 CA PerBit enable=1, Macro0, CA PI delay=32
2506 11:36:27.165539
2507 11:36:27.168813 [CBTSetCACLKResult] CA Dly = 32
2508 11:36:27.168875 CS Dly: 6 (0~38)
2509 11:36:27.168926
2510 11:36:27.172163 ----->DramcWriteLeveling(PI) begin...
2511 11:36:27.172223 ==
2512 11:36:27.175928 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:36:27.182212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:36:27.182281 ==
2515 11:36:27.185498 Write leveling (Byte 0): 32 => 32
2516 11:36:27.188817 Write leveling (Byte 1): 29 => 29
2517 11:36:27.188887 DramcWriteLeveling(PI) end<-----
2518 11:36:27.192512
2519 11:36:27.192580 ==
2520 11:36:27.195440 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 11:36:27.199214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 11:36:27.199283 ==
2523 11:36:27.202315 [Gating] SW mode calibration
2524 11:36:27.208780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 11:36:27.212209 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 11:36:27.218723 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2527 11:36:27.222709 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2528 11:36:27.226053 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 11:36:27.232225 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:36:27.235813 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:36:27.238745 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:36:27.245546 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2533 11:36:27.248871 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2534 11:36:27.252406 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2535 11:36:27.258747 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:36:27.262281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:36:27.265922 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:36:27.268620 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:36:27.275575 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:36:27.278974 1 0 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2541 11:36:27.282127 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2542 11:36:27.288855 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2543 11:36:27.292204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:36:27.295524 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:36:27.302415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:36:27.305842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:36:27.309459 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:36:27.315833 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 11:36:27.319808 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 11:36:27.323092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 11:36:27.329640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:36:27.332387 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:36:27.336190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:36:27.339179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:36:27.346195 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:36:27.349257 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:36:27.353012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:36:27.359337 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:36:27.362698 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:36:27.365789 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:36:27.372953 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:36:27.375871 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:36:27.379603 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:36:27.386610 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 11:36:27.389644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2566 11:36:27.392777 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2567 11:36:27.400034 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 11:36:27.400106 Total UI for P1: 0, mck2ui 16
2569 11:36:27.402665 best dqsien dly found for B0: ( 1, 3, 28)
2570 11:36:27.406457 Total UI for P1: 0, mck2ui 16
2571 11:36:27.409640 best dqsien dly found for B1: ( 1, 3, 30)
2572 11:36:27.412818 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 11:36:27.419355 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2574 11:36:27.419425
2575 11:36:27.423071 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 11:36:27.426256 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2577 11:36:27.429506 [Gating] SW calibration Done
2578 11:36:27.429580 ==
2579 11:36:27.432791 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 11:36:27.436110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 11:36:27.436188 ==
2582 11:36:27.436243 RX Vref Scan: 0
2583 11:36:27.436295
2584 11:36:27.439361 RX Vref 0 -> 0, step: 1
2585 11:36:27.439423
2586 11:36:27.442847 RX Delay -40 -> 252, step: 8
2587 11:36:27.445974 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2588 11:36:27.449505 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2589 11:36:27.456664 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2590 11:36:27.459497 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2591 11:36:27.462914 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2592 11:36:27.466075 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2593 11:36:27.469856 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2594 11:36:27.476383 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2595 11:36:27.479548 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2596 11:36:27.482832 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2597 11:36:27.486159 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2598 11:36:27.489184 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2599 11:36:27.496475 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2600 11:36:27.499852 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2601 11:36:27.503102 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2602 11:36:27.505954 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2603 11:36:27.506074 ==
2604 11:36:27.509367 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 11:36:27.512715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 11:36:27.516467 ==
2607 11:36:27.516536 DQS Delay:
2608 11:36:27.516594 DQS0 = 0, DQS1 = 0
2609 11:36:27.519510 DQM Delay:
2610 11:36:27.519576 DQM0 = 121, DQM1 = 113
2611 11:36:27.523022 DQ Delay:
2612 11:36:27.526155 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2613 11:36:27.530049 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2614 11:36:27.533159 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2615 11:36:27.536312 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2616 11:36:27.536377
2617 11:36:27.536432
2618 11:36:27.536484 ==
2619 11:36:27.539718 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 11:36:27.543483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 11:36:27.543546 ==
2622 11:36:27.543599
2623 11:36:27.543649
2624 11:36:27.546822 TX Vref Scan disable
2625 11:36:27.549594 == TX Byte 0 ==
2626 11:36:27.553201 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2627 11:36:27.556446 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2628 11:36:27.560050 == TX Byte 1 ==
2629 11:36:27.563009 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2630 11:36:27.566506 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2631 11:36:27.566571 ==
2632 11:36:27.570395 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:36:27.573385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:36:27.576544 ==
2635 11:36:27.587202 TX Vref=22, minBit 0, minWin=25, winSum=410
2636 11:36:27.590476 TX Vref=24, minBit 0, minWin=25, winSum=413
2637 11:36:27.593434 TX Vref=26, minBit 1, minWin=25, winSum=419
2638 11:36:27.596807 TX Vref=28, minBit 5, minWin=26, winSum=426
2639 11:36:27.600083 TX Vref=30, minBit 0, minWin=26, winSum=425
2640 11:36:27.603559 TX Vref=32, minBit 0, minWin=26, winSum=423
2641 11:36:27.610088 [TxChooseVref] Worse bit 5, Min win 26, Win sum 426, Final Vref 28
2642 11:36:27.610171
2643 11:36:27.613239 Final TX Range 1 Vref 28
2644 11:36:27.613302
2645 11:36:27.613371 ==
2646 11:36:27.617371 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 11:36:27.620487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 11:36:27.620553 ==
2649 11:36:27.620625
2650 11:36:27.620691
2651 11:36:27.623721 TX Vref Scan disable
2652 11:36:27.626603 == TX Byte 0 ==
2653 11:36:27.630158 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2654 11:36:27.633103 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2655 11:36:27.636700 == TX Byte 1 ==
2656 11:36:27.639934 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2657 11:36:27.643134 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2658 11:36:27.643209
2659 11:36:27.646877 [DATLAT]
2660 11:36:27.646946 Freq=1200, CH0 RK0
2661 11:36:27.647016
2662 11:36:27.650160 DATLAT Default: 0xd
2663 11:36:27.650247 0, 0xFFFF, sum = 0
2664 11:36:27.653476 1, 0xFFFF, sum = 0
2665 11:36:27.653563 2, 0xFFFF, sum = 0
2666 11:36:27.656936 3, 0xFFFF, sum = 0
2667 11:36:27.657000 4, 0xFFFF, sum = 0
2668 11:36:27.660299 5, 0xFFFF, sum = 0
2669 11:36:27.660387 6, 0xFFFF, sum = 0
2670 11:36:27.663264 7, 0xFFFF, sum = 0
2671 11:36:27.663350 8, 0xFFFF, sum = 0
2672 11:36:27.666456 9, 0xFFFF, sum = 0
2673 11:36:27.670191 10, 0xFFFF, sum = 0
2674 11:36:27.670259 11, 0xFFFF, sum = 0
2675 11:36:27.673504 12, 0x0, sum = 1
2676 11:36:27.673593 13, 0x0, sum = 2
2677 11:36:27.673665 14, 0x0, sum = 3
2678 11:36:27.676499 15, 0x0, sum = 4
2679 11:36:27.676563 best_step = 13
2680 11:36:27.676633
2681 11:36:27.676698 ==
2682 11:36:27.680184 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:36:27.687251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:36:27.687316 ==
2685 11:36:27.687410 RX Vref Scan: 1
2686 11:36:27.687493
2687 11:36:27.689794 Set Vref Range= 32 -> 127
2688 11:36:27.689858
2689 11:36:27.693729 RX Vref 32 -> 127, step: 1
2690 11:36:27.693792
2691 11:36:27.696855 RX Delay -13 -> 252, step: 4
2692 11:36:27.696921
2693 11:36:27.700096 Set Vref, RX VrefLevel [Byte0]: 32
2694 11:36:27.703387 [Byte1]: 32
2695 11:36:27.703452
2696 11:36:27.706719 Set Vref, RX VrefLevel [Byte0]: 33
2697 11:36:27.710196 [Byte1]: 33
2698 11:36:27.710290
2699 11:36:27.713559 Set Vref, RX VrefLevel [Byte0]: 34
2700 11:36:27.716691 [Byte1]: 34
2701 11:36:27.720880
2702 11:36:27.720969 Set Vref, RX VrefLevel [Byte0]: 35
2703 11:36:27.724020 [Byte1]: 35
2704 11:36:27.728610
2705 11:36:27.728675 Set Vref, RX VrefLevel [Byte0]: 36
2706 11:36:27.732041 [Byte1]: 36
2707 11:36:27.736485
2708 11:36:27.736548 Set Vref, RX VrefLevel [Byte0]: 37
2709 11:36:27.739768 [Byte1]: 37
2710 11:36:27.744281
2711 11:36:27.744352 Set Vref, RX VrefLevel [Byte0]: 38
2712 11:36:27.747826 [Byte1]: 38
2713 11:36:27.752315
2714 11:36:27.752381 Set Vref, RX VrefLevel [Byte0]: 39
2715 11:36:27.755310 [Byte1]: 39
2716 11:36:27.760280
2717 11:36:27.760344 Set Vref, RX VrefLevel [Byte0]: 40
2718 11:36:27.763245 [Byte1]: 40
2719 11:36:27.767948
2720 11:36:27.768016 Set Vref, RX VrefLevel [Byte0]: 41
2721 11:36:27.771725 [Byte1]: 41
2722 11:36:27.776328
2723 11:36:27.776394 Set Vref, RX VrefLevel [Byte0]: 42
2724 11:36:27.779697 [Byte1]: 42
2725 11:36:27.784223
2726 11:36:27.784288 Set Vref, RX VrefLevel [Byte0]: 43
2727 11:36:27.787038 [Byte1]: 43
2728 11:36:27.791558
2729 11:36:27.791622 Set Vref, RX VrefLevel [Byte0]: 44
2730 11:36:27.794923 [Byte1]: 44
2731 11:36:27.799712
2732 11:36:27.799778 Set Vref, RX VrefLevel [Byte0]: 45
2733 11:36:27.802796 [Byte1]: 45
2734 11:36:27.807319
2735 11:36:27.807385 Set Vref, RX VrefLevel [Byte0]: 46
2736 11:36:27.810759 [Byte1]: 46
2737 11:36:27.815664
2738 11:36:27.815730 Set Vref, RX VrefLevel [Byte0]: 47
2739 11:36:27.818785 [Byte1]: 47
2740 11:36:27.823253
2741 11:36:27.823319 Set Vref, RX VrefLevel [Byte0]: 48
2742 11:36:27.826452 [Byte1]: 48
2743 11:36:27.831192
2744 11:36:27.831257 Set Vref, RX VrefLevel [Byte0]: 49
2745 11:36:27.834396 [Byte1]: 49
2746 11:36:27.839224
2747 11:36:27.839288 Set Vref, RX VrefLevel [Byte0]: 50
2748 11:36:27.842438 [Byte1]: 50
2749 11:36:27.846806
2750 11:36:27.846872 Set Vref, RX VrefLevel [Byte0]: 51
2751 11:36:27.850749 [Byte1]: 51
2752 11:36:27.855249
2753 11:36:27.855316 Set Vref, RX VrefLevel [Byte0]: 52
2754 11:36:27.857992 [Byte1]: 52
2755 11:36:27.862493
2756 11:36:27.862559 Set Vref, RX VrefLevel [Byte0]: 53
2757 11:36:27.865769 [Byte1]: 53
2758 11:36:27.870527
2759 11:36:27.870594 Set Vref, RX VrefLevel [Byte0]: 54
2760 11:36:27.874338 [Byte1]: 54
2761 11:36:27.878254
2762 11:36:27.878347 Set Vref, RX VrefLevel [Byte0]: 55
2763 11:36:27.881616 [Byte1]: 55
2764 11:36:27.886618
2765 11:36:27.886686 Set Vref, RX VrefLevel [Byte0]: 56
2766 11:36:27.889789 [Byte1]: 56
2767 11:36:27.894166
2768 11:36:27.894233 Set Vref, RX VrefLevel [Byte0]: 57
2769 11:36:27.897563 [Byte1]: 57
2770 11:36:27.902171
2771 11:36:27.902236 Set Vref, RX VrefLevel [Byte0]: 58
2772 11:36:27.905409 [Byte1]: 58
2773 11:36:27.909937
2774 11:36:27.910064 Set Vref, RX VrefLevel [Byte0]: 59
2775 11:36:27.913312 [Byte1]: 59
2776 11:36:27.917739
2777 11:36:27.917827 Set Vref, RX VrefLevel [Byte0]: 60
2778 11:36:27.921677 [Byte1]: 60
2779 11:36:27.926494
2780 11:36:27.926559 Set Vref, RX VrefLevel [Byte0]: 61
2781 11:36:27.929045 [Byte1]: 61
2782 11:36:27.933422
2783 11:36:27.933484 Set Vref, RX VrefLevel [Byte0]: 62
2784 11:36:27.936881 [Byte1]: 62
2785 11:36:27.941498
2786 11:36:27.941583 Set Vref, RX VrefLevel [Byte0]: 63
2787 11:36:27.944866 [Byte1]: 63
2788 11:36:27.949703
2789 11:36:27.949801 Set Vref, RX VrefLevel [Byte0]: 64
2790 11:36:27.952838 [Byte1]: 64
2791 11:36:27.957268
2792 11:36:27.957355 Set Vref, RX VrefLevel [Byte0]: 65
2793 11:36:27.960853 [Byte1]: 65
2794 11:36:27.965638
2795 11:36:27.965711 Set Vref, RX VrefLevel [Byte0]: 66
2796 11:36:27.968891 [Byte1]: 66
2797 11:36:27.973007
2798 11:36:27.973079 Set Vref, RX VrefLevel [Byte0]: 67
2799 11:36:27.976165 [Byte1]: 67
2800 11:36:27.981461
2801 11:36:27.981555 Set Vref, RX VrefLevel [Byte0]: 68
2802 11:36:27.984072 [Byte1]: 68
2803 11:36:27.989012
2804 11:36:27.989102 Set Vref, RX VrefLevel [Byte0]: 69
2805 11:36:27.992366 [Byte1]: 69
2806 11:36:27.996758
2807 11:36:27.996853 Final RX Vref Byte 0 = 54 to rank0
2808 11:36:28.000037 Final RX Vref Byte 1 = 48 to rank0
2809 11:36:28.003935 Final RX Vref Byte 0 = 54 to rank1
2810 11:36:28.007006 Final RX Vref Byte 1 = 48 to rank1==
2811 11:36:28.009979 Dram Type= 6, Freq= 0, CH_0, rank 0
2812 11:36:28.013472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 11:36:28.017329 ==
2814 11:36:28.017426 DQS Delay:
2815 11:36:28.017513 DQS0 = 0, DQS1 = 0
2816 11:36:28.020771 DQM Delay:
2817 11:36:28.020842 DQM0 = 120, DQM1 = 111
2818 11:36:28.023888 DQ Delay:
2819 11:36:28.027181 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2820 11:36:28.030416 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2821 11:36:28.034824 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =104
2822 11:36:28.037532 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2823 11:36:28.037621
2824 11:36:28.037702
2825 11:36:28.044136 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2826 11:36:28.047207 CH0 RK0: MR19=404, MR18=150E
2827 11:36:28.053755 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2828 11:36:28.053855
2829 11:36:28.057297 ----->DramcWriteLeveling(PI) begin...
2830 11:36:28.057364 ==
2831 11:36:28.060885 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 11:36:28.063981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 11:36:28.064076 ==
2834 11:36:28.067344 Write leveling (Byte 0): 33 => 33
2835 11:36:28.070526 Write leveling (Byte 1): 29 => 29
2836 11:36:28.073876 DramcWriteLeveling(PI) end<-----
2837 11:36:28.073962
2838 11:36:28.074089 ==
2839 11:36:28.077285 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 11:36:28.080674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 11:36:28.083980 ==
2842 11:36:28.084049 [Gating] SW mode calibration
2843 11:36:28.090906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2844 11:36:28.097776 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2845 11:36:28.100815 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2846 11:36:28.107603 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:36:28.110729 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 11:36:28.113981 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 11:36:28.121034 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 11:36:28.124385 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 11:36:28.127687 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 11:36:28.133986 0 15 28 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 1)
2853 11:36:28.137611 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2854 11:36:28.140723 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:36:28.144106 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 11:36:28.150664 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 11:36:28.153858 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 11:36:28.157278 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 11:36:28.163954 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2860 11:36:28.167357 1 0 28 | B1->B0 | 3939 3938 | 0 1 | (0 0) (0 0)
2861 11:36:28.170530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:36:28.177291 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 11:36:28.180613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 11:36:28.183946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 11:36:28.191317 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:36:28.194441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:36:28.197751 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 11:36:28.204385 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2869 11:36:28.207988 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:36:28.210942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:36:28.218067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:36:28.221175 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:36:28.224321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:36:28.227326 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:36:28.234460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:36:28.237753 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:36:28.241216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:36:28.247983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:36:28.250995 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:36:28.254238 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:36:28.260930 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:36:28.264686 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:36:28.267651 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:36:28.274687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2885 11:36:28.277972 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2886 11:36:28.280954 Total UI for P1: 0, mck2ui 16
2887 11:36:28.284492 best dqsien dly found for B1: ( 1, 3, 28)
2888 11:36:28.287876 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 11:36:28.291055 Total UI for P1: 0, mck2ui 16
2890 11:36:28.294452 best dqsien dly found for B0: ( 1, 3, 30)
2891 11:36:28.297603 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2892 11:36:28.300816 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2893 11:36:28.300887
2894 11:36:28.304158 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2895 11:36:28.310879 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 11:36:28.310958 [Gating] SW calibration Done
2897 11:36:28.311030 ==
2898 11:36:28.314264 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 11:36:28.320878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 11:36:28.320969 ==
2901 11:36:28.321042 RX Vref Scan: 0
2902 11:36:28.321113
2903 11:36:28.324498 RX Vref 0 -> 0, step: 1
2904 11:36:28.324597
2905 11:36:28.327840 RX Delay -40 -> 252, step: 8
2906 11:36:28.330991 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2907 11:36:28.334519 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2908 11:36:28.337779 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2909 11:36:28.344422 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2910 11:36:28.347335 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2911 11:36:28.351101 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2912 11:36:28.353937 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2913 11:36:28.357305 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2914 11:36:28.360672 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2915 11:36:28.367465 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2916 11:36:28.370720 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2917 11:36:28.373941 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2918 11:36:28.377471 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2919 11:36:28.384318 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2920 11:36:28.387595 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2921 11:36:28.390930 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2922 11:36:28.391030 ==
2923 11:36:28.394163 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 11:36:28.397761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 11:36:28.397861 ==
2926 11:36:28.401263 DQS Delay:
2927 11:36:28.401351 DQS0 = 0, DQS1 = 0
2928 11:36:28.404270 DQM Delay:
2929 11:36:28.404336 DQM0 = 121, DQM1 = 112
2930 11:36:28.404406 DQ Delay:
2931 11:36:28.407601 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2932 11:36:28.410828 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2933 11:36:28.417238 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2934 11:36:28.420847 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2935 11:36:28.420917
2936 11:36:28.420987
2937 11:36:28.421061 ==
2938 11:36:28.423685 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 11:36:28.427560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 11:36:28.427661 ==
2941 11:36:28.427752
2942 11:36:28.427839
2943 11:36:28.430854 TX Vref Scan disable
2944 11:36:28.434253 == TX Byte 0 ==
2945 11:36:28.437730 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2946 11:36:28.440600 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2947 11:36:28.443999 == TX Byte 1 ==
2948 11:36:28.447254 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2949 11:36:28.450918 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2950 11:36:28.450990 ==
2951 11:36:28.454099 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 11:36:28.457067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 11:36:28.460310 ==
2954 11:36:28.470889 TX Vref=22, minBit 1, minWin=25, winSum=415
2955 11:36:28.474124 TX Vref=24, minBit 3, minWin=25, winSum=421
2956 11:36:28.477296 TX Vref=26, minBit 1, minWin=26, winSum=422
2957 11:36:28.480630 TX Vref=28, minBit 3, minWin=26, winSum=430
2958 11:36:28.484118 TX Vref=30, minBit 12, minWin=25, winSum=428
2959 11:36:28.487763 TX Vref=32, minBit 0, minWin=26, winSum=426
2960 11:36:28.494883 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
2961 11:36:28.494959
2962 11:36:28.497928 Final TX Range 1 Vref 28
2963 11:36:28.498048
2964 11:36:28.498109 ==
2965 11:36:28.501195 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 11:36:28.504238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 11:36:28.504314 ==
2968 11:36:28.504372
2969 11:36:28.507503
2970 11:36:28.507577 TX Vref Scan disable
2971 11:36:28.510967 == TX Byte 0 ==
2972 11:36:28.514090 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2973 11:36:28.517607 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2974 11:36:28.520900 == TX Byte 1 ==
2975 11:36:28.524748 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2976 11:36:28.527647 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2977 11:36:28.527736
2978 11:36:28.530742 [DATLAT]
2979 11:36:28.530842 Freq=1200, CH0 RK1
2980 11:36:28.530922
2981 11:36:28.534202 DATLAT Default: 0xd
2982 11:36:28.534277 0, 0xFFFF, sum = 0
2983 11:36:28.537882 1, 0xFFFF, sum = 0
2984 11:36:28.537982 2, 0xFFFF, sum = 0
2985 11:36:28.540952 3, 0xFFFF, sum = 0
2986 11:36:28.541028 4, 0xFFFF, sum = 0
2987 11:36:28.544429 5, 0xFFFF, sum = 0
2988 11:36:28.547475 6, 0xFFFF, sum = 0
2989 11:36:28.547551 7, 0xFFFF, sum = 0
2990 11:36:28.550760 8, 0xFFFF, sum = 0
2991 11:36:28.550836 9, 0xFFFF, sum = 0
2992 11:36:28.554015 10, 0xFFFF, sum = 0
2993 11:36:28.554105 11, 0xFFFF, sum = 0
2994 11:36:28.557912 12, 0x0, sum = 1
2995 11:36:28.558001 13, 0x0, sum = 2
2996 11:36:28.560702 14, 0x0, sum = 3
2997 11:36:28.560777 15, 0x0, sum = 4
2998 11:36:28.560836 best_step = 13
2999 11:36:28.560890
3000 11:36:28.564298 ==
3001 11:36:28.567555 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 11:36:28.570724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 11:36:28.570799 ==
3004 11:36:28.570857 RX Vref Scan: 0
3005 11:36:28.570911
3006 11:36:28.573884 RX Vref 0 -> 0, step: 1
3007 11:36:28.573957
3008 11:36:28.577691 RX Delay -13 -> 252, step: 4
3009 11:36:28.580988 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3010 11:36:28.587714 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3011 11:36:28.591138 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3012 11:36:28.594600 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3013 11:36:28.597287 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3014 11:36:28.601010 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3015 11:36:28.604124 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3016 11:36:28.610812 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3017 11:36:28.614342 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3018 11:36:28.617660 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3019 11:36:28.620831 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3020 11:36:28.624311 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3021 11:36:28.630559 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3022 11:36:28.633765 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3023 11:36:28.637291 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3024 11:36:28.640339 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3025 11:36:28.640430 ==
3026 11:36:28.643630 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 11:36:28.650595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 11:36:28.650673 ==
3029 11:36:28.650732 DQS Delay:
3030 11:36:28.653727 DQS0 = 0, DQS1 = 0
3031 11:36:28.653788 DQM Delay:
3032 11:36:28.656947 DQM0 = 120, DQM1 = 109
3033 11:36:28.657024 DQ Delay:
3034 11:36:28.660605 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3035 11:36:28.663765 DQ4 =122, DQ5 =116, DQ6 =124, DQ7 =126
3036 11:36:28.667433 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3037 11:36:28.670302 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3038 11:36:28.670377
3039 11:36:28.670435
3040 11:36:28.680309 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3041 11:36:28.680385 CH0 RK1: MR19=403, MR18=11F1
3042 11:36:28.687165 CH0_RK1: MR19=0x403, MR18=0x11F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3043 11:36:28.690454 [RxdqsGatingPostProcess] freq 1200
3044 11:36:28.697306 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3045 11:36:28.700644 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 11:36:28.703701 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 11:36:28.707128 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 11:36:28.710546 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 11:36:28.713188 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 11:36:28.716627 best DQS1 dly(2T, 0.5T) = (0, 11)
3051 11:36:28.719889 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 11:36:28.723693 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3053 11:36:28.723770 Pre-setting of DQS Precalculation
3054 11:36:28.730407 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3055 11:36:28.730510 ==
3056 11:36:28.733637 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 11:36:28.736526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:36:28.736628 ==
3059 11:36:28.743174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3060 11:36:28.749743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3061 11:36:28.757393 [CA 0] Center 37 (7~68) winsize 62
3062 11:36:28.760740 [CA 1] Center 37 (7~68) winsize 62
3063 11:36:28.763711 [CA 2] Center 34 (4~65) winsize 62
3064 11:36:28.767298 [CA 3] Center 34 (4~64) winsize 61
3065 11:36:28.770654 [CA 4] Center 34 (4~64) winsize 61
3066 11:36:28.773757 [CA 5] Center 33 (3~63) winsize 61
3067 11:36:28.773827
3068 11:36:28.777349 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3069 11:36:28.777444
3070 11:36:28.780417 [CATrainingPosCal] consider 1 rank data
3071 11:36:28.783893 u2DelayCellTimex100 = 270/100 ps
3072 11:36:28.786914 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 11:36:28.793803 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 11:36:28.797051 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3075 11:36:28.800445 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3076 11:36:28.803834 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3077 11:36:28.806939 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3078 11:36:28.807010
3079 11:36:28.810570 CA PerBit enable=1, Macro0, CA PI delay=33
3080 11:36:28.810635
3081 11:36:28.813713 [CBTSetCACLKResult] CA Dly = 33
3082 11:36:28.813798 CS Dly: 8 (0~39)
3083 11:36:28.817097 ==
3084 11:36:28.820577 Dram Type= 6, Freq= 0, CH_1, rank 1
3085 11:36:28.823938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:36:28.824045 ==
3087 11:36:28.827226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 11:36:28.833623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3089 11:36:28.843317 [CA 0] Center 37 (7~68) winsize 62
3090 11:36:28.846000 [CA 1] Center 38 (8~68) winsize 61
3091 11:36:28.849434 [CA 2] Center 35 (5~66) winsize 62
3092 11:36:28.853107 [CA 3] Center 34 (4~65) winsize 62
3093 11:36:28.856518 [CA 4] Center 34 (4~65) winsize 62
3094 11:36:28.859750 [CA 5] Center 34 (4~64) winsize 61
3095 11:36:28.859825
3096 11:36:28.863267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 11:36:28.863342
3098 11:36:28.866544 [CATrainingPosCal] consider 2 rank data
3099 11:36:28.869403 u2DelayCellTimex100 = 270/100 ps
3100 11:36:28.873126 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 11:36:28.875964 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3102 11:36:28.882573 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3103 11:36:28.885883 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 11:36:28.889182 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 11:36:28.893222 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3106 11:36:28.893296
3107 11:36:28.895971 CA PerBit enable=1, Macro0, CA PI delay=33
3108 11:36:28.896045
3109 11:36:28.899324 [CBTSetCACLKResult] CA Dly = 33
3110 11:36:28.899403 CS Dly: 9 (0~41)
3111 11:36:28.899461
3112 11:36:28.902933 ----->DramcWriteLeveling(PI) begin...
3113 11:36:28.906478 ==
3114 11:36:28.909670 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:36:28.912785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:36:28.912882 ==
3117 11:36:28.915988 Write leveling (Byte 0): 26 => 26
3118 11:36:28.919847 Write leveling (Byte 1): 26 => 26
3119 11:36:28.922952 DramcWriteLeveling(PI) end<-----
3120 11:36:28.923068
3121 11:36:28.923151 ==
3122 11:36:28.925955 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 11:36:28.929350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 11:36:28.929425 ==
3125 11:36:28.932668 [Gating] SW mode calibration
3126 11:36:28.939619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3127 11:36:28.946297 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3128 11:36:28.949181 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:36:28.952664 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 11:36:28.959221 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 11:36:28.962477 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 11:36:28.965922 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 11:36:28.969277 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 11:36:28.975935 0 15 24 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
3135 11:36:28.979231 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3136 11:36:28.982357 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:36:28.989132 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:36:28.992595 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 11:36:28.995916 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 11:36:29.002589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 11:36:29.005629 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 11:36:29.009020 1 0 24 | B1->B0 | 3737 4242 | 1 0 | (0 0) (1 1)
3143 11:36:29.015969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:36:29.019264 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:36:29.022646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 11:36:29.028978 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:36:29.032897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:36:29.035457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:36:29.042412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:36:29.045664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3151 11:36:29.049320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3152 11:36:29.056230 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:36:29.059190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:36:29.062581 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:36:29.068824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:36:29.072312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:36:29.075352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:36:29.078783 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:36:29.085514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:36:29.089016 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:36:29.092355 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:36:29.099385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:36:29.102584 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:36:29.105357 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:36:29.111947 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:36:29.115726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 11:36:29.119108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 11:36:29.121922 Total UI for P1: 0, mck2ui 16
3169 11:36:29.125727 best dqsien dly found for B0: ( 1, 3, 24)
3170 11:36:29.128538 Total UI for P1: 0, mck2ui 16
3171 11:36:29.132367 best dqsien dly found for B1: ( 1, 3, 24)
3172 11:36:29.135646 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3173 11:36:29.138962 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3174 11:36:29.139038
3175 11:36:29.145419 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3176 11:36:29.148699 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3177 11:36:29.152383 [Gating] SW calibration Done
3178 11:36:29.152458 ==
3179 11:36:29.155572 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 11:36:29.158595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 11:36:29.158672 ==
3182 11:36:29.158731 RX Vref Scan: 0
3183 11:36:29.158785
3184 11:36:29.161844 RX Vref 0 -> 0, step: 1
3185 11:36:29.161920
3186 11:36:29.166115 RX Delay -40 -> 252, step: 8
3187 11:36:29.169176 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3188 11:36:29.172216 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3189 11:36:29.178641 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3190 11:36:29.181668 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3191 11:36:29.185147 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3192 11:36:29.188251 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3193 11:36:29.191821 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3194 11:36:29.198422 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3195 11:36:29.202181 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3196 11:36:29.205520 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3197 11:36:29.208232 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3198 11:36:29.211815 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3199 11:36:29.218254 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3200 11:36:29.221605 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3201 11:36:29.224995 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3202 11:36:29.228383 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3203 11:36:29.228458 ==
3204 11:36:29.231524 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 11:36:29.238591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 11:36:29.238668 ==
3207 11:36:29.238726 DQS Delay:
3208 11:36:29.241846 DQS0 = 0, DQS1 = 0
3209 11:36:29.241921 DQM Delay:
3210 11:36:29.241993 DQM0 = 120, DQM1 = 116
3211 11:36:29.245099 DQ Delay:
3212 11:36:29.248246 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3213 11:36:29.251300 DQ4 =123, DQ5 =127, DQ6 =127, DQ7 =123
3214 11:36:29.255160 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3215 11:36:29.258162 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3216 11:36:29.258236
3217 11:36:29.258294
3218 11:36:29.258346 ==
3219 11:36:29.261273 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 11:36:29.264550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 11:36:29.267835 ==
3222 11:36:29.267909
3223 11:36:29.267966
3224 11:36:29.268020 TX Vref Scan disable
3225 11:36:29.271114 == TX Byte 0 ==
3226 11:36:29.274344 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3227 11:36:29.277644 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3228 11:36:29.281671 == TX Byte 1 ==
3229 11:36:29.284411 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 11:36:29.287647 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 11:36:29.291077 ==
3232 11:36:29.294729 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 11:36:29.297773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 11:36:29.297873 ==
3235 11:36:29.308685 TX Vref=22, minBit 11, minWin=24, winSum=412
3236 11:36:29.311987 TX Vref=24, minBit 9, minWin=25, winSum=419
3237 11:36:29.315180 TX Vref=26, minBit 2, minWin=26, winSum=426
3238 11:36:29.318951 TX Vref=28, minBit 1, minWin=26, winSum=428
3239 11:36:29.322212 TX Vref=30, minBit 9, minWin=25, winSum=429
3240 11:36:29.328556 TX Vref=32, minBit 2, minWin=26, winSum=431
3241 11:36:29.331961 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 32
3242 11:36:29.332036
3243 11:36:29.335315 Final TX Range 1 Vref 32
3244 11:36:29.335390
3245 11:36:29.335453 ==
3246 11:36:29.338478 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 11:36:29.341691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 11:36:29.341788 ==
3249 11:36:29.345066
3250 11:36:29.345169
3251 11:36:29.345273 TX Vref Scan disable
3252 11:36:29.348795 == TX Byte 0 ==
3253 11:36:29.352128 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3254 11:36:29.355416 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3255 11:36:29.358457 == TX Byte 1 ==
3256 11:36:29.361606 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 11:36:29.364955 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 11:36:29.368780
3259 11:36:29.368881 [DATLAT]
3260 11:36:29.368966 Freq=1200, CH1 RK0
3261 11:36:29.369047
3262 11:36:29.372067 DATLAT Default: 0xd
3263 11:36:29.372165 0, 0xFFFF, sum = 0
3264 11:36:29.375463 1, 0xFFFF, sum = 0
3265 11:36:29.375538 2, 0xFFFF, sum = 0
3266 11:36:29.378591 3, 0xFFFF, sum = 0
3267 11:36:29.378666 4, 0xFFFF, sum = 0
3268 11:36:29.381806 5, 0xFFFF, sum = 0
3269 11:36:29.385017 6, 0xFFFF, sum = 0
3270 11:36:29.385091 7, 0xFFFF, sum = 0
3271 11:36:29.388524 8, 0xFFFF, sum = 0
3272 11:36:29.388599 9, 0xFFFF, sum = 0
3273 11:36:29.391989 10, 0xFFFF, sum = 0
3274 11:36:29.392069 11, 0xFFFF, sum = 0
3275 11:36:29.395151 12, 0x0, sum = 1
3276 11:36:29.395227 13, 0x0, sum = 2
3277 11:36:29.398418 14, 0x0, sum = 3
3278 11:36:29.398493 15, 0x0, sum = 4
3279 11:36:29.398551 best_step = 13
3280 11:36:29.401639
3281 11:36:29.401713 ==
3282 11:36:29.405129 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 11:36:29.408516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 11:36:29.408591 ==
3285 11:36:29.408649 RX Vref Scan: 1
3286 11:36:29.408702
3287 11:36:29.411733 Set Vref Range= 32 -> 127
3288 11:36:29.411831
3289 11:36:29.414724 RX Vref 32 -> 127, step: 1
3290 11:36:29.414801
3291 11:36:29.418222 RX Delay -5 -> 252, step: 4
3292 11:36:29.418289
3293 11:36:29.421265 Set Vref, RX VrefLevel [Byte0]: 32
3294 11:36:29.424658 [Byte1]: 32
3295 11:36:29.424756
3296 11:36:29.428137 Set Vref, RX VrefLevel [Byte0]: 33
3297 11:36:29.431346 [Byte1]: 33
3298 11:36:29.434884
3299 11:36:29.434960 Set Vref, RX VrefLevel [Byte0]: 34
3300 11:36:29.437945 [Byte1]: 34
3301 11:36:29.442490
3302 11:36:29.442564 Set Vref, RX VrefLevel [Byte0]: 35
3303 11:36:29.445858 [Byte1]: 35
3304 11:36:29.450547
3305 11:36:29.450621 Set Vref, RX VrefLevel [Byte0]: 36
3306 11:36:29.453726 [Byte1]: 36
3307 11:36:29.458411
3308 11:36:29.458485 Set Vref, RX VrefLevel [Byte0]: 37
3309 11:36:29.461923 [Byte1]: 37
3310 11:36:29.466340
3311 11:36:29.466415 Set Vref, RX VrefLevel [Byte0]: 38
3312 11:36:29.469571 [Byte1]: 38
3313 11:36:29.474430
3314 11:36:29.474503 Set Vref, RX VrefLevel [Byte0]: 39
3315 11:36:29.477591 [Byte1]: 39
3316 11:36:29.482063
3317 11:36:29.482137 Set Vref, RX VrefLevel [Byte0]: 40
3318 11:36:29.485283 [Byte1]: 40
3319 11:36:29.489856
3320 11:36:29.489929 Set Vref, RX VrefLevel [Byte0]: 41
3321 11:36:29.493112 [Byte1]: 41
3322 11:36:29.497600
3323 11:36:29.497674 Set Vref, RX VrefLevel [Byte0]: 42
3324 11:36:29.500899 [Byte1]: 42
3325 11:36:29.505070
3326 11:36:29.505143 Set Vref, RX VrefLevel [Byte0]: 43
3327 11:36:29.511601 [Byte1]: 43
3328 11:36:29.511675
3329 11:36:29.515825 Set Vref, RX VrefLevel [Byte0]: 44
3330 11:36:29.518202 [Byte1]: 44
3331 11:36:29.518275
3332 11:36:29.521560 Set Vref, RX VrefLevel [Byte0]: 45
3333 11:36:29.525072 [Byte1]: 45
3334 11:36:29.529303
3335 11:36:29.529376 Set Vref, RX VrefLevel [Byte0]: 46
3336 11:36:29.532191 [Byte1]: 46
3337 11:36:29.536803
3338 11:36:29.536909 Set Vref, RX VrefLevel [Byte0]: 47
3339 11:36:29.540182 [Byte1]: 47
3340 11:36:29.545077
3341 11:36:29.545168 Set Vref, RX VrefLevel [Byte0]: 48
3342 11:36:29.547915 [Byte1]: 48
3343 11:36:29.552604
3344 11:36:29.552678 Set Vref, RX VrefLevel [Byte0]: 49
3345 11:36:29.556064 [Byte1]: 49
3346 11:36:29.560520
3347 11:36:29.560594 Set Vref, RX VrefLevel [Byte0]: 50
3348 11:36:29.563682 [Byte1]: 50
3349 11:36:29.568504
3350 11:36:29.568577 Set Vref, RX VrefLevel [Byte0]: 51
3351 11:36:29.571544 [Byte1]: 51
3352 11:36:29.576126
3353 11:36:29.576194 Set Vref, RX VrefLevel [Byte0]: 52
3354 11:36:29.579736 [Byte1]: 52
3355 11:36:29.583918
3356 11:36:29.584002 Set Vref, RX VrefLevel [Byte0]: 53
3357 11:36:29.587174 [Byte1]: 53
3358 11:36:29.591862
3359 11:36:29.591950 Set Vref, RX VrefLevel [Byte0]: 54
3360 11:36:29.594839 [Byte1]: 54
3361 11:36:29.599482
3362 11:36:29.599570 Set Vref, RX VrefLevel [Byte0]: 55
3363 11:36:29.602619 [Byte1]: 55
3364 11:36:29.607462
3365 11:36:29.610744 Set Vref, RX VrefLevel [Byte0]: 56
3366 11:36:29.610817 [Byte1]: 56
3367 11:36:29.615448
3368 11:36:29.615515 Set Vref, RX VrefLevel [Byte0]: 57
3369 11:36:29.618761 [Byte1]: 57
3370 11:36:29.623564
3371 11:36:29.623632 Set Vref, RX VrefLevel [Byte0]: 58
3372 11:36:29.626780 [Byte1]: 58
3373 11:36:29.630932
3374 11:36:29.631007 Set Vref, RX VrefLevel [Byte0]: 59
3375 11:36:29.634195 [Byte1]: 59
3376 11:36:29.638858
3377 11:36:29.638932 Set Vref, RX VrefLevel [Byte0]: 60
3378 11:36:29.641964 [Byte1]: 60
3379 11:36:29.646507
3380 11:36:29.646582 Set Vref, RX VrefLevel [Byte0]: 61
3381 11:36:29.650382 [Byte1]: 61
3382 11:36:29.654256
3383 11:36:29.654334 Set Vref, RX VrefLevel [Byte0]: 62
3384 11:36:29.657573 [Byte1]: 62
3385 11:36:29.662346
3386 11:36:29.662445 Set Vref, RX VrefLevel [Byte0]: 63
3387 11:36:29.665982 [Byte1]: 63
3388 11:36:29.670272
3389 11:36:29.670355 Set Vref, RX VrefLevel [Byte0]: 64
3390 11:36:29.673543 [Byte1]: 64
3391 11:36:29.678187
3392 11:36:29.678273 Set Vref, RX VrefLevel [Byte0]: 65
3393 11:36:29.681270 [Byte1]: 65
3394 11:36:29.686048
3395 11:36:29.686126 Set Vref, RX VrefLevel [Byte0]: 66
3396 11:36:29.688884 [Byte1]: 66
3397 11:36:29.693857
3398 11:36:29.693933 Set Vref, RX VrefLevel [Byte0]: 67
3399 11:36:29.696889 [Byte1]: 67
3400 11:36:29.701751
3401 11:36:29.701823 Set Vref, RX VrefLevel [Byte0]: 68
3402 11:36:29.705333 [Byte1]: 68
3403 11:36:29.709413
3404 11:36:29.709494 Set Vref, RX VrefLevel [Byte0]: 69
3405 11:36:29.712649 [Byte1]: 69
3406 11:36:29.717430
3407 11:36:29.717526 Final RX Vref Byte 0 = 55 to rank0
3408 11:36:29.720784 Final RX Vref Byte 1 = 52 to rank0
3409 11:36:29.724021 Final RX Vref Byte 0 = 55 to rank1
3410 11:36:29.727256 Final RX Vref Byte 1 = 52 to rank1==
3411 11:36:29.730684 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 11:36:29.737560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 11:36:29.737671 ==
3414 11:36:29.737757 DQS Delay:
3415 11:36:29.737847 DQS0 = 0, DQS1 = 0
3416 11:36:29.740806 DQM Delay:
3417 11:36:29.740884 DQM0 = 120, DQM1 = 117
3418 11:36:29.743957 DQ Delay:
3419 11:36:29.747836 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3420 11:36:29.751026 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =122
3421 11:36:29.753809 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3422 11:36:29.757697 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3423 11:36:29.757773
3424 11:36:29.757833
3425 11:36:29.764191 [DQSOSCAuto] RK0, (LSB)MR18= 0x517, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3426 11:36:29.767256 CH1 RK0: MR19=404, MR18=517
3427 11:36:29.773810 CH1_RK0: MR19=0x404, MR18=0x517, DQSOSC=401, MR23=63, INC=40, DEC=27
3428 11:36:29.773888
3429 11:36:29.777714 ----->DramcWriteLeveling(PI) begin...
3430 11:36:29.777793 ==
3431 11:36:29.780225 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:36:29.783668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 11:36:29.786971 ==
3434 11:36:29.787094 Write leveling (Byte 0): 26 => 26
3435 11:36:29.790261 Write leveling (Byte 1): 30 => 30
3436 11:36:29.793652 DramcWriteLeveling(PI) end<-----
3437 11:36:29.793749
3438 11:36:29.793834 ==
3439 11:36:29.797252 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 11:36:29.803845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 11:36:29.803959 ==
3442 11:36:29.804045 [Gating] SW mode calibration
3443 11:36:29.813886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3444 11:36:29.817078 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3445 11:36:29.823658 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 11:36:29.826713 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 11:36:29.829966 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:36:29.833439 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:36:29.840241 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:36:29.843566 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3451 11:36:29.846980 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (0 0)
3452 11:36:29.853943 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 1)
3453 11:36:29.857299 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 11:36:29.860342 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:36:29.866796 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:36:29.869957 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:36:29.873359 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:36:29.880179 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3459 11:36:29.883096 1 0 24 | B1->B0 | 4545 2c2c | 0 0 | (0 0) (0 0)
3460 11:36:29.886446 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:36:29.893858 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 11:36:29.896482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:36:29.899986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:36:29.906582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:36:29.909797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:36:29.913363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:36:29.919773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3468 11:36:29.923047 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3469 11:36:29.926330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:36:29.933108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:36:29.936308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:36:29.940058 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:36:29.946414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:36:29.949798 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:36:29.952869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:36:29.959689 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:36:29.963447 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:36:29.966215 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:36:29.969674 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:36:29.976220 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:36:29.979431 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3482 11:36:29.982830 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3483 11:36:29.989963 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3484 11:36:29.993385 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3485 11:36:29.996130 Total UI for P1: 0, mck2ui 16
3486 11:36:29.999891 best dqsien dly found for B1: ( 1, 3, 20)
3487 11:36:30.002743 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 11:36:30.006678 Total UI for P1: 0, mck2ui 16
3489 11:36:30.009802 best dqsien dly found for B0: ( 1, 3, 26)
3490 11:36:30.013104 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3491 11:36:30.016476 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3492 11:36:30.019529
3493 11:36:30.023232 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3494 11:36:30.025977 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3495 11:36:30.029239 [Gating] SW calibration Done
3496 11:36:30.029330 ==
3497 11:36:30.032551 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 11:36:30.035707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 11:36:30.035775 ==
3500 11:36:30.035831 RX Vref Scan: 0
3501 11:36:30.039485
3502 11:36:30.039581 RX Vref 0 -> 0, step: 1
3503 11:36:30.039671
3504 11:36:30.042681 RX Delay -40 -> 252, step: 8
3505 11:36:30.046158 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3506 11:36:30.049166 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3507 11:36:30.055867 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3508 11:36:30.059214 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3509 11:36:30.062853 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3510 11:36:30.065533 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3511 11:36:30.069501 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3512 11:36:30.075483 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3513 11:36:30.078692 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3514 11:36:30.082396 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3515 11:36:30.085657 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3516 11:36:30.088972 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3517 11:36:30.095853 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3518 11:36:30.099157 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3519 11:36:30.102221 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3520 11:36:30.105562 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3521 11:36:30.105622 ==
3522 11:36:30.109076 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 11:36:30.115369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 11:36:30.115445 ==
3525 11:36:30.115503 DQS Delay:
3526 11:36:30.119602 DQS0 = 0, DQS1 = 0
3527 11:36:30.119674 DQM Delay:
3528 11:36:30.122127 DQM0 = 120, DQM1 = 118
3529 11:36:30.122197 DQ Delay:
3530 11:36:30.125550 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3531 11:36:30.128611 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3532 11:36:30.132210 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3533 11:36:30.135447 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3534 11:36:30.135527
3535 11:36:30.135582
3536 11:36:30.135634 ==
3537 11:36:30.139129 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 11:36:30.145470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 11:36:30.145567 ==
3540 11:36:30.145647
3541 11:36:30.145724
3542 11:36:30.145808 TX Vref Scan disable
3543 11:36:30.149206 == TX Byte 0 ==
3544 11:36:30.152223 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3545 11:36:30.158623 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3546 11:36:30.158690 == TX Byte 1 ==
3547 11:36:30.161918 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3548 11:36:30.168686 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3549 11:36:30.168752 ==
3550 11:36:30.171979 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 11:36:30.175375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 11:36:30.175462 ==
3553 11:36:30.186392 TX Vref=22, minBit 9, minWin=25, winSum=419
3554 11:36:30.190134 TX Vref=24, minBit 0, minWin=26, winSum=425
3555 11:36:30.193447 TX Vref=26, minBit 2, minWin=26, winSum=433
3556 11:36:30.196604 TX Vref=28, minBit 9, minWin=26, winSum=433
3557 11:36:30.199873 TX Vref=30, minBit 9, minWin=26, winSum=436
3558 11:36:30.203587 TX Vref=32, minBit 9, minWin=26, winSum=438
3559 11:36:30.210142 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 32
3560 11:36:30.210268
3561 11:36:30.213539 Final TX Range 1 Vref 32
3562 11:36:30.213650
3563 11:36:30.213707 ==
3564 11:36:30.216599 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 11:36:30.220531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 11:36:30.220621 ==
3567 11:36:30.220709
3568 11:36:30.223134
3569 11:36:30.223197 TX Vref Scan disable
3570 11:36:30.226926 == TX Byte 0 ==
3571 11:36:30.230142 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 11:36:30.233454 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 11:36:30.236579 == TX Byte 1 ==
3574 11:36:30.239813 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3575 11:36:30.243555 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3576 11:36:30.243619
3577 11:36:30.246694 [DATLAT]
3578 11:36:30.246781 Freq=1200, CH1 RK1
3579 11:36:30.246861
3580 11:36:30.250517 DATLAT Default: 0xd
3581 11:36:30.250583 0, 0xFFFF, sum = 0
3582 11:36:30.253509 1, 0xFFFF, sum = 0
3583 11:36:30.253570 2, 0xFFFF, sum = 0
3584 11:36:30.256448 3, 0xFFFF, sum = 0
3585 11:36:30.256508 4, 0xFFFF, sum = 0
3586 11:36:30.260177 5, 0xFFFF, sum = 0
3587 11:36:30.260253 6, 0xFFFF, sum = 0
3588 11:36:30.263436 7, 0xFFFF, sum = 0
3589 11:36:30.266623 8, 0xFFFF, sum = 0
3590 11:36:30.266698 9, 0xFFFF, sum = 0
3591 11:36:30.269880 10, 0xFFFF, sum = 0
3592 11:36:30.269955 11, 0xFFFF, sum = 0
3593 11:36:30.273154 12, 0x0, sum = 1
3594 11:36:30.273229 13, 0x0, sum = 2
3595 11:36:30.276357 14, 0x0, sum = 3
3596 11:36:30.276432 15, 0x0, sum = 4
3597 11:36:30.276491 best_step = 13
3598 11:36:30.276543
3599 11:36:30.279814 ==
3600 11:36:30.283263 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 11:36:30.286158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 11:36:30.286233 ==
3603 11:36:30.286291 RX Vref Scan: 0
3604 11:36:30.286345
3605 11:36:30.290151 RX Vref 0 -> 0, step: 1
3606 11:36:30.290224
3607 11:36:30.292921 RX Delay -5 -> 252, step: 4
3608 11:36:30.296399 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3609 11:36:30.303180 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3610 11:36:30.306279 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3611 11:36:30.309663 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3612 11:36:30.312941 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3613 11:36:30.316258 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3614 11:36:30.322954 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3615 11:36:30.325998 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3616 11:36:30.330043 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3617 11:36:30.333004 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3618 11:36:30.336115 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3619 11:36:30.342754 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3620 11:36:30.345804 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3621 11:36:30.349133 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3622 11:36:30.352519 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3623 11:36:30.356248 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3624 11:36:30.359474 ==
3625 11:36:30.359548 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 11:36:30.366025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 11:36:30.366116 ==
3628 11:36:30.366174 DQS Delay:
3629 11:36:30.368939 DQS0 = 0, DQS1 = 0
3630 11:36:30.369013 DQM Delay:
3631 11:36:30.372959 DQM0 = 120, DQM1 = 117
3632 11:36:30.373033 DQ Delay:
3633 11:36:30.376625 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3634 11:36:30.379654 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3635 11:36:30.382391 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =112
3636 11:36:30.386267 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128
3637 11:36:30.386341
3638 11:36:30.386398
3639 11:36:30.395746 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3640 11:36:30.399030 CH1 RK1: MR19=403, MR18=14F0
3641 11:36:30.402541 CH1_RK1: MR19=0x403, MR18=0x14F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3642 11:36:30.406055 [RxdqsGatingPostProcess] freq 1200
3643 11:36:30.412234 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 11:36:30.415602 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 11:36:30.419030 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 11:36:30.422218 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 11:36:30.425591 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 11:36:30.429419 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 11:36:30.432778 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 11:36:30.435700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 11:36:30.438780 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 11:36:30.438854 Pre-setting of DQS Precalculation
3653 11:36:30.445950 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 11:36:30.452199 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 11:36:30.458755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 11:36:30.458830
3657 11:36:30.458888
3658 11:36:30.461974 [Calibration Summary] 2400 Mbps
3659 11:36:30.465264 CH 0, Rank 0
3660 11:36:30.465338 SW Impedance : PASS
3661 11:36:30.469120 DUTY Scan : NO K
3662 11:36:30.472286 ZQ Calibration : PASS
3663 11:36:30.472361 Jitter Meter : NO K
3664 11:36:30.475680 CBT Training : PASS
3665 11:36:30.478724 Write leveling : PASS
3666 11:36:30.478798 RX DQS gating : PASS
3667 11:36:30.482188 RX DQ/DQS(RDDQC) : PASS
3668 11:36:30.485346 TX DQ/DQS : PASS
3669 11:36:30.485421 RX DATLAT : PASS
3670 11:36:30.488631 RX DQ/DQS(Engine): PASS
3671 11:36:30.488705 TX OE : NO K
3672 11:36:30.492104 All Pass.
3673 11:36:30.492178
3674 11:36:30.492235 CH 0, Rank 1
3675 11:36:30.495316 SW Impedance : PASS
3676 11:36:30.495390 DUTY Scan : NO K
3677 11:36:30.499050 ZQ Calibration : PASS
3678 11:36:30.502141 Jitter Meter : NO K
3679 11:36:30.502215 CBT Training : PASS
3680 11:36:30.505476 Write leveling : PASS
3681 11:36:30.508628 RX DQS gating : PASS
3682 11:36:30.508702 RX DQ/DQS(RDDQC) : PASS
3683 11:36:30.511997 TX DQ/DQS : PASS
3684 11:36:30.515331 RX DATLAT : PASS
3685 11:36:30.515404 RX DQ/DQS(Engine): PASS
3686 11:36:30.518555 TX OE : NO K
3687 11:36:30.518629 All Pass.
3688 11:36:30.518688
3689 11:36:30.521817 CH 1, Rank 0
3690 11:36:30.521890 SW Impedance : PASS
3691 11:36:30.525474 DUTY Scan : NO K
3692 11:36:30.528639 ZQ Calibration : PASS
3693 11:36:30.528714 Jitter Meter : NO K
3694 11:36:30.531806 CBT Training : PASS
3695 11:36:30.535335 Write leveling : PASS
3696 11:36:30.535409 RX DQS gating : PASS
3697 11:36:30.538322 RX DQ/DQS(RDDQC) : PASS
3698 11:36:30.538395 TX DQ/DQS : PASS
3699 11:36:30.541828 RX DATLAT : PASS
3700 11:36:30.545360 RX DQ/DQS(Engine): PASS
3701 11:36:30.545434 TX OE : NO K
3702 11:36:30.548777 All Pass.
3703 11:36:30.548850
3704 11:36:30.548908 CH 1, Rank 1
3705 11:36:30.551780 SW Impedance : PASS
3706 11:36:30.551854 DUTY Scan : NO K
3707 11:36:30.554852 ZQ Calibration : PASS
3708 11:36:30.558411 Jitter Meter : NO K
3709 11:36:30.558485 CBT Training : PASS
3710 11:36:30.561925 Write leveling : PASS
3711 11:36:30.565151 RX DQS gating : PASS
3712 11:36:30.565225 RX DQ/DQS(RDDQC) : PASS
3713 11:36:30.568407 TX DQ/DQS : PASS
3714 11:36:30.571463 RX DATLAT : PASS
3715 11:36:30.571537 RX DQ/DQS(Engine): PASS
3716 11:36:30.574890 TX OE : NO K
3717 11:36:30.574965 All Pass.
3718 11:36:30.575022
3719 11:36:30.578912 DramC Write-DBI off
3720 11:36:30.581695 PER_BANK_REFRESH: Hybrid Mode
3721 11:36:30.581769 TX_TRACKING: ON
3722 11:36:30.591650 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 11:36:30.595023 [FAST_K] Save calibration result to emmc
3724 11:36:30.598225 dramc_set_vcore_voltage set vcore to 650000
3725 11:36:30.601459 Read voltage for 600, 5
3726 11:36:30.601533 Vio18 = 0
3727 11:36:30.601591 Vcore = 650000
3728 11:36:30.605434 Vdram = 0
3729 11:36:30.605508 Vddq = 0
3730 11:36:30.605566 Vmddr = 0
3731 11:36:30.611786 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 11:36:30.614946 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 11:36:30.618245 MEM_TYPE=3, freq_sel=19
3734 11:36:30.621730 sv_algorithm_assistance_LP4_1600
3735 11:36:30.624873 ============ PULL DRAM RESETB DOWN ============
3736 11:36:30.628095 ========== PULL DRAM RESETB DOWN end =========
3737 11:36:30.634816 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 11:36:30.638160 ===================================
3739 11:36:30.638226 LPDDR4 DRAM CONFIGURATION
3740 11:36:30.641556 ===================================
3741 11:36:30.644820 EX_ROW_EN[0] = 0x0
3742 11:36:30.648277 EX_ROW_EN[1] = 0x0
3743 11:36:30.648336 LP4Y_EN = 0x0
3744 11:36:30.651293 WORK_FSP = 0x0
3745 11:36:30.651354 WL = 0x2
3746 11:36:30.655003 RL = 0x2
3747 11:36:30.655094 BL = 0x2
3748 11:36:30.657861 RPST = 0x0
3749 11:36:30.657921 RD_PRE = 0x0
3750 11:36:30.661287 WR_PRE = 0x1
3751 11:36:30.661349 WR_PST = 0x0
3752 11:36:30.664724 DBI_WR = 0x0
3753 11:36:30.664784 DBI_RD = 0x0
3754 11:36:30.668313 OTF = 0x1
3755 11:36:30.671292 ===================================
3756 11:36:30.674942 ===================================
3757 11:36:30.675006 ANA top config
3758 11:36:30.677748 ===================================
3759 11:36:30.681262 DLL_ASYNC_EN = 0
3760 11:36:30.684598 ALL_SLAVE_EN = 1
3761 11:36:30.688148 NEW_RANK_MODE = 1
3762 11:36:30.688213 DLL_IDLE_MODE = 1
3763 11:36:30.692285 LP45_APHY_COMB_EN = 1
3764 11:36:30.694589 TX_ODT_DIS = 1
3765 11:36:30.698096 NEW_8X_MODE = 1
3766 11:36:30.701131 ===================================
3767 11:36:30.704456 ===================================
3768 11:36:30.707560 data_rate = 1200
3769 11:36:30.707630 CKR = 1
3770 11:36:30.710963 DQ_P2S_RATIO = 8
3771 11:36:30.714873 ===================================
3772 11:36:30.718049 CA_P2S_RATIO = 8
3773 11:36:30.721224 DQ_CA_OPEN = 0
3774 11:36:30.724540 DQ_SEMI_OPEN = 0
3775 11:36:30.727849 CA_SEMI_OPEN = 0
3776 11:36:30.727927 CA_FULL_RATE = 0
3777 11:36:30.731150 DQ_CKDIV4_EN = 1
3778 11:36:30.734463 CA_CKDIV4_EN = 1
3779 11:36:30.738165 CA_PREDIV_EN = 0
3780 11:36:30.741431 PH8_DLY = 0
3781 11:36:30.741506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 11:36:30.744494 DQ_AAMCK_DIV = 4
3783 11:36:30.747935 CA_AAMCK_DIV = 4
3784 11:36:30.751239 CA_ADMCK_DIV = 4
3785 11:36:30.754526 DQ_TRACK_CA_EN = 0
3786 11:36:30.757905 CA_PICK = 600
3787 11:36:30.761323 CA_MCKIO = 600
3788 11:36:30.761397 MCKIO_SEMI = 0
3789 11:36:30.765057 PLL_FREQ = 2288
3790 11:36:30.768259 DQ_UI_PI_RATIO = 32
3791 11:36:30.771682 CA_UI_PI_RATIO = 0
3792 11:36:30.774746 ===================================
3793 11:36:30.778471 ===================================
3794 11:36:30.781362 memory_type:LPDDR4
3795 11:36:30.781481 GP_NUM : 10
3796 11:36:30.784779 SRAM_EN : 1
3797 11:36:30.784853 MD32_EN : 0
3798 11:36:30.787724 ===================================
3799 11:36:30.791460 [ANA_INIT] >>>>>>>>>>>>>>
3800 11:36:30.794296 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 11:36:30.798068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 11:36:30.801338 ===================================
3803 11:36:30.804897 data_rate = 1200,PCW = 0X5800
3804 11:36:30.807624 ===================================
3805 11:36:30.811185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 11:36:30.817792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 11:36:30.821354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 11:36:30.827712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 11:36:30.831225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 11:36:30.834425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 11:36:30.834503 [ANA_INIT] flow start
3812 11:36:30.837853 [ANA_INIT] PLL >>>>>>>>
3813 11:36:30.840904 [ANA_INIT] PLL <<<<<<<<
3814 11:36:30.840978 [ANA_INIT] MIDPI >>>>>>>>
3815 11:36:30.844437 [ANA_INIT] MIDPI <<<<<<<<
3816 11:36:30.847687 [ANA_INIT] DLL >>>>>>>>
3817 11:36:30.847765 [ANA_INIT] flow end
3818 11:36:30.854247 ============ LP4 DIFF to SE enter ============
3819 11:36:30.857551 ============ LP4 DIFF to SE exit ============
3820 11:36:30.860945 [ANA_INIT] <<<<<<<<<<<<<
3821 11:36:30.864138 [Flow] Enable top DCM control >>>>>
3822 11:36:30.864213 [Flow] Enable top DCM control <<<<<
3823 11:36:30.868018 Enable DLL master slave shuffle
3824 11:36:30.874687 ==============================================================
3825 11:36:30.878000 Gating Mode config
3826 11:36:30.880657 ==============================================================
3827 11:36:30.884322 Config description:
3828 11:36:30.894657 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 11:36:30.901129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 11:36:30.904444 SELPH_MODE 0: By rank 1: By Phase
3831 11:36:30.911086 ==============================================================
3832 11:36:30.914643 GAT_TRACK_EN = 1
3833 11:36:30.917949 RX_GATING_MODE = 2
3834 11:36:30.921280 RX_GATING_TRACK_MODE = 2
3835 11:36:30.921354 SELPH_MODE = 1
3836 11:36:30.924367 PICG_EARLY_EN = 1
3837 11:36:30.927567 VALID_LAT_VALUE = 1
3838 11:36:30.934327 ==============================================================
3839 11:36:30.937769 Enter into Gating configuration >>>>
3840 11:36:30.941067 Exit from Gating configuration <<<<
3841 11:36:30.944285 Enter into DVFS_PRE_config >>>>>
3842 11:36:30.954167 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 11:36:30.957611 Exit from DVFS_PRE_config <<<<<
3844 11:36:30.960960 Enter into PICG configuration >>>>
3845 11:36:30.964419 Exit from PICG configuration <<<<
3846 11:36:30.967565 [RX_INPUT] configuration >>>>>
3847 11:36:30.970927 [RX_INPUT] configuration <<<<<
3848 11:36:30.974036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 11:36:30.980597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 11:36:30.987324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 11:36:30.993875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 11:36:31.000235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 11:36:31.003568 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 11:36:31.010744 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 11:36:31.013974 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 11:36:31.017007 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 11:36:31.020480 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 11:36:31.023796 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 11:36:31.030497 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 11:36:31.033918 ===================================
3861 11:36:31.036851 LPDDR4 DRAM CONFIGURATION
3862 11:36:31.040189 ===================================
3863 11:36:31.040265 EX_ROW_EN[0] = 0x0
3864 11:36:31.044005 EX_ROW_EN[1] = 0x0
3865 11:36:31.044081 LP4Y_EN = 0x0
3866 11:36:31.047296 WORK_FSP = 0x0
3867 11:36:31.047371 WL = 0x2
3868 11:36:31.050436 RL = 0x2
3869 11:36:31.050510 BL = 0x2
3870 11:36:31.053698 RPST = 0x0
3871 11:36:31.053772 RD_PRE = 0x0
3872 11:36:31.057240 WR_PRE = 0x1
3873 11:36:31.057315 WR_PST = 0x0
3874 11:36:31.060224 DBI_WR = 0x0
3875 11:36:31.060298 DBI_RD = 0x0
3876 11:36:31.063993 OTF = 0x1
3877 11:36:31.066888 ===================================
3878 11:36:31.070304 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 11:36:31.073703 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 11:36:31.079968 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 11:36:31.083728 ===================================
3882 11:36:31.083821 LPDDR4 DRAM CONFIGURATION
3883 11:36:31.086942 ===================================
3884 11:36:31.089977 EX_ROW_EN[0] = 0x10
3885 11:36:31.093166 EX_ROW_EN[1] = 0x0
3886 11:36:31.093238 LP4Y_EN = 0x0
3887 11:36:31.096924 WORK_FSP = 0x0
3888 11:36:31.096993 WL = 0x2
3889 11:36:31.100185 RL = 0x2
3890 11:36:31.100252 BL = 0x2
3891 11:36:31.103431 RPST = 0x0
3892 11:36:31.103507 RD_PRE = 0x0
3893 11:36:31.106826 WR_PRE = 0x1
3894 11:36:31.106900 WR_PST = 0x0
3895 11:36:31.110185 DBI_WR = 0x0
3896 11:36:31.110259 DBI_RD = 0x0
3897 11:36:31.113373 OTF = 0x1
3898 11:36:31.116604 ===================================
3899 11:36:31.123785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 11:36:31.126867 nWR fixed to 30
3901 11:36:31.126959 [ModeRegInit_LP4] CH0 RK0
3902 11:36:31.129827 [ModeRegInit_LP4] CH0 RK1
3903 11:36:31.133639 [ModeRegInit_LP4] CH1 RK0
3904 11:36:31.137071 [ModeRegInit_LP4] CH1 RK1
3905 11:36:31.137146 match AC timing 17
3906 11:36:31.143279 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 11:36:31.146854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 11:36:31.150286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 11:36:31.156569 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 11:36:31.160563 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 11:36:31.160637 ==
3912 11:36:31.163325 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 11:36:31.167322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 11:36:31.167401 ==
3915 11:36:31.173459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 11:36:31.180023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3917 11:36:31.183472 [CA 0] Center 35 (5~66) winsize 62
3918 11:36:31.186475 [CA 1] Center 35 (5~66) winsize 62
3919 11:36:31.189814 [CA 2] Center 34 (3~65) winsize 63
3920 11:36:31.193476 [CA 3] Center 33 (2~64) winsize 63
3921 11:36:31.196526 [CA 4] Center 33 (2~64) winsize 63
3922 11:36:31.199604 [CA 5] Center 32 (2~62) winsize 61
3923 11:36:31.199672
3924 11:36:31.203512 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3925 11:36:31.203579
3926 11:36:31.206869 [CATrainingPosCal] consider 1 rank data
3927 11:36:31.209978 u2DelayCellTimex100 = 270/100 ps
3928 11:36:31.213041 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3929 11:36:31.216815 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3930 11:36:31.220111 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3931 11:36:31.223409 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3932 11:36:31.226717 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3933 11:36:31.229961 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3934 11:36:31.230047
3935 11:36:31.236591 CA PerBit enable=1, Macro0, CA PI delay=32
3936 11:36:31.236667
3937 11:36:31.236726 [CBTSetCACLKResult] CA Dly = 32
3938 11:36:31.239900 CS Dly: 4 (0~35)
3939 11:36:31.239976 ==
3940 11:36:31.243089 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 11:36:31.246317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 11:36:31.246394 ==
3943 11:36:31.252983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 11:36:31.259978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 11:36:31.262930 [CA 0] Center 35 (5~66) winsize 62
3946 11:36:31.266227 [CA 1] Center 35 (5~66) winsize 62
3947 11:36:31.269738 [CA 2] Center 34 (3~65) winsize 63
3948 11:36:31.273013 [CA 3] Center 33 (3~64) winsize 62
3949 11:36:31.275985 [CA 4] Center 33 (2~64) winsize 63
3950 11:36:31.279643 [CA 5] Center 32 (2~63) winsize 62
3951 11:36:31.279720
3952 11:36:31.282614 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 11:36:31.282691
3954 11:36:31.286441 [CATrainingPosCal] consider 2 rank data
3955 11:36:31.289414 u2DelayCellTimex100 = 270/100 ps
3956 11:36:31.292682 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3957 11:36:31.296413 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3958 11:36:31.299571 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3959 11:36:31.302908 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3960 11:36:31.306217 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3961 11:36:31.312398 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3962 11:36:31.312472
3963 11:36:31.315738 CA PerBit enable=1, Macro0, CA PI delay=32
3964 11:36:31.315812
3965 11:36:31.319260 [CBTSetCACLKResult] CA Dly = 32
3966 11:36:31.319334 CS Dly: 4 (0~36)
3967 11:36:31.319394
3968 11:36:31.322321 ----->DramcWriteLeveling(PI) begin...
3969 11:36:31.322396 ==
3970 11:36:31.326215 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 11:36:31.328978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 11:36:31.332820 ==
3973 11:36:31.335568 Write leveling (Byte 0): 34 => 34
3974 11:36:31.335632 Write leveling (Byte 1): 30 => 30
3975 11:36:31.338859 DramcWriteLeveling(PI) end<-----
3976 11:36:31.338926
3977 11:36:31.338980 ==
3978 11:36:31.342478 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 11:36:31.348870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 11:36:31.348944 ==
3981 11:36:31.352718 [Gating] SW mode calibration
3982 11:36:31.358984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 11:36:31.362184 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 11:36:31.369220 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 11:36:31.372458 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 11:36:31.375857 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 11:36:31.379159 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
3988 11:36:31.385943 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3989 11:36:31.388940 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 11:36:31.392497 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 11:36:31.399024 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:36:31.402391 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:36:31.405577 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:36:31.412119 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:36:31.415747 0 10 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
3996 11:36:31.418755 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
3997 11:36:31.425525 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:36:31.429319 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:36:31.432440 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:36:31.438967 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:36:31.442742 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:36:31.445966 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:36:31.452144 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4004 11:36:31.455807 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4005 11:36:31.459079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:36:31.465848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:36:31.468931 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:36:31.472374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:36:31.478739 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:36:31.482609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:36:31.485687 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:36:31.489021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:36:31.495872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:36:31.499167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:36:31.502182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:36:31.509065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:36:31.512419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:36:31.515381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:36:31.522766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4020 11:36:31.525368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 11:36:31.528922 Total UI for P1: 0, mck2ui 16
4022 11:36:31.532204 best dqsien dly found for B0: ( 0, 13, 12)
4023 11:36:31.535613 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 11:36:31.538833 Total UI for P1: 0, mck2ui 16
4025 11:36:31.542147 best dqsien dly found for B1: ( 0, 13, 16)
4026 11:36:31.545313 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4027 11:36:31.548616 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 11:36:31.548713
4029 11:36:31.555388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4030 11:36:31.558749 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 11:36:31.561897 [Gating] SW calibration Done
4032 11:36:31.561982 ==
4033 11:36:31.565539 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 11:36:31.568888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 11:36:31.568962 ==
4036 11:36:31.569018 RX Vref Scan: 0
4037 11:36:31.569070
4038 11:36:31.572096 RX Vref 0 -> 0, step: 1
4039 11:36:31.572159
4040 11:36:31.575338 RX Delay -230 -> 252, step: 16
4041 11:36:31.578492 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4042 11:36:31.581826 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4043 11:36:31.588517 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4044 11:36:31.592221 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4045 11:36:31.594977 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4046 11:36:31.598963 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4047 11:36:31.605478 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4048 11:36:31.608725 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4049 11:36:31.612421 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4050 11:36:31.615472 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4051 11:36:31.618781 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4052 11:36:31.625191 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4053 11:36:31.628440 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4054 11:36:31.631754 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4055 11:36:31.635007 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4056 11:36:31.641967 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4057 11:36:31.642103 ==
4058 11:36:31.645664 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 11:36:31.648496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 11:36:31.648595 ==
4061 11:36:31.648681 DQS Delay:
4062 11:36:31.651900 DQS0 = 0, DQS1 = 0
4063 11:36:31.651974 DQM Delay:
4064 11:36:31.655173 DQM0 = 50, DQM1 = 45
4065 11:36:31.655248 DQ Delay:
4066 11:36:31.658623 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4067 11:36:31.662377 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =65
4068 11:36:31.665230 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4069 11:36:31.668799 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4070 11:36:31.668873
4071 11:36:31.668930
4072 11:36:31.668983 ==
4073 11:36:31.672002 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 11:36:31.675443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 11:36:31.675519 ==
4076 11:36:31.675576
4077 11:36:31.678692
4078 11:36:31.678766 TX Vref Scan disable
4079 11:36:31.681922 == TX Byte 0 ==
4080 11:36:31.685195 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4081 11:36:31.688656 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4082 11:36:31.692013 == TX Byte 1 ==
4083 11:36:31.695407 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4084 11:36:31.698499 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4085 11:36:31.698577 ==
4086 11:36:31.701993 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 11:36:31.708632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 11:36:31.708706 ==
4089 11:36:31.708763
4090 11:36:31.708816
4091 11:36:31.711830 TX Vref Scan disable
4092 11:36:31.711905 == TX Byte 0 ==
4093 11:36:31.718299 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4094 11:36:31.721781 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4095 11:36:31.721855 == TX Byte 1 ==
4096 11:36:31.728317 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4097 11:36:31.731651 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4098 11:36:31.731726
4099 11:36:31.731784 [DATLAT]
4100 11:36:31.734849 Freq=600, CH0 RK0
4101 11:36:31.734924
4102 11:36:31.734981 DATLAT Default: 0x9
4103 11:36:31.738361 0, 0xFFFF, sum = 0
4104 11:36:31.738436 1, 0xFFFF, sum = 0
4105 11:36:31.741420 2, 0xFFFF, sum = 0
4106 11:36:31.741495 3, 0xFFFF, sum = 0
4107 11:36:31.744724 4, 0xFFFF, sum = 0
4108 11:36:31.744799 5, 0xFFFF, sum = 0
4109 11:36:31.748365 6, 0xFFFF, sum = 0
4110 11:36:31.751611 7, 0xFFFF, sum = 0
4111 11:36:31.751686 8, 0x0, sum = 1
4112 11:36:31.751744 9, 0x0, sum = 2
4113 11:36:31.755014 10, 0x0, sum = 3
4114 11:36:31.755089 11, 0x0, sum = 4
4115 11:36:31.758190 best_step = 9
4116 11:36:31.758264
4117 11:36:31.758322 ==
4118 11:36:31.761794 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 11:36:31.764611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 11:36:31.764686 ==
4121 11:36:31.768238 RX Vref Scan: 1
4122 11:36:31.768312
4123 11:36:31.768370 RX Vref 0 -> 0, step: 1
4124 11:36:31.768422
4125 11:36:31.771208 RX Delay -163 -> 252, step: 8
4126 11:36:31.771282
4127 11:36:31.775186 Set Vref, RX VrefLevel [Byte0]: 54
4128 11:36:31.777770 [Byte1]: 48
4129 11:36:31.781588
4130 11:36:31.781662 Final RX Vref Byte 0 = 54 to rank0
4131 11:36:31.785446 Final RX Vref Byte 1 = 48 to rank0
4132 11:36:31.788503 Final RX Vref Byte 0 = 54 to rank1
4133 11:36:31.791411 Final RX Vref Byte 1 = 48 to rank1==
4134 11:36:31.795021 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 11:36:31.801611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:36:31.801686 ==
4137 11:36:31.801743 DQS Delay:
4138 11:36:31.804872 DQS0 = 0, DQS1 = 0
4139 11:36:31.804946 DQM Delay:
4140 11:36:31.805003 DQM0 = 52, DQM1 = 46
4141 11:36:31.808354 DQ Delay:
4142 11:36:31.811720 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4143 11:36:31.815027 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4144 11:36:31.818291 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4145 11:36:31.821705 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4146 11:36:31.821778
4147 11:36:31.821836
4148 11:36:31.827780 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4149 11:36:31.831197 CH0 RK0: MR19=808, MR18=7164
4150 11:36:31.837736 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4151 11:36:31.837811
4152 11:36:31.841654 ----->DramcWriteLeveling(PI) begin...
4153 11:36:31.841730 ==
4154 11:36:31.844831 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 11:36:31.848239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 11:36:31.848315 ==
4157 11:36:31.851205 Write leveling (Byte 0): 33 => 33
4158 11:36:31.854521 Write leveling (Byte 1): 30 => 30
4159 11:36:31.857682 DramcWriteLeveling(PI) end<-----
4160 11:36:31.857756
4161 11:36:31.857814 ==
4162 11:36:31.861040 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 11:36:31.864487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 11:36:31.864561 ==
4165 11:36:31.867947 [Gating] SW mode calibration
4166 11:36:31.875096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 11:36:31.881349 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 11:36:31.884376 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 11:36:31.890851 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 11:36:31.894515 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 11:36:31.897525 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4172 11:36:31.904317 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4173 11:36:31.907622 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:36:31.911366 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:36:31.917928 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:36:31.921264 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:36:31.924483 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 11:36:31.927987 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 11:36:31.934553 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4180 11:36:31.937561 0 10 16 | B1->B0 | 4040 4040 | 1 1 | (0 0) (0 0)
4181 11:36:31.941087 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:36:31.947676 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:36:31.950955 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:36:31.957189 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:36:31.960488 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:36:31.963898 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 11:36:31.967106 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4188 11:36:31.973629 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4189 11:36:31.976942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:36:31.980717 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:36:31.987283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:36:31.990588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:36:31.993949 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:36:32.000562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:36:32.003717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:36:32.007357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:36:32.013518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:36:32.017082 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:36:32.020011 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:36:32.026795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:36:32.030423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:36:32.033682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:36:32.039894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:36:32.043392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 11:36:32.046906 Total UI for P1: 0, mck2ui 16
4206 11:36:32.050345 best dqsien dly found for B0: ( 0, 13, 14)
4207 11:36:32.053437 Total UI for P1: 0, mck2ui 16
4208 11:36:32.056910 best dqsien dly found for B1: ( 0, 13, 14)
4209 11:36:32.059813 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4210 11:36:32.063111 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4211 11:36:32.063173
4212 11:36:32.066994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4213 11:36:32.070117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4214 11:36:32.073572 [Gating] SW calibration Done
4215 11:36:32.073631 ==
4216 11:36:32.076822 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 11:36:32.083214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 11:36:32.083282 ==
4219 11:36:32.083347 RX Vref Scan: 0
4220 11:36:32.083399
4221 11:36:32.086473 RX Vref 0 -> 0, step: 1
4222 11:36:32.086531
4223 11:36:32.090428 RX Delay -230 -> 252, step: 16
4224 11:36:32.093557 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4225 11:36:32.096950 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4226 11:36:32.100085 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4227 11:36:32.106891 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4228 11:36:32.110161 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4229 11:36:32.113424 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4230 11:36:32.116834 iDelay=218, Bit 6, Center 65 (-70 ~ 201) 272
4231 11:36:32.120128 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4232 11:36:32.126717 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4233 11:36:32.129870 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4234 11:36:32.133448 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4235 11:36:32.136763 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4236 11:36:32.140113 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4237 11:36:32.146528 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4238 11:36:32.149812 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4239 11:36:32.153037 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4240 11:36:32.153102 ==
4241 11:36:32.156880 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 11:36:32.163834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 11:36:32.163905 ==
4244 11:36:32.163961 DQS Delay:
4245 11:36:32.164013 DQS0 = 0, DQS1 = 0
4246 11:36:32.166881 DQM Delay:
4247 11:36:32.166942 DQM0 = 55, DQM1 = 45
4248 11:36:32.170084 DQ Delay:
4249 11:36:32.173588 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4250 11:36:32.173657 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =73
4251 11:36:32.176531 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =41
4252 11:36:32.179758 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4253 11:36:32.183271
4254 11:36:32.183357
4255 11:36:32.183435 ==
4256 11:36:32.186384 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 11:36:32.189738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 11:36:32.189837 ==
4259 11:36:32.189943
4260 11:36:32.190051
4261 11:36:32.193395 TX Vref Scan disable
4262 11:36:32.193467 == TX Byte 0 ==
4263 11:36:32.199732 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4264 11:36:32.203686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4265 11:36:32.203766 == TX Byte 1 ==
4266 11:36:32.209681 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4267 11:36:32.212953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4268 11:36:32.213028 ==
4269 11:36:32.216271 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 11:36:32.220371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 11:36:32.220447 ==
4272 11:36:32.220508
4273 11:36:32.220565
4274 11:36:32.222894 TX Vref Scan disable
4275 11:36:32.226145 == TX Byte 0 ==
4276 11:36:32.229538 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4277 11:36:32.236252 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4278 11:36:32.236329 == TX Byte 1 ==
4279 11:36:32.239616 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4280 11:36:32.246139 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4281 11:36:32.246215
4282 11:36:32.246273 [DATLAT]
4283 11:36:32.246327 Freq=600, CH0 RK1
4284 11:36:32.246379
4285 11:36:32.249907 DATLAT Default: 0x9
4286 11:36:32.249981 0, 0xFFFF, sum = 0
4287 11:36:32.252511 1, 0xFFFF, sum = 0
4288 11:36:32.252587 2, 0xFFFF, sum = 0
4289 11:36:32.256103 3, 0xFFFF, sum = 0
4290 11:36:32.259606 4, 0xFFFF, sum = 0
4291 11:36:32.259682 5, 0xFFFF, sum = 0
4292 11:36:32.262626 6, 0xFFFF, sum = 0
4293 11:36:32.262703 7, 0xFFFF, sum = 0
4294 11:36:32.266213 8, 0x0, sum = 1
4295 11:36:32.266289 9, 0x0, sum = 2
4296 11:36:32.266349 10, 0x0, sum = 3
4297 11:36:32.269571 11, 0x0, sum = 4
4298 11:36:32.269646 best_step = 9
4299 11:36:32.269704
4300 11:36:32.269758 ==
4301 11:36:32.272735 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 11:36:32.278965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 11:36:32.279040 ==
4304 11:36:32.279098 RX Vref Scan: 0
4305 11:36:32.279151
4306 11:36:32.283103 RX Vref 0 -> 0, step: 1
4307 11:36:32.283178
4308 11:36:32.285962 RX Delay -163 -> 252, step: 8
4309 11:36:32.289522 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4310 11:36:32.295988 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4311 11:36:32.298971 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4312 11:36:32.302444 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4313 11:36:32.305485 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4314 11:36:32.308898 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4315 11:36:32.315572 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4316 11:36:32.319361 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4317 11:36:32.322747 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4318 11:36:32.325929 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4319 11:36:32.328799 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4320 11:36:32.335993 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4321 11:36:32.339406 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4322 11:36:32.342471 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4323 11:36:32.345799 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4324 11:36:32.352438 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4325 11:36:32.352513 ==
4326 11:36:32.355583 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 11:36:32.358650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 11:36:32.358725 ==
4329 11:36:32.358784 DQS Delay:
4330 11:36:32.362039 DQS0 = 0, DQS1 = 0
4331 11:36:32.362128 DQM Delay:
4332 11:36:32.365289 DQM0 = 54, DQM1 = 46
4333 11:36:32.365365 DQ Delay:
4334 11:36:32.369126 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4335 11:36:32.372180 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4336 11:36:32.375296 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4337 11:36:32.378671 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4338 11:36:32.378744
4339 11:36:32.378802
4340 11:36:32.385680 [DQSOSCAuto] RK1, (LSB)MR18= 0x6929, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4341 11:36:32.388863 CH0 RK1: MR19=808, MR18=6929
4342 11:36:32.395307 CH0_RK1: MR19=0x808, MR18=0x6929, DQSOSC=390, MR23=63, INC=172, DEC=114
4343 11:36:32.398933 [RxdqsGatingPostProcess] freq 600
4344 11:36:32.405243 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4345 11:36:32.405318 Pre-setting of DQS Precalculation
4346 11:36:32.411891 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4347 11:36:32.411965 ==
4348 11:36:32.415202 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 11:36:32.418453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:36:32.418532 ==
4351 11:36:32.425617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 11:36:32.432006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4353 11:36:32.435104 [CA 0] Center 36 (5~67) winsize 63
4354 11:36:32.438709 [CA 1] Center 36 (6~67) winsize 62
4355 11:36:32.442254 [CA 2] Center 35 (4~66) winsize 63
4356 11:36:32.445101 [CA 3] Center 34 (4~65) winsize 62
4357 11:36:32.448431 [CA 4] Center 34 (4~65) winsize 62
4358 11:36:32.451833 [CA 5] Center 34 (4~65) winsize 62
4359 11:36:32.451907
4360 11:36:32.455109 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4361 11:36:32.455183
4362 11:36:32.458332 [CATrainingPosCal] consider 1 rank data
4363 11:36:32.462085 u2DelayCellTimex100 = 270/100 ps
4364 11:36:32.465510 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4365 11:36:32.468819 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4366 11:36:32.472040 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4367 11:36:32.475345 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4368 11:36:32.478617 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 11:36:32.482154 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 11:36:32.482251
4371 11:36:32.489008 CA PerBit enable=1, Macro0, CA PI delay=34
4372 11:36:32.489083
4373 11:36:32.491591 [CBTSetCACLKResult] CA Dly = 34
4374 11:36:32.491665 CS Dly: 5 (0~36)
4375 11:36:32.491722 ==
4376 11:36:32.495057 Dram Type= 6, Freq= 0, CH_1, rank 1
4377 11:36:32.498447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:36:32.498522 ==
4379 11:36:32.505325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 11:36:32.511674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 11:36:32.515055 [CA 0] Center 36 (5~67) winsize 63
4382 11:36:32.518247 [CA 1] Center 36 (5~67) winsize 63
4383 11:36:32.521648 [CA 2] Center 35 (4~66) winsize 63
4384 11:36:32.524877 [CA 3] Center 35 (4~66) winsize 63
4385 11:36:32.528878 [CA 4] Center 35 (4~66) winsize 63
4386 11:36:32.532420 [CA 5] Center 34 (3~65) winsize 63
4387 11:36:32.532496
4388 11:36:32.535596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 11:36:32.535694
4390 11:36:32.538760 [CATrainingPosCal] consider 2 rank data
4391 11:36:32.541646 u2DelayCellTimex100 = 270/100 ps
4392 11:36:32.545223 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4393 11:36:32.548426 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4394 11:36:32.551711 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4395 11:36:32.555376 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4396 11:36:32.558655 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 11:36:32.561601 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 11:36:32.565274
4399 11:36:32.568232 CA PerBit enable=1, Macro0, CA PI delay=34
4400 11:36:32.568307
4401 11:36:32.571576 [CBTSetCACLKResult] CA Dly = 34
4402 11:36:32.571651 CS Dly: 6 (0~38)
4403 11:36:32.571709
4404 11:36:32.575138 ----->DramcWriteLeveling(PI) begin...
4405 11:36:32.575213 ==
4406 11:36:32.578777 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 11:36:32.581957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 11:36:32.585176 ==
4409 11:36:32.585250 Write leveling (Byte 0): 31 => 31
4410 11:36:32.588207 Write leveling (Byte 1): 31 => 31
4411 11:36:32.591317 DramcWriteLeveling(PI) end<-----
4412 11:36:32.591392
4413 11:36:32.591450 ==
4414 11:36:32.594968 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 11:36:32.601470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 11:36:32.601545 ==
4417 11:36:32.604717 [Gating] SW mode calibration
4418 11:36:32.611451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4419 11:36:32.614673 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4420 11:36:32.621580 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 11:36:32.625151 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 11:36:32.627875 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4423 11:36:32.635009 0 9 12 | B1->B0 | 2e2e 2d2d | 1 1 | (1 0) (1 0)
4424 11:36:32.638212 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4425 11:36:32.641585 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:36:32.644966 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:36:32.651122 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 11:36:32.654656 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 11:36:32.657636 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 11:36:32.664774 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4431 11:36:32.668090 0 10 12 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
4432 11:36:32.671425 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:36:32.677676 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:36:32.681421 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:36:32.684311 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:36:32.691041 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:36:32.694685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:36:32.698154 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:36:32.704417 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4440 11:36:32.707850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:36:32.711633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:36:32.717791 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:36:32.721291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:36:32.724431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:36:32.731561 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:36:32.734681 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:36:32.737606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:36:32.744343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:36:32.747780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:36:32.751651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:36:32.754286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:36:32.761171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:36:32.764734 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:36:32.767647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4455 11:36:32.774625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4456 11:36:32.774700 Total UI for P1: 0, mck2ui 16
4457 11:36:32.781189 best dqsien dly found for B0: ( 0, 13, 8)
4458 11:36:32.785291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 11:36:32.788645 Total UI for P1: 0, mck2ui 16
4460 11:36:32.791149 best dqsien dly found for B1: ( 0, 13, 12)
4461 11:36:32.794802 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4462 11:36:32.798226 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4463 11:36:32.798301
4464 11:36:32.801476 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4465 11:36:32.804723 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4466 11:36:32.808260 [Gating] SW calibration Done
4467 11:36:32.808335 ==
4468 11:36:32.811738 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 11:36:32.814532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 11:36:32.817861 ==
4471 11:36:32.817958 RX Vref Scan: 0
4472 11:36:32.818067
4473 11:36:32.821188 RX Vref 0 -> 0, step: 1
4474 11:36:32.821263
4475 11:36:32.824783 RX Delay -230 -> 252, step: 16
4476 11:36:32.827772 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4477 11:36:32.831005 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4478 11:36:32.834755 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4479 11:36:32.841026 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4480 11:36:32.844348 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4481 11:36:32.847389 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4482 11:36:32.851240 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4483 11:36:32.854575 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4484 11:36:32.861168 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4485 11:36:32.864598 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4486 11:36:32.867832 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4487 11:36:32.871056 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4488 11:36:32.877591 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4489 11:36:32.881137 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4490 11:36:32.884617 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4491 11:36:32.887260 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4492 11:36:32.887335 ==
4493 11:36:32.890558 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 11:36:32.897586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 11:36:32.897661 ==
4496 11:36:32.897719 DQS Delay:
4497 11:36:32.900690 DQS0 = 0, DQS1 = 0
4498 11:36:32.900765 DQM Delay:
4499 11:36:32.900823 DQM0 = 52, DQM1 = 49
4500 11:36:32.903967 DQ Delay:
4501 11:36:32.907179 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4502 11:36:32.910561 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4503 11:36:32.914069 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4504 11:36:32.917185 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4505 11:36:32.917259
4506 11:36:32.917316
4507 11:36:32.917370 ==
4508 11:36:32.920695 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 11:36:32.923851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 11:36:32.923926 ==
4511 11:36:32.923984
4512 11:36:32.924037
4513 11:36:32.927277 TX Vref Scan disable
4514 11:36:32.930581 == TX Byte 0 ==
4515 11:36:32.933814 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 11:36:32.937167 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 11:36:32.940848 == TX Byte 1 ==
4518 11:36:32.944100 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 11:36:32.947280 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 11:36:32.947354 ==
4521 11:36:32.950724 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 11:36:32.953868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 11:36:32.957769 ==
4524 11:36:32.957844
4525 11:36:32.957902
4526 11:36:32.957956 TX Vref Scan disable
4527 11:36:32.960908 == TX Byte 0 ==
4528 11:36:32.964182 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 11:36:32.967579 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 11:36:32.970892 == TX Byte 1 ==
4531 11:36:32.974440 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4532 11:36:32.980783 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4533 11:36:32.980859
4534 11:36:32.980918 [DATLAT]
4535 11:36:32.980971 Freq=600, CH1 RK0
4536 11:36:32.981024
4537 11:36:32.983846 DATLAT Default: 0x9
4538 11:36:32.983920 0, 0xFFFF, sum = 0
4539 11:36:32.987488 1, 0xFFFF, sum = 0
4540 11:36:32.987564 2, 0xFFFF, sum = 0
4541 11:36:32.990547 3, 0xFFFF, sum = 0
4542 11:36:32.993963 4, 0xFFFF, sum = 0
4543 11:36:32.994046 5, 0xFFFF, sum = 0
4544 11:36:32.997266 6, 0xFFFF, sum = 0
4545 11:36:32.997342 7, 0xFFFF, sum = 0
4546 11:36:33.000615 8, 0x0, sum = 1
4547 11:36:33.000692 9, 0x0, sum = 2
4548 11:36:33.000751 10, 0x0, sum = 3
4549 11:36:33.004186 11, 0x0, sum = 4
4550 11:36:33.004262 best_step = 9
4551 11:36:33.004320
4552 11:36:33.004375 ==
4553 11:36:33.007507 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 11:36:33.014390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 11:36:33.014466 ==
4556 11:36:33.014524 RX Vref Scan: 1
4557 11:36:33.014579
4558 11:36:33.017473 RX Vref 0 -> 0, step: 1
4559 11:36:33.017548
4560 11:36:33.020595 RX Delay -147 -> 252, step: 8
4561 11:36:33.020670
4562 11:36:33.023938 Set Vref, RX VrefLevel [Byte0]: 55
4563 11:36:33.027118 [Byte1]: 52
4564 11:36:33.027193
4565 11:36:33.030423 Final RX Vref Byte 0 = 55 to rank0
4566 11:36:33.033670 Final RX Vref Byte 1 = 52 to rank0
4567 11:36:33.037615 Final RX Vref Byte 0 = 55 to rank1
4568 11:36:33.041080 Final RX Vref Byte 1 = 52 to rank1==
4569 11:36:33.043556 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 11:36:33.047563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:36:33.047639 ==
4572 11:36:33.050750 DQS Delay:
4573 11:36:33.050825 DQS0 = 0, DQS1 = 0
4574 11:36:33.050882 DQM Delay:
4575 11:36:33.053726 DQM0 = 49, DQM1 = 45
4576 11:36:33.053800 DQ Delay:
4577 11:36:33.056997 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4578 11:36:33.060442 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4579 11:36:33.063662 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4580 11:36:33.066810 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4581 11:36:33.066891
4582 11:36:33.066955
4583 11:36:33.076851 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4584 11:36:33.080724 CH1 RK0: MR19=808, MR18=496E
4585 11:36:33.083875 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4586 11:36:33.083952
4587 11:36:33.086871 ----->DramcWriteLeveling(PI) begin...
4588 11:36:33.090338 ==
4589 11:36:33.093518 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 11:36:33.096873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 11:36:33.096949 ==
4592 11:36:33.099995 Write leveling (Byte 0): 31 => 31
4593 11:36:33.103536 Write leveling (Byte 1): 31 => 31
4594 11:36:33.106998 DramcWriteLeveling(PI) end<-----
4595 11:36:33.107073
4596 11:36:33.107131 ==
4597 11:36:33.110250 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 11:36:33.113713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 11:36:33.113789 ==
4600 11:36:33.116816 [Gating] SW mode calibration
4601 11:36:33.123853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4602 11:36:33.130218 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4603 11:36:33.133386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 11:36:33.136759 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 11:36:33.140673 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4606 11:36:33.147276 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
4607 11:36:33.149933 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:36:33.153163 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:36:33.159844 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:36:33.163264 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:36:33.166427 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 11:36:33.173834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 11:36:33.177123 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 11:36:33.180274 0 10 12 | B1->B0 | 3737 3535 | 1 0 | (0 0) (0 0)
4615 11:36:33.187135 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:36:33.190309 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:36:33.193218 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:36:33.200583 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:36:33.203141 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:36:33.206898 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 11:36:33.213491 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 11:36:33.216879 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4623 11:36:33.220114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4624 11:36:33.226683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:36:33.229915 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:36:33.232863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:36:33.239717 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:36:33.243115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:36:33.246235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:36:33.252873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:36:33.256818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:36:33.260013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:36:33.266409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:36:33.269760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:36:33.272917 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:36:33.276319 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:36:33.282849 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:36:33.286222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4639 11:36:33.289627 Total UI for P1: 0, mck2ui 16
4640 11:36:33.292998 best dqsien dly found for B1: ( 0, 13, 10)
4641 11:36:33.296181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 11:36:33.299258 Total UI for P1: 0, mck2ui 16
4643 11:36:33.303207 best dqsien dly found for B0: ( 0, 13, 12)
4644 11:36:33.306360 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4645 11:36:33.312743 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4646 11:36:33.312818
4647 11:36:33.315991 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4648 11:36:33.319455 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4649 11:36:33.322785 [Gating] SW calibration Done
4650 11:36:33.322860 ==
4651 11:36:33.325934 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 11:36:33.329803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 11:36:33.329878 ==
4654 11:36:33.333084 RX Vref Scan: 0
4655 11:36:33.333158
4656 11:36:33.333216 RX Vref 0 -> 0, step: 1
4657 11:36:33.333270
4658 11:36:33.335781 RX Delay -230 -> 252, step: 16
4659 11:36:33.339290 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4660 11:36:33.345943 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4661 11:36:33.349747 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4662 11:36:33.352692 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4663 11:36:33.355944 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4664 11:36:33.359212 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4665 11:36:33.365618 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4666 11:36:33.368898 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4667 11:36:33.372197 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4668 11:36:33.375529 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4669 11:36:33.382630 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4670 11:36:33.385881 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4671 11:36:33.389187 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4672 11:36:33.392413 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4673 11:36:33.398983 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4674 11:36:33.402467 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4675 11:36:33.402542 ==
4676 11:36:33.406199 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 11:36:33.409491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 11:36:33.409566 ==
4679 11:36:33.409625 DQS Delay:
4680 11:36:33.412468 DQS0 = 0, DQS1 = 0
4681 11:36:33.412543 DQM Delay:
4682 11:36:33.416097 DQM0 = 51, DQM1 = 50
4683 11:36:33.416171 DQ Delay:
4684 11:36:33.419383 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4685 11:36:33.422862 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4686 11:36:33.425547 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4687 11:36:33.428872 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4688 11:36:33.428946
4689 11:36:33.429004
4690 11:36:33.429056 ==
4691 11:36:33.432197 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 11:36:33.436089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 11:36:33.438867 ==
4694 11:36:33.438941
4695 11:36:33.438998
4696 11:36:33.439050 TX Vref Scan disable
4697 11:36:33.442828 == TX Byte 0 ==
4698 11:36:33.445967 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4699 11:36:33.449185 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4700 11:36:33.452249 == TX Byte 1 ==
4701 11:36:33.455839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4702 11:36:33.459368 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4703 11:36:33.462689 ==
4704 11:36:33.466044 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 11:36:33.468827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 11:36:33.468930 ==
4707 11:36:33.468988
4708 11:36:33.469041
4709 11:36:33.471981 TX Vref Scan disable
4710 11:36:33.472056 == TX Byte 0 ==
4711 11:36:33.478807 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4712 11:36:33.482464 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4713 11:36:33.482539 == TX Byte 1 ==
4714 11:36:33.489073 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 11:36:33.492431 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 11:36:33.492565
4717 11:36:33.492680 [DATLAT]
4718 11:36:33.495688 Freq=600, CH1 RK1
4719 11:36:33.495762
4720 11:36:33.495820 DATLAT Default: 0x9
4721 11:36:33.499003 0, 0xFFFF, sum = 0
4722 11:36:33.499079 1, 0xFFFF, sum = 0
4723 11:36:33.502474 2, 0xFFFF, sum = 0
4724 11:36:33.502549 3, 0xFFFF, sum = 0
4725 11:36:33.505578 4, 0xFFFF, sum = 0
4726 11:36:33.508601 5, 0xFFFF, sum = 0
4727 11:36:33.508677 6, 0xFFFF, sum = 0
4728 11:36:33.512446 7, 0xFFFF, sum = 0
4729 11:36:33.512545 8, 0x0, sum = 1
4730 11:36:33.512632 9, 0x0, sum = 2
4731 11:36:33.515627 10, 0x0, sum = 3
4732 11:36:33.515703 11, 0x0, sum = 4
4733 11:36:33.519029 best_step = 9
4734 11:36:33.519104
4735 11:36:33.519161 ==
4736 11:36:33.521939 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 11:36:33.525711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 11:36:33.525787 ==
4739 11:36:33.528679 RX Vref Scan: 0
4740 11:36:33.528759
4741 11:36:33.528817 RX Vref 0 -> 0, step: 1
4742 11:36:33.528870
4743 11:36:33.531956 RX Delay -163 -> 252, step: 8
4744 11:36:33.539273 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4745 11:36:33.542599 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4746 11:36:33.546081 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4747 11:36:33.549319 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4748 11:36:33.552656 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4749 11:36:33.559429 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4750 11:36:33.562524 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4751 11:36:33.566281 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4752 11:36:33.569410 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4753 11:36:33.572927 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4754 11:36:33.579525 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4755 11:36:33.582179 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4756 11:36:33.585954 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4757 11:36:33.589593 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4758 11:36:33.595581 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4759 11:36:33.599159 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4760 11:36:33.599263 ==
4761 11:36:33.602380 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 11:36:33.605869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 11:36:33.605944 ==
4764 11:36:33.609115 DQS Delay:
4765 11:36:33.609189 DQS0 = 0, DQS1 = 0
4766 11:36:33.609246 DQM Delay:
4767 11:36:33.612640 DQM0 = 49, DQM1 = 45
4768 11:36:33.612714 DQ Delay:
4769 11:36:33.615793 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4770 11:36:33.619055 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4771 11:36:33.622194 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4772 11:36:33.625917 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4773 11:36:33.625991
4774 11:36:33.626088
4775 11:36:33.635737 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4776 11:36:33.635813 CH1 RK1: MR19=808, MR18=6D24
4777 11:36:33.642283 CH1_RK1: MR19=0x808, MR18=0x6D24, DQSOSC=389, MR23=63, INC=173, DEC=115
4778 11:36:33.646139 [RxdqsGatingPostProcess] freq 600
4779 11:36:33.652408 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4780 11:36:33.655608 Pre-setting of DQS Precalculation
4781 11:36:33.658796 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4782 11:36:33.665739 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4783 11:36:33.675240 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4784 11:36:33.675337
4785 11:36:33.675422
4786 11:36:33.678786 [Calibration Summary] 1200 Mbps
4787 11:36:33.678877 CH 0, Rank 0
4788 11:36:33.682394 SW Impedance : PASS
4789 11:36:33.682489 DUTY Scan : NO K
4790 11:36:33.685389 ZQ Calibration : PASS
4791 11:36:33.685464 Jitter Meter : NO K
4792 11:36:33.688774 CBT Training : PASS
4793 11:36:33.691959 Write leveling : PASS
4794 11:36:33.692033 RX DQS gating : PASS
4795 11:36:33.695211 RX DQ/DQS(RDDQC) : PASS
4796 11:36:33.698869 TX DQ/DQS : PASS
4797 11:36:33.698968 RX DATLAT : PASS
4798 11:36:33.701765 RX DQ/DQS(Engine): PASS
4799 11:36:33.705820 TX OE : NO K
4800 11:36:33.705924 All Pass.
4801 11:36:33.706026
4802 11:36:33.706096 CH 0, Rank 1
4803 11:36:33.708442 SW Impedance : PASS
4804 11:36:33.711843 DUTY Scan : NO K
4805 11:36:33.711918 ZQ Calibration : PASS
4806 11:36:33.715067 Jitter Meter : NO K
4807 11:36:33.718479 CBT Training : PASS
4808 11:36:33.718561 Write leveling : PASS
4809 11:36:33.721676 RX DQS gating : PASS
4810 11:36:33.725060 RX DQ/DQS(RDDQC) : PASS
4811 11:36:33.725153 TX DQ/DQS : PASS
4812 11:36:33.728638 RX DATLAT : PASS
4813 11:36:33.728733 RX DQ/DQS(Engine): PASS
4814 11:36:33.731872 TX OE : NO K
4815 11:36:33.731946 All Pass.
4816 11:36:33.732004
4817 11:36:33.735237 CH 1, Rank 0
4818 11:36:33.735311 SW Impedance : PASS
4819 11:36:33.738732 DUTY Scan : NO K
4820 11:36:33.741953 ZQ Calibration : PASS
4821 11:36:33.742093 Jitter Meter : NO K
4822 11:36:33.745533 CBT Training : PASS
4823 11:36:33.748755 Write leveling : PASS
4824 11:36:33.748864 RX DQS gating : PASS
4825 11:36:33.752068 RX DQ/DQS(RDDQC) : PASS
4826 11:36:33.755206 TX DQ/DQS : PASS
4827 11:36:33.755280 RX DATLAT : PASS
4828 11:36:33.758569 RX DQ/DQS(Engine): PASS
4829 11:36:33.761676 TX OE : NO K
4830 11:36:33.761750 All Pass.
4831 11:36:33.761808
4832 11:36:33.761861 CH 1, Rank 1
4833 11:36:33.765437 SW Impedance : PASS
4834 11:36:33.768738 DUTY Scan : NO K
4835 11:36:33.768814 ZQ Calibration : PASS
4836 11:36:33.772023 Jitter Meter : NO K
4837 11:36:33.775277 CBT Training : PASS
4838 11:36:33.775352 Write leveling : PASS
4839 11:36:33.778559 RX DQS gating : PASS
4840 11:36:33.781830 RX DQ/DQS(RDDQC) : PASS
4841 11:36:33.781905 TX DQ/DQS : PASS
4842 11:36:33.785140 RX DATLAT : PASS
4843 11:36:33.785223 RX DQ/DQS(Engine): PASS
4844 11:36:33.788297 TX OE : NO K
4845 11:36:33.788371 All Pass.
4846 11:36:33.788429
4847 11:36:33.792074 DramC Write-DBI off
4848 11:36:33.795149 PER_BANK_REFRESH: Hybrid Mode
4849 11:36:33.795223 TX_TRACKING: ON
4850 11:36:33.804744 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4851 11:36:33.808371 [FAST_K] Save calibration result to emmc
4852 11:36:33.811851 dramc_set_vcore_voltage set vcore to 662500
4853 11:36:33.815101 Read voltage for 933, 3
4854 11:36:33.815176 Vio18 = 0
4855 11:36:33.815263 Vcore = 662500
4856 11:36:33.818405 Vdram = 0
4857 11:36:33.818478 Vddq = 0
4858 11:36:33.818536 Vmddr = 0
4859 11:36:33.824909 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4860 11:36:33.828255 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4861 11:36:33.831515 MEM_TYPE=3, freq_sel=17
4862 11:36:33.834715 sv_algorithm_assistance_LP4_1600
4863 11:36:33.838398 ============ PULL DRAM RESETB DOWN ============
4864 11:36:33.844883 ========== PULL DRAM RESETB DOWN end =========
4865 11:36:33.848440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 11:36:33.851434 ===================================
4867 11:36:33.854853 LPDDR4 DRAM CONFIGURATION
4868 11:36:33.858097 ===================================
4869 11:36:33.858177 EX_ROW_EN[0] = 0x0
4870 11:36:33.862071 EX_ROW_EN[1] = 0x0
4871 11:36:33.862146 LP4Y_EN = 0x0
4872 11:36:33.864769 WORK_FSP = 0x0
4873 11:36:33.864844 WL = 0x3
4874 11:36:33.868110 RL = 0x3
4875 11:36:33.868184 BL = 0x2
4876 11:36:33.871427 RPST = 0x0
4877 11:36:33.871501 RD_PRE = 0x0
4878 11:36:33.874710 WR_PRE = 0x1
4879 11:36:33.874785 WR_PST = 0x0
4880 11:36:33.878406 DBI_WR = 0x0
4881 11:36:33.881795 DBI_RD = 0x0
4882 11:36:33.881885 OTF = 0x1
4883 11:36:33.884841 ===================================
4884 11:36:33.888183 ===================================
4885 11:36:33.888300 ANA top config
4886 11:36:33.891497 ===================================
4887 11:36:33.894818 DLL_ASYNC_EN = 0
4888 11:36:33.898239 ALL_SLAVE_EN = 1
4889 11:36:33.901517 NEW_RANK_MODE = 1
4890 11:36:33.904534 DLL_IDLE_MODE = 1
4891 11:36:33.904649 LP45_APHY_COMB_EN = 1
4892 11:36:33.908379 TX_ODT_DIS = 1
4893 11:36:33.911398 NEW_8X_MODE = 1
4894 11:36:33.914768 ===================================
4895 11:36:33.917749 ===================================
4896 11:36:33.921456 data_rate = 1866
4897 11:36:33.924813 CKR = 1
4898 11:36:33.924888 DQ_P2S_RATIO = 8
4899 11:36:33.928027 ===================================
4900 11:36:33.931245 CA_P2S_RATIO = 8
4901 11:36:33.934529 DQ_CA_OPEN = 0
4902 11:36:33.937681 DQ_SEMI_OPEN = 0
4903 11:36:33.941032 CA_SEMI_OPEN = 0
4904 11:36:33.944560 CA_FULL_RATE = 0
4905 11:36:33.944624 DQ_CKDIV4_EN = 1
4906 11:36:33.947706 CA_CKDIV4_EN = 1
4907 11:36:33.951136 CA_PREDIV_EN = 0
4908 11:36:33.954426 PH8_DLY = 0
4909 11:36:33.957618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4910 11:36:33.960778 DQ_AAMCK_DIV = 4
4911 11:36:33.960860 CA_AAMCK_DIV = 4
4912 11:36:33.964143 CA_ADMCK_DIV = 4
4913 11:36:33.967479 DQ_TRACK_CA_EN = 0
4914 11:36:33.970754 CA_PICK = 933
4915 11:36:33.974063 CA_MCKIO = 933
4916 11:36:33.977490 MCKIO_SEMI = 0
4917 11:36:33.980809 PLL_FREQ = 3732
4918 11:36:33.980895 DQ_UI_PI_RATIO = 32
4919 11:36:33.984282 CA_UI_PI_RATIO = 0
4920 11:36:33.987482 ===================================
4921 11:36:33.990725 ===================================
4922 11:36:33.994452 memory_type:LPDDR4
4923 11:36:33.997664 GP_NUM : 10
4924 11:36:33.997730 SRAM_EN : 1
4925 11:36:34.000946 MD32_EN : 0
4926 11:36:34.004270 ===================================
4927 11:36:34.004334 [ANA_INIT] >>>>>>>>>>>>>>
4928 11:36:34.007829 <<<<<< [CONFIGURE PHASE]: ANA_TX
4929 11:36:34.010897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4930 11:36:34.014183 ===================================
4931 11:36:34.017518 data_rate = 1866,PCW = 0X8f00
4932 11:36:34.020656 ===================================
4933 11:36:34.024092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4934 11:36:34.030768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 11:36:34.034224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 11:36:34.040998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4937 11:36:34.044119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4938 11:36:34.047819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4939 11:36:34.050672 [ANA_INIT] flow start
4940 11:36:34.050753 [ANA_INIT] PLL >>>>>>>>
4941 11:36:34.054077 [ANA_INIT] PLL <<<<<<<<
4942 11:36:34.057476 [ANA_INIT] MIDPI >>>>>>>>
4943 11:36:34.057540 [ANA_INIT] MIDPI <<<<<<<<
4944 11:36:34.060437 [ANA_INIT] DLL >>>>>>>>
4945 11:36:34.064063 [ANA_INIT] flow end
4946 11:36:34.067410 ============ LP4 DIFF to SE enter ============
4947 11:36:34.070804 ============ LP4 DIFF to SE exit ============
4948 11:36:34.074159 [ANA_INIT] <<<<<<<<<<<<<
4949 11:36:34.077513 [Flow] Enable top DCM control >>>>>
4950 11:36:34.080250 [Flow] Enable top DCM control <<<<<
4951 11:36:34.083686 Enable DLL master slave shuffle
4952 11:36:34.087003 ==============================================================
4953 11:36:34.090573 Gating Mode config
4954 11:36:34.096921 ==============================================================
4955 11:36:34.096996 Config description:
4956 11:36:34.107064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4957 11:36:34.113802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4958 11:36:34.116670 SELPH_MODE 0: By rank 1: By Phase
4959 11:36:34.123543 ==============================================================
4960 11:36:34.126922 GAT_TRACK_EN = 1
4961 11:36:34.130223 RX_GATING_MODE = 2
4962 11:36:34.133440 RX_GATING_TRACK_MODE = 2
4963 11:36:34.137006 SELPH_MODE = 1
4964 11:36:34.140504 PICG_EARLY_EN = 1
4965 11:36:34.143821 VALID_LAT_VALUE = 1
4966 11:36:34.146678 ==============================================================
4967 11:36:34.150300 Enter into Gating configuration >>>>
4968 11:36:34.153257 Exit from Gating configuration <<<<
4969 11:36:34.156645 Enter into DVFS_PRE_config >>>>>
4970 11:36:34.169941 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4971 11:36:34.170025 Exit from DVFS_PRE_config <<<<<
4972 11:36:34.173369 Enter into PICG configuration >>>>
4973 11:36:34.176857 Exit from PICG configuration <<<<
4974 11:36:34.179966 [RX_INPUT] configuration >>>>>
4975 11:36:34.183622 [RX_INPUT] configuration <<<<<
4976 11:36:34.189809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4977 11:36:34.193576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4978 11:36:34.200246 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 11:36:34.206764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 11:36:34.213288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 11:36:34.220181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 11:36:34.223423 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4983 11:36:34.226794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4984 11:36:34.230166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4985 11:36:34.236208 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4986 11:36:34.240374 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4987 11:36:34.243042 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 11:36:34.246810 ===================================
4989 11:36:34.249848 LPDDR4 DRAM CONFIGURATION
4990 11:36:34.253326 ===================================
4991 11:36:34.253401 EX_ROW_EN[0] = 0x0
4992 11:36:34.256552 EX_ROW_EN[1] = 0x0
4993 11:36:34.260149 LP4Y_EN = 0x0
4994 11:36:34.260214 WORK_FSP = 0x0
4995 11:36:34.262888 WL = 0x3
4996 11:36:34.262963 RL = 0x3
4997 11:36:34.266660 BL = 0x2
4998 11:36:34.266741 RPST = 0x0
4999 11:36:34.269967 RD_PRE = 0x0
5000 11:36:34.270100 WR_PRE = 0x1
5001 11:36:34.272956 WR_PST = 0x0
5002 11:36:34.273031 DBI_WR = 0x0
5003 11:36:34.276867 DBI_RD = 0x0
5004 11:36:34.276940 OTF = 0x1
5005 11:36:34.280071 ===================================
5006 11:36:34.282755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5007 11:36:34.289489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5008 11:36:34.293233 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 11:36:34.296049 ===================================
5010 11:36:34.299620 LPDDR4 DRAM CONFIGURATION
5011 11:36:34.303189 ===================================
5012 11:36:34.303264 EX_ROW_EN[0] = 0x10
5013 11:36:34.306444 EX_ROW_EN[1] = 0x0
5014 11:36:34.306519 LP4Y_EN = 0x0
5015 11:36:34.309659 WORK_FSP = 0x0
5016 11:36:34.312973 WL = 0x3
5017 11:36:34.313049 RL = 0x3
5018 11:36:34.316170 BL = 0x2
5019 11:36:34.316243 RPST = 0x0
5020 11:36:34.319325 RD_PRE = 0x0
5021 11:36:34.319399 WR_PRE = 0x1
5022 11:36:34.323219 WR_PST = 0x0
5023 11:36:34.323294 DBI_WR = 0x0
5024 11:36:34.326769 DBI_RD = 0x0
5025 11:36:34.326844 OTF = 0x1
5026 11:36:34.329822 ===================================
5027 11:36:34.335830 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5028 11:36:34.340608 nWR fixed to 30
5029 11:36:34.343823 [ModeRegInit_LP4] CH0 RK0
5030 11:36:34.343898 [ModeRegInit_LP4] CH0 RK1
5031 11:36:34.346641 [ModeRegInit_LP4] CH1 RK0
5032 11:36:34.349996 [ModeRegInit_LP4] CH1 RK1
5033 11:36:34.350093 match AC timing 9
5034 11:36:34.356740 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5035 11:36:34.360392 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5036 11:36:34.363792 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5037 11:36:34.370225 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5038 11:36:34.373588 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5039 11:36:34.373663 ==
5040 11:36:34.376601 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 11:36:34.380281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 11:36:34.380356 ==
5043 11:36:34.387087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 11:36:34.393591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5045 11:36:34.396845 [CA 0] Center 37 (6~68) winsize 63
5046 11:36:34.400342 [CA 1] Center 37 (7~68) winsize 62
5047 11:36:34.403533 [CA 2] Center 34 (4~65) winsize 62
5048 11:36:34.406803 [CA 3] Center 34 (3~65) winsize 63
5049 11:36:34.410162 [CA 4] Center 33 (2~64) winsize 63
5050 11:36:34.413232 [CA 5] Center 32 (2~62) winsize 61
5051 11:36:34.413308
5052 11:36:34.416779 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5053 11:36:34.416855
5054 11:36:34.419859 [CATrainingPosCal] consider 1 rank data
5055 11:36:34.423177 u2DelayCellTimex100 = 270/100 ps
5056 11:36:34.426862 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5057 11:36:34.429954 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5058 11:36:34.433541 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5059 11:36:34.436486 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5060 11:36:34.439874 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5061 11:36:34.443127 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5062 11:36:34.446436
5063 11:36:34.449919 CA PerBit enable=1, Macro0, CA PI delay=32
5064 11:36:34.450025
5065 11:36:34.452938 [CBTSetCACLKResult] CA Dly = 32
5066 11:36:34.453014 CS Dly: 5 (0~36)
5067 11:36:34.453072 ==
5068 11:36:34.456833 Dram Type= 6, Freq= 0, CH_0, rank 1
5069 11:36:34.460552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 11:36:34.460633 ==
5071 11:36:34.466768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 11:36:34.473160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 11:36:34.476498 [CA 0] Center 37 (6~68) winsize 63
5074 11:36:34.479861 [CA 1] Center 37 (6~68) winsize 63
5075 11:36:34.483083 [CA 2] Center 34 (4~65) winsize 62
5076 11:36:34.487006 [CA 3] Center 33 (3~64) winsize 62
5077 11:36:34.489843 [CA 4] Center 32 (2~63) winsize 62
5078 11:36:34.493119 [CA 5] Center 32 (2~62) winsize 61
5079 11:36:34.493193
5080 11:36:34.496619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 11:36:34.496694
5082 11:36:34.499675 [CATrainingPosCal] consider 2 rank data
5083 11:36:34.503594 u2DelayCellTimex100 = 270/100 ps
5084 11:36:34.506837 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5085 11:36:34.509599 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5086 11:36:34.512876 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5087 11:36:34.516601 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5088 11:36:34.519673 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5089 11:36:34.526433 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5090 11:36:34.526522
5091 11:36:34.530065 CA PerBit enable=1, Macro0, CA PI delay=32
5092 11:36:34.530140
5093 11:36:34.533093 [CBTSetCACLKResult] CA Dly = 32
5094 11:36:34.533168 CS Dly: 5 (0~37)
5095 11:36:34.533224
5096 11:36:34.536303 ----->DramcWriteLeveling(PI) begin...
5097 11:36:34.536381 ==
5098 11:36:34.539508 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 11:36:34.543095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 11:36:34.546079 ==
5101 11:36:34.546169 Write leveling (Byte 0): 34 => 34
5102 11:36:34.549820 Write leveling (Byte 1): 29 => 29
5103 11:36:34.552939 DramcWriteLeveling(PI) end<-----
5104 11:36:34.553016
5105 11:36:34.553074 ==
5106 11:36:34.556295 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 11:36:34.562774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 11:36:34.562849 ==
5109 11:36:34.566049 [Gating] SW mode calibration
5110 11:36:34.572711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5111 11:36:34.576563 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5112 11:36:34.582604 0 14 0 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
5113 11:36:34.586332 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:36:34.589501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:36:34.596056 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:36:34.599149 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:36:34.602632 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 11:36:34.609277 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5119 11:36:34.612417 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
5120 11:36:34.615764 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5121 11:36:34.622314 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:36:34.626167 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:36:34.629589 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:36:34.632682 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:36:34.639516 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 11:36:34.642893 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5127 11:36:34.646136 0 15 28 | B1->B0 | 2828 4040 | 0 0 | (0 0) (1 1)
5128 11:36:34.652716 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5129 11:36:34.656074 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:36:34.659118 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:36:34.665805 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:36:34.669712 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:36:34.672521 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 11:36:34.679044 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 11:36:34.682243 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5136 11:36:34.686084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5137 11:36:34.692565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:36:34.695529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:36:34.698713 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:36:34.705344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:36:34.709249 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:36:34.712395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:36:34.719093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:36:34.722366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:36:34.725398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:36:34.732622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:36:34.735876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:36:34.739164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:36:34.742174 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:36:34.749217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5151 11:36:34.752481 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 11:36:34.755584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:36:34.758869 Total UI for P1: 0, mck2ui 16
5154 11:36:34.762191 best dqsien dly found for B0: ( 1, 2, 26)
5155 11:36:34.765988 Total UI for P1: 0, mck2ui 16
5156 11:36:34.769066 best dqsien dly found for B1: ( 1, 2, 30)
5157 11:36:34.772418 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5158 11:36:34.776133 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5159 11:36:34.776208
5160 11:36:34.782568 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5161 11:36:34.785702 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5162 11:36:34.788989 [Gating] SW calibration Done
5163 11:36:34.789064 ==
5164 11:36:34.792205 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 11:36:34.795992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 11:36:34.796067 ==
5167 11:36:34.796125 RX Vref Scan: 0
5168 11:36:34.796179
5169 11:36:34.799211 RX Vref 0 -> 0, step: 1
5170 11:36:34.799285
5171 11:36:34.802773 RX Delay -80 -> 252, step: 8
5172 11:36:34.805894 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5173 11:36:34.808745 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5174 11:36:34.812446 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5175 11:36:34.819043 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5176 11:36:34.822346 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5177 11:36:34.825566 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5178 11:36:34.828951 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5179 11:36:34.832369 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5180 11:36:34.839117 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5181 11:36:34.842296 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5182 11:36:34.845644 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5183 11:36:34.848845 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5184 11:36:34.852826 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5185 11:36:34.856189 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5186 11:36:34.862688 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5187 11:36:34.865982 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5188 11:36:34.866102 ==
5189 11:36:34.869346 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 11:36:34.872355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 11:36:34.872431 ==
5192 11:36:34.872489 DQS Delay:
5193 11:36:34.876219 DQS0 = 0, DQS1 = 0
5194 11:36:34.876294 DQM Delay:
5195 11:36:34.879168 DQM0 = 105, DQM1 = 95
5196 11:36:34.879242 DQ Delay:
5197 11:36:34.882756 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =103
5198 11:36:34.885889 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5199 11:36:34.889273 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5200 11:36:34.892377 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5201 11:36:34.892452
5202 11:36:34.892509
5203 11:36:34.892562 ==
5204 11:36:34.895813 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 11:36:34.902218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 11:36:34.902294 ==
5207 11:36:34.902352
5208 11:36:34.902406
5209 11:36:34.902473 TX Vref Scan disable
5210 11:36:34.906272 == TX Byte 0 ==
5211 11:36:34.909612 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5212 11:36:34.915847 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5213 11:36:34.915923 == TX Byte 1 ==
5214 11:36:34.919037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5215 11:36:34.925626 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5216 11:36:34.925701 ==
5217 11:36:34.929460 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:36:34.932333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:36:34.932409 ==
5220 11:36:34.932467
5221 11:36:34.932520
5222 11:36:34.936099 TX Vref Scan disable
5223 11:36:34.936174 == TX Byte 0 ==
5224 11:36:34.942624 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5225 11:36:34.946194 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5226 11:36:34.946270 == TX Byte 1 ==
5227 11:36:34.952493 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5228 11:36:34.955681 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5229 11:36:34.955756
5230 11:36:34.955823 [DATLAT]
5231 11:36:34.958962 Freq=933, CH0 RK0
5232 11:36:34.959037
5233 11:36:34.959095 DATLAT Default: 0xd
5234 11:36:34.962394 0, 0xFFFF, sum = 0
5235 11:36:34.962471 1, 0xFFFF, sum = 0
5236 11:36:34.966123 2, 0xFFFF, sum = 0
5237 11:36:34.966199 3, 0xFFFF, sum = 0
5238 11:36:34.969565 4, 0xFFFF, sum = 0
5239 11:36:34.969641 5, 0xFFFF, sum = 0
5240 11:36:34.972709 6, 0xFFFF, sum = 0
5241 11:36:34.972784 7, 0xFFFF, sum = 0
5242 11:36:34.976100 8, 0xFFFF, sum = 0
5243 11:36:34.979314 9, 0xFFFF, sum = 0
5244 11:36:34.979390 10, 0x0, sum = 1
5245 11:36:34.979450 11, 0x0, sum = 2
5246 11:36:34.982687 12, 0x0, sum = 3
5247 11:36:34.982763 13, 0x0, sum = 4
5248 11:36:34.985870 best_step = 11
5249 11:36:34.985945
5250 11:36:34.986002 ==
5251 11:36:34.988924 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 11:36:34.992220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 11:36:34.992289 ==
5254 11:36:34.995660 RX Vref Scan: 1
5255 11:36:34.995735
5256 11:36:34.995792 RX Vref 0 -> 0, step: 1
5257 11:36:34.995846
5258 11:36:34.999426 RX Delay -45 -> 252, step: 4
5259 11:36:34.999500
5260 11:36:35.002635 Set Vref, RX VrefLevel [Byte0]: 54
5261 11:36:35.005459 [Byte1]: 48
5262 11:36:35.009773
5263 11:36:35.009847 Final RX Vref Byte 0 = 54 to rank0
5264 11:36:35.013127 Final RX Vref Byte 1 = 48 to rank0
5265 11:36:35.016318 Final RX Vref Byte 0 = 54 to rank1
5266 11:36:35.020099 Final RX Vref Byte 1 = 48 to rank1==
5267 11:36:35.023295 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 11:36:35.030122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 11:36:35.030201 ==
5270 11:36:35.030259 DQS Delay:
5271 11:36:35.030313 DQS0 = 0, DQS1 = 0
5272 11:36:35.032986 DQM Delay:
5273 11:36:35.033061 DQM0 = 104, DQM1 = 94
5274 11:36:35.036620 DQ Delay:
5275 11:36:35.039706 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5276 11:36:35.043067 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5277 11:36:35.046424 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =88
5278 11:36:35.049540 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5279 11:36:35.049615
5280 11:36:35.049673
5281 11:36:35.056446 [DQSOSCAuto] RK0, (LSB)MR18= 0x362d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 404 ps
5282 11:36:35.060034 CH0 RK0: MR19=505, MR18=362D
5283 11:36:35.066884 CH0_RK0: MR19=0x505, MR18=0x362D, DQSOSC=404, MR23=63, INC=66, DEC=44
5284 11:36:35.066960
5285 11:36:35.070054 ----->DramcWriteLeveling(PI) begin...
5286 11:36:35.070130 ==
5287 11:36:35.073192 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 11:36:35.076632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 11:36:35.076707 ==
5290 11:36:35.079862 Write leveling (Byte 0): 32 => 32
5291 11:36:35.083047 Write leveling (Byte 1): 30 => 30
5292 11:36:35.086426 DramcWriteLeveling(PI) end<-----
5293 11:36:35.086502
5294 11:36:35.086559 ==
5295 11:36:35.090435 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 11:36:35.093211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 11:36:35.096832 ==
5298 11:36:35.096900 [Gating] SW mode calibration
5299 11:36:35.106429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5300 11:36:35.109669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5301 11:36:35.113417 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 0)
5302 11:36:35.119981 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:36:35.122810 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 11:36:35.126213 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:36:35.132999 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 11:36:35.136852 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 11:36:35.139997 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5308 11:36:35.146553 0 14 28 | B1->B0 | 2b2b 2c2c | 0 0 | (1 0) (0 0)
5309 11:36:35.149734 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5310 11:36:35.153040 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:36:35.159695 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:36:35.163152 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:36:35.166877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:36:35.170118 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 11:36:35.176425 0 15 24 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
5316 11:36:35.180043 0 15 28 | B1->B0 | 4242 3939 | 1 0 | (0 0) (0 0)
5317 11:36:35.182899 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5318 11:36:35.189553 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:36:35.193564 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:36:35.196137 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:36:35.203333 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:36:35.206484 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:36:35.209602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 11:36:35.216210 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5325 11:36:35.219748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:36:35.222889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:36:35.229752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:36:35.232836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:36:35.236072 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:36:35.243096 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:36:35.246491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:36:35.249691 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:36:35.255913 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:36:35.259639 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:36:35.263053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:36:35.269463 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:36:35.272838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:36:35.276071 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:36:35.282637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5340 11:36:35.285958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5341 11:36:35.289128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:36:35.292762 Total UI for P1: 0, mck2ui 16
5343 11:36:35.296139 best dqsien dly found for B0: ( 1, 2, 28)
5344 11:36:35.299273 Total UI for P1: 0, mck2ui 16
5345 11:36:35.302592 best dqsien dly found for B1: ( 1, 2, 26)
5346 11:36:35.306070 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5347 11:36:35.309405 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5348 11:36:35.309465
5349 11:36:35.312630 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 11:36:35.319246 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5351 11:36:35.319315 [Gating] SW calibration Done
5352 11:36:35.319370 ==
5353 11:36:35.322454 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 11:36:35.329197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 11:36:35.329274 ==
5356 11:36:35.329332 RX Vref Scan: 0
5357 11:36:35.329386
5358 11:36:35.332273 RX Vref 0 -> 0, step: 1
5359 11:36:35.332347
5360 11:36:35.335927 RX Delay -80 -> 252, step: 8
5361 11:36:35.339241 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5362 11:36:35.342382 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5363 11:36:35.345551 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5364 11:36:35.352507 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5365 11:36:35.355530 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5366 11:36:35.358790 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5367 11:36:35.362026 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5368 11:36:35.365852 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5369 11:36:35.368635 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5370 11:36:35.375976 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5371 11:36:35.378868 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5372 11:36:35.381972 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5373 11:36:35.385324 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5374 11:36:35.388732 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5375 11:36:35.391898 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5376 11:36:35.399052 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5377 11:36:35.399127 ==
5378 11:36:35.402019 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 11:36:35.405541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 11:36:35.405610 ==
5381 11:36:35.405673 DQS Delay:
5382 11:36:35.408720 DQS0 = 0, DQS1 = 0
5383 11:36:35.408787 DQM Delay:
5384 11:36:35.412312 DQM0 = 105, DQM1 = 92
5385 11:36:35.412374 DQ Delay:
5386 11:36:35.415473 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5387 11:36:35.418721 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5388 11:36:35.422218 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5389 11:36:35.425883 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5390 11:36:35.425973
5391 11:36:35.426065
5392 11:36:35.426151 ==
5393 11:36:35.428814 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 11:36:35.431863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 11:36:35.435628 ==
5396 11:36:35.435690
5397 11:36:35.435744
5398 11:36:35.435795 TX Vref Scan disable
5399 11:36:35.439084 == TX Byte 0 ==
5400 11:36:35.441642 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5401 11:36:35.444917 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5402 11:36:35.448962 == TX Byte 1 ==
5403 11:36:35.451862 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5404 11:36:35.455213 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5405 11:36:35.458304 ==
5406 11:36:35.462087 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 11:36:35.465467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 11:36:35.465537 ==
5409 11:36:35.465595
5410 11:36:35.465648
5411 11:36:35.468612 TX Vref Scan disable
5412 11:36:35.468674 == TX Byte 0 ==
5413 11:36:35.475448 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5414 11:36:35.478471 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5415 11:36:35.478564 == TX Byte 1 ==
5416 11:36:35.485080 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5417 11:36:35.488631 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5418 11:36:35.488699
5419 11:36:35.488753 [DATLAT]
5420 11:36:35.491947 Freq=933, CH0 RK1
5421 11:36:35.492010
5422 11:36:35.492068 DATLAT Default: 0xb
5423 11:36:35.495220 0, 0xFFFF, sum = 0
5424 11:36:35.495294 1, 0xFFFF, sum = 0
5425 11:36:35.498584 2, 0xFFFF, sum = 0
5426 11:36:35.498649 3, 0xFFFF, sum = 0
5427 11:36:35.501922 4, 0xFFFF, sum = 0
5428 11:36:35.501999 5, 0xFFFF, sum = 0
5429 11:36:35.505021 6, 0xFFFF, sum = 0
5430 11:36:35.505097 7, 0xFFFF, sum = 0
5431 11:36:35.508862 8, 0xFFFF, sum = 0
5432 11:36:35.508938 9, 0xFFFF, sum = 0
5433 11:36:35.511651 10, 0x0, sum = 1
5434 11:36:35.511727 11, 0x0, sum = 2
5435 11:36:35.515033 12, 0x0, sum = 3
5436 11:36:35.515110 13, 0x0, sum = 4
5437 11:36:35.518262 best_step = 11
5438 11:36:35.518332
5439 11:36:35.518389 ==
5440 11:36:35.522131 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 11:36:35.525329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 11:36:35.525395 ==
5443 11:36:35.528877 RX Vref Scan: 0
5444 11:36:35.528940
5445 11:36:35.529001 RX Vref 0 -> 0, step: 1
5446 11:36:35.529059
5447 11:36:35.532190 RX Delay -53 -> 252, step: 4
5448 11:36:35.538900 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5449 11:36:35.542161 iDelay=195, Bit 1, Center 106 (19 ~ 194) 176
5450 11:36:35.545332 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5451 11:36:35.548736 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5452 11:36:35.552090 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5453 11:36:35.558748 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5454 11:36:35.562031 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5455 11:36:35.565177 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5456 11:36:35.568740 iDelay=195, Bit 8, Center 84 (-1 ~ 170) 172
5457 11:36:35.572028 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5458 11:36:35.578443 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5459 11:36:35.582264 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5460 11:36:35.585378 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5461 11:36:35.588476 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5462 11:36:35.592099 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5463 11:36:35.599031 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5464 11:36:35.599123 ==
5465 11:36:35.601950 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 11:36:35.605175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 11:36:35.605250 ==
5468 11:36:35.605308 DQS Delay:
5469 11:36:35.608501 DQS0 = 0, DQS1 = 0
5470 11:36:35.608576 DQM Delay:
5471 11:36:35.612006 DQM0 = 104, DQM1 = 93
5472 11:36:35.612081 DQ Delay:
5473 11:36:35.615358 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5474 11:36:35.618483 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5475 11:36:35.622485 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5476 11:36:35.625444 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5477 11:36:35.625519
5478 11:36:35.625576
5479 11:36:35.635220 [DQSOSCAuto] RK1, (LSB)MR18= 0x3008, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 406 ps
5480 11:36:35.635297 CH0 RK1: MR19=505, MR18=3008
5481 11:36:35.642271 CH0_RK1: MR19=0x505, MR18=0x3008, DQSOSC=406, MR23=63, INC=65, DEC=43
5482 11:36:35.645332 [RxdqsGatingPostProcess] freq 933
5483 11:36:35.651682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5484 11:36:35.655022 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 11:36:35.658890 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 11:36:35.662113 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 11:36:35.665419 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 11:36:35.668655 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 11:36:35.668731 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 11:36:35.671547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 11:36:35.675425 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 11:36:35.678915 Pre-setting of DQS Precalculation
5493 11:36:35.684968 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5494 11:36:35.685044 ==
5495 11:36:35.688350 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 11:36:35.691694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 11:36:35.691770 ==
5498 11:36:35.698565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 11:36:35.705187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5500 11:36:35.708724 [CA 0] Center 36 (6~67) winsize 62
5501 11:36:35.711636 [CA 1] Center 36 (6~67) winsize 62
5502 11:36:35.714814 [CA 2] Center 34 (4~65) winsize 62
5503 11:36:35.718197 [CA 3] Center 34 (4~65) winsize 62
5504 11:36:35.721558 [CA 4] Center 34 (4~64) winsize 61
5505 11:36:35.721633 [CA 5] Center 33 (3~64) winsize 62
5506 11:36:35.724968
5507 11:36:35.728298 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5508 11:36:35.728373
5509 11:36:35.731503 [CATrainingPosCal] consider 1 rank data
5510 11:36:35.735667 u2DelayCellTimex100 = 270/100 ps
5511 11:36:35.738208 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5512 11:36:35.741941 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5513 11:36:35.745427 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5514 11:36:35.748555 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5515 11:36:35.751814 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5516 11:36:35.754782 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5517 11:36:35.754857
5518 11:36:35.758120 CA PerBit enable=1, Macro0, CA PI delay=33
5519 11:36:35.758195
5520 11:36:35.761544 [CBTSetCACLKResult] CA Dly = 33
5521 11:36:35.764815 CS Dly: 7 (0~38)
5522 11:36:35.764889 ==
5523 11:36:35.768649 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 11:36:35.771984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 11:36:35.772060 ==
5526 11:36:35.778684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 11:36:35.785362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 11:36:35.788611 [CA 0] Center 36 (6~67) winsize 62
5529 11:36:35.791615 [CA 1] Center 37 (7~68) winsize 62
5530 11:36:35.795452 [CA 2] Center 35 (5~66) winsize 62
5531 11:36:35.798030 [CA 3] Center 34 (4~65) winsize 62
5532 11:36:35.801504 [CA 4] Center 34 (4~65) winsize 62
5533 11:36:35.805124 [CA 5] Center 34 (4~64) winsize 61
5534 11:36:35.805198
5535 11:36:35.807922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 11:36:35.807997
5537 11:36:35.811729 [CATrainingPosCal] consider 2 rank data
5538 11:36:35.814820 u2DelayCellTimex100 = 270/100 ps
5539 11:36:35.818146 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5540 11:36:35.821555 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5541 11:36:35.824777 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5542 11:36:35.828219 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5543 11:36:35.831188 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 11:36:35.834504 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5545 11:36:35.834580
5546 11:36:35.841345 CA PerBit enable=1, Macro0, CA PI delay=34
5547 11:36:35.841420
5548 11:36:35.841479 [CBTSetCACLKResult] CA Dly = 34
5549 11:36:35.844721 CS Dly: 8 (0~40)
5550 11:36:35.844795
5551 11:36:35.848014 ----->DramcWriteLeveling(PI) begin...
5552 11:36:35.848090 ==
5553 11:36:35.851551 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 11:36:35.854680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 11:36:35.854756 ==
5556 11:36:35.857635 Write leveling (Byte 0): 29 => 29
5557 11:36:35.861306 Write leveling (Byte 1): 27 => 27
5558 11:36:35.864711 DramcWriteLeveling(PI) end<-----
5559 11:36:35.864786
5560 11:36:35.864844 ==
5561 11:36:35.868073 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 11:36:35.873914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 11:36:35.873991 ==
5564 11:36:35.874093 [Gating] SW mode calibration
5565 11:36:35.884455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5566 11:36:35.888097 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5567 11:36:35.890869 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:36:35.897229 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:36:35.900900 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:36:35.904205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:36:35.910719 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 11:36:35.913728 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 11:36:35.917032 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5574 11:36:35.923704 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5575 11:36:35.926919 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:36:35.930281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:36:35.936862 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:36:35.940463 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:36:35.943554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:36:35.950378 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5581 11:36:35.953569 0 15 24 | B1->B0 | 2727 3a39 | 0 1 | (0 0) (1 1)
5582 11:36:35.957020 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5583 11:36:35.963492 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:36:35.967047 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:36:35.970071 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:36:35.976945 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:36:35.980214 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:36:35.983276 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:36:35.989723 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 11:36:35.992961 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5591 11:36:35.996258 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:36:36.003446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:36:36.006525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:36:36.009769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:36:36.016490 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:36:36.019673 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:36:36.023038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:36:36.029597 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:36:36.032960 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:36:36.036794 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:36:36.043251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:36:36.046369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:36:36.049586 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:36:36.056545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 11:36:36.059729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 11:36:36.063078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:36:36.066480 Total UI for P1: 0, mck2ui 16
5608 11:36:36.069592 best dqsien dly found for B0: ( 1, 2, 24)
5609 11:36:36.072871 Total UI for P1: 0, mck2ui 16
5610 11:36:36.076266 best dqsien dly found for B1: ( 1, 2, 24)
5611 11:36:36.080041 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5612 11:36:36.083294 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5613 11:36:36.083369
5614 11:36:36.086266 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5615 11:36:36.092628 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5616 11:36:36.092703 [Gating] SW calibration Done
5617 11:36:36.092762 ==
5618 11:36:36.097223 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 11:36:36.103052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 11:36:36.103125 ==
5621 11:36:36.103182 RX Vref Scan: 0
5622 11:36:36.103242
5623 11:36:36.106167 RX Vref 0 -> 0, step: 1
5624 11:36:36.106233
5625 11:36:36.109244 RX Delay -80 -> 252, step: 8
5626 11:36:36.112411 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5627 11:36:36.115842 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5628 11:36:36.119161 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5629 11:36:36.122420 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5630 11:36:36.129160 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5631 11:36:36.133070 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5632 11:36:36.136028 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5633 11:36:36.139156 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5634 11:36:36.142458 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5635 11:36:36.145642 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5636 11:36:36.152641 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5637 11:36:36.155540 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5638 11:36:36.159314 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5639 11:36:36.162307 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5640 11:36:36.165611 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5641 11:36:36.172203 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5642 11:36:36.172289 ==
5643 11:36:36.175657 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:36:36.178770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:36:36.178833 ==
5646 11:36:36.178893 DQS Delay:
5647 11:36:36.182362 DQS0 = 0, DQS1 = 0
5648 11:36:36.182424 DQM Delay:
5649 11:36:36.185492 DQM0 = 102, DQM1 = 98
5650 11:36:36.185556 DQ Delay:
5651 11:36:36.188781 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5652 11:36:36.192491 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5653 11:36:36.195790 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5654 11:36:36.199497 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5655 11:36:36.199588
5656 11:36:36.199672
5657 11:36:36.199729 ==
5658 11:36:36.202389 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 11:36:36.209186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 11:36:36.209256 ==
5661 11:36:36.209309
5662 11:36:36.209359
5663 11:36:36.209408 TX Vref Scan disable
5664 11:36:36.212411 == TX Byte 0 ==
5665 11:36:36.215665 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5666 11:36:36.222242 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5667 11:36:36.222310 == TX Byte 1 ==
5668 11:36:36.226039 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 11:36:36.232587 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 11:36:36.232654 ==
5671 11:36:36.236037 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 11:36:36.239096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 11:36:36.239189 ==
5674 11:36:36.239270
5675 11:36:36.239360
5676 11:36:36.242414 TX Vref Scan disable
5677 11:36:36.242475 == TX Byte 0 ==
5678 11:36:36.248982 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5679 11:36:36.252163 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5680 11:36:36.252226 == TX Byte 1 ==
5681 11:36:36.258893 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 11:36:36.262038 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 11:36:36.262122
5684 11:36:36.262177 [DATLAT]
5685 11:36:36.265788 Freq=933, CH1 RK0
5686 11:36:36.265854
5687 11:36:36.265962 DATLAT Default: 0xd
5688 11:36:36.268831 0, 0xFFFF, sum = 0
5689 11:36:36.268921 1, 0xFFFF, sum = 0
5690 11:36:36.272301 2, 0xFFFF, sum = 0
5691 11:36:36.272370 3, 0xFFFF, sum = 0
5692 11:36:36.275307 4, 0xFFFF, sum = 0
5693 11:36:36.275367 5, 0xFFFF, sum = 0
5694 11:36:36.278766 6, 0xFFFF, sum = 0
5695 11:36:36.282496 7, 0xFFFF, sum = 0
5696 11:36:36.282590 8, 0xFFFF, sum = 0
5697 11:36:36.285688 9, 0xFFFF, sum = 0
5698 11:36:36.285752 10, 0x0, sum = 1
5699 11:36:36.288979 11, 0x0, sum = 2
5700 11:36:36.289040 12, 0x0, sum = 3
5701 11:36:36.289091 13, 0x0, sum = 4
5702 11:36:36.292342 best_step = 11
5703 11:36:36.292402
5704 11:36:36.292451 ==
5705 11:36:36.295454 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 11:36:36.298876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 11:36:36.298941 ==
5708 11:36:36.302206 RX Vref Scan: 1
5709 11:36:36.302268
5710 11:36:36.302326 RX Vref 0 -> 0, step: 1
5711 11:36:36.305652
5712 11:36:36.305745 RX Delay -45 -> 252, step: 4
5713 11:36:36.305826
5714 11:36:36.308890 Set Vref, RX VrefLevel [Byte0]: 55
5715 11:36:36.312155 [Byte1]: 52
5716 11:36:36.316193
5717 11:36:36.316268 Final RX Vref Byte 0 = 55 to rank0
5718 11:36:36.320020 Final RX Vref Byte 1 = 52 to rank0
5719 11:36:36.323265 Final RX Vref Byte 0 = 55 to rank1
5720 11:36:36.326612 Final RX Vref Byte 1 = 52 to rank1==
5721 11:36:36.329487 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:36:36.335997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:36:36.336073 ==
5724 11:36:36.336131 DQS Delay:
5725 11:36:36.336185 DQS0 = 0, DQS1 = 0
5726 11:36:36.339974 DQM Delay:
5727 11:36:36.340049 DQM0 = 103, DQM1 = 99
5728 11:36:36.342751 DQ Delay:
5729 11:36:36.346307 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5730 11:36:36.349612 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5731 11:36:36.352864 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5732 11:36:36.356252 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5733 11:36:36.356327
5734 11:36:36.356385
5735 11:36:36.362749 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5736 11:36:36.365845 CH1 RK0: MR19=505, MR18=1C33
5737 11:36:36.372613 CH1_RK0: MR19=0x505, MR18=0x1C33, DQSOSC=405, MR23=63, INC=66, DEC=44
5738 11:36:36.372689
5739 11:36:36.376188 ----->DramcWriteLeveling(PI) begin...
5740 11:36:36.376296 ==
5741 11:36:36.379114 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 11:36:36.383030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:36:36.383152 ==
5744 11:36:36.385947 Write leveling (Byte 0): 29 => 29
5745 11:36:36.389458 Write leveling (Byte 1): 29 => 29
5746 11:36:36.392807 DramcWriteLeveling(PI) end<-----
5747 11:36:36.392918
5748 11:36:36.393001 ==
5749 11:36:36.396145 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 11:36:36.402896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 11:36:36.402975 ==
5752 11:36:36.403052 [Gating] SW mode calibration
5753 11:36:36.412701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 11:36:36.415587 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 11:36:36.419209 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:36:36.425861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:36:36.429141 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:36:36.432173 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:36:36.438868 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:36:36.442440 0 14 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5761 11:36:36.446083 0 14 24 | B1->B0 | 2f2f 3232 | 0 0 | (0 1) (0 1)
5762 11:36:36.452383 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5763 11:36:36.455883 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:36:36.459391 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:36:36.466039 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:36:36.469206 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:36:36.472582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:36:36.479427 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:36:36.482276 0 15 24 | B1->B0 | 3636 2828 | 1 0 | (0 0) (0 0)
5770 11:36:36.485982 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5771 11:36:36.492486 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:36:36.495486 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:36:36.499019 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:36:36.505808 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:36:36.508994 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:36:36.512328 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:36:36.518984 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5778 11:36:36.522090 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5779 11:36:36.525284 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:36:36.532327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:36:36.535685 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:36:36.539069 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:36:36.545425 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:36:36.548650 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:36:36.552008 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:36:36.555192 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:36:36.562027 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:36:36.565661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:36:36.568606 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:36:36.575578 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:36:36.578820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:36:36.581953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:36:36.588932 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5794 11:36:36.591792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 11:36:36.595658 Total UI for P1: 0, mck2ui 16
5796 11:36:36.598770 best dqsien dly found for B0: ( 1, 2, 24)
5797 11:36:36.602460 Total UI for P1: 0, mck2ui 16
5798 11:36:36.605580 best dqsien dly found for B1: ( 1, 2, 26)
5799 11:36:36.608597 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5800 11:36:36.611674 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5801 11:36:36.611749
5802 11:36:36.615437 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 11:36:36.618662 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5804 11:36:36.621991 [Gating] SW calibration Done
5805 11:36:36.622086 ==
5806 11:36:36.625106 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 11:36:36.628442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 11:36:36.631869 ==
5809 11:36:36.631943 RX Vref Scan: 0
5810 11:36:36.632001
5811 11:36:36.635753 RX Vref 0 -> 0, step: 1
5812 11:36:36.635828
5813 11:36:36.638864 RX Delay -80 -> 252, step: 8
5814 11:36:36.642266 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5815 11:36:36.645179 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5816 11:36:36.648936 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5817 11:36:36.651706 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5818 11:36:36.655392 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5819 11:36:36.661890 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5820 11:36:36.665006 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5821 11:36:36.668997 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5822 11:36:36.671744 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5823 11:36:36.675906 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5824 11:36:36.682462 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5825 11:36:36.685083 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5826 11:36:36.688644 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5827 11:36:36.691911 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5828 11:36:36.695121 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5829 11:36:36.701989 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5830 11:36:36.702072 ==
5831 11:36:36.704973 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 11:36:36.708833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 11:36:36.708957 ==
5834 11:36:36.709016 DQS Delay:
5835 11:36:36.711366 DQS0 = 0, DQS1 = 0
5836 11:36:36.711438 DQM Delay:
5837 11:36:36.715225 DQM0 = 105, DQM1 = 98
5838 11:36:36.715293 DQ Delay:
5839 11:36:36.718028 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =103
5840 11:36:36.721798 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5841 11:36:36.724672 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5842 11:36:36.728275 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5843 11:36:36.728346
5844 11:36:36.728404
5845 11:36:36.728457 ==
5846 11:36:36.731549 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 11:36:36.738321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 11:36:36.738400 ==
5849 11:36:36.738458
5850 11:36:36.738510
5851 11:36:36.738560 TX Vref Scan disable
5852 11:36:36.741525 == TX Byte 0 ==
5853 11:36:36.745213 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5854 11:36:36.751659 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5855 11:36:36.751806 == TX Byte 1 ==
5856 11:36:36.755004 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 11:36:36.761662 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 11:36:36.761802 ==
5859 11:36:36.765294 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 11:36:36.768200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 11:36:36.768363 ==
5862 11:36:36.768451
5863 11:36:36.768528
5864 11:36:36.771571 TX Vref Scan disable
5865 11:36:36.771721 == TX Byte 0 ==
5866 11:36:36.778442 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5867 11:36:36.782047 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5868 11:36:36.782251 == TX Byte 1 ==
5869 11:36:36.788487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5870 11:36:36.792137 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5871 11:36:36.792395
5872 11:36:36.792549 [DATLAT]
5873 11:36:36.795274 Freq=933, CH1 RK1
5874 11:36:36.795469
5875 11:36:36.795613 DATLAT Default: 0xb
5876 11:36:36.798699 0, 0xFFFF, sum = 0
5877 11:36:36.798992 1, 0xFFFF, sum = 0
5878 11:36:36.801893 2, 0xFFFF, sum = 0
5879 11:36:36.802220 3, 0xFFFF, sum = 0
5880 11:36:36.805206 4, 0xFFFF, sum = 0
5881 11:36:36.808498 5, 0xFFFF, sum = 0
5882 11:36:36.808785 6, 0xFFFF, sum = 0
5883 11:36:36.811547 7, 0xFFFF, sum = 0
5884 11:36:36.811908 8, 0xFFFF, sum = 0
5885 11:36:36.814715 9, 0xFFFF, sum = 0
5886 11:36:36.815104 10, 0x0, sum = 1
5887 11:36:36.818485 11, 0x0, sum = 2
5888 11:36:36.819073 12, 0x0, sum = 3
5889 11:36:36.819572 13, 0x0, sum = 4
5890 11:36:36.822039 best_step = 11
5891 11:36:36.822471
5892 11:36:36.822801 ==
5893 11:36:36.825535 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 11:36:36.828641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 11:36:36.829120 ==
5896 11:36:36.831729 RX Vref Scan: 0
5897 11:36:36.832163
5898 11:36:36.832492 RX Vref 0 -> 0, step: 1
5899 11:36:36.834763
5900 11:36:36.835183 RX Delay -45 -> 252, step: 4
5901 11:36:36.842418 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5902 11:36:36.845672 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5903 11:36:36.849007 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5904 11:36:36.852284 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5905 11:36:36.855557 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5906 11:36:36.862648 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5907 11:36:36.865618 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5908 11:36:36.869262 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5909 11:36:36.872199 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5910 11:36:36.875835 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5911 11:36:36.881990 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5912 11:36:36.885728 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5913 11:36:36.888652 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5914 11:36:36.892330 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5915 11:36:36.895464 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5916 11:36:36.902421 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5917 11:36:36.902918 ==
5918 11:36:36.905998 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 11:36:36.909335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 11:36:36.909831 ==
5921 11:36:36.910226 DQS Delay:
5922 11:36:36.913158 DQS0 = 0, DQS1 = 0
5923 11:36:36.913677 DQM Delay:
5924 11:36:36.915283 DQM0 = 105, DQM1 = 100
5925 11:36:36.915747 DQ Delay:
5926 11:36:36.918992 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5927 11:36:36.922125 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5928 11:36:36.925269 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5929 11:36:36.928975 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5930 11:36:36.929359
5931 11:36:36.929658
5932 11:36:36.938727 [DQSOSCAuto] RK1, (LSB)MR18= 0x3105, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5933 11:36:36.939219 CH1 RK1: MR19=505, MR18=3105
5934 11:36:36.945800 CH1_RK1: MR19=0x505, MR18=0x3105, DQSOSC=406, MR23=63, INC=65, DEC=43
5935 11:36:36.948992 [RxdqsGatingPostProcess] freq 933
5936 11:36:36.955379 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 11:36:36.958891 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 11:36:36.962104 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 11:36:36.965396 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 11:36:36.969302 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 11:36:36.971875 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 11:36:36.975891 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 11:36:36.979353 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 11:36:36.982877 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 11:36:36.983377 Pre-setting of DQS Precalculation
5946 11:36:36.988959 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 11:36:36.995250 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 11:36:37.002074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 11:36:37.002587
5950 11:36:37.002920
5951 11:36:37.005393 [Calibration Summary] 1866 Mbps
5952 11:36:37.008941 CH 0, Rank 0
5953 11:36:37.009452 SW Impedance : PASS
5954 11:36:37.012154 DUTY Scan : NO K
5955 11:36:37.015121 ZQ Calibration : PASS
5956 11:36:37.015593 Jitter Meter : NO K
5957 11:36:37.018304 CBT Training : PASS
5958 11:36:37.018731 Write leveling : PASS
5959 11:36:37.022354 RX DQS gating : PASS
5960 11:36:37.024865 RX DQ/DQS(RDDQC) : PASS
5961 11:36:37.025246 TX DQ/DQS : PASS
5962 11:36:37.028461 RX DATLAT : PASS
5963 11:36:37.032526 RX DQ/DQS(Engine): PASS
5964 11:36:37.033028 TX OE : NO K
5965 11:36:37.035460 All Pass.
5966 11:36:37.035880
5967 11:36:37.036206 CH 0, Rank 1
5968 11:36:37.038839 SW Impedance : PASS
5969 11:36:37.039266 DUTY Scan : NO K
5970 11:36:37.041642 ZQ Calibration : PASS
5971 11:36:37.045863 Jitter Meter : NO K
5972 11:36:37.046438 CBT Training : PASS
5973 11:36:37.049296 Write leveling : PASS
5974 11:36:37.051596 RX DQS gating : PASS
5975 11:36:37.052022 RX DQ/DQS(RDDQC) : PASS
5976 11:36:37.055194 TX DQ/DQS : PASS
5977 11:36:37.058779 RX DATLAT : PASS
5978 11:36:37.059251 RX DQ/DQS(Engine): PASS
5979 11:36:37.062127 TX OE : NO K
5980 11:36:37.062639 All Pass.
5981 11:36:37.062972
5982 11:36:37.065506 CH 1, Rank 0
5983 11:36:37.066053 SW Impedance : PASS
5984 11:36:37.068785 DUTY Scan : NO K
5985 11:36:37.071979 ZQ Calibration : PASS
5986 11:36:37.072415 Jitter Meter : NO K
5987 11:36:37.075562 CBT Training : PASS
5988 11:36:37.076074 Write leveling : PASS
5989 11:36:37.078948 RX DQS gating : PASS
5990 11:36:37.082140 RX DQ/DQS(RDDQC) : PASS
5991 11:36:37.082647 TX DQ/DQS : PASS
5992 11:36:37.085551 RX DATLAT : PASS
5993 11:36:37.088466 RX DQ/DQS(Engine): PASS
5994 11:36:37.088908 TX OE : NO K
5995 11:36:37.092164 All Pass.
5996 11:36:37.092664
5997 11:36:37.092997 CH 1, Rank 1
5998 11:36:37.095280 SW Impedance : PASS
5999 11:36:37.095706 DUTY Scan : NO K
6000 11:36:37.098467 ZQ Calibration : PASS
6001 11:36:37.101888 Jitter Meter : NO K
6002 11:36:37.102434 CBT Training : PASS
6003 11:36:37.105147 Write leveling : PASS
6004 11:36:37.108617 RX DQS gating : PASS
6005 11:36:37.109112 RX DQ/DQS(RDDQC) : PASS
6006 11:36:37.111129 TX DQ/DQS : PASS
6007 11:36:37.114947 RX DATLAT : PASS
6008 11:36:37.115442 RX DQ/DQS(Engine): PASS
6009 11:36:37.118056 TX OE : NO K
6010 11:36:37.118498 All Pass.
6011 11:36:37.118829
6012 11:36:37.121782 DramC Write-DBI off
6013 11:36:37.124716 PER_BANK_REFRESH: Hybrid Mode
6014 11:36:37.125140 TX_TRACKING: ON
6015 11:36:37.134693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 11:36:37.137672 [FAST_K] Save calibration result to emmc
6017 11:36:37.141073 dramc_set_vcore_voltage set vcore to 650000
6018 11:36:37.144411 Read voltage for 400, 6
6019 11:36:37.144791 Vio18 = 0
6020 11:36:37.145086 Vcore = 650000
6021 11:36:37.148060 Vdram = 0
6022 11:36:37.148440 Vddq = 0
6023 11:36:37.148736 Vmddr = 0
6024 11:36:37.154876 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 11:36:37.158089 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 11:36:37.161454 MEM_TYPE=3, freq_sel=20
6027 11:36:37.165129 sv_algorithm_assistance_LP4_800
6028 11:36:37.168218 ============ PULL DRAM RESETB DOWN ============
6029 11:36:37.171381 ========== PULL DRAM RESETB DOWN end =========
6030 11:36:37.177781 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 11:36:37.181844 ===================================
6032 11:36:37.182347 LPDDR4 DRAM CONFIGURATION
6033 11:36:37.185017 ===================================
6034 11:36:37.188131 EX_ROW_EN[0] = 0x0
6035 11:36:37.191333 EX_ROW_EN[1] = 0x0
6036 11:36:37.191758 LP4Y_EN = 0x0
6037 11:36:37.194533 WORK_FSP = 0x0
6038 11:36:37.194958 WL = 0x2
6039 11:36:37.197875 RL = 0x2
6040 11:36:37.198312 BL = 0x2
6041 11:36:37.201563 RPST = 0x0
6042 11:36:37.202090 RD_PRE = 0x0
6043 11:36:37.204677 WR_PRE = 0x1
6044 11:36:37.205117 WR_PST = 0x0
6045 11:36:37.207893 DBI_WR = 0x0
6046 11:36:37.208278 DBI_RD = 0x0
6047 11:36:37.210955 OTF = 0x1
6048 11:36:37.214593 ===================================
6049 11:36:37.218108 ===================================
6050 11:36:37.218616 ANA top config
6051 11:36:37.221062 ===================================
6052 11:36:37.224117 DLL_ASYNC_EN = 0
6053 11:36:37.227443 ALL_SLAVE_EN = 1
6054 11:36:37.227827 NEW_RANK_MODE = 1
6055 11:36:37.231142 DLL_IDLE_MODE = 1
6056 11:36:37.234368 LP45_APHY_COMB_EN = 1
6057 11:36:37.237595 TX_ODT_DIS = 1
6058 11:36:37.240996 NEW_8X_MODE = 1
6059 11:36:37.244485 ===================================
6060 11:36:37.247694 ===================================
6061 11:36:37.248092 data_rate = 800
6062 11:36:37.251160 CKR = 1
6063 11:36:37.254569 DQ_P2S_RATIO = 4
6064 11:36:37.257509 ===================================
6065 11:36:37.260493 CA_P2S_RATIO = 4
6066 11:36:37.264277 DQ_CA_OPEN = 0
6067 11:36:37.267832 DQ_SEMI_OPEN = 1
6068 11:36:37.268287 CA_SEMI_OPEN = 1
6069 11:36:37.270910 CA_FULL_RATE = 0
6070 11:36:37.274672 DQ_CKDIV4_EN = 0
6071 11:36:37.277830 CA_CKDIV4_EN = 1
6072 11:36:37.281013 CA_PREDIV_EN = 0
6073 11:36:37.284401 PH8_DLY = 0
6074 11:36:37.284855 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 11:36:37.287634 DQ_AAMCK_DIV = 0
6076 11:36:37.290622 CA_AAMCK_DIV = 0
6077 11:36:37.294439 CA_ADMCK_DIV = 4
6078 11:36:37.297167 DQ_TRACK_CA_EN = 0
6079 11:36:37.301285 CA_PICK = 800
6080 11:36:37.304510 CA_MCKIO = 400
6081 11:36:37.305002 MCKIO_SEMI = 400
6082 11:36:37.307330 PLL_FREQ = 3016
6083 11:36:37.310888 DQ_UI_PI_RATIO = 32
6084 11:36:37.314170 CA_UI_PI_RATIO = 32
6085 11:36:37.317275 ===================================
6086 11:36:37.320832 ===================================
6087 11:36:37.323675 memory_type:LPDDR4
6088 11:36:37.324057 GP_NUM : 10
6089 11:36:37.326866 SRAM_EN : 1
6090 11:36:37.330511 MD32_EN : 0
6091 11:36:37.333691 ===================================
6092 11:36:37.334113 [ANA_INIT] >>>>>>>>>>>>>>
6093 11:36:37.337736 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 11:36:37.340967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 11:36:37.343929 ===================================
6096 11:36:37.347052 data_rate = 800,PCW = 0X7400
6097 11:36:37.350631 ===================================
6098 11:36:37.353783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 11:36:37.360996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 11:36:37.371006 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 11:36:37.373575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 11:36:37.377190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 11:36:37.380845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 11:36:37.383818 [ANA_INIT] flow start
6105 11:36:37.387231 [ANA_INIT] PLL >>>>>>>>
6106 11:36:37.387699 [ANA_INIT] PLL <<<<<<<<
6107 11:36:37.390419 [ANA_INIT] MIDPI >>>>>>>>
6108 11:36:37.394270 [ANA_INIT] MIDPI <<<<<<<<
6109 11:36:37.397606 [ANA_INIT] DLL >>>>>>>>
6110 11:36:37.398158 [ANA_INIT] flow end
6111 11:36:37.400894 ============ LP4 DIFF to SE enter ============
6112 11:36:37.407363 ============ LP4 DIFF to SE exit ============
6113 11:36:37.407875 [ANA_INIT] <<<<<<<<<<<<<
6114 11:36:37.410605 [Flow] Enable top DCM control >>>>>
6115 11:36:37.413898 [Flow] Enable top DCM control <<<<<
6116 11:36:37.417103 Enable DLL master slave shuffle
6117 11:36:37.423368 ==============================================================
6118 11:36:37.423811 Gating Mode config
6119 11:36:37.430468 ==============================================================
6120 11:36:37.433496 Config description:
6121 11:36:37.443419 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 11:36:37.450176 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 11:36:37.454061 SELPH_MODE 0: By rank 1: By Phase
6124 11:36:37.460143 ==============================================================
6125 11:36:37.463843 GAT_TRACK_EN = 0
6126 11:36:37.464286 RX_GATING_MODE = 2
6127 11:36:37.467007 RX_GATING_TRACK_MODE = 2
6128 11:36:37.470341 SELPH_MODE = 1
6129 11:36:37.473549 PICG_EARLY_EN = 1
6130 11:36:37.476979 VALID_LAT_VALUE = 1
6131 11:36:37.483646 ==============================================================
6132 11:36:37.486810 Enter into Gating configuration >>>>
6133 11:36:37.490393 Exit from Gating configuration <<<<
6134 11:36:37.493883 Enter into DVFS_PRE_config >>>>>
6135 11:36:37.504024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 11:36:37.507347 Exit from DVFS_PRE_config <<<<<
6137 11:36:37.510660 Enter into PICG configuration >>>>
6138 11:36:37.513941 Exit from PICG configuration <<<<
6139 11:36:37.516855 [RX_INPUT] configuration >>>>>
6140 11:36:37.520475 [RX_INPUT] configuration <<<<<
6141 11:36:37.523345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 11:36:37.530429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 11:36:37.536540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 11:36:37.540698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 11:36:37.546917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 11:36:37.553448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 11:36:37.557284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 11:36:37.559806 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 11:36:37.566524 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 11:36:37.570274 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 11:36:37.573466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 11:36:37.580424 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 11:36:37.583870 ===================================
6154 11:36:37.584342 LPDDR4 DRAM CONFIGURATION
6155 11:36:37.586943 ===================================
6156 11:36:37.589800 EX_ROW_EN[0] = 0x0
6157 11:36:37.590221 EX_ROW_EN[1] = 0x0
6158 11:36:37.593420 LP4Y_EN = 0x0
6159 11:36:37.593808 WORK_FSP = 0x0
6160 11:36:37.597022 WL = 0x2
6161 11:36:37.600608 RL = 0x2
6162 11:36:37.601069 BL = 0x2
6163 11:36:37.603493 RPST = 0x0
6164 11:36:37.603879 RD_PRE = 0x0
6165 11:36:37.606896 WR_PRE = 0x1
6166 11:36:37.607400 WR_PST = 0x0
6167 11:36:37.610476 DBI_WR = 0x0
6168 11:36:37.610982 DBI_RD = 0x0
6169 11:36:37.613657 OTF = 0x1
6170 11:36:37.616715 ===================================
6171 11:36:37.619998 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 11:36:37.623285 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 11:36:37.626578 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 11:36:37.630467 ===================================
6175 11:36:37.633527 LPDDR4 DRAM CONFIGURATION
6176 11:36:37.637386 ===================================
6177 11:36:37.640083 EX_ROW_EN[0] = 0x10
6178 11:36:37.640588 EX_ROW_EN[1] = 0x0
6179 11:36:37.643316 LP4Y_EN = 0x0
6180 11:36:37.643848 WORK_FSP = 0x0
6181 11:36:37.646528 WL = 0x2
6182 11:36:37.646955 RL = 0x2
6183 11:36:37.649933 BL = 0x2
6184 11:36:37.650472 RPST = 0x0
6185 11:36:37.652952 RD_PRE = 0x0
6186 11:36:37.656280 WR_PRE = 0x1
6187 11:36:37.656706 WR_PST = 0x0
6188 11:36:37.660038 DBI_WR = 0x0
6189 11:36:37.660443 DBI_RD = 0x0
6190 11:36:37.663213 OTF = 0x1
6191 11:36:37.666761 ===================================
6192 11:36:37.670540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 11:36:37.675401 nWR fixed to 30
6194 11:36:37.678188 [ModeRegInit_LP4] CH0 RK0
6195 11:36:37.678568 [ModeRegInit_LP4] CH0 RK1
6196 11:36:37.681980 [ModeRegInit_LP4] CH1 RK0
6197 11:36:37.685235 [ModeRegInit_LP4] CH1 RK1
6198 11:36:37.685733 match AC timing 19
6199 11:36:37.691966 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 11:36:37.694976 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 11:36:37.698362 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 11:36:37.705267 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 11:36:37.708575 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 11:36:37.709071 ==
6205 11:36:37.711455 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 11:36:37.715194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 11:36:37.715661 ==
6208 11:36:37.721436 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 11:36:37.728745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 11:36:37.731916 [CA 0] Center 36 (8~64) winsize 57
6211 11:36:37.735323 [CA 1] Center 36 (8~64) winsize 57
6212 11:36:37.738681 [CA 2] Center 36 (8~64) winsize 57
6213 11:36:37.739203 [CA 3] Center 36 (8~64) winsize 57
6214 11:36:37.741876 [CA 4] Center 36 (8~64) winsize 57
6215 11:36:37.745100 [CA 5] Center 36 (8~64) winsize 57
6216 11:36:37.745614
6217 11:36:37.752066 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 11:36:37.752557
6219 11:36:37.754842 [CATrainingPosCal] consider 1 rank data
6220 11:36:37.758207 u2DelayCellTimex100 = 270/100 ps
6221 11:36:37.761024 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:36:37.764994 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:36:37.768171 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:36:37.771374 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:36:37.775121 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:36:37.778400 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:36:37.778861
6228 11:36:37.781795 CA PerBit enable=1, Macro0, CA PI delay=36
6229 11:36:37.782306
6230 11:36:37.785341 [CBTSetCACLKResult] CA Dly = 36
6231 11:36:37.788373 CS Dly: 1 (0~32)
6232 11:36:37.788871 ==
6233 11:36:37.791242 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 11:36:37.794738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 11:36:37.795138 ==
6236 11:36:37.801505 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 11:36:37.804723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 11:36:37.808042 [CA 0] Center 36 (8~64) winsize 57
6239 11:36:37.811249 [CA 1] Center 36 (8~64) winsize 57
6240 11:36:37.814954 [CA 2] Center 36 (8~64) winsize 57
6241 11:36:37.817753 [CA 3] Center 36 (8~64) winsize 57
6242 11:36:37.821410 [CA 4] Center 36 (8~64) winsize 57
6243 11:36:37.824974 [CA 5] Center 36 (8~64) winsize 57
6244 11:36:37.825363
6245 11:36:37.828166 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 11:36:37.828545
6247 11:36:37.831428 [CATrainingPosCal] consider 2 rank data
6248 11:36:37.834891 u2DelayCellTimex100 = 270/100 ps
6249 11:36:37.837957 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:36:37.841492 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:36:37.844595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:36:37.851211 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:36:37.854720 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:36:37.858130 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:36:37.858585
6256 11:36:37.861370 CA PerBit enable=1, Macro0, CA PI delay=36
6257 11:36:37.861748
6258 11:36:37.865176 [CBTSetCACLKResult] CA Dly = 36
6259 11:36:37.865555 CS Dly: 1 (0~32)
6260 11:36:37.865849
6261 11:36:37.868050 ----->DramcWriteLeveling(PI) begin...
6262 11:36:37.868434 ==
6263 11:36:37.871146 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 11:36:37.877896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:36:37.878421 ==
6266 11:36:37.881241 Write leveling (Byte 0): 40 => 8
6267 11:36:37.881620 Write leveling (Byte 1): 40 => 8
6268 11:36:37.884911 DramcWriteLeveling(PI) end<-----
6269 11:36:37.885550
6270 11:36:37.885883 ==
6271 11:36:37.888262 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 11:36:37.894711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 11:36:37.895161 ==
6274 11:36:37.898131 [Gating] SW mode calibration
6275 11:36:37.905004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 11:36:37.908692 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 11:36:37.914457 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 11:36:37.918049 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 11:36:37.921551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 11:36:37.928009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 11:36:37.930882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:36:37.934228 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:36:37.941420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:36:37.944522 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 11:36:37.947597 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 11:36:37.950882 Total UI for P1: 0, mck2ui 16
6287 11:36:37.954518 best dqsien dly found for B0: ( 0, 14, 24)
6288 11:36:37.957792 Total UI for P1: 0, mck2ui 16
6289 11:36:37.960887 best dqsien dly found for B1: ( 0, 14, 24)
6290 11:36:37.964458 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 11:36:37.967804 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 11:36:37.968282
6293 11:36:37.971052 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 11:36:37.977662 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 11:36:37.978185 [Gating] SW calibration Done
6296 11:36:37.980946 ==
6297 11:36:37.981343 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 11:36:37.987843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 11:36:37.988325 ==
6300 11:36:37.988737 RX Vref Scan: 0
6301 11:36:37.989118
6302 11:36:37.991368 RX Vref 0 -> 0, step: 1
6303 11:36:37.991850
6304 11:36:37.994360 RX Delay -410 -> 252, step: 16
6305 11:36:37.997771 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6306 11:36:38.000937 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6307 11:36:38.007697 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6308 11:36:38.010632 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6309 11:36:38.014321 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6310 11:36:38.017410 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6311 11:36:38.024260 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6312 11:36:38.027628 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6313 11:36:38.030791 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6314 11:36:38.033985 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6315 11:36:38.040564 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6316 11:36:38.044085 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6317 11:36:38.047400 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6318 11:36:38.050582 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6319 11:36:38.057707 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6320 11:36:38.060838 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6321 11:36:38.061215 ==
6322 11:36:38.064321 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 11:36:38.068081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 11:36:38.068543 ==
6325 11:36:38.070577 DQS Delay:
6326 11:36:38.070956 DQS0 = 27, DQS1 = 35
6327 11:36:38.071250 DQM Delay:
6328 11:36:38.074721 DQM0 = 13, DQM1 = 16
6329 11:36:38.075180 DQ Delay:
6330 11:36:38.078132 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =0
6331 11:36:38.081319 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6332 11:36:38.084584 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6333 11:36:38.087830 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6334 11:36:38.088294
6335 11:36:38.088591
6336 11:36:38.088865 ==
6337 11:36:38.090876 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 11:36:38.094374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:36:38.097419 ==
6340 11:36:38.097879
6341 11:36:38.098212
6342 11:36:38.098486 TX Vref Scan disable
6343 11:36:38.101372 == TX Byte 0 ==
6344 11:36:38.104359 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 11:36:38.108085 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 11:36:38.111142 == TX Byte 1 ==
6347 11:36:38.114218 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 11:36:38.117511 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 11:36:38.117901 ==
6350 11:36:38.120955 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 11:36:38.124068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 11:36:38.127956 ==
6353 11:36:38.128334
6354 11:36:38.128622
6355 11:36:38.128891 TX Vref Scan disable
6356 11:36:38.130523 == TX Byte 0 ==
6357 11:36:38.134417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 11:36:38.137738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 11:36:38.140991 == TX Byte 1 ==
6360 11:36:38.144277 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 11:36:38.147284 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 11:36:38.147668
6363 11:36:38.147961 [DATLAT]
6364 11:36:38.151500 Freq=400, CH0 RK0
6365 11:36:38.151983
6366 11:36:38.154826 DATLAT Default: 0xf
6367 11:36:38.155289 0, 0xFFFF, sum = 0
6368 11:36:38.157819 1, 0xFFFF, sum = 0
6369 11:36:38.158344 2, 0xFFFF, sum = 0
6370 11:36:38.160926 3, 0xFFFF, sum = 0
6371 11:36:38.161334 4, 0xFFFF, sum = 0
6372 11:36:38.164046 5, 0xFFFF, sum = 0
6373 11:36:38.164435 6, 0xFFFF, sum = 0
6374 11:36:38.167717 7, 0xFFFF, sum = 0
6375 11:36:38.168182 8, 0xFFFF, sum = 0
6376 11:36:38.171053 9, 0xFFFF, sum = 0
6377 11:36:38.171441 10, 0xFFFF, sum = 0
6378 11:36:38.174187 11, 0xFFFF, sum = 0
6379 11:36:38.174575 12, 0xFFFF, sum = 0
6380 11:36:38.177510 13, 0x0, sum = 1
6381 11:36:38.177977 14, 0x0, sum = 2
6382 11:36:38.181162 15, 0x0, sum = 3
6383 11:36:38.181628 16, 0x0, sum = 4
6384 11:36:38.184025 best_step = 14
6385 11:36:38.184409
6386 11:36:38.184721 ==
6387 11:36:38.187926 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 11:36:38.190743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 11:36:38.191130 ==
6390 11:36:38.194691 RX Vref Scan: 1
6391 11:36:38.195158
6392 11:36:38.195455 RX Vref 0 -> 0, step: 1
6393 11:36:38.195736
6394 11:36:38.197817 RX Delay -311 -> 252, step: 8
6395 11:36:38.198273
6396 11:36:38.201649 Set Vref, RX VrefLevel [Byte0]: 54
6397 11:36:38.204158 [Byte1]: 48
6398 11:36:38.208767
6399 11:36:38.209225 Final RX Vref Byte 0 = 54 to rank0
6400 11:36:38.211680 Final RX Vref Byte 1 = 48 to rank0
6401 11:36:38.215234 Final RX Vref Byte 0 = 54 to rank1
6402 11:36:38.218034 Final RX Vref Byte 1 = 48 to rank1==
6403 11:36:38.221422 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:36:38.228200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:36:38.228600 ==
6406 11:36:38.228897 DQS Delay:
6407 11:36:38.231389 DQS0 = 28, DQS1 = 36
6408 11:36:38.231732 DQM Delay:
6409 11:36:38.232014 DQM0 = 10, DQM1 = 12
6410 11:36:38.234715 DQ Delay:
6411 11:36:38.238674 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6412 11:36:38.239062 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6413 11:36:38.241448 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6414 11:36:38.244804 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6415 11:36:38.245249
6416 11:36:38.247915
6417 11:36:38.254467 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7c3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6418 11:36:38.257643 CH0 RK0: MR19=C0C, MR18=D7C3
6419 11:36:38.265144 CH0_RK0: MR19=0xC0C, MR18=0xD7C3, DQSOSC=383, MR23=63, INC=402, DEC=268
6420 11:36:38.265624 ==
6421 11:36:38.268354 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 11:36:38.271583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 11:36:38.272043 ==
6424 11:36:38.274648 [Gating] SW mode calibration
6425 11:36:38.281170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 11:36:38.287975 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 11:36:38.291417 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 11:36:38.294700 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 11:36:38.301311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 11:36:38.304641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 11:36:38.308328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:36:38.311329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:36:38.318049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:36:38.321201 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:36:38.324374 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 11:36:38.328329 Total UI for P1: 0, mck2ui 16
6437 11:36:38.331084 best dqsien dly found for B0: ( 0, 14, 24)
6438 11:36:38.334632 Total UI for P1: 0, mck2ui 16
6439 11:36:38.338169 best dqsien dly found for B1: ( 0, 14, 24)
6440 11:36:38.341440 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 11:36:38.344684 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 11:36:38.347610
6443 11:36:38.351388 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 11:36:38.354694 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 11:36:38.358114 [Gating] SW calibration Done
6446 11:36:38.358491 ==
6447 11:36:38.361517 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 11:36:38.364857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 11:36:38.365239 ==
6450 11:36:38.365534 RX Vref Scan: 0
6451 11:36:38.365810
6452 11:36:38.367973 RX Vref 0 -> 0, step: 1
6453 11:36:38.368348
6454 11:36:38.371310 RX Delay -410 -> 252, step: 16
6455 11:36:38.374851 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6456 11:36:38.381534 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6457 11:36:38.385016 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6458 11:36:38.388353 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6459 11:36:38.391240 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6460 11:36:38.398268 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6461 11:36:38.401486 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6462 11:36:38.404803 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6463 11:36:38.407949 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6464 11:36:38.411569 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6465 11:36:38.418178 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6466 11:36:38.421069 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6467 11:36:38.424316 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6468 11:36:38.430848 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6469 11:36:38.434363 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6470 11:36:38.437656 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6471 11:36:38.438141 ==
6472 11:36:38.441160 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 11:36:38.444719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 11:36:38.445308 ==
6475 11:36:38.448194 DQS Delay:
6476 11:36:38.448572 DQS0 = 27, DQS1 = 35
6477 11:36:38.450905 DQM Delay:
6478 11:36:38.451282 DQM0 = 12, DQM1 = 11
6479 11:36:38.454357 DQ Delay:
6480 11:36:38.454812 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6481 11:36:38.458098 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6482 11:36:38.461225 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6483 11:36:38.464612 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6484 11:36:38.465079
6485 11:36:38.465379
6486 11:36:38.465653 ==
6487 11:36:38.467594 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 11:36:38.474538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 11:36:38.474987 ==
6490 11:36:38.475292
6491 11:36:38.475571
6492 11:36:38.475835 TX Vref Scan disable
6493 11:36:38.477841 == TX Byte 0 ==
6494 11:36:38.480984 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6495 11:36:38.484264 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6496 11:36:38.487833 == TX Byte 1 ==
6497 11:36:38.491156 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6498 11:36:38.494563 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6499 11:36:38.494952 ==
6500 11:36:38.497849 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 11:36:38.504424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 11:36:38.504819 ==
6503 11:36:38.505122
6504 11:36:38.505399
6505 11:36:38.505667 TX Vref Scan disable
6506 11:36:38.507761 == TX Byte 0 ==
6507 11:36:38.510869 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6508 11:36:38.514945 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6509 11:36:38.517812 == TX Byte 1 ==
6510 11:36:38.521317 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6511 11:36:38.524538 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6512 11:36:38.524926
6513 11:36:38.527807 [DATLAT]
6514 11:36:38.528194 Freq=400, CH0 RK1
6515 11:36:38.528497
6516 11:36:38.530952 DATLAT Default: 0xe
6517 11:36:38.531475 0, 0xFFFF, sum = 0
6518 11:36:38.534466 1, 0xFFFF, sum = 0
6519 11:36:38.534876 2, 0xFFFF, sum = 0
6520 11:36:38.537773 3, 0xFFFF, sum = 0
6521 11:36:38.538297 4, 0xFFFF, sum = 0
6522 11:36:38.540985 5, 0xFFFF, sum = 0
6523 11:36:38.541403 6, 0xFFFF, sum = 0
6524 11:36:38.544503 7, 0xFFFF, sum = 0
6525 11:36:38.544893 8, 0xFFFF, sum = 0
6526 11:36:38.547409 9, 0xFFFF, sum = 0
6527 11:36:38.547972 10, 0xFFFF, sum = 0
6528 11:36:38.551001 11, 0xFFFF, sum = 0
6529 11:36:38.554048 12, 0xFFFF, sum = 0
6530 11:36:38.554462 13, 0x0, sum = 1
6531 11:36:38.554871 14, 0x0, sum = 2
6532 11:36:38.557497 15, 0x0, sum = 3
6533 11:36:38.557902 16, 0x0, sum = 4
6534 11:36:38.560884 best_step = 14
6535 11:36:38.561279
6536 11:36:38.561766 ==
6537 11:36:38.564393 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 11:36:38.567827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 11:36:38.568228 ==
6540 11:36:38.571206 RX Vref Scan: 0
6541 11:36:38.571681
6542 11:36:38.572085 RX Vref 0 -> 0, step: 1
6543 11:36:38.572457
6544 11:36:38.574190 RX Delay -311 -> 252, step: 8
6545 11:36:38.582387 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6546 11:36:38.585795 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6547 11:36:38.589317 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6548 11:36:38.592144 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6549 11:36:38.599219 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6550 11:36:38.602407 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6551 11:36:38.606092 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6552 11:36:38.608800 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6553 11:36:38.616049 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6554 11:36:38.619133 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6555 11:36:38.622461 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6556 11:36:38.625423 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6557 11:36:38.632369 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6558 11:36:38.635621 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6559 11:36:38.639050 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6560 11:36:38.643019 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6561 11:36:38.646190 ==
6562 11:36:38.649308 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 11:36:38.652534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 11:36:38.652925 ==
6565 11:36:38.653227 DQS Delay:
6566 11:36:38.655646 DQS0 = 24, DQS1 = 32
6567 11:36:38.656031 DQM Delay:
6568 11:36:38.658908 DQM0 = 8, DQM1 = 9
6569 11:36:38.659293 DQ Delay:
6570 11:36:38.662387 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6571 11:36:38.665901 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6572 11:36:38.666427 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6573 11:36:38.672500 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6574 11:36:38.672887
6575 11:36:38.673186
6576 11:36:38.678884 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6577 11:36:38.681954 CH0 RK1: MR19=C0C, MR18=BD5D
6578 11:36:38.688587 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6579 11:36:38.691828 [RxdqsGatingPostProcess] freq 400
6580 11:36:38.695683 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 11:36:38.698924 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 11:36:38.702441 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 11:36:38.705505 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 11:36:38.708919 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 11:36:38.711942 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 11:36:38.715771 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 11:36:38.718799 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 11:36:38.721639 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 11:36:38.725215 Pre-setting of DQS Precalculation
6590 11:36:38.728561 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 11:36:38.728962 ==
6592 11:36:38.731679 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 11:36:38.738816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:36:38.739298 ==
6595 11:36:38.742084 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 11:36:38.748535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6597 11:36:38.751851 [CA 0] Center 36 (8~64) winsize 57
6598 11:36:38.755487 [CA 1] Center 36 (8~64) winsize 57
6599 11:36:38.758591 [CA 2] Center 36 (8~64) winsize 57
6600 11:36:38.761699 [CA 3] Center 36 (8~64) winsize 57
6601 11:36:38.765271 [CA 4] Center 36 (8~64) winsize 57
6602 11:36:38.768994 [CA 5] Center 36 (8~64) winsize 57
6603 11:36:38.769475
6604 11:36:38.771948 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6605 11:36:38.772347
6606 11:36:38.775337 [CATrainingPosCal] consider 1 rank data
6607 11:36:38.778978 u2DelayCellTimex100 = 270/100 ps
6608 11:36:38.781968 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:36:38.785410 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:36:38.788939 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:36:38.791663 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:36:38.795431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:36:38.798471 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:36:38.798889
6615 11:36:38.805136 CA PerBit enable=1, Macro0, CA PI delay=36
6616 11:36:38.805618
6617 11:36:38.809141 [CBTSetCACLKResult] CA Dly = 36
6618 11:36:38.809618 CS Dly: 1 (0~32)
6619 11:36:38.810055 ==
6620 11:36:38.812482 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 11:36:38.815748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 11:36:38.816224 ==
6623 11:36:38.821928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 11:36:38.828238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6625 11:36:38.831698 [CA 0] Center 36 (8~64) winsize 57
6626 11:36:38.835006 [CA 1] Center 36 (8~64) winsize 57
6627 11:36:38.838236 [CA 2] Center 36 (8~64) winsize 57
6628 11:36:38.841938 [CA 3] Center 36 (8~64) winsize 57
6629 11:36:38.844788 [CA 4] Center 36 (8~64) winsize 57
6630 11:36:38.845265 [CA 5] Center 36 (8~64) winsize 57
6631 11:36:38.848448
6632 11:36:38.851466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6633 11:36:38.851864
6634 11:36:38.854825 [CATrainingPosCal] consider 2 rank data
6635 11:36:38.857987 u2DelayCellTimex100 = 270/100 ps
6636 11:36:38.861727 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:36:38.864890 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:36:38.868323 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:36:38.871680 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:36:38.874869 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:36:38.877810 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:36:38.878250
6643 11:36:38.881581 CA PerBit enable=1, Macro0, CA PI delay=36
6644 11:36:38.882095
6645 11:36:38.884634 [CBTSetCACLKResult] CA Dly = 36
6646 11:36:38.888261 CS Dly: 1 (0~32)
6647 11:36:38.888738
6648 11:36:38.891221 ----->DramcWriteLeveling(PI) begin...
6649 11:36:38.891625 ==
6650 11:36:38.894719 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 11:36:38.897859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:36:38.898309 ==
6653 11:36:38.901120 Write leveling (Byte 0): 40 => 8
6654 11:36:38.904686 Write leveling (Byte 1): 40 => 8
6655 11:36:38.908345 DramcWriteLeveling(PI) end<-----
6656 11:36:38.908824
6657 11:36:38.909228 ==
6658 11:36:38.911241 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 11:36:38.914802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:36:38.915277 ==
6661 11:36:38.917813 [Gating] SW mode calibration
6662 11:36:38.924553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 11:36:38.931360 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 11:36:38.934575 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 11:36:38.941426 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 11:36:38.944537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 11:36:38.947931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 11:36:38.951309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:36:38.957559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:36:38.961068 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:36:38.964951 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 11:36:38.971508 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 11:36:38.974402 Total UI for P1: 0, mck2ui 16
6674 11:36:38.977902 best dqsien dly found for B0: ( 0, 14, 24)
6675 11:36:38.978398 Total UI for P1: 0, mck2ui 16
6676 11:36:38.984586 best dqsien dly found for B1: ( 0, 14, 24)
6677 11:36:38.987816 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 11:36:38.991518 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 11:36:38.992021
6680 11:36:38.994508 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 11:36:38.998468 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 11:36:39.001673 [Gating] SW calibration Done
6683 11:36:39.002194 ==
6684 11:36:39.005111 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 11:36:39.008245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 11:36:39.008757 ==
6687 11:36:39.011473 RX Vref Scan: 0
6688 11:36:39.011962
6689 11:36:39.012289 RX Vref 0 -> 0, step: 1
6690 11:36:39.012592
6691 11:36:39.014553 RX Delay -410 -> 252, step: 16
6692 11:36:39.021195 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6693 11:36:39.024423 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6694 11:36:39.027471 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6695 11:36:39.030810 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6696 11:36:39.037270 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6697 11:36:39.040854 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6698 11:36:39.044886 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6699 11:36:39.047269 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6700 11:36:39.053922 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6701 11:36:39.057290 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6702 11:36:39.060649 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6703 11:36:39.064507 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6704 11:36:39.071284 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6705 11:36:39.074470 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6706 11:36:39.077668 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6707 11:36:39.080940 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6708 11:36:39.083957 ==
6709 11:36:39.084514 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 11:36:39.091030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 11:36:39.091414 ==
6712 11:36:39.091710 DQS Delay:
6713 11:36:39.094230 DQS0 = 35, DQS1 = 35
6714 11:36:39.094609 DQM Delay:
6715 11:36:39.097421 DQM0 = 16, DQM1 = 13
6716 11:36:39.097868 DQ Delay:
6717 11:36:39.100666 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6718 11:36:39.103806 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =8
6719 11:36:39.107685 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6720 11:36:39.110837 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6721 11:36:39.111239
6722 11:36:39.111540
6723 11:36:39.111838 ==
6724 11:36:39.114431 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 11:36:39.117106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:36:39.117572 ==
6727 11:36:39.118045
6728 11:36:39.118336
6729 11:36:39.120483 TX Vref Scan disable
6730 11:36:39.120991 == TX Byte 0 ==
6731 11:36:39.127217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 11:36:39.130497 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 11:36:39.130880 == TX Byte 1 ==
6734 11:36:39.133822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 11:36:39.140398 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 11:36:39.140696 ==
6737 11:36:39.143670 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 11:36:39.147179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 11:36:39.147471 ==
6740 11:36:39.147681
6741 11:36:39.147894
6742 11:36:39.150711 TX Vref Scan disable
6743 11:36:39.150979 == TX Byte 0 ==
6744 11:36:39.157395 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 11:36:39.160764 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 11:36:39.161057 == TX Byte 1 ==
6747 11:36:39.166976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 11:36:39.170971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 11:36:39.171258
6750 11:36:39.171473 [DATLAT]
6751 11:36:39.173809 Freq=400, CH1 RK0
6752 11:36:39.174108
6753 11:36:39.174323 DATLAT Default: 0xf
6754 11:36:39.177233 0, 0xFFFF, sum = 0
6755 11:36:39.177508 1, 0xFFFF, sum = 0
6756 11:36:39.180563 2, 0xFFFF, sum = 0
6757 11:36:39.180914 3, 0xFFFF, sum = 0
6758 11:36:39.184235 4, 0xFFFF, sum = 0
6759 11:36:39.184521 5, 0xFFFF, sum = 0
6760 11:36:39.187254 6, 0xFFFF, sum = 0
6761 11:36:39.187533 7, 0xFFFF, sum = 0
6762 11:36:39.190391 8, 0xFFFF, sum = 0
6763 11:36:39.190837 9, 0xFFFF, sum = 0
6764 11:36:39.193591 10, 0xFFFF, sum = 0
6765 11:36:39.193998 11, 0xFFFF, sum = 0
6766 11:36:39.196951 12, 0xFFFF, sum = 0
6767 11:36:39.197411 13, 0x0, sum = 1
6768 11:36:39.200351 14, 0x0, sum = 2
6769 11:36:39.200767 15, 0x0, sum = 3
6770 11:36:39.204270 16, 0x0, sum = 4
6771 11:36:39.204677 best_step = 14
6772 11:36:39.205003
6773 11:36:39.205222 ==
6774 11:36:39.207268 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 11:36:39.213572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 11:36:39.213648 ==
6777 11:36:39.213707 RX Vref Scan: 1
6778 11:36:39.213761
6779 11:36:39.217130 RX Vref 0 -> 0, step: 1
6780 11:36:39.217204
6781 11:36:39.220571 RX Delay -311 -> 252, step: 8
6782 11:36:39.220656
6783 11:36:39.223746 Set Vref, RX VrefLevel [Byte0]: 55
6784 11:36:39.227251 [Byte1]: 52
6785 11:36:39.227329
6786 11:36:39.229985 Final RX Vref Byte 0 = 55 to rank0
6787 11:36:39.233760 Final RX Vref Byte 1 = 52 to rank0
6788 11:36:39.237052 Final RX Vref Byte 0 = 55 to rank1
6789 11:36:39.240562 Final RX Vref Byte 1 = 52 to rank1==
6790 11:36:39.243481 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:36:39.246668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:36:39.246754 ==
6793 11:36:39.249934 DQS Delay:
6794 11:36:39.250062 DQS0 = 32, DQS1 = 32
6795 11:36:39.253500 DQM Delay:
6796 11:36:39.253599 DQM0 = 13, DQM1 = 10
6797 11:36:39.256718 DQ Delay:
6798 11:36:39.256851 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6799 11:36:39.260061 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6800 11:36:39.263974 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6801 11:36:39.267035 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6802 11:36:39.267195
6803 11:36:39.267331
6804 11:36:39.277141 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6805 11:36:39.280697 CH1 RK0: MR19=C0C, MR18=94CC
6806 11:36:39.283610 CH1_RK0: MR19=0xC0C, MR18=0x94CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6807 11:36:39.287193 ==
6808 11:36:39.290569 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 11:36:39.293905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 11:36:39.294209 ==
6811 11:36:39.297593 [Gating] SW mode calibration
6812 11:36:39.303611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 11:36:39.307324 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 11:36:39.313683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 11:36:39.316802 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 11:36:39.319898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 11:36:39.326936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 11:36:39.330063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:36:39.334101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:36:39.339958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 11:36:39.344113 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 11:36:39.346765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 11:36:39.350438 Total UI for P1: 0, mck2ui 16
6824 11:36:39.353446 best dqsien dly found for B0: ( 0, 14, 24)
6825 11:36:39.356521 Total UI for P1: 0, mck2ui 16
6826 11:36:39.360479 best dqsien dly found for B1: ( 0, 14, 24)
6827 11:36:39.363632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 11:36:39.367101 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 11:36:39.367487
6830 11:36:39.370319 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 11:36:39.376790 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 11:36:39.377250 [Gating] SW calibration Done
6833 11:36:39.380997 ==
6834 11:36:39.381471 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 11:36:39.387296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 11:36:39.387791 ==
6837 11:36:39.388103 RX Vref Scan: 0
6838 11:36:39.388380
6839 11:36:39.390261 RX Vref 0 -> 0, step: 1
6840 11:36:39.390646
6841 11:36:39.393947 RX Delay -410 -> 252, step: 16
6842 11:36:39.397345 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6843 11:36:39.400507 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6844 11:36:39.407272 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6845 11:36:39.410690 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6846 11:36:39.413459 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6847 11:36:39.417133 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6848 11:36:39.423257 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6849 11:36:39.426754 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6850 11:36:39.430388 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6851 11:36:39.433789 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6852 11:36:39.439760 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6853 11:36:39.443475 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6854 11:36:39.446808 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6855 11:36:39.450101 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6856 11:36:39.456930 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6857 11:36:39.460317 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6858 11:36:39.460862 ==
6859 11:36:39.463517 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 11:36:39.467050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 11:36:39.467439 ==
6862 11:36:39.470286 DQS Delay:
6863 11:36:39.470671 DQS0 = 35, DQS1 = 35
6864 11:36:39.473493 DQM Delay:
6865 11:36:39.473886 DQM0 = 17, DQM1 = 14
6866 11:36:39.474343 DQ Delay:
6867 11:36:39.476694 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6868 11:36:39.480008 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6869 11:36:39.483203 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6870 11:36:39.486453 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6871 11:36:39.486966
6872 11:36:39.487275
6873 11:36:39.487680 ==
6874 11:36:39.490169 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 11:36:39.496857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 11:36:39.497321 ==
6877 11:36:39.497621
6878 11:36:39.497895
6879 11:36:39.498218 TX Vref Scan disable
6880 11:36:39.499903 == TX Byte 0 ==
6881 11:36:39.504131 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6882 11:36:39.506584 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6883 11:36:39.510569 == TX Byte 1 ==
6884 11:36:39.513799 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6885 11:36:39.517343 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6886 11:36:39.517805 ==
6887 11:36:39.520124 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 11:36:39.526907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 11:36:39.527359 ==
6890 11:36:39.527661
6891 11:36:39.527935
6892 11:36:39.528205 TX Vref Scan disable
6893 11:36:39.530125 == TX Byte 0 ==
6894 11:36:39.533533 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6895 11:36:39.536836 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6896 11:36:39.540135 == TX Byte 1 ==
6897 11:36:39.543387 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6898 11:36:39.546502 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6899 11:36:39.546915
6900 11:36:39.549936 [DATLAT]
6901 11:36:39.550397 Freq=400, CH1 RK1
6902 11:36:39.550718
6903 11:36:39.553051 DATLAT Default: 0xe
6904 11:36:39.553603 0, 0xFFFF, sum = 0
6905 11:36:39.556312 1, 0xFFFF, sum = 0
6906 11:36:39.556705 2, 0xFFFF, sum = 0
6907 11:36:39.559781 3, 0xFFFF, sum = 0
6908 11:36:39.560170 4, 0xFFFF, sum = 0
6909 11:36:39.563047 5, 0xFFFF, sum = 0
6910 11:36:39.563651 6, 0xFFFF, sum = 0
6911 11:36:39.566659 7, 0xFFFF, sum = 0
6912 11:36:39.567367 8, 0xFFFF, sum = 0
6913 11:36:39.569509 9, 0xFFFF, sum = 0
6914 11:36:39.570282 10, 0xFFFF, sum = 0
6915 11:36:39.572724 11, 0xFFFF, sum = 0
6916 11:36:39.576133 12, 0xFFFF, sum = 0
6917 11:36:39.576715 13, 0x0, sum = 1
6918 11:36:39.579666 14, 0x0, sum = 2
6919 11:36:39.580068 15, 0x0, sum = 3
6920 11:36:39.580644 16, 0x0, sum = 4
6921 11:36:39.582830 best_step = 14
6922 11:36:39.583379
6923 11:36:39.583868 ==
6924 11:36:39.586643 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 11:36:39.589863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 11:36:39.590382 ==
6927 11:36:39.592958 RX Vref Scan: 0
6928 11:36:39.593442
6929 11:36:39.593905 RX Vref 0 -> 0, step: 1
6930 11:36:39.596208
6931 11:36:39.596766 RX Delay -311 -> 252, step: 8
6932 11:36:39.604441 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6933 11:36:39.607515 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6934 11:36:39.611542 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6935 11:36:39.617746 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6936 11:36:39.620977 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6937 11:36:39.624482 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6938 11:36:39.627622 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6939 11:36:39.630785 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6940 11:36:39.637422 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6941 11:36:39.641322 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6942 11:36:39.644659 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6943 11:36:39.647429 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6944 11:36:39.654372 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6945 11:36:39.657786 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6946 11:36:39.660591 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6947 11:36:39.667071 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6948 11:36:39.667351 ==
6949 11:36:39.670462 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 11:36:39.673818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 11:36:39.674124 ==
6952 11:36:39.674343 DQS Delay:
6953 11:36:39.676903 DQS0 = 28, DQS1 = 32
6954 11:36:39.677176 DQM Delay:
6955 11:36:39.680537 DQM0 = 11, DQM1 = 11
6956 11:36:39.680810 DQ Delay:
6957 11:36:39.683676 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6958 11:36:39.687016 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6959 11:36:39.690799 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6960 11:36:39.693991 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6961 11:36:39.694305
6962 11:36:39.694585
6963 11:36:39.700477 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 384 ps
6964 11:36:39.704028 CH1 RK1: MR19=C0C, MR18=CF5E
6965 11:36:39.710351 CH1_RK1: MR19=0xC0C, MR18=0xCF5E, DQSOSC=384, MR23=63, INC=400, DEC=267
6966 11:36:39.713737 [RxdqsGatingPostProcess] freq 400
6967 11:36:39.720499 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 11:36:39.720783 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 11:36:39.723954 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 11:36:39.727112 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 11:36:39.730491 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 11:36:39.733856 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 11:36:39.737079 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 11:36:39.740150 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 11:36:39.743709 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 11:36:39.746760 Pre-setting of DQS Precalculation
6977 11:36:39.753273 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 11:36:39.760346 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 11:36:39.767055 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 11:36:39.767200
6981 11:36:39.767345
6982 11:36:39.770199 [Calibration Summary] 800 Mbps
6983 11:36:39.770343 CH 0, Rank 0
6984 11:36:39.773528 SW Impedance : PASS
6985 11:36:39.776673 DUTY Scan : NO K
6986 11:36:39.776822 ZQ Calibration : PASS
6987 11:36:39.780115 Jitter Meter : NO K
6988 11:36:39.780260 CBT Training : PASS
6989 11:36:39.783153 Write leveling : PASS
6990 11:36:39.786745 RX DQS gating : PASS
6991 11:36:39.786888 RX DQ/DQS(RDDQC) : PASS
6992 11:36:39.789935 TX DQ/DQS : PASS
6993 11:36:39.793372 RX DATLAT : PASS
6994 11:36:39.793517 RX DQ/DQS(Engine): PASS
6995 11:36:39.796521 TX OE : NO K
6996 11:36:39.796664 All Pass.
6997 11:36:39.796808
6998 11:36:39.799954 CH 0, Rank 1
6999 11:36:39.800098 SW Impedance : PASS
7000 11:36:39.803578 DUTY Scan : NO K
7001 11:36:39.806499 ZQ Calibration : PASS
7002 11:36:39.806681 Jitter Meter : NO K
7003 11:36:39.809988 CBT Training : PASS
7004 11:36:39.813594 Write leveling : NO K
7005 11:36:39.813734 RX DQS gating : PASS
7006 11:36:39.816829 RX DQ/DQS(RDDQC) : PASS
7007 11:36:39.819865 TX DQ/DQS : PASS
7008 11:36:39.820013 RX DATLAT : PASS
7009 11:36:39.823246 RX DQ/DQS(Engine): PASS
7010 11:36:39.823424 TX OE : NO K
7011 11:36:39.826648 All Pass.
7012 11:36:39.826786
7013 11:36:39.826893 CH 1, Rank 0
7014 11:36:39.829782 SW Impedance : PASS
7015 11:36:39.829921 DUTY Scan : NO K
7016 11:36:39.833376 ZQ Calibration : PASS
7017 11:36:39.836632 Jitter Meter : NO K
7018 11:36:39.836772 CBT Training : PASS
7019 11:36:39.840237 Write leveling : PASS
7020 11:36:39.843251 RX DQS gating : PASS
7021 11:36:39.843389 RX DQ/DQS(RDDQC) : PASS
7022 11:36:39.846592 TX DQ/DQS : PASS
7023 11:36:39.849829 RX DATLAT : PASS
7024 11:36:39.849966 RX DQ/DQS(Engine): PASS
7025 11:36:39.853063 TX OE : NO K
7026 11:36:39.853201 All Pass.
7027 11:36:39.853307
7028 11:36:39.856459 CH 1, Rank 1
7029 11:36:39.856620 SW Impedance : PASS
7030 11:36:39.859755 DUTY Scan : NO K
7031 11:36:39.863083 ZQ Calibration : PASS
7032 11:36:39.863221 Jitter Meter : NO K
7033 11:36:39.866448 CBT Training : PASS
7034 11:36:39.869768 Write leveling : NO K
7035 11:36:39.869906 RX DQS gating : PASS
7036 11:36:39.873266 RX DQ/DQS(RDDQC) : PASS
7037 11:36:39.873406 TX DQ/DQS : PASS
7038 11:36:39.876732 RX DATLAT : PASS
7039 11:36:39.879899 RX DQ/DQS(Engine): PASS
7040 11:36:39.880037 TX OE : NO K
7041 11:36:39.883217 All Pass.
7042 11:36:39.883335
7043 11:36:39.883427 DramC Write-DBI off
7044 11:36:39.886021 PER_BANK_REFRESH: Hybrid Mode
7045 11:36:39.889527 TX_TRACKING: ON
7046 11:36:39.896450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 11:36:39.899602 [FAST_K] Save calibration result to emmc
7048 11:36:39.903222 dramc_set_vcore_voltage set vcore to 725000
7049 11:36:39.906314 Read voltage for 1600, 0
7050 11:36:39.906390 Vio18 = 0
7051 11:36:39.909682 Vcore = 725000
7052 11:36:39.909750 Vdram = 0
7053 11:36:39.909834 Vddq = 0
7054 11:36:39.912823 Vmddr = 0
7055 11:36:39.915809 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 11:36:39.922899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 11:36:39.922977 MEM_TYPE=3, freq_sel=13
7058 11:36:39.926306 sv_algorithm_assistance_LP4_3733
7059 11:36:39.932791 ============ PULL DRAM RESETB DOWN ============
7060 11:36:39.936433 ========== PULL DRAM RESETB DOWN end =========
7061 11:36:39.939776 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 11:36:39.943155 ===================================
7063 11:36:39.946348 LPDDR4 DRAM CONFIGURATION
7064 11:36:39.949410 ===================================
7065 11:36:39.952786 EX_ROW_EN[0] = 0x0
7066 11:36:39.952863 EX_ROW_EN[1] = 0x0
7067 11:36:39.955937 LP4Y_EN = 0x0
7068 11:36:39.956014 WORK_FSP = 0x1
7069 11:36:39.959154 WL = 0x5
7070 11:36:39.959231 RL = 0x5
7071 11:36:39.962617 BL = 0x2
7072 11:36:39.962694 RPST = 0x0
7073 11:36:39.966121 RD_PRE = 0x0
7074 11:36:39.966199 WR_PRE = 0x1
7075 11:36:39.969444 WR_PST = 0x1
7076 11:36:39.969520 DBI_WR = 0x0
7077 11:36:39.972772 DBI_RD = 0x0
7078 11:36:39.972849 OTF = 0x1
7079 11:36:39.976213 ===================================
7080 11:36:39.979402 ===================================
7081 11:36:39.982775 ANA top config
7082 11:36:39.986326 ===================================
7083 11:36:39.989602 DLL_ASYNC_EN = 0
7084 11:36:39.989678 ALL_SLAVE_EN = 0
7085 11:36:39.992803 NEW_RANK_MODE = 1
7086 11:36:39.996120 DLL_IDLE_MODE = 1
7087 11:36:39.999151 LP45_APHY_COMB_EN = 1
7088 11:36:39.999228 TX_ODT_DIS = 0
7089 11:36:40.002287 NEW_8X_MODE = 1
7090 11:36:40.005883 ===================================
7091 11:36:40.009377 ===================================
7092 11:36:40.012329 data_rate = 3200
7093 11:36:40.015890 CKR = 1
7094 11:36:40.019702 DQ_P2S_RATIO = 8
7095 11:36:40.022680 ===================================
7096 11:36:40.026187 CA_P2S_RATIO = 8
7097 11:36:40.026574 DQ_CA_OPEN = 0
7098 11:36:40.029594 DQ_SEMI_OPEN = 0
7099 11:36:40.032890 CA_SEMI_OPEN = 0
7100 11:36:40.035971 CA_FULL_RATE = 0
7101 11:36:40.039245 DQ_CKDIV4_EN = 0
7102 11:36:40.042467 CA_CKDIV4_EN = 0
7103 11:36:40.042848 CA_PREDIV_EN = 0
7104 11:36:40.046000 PH8_DLY = 12
7105 11:36:40.049119 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 11:36:40.052554 DQ_AAMCK_DIV = 4
7107 11:36:40.056192 CA_AAMCK_DIV = 4
7108 11:36:40.058859 CA_ADMCK_DIV = 4
7109 11:36:40.059217 DQ_TRACK_CA_EN = 0
7110 11:36:40.062383 CA_PICK = 1600
7111 11:36:40.065996 CA_MCKIO = 1600
7112 11:36:40.068928 MCKIO_SEMI = 0
7113 11:36:40.072107 PLL_FREQ = 3068
7114 11:36:40.076030 DQ_UI_PI_RATIO = 32
7115 11:36:40.079435 CA_UI_PI_RATIO = 0
7116 11:36:40.082878 ===================================
7117 11:36:40.086093 ===================================
7118 11:36:40.086391 memory_type:LPDDR4
7119 11:36:40.089432 GP_NUM : 10
7120 11:36:40.092755 SRAM_EN : 1
7121 11:36:40.092998 MD32_EN : 0
7122 11:36:40.095887 ===================================
7123 11:36:40.099385 [ANA_INIT] >>>>>>>>>>>>>>
7124 11:36:40.102651 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 11:36:40.105965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 11:36:40.109340 ===================================
7127 11:36:40.112473 data_rate = 3200,PCW = 0X7600
7128 11:36:40.115802 ===================================
7129 11:36:40.118784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 11:36:40.122716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 11:36:40.128881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 11:36:40.132441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 11:36:40.135750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 11:36:40.139025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 11:36:40.142054 [ANA_INIT] flow start
7136 11:36:40.145625 [ANA_INIT] PLL >>>>>>>>
7137 11:36:40.145748 [ANA_INIT] PLL <<<<<<<<
7138 11:36:40.148852 [ANA_INIT] MIDPI >>>>>>>>
7139 11:36:40.152348 [ANA_INIT] MIDPI <<<<<<<<
7140 11:36:40.152470 [ANA_INIT] DLL >>>>>>>>
7141 11:36:40.155576 [ANA_INIT] DLL <<<<<<<<
7142 11:36:40.158734 [ANA_INIT] flow end
7143 11:36:40.162073 ============ LP4 DIFF to SE enter ============
7144 11:36:40.165495 ============ LP4 DIFF to SE exit ============
7145 11:36:40.168734 [ANA_INIT] <<<<<<<<<<<<<
7146 11:36:40.172615 [Flow] Enable top DCM control >>>>>
7147 11:36:40.176051 [Flow] Enable top DCM control <<<<<
7148 11:36:40.178849 Enable DLL master slave shuffle
7149 11:36:40.182442 ==============================================================
7150 11:36:40.185950 Gating Mode config
7151 11:36:40.191857 ==============================================================
7152 11:36:40.191955 Config description:
7153 11:36:40.202235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 11:36:40.208631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 11:36:40.212444 SELPH_MODE 0: By rank 1: By Phase
7156 11:36:40.218704 ==============================================================
7157 11:36:40.221880 GAT_TRACK_EN = 1
7158 11:36:40.225404 RX_GATING_MODE = 2
7159 11:36:40.228804 RX_GATING_TRACK_MODE = 2
7160 11:36:40.231933 SELPH_MODE = 1
7161 11:36:40.235283 PICG_EARLY_EN = 1
7162 11:36:40.239059 VALID_LAT_VALUE = 1
7163 11:36:40.241767 ==============================================================
7164 11:36:40.245416 Enter into Gating configuration >>>>
7165 11:36:40.248365 Exit from Gating configuration <<<<
7166 11:36:40.251699 Enter into DVFS_PRE_config >>>>>
7167 11:36:40.265674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 11:36:40.265804 Exit from DVFS_PRE_config <<<<<
7169 11:36:40.268831 Enter into PICG configuration >>>>
7170 11:36:40.271523 Exit from PICG configuration <<<<
7171 11:36:40.275550 [RX_INPUT] configuration >>>>>
7172 11:36:40.278569 [RX_INPUT] configuration <<<<<
7173 11:36:40.285411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 11:36:40.288117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 11:36:40.295188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 11:36:40.301625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 11:36:40.308196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 11:36:40.315020 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 11:36:40.318814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 11:36:40.321876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 11:36:40.324723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 11:36:40.331418 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 11:36:40.334846 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 11:36:40.338198 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 11:36:40.341366 ===================================
7186 11:36:40.344623 LPDDR4 DRAM CONFIGURATION
7187 11:36:40.348049 ===================================
7188 11:36:40.348137 EX_ROW_EN[0] = 0x0
7189 11:36:40.351331 EX_ROW_EN[1] = 0x0
7190 11:36:40.355100 LP4Y_EN = 0x0
7191 11:36:40.355222 WORK_FSP = 0x1
7192 11:36:40.358587 WL = 0x5
7193 11:36:40.358684 RL = 0x5
7194 11:36:40.361960 BL = 0x2
7195 11:36:40.362103 RPST = 0x0
7196 11:36:40.364719 RD_PRE = 0x0
7197 11:36:40.364831 WR_PRE = 0x1
7198 11:36:40.368566 WR_PST = 0x1
7199 11:36:40.368692 DBI_WR = 0x0
7200 11:36:40.371434 DBI_RD = 0x0
7201 11:36:40.371534 OTF = 0x1
7202 11:36:40.374826 ===================================
7203 11:36:40.378601 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 11:36:40.384898 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 11:36:40.388033 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 11:36:40.391675 ===================================
7207 11:36:40.394982 LPDDR4 DRAM CONFIGURATION
7208 11:36:40.398632 ===================================
7209 11:36:40.398793 EX_ROW_EN[0] = 0x10
7210 11:36:40.401967 EX_ROW_EN[1] = 0x0
7211 11:36:40.402143 LP4Y_EN = 0x0
7212 11:36:40.405396 WORK_FSP = 0x1
7213 11:36:40.405575 WL = 0x5
7214 11:36:40.408550 RL = 0x5
7215 11:36:40.408733 BL = 0x2
7216 11:36:40.411727 RPST = 0x0
7217 11:36:40.414755 RD_PRE = 0x0
7218 11:36:40.414905 WR_PRE = 0x1
7219 11:36:40.418243 WR_PST = 0x1
7220 11:36:40.418398 DBI_WR = 0x0
7221 11:36:40.421517 DBI_RD = 0x0
7222 11:36:40.421697 OTF = 0x1
7223 11:36:40.424928 ===================================
7224 11:36:40.431341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 11:36:40.431559 ==
7226 11:36:40.434968 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 11:36:40.438585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 11:36:40.438807 ==
7229 11:36:40.441789 [Duty_Offset_Calibration]
7230 11:36:40.442077 B0:2 B1:1 CA:1
7231 11:36:40.445212
7232 11:36:40.447879 [DutyScan_Calibration_Flow] k_type=0
7233 11:36:40.456588
7234 11:36:40.456872 ==CLK 0==
7235 11:36:40.459776 Final CLK duty delay cell = 0
7236 11:36:40.462838 [0] MAX Duty = 5156%(X100), DQS PI = 22
7237 11:36:40.466259 [0] MIN Duty = 4907%(X100), DQS PI = 0
7238 11:36:40.466621 [0] AVG Duty = 5031%(X100)
7239 11:36:40.469688
7240 11:36:40.469906 CH0 CLK Duty spec in!! Max-Min= 249%
7241 11:36:40.476784 [DutyScan_Calibration_Flow] ====Done====
7242 11:36:40.477057
7243 11:36:40.479763 [DutyScan_Calibration_Flow] k_type=1
7244 11:36:40.496195
7245 11:36:40.496622 ==DQS 0 ==
7246 11:36:40.499330 Final DQS duty delay cell = -4
7247 11:36:40.502434 [-4] MAX Duty = 5094%(X100), DQS PI = 24
7248 11:36:40.505380 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7249 11:36:40.508853 [-4] AVG Duty = 4875%(X100)
7250 11:36:40.509273
7251 11:36:40.509691 ==DQS 1 ==
7252 11:36:40.512598 Final DQS duty delay cell = 0
7253 11:36:40.516065 [0] MAX Duty = 5187%(X100), DQS PI = 6
7254 11:36:40.518457 [0] MIN Duty = 5031%(X100), DQS PI = 52
7255 11:36:40.521914 [0] AVG Duty = 5109%(X100)
7256 11:36:40.522318
7257 11:36:40.525197 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7258 11:36:40.525579
7259 11:36:40.528975 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7260 11:36:40.532259 [DutyScan_Calibration_Flow] ====Done====
7261 11:36:40.532722
7262 11:36:40.535280 [DutyScan_Calibration_Flow] k_type=3
7263 11:36:40.663153
7264 11:36:40.663754 ==DQM 0 ==
7265 11:36:40.664238 Final DQM duty delay cell = 0
7266 11:36:40.664722 [0] MAX Duty = 5187%(X100), DQS PI = 26
7267 11:36:40.665169 [0] MIN Duty = 4844%(X100), DQS PI = 60
7268 11:36:40.665608 [0] AVG Duty = 5015%(X100)
7269 11:36:40.666081
7270 11:36:40.666522 ==DQM 1 ==
7271 11:36:40.666958 Final DQM duty delay cell = 0
7272 11:36:40.667395 [0] MAX Duty = 5187%(X100), DQS PI = 4
7273 11:36:40.667826 [0] MIN Duty = 5062%(X100), DQS PI = 14
7274 11:36:40.668253 [0] AVG Duty = 5124%(X100)
7275 11:36:40.668680
7276 11:36:40.669113 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7277 11:36:40.669545
7278 11:36:40.669967 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7279 11:36:40.670427 [DutyScan_Calibration_Flow] ====Done====
7280 11:36:40.670856
7281 11:36:40.671295 [DutyScan_Calibration_Flow] k_type=2
7282 11:36:40.671678
7283 11:36:40.671994 ==DQ 0 ==
7284 11:36:40.672258 Final DQ duty delay cell = 0
7285 11:36:40.672518 [0] MAX Duty = 5062%(X100), DQS PI = 26
7286 11:36:40.672775 [0] MIN Duty = 4907%(X100), DQS PI = 0
7287 11:36:40.673026 [0] AVG Duty = 4984%(X100)
7288 11:36:40.673274
7289 11:36:40.673523 ==DQ 1 ==
7290 11:36:40.673773 Final DQ duty delay cell = 0
7291 11:36:40.674060 [0] MAX Duty = 5093%(X100), DQS PI = 6
7292 11:36:40.674329 [0] MIN Duty = 4938%(X100), DQS PI = 34
7293 11:36:40.674578 [0] AVG Duty = 5015%(X100)
7294 11:36:40.674822
7295 11:36:40.675066 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7296 11:36:40.675314
7297 11:36:40.675560 CH0 DQ 1 Duty spec in!! Max-Min= 155%
7298 11:36:40.675810 [DutyScan_Calibration_Flow] ====Done====
7299 11:36:40.676057 ==
7300 11:36:40.676305 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 11:36:40.676554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 11:36:40.676805 ==
7303 11:36:40.677050 [Duty_Offset_Calibration]
7304 11:36:40.677295 B0:1 B1:0 CA:0
7305 11:36:40.677538
7306 11:36:40.677782 [DutyScan_Calibration_Flow] k_type=0
7307 11:36:40.678364
7308 11:36:40.678636 ==CLK 0==
7309 11:36:40.678890 Final CLK duty delay cell = -4
7310 11:36:40.679141 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7311 11:36:40.679440 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7312 11:36:40.682817 [-4] AVG Duty = 4922%(X100)
7313 11:36:40.683199
7314 11:36:40.686535 CH1 CLK Duty spec in!! Max-Min= 156%
7315 11:36:40.689716 [DutyScan_Calibration_Flow] ====Done====
7316 11:36:40.690137
7317 11:36:40.693088 [DutyScan_Calibration_Flow] k_type=1
7318 11:36:40.709682
7319 11:36:40.710064 ==DQS 0 ==
7320 11:36:40.712919 Final DQS duty delay cell = 0
7321 11:36:40.716036 [0] MAX Duty = 5094%(X100), DQS PI = 16
7322 11:36:40.719399 [0] MIN Duty = 4844%(X100), DQS PI = 48
7323 11:36:40.722702 [0] AVG Duty = 4969%(X100)
7324 11:36:40.723084
7325 11:36:40.723378 ==DQS 1 ==
7326 11:36:40.726250 Final DQS duty delay cell = 0
7327 11:36:40.729463 [0] MAX Duty = 5249%(X100), DQS PI = 16
7328 11:36:40.732702 [0] MIN Duty = 4938%(X100), DQS PI = 8
7329 11:36:40.735723 [0] AVG Duty = 5093%(X100)
7330 11:36:40.736099
7331 11:36:40.739372 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7332 11:36:40.739750
7333 11:36:40.743555 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7334 11:36:40.746578 [DutyScan_Calibration_Flow] ====Done====
7335 11:36:40.746959
7336 11:36:40.748957 [DutyScan_Calibration_Flow] k_type=3
7337 11:36:40.766355
7338 11:36:40.767032 ==DQM 0 ==
7339 11:36:40.769664 Final DQM duty delay cell = 0
7340 11:36:40.772910 [0] MAX Duty = 5187%(X100), DQS PI = 8
7341 11:36:40.776306 [0] MIN Duty = 4969%(X100), DQS PI = 48
7342 11:36:40.776842 [0] AVG Duty = 5078%(X100)
7343 11:36:40.779704
7344 11:36:40.780087 ==DQM 1 ==
7345 11:36:40.783349 Final DQM duty delay cell = 0
7346 11:36:40.786164 [0] MAX Duty = 5062%(X100), DQS PI = 16
7347 11:36:40.789674 [0] MIN Duty = 4907%(X100), DQS PI = 34
7348 11:36:40.793326 [0] AVG Duty = 4984%(X100)
7349 11:36:40.793792
7350 11:36:40.796199 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7351 11:36:40.796605
7352 11:36:40.799742 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7353 11:36:40.802927 [DutyScan_Calibration_Flow] ====Done====
7354 11:36:40.803391
7355 11:36:40.806347 [DutyScan_Calibration_Flow] k_type=2
7356 11:36:40.822644
7357 11:36:40.823143 ==DQ 0 ==
7358 11:36:40.826074 Final DQ duty delay cell = -4
7359 11:36:40.829323 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7360 11:36:40.832325 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7361 11:36:40.835534 [-4] AVG Duty = 4968%(X100)
7362 11:36:40.835983
7363 11:36:40.836304 ==DQ 1 ==
7364 11:36:40.838819 Final DQ duty delay cell = 0
7365 11:36:40.842116 [0] MAX Duty = 5124%(X100), DQS PI = 18
7366 11:36:40.845447 [0] MIN Duty = 4938%(X100), DQS PI = 8
7367 11:36:40.848712 [0] AVG Duty = 5031%(X100)
7368 11:36:40.849153
7369 11:36:40.851869 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7370 11:36:40.852385
7371 11:36:40.855326 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7372 11:36:40.858608 [DutyScan_Calibration_Flow] ====Done====
7373 11:36:40.862156 nWR fixed to 30
7374 11:36:40.865801 [ModeRegInit_LP4] CH0 RK0
7375 11:36:40.866228 [ModeRegInit_LP4] CH0 RK1
7376 11:36:40.869242 [ModeRegInit_LP4] CH1 RK0
7377 11:36:40.872522 [ModeRegInit_LP4] CH1 RK1
7378 11:36:40.873031 match AC timing 5
7379 11:36:40.879027 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 11:36:40.881953 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 11:36:40.885407 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 11:36:40.892354 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 11:36:40.895269 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 11:36:40.895693 [MiockJmeterHQA]
7385 11:36:40.895987
7386 11:36:40.898996 [DramcMiockJmeter] u1RxGatingPI = 0
7387 11:36:40.902206 0 : 4254, 4029
7388 11:36:40.902605 4 : 4363, 4138
7389 11:36:40.905210 8 : 4257, 4029
7390 11:36:40.905631 12 : 4363, 4138
7391 11:36:40.905959 16 : 4252, 4027
7392 11:36:40.908861 20 : 4252, 4027
7393 11:36:40.909422 24 : 4253, 4027
7394 11:36:40.912227 28 : 4363, 4138
7395 11:36:40.912747 32 : 4363, 4138
7396 11:36:40.915537 36 : 4252, 4027
7397 11:36:40.916047 40 : 4252, 4027
7398 11:36:40.918936 44 : 4252, 4027
7399 11:36:40.919517 48 : 4252, 4027
7400 11:36:40.919861 52 : 4255, 4029
7401 11:36:40.922288 56 : 4363, 4138
7402 11:36:40.922718 60 : 4250, 4027
7403 11:36:40.925615 64 : 4253, 4027
7404 11:36:40.926224 68 : 4250, 4027
7405 11:36:40.928943 72 : 4252, 4029
7406 11:36:40.929357 76 : 4250, 4027
7407 11:36:40.929710 80 : 4361, 4138
7408 11:36:40.931834 84 : 4360, 4137
7409 11:36:40.932233 88 : 4252, 93
7410 11:36:40.935202 92 : 4250, 0
7411 11:36:40.935607 96 : 4253, 0
7412 11:36:40.936006 100 : 4250, 0
7413 11:36:40.939120 104 : 4249, 0
7414 11:36:40.939519 108 : 4250, 0
7415 11:36:40.941710 112 : 4252, 0
7416 11:36:40.942151 116 : 4250, 0
7417 11:36:40.942554 120 : 4250, 0
7418 11:36:40.945139 124 : 4252, 0
7419 11:36:40.945543 128 : 4361, 0
7420 11:36:40.948894 132 : 4361, 0
7421 11:36:40.949295 136 : 4363, 0
7422 11:36:40.949695 140 : 4250, 0
7423 11:36:40.952170 144 : 4250, 0
7424 11:36:40.952575 148 : 4250, 0
7425 11:36:40.952974 152 : 4252, 0
7426 11:36:40.955080 156 : 4250, 0
7427 11:36:40.955716 160 : 4250, 0
7428 11:36:40.958697 164 : 4252, 0
7429 11:36:40.959115 168 : 4250, 0
7430 11:36:40.959513 172 : 4250, 0
7431 11:36:40.961890 176 : 4252, 0
7432 11:36:40.962369 180 : 4361, 0
7433 11:36:40.965327 184 : 4361, 0
7434 11:36:40.965783 188 : 4363, 0
7435 11:36:40.966251 192 : 4250, 0
7436 11:36:40.968426 196 : 4250, 0
7437 11:36:40.968989 200 : 4363, 0
7438 11:36:40.971796 204 : 4250, 1233
7439 11:36:40.972100 208 : 4363, 4099
7440 11:36:40.974986 212 : 4250, 4027
7441 11:36:40.975334 216 : 4250, 4027
7442 11:36:40.978369 220 : 4250, 4027
7443 11:36:40.978675 224 : 4252, 4029
7444 11:36:40.978916 228 : 4250, 4027
7445 11:36:40.981816 232 : 4252, 4027
7446 11:36:40.981984 236 : 4361, 4138
7447 11:36:40.985068 240 : 4250, 4027
7448 11:36:40.985278 244 : 4250, 4027
7449 11:36:40.988372 248 : 4361, 4137
7450 11:36:40.988589 252 : 4250, 4027
7451 11:36:40.991963 256 : 4250, 4027
7452 11:36:40.992131 260 : 4363, 4140
7453 11:36:40.995035 264 : 4250, 4027
7454 11:36:40.995207 268 : 4250, 4027
7455 11:36:40.998411 272 : 4250, 4027
7456 11:36:40.998585 276 : 4252, 4029
7457 11:36:40.998718 280 : 4250, 4027
7458 11:36:41.001451 284 : 4252, 4029
7459 11:36:41.001629 288 : 4361, 4138
7460 11:36:41.005522 292 : 4250, 4027
7461 11:36:41.005690 296 : 4250, 4027
7462 11:36:41.008146 300 : 4361, 4137
7463 11:36:41.008332 304 : 4250, 4027
7464 11:36:41.011363 308 : 4250, 3967
7465 11:36:41.011549 312 : 4363, 2317
7466 11:36:41.014873 316 : 4250, 10
7467 11:36:41.015041
7468 11:36:41.015167 MIOCK jitter meter ch=0
7469 11:36:41.015287
7470 11:36:41.017776 1T = (316-88) = 228 dly cells
7471 11:36:41.024527 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7472 11:36:41.024698 ==
7473 11:36:41.028094 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 11:36:41.031070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 11:36:41.031243 ==
7476 11:36:41.037759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 11:36:41.041207 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 11:36:41.047890 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 11:36:41.051061 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 11:36:41.061161 [CA 0] Center 42 (12~73) winsize 62
7481 11:36:41.064420 [CA 1] Center 42 (12~73) winsize 62
7482 11:36:41.067674 [CA 2] Center 37 (7~67) winsize 61
7483 11:36:41.070837 [CA 3] Center 37 (7~67) winsize 61
7484 11:36:41.074041 [CA 4] Center 36 (6~66) winsize 61
7485 11:36:41.077528 [CA 5] Center 35 (6~64) winsize 59
7486 11:36:41.077767
7487 11:36:41.080916 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 11:36:41.081099
7489 11:36:41.084256 [CATrainingPosCal] consider 1 rank data
7490 11:36:41.087512 u2DelayCellTimex100 = 285/100 ps
7491 11:36:41.091253 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7492 11:36:41.097819 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7493 11:36:41.101207 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7494 11:36:41.104753 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7495 11:36:41.107374 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7496 11:36:41.110679 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7497 11:36:41.110918
7498 11:36:41.114118 CA PerBit enable=1, Macro0, CA PI delay=35
7499 11:36:41.114285
7500 11:36:41.117877 [CBTSetCACLKResult] CA Dly = 35
7501 11:36:41.121603 CS Dly: 9 (0~40)
7502 11:36:41.124110 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 11:36:41.127844 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 11:36:41.128010 ==
7505 11:36:41.131032 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 11:36:41.134159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 11:36:41.134326 ==
7508 11:36:41.141125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 11:36:41.144545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 11:36:41.151174 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 11:36:41.154247 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 11:36:41.164418 [CA 0] Center 42 (12~73) winsize 62
7513 11:36:41.167979 [CA 1] Center 42 (12~73) winsize 62
7514 11:36:41.171232 [CA 2] Center 38 (8~68) winsize 61
7515 11:36:41.174577 [CA 3] Center 37 (7~68) winsize 62
7516 11:36:41.178085 [CA 4] Center 35 (5~65) winsize 61
7517 11:36:41.181536 [CA 5] Center 35 (5~65) winsize 61
7518 11:36:41.182066
7519 11:36:41.184809 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7520 11:36:41.185218
7521 11:36:41.187991 [CATrainingPosCal] consider 2 rank data
7522 11:36:41.191568 u2DelayCellTimex100 = 285/100 ps
7523 11:36:41.194702 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7524 11:36:41.201337 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7525 11:36:41.204703 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7526 11:36:41.207836 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7527 11:36:41.211212 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7528 11:36:41.214750 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7529 11:36:41.215149
7530 11:36:41.217988 CA PerBit enable=1, Macro0, CA PI delay=35
7531 11:36:41.218449
7532 11:36:41.220777 [CBTSetCACLKResult] CA Dly = 35
7533 11:36:41.224768 CS Dly: 10 (0~42)
7534 11:36:41.228050 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 11:36:41.231199 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 11:36:41.231691
7537 11:36:41.234630 ----->DramcWriteLeveling(PI) begin...
7538 11:36:41.235187 ==
7539 11:36:41.237239 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 11:36:41.240971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 11:36:41.244655 ==
7542 11:36:41.245069 Write leveling (Byte 0): 37 => 37
7543 11:36:41.247301 Write leveling (Byte 1): 27 => 27
7544 11:36:41.250498 DramcWriteLeveling(PI) end<-----
7545 11:36:41.250919
7546 11:36:41.251330 ==
7547 11:36:41.253949 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 11:36:41.260909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 11:36:41.261337 ==
7550 11:36:41.263941 [Gating] SW mode calibration
7551 11:36:41.270571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 11:36:41.273712 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 11:36:41.280232 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 11:36:41.284213 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 11:36:41.286859 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7556 11:36:41.290574 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7557 11:36:41.296797 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7558 11:36:41.300408 1 4 20 | B1->B0 | 3434 3636 | 0 0 | (0 0) (0 0)
7559 11:36:41.303620 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7560 11:36:41.310335 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7561 11:36:41.313421 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7562 11:36:41.316962 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7563 11:36:41.323695 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
7564 11:36:41.326875 1 5 12 | B1->B0 | 3434 2827 | 1 1 | (1 1) (1 0)
7565 11:36:41.330196 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
7566 11:36:41.336985 1 5 20 | B1->B0 | 2626 2727 | 0 0 | (1 0) (0 0)
7567 11:36:41.340160 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7568 11:36:41.343569 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7569 11:36:41.350329 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7570 11:36:41.353930 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7571 11:36:41.357075 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7572 11:36:41.363563 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7573 11:36:41.367377 1 6 16 | B1->B0 | 2929 4645 | 0 1 | (0 0) (0 0)
7574 11:36:41.370322 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7575 11:36:41.377431 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:36:41.380467 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7577 11:36:41.383924 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 11:36:41.390138 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 11:36:41.393630 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 11:36:41.397071 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 11:36:41.403542 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 11:36:41.407321 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 11:36:41.410082 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:36:41.417340 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:36:41.420568 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:36:41.423835 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:36:41.427421 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:36:41.433913 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:36:41.437517 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:36:41.440750 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:36:41.447753 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:36:41.450931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:36:41.454214 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:36:41.460754 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:36:41.464498 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 11:36:41.467335 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 11:36:41.473923 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7598 11:36:41.477120 Total UI for P1: 0, mck2ui 16
7599 11:36:41.480468 best dqsien dly found for B0: ( 1, 9, 10)
7600 11:36:41.483600 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 11:36:41.487001 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 11:36:41.489999 Total UI for P1: 0, mck2ui 16
7603 11:36:41.493453 best dqsien dly found for B1: ( 1, 9, 20)
7604 11:36:41.496668 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7605 11:36:41.499971 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7606 11:36:41.500363
7607 11:36:41.506631 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7608 11:36:41.509878 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7609 11:36:41.512846 [Gating] SW calibration Done
7610 11:36:41.513226 ==
7611 11:36:41.516747 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 11:36:41.520319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 11:36:41.520795 ==
7614 11:36:41.521095 RX Vref Scan: 0
7615 11:36:41.523412
7616 11:36:41.523864 RX Vref 0 -> 0, step: 1
7617 11:36:41.524168
7618 11:36:41.526843 RX Delay 0 -> 252, step: 8
7619 11:36:41.529781 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7620 11:36:41.533144 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7621 11:36:41.539898 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7622 11:36:41.543406 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7623 11:36:41.546789 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7624 11:36:41.550245 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7625 11:36:41.553433 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7626 11:36:41.559637 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7627 11:36:41.563553 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7628 11:36:41.566842 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7629 11:36:41.570114 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7630 11:36:41.573465 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7631 11:36:41.580133 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7632 11:36:41.583162 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7633 11:36:41.586158 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7634 11:36:41.589976 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7635 11:36:41.590560 ==
7636 11:36:41.593253 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 11:36:41.599989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 11:36:41.600489 ==
7639 11:36:41.600828 DQS Delay:
7640 11:36:41.601131 DQS0 = 0, DQS1 = 0
7641 11:36:41.602636 DQM Delay:
7642 11:36:41.603058 DQM0 = 136, DQM1 = 129
7643 11:36:41.606676 DQ Delay:
7644 11:36:41.609455 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7645 11:36:41.612995 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =143
7646 11:36:41.616675 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7647 11:36:41.619507 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7648 11:36:41.620016
7649 11:36:41.620458
7650 11:36:41.620937 ==
7651 11:36:41.623016 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 11:36:41.626650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 11:36:41.627181 ==
7654 11:36:41.629688
7655 11:36:41.630208
7656 11:36:41.630637 TX Vref Scan disable
7657 11:36:41.632898 == TX Byte 0 ==
7658 11:36:41.636334 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7659 11:36:41.639512 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7660 11:36:41.642705 == TX Byte 1 ==
7661 11:36:41.645741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7662 11:36:41.649076 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7663 11:36:41.652656 ==
7664 11:36:41.653118 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 11:36:41.658949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 11:36:41.659379 ==
7667 11:36:41.672421
7668 11:36:41.675269 TX Vref early break, caculate TX vref
7669 11:36:41.678828 TX Vref=16, minBit 1, minWin=22, winSum=372
7670 11:36:41.682364 TX Vref=18, minBit 0, minWin=23, winSum=382
7671 11:36:41.685502 TX Vref=20, minBit 1, minWin=23, winSum=399
7672 11:36:41.688913 TX Vref=22, minBit 0, minWin=24, winSum=407
7673 11:36:41.692189 TX Vref=24, minBit 0, minWin=25, winSum=413
7674 11:36:41.698848 TX Vref=26, minBit 0, minWin=25, winSum=423
7675 11:36:41.701624 TX Vref=28, minBit 0, minWin=25, winSum=417
7676 11:36:41.705186 TX Vref=30, minBit 0, minWin=24, winSum=411
7677 11:36:41.708763 TX Vref=32, minBit 2, minWin=23, winSum=402
7678 11:36:41.711803 TX Vref=34, minBit 1, minWin=23, winSum=391
7679 11:36:41.718939 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
7680 11:36:41.719466
7681 11:36:41.722114 Final TX Range 0 Vref 26
7682 11:36:41.722469
7683 11:36:41.722756 ==
7684 11:36:41.725306 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 11:36:41.728615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 11:36:41.729006 ==
7687 11:36:41.729306
7688 11:36:41.729579
7689 11:36:41.731954 TX Vref Scan disable
7690 11:36:41.738795 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7691 11:36:41.739185 == TX Byte 0 ==
7692 11:36:41.742181 u2DelayCellOfst[0]=13 cells (4 PI)
7693 11:36:41.746112 u2DelayCellOfst[1]=17 cells (5 PI)
7694 11:36:41.749260 u2DelayCellOfst[2]=13 cells (4 PI)
7695 11:36:41.752130 u2DelayCellOfst[3]=10 cells (3 PI)
7696 11:36:41.755306 u2DelayCellOfst[4]=10 cells (3 PI)
7697 11:36:41.758570 u2DelayCellOfst[5]=0 cells (0 PI)
7698 11:36:41.761778 u2DelayCellOfst[6]=20 cells (6 PI)
7699 11:36:41.762263 u2DelayCellOfst[7]=17 cells (5 PI)
7700 11:36:41.769110 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7701 11:36:41.772552 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7702 11:36:41.772985 == TX Byte 1 ==
7703 11:36:41.776028 u2DelayCellOfst[8]=0 cells (0 PI)
7704 11:36:41.779010 u2DelayCellOfst[9]=0 cells (0 PI)
7705 11:36:41.782433 u2DelayCellOfst[10]=10 cells (3 PI)
7706 11:36:41.785672 u2DelayCellOfst[11]=3 cells (1 PI)
7707 11:36:41.788852 u2DelayCellOfst[12]=10 cells (3 PI)
7708 11:36:41.792545 u2DelayCellOfst[13]=13 cells (4 PI)
7709 11:36:41.795696 u2DelayCellOfst[14]=17 cells (5 PI)
7710 11:36:41.798670 u2DelayCellOfst[15]=10 cells (3 PI)
7711 11:36:41.802536 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7712 11:36:41.805553 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7713 11:36:41.809041 DramC Write-DBI on
7714 11:36:41.809535 ==
7715 11:36:41.812534 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 11:36:41.816041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 11:36:41.816542 ==
7718 11:36:41.816873
7719 11:36:41.817173
7720 11:36:41.818842 TX Vref Scan disable
7721 11:36:41.822250 == TX Byte 0 ==
7722 11:36:41.825522 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7723 11:36:41.828778 == TX Byte 1 ==
7724 11:36:41.832699 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7725 11:36:41.833198 DramC Write-DBI off
7726 11:36:41.833529
7727 11:36:41.835647 [DATLAT]
7728 11:36:41.836069 Freq=1600, CH0 RK0
7729 11:36:41.836402
7730 11:36:41.839285 DATLAT Default: 0xf
7731 11:36:41.839779 0, 0xFFFF, sum = 0
7732 11:36:41.842476 1, 0xFFFF, sum = 0
7733 11:36:41.842908 2, 0xFFFF, sum = 0
7734 11:36:41.845428 3, 0xFFFF, sum = 0
7735 11:36:41.845859 4, 0xFFFF, sum = 0
7736 11:36:41.849519 5, 0xFFFF, sum = 0
7737 11:36:41.850126 6, 0xFFFF, sum = 0
7738 11:36:41.852059 7, 0xFFFF, sum = 0
7739 11:36:41.855519 8, 0xFFFF, sum = 0
7740 11:36:41.856042 9, 0xFFFF, sum = 0
7741 11:36:41.858549 10, 0xFFFF, sum = 0
7742 11:36:41.858981 11, 0xFFFF, sum = 0
7743 11:36:41.861923 12, 0xFFFF, sum = 0
7744 11:36:41.862400 13, 0xFFFF, sum = 0
7745 11:36:41.865320 14, 0x0, sum = 1
7746 11:36:41.865796 15, 0x0, sum = 2
7747 11:36:41.868609 16, 0x0, sum = 3
7748 11:36:41.869043 17, 0x0, sum = 4
7749 11:36:41.871669 best_step = 15
7750 11:36:41.872231
7751 11:36:41.872685 ==
7752 11:36:41.874826 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 11:36:41.878359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 11:36:41.878754 ==
7755 11:36:41.879057 RX Vref Scan: 1
7756 11:36:41.879336
7757 11:36:41.881637 Set Vref Range= 24 -> 127
7758 11:36:41.882060
7759 11:36:41.885042 RX Vref 24 -> 127, step: 1
7760 11:36:41.885430
7761 11:36:41.888299 RX Delay 19 -> 252, step: 4
7762 11:36:41.888684
7763 11:36:41.891730 Set Vref, RX VrefLevel [Byte0]: 24
7764 11:36:41.895022 [Byte1]: 24
7765 11:36:41.895417
7766 11:36:41.898448 Set Vref, RX VrefLevel [Byte0]: 25
7767 11:36:41.902206 [Byte1]: 25
7768 11:36:41.902594
7769 11:36:41.904921 Set Vref, RX VrefLevel [Byte0]: 26
7770 11:36:41.908696 [Byte1]: 26
7771 11:36:41.912531
7772 11:36:41.912993 Set Vref, RX VrefLevel [Byte0]: 27
7773 11:36:41.915807 [Byte1]: 27
7774 11:36:41.919839
7775 11:36:41.920293 Set Vref, RX VrefLevel [Byte0]: 28
7776 11:36:41.922765 [Byte1]: 28
7777 11:36:41.926978
7778 11:36:41.927361 Set Vref, RX VrefLevel [Byte0]: 29
7779 11:36:41.930166 [Byte1]: 29
7780 11:36:41.934944
7781 11:36:41.935448 Set Vref, RX VrefLevel [Byte0]: 30
7782 11:36:41.937704 [Byte1]: 30
7783 11:36:41.942104
7784 11:36:41.942586 Set Vref, RX VrefLevel [Byte0]: 31
7785 11:36:41.945312 [Byte1]: 31
7786 11:36:41.949926
7787 11:36:41.950356 Set Vref, RX VrefLevel [Byte0]: 32
7788 11:36:41.953421 [Byte1]: 32
7789 11:36:41.957539
7790 11:36:41.957946 Set Vref, RX VrefLevel [Byte0]: 33
7791 11:36:41.960913 [Byte1]: 33
7792 11:36:41.964828
7793 11:36:41.965226 Set Vref, RX VrefLevel [Byte0]: 34
7794 11:36:41.971773 [Byte1]: 34
7795 11:36:41.972196
7796 11:36:41.974660 Set Vref, RX VrefLevel [Byte0]: 35
7797 11:36:41.977805 [Byte1]: 35
7798 11:36:41.978245
7799 11:36:41.981484 Set Vref, RX VrefLevel [Byte0]: 36
7800 11:36:41.984806 [Byte1]: 36
7801 11:36:41.985189
7802 11:36:41.987800 Set Vref, RX VrefLevel [Byte0]: 37
7803 11:36:41.991624 [Byte1]: 37
7804 11:36:41.994905
7805 11:36:41.995268 Set Vref, RX VrefLevel [Byte0]: 38
7806 11:36:41.998124 [Byte1]: 38
7807 11:36:42.002709
7808 11:36:42.003006 Set Vref, RX VrefLevel [Byte0]: 39
7809 11:36:42.006130 [Byte1]: 39
7810 11:36:42.010280
7811 11:36:42.010543 Set Vref, RX VrefLevel [Byte0]: 40
7812 11:36:42.013776 [Byte1]: 40
7813 11:36:42.017600
7814 11:36:42.017803 Set Vref, RX VrefLevel [Byte0]: 41
7815 11:36:42.020893 [Byte1]: 41
7816 11:36:42.025094
7817 11:36:42.025299 Set Vref, RX VrefLevel [Byte0]: 42
7818 11:36:42.028940 [Byte1]: 42
7819 11:36:42.032905
7820 11:36:42.033109 Set Vref, RX VrefLevel [Byte0]: 43
7821 11:36:42.036230 [Byte1]: 43
7822 11:36:42.040389
7823 11:36:42.040602 Set Vref, RX VrefLevel [Byte0]: 44
7824 11:36:42.043852 [Byte1]: 44
7825 11:36:42.048522
7826 11:36:42.048792 Set Vref, RX VrefLevel [Byte0]: 45
7827 11:36:42.051467 [Byte1]: 45
7828 11:36:42.055716
7829 11:36:42.056022 Set Vref, RX VrefLevel [Byte0]: 46
7830 11:36:42.058941 [Byte1]: 46
7831 11:36:42.063460
7832 11:36:42.063998 Set Vref, RX VrefLevel [Byte0]: 47
7833 11:36:42.066563 [Byte1]: 47
7834 11:36:42.071135
7835 11:36:42.071521 Set Vref, RX VrefLevel [Byte0]: 48
7836 11:36:42.074670 [Byte1]: 48
7837 11:36:42.078666
7838 11:36:42.078985 Set Vref, RX VrefLevel [Byte0]: 49
7839 11:36:42.081827 [Byte1]: 49
7840 11:36:42.085565
7841 11:36:42.085887 Set Vref, RX VrefLevel [Byte0]: 50
7842 11:36:42.089400 [Byte1]: 50
7843 11:36:42.093350
7844 11:36:42.093708 Set Vref, RX VrefLevel [Byte0]: 51
7845 11:36:42.097053 [Byte1]: 51
7846 11:36:42.100936
7847 11:36:42.101302 Set Vref, RX VrefLevel [Byte0]: 52
7848 11:36:42.104391 [Byte1]: 52
7849 11:36:42.109512
7850 11:36:42.109862 Set Vref, RX VrefLevel [Byte0]: 53
7851 11:36:42.112424 [Byte1]: 53
7852 11:36:42.116712
7853 11:36:42.117068 Set Vref, RX VrefLevel [Byte0]: 54
7854 11:36:42.119557 [Byte1]: 54
7855 11:36:42.124278
7856 11:36:42.124598 Set Vref, RX VrefLevel [Byte0]: 55
7857 11:36:42.127611 [Byte1]: 55
7858 11:36:42.131416
7859 11:36:42.131766 Set Vref, RX VrefLevel [Byte0]: 56
7860 11:36:42.134728 [Byte1]: 56
7861 11:36:42.139077
7862 11:36:42.139396 Set Vref, RX VrefLevel [Byte0]: 57
7863 11:36:42.142343 [Byte1]: 57
7864 11:36:42.146518
7865 11:36:42.146895 Set Vref, RX VrefLevel [Byte0]: 58
7866 11:36:42.150435 [Byte1]: 58
7867 11:36:42.154523
7868 11:36:42.154898 Set Vref, RX VrefLevel [Byte0]: 59
7869 11:36:42.157810 [Byte1]: 59
7870 11:36:42.161599
7871 11:36:42.161933 Set Vref, RX VrefLevel [Byte0]: 60
7872 11:36:42.164819 [Byte1]: 60
7873 11:36:42.169279
7874 11:36:42.169509 Set Vref, RX VrefLevel [Byte0]: 61
7875 11:36:42.172645 [Byte1]: 61
7876 11:36:42.176910
7877 11:36:42.177091 Set Vref, RX VrefLevel [Byte0]: 62
7878 11:36:42.180087 [Byte1]: 62
7879 11:36:42.184310
7880 11:36:42.184531 Set Vref, RX VrefLevel [Byte0]: 63
7881 11:36:42.187465 [Byte1]: 63
7882 11:36:42.191786
7883 11:36:42.191969 Set Vref, RX VrefLevel [Byte0]: 64
7884 11:36:42.195343 [Byte1]: 64
7885 11:36:42.199650
7886 11:36:42.199798 Set Vref, RX VrefLevel [Byte0]: 65
7887 11:36:42.203133 [Byte1]: 65
7888 11:36:42.207230
7889 11:36:42.207442 Set Vref, RX VrefLevel [Byte0]: 66
7890 11:36:42.210949 [Byte1]: 66
7891 11:36:42.214919
7892 11:36:42.215139 Set Vref, RX VrefLevel [Byte0]: 67
7893 11:36:42.218050 [Byte1]: 67
7894 11:36:42.222423
7895 11:36:42.222745 Set Vref, RX VrefLevel [Byte0]: 68
7896 11:36:42.226030 [Byte1]: 68
7897 11:36:42.230919
7898 11:36:42.231318 Set Vref, RX VrefLevel [Byte0]: 69
7899 11:36:42.233029 [Byte1]: 69
7900 11:36:42.237615
7901 11:36:42.238113 Set Vref, RX VrefLevel [Byte0]: 70
7902 11:36:42.241007 [Byte1]: 70
7903 11:36:42.245848
7904 11:36:42.246368 Set Vref, RX VrefLevel [Byte0]: 71
7905 11:36:42.248477 [Byte1]: 71
7906 11:36:42.252909
7907 11:36:42.253404 Set Vref, RX VrefLevel [Byte0]: 72
7908 11:36:42.256346 [Byte1]: 72
7909 11:36:42.260621
7910 11:36:42.261041 Set Vref, RX VrefLevel [Byte0]: 73
7911 11:36:42.263930 [Byte1]: 73
7912 11:36:42.267954
7913 11:36:42.268431 Set Vref, RX VrefLevel [Byte0]: 74
7914 11:36:42.271407 [Byte1]: 74
7915 11:36:42.275218
7916 11:36:42.275692 Final RX Vref Byte 0 = 60 to rank0
7917 11:36:42.279087 Final RX Vref Byte 1 = 59 to rank0
7918 11:36:42.281793 Final RX Vref Byte 0 = 60 to rank1
7919 11:36:42.285911 Final RX Vref Byte 1 = 59 to rank1==
7920 11:36:42.288728 Dram Type= 6, Freq= 0, CH_0, rank 0
7921 11:36:42.295100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7922 11:36:42.295634 ==
7923 11:36:42.296098 DQS Delay:
7924 11:36:42.296521 DQS0 = 0, DQS1 = 0
7925 11:36:42.298466 DQM Delay:
7926 11:36:42.298962 DQM0 = 134, DQM1 = 127
7927 11:36:42.302085 DQ Delay:
7928 11:36:42.305204 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7929 11:36:42.308458 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7930 11:36:42.311755 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7931 11:36:42.314914 DQ12 =132, DQ13 =130, DQ14 =138, DQ15 =134
7932 11:36:42.315291
7933 11:36:42.315608
7934 11:36:42.315907
7935 11:36:42.318627 [DramC_TX_OE_Calibration] TA2
7936 11:36:42.321916 Original DQ_B0 (3 6) =30, OEN = 27
7937 11:36:42.324926 Original DQ_B1 (3 6) =30, OEN = 27
7938 11:36:42.328154 24, 0x0, End_B0=24 End_B1=24
7939 11:36:42.328344 25, 0x0, End_B0=25 End_B1=25
7940 11:36:42.331687 26, 0x0, End_B0=26 End_B1=26
7941 11:36:42.334785 27, 0x0, End_B0=27 End_B1=27
7942 11:36:42.337826 28, 0x0, End_B0=28 End_B1=28
7943 11:36:42.341703 29, 0x0, End_B0=29 End_B1=29
7944 11:36:42.341843 30, 0x0, End_B0=30 End_B1=30
7945 11:36:42.345252 31, 0x4141, End_B0=30 End_B1=30
7946 11:36:42.348225 Byte0 end_step=30 best_step=27
7947 11:36:42.351338 Byte1 end_step=30 best_step=27
7948 11:36:42.354991 Byte0 TX OE(2T, 0.5T) = (3, 3)
7949 11:36:42.358033 Byte1 TX OE(2T, 0.5T) = (3, 3)
7950 11:36:42.358196
7951 11:36:42.358306
7952 11:36:42.364884 [DQSOSCAuto] RK0, (LSB)MR18= 0x2924, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
7953 11:36:42.368361 CH0 RK0: MR19=303, MR18=2924
7954 11:36:42.375018 CH0_RK0: MR19=0x303, MR18=0x2924, DQSOSC=389, MR23=63, INC=24, DEC=16
7955 11:36:42.375205
7956 11:36:42.377904 ----->DramcWriteLeveling(PI) begin...
7957 11:36:42.378072 ==
7958 11:36:42.381034 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 11:36:42.385001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 11:36:42.385188 ==
7961 11:36:42.388182 Write leveling (Byte 0): 39 => 39
7962 11:36:42.391078 Write leveling (Byte 1): 26 => 26
7963 11:36:42.394694 DramcWriteLeveling(PI) end<-----
7964 11:36:42.394869
7965 11:36:42.394979 ==
7966 11:36:42.398043 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 11:36:42.401448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 11:36:42.401588 ==
7969 11:36:42.404570 [Gating] SW mode calibration
7970 11:36:42.410926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7971 11:36:42.417788 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7972 11:36:42.420914 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7973 11:36:42.424603 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7974 11:36:42.431069 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7975 11:36:42.434407 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7976 11:36:42.438143 1 4 16 | B1->B0 | 3232 3737 | 1 1 | (1 1) (0 0)
7977 11:36:42.444666 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 11:36:42.447706 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7979 11:36:42.450987 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7980 11:36:42.457917 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7981 11:36:42.460801 1 5 4 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7982 11:36:42.464857 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 0) (0 0)
7983 11:36:42.470885 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
7984 11:36:42.474179 1 5 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
7985 11:36:42.478137 1 5 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7986 11:36:42.484656 1 5 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7987 11:36:42.487850 1 5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7988 11:36:42.491215 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7989 11:36:42.498128 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7990 11:36:42.501753 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7991 11:36:42.504580 1 6 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (1 1)
7992 11:36:42.511551 1 6 16 | B1->B0 | 4040 4645 | 0 1 | (0 0) (0 0)
7993 11:36:42.514971 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7994 11:36:42.517727 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 11:36:42.524880 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 11:36:42.528210 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 11:36:42.531328 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 11:36:42.534727 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 11:36:42.541779 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 11:36:42.544997 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8001 11:36:42.548014 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:36:42.555306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:36:42.558690 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:36:42.561379 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:36:42.567801 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:36:42.571156 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:36:42.574284 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:36:42.581198 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:36:42.584628 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:36:42.587636 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:36:42.594541 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:36:42.598043 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:36:42.600795 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:36:42.607888 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8015 11:36:42.611215 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8016 11:36:42.614468 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8017 11:36:42.621210 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 11:36:42.621715 Total UI for P1: 0, mck2ui 16
8019 11:36:42.627174 best dqsien dly found for B0: ( 1, 9, 12)
8020 11:36:42.627669 Total UI for P1: 0, mck2ui 16
8021 11:36:42.633989 best dqsien dly found for B1: ( 1, 9, 14)
8022 11:36:42.637390 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8023 11:36:42.640424 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8024 11:36:42.640853
8025 11:36:42.644389 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8026 11:36:42.647653 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8027 11:36:42.651106 [Gating] SW calibration Done
8028 11:36:42.651600 ==
8029 11:36:42.654239 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 11:36:42.657683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 11:36:42.658223 ==
8032 11:36:42.660975 RX Vref Scan: 0
8033 11:36:42.661396
8034 11:36:42.661727 RX Vref 0 -> 0, step: 1
8035 11:36:42.664060
8036 11:36:42.664535 RX Delay 0 -> 252, step: 8
8037 11:36:42.667140 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8038 11:36:42.673870 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8039 11:36:42.677319 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8040 11:36:42.680666 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8041 11:36:42.683492 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8042 11:36:42.686892 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8043 11:36:42.694074 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8044 11:36:42.696972 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8045 11:36:42.700221 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8046 11:36:42.703447 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8047 11:36:42.707103 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8048 11:36:42.713802 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8049 11:36:42.717179 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8050 11:36:42.720820 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8051 11:36:42.723439 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8052 11:36:42.730087 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8053 11:36:42.730556 ==
8054 11:36:42.733532 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 11:36:42.737134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 11:36:42.737603 ==
8057 11:36:42.738329 DQS Delay:
8058 11:36:42.740126 DQS0 = 0, DQS1 = 0
8059 11:36:42.740544 DQM Delay:
8060 11:36:42.743639 DQM0 = 136, DQM1 = 128
8061 11:36:42.744024 DQ Delay:
8062 11:36:42.746845 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8063 11:36:42.750240 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8064 11:36:42.753378 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8065 11:36:42.756624 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8066 11:36:42.757192
8067 11:36:42.757506
8068 11:36:42.759779 ==
8069 11:36:42.760307 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 11:36:42.767072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 11:36:42.767496 ==
8072 11:36:42.767993
8073 11:36:42.768421
8074 11:36:42.769506 TX Vref Scan disable
8075 11:36:42.770093 == TX Byte 0 ==
8076 11:36:42.773356 Update DQ dly =996 (3 ,6, 36) DQ OEN =(3 ,3)
8077 11:36:42.780309 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8078 11:36:42.780696 == TX Byte 1 ==
8079 11:36:42.783493 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8080 11:36:42.789952 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8081 11:36:42.790375 ==
8082 11:36:42.793455 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 11:36:42.796283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 11:36:42.796678 ==
8085 11:36:42.812022
8086 11:36:42.815442 TX Vref early break, caculate TX vref
8087 11:36:42.818689 TX Vref=16, minBit 1, minWin=22, winSum=385
8088 11:36:42.822112 TX Vref=18, minBit 1, minWin=23, winSum=396
8089 11:36:42.825477 TX Vref=20, minBit 1, minWin=23, winSum=404
8090 11:36:42.829135 TX Vref=22, minBit 1, minWin=24, winSum=414
8091 11:36:42.832620 TX Vref=24, minBit 0, minWin=25, winSum=424
8092 11:36:42.839281 TX Vref=26, minBit 1, minWin=25, winSum=425
8093 11:36:42.842124 TX Vref=28, minBit 4, minWin=25, winSum=425
8094 11:36:42.845577 TX Vref=30, minBit 4, minWin=25, winSum=417
8095 11:36:42.849157 TX Vref=32, minBit 0, minWin=25, winSum=410
8096 11:36:42.852524 TX Vref=34, minBit 5, minWin=24, winSum=406
8097 11:36:42.855536 TX Vref=36, minBit 4, minWin=23, winSum=392
8098 11:36:42.862185 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8099 11:36:42.862582
8100 11:36:42.865546 Final TX Range 0 Vref 26
8101 11:36:42.865942
8102 11:36:42.866298 ==
8103 11:36:42.868758 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 11:36:42.872040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 11:36:42.872463 ==
8106 11:36:42.872765
8107 11:36:42.873037
8108 11:36:42.875764 TX Vref Scan disable
8109 11:36:42.882489 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8110 11:36:42.882945 == TX Byte 0 ==
8111 11:36:42.885908 u2DelayCellOfst[0]=13 cells (4 PI)
8112 11:36:42.889056 u2DelayCellOfst[1]=13 cells (4 PI)
8113 11:36:42.892605 u2DelayCellOfst[2]=10 cells (3 PI)
8114 11:36:42.895932 u2DelayCellOfst[3]=10 cells (3 PI)
8115 11:36:42.898797 u2DelayCellOfst[4]=10 cells (3 PI)
8116 11:36:42.902540 u2DelayCellOfst[5]=0 cells (0 PI)
8117 11:36:42.905376 u2DelayCellOfst[6]=17 cells (5 PI)
8118 11:36:42.908955 u2DelayCellOfst[7]=17 cells (5 PI)
8119 11:36:42.912572 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8120 11:36:42.915367 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8121 11:36:42.918546 == TX Byte 1 ==
8122 11:36:42.922148 u2DelayCellOfst[8]=3 cells (1 PI)
8123 11:36:42.925579 u2DelayCellOfst[9]=0 cells (0 PI)
8124 11:36:42.926125 u2DelayCellOfst[10]=6 cells (2 PI)
8125 11:36:42.928878 u2DelayCellOfst[11]=3 cells (1 PI)
8126 11:36:42.932175 u2DelayCellOfst[12]=10 cells (3 PI)
8127 11:36:42.935979 u2DelayCellOfst[13]=10 cells (3 PI)
8128 11:36:42.938918 u2DelayCellOfst[14]=13 cells (4 PI)
8129 11:36:42.941893 u2DelayCellOfst[15]=10 cells (3 PI)
8130 11:36:42.949073 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8131 11:36:42.951980 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8132 11:36:42.952405 DramC Write-DBI on
8133 11:36:42.952733 ==
8134 11:36:42.955541 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:36:42.961838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:36:42.962376 ==
8137 11:36:42.962748
8138 11:36:42.963058
8139 11:36:42.963347 TX Vref Scan disable
8140 11:36:42.966423 == TX Byte 0 ==
8141 11:36:42.969349 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
8142 11:36:42.972841 == TX Byte 1 ==
8143 11:36:42.976040 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8144 11:36:42.979234 DramC Write-DBI off
8145 11:36:42.979628
8146 11:36:42.979926 [DATLAT]
8147 11:36:42.980202 Freq=1600, CH0 RK1
8148 11:36:42.980465
8149 11:36:42.982949 DATLAT Default: 0xf
8150 11:36:42.983328 0, 0xFFFF, sum = 0
8151 11:36:42.986393 1, 0xFFFF, sum = 0
8152 11:36:42.986857 2, 0xFFFF, sum = 0
8153 11:36:42.989217 3, 0xFFFF, sum = 0
8154 11:36:42.989606 4, 0xFFFF, sum = 0
8155 11:36:42.993055 5, 0xFFFF, sum = 0
8156 11:36:42.996676 6, 0xFFFF, sum = 0
8157 11:36:42.997183 7, 0xFFFF, sum = 0
8158 11:36:42.999664 8, 0xFFFF, sum = 0
8159 11:36:43.000093 9, 0xFFFF, sum = 0
8160 11:36:43.002860 10, 0xFFFF, sum = 0
8161 11:36:43.003289 11, 0xFFFF, sum = 0
8162 11:36:43.005879 12, 0xFFFF, sum = 0
8163 11:36:43.006325 13, 0xFFFF, sum = 0
8164 11:36:43.009688 14, 0x0, sum = 1
8165 11:36:43.010233 15, 0x0, sum = 2
8166 11:36:43.013381 16, 0x0, sum = 3
8167 11:36:43.013884 17, 0x0, sum = 4
8168 11:36:43.016544 best_step = 15
8169 11:36:43.017038
8170 11:36:43.017368 ==
8171 11:36:43.019905 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 11:36:43.022560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 11:36:43.022985 ==
8174 11:36:43.023313 RX Vref Scan: 0
8175 11:36:43.023618
8176 11:36:43.026489 RX Vref 0 -> 0, step: 1
8177 11:36:43.026913
8178 11:36:43.029460 RX Delay 19 -> 252, step: 4
8179 11:36:43.032816 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8180 11:36:43.039435 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8181 11:36:43.042458 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8182 11:36:43.046432 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8183 11:36:43.049379 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8184 11:36:43.052494 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8185 11:36:43.058937 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8186 11:36:43.062719 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8187 11:36:43.066170 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8188 11:36:43.069572 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8189 11:36:43.072470 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8190 11:36:43.079130 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8191 11:36:43.082543 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8192 11:36:43.086453 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8193 11:36:43.089299 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8194 11:36:43.092628 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8195 11:36:43.095748 ==
8196 11:36:43.096128 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 11:36:43.102600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 11:36:43.103060 ==
8199 11:36:43.103389 DQS Delay:
8200 11:36:43.105820 DQS0 = 0, DQS1 = 0
8201 11:36:43.106258 DQM Delay:
8202 11:36:43.109598 DQM0 = 134, DQM1 = 127
8203 11:36:43.110104 DQ Delay:
8204 11:36:43.112701 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8205 11:36:43.116192 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8206 11:36:43.119301 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8207 11:36:43.122561 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
8208 11:36:43.122946
8209 11:36:43.123239
8210 11:36:43.123509
8211 11:36:43.125684 [DramC_TX_OE_Calibration] TA2
8212 11:36:43.129460 Original DQ_B0 (3 6) =30, OEN = 27
8213 11:36:43.132153 Original DQ_B1 (3 6) =30, OEN = 27
8214 11:36:43.135952 24, 0x0, End_B0=24 End_B1=24
8215 11:36:43.138935 25, 0x0, End_B0=25 End_B1=25
8216 11:36:43.139321 26, 0x0, End_B0=26 End_B1=26
8217 11:36:43.141993 27, 0x0, End_B0=27 End_B1=27
8218 11:36:43.145606 28, 0x0, End_B0=28 End_B1=28
8219 11:36:43.148981 29, 0x0, End_B0=29 End_B1=29
8220 11:36:43.149486 30, 0x0, End_B0=30 End_B1=30
8221 11:36:43.152200 31, 0x4545, End_B0=30 End_B1=30
8222 11:36:43.155544 Byte0 end_step=30 best_step=27
8223 11:36:43.159502 Byte1 end_step=30 best_step=27
8224 11:36:43.162736 Byte0 TX OE(2T, 0.5T) = (3, 3)
8225 11:36:43.165623 Byte1 TX OE(2T, 0.5T) = (3, 3)
8226 11:36:43.166072
8227 11:36:43.166409
8228 11:36:43.172280 [DQSOSCAuto] RK1, (LSB)MR18= 0x2007, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8229 11:36:43.175665 CH0 RK1: MR19=303, MR18=2007
8230 11:36:43.182037 CH0_RK1: MR19=0x303, MR18=0x2007, DQSOSC=393, MR23=63, INC=23, DEC=15
8231 11:36:43.185636 [RxdqsGatingPostProcess] freq 1600
8232 11:36:43.188485 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8233 11:36:43.192452 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 11:36:43.195567 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 11:36:43.198526 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 11:36:43.202565 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 11:36:43.206087 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 11:36:43.208755 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 11:36:43.212096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 11:36:43.215228 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 11:36:43.218750 Pre-setting of DQS Precalculation
8242 11:36:43.222053 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8243 11:36:43.222560 ==
8244 11:36:43.225634 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 11:36:43.232045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 11:36:43.232473 ==
8247 11:36:43.235530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8248 11:36:43.241799 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8249 11:36:43.245094 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8250 11:36:43.251233 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8251 11:36:43.259191 [CA 0] Center 41 (12~71) winsize 60
8252 11:36:43.262616 [CA 1] Center 41 (11~71) winsize 61
8253 11:36:43.265899 [CA 2] Center 38 (8~68) winsize 61
8254 11:36:43.269077 [CA 3] Center 37 (9~66) winsize 58
8255 11:36:43.272144 [CA 4] Center 38 (9~67) winsize 59
8256 11:36:43.275528 [CA 5] Center 36 (7~66) winsize 60
8257 11:36:43.275951
8258 11:36:43.278722 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8259 11:36:43.279108
8260 11:36:43.282881 [CATrainingPosCal] consider 1 rank data
8261 11:36:43.286002 u2DelayCellTimex100 = 285/100 ps
8262 11:36:43.289414 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8263 11:36:43.295957 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8264 11:36:43.299298 CA2 delay=38 (8~68),Diff = 2 PI (6 cell)
8265 11:36:43.302568 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8266 11:36:43.305743 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8267 11:36:43.308908 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8268 11:36:43.309334
8269 11:36:43.312456 CA PerBit enable=1, Macro0, CA PI delay=36
8270 11:36:43.312956
8271 11:36:43.315242 [CBTSetCACLKResult] CA Dly = 36
8272 11:36:43.319192 CS Dly: 10 (0~41)
8273 11:36:43.322621 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8274 11:36:43.325988 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8275 11:36:43.326535 ==
8276 11:36:43.329444 Dram Type= 6, Freq= 0, CH_1, rank 1
8277 11:36:43.332705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 11:36:43.333223 ==
8279 11:36:43.339228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 11:36:43.342355 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 11:36:43.349085 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 11:36:43.352316 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 11:36:43.362222 [CA 0] Center 42 (12~72) winsize 61
8284 11:36:43.365674 [CA 1] Center 42 (12~72) winsize 61
8285 11:36:43.369101 [CA 2] Center 38 (9~68) winsize 60
8286 11:36:43.372410 [CA 3] Center 37 (8~67) winsize 60
8287 11:36:43.375423 [CA 4] Center 38 (8~68) winsize 61
8288 11:36:43.378674 [CA 5] Center 37 (8~67) winsize 60
8289 11:36:43.379096
8290 11:36:43.382177 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8291 11:36:43.382691
8292 11:36:43.386224 [CATrainingPosCal] consider 2 rank data
8293 11:36:43.389246 u2DelayCellTimex100 = 285/100 ps
8294 11:36:43.392484 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8295 11:36:43.399026 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8296 11:36:43.402687 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8297 11:36:43.405304 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8298 11:36:43.409358 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8299 11:36:43.412255 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8300 11:36:43.412681
8301 11:36:43.415454 CA PerBit enable=1, Macro0, CA PI delay=37
8302 11:36:43.415875
8303 11:36:43.418809 [CBTSetCACLKResult] CA Dly = 37
8304 11:36:43.422414 CS Dly: 11 (0~44)
8305 11:36:43.425214 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 11:36:43.428625 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 11:36:43.429019
8308 11:36:43.432055 ----->DramcWriteLeveling(PI) begin...
8309 11:36:43.432441 ==
8310 11:36:43.435374 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 11:36:43.438456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 11:36:43.441802 ==
8313 11:36:43.442216 Write leveling (Byte 0): 25 => 25
8314 11:36:43.445937 Write leveling (Byte 1): 30 => 30
8315 11:36:43.448596 DramcWriteLeveling(PI) end<-----
8316 11:36:43.449047
8317 11:36:43.449342 ==
8318 11:36:43.451904 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 11:36:43.458906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 11:36:43.459290 ==
8321 11:36:43.461945 [Gating] SW mode calibration
8322 11:36:43.468876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8323 11:36:43.471739 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8324 11:36:43.478218 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 11:36:43.481705 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 11:36:43.485128 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8327 11:36:43.491796 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8328 11:36:43.494620 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:36:43.498685 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 11:36:43.504813 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 11:36:43.508087 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 11:36:43.511529 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 11:36:43.518908 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 11:36:43.521754 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8335 11:36:43.524702 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
8336 11:36:43.528001 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:36:43.535047 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 11:36:43.537920 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 11:36:43.541315 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 11:36:43.548456 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 11:36:43.551918 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 11:36:43.554978 1 6 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8343 11:36:43.561711 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8344 11:36:43.565100 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:36:43.568118 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:36:43.574971 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 11:36:43.577996 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 11:36:43.581921 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 11:36:43.588205 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 11:36:43.591034 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8351 11:36:43.595022 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8352 11:36:43.601507 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:36:43.604865 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:36:43.607889 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:36:43.614318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:36:43.618079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:36:43.620616 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:36:43.627937 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:36:43.631357 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:36:43.634134 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:36:43.640936 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:36:43.644518 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:36:43.647928 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:36:43.654697 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:36:43.658131 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:36:43.661174 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8367 11:36:43.664796 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 11:36:43.671181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:36:43.674476 Total UI for P1: 0, mck2ui 16
8370 11:36:43.677964 best dqsien dly found for B0: ( 1, 9, 10)
8371 11:36:43.681406 Total UI for P1: 0, mck2ui 16
8372 11:36:43.684265 best dqsien dly found for B1: ( 1, 9, 10)
8373 11:36:43.687433 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8374 11:36:43.690634 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8375 11:36:43.691020
8376 11:36:43.694718 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8377 11:36:43.697866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 11:36:43.700960 [Gating] SW calibration Done
8379 11:36:43.701457 ==
8380 11:36:43.703991 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 11:36:43.707357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 11:36:43.707787 ==
8383 11:36:43.710820 RX Vref Scan: 0
8384 11:36:43.711310
8385 11:36:43.714746 RX Vref 0 -> 0, step: 1
8386 11:36:43.715241
8387 11:36:43.715569 RX Delay 0 -> 252, step: 8
8388 11:36:43.718301 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8389 11:36:43.724860 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8390 11:36:43.727342 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8391 11:36:43.731251 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8392 11:36:43.734420 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8393 11:36:43.737401 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8394 11:36:43.744347 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8395 11:36:43.748409 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8396 11:36:43.751304 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8397 11:36:43.754084 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8398 11:36:43.757926 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8399 11:36:43.764708 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8400 11:36:43.767459 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8401 11:36:43.770597 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8402 11:36:43.773983 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8403 11:36:43.780557 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8404 11:36:43.781088 ==
8405 11:36:43.783720 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 11:36:43.787331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 11:36:43.787734 ==
8408 11:36:43.788118 DQS Delay:
8409 11:36:43.790240 DQS0 = 0, DQS1 = 0
8410 11:36:43.790722 DQM Delay:
8411 11:36:43.793485 DQM0 = 137, DQM1 = 132
8412 11:36:43.794156 DQ Delay:
8413 11:36:43.797224 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8414 11:36:43.800521 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8415 11:36:43.803548 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8416 11:36:43.807479 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8417 11:36:43.808156
8418 11:36:43.808670
8419 11:36:43.810720 ==
8420 11:36:43.811106 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 11:36:43.816947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 11:36:43.817445 ==
8423 11:36:43.817758
8424 11:36:43.818085
8425 11:36:43.820235 TX Vref Scan disable
8426 11:36:43.820619 == TX Byte 0 ==
8427 11:36:43.823558 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8428 11:36:43.830351 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8429 11:36:43.830754 == TX Byte 1 ==
8430 11:36:43.833413 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8431 11:36:43.840707 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8432 11:36:43.841169 ==
8433 11:36:43.843811 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 11:36:43.846726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 11:36:43.847115 ==
8436 11:36:43.860520
8437 11:36:43.863491 TX Vref early break, caculate TX vref
8438 11:36:43.866562 TX Vref=16, minBit 0, minWin=23, winSum=376
8439 11:36:43.870052 TX Vref=18, minBit 6, minWin=23, winSum=387
8440 11:36:43.872962 TX Vref=20, minBit 1, minWin=23, winSum=396
8441 11:36:43.877069 TX Vref=22, minBit 1, minWin=24, winSum=407
8442 11:36:43.880436 TX Vref=24, minBit 0, minWin=25, winSum=413
8443 11:36:43.886541 TX Vref=26, minBit 6, minWin=25, winSum=425
8444 11:36:43.890123 TX Vref=28, minBit 0, minWin=26, winSum=425
8445 11:36:43.893690 TX Vref=30, minBit 0, minWin=24, winSum=421
8446 11:36:43.896659 TX Vref=32, minBit 0, minWin=25, winSum=413
8447 11:36:43.900435 TX Vref=34, minBit 0, minWin=23, winSum=402
8448 11:36:43.906791 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8449 11:36:43.907296
8450 11:36:43.909632 Final TX Range 0 Vref 28
8451 11:36:43.910075
8452 11:36:43.910411 ==
8453 11:36:43.913136 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 11:36:43.916811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 11:36:43.917311 ==
8456 11:36:43.917643
8457 11:36:43.917947
8458 11:36:43.919848 TX Vref Scan disable
8459 11:36:43.926578 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8460 11:36:43.927065 == TX Byte 0 ==
8461 11:36:43.929894 u2DelayCellOfst[0]=17 cells (5 PI)
8462 11:36:43.933389 u2DelayCellOfst[1]=10 cells (3 PI)
8463 11:36:43.936825 u2DelayCellOfst[2]=0 cells (0 PI)
8464 11:36:43.940203 u2DelayCellOfst[3]=3 cells (1 PI)
8465 11:36:43.943108 u2DelayCellOfst[4]=6 cells (2 PI)
8466 11:36:43.946434 u2DelayCellOfst[5]=17 cells (5 PI)
8467 11:36:43.949473 u2DelayCellOfst[6]=17 cells (5 PI)
8468 11:36:43.949901 u2DelayCellOfst[7]=3 cells (1 PI)
8469 11:36:43.956098 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8470 11:36:43.959225 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8471 11:36:43.959615 == TX Byte 1 ==
8472 11:36:43.962633 u2DelayCellOfst[8]=0 cells (0 PI)
8473 11:36:43.965973 u2DelayCellOfst[9]=3 cells (1 PI)
8474 11:36:43.969296 u2DelayCellOfst[10]=10 cells (3 PI)
8475 11:36:43.972564 u2DelayCellOfst[11]=3 cells (1 PI)
8476 11:36:43.976216 u2DelayCellOfst[12]=13 cells (4 PI)
8477 11:36:43.979617 u2DelayCellOfst[13]=13 cells (4 PI)
8478 11:36:43.982974 u2DelayCellOfst[14]=17 cells (5 PI)
8479 11:36:43.986372 u2DelayCellOfst[15]=17 cells (5 PI)
8480 11:36:43.989572 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8481 11:36:43.996096 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8482 11:36:43.996546 DramC Write-DBI on
8483 11:36:43.996847 ==
8484 11:36:43.999690 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:36:44.002632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:36:44.006074 ==
8487 11:36:44.006541
8488 11:36:44.006849
8489 11:36:44.007129 TX Vref Scan disable
8490 11:36:44.009668 == TX Byte 0 ==
8491 11:36:44.013284 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8492 11:36:44.016311 == TX Byte 1 ==
8493 11:36:44.019472 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8494 11:36:44.023141 DramC Write-DBI off
8495 11:36:44.023637
8496 11:36:44.023972 [DATLAT]
8497 11:36:44.024283 Freq=1600, CH1 RK0
8498 11:36:44.024579
8499 11:36:44.026065 DATLAT Default: 0xf
8500 11:36:44.026496 0, 0xFFFF, sum = 0
8501 11:36:44.029005 1, 0xFFFF, sum = 0
8502 11:36:44.032371 2, 0xFFFF, sum = 0
8503 11:36:44.032805 3, 0xFFFF, sum = 0
8504 11:36:44.035893 4, 0xFFFF, sum = 0
8505 11:36:44.036340 5, 0xFFFF, sum = 0
8506 11:36:44.039309 6, 0xFFFF, sum = 0
8507 11:36:44.039702 7, 0xFFFF, sum = 0
8508 11:36:44.042300 8, 0xFFFF, sum = 0
8509 11:36:44.042721 9, 0xFFFF, sum = 0
8510 11:36:44.045727 10, 0xFFFF, sum = 0
8511 11:36:44.046137 11, 0xFFFF, sum = 0
8512 11:36:44.049130 12, 0xFFFF, sum = 0
8513 11:36:44.049599 13, 0xFFFF, sum = 0
8514 11:36:44.052581 14, 0x0, sum = 1
8515 11:36:44.053061 15, 0x0, sum = 2
8516 11:36:44.055537 16, 0x0, sum = 3
8517 11:36:44.055968 17, 0x0, sum = 4
8518 11:36:44.059232 best_step = 15
8519 11:36:44.059610
8520 11:36:44.059905 ==
8521 11:36:44.062439 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 11:36:44.066125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 11:36:44.066512 ==
8524 11:36:44.066815 RX Vref Scan: 1
8525 11:36:44.069371
8526 11:36:44.069750 Set Vref Range= 24 -> 127
8527 11:36:44.070084
8528 11:36:44.072564 RX Vref 24 -> 127, step: 1
8529 11:36:44.072947
8530 11:36:44.076286 RX Delay 27 -> 252, step: 4
8531 11:36:44.076741
8532 11:36:44.079321 Set Vref, RX VrefLevel [Byte0]: 24
8533 11:36:44.082808 [Byte1]: 24
8534 11:36:44.083189
8535 11:36:44.085965 Set Vref, RX VrefLevel [Byte0]: 25
8536 11:36:44.089573 [Byte1]: 25
8537 11:36:44.089960
8538 11:36:44.092949 Set Vref, RX VrefLevel [Byte0]: 26
8539 11:36:44.096200 [Byte1]: 26
8540 11:36:44.099921
8541 11:36:44.100380 Set Vref, RX VrefLevel [Byte0]: 27
8542 11:36:44.103060 [Byte1]: 27
8543 11:36:44.106967
8544 11:36:44.107421 Set Vref, RX VrefLevel [Byte0]: 28
8545 11:36:44.113967 [Byte1]: 28
8546 11:36:44.114462
8547 11:36:44.117128 Set Vref, RX VrefLevel [Byte0]: 29
8548 11:36:44.120809 [Byte1]: 29
8549 11:36:44.121305
8550 11:36:44.124021 Set Vref, RX VrefLevel [Byte0]: 30
8551 11:36:44.126634 [Byte1]: 30
8552 11:36:44.127130
8553 11:36:44.130184 Set Vref, RX VrefLevel [Byte0]: 31
8554 11:36:44.133572 [Byte1]: 31
8555 11:36:44.137700
8556 11:36:44.138237 Set Vref, RX VrefLevel [Byte0]: 32
8557 11:36:44.140407 [Byte1]: 32
8558 11:36:44.144430
8559 11:36:44.144899 Set Vref, RX VrefLevel [Byte0]: 33
8560 11:36:44.148502 [Byte1]: 33
8561 11:36:44.152684
8562 11:36:44.153178 Set Vref, RX VrefLevel [Byte0]: 34
8563 11:36:44.155426 [Byte1]: 34
8564 11:36:44.160084
8565 11:36:44.160577 Set Vref, RX VrefLevel [Byte0]: 35
8566 11:36:44.163301 [Byte1]: 35
8567 11:36:44.167355
8568 11:36:44.167793 Set Vref, RX VrefLevel [Byte0]: 36
8569 11:36:44.170391 [Byte1]: 36
8570 11:36:44.175106
8571 11:36:44.175488 Set Vref, RX VrefLevel [Byte0]: 37
8572 11:36:44.177933 [Byte1]: 37
8573 11:36:44.182208
8574 11:36:44.182610 Set Vref, RX VrefLevel [Byte0]: 38
8575 11:36:44.185635 [Byte1]: 38
8576 11:36:44.189593
8577 11:36:44.189974 Set Vref, RX VrefLevel [Byte0]: 39
8578 11:36:44.192966 [Byte1]: 39
8579 11:36:44.197489
8580 11:36:44.197866 Set Vref, RX VrefLevel [Byte0]: 40
8581 11:36:44.200561 [Byte1]: 40
8582 11:36:44.204828
8583 11:36:44.205207 Set Vref, RX VrefLevel [Byte0]: 41
8584 11:36:44.208284 [Byte1]: 41
8585 11:36:44.212997
8586 11:36:44.213452 Set Vref, RX VrefLevel [Byte0]: 42
8587 11:36:44.216109 [Byte1]: 42
8588 11:36:44.220313
8589 11:36:44.220770 Set Vref, RX VrefLevel [Byte0]: 43
8590 11:36:44.223476 [Byte1]: 43
8591 11:36:44.228041
8592 11:36:44.228539 Set Vref, RX VrefLevel [Byte0]: 44
8593 11:36:44.231323 [Byte1]: 44
8594 11:36:44.235457
8595 11:36:44.235999 Set Vref, RX VrefLevel [Byte0]: 45
8596 11:36:44.238497 [Byte1]: 45
8597 11:36:44.243104
8598 11:36:44.243596 Set Vref, RX VrefLevel [Byte0]: 46
8599 11:36:44.245825 [Byte1]: 46
8600 11:36:44.250493
8601 11:36:44.250986 Set Vref, RX VrefLevel [Byte0]: 47
8602 11:36:44.253282 [Byte1]: 47
8603 11:36:44.258270
8604 11:36:44.258755 Set Vref, RX VrefLevel [Byte0]: 48
8605 11:36:44.261253 [Byte1]: 48
8606 11:36:44.265837
8607 11:36:44.266309 Set Vref, RX VrefLevel [Byte0]: 49
8608 11:36:44.268413 [Byte1]: 49
8609 11:36:44.273082
8610 11:36:44.273501 Set Vref, RX VrefLevel [Byte0]: 50
8611 11:36:44.276369 [Byte1]: 50
8612 11:36:44.280321
8613 11:36:44.280825 Set Vref, RX VrefLevel [Byte0]: 51
8614 11:36:44.283806 [Byte1]: 51
8615 11:36:44.287867
8616 11:36:44.288301 Set Vref, RX VrefLevel [Byte0]: 52
8617 11:36:44.291537 [Byte1]: 52
8618 11:36:44.295849
8619 11:36:44.296354 Set Vref, RX VrefLevel [Byte0]: 53
8620 11:36:44.298681 [Byte1]: 53
8621 11:36:44.302988
8622 11:36:44.303405 Set Vref, RX VrefLevel [Byte0]: 54
8623 11:36:44.306697 [Byte1]: 54
8624 11:36:44.310754
8625 11:36:44.311249 Set Vref, RX VrefLevel [Byte0]: 55
8626 11:36:44.314176 [Byte1]: 55
8627 11:36:44.318112
8628 11:36:44.318606 Set Vref, RX VrefLevel [Byte0]: 56
8629 11:36:44.321420 [Byte1]: 56
8630 11:36:44.325566
8631 11:36:44.326112 Set Vref, RX VrefLevel [Byte0]: 57
8632 11:36:44.329119 [Byte1]: 57
8633 11:36:44.333282
8634 11:36:44.333777 Set Vref, RX VrefLevel [Byte0]: 58
8635 11:36:44.337262 [Byte1]: 58
8636 11:36:44.341220
8637 11:36:44.341715 Set Vref, RX VrefLevel [Byte0]: 59
8638 11:36:44.344257 [Byte1]: 59
8639 11:36:44.348540
8640 11:36:44.349099 Set Vref, RX VrefLevel [Byte0]: 60
8641 11:36:44.351824 [Byte1]: 60
8642 11:36:44.356545
8643 11:36:44.357140 Set Vref, RX VrefLevel [Byte0]: 61
8644 11:36:44.358740 [Byte1]: 61
8645 11:36:44.363046
8646 11:36:44.363689 Set Vref, RX VrefLevel [Byte0]: 62
8647 11:36:44.366563 [Byte1]: 62
8648 11:36:44.370514
8649 11:36:44.370947 Set Vref, RX VrefLevel [Byte0]: 63
8650 11:36:44.373904 [Byte1]: 63
8651 11:36:44.378132
8652 11:36:44.378630 Set Vref, RX VrefLevel [Byte0]: 64
8653 11:36:44.381881 [Byte1]: 64
8654 11:36:44.385785
8655 11:36:44.386261 Set Vref, RX VrefLevel [Byte0]: 65
8656 11:36:44.389479 [Byte1]: 65
8657 11:36:44.393548
8658 11:36:44.394082 Set Vref, RX VrefLevel [Byte0]: 66
8659 11:36:44.397027 [Byte1]: 66
8660 11:36:44.401026
8661 11:36:44.401544 Set Vref, RX VrefLevel [Byte0]: 67
8662 11:36:44.404390 [Byte1]: 67
8663 11:36:44.408472
8664 11:36:44.408981 Set Vref, RX VrefLevel [Byte0]: 68
8665 11:36:44.412133 [Byte1]: 68
8666 11:36:44.416335
8667 11:36:44.416830 Set Vref, RX VrefLevel [Byte0]: 69
8668 11:36:44.419613 [Byte1]: 69
8669 11:36:44.423587
8670 11:36:44.424082 Set Vref, RX VrefLevel [Byte0]: 70
8671 11:36:44.427029 [Byte1]: 70
8672 11:36:44.431271
8673 11:36:44.431767 Set Vref, RX VrefLevel [Byte0]: 71
8674 11:36:44.434403 [Byte1]: 71
8675 11:36:44.438785
8676 11:36:44.439300 Set Vref, RX VrefLevel [Byte0]: 72
8677 11:36:44.441922 [Byte1]: 72
8678 11:36:44.446441
8679 11:36:44.446861 Set Vref, RX VrefLevel [Byte0]: 73
8680 11:36:44.449722 [Byte1]: 73
8681 11:36:44.453520
8682 11:36:44.453936 Set Vref, RX VrefLevel [Byte0]: 74
8683 11:36:44.456904 [Byte1]: 74
8684 11:36:44.461470
8685 11:36:44.462176 Set Vref, RX VrefLevel [Byte0]: 75
8686 11:36:44.464338 [Byte1]: 75
8687 11:36:44.468901
8688 11:36:44.469394 Set Vref, RX VrefLevel [Byte0]: 76
8689 11:36:44.472022 [Byte1]: 76
8690 11:36:44.476550
8691 11:36:44.477048 Set Vref, RX VrefLevel [Byte0]: 77
8692 11:36:44.479631 [Byte1]: 77
8693 11:36:44.484137
8694 11:36:44.484657 Set Vref, RX VrefLevel [Byte0]: 78
8695 11:36:44.487474 [Byte1]: 78
8696 11:36:44.491519
8697 11:36:44.491939 Final RX Vref Byte 0 = 56 to rank0
8698 11:36:44.494789 Final RX Vref Byte 1 = 54 to rank0
8699 11:36:44.498218 Final RX Vref Byte 0 = 56 to rank1
8700 11:36:44.501239 Final RX Vref Byte 1 = 54 to rank1==
8701 11:36:44.504532 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 11:36:44.510997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 11:36:44.511507 ==
8704 11:36:44.511843 DQS Delay:
8705 11:36:44.512149 DQS0 = 0, DQS1 = 0
8706 11:36:44.514653 DQM Delay:
8707 11:36:44.515167 DQM0 = 134, DQM1 = 130
8708 11:36:44.518054 DQ Delay:
8709 11:36:44.521603 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8710 11:36:44.524517 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8711 11:36:44.527721 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8712 11:36:44.531047 DQ12 =138, DQ13 =136, DQ14 =140, DQ15 =140
8713 11:36:44.531425
8714 11:36:44.531721
8715 11:36:44.531991
8716 11:36:44.534329 [DramC_TX_OE_Calibration] TA2
8717 11:36:44.538039 Original DQ_B0 (3 6) =30, OEN = 27
8718 11:36:44.540894 Original DQ_B1 (3 6) =30, OEN = 27
8719 11:36:44.544511 24, 0x0, End_B0=24 End_B1=24
8720 11:36:44.544897 25, 0x0, End_B0=25 End_B1=25
8721 11:36:44.547573 26, 0x0, End_B0=26 End_B1=26
8722 11:36:44.550740 27, 0x0, End_B0=27 End_B1=27
8723 11:36:44.554260 28, 0x0, End_B0=28 End_B1=28
8724 11:36:44.557686 29, 0x0, End_B0=29 End_B1=29
8725 11:36:44.558210 30, 0x0, End_B0=30 End_B1=30
8726 11:36:44.560972 31, 0x4141, End_B0=30 End_B1=30
8727 11:36:44.563997 Byte0 end_step=30 best_step=27
8728 11:36:44.567311 Byte1 end_step=30 best_step=27
8729 11:36:44.570833 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 11:36:44.574105 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 11:36:44.574658
8732 11:36:44.574976
8733 11:36:44.581062 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8734 11:36:44.584103 CH1 RK0: MR19=303, MR18=1725
8735 11:36:44.591167 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8736 11:36:44.591628
8737 11:36:44.594708 ----->DramcWriteLeveling(PI) begin...
8738 11:36:44.595185 ==
8739 11:36:44.597849 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 11:36:44.600656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 11:36:44.601040 ==
8742 11:36:44.604033 Write leveling (Byte 0): 25 => 25
8743 11:36:44.607500 Write leveling (Byte 1): 28 => 28
8744 11:36:44.610790 DramcWriteLeveling(PI) end<-----
8745 11:36:44.611251
8746 11:36:44.611586 ==
8747 11:36:44.614135 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 11:36:44.617301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 11:36:44.617738 ==
8750 11:36:44.620886 [Gating] SW mode calibration
8751 11:36:44.627280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 11:36:44.633844 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 11:36:44.637554 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:36:44.640857 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 11:36:44.647017 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8756 11:36:44.650313 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8757 11:36:44.654163 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:36:44.660848 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 11:36:44.663790 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 11:36:44.667325 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 11:36:44.674125 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 11:36:44.677488 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8763 11:36:44.680565 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
8764 11:36:44.687199 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
8765 11:36:44.690614 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:36:44.693785 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:36:44.701160 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:36:44.703815 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:36:44.707100 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 11:36:44.714402 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8771 11:36:44.716760 1 6 8 | B1->B0 | 3f3f 2828 | 0 0 | (0 0) (0 0)
8772 11:36:44.720340 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8773 11:36:44.727021 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:36:44.730740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:36:44.733905 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:36:44.740218 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 11:36:44.743487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 11:36:44.747316 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 11:36:44.750111 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8780 11:36:44.757444 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8781 11:36:44.760834 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:36:44.763727 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:36:44.770382 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:36:44.773780 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:36:44.777088 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:36:44.783370 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:36:44.787359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:36:44.790230 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:36:44.797403 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:36:44.800198 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:36:44.803427 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:36:44.810250 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:36:44.814402 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:36:44.816855 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8795 11:36:44.823905 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8796 11:36:44.826956 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8797 11:36:44.830676 Total UI for P1: 0, mck2ui 16
8798 11:36:44.833481 best dqsien dly found for B1: ( 1, 9, 6)
8799 11:36:44.837121 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8800 11:36:44.843510 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 11:36:44.843991 Total UI for P1: 0, mck2ui 16
8802 11:36:44.849951 best dqsien dly found for B0: ( 1, 9, 14)
8803 11:36:44.853526 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8804 11:36:44.856260 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8805 11:36:44.856834
8806 11:36:44.859726 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8807 11:36:44.863099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8808 11:36:44.866356 [Gating] SW calibration Done
8809 11:36:44.866737 ==
8810 11:36:44.869630 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 11:36:44.872816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 11:36:44.873484 ==
8813 11:36:44.876507 RX Vref Scan: 0
8814 11:36:44.876932
8815 11:36:44.877248 RX Vref 0 -> 0, step: 1
8816 11:36:44.877825
8817 11:36:44.879440 RX Delay 0 -> 252, step: 8
8818 11:36:44.883283 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8819 11:36:44.890296 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8820 11:36:44.893357 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8821 11:36:44.896571 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8822 11:36:44.899893 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8823 11:36:44.903299 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8824 11:36:44.906191 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8825 11:36:44.913470 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8826 11:36:44.916859 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8827 11:36:44.919682 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8828 11:36:44.923104 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8829 11:36:44.926513 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8830 11:36:44.933178 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8831 11:36:44.936234 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8832 11:36:44.939631 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8833 11:36:44.943481 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8834 11:36:44.943987 ==
8835 11:36:44.946602 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 11:36:44.953114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 11:36:44.953622 ==
8838 11:36:44.953971 DQS Delay:
8839 11:36:44.956480 DQS0 = 0, DQS1 = 0
8840 11:36:44.956985 DQM Delay:
8841 11:36:44.959618 DQM0 = 136, DQM1 = 133
8842 11:36:44.960113 DQ Delay:
8843 11:36:44.963389 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8844 11:36:44.966760 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8845 11:36:44.970179 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8846 11:36:44.973481 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8847 11:36:44.974060
8848 11:36:44.974530
8849 11:36:44.974904 ==
8850 11:36:44.976397 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 11:36:44.983066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 11:36:44.983550 ==
8853 11:36:44.983902
8854 11:36:44.984206
8855 11:36:44.984496 TX Vref Scan disable
8856 11:36:44.986115 == TX Byte 0 ==
8857 11:36:44.989810 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 11:36:44.993259 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8859 11:36:44.995970 == TX Byte 1 ==
8860 11:36:44.999884 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8861 11:36:45.006124 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8862 11:36:45.006626 ==
8863 11:36:45.009551 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 11:36:45.012814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 11:36:45.013248 ==
8866 11:36:45.026330
8867 11:36:45.029715 TX Vref early break, caculate TX vref
8868 11:36:45.032802 TX Vref=16, minBit 0, minWin=23, winSum=381
8869 11:36:45.035728 TX Vref=18, minBit 0, minWin=24, winSum=394
8870 11:36:45.039066 TX Vref=20, minBit 0, minWin=24, winSum=404
8871 11:36:45.042715 TX Vref=22, minBit 9, minWin=24, winSum=409
8872 11:36:45.046379 TX Vref=24, minBit 0, minWin=25, winSum=421
8873 11:36:45.053197 TX Vref=26, minBit 0, minWin=25, winSum=426
8874 11:36:45.056221 TX Vref=28, minBit 0, minWin=26, winSum=428
8875 11:36:45.059435 TX Vref=30, minBit 0, minWin=25, winSum=422
8876 11:36:45.062706 TX Vref=32, minBit 0, minWin=25, winSum=414
8877 11:36:45.065740 TX Vref=34, minBit 0, minWin=24, winSum=406
8878 11:36:45.069051 TX Vref=36, minBit 0, minWin=23, winSum=395
8879 11:36:45.076075 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8880 11:36:45.076628
8881 11:36:45.078977 Final TX Range 0 Vref 28
8882 11:36:45.079399
8883 11:36:45.079725 ==
8884 11:36:45.082726 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 11:36:45.086099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 11:36:45.086605 ==
8887 11:36:45.086939
8888 11:36:45.087245
8889 11:36:45.089500 TX Vref Scan disable
8890 11:36:45.095926 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8891 11:36:45.096488 == TX Byte 0 ==
8892 11:36:45.099219 u2DelayCellOfst[0]=17 cells (5 PI)
8893 11:36:45.102611 u2DelayCellOfst[1]=10 cells (3 PI)
8894 11:36:45.106478 u2DelayCellOfst[2]=0 cells (0 PI)
8895 11:36:45.109259 u2DelayCellOfst[3]=6 cells (2 PI)
8896 11:36:45.112346 u2DelayCellOfst[4]=10 cells (3 PI)
8897 11:36:45.116513 u2DelayCellOfst[5]=17 cells (5 PI)
8898 11:36:45.119294 u2DelayCellOfst[6]=17 cells (5 PI)
8899 11:36:45.122984 u2DelayCellOfst[7]=3 cells (1 PI)
8900 11:36:45.126360 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8901 11:36:45.129783 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 11:36:45.132837 == TX Byte 1 ==
8903 11:36:45.135601 u2DelayCellOfst[8]=0 cells (0 PI)
8904 11:36:45.136028 u2DelayCellOfst[9]=6 cells (2 PI)
8905 11:36:45.139483 u2DelayCellOfst[10]=13 cells (4 PI)
8906 11:36:45.142557 u2DelayCellOfst[11]=10 cells (3 PI)
8907 11:36:45.145620 u2DelayCellOfst[12]=17 cells (5 PI)
8908 11:36:45.149075 u2DelayCellOfst[13]=17 cells (5 PI)
8909 11:36:45.152554 u2DelayCellOfst[14]=20 cells (6 PI)
8910 11:36:45.156167 u2DelayCellOfst[15]=20 cells (6 PI)
8911 11:36:45.158616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8912 11:36:45.165370 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 11:36:45.165822 DramC Write-DBI on
8914 11:36:45.166214 ==
8915 11:36:45.169163 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 11:36:45.175857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 11:36:45.176353 ==
8918 11:36:45.176686
8919 11:36:45.176989
8920 11:36:45.177496 TX Vref Scan disable
8921 11:36:45.179040 == TX Byte 0 ==
8922 11:36:45.182868 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8923 11:36:45.186378 == TX Byte 1 ==
8924 11:36:45.189748 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8925 11:36:45.190310 DramC Write-DBI off
8926 11:36:45.192919
8927 11:36:45.193337 [DATLAT]
8928 11:36:45.193662 Freq=1600, CH1 RK1
8929 11:36:45.193965
8930 11:36:45.196083 DATLAT Default: 0xf
8931 11:36:45.196501 0, 0xFFFF, sum = 0
8932 11:36:45.199677 1, 0xFFFF, sum = 0
8933 11:36:45.200184 2, 0xFFFF, sum = 0
8934 11:36:45.202939 3, 0xFFFF, sum = 0
8935 11:36:45.206416 4, 0xFFFF, sum = 0
8936 11:36:45.206927 5, 0xFFFF, sum = 0
8937 11:36:45.209489 6, 0xFFFF, sum = 0
8938 11:36:45.209995 7, 0xFFFF, sum = 0
8939 11:36:45.212674 8, 0xFFFF, sum = 0
8940 11:36:45.213100 9, 0xFFFF, sum = 0
8941 11:36:45.216092 10, 0xFFFF, sum = 0
8942 11:36:45.216602 11, 0xFFFF, sum = 0
8943 11:36:45.219431 12, 0xFFFF, sum = 0
8944 11:36:45.219942 13, 0xFFFF, sum = 0
8945 11:36:45.222838 14, 0x0, sum = 1
8946 11:36:45.223352 15, 0x0, sum = 2
8947 11:36:45.226385 16, 0x0, sum = 3
8948 11:36:45.226897 17, 0x0, sum = 4
8949 11:36:45.229311 best_step = 15
8950 11:36:45.229814
8951 11:36:45.230208 ==
8952 11:36:45.232488 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 11:36:45.235954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 11:36:45.236460 ==
8955 11:36:45.236838 RX Vref Scan: 0
8956 11:36:45.238908
8957 11:36:45.239345 RX Vref 0 -> 0, step: 1
8958 11:36:45.239676
8959 11:36:45.242660 RX Delay 19 -> 252, step: 4
8960 11:36:45.246081 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8961 11:36:45.252229 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8962 11:36:45.255948 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8963 11:36:45.259364 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8964 11:36:45.262349 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8965 11:36:45.265743 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8966 11:36:45.269387 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8967 11:36:45.275663 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8968 11:36:45.278919 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8969 11:36:45.282670 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8970 11:36:45.285742 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8971 11:36:45.289327 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8972 11:36:45.296257 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8973 11:36:45.299461 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8974 11:36:45.302859 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8975 11:36:45.305689 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8976 11:36:45.306149 ==
8977 11:36:45.309628 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 11:36:45.316232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 11:36:45.316736 ==
8980 11:36:45.317070 DQS Delay:
8981 11:36:45.318711 DQS0 = 0, DQS1 = 0
8982 11:36:45.319131 DQM Delay:
8983 11:36:45.319461 DQM0 = 134, DQM1 = 131
8984 11:36:45.322915 DQ Delay:
8985 11:36:45.325574 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8986 11:36:45.328620 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8987 11:36:45.332251 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =126
8988 11:36:45.335507 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8989 11:36:45.335977
8990 11:36:45.336399
8991 11:36:45.336841
8992 11:36:45.338580 [DramC_TX_OE_Calibration] TA2
8993 11:36:45.341915 Original DQ_B0 (3 6) =30, OEN = 27
8994 11:36:45.345368 Original DQ_B1 (3 6) =30, OEN = 27
8995 11:36:45.348719 24, 0x0, End_B0=24 End_B1=24
8996 11:36:45.351730 25, 0x0, End_B0=25 End_B1=25
8997 11:36:45.352124 26, 0x0, End_B0=26 End_B1=26
8998 11:36:45.355234 27, 0x0, End_B0=27 End_B1=27
8999 11:36:45.358943 28, 0x0, End_B0=28 End_B1=28
9000 11:36:45.361834 29, 0x0, End_B0=29 End_B1=29
9001 11:36:45.362255 30, 0x0, End_B0=30 End_B1=30
9002 11:36:45.365418 31, 0x4141, End_B0=30 End_B1=30
9003 11:36:45.368992 Byte0 end_step=30 best_step=27
9004 11:36:45.371628 Byte1 end_step=30 best_step=27
9005 11:36:45.375400 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 11:36:45.378388 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 11:36:45.378866
9008 11:36:45.379170
9009 11:36:45.385168 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9010 11:36:45.388459 CH1 RK1: MR19=303, MR18=2308
9011 11:36:45.394894 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9012 11:36:45.398091 [RxdqsGatingPostProcess] freq 1600
9013 11:36:45.401745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 11:36:45.405453 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 11:36:45.408553 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 11:36:45.411922 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 11:36:45.414766 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 11:36:45.418204 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 11:36:45.422149 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 11:36:45.425459 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 11:36:45.428486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 11:36:45.432213 Pre-setting of DQS Precalculation
9023 11:36:45.434919 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 11:36:45.441328 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 11:36:45.451876 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 11:36:45.452383
9027 11:36:45.452713
9028 11:36:45.455209 [Calibration Summary] 3200 Mbps
9029 11:36:45.455709 CH 0, Rank 0
9030 11:36:45.458744 SW Impedance : PASS
9031 11:36:45.459244 DUTY Scan : NO K
9032 11:36:45.461596 ZQ Calibration : PASS
9033 11:36:45.462128 Jitter Meter : NO K
9034 11:36:45.465402 CBT Training : PASS
9035 11:36:45.468076 Write leveling : PASS
9036 11:36:45.468499 RX DQS gating : PASS
9037 11:36:45.471802 RX DQ/DQS(RDDQC) : PASS
9038 11:36:45.474949 TX DQ/DQS : PASS
9039 11:36:45.475333 RX DATLAT : PASS
9040 11:36:45.478399 RX DQ/DQS(Engine): PASS
9041 11:36:45.481506 TX OE : PASS
9042 11:36:45.481888 All Pass.
9043 11:36:45.482238
9044 11:36:45.482518 CH 0, Rank 1
9045 11:36:45.484962 SW Impedance : PASS
9046 11:36:45.488264 DUTY Scan : NO K
9047 11:36:45.488728 ZQ Calibration : PASS
9048 11:36:45.491270 Jitter Meter : NO K
9049 11:36:45.494582 CBT Training : PASS
9050 11:36:45.494962 Write leveling : PASS
9051 11:36:45.497993 RX DQS gating : PASS
9052 11:36:45.502098 RX DQ/DQS(RDDQC) : PASS
9053 11:36:45.502486 TX DQ/DQS : PASS
9054 11:36:45.505245 RX DATLAT : PASS
9055 11:36:45.505632 RX DQ/DQS(Engine): PASS
9056 11:36:45.508532 TX OE : PASS
9057 11:36:45.509003 All Pass.
9058 11:36:45.509310
9059 11:36:45.511780 CH 1, Rank 0
9060 11:36:45.512162 SW Impedance : PASS
9061 11:36:45.514679 DUTY Scan : NO K
9062 11:36:45.518265 ZQ Calibration : PASS
9063 11:36:45.518731 Jitter Meter : NO K
9064 11:36:45.521396 CBT Training : PASS
9065 11:36:45.525257 Write leveling : PASS
9066 11:36:45.525723 RX DQS gating : PASS
9067 11:36:45.528464 RX DQ/DQS(RDDQC) : PASS
9068 11:36:45.531976 TX DQ/DQS : PASS
9069 11:36:45.532478 RX DATLAT : PASS
9070 11:36:45.534657 RX DQ/DQS(Engine): PASS
9071 11:36:45.537924 TX OE : PASS
9072 11:36:45.538465 All Pass.
9073 11:36:45.538788
9074 11:36:45.539073 CH 1, Rank 1
9075 11:36:45.541568 SW Impedance : PASS
9076 11:36:45.545066 DUTY Scan : NO K
9077 11:36:45.545532 ZQ Calibration : PASS
9078 11:36:45.547785 Jitter Meter : NO K
9079 11:36:45.551450 CBT Training : PASS
9080 11:36:45.551616 Write leveling : PASS
9081 11:36:45.555272 RX DQS gating : PASS
9082 11:36:45.555504 RX DQ/DQS(RDDQC) : PASS
9083 11:36:45.557941 TX DQ/DQS : PASS
9084 11:36:45.561655 RX DATLAT : PASS
9085 11:36:45.561890 RX DQ/DQS(Engine): PASS
9086 11:36:45.564976 TX OE : PASS
9087 11:36:45.565253 All Pass.
9088 11:36:45.565477
9089 11:36:45.567873 DramC Write-DBI on
9090 11:36:45.571593 PER_BANK_REFRESH: Hybrid Mode
9091 11:36:45.571917 TX_TRACKING: ON
9092 11:36:45.581143 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 11:36:45.588165 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 11:36:45.594765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 11:36:45.601871 [FAST_K] Save calibration result to emmc
9096 11:36:45.602407 sync common calibartion params.
9097 11:36:45.605126 sync cbt_mode0:1, 1:1
9098 11:36:45.608180 dram_init: ddr_geometry: 2
9099 11:36:45.608611 dram_init: ddr_geometry: 2
9100 11:36:45.611172 dram_init: ddr_geometry: 2
9101 11:36:45.614484 0:dram_rank_size:100000000
9102 11:36:45.617643 1:dram_rank_size:100000000
9103 11:36:45.621682 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 11:36:45.624385 DFS_SHUFFLE_HW_MODE: ON
9105 11:36:45.627835 dramc_set_vcore_voltage set vcore to 725000
9106 11:36:45.630985 Read voltage for 1600, 0
9107 11:36:45.631413 Vio18 = 0
9108 11:36:45.634530 Vcore = 725000
9109 11:36:45.635038 Vdram = 0
9110 11:36:45.635375 Vddq = 0
9111 11:36:45.635679 Vmddr = 0
9112 11:36:45.637739 switch to 3200 Mbps bootup
9113 11:36:45.641298 [DramcRunTimeConfig]
9114 11:36:45.641727 PHYPLL
9115 11:36:45.642126 DPM_CONTROL_AFTERK: ON
9116 11:36:45.644201 PER_BANK_REFRESH: ON
9117 11:36:45.647795 REFRESH_OVERHEAD_REDUCTION: ON
9118 11:36:45.648403 CMD_PICG_NEW_MODE: OFF
9119 11:36:45.651083 XRTWTW_NEW_MODE: ON
9120 11:36:45.654342 XRTRTR_NEW_MODE: ON
9121 11:36:45.654731 TX_TRACKING: ON
9122 11:36:45.657632 RDSEL_TRACKING: OFF
9123 11:36:45.658046 DQS Precalculation for DVFS: ON
9124 11:36:45.661442 RX_TRACKING: OFF
9125 11:36:45.661906 HW_GATING DBG: ON
9126 11:36:45.664142 ZQCS_ENABLE_LP4: ON
9127 11:36:45.664630 RX_PICG_NEW_MODE: ON
9128 11:36:45.667678 TX_PICG_NEW_MODE: ON
9129 11:36:45.670814 ENABLE_RX_DCM_DPHY: ON
9130 11:36:45.674159 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 11:36:45.674585 DUMMY_READ_FOR_TRACKING: OFF
9132 11:36:45.677589 !!! SPM_CONTROL_AFTERK: OFF
9133 11:36:45.681236 !!! SPM could not control APHY
9134 11:36:45.684721 IMPEDANCE_TRACKING: ON
9135 11:36:45.685183 TEMP_SENSOR: ON
9136 11:36:45.687663 HW_SAVE_FOR_SR: OFF
9137 11:36:45.688052 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 11:36:45.694664 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 11:36:45.695134 Read ODT Tracking: ON
9140 11:36:45.697785 Refresh Rate DeBounce: ON
9141 11:36:45.698280 DFS_NO_QUEUE_FLUSH: ON
9142 11:36:45.701771 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 11:36:45.705043 ENABLE_DFS_RUNTIME_MRW: OFF
9144 11:36:45.707638 DDR_RESERVE_NEW_MODE: ON
9145 11:36:45.708061 MR_CBT_SWITCH_FREQ: ON
9146 11:36:45.711401 =========================
9147 11:36:45.730645 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 11:36:45.733939 dram_init: ddr_geometry: 2
9149 11:36:45.752073 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 11:36:45.755282 dram_init: dram init end (result: 0)
9151 11:36:45.761975 DRAM-K: Full calibration passed in 24492 msecs
9152 11:36:45.765166 MRC: failed to locate region type 0.
9153 11:36:45.765619 DRAM rank0 size:0x100000000,
9154 11:36:45.768796 DRAM rank1 size=0x100000000
9155 11:36:45.779075 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 11:36:45.785097 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 11:36:45.791616 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 11:36:45.798043 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 11:36:45.802222 DRAM rank0 size:0x100000000,
9160 11:36:45.805085 DRAM rank1 size=0x100000000
9161 11:36:45.805507 CBMEM:
9162 11:36:45.808515 IMD: root @ 0xfffff000 254 entries.
9163 11:36:45.811874 IMD: root @ 0xffffec00 62 entries.
9164 11:36:45.814807 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 11:36:45.818912 WARNING: RO_VPD is uninitialized or empty.
9166 11:36:45.825020 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 11:36:45.832453 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 11:36:45.844831 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9169 11:36:45.856467 BS: romstage times (exec / console): total (unknown) / 24018 ms
9170 11:36:45.856969
9171 11:36:45.857299
9172 11:36:45.866385 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 11:36:45.869953 ARM64: Exception handlers installed.
9174 11:36:45.872745 ARM64: Testing exception
9175 11:36:45.876147 ARM64: Done test exception
9176 11:36:45.876667 Enumerating buses...
9177 11:36:45.879439 Show all devs... Before device enumeration.
9178 11:36:45.882537 Root Device: enabled 1
9179 11:36:45.885654 CPU_CLUSTER: 0: enabled 1
9180 11:36:45.886074 CPU: 00: enabled 1
9181 11:36:45.888983 Compare with tree...
9182 11:36:45.889369 Root Device: enabled 1
9183 11:36:45.892507 CPU_CLUSTER: 0: enabled 1
9184 11:36:45.895624 CPU: 00: enabled 1
9185 11:36:45.896113 Root Device scanning...
9186 11:36:45.898996 scan_static_bus for Root Device
9187 11:36:45.902626 CPU_CLUSTER: 0 enabled
9188 11:36:45.905779 scan_static_bus for Root Device done
9189 11:36:45.909095 scan_bus: bus Root Device finished in 8 msecs
9190 11:36:45.909506 done
9191 11:36:45.915718 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 11:36:45.918947 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 11:36:45.925519 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 11:36:45.928873 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 11:36:45.932360 Allocating resources...
9196 11:36:45.935538 Reading resources...
9197 11:36:45.938861 Root Device read_resources bus 0 link: 0
9198 11:36:45.939287 DRAM rank0 size:0x100000000,
9199 11:36:45.941988 DRAM rank1 size=0x100000000
9200 11:36:45.945952 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 11:36:45.948578 CPU: 00 missing read_resources
9202 11:36:45.952365 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 11:36:45.959530 Root Device read_resources bus 0 link: 0 done
9204 11:36:45.959998 Done reading resources.
9205 11:36:45.965538 Show resources in subtree (Root Device)...After reading.
9206 11:36:45.969449 Root Device child on link 0 CPU_CLUSTER: 0
9207 11:36:45.972471 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 11:36:45.982889 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 11:36:45.983363 CPU: 00
9210 11:36:45.986406 Root Device assign_resources, bus 0 link: 0
9211 11:36:45.989667 CPU_CLUSTER: 0 missing set_resources
9212 11:36:45.995733 Root Device assign_resources, bus 0 link: 0 done
9213 11:36:45.996240 Done setting resources.
9214 11:36:46.002716 Show resources in subtree (Root Device)...After assigning values.
9215 11:36:46.005685 Root Device child on link 0 CPU_CLUSTER: 0
9216 11:36:46.008713 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 11:36:46.018991 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 11:36:46.019495 CPU: 00
9219 11:36:46.022284 Done allocating resources.
9220 11:36:46.025745 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 11:36:46.029595 Enabling resources...
9222 11:36:46.030161 done.
9223 11:36:46.035753 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 11:36:46.036266 Initializing devices...
9225 11:36:46.038992 Root Device init
9226 11:36:46.039485 init hardware done!
9227 11:36:46.042040 0x00000018: ctrlr->caps
9228 11:36:46.045127 52.000 MHz: ctrlr->f_max
9229 11:36:46.045580 0.400 MHz: ctrlr->f_min
9230 11:36:46.048393 0x40ff8080: ctrlr->voltages
9231 11:36:46.048830 sclk: 390625
9232 11:36:46.052162 Bus Width = 1
9233 11:36:46.052579 sclk: 390625
9234 11:36:46.055654 Bus Width = 1
9235 11:36:46.056114 Early init status = 3
9236 11:36:46.061986 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 11:36:46.065539 in-header: 03 fc 00 00 01 00 00 00
9238 11:36:46.066051 in-data: 00
9239 11:36:46.072390 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 11:36:46.074716 in-header: 03 fd 00 00 00 00 00 00
9241 11:36:46.078659 in-data:
9242 11:36:46.082357 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 11:36:46.085327 in-header: 03 fc 00 00 01 00 00 00
9244 11:36:46.088620 in-data: 00
9245 11:36:46.092214 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 11:36:46.097420 in-header: 03 fd 00 00 00 00 00 00
9247 11:36:46.100713 in-data:
9248 11:36:46.103474 [SSUSB] Setting up USB HOST controller...
9249 11:36:46.106797 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 11:36:46.110714 [SSUSB] phy power-on done.
9251 11:36:46.114176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 11:36:46.120360 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 11:36:46.123735 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 11:36:46.130071 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 11:36:46.136934 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9256 11:36:46.143205 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 11:36:46.150177 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 11:36:46.156811 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9259 11:36:46.159856 SPM: binary array size = 0x9dc
9260 11:36:46.163081 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 11:36:46.169701 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 11:36:46.176426 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 11:36:46.179837 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 11:36:46.186552 configure_display: Starting display init
9265 11:36:46.221012 anx7625_power_on_init: Init interface.
9266 11:36:46.223477 anx7625_disable_pd_protocol: Disabled PD feature.
9267 11:36:46.226975 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 11:36:46.254913 anx7625_start_dp_work: Secure OCM version=00
9269 11:36:46.258199 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 11:36:46.273290 sp_tx_get_edid_block: EDID Block = 1
9271 11:36:46.375473 Extracted contents:
9272 11:36:46.378636 header: 00 ff ff ff ff ff ff 00
9273 11:36:46.382287 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 11:36:46.385941 version: 01 04
9275 11:36:46.388692 basic params: 95 1f 11 78 0a
9276 11:36:46.392024 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 11:36:46.395878 established: 00 00 00
9278 11:36:46.402329 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 11:36:46.405117 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 11:36:46.412506 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 11:36:46.418444 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 11:36:46.425264 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 11:36:46.428633 extensions: 00
9284 11:36:46.429166 checksum: fb
9285 11:36:46.429614
9286 11:36:46.431902 Manufacturer: IVO Model 57d Serial Number 0
9287 11:36:46.435148 Made week 0 of 2020
9288 11:36:46.435544 EDID version: 1.4
9289 11:36:46.438713 Digital display
9290 11:36:46.442220 6 bits per primary color channel
9291 11:36:46.442696 DisplayPort interface
9292 11:36:46.445165 Maximum image size: 31 cm x 17 cm
9293 11:36:46.445558 Gamma: 220%
9294 11:36:46.448727 Check DPMS levels
9295 11:36:46.452008 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 11:36:46.455098 First detailed timing is preferred timing
9297 11:36:46.458605 Established timings supported:
9298 11:36:46.462044 Standard timings supported:
9299 11:36:46.462514 Detailed timings
9300 11:36:46.468493 Hex of detail: 383680a07038204018303c0035ae10000019
9301 11:36:46.471856 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 11:36:46.478362 0780 0798 07c8 0820 hborder 0
9303 11:36:46.481696 0438 043b 0447 0458 vborder 0
9304 11:36:46.482114 -hsync -vsync
9305 11:36:46.484823 Did detailed timing
9306 11:36:46.488675 Hex of detail: 000000000000000000000000000000000000
9307 11:36:46.491871 Manufacturer-specified data, tag 0
9308 11:36:46.498164 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 11:36:46.498545 ASCII string: InfoVision
9310 11:36:46.504710 Hex of detail: 000000fe00523134304e574635205248200a
9311 11:36:46.505090 ASCII string: R140NWF5 RH
9312 11:36:46.508858 Checksum
9313 11:36:46.509314 Checksum: 0xfb (valid)
9314 11:36:46.515237 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 11:36:46.518553 DSI data_rate: 832800000 bps
9316 11:36:46.521785 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 11:36:46.525249 anx7625_parse_edid: pixelclock(138800).
9318 11:36:46.531644 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 11:36:46.535096 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 11:36:46.538588 anx7625_dsi_config: config dsi.
9321 11:36:46.545084 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 11:36:46.557358 anx7625_dsi_config: success to config DSI
9323 11:36:46.560728 anx7625_dp_start: MIPI phy setup OK.
9324 11:36:46.564559 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 11:36:46.567135 mtk_ddp_mode_set invalid vrefresh 60
9326 11:36:46.570770 main_disp_path_setup
9327 11:36:46.571233 ovl_layer_smi_id_en
9328 11:36:46.573794 ovl_layer_smi_id_en
9329 11:36:46.574219 ccorr_config
9330 11:36:46.574519 aal_config
9331 11:36:46.577713 gamma_config
9332 11:36:46.578126 postmask_config
9333 11:36:46.580798 dither_config
9334 11:36:46.584415 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 11:36:46.590953 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 11:36:46.594410 Root Device init finished in 552 msecs
9337 11:36:46.594870 CPU_CLUSTER: 0 init
9338 11:36:46.604305 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 11:36:46.608039 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 11:36:46.611009 APU_MBOX 0x190000b0 = 0x10001
9341 11:36:46.614200 APU_MBOX 0x190001b0 = 0x10001
9342 11:36:46.617662 APU_MBOX 0x190005b0 = 0x10001
9343 11:36:46.620608 APU_MBOX 0x190006b0 = 0x10001
9344 11:36:46.624261 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 11:36:46.636552 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9346 11:36:46.648873 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 11:36:46.655408 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 11:36:46.667190 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9349 11:36:46.675846 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 11:36:46.679437 CPU_CLUSTER: 0 init finished in 81 msecs
9351 11:36:46.682946 Devices initialized
9352 11:36:46.686050 Show all devs... After init.
9353 11:36:46.686446 Root Device: enabled 1
9354 11:36:46.689405 CPU_CLUSTER: 0: enabled 1
9355 11:36:46.692528 CPU: 00: enabled 1
9356 11:36:46.696002 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9357 11:36:46.699200 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 11:36:46.702958 ELOG: NV offset 0x57f000 size 0x1000
9359 11:36:46.709140 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9360 11:36:46.715992 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 11:36:46.719179 ELOG: Event(17) added with size 13 at 2024-07-17 11:36:31 UTC
9362 11:36:46.723429 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 11:36:46.726531 in-header: 03 4b 00 00 2c 00 00 00
9364 11:36:46.739668 in-data: f2 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 11:36:46.746458 ELOG: Event(A1) added with size 10 at 2024-07-17 11:36:31 UTC
9366 11:36:46.753061 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9367 11:36:46.759492 ELOG: Event(A0) added with size 9 at 2024-07-17 11:36:31 UTC
9368 11:36:46.762442 elog_add_boot_reason: Logged dev mode boot
9369 11:36:46.765864 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 11:36:46.769311 Finalize devices...
9371 11:36:46.769755 Devices finalized
9372 11:36:46.775784 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 11:36:46.780112 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9374 11:36:46.782550 in-header: 03 07 00 00 08 00 00 00
9375 11:36:46.785760 in-data: aa e4 47 04 13 02 00 00
9376 11:36:46.788985 Chrome EC: UHEPI supported
9377 11:36:46.795814 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9378 11:36:46.799688 in-header: 03 a9 00 00 08 00 00 00
9379 11:36:46.802306 in-data: 84 60 60 08 00 00 00 00
9380 11:36:46.805441 ELOG: Event(91) added with size 10 at 2024-07-17 11:36:31 UTC
9381 11:36:46.812648 Chrome EC: clear events_b mask to 0x0000000020004000
9382 11:36:46.819248 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9383 11:36:46.822761 in-header: 03 fd 00 00 00 00 00 00
9384 11:36:46.822867 in-data:
9385 11:36:46.829935 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9386 11:36:46.833185 Writing coreboot table at 0xffe64000
9387 11:36:46.836326 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 11:36:46.840038 1. 0000000040000000-00000000400fffff: RAM
9389 11:36:46.842948 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 11:36:46.846806 3. 000000004032b000-00000000545fffff: RAM
9391 11:36:46.853784 4. 0000000054600000-000000005465ffff: BL31
9392 11:36:46.856782 5. 0000000054660000-00000000ffe63fff: RAM
9393 11:36:46.859780 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 11:36:46.863100 7. 0000000100000000-000000023fffffff: RAM
9395 11:36:46.867157 Passing 5 GPIOs to payload:
9396 11:36:46.873416 NAME | PORT | POLARITY | VALUE
9397 11:36:46.876549 EC in RW | 0x000000aa | low | undefined
9398 11:36:46.879975 EC interrupt | 0x00000005 | low | undefined
9399 11:36:46.886382 TPM interrupt | 0x000000ab | high | undefined
9400 11:36:46.889642 SD card detect | 0x00000011 | high | undefined
9401 11:36:46.896661 speaker enable | 0x00000093 | high | undefined
9402 11:36:46.899612 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 11:36:46.903526 in-header: 03 f9 00 00 02 00 00 00
9404 11:36:46.903987 in-data: 02 00
9405 11:36:46.906501 ADC[4]: Raw value=904726 ID=7
9406 11:36:46.910173 ADC[3]: Raw value=213441 ID=1
9407 11:36:46.910633 RAM Code: 0x71
9408 11:36:46.913574 ADC[6]: Raw value=75701 ID=0
9409 11:36:46.916698 ADC[5]: Raw value=212703 ID=1
9410 11:36:46.917202 SKU Code: 0x1
9411 11:36:46.923435 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9e3a
9412 11:36:46.926749 coreboot table: 964 bytes.
9413 11:36:46.930125 IMD ROOT 0. 0xfffff000 0x00001000
9414 11:36:46.933004 IMD SMALL 1. 0xffffe000 0x00001000
9415 11:36:46.933432 RO MCACHE 2. 0xffffc000 0x00001104
9416 11:36:46.936732 CONSOLE 3. 0xfff7c000 0x00080000
9417 11:36:46.939574 FMAP 4. 0xfff7b000 0x00000452
9418 11:36:46.943224 TIME STAMP 5. 0xfff7a000 0x00000910
9419 11:36:46.946383 VBOOT WORK 6. 0xfff66000 0x00014000
9420 11:36:46.949656 RAMOOPS 7. 0xffe66000 0x00100000
9421 11:36:46.953010 COREBOOT 8. 0xffe64000 0x00002000
9422 11:36:46.956436 IMD small region:
9423 11:36:46.959827 IMD ROOT 0. 0xffffec00 0x00000400
9424 11:36:46.963146 VPD 1. 0xffffeb80 0x0000006c
9425 11:36:46.966328 MMC STATUS 2. 0xffffeb60 0x00000004
9426 11:36:46.972839 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 11:36:46.979605 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9428 11:36:47.018151 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9429 11:36:47.021773 Checking segment from ROM address 0x40100000
9430 11:36:47.024762 Checking segment from ROM address 0x4010001c
9431 11:36:47.031724 Loading segment from ROM address 0x40100000
9432 11:36:47.032278 code (compression=0)
9433 11:36:47.041199 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9434 11:36:47.048083 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9435 11:36:47.048514 it's not compressed!
9436 11:36:47.054608 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9437 11:36:47.058208 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9438 11:36:47.078599 Loading segment from ROM address 0x4010001c
9439 11:36:47.079079 Entry Point 0x80000000
9440 11:36:47.081708 Loaded segments
9441 11:36:47.084902 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9442 11:36:47.091674 Jumping to boot code at 0x80000000(0xffe64000)
9443 11:36:47.098112 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9444 11:36:47.105003 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9445 11:36:47.113160 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9446 11:36:47.116048 Checking segment from ROM address 0x40100000
9447 11:36:47.119535 Checking segment from ROM address 0x4010001c
9448 11:36:47.126491 Loading segment from ROM address 0x40100000
9449 11:36:47.127001 code (compression=1)
9450 11:36:47.133372 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9451 11:36:47.142649 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9452 11:36:47.142932 using LZMA
9453 11:36:47.150868 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9454 11:36:47.157445 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9455 11:36:47.161174 Loading segment from ROM address 0x4010001c
9456 11:36:47.161403 Entry Point 0x54601000
9457 11:36:47.164189 Loaded segments
9458 11:36:47.167513 NOTICE: MT8192 bl31_setup
9459 11:36:47.174334 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9460 11:36:47.177714 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9461 11:36:47.181062 WARNING: region 0:
9462 11:36:47.184635 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 11:36:47.184801 WARNING: region 1:
9464 11:36:47.191158 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9465 11:36:47.194327 WARNING: region 2:
9466 11:36:47.197664 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9467 11:36:47.201037 WARNING: region 3:
9468 11:36:47.204168 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 11:36:47.207478 WARNING: region 4:
9470 11:36:47.214251 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 11:36:47.214418 WARNING: region 5:
9472 11:36:47.217334 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 11:36:47.221024 WARNING: region 6:
9474 11:36:47.224155 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 11:36:47.227540 WARNING: region 7:
9476 11:36:47.231108 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 11:36:47.237507 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9478 11:36:47.240418 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9479 11:36:47.244021 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9480 11:36:47.250551 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9481 11:36:47.253749 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9482 11:36:47.257277 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9483 11:36:47.264542 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9484 11:36:47.267818 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9485 11:36:47.274262 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9486 11:36:47.277047 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9487 11:36:47.281127 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9488 11:36:47.287565 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9489 11:36:47.291451 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9490 11:36:47.294398 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9491 11:36:47.300643 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9492 11:36:47.304308 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9493 11:36:47.311128 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9494 11:36:47.313731 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9495 11:36:47.317230 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9496 11:36:47.323968 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9497 11:36:47.327809 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9498 11:36:47.331078 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9499 11:36:47.337143 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9500 11:36:47.340533 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9501 11:36:47.347094 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9502 11:36:47.350686 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9503 11:36:47.357178 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9504 11:36:47.360480 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9505 11:36:47.364211 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9506 11:36:47.370583 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9507 11:36:47.374188 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9508 11:36:47.377006 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9509 11:36:47.383577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9510 11:36:47.386848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9511 11:36:47.390728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9512 11:36:47.393865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9513 11:36:47.400643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9514 11:36:47.403709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9515 11:36:47.407453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9516 11:36:47.410596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9517 11:36:47.417060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9518 11:36:47.420393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9519 11:36:47.423721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9520 11:36:47.427019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9521 11:36:47.433780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9522 11:36:47.436998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9523 11:36:47.440427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9524 11:36:47.443947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9525 11:36:47.450324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9526 11:36:47.453908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9527 11:36:47.460579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9528 11:36:47.463878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9529 11:36:47.470287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9530 11:36:47.474056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9531 11:36:47.477539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9532 11:36:47.483519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9533 11:36:47.487465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9534 11:36:47.493722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9535 11:36:47.497147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9536 11:36:47.504207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9537 11:36:47.507250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9538 11:36:47.514096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9539 11:36:47.517055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9540 11:36:47.519999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9541 11:36:47.527157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9542 11:36:47.530476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9543 11:36:47.537054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9544 11:36:47.540413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9545 11:36:47.546930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9546 11:36:47.550390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9547 11:36:47.553935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9548 11:36:47.560699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9549 11:36:47.563827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9550 11:36:47.570576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9551 11:36:47.573613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9552 11:36:47.580408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9553 11:36:47.583993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9554 11:36:47.587303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9555 11:36:47.593687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9556 11:36:47.596931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9557 11:36:47.603829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9558 11:36:47.606935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9559 11:36:47.613459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9560 11:36:47.616897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9561 11:36:47.623450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9562 11:36:47.626867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9563 11:36:47.629923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9564 11:36:47.636875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9565 11:36:47.640445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9566 11:36:47.647165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9567 11:36:47.649966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9568 11:36:47.656522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9569 11:36:47.660445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9570 11:36:47.663441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9571 11:36:47.670087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9572 11:36:47.673675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9573 11:36:47.680530 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9574 11:36:47.683486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9575 11:36:47.686808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9576 11:36:47.690089 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9577 11:36:47.696753 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9578 11:36:47.699901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9579 11:36:47.703646 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9580 11:36:47.710214 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9581 11:36:47.713494 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9582 11:36:47.720062 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9583 11:36:47.723560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9584 11:36:47.726801 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9585 11:36:47.733319 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9586 11:36:47.736588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9587 11:36:47.743147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9588 11:36:47.746429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9589 11:36:47.749739 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9590 11:36:47.756644 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9591 11:36:47.760107 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9592 11:36:47.766873 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9593 11:36:47.770078 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9594 11:36:47.773558 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9595 11:36:47.776593 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9596 11:36:47.783458 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9597 11:36:47.786945 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9598 11:36:47.789786 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9599 11:36:47.793190 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9600 11:36:47.800291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9601 11:36:47.803720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9602 11:36:47.806832 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9603 11:36:47.813116 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9604 11:36:47.817040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9605 11:36:47.823352 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9606 11:36:47.826615 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9607 11:36:47.830595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9608 11:36:47.836850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9609 11:36:47.839857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9610 11:36:47.843460 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9611 11:36:47.849972 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9612 11:36:47.853232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9613 11:36:47.860469 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9614 11:36:47.863211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9615 11:36:47.866627 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9616 11:36:47.873442 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9617 11:36:47.876933 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9618 11:36:47.883678 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9619 11:36:47.886848 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9620 11:36:47.890216 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9621 11:36:47.897605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9622 11:36:47.900024 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9623 11:36:47.903181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9624 11:36:47.909844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9625 11:36:47.913204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9626 11:36:47.919862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9627 11:36:47.923348 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9628 11:36:47.926753 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9629 11:36:47.933752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9630 11:36:47.936623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9631 11:36:47.943538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9632 11:36:47.946570 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9633 11:36:47.950495 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9634 11:36:47.957080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9635 11:36:47.960373 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9636 11:36:47.963476 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9637 11:36:47.970039 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9638 11:36:47.973290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9639 11:36:47.979802 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9640 11:36:47.983246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9641 11:36:47.986367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9642 11:36:47.993396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9643 11:36:47.996115 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9644 11:36:48.002849 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9645 11:36:48.006158 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9646 11:36:48.009472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9647 11:36:48.016071 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9648 11:36:48.020181 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9649 11:36:48.026650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9650 11:36:48.029726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9651 11:36:48.033227 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9652 11:36:48.040198 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9653 11:36:48.042902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9654 11:36:48.049747 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9655 11:36:48.053588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9656 11:36:48.056626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9657 11:36:48.063401 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9658 11:36:48.066674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9659 11:36:48.069876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9660 11:36:48.076340 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9661 11:36:48.079791 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9662 11:36:48.086635 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9663 11:36:48.089694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9664 11:36:48.093691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9665 11:36:48.100204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9666 11:36:48.103035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9667 11:36:48.110069 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9668 11:36:48.113306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9669 11:36:48.116557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9670 11:36:48.123247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9671 11:36:48.126459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9672 11:36:48.133361 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9673 11:36:48.136065 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9674 11:36:48.143038 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9675 11:36:48.146271 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9676 11:36:48.149560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9677 11:36:48.156776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9678 11:36:48.160128 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9679 11:36:48.166368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9680 11:36:48.169571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9681 11:36:48.172821 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9682 11:36:48.179645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9683 11:36:48.182808 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9684 11:36:48.189830 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9685 11:36:48.193339 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9686 11:36:48.197305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9687 11:36:48.202803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9688 11:36:48.205972 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9689 11:36:48.212701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9690 11:36:48.216426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9691 11:36:48.219597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9692 11:36:48.226180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9693 11:36:48.229284 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9694 11:36:48.236463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9695 11:36:48.239900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9696 11:36:48.246444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9697 11:36:48.249842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9698 11:36:48.252738 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9699 11:36:48.259509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9700 11:36:48.262924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9701 11:36:48.269468 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9702 11:36:48.272876 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9703 11:36:48.279927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9704 11:36:48.283498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9705 11:36:48.286255 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9706 11:36:48.289538 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9707 11:36:48.296136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9708 11:36:48.299436 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9709 11:36:48.302812 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9710 11:36:48.306540 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9711 11:36:48.313191 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9712 11:36:48.316035 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9713 11:36:48.322877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9714 11:36:48.326074 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9715 11:36:48.329705 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9716 11:36:48.336091 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9717 11:36:48.339424 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9718 11:36:48.342839 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9719 11:36:48.350050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9720 11:36:48.352905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9721 11:36:48.355981 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9722 11:36:48.363238 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9723 11:36:48.366557 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9724 11:36:48.372984 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9725 11:36:48.376275 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9726 11:36:48.379491 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9727 11:36:48.386307 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9728 11:36:48.389510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9729 11:36:48.392814 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9730 11:36:48.399532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9731 11:36:48.402807 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9732 11:36:48.406582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9733 11:36:48.413231 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9734 11:36:48.416269 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9735 11:36:48.419438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9736 11:36:48.426178 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9737 11:36:48.429404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9738 11:36:48.435751 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9739 11:36:48.438966 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9740 11:36:48.442581 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9741 11:36:48.449579 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9742 11:36:48.452506 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9743 11:36:48.455499 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9744 11:36:48.462374 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9745 11:36:48.465638 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9746 11:36:48.468920 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9747 11:36:48.472288 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9748 11:36:48.479331 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9749 11:36:48.482234 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9750 11:36:48.485575 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9751 11:36:48.489451 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9752 11:36:48.495879 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9753 11:36:48.499106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9754 11:36:48.502443 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9755 11:36:48.505802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9756 11:36:48.512485 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9757 11:36:48.515510 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9758 11:36:48.519069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9759 11:36:48.525693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9760 11:36:48.529233 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9761 11:36:48.532621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9762 11:36:48.539231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9763 11:36:48.542625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9764 11:36:48.549685 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9765 11:36:48.552867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9766 11:36:48.556246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9767 11:36:48.563243 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9768 11:36:48.566406 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9769 11:36:48.572975 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9770 11:36:48.575859 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9771 11:36:48.582513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9772 11:36:48.586140 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9773 11:36:48.589266 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9774 11:36:48.596349 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9775 11:36:48.598896 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9776 11:36:48.606036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9777 11:36:48.609416 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9778 11:36:48.612421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9779 11:36:48.619644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9780 11:36:48.622543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9781 11:36:48.629459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9782 11:36:48.632608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9783 11:36:48.635829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9784 11:36:48.642907 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9785 11:36:48.646124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9786 11:36:48.652223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9787 11:36:48.655551 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9788 11:36:48.659150 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9789 11:36:48.665457 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9790 11:36:48.668799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9791 11:36:48.675622 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9792 11:36:48.678822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9793 11:36:48.682952 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9794 11:36:48.689193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9795 11:36:48.693007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9796 11:36:48.699306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9797 11:36:48.702597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9798 11:36:48.706085 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9799 11:36:48.712627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9800 11:36:48.716092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9801 11:36:48.722455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9802 11:36:48.725690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9803 11:36:48.729028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9804 11:36:48.735441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9805 11:36:48.739703 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9806 11:36:48.746196 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9807 11:36:48.749001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9808 11:36:48.752276 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9809 11:36:48.759466 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9810 11:36:48.762753 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9811 11:36:48.768913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9812 11:36:48.772199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9813 11:36:48.778951 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9814 11:36:48.782708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9815 11:36:48.785845 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9816 11:36:48.792041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9817 11:36:48.795359 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9818 11:36:48.802508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9819 11:36:48.806185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9820 11:36:48.809338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9821 11:36:48.816024 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9822 11:36:48.819140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9823 11:36:48.822285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9824 11:36:48.829133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9825 11:36:48.832373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9826 11:36:48.838908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9827 11:36:48.841994 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9828 11:36:48.849143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9829 11:36:48.852557 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9830 11:36:48.855481 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9831 11:36:48.861944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9832 11:36:48.865342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9833 11:36:48.871996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9834 11:36:48.875756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9835 11:36:48.881890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9836 11:36:48.885112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9837 11:36:48.888704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9838 11:36:48.895681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9839 11:36:48.898710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9840 11:36:48.905636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9841 11:36:48.909166 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9842 11:36:48.915517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9843 11:36:48.919034 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9844 11:36:48.922164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9845 11:36:48.928761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9846 11:36:48.931857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9847 11:36:48.938551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9848 11:36:48.941868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9849 11:36:48.948611 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9850 11:36:48.952029 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9851 11:36:48.955378 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9852 11:36:48.962541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9853 11:36:48.965801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9854 11:36:48.972383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9855 11:36:48.975519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9856 11:36:48.978590 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9857 11:36:48.985438 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9858 11:36:48.988791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9859 11:36:48.995364 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9860 11:36:48.998415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9861 11:36:49.004894 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9862 11:36:49.008579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9863 11:36:49.012056 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9864 11:36:49.018630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9865 11:36:49.022296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9866 11:36:49.028596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9867 11:36:49.031772 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9868 11:36:49.039023 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9869 11:36:49.042339 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9870 11:36:49.045412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9871 11:36:49.051685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9872 11:36:49.055516 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9873 11:36:49.061990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9874 11:36:49.065039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9875 11:36:49.071774 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9876 11:36:49.075116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9877 11:36:49.081676 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9878 11:36:49.085220 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9879 11:36:49.088619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9880 11:36:49.095127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9881 11:36:49.098593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9882 11:36:49.104839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9883 11:36:49.108938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9884 11:36:49.114915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9885 11:36:49.118480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9886 11:36:49.121773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9887 11:36:49.128398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9888 11:36:49.131691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9889 11:36:49.138730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9890 11:36:49.141731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9891 11:36:49.148239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9892 11:36:49.152100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9893 11:36:49.158224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9894 11:36:49.161312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9895 11:36:49.167951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9896 11:36:49.172038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9897 11:36:49.178322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9898 11:36:49.181618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9899 11:36:49.188237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9900 11:36:49.191554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9901 11:36:49.198328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9902 11:36:49.201863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9903 11:36:49.207672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9904 11:36:49.211668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9905 11:36:49.218286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9906 11:36:49.221373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9907 11:36:49.228109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9908 11:36:49.231283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9909 11:36:49.238229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9910 11:36:49.241625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9911 11:36:49.244972 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9912 11:36:49.247781 INFO: [APUAPC] vio 0
9913 11:36:49.254753 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9914 11:36:49.258073 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9915 11:36:49.261235 INFO: [APUAPC] D0_APC_0: 0x400510
9916 11:36:49.264640 INFO: [APUAPC] D0_APC_1: 0x0
9917 11:36:49.267707 INFO: [APUAPC] D0_APC_2: 0x1540
9918 11:36:49.270654 INFO: [APUAPC] D0_APC_3: 0x0
9919 11:36:49.274259 INFO: [APUAPC] D1_APC_0: 0xffffffff
9920 11:36:49.277290 INFO: [APUAPC] D1_APC_1: 0xffffffff
9921 11:36:49.280564 INFO: [APUAPC] D1_APC_2: 0x3fffff
9922 11:36:49.284163 INFO: [APUAPC] D1_APC_3: 0x0
9923 11:36:49.287446 INFO: [APUAPC] D2_APC_0: 0xffffffff
9924 11:36:49.291073 INFO: [APUAPC] D2_APC_1: 0xffffffff
9925 11:36:49.294264 INFO: [APUAPC] D2_APC_2: 0x3fffff
9926 11:36:49.298221 INFO: [APUAPC] D2_APC_3: 0x0
9927 11:36:49.301145 INFO: [APUAPC] D3_APC_0: 0xffffffff
9928 11:36:49.304622 INFO: [APUAPC] D3_APC_1: 0xffffffff
9929 11:36:49.307944 INFO: [APUAPC] D3_APC_2: 0x3fffff
9930 11:36:49.308330 INFO: [APUAPC] D3_APC_3: 0x0
9931 11:36:49.311348 INFO: [APUAPC] D4_APC_0: 0xffffffff
9932 11:36:49.318548 INFO: [APUAPC] D4_APC_1: 0xffffffff
9933 11:36:49.319077 INFO: [APUAPC] D4_APC_2: 0x3fffff
9934 11:36:49.321435 INFO: [APUAPC] D4_APC_3: 0x0
9935 11:36:49.325082 INFO: [APUAPC] D5_APC_0: 0xffffffff
9936 11:36:49.328325 INFO: [APUAPC] D5_APC_1: 0xffffffff
9937 11:36:49.331130 INFO: [APUAPC] D5_APC_2: 0x3fffff
9938 11:36:49.334854 INFO: [APUAPC] D5_APC_3: 0x0
9939 11:36:49.338242 INFO: [APUAPC] D6_APC_0: 0xffffffff
9940 11:36:49.341546 INFO: [APUAPC] D6_APC_1: 0xffffffff
9941 11:36:49.344961 INFO: [APUAPC] D6_APC_2: 0x3fffff
9942 11:36:49.348302 INFO: [APUAPC] D6_APC_3: 0x0
9943 11:36:49.351263 INFO: [APUAPC] D7_APC_0: 0xffffffff
9944 11:36:49.354636 INFO: [APUAPC] D7_APC_1: 0xffffffff
9945 11:36:49.357777 INFO: [APUAPC] D7_APC_2: 0x3fffff
9946 11:36:49.360904 INFO: [APUAPC] D7_APC_3: 0x0
9947 11:36:49.364629 INFO: [APUAPC] D8_APC_0: 0xffffffff
9948 11:36:49.367852 INFO: [APUAPC] D8_APC_1: 0xffffffff
9949 11:36:49.370619 INFO: [APUAPC] D8_APC_2: 0x3fffff
9950 11:36:49.373992 INFO: [APUAPC] D8_APC_3: 0x0
9951 11:36:49.377483 INFO: [APUAPC] D9_APC_0: 0xffffffff
9952 11:36:49.380788 INFO: [APUAPC] D9_APC_1: 0xffffffff
9953 11:36:49.384712 INFO: [APUAPC] D9_APC_2: 0x3fffff
9954 11:36:49.387395 INFO: [APUAPC] D9_APC_3: 0x0
9955 11:36:49.390951 INFO: [APUAPC] D10_APC_0: 0xffffffff
9956 11:36:49.393985 INFO: [APUAPC] D10_APC_1: 0xffffffff
9957 11:36:49.397954 INFO: [APUAPC] D10_APC_2: 0x3fffff
9958 11:36:49.400727 INFO: [APUAPC] D10_APC_3: 0x0
9959 11:36:49.404174 INFO: [APUAPC] D11_APC_0: 0xffffffff
9960 11:36:49.408033 INFO: [APUAPC] D11_APC_1: 0xffffffff
9961 11:36:49.411177 INFO: [APUAPC] D11_APC_2: 0x3fffff
9962 11:36:49.414755 INFO: [APUAPC] D11_APC_3: 0x0
9963 11:36:49.417812 INFO: [APUAPC] D12_APC_0: 0xffffffff
9964 11:36:49.421178 INFO: [APUAPC] D12_APC_1: 0xffffffff
9965 11:36:49.424612 INFO: [APUAPC] D12_APC_2: 0x3fffff
9966 11:36:49.427520 INFO: [APUAPC] D12_APC_3: 0x0
9967 11:36:49.431151 INFO: [APUAPC] D13_APC_0: 0xffffffff
9968 11:36:49.434815 INFO: [APUAPC] D13_APC_1: 0xffffffff
9969 11:36:49.437643 INFO: [APUAPC] D13_APC_2: 0x3fffff
9970 11:36:49.441249 INFO: [APUAPC] D13_APC_3: 0x0
9971 11:36:49.444342 INFO: [APUAPC] D14_APC_0: 0xffffffff
9972 11:36:49.447736 INFO: [APUAPC] D14_APC_1: 0xffffffff
9973 11:36:49.450825 INFO: [APUAPC] D14_APC_2: 0x3fffff
9974 11:36:49.454998 INFO: [APUAPC] D14_APC_3: 0x0
9975 11:36:49.457601 INFO: [APUAPC] D15_APC_0: 0xffffffff
9976 11:36:49.461281 INFO: [APUAPC] D15_APC_1: 0xffffffff
9977 11:36:49.464666 INFO: [APUAPC] D15_APC_2: 0x3fffff
9978 11:36:49.467722 INFO: [APUAPC] D15_APC_3: 0x0
9979 11:36:49.471276 INFO: [APUAPC] APC_CON: 0x4
9980 11:36:49.474313 INFO: [NOCDAPC] D0_APC_0: 0x0
9981 11:36:49.477636 INFO: [NOCDAPC] D0_APC_1: 0x0
9982 11:36:49.478060 INFO: [NOCDAPC] D1_APC_0: 0x0
9983 11:36:49.480794 INFO: [NOCDAPC] D1_APC_1: 0xfff
9984 11:36:49.484317 INFO: [NOCDAPC] D2_APC_0: 0x0
9985 11:36:49.487615 INFO: [NOCDAPC] D2_APC_1: 0xfff
9986 11:36:49.490761 INFO: [NOCDAPC] D3_APC_0: 0x0
9987 11:36:49.494090 INFO: [NOCDAPC] D3_APC_1: 0xfff
9988 11:36:49.497850 INFO: [NOCDAPC] D4_APC_0: 0x0
9989 11:36:49.500645 INFO: [NOCDAPC] D4_APC_1: 0xfff
9990 11:36:49.504578 INFO: [NOCDAPC] D5_APC_0: 0x0
9991 11:36:49.507344 INFO: [NOCDAPC] D5_APC_1: 0xfff
9992 11:36:49.511425 INFO: [NOCDAPC] D6_APC_0: 0x0
9993 11:36:49.514147 INFO: [NOCDAPC] D6_APC_1: 0xfff
9994 11:36:49.514655 INFO: [NOCDAPC] D7_APC_0: 0x0
9995 11:36:49.517263 INFO: [NOCDAPC] D7_APC_1: 0xfff
9996 11:36:49.520706 INFO: [NOCDAPC] D8_APC_0: 0x0
9997 11:36:49.523998 INFO: [NOCDAPC] D8_APC_1: 0xfff
9998 11:36:49.527165 INFO: [NOCDAPC] D9_APC_0: 0x0
9999 11:36:49.530860 INFO: [NOCDAPC] D9_APC_1: 0xfff
10000 11:36:49.534207 INFO: [NOCDAPC] D10_APC_0: 0x0
10001 11:36:49.537341 INFO: [NOCDAPC] D10_APC_1: 0xfff
10002 11:36:49.540603 INFO: [NOCDAPC] D11_APC_0: 0x0
10003 11:36:49.543530 INFO: [NOCDAPC] D11_APC_1: 0xfff
10004 11:36:49.547428 INFO: [NOCDAPC] D12_APC_0: 0x0
10005 11:36:49.550399 INFO: [NOCDAPC] D12_APC_1: 0xfff
10006 11:36:49.550798 INFO: [NOCDAPC] D13_APC_0: 0x0
10007 11:36:49.553766 INFO: [NOCDAPC] D13_APC_1: 0xfff
10008 11:36:49.557205 INFO: [NOCDAPC] D14_APC_0: 0x0
10009 11:36:49.560824 INFO: [NOCDAPC] D14_APC_1: 0xfff
10010 11:36:49.564122 INFO: [NOCDAPC] D15_APC_0: 0x0
10011 11:36:49.567410 INFO: [NOCDAPC] D15_APC_1: 0xfff
10012 11:36:49.570744 INFO: [NOCDAPC] APC_CON: 0x4
10013 11:36:49.573883 INFO: [APUAPC] set_apusys_apc done
10014 11:36:49.576925 INFO: [DEVAPC] devapc_init done
10015 11:36:49.580629 INFO: GICv3 without legacy support detected.
10016 11:36:49.583838 INFO: ARM GICv3 driver initialized in EL3
10017 11:36:49.587175 INFO: Maximum SPI INTID supported: 639
10018 11:36:49.593944 INFO: BL31: Initializing runtime services
10019 11:36:49.597433 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10020 11:36:49.600623 INFO: SPM: enable CPC mode
10021 11:36:49.607384 INFO: mcdi ready for mcusys-off-idle and system suspend
10022 11:36:49.610712 INFO: BL31: Preparing for EL3 exit to normal world
10023 11:36:49.614323 INFO: Entry point address = 0x80000000
10024 11:36:49.617300 INFO: SPSR = 0x8
10025 11:36:49.622272
10026 11:36:49.622657
10027 11:36:49.622959
10028 11:36:49.625685 Starting depthcharge on Spherion...
10029 11:36:49.626103
10030 11:36:49.626407 Wipe memory regions:
10031 11:36:49.626689
10032 11:36:49.628997 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10033 11:36:49.629446 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10034 11:36:49.629809 Setting prompt string to ['asurada:']
10035 11:36:49.630160 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10036 11:36:49.630752 [0x00000040000000, 0x00000054600000)
10037 11:36:49.751369
10038 11:36:49.751587 [0x00000054660000, 0x00000080000000)
10039 11:36:50.012324
10040 11:36:50.015519 [0x000000821a7280, 0x000000ffe64000)
10041 11:36:50.756472
10042 11:36:50.756585 [0x00000100000000, 0x00000240000000)
10043 11:36:52.647021
10044 11:36:52.650153 Initializing XHCI USB controller at 0x11200000.
10045 11:36:53.688627
10046 11:36:53.691905 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10047 11:36:53.692297
10048 11:36:53.692604
10049 11:36:53.693262 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 11:36:53.693615 Sending line: 'tftpboot 192.168.201.1 14864641/tftp-deploy-ttb4uouz/kernel/image.itb 14864641/tftp-deploy-ttb4uouz/kernel/cmdline '
10052 11:36:53.795102 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 11:36:53.795562 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10054 11:36:53.800368 asurada: tftpboot 192.168.201.1 14864641/tftp-deploy-ttb4uouz/kernel/image.ittp-deploy-ttb4uouz/kernel/cmdline
10055 11:36:53.800807
10056 11:36:53.801142 Waiting for link
10057 11:36:53.958549
10058 11:36:53.959012 R8152: Initializing
10059 11:36:53.959318
10060 11:36:53.961968 Version 9 (ocp_data = 6010)
10061 11:36:53.962501
10062 11:36:53.964890 R8152: Done initializing
10063 11:36:53.965280
10064 11:36:53.965583 Adding net device
10065 11:36:55.910112
10066 11:36:55.910543 done.
10067 11:36:55.910887
10068 11:36:55.911178 MAC: 00:e0:4c:78:7a:aa
10069 11:36:55.911457
10070 11:36:55.913257 Sending DHCP discover... done.
10071 11:36:55.913645
10072 11:36:55.917083 Waiting for reply... done.
10073 11:36:55.917517
10074 11:36:55.920098 Sending DHCP request... done.
10075 11:36:55.920267
10076 11:36:55.923467 Waiting for reply... done.
10077 11:36:55.923637
10078 11:36:55.923767 My ip is 192.168.201.12
10079 11:36:55.923890
10080 11:36:55.926367 The DHCP server ip is 192.168.201.1
10081 11:36:55.926539
10082 11:36:55.932767 TFTP server IP predefined by user: 192.168.201.1
10083 11:36:55.932983
10084 11:36:55.939813 Bootfile predefined by user: 14864641/tftp-deploy-ttb4uouz/kernel/image.itb
10085 11:36:55.939983
10086 11:36:55.942920 Sending tftp read request... done.
10087 11:36:55.943090
10088 11:36:55.948046 Waiting for the transfer...
10089 11:36:55.948217
10090 11:36:56.205183 00000000 ################################################################
10091 11:36:56.205294
10092 11:36:56.465943 00080000 ################################################################
10093 11:36:56.466107
10094 11:36:56.731532 00100000 ################################################################
10095 11:36:56.731658
10096 11:36:56.987696 00180000 ################################################################
10097 11:36:56.987851
10098 11:36:57.257185 00200000 ################################################################
10099 11:36:57.257309
10100 11:36:57.530988 00280000 ################################################################
10101 11:36:57.531131
10102 11:36:57.789687 00300000 ################################################################
10103 11:36:57.789801
10104 11:36:58.044405 00380000 ################################################################
10105 11:36:58.044547
10106 11:36:58.309616 00400000 ################################################################
10107 11:36:58.309729
10108 11:36:58.568549 00480000 ################################################################
10109 11:36:58.568683
10110 11:36:58.821718 00500000 ################################################################
10111 11:36:58.821835
10112 11:36:59.078201 00580000 ################################################################
10113 11:36:59.078392
10114 11:36:59.333482 00600000 ################################################################
10115 11:36:59.333599
10116 11:36:59.599076 00680000 ################################################################
10117 11:36:59.599215
10118 11:36:59.860298 00700000 ################################################################
10119 11:36:59.860412
10120 11:37:00.122984 00780000 ################################################################
10121 11:37:00.123098
10122 11:37:00.370412 00800000 ################################################################
10123 11:37:00.370520
10124 11:37:00.623834 00880000 ################################################################
10125 11:37:00.623949
10126 11:37:00.884386 00900000 ################################################################
10127 11:37:00.884530
10128 11:37:01.137484 00980000 ################################################################
10129 11:37:01.137600
10130 11:37:01.412664 00a00000 ################################################################
10131 11:37:01.412776
10132 11:37:01.676970 00a80000 ################################################################
10133 11:37:01.677086
10134 11:37:01.930964 00b00000 ################################################################
10135 11:37:01.931079
10136 11:37:02.206821 00b80000 ################################################################
10137 11:37:02.206951
10138 11:37:02.484580 00c00000 ################################################################
10139 11:37:02.484694
10140 11:37:02.754216 00c80000 ################################################################
10141 11:37:02.754332
10142 11:37:03.004133 00d00000 ################################################################
10143 11:37:03.004246
10144 11:37:03.255879 00d80000 ################################################################
10145 11:37:03.255996
10146 11:37:03.525921 00e00000 ################################################################
10147 11:37:03.526075
10148 11:37:03.797415 00e80000 ################################################################
10149 11:37:03.797538
10150 11:37:04.070033 00f00000 ################################################################
10151 11:37:04.070180
10152 11:37:04.352384 00f80000 ################################################################
10153 11:37:04.352501
10154 11:37:04.613827 01000000 ################################################################
10155 11:37:04.613944
10156 11:37:04.901963 01080000 ################################################################
10157 11:37:04.902131
10158 11:37:05.172587 01100000 ################################################################
10159 11:37:05.172714
10160 11:37:05.419839 01180000 ################################################################
10161 11:37:05.419967
10162 11:37:05.665957 01200000 ################################################################
10163 11:37:05.666131
10164 11:37:05.920054 01280000 ################################################################
10165 11:37:05.920185
10166 11:37:06.173388 01300000 ################################################################
10167 11:37:06.173521
10168 11:37:06.443147 01380000 ################################################################
10169 11:37:06.443276
10170 11:37:06.730467 01400000 ################################################################
10171 11:37:06.730588
10172 11:37:06.988498 01480000 ################################################################
10173 11:37:06.988622
10174 11:37:07.236530 01500000 ################################################################
10175 11:37:07.236657
10176 11:37:07.483727 01580000 ################################################################
10177 11:37:07.483849
10178 11:37:07.743345 01600000 ################################################################
10179 11:37:07.743493
10180 11:37:08.001144 01680000 ################################################################
10181 11:37:08.001306
10182 11:37:08.248879 01700000 ################################################################
10183 11:37:08.249010
10184 11:37:08.513053 01780000 ################################################################
10185 11:37:08.513182
10186 11:37:08.769571 01800000 ################################################################
10187 11:37:08.769701
10188 11:37:09.037505 01880000 ################################################################
10189 11:37:09.037631
10190 11:37:09.323331 01900000 ################################################################
10191 11:37:09.323448
10192 11:37:09.584953 01980000 ################################################################
10193 11:37:09.585098
10194 11:37:09.836431 01a00000 ################################################################
10195 11:37:09.836548
10196 11:37:10.089372 01a80000 ################################################################
10197 11:37:10.089501
10198 11:37:10.366527 01b00000 ################################################################
10199 11:37:10.366652
10200 11:37:10.642190 01b80000 ################################################################
10201 11:37:10.642318
10202 11:37:10.891800 01c00000 ################################################################
10203 11:37:10.891947
10204 11:37:11.154505 01c80000 ################################################################
10205 11:37:11.154626
10206 11:37:11.402361 01d00000 ################################################################
10207 11:37:11.402484
10208 11:37:11.679896 01d80000 ################################################################
10209 11:37:11.680026
10210 11:37:11.958572 01e00000 ################################################################
10211 11:37:11.958701
10212 11:37:12.230763 01e80000 ################################################################
10213 11:37:12.230884
10214 11:37:12.503294 01f00000 ################################################################
10215 11:37:12.503423
10216 11:37:12.773979 01f80000 ################################################################
10217 11:37:12.774114
10218 11:37:13.046987 02000000 ################################################################
10219 11:37:13.047115
10220 11:37:13.324073 02080000 ################################################################
10221 11:37:13.324221
10222 11:37:13.600924 02100000 ################################################################
10223 11:37:13.601048
10224 11:37:13.871954 02180000 ################################################################
10225 11:37:13.872073
10226 11:37:14.156054 02200000 ################################################################
10227 11:37:14.156177
10228 11:37:14.431783 02280000 ################################################################
10229 11:37:14.431935
10230 11:37:14.720991 02300000 ################################################################
10231 11:37:14.721115
10232 11:37:14.994217 02380000 ################################################################
10233 11:37:14.994334
10234 11:37:15.265879 02400000 ################################################################
10235 11:37:15.266000
10236 11:37:15.522518 02480000 ################################################################
10237 11:37:15.522642
10238 11:37:15.794279 02500000 ################################################################
10239 11:37:15.794400
10240 11:37:16.081991 02580000 ################################################################
10241 11:37:16.082141
10242 11:37:16.349988 02600000 ################################################################
10243 11:37:16.350167
10244 11:37:16.609383 02680000 ################################################################
10245 11:37:16.609500
10246 11:37:16.861732 02700000 ################################################################
10247 11:37:16.861846
10248 11:37:17.128922 02780000 ################################################################
10249 11:37:17.129039
10250 11:37:17.403549 02800000 ################################################################
10251 11:37:17.403660
10252 11:37:17.656654 02880000 ################################################################
10253 11:37:17.656775
10254 11:37:17.927604 02900000 ################################################################
10255 11:37:17.927729
10256 11:37:18.194189 02980000 ################################################################
10257 11:37:18.194312
10258 11:37:18.461596 02a00000 ################################################################
10259 11:37:18.461829
10260 11:37:18.738239 02a80000 ################################################################
10261 11:37:18.738363
10262 11:37:19.030690 02b00000 ################################################################
10263 11:37:19.030812
10264 11:37:19.321379 02b80000 ################################################################
10265 11:37:19.321500
10266 11:37:19.605068 02c00000 ################################################################
10267 11:37:19.605189
10268 11:37:19.880171 02c80000 ################################################################
10269 11:37:19.880287
10270 11:37:20.163188 02d00000 ################################################################
10271 11:37:20.163340
10272 11:37:20.460853 02d80000 ################################################################
10273 11:37:20.460975
10274 11:37:20.757363 02e00000 ################################################################
10275 11:37:20.757505
10276 11:37:21.054863 02e80000 ################################################################
10277 11:37:21.054988
10278 11:37:21.353318 02f00000 ################################################################
10279 11:37:21.353443
10280 11:37:21.634277 02f80000 ################################################################
10281 11:37:21.634400
10282 11:37:21.891144 03000000 ################################################################
10283 11:37:21.891267
10284 11:37:22.169457 03080000 ################################################################
10285 11:37:22.169588
10286 11:37:22.454320 03100000 ################################################################
10287 11:37:22.454447
10288 11:37:22.738143 03180000 ################################################################
10289 11:37:22.738271
10290 11:37:23.008510 03200000 ################################################################
10291 11:37:23.008636
10292 11:37:23.287019 03280000 ################################################################
10293 11:37:23.287138
10294 11:37:23.554611 03300000 ################################################################
10295 11:37:23.554722
10296 11:37:23.742174 03380000 ############################################## done.
10297 11:37:23.742290
10298 11:37:23.745699 The bootfile was 54375530 bytes long.
10299 11:37:23.745780
10300 11:37:23.745841 Sending tftp read request... done.
10301 11:37:23.748860
10302 11:37:23.748937 Waiting for the transfer...
10303 11:37:23.749003
10304 11:37:23.752245 00000000 # done.
10305 11:37:23.752325
10306 11:37:23.758873 Command line loaded dynamically from TFTP file: 14864641/tftp-deploy-ttb4uouz/kernel/cmdline
10307 11:37:23.758952
10308 11:37:23.772393 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 11:37:23.772548
10310 11:37:23.775800 Loading FIT.
10311 11:37:23.775948
10312 11:37:23.778741 Image ramdisk-1 has 41207950 bytes.
10313 11:37:23.778873
10314 11:37:23.778979 Image fdt-1 has 47258 bytes.
10315 11:37:23.779081
10316 11:37:23.782972 Image kernel-1 has 13118294 bytes.
10317 11:37:23.783078
10318 11:37:23.791976 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 11:37:23.792147
10320 11:37:23.808736 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 11:37:23.809005
10322 11:37:23.816107 Choosing best match conf-1 for compat google,spherion-rev2.
10323 11:37:23.819330
10324 11:37:23.824410 Connected to device vid:did:rid of 1ae0:0028:00
10325 11:37:23.832724
10326 11:37:23.835651 tpm_get_response: command 0x17b, return code 0x0
10327 11:37:23.836095
10328 11:37:23.842248 ec_init: CrosEC protocol v3 supported (256, 248)
10329 11:37:23.842756
10330 11:37:23.845393 tpm_cleanup: add release locality here.
10331 11:37:23.845829
10332 11:37:23.848957 Shutting down all USB controllers.
10333 11:37:23.849468
10334 11:37:23.852954 Removing current net device
10335 11:37:23.853462
10336 11:37:23.855263 Exiting depthcharge with code 4 at timestamp: 63541753
10337 11:37:23.855640
10338 11:37:23.859458 LZMA decompressing kernel-1 to 0x821a6718
10339 11:37:23.859971
10340 11:37:23.862478 LZMA decompressing kernel-1 to 0x40000000
10341 11:37:25.478786
10342 11:37:25.479293 jumping to kernel
10343 11:37:25.481391 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10344 11:37:25.481902 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10345 11:37:25.482343 Setting prompt string to ['Linux version [0-9]']
10346 11:37:25.482694 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 11:37:25.483044 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 11:37:25.560457
10349 11:37:25.564212 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 11:37:25.567573 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10351 11:37:25.568144 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 11:37:25.568522 Setting prompt string to []
10353 11:37:25.568916 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 11:37:25.569299 Using line separator: #'\n'#
10355 11:37:25.569670 No login prompt set.
10356 11:37:25.570056 Parsing kernel messages
10357 11:37:25.570374 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 11:37:25.570926 [login-action] Waiting for messages, (timeout 00:03:44)
10359 11:37:25.571264 Waiting using forced prompt support (timeout 00:01:52)
10360 11:37:25.587260 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10361 11:37:25.589974 [ 0.000000] random: crng init done
10362 11:37:25.593202 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10363 11:37:25.596678 [ 0.000000] efi: UEFI not found.
10364 11:37:25.607101 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10365 11:37:25.613498 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10366 11:37:25.623204 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10367 11:37:25.633797 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10368 11:37:25.640315 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10369 11:37:25.643804 [ 0.000000] printk: bootconsole [mtk8250] enabled
10370 11:37:25.651776 [ 0.000000] NUMA: No NUMA configuration found
10371 11:37:25.658257 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 11:37:25.665283 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10373 11:37:25.665793 [ 0.000000] Zone ranges:
10374 11:37:25.671247 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 11:37:25.674531 [ 0.000000] DMA32 empty
10376 11:37:25.681409 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 11:37:25.684503 [ 0.000000] Movable zone start for each node
10378 11:37:25.688105 [ 0.000000] Early memory node ranges
10379 11:37:25.694512 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 11:37:25.701186 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 11:37:25.707763 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 11:37:25.714173 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 11:37:25.721160 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 11:37:25.727794 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 11:37:25.784404 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 11:37:25.791293 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 11:37:25.798211 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 11:37:25.801615 [ 0.000000] psci: probing for conduit method from DT.
10389 11:37:25.807901 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 11:37:25.811343 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 11:37:25.818137 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 11:37:25.821201 [ 0.000000] psci: SMC Calling Convention v1.2
10393 11:37:25.827681 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10394 11:37:25.830828 [ 0.000000] Detected VIPT I-cache on CPU0
10395 11:37:25.837779 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 11:37:25.844582 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 11:37:25.851239 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 11:37:25.857590 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 11:37:25.864468 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 11:37:25.870956 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 11:37:25.877845 [ 0.000000] alternatives: applying boot alternatives
10402 11:37:25.884193 [ 0.000000] Fallback order for Node 0: 0
10403 11:37:25.890669 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 11:37:25.894050 [ 0.000000] Policy zone: Normal
10405 11:37:25.906908 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10406 11:37:25.917702 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 11:37:25.929120 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 11:37:25.938392 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 11:37:25.945384 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10410 11:37:25.948472 <6>[ 0.000000] software IO TLB: area num 8.
10411 11:37:26.005946 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 11:37:26.155067 <6>[ 0.000000] Memory: 7923820K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 428948K reserved, 32768K cma-reserved)
10413 11:37:26.161347 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 11:37:26.167886 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 11:37:26.171346 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10416 11:37:26.178750 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 11:37:26.184886 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 11:37:26.188625 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10419 11:37:26.198378 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 11:37:26.204603 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 11:37:26.211135 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 11:37:26.218031 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 11:37:26.220955 <6>[ 0.000000] GICv3: 608 SPIs implemented
10424 11:37:26.224820 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10425 11:37:26.231336 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10426 11:37:26.235570 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 11:37:26.241433 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 11:37:26.254360 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 11:37:26.264443 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 11:37:26.274132 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 11:37:26.282062 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 11:37:26.294868 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 11:37:26.301694 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 11:37:26.308118 <6>[ 0.009231] Console: colour dummy device 80x25
10435 11:37:26.318265 <6>[ 0.013965] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 11:37:26.324888 <6>[ 0.024471] pid_max: default: 32768 minimum: 301
10437 11:37:26.327783 <6>[ 0.029373] LSM: Security Framework initializing
10438 11:37:26.334713 <6>[ 0.034311] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:37:26.344597 <6>[ 0.042125] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 11:37:26.352161 <6>[ 0.051565] cblist_init_generic: Setting adjustable number of callback queues.
10441 11:37:26.358533 <6>[ 0.059007] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 11:37:26.368419 <6>[ 0.065347] cblist_init_generic: Setting adjustable number of callback queues.
10443 11:37:26.371397 <6>[ 0.072773] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 11:37:26.379024 <6>[ 0.079174] rcu: Hierarchical SRCU implementation.
10445 11:37:26.385044 <6>[ 0.084220] rcu: Max phase no-delay instances is 1000.
10446 11:37:26.391341 <6>[ 0.091240] EFI services will not be available.
10447 11:37:26.394266 <6>[ 0.096199] smp: Bringing up secondary CPUs ...
10448 11:37:26.402785 <6>[ 0.101251] Detected VIPT I-cache on CPU1
10449 11:37:26.409140 <6>[ 0.101323] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10450 11:37:26.415876 <6>[ 0.101356] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10451 11:37:26.419378 <6>[ 0.101701] Detected VIPT I-cache on CPU2
10452 11:37:26.426168 <6>[ 0.101755] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10453 11:37:26.432851 <6>[ 0.101773] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10454 11:37:26.439508 <6>[ 0.102034] Detected VIPT I-cache on CPU3
10455 11:37:26.446414 <6>[ 0.102083] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10456 11:37:26.452849 <6>[ 0.102098] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10457 11:37:26.455775 <6>[ 0.102402] CPU features: detected: Spectre-v4
10458 11:37:26.462646 <6>[ 0.102409] CPU features: detected: Spectre-BHB
10459 11:37:26.466157 <6>[ 0.102415] Detected PIPT I-cache on CPU4
10460 11:37:26.473161 <6>[ 0.102476] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10461 11:37:26.479326 <6>[ 0.102494] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10462 11:37:26.482960 <6>[ 0.102788] Detected PIPT I-cache on CPU5
10463 11:37:26.492933 <6>[ 0.102850] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10464 11:37:26.499404 <6>[ 0.102866] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10465 11:37:26.502947 <6>[ 0.103149] Detected PIPT I-cache on CPU6
10466 11:37:26.509250 <6>[ 0.103216] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10467 11:37:26.516410 <6>[ 0.103232] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10468 11:37:26.519591 <6>[ 0.103531] Detected PIPT I-cache on CPU7
10469 11:37:26.529206 <6>[ 0.103597] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10470 11:37:26.535679 <6>[ 0.103613] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10471 11:37:26.539523 <6>[ 0.103662] smp: Brought up 1 node, 8 CPUs
10472 11:37:26.542638 <6>[ 0.244918] SMP: Total of 8 processors activated.
10473 11:37:26.549322 <6>[ 0.249870] CPU features: detected: 32-bit EL0 Support
10474 11:37:26.558747 <6>[ 0.255232] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10475 11:37:26.565443 <6>[ 0.264088] CPU features: detected: Common not Private translations
10476 11:37:26.569126 <6>[ 0.270564] CPU features: detected: CRC32 instructions
10477 11:37:26.575821 <6>[ 0.275915] CPU features: detected: RCpc load-acquire (LDAPR)
10478 11:37:26.581980 <6>[ 0.281875] CPU features: detected: LSE atomic instructions
10479 11:37:26.588774 <6>[ 0.287657] CPU features: detected: Privileged Access Never
10480 11:37:26.592115 <6>[ 0.293436] CPU features: detected: RAS Extension Support
10481 11:37:26.598699 <6>[ 0.299045] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10482 11:37:26.605146 <6>[ 0.306265] CPU: All CPU(s) started at EL2
10483 11:37:26.612126 <6>[ 0.310608] alternatives: applying system-wide alternatives
10484 11:37:26.620277 <6>[ 0.321489] devtmpfs: initialized
10485 11:37:26.632764 <6>[ 0.330299] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10486 11:37:26.642317 <6>[ 0.340258] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10487 11:37:26.648968 <6>[ 0.348518] pinctrl core: initialized pinctrl subsystem
10488 11:37:26.652691 <6>[ 0.355244] DMI not present or invalid.
10489 11:37:26.659175 <6>[ 0.359659] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10490 11:37:26.668887 <6>[ 0.366558] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10491 11:37:26.675621 <6>[ 0.374149] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10492 11:37:26.685889 <6>[ 0.382378] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10493 11:37:26.688538 <6>[ 0.390622] audit: initializing netlink subsys (disabled)
10494 11:37:26.698829 <5>[ 0.396319] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10495 11:37:26.705750 <6>[ 0.397061] thermal_sys: Registered thermal governor 'step_wise'
10496 11:37:26.711866 <6>[ 0.404287] thermal_sys: Registered thermal governor 'power_allocator'
10497 11:37:26.715377 <6>[ 0.410541] cpuidle: using governor menu
10498 11:37:26.721996 <6>[ 0.421499] NET: Registered PF_QIPCRTR protocol family
10499 11:37:26.729031 <6>[ 0.426999] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10500 11:37:26.734834 <6>[ 0.434098] ASID allocator initialised with 32768 entries
10501 11:37:26.738886 <6>[ 0.440675] Serial: AMBA PL011 UART driver
10502 11:37:26.749076 <4>[ 0.450410] Trying to register duplicate clock ID: 134
10503 11:37:26.807122 <6>[ 0.511795] KASLR enabled
10504 11:37:26.821321 <6>[ 0.519464] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10505 11:37:26.828066 <6>[ 0.526477] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10506 11:37:26.835176 <6>[ 0.532965] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10507 11:37:26.841357 <6>[ 0.539969] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10508 11:37:26.848365 <6>[ 0.546457] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10509 11:37:26.854857 <6>[ 0.553459] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10510 11:37:26.861396 <6>[ 0.559945] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10511 11:37:26.868481 <6>[ 0.566951] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10512 11:37:26.871929 <6>[ 0.574489] ACPI: Interpreter disabled.
10513 11:37:26.879716 <6>[ 0.580930] iommu: Default domain type: Translated
10514 11:37:26.886880 <6>[ 0.586040] iommu: DMA domain TLB invalidation policy: strict mode
10515 11:37:26.890077 <5>[ 0.592689] SCSI subsystem initialized
10516 11:37:26.896679 <6>[ 0.596855] usbcore: registered new interface driver usbfs
10517 11:37:26.903333 <6>[ 0.602584] usbcore: registered new interface driver hub
10518 11:37:26.906571 <6>[ 0.608131] usbcore: registered new device driver usb
10519 11:37:26.913752 <6>[ 0.614235] pps_core: LinuxPPS API ver. 1 registered
10520 11:37:26.923643 <6>[ 0.619431] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10521 11:37:26.926636 <6>[ 0.628772] PTP clock support registered
10522 11:37:26.929579 <6>[ 0.633017] EDAC MC: Ver: 3.0.0
10523 11:37:26.937498 <6>[ 0.638187] FPGA manager framework
10524 11:37:26.940644 <6>[ 0.641864] Advanced Linux Sound Architecture Driver Initialized.
10525 11:37:26.944177 <6>[ 0.648649] vgaarb: loaded
10526 11:37:26.951207 <6>[ 0.651810] clocksource: Switched to clocksource arch_sys_counter
10527 11:37:26.957565 <5>[ 0.658249] VFS: Disk quotas dquot_6.6.0
10528 11:37:26.963767 <6>[ 0.662436] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 11:37:26.966993 <6>[ 0.669623] pnp: PnP ACPI: disabled
10530 11:37:26.974971 <6>[ 0.676311] NET: Registered PF_INET protocol family
10531 11:37:26.984858 <6>[ 0.681904] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10532 11:37:26.995995 <6>[ 0.694252] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10533 11:37:27.006141 <6>[ 0.703068] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10534 11:37:27.012926 <6>[ 0.711039] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10535 11:37:27.022815 <6>[ 0.719743] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10536 11:37:27.029300 <6>[ 0.729499] TCP: Hash tables configured (established 65536 bind 65536)
10537 11:37:27.035942 <6>[ 0.736361] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 11:37:27.046216 <6>[ 0.743557] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 11:37:27.052588 <6>[ 0.751259] NET: Registered PF_UNIX/PF_LOCAL protocol family
10540 11:37:27.056028 <6>[ 0.757393] RPC: Registered named UNIX socket transport module.
10541 11:37:27.062590 <6>[ 0.763549] RPC: Registered udp transport module.
10542 11:37:27.065824 <6>[ 0.768484] RPC: Registered tcp transport module.
10543 11:37:27.072342 <6>[ 0.773417] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 11:37:27.078700 <6>[ 0.780086] PCI: CLS 0 bytes, default 64
10545 11:37:27.082788 <6>[ 0.784416] Unpacking initramfs...
10546 11:37:27.098404 <6>[ 0.796325] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 11:37:27.108391 <6>[ 0.804970] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 11:37:27.111734 <6>[ 0.813809] kvm [1]: IPA Size Limit: 40 bits
10549 11:37:27.118483 <6>[ 0.818337] kvm [1]: GICv3: no GICV resource entry
10550 11:37:27.121829 <6>[ 0.823354] kvm [1]: disabling GICv2 emulation
10551 11:37:27.128130 <6>[ 0.828041] kvm [1]: GIC system register CPU interface enabled
10552 11:37:27.135167 <6>[ 0.835879] kvm [1]: vgic interrupt IRQ18
10553 11:37:27.137915 <6>[ 0.840259] kvm [1]: VHE mode initialized successfully
10554 11:37:27.145976 <5>[ 0.846622] Initialise system trusted keyrings
10555 11:37:27.152462 <6>[ 0.851437] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10556 11:37:27.160208 <6>[ 0.861359] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10557 11:37:27.167392 <5>[ 0.867749] NFS: Registering the id_resolver key type
10558 11:37:27.170752 <5>[ 0.873045] Key type id_resolver registered
10559 11:37:27.177148 <5>[ 0.877459] Key type id_legacy registered
10560 11:37:27.183375 <6>[ 0.881735] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10561 11:37:27.190049 <6>[ 0.888659] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10562 11:37:27.196747 <6>[ 0.896381] 9p: Installing v9fs 9p2000 file system support
10563 11:37:27.232881 <5>[ 0.934078] Key type asymmetric registered
10564 11:37:27.236185 <5>[ 0.938407] Asymmetric key parser 'x509' registered
10565 11:37:27.246990 <6>[ 0.943538] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10566 11:37:27.249437 <6>[ 0.951152] io scheduler mq-deadline registered
10567 11:37:27.253357 <6>[ 0.955936] io scheduler kyber registered
10568 11:37:27.271940 <6>[ 0.972889] EINJ: ACPI disabled.
10569 11:37:27.304754 <4>[ 0.999136] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 11:37:27.314406 <4>[ 1.009767] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 11:37:27.329157 <6>[ 1.030752] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10572 11:37:27.337582 <6>[ 1.038801] printk: console [ttyS0] disabled
10573 11:37:27.365751 <6>[ 1.063450] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10574 11:37:27.372981 <6>[ 1.072924] printk: console [ttyS0] enabled
10575 11:37:27.375887 <6>[ 1.072924] printk: console [ttyS0] enabled
10576 11:37:27.382544 <6>[ 1.081818] printk: bootconsole [mtk8250] disabled
10577 11:37:27.385828 <6>[ 1.081818] printk: bootconsole [mtk8250] disabled
10578 11:37:27.392516 <6>[ 1.093077] SuperH (H)SCI(F) driver initialized
10579 11:37:27.395318 <6>[ 1.098357] msm_serial: driver initialized
10580 11:37:27.409207 <6>[ 1.107353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10581 11:37:27.419450 <6>[ 1.115902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10582 11:37:27.426245 <6>[ 1.124444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10583 11:37:27.436228 <6>[ 1.133073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10584 11:37:27.443195 <6>[ 1.141781] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10585 11:37:27.453101 <6>[ 1.150496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10586 11:37:27.462824 <6>[ 1.159037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10587 11:37:27.469440 <6>[ 1.167861] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10588 11:37:27.479106 <6>[ 1.176408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10589 11:37:27.490822 <6>[ 1.191976] loop: module loaded
10590 11:37:27.497512 <6>[ 1.198024] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10591 11:37:27.520195 <4>[ 1.221392] mtk-pmic-keys: Failed to locate of_node [id: -1]
10592 11:37:27.526960 <6>[ 1.228239] megasas: 07.719.03.00-rc1
10593 11:37:27.536534 <6>[ 1.237853] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10594 11:37:27.550649 <6>[ 1.251196] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10595 11:37:27.567254 <6>[ 1.267972] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10596 11:37:27.624024 <6>[ 1.318603] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10597 11:37:28.821607 <6>[ 2.522891] Freeing initrd memory: 40236K
10598 11:37:28.833247 <6>[ 2.534714] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10599 11:37:28.844135 <6>[ 2.545660] tun: Universal TUN/TAP device driver, 1.6
10600 11:37:28.847802 <6>[ 2.551726] thunder_xcv, ver 1.0
10601 11:37:28.851158 <6>[ 2.555232] thunder_bgx, ver 1.0
10602 11:37:28.854454 <6>[ 2.558749] nicpf, ver 1.0
10603 11:37:28.865252 <6>[ 2.562766] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10604 11:37:28.868155 <6>[ 2.570243] hns3: Copyright (c) 2017 Huawei Corporation.
10605 11:37:28.871844 <6>[ 2.575833] hclge is initializing
10606 11:37:28.878141 <6>[ 2.579404] e1000: Intel(R) PRO/1000 Network Driver
10607 11:37:28.884726 <6>[ 2.584534] e1000: Copyright (c) 1999-2006 Intel Corporation.
10608 11:37:28.887779 <6>[ 2.590548] e1000e: Intel(R) PRO/1000 Network Driver
10609 11:37:28.894677 <6>[ 2.595763] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10610 11:37:28.901037 <6>[ 2.601950] igb: Intel(R) Gigabit Ethernet Network Driver
10611 11:37:28.907696 <6>[ 2.607600] igb: Copyright (c) 2007-2014 Intel Corporation.
10612 11:37:28.914524 <6>[ 2.613436] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10613 11:37:28.921721 <6>[ 2.619954] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10614 11:37:28.924367 <6>[ 2.626416] sky2: driver version 1.30
10615 11:37:28.930935 <6>[ 2.631346] usbcore: registered new device driver r8152-cfgselector
10616 11:37:28.937761 <6>[ 2.637884] usbcore: registered new interface driver r8152
10617 11:37:28.940914 <6>[ 2.643706] VFIO - User Level meta-driver version: 0.3
10618 11:37:28.950298 <6>[ 2.651934] usbcore: registered new interface driver usb-storage
10619 11:37:28.957439 <6>[ 2.658381] usbcore: registered new device driver onboard-usb-hub
10620 11:37:28.966238 <6>[ 2.667532] mt6397-rtc mt6359-rtc: registered as rtc0
10621 11:37:28.976585 <6>[ 2.672998] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:37:13 UTC (1721216233)
10622 11:37:28.979270 <6>[ 2.682563] i2c_dev: i2c /dev entries driver
10623 11:37:28.993377 <4>[ 2.694722] cpu cpu0: supply cpu not found, using dummy regulator
10624 11:37:28.999871 <4>[ 2.701149] cpu cpu1: supply cpu not found, using dummy regulator
10625 11:37:29.006673 <4>[ 2.707578] cpu cpu2: supply cpu not found, using dummy regulator
10626 11:37:29.013147 <4>[ 2.713982] cpu cpu3: supply cpu not found, using dummy regulator
10627 11:37:29.019969 <4>[ 2.720378] cpu cpu4: supply cpu not found, using dummy regulator
10628 11:37:29.026798 <4>[ 2.726777] cpu cpu5: supply cpu not found, using dummy regulator
10629 11:37:29.032726 <4>[ 2.733172] cpu cpu6: supply cpu not found, using dummy regulator
10630 11:37:29.039394 <4>[ 2.739587] cpu cpu7: supply cpu not found, using dummy regulator
10631 11:37:29.060298 <6>[ 2.761228] cpu cpu0: EM: created perf domain
10632 11:37:29.063488 <6>[ 2.766143] cpu cpu4: EM: created perf domain
10633 11:37:29.070707 <6>[ 2.771743] sdhci: Secure Digital Host Controller Interface driver
10634 11:37:29.077128 <6>[ 2.778176] sdhci: Copyright(c) Pierre Ossman
10635 11:37:29.083344 <6>[ 2.783137] Synopsys Designware Multimedia Card Interface Driver
10636 11:37:29.090252 <6>[ 2.789775] sdhci-pltfm: SDHCI platform and OF driver helper
10637 11:37:29.093949 <6>[ 2.789829] mmc0: CQHCI version 5.10
10638 11:37:29.100545 <6>[ 2.799834] ledtrig-cpu: registered to indicate activity on CPUs
10639 11:37:29.106784 <6>[ 2.806815] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10640 11:37:29.113278 <6>[ 2.813868] usbcore: registered new interface driver usbhid
10641 11:37:29.116454 <6>[ 2.819690] usbhid: USB HID core driver
10642 11:37:29.124225 <6>[ 2.823901] spi_master spi0: will run message pump with realtime priority
10643 11:37:29.171282 <6>[ 2.865968] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10644 11:37:29.190480 <6>[ 2.881353] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10645 11:37:29.193722 <6>[ 2.894107] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10646 11:37:29.200266 <6>[ 2.896241] cros-ec-spi spi0.0: Chrome EC device registered
10647 11:37:29.203920 <6>[ 2.906758] mmc0: Command Queue Engine enabled
10648 11:37:29.210778 <6>[ 2.911478] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10649 11:37:29.217557 <6>[ 2.918985] mmcblk0: mmc0:0001 DA4128 116 GiB
10650 11:37:29.227705 <6>[ 2.920096] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10651 11:37:29.234211 <6>[ 2.927715] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10652 11:37:29.237532 <6>[ 2.934004] NET: Registered PF_PACKET protocol family
10653 11:37:29.244050 <6>[ 2.939966] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10654 11:37:29.247228 <6>[ 2.944302] 9pnet: Installing 9P2000 support
10655 11:37:29.254395 <6>[ 2.950169] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10656 11:37:29.257520 <5>[ 2.953987] Key type dns_resolver registered
10657 11:37:29.264131 <6>[ 2.959915] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10658 11:37:29.267444 <6>[ 2.964317] registered taskstats version 1
10659 11:37:29.274033 <5>[ 2.974613] Loading compiled-in X.509 certificates
10660 11:37:29.301581 <4>[ 2.996085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 11:37:29.311171 <4>[ 3.006807] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 11:37:29.326366 <6>[ 3.027238] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10663 11:37:29.332775 <6>[ 3.034051] xhci-mtk 11200000.usb: xHCI Host Controller
10664 11:37:29.339049 <6>[ 3.039551] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10665 11:37:29.349506 <6>[ 3.047413] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10666 11:37:29.356014 <6>[ 3.056844] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10667 11:37:29.362441 <6>[ 3.063041] xhci-mtk 11200000.usb: xHCI Host Controller
10668 11:37:29.369134 <6>[ 3.068532] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10669 11:37:29.375797 <6>[ 3.076185] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10670 11:37:29.382635 <6>[ 3.084100] hub 1-0:1.0: USB hub found
10671 11:37:29.386028 <6>[ 3.088117] hub 1-0:1.0: 1 port detected
10672 11:37:29.392634 <6>[ 3.092404] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10673 11:37:29.399876 <6>[ 3.101215] hub 2-0:1.0: USB hub found
10674 11:37:29.402945 <6>[ 3.105235] hub 2-0:1.0: 1 port detected
10675 11:37:29.412396 <6>[ 3.113551] mtk-msdc 11f70000.mmc: Got CD GPIO
10676 11:37:29.425880 <6>[ 3.123647] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10677 11:37:29.435473 <6>[ 3.132026] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10678 11:37:29.442095 <6>[ 3.140367] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10679 11:37:29.452059 <6>[ 3.148713] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10680 11:37:29.459049 <6>[ 3.157053] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10681 11:37:29.469226 <6>[ 3.165393] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10682 11:37:29.475504 <6>[ 3.173733] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10683 11:37:29.485385 <6>[ 3.182072] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10684 11:37:29.491913 <6>[ 3.190410] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10685 11:37:29.501737 <6>[ 3.198748] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10686 11:37:29.508486 <6>[ 3.207087] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10687 11:37:29.518857 <6>[ 3.215435] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10688 11:37:29.525129 <6>[ 3.223774] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10689 11:37:29.535037 <6>[ 3.232112] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10690 11:37:29.542539 <6>[ 3.240451] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10691 11:37:29.548587 <6>[ 3.249154] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10692 11:37:29.555259 <6>[ 3.256150] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10693 11:37:29.562221 <6>[ 3.262905] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10694 11:37:29.571936 <6>[ 3.269700] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10695 11:37:29.578586 <6>[ 3.276633] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10696 11:37:29.584903 <6>[ 3.283502] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10697 11:37:29.594549 <6>[ 3.292639] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10698 11:37:29.605092 <6>[ 3.301761] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10699 11:37:29.614188 <6>[ 3.311055] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10700 11:37:29.623968 <6>[ 3.320528] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10701 11:37:29.634087 <6>[ 3.329996] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10702 11:37:29.641065 <6>[ 3.339116] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10703 11:37:29.650809 <6>[ 3.348586] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10704 11:37:29.660932 <6>[ 3.357706] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10705 11:37:29.670608 <6>[ 3.367002] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10706 11:37:29.680355 <6>[ 3.377162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10707 11:37:29.690999 <6>[ 3.388684] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10708 11:37:29.817735 <6>[ 3.516095] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10709 11:37:29.972522 <6>[ 3.674018] hub 1-1:1.0: USB hub found
10710 11:37:29.975967 <6>[ 3.678545] hub 1-1:1.0: 4 ports detected
10711 11:37:29.985867 <6>[ 3.687689] hub 1-1:1.0: USB hub found
10712 11:37:29.989489 <6>[ 3.692028] hub 1-1:1.0: 4 ports detected
10713 11:37:30.098330 <6>[ 3.796440] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10714 11:37:30.125185 <6>[ 3.826066] hub 2-1:1.0: USB hub found
10715 11:37:30.127827 <6>[ 3.830574] hub 2-1:1.0: 3 ports detected
10716 11:37:30.139567 <6>[ 3.840994] hub 2-1:1.0: USB hub found
10717 11:37:30.142905 <6>[ 3.845423] hub 2-1:1.0: 3 ports detected
10718 11:37:30.309781 <6>[ 4.008128] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10719 11:37:30.441643 <6>[ 4.143505] hub 1-1.4:1.0: USB hub found
10720 11:37:30.444998 <6>[ 4.148104] hub 1-1.4:1.0: 2 ports detected
10721 11:37:30.460010 <6>[ 4.161234] hub 1-1.4:1.0: USB hub found
10722 11:37:30.462491 <6>[ 4.165832] hub 1-1.4:1.0: 2 ports detected
10723 11:37:30.521741 <6>[ 4.220346] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10724 11:37:30.630612 <6>[ 4.328749] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 11:37:30.666359 <4>[ 4.364800] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10726 11:37:30.676525 <4>[ 4.373917] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10727 11:37:30.716326 <6>[ 4.417648] r8152 2-1.3:1.0 eth0: v1.12.13
10728 11:37:30.761621 <6>[ 4.460100] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10729 11:37:30.957585 <6>[ 4.656033] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10730 11:37:32.330919 <6>[ 6.032401] r8152 2-1.3:1.0 eth0: carrier on
10731 11:37:35.181467 <5>[ 6.059889] Sending DHCP requests .., OK
10732 11:37:35.188456 <6>[ 8.888246] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10733 11:37:35.191564 <6>[ 8.896540] IP-Config: Complete:
10734 11:37:35.205446 <6>[ 8.900037] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10735 11:37:35.211897 <6>[ 8.910755] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10736 11:37:35.218043 <6>[ 8.919406] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10737 11:37:35.224978 <6>[ 8.919416] nameserver0=192.168.201.1
10738 11:37:35.228224 <6>[ 8.931552] clk: Disabling unused clocks
10739 11:37:35.231952 <6>[ 8.937274] ALSA device list:
10740 11:37:35.238882 <6>[ 8.940513] No soundcards found.
10741 11:37:35.245860 <6>[ 8.948073] Freeing unused kernel memory: 8512K
10742 11:37:35.248944 <6>[ 8.953007] Run /init as init process
10743 11:37:35.279560 <6>[ 8.981827] NET: Registered PF_INET6 protocol family
10744 11:37:35.286909 <6>[ 8.988453] Segment Routing with IPv6
10745 11:37:35.289321 <6>[ 8.992406] In-situ OAM (IOAM) with IPv6
10746 11:37:35.331164 <30>[ 9.006771] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10747 11:37:35.338170 <30>[ 9.039822] systemd[1]: Detected architecture arm64.
10748 11:37:35.338681
10749 11:37:35.345015 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10750 11:37:35.345526
10751 11:37:35.357866 <30>[ 9.060173] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10752 11:37:35.510711 <30>[ 9.209433] systemd[1]: Queued start job for default target graphical.target.
10753 11:37:35.559008 <30>[ 9.257668] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10754 11:37:35.565891 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10755 11:37:35.586087 <30>[ 9.284568] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10756 11:37:35.592282 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10757 11:37:35.615220 <30>[ 9.313579] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10758 11:37:35.625086 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10759 11:37:35.642233 <30>[ 9.340763] systemd[1]: Created slice user.slice - User and Session Slice.
10760 11:37:35.648787 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10761 11:37:35.668763 <30>[ 9.364266] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10762 11:37:35.675582 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10763 11:37:35.696929 <30>[ 9.392329] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10764 11:37:35.703568 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10765 11:37:35.732167 <30>[ 9.420698] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10766 11:37:35.742167 <30>[ 9.440622] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10767 11:37:35.748046 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10768 11:37:35.765625 <30>[ 9.464515] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10769 11:37:35.772297 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10770 11:37:35.793871 <30>[ 9.492600] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10771 11:37:35.803841 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10772 11:37:35.818630 <30>[ 9.520714] systemd[1]: Reached target paths.target - Path Units.
10773 11:37:35.829074 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10774 11:37:35.850304 <30>[ 9.548295] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10775 11:37:35.856082 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10776 11:37:35.870267 <30>[ 9.572116] systemd[1]: Reached target slices.target - Slice Units.
10777 11:37:35.880224 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10778 11:37:35.894804 <30>[ 9.596567] systemd[1]: Reached target swap.target - Swaps.
10779 11:37:35.900985 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10780 11:37:35.921447 <30>[ 9.620651] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10781 11:37:35.931603 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10782 11:37:35.950272 <30>[ 9.648926] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10783 11:37:35.959772 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10784 11:37:35.979841 <30>[ 9.678202] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10785 11:37:35.989478 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10786 11:37:36.006388 <30>[ 9.704779] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10787 11:37:36.015789 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10788 11:37:36.033958 <30>[ 9.732729] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10789 11:37:36.040952 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10790 11:37:36.058121 <30>[ 9.756802] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10791 11:37:36.068023 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10792 11:37:36.087345 <30>[ 9.785591] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10793 11:37:36.096502 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10794 11:37:36.114923 <30>[ 9.813265] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10795 11:37:36.124485 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10796 11:37:36.174097 <30>[ 9.872284] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10797 11:37:36.180110 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10798 11:37:36.200722 <30>[ 9.899199] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10799 11:37:36.207126 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10800 11:37:36.227592 <30>[ 9.926204] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10801 11:37:36.234106 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10802 11:37:36.260575 <30>[ 9.952389] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10803 11:37:36.272411 <30>[ 9.970702] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10804 11:37:36.281902 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10805 11:37:36.301326 <30>[ 10.000202] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10806 11:37:36.308301 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10807 11:37:36.334170 <30>[ 10.033333] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10808 11:37:36.347683 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.047419] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10809 11:37:36.350766 Module dm_mod...
10810 11:37:36.374856 <30>[ 10.073428] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10811 11:37:36.381302 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10812 11:37:36.406773 <30>[ 10.105373] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10813 11:37:36.413331 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10814 11:37:36.438421 <30>[ 10.137163] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10815 11:37:36.445108 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10816 11:37:36.501870 <30>[ 10.200819] systemd[1]: Starting systemd-journald.service - Journal Service...
10817 11:37:36.509170 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10818 11:37:36.532549 <30>[ 10.231400] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10819 11:37:36.539190 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10820 11:37:36.563604 <30>[ 10.259095] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10821 11:37:36.569851 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10822 11:37:36.594361 <30>[ 10.293182] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10823 11:37:36.604238 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10824 11:37:36.624892 <30>[ 10.323870] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10825 11:37:36.631764 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10826 11:37:36.657920 <30>[ 10.356180] systemd[1]: Started systemd-journald.service - Journal Service.
10827 11:37:36.664354 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10828 11:37:36.683839 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10829 11:37:36.702044 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10830 11:37:36.721943 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10831 11:37:36.743302 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10832 11:37:36.763468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10833 11:37:36.784560 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10834 11:37:36.804627 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10835 11:37:36.824594 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10836 11:37:36.844673 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10837 11:37:36.863568 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10838 11:37:36.887911 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10839 11:37:36.911982 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10840 11:37:36.930393 See 'systemctl status systemd-remount-fs.service' for details.
10841 11:37:36.955365 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10842 11:37:36.980492 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10843 11:37:37.029961 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10844 11:37:37.048903 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10845 11:37:37.060046 <46>[ 10.758726] systemd-journald[182]: Received client request to flush runtime journal.
10846 11:37:37.075487 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10847 11:37:37.103411 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10848 11:37:37.126861 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10849 11:37:37.155669 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10850 11:37:37.175333 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10851 11:37:37.195117 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10852 11:37:37.218494 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10853 11:37:37.238542 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10854 11:37:37.274039 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10855 11:37:37.295665 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10856 11:37:37.317869 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10857 11:37:37.336998 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10858 11:37:37.373805 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10859 11:37:37.402971 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10860 11:37:37.428323 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10861 11:37:37.462243 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10862 11:37:37.490899 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10863 11:37:37.503942 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10864 11:37:37.531906 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10865 11:37:37.555073 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10866 11:37:37.616987 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10867 11:37:37.711769 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10868 11:37:37.729915 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10869 11:37:37.750307 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10870 11:37:37.771220 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10871 11:37:37.790572 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10872 11:37:37.806050 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10873 11:37:37.830057 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10874 11:37:37.840500 <6>[ 11.539430] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10875 11:37:37.846984 <6>[ 11.540124] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10876 11:37:37.856824 <6>[ 11.555199] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10877 11:37:37.863651 <6>[ 11.560789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10878 11:37:37.873339 <6>[ 11.563921] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10879 11:37:37.880472 <6>[ 11.572058] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10880 11:37:37.890196 <4>[ 11.588967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10881 11:37:37.899959 <6>[ 11.598843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10882 11:37:37.907012 <6>[ 11.607059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10883 11:37:37.916679 <3>[ 11.608160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 11:37:37.922870 <3>[ 11.623734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 11:37:37.933315 <3>[ 11.632530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 11:37:37.939838 <6>[ 11.632839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10887 11:37:37.950069 <6>[ 11.648582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10888 11:37:37.956851 <6>[ 11.656491] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10889 11:37:37.963260 <6>[ 11.657280] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10890 11:37:37.973003 <6>[ 11.664324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10891 11:37:37.983421 <3>[ 11.681411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 11:37:37.989891 <3>[ 11.689556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 11:37:37.999428 <3>[ 11.697728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 11:37:38.006390 <6>[ 11.701311] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10895 11:37:38.012668 <3>[ 11.705839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 11:37:38.023145 <3>[ 11.721589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 11:37:38.026194 <6>[ 11.728626] remoteproc remoteproc0: scp is available
10898 11:37:38.032814 <6>[ 11.730336] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10899 11:37:38.039843 <6>[ 11.734990] remoteproc remoteproc0: powering up scp
10900 11:37:38.047089 <4>[ 11.738811] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10901 11:37:38.053600 <4>[ 11.738811] Fallback method does not support PEC.
10902 11:37:38.060430 <6>[ 11.741895] pci_bus 0000:00: root bus resource [bus 00-ff]
10903 11:37:38.067501 <6>[ 11.746950] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10904 11:37:38.077346 <3>[ 11.755513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 11:37:38.084066 <6>[ 11.760671] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10906 11:37:38.087933 <6>[ 11.767991] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10907 11:37:38.097166 <6>[ 11.775175] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10908 11:37:38.107160 <3>[ 11.785039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 11:37:38.114112 <6>[ 11.790932] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10910 11:37:38.120411 <3>[ 11.804706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 11:37:38.130699 <6>[ 11.815350] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10912 11:37:38.137015 <3>[ 11.821612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 11:37:38.143605 <6>[ 11.829526] pci 0000:00:00.0: supports D1 D2
10914 11:37:38.150305 <3>[ 11.836953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 11:37:38.157122 <6>[ 11.845019] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10916 11:37:38.167139 <6>[ 11.847071] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10917 11:37:38.173425 <3>[ 11.849552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 11:37:38.180706 <3>[ 11.849661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 11:37:38.187128 <6>[ 11.856726] mc: Linux media interface: v0.10
10920 11:37:38.193581 <3>[ 11.893827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 11:37:38.203689 <3>[ 11.901951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 11:37:38.210456 <6>[ 11.909733] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10923 11:37:38.216644 <6>[ 11.909757] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10924 11:37:38.223147 <6>[ 11.909770] remoteproc remoteproc0: remote processor scp is now up
10925 11:37:38.233313 <3>[ 11.910033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 11:37:38.239559 <6>[ 11.924448] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10927 11:37:38.249855 Startin<3>[ 11.925580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 11:37:38.256823 <6>[ 11.932044] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10929 11:37:38.266351 g [0;1;39msyste<3>[ 11.956100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 11:37:38.272996 <6>[ 11.963283] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10931 11:37:38.283009 md-networkd.…i<4>[ 11.978102] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10932 11:37:38.289976 <6>[ 11.980402] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10933 11:37:38.296643 ce[0m - Network<6>[ 11.996902] pci 0000:01:00.0: supports D1 D2
10934 11:37:38.303061 <4>[ 12.002273] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10935 11:37:38.309650 <6>[ 12.002536] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10936 11:37:38.316268 Configuration..<6>[ 12.017637] videodev: Linux video capture interface: v2.00
10937 11:37:38.316738 .
10938 11:37:38.333152 <6>[ 12.032112] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10939 11:37:38.340115 <6>[ 12.039411] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10940 11:37:38.349757 <6>[ 12.041101] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10941 11:37:38.359568 <6>[ 12.047626] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10942 11:37:38.367129 <6>[ 12.047673] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10943 11:37:38.373894 <6>[ 12.047713] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10944 11:37:38.384238 <6>[ 12.047728] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10945 11:37:38.387828 <6>[ 12.047741] pci 0000:00:00.0: PCI bridge to [bus 01]
10946 11:37:38.394241 <6>[ 12.047753] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10947 11:37:38.401003 <6>[ 12.052817] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10948 11:37:38.410581 <6>[ 12.066386] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10949 11:37:38.421072 <6>[ 12.067669] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10950 11:37:38.427532 <5>[ 12.067748] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10951 11:37:38.437524 <6>[ 12.070003] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10952 11:37:38.441023 <6>[ 12.074892] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10953 11:37:38.450948 <3>[ 12.074928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:37:38.458172 <5>[ 12.081519] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10955 11:37:38.464129 <5>[ 12.081753] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10956 11:37:38.474374 <4>[ 12.081815] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10957 11:37:38.481027 <6>[ 12.081820] cfg80211: failed to load regulatory.db
10958 11:37:38.487695 <3>[ 12.094479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:37:38.494216 <6>[ 12.095762] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10960 11:37:38.504396 <6>[ 12.120897] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10961 11:37:38.511188 <3>[ 12.158259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:37:38.521728 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10963 11:37:38.617785 <6>[ 12.320259] Bluetooth: Core ver 2.22
10964 11:37:38.627996 Starting [0;1;39mdbus.service[0m - D-<6>[ 12.328332] NET: Registered PF_BLUETOOTH protocol family
10965 11:37:38.634834 Bus System Messa<6>[ 12.335046] Bluetooth: HCI device and connection manager initialized
10966 11:37:38.635418 ge Bus...
10967 11:37:38.641327 <6>[ 12.343054] Bluetooth: HCI socket layer initialized
10968 11:37:38.648019 <6>[ 12.349248] Bluetooth: L2CAP socket layer initialized
10969 11:37:38.651211 <6>[ 12.354746] Bluetooth: SCO socket layer initialized
10970 11:37:38.665608 <6>[ 12.364542] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10971 11:37:38.679088 <6>[ 12.375317] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10972 11:37:38.699168 <3>[ 12.398189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 11:37:38.705533 <6>[ 12.398457] usbcore: registered new interface driver uvcvideo
10974 11:37:38.716128 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10975 11:37:38.733166 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10976 11:37:38.751206 <6>[ 12.450284] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10977 11:37:38.757612 <6>[ 12.457980] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10978 11:37:38.764529 <6>[ 12.459329] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10979 11:37:38.778087 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus<6>[ 12.477398] usbcore: registered new interface driver btusb
10980 11:37:38.778607 .
10981 11:37:38.788317 <4>[ 12.478811] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10982 11:37:38.794199 <6>[ 12.483948] mt7921e 0000:01:00.0: ASIC revision: 79610010
10983 11:37:38.797887 <3>[ 12.494793] Bluetooth: hci0: Failed to load firmware file (-2)
10984 11:37:38.804700 <3>[ 12.494800] Bluetooth: hci0: Failed to set up firmware (-2)
10985 11:37:38.814367 <4>[ 12.494806] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10986 11:37:38.827208 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10987 11:37:38.846593 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10988 11:37:38.859575 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10989 11:37:38.879744 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10990 11:37:38.919520 <6>[ 12.618754] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10991 11:37:38.922864 <6>[ 12.618754]
10992 11:37:38.933710 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10993 11:37:38.956499 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10994 11:37:38.967465 <3>[ 12.666910] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 11:37:38.980368 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10996 11:37:39.006957 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice<3>[ 12.704234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 11:37:39.010551 [0m - Permit User Sessions.
10998 11:37:39.031099 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10999 11:37:39.042478 <3>[ 12.741783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:37:39.077556 <3>[ 12.776787] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 11:37:39.089930 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11002 11:37:39.140039 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11003 11:37:39.160173 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11004 11:37:39.175381 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11005 11:37:39.190696 <6>[ 12.888968] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11006 11:37:39.200259 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11007 11:37:39.246429 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11008 11:37:39.270863 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11009 11:37:39.292381 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11010 11:37:39.327000 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11011 11:37:39.366170
11012 11:37:39.370067 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11013 11:37:39.370574
11014 11:37:39.372382 debian-bookworm-arm64 login: root (automatic login)
11015 11:37:39.372810
11016 11:37:39.388764 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11017 11:37:39.389272
11018 11:37:39.395519 The programs included with the Debian GNU/Linux system are free software;
11019 11:37:39.401839 the exact distribution terms for each program are described in the
11020 11:37:39.405406 individual files in /usr/share/doc/*/copyright.
11021 11:37:39.405912
11022 11:37:39.412043 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11023 11:37:39.414885 permitted by applicable law.
11024 11:37:39.416227 Matched prompt #10: / #
11026 11:37:39.417234 Setting prompt string to ['/ #']
11027 11:37:39.417703 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11029 11:37:39.418718 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11030 11:37:39.419171 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11031 11:37:39.419502 Setting prompt string to ['/ #']
11032 11:37:39.419864 Forcing a shell prompt, looking for ['/ #']
11033 11:37:39.420169 Sending line: ''
11035 11:37:39.471331 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 11:37:39.471745 Waiting using forced prompt support (timeout 00:02:30)
11037 11:37:39.477757 / #
11038 11:37:39.478683 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11039 11:37:39.479199 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11040 11:37:39.479663 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11041 11:37:39.480100 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11042 11:37:39.480560 end: 2 depthcharge-action (duration 00:01:30) [common]
11043 11:37:39.481007 start: 3 lava-test-retry (timeout 00:08:09) [common]
11044 11:37:39.481450 start: 3.1 lava-test-shell (timeout 00:08:09) [common]
11045 11:37:39.481809 Using namespace: common
11046 11:37:39.482189 Sending line: '#'
11048 11:37:39.583514 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11049 11:37:39.589530 / # #
11050 11:37:39.590187 Using /lava-14864641
11051 11:37:39.590514 Sending line: 'export SHELL=/bin/sh'
11053 11:37:39.698646 / # export SHELL=/bin/sh
11054 11:37:39.699384 Sending line: '. /lava-14864641/environment'
11056 11:37:39.807033 / # . /lava-14864641/environment
11057 11:37:39.807847 Sending line: '/lava-14864641/bin/lava-test-runner /lava-14864641/0'
11059 11:37:39.909360 Test shell timeout: 10s (minimum of the action and connection timeout)
11060 11:37:39.915269 / # /lava-14864641/bin/lava-test-runner /lava-14864641/0
11061 11:37:39.939508 + export TESTRUN_ID=0_v4l2-compliance-uvc
11062 11:37:39.943521 + cd /lava-14864641/0/tests/0_v4l2-compliance-uvc
11063 11:37:39.944043 + cat uuid
11064 11:37:39.946250 + UUID=14864641_1.5.2.3.1
11065 11:37:39.946684 + set +x
11066 11:37:39.953226 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14864641_1.5.2.3.1>
11067 11:37:39.954154 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14864641_1.5.2.3.1
11068 11:37:39.954568 Starting test lava.0_v4l2-compliance-uvc (14864641_1.5.2.3.1)
11069 11:37:39.954987 Skipping test definition patterns.
11070 11:37:39.956092 + /usr/bin/v4l2-parser.sh -d uvcvideo
11071 11:37:39.963018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11072 11:37:39.963529 device: /dev/video0
11073 11:37:39.964110 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11075 11:37:40.047840 <6>[ 13.749989] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11076 11:37:46.523713 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11077 11:37:46.536326 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11078 11:37:46.545460
11079 11:37:46.562949 Compliance test for uvcvideo device /dev/video0:
11080 11:37:46.569347
11081 11:37:46.582523 Driver Info:
11082 11:37:46.593337 Driver name : uvcvideo
11083 11:37:46.611871 Card type : HD User Facing: HD User Facing
11084 11:37:46.621757 Bus info : usb-11200000.usb-1.4.1
11085 11:37:46.629017 Driver version : 6.1.96
11086 11:37:46.641098 Capabilities : 0x84a00001
11087 11:37:46.653852 Metadata Capture
11088 11:37:46.664873 Streaming
11089 11:37:46.674941 Extended Pix Format
11090 11:37:46.686670 Device Capabilities
11091 11:37:46.700644 Device Caps : 0x04200001
11092 11:37:46.714225 Streaming
11093 11:37:46.726853 Extended Pix Format
11094 11:37:46.737689 Media Driver Info:
11095 11:37:46.747344 Driver name : uvcvideo
11096 11:37:46.762159 Model : HD User Facing: HD User Facing
11097 11:37:46.772738 Serial : 200901010001
11098 11:37:46.788003 Bus info : usb-11200000.usb-1.4.1
11099 11:37:46.795239 Media version : 6.1.96
11100 11:37:46.811037 Hardware revision: 0x00009758 (38744)
11101 11:37:46.819570 Driver version : 6.1.96
11102 11:37:46.834324 Interface Info:
11103 11:37:46.848291 <LAVA_SIGNAL_TESTSET START Interface-Info>
11104 11:37:46.848811 ID : 0x03000002
11105 11:37:46.849400 Received signal: <TESTSET> START Interface-Info
11106 11:37:46.849762 Starting test_set Interface-Info
11107 11:37:46.858625 Type : V4L Video
11108 11:37:46.869139 Entity Info:
11109 11:37:46.876687 <LAVA_SIGNAL_TESTSET STOP>
11110 11:37:46.877427 Received signal: <TESTSET> STOP
11111 11:37:46.877772 Closing test_set Interface-Info
11112 11:37:46.886653 <LAVA_SIGNAL_TESTSET START Entity-Info>
11113 11:37:46.887151 ID : 0x00000001 (1)
11114 11:37:46.887736 Received signal: <TESTSET> START Entity-Info
11115 11:37:46.888086 Starting test_set Entity-Info
11116 11:37:46.903827 Name : HD User Facing: HD User Facing
11117 11:37:46.911603 Function : V4L2 I/O
11118 11:37:46.924319 Flags : default
11119 11:37:46.935865 Pad 0x01000007 : 0: Sink
11120 11:37:46.956496 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11121 11:37:46.957136
11122 11:37:46.968782 Required ioctls:
11123 11:37:46.976655 <LAVA_SIGNAL_TESTSET STOP>
11124 11:37:46.977274 Received signal: <TESTSET> STOP
11125 11:37:46.977582 Closing test_set Entity-Info
11126 11:37:46.985863 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11127 11:37:46.986705 Received signal: <TESTSET> START Required-ioctls
11128 11:37:46.987035 Starting test_set Required-ioctls
11129 11:37:46.989101 test MC information (see 'Media Driver Info' above): OK
11130 11:37:47.012727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11131 11:37:47.013472 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11133 11:37:47.016893 test VIDIOC_QUERYCAP: OK
11134 11:37:47.033244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11135 11:37:47.033967 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11137 11:37:47.036835 test invalid ioctls: OK
11138 11:37:47.059138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11139 11:37:47.059252
11140 11:37:47.059479 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11142 11:37:47.069411 Allow for multiple opens:
11143 11:37:47.076876 <LAVA_SIGNAL_TESTSET STOP>
11144 11:37:47.077131 Received signal: <TESTSET> STOP
11145 11:37:47.077195 Closing test_set Required-ioctls
11146 11:37:47.086444 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11147 11:37:47.086714 Received signal: <TESTSET> START Allow-for-multiple-opens
11148 11:37:47.086778 Starting test_set Allow-for-multiple-opens
11149 11:37:47.089747 test second /dev/video0 open: OK
11150 11:37:47.112456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11151 11:37:47.112767 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11153 11:37:47.115405 test VIDIOC_QUERYCAP: OK
11154 11:37:47.137666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11155 11:37:47.137942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11157 11:37:47.141461 test VIDIOC_G/S_PRIORITY: OK
11158 11:37:47.163190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11159 11:37:47.163476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11161 11:37:47.166096 test for unlimited opens: OK
11162 11:37:47.188926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11163 11:37:47.189039
11164 11:37:47.189264 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11166 11:37:47.199828 Debug ioctls:
11167 11:37:47.206818 <LAVA_SIGNAL_TESTSET STOP>
11168 11:37:47.207087 Received signal: <TESTSET> STOP
11169 11:37:47.207166 Closing test_set Allow-for-multiple-opens
11170 11:37:47.216193 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11171 11:37:47.216513 Received signal: <TESTSET> START Debug-ioctls
11172 11:37:47.216621 Starting test_set Debug-ioctls
11173 11:37:47.219393 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11174 11:37:47.243235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11175 11:37:47.243570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11177 11:37:47.249973 test VIDIOC_LOG_STATUS: OK (Not Supported)
11178 11:37:47.270118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11179 11:37:47.270268
11180 11:37:47.270532 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11182 11:37:47.284075 Input ioctls:
11183 11:37:47.292054 <LAVA_SIGNAL_TESTSET STOP>
11184 11:37:47.292443 Received signal: <TESTSET> STOP
11185 11:37:47.292578 Closing test_set Debug-ioctls
11186 11:37:47.301645 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11187 11:37:47.302069 Received signal: <TESTSET> START Input-ioctls
11188 11:37:47.302228 Starting test_set Input-ioctls
11189 11:37:47.305006 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11190 11:37:47.330172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11191 11:37:47.331036 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11193 11:37:47.333068 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11194 11:37:47.352750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11195 11:37:47.353657 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11197 11:37:47.359477 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11198 11:37:47.377281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11199 11:37:47.378058 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11201 11:37:47.380764 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11202 11:37:47.402871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11203 11:37:47.403618 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11205 11:37:47.406205 test VIDIOC_G/S/ENUMINPUT: OK
11206 11:37:47.432257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11207 11:37:47.433005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11209 11:37:47.435510 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11210 11:37:47.457166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11211 11:37:47.457891 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11213 11:37:47.460296 Inputs: 1 Audio Inputs: 0 Tuners: 0
11214 11:37:47.469304
11215 11:37:47.485191 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11216 11:37:47.505728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11217 11:37:47.506545 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11219 11:37:47.511990 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11220 11:37:47.534674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11221 11:37:47.535428 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11223 11:37:47.540969 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11224 11:37:47.564908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11225 11:37:47.565677 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11227 11:37:47.571250 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11228 11:37:47.590758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11229 11:37:47.591497 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11231 11:37:47.596976 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11232 11:37:47.614194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11233 11:37:47.614686
11234 11:37:47.615251 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11236 11:37:47.634470 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11237 11:37:47.662167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11238 11:37:47.662915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11240 11:37:47.668597 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11241 11:37:47.689989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11242 11:37:47.690764 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11244 11:37:47.693288 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11245 11:37:47.711293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11246 11:37:47.712041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11248 11:37:47.714705 test VIDIOC_G/S_EDID: OK (Not Supported)
11249 11:37:47.735566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11250 11:37:47.736063
11251 11:37:47.736670 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11253 11:37:47.747379 Control ioctls (Input 0):
11254 11:37:47.755061 <LAVA_SIGNAL_TESTSET STOP>
11255 11:37:47.755805 Received signal: <TESTSET> STOP
11256 11:37:47.756147 Closing test_set Input-ioctls
11257 11:37:47.765713 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11258 11:37:47.766583 Received signal: <TESTSET> START Control-ioctls-Input-0
11259 11:37:47.766984 Starting test_set Control-ioctls-Input-0
11260 11:37:47.768318 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11261 11:37:47.798126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11262 11:37:47.798636 test VIDIOC_QUERYCTRL: OK
11263 11:37:47.799215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11265 11:37:47.819956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11266 11:37:47.820702 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11268 11:37:47.822871 test VIDIOC_G/S_CTRL: OK
11269 11:37:47.846894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11270 11:37:47.847636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11272 11:37:47.850116 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11273 11:37:47.871722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11274 11:37:47.872461 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11276 11:37:47.878588 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11277 11:37:47.899621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11278 11:37:47.900383 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11280 11:37:47.902834 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11281 11:37:47.922530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11282 11:37:47.923269 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11284 11:37:47.925722 Standard Controls: 16 Private Controls: 0
11285 11:37:47.933043
11286 11:37:47.944713 Format ioctls (Input 0):
11287 11:37:47.950624 <LAVA_SIGNAL_TESTSET STOP>
11288 11:37:47.951366 Received signal: <TESTSET> STOP
11289 11:37:47.951705 Closing test_set Control-ioctls-Input-0
11290 11:37:47.960906 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11291 11:37:47.961646 Received signal: <TESTSET> START Format-ioctls-Input-0
11292 11:37:47.961997 Starting test_set Format-ioctls-Input-0
11293 11:37:47.964261 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11294 11:37:47.988637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11295 11:37:47.989429 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11297 11:37:47.991607 test VIDIOC_G/S_PARM: OK
11298 11:37:48.011282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11299 11:37:48.012121 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11301 11:37:48.014487 test VIDIOC_G_FBUF: OK (Not Supported)
11302 11:37:48.040488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11303 11:37:48.041198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11305 11:37:48.043891 test VIDIOC_G_FMT: OK
11306 11:37:48.064886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11307 11:37:48.065624 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11309 11:37:48.068071 test VIDIOC_TRY_FMT: OK
11310 11:37:48.090087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11311 11:37:48.090838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11313 11:37:48.097022 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11314 11:37:48.102209 test VIDIOC_S_FMT: OK
11315 11:37:48.126335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11316 11:37:48.127088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11318 11:37:48.129756 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11319 11:37:48.154986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11320 11:37:48.155737 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11322 11:37:48.157692 test Cropping: OK (Not Supported)
11323 11:37:48.180726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11324 11:37:48.181481 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11326 11:37:48.183967 test Composing: OK (Not Supported)
11327 11:37:48.206721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11328 11:37:48.207470 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11330 11:37:48.209567 test Scaling: OK (Not Supported)
11331 11:37:48.231330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11332 11:37:48.231827
11333 11:37:48.232413 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11335 11:37:48.242802 Codec ioctls (Input 0):
11336 11:37:48.249393 <LAVA_SIGNAL_TESTSET STOP>
11337 11:37:48.250133 Received signal: <TESTSET> STOP
11338 11:37:48.250491 Closing test_set Format-ioctls-Input-0
11339 11:37:48.259029 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11340 11:37:48.259785 Received signal: <TESTSET> START Codec-ioctls-Input-0
11341 11:37:48.260154 Starting test_set Codec-ioctls-Input-0
11342 11:37:48.262336 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11343 11:37:48.284308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11344 11:37:48.285092 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11346 11:37:48.290428 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11347 11:37:48.309746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11348 11:37:48.310512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11350 11:37:48.316189 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11351 11:37:48.338684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11352 11:37:48.339203
11353 11:37:48.339783 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11355 11:37:48.349896 Buffer ioctls (Input 0):
11356 11:37:48.356452 <LAVA_SIGNAL_TESTSET STOP>
11357 11:37:48.357203 Received signal: <TESTSET> STOP
11358 11:37:48.357547 Closing test_set Codec-ioctls-Input-0
11359 11:37:48.366263 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11360 11:37:48.367013 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11361 11:37:48.367367 Starting test_set Buffer-ioctls-Input-0
11362 11:37:48.369386 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11363 11:37:48.394528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11364 11:37:48.395275 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11366 11:37:48.398390 test CREATE_BUFS maximum buffers: OK
11367 11:37:48.416355 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11369 11:37:48.420204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11370 11:37:48.420710 test VIDIOC_EXPBUF: OK
11371 11:37:48.442833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11372 11:37:48.443595 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11374 11:37:48.446471 test Requests: OK (Not Supported)
11375 11:37:48.468101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11376 11:37:48.468613
11377 11:37:48.469201 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11379 11:37:48.483725 Test input 0:
11380 11:37:48.499188
11381 11:37:48.514384 Streaming ioctls:
11382 11:37:48.521635 <LAVA_SIGNAL_TESTSET STOP>
11383 11:37:48.522446 Received signal: <TESTSET> STOP
11384 11:37:48.522795 Closing test_set Buffer-ioctls-Input-0
11385 11:37:48.531237 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11386 11:37:48.531985 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11387 11:37:48.532340 Starting test_set Streaming-ioctls_Test-input-0
11388 11:37:48.534330 test read/write: OK (Not Supported)
11389 11:37:48.561561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11390 11:37:48.562403 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11392 11:37:48.564915 test blocking wait: OK
11393 11:37:48.586728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11394 11:37:48.587444 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11396 11:37:48.593348 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11397 11:37:48.598327 test MMAP (no poll): FAIL
11398 11:37:48.622052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11399 11:37:48.622418 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11401 11:37:48.628482 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11402 11:37:48.637487 test MMAP (select): FAIL
11403 11:37:48.661627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11404 11:37:48.661893 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11406 11:37:48.668092 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11407 11:37:48.673456 test MMAP (epoll): FAIL
11408 11:37:48.697139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11409 11:37:48.697230
11410 11:37:48.697454 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11412 11:37:48.711519
11413 11:37:48.894589
11414 11:37:48.902741 test USERPTR (no poll): OK
11415 11:37:48.928517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11416 11:37:48.928632
11417 11:37:48.928860 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11419 11:37:48.939796
11420 11:37:49.112910
11421 11:37:49.121700 test USERPTR (select): OK
11422 11:37:49.145112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11423 11:37:49.145398 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11425 11:37:49.151559 test DMABUF: Cannot test, specify --expbuf-device
11426 11:37:49.156571
11427 11:37:49.175994 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11428 11:37:49.179224 <LAVA_TEST_RUNNER EXIT>
11429 11:37:49.179476 ok: lava_test_shell seems to have completed
11430 11:37:49.179549 Marking unfinished test run as failed
11432 11:37:49.180560 device-presence: pass
MC-information-see-Media-Driver-Info-above:
set: Required-ioctls
result: pass
VIDIOC_QUERYCAP:
set: Allow-for-multiple-opens
result: pass
invalid-ioctls:
set: Required-ioctls
result: pass
second-/dev/video0-open:
set: Allow-for-multiple-opens
result: pass
VIDIOC_G/S_PRIORITY:
set: Allow-for-multiple-opens
result: pass
for-unlimited-opens:
set: Allow-for-multiple-opens
result: pass
VIDIOC_DBG_G/S_REGISTER:
set: Debug-ioctls
result: pass
VIDIOC_LOG_STATUS:
set: Debug-ioctls
result: pass
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
set: Input-ioctls
result: pass
VIDIOC_G/S_FREQUENCY:
set: Input-ioctls
result: pass
VIDIOC_S_HW_FREQ_SEEK:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMINPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDIO:
set: Input-ioctls
result: pass
VIDIOC_G/S_MODULATOR:
set: Input-ioctls
result: pass
VIDIOC_ENUMAUDOUT:
set: Input-ioctls
result: pass
VIDIOC_G/S/ENUMOUTPUT:
set: Input-ioctls
result: pass
VIDIOC_G/S_AUDOUT:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_STD:
set: Input-ioctls
result: pass
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
set: Input-ioctls
result: pass
VIDIOC_DV_TIMINGS_CAP:
set: Input-ioctls
result: pass
VIDIOC_G/S_EDID:
set: Input-ioctls
result: pass
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
set: Control-ioctls-Input-0
result: pass
VIDIOC_QUERYCTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_CTRL:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S/TRY_EXT_CTRLS:
set: Control-ioctls-Input-0
result: pass
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
set: Control-ioctls-Input-0
result: pass
VIDIOC_G/S_JPEGCOMP:
set: Control-ioctls-Input-0
result: pass
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G/S_PARM:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FBUF:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_S_FMT:
set: Format-ioctls-Input-0
result: pass
VIDIOC_G_SLICED_VBI_CAP:
set: Format-ioctls-Input-0
result: pass
Cropping:
set: Format-ioctls-Input-0
result: pass
Composing:
set: Format-ioctls-Input-0
result: pass
Scaling:
set: Format-ioctls-Input-0
result: pass
VIDIOC_TRY_ENCODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_G_ENC_INDEX:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_TRY_DECODER_CMD:
set: Codec-ioctls-Input-0
result: pass
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
set: Buffer-ioctls-Input-0
result: pass
CREATE_BUFS-maximum-buffers:
set: Buffer-ioctls-Input-0
result: pass
VIDIOC_EXPBUF:
set: Buffer-ioctls-Input-0
result: pass
Requests:
set: Buffer-ioctls-Input-0
result: pass
read/write:
set: Streaming-ioctls_Test-input-0
result: pass
blocking-wait:
set: Streaming-ioctls_Test-input-0
result: pass
MMAP-no-poll:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-select:
set: Streaming-ioctls_Test-input-0
result: fail
MMAP-epoll:
set: Streaming-ioctls_Test-input-0
result: fail
USERPTR-no-poll:
set: Streaming-ioctls_Test-input-0
result: pass
USERPTR-select:
set: Streaming-ioctls_Test-input-0
result: pass
11433 11:37:49.180697 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11434 11:37:49.180792 end: 3 lava-test-retry (duration 00:00:10) [common]
11435 11:37:49.180887 start: 4 finalize (timeout 00:07:59) [common]
11436 11:37:49.180980 start: 4.1 power-off (timeout 00:00:30) [common]
11437 11:37:49.181201 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11438 11:37:51.255352 >> Command sent successfully.
11439 11:37:51.258809 Returned 0 in 2 seconds
11440 11:37:51.258952 end: 4.1 power-off (duration 00:00:02) [common]
11442 11:37:51.259145 start: 4.2 read-feedback (timeout 00:07:57) [common]
11443 11:37:51.259279 Listened to connection for namespace 'common' for up to 1s
11444 11:37:52.260324 Finalising connection for namespace 'common'
11445 11:37:52.260453 Disconnecting from shell: Finalise
11446 11:37:52.260518 / #
11447 11:37:52.360790 end: 4.2 read-feedback (duration 00:00:01) [common]
11448 11:37:52.360931 end: 4 finalize (duration 00:00:03) [common]
11449 11:37:52.361036 Cleaning after the job
11450 11:37:52.361131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/ramdisk
11451 11:37:52.365148 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/kernel
11452 11:37:52.376781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/dtb
11453 11:37:52.376953 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864641/tftp-deploy-ttb4uouz/modules
11454 11:37:52.382598 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864641
11455 11:37:52.446778 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864641
11456 11:37:52.446934 Job finished correctly