Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:30:57.927660 lava-dispatcher, installed at version: 2024.05
2 11:30:57.927856 start: 0 validate
3 11:30:57.927962 Start time: 2024-07-17 11:30:57.927956+00:00 (UTC)
4 11:30:57.928098 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:30:57.928242 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 11:30:58.181312 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:30:58.182351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:30:58.446608 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:30:58.447424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:31:39.145412 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:31:39.146228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:31:39.667703 validate duration: 41.74
14 11:31:39.668900 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:31:39.669456 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:31:39.669911 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:31:39.670584 Not decompressing ramdisk as can be used compressed.
18 11:31:39.671041 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 11:31:39.671403 saving as /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/ramdisk/rootfs.cpio.gz
20 11:31:39.671779 total size: 8181887 (7 MB)
21 11:31:50.778513 progress 0 % (0 MB)
22 11:31:50.791714 progress 5 % (0 MB)
23 11:31:50.803179 progress 10 % (0 MB)
24 11:31:50.812039 progress 15 % (1 MB)
25 11:31:50.817701 progress 20 % (1 MB)
26 11:31:50.822722 progress 25 % (1 MB)
27 11:31:50.826500 progress 30 % (2 MB)
28 11:31:50.829976 progress 35 % (2 MB)
29 11:31:50.832980 progress 40 % (3 MB)
30 11:31:50.836125 progress 45 % (3 MB)
31 11:31:50.838848 progress 50 % (3 MB)
32 11:31:50.841734 progress 55 % (4 MB)
33 11:31:50.844008 progress 60 % (4 MB)
34 11:31:50.846434 progress 65 % (5 MB)
35 11:31:50.848679 progress 70 % (5 MB)
36 11:31:50.850956 progress 75 % (5 MB)
37 11:31:50.853205 progress 80 % (6 MB)
38 11:31:50.855814 progress 85 % (6 MB)
39 11:31:50.857805 progress 90 % (7 MB)
40 11:31:50.859995 progress 95 % (7 MB)
41 11:31:50.861965 progress 100 % (7 MB)
42 11:31:50.862158 7 MB downloaded in 11.19 s (0.70 MB/s)
43 11:31:50.862309 end: 1.1.1 http-download (duration 00:00:11) [common]
45 11:31:50.862531 end: 1.1 download-retry (duration 00:00:11) [common]
46 11:31:50.862609 start: 1.2 download-retry (timeout 00:09:49) [common]
47 11:31:50.862684 start: 1.2.1 http-download (timeout 00:09:49) [common]
48 11:31:50.862817 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:31:50.862879 saving as /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/kernel/Image
50 11:31:50.862932 total size: 54813184 (52 MB)
51 11:31:50.862985 No compression specified
52 11:31:51.122727 progress 0 % (0 MB)
53 11:31:51.172574 progress 5 % (2 MB)
54 11:31:51.190407 progress 10 % (5 MB)
55 11:31:51.205108 progress 15 % (7 MB)
56 11:31:51.219086 progress 20 % (10 MB)
57 11:31:51.233036 progress 25 % (13 MB)
58 11:31:51.246686 progress 30 % (15 MB)
59 11:31:51.260651 progress 35 % (18 MB)
60 11:31:51.274734 progress 40 % (20 MB)
61 11:31:51.288544 progress 45 % (23 MB)
62 11:31:51.302486 progress 50 % (26 MB)
63 11:31:51.316560 progress 55 % (28 MB)
64 11:31:51.330541 progress 60 % (31 MB)
65 11:31:51.344599 progress 65 % (34 MB)
66 11:31:51.358993 progress 70 % (36 MB)
67 11:31:51.373149 progress 75 % (39 MB)
68 11:31:51.387367 progress 80 % (41 MB)
69 11:31:51.401761 progress 85 % (44 MB)
70 11:31:51.415907 progress 90 % (47 MB)
71 11:31:51.429805 progress 95 % (49 MB)
72 11:31:51.443650 progress 100 % (52 MB)
73 11:31:51.443887 52 MB downloaded in 0.58 s (89.98 MB/s)
74 11:31:51.444040 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:31:51.444245 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:31:51.444325 start: 1.3 download-retry (timeout 00:09:48) [common]
78 11:31:51.444400 start: 1.3.1 http-download (timeout 00:09:48) [common]
79 11:31:51.444588 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:31:51.444654 saving as /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/dtb/mt8192-asurada-spherion-r0.dtb
81 11:31:51.444707 total size: 47258 (0 MB)
82 11:31:51.444760 No compression specified
83 11:31:51.703698 progress 69 % (0 MB)
84 11:31:51.704519 progress 100 % (0 MB)
85 11:31:51.704948 0 MB downloaded in 0.26 s (0.17 MB/s)
86 11:31:51.705294 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:31:51.705871 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:31:51.706093 start: 1.4 download-retry (timeout 00:09:48) [common]
90 11:31:51.706310 start: 1.4.1 http-download (timeout 00:09:48) [common]
91 11:31:51.706635 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:31:51.706811 saving as /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/modules/modules.tar
93 11:31:51.706966 total size: 8610184 (8 MB)
94 11:31:51.707122 Using unxz to decompress xz
95 11:31:51.711541 progress 0 % (0 MB)
96 11:31:51.750397 progress 5 % (0 MB)
97 11:31:51.774459 progress 10 % (0 MB)
98 11:31:51.797874 progress 15 % (1 MB)
99 11:31:51.821696 progress 20 % (1 MB)
100 11:31:51.844794 progress 25 % (2 MB)
101 11:31:51.868283 progress 30 % (2 MB)
102 11:31:51.891017 progress 35 % (2 MB)
103 11:31:51.917390 progress 40 % (3 MB)
104 11:31:51.942884 progress 45 % (3 MB)
105 11:31:51.967900 progress 50 % (4 MB)
106 11:31:51.992596 progress 55 % (4 MB)
107 11:31:52.016551 progress 60 % (4 MB)
108 11:31:52.039682 progress 65 % (5 MB)
109 11:31:52.065505 progress 70 % (5 MB)
110 11:31:52.092677 progress 75 % (6 MB)
111 11:31:52.119968 progress 80 % (6 MB)
112 11:31:52.143547 progress 85 % (7 MB)
113 11:31:52.166818 progress 90 % (7 MB)
114 11:31:52.189895 progress 95 % (7 MB)
115 11:31:52.212792 progress 100 % (8 MB)
116 11:31:52.218229 8 MB downloaded in 0.51 s (16.06 MB/s)
117 11:31:52.218401 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:31:52.218727 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:31:52.218822 start: 1.5 prepare-tftp-overlay (timeout 00:09:47) [common]
121 11:31:52.218912 start: 1.5.1 extract-nfsrootfs (timeout 00:09:47) [common]
122 11:31:52.218994 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:31:52.219079 start: 1.5.2 lava-overlay (timeout 00:09:47) [common]
124 11:31:52.219281 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40
125 11:31:52.219434 makedir: /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin
126 11:31:52.219591 makedir: /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/tests
127 11:31:52.219689 makedir: /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/results
128 11:31:52.219786 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-add-keys
129 11:31:52.219930 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-add-sources
130 11:31:52.220057 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-background-process-start
131 11:31:52.220188 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-background-process-stop
132 11:31:52.220327 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-common-functions
133 11:31:52.220477 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-echo-ipv4
134 11:31:52.220627 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-install-packages
135 11:31:52.220775 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-installed-packages
136 11:31:52.220921 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-os-build
137 11:31:52.221044 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-probe-channel
138 11:31:52.221168 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-probe-ip
139 11:31:52.221291 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-target-ip
140 11:31:52.221413 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-target-mac
141 11:31:52.221557 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-target-storage
142 11:31:52.221699 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-case
143 11:31:52.221881 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-event
144 11:31:52.222029 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-feedback
145 11:31:52.222176 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-raise
146 11:31:52.222323 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-reference
147 11:31:52.222472 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-runner
148 11:31:52.222624 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-set
149 11:31:52.222772 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-test-shell
150 11:31:52.222922 Updating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-install-packages (oe)
151 11:31:52.223097 Updating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/bin/lava-installed-packages (oe)
152 11:31:52.223242 Creating /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/environment
153 11:31:52.223367 LAVA metadata
154 11:31:52.223501 - LAVA_JOB_ID=14864571
155 11:31:52.223591 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:31:52.223724 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:47) [common]
157 11:31:52.223808 skipped lava-vland-overlay
158 11:31:52.223913 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:31:52.224018 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
160 11:31:52.224098 skipped lava-multinode-overlay
161 11:31:52.224200 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:31:52.224303 start: 1.5.2.3 test-definition (timeout 00:09:47) [common]
163 11:31:52.224407 Loading test definitions
164 11:31:52.224519 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:47) [common]
165 11:31:52.224606 Using /lava-14864571 at stage 0
166 11:31:52.225012 uuid=14864571_1.5.2.3.1 testdef=None
167 11:31:52.225123 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:31:52.225233 start: 1.5.2.3.2 test-overlay (timeout 00:09:47) [common]
169 11:31:52.225882 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:31:52.226212 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:47) [common]
172 11:31:52.226830 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:31:52.227058 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
175 11:31:52.227905 runner path: /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/0/tests/0_dmesg test_uuid 14864571_1.5.2.3.1
176 11:31:52.228083 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:31:52.228407 Creating lava-test-runner.conf files
179 11:31:52.228497 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864571/lava-overlay-t3zpet40/lava-14864571/0 for stage 0
180 11:31:52.228618 - 0_dmesg
181 11:31:52.228742 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:31:52.228852 start: 1.5.2.4 compress-overlay (timeout 00:09:47) [common]
183 11:31:52.235596 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:31:52.235709 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
185 11:31:52.235806 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:31:52.235897 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:31:52.235986 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
188 11:31:52.469884 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 11:31:52.470026 start: 1.5.4 extract-modules (timeout 00:09:47) [common]
190 11:31:52.470118 extracting modules file /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864571/extract-overlay-ramdisk-_6s_1uw0/ramdisk
191 11:31:52.684878 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:31:52.685023 start: 1.5.5 apply-overlay-tftp (timeout 00:09:47) [common]
193 11:31:52.685107 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864571/compress-overlay-92gb9udq/overlay-1.5.2.4.tar.gz to ramdisk
194 11:31:52.685166 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864571/compress-overlay-92gb9udq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864571/extract-overlay-ramdisk-_6s_1uw0/ramdisk
195 11:31:52.691494 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:31:52.691597 start: 1.5.6 configure-preseed-file (timeout 00:09:47) [common]
197 11:31:52.691674 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:31:52.691748 start: 1.5.7 compress-ramdisk (timeout 00:09:47) [common]
199 11:31:52.691843 Building ramdisk /var/lib/lava/dispatcher/tmp/14864571/extract-overlay-ramdisk-_6s_1uw0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864571/extract-overlay-ramdisk-_6s_1uw0/ramdisk
200 11:31:53.071490 >> 144748 blocks
201 11:31:55.452915 rename /var/lib/lava/dispatcher/tmp/14864571/extract-overlay-ramdisk-_6s_1uw0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/ramdisk/ramdisk.cpio.gz
202 11:31:55.453082 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 11:31:55.453168 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
204 11:31:55.453246 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
205 11:31:55.453321 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/kernel/Image']
206 11:32:10.332413 Returned 0 in 14 seconds
207 11:32:10.332609 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/kernel/image.itb
208 11:32:10.786197 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:32:10.786328 output: Created: Wed Jul 17 12:32:10 2024
210 11:32:10.786390 output: Image 0 (kernel-1)
211 11:32:10.786443 output: Description:
212 11:32:10.786494 output: Created: Wed Jul 17 12:32:10 2024
213 11:32:10.786542 output: Type: Kernel Image
214 11:32:10.786590 output: Compression: lzma compressed
215 11:32:10.786641 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:32:10.786689 output: Architecture: AArch64
217 11:32:10.786735 output: OS: Linux
218 11:32:10.786781 output: Load Address: 0x00000000
219 11:32:10.786827 output: Entry Point: 0x00000000
220 11:32:10.786875 output: Hash algo: crc32
221 11:32:10.786922 output: Hash value: 83448d17
222 11:32:10.786969 output: Image 1 (fdt-1)
223 11:32:10.787015 output: Description: mt8192-asurada-spherion-r0
224 11:32:10.787061 output: Created: Wed Jul 17 12:32:10 2024
225 11:32:10.787108 output: Type: Flat Device Tree
226 11:32:10.787155 output: Compression: uncompressed
227 11:32:10.787202 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:32:10.787249 output: Architecture: AArch64
229 11:32:10.787295 output: Hash algo: crc32
230 11:32:10.787341 output: Hash value: 0f8e4d2e
231 11:32:10.787387 output: Image 2 (ramdisk-1)
232 11:32:10.787457 output: Description: unavailable
233 11:32:10.787519 output: Created: Wed Jul 17 12:32:10 2024
234 11:32:10.787566 output: Type: RAMDisk Image
235 11:32:10.787612 output: Compression: uncompressed
236 11:32:10.787657 output: Data Size: 21363744 Bytes = 20863.03 KiB = 20.37 MiB
237 11:32:10.787703 output: Architecture: AArch64
238 11:32:10.787749 output: OS: Linux
239 11:32:10.787799 output: Load Address: unavailable
240 11:32:10.787872 output: Entry Point: unavailable
241 11:32:10.787921 output: Hash algo: crc32
242 11:32:10.787967 output: Hash value: 33720613
243 11:32:10.788013 output: Default Configuration: 'conf-1'
244 11:32:10.788060 output: Configuration 0 (conf-1)
245 11:32:10.788106 output: Description: mt8192-asurada-spherion-r0
246 11:32:10.788152 output: Kernel: kernel-1
247 11:32:10.788198 output: Init Ramdisk: ramdisk-1
248 11:32:10.788245 output: FDT: fdt-1
249 11:32:10.788291 output: Loadables: kernel-1
250 11:32:10.788336 output:
251 11:32:10.788437 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:32:10.788510 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:32:10.788582 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 11:32:10.788654 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
255 11:32:10.788711 No LXC device requested
256 11:32:10.788777 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:32:10.788848 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
258 11:32:10.788914 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:32:10.788968 Checking files for TFTP limit of 4294967296 bytes.
260 11:32:10.789324 end: 1 tftp-deploy (duration 00:00:31) [common]
261 11:32:10.789409 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:32:10.789485 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:32:10.789569 substitutions:
264 11:32:10.789627 - {DTB}: 14864571/tftp-deploy-y53ldle6/dtb/mt8192-asurada-spherion-r0.dtb
265 11:32:10.789681 - {INITRD}: 14864571/tftp-deploy-y53ldle6/ramdisk/ramdisk.cpio.gz
266 11:32:10.789732 - {KERNEL}: 14864571/tftp-deploy-y53ldle6/kernel/Image
267 11:32:10.789784 - {LAVA_MAC}: None
268 11:32:10.789837 - {PRESEED_CONFIG}: None
269 11:32:10.789884 - {PRESEED_LOCAL}: None
270 11:32:10.789932 - {RAMDISK}: 14864571/tftp-deploy-y53ldle6/ramdisk/ramdisk.cpio.gz
271 11:32:10.789984 - {ROOT_PART}: None
272 11:32:10.790031 - {ROOT}: None
273 11:32:10.790079 - {SERVER_IP}: 192.168.201.1
274 11:32:10.790126 - {TEE}: None
275 11:32:10.790173 Parsed boot commands:
276 11:32:10.790220 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:32:10.790358 Parsed boot commands: tftpboot 192.168.201.1 14864571/tftp-deploy-y53ldle6/kernel/image.itb 14864571/tftp-deploy-y53ldle6/kernel/cmdline
278 11:32:10.790435 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:32:10.790507 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:32:10.790578 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:32:10.790646 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:32:10.790698 Not connected, no need to disconnect.
283 11:32:10.790760 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:32:10.790827 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:32:10.790880 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 11:32:10.794048 Setting prompt string to ['lava-test: # ']
287 11:32:10.794365 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:32:10.794462 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:32:10.794569 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:32:10.794648 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:32:10.794821 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=reboot']
292 11:32:19.925634 >> Command sent successfully.
293 11:32:19.941796 Returned 0 in 9 seconds
294 11:32:19.942278 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:32:19.942925 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:32:19.943193 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:32:19.943406 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:32:19.943645 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:32:19.943834 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:32:19.944842 [Enter `^Ec?' for help]
302 11:32:21.576559
303 11:32:21.577082
304 11:32:21.577447 F0: 102B 0000
305 11:32:21.577799
306 11:32:21.578077 F3: 1001 0000 [0200]
307 11:32:21.579924
308 11:32:21.580307 F3: 1001 0000
309 11:32:21.580607
310 11:32:21.581024 F7: 102D 0000
311 11:32:21.581445
312 11:32:21.583711 F1: 0000 0000
313 11:32:21.584088
314 11:32:21.584378 V0: 0000 0000 [0001]
315 11:32:21.584752
316 11:32:21.585065 00: 0007 8000
317 11:32:21.587408
318 11:32:21.587814 01: 0000 0000
319 11:32:21.588122
320 11:32:21.588508 BP: 0C00 0209 [0000]
321 11:32:21.588797
322 11:32:21.590698 G0: 1182 0000
323 11:32:21.591071
324 11:32:21.591360 EC: 0000 0021 [4000]
325 11:32:21.591694
326 11:32:21.594236 S7: 0000 0000 [0000]
327 11:32:21.594612
328 11:32:21.594930 CC: 0000 0000 [0001]
329 11:32:21.595358
330 11:32:21.597572 T0: 0000 0040 [010F]
331 11:32:21.597951
332 11:32:21.598244 Jump to BL
333 11:32:21.598513
334 11:32:21.624111
335 11:32:21.624478
336 11:32:21.629998 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:32:21.633744 ARM64: Exception handlers installed.
338 11:32:21.637269 ARM64: Testing exception
339 11:32:21.640958 ARM64: Done test exception
340 11:32:21.648280 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:32:21.658062 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:32:21.665195 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:32:21.675262 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:32:21.681775 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:32:21.687989 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:32:21.700047 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:32:21.706543 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:32:21.726425 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:32:21.729454 WDT: Last reset was cold boot
350 11:32:21.733203 SPI1(PAD0) initialized at 2873684 Hz
351 11:32:21.735952 SPI5(PAD0) initialized at 992727 Hz
352 11:32:21.739575 VBOOT: Loading verstage.
353 11:32:21.745984 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:32:21.749300 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:32:21.753055 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:32:21.756050 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:32:21.763888 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:32:21.770288 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:32:21.781335 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:32:21.781734
361 11:32:21.782233
362 11:32:21.791406 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:32:21.794890 ARM64: Exception handlers installed.
364 11:32:21.797807 ARM64: Testing exception
365 11:32:21.801333 ARM64: Done test exception
366 11:32:21.804354 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:32:21.807537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:32:21.822380 Probing TPM: . done!
369 11:32:21.822860 TPM ready after 0 ms
370 11:32:21.828822 Connected to device vid:did:rid of 1ae0:0028:00
371 11:32:21.838876 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
372 11:32:21.875948 Initialized TPM device CR50 revision 0
373 11:32:21.888538 tlcl_send_startup: Startup return code is 0
374 11:32:21.888939 TPM: setup succeeded
375 11:32:21.900464 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:32:21.909306 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:32:21.916239 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:32:21.928046 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:32:21.931444 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:32:21.935304 in-header: 03 07 00 00 08 00 00 00
381 11:32:21.938436 in-data: aa e4 47 04 13 02 00 00
382 11:32:21.941579 Chrome EC: UHEPI supported
383 11:32:21.948581 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:32:21.951738 in-header: 03 a9 00 00 08 00 00 00
385 11:32:21.955292 in-data: 84 60 60 08 00 00 00 00
386 11:32:21.955720 Phase 1
387 11:32:21.961759 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:32:21.965454 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:32:21.972002 VB2:vb2_check_recovery() Recovery was requested manually
390 11:32:21.978286 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:32:21.978721 Recovery requested (1009000e)
392 11:32:21.987344 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:32:21.992836 tlcl_extend: response is 0
394 11:32:22.000660 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:32:22.006252 tlcl_extend: response is 0
396 11:32:22.012382 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:32:22.033086 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:32:22.040712 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:32:22.041145
400 11:32:22.041447
401 11:32:22.051012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:32:22.054293 ARM64: Exception handlers installed.
403 11:32:22.054674 ARM64: Testing exception
404 11:32:22.057930 ARM64: Done test exception
405 11:32:22.078253 pmic_efuse_setting: Set efuses in 11 msecs
406 11:32:22.081719 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:32:22.088471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:32:22.091923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:32:22.098328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:32:22.101547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:32:22.108291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:32:22.111556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:32:22.118610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:32:22.121826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:32:22.125168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:32:22.131642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:32:22.134941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:32:22.141268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:32:22.145053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:32:22.151533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:32:22.158247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:32:22.161463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:32:22.167964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:32:22.174744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:32:22.178138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:32:22.184887 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:32:22.191525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:32:22.194711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:32:22.201144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:32:22.208032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:32:22.211219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:32:22.217831 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:32:22.225196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:32:22.227913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:32:22.231268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:32:22.237808 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:32:22.241118 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:32:22.247977 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:32:22.250944 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:32:22.257944 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:32:22.261140 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:32:22.267968 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:32:22.274306 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:32:22.278084 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:32:22.281325 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:32:22.284441 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:32:22.291310 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:32:22.294630 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:32:22.301122 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:32:22.304676 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:32:22.307636 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:32:22.311271 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:32:22.317944 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:32:22.321171 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:32:22.324332 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:32:22.331002 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:32:22.334559 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:32:22.340938 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:32:22.350617 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:32:22.354245 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:32:22.364111 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:32:22.370507 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:32:22.377092 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:32:22.380253 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:32:22.383531 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:32:22.391376 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
467 11:32:22.397817 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:32:22.401391 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 11:32:22.407769 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:32:22.415930 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 11:32:22.425699 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 11:32:22.435003 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 11:32:22.444470 [RTC]rtc_get_frequency_meter,154: input=13, output=805
474 11:32:22.453881 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 11:32:22.463023 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 11:32:22.472968 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 11:32:22.476126 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 11:32:22.483537 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 11:32:22.486999 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:32:22.490180 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:32:22.496798 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:32:22.499921 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:32:22.503145 ADC[4]: Raw value=903400 ID=7
484 11:32:22.503578 ADC[3]: Raw value=213282 ID=1
485 11:32:22.506486 RAM Code: 0x71
486 11:32:22.509773 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:32:22.516752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:32:22.523225 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:32:22.529610 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:32:22.533896 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:32:22.536623 in-header: 03 07 00 00 08 00 00 00
492 11:32:22.540217 in-data: aa e4 47 04 13 02 00 00
493 11:32:22.543011 Chrome EC: UHEPI supported
494 11:32:22.549721 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:32:22.552954 in-header: 03 a9 00 00 08 00 00 00
496 11:32:22.556554 in-data: 84 60 60 08 00 00 00 00
497 11:32:22.559723 MRC: failed to locate region type 0.
498 11:32:22.566409 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:32:22.569874 DRAM-K: Running full calibration
500 11:32:22.576374 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:32:22.579385 header.status = 0x0
502 11:32:22.582719 header.version = 0x6 (expected: 0x6)
503 11:32:22.585908 header.size = 0xd00 (expected: 0xd00)
504 11:32:22.586298 header.flags = 0x0
505 11:32:22.592598 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:32:22.610564 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:32:22.616839 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:32:22.620045 dram_init: ddr_geometry: 2
509 11:32:22.623174 [EMI] MDL number = 2
510 11:32:22.623686 [EMI] Get MDL freq = 0
511 11:32:22.626522 dram_init: ddr_type: 0
512 11:32:22.627038 is_discrete_lpddr4: 1
513 11:32:22.630172 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:32:22.630632
515 11:32:22.630936
516 11:32:22.633458 [Bian_co] ETT version 0.0.0.1
517 11:32:22.640149 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:32:22.640543
519 11:32:22.643549 dramc_set_vcore_voltage set vcore to 650000
520 11:32:22.646941 Read voltage for 800, 4
521 11:32:22.647341 Vio18 = 0
522 11:32:22.647847 Vcore = 650000
523 11:32:22.648163 Vdram = 0
524 11:32:22.650174 Vddq = 0
525 11:32:22.650563 Vmddr = 0
526 11:32:22.653372 dram_init: config_dvfs: 1
527 11:32:22.656951 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:32:22.663259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:32:22.666738 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 11:32:22.669889 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 11:32:22.673358 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 11:32:22.676247 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 11:32:22.679734 MEM_TYPE=3, freq_sel=18
534 11:32:22.682942 sv_algorithm_assistance_LP4_1600
535 11:32:22.686443 ============ PULL DRAM RESETB DOWN ============
536 11:32:22.693252 ========== PULL DRAM RESETB DOWN end =========
537 11:32:22.696952 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:32:22.700818 ===================================
539 11:32:22.701381 LPDDR4 DRAM CONFIGURATION
540 11:32:22.704390 ===================================
541 11:32:22.707891 EX_ROW_EN[0] = 0x0
542 11:32:22.708409 EX_ROW_EN[1] = 0x0
543 11:32:22.711302 LP4Y_EN = 0x0
544 11:32:22.711724 WORK_FSP = 0x0
545 11:32:22.714841 WL = 0x2
546 11:32:22.715341 RL = 0x2
547 11:32:22.718893 BL = 0x2
548 11:32:22.719385 RPST = 0x0
549 11:32:22.722970 RD_PRE = 0x0
550 11:32:22.723568 WR_PRE = 0x1
551 11:32:22.726339 WR_PST = 0x0
552 11:32:22.726726 DBI_WR = 0x0
553 11:32:22.729996 DBI_RD = 0x0
554 11:32:22.730460 OTF = 0x1
555 11:32:22.732942 ===================================
556 11:32:22.735969 ===================================
557 11:32:22.739284 ANA top config
558 11:32:22.739705 ===================================
559 11:32:22.742562 DLL_ASYNC_EN = 0
560 11:32:22.745792 ALL_SLAVE_EN = 1
561 11:32:22.749523 NEW_RANK_MODE = 1
562 11:32:22.752708 DLL_IDLE_MODE = 1
563 11:32:22.753096 LP45_APHY_COMB_EN = 1
564 11:32:22.755898 TX_ODT_DIS = 1
565 11:32:22.759479 NEW_8X_MODE = 1
566 11:32:22.762646 ===================================
567 11:32:22.765977 ===================================
568 11:32:22.769033 data_rate = 1600
569 11:32:22.772511 CKR = 1
570 11:32:22.772903 DQ_P2S_RATIO = 8
571 11:32:22.775608 ===================================
572 11:32:22.778906 CA_P2S_RATIO = 8
573 11:32:22.782656 DQ_CA_OPEN = 0
574 11:32:22.785773 DQ_SEMI_OPEN = 0
575 11:32:22.788813 CA_SEMI_OPEN = 0
576 11:32:22.792477 CA_FULL_RATE = 0
577 11:32:22.792861 DQ_CKDIV4_EN = 1
578 11:32:22.795305 CA_CKDIV4_EN = 1
579 11:32:22.799201 CA_PREDIV_EN = 0
580 11:32:22.802490 PH8_DLY = 0
581 11:32:22.805425 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:32:22.808791 DQ_AAMCK_DIV = 4
583 11:32:22.809195 CA_AAMCK_DIV = 4
584 11:32:22.812125 CA_ADMCK_DIV = 4
585 11:32:22.815351 DQ_TRACK_CA_EN = 0
586 11:32:22.818809 CA_PICK = 800
587 11:32:22.821977 CA_MCKIO = 800
588 11:32:22.825273 MCKIO_SEMI = 0
589 11:32:22.828958 PLL_FREQ = 3068
590 11:32:22.829344 DQ_UI_PI_RATIO = 32
591 11:32:22.832334 CA_UI_PI_RATIO = 0
592 11:32:22.835820 ===================================
593 11:32:22.838935 ===================================
594 11:32:22.842316 memory_type:LPDDR4
595 11:32:22.845803 GP_NUM : 10
596 11:32:22.846189 SRAM_EN : 1
597 11:32:22.849041 MD32_EN : 0
598 11:32:22.851885 ===================================
599 11:32:22.855199 [ANA_INIT] >>>>>>>>>>>>>>
600 11:32:22.855628 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:32:22.858524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:32:22.862075 ===================================
603 11:32:22.865739 data_rate = 1600,PCW = 0X7600
604 11:32:22.868583 ===================================
605 11:32:22.872510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:32:22.879131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:32:22.885190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:32:22.888426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:32:22.892093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:32:22.895086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:32:22.898550 [ANA_INIT] flow start
612 11:32:22.898935 [ANA_INIT] PLL >>>>>>>>
613 11:32:22.902064 [ANA_INIT] PLL <<<<<<<<
614 11:32:22.905333 [ANA_INIT] MIDPI >>>>>>>>
615 11:32:22.905720 [ANA_INIT] MIDPI <<<<<<<<
616 11:32:22.911884 [ANA_INIT] DLL >>>>>>>>
617 11:32:22.912273 [ANA_INIT] flow end
618 11:32:22.915357 ============ LP4 DIFF to SE enter ============
619 11:32:22.918273 ============ LP4 DIFF to SE exit ============
620 11:32:22.921831 [ANA_INIT] <<<<<<<<<<<<<
621 11:32:22.924805 [Flow] Enable top DCM control >>>>>
622 11:32:22.928497 [Flow] Enable top DCM control <<<<<
623 11:32:22.931721 Enable DLL master slave shuffle
624 11:32:22.938334 ==============================================================
625 11:32:22.938727 Gating Mode config
626 11:32:22.944718 ==============================================================
627 11:32:22.945109 Config description:
628 11:32:22.954638 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:32:22.961141 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:32:22.968423 SELPH_MODE 0: By rank 1: By Phase
631 11:32:22.971389 ==============================================================
632 11:32:22.974840 GAT_TRACK_EN = 1
633 11:32:22.978004 RX_GATING_MODE = 2
634 11:32:22.981262 RX_GATING_TRACK_MODE = 2
635 11:32:22.984677 SELPH_MODE = 1
636 11:32:22.987533 PICG_EARLY_EN = 1
637 11:32:22.991107 VALID_LAT_VALUE = 1
638 11:32:22.994690 ==============================================================
639 11:32:22.997818 Enter into Gating configuration >>>>
640 11:32:23.001392 Exit from Gating configuration <<<<
641 11:32:23.004551 Enter into DVFS_PRE_config >>>>>
642 11:32:23.017858 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:32:23.021487 Exit from DVFS_PRE_config <<<<<
644 11:32:23.024617 Enter into PICG configuration >>>>
645 11:32:23.025020 Exit from PICG configuration <<<<
646 11:32:23.027973 [RX_INPUT] configuration >>>>>
647 11:32:23.031489 [RX_INPUT] configuration <<<<<
648 11:32:23.037764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:32:23.041497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:32:23.047868 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:32:23.054071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:32:23.060770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:32:23.067455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:32:23.070936 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:32:23.073998 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:32:23.080952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:32:23.084416 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:32:23.087763 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:32:23.091017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:32:23.094188 ===================================
661 11:32:23.097571 LPDDR4 DRAM CONFIGURATION
662 11:32:23.100742 ===================================
663 11:32:23.103923 EX_ROW_EN[0] = 0x0
664 11:32:23.104308 EX_ROW_EN[1] = 0x0
665 11:32:23.107389 LP4Y_EN = 0x0
666 11:32:23.107816 WORK_FSP = 0x0
667 11:32:23.111185 WL = 0x2
668 11:32:23.111611 RL = 0x2
669 11:32:23.113855 BL = 0x2
670 11:32:23.114235 RPST = 0x0
671 11:32:23.117209 RD_PRE = 0x0
672 11:32:23.117591 WR_PRE = 0x1
673 11:32:23.120678 WR_PST = 0x0
674 11:32:23.121059 DBI_WR = 0x0
675 11:32:23.124136 DBI_RD = 0x0
676 11:32:23.124526 OTF = 0x1
677 11:32:23.127527 ===================================
678 11:32:23.133810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:32:23.137252 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:32:23.140724 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:32:23.143768 ===================================
682 11:32:23.147117 LPDDR4 DRAM CONFIGURATION
683 11:32:23.150472 ===================================
684 11:32:23.154093 EX_ROW_EN[0] = 0x10
685 11:32:23.154482 EX_ROW_EN[1] = 0x0
686 11:32:23.157036 LP4Y_EN = 0x0
687 11:32:23.157460 WORK_FSP = 0x0
688 11:32:23.160447 WL = 0x2
689 11:32:23.160836 RL = 0x2
690 11:32:23.163666 BL = 0x2
691 11:32:23.164059 RPST = 0x0
692 11:32:23.167048 RD_PRE = 0x0
693 11:32:23.167477 WR_PRE = 0x1
694 11:32:23.170538 WR_PST = 0x0
695 11:32:23.170922 DBI_WR = 0x0
696 11:32:23.173744 DBI_RD = 0x0
697 11:32:23.174218 OTF = 0x1
698 11:32:23.177903 ===================================
699 11:32:23.183508 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:32:23.188726 nWR fixed to 40
701 11:32:23.191744 [ModeRegInit_LP4] CH0 RK0
702 11:32:23.192131 [ModeRegInit_LP4] CH0 RK1
703 11:32:23.195135 [ModeRegInit_LP4] CH1 RK0
704 11:32:23.198157 [ModeRegInit_LP4] CH1 RK1
705 11:32:23.198547 match AC timing 13
706 11:32:23.204692 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:32:23.208126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:32:23.211612 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:32:23.218353 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:32:23.221581 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:32:23.224643 [EMI DOE] emi_dcm 0
712 11:32:23.228158 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:32:23.228549 ==
714 11:32:23.231217 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:32:23.234791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:32:23.235184 ==
717 11:32:23.241783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:32:23.247862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:32:23.256255 [CA 0] Center 37 (6~68) winsize 63
720 11:32:23.259188 [CA 1] Center 37 (6~68) winsize 63
721 11:32:23.262560 [CA 2] Center 34 (4~65) winsize 62
722 11:32:23.265698 [CA 3] Center 34 (4~65) winsize 62
723 11:32:23.269764 [CA 4] Center 34 (4~64) winsize 61
724 11:32:23.272414 [CA 5] Center 33 (3~64) winsize 62
725 11:32:23.272871
726 11:32:23.276120 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:32:23.276509
728 11:32:23.279566 [CATrainingPosCal] consider 1 rank data
729 11:32:23.284289 u2DelayCellTimex100 = 270/100 ps
730 11:32:23.287355 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 11:32:23.290227 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:32:23.293488 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:32:23.296446 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:32:23.299986 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
735 11:32:23.307025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:32:23.307412
737 11:32:23.309927 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:32:23.310309
739 11:32:23.313300 [CBTSetCACLKResult] CA Dly = 33
740 11:32:23.313687 CS Dly: 7 (0~38)
741 11:32:23.314156 ==
742 11:32:23.316915 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:32:23.320031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:32:23.323016 ==
745 11:32:23.326905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:32:23.333050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:32:23.342043 [CA 0] Center 37 (6~68) winsize 63
748 11:32:23.345379 [CA 1] Center 37 (6~68) winsize 63
749 11:32:23.348972 [CA 2] Center 34 (4~65) winsize 62
750 11:32:23.352102 [CA 3] Center 34 (4~65) winsize 62
751 11:32:23.355101 [CA 4] Center 33 (3~64) winsize 62
752 11:32:23.358365 [CA 5] Center 33 (3~64) winsize 62
753 11:32:23.358748
754 11:32:23.361853 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:32:23.362248
756 11:32:23.365491 [CATrainingPosCal] consider 2 rank data
757 11:32:23.368800 u2DelayCellTimex100 = 270/100 ps
758 11:32:23.372549 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 11:32:23.378714 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 11:32:23.381870 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:32:23.385106 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:32:23.388549 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 11:32:23.391946 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:32:23.392345
765 11:32:23.395005 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:32:23.395401
767 11:32:23.398721 [CBTSetCACLKResult] CA Dly = 33
768 11:32:23.399116 CS Dly: 7 (0~38)
769 11:32:23.401489
770 11:32:23.404739 ----->DramcWriteLeveling(PI) begin...
771 11:32:23.405139 ==
772 11:32:23.408337 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:32:23.411753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:32:23.412146 ==
775 11:32:23.415061 Write leveling (Byte 0): 32 => 32
776 11:32:23.418384 Write leveling (Byte 1): 31 => 31
777 11:32:23.421542 DramcWriteLeveling(PI) end<-----
778 11:32:23.421934
779 11:32:23.422233 ==
780 11:32:23.424700 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:32:23.428094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:32:23.428513 ==
783 11:32:23.431985 [Gating] SW mode calibration
784 11:32:23.438273 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:32:23.444710 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:32:23.447929 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:32:23.451150 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:32:23.458078 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:32:23.461470 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:32:23.464434 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:32:23.471085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:32:23.474293 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:32:23.477954 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:32:23.484369 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:32:23.487834 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:32:23.491399 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:32:23.497878 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:32:23.500999 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:32:23.504416 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:32:23.511255 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:32:23.514037 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:32:23.517758 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:32:23.524002 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:32:23.527368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 11:32:23.530629 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 11:32:23.537151 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:32:23.540753 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:32:23.544274 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:32:23.547523 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:32:23.553934 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:32:23.557039 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:32:23.560489 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
813 11:32:23.566885 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 11:32:23.570689 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:32:23.573735 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:32:23.580533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:32:23.583360 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:32:23.586742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:32:23.593403 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 11:32:23.597472 0 10 8 | B1->B0 | 3434 2b2b | 0 1 | (0 0) (1 0)
821 11:32:23.600089 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
822 11:32:23.606740 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:32:23.610258 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:32:23.613542 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:32:23.620257 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:32:23.623483 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:32:23.626534 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 11:32:23.633240 0 11 8 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
829 11:32:23.636392 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
830 11:32:23.639748 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:32:23.646522 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:32:23.649858 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:32:23.653239 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:32:23.659490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:32:23.663591 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:32:23.666787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 11:32:23.672903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:32:23.676168 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:32:23.679657 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:32:23.686480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:32:23.689743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:32:23.693168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:32:23.699632 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:32:23.703147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:32:23.706067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:32:23.712513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:32:23.715883 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:32:23.719291 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:32:23.722603 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:32:23.729186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:32:23.732497 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:32:23.735956 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 11:32:23.742803 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 11:32:23.745601 Total UI for P1: 0, mck2ui 16
855 11:32:23.749073 best dqsien dly found for B0: ( 0, 14, 8)
856 11:32:23.752718 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 11:32:23.755995 Total UI for P1: 0, mck2ui 16
858 11:32:23.759368 best dqsien dly found for B1: ( 0, 14, 12)
859 11:32:23.762558 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 11:32:23.765894 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 11:32:23.765989
862 11:32:23.769277 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:32:23.772547 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 11:32:23.776174 [Gating] SW calibration Done
865 11:32:23.776254 ==
866 11:32:23.779206 Dram Type= 6, Freq= 0, CH_0, rank 0
867 11:32:23.785653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 11:32:23.785734 ==
869 11:32:23.785812 RX Vref Scan: 0
870 11:32:23.785885
871 11:32:23.788734 RX Vref 0 -> 0, step: 1
872 11:32:23.788813
873 11:32:23.792200 RX Delay -130 -> 252, step: 16
874 11:32:23.795385 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 11:32:23.798604 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 11:32:23.802208 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
877 11:32:23.808623 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
878 11:32:23.812470 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 11:32:23.815406 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 11:32:23.818567 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 11:32:23.822012 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 11:32:23.829014 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 11:32:23.832030 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 11:32:23.835216 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 11:32:23.838819 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 11:32:23.842381 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
887 11:32:23.848769 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 11:32:23.852551 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 11:32:23.855788 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 11:32:23.856094 ==
891 11:32:23.858490 Dram Type= 6, Freq= 0, CH_0, rank 0
892 11:32:23.862066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 11:32:23.862371 ==
894 11:32:23.865201 DQS Delay:
895 11:32:23.865501 DQS0 = 0, DQS1 = 0
896 11:32:23.868748 DQM Delay:
897 11:32:23.869148 DQM0 = 83, DQM1 = 71
898 11:32:23.869485 DQ Delay:
899 11:32:23.872067 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
900 11:32:23.875304 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
901 11:32:23.878611 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
902 11:32:23.881808 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
903 11:32:23.881952
904 11:32:23.882065
905 11:32:23.885301 ==
906 11:32:23.888262 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:32:23.891561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:32:23.891699 ==
909 11:32:23.891783
910 11:32:23.891860
911 11:32:23.895763 TX Vref Scan disable
912 11:32:23.895872 == TX Byte 0 ==
913 11:32:23.898643 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 11:32:23.904965 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 11:32:23.905061 == TX Byte 1 ==
916 11:32:23.911808 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 11:32:23.914693 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 11:32:23.914771 ==
919 11:32:23.918319 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:32:23.921415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:32:23.921491 ==
922 11:32:23.935149 TX Vref=22, minBit 4, minWin=27, winSum=446
923 11:32:23.938074 TX Vref=24, minBit 5, minWin=27, winSum=445
924 11:32:23.941526 TX Vref=26, minBit 4, minWin=27, winSum=445
925 11:32:23.944748 TX Vref=28, minBit 5, minWin=27, winSum=452
926 11:32:23.948294 TX Vref=30, minBit 10, minWin=27, winSum=449
927 11:32:23.954558 TX Vref=32, minBit 10, minWin=27, winSum=450
928 11:32:23.957772 [TxChooseVref] Worse bit 5, Min win 27, Win sum 452, Final Vref 28
929 11:32:23.957858
930 11:32:23.961598 Final TX Range 1 Vref 28
931 11:32:23.961712
932 11:32:23.961813 ==
933 11:32:23.964703 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:32:23.967937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:32:23.971044 ==
936 11:32:23.971145
937 11:32:23.971222
938 11:32:23.971295 TX Vref Scan disable
939 11:32:23.974733 == TX Byte 0 ==
940 11:32:23.978384 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 11:32:23.985075 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 11:32:23.985217 == TX Byte 1 ==
943 11:32:23.987903 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 11:32:23.994564 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 11:32:23.994726
946 11:32:23.994849 [DATLAT]
947 11:32:23.994961 Freq=800, CH0 RK0
948 11:32:23.995071
949 11:32:23.998326 DATLAT Default: 0xa
950 11:32:24.001341 0, 0xFFFF, sum = 0
951 11:32:24.001569 1, 0xFFFF, sum = 0
952 11:32:24.004534 2, 0xFFFF, sum = 0
953 11:32:24.004751 3, 0xFFFF, sum = 0
954 11:32:24.008404 4, 0xFFFF, sum = 0
955 11:32:24.008567 5, 0xFFFF, sum = 0
956 11:32:24.011498 6, 0xFFFF, sum = 0
957 11:32:24.011728 7, 0xFFFF, sum = 0
958 11:32:24.014729 8, 0xFFFF, sum = 0
959 11:32:24.014865 9, 0x0, sum = 1
960 11:32:24.017706 10, 0x0, sum = 2
961 11:32:24.017830 11, 0x0, sum = 3
962 11:32:24.017921 12, 0x0, sum = 4
963 11:32:24.021139 best_step = 10
964 11:32:24.021262
965 11:32:24.021351 ==
966 11:32:24.024829 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:32:24.027628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:32:24.027722 ==
969 11:32:24.031223 RX Vref Scan: 1
970 11:32:24.031345
971 11:32:24.034436 Set Vref Range= 32 -> 127
972 11:32:24.034526
973 11:32:24.034595 RX Vref 32 -> 127, step: 1
974 11:32:24.034661
975 11:32:24.038642 RX Delay -111 -> 252, step: 8
976 11:32:24.038734
977 11:32:24.041188 Set Vref, RX VrefLevel [Byte0]: 32
978 11:32:24.044125 [Byte1]: 32
979 11:32:24.047537
980 11:32:24.047627 Set Vref, RX VrefLevel [Byte0]: 33
981 11:32:24.050835 [Byte1]: 33
982 11:32:24.055530
983 11:32:24.055621 Set Vref, RX VrefLevel [Byte0]: 34
984 11:32:24.058828 [Byte1]: 34
985 11:32:24.062726
986 11:32:24.062818 Set Vref, RX VrefLevel [Byte0]: 35
987 11:32:24.066122 [Byte1]: 35
988 11:32:24.070871
989 11:32:24.070966 Set Vref, RX VrefLevel [Byte0]: 36
990 11:32:24.074299 [Byte1]: 36
991 11:32:24.078465
992 11:32:24.078556 Set Vref, RX VrefLevel [Byte0]: 37
993 11:32:24.081383 [Byte1]: 37
994 11:32:24.085766
995 11:32:24.085856 Set Vref, RX VrefLevel [Byte0]: 38
996 11:32:24.089371 [Byte1]: 38
997 11:32:24.093713
998 11:32:24.093805 Set Vref, RX VrefLevel [Byte0]: 39
999 11:32:24.096740 [Byte1]: 39
1000 11:32:24.101494
1001 11:32:24.101589 Set Vref, RX VrefLevel [Byte0]: 40
1002 11:32:24.104201 [Byte1]: 40
1003 11:32:24.108957
1004 11:32:24.109048 Set Vref, RX VrefLevel [Byte0]: 41
1005 11:32:24.112681 [Byte1]: 41
1006 11:32:24.116776
1007 11:32:24.116883 Set Vref, RX VrefLevel [Byte0]: 42
1008 11:32:24.119798 [Byte1]: 42
1009 11:32:24.124494
1010 11:32:24.124614 Set Vref, RX VrefLevel [Byte0]: 43
1011 11:32:24.127269 [Byte1]: 43
1012 11:32:24.131921
1013 11:32:24.132072 Set Vref, RX VrefLevel [Byte0]: 44
1014 11:32:24.135290 [Byte1]: 44
1015 11:32:24.139689
1016 11:32:24.139864 Set Vref, RX VrefLevel [Byte0]: 45
1017 11:32:24.142901 [Byte1]: 45
1018 11:32:24.147501
1019 11:32:24.147751 Set Vref, RX VrefLevel [Byte0]: 46
1020 11:32:24.150811 [Byte1]: 46
1021 11:32:24.155316
1022 11:32:24.155739 Set Vref, RX VrefLevel [Byte0]: 47
1023 11:32:24.158350 [Byte1]: 47
1024 11:32:24.162748
1025 11:32:24.163129 Set Vref, RX VrefLevel [Byte0]: 48
1026 11:32:24.165754 [Byte1]: 48
1027 11:32:24.170694
1028 11:32:24.171079 Set Vref, RX VrefLevel [Byte0]: 49
1029 11:32:24.173489 [Byte1]: 49
1030 11:32:24.177848
1031 11:32:24.178230 Set Vref, RX VrefLevel [Byte0]: 50
1032 11:32:24.181225 [Byte1]: 50
1033 11:32:24.185654
1034 11:32:24.186039 Set Vref, RX VrefLevel [Byte0]: 51
1035 11:32:24.188757 [Byte1]: 51
1036 11:32:24.193418
1037 11:32:24.193799 Set Vref, RX VrefLevel [Byte0]: 52
1038 11:32:24.196761 [Byte1]: 52
1039 11:32:24.200922
1040 11:32:24.201317 Set Vref, RX VrefLevel [Byte0]: 53
1041 11:32:24.204277 [Byte1]: 53
1042 11:32:24.208667
1043 11:32:24.209028 Set Vref, RX VrefLevel [Byte0]: 54
1044 11:32:24.212109 [Byte1]: 54
1045 11:32:24.216424
1046 11:32:24.216818 Set Vref, RX VrefLevel [Byte0]: 55
1047 11:32:24.219278 [Byte1]: 55
1048 11:32:24.224520
1049 11:32:24.224904 Set Vref, RX VrefLevel [Byte0]: 56
1050 11:32:24.227170 [Byte1]: 56
1051 11:32:24.231579
1052 11:32:24.231966 Set Vref, RX VrefLevel [Byte0]: 57
1053 11:32:24.234798 [Byte1]: 57
1054 11:32:24.238999
1055 11:32:24.239349 Set Vref, RX VrefLevel [Byte0]: 58
1056 11:32:24.242382 [Byte1]: 58
1057 11:32:24.246985
1058 11:32:24.247462 Set Vref, RX VrefLevel [Byte0]: 59
1059 11:32:24.249846 [Byte1]: 59
1060 11:32:24.254581
1061 11:32:24.254974 Set Vref, RX VrefLevel [Byte0]: 60
1062 11:32:24.257840 [Byte1]: 60
1063 11:32:24.261884
1064 11:32:24.262269 Set Vref, RX VrefLevel [Byte0]: 61
1065 11:32:24.265479 [Byte1]: 61
1066 11:32:24.269797
1067 11:32:24.270203 Set Vref, RX VrefLevel [Byte0]: 62
1068 11:32:24.273077 [Byte1]: 62
1069 11:32:24.277427
1070 11:32:24.277820 Set Vref, RX VrefLevel [Byte0]: 63
1071 11:32:24.280801 [Byte1]: 63
1072 11:32:24.285058
1073 11:32:24.285447 Set Vref, RX VrefLevel [Byte0]: 64
1074 11:32:24.288372 [Byte1]: 64
1075 11:32:24.292535
1076 11:32:24.292922 Set Vref, RX VrefLevel [Byte0]: 65
1077 11:32:24.296244 [Byte1]: 65
1078 11:32:24.300071
1079 11:32:24.300646 Set Vref, RX VrefLevel [Byte0]: 66
1080 11:32:24.303853 [Byte1]: 66
1081 11:32:24.307761
1082 11:32:24.308143 Set Vref, RX VrefLevel [Byte0]: 67
1083 11:32:24.311082 [Byte1]: 67
1084 11:32:24.315623
1085 11:32:24.316006 Set Vref, RX VrefLevel [Byte0]: 68
1086 11:32:24.318916 [Byte1]: 68
1087 11:32:24.323002
1088 11:32:24.323384 Set Vref, RX VrefLevel [Byte0]: 69
1089 11:32:24.326898 [Byte1]: 69
1090 11:32:24.330747
1091 11:32:24.331137 Set Vref, RX VrefLevel [Byte0]: 70
1092 11:32:24.334397 [Byte1]: 70
1093 11:32:24.338450
1094 11:32:24.338941 Set Vref, RX VrefLevel [Byte0]: 71
1095 11:32:24.341775 [Byte1]: 71
1096 11:32:24.346161
1097 11:32:24.346527 Set Vref, RX VrefLevel [Byte0]: 72
1098 11:32:24.349633 [Byte1]: 72
1099 11:32:24.353960
1100 11:32:24.354344 Set Vref, RX VrefLevel [Byte0]: 73
1101 11:32:24.357146 [Byte1]: 73
1102 11:32:24.361330
1103 11:32:24.361712 Set Vref, RX VrefLevel [Byte0]: 74
1104 11:32:24.364644 [Byte1]: 74
1105 11:32:24.369190
1106 11:32:24.369710 Set Vref, RX VrefLevel [Byte0]: 75
1107 11:32:24.372692 [Byte1]: 75
1108 11:32:24.377089
1109 11:32:24.377471 Set Vref, RX VrefLevel [Byte0]: 76
1110 11:32:24.380345 [Byte1]: 76
1111 11:32:24.384685
1112 11:32:24.385067 Set Vref, RX VrefLevel [Byte0]: 77
1113 11:32:24.390988 [Byte1]: 77
1114 11:32:24.391375
1115 11:32:24.394537 Set Vref, RX VrefLevel [Byte0]: 78
1116 11:32:24.397508 [Byte1]: 78
1117 11:32:24.397892
1118 11:32:24.400938 Set Vref, RX VrefLevel [Byte0]: 79
1119 11:32:24.404519 [Byte1]: 79
1120 11:32:24.404901
1121 11:32:24.407743 Set Vref, RX VrefLevel [Byte0]: 80
1122 11:32:24.411075 [Byte1]: 80
1123 11:32:24.415511
1124 11:32:24.415898 Set Vref, RX VrefLevel [Byte0]: 81
1125 11:32:24.418214 [Byte1]: 81
1126 11:32:24.422624
1127 11:32:24.423004 Set Vref, RX VrefLevel [Byte0]: 82
1128 11:32:24.425746 [Byte1]: 82
1129 11:32:24.430139
1130 11:32:24.430521 Set Vref, RX VrefLevel [Byte0]: 83
1131 11:32:24.434044 [Byte1]: 83
1132 11:32:24.437703
1133 11:32:24.438090 Final RX Vref Byte 0 = 62 to rank0
1134 11:32:24.441826 Final RX Vref Byte 1 = 53 to rank0
1135 11:32:24.444367 Final RX Vref Byte 0 = 62 to rank1
1136 11:32:24.448243 Final RX Vref Byte 1 = 53 to rank1==
1137 11:32:24.451179 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 11:32:24.457887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 11:32:24.458286 ==
1140 11:32:24.458586 DQS Delay:
1141 11:32:24.460819 DQS0 = 0, DQS1 = 0
1142 11:32:24.461205 DQM Delay:
1143 11:32:24.461664 DQM0 = 87, DQM1 = 76
1144 11:32:24.464208 DQ Delay:
1145 11:32:24.467985 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1146 11:32:24.470722 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1147 11:32:24.474072 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1148 11:32:24.477555 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1149 11:32:24.477939
1150 11:32:24.478232
1151 11:32:24.484053 [DQSOSCAuto] RK0, (LSB)MR18= 0x492a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1152 11:32:24.487384 CH0 RK0: MR19=606, MR18=492A
1153 11:32:24.534874 CH0_RK0: MR19=0x606, MR18=0x492A, DQSOSC=391, MR23=63, INC=96, DEC=64
1154 11:32:24.535343
1155 11:32:24.535712 ----->DramcWriteLeveling(PI) begin...
1156 11:32:24.536128 ==
1157 11:32:24.536555 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 11:32:24.537145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 11:32:24.537441 ==
1160 11:32:24.537703 Write leveling (Byte 0): 30 => 30
1161 11:32:24.537960 Write leveling (Byte 1): 30 => 30
1162 11:32:24.538213 DramcWriteLeveling(PI) end<-----
1163 11:32:24.538460
1164 11:32:24.538706 ==
1165 11:32:24.538953 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 11:32:24.539202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 11:32:24.539493 ==
1168 11:32:24.539756 [Gating] SW mode calibration
1169 11:32:24.540005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 11:32:24.578865 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 11:32:24.579272 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 11:32:24.580088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1173 11:32:24.580472 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1174 11:32:24.580837 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:32:24.581192 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:32:24.581562 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:32:24.581840 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:32:24.582101 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:32:24.582421 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:32:24.594055 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:32:24.594514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:32:24.595135 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:32:24.597894 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:32:24.600914 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:32:24.604605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:32:24.607455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:32:24.611092 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:32:24.614115 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1189 11:32:24.621091 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1190 11:32:24.624427 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:32:24.627338 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:32:24.634669 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:32:24.637999 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:32:24.640846 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:32:24.647385 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:32:24.650758 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:32:24.654200 0 9 8 | B1->B0 | 2424 2c2c | 1 0 | (1 1) (0 0)
1198 11:32:24.660636 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1199 11:32:24.663893 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 11:32:24.667293 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 11:32:24.673761 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 11:32:24.677298 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 11:32:24.680686 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 11:32:24.687280 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1205 11:32:24.690576 0 10 8 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 0)
1206 11:32:24.693560 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:32:24.700348 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:32:24.703675 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:32:24.706914 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:32:24.713763 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:32:24.717101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:32:24.720152 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:32:24.726805 0 11 8 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
1214 11:32:24.730582 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 11:32:24.734568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 11:32:24.740138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 11:32:24.743489 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 11:32:24.746951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 11:32:24.753561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 11:32:24.757072 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 11:32:24.760004 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1222 11:32:24.766663 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1223 11:32:24.770190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:32:24.773318 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 11:32:24.779829 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 11:32:24.783135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 11:32:24.786366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 11:32:24.792861 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 11:32:24.796211 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 11:32:24.800028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 11:32:24.806277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 11:32:24.809537 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 11:32:24.812932 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 11:32:24.819753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 11:32:24.822961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 11:32:24.826431 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1237 11:32:24.832789 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1238 11:32:24.833175 Total UI for P1: 0, mck2ui 16
1239 11:32:24.836196 best dqsien dly found for B0: ( 0, 14, 4)
1240 11:32:24.842802 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 11:32:24.846340 Total UI for P1: 0, mck2ui 16
1242 11:32:24.849499 best dqsien dly found for B1: ( 0, 14, 6)
1243 11:32:24.852757 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1244 11:32:24.856359 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1245 11:32:24.856738
1246 11:32:24.859372 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1247 11:32:24.862510 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1248 11:32:24.866172 [Gating] SW calibration Done
1249 11:32:24.866549 ==
1250 11:32:24.869321 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 11:32:24.872541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 11:32:24.872925 ==
1253 11:32:24.876323 RX Vref Scan: 0
1254 11:32:24.876705
1255 11:32:24.876998 RX Vref 0 -> 0, step: 1
1256 11:32:24.877272
1257 11:32:24.879746 RX Delay -130 -> 252, step: 16
1258 11:32:24.885966 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1259 11:32:24.889619 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1260 11:32:24.892753 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1261 11:32:24.896317 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1262 11:32:24.899621 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1263 11:32:24.902826 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1264 11:32:24.909412 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1265 11:32:24.912891 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1266 11:32:24.916243 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1267 11:32:24.919367 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1268 11:32:24.922639 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1269 11:32:24.929338 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1270 11:32:24.932279 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1271 11:32:24.936636 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1272 11:32:24.939306 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1273 11:32:24.945496 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1274 11:32:24.946020 ==
1275 11:32:24.949131 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 11:32:24.953040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 11:32:24.953545 ==
1278 11:32:24.954004 DQS Delay:
1279 11:32:24.955771 DQS0 = 0, DQS1 = 0
1280 11:32:24.956174 DQM Delay:
1281 11:32:24.958868 DQM0 = 83, DQM1 = 76
1282 11:32:24.959255 DQ Delay:
1283 11:32:24.962396 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1284 11:32:24.965514 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1285 11:32:24.968932 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1286 11:32:24.972353 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1287 11:32:24.972740
1288 11:32:24.973034
1289 11:32:24.973303 ==
1290 11:32:24.975369 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:32:24.979218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:32:24.979660 ==
1293 11:32:24.982453
1294 11:32:24.982843
1295 11:32:24.983230 TX Vref Scan disable
1296 11:32:24.985846 == TX Byte 0 ==
1297 11:32:24.989194 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1298 11:32:24.992004 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1299 11:32:24.995105 == TX Byte 1 ==
1300 11:32:24.998688 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1301 11:32:25.001888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1302 11:32:25.002287 ==
1303 11:32:25.005581 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 11:32:25.011748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 11:32:25.012146 ==
1306 11:32:25.023851 TX Vref=22, minBit 9, minWin=27, winSum=447
1307 11:32:25.026930 TX Vref=24, minBit 9, minWin=27, winSum=445
1308 11:32:25.030412 TX Vref=26, minBit 9, minWin=27, winSum=450
1309 11:32:25.033844 TX Vref=28, minBit 8, minWin=27, winSum=452
1310 11:32:25.037007 TX Vref=30, minBit 9, minWin=27, winSum=449
1311 11:32:25.043646 TX Vref=32, minBit 9, minWin=27, winSum=445
1312 11:32:25.047028 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 28
1313 11:32:25.047230
1314 11:32:25.050100 Final TX Range 1 Vref 28
1315 11:32:25.050304
1316 11:32:25.050458 ==
1317 11:32:25.053394 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:32:25.057076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:32:25.057280 ==
1320 11:32:25.060218
1321 11:32:25.060418
1322 11:32:25.060573 TX Vref Scan disable
1323 11:32:25.063413 == TX Byte 0 ==
1324 11:32:25.067264 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1325 11:32:25.073752 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1326 11:32:25.074128 == TX Byte 1 ==
1327 11:32:25.077087 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1328 11:32:25.084233 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1329 11:32:25.084617
1330 11:32:25.084910 [DATLAT]
1331 11:32:25.085180 Freq=800, CH0 RK1
1332 11:32:25.085443
1333 11:32:25.086802 DATLAT Default: 0xa
1334 11:32:25.087178 0, 0xFFFF, sum = 0
1335 11:32:25.090330 1, 0xFFFF, sum = 0
1336 11:32:25.093716 2, 0xFFFF, sum = 0
1337 11:32:25.094096 3, 0xFFFF, sum = 0
1338 11:32:25.097211 4, 0xFFFF, sum = 0
1339 11:32:25.097595 5, 0xFFFF, sum = 0
1340 11:32:25.099984 6, 0xFFFF, sum = 0
1341 11:32:25.100369 7, 0xFFFF, sum = 0
1342 11:32:25.103831 8, 0xFFFF, sum = 0
1343 11:32:25.104219 9, 0x0, sum = 1
1344 11:32:25.106846 10, 0x0, sum = 2
1345 11:32:25.107232 11, 0x0, sum = 3
1346 11:32:25.107562 12, 0x0, sum = 4
1347 11:32:25.109906 best_step = 10
1348 11:32:25.110350
1349 11:32:25.110653 ==
1350 11:32:25.113153 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 11:32:25.116901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 11:32:25.117284 ==
1353 11:32:25.120042 RX Vref Scan: 0
1354 11:32:25.120416
1355 11:32:25.123202 RX Vref 0 -> 0, step: 1
1356 11:32:25.123622
1357 11:32:25.123915 RX Delay -111 -> 252, step: 8
1358 11:32:25.130285 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1359 11:32:25.133716 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1360 11:32:25.137139 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1361 11:32:25.140640 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1362 11:32:25.143987 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1363 11:32:25.150244 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1364 11:32:25.153876 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1365 11:32:25.157284 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1366 11:32:25.160051 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1367 11:32:25.163591 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1368 11:32:25.169882 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1369 11:32:25.173606 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1370 11:32:25.176651 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1371 11:32:25.179909 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1372 11:32:25.187032 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1373 11:32:25.190506 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1374 11:32:25.190903 ==
1375 11:32:25.193013 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 11:32:25.196626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 11:32:25.197025 ==
1378 11:32:25.199926 DQS Delay:
1379 11:32:25.200321 DQS0 = 0, DQS1 = 0
1380 11:32:25.200713 DQM Delay:
1381 11:32:25.202823 DQM0 = 85, DQM1 = 77
1382 11:32:25.203221 DQ Delay:
1383 11:32:25.206647 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1384 11:32:25.210099 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1385 11:32:25.212916 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1386 11:32:25.216504 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1387 11:32:25.216898
1388 11:32:25.217285
1389 11:32:25.226526 [DQSOSCAuto] RK1, (LSB)MR18= 0x440b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1390 11:32:25.229254 CH0 RK1: MR19=606, MR18=440B
1391 11:32:25.232956 CH0_RK1: MR19=0x606, MR18=0x440B, DQSOSC=392, MR23=63, INC=96, DEC=64
1392 11:32:25.235844 [RxdqsGatingPostProcess] freq 800
1393 11:32:25.242678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1394 11:32:25.246097 Pre-setting of DQS Precalculation
1395 11:32:25.249127 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1396 11:32:25.249557 ==
1397 11:32:25.252701 Dram Type= 6, Freq= 0, CH_1, rank 0
1398 11:32:25.259006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 11:32:25.259421 ==
1400 11:32:25.262409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 11:32:25.269153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 11:32:25.278877 [CA 0] Center 36 (6~67) winsize 62
1403 11:32:25.282515 [CA 1] Center 36 (6~67) winsize 62
1404 11:32:25.285528 [CA 2] Center 34 (4~65) winsize 62
1405 11:32:25.288707 [CA 3] Center 34 (3~65) winsize 63
1406 11:32:25.292048 [CA 4] Center 34 (4~65) winsize 62
1407 11:32:25.295476 [CA 5] Center 34 (3~65) winsize 63
1408 11:32:25.295827
1409 11:32:25.298706 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 11:32:25.299089
1411 11:32:25.301873 [CATrainingPosCal] consider 1 rank data
1412 11:32:25.305129 u2DelayCellTimex100 = 270/100 ps
1413 11:32:25.308529 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 11:32:25.315531 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 11:32:25.318613 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 11:32:25.321902 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 11:32:25.325294 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 11:32:25.328485 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1419 11:32:25.328866
1420 11:32:25.331767 CA PerBit enable=1, Macro0, CA PI delay=34
1421 11:32:25.332150
1422 11:32:25.335284 [CBTSetCACLKResult] CA Dly = 34
1423 11:32:25.338323 CS Dly: 4 (0~35)
1424 11:32:25.338703 ==
1425 11:32:25.341832 Dram Type= 6, Freq= 0, CH_1, rank 1
1426 11:32:25.344987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 11:32:25.345372 ==
1428 11:32:25.351767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 11:32:25.354768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 11:32:25.364968 [CA 0] Center 37 (7~67) winsize 61
1431 11:32:25.368204 [CA 1] Center 37 (6~68) winsize 63
1432 11:32:25.371876 [CA 2] Center 34 (4~65) winsize 62
1433 11:32:25.375253 [CA 3] Center 34 (3~65) winsize 63
1434 11:32:25.378370 [CA 4] Center 34 (4~65) winsize 62
1435 11:32:25.381591 [CA 5] Center 34 (3~65) winsize 63
1436 11:32:25.381971
1437 11:32:25.385574 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1438 11:32:25.385986
1439 11:32:25.388121 [CATrainingPosCal] consider 2 rank data
1440 11:32:25.391542 u2DelayCellTimex100 = 270/100 ps
1441 11:32:25.394538 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1442 11:32:25.401265 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 11:32:25.404536 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 11:32:25.407959 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1445 11:32:25.411306 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 11:32:25.414735 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1447 11:32:25.415116
1448 11:32:25.417940 CA PerBit enable=1, Macro0, CA PI delay=34
1449 11:32:25.418348
1450 11:32:25.421132 [CBTSetCACLKResult] CA Dly = 34
1451 11:32:25.424813 CS Dly: 5 (0~38)
1452 11:32:25.425197
1453 11:32:25.427822 ----->DramcWriteLeveling(PI) begin...
1454 11:32:25.428213 ==
1455 11:32:25.430914 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 11:32:25.434043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 11:32:25.434444 ==
1458 11:32:25.437736 Write leveling (Byte 0): 28 => 28
1459 11:32:25.441087 Write leveling (Byte 1): 29 => 29
1460 11:32:25.444097 DramcWriteLeveling(PI) end<-----
1461 11:32:25.444479
1462 11:32:25.444769 ==
1463 11:32:25.447470 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 11:32:25.450994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 11:32:25.451380 ==
1466 11:32:25.453870 [Gating] SW mode calibration
1467 11:32:25.460615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1468 11:32:25.467383 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1469 11:32:25.471056 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1470 11:32:25.474372 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1471 11:32:25.480740 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:32:25.483806 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:32:25.487115 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:32:25.493531 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:32:25.497543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:32:25.500482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:32:25.507354 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:32:25.510983 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:32:25.513318 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:32:25.520360 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:32:25.523271 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:32:25.526704 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:32:25.533581 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:32:25.536522 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:32:25.539869 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1486 11:32:25.546452 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1487 11:32:25.549744 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1488 11:32:25.553152 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:32:25.559687 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:32:25.563177 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:32:25.566717 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:32:25.573053 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:32:25.576055 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:32:25.579599 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1495 11:32:25.586344 0 9 8 | B1->B0 | 2828 3232 | 1 0 | (0 0) (0 0)
1496 11:32:25.589592 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 11:32:25.592875 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 11:32:25.599287 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 11:32:25.602925 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 11:32:25.606040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 11:32:25.613872 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1502 11:32:25.615840 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1503 11:32:25.619181 0 10 8 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
1504 11:32:25.626082 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:32:25.628943 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:32:25.632607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:32:25.639172 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:32:25.642485 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:32:25.645906 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:32:25.652392 0 11 4 | B1->B0 | 2525 2c2c | 1 0 | (0 0) (0 0)
1511 11:32:25.655491 0 11 8 | B1->B0 | 3939 3c3c | 0 0 | (0 0) (0 0)
1512 11:32:25.658405 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 11:32:25.665141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 11:32:25.668531 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 11:32:25.672397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 11:32:25.678765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 11:32:25.681815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 11:32:25.684840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1519 11:32:25.691654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:32:25.694870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:32:25.698242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:32:25.704664 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 11:32:25.708581 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 11:32:25.712184 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 11:32:25.718047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 11:32:25.721529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 11:32:25.724458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 11:32:25.731035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 11:32:25.734513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 11:32:25.738016 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 11:32:25.744678 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 11:32:25.747655 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 11:32:25.750947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 11:32:25.757793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1535 11:32:25.761420 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1536 11:32:25.764359 Total UI for P1: 0, mck2ui 16
1537 11:32:25.767776 best dqsien dly found for B0: ( 0, 14, 4)
1538 11:32:25.771038 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 11:32:25.774594 Total UI for P1: 0, mck2ui 16
1540 11:32:25.777563 best dqsien dly found for B1: ( 0, 14, 6)
1541 11:32:25.780722 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1542 11:32:25.784086 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1543 11:32:25.784689
1544 11:32:25.787540 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1545 11:32:25.794317 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1546 11:32:25.794708 [Gating] SW calibration Done
1547 11:32:25.795004 ==
1548 11:32:25.797339 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 11:32:25.804491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 11:32:25.804892 ==
1551 11:32:25.805473 RX Vref Scan: 0
1552 11:32:25.805862
1553 11:32:25.808183 RX Vref 0 -> 0, step: 1
1554 11:32:25.808578
1555 11:32:25.810735 RX Delay -130 -> 252, step: 16
1556 11:32:25.813922 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1557 11:32:25.817131 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1558 11:32:25.820508 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1559 11:32:25.827574 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1560 11:32:25.830541 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1561 11:32:25.833659 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1562 11:32:25.837469 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1563 11:32:25.843599 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1564 11:32:25.846984 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1565 11:32:25.850235 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1566 11:32:25.853348 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1567 11:32:25.857008 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1568 11:32:25.863522 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1569 11:32:25.866839 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1570 11:32:25.870352 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1571 11:32:25.873766 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1572 11:32:25.874148 ==
1573 11:32:25.877149 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 11:32:25.880281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 11:32:25.883698 ==
1576 11:32:25.884091 DQS Delay:
1577 11:32:25.884413 DQS0 = 0, DQS1 = 0
1578 11:32:25.886907 DQM Delay:
1579 11:32:25.887287 DQM0 = 88, DQM1 = 79
1580 11:32:25.890507 DQ Delay:
1581 11:32:25.893291 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1582 11:32:25.896993 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1583 11:32:25.899823 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1584 11:32:25.903682 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1585 11:32:25.904064
1586 11:32:25.904398
1587 11:32:25.904673 ==
1588 11:32:25.906396 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:32:25.909705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:32:25.910094 ==
1591 11:32:25.910387
1592 11:32:25.910657
1593 11:32:25.913680 TX Vref Scan disable
1594 11:32:25.914063 == TX Byte 0 ==
1595 11:32:25.919841 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1596 11:32:25.922933 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1597 11:32:25.926290 == TX Byte 1 ==
1598 11:32:25.930309 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 11:32:25.933279 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 11:32:25.933671 ==
1601 11:32:25.936692 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 11:32:25.939889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 11:32:25.940350 ==
1604 11:32:25.954110 TX Vref=22, minBit 8, minWin=27, winSum=443
1605 11:32:25.957062 TX Vref=24, minBit 8, minWin=27, winSum=445
1606 11:32:25.960510 TX Vref=26, minBit 9, minWin=27, winSum=450
1607 11:32:25.963489 TX Vref=28, minBit 9, minWin=27, winSum=448
1608 11:32:25.966687 TX Vref=30, minBit 8, minWin=27, winSum=447
1609 11:32:25.973530 TX Vref=32, minBit 8, minWin=27, winSum=446
1610 11:32:25.976645 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 26
1611 11:32:25.976945
1612 11:32:25.980105 Final TX Range 1 Vref 26
1613 11:32:25.980325
1614 11:32:25.980483 ==
1615 11:32:25.983488 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 11:32:25.986801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 11:32:25.987062 ==
1618 11:32:25.990376
1619 11:32:25.990588
1620 11:32:25.990747 TX Vref Scan disable
1621 11:32:25.993619 == TX Byte 0 ==
1622 11:32:25.997145 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1623 11:32:26.003254 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1624 11:32:26.003541 == TX Byte 1 ==
1625 11:32:26.006468 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1626 11:32:26.013006 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1627 11:32:26.013212
1628 11:32:26.013369 [DATLAT]
1629 11:32:26.013516 Freq=800, CH1 RK0
1630 11:32:26.013659
1631 11:32:26.016307 DATLAT Default: 0xa
1632 11:32:26.019598 0, 0xFFFF, sum = 0
1633 11:32:26.019819 1, 0xFFFF, sum = 0
1634 11:32:26.023390 2, 0xFFFF, sum = 0
1635 11:32:26.023633 3, 0xFFFF, sum = 0
1636 11:32:26.026389 4, 0xFFFF, sum = 0
1637 11:32:26.026592 5, 0xFFFF, sum = 0
1638 11:32:26.029688 6, 0xFFFF, sum = 0
1639 11:32:26.029903 7, 0xFFFF, sum = 0
1640 11:32:26.033093 8, 0xFFFF, sum = 0
1641 11:32:26.033304 9, 0x0, sum = 1
1642 11:32:26.036351 10, 0x0, sum = 2
1643 11:32:26.036562 11, 0x0, sum = 3
1644 11:32:26.039704 12, 0x0, sum = 4
1645 11:32:26.039914 best_step = 10
1646 11:32:26.040077
1647 11:32:26.040227 ==
1648 11:32:26.042963 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 11:32:26.046176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 11:32:26.046387 ==
1651 11:32:26.049639 RX Vref Scan: 1
1652 11:32:26.049806
1653 11:32:26.052922 Set Vref Range= 32 -> 127
1654 11:32:26.053064
1655 11:32:26.053173 RX Vref 32 -> 127, step: 1
1656 11:32:26.053274
1657 11:32:26.056260 RX Delay -95 -> 252, step: 8
1658 11:32:26.056400
1659 11:32:26.059327 Set Vref, RX VrefLevel [Byte0]: 32
1660 11:32:26.063067 [Byte1]: 32
1661 11:32:26.066169
1662 11:32:26.066311 Set Vref, RX VrefLevel [Byte0]: 33
1663 11:32:26.070065 [Byte1]: 33
1664 11:32:26.073827
1665 11:32:26.073918 Set Vref, RX VrefLevel [Byte0]: 34
1666 11:32:26.077468 [Byte1]: 34
1667 11:32:26.081387
1668 11:32:26.081472 Set Vref, RX VrefLevel [Byte0]: 35
1669 11:32:26.084588 [Byte1]: 35
1670 11:32:26.088932
1671 11:32:26.089018 Set Vref, RX VrefLevel [Byte0]: 36
1672 11:32:26.092604 [Byte1]: 36
1673 11:32:26.096523
1674 11:32:26.096602 Set Vref, RX VrefLevel [Byte0]: 37
1675 11:32:26.100411 [Byte1]: 37
1676 11:32:26.104383
1677 11:32:26.104463 Set Vref, RX VrefLevel [Byte0]: 38
1678 11:32:26.107417 [Byte1]: 38
1679 11:32:26.111597
1680 11:32:26.111678 Set Vref, RX VrefLevel [Byte0]: 39
1681 11:32:26.118422 [Byte1]: 39
1682 11:32:26.118507
1683 11:32:26.121418 Set Vref, RX VrefLevel [Byte0]: 40
1684 11:32:26.124983 [Byte1]: 40
1685 11:32:26.125059
1686 11:32:26.128289 Set Vref, RX VrefLevel [Byte0]: 41
1687 11:32:26.131166 [Byte1]: 41
1688 11:32:26.131245
1689 11:32:26.134535 Set Vref, RX VrefLevel [Byte0]: 42
1690 11:32:26.137818 [Byte1]: 42
1691 11:32:26.142273
1692 11:32:26.142357 Set Vref, RX VrefLevel [Byte0]: 43
1693 11:32:26.145986 [Byte1]: 43
1694 11:32:26.149682
1695 11:32:26.149762 Set Vref, RX VrefLevel [Byte0]: 44
1696 11:32:26.153265 [Byte1]: 44
1697 11:32:26.157191
1698 11:32:26.157275 Set Vref, RX VrefLevel [Byte0]: 45
1699 11:32:26.160586 [Byte1]: 45
1700 11:32:26.165378
1701 11:32:26.165462 Set Vref, RX VrefLevel [Byte0]: 46
1702 11:32:26.168471 [Byte1]: 46
1703 11:32:26.172345
1704 11:32:26.172432 Set Vref, RX VrefLevel [Byte0]: 47
1705 11:32:26.175682 [Byte1]: 47
1706 11:32:26.180163
1707 11:32:26.180255 Set Vref, RX VrefLevel [Byte0]: 48
1708 11:32:26.183701 [Byte1]: 48
1709 11:32:26.188149
1710 11:32:26.188226 Set Vref, RX VrefLevel [Byte0]: 49
1711 11:32:26.191291 [Byte1]: 49
1712 11:32:26.195184
1713 11:32:26.195259 Set Vref, RX VrefLevel [Byte0]: 50
1714 11:32:26.198350 [Byte1]: 50
1715 11:32:26.202586
1716 11:32:26.202662 Set Vref, RX VrefLevel [Byte0]: 51
1717 11:32:26.206375 [Byte1]: 51
1718 11:32:26.210709
1719 11:32:26.210788 Set Vref, RX VrefLevel [Byte0]: 52
1720 11:32:26.216907 [Byte1]: 52
1721 11:32:26.216997
1722 11:32:26.220227 Set Vref, RX VrefLevel [Byte0]: 53
1723 11:32:26.223395 [Byte1]: 53
1724 11:32:26.223503
1725 11:32:26.227116 Set Vref, RX VrefLevel [Byte0]: 54
1726 11:32:26.230152 [Byte1]: 54
1727 11:32:26.230257
1728 11:32:26.233638 Set Vref, RX VrefLevel [Byte0]: 55
1729 11:32:26.237002 [Byte1]: 55
1730 11:32:26.240685
1731 11:32:26.240812 Set Vref, RX VrefLevel [Byte0]: 56
1732 11:32:26.244502 [Byte1]: 56
1733 11:32:26.248398
1734 11:32:26.248564 Set Vref, RX VrefLevel [Byte0]: 57
1735 11:32:26.251794 [Byte1]: 57
1736 11:32:26.256125
1737 11:32:26.256311 Set Vref, RX VrefLevel [Byte0]: 58
1738 11:32:26.259933 [Byte1]: 58
1739 11:32:26.264555
1740 11:32:26.264843 Set Vref, RX VrefLevel [Byte0]: 59
1741 11:32:26.267118 [Byte1]: 59
1742 11:32:26.271766
1743 11:32:26.272151 Set Vref, RX VrefLevel [Byte0]: 60
1744 11:32:26.274714 [Byte1]: 60
1745 11:32:26.279176
1746 11:32:26.279584 Set Vref, RX VrefLevel [Byte0]: 61
1747 11:32:26.282339 [Byte1]: 61
1748 11:32:26.286984
1749 11:32:26.287395 Set Vref, RX VrefLevel [Byte0]: 62
1750 11:32:26.290081 [Byte1]: 62
1751 11:32:26.294186
1752 11:32:26.294574 Set Vref, RX VrefLevel [Byte0]: 63
1753 11:32:26.297874 [Byte1]: 63
1754 11:32:26.302388
1755 11:32:26.302776 Set Vref, RX VrefLevel [Byte0]: 64
1756 11:32:26.305200 [Byte1]: 64
1757 11:32:26.309730
1758 11:32:26.310118 Set Vref, RX VrefLevel [Byte0]: 65
1759 11:32:26.312840 [Byte1]: 65
1760 11:32:26.317139
1761 11:32:26.317578 Set Vref, RX VrefLevel [Byte0]: 66
1762 11:32:26.320331 [Byte1]: 66
1763 11:32:26.324843
1764 11:32:26.325272 Set Vref, RX VrefLevel [Byte0]: 67
1765 11:32:26.328283 [Byte1]: 67
1766 11:32:26.332395
1767 11:32:26.332813 Set Vref, RX VrefLevel [Byte0]: 68
1768 11:32:26.335698 [Byte1]: 68
1769 11:32:26.340387
1770 11:32:26.340816 Set Vref, RX VrefLevel [Byte0]: 69
1771 11:32:26.343596 [Byte1]: 69
1772 11:32:26.347841
1773 11:32:26.348417 Set Vref, RX VrefLevel [Byte0]: 70
1774 11:32:26.351067 [Byte1]: 70
1775 11:32:26.354929
1776 11:32:26.355327 Set Vref, RX VrefLevel [Byte0]: 71
1777 11:32:26.358459 [Byte1]: 71
1778 11:32:26.362828
1779 11:32:26.363225 Set Vref, RX VrefLevel [Byte0]: 72
1780 11:32:26.366352 [Byte1]: 72
1781 11:32:26.370497
1782 11:32:26.370925 Set Vref, RX VrefLevel [Byte0]: 73
1783 11:32:26.373398 [Byte1]: 73
1784 11:32:26.377873
1785 11:32:26.378105 Set Vref, RX VrefLevel [Byte0]: 74
1786 11:32:26.381549 [Byte1]: 74
1787 11:32:26.385451
1788 11:32:26.385641 Set Vref, RX VrefLevel [Byte0]: 75
1789 11:32:26.389035 [Byte1]: 75
1790 11:32:26.393393
1791 11:32:26.393544 Set Vref, RX VrefLevel [Byte0]: 76
1792 11:32:26.396414 [Byte1]: 76
1793 11:32:26.400691
1794 11:32:26.400831 Set Vref, RX VrefLevel [Byte0]: 77
1795 11:32:26.403618 [Byte1]: 77
1796 11:32:26.407906
1797 11:32:26.408037 Set Vref, RX VrefLevel [Byte0]: 78
1798 11:32:26.414397 [Byte1]: 78
1799 11:32:26.414495
1800 11:32:26.417715 Final RX Vref Byte 0 = 56 to rank0
1801 11:32:26.421809 Final RX Vref Byte 1 = 66 to rank0
1802 11:32:26.424771 Final RX Vref Byte 0 = 56 to rank1
1803 11:32:26.427676 Final RX Vref Byte 1 = 66 to rank1==
1804 11:32:26.430917 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 11:32:26.434219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 11:32:26.434318 ==
1807 11:32:26.434402 DQS Delay:
1808 11:32:26.438147 DQS0 = 0, DQS1 = 0
1809 11:32:26.438244 DQM Delay:
1810 11:32:26.441192 DQM0 = 86, DQM1 = 78
1811 11:32:26.441281 DQ Delay:
1812 11:32:26.444897 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1813 11:32:26.448010 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1814 11:32:26.451251 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1815 11:32:26.454463 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1816 11:32:26.454582
1817 11:32:26.454696
1818 11:32:26.460884 [DQSOSCAuto] RK0, (LSB)MR18= 0x3621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1819 11:32:26.464354 CH1 RK0: MR19=606, MR18=3621
1820 11:32:26.471009 CH1_RK0: MR19=0x606, MR18=0x3621, DQSOSC=396, MR23=63, INC=94, DEC=62
1821 11:32:26.471167
1822 11:32:26.474432 ----->DramcWriteLeveling(PI) begin...
1823 11:32:26.474607 ==
1824 11:32:26.477694 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 11:32:26.481270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 11:32:26.484072 ==
1827 11:32:26.484314 Write leveling (Byte 0): 26 => 26
1828 11:32:26.487792 Write leveling (Byte 1): 30 => 30
1829 11:32:26.490773 DramcWriteLeveling(PI) end<-----
1830 11:32:26.491008
1831 11:32:26.491191 ==
1832 11:32:26.494614 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 11:32:26.501026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:32:26.501421 ==
1835 11:32:26.501723 [Gating] SW mode calibration
1836 11:32:26.511046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 11:32:26.514050 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 11:32:26.520896 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1839 11:32:26.524205 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1840 11:32:26.527760 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:32:26.533810 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:32:26.537352 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:32:26.540828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:32:26.547128 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:32:26.550622 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:32:26.553844 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:32:26.560214 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:32:26.563882 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:32:26.567201 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:32:26.573488 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:32:26.576596 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:32:26.580035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:32:26.586484 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:32:26.590016 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:32:26.593564 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 11:32:26.599768 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1857 11:32:26.603504 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:32:26.606564 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:32:26.612948 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:32:26.616421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:32:26.619870 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:32:26.626726 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:32:26.629733 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:32:26.633471 0 9 8 | B1->B0 | 3131 2525 | 1 0 | (1 1) (0 0)
1865 11:32:26.639650 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 11:32:26.643228 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 11:32:26.646349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 11:32:26.653240 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 11:32:26.656281 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 11:32:26.659313 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 11:32:26.662943 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1872 11:32:26.669164 0 10 8 | B1->B0 | 2525 2626 | 0 1 | (1 0) (1 0)
1873 11:32:26.672562 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:32:26.676157 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:32:26.682927 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:32:26.686037 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:32:26.689312 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:32:26.695730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:32:26.698896 0 11 4 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
1880 11:32:26.702604 0 11 8 | B1->B0 | 4141 3a3a | 1 0 | (1 1) (0 0)
1881 11:32:26.709619 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 11:32:26.712296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 11:32:26.715735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 11:32:26.722366 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 11:32:26.725729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 11:32:26.728966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 11:32:26.735739 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1888 11:32:26.739453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:32:26.742411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:32:26.748523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 11:32:26.751941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 11:32:26.755037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 11:32:26.761762 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 11:32:26.765328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 11:32:26.768837 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 11:32:26.775469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 11:32:26.778673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:32:26.781754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:32:26.788336 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:32:26.791724 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:32:26.795081 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:32:26.801801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:32:26.805295 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1904 11:32:26.808219 Total UI for P1: 0, mck2ui 16
1905 11:32:26.811748 best dqsien dly found for B1: ( 0, 14, 2)
1906 11:32:26.815240 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 11:32:26.818307 Total UI for P1: 0, mck2ui 16
1908 11:32:26.821471 best dqsien dly found for B0: ( 0, 14, 4)
1909 11:32:26.825485 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1910 11:32:26.828296 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1911 11:32:26.828681
1912 11:32:26.831540 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1913 11:32:26.838429 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1914 11:32:26.838828 [Gating] SW calibration Done
1915 11:32:26.839178 ==
1916 11:32:26.841957 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 11:32:26.848459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 11:32:26.848875 ==
1919 11:32:26.849357 RX Vref Scan: 0
1920 11:32:26.849919
1921 11:32:26.851407 RX Vref 0 -> 0, step: 1
1922 11:32:26.851885
1923 11:32:26.855060 RX Delay -130 -> 252, step: 16
1924 11:32:26.858404 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1925 11:32:26.861752 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1926 11:32:26.864830 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1927 11:32:26.871324 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1928 11:32:26.874440 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1929 11:32:26.878425 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1930 11:32:26.881728 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1931 11:32:26.884402 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1932 11:32:26.891481 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1933 11:32:26.894847 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1934 11:32:26.897874 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1935 11:32:26.901285 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1936 11:32:26.907682 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1937 11:32:26.911149 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1938 11:32:26.914306 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1939 11:32:26.917450 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1940 11:32:26.918009 ==
1941 11:32:26.921043 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 11:32:26.927870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 11:32:26.928252 ==
1944 11:32:26.928546 DQS Delay:
1945 11:32:26.928816 DQS0 = 0, DQS1 = 0
1946 11:32:26.931366 DQM Delay:
1947 11:32:26.931800 DQM0 = 87, DQM1 = 79
1948 11:32:26.935101 DQ Delay:
1949 11:32:26.935531 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1950 11:32:26.937965 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1951 11:32:26.944440 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1952 11:32:26.947609 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1953 11:32:26.947994
1954 11:32:26.948294
1955 11:32:26.948568 ==
1956 11:32:26.950693 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:32:26.954105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:32:26.954658 ==
1959 11:32:26.955164
1960 11:32:26.955641
1961 11:32:26.957569 TX Vref Scan disable
1962 11:32:26.958065 == TX Byte 0 ==
1963 11:32:26.964196 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 11:32:26.967825 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 11:32:26.970783 == TX Byte 1 ==
1966 11:32:26.974108 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1967 11:32:26.977300 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1968 11:32:26.977792 ==
1969 11:32:26.980711 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 11:32:26.983906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 11:32:26.984395 ==
1972 11:32:26.998245 TX Vref=22, minBit 8, minWin=26, winSum=442
1973 11:32:27.001934 TX Vref=24, minBit 8, minWin=27, winSum=447
1974 11:32:27.004819 TX Vref=26, minBit 8, minWin=27, winSum=449
1975 11:32:27.008424 TX Vref=28, minBit 8, minWin=27, winSum=451
1976 11:32:27.011868 TX Vref=30, minBit 8, minWin=27, winSum=451
1977 11:32:27.018454 TX Vref=32, minBit 8, minWin=27, winSum=449
1978 11:32:27.021758 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1979 11:32:27.022257
1980 11:32:27.024590 Final TX Range 1 Vref 28
1981 11:32:27.025081
1982 11:32:27.025536 ==
1983 11:32:27.028372 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 11:32:27.031527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 11:32:27.032012 ==
1986 11:32:27.034656
1987 11:32:27.035132
1988 11:32:27.035624 TX Vref Scan disable
1989 11:32:27.038384 == TX Byte 0 ==
1990 11:32:27.041782 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1991 11:32:27.048247 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1992 11:32:27.048733 == TX Byte 1 ==
1993 11:32:27.051972 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 11:32:27.057985 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 11:32:27.058384
1996 11:32:27.058782 [DATLAT]
1997 11:32:27.059158 Freq=800, CH1 RK1
1998 11:32:27.059562
1999 11:32:27.061640 DATLAT Default: 0xa
2000 11:32:27.062038 0, 0xFFFF, sum = 0
2001 11:32:27.064703 1, 0xFFFF, sum = 0
2002 11:32:27.068169 2, 0xFFFF, sum = 0
2003 11:32:27.068576 3, 0xFFFF, sum = 0
2004 11:32:27.071482 4, 0xFFFF, sum = 0
2005 11:32:27.071905 5, 0xFFFF, sum = 0
2006 11:32:27.074541 6, 0xFFFF, sum = 0
2007 11:32:27.074948 7, 0xFFFF, sum = 0
2008 11:32:27.077921 8, 0xFFFF, sum = 0
2009 11:32:27.078385 9, 0x0, sum = 1
2010 11:32:27.081314 10, 0x0, sum = 2
2011 11:32:27.081719 11, 0x0, sum = 3
2012 11:32:27.082121 12, 0x0, sum = 4
2013 11:32:27.084771 best_step = 10
2014 11:32:27.085167
2015 11:32:27.085560 ==
2016 11:32:27.088284 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 11:32:27.091350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 11:32:27.091885 ==
2019 11:32:27.094668 RX Vref Scan: 0
2020 11:32:27.095066
2021 11:32:27.095486 RX Vref 0 -> 0, step: 1
2022 11:32:27.097694
2023 11:32:27.098093 RX Delay -95 -> 252, step: 8
2024 11:32:27.104667 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2025 11:32:27.108406 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2026 11:32:27.111761 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2027 11:32:27.114982 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2028 11:32:27.118453 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2029 11:32:27.124883 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2030 11:32:27.128494 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2031 11:32:27.131778 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2032 11:32:27.135040 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2033 11:32:27.138403 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2034 11:32:27.144923 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2035 11:32:27.148253 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2036 11:32:27.151321 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2037 11:32:27.155046 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2038 11:32:27.161649 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2039 11:32:27.164572 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2040 11:32:27.164964 ==
2041 11:32:27.168125 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 11:32:27.171358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 11:32:27.171789 ==
2044 11:32:27.172095 DQS Delay:
2045 11:32:27.174647 DQS0 = 0, DQS1 = 0
2046 11:32:27.175035 DQM Delay:
2047 11:32:27.178295 DQM0 = 87, DQM1 = 78
2048 11:32:27.178831 DQ Delay:
2049 11:32:27.181459 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2050 11:32:27.184722 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2051 11:32:27.187930 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2052 11:32:27.191306 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2053 11:32:27.191817
2054 11:32:27.192267
2055 11:32:27.201461 [DQSOSCAuto] RK1, (LSB)MR18= 0x1710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2056 11:32:27.201856 CH1 RK1: MR19=606, MR18=1710
2057 11:32:27.208038 CH1_RK1: MR19=0x606, MR18=0x1710, DQSOSC=404, MR23=63, INC=90, DEC=60
2058 11:32:27.211143 [RxdqsGatingPostProcess] freq 800
2059 11:32:27.217926 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2060 11:32:27.221393 Pre-setting of DQS Precalculation
2061 11:32:27.224236 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2062 11:32:27.230854 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2063 11:32:27.240937 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2064 11:32:27.241326
2065 11:32:27.241625
2066 11:32:27.244177 [Calibration Summary] 1600 Mbps
2067 11:32:27.244569 CH 0, Rank 0
2068 11:32:27.247340 SW Impedance : PASS
2069 11:32:27.247767 DUTY Scan : NO K
2070 11:32:27.251065 ZQ Calibration : PASS
2071 11:32:27.254095 Jitter Meter : NO K
2072 11:32:27.254484 CBT Training : PASS
2073 11:32:27.257744 Write leveling : PASS
2074 11:32:27.258131 RX DQS gating : PASS
2075 11:32:27.261115 RX DQ/DQS(RDDQC) : PASS
2076 11:32:27.264560 TX DQ/DQS : PASS
2077 11:32:27.264950 RX DATLAT : PASS
2078 11:32:27.267558 RX DQ/DQS(Engine): PASS
2079 11:32:27.270754 TX OE : NO K
2080 11:32:27.271143 All Pass.
2081 11:32:27.271474
2082 11:32:27.271765 CH 0, Rank 1
2083 11:32:27.274335 SW Impedance : PASS
2084 11:32:27.277887 DUTY Scan : NO K
2085 11:32:27.278277 ZQ Calibration : PASS
2086 11:32:27.280958 Jitter Meter : NO K
2087 11:32:27.284457 CBT Training : PASS
2088 11:32:27.284844 Write leveling : PASS
2089 11:32:27.287500 RX DQS gating : PASS
2090 11:32:27.290950 RX DQ/DQS(RDDQC) : PASS
2091 11:32:27.291334 TX DQ/DQS : PASS
2092 11:32:27.294326 RX DATLAT : PASS
2093 11:32:27.297306 RX DQ/DQS(Engine): PASS
2094 11:32:27.297694 TX OE : NO K
2095 11:32:27.300651 All Pass.
2096 11:32:27.301037
2097 11:32:27.301370 CH 1, Rank 0
2098 11:32:27.304156 SW Impedance : PASS
2099 11:32:27.304545 DUTY Scan : NO K
2100 11:32:27.307385 ZQ Calibration : PASS
2101 11:32:27.310652 Jitter Meter : NO K
2102 11:32:27.311041 CBT Training : PASS
2103 11:32:27.313887 Write leveling : PASS
2104 11:32:27.314276 RX DQS gating : PASS
2105 11:32:27.317387 RX DQ/DQS(RDDQC) : PASS
2106 11:32:27.321251 TX DQ/DQS : PASS
2107 11:32:27.321763 RX DATLAT : PASS
2108 11:32:27.324152 RX DQ/DQS(Engine): PASS
2109 11:32:27.327270 TX OE : NO K
2110 11:32:27.327726 All Pass.
2111 11:32:27.328129
2112 11:32:27.328509 CH 1, Rank 1
2113 11:32:27.330658 SW Impedance : PASS
2114 11:32:27.334165 DUTY Scan : NO K
2115 11:32:27.334567 ZQ Calibration : PASS
2116 11:32:27.337120 Jitter Meter : NO K
2117 11:32:27.340249 CBT Training : PASS
2118 11:32:27.340651 Write leveling : PASS
2119 11:32:27.343873 RX DQS gating : PASS
2120 11:32:27.346976 RX DQ/DQS(RDDQC) : PASS
2121 11:32:27.347362 TX DQ/DQS : PASS
2122 11:32:27.350528 RX DATLAT : PASS
2123 11:32:27.353896 RX DQ/DQS(Engine): PASS
2124 11:32:27.354284 TX OE : NO K
2125 11:32:27.357043 All Pass.
2126 11:32:27.357430
2127 11:32:27.357730 DramC Write-DBI off
2128 11:32:27.360272 PER_BANK_REFRESH: Hybrid Mode
2129 11:32:27.360666 TX_TRACKING: ON
2130 11:32:27.363631 [GetDramInforAfterCalByMRR] Vendor 6.
2131 11:32:27.370481 [GetDramInforAfterCalByMRR] Revision 606.
2132 11:32:27.373463 [GetDramInforAfterCalByMRR] Revision 2 0.
2133 11:32:27.373945 MR0 0x3b3b
2134 11:32:27.374363 MR8 0x5151
2135 11:32:27.376766 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 11:32:27.377125
2137 11:32:27.380253 MR0 0x3b3b
2138 11:32:27.380526 MR8 0x5151
2139 11:32:27.383688 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 11:32:27.383965
2141 11:32:27.393470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2142 11:32:27.396611 [FAST_K] Save calibration result to emmc
2143 11:32:27.399835 [FAST_K] Save calibration result to emmc
2144 11:32:27.403229 dram_init: config_dvfs: 1
2145 11:32:27.406702 dramc_set_vcore_voltage set vcore to 662500
2146 11:32:27.410112 Read voltage for 1200, 2
2147 11:32:27.410408 Vio18 = 0
2148 11:32:27.410694 Vcore = 662500
2149 11:32:27.413234 Vdram = 0
2150 11:32:27.413521 Vddq = 0
2151 11:32:27.413805 Vmddr = 0
2152 11:32:27.420193 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2153 11:32:27.423204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2154 11:32:27.426546 MEM_TYPE=3, freq_sel=15
2155 11:32:27.429804 sv_algorithm_assistance_LP4_1600
2156 11:32:27.433104 ============ PULL DRAM RESETB DOWN ============
2157 11:32:27.436656 ========== PULL DRAM RESETB DOWN end =========
2158 11:32:27.442895 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2159 11:32:27.446718 ===================================
2160 11:32:27.447238 LPDDR4 DRAM CONFIGURATION
2161 11:32:27.449548 ===================================
2162 11:32:27.453089 EX_ROW_EN[0] = 0x0
2163 11:32:27.456565 EX_ROW_EN[1] = 0x0
2164 11:32:27.456948 LP4Y_EN = 0x0
2165 11:32:27.459778 WORK_FSP = 0x0
2166 11:32:27.460158 WL = 0x4
2167 11:32:27.462800 RL = 0x4
2168 11:32:27.463283 BL = 0x2
2169 11:32:27.466355 RPST = 0x0
2170 11:32:27.466830 RD_PRE = 0x0
2171 11:32:27.469534 WR_PRE = 0x1
2172 11:32:27.470026 WR_PST = 0x0
2173 11:32:27.473389 DBI_WR = 0x0
2174 11:32:27.473860 DBI_RD = 0x0
2175 11:32:27.476285 OTF = 0x1
2176 11:32:27.479615 ===================================
2177 11:32:27.483095 ===================================
2178 11:32:27.483664 ANA top config
2179 11:32:27.486516 ===================================
2180 11:32:27.489595 DLL_ASYNC_EN = 0
2181 11:32:27.492771 ALL_SLAVE_EN = 0
2182 11:32:27.496110 NEW_RANK_MODE = 1
2183 11:32:27.496513 DLL_IDLE_MODE = 1
2184 11:32:27.499768 LP45_APHY_COMB_EN = 1
2185 11:32:27.502783 TX_ODT_DIS = 1
2186 11:32:27.505960 NEW_8X_MODE = 1
2187 11:32:27.509588 ===================================
2188 11:32:27.513150 ===================================
2189 11:32:27.516071 data_rate = 2400
2190 11:32:27.516473 CKR = 1
2191 11:32:27.519683 DQ_P2S_RATIO = 8
2192 11:32:27.522518 ===================================
2193 11:32:27.526227 CA_P2S_RATIO = 8
2194 11:32:27.529374 DQ_CA_OPEN = 0
2195 11:32:27.532872 DQ_SEMI_OPEN = 0
2196 11:32:27.535791 CA_SEMI_OPEN = 0
2197 11:32:27.536176 CA_FULL_RATE = 0
2198 11:32:27.539190 DQ_CKDIV4_EN = 0
2199 11:32:27.542751 CA_CKDIV4_EN = 0
2200 11:32:27.546053 CA_PREDIV_EN = 0
2201 11:32:27.549048 PH8_DLY = 17
2202 11:32:27.552603 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2203 11:32:27.552986 DQ_AAMCK_DIV = 4
2204 11:32:27.555694 CA_AAMCK_DIV = 4
2205 11:32:27.559382 CA_ADMCK_DIV = 4
2206 11:32:27.562745 DQ_TRACK_CA_EN = 0
2207 11:32:27.566234 CA_PICK = 1200
2208 11:32:27.569056 CA_MCKIO = 1200
2209 11:32:27.572506 MCKIO_SEMI = 0
2210 11:32:27.575482 PLL_FREQ = 2366
2211 11:32:27.575869 DQ_UI_PI_RATIO = 32
2212 11:32:27.578963 CA_UI_PI_RATIO = 0
2213 11:32:27.581982 ===================================
2214 11:32:27.585830 ===================================
2215 11:32:27.588797 memory_type:LPDDR4
2216 11:32:27.592577 GP_NUM : 10
2217 11:32:27.592962 SRAM_EN : 1
2218 11:32:27.595293 MD32_EN : 0
2219 11:32:27.599287 ===================================
2220 11:32:27.599749 [ANA_INIT] >>>>>>>>>>>>>>
2221 11:32:27.601944 <<<<<< [CONFIGURE PHASE]: ANA_TX
2222 11:32:27.605413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2223 11:32:27.608814 ===================================
2224 11:32:27.612099 data_rate = 2400,PCW = 0X5b00
2225 11:32:27.615588 ===================================
2226 11:32:27.618495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2227 11:32:27.625213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2228 11:32:27.631911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 11:32:27.635354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2230 11:32:27.638258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2231 11:32:27.641704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2232 11:32:27.644930 [ANA_INIT] flow start
2233 11:32:27.645319 [ANA_INIT] PLL >>>>>>>>
2234 11:32:27.648679 [ANA_INIT] PLL <<<<<<<<
2235 11:32:27.651677 [ANA_INIT] MIDPI >>>>>>>>
2236 11:32:27.652065 [ANA_INIT] MIDPI <<<<<<<<
2237 11:32:27.654954 [ANA_INIT] DLL >>>>>>>>
2238 11:32:27.658253 [ANA_INIT] DLL <<<<<<<<
2239 11:32:27.658639 [ANA_INIT] flow end
2240 11:32:27.665018 ============ LP4 DIFF to SE enter ============
2241 11:32:27.668278 ============ LP4 DIFF to SE exit ============
2242 11:32:27.671736 [ANA_INIT] <<<<<<<<<<<<<
2243 11:32:27.674885 [Flow] Enable top DCM control >>>>>
2244 11:32:27.678091 [Flow] Enable top DCM control <<<<<
2245 11:32:27.678475 Enable DLL master slave shuffle
2246 11:32:27.685365 ==============================================================
2247 11:32:27.688306 Gating Mode config
2248 11:32:27.691665 ==============================================================
2249 11:32:27.695078 Config description:
2250 11:32:27.705115 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2251 11:32:27.711697 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2252 11:32:27.714859 SELPH_MODE 0: By rank 1: By Phase
2253 11:32:27.721507 ==============================================================
2254 11:32:27.724782 GAT_TRACK_EN = 1
2255 11:32:27.728417 RX_GATING_MODE = 2
2256 11:32:27.731347 RX_GATING_TRACK_MODE = 2
2257 11:32:27.734877 SELPH_MODE = 1
2258 11:32:27.735260 PICG_EARLY_EN = 1
2259 11:32:27.738423 VALID_LAT_VALUE = 1
2260 11:32:27.744952 ==============================================================
2261 11:32:27.748255 Enter into Gating configuration >>>>
2262 11:32:27.751527 Exit from Gating configuration <<<<
2263 11:32:27.755170 Enter into DVFS_PRE_config >>>>>
2264 11:32:27.764724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2265 11:32:27.767756 Exit from DVFS_PRE_config <<<<<
2266 11:32:27.771133 Enter into PICG configuration >>>>
2267 11:32:27.774469 Exit from PICG configuration <<<<
2268 11:32:27.777491 [RX_INPUT] configuration >>>>>
2269 11:32:27.780883 [RX_INPUT] configuration <<<<<
2270 11:32:27.784784 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2271 11:32:27.791014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2272 11:32:27.797787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 11:32:27.804054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 11:32:27.810706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 11:32:27.817318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 11:32:27.820728 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2277 11:32:27.824278 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2278 11:32:27.827199 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2279 11:32:27.833937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2280 11:32:27.837244 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2281 11:32:27.840232 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 11:32:27.843837 ===================================
2283 11:32:27.846827 LPDDR4 DRAM CONFIGURATION
2284 11:32:27.850311 ===================================
2285 11:32:27.850692 EX_ROW_EN[0] = 0x0
2286 11:32:27.853741 EX_ROW_EN[1] = 0x0
2287 11:32:27.856808 LP4Y_EN = 0x0
2288 11:32:27.857191 WORK_FSP = 0x0
2289 11:32:27.860400 WL = 0x4
2290 11:32:27.860782 RL = 0x4
2291 11:32:27.864049 BL = 0x2
2292 11:32:27.864430 RPST = 0x0
2293 11:32:27.866985 RD_PRE = 0x0
2294 11:32:27.867369 WR_PRE = 0x1
2295 11:32:27.870076 WR_PST = 0x0
2296 11:32:27.870458 DBI_WR = 0x0
2297 11:32:27.873371 DBI_RD = 0x0
2298 11:32:27.873757 OTF = 0x1
2299 11:32:27.876795 ===================================
2300 11:32:27.879995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2301 11:32:27.886943 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2302 11:32:27.890230 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 11:32:27.893397 ===================================
2304 11:32:27.897309 LPDDR4 DRAM CONFIGURATION
2305 11:32:27.900234 ===================================
2306 11:32:27.900626 EX_ROW_EN[0] = 0x10
2307 11:32:27.903328 EX_ROW_EN[1] = 0x0
2308 11:32:27.903883 LP4Y_EN = 0x0
2309 11:32:27.906935 WORK_FSP = 0x0
2310 11:32:27.907312 WL = 0x4
2311 11:32:27.910486 RL = 0x4
2312 11:32:27.916102 BL = 0x2
2313 11:32:27.916469 RPST = 0x0
2314 11:32:27.916930 RD_PRE = 0x0
2315 11:32:27.917098 WR_PRE = 0x1
2316 11:32:27.919649 WR_PST = 0x0
2317 11:32:27.919871 DBI_WR = 0x0
2318 11:32:27.922839 DBI_RD = 0x0
2319 11:32:27.923001 OTF = 0x1
2320 11:32:27.926650 ===================================
2321 11:32:27.933128 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2322 11:32:27.933250 ==
2323 11:32:27.936133 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 11:32:27.939643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2325 11:32:27.939750 ==
2326 11:32:27.942732 [Duty_Offset_Calibration]
2327 11:32:27.945996 B0:1 B1:-1 CA:0
2328 11:32:27.946087
2329 11:32:27.949235 [DutyScan_Calibration_Flow] k_type=0
2330 11:32:27.957668
2331 11:32:27.957757 ==CLK 0==
2332 11:32:27.960609 Final CLK duty delay cell = 0
2333 11:32:27.964044 [0] MAX Duty = 5094%(X100), DQS PI = 16
2334 11:32:27.967542 [0] MIN Duty = 4875%(X100), DQS PI = 8
2335 11:32:27.967641 [0] AVG Duty = 4984%(X100)
2336 11:32:27.970755
2337 11:32:27.974183 CH0 CLK Duty spec in!! Max-Min= 219%
2338 11:32:27.977210 [DutyScan_Calibration_Flow] ====Done====
2339 11:32:27.977333
2340 11:32:27.980792 [DutyScan_Calibration_Flow] k_type=1
2341 11:32:27.996063
2342 11:32:27.996245 ==DQS 0 ==
2343 11:32:27.999299 Final DQS duty delay cell = -4
2344 11:32:28.002727 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2345 11:32:28.006629 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2346 11:32:28.009886 [-4] AVG Duty = 4968%(X100)
2347 11:32:28.010246
2348 11:32:28.010513 ==DQS 1 ==
2349 11:32:28.013405 Final DQS duty delay cell = 0
2350 11:32:28.016383 [0] MAX Duty = 5124%(X100), DQS PI = 4
2351 11:32:28.019733 [0] MIN Duty = 5000%(X100), DQS PI = 22
2352 11:32:28.022947 [0] AVG Duty = 5062%(X100)
2353 11:32:28.023331
2354 11:32:28.026288 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2355 11:32:28.026673
2356 11:32:28.029688 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2357 11:32:28.032412 [DutyScan_Calibration_Flow] ====Done====
2358 11:32:28.032797
2359 11:32:28.035785 [DutyScan_Calibration_Flow] k_type=3
2360 11:32:28.053914
2361 11:32:28.054314 ==DQM 0 ==
2362 11:32:28.057104 Final DQM duty delay cell = 0
2363 11:32:28.060928 [0] MAX Duty = 5062%(X100), DQS PI = 22
2364 11:32:28.064003 [0] MIN Duty = 4875%(X100), DQS PI = 8
2365 11:32:28.067112 [0] AVG Duty = 4968%(X100)
2366 11:32:28.067537
2367 11:32:28.067843 ==DQM 1 ==
2368 11:32:28.070659 Final DQM duty delay cell = 4
2369 11:32:28.074249 [4] MAX Duty = 5187%(X100), DQS PI = 16
2370 11:32:28.077402 [4] MIN Duty = 4969%(X100), DQS PI = 26
2371 11:32:28.080617 [4] AVG Duty = 5078%(X100)
2372 11:32:28.081001
2373 11:32:28.083745 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2374 11:32:28.084129
2375 11:32:28.087178 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2376 11:32:28.090348 [DutyScan_Calibration_Flow] ====Done====
2377 11:32:28.090734
2378 11:32:28.093691 [DutyScan_Calibration_Flow] k_type=2
2379 11:32:28.110069
2380 11:32:28.110524 ==DQ 0 ==
2381 11:32:28.113109 Final DQ duty delay cell = 0
2382 11:32:28.116524 [0] MAX Duty = 5125%(X100), DQS PI = 20
2383 11:32:28.119930 [0] MIN Duty = 5000%(X100), DQS PI = 0
2384 11:32:28.120314 [0] AVG Duty = 5062%(X100)
2385 11:32:28.123179
2386 11:32:28.123602 ==DQ 1 ==
2387 11:32:28.126538 Final DQ duty delay cell = -4
2388 11:32:28.129720 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2389 11:32:28.132749 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2390 11:32:28.136125 [-4] AVG Duty = 4922%(X100)
2391 11:32:28.136512
2392 11:32:28.139534 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2393 11:32:28.139923
2394 11:32:28.142801 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2395 11:32:28.146396 [DutyScan_Calibration_Flow] ====Done====
2396 11:32:28.146822 ==
2397 11:32:28.149799 Dram Type= 6, Freq= 0, CH_1, rank 0
2398 11:32:28.152480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2399 11:32:28.152929 ==
2400 11:32:28.155948 [Duty_Offset_Calibration]
2401 11:32:28.156414 B0:-1 B1:1 CA:2
2402 11:32:28.156728
2403 11:32:28.159163 [DutyScan_Calibration_Flow] k_type=0
2404 11:32:28.170119
2405 11:32:28.170503 ==CLK 0==
2406 11:32:28.173075 Final CLK duty delay cell = 0
2407 11:32:28.176729 [0] MAX Duty = 5156%(X100), DQS PI = 6
2408 11:32:28.179596 [0] MIN Duty = 5000%(X100), DQS PI = 28
2409 11:32:28.179997 [0] AVG Duty = 5078%(X100)
2410 11:32:28.183204
2411 11:32:28.186767 CH1 CLK Duty spec in!! Max-Min= 156%
2412 11:32:28.190088 [DutyScan_Calibration_Flow] ====Done====
2413 11:32:28.190609
2414 11:32:28.193012 [DutyScan_Calibration_Flow] k_type=1
2415 11:32:28.209992
2416 11:32:28.210520 ==DQS 0 ==
2417 11:32:28.212697 Final DQS duty delay cell = 0
2418 11:32:28.215848 [0] MAX Duty = 5125%(X100), DQS PI = 18
2419 11:32:28.219293 [0] MIN Duty = 4875%(X100), DQS PI = 38
2420 11:32:28.222290 [0] AVG Duty = 5000%(X100)
2421 11:32:28.222809
2422 11:32:28.223241 ==DQS 1 ==
2423 11:32:28.225975 Final DQS duty delay cell = 0
2424 11:32:28.229379 [0] MAX Duty = 5094%(X100), DQS PI = 42
2425 11:32:28.232271 [0] MIN Duty = 4969%(X100), DQS PI = 26
2426 11:32:28.235724 [0] AVG Duty = 5031%(X100)
2427 11:32:28.236161
2428 11:32:28.238884 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2429 11:32:28.239324
2430 11:32:28.242361 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2431 11:32:28.245793 [DutyScan_Calibration_Flow] ====Done====
2432 11:32:28.246320
2433 11:32:28.248603 [DutyScan_Calibration_Flow] k_type=3
2434 11:32:28.264813
2435 11:32:28.265326 ==DQM 0 ==
2436 11:32:28.268528 Final DQM duty delay cell = -4
2437 11:32:28.271927 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2438 11:32:28.275129 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2439 11:32:28.278168 [-4] AVG Duty = 4937%(X100)
2440 11:32:28.278682
2441 11:32:28.279120 ==DQM 1 ==
2442 11:32:28.281877 Final DQM duty delay cell = 0
2443 11:32:28.284742 [0] MAX Duty = 5187%(X100), DQS PI = 34
2444 11:32:28.288516 [0] MIN Duty = 4969%(X100), DQS PI = 0
2445 11:32:28.291575 [0] AVG Duty = 5078%(X100)
2446 11:32:28.292097
2447 11:32:28.295065 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2448 11:32:28.295627
2449 11:32:28.298139 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2450 11:32:28.301296 [DutyScan_Calibration_Flow] ====Done====
2451 11:32:28.301734
2452 11:32:28.304830 [DutyScan_Calibration_Flow] k_type=2
2453 11:32:28.322139
2454 11:32:28.322651 ==DQ 0 ==
2455 11:32:28.325393 Final DQ duty delay cell = 0
2456 11:32:28.328330 [0] MAX Duty = 5156%(X100), DQS PI = 0
2457 11:32:28.331810 [0] MIN Duty = 4876%(X100), DQS PI = 40
2458 11:32:28.332255 [0] AVG Duty = 5016%(X100)
2459 11:32:28.332688
2460 11:32:28.335421 ==DQ 1 ==
2461 11:32:28.338436 Final DQ duty delay cell = 0
2462 11:32:28.341633 [0] MAX Duty = 5124%(X100), DQS PI = 42
2463 11:32:28.344718 [0] MIN Duty = 4969%(X100), DQS PI = 0
2464 11:32:28.345161 [0] AVG Duty = 5046%(X100)
2465 11:32:28.345593
2466 11:32:28.348149 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2467 11:32:28.352027
2468 11:32:28.354636 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2469 11:32:28.358124 [DutyScan_Calibration_Flow] ====Done====
2470 11:32:28.361370 nWR fixed to 30
2471 11:32:28.361804 [ModeRegInit_LP4] CH0 RK0
2472 11:32:28.365776 [ModeRegInit_LP4] CH0 RK1
2473 11:32:28.367695 [ModeRegInit_LP4] CH1 RK0
2474 11:32:28.371580 [ModeRegInit_LP4] CH1 RK1
2475 11:32:28.372084 match AC timing 7
2476 11:32:28.377970 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2477 11:32:28.381530 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2478 11:32:28.384821 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2479 11:32:28.391573 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2480 11:32:28.395404 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2481 11:32:28.395955 ==
2482 11:32:28.398087 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 11:32:28.401242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 11:32:28.401692 ==
2485 11:32:28.407748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 11:32:28.414757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 11:32:28.421511 [CA 0] Center 39 (9~70) winsize 62
2488 11:32:28.425144 [CA 1] Center 39 (9~70) winsize 62
2489 11:32:28.428482 [CA 2] Center 35 (5~66) winsize 62
2490 11:32:28.432019 [CA 3] Center 35 (5~65) winsize 61
2491 11:32:28.435250 [CA 4] Center 33 (3~64) winsize 62
2492 11:32:28.438651 [CA 5] Center 33 (4~63) winsize 60
2493 11:32:28.439187
2494 11:32:28.441658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 11:32:28.442174
2496 11:32:28.444530 [CATrainingPosCal] consider 1 rank data
2497 11:32:28.447970 u2DelayCellTimex100 = 270/100 ps
2498 11:32:28.451685 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2499 11:32:28.457998 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 11:32:28.461858 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 11:32:28.464724 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2502 11:32:28.467739 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2503 11:32:28.471552 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2504 11:32:28.472067
2505 11:32:28.474973 CA PerBit enable=1, Macro0, CA PI delay=33
2506 11:32:28.475699
2507 11:32:28.477976 [CBTSetCACLKResult] CA Dly = 33
2508 11:32:28.480902 CS Dly: 8 (0~39)
2509 11:32:28.481327 ==
2510 11:32:28.484642 Dram Type= 6, Freq= 0, CH_0, rank 1
2511 11:32:28.488238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 11:32:28.488766 ==
2513 11:32:28.494640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 11:32:28.497802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 11:32:28.507551 [CA 0] Center 39 (9~70) winsize 62
2516 11:32:28.510618 [CA 1] Center 39 (9~70) winsize 62
2517 11:32:28.513897 [CA 2] Center 35 (5~66) winsize 62
2518 11:32:28.517219 [CA 3] Center 34 (4~65) winsize 62
2519 11:32:28.520267 [CA 4] Center 33 (3~64) winsize 62
2520 11:32:28.524158 [CA 5] Center 33 (3~63) winsize 61
2521 11:32:28.524684
2522 11:32:28.527052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 11:32:28.527550
2524 11:32:28.530322 [CATrainingPosCal] consider 2 rank data
2525 11:32:28.533894 u2DelayCellTimex100 = 270/100 ps
2526 11:32:28.537389 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2527 11:32:28.543577 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 11:32:28.546730 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2529 11:32:28.550303 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2530 11:32:28.553406 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2531 11:32:28.556843 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2532 11:32:28.557286
2533 11:32:28.560129 CA PerBit enable=1, Macro0, CA PI delay=33
2534 11:32:28.560571
2535 11:32:28.563565 [CBTSetCACLKResult] CA Dly = 33
2536 11:32:28.567049 CS Dly: 9 (0~41)
2537 11:32:28.567615
2538 11:32:28.570059 ----->DramcWriteLeveling(PI) begin...
2539 11:32:28.570504 ==
2540 11:32:28.573904 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 11:32:28.576885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 11:32:28.577412 ==
2543 11:32:28.580252 Write leveling (Byte 0): 32 => 32
2544 11:32:28.583829 Write leveling (Byte 1): 32 => 32
2545 11:32:28.586596 DramcWriteLeveling(PI) end<-----
2546 11:32:28.587033
2547 11:32:28.587483 ==
2548 11:32:28.590429 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 11:32:28.593684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 11:32:28.594129 ==
2551 11:32:28.596900 [Gating] SW mode calibration
2552 11:32:28.603337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2553 11:32:28.609661 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2554 11:32:28.613295 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2555 11:32:28.616263 0 15 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2556 11:32:28.623036 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 11:32:28.626132 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 11:32:28.630027 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 11:32:28.636458 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 11:32:28.639530 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2561 11:32:28.642917 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2562 11:32:28.649650 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2563 11:32:28.653009 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2564 11:32:28.656157 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 11:32:28.662761 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 11:32:28.666408 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 11:32:28.669272 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 11:32:28.676125 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 11:32:28.679589 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
2570 11:32:28.683006 1 1 0 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2571 11:32:28.690120 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2572 11:32:28.692500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 11:32:28.695630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:32:28.702282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 11:32:28.705859 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 11:32:28.709235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 11:32:28.715671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 11:32:28.718817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2579 11:32:28.722334 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 11:32:28.729403 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 11:32:28.732900 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 11:32:28.735913 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 11:32:28.742347 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 11:32:28.745571 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 11:32:28.748574 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 11:32:28.751820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 11:32:28.759413 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 11:32:28.762073 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:32:28.765761 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:32:28.772346 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:32:28.776105 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:32:28.779074 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2593 11:32:28.785165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2594 11:32:28.788878 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2595 11:32:28.792159 Total UI for P1: 0, mck2ui 16
2596 11:32:28.795332 best dqsien dly found for B0: ( 1, 3, 26)
2597 11:32:28.798947 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 11:32:28.802185 Total UI for P1: 0, mck2ui 16
2599 11:32:28.805239 best dqsien dly found for B1: ( 1, 4, 0)
2600 11:32:28.808392 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2601 11:32:28.811756 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2602 11:32:28.812209
2603 11:32:28.818406 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2604 11:32:28.821724 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2605 11:32:28.825122 [Gating] SW calibration Done
2606 11:32:28.825548 ==
2607 11:32:28.828592 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 11:32:28.831663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 11:32:28.832093 ==
2610 11:32:28.832421 RX Vref Scan: 0
2611 11:32:28.832726
2612 11:32:28.835189 RX Vref 0 -> 0, step: 1
2613 11:32:28.835664
2614 11:32:28.838471 RX Delay -40 -> 252, step: 8
2615 11:32:28.841596 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2616 11:32:28.844714 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2617 11:32:28.851497 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2618 11:32:28.854735 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2619 11:32:28.858169 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2620 11:32:28.861644 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2621 11:32:28.864724 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2622 11:32:28.871858 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2623 11:32:28.874697 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2624 11:32:28.878465 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2625 11:32:28.881327 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2626 11:32:28.884571 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2627 11:32:28.891263 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2628 11:32:28.894778 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2629 11:32:28.898220 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2630 11:32:28.900867 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2631 11:32:28.901295 ==
2632 11:32:28.904377 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:32:28.911268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:32:28.911854 ==
2635 11:32:28.912236 DQS Delay:
2636 11:32:28.912545 DQS0 = 0, DQS1 = 0
2637 11:32:28.914313 DQM Delay:
2638 11:32:28.914737 DQM0 = 119, DQM1 = 106
2639 11:32:28.917431 DQ Delay:
2640 11:32:28.920974 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2641 11:32:28.924133 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2642 11:32:28.927848 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2643 11:32:28.931136 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2644 11:32:28.931698
2645 11:32:28.932032
2646 11:32:28.932335 ==
2647 11:32:28.934394 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 11:32:28.937614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 11:32:28.940865 ==
2650 11:32:28.941288
2651 11:32:28.941617
2652 11:32:28.941922 TX Vref Scan disable
2653 11:32:28.944008 == TX Byte 0 ==
2654 11:32:28.947591 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2655 11:32:28.950682 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2656 11:32:28.953844 == TX Byte 1 ==
2657 11:32:28.957692 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2658 11:32:28.960679 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2659 11:32:28.963971 ==
2660 11:32:28.964397 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 11:32:28.970820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 11:32:28.971320 ==
2663 11:32:28.981218 TX Vref=22, minBit 4, minWin=25, winSum=414
2664 11:32:28.984408 TX Vref=24, minBit 4, minWin=25, winSum=421
2665 11:32:28.987728 TX Vref=26, minBit 4, minWin=26, winSum=425
2666 11:32:28.991575 TX Vref=28, minBit 4, minWin=26, winSum=425
2667 11:32:28.994586 TX Vref=30, minBit 1, minWin=26, winSum=427
2668 11:32:29.001421 TX Vref=32, minBit 10, minWin=25, winSum=427
2669 11:32:29.005218 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2670 11:32:29.005719
2671 11:32:29.008370 Final TX Range 1 Vref 30
2672 11:32:29.008877
2673 11:32:29.009209 ==
2674 11:32:29.011147 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:32:29.014431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:32:29.017882 ==
2677 11:32:29.018385
2678 11:32:29.018729
2679 11:32:29.019037 TX Vref Scan disable
2680 11:32:29.021050 == TX Byte 0 ==
2681 11:32:29.024733 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2682 11:32:29.031248 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2683 11:32:29.031809 == TX Byte 1 ==
2684 11:32:29.034623 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2685 11:32:29.040933 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2686 11:32:29.041431
2687 11:32:29.041761 [DATLAT]
2688 11:32:29.042069 Freq=1200, CH0 RK0
2689 11:32:29.042366
2690 11:32:29.044324 DATLAT Default: 0xd
2691 11:32:29.044748 0, 0xFFFF, sum = 0
2692 11:32:29.047679 1, 0xFFFF, sum = 0
2693 11:32:29.048109 2, 0xFFFF, sum = 0
2694 11:32:29.051584 3, 0xFFFF, sum = 0
2695 11:32:29.054359 4, 0xFFFF, sum = 0
2696 11:32:29.054870 5, 0xFFFF, sum = 0
2697 11:32:29.058013 6, 0xFFFF, sum = 0
2698 11:32:29.058460 7, 0xFFFF, sum = 0
2699 11:32:29.061127 8, 0xFFFF, sum = 0
2700 11:32:29.061662 9, 0xFFFF, sum = 0
2701 11:32:29.064338 10, 0xFFFF, sum = 0
2702 11:32:29.064841 11, 0xFFFF, sum = 0
2703 11:32:29.067823 12, 0x0, sum = 1
2704 11:32:29.068324 13, 0x0, sum = 2
2705 11:32:29.071495 14, 0x0, sum = 3
2706 11:32:29.072006 15, 0x0, sum = 4
2707 11:32:29.074403 best_step = 13
2708 11:32:29.074923
2709 11:32:29.075260 ==
2710 11:32:29.077786 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:32:29.081508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:32:29.082016 ==
2713 11:32:29.082376 RX Vref Scan: 1
2714 11:32:29.082697
2715 11:32:29.084292 Set Vref Range= 32 -> 127
2716 11:32:29.084716
2717 11:32:29.088063 RX Vref 32 -> 127, step: 1
2718 11:32:29.088631
2719 11:32:29.090667 RX Delay -21 -> 252, step: 4
2720 11:32:29.091089
2721 11:32:29.094179 Set Vref, RX VrefLevel [Byte0]: 32
2722 11:32:29.097512 [Byte1]: 32
2723 11:32:29.098010
2724 11:32:29.100917 Set Vref, RX VrefLevel [Byte0]: 33
2725 11:32:29.103938 [Byte1]: 33
2726 11:32:29.108003
2727 11:32:29.108453 Set Vref, RX VrefLevel [Byte0]: 34
2728 11:32:29.110970 [Byte1]: 34
2729 11:32:29.115905
2730 11:32:29.116405 Set Vref, RX VrefLevel [Byte0]: 35
2731 11:32:29.118971 [Byte1]: 35
2732 11:32:29.123622
2733 11:32:29.124117 Set Vref, RX VrefLevel [Byte0]: 36
2734 11:32:29.127100 [Byte1]: 36
2735 11:32:29.131533
2736 11:32:29.132026 Set Vref, RX VrefLevel [Byte0]: 37
2737 11:32:29.134802 [Byte1]: 37
2738 11:32:29.139536
2739 11:32:29.140030 Set Vref, RX VrefLevel [Byte0]: 38
2740 11:32:29.142591 [Byte1]: 38
2741 11:32:29.147123
2742 11:32:29.147587 Set Vref, RX VrefLevel [Byte0]: 39
2743 11:32:29.150558 [Byte1]: 39
2744 11:32:29.155553
2745 11:32:29.156230 Set Vref, RX VrefLevel [Byte0]: 40
2746 11:32:29.158386 [Byte1]: 40
2747 11:32:29.162788
2748 11:32:29.163210 Set Vref, RX VrefLevel [Byte0]: 41
2749 11:32:29.166227 [Byte1]: 41
2750 11:32:29.170878
2751 11:32:29.171300 Set Vref, RX VrefLevel [Byte0]: 42
2752 11:32:29.174071 [Byte1]: 42
2753 11:32:29.179034
2754 11:32:29.179541 Set Vref, RX VrefLevel [Byte0]: 43
2755 11:32:29.182215 [Byte1]: 43
2756 11:32:29.186569
2757 11:32:29.186992 Set Vref, RX VrefLevel [Byte0]: 44
2758 11:32:29.189868 [Byte1]: 44
2759 11:32:29.195020
2760 11:32:29.195315 Set Vref, RX VrefLevel [Byte0]: 45
2761 11:32:29.197932 [Byte1]: 45
2762 11:32:29.202701
2763 11:32:29.202942 Set Vref, RX VrefLevel [Byte0]: 46
2764 11:32:29.205739 [Byte1]: 46
2765 11:32:29.210651
2766 11:32:29.210797 Set Vref, RX VrefLevel [Byte0]: 47
2767 11:32:29.213962 [Byte1]: 47
2768 11:32:29.218388
2769 11:32:29.218772 Set Vref, RX VrefLevel [Byte0]: 48
2770 11:32:29.224633 [Byte1]: 48
2771 11:32:29.225016
2772 11:32:29.228055 Set Vref, RX VrefLevel [Byte0]: 49
2773 11:32:29.231749 [Byte1]: 49
2774 11:32:29.232130
2775 11:32:29.235045 Set Vref, RX VrefLevel [Byte0]: 50
2776 11:32:29.238245 [Byte1]: 50
2777 11:32:29.242606
2778 11:32:29.243114 Set Vref, RX VrefLevel [Byte0]: 51
2779 11:32:29.245447 [Byte1]: 51
2780 11:32:29.250144
2781 11:32:29.250581 Set Vref, RX VrefLevel [Byte0]: 52
2782 11:32:29.253850 [Byte1]: 52
2783 11:32:29.258136
2784 11:32:29.258604 Set Vref, RX VrefLevel [Byte0]: 53
2785 11:32:29.261245 [Byte1]: 53
2786 11:32:29.266162
2787 11:32:29.266763 Set Vref, RX VrefLevel [Byte0]: 54
2788 11:32:29.269199 [Byte1]: 54
2789 11:32:29.274789
2790 11:32:29.275181 Set Vref, RX VrefLevel [Byte0]: 55
2791 11:32:29.277434 [Byte1]: 55
2792 11:32:29.282050
2793 11:32:29.282697 Set Vref, RX VrefLevel [Byte0]: 56
2794 11:32:29.285352 [Byte1]: 56
2795 11:32:29.290202
2796 11:32:29.290599 Set Vref, RX VrefLevel [Byte0]: 57
2797 11:32:29.294014 [Byte1]: 57
2798 11:32:29.298051
2799 11:32:29.298554 Set Vref, RX VrefLevel [Byte0]: 58
2800 11:32:29.301147 [Byte1]: 58
2801 11:32:29.306085
2802 11:32:29.306591 Set Vref, RX VrefLevel [Byte0]: 59
2803 11:32:29.308835 [Byte1]: 59
2804 11:32:29.313582
2805 11:32:29.314086 Set Vref, RX VrefLevel [Byte0]: 60
2806 11:32:29.316802 [Byte1]: 60
2807 11:32:29.321776
2808 11:32:29.324884 Set Vref, RX VrefLevel [Byte0]: 61
2809 11:32:29.328378 [Byte1]: 61
2810 11:32:29.328903
2811 11:32:29.331575 Set Vref, RX VrefLevel [Byte0]: 62
2812 11:32:29.334638 [Byte1]: 62
2813 11:32:29.335148
2814 11:32:29.338479 Set Vref, RX VrefLevel [Byte0]: 63
2815 11:32:29.341679 [Byte1]: 63
2816 11:32:29.345441
2817 11:32:29.345877 Set Vref, RX VrefLevel [Byte0]: 64
2818 11:32:29.348850 [Byte1]: 64
2819 11:32:29.353140
2820 11:32:29.353559 Set Vref, RX VrefLevel [Byte0]: 65
2821 11:32:29.356774 [Byte1]: 65
2822 11:32:29.361330
2823 11:32:29.361813 Set Vref, RX VrefLevel [Byte0]: 66
2824 11:32:29.364618 [Byte1]: 66
2825 11:32:29.369275
2826 11:32:29.369767 Set Vref, RX VrefLevel [Byte0]: 67
2827 11:32:29.372865 [Byte1]: 67
2828 11:32:29.377764
2829 11:32:29.378186 Set Vref, RX VrefLevel [Byte0]: 68
2830 11:32:29.380066 [Byte1]: 68
2831 11:32:29.384771
2832 11:32:29.385190 Set Vref, RX VrefLevel [Byte0]: 69
2833 11:32:29.388601 [Byte1]: 69
2834 11:32:29.393379
2835 11:32:29.393878 Set Vref, RX VrefLevel [Byte0]: 70
2836 11:32:29.396033 [Byte1]: 70
2837 11:32:29.401040
2838 11:32:29.401517 Set Vref, RX VrefLevel [Byte0]: 71
2839 11:32:29.404779 [Byte1]: 71
2840 11:32:29.409461
2841 11:32:29.409974 Set Vref, RX VrefLevel [Byte0]: 72
2842 11:32:29.412353 [Byte1]: 72
2843 11:32:29.416550
2844 11:32:29.416971 Set Vref, RX VrefLevel [Byte0]: 73
2845 11:32:29.420159 [Byte1]: 73
2846 11:32:29.424869
2847 11:32:29.425363 Set Vref, RX VrefLevel [Byte0]: 74
2848 11:32:29.427958 [Byte1]: 74
2849 11:32:29.433172
2850 11:32:29.433595 Set Vref, RX VrefLevel [Byte0]: 75
2851 11:32:29.435915 [Byte1]: 75
2852 11:32:29.440231
2853 11:32:29.440703 Set Vref, RX VrefLevel [Byte0]: 76
2854 11:32:29.443569 [Byte1]: 76
2855 11:32:29.448396
2856 11:32:29.448814 Set Vref, RX VrefLevel [Byte0]: 77
2857 11:32:29.451916 [Byte1]: 77
2858 11:32:29.456617
2859 11:32:29.457115 Set Vref, RX VrefLevel [Byte0]: 78
2860 11:32:29.459791 [Byte1]: 78
2861 11:32:29.464672
2862 11:32:29.465244 Set Vref, RX VrefLevel [Byte0]: 79
2863 11:32:29.467928 [Byte1]: 79
2864 11:32:29.472744
2865 11:32:29.473242 Final RX Vref Byte 0 = 55 to rank0
2866 11:32:29.475658 Final RX Vref Byte 1 = 49 to rank0
2867 11:32:29.478921 Final RX Vref Byte 0 = 55 to rank1
2868 11:32:29.482863 Final RX Vref Byte 1 = 49 to rank1==
2869 11:32:29.485377 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 11:32:29.492308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 11:32:29.492746 ==
2872 11:32:29.493075 DQS Delay:
2873 11:32:29.493426 DQS0 = 0, DQS1 = 0
2874 11:32:29.495746 DQM Delay:
2875 11:32:29.496165 DQM0 = 118, DQM1 = 106
2876 11:32:29.499105 DQ Delay:
2877 11:32:29.502058 DQ0 =114, DQ1 =120, DQ2 =116, DQ3 =114
2878 11:32:29.505839 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2879 11:32:29.509029 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2880 11:32:29.511821 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2881 11:32:29.512260
2882 11:32:29.512684
2883 11:32:29.522174 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2884 11:32:29.522660 CH0 RK0: MR19=403, MR18=13FF
2885 11:32:29.528988 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2886 11:32:29.529485
2887 11:32:29.531781 ----->DramcWriteLeveling(PI) begin...
2888 11:32:29.532210 ==
2889 11:32:29.535271 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:32:29.542013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:32:29.542509 ==
2892 11:32:29.545101 Write leveling (Byte 0): 31 => 31
2893 11:32:29.545655 Write leveling (Byte 1): 28 => 28
2894 11:32:29.548422 DramcWriteLeveling(PI) end<-----
2895 11:32:29.548842
2896 11:32:29.549164 ==
2897 11:32:29.551509 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 11:32:29.558647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 11:32:29.559142 ==
2900 11:32:29.561711 [Gating] SW mode calibration
2901 11:32:29.569026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 11:32:29.571658 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 11:32:29.578678 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2904 11:32:29.581516 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2905 11:32:29.585047 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:32:29.591155 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:32:29.595231 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:32:29.598015 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:32:29.605014 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:32:29.608079 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2911 11:32:29.611371 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
2912 11:32:29.617869 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:32:29.621331 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:32:29.624160 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:32:29.631129 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:32:29.635354 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:32:29.637648 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:32:29.643999 1 0 28 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2919 11:32:29.647980 1 1 0 | B1->B0 | 3131 4343 | 1 0 | (0 0) (0 0)
2920 11:32:29.651129 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:32:29.657926 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:32:29.660655 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:32:29.664085 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:32:29.671228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:32:29.674464 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:32:29.677154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 11:32:29.684086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2928 11:32:29.687189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:32:29.690681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:32:29.696904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:32:29.700156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:32:29.704149 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:32:29.710272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:32:29.713374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:32:29.716750 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:32:29.723131 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:32:29.727152 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:32:29.729893 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:32:29.736508 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:32:29.739599 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:32:29.743891 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:32:29.749936 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2943 11:32:29.753002 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2944 11:32:29.756207 Total UI for P1: 0, mck2ui 16
2945 11:32:29.759810 best dqsien dly found for B0: ( 1, 3, 28)
2946 11:32:29.762956 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:32:29.766424 Total UI for P1: 0, mck2ui 16
2948 11:32:29.769423 best dqsien dly found for B1: ( 1, 4, 0)
2949 11:32:29.772985 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2950 11:32:29.776469 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2951 11:32:29.776965
2952 11:32:29.779623 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 11:32:29.785928 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2954 11:32:29.786419 [Gating] SW calibration Done
2955 11:32:29.786751 ==
2956 11:32:29.789510 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:32:29.796162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:32:29.796669 ==
2959 11:32:29.797089 RX Vref Scan: 0
2960 11:32:29.797402
2961 11:32:29.799198 RX Vref 0 -> 0, step: 1
2962 11:32:29.799671
2963 11:32:29.802646 RX Delay -40 -> 252, step: 8
2964 11:32:29.805806 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2965 11:32:29.809250 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 11:32:29.812502 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2967 11:32:29.819274 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2968 11:32:29.822266 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2969 11:32:29.825824 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2970 11:32:29.828760 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 11:32:29.835614 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2972 11:32:29.838937 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2973 11:32:29.842385 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2974 11:32:29.845357 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2975 11:32:29.848823 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2976 11:32:29.855127 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2977 11:32:29.858740 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2978 11:32:29.862473 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2979 11:32:29.865615 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2980 11:32:29.866129 ==
2981 11:32:29.868492 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:32:29.875268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:32:29.875835 ==
2984 11:32:29.876171 DQS Delay:
2985 11:32:29.876473 DQS0 = 0, DQS1 = 0
2986 11:32:29.878727 DQM Delay:
2987 11:32:29.879239 DQM0 = 117, DQM1 = 108
2988 11:32:29.882166 DQ Delay:
2989 11:32:29.885418 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2990 11:32:29.888494 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2991 11:32:29.891852 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2992 11:32:29.895272 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2993 11:32:29.895746
2994 11:32:29.896171
2995 11:32:29.896481 ==
2996 11:32:29.898430 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:32:29.902025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:32:29.902554 ==
2999 11:32:29.905138
3000 11:32:29.905553
3001 11:32:29.905878 TX Vref Scan disable
3002 11:32:29.908063 == TX Byte 0 ==
3003 11:32:29.911848 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3004 11:32:29.914735 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3005 11:32:29.918280 == TX Byte 1 ==
3006 11:32:29.921572 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3007 11:32:29.924799 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3008 11:32:29.925224 ==
3009 11:32:29.928004 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:32:29.934733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:32:29.935266 ==
3012 11:32:29.945742 TX Vref=22, minBit 13, minWin=25, winSum=420
3013 11:32:29.949012 TX Vref=24, minBit 10, minWin=25, winSum=422
3014 11:32:29.952851 TX Vref=26, minBit 3, minWin=26, winSum=426
3015 11:32:29.955789 TX Vref=28, minBit 13, minWin=25, winSum=430
3016 11:32:29.959116 TX Vref=30, minBit 0, minWin=27, winSum=434
3017 11:32:29.965586 TX Vref=32, minBit 4, minWin=26, winSum=431
3018 11:32:29.968939 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 30
3019 11:32:29.969438
3020 11:32:29.972313 Final TX Range 1 Vref 30
3021 11:32:29.972810
3022 11:32:29.973142 ==
3023 11:32:29.975847 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:32:29.982234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:32:29.982754 ==
3026 11:32:29.983087
3027 11:32:29.983566
3028 11:32:29.983998 TX Vref Scan disable
3029 11:32:29.985941 == TX Byte 0 ==
3030 11:32:29.989704 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3031 11:32:29.995735 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3032 11:32:29.996188 == TX Byte 1 ==
3033 11:32:29.998630 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3034 11:32:30.005843 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3035 11:32:30.006330
3036 11:32:30.006677 [DATLAT]
3037 11:32:30.006991 Freq=1200, CH0 RK1
3038 11:32:30.007288
3039 11:32:30.008958 DATLAT Default: 0xd
3040 11:32:30.012365 0, 0xFFFF, sum = 0
3041 11:32:30.012839 1, 0xFFFF, sum = 0
3042 11:32:30.015295 2, 0xFFFF, sum = 0
3043 11:32:30.015755 3, 0xFFFF, sum = 0
3044 11:32:30.019239 4, 0xFFFF, sum = 0
3045 11:32:30.019709 5, 0xFFFF, sum = 0
3046 11:32:30.021810 6, 0xFFFF, sum = 0
3047 11:32:30.022238 7, 0xFFFF, sum = 0
3048 11:32:30.025370 8, 0xFFFF, sum = 0
3049 11:32:30.025796 9, 0xFFFF, sum = 0
3050 11:32:30.028800 10, 0xFFFF, sum = 0
3051 11:32:30.029229 11, 0xFFFF, sum = 0
3052 11:32:30.031751 12, 0x0, sum = 1
3053 11:32:30.032179 13, 0x0, sum = 2
3054 11:32:30.035244 14, 0x0, sum = 3
3055 11:32:30.035676 15, 0x0, sum = 4
3056 11:32:30.038860 best_step = 13
3057 11:32:30.039311
3058 11:32:30.039664 ==
3059 11:32:30.041750 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 11:32:30.045514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 11:32:30.045970 ==
3062 11:32:30.048275 RX Vref Scan: 0
3063 11:32:30.048681
3064 11:32:30.048978 RX Vref 0 -> 0, step: 1
3065 11:32:30.049253
3066 11:32:30.051846 RX Delay -21 -> 252, step: 4
3067 11:32:30.058351 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3068 11:32:30.061676 iDelay=195, Bit 1, Center 120 (51 ~ 190) 140
3069 11:32:30.065085 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3070 11:32:30.068487 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3071 11:32:30.071502 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3072 11:32:30.078120 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3073 11:32:30.081341 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 11:32:30.084810 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3075 11:32:30.087894 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3076 11:32:30.090798 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3077 11:32:30.097672 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3078 11:32:30.101319 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3079 11:32:30.104715 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3080 11:32:30.107501 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3081 11:32:30.114344 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3082 11:32:30.117560 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3083 11:32:30.118080 ==
3084 11:32:30.120810 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:32:30.124126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:32:30.124554 ==
3087 11:32:30.127540 DQS Delay:
3088 11:32:30.127966 DQS0 = 0, DQS1 = 0
3089 11:32:30.128295 DQM Delay:
3090 11:32:30.130930 DQM0 = 116, DQM1 = 107
3091 11:32:30.131348 DQ Delay:
3092 11:32:30.134507 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3093 11:32:30.137490 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3094 11:32:30.140617 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3095 11:32:30.147561 DQ12 =110, DQ13 =114, DQ14 =118, DQ15 =116
3096 11:32:30.148065
3097 11:32:30.148397
3098 11:32:30.154021 [DQSOSCAuto] RK1, (LSB)MR18= 0xfea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3099 11:32:30.157459 CH0 RK1: MR19=403, MR18=FEA
3100 11:32:30.163898 CH0_RK1: MR19=0x403, MR18=0xFEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3101 11:32:30.167634 [RxdqsGatingPostProcess] freq 1200
3102 11:32:30.170741 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 11:32:30.174155 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 11:32:30.177627 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 11:32:30.180762 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 11:32:30.183769 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 11:32:30.187012 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 11:32:30.190778 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 11:32:30.193463 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 11:32:30.196971 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 11:32:30.199954 Pre-setting of DQS Precalculation
3112 11:32:30.203349 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 11:32:30.203800 ==
3114 11:32:30.206557 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:32:30.213077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:32:30.213574 ==
3117 11:32:30.217349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 11:32:30.223234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 11:32:30.232139 [CA 0] Center 37 (7~68) winsize 62
3120 11:32:30.235586 [CA 1] Center 37 (7~68) winsize 62
3121 11:32:30.239120 [CA 2] Center 34 (4~64) winsize 61
3122 11:32:30.242114 [CA 3] Center 33 (3~64) winsize 62
3123 11:32:30.244910 [CA 4] Center 34 (4~64) winsize 61
3124 11:32:30.248127 [CA 5] Center 33 (3~64) winsize 62
3125 11:32:30.248558
3126 11:32:30.251822 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 11:32:30.252248
3128 11:32:30.254846 [CATrainingPosCal] consider 1 rank data
3129 11:32:30.258759 u2DelayCellTimex100 = 270/100 ps
3130 11:32:30.261588 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 11:32:30.268881 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 11:32:30.271973 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 11:32:30.274781 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 11:32:30.277801 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 11:32:30.281623 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 11:32:30.282049
3137 11:32:30.284235 CA PerBit enable=1, Macro0, CA PI delay=33
3138 11:32:30.284660
3139 11:32:30.287686 [CBTSetCACLKResult] CA Dly = 33
3140 11:32:30.291470 CS Dly: 5 (0~36)
3141 11:32:30.292092 ==
3142 11:32:30.294597 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 11:32:30.297714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 11:32:30.298149 ==
3145 11:32:30.303969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 11:32:30.307398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 11:32:30.318114 [CA 0] Center 38 (8~68) winsize 61
3148 11:32:30.320729 [CA 1] Center 37 (7~68) winsize 62
3149 11:32:30.323717 [CA 2] Center 34 (4~65) winsize 62
3150 11:32:30.326982 [CA 3] Center 33 (3~64) winsize 62
3151 11:32:30.330409 [CA 4] Center 34 (4~65) winsize 62
3152 11:32:30.333810 [CA 5] Center 33 (3~64) winsize 62
3153 11:32:30.334196
3154 11:32:30.337237 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3155 11:32:30.337618
3156 11:32:30.340431 [CATrainingPosCal] consider 2 rank data
3157 11:32:30.343549 u2DelayCellTimex100 = 270/100 ps
3158 11:32:30.347222 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 11:32:30.353828 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 11:32:30.356609 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 11:32:30.360208 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3162 11:32:30.363242 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 11:32:30.366540 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3164 11:32:30.366926
3165 11:32:30.369741 CA PerBit enable=1, Macro0, CA PI delay=33
3166 11:32:30.370154
3167 11:32:30.373371 [CBTSetCACLKResult] CA Dly = 33
3168 11:32:30.376268 CS Dly: 7 (0~40)
3169 11:32:30.376658
3170 11:32:30.379479 ----->DramcWriteLeveling(PI) begin...
3171 11:32:30.379883 ==
3172 11:32:30.382992 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 11:32:30.386088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 11:32:30.386483 ==
3175 11:32:30.389688 Write leveling (Byte 0): 23 => 23
3176 11:32:30.392800 Write leveling (Byte 1): 28 => 28
3177 11:32:30.396610 DramcWriteLeveling(PI) end<-----
3178 11:32:30.396995
3179 11:32:30.397294 ==
3180 11:32:30.399783 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 11:32:30.402758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:32:30.403164 ==
3183 11:32:30.406147 [Gating] SW mode calibration
3184 11:32:30.412648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 11:32:30.419547 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 11:32:30.422815 0 15 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
3187 11:32:30.429243 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:32:30.432256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:32:30.436102 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:32:30.442290 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:32:30.445695 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:32:30.449522 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3193 11:32:30.455668 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3194 11:32:30.458745 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:32:30.462058 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:32:30.468882 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:32:30.472303 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:32:30.475523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:32:30.482205 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3200 11:32:30.485028 1 0 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3201 11:32:30.488853 1 0 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3202 11:32:30.495845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:32:30.498938 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:32:30.501650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:32:30.508362 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:32:30.511648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:32:30.514825 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:32:30.521783 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 11:32:30.524538 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 11:32:30.528004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:32:30.534873 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:32:30.538109 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:32:30.541740 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:32:30.547746 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:32:30.551358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:32:30.554801 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:32:30.561034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:32:30.564642 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:32:30.567616 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:32:30.574436 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:32:30.577431 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:32:30.581131 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:32:30.587964 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:32:30.591121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 11:32:30.593941 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3226 11:32:30.597773 Total UI for P1: 0, mck2ui 16
3227 11:32:30.600931 best dqsien dly found for B0: ( 1, 3, 24)
3228 11:32:30.604310 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:32:30.607512 Total UI for P1: 0, mck2ui 16
3230 11:32:30.611079 best dqsien dly found for B1: ( 1, 3, 26)
3231 11:32:30.614315 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3232 11:32:30.620773 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 11:32:30.621200
3234 11:32:30.623941 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3235 11:32:30.627057 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 11:32:30.630263 [Gating] SW calibration Done
3237 11:32:30.630688 ==
3238 11:32:30.634166 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:32:30.637521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:32:30.638021 ==
3241 11:32:30.640431 RX Vref Scan: 0
3242 11:32:30.640856
3243 11:32:30.641187 RX Vref 0 -> 0, step: 1
3244 11:32:30.641499
3245 11:32:30.643521 RX Delay -40 -> 252, step: 8
3246 11:32:30.646785 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3247 11:32:30.653357 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3248 11:32:30.656769 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3249 11:32:30.660115 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3250 11:32:30.663279 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3251 11:32:30.666384 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3252 11:32:30.673312 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3253 11:32:30.676629 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3254 11:32:30.679983 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3255 11:32:30.683342 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3256 11:32:30.686366 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3257 11:32:30.693168 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3258 11:32:30.696286 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3259 11:32:30.699928 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3260 11:32:30.703062 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3261 11:32:30.706668 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3262 11:32:30.709619 ==
3263 11:32:30.712804 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:32:30.716345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:32:30.716779 ==
3266 11:32:30.717115 DQS Delay:
3267 11:32:30.719648 DQS0 = 0, DQS1 = 0
3268 11:32:30.720026 DQM Delay:
3269 11:32:30.722908 DQM0 = 119, DQM1 = 110
3270 11:32:30.723337 DQ Delay:
3271 11:32:30.726073 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =119
3272 11:32:30.729452 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3273 11:32:30.732916 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3274 11:32:30.736256 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3275 11:32:30.736686
3276 11:32:30.737014
3277 11:32:30.737528 ==
3278 11:32:30.739643 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 11:32:30.746186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 11:32:30.746699 ==
3281 11:32:30.747034
3282 11:32:30.747339
3283 11:32:30.747696 TX Vref Scan disable
3284 11:32:30.749522 == TX Byte 0 ==
3285 11:32:30.752870 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3286 11:32:30.759276 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3287 11:32:30.759753 == TX Byte 1 ==
3288 11:32:30.762560 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 11:32:30.769582 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 11:32:30.770015 ==
3291 11:32:30.772392 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:32:30.776013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:32:30.776525 ==
3294 11:32:30.787766 TX Vref=22, minBit 9, minWin=25, winSum=419
3295 11:32:30.791278 TX Vref=24, minBit 0, minWin=26, winSum=428
3296 11:32:30.794243 TX Vref=26, minBit 0, minWin=26, winSum=431
3297 11:32:30.797286 TX Vref=28, minBit 1, minWin=26, winSum=430
3298 11:32:30.801309 TX Vref=30, minBit 1, minWin=26, winSum=430
3299 11:32:30.807385 TX Vref=32, minBit 10, minWin=25, winSum=425
3300 11:32:30.810737 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
3301 11:32:30.811254
3302 11:32:30.813897 Final TX Range 1 Vref 26
3303 11:32:30.814319
3304 11:32:30.814647 ==
3305 11:32:30.816962 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 11:32:30.820774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 11:32:30.824066 ==
3308 11:32:30.824478
3309 11:32:30.824797
3310 11:32:30.825095 TX Vref Scan disable
3311 11:32:30.827539 == TX Byte 0 ==
3312 11:32:30.830728 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3313 11:32:30.837355 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3314 11:32:30.837778 == TX Byte 1 ==
3315 11:32:30.840614 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3316 11:32:30.846934 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3317 11:32:30.847275
3318 11:32:30.847512 [DATLAT]
3319 11:32:30.847707 Freq=1200, CH1 RK0
3320 11:32:30.847893
3321 11:32:30.850543 DATLAT Default: 0xd
3322 11:32:30.850809 0, 0xFFFF, sum = 0
3323 11:32:30.853540 1, 0xFFFF, sum = 0
3324 11:32:30.857027 2, 0xFFFF, sum = 0
3325 11:32:30.857311 3, 0xFFFF, sum = 0
3326 11:32:30.860083 4, 0xFFFF, sum = 0
3327 11:32:30.860357 5, 0xFFFF, sum = 0
3328 11:32:30.864075 6, 0xFFFF, sum = 0
3329 11:32:30.864432 7, 0xFFFF, sum = 0
3330 11:32:30.866950 8, 0xFFFF, sum = 0
3331 11:32:30.867225 9, 0xFFFF, sum = 0
3332 11:32:30.870268 10, 0xFFFF, sum = 0
3333 11:32:30.870644 11, 0xFFFF, sum = 0
3334 11:32:30.873887 12, 0x0, sum = 1
3335 11:32:30.874242 13, 0x0, sum = 2
3336 11:32:30.877145 14, 0x0, sum = 3
3337 11:32:30.877576 15, 0x0, sum = 4
3338 11:32:30.880361 best_step = 13
3339 11:32:30.880780
3340 11:32:30.881053 ==
3341 11:32:30.883901 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 11:32:30.886853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 11:32:30.887353 ==
3344 11:32:30.890424 RX Vref Scan: 1
3345 11:32:30.890913
3346 11:32:30.891240 Set Vref Range= 32 -> 127
3347 11:32:30.891583
3348 11:32:30.893340 RX Vref 32 -> 127, step: 1
3349 11:32:30.893767
3350 11:32:30.896956 RX Delay -21 -> 252, step: 4
3351 11:32:30.897456
3352 11:32:30.900066 Set Vref, RX VrefLevel [Byte0]: 32
3353 11:32:30.902997 [Byte1]: 32
3354 11:32:30.903526
3355 11:32:30.906451 Set Vref, RX VrefLevel [Byte0]: 33
3356 11:32:30.910142 [Byte1]: 33
3357 11:32:30.914137
3358 11:32:30.914628 Set Vref, RX VrefLevel [Byte0]: 34
3359 11:32:30.917075 [Byte1]: 34
3360 11:32:30.922083
3361 11:32:30.922578 Set Vref, RX VrefLevel [Byte0]: 35
3362 11:32:30.924915 [Byte1]: 35
3363 11:32:30.929820
3364 11:32:30.930240 Set Vref, RX VrefLevel [Byte0]: 36
3365 11:32:30.933667 [Byte1]: 36
3366 11:32:30.937694
3367 11:32:30.940806 Set Vref, RX VrefLevel [Byte0]: 37
3368 11:32:30.944253 [Byte1]: 37
3369 11:32:30.944675
3370 11:32:30.947349 Set Vref, RX VrefLevel [Byte0]: 38
3371 11:32:30.950503 [Byte1]: 38
3372 11:32:30.950924
3373 11:32:30.954043 Set Vref, RX VrefLevel [Byte0]: 39
3374 11:32:30.957191 [Byte1]: 39
3375 11:32:30.961203
3376 11:32:30.961624 Set Vref, RX VrefLevel [Byte0]: 40
3377 11:32:30.964845 [Byte1]: 40
3378 11:32:30.969377
3379 11:32:30.970009 Set Vref, RX VrefLevel [Byte0]: 41
3380 11:32:30.972837 [Byte1]: 41
3381 11:32:30.977746
3382 11:32:30.978238 Set Vref, RX VrefLevel [Byte0]: 42
3383 11:32:30.980301 [Byte1]: 42
3384 11:32:30.985287
3385 11:32:30.985785 Set Vref, RX VrefLevel [Byte0]: 43
3386 11:32:30.988799 [Byte1]: 43
3387 11:32:30.993128
3388 11:32:30.993632 Set Vref, RX VrefLevel [Byte0]: 44
3389 11:32:30.996083 [Byte1]: 44
3390 11:32:31.001028
3391 11:32:31.001468 Set Vref, RX VrefLevel [Byte0]: 45
3392 11:32:31.007366 [Byte1]: 45
3393 11:32:31.007925
3394 11:32:31.010908 Set Vref, RX VrefLevel [Byte0]: 46
3395 11:32:31.014127 [Byte1]: 46
3396 11:32:31.014623
3397 11:32:31.017191 Set Vref, RX VrefLevel [Byte0]: 47
3398 11:32:31.020350 [Byte1]: 47
3399 11:32:31.025582
3400 11:32:31.026074 Set Vref, RX VrefLevel [Byte0]: 48
3401 11:32:31.028054 [Byte1]: 48
3402 11:32:31.032515
3403 11:32:31.032932 Set Vref, RX VrefLevel [Byte0]: 49
3404 11:32:31.036165 [Byte1]: 49
3405 11:32:31.040752
3406 11:32:31.041167 Set Vref, RX VrefLevel [Byte0]: 50
3407 11:32:31.043845 [Byte1]: 50
3408 11:32:31.048684
3409 11:32:31.049099 Set Vref, RX VrefLevel [Byte0]: 51
3410 11:32:31.052107 [Byte1]: 51
3411 11:32:31.056608
3412 11:32:31.057119 Set Vref, RX VrefLevel [Byte0]: 52
3413 11:32:31.059841 [Byte1]: 52
3414 11:32:31.064067
3415 11:32:31.064482 Set Vref, RX VrefLevel [Byte0]: 53
3416 11:32:31.068302 [Byte1]: 53
3417 11:32:31.072392
3418 11:32:31.072885 Set Vref, RX VrefLevel [Byte0]: 54
3419 11:32:31.075501 [Byte1]: 54
3420 11:32:31.080857
3421 11:32:31.081275 Set Vref, RX VrefLevel [Byte0]: 55
3422 11:32:31.083562 [Byte1]: 55
3423 11:32:31.087898
3424 11:32:31.088321 Set Vref, RX VrefLevel [Byte0]: 56
3425 11:32:31.091369 [Byte1]: 56
3426 11:32:31.096079
3427 11:32:31.096497 Set Vref, RX VrefLevel [Byte0]: 57
3428 11:32:31.099204 [Byte1]: 57
3429 11:32:31.103900
3430 11:32:31.104319 Set Vref, RX VrefLevel [Byte0]: 58
3431 11:32:31.107530 [Byte1]: 58
3432 11:32:31.111519
3433 11:32:31.111943 Set Vref, RX VrefLevel [Byte0]: 59
3434 11:32:31.115079 [Byte1]: 59
3435 11:32:31.120316
3436 11:32:31.120999 Set Vref, RX VrefLevel [Byte0]: 60
3437 11:32:31.122842 [Byte1]: 60
3438 11:32:31.127697
3439 11:32:31.128116 Set Vref, RX VrefLevel [Byte0]: 61
3440 11:32:31.131115 [Byte1]: 61
3441 11:32:31.135831
3442 11:32:31.136255 Set Vref, RX VrefLevel [Byte0]: 62
3443 11:32:31.138770 [Byte1]: 62
3444 11:32:31.143516
3445 11:32:31.143948 Set Vref, RX VrefLevel [Byte0]: 63
3446 11:32:31.146715 [Byte1]: 63
3447 11:32:31.151647
3448 11:32:31.152083 Set Vref, RX VrefLevel [Byte0]: 64
3449 11:32:31.154465 [Byte1]: 64
3450 11:32:31.159397
3451 11:32:31.159837 Set Vref, RX VrefLevel [Byte0]: 65
3452 11:32:31.162939 [Byte1]: 65
3453 11:32:31.167531
3454 11:32:31.167961 Set Vref, RX VrefLevel [Byte0]: 66
3455 11:32:31.170660 [Byte1]: 66
3456 11:32:31.174972
3457 11:32:31.175497 Set Vref, RX VrefLevel [Byte0]: 67
3458 11:32:31.178533 [Byte1]: 67
3459 11:32:31.183158
3460 11:32:31.183711 Set Vref, RX VrefLevel [Byte0]: 68
3461 11:32:31.186573 [Byte1]: 68
3462 11:32:31.191326
3463 11:32:31.191879 Set Vref, RX VrefLevel [Byte0]: 69
3464 11:32:31.194428 [Byte1]: 69
3465 11:32:31.198716
3466 11:32:31.199336 Set Vref, RX VrefLevel [Byte0]: 70
3467 11:32:31.205699 [Byte1]: 70
3468 11:32:31.206183
3469 11:32:31.208964 Final RX Vref Byte 0 = 50 to rank0
3470 11:32:31.211848 Final RX Vref Byte 1 = 51 to rank0
3471 11:32:31.214949 Final RX Vref Byte 0 = 50 to rank1
3472 11:32:31.218576 Final RX Vref Byte 1 = 51 to rank1==
3473 11:32:31.221575 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 11:32:31.225104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 11:32:31.225562 ==
3476 11:32:31.225898 DQS Delay:
3477 11:32:31.228898 DQS0 = 0, DQS1 = 0
3478 11:32:31.229389 DQM Delay:
3479 11:32:31.231798 DQM0 = 117, DQM1 = 110
3480 11:32:31.232226 DQ Delay:
3481 11:32:31.234836 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3482 11:32:31.238335 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3483 11:32:31.242181 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =98
3484 11:32:31.245086 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3485 11:32:31.248457
3486 11:32:31.248880
3487 11:32:31.255161 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3488 11:32:31.258473 CH1 RK0: MR19=403, MR18=4F7
3489 11:32:31.264766 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3490 11:32:31.265378
3491 11:32:31.268114 ----->DramcWriteLeveling(PI) begin...
3492 11:32:31.268709 ==
3493 11:32:31.271236 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 11:32:31.274529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 11:32:31.274957 ==
3496 11:32:31.278012 Write leveling (Byte 0): 24 => 24
3497 11:32:31.281321 Write leveling (Byte 1): 29 => 29
3498 11:32:31.284586 DramcWriteLeveling(PI) end<-----
3499 11:32:31.285107
3500 11:32:31.285446 ==
3501 11:32:31.287939 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:32:31.291155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:32:31.291651 ==
3504 11:32:31.294145 [Gating] SW mode calibration
3505 11:32:31.300795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 11:32:31.307380 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 11:32:31.310432 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
3508 11:32:31.317385 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 11:32:31.320738 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 11:32:31.324044 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:32:31.330442 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:32:31.333846 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 11:32:31.336864 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3514 11:32:31.343550 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3515 11:32:31.346800 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 11:32:31.349856 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 11:32:31.357214 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:32:31.359758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:32:31.363221 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:32:31.370173 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 11:32:31.373297 1 0 24 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
3522 11:32:31.376273 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3523 11:32:31.383302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:32:31.386639 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:32:31.389667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 11:32:31.396388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:32:31.399325 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:32:31.403217 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:32:31.409607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3530 11:32:31.412548 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3531 11:32:31.415738 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:32:31.423014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:32:31.425847 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:32:31.429207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:32:31.435543 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:32:31.438897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:32:31.442644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:32:31.448780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:32:31.452173 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:32:31.455725 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:32:31.462031 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:32:31.465562 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:32:31.468554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:32:31.475260 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:32:31.478241 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3546 11:32:31.481872 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3547 11:32:31.488886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 11:32:31.489413 Total UI for P1: 0, mck2ui 16
3549 11:32:31.495275 best dqsien dly found for B0: ( 1, 3, 28)
3550 11:32:31.495779 Total UI for P1: 0, mck2ui 16
3551 11:32:31.498185 best dqsien dly found for B1: ( 1, 3, 26)
3552 11:32:31.505644 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3553 11:32:31.508502 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3554 11:32:31.509090
3555 11:32:31.511588 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3556 11:32:31.515419 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3557 11:32:31.518731 [Gating] SW calibration Done
3558 11:32:31.519133 ==
3559 11:32:31.521834 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 11:32:31.525016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 11:32:31.525417 ==
3562 11:32:31.528814 RX Vref Scan: 0
3563 11:32:31.529207
3564 11:32:31.529596 RX Vref 0 -> 0, step: 1
3565 11:32:31.529983
3566 11:32:31.531563 RX Delay -40 -> 252, step: 8
3567 11:32:31.535164 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3568 11:32:31.541552 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3569 11:32:31.544698 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3570 11:32:31.547800 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3571 11:32:31.551325 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3572 11:32:31.554815 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3573 11:32:31.561066 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3574 11:32:31.563999 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3575 11:32:31.567507 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3576 11:32:31.571659 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3577 11:32:31.574028 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3578 11:32:31.580743 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3579 11:32:31.584531 iDelay=200, Bit 12, Center 123 (48 ~ 199) 152
3580 11:32:31.587676 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3581 11:32:31.590787 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3582 11:32:31.594471 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3583 11:32:31.597469 ==
3584 11:32:31.600714 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:32:31.603997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:32:31.604125 ==
3587 11:32:31.604195 DQS Delay:
3588 11:32:31.608004 DQS0 = 0, DQS1 = 0
3589 11:32:31.608160 DQM Delay:
3590 11:32:31.610735 DQM0 = 118, DQM1 = 111
3591 11:32:31.610893 DQ Delay:
3592 11:32:31.614148 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3593 11:32:31.617567 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3594 11:32:31.620728 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3595 11:32:31.624172 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3596 11:32:31.624367
3597 11:32:31.624483
3598 11:32:31.624591 ==
3599 11:32:31.627637 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:32:31.633610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:32:31.633860 ==
3602 11:32:31.634014
3603 11:32:31.634140
3604 11:32:31.634256 TX Vref Scan disable
3605 11:32:31.637378 == TX Byte 0 ==
3606 11:32:31.640869 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3607 11:32:31.647820 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3608 11:32:31.648215 == TX Byte 1 ==
3609 11:32:31.650788 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3610 11:32:31.657836 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3611 11:32:31.658359 ==
3612 11:32:31.661040 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 11:32:31.664160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 11:32:31.664688 ==
3615 11:32:31.675840 TX Vref=22, minBit 0, minWin=25, winSum=421
3616 11:32:31.679659 TX Vref=24, minBit 1, minWin=25, winSum=425
3617 11:32:31.682547 TX Vref=26, minBit 3, minWin=26, winSum=434
3618 11:32:31.686238 TX Vref=28, minBit 9, minWin=25, winSum=432
3619 11:32:31.689452 TX Vref=30, minBit 5, minWin=26, winSum=432
3620 11:32:31.695559 TX Vref=32, minBit 0, minWin=26, winSum=429
3621 11:32:31.698815 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 26
3622 11:32:31.699246
3623 11:32:31.702675 Final TX Range 1 Vref 26
3624 11:32:31.703188
3625 11:32:31.703566 ==
3626 11:32:31.705739 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:32:31.708817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:32:31.712374 ==
3629 11:32:31.712801
3630 11:32:31.713128
3631 11:32:31.713435 TX Vref Scan disable
3632 11:32:31.715396 == TX Byte 0 ==
3633 11:32:31.718857 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3634 11:32:31.725602 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3635 11:32:31.726131 == TX Byte 1 ==
3636 11:32:31.728766 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3637 11:32:31.735338 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3638 11:32:31.735882
3639 11:32:31.736218 [DATLAT]
3640 11:32:31.736523 Freq=1200, CH1 RK1
3641 11:32:31.736816
3642 11:32:31.738796 DATLAT Default: 0xd
3643 11:32:31.739217 0, 0xFFFF, sum = 0
3644 11:32:31.741818 1, 0xFFFF, sum = 0
3645 11:32:31.745576 2, 0xFFFF, sum = 0
3646 11:32:31.746002 3, 0xFFFF, sum = 0
3647 11:32:31.748574 4, 0xFFFF, sum = 0
3648 11:32:31.749015 5, 0xFFFF, sum = 0
3649 11:32:31.751976 6, 0xFFFF, sum = 0
3650 11:32:31.752363 7, 0xFFFF, sum = 0
3651 11:32:31.755058 8, 0xFFFF, sum = 0
3652 11:32:31.755614 9, 0xFFFF, sum = 0
3653 11:32:31.758675 10, 0xFFFF, sum = 0
3654 11:32:31.759063 11, 0xFFFF, sum = 0
3655 11:32:31.761795 12, 0x0, sum = 1
3656 11:32:31.762261 13, 0x0, sum = 2
3657 11:32:31.765386 14, 0x0, sum = 3
3658 11:32:31.765815 15, 0x0, sum = 4
3659 11:32:31.768753 best_step = 13
3660 11:32:31.769129
3661 11:32:31.769421 ==
3662 11:32:31.771988 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 11:32:31.775317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 11:32:31.775845 ==
3665 11:32:31.776181 RX Vref Scan: 0
3666 11:32:31.779071
3667 11:32:31.779657 RX Vref 0 -> 0, step: 1
3668 11:32:31.780001
3669 11:32:31.782227 RX Delay -21 -> 252, step: 4
3670 11:32:31.788412 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3671 11:32:31.792393 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3672 11:32:31.795313 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3673 11:32:31.798607 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3674 11:32:31.801670 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3675 11:32:31.808683 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3676 11:32:31.811814 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3677 11:32:31.815056 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3678 11:32:31.818148 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3679 11:32:31.822221 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3680 11:32:31.828273 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3681 11:32:31.831652 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3682 11:32:31.834771 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3683 11:32:31.837901 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3684 11:32:31.841369 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3685 11:32:31.847771 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3686 11:32:31.848261 ==
3687 11:32:31.851306 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 11:32:31.854588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 11:32:31.855093 ==
3690 11:32:31.855470 DQS Delay:
3691 11:32:31.858348 DQS0 = 0, DQS1 = 0
3692 11:32:31.858770 DQM Delay:
3693 11:32:31.861381 DQM0 = 117, DQM1 = 110
3694 11:32:31.861879 DQ Delay:
3695 11:32:31.864363 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3696 11:32:31.867412 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3697 11:32:31.870848 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3698 11:32:31.878181 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =118
3699 11:32:31.878682
3700 11:32:31.879014
3701 11:32:31.883946 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
3702 11:32:31.887829 CH1 RK1: MR19=303, MR18=F6F2
3703 11:32:31.893816 CH1_RK1: MR19=0x303, MR18=0xF6F2, DQSOSC=414, MR23=63, INC=38, DEC=25
3704 11:32:31.897193 [RxdqsGatingPostProcess] freq 1200
3705 11:32:31.900423 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 11:32:31.904113 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 11:32:31.907531 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 11:32:31.910537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 11:32:31.913766 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 11:32:31.917028 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 11:32:31.920100 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 11:32:31.923671 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 11:32:31.927160 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 11:32:31.930389 Pre-setting of DQS Precalculation
3715 11:32:31.933569 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 11:32:31.943306 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 11:32:31.950026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 11:32:31.950529
3719 11:32:31.950907
3720 11:32:31.953104 [Calibration Summary] 2400 Mbps
3721 11:32:31.953529 CH 0, Rank 0
3722 11:32:31.957012 SW Impedance : PASS
3723 11:32:31.957534 DUTY Scan : NO K
3724 11:32:31.960127 ZQ Calibration : PASS
3725 11:32:31.963357 Jitter Meter : NO K
3726 11:32:31.963824 CBT Training : PASS
3727 11:32:31.966650 Write leveling : PASS
3728 11:32:31.970070 RX DQS gating : PASS
3729 11:32:31.970572 RX DQ/DQS(RDDQC) : PASS
3730 11:32:31.973561 TX DQ/DQS : PASS
3731 11:32:31.976354 RX DATLAT : PASS
3732 11:32:31.976781 RX DQ/DQS(Engine): PASS
3733 11:32:31.979591 TX OE : NO K
3734 11:32:31.980018 All Pass.
3735 11:32:31.980342
3736 11:32:31.982791 CH 0, Rank 1
3737 11:32:31.983215 SW Impedance : PASS
3738 11:32:31.986342 DUTY Scan : NO K
3739 11:32:31.990262 ZQ Calibration : PASS
3740 11:32:31.990841 Jitter Meter : NO K
3741 11:32:31.993109 CBT Training : PASS
3742 11:32:31.996241 Write leveling : PASS
3743 11:32:31.996663 RX DQS gating : PASS
3744 11:32:31.999523 RX DQ/DQS(RDDQC) : PASS
3745 11:32:32.002731 TX DQ/DQS : PASS
3746 11:32:32.003180 RX DATLAT : PASS
3747 11:32:32.005940 RX DQ/DQS(Engine): PASS
3748 11:32:32.006369 TX OE : NO K
3749 11:32:32.009403 All Pass.
3750 11:32:32.009825
3751 11:32:32.010153 CH 1, Rank 0
3752 11:32:32.012952 SW Impedance : PASS
3753 11:32:32.016100 DUTY Scan : NO K
3754 11:32:32.016524 ZQ Calibration : PASS
3755 11:32:32.019199 Jitter Meter : NO K
3756 11:32:32.019706 CBT Training : PASS
3757 11:32:32.022799 Write leveling : PASS
3758 11:32:32.025606 RX DQS gating : PASS
3759 11:32:32.026034 RX DQ/DQS(RDDQC) : PASS
3760 11:32:32.028956 TX DQ/DQS : PASS
3761 11:32:32.032483 RX DATLAT : PASS
3762 11:32:32.033084 RX DQ/DQS(Engine): PASS
3763 11:32:32.035489 TX OE : NO K
3764 11:32:32.035920 All Pass.
3765 11:32:32.036247
3766 11:32:32.039282 CH 1, Rank 1
3767 11:32:32.039829 SW Impedance : PASS
3768 11:32:32.042545 DUTY Scan : NO K
3769 11:32:32.046077 ZQ Calibration : PASS
3770 11:32:32.046577 Jitter Meter : NO K
3771 11:32:32.049290 CBT Training : PASS
3772 11:32:32.052176 Write leveling : PASS
3773 11:32:32.052606 RX DQS gating : PASS
3774 11:32:32.055183 RX DQ/DQS(RDDQC) : PASS
3775 11:32:32.059031 TX DQ/DQS : PASS
3776 11:32:32.059575 RX DATLAT : PASS
3777 11:32:32.062653 RX DQ/DQS(Engine): PASS
3778 11:32:32.065158 TX OE : NO K
3779 11:32:32.065590 All Pass.
3780 11:32:32.065918
3781 11:32:32.066228 DramC Write-DBI off
3782 11:32:32.068892 PER_BANK_REFRESH: Hybrid Mode
3783 11:32:32.072209 TX_TRACKING: ON
3784 11:32:32.079048 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 11:32:32.085503 [FAST_K] Save calibration result to emmc
3786 11:32:32.088628 dramc_set_vcore_voltage set vcore to 650000
3787 11:32:32.089132 Read voltage for 600, 5
3788 11:32:32.091791 Vio18 = 0
3789 11:32:32.092219 Vcore = 650000
3790 11:32:32.092551 Vdram = 0
3791 11:32:32.094827 Vddq = 0
3792 11:32:32.095252 Vmddr = 0
3793 11:32:32.098034 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 11:32:32.105088 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 11:32:32.107918 MEM_TYPE=3, freq_sel=19
3796 11:32:32.111865 sv_algorithm_assistance_LP4_1600
3797 11:32:32.115022 ============ PULL DRAM RESETB DOWN ============
3798 11:32:32.117883 ========== PULL DRAM RESETB DOWN end =========
3799 11:32:32.124770 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 11:32:32.127999 ===================================
3801 11:32:32.128428 LPDDR4 DRAM CONFIGURATION
3802 11:32:32.131187 ===================================
3803 11:32:32.134658 EX_ROW_EN[0] = 0x0
3804 11:32:32.135253 EX_ROW_EN[1] = 0x0
3805 11:32:32.138053 LP4Y_EN = 0x0
3806 11:32:32.141117 WORK_FSP = 0x0
3807 11:32:32.141631 WL = 0x2
3808 11:32:32.144424 RL = 0x2
3809 11:32:32.144850 BL = 0x2
3810 11:32:32.147837 RPST = 0x0
3811 11:32:32.148264 RD_PRE = 0x0
3812 11:32:32.150867 WR_PRE = 0x1
3813 11:32:32.151296 WR_PST = 0x0
3814 11:32:32.154487 DBI_WR = 0x0
3815 11:32:32.154988 DBI_RD = 0x0
3816 11:32:32.158036 OTF = 0x1
3817 11:32:32.160903 ===================================
3818 11:32:32.163968 ===================================
3819 11:32:32.164396 ANA top config
3820 11:32:32.167658 ===================================
3821 11:32:32.170577 DLL_ASYNC_EN = 0
3822 11:32:32.174251 ALL_SLAVE_EN = 1
3823 11:32:32.174760 NEW_RANK_MODE = 1
3824 11:32:32.177273 DLL_IDLE_MODE = 1
3825 11:32:32.180847 LP45_APHY_COMB_EN = 1
3826 11:32:32.184239 TX_ODT_DIS = 1
3827 11:32:32.187473 NEW_8X_MODE = 1
3828 11:32:32.191408 ===================================
3829 11:32:32.194071 ===================================
3830 11:32:32.197484 data_rate = 1200
3831 11:32:32.197912 CKR = 1
3832 11:32:32.201036 DQ_P2S_RATIO = 8
3833 11:32:32.204196 ===================================
3834 11:32:32.207563 CA_P2S_RATIO = 8
3835 11:32:32.210880 DQ_CA_OPEN = 0
3836 11:32:32.213990 DQ_SEMI_OPEN = 0
3837 11:32:32.214495 CA_SEMI_OPEN = 0
3838 11:32:32.217758 CA_FULL_RATE = 0
3839 11:32:32.220643 DQ_CKDIV4_EN = 1
3840 11:32:32.223912 CA_CKDIV4_EN = 1
3841 11:32:32.227111 CA_PREDIV_EN = 0
3842 11:32:32.230489 PH8_DLY = 0
3843 11:32:32.233925 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 11:32:32.234351 DQ_AAMCK_DIV = 4
3845 11:32:32.236729 CA_AAMCK_DIV = 4
3846 11:32:32.240300 CA_ADMCK_DIV = 4
3847 11:32:32.243742 DQ_TRACK_CA_EN = 0
3848 11:32:32.246909 CA_PICK = 600
3849 11:32:32.250417 CA_MCKIO = 600
3850 11:32:32.250916 MCKIO_SEMI = 0
3851 11:32:32.253810 PLL_FREQ = 2288
3852 11:32:32.256805 DQ_UI_PI_RATIO = 32
3853 11:32:32.260183 CA_UI_PI_RATIO = 0
3854 11:32:32.263371 ===================================
3855 11:32:32.266488 ===================================
3856 11:32:32.270378 memory_type:LPDDR4
3857 11:32:32.270877 GP_NUM : 10
3858 11:32:32.273543 SRAM_EN : 1
3859 11:32:32.276396 MD32_EN : 0
3860 11:32:32.280067 ===================================
3861 11:32:32.280573 [ANA_INIT] >>>>>>>>>>>>>>
3862 11:32:32.283116 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 11:32:32.286758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 11:32:32.289571 ===================================
3865 11:32:32.292942 data_rate = 1200,PCW = 0X5800
3866 11:32:32.296339 ===================================
3867 11:32:32.299397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 11:32:32.306517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 11:32:32.309544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 11:32:32.316100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 11:32:32.319220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 11:32:32.323185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 11:32:32.326091 [ANA_INIT] flow start
3874 11:32:32.326526 [ANA_INIT] PLL >>>>>>>>
3875 11:32:32.329113 [ANA_INIT] PLL <<<<<<<<
3876 11:32:32.332823 [ANA_INIT] MIDPI >>>>>>>>
3877 11:32:32.333326 [ANA_INIT] MIDPI <<<<<<<<
3878 11:32:32.335841 [ANA_INIT] DLL >>>>>>>>
3879 11:32:32.339131 [ANA_INIT] flow end
3880 11:32:32.342363 ============ LP4 DIFF to SE enter ============
3881 11:32:32.346058 ============ LP4 DIFF to SE exit ============
3882 11:32:32.348633 [ANA_INIT] <<<<<<<<<<<<<
3883 11:32:32.352864 [Flow] Enable top DCM control >>>>>
3884 11:32:32.355418 [Flow] Enable top DCM control <<<<<
3885 11:32:32.358845 Enable DLL master slave shuffle
3886 11:32:32.365282 ==============================================================
3887 11:32:32.365717 Gating Mode config
3888 11:32:32.371711 ==============================================================
3889 11:32:32.372096 Config description:
3890 11:32:32.381986 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 11:32:32.388441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 11:32:32.394890 SELPH_MODE 0: By rank 1: By Phase
3893 11:32:32.398486 ==============================================================
3894 11:32:32.401682 GAT_TRACK_EN = 1
3895 11:32:32.404714 RX_GATING_MODE = 2
3896 11:32:32.408114 RX_GATING_TRACK_MODE = 2
3897 11:32:32.411523 SELPH_MODE = 1
3898 11:32:32.414850 PICG_EARLY_EN = 1
3899 11:32:32.418466 VALID_LAT_VALUE = 1
3900 11:32:32.421414 ==============================================================
3901 11:32:32.424815 Enter into Gating configuration >>>>
3902 11:32:32.428216 Exit from Gating configuration <<<<
3903 11:32:32.431709 Enter into DVFS_PRE_config >>>>>
3904 11:32:32.444984 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 11:32:32.447946 Exit from DVFS_PRE_config <<<<<
3906 11:32:32.451522 Enter into PICG configuration >>>>
3907 11:32:32.454820 Exit from PICG configuration <<<<
3908 11:32:32.455327 [RX_INPUT] configuration >>>>>
3909 11:32:32.457823 [RX_INPUT] configuration <<<<<
3910 11:32:32.464546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 11:32:32.467882 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 11:32:32.474331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 11:32:32.481123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 11:32:32.487745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 11:32:32.494387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 11:32:32.497586 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 11:32:32.500694 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 11:32:32.507484 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 11:32:32.510643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 11:32:32.513819 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 11:32:32.520296 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 11:32:32.523877 ===================================
3923 11:32:32.524482 LPDDR4 DRAM CONFIGURATION
3924 11:32:32.526847 ===================================
3925 11:32:32.530142 EX_ROW_EN[0] = 0x0
3926 11:32:32.530735 EX_ROW_EN[1] = 0x0
3927 11:32:32.533700 LP4Y_EN = 0x0
3928 11:32:32.536839 WORK_FSP = 0x0
3929 11:32:32.537412 WL = 0x2
3930 11:32:32.540182 RL = 0x2
3931 11:32:32.540727 BL = 0x2
3932 11:32:32.543705 RPST = 0x0
3933 11:32:32.544110 RD_PRE = 0x0
3934 11:32:32.546524 WR_PRE = 0x1
3935 11:32:32.546912 WR_PST = 0x0
3936 11:32:32.549978 DBI_WR = 0x0
3937 11:32:32.550366 DBI_RD = 0x0
3938 11:32:32.553558 OTF = 0x1
3939 11:32:32.556758 ===================================
3940 11:32:32.559815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 11:32:32.563691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 11:32:32.569743 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 11:32:32.572959 ===================================
3944 11:32:32.573423 LPDDR4 DRAM CONFIGURATION
3945 11:32:32.576418 ===================================
3946 11:32:32.580185 EX_ROW_EN[0] = 0x10
3947 11:32:32.583031 EX_ROW_EN[1] = 0x0
3948 11:32:32.583450 LP4Y_EN = 0x0
3949 11:32:32.586709 WORK_FSP = 0x0
3950 11:32:32.587109 WL = 0x2
3951 11:32:32.589466 RL = 0x2
3952 11:32:32.589867 BL = 0x2
3953 11:32:32.593047 RPST = 0x0
3954 11:32:32.593445 RD_PRE = 0x0
3955 11:32:32.595962 WR_PRE = 0x1
3956 11:32:32.596364 WR_PST = 0x0
3957 11:32:32.599609 DBI_WR = 0x0
3958 11:32:32.600005 DBI_RD = 0x0
3959 11:32:32.602766 OTF = 0x1
3960 11:32:32.605939 ===================================
3961 11:32:32.612647 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 11:32:32.616036 nWR fixed to 30
3963 11:32:32.619241 [ModeRegInit_LP4] CH0 RK0
3964 11:32:32.619673 [ModeRegInit_LP4] CH0 RK1
3965 11:32:32.622731 [ModeRegInit_LP4] CH1 RK0
3966 11:32:32.625971 [ModeRegInit_LP4] CH1 RK1
3967 11:32:32.626370 match AC timing 17
3968 11:32:32.632651 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 11:32:32.635376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 11:32:32.638909 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 11:32:32.646426 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 11:32:32.649449 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 11:32:32.649950 ==
3974 11:32:32.652434 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 11:32:32.655849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 11:32:32.656282 ==
3977 11:32:32.662574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 11:32:32.668872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3979 11:32:32.672138 [CA 0] Center 36 (6~66) winsize 61
3980 11:32:32.675311 [CA 1] Center 36 (6~66) winsize 61
3981 11:32:32.678694 [CA 2] Center 34 (4~64) winsize 61
3982 11:32:32.682114 [CA 3] Center 34 (4~65) winsize 62
3983 11:32:32.685171 [CA 4] Center 33 (3~64) winsize 62
3984 11:32:32.688948 [CA 5] Center 33 (3~64) winsize 62
3985 11:32:32.689349
3986 11:32:32.692601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3987 11:32:32.693113
3988 11:32:32.695272 [CATrainingPosCal] consider 1 rank data
3989 11:32:32.698979 u2DelayCellTimex100 = 270/100 ps
3990 11:32:32.702007 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 11:32:32.705245 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3992 11:32:32.708819 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 11:32:32.712442 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 11:32:32.715411 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 11:32:32.718374 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 11:32:32.721666
3997 11:32:32.725565 CA PerBit enable=1, Macro0, CA PI delay=33
3998 11:32:32.725996
3999 11:32:32.728367 [CBTSetCACLKResult] CA Dly = 33
4000 11:32:32.728796 CS Dly: 6 (0~37)
4001 11:32:32.729128 ==
4002 11:32:32.732090 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 11:32:32.734796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 11:32:32.738465 ==
4005 11:32:32.741901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 11:32:32.748366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4007 11:32:32.752052 [CA 0] Center 36 (6~66) winsize 61
4008 11:32:32.754692 [CA 1] Center 36 (6~66) winsize 61
4009 11:32:32.758568 [CA 2] Center 34 (4~64) winsize 61
4010 11:32:32.761411 [CA 3] Center 34 (4~64) winsize 61
4011 11:32:32.764928 [CA 4] Center 33 (3~64) winsize 62
4012 11:32:32.767765 [CA 5] Center 33 (2~64) winsize 63
4013 11:32:32.768194
4014 11:32:32.771421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4015 11:32:32.771972
4016 11:32:32.774516 [CATrainingPosCal] consider 2 rank data
4017 11:32:32.778010 u2DelayCellTimex100 = 270/100 ps
4018 11:32:32.781308 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 11:32:32.784356 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4020 11:32:32.787719 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4021 11:32:32.794283 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4022 11:32:32.797464 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 11:32:32.800798 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 11:32:32.801291
4025 11:32:32.804329 CA PerBit enable=1, Macro0, CA PI delay=33
4026 11:32:32.804830
4027 11:32:32.807559 [CBTSetCACLKResult] CA Dly = 33
4028 11:32:32.807991 CS Dly: 6 (0~37)
4029 11:32:32.808329
4030 11:32:32.810803 ----->DramcWriteLeveling(PI) begin...
4031 11:32:32.813882 ==
4032 11:32:32.817611 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 11:32:32.820502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 11:32:32.821003 ==
4035 11:32:32.823942 Write leveling (Byte 0): 31 => 31
4036 11:32:32.826970 Write leveling (Byte 1): 29 => 29
4037 11:32:32.830227 DramcWriteLeveling(PI) end<-----
4038 11:32:32.830656
4039 11:32:32.830983 ==
4040 11:32:32.834193 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 11:32:32.836857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 11:32:32.837288 ==
4043 11:32:32.840248 [Gating] SW mode calibration
4044 11:32:32.847196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 11:32:32.853712 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 11:32:32.857336 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 11:32:32.860173 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 11:32:32.866496 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 11:32:32.870070 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4050 11:32:32.873728 0 9 16 | B1->B0 | 2e2e 2727 | 1 0 | (1 1) (0 0)
4051 11:32:32.879996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:32:32.883328 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:32:32.887042 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:32:32.892799 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:32:32.896309 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:32:32.899739 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:32:32.906342 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:32:32.909971 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4059 11:32:32.913074 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:32:32.919529 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:32:32.923069 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:32:32.926262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:32:32.932793 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:32:32.936452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:32:32.939313 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 11:32:32.946102 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 11:32:32.949416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:32:32.952887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:32:32.959405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:32:32.962754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:32:32.965915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:32:32.972549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:32:32.975965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:32:32.978896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:32:32.985727 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:32:32.988857 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:32:32.992009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:32:32.999078 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:32:33.001794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:32:33.005321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:32:33.012095 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:32:33.015341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 11:32:33.018659 Total UI for P1: 0, mck2ui 16
4084 11:32:33.021477 best dqsien dly found for B0: ( 0, 13, 14)
4085 11:32:33.025395 Total UI for P1: 0, mck2ui 16
4086 11:32:33.028663 best dqsien dly found for B1: ( 0, 13, 14)
4087 11:32:33.032038 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4088 11:32:33.035112 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4089 11:32:33.035690
4090 11:32:33.038215 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 11:32:33.041522 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4092 11:32:33.045133 [Gating] SW calibration Done
4093 11:32:33.045630 ==
4094 11:32:33.048151 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 11:32:33.051585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 11:32:33.054865 ==
4097 11:32:33.055292 RX Vref Scan: 0
4098 11:32:33.055745
4099 11:32:33.057967 RX Vref 0 -> 0, step: 1
4100 11:32:33.058539
4101 11:32:33.061527 RX Delay -230 -> 252, step: 16
4102 11:32:33.064824 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4103 11:32:33.068397 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4104 11:32:33.070878 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4105 11:32:33.078139 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4106 11:32:33.081530 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4107 11:32:33.084423 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4108 11:32:33.088050 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 11:32:33.094242 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 11:32:33.097730 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4111 11:32:33.100788 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 11:32:33.104641 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 11:32:33.107593 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4114 11:32:33.114058 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4115 11:32:33.117226 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4116 11:32:33.120285 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4117 11:32:33.127506 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4118 11:32:33.128051 ==
4119 11:32:33.130501 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 11:32:33.134111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 11:32:33.134545 ==
4122 11:32:33.134878 DQS Delay:
4123 11:32:33.137282 DQS0 = 0, DQS1 = 0
4124 11:32:33.137714 DQM Delay:
4125 11:32:33.140348 DQM0 = 40, DQM1 = 30
4126 11:32:33.140774 DQ Delay:
4127 11:32:33.143951 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4128 11:32:33.146833 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4129 11:32:33.150428 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4130 11:32:33.153341 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4131 11:32:33.153767
4132 11:32:33.154098
4133 11:32:33.154402 ==
4134 11:32:33.157271 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 11:32:33.160389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:32:33.160824 ==
4137 11:32:33.161156
4138 11:32:33.163229
4139 11:32:33.163703 TX Vref Scan disable
4140 11:32:33.166945 == TX Byte 0 ==
4141 11:32:33.169916 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4142 11:32:33.173124 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4143 11:32:33.176661 == TX Byte 1 ==
4144 11:32:33.179676 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4145 11:32:33.183349 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4146 11:32:33.183896 ==
4147 11:32:33.186597 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:32:33.193171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:32:33.193610 ==
4150 11:32:33.193942
4151 11:32:33.194242
4152 11:32:33.194533 TX Vref Scan disable
4153 11:32:33.197989 == TX Byte 0 ==
4154 11:32:33.202101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4155 11:32:33.207871 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4156 11:32:33.208358 == TX Byte 1 ==
4157 11:32:33.211064 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4158 11:32:33.217516 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4159 11:32:33.217947
4160 11:32:33.218276 [DATLAT]
4161 11:32:33.218582 Freq=600, CH0 RK0
4162 11:32:33.218876
4163 11:32:33.221003 DATLAT Default: 0x9
4164 11:32:33.221428 0, 0xFFFF, sum = 0
4165 11:32:33.224465 1, 0xFFFF, sum = 0
4166 11:32:33.228111 2, 0xFFFF, sum = 0
4167 11:32:33.228617 3, 0xFFFF, sum = 0
4168 11:32:33.231083 4, 0xFFFF, sum = 0
4169 11:32:33.231535 5, 0xFFFF, sum = 0
4170 11:32:33.234284 6, 0xFFFF, sum = 0
4171 11:32:33.234787 7, 0xFFFF, sum = 0
4172 11:32:33.237482 8, 0x0, sum = 1
4173 11:32:33.237915 9, 0x0, sum = 2
4174 11:32:33.238252 10, 0x0, sum = 3
4175 11:32:33.240430 11, 0x0, sum = 4
4176 11:32:33.240861 best_step = 9
4177 11:32:33.241189
4178 11:32:33.243888 ==
4179 11:32:33.244313 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 11:32:33.250842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:32:33.251361 ==
4182 11:32:33.251755 RX Vref Scan: 1
4183 11:32:33.252065
4184 11:32:33.254205 RX Vref 0 -> 0, step: 1
4185 11:32:33.254700
4186 11:32:33.257102 RX Delay -195 -> 252, step: 8
4187 11:32:33.257654
4188 11:32:33.260484 Set Vref, RX VrefLevel [Byte0]: 55
4189 11:32:33.263701 [Byte1]: 49
4190 11:32:33.264214
4191 11:32:33.267185 Final RX Vref Byte 0 = 55 to rank0
4192 11:32:33.270495 Final RX Vref Byte 1 = 49 to rank0
4193 11:32:33.273697 Final RX Vref Byte 0 = 55 to rank1
4194 11:32:33.277010 Final RX Vref Byte 1 = 49 to rank1==
4195 11:32:33.280441 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:32:33.283521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:32:33.287195 ==
4198 11:32:33.287744 DQS Delay:
4199 11:32:33.288082 DQS0 = 0, DQS1 = 0
4200 11:32:33.290431 DQM Delay:
4201 11:32:33.290866 DQM0 = 43, DQM1 = 32
4202 11:32:33.293527 DQ Delay:
4203 11:32:33.294024 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4204 11:32:33.296939 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4205 11:32:33.300123 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4206 11:32:33.303094 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4207 11:32:33.306809
4208 11:32:33.307308
4209 11:32:33.313892 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4210 11:32:33.316630 CH0 RK0: MR19=808, MR18=6C44
4211 11:32:33.323225 CH0_RK0: MR19=0x808, MR18=0x6C44, DQSOSC=389, MR23=63, INC=173, DEC=115
4212 11:32:33.323686
4213 11:32:33.326590 ----->DramcWriteLeveling(PI) begin...
4214 11:32:33.327094 ==
4215 11:32:33.330110 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 11:32:33.333669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 11:32:33.334175 ==
4218 11:32:33.336277 Write leveling (Byte 0): 32 => 32
4219 11:32:33.339700 Write leveling (Byte 1): 30 => 30
4220 11:32:33.342821 DramcWriteLeveling(PI) end<-----
4221 11:32:33.343247
4222 11:32:33.343633 ==
4223 11:32:33.346209 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 11:32:33.349344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:32:33.349847 ==
4226 11:32:33.352605 [Gating] SW mode calibration
4227 11:32:33.359196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 11:32:33.366225 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 11:32:33.369445 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 11:32:33.376083 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 11:32:33.379697 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 11:32:33.383110 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4233 11:32:33.389107 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4234 11:32:33.392720 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:32:33.395917 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:32:33.402366 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:32:33.405484 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:32:33.409047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:32:33.415975 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:32:33.419087 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4241 11:32:33.422585 0 10 16 | B1->B0 | 3b3b 4242 | 0 1 | (0 0) (0 0)
4242 11:32:33.428833 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:32:33.432481 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:32:33.435644 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:32:33.441902 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:32:33.445543 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:32:33.448649 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:32:33.455172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4249 11:32:33.458693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4250 11:32:33.462233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:32:33.465401 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:32:33.472167 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:32:33.475383 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:32:33.478560 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:32:33.485305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:32:33.488471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:32:33.492066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:32:33.498540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:32:33.501787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:32:33.505442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:32:33.511501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:32:33.514853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:32:33.518366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:32:33.525098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4265 11:32:33.527799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 11:32:33.531620 Total UI for P1: 0, mck2ui 16
4267 11:32:33.534379 best dqsien dly found for B0: ( 0, 13, 12)
4268 11:32:33.537611 Total UI for P1: 0, mck2ui 16
4269 11:32:33.540867 best dqsien dly found for B1: ( 0, 13, 12)
4270 11:32:33.543989 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4271 11:32:33.547792 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4272 11:32:33.548214
4273 11:32:33.554172 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4274 11:32:33.557388 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4275 11:32:33.557976 [Gating] SW calibration Done
4276 11:32:33.560785 ==
4277 11:32:33.564060 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 11:32:33.567583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 11:32:33.568070 ==
4280 11:32:33.568405 RX Vref Scan: 0
4281 11:32:33.568709
4282 11:32:33.570800 RX Vref 0 -> 0, step: 1
4283 11:32:33.571300
4284 11:32:33.574004 RX Delay -230 -> 252, step: 16
4285 11:32:33.577236 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4286 11:32:33.580192 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4287 11:32:33.587071 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4288 11:32:33.590331 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4289 11:32:33.593487 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4290 11:32:33.597141 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4291 11:32:33.603503 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4292 11:32:33.606645 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4293 11:32:33.609983 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4294 11:32:33.613656 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4295 11:32:33.619896 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4296 11:32:33.622845 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4297 11:32:33.626228 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4298 11:32:33.630162 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4299 11:32:33.636469 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4300 11:32:33.639686 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4301 11:32:33.640156 ==
4302 11:32:33.642854 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 11:32:33.646257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 11:32:33.646748 ==
4305 11:32:33.649359 DQS Delay:
4306 11:32:33.649893 DQS0 = 0, DQS1 = 0
4307 11:32:33.650371 DQM Delay:
4308 11:32:33.652782 DQM0 = 43, DQM1 = 37
4309 11:32:33.653247 DQ Delay:
4310 11:32:33.655686 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4311 11:32:33.659359 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4312 11:32:33.662340 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4313 11:32:33.665775 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4314 11:32:33.666317
4315 11:32:33.666742
4316 11:32:33.667036 ==
4317 11:32:33.669214 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:32:33.675373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:32:33.675668 ==
4320 11:32:33.675900
4321 11:32:33.676131
4322 11:32:33.676349 TX Vref Scan disable
4323 11:32:33.679166 == TX Byte 0 ==
4324 11:32:33.682539 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4325 11:32:33.689266 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4326 11:32:33.689432 == TX Byte 1 ==
4327 11:32:33.692807 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4328 11:32:33.698949 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4329 11:32:33.699046 ==
4330 11:32:33.702058 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:32:33.705292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:32:33.705394 ==
4333 11:32:33.705485
4334 11:32:33.705581
4335 11:32:33.708902 TX Vref Scan disable
4336 11:32:33.712096 == TX Byte 0 ==
4337 11:32:33.715413 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4338 11:32:33.718741 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4339 11:32:33.722168 == TX Byte 1 ==
4340 11:32:33.725263 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4341 11:32:33.728888 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4342 11:32:33.728983
4343 11:32:33.731958 [DATLAT]
4344 11:32:33.732061 Freq=600, CH0 RK1
4345 11:32:33.732140
4346 11:32:33.735202 DATLAT Default: 0x9
4347 11:32:33.735345 0, 0xFFFF, sum = 0
4348 11:32:33.738430 1, 0xFFFF, sum = 0
4349 11:32:33.738550 2, 0xFFFF, sum = 0
4350 11:32:33.741864 3, 0xFFFF, sum = 0
4351 11:32:33.741992 4, 0xFFFF, sum = 0
4352 11:32:33.745561 5, 0xFFFF, sum = 0
4353 11:32:33.745690 6, 0xFFFF, sum = 0
4354 11:32:33.748677 7, 0xFFFF, sum = 0
4355 11:32:33.748889 8, 0x0, sum = 1
4356 11:32:33.751706 9, 0x0, sum = 2
4357 11:32:33.751924 10, 0x0, sum = 3
4358 11:32:33.755176 11, 0x0, sum = 4
4359 11:32:33.755459 best_step = 9
4360 11:32:33.755624
4361 11:32:33.755757 ==
4362 11:32:33.758672 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 11:32:33.761757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:32:33.762150 ==
4365 11:32:33.765707 RX Vref Scan: 0
4366 11:32:33.766080
4367 11:32:33.768715 RX Vref 0 -> 0, step: 1
4368 11:32:33.769117
4369 11:32:33.769416 RX Delay -179 -> 252, step: 8
4370 11:32:33.776641 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4371 11:32:33.779997 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4372 11:32:33.782964 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4373 11:32:33.786850 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4374 11:32:33.793347 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4375 11:32:33.796255 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4376 11:32:33.799808 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4377 11:32:33.803150 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4378 11:32:33.806707 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4379 11:32:33.812701 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4380 11:32:33.816035 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4381 11:32:33.819958 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4382 11:32:33.822935 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4383 11:32:33.829506 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4384 11:32:33.832661 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4385 11:32:33.835822 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4386 11:32:33.836248 ==
4387 11:32:33.839261 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 11:32:33.846068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 11:32:33.846578 ==
4390 11:32:33.846915 DQS Delay:
4391 11:32:33.847220 DQS0 = 0, DQS1 = 0
4392 11:32:33.849389 DQM Delay:
4393 11:32:33.849889 DQM0 = 42, DQM1 = 36
4394 11:32:33.853216 DQ Delay:
4395 11:32:33.856092 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4396 11:32:33.859496 DQ4 =40, DQ5 =36, DQ6 =52, DQ7 =52
4397 11:32:33.862635 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4398 11:32:33.865724 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4399 11:32:33.866298
4400 11:32:33.866637
4401 11:32:33.872273 [DQSOSCAuto] RK1, (LSB)MR18= 0x6215, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4402 11:32:33.876147 CH0 RK1: MR19=808, MR18=6215
4403 11:32:33.882340 CH0_RK1: MR19=0x808, MR18=0x6215, DQSOSC=391, MR23=63, INC=171, DEC=114
4404 11:32:33.885441 [RxdqsGatingPostProcess] freq 600
4405 11:32:33.888889 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4406 11:32:33.892160 Pre-setting of DQS Precalculation
4407 11:32:33.898930 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4408 11:32:33.899422 ==
4409 11:32:33.901919 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 11:32:33.905507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 11:32:33.905951 ==
4412 11:32:33.911773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 11:32:33.918590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4414 11:32:33.921607 [CA 0] Center 35 (5~66) winsize 62
4415 11:32:33.925043 [CA 1] Center 35 (5~66) winsize 62
4416 11:32:33.928097 [CA 2] Center 34 (4~65) winsize 62
4417 11:32:33.931390 [CA 3] Center 33 (3~64) winsize 62
4418 11:32:33.934801 [CA 4] Center 34 (4~64) winsize 61
4419 11:32:33.937956 [CA 5] Center 33 (3~64) winsize 62
4420 11:32:33.938380
4421 11:32:33.941771 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4422 11:32:33.942268
4423 11:32:33.945090 [CATrainingPosCal] consider 1 rank data
4424 11:32:33.948153 u2DelayCellTimex100 = 270/100 ps
4425 11:32:33.951394 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 11:32:33.954351 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 11:32:33.958291 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 11:32:33.961699 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 11:32:33.964573 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4430 11:32:33.968190 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 11:32:33.971253
4432 11:32:33.974798 CA PerBit enable=1, Macro0, CA PI delay=33
4433 11:32:33.975512
4434 11:32:33.977893 [CBTSetCACLKResult] CA Dly = 33
4435 11:32:33.978400 CS Dly: 5 (0~36)
4436 11:32:33.978733 ==
4437 11:32:33.980883 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 11:32:33.984509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 11:32:33.987328 ==
4440 11:32:33.990930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4441 11:32:33.997349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4442 11:32:34.000805 [CA 0] Center 35 (5~66) winsize 62
4443 11:32:34.004459 [CA 1] Center 36 (6~66) winsize 61
4444 11:32:34.007123 [CA 2] Center 34 (3~65) winsize 63
4445 11:32:34.010662 [CA 3] Center 33 (3~64) winsize 62
4446 11:32:34.013782 [CA 4] Center 34 (4~65) winsize 62
4447 11:32:34.017720 [CA 5] Center 34 (3~65) winsize 63
4448 11:32:34.018175
4449 11:32:34.020772 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4450 11:32:34.021199
4451 11:32:34.023858 [CATrainingPosCal] consider 2 rank data
4452 11:32:34.028042 u2DelayCellTimex100 = 270/100 ps
4453 11:32:34.030384 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4454 11:32:34.033809 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4455 11:32:34.037294 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 11:32:34.043986 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 11:32:34.047021 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4458 11:32:34.050549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 11:32:34.051125
4460 11:32:34.053982 CA PerBit enable=1, Macro0, CA PI delay=33
4461 11:32:34.054422
4462 11:32:34.056971 [CBTSetCACLKResult] CA Dly = 33
4463 11:32:34.057395 CS Dly: 5 (0~37)
4464 11:32:34.057723
4465 11:32:34.060246 ----->DramcWriteLeveling(PI) begin...
4466 11:32:34.060800 ==
4467 11:32:34.063328 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 11:32:34.069997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 11:32:34.070439 ==
4470 11:32:34.073515 Write leveling (Byte 0): 28 => 28
4471 11:32:34.076562 Write leveling (Byte 1): 29 => 29
4472 11:32:34.080381 DramcWriteLeveling(PI) end<-----
4473 11:32:34.080844
4474 11:32:34.081146 ==
4475 11:32:34.083461 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 11:32:34.086965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 11:32:34.087467 ==
4478 11:32:34.089737 [Gating] SW mode calibration
4479 11:32:34.096494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4480 11:32:34.103467 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4481 11:32:34.106504 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 11:32:34.109907 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 11:32:34.115982 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4484 11:32:34.119809 0 9 12 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
4485 11:32:34.123340 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4486 11:32:34.129219 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:32:34.133016 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:32:34.136021 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 11:32:34.142722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:32:34.145948 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 11:32:34.149317 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4492 11:32:34.156090 0 10 12 | B1->B0 | 2a2a 3c3c | 0 1 | (0 0) (0 0)
4493 11:32:34.159359 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4494 11:32:34.163013 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:32:34.169416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:32:34.172739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:32:34.176420 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:32:34.179273 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 11:32:34.185749 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:32:34.189406 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4501 11:32:34.192603 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:32:34.198797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:32:34.202174 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:32:34.205337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:32:34.212258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:32:34.215386 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:32:34.218923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:32:34.225246 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:32:34.228354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:32:34.232026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:32:34.238850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:32:34.242111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:32:34.245338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:32:34.251744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:32:34.255170 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:32:34.258370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4517 11:32:34.265134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 11:32:34.267954 Total UI for P1: 0, mck2ui 16
4519 11:32:34.271668 best dqsien dly found for B0: ( 0, 13, 12)
4520 11:32:34.274966 Total UI for P1: 0, mck2ui 16
4521 11:32:34.278263 best dqsien dly found for B1: ( 0, 13, 14)
4522 11:32:34.281456 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4523 11:32:34.284471 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4524 11:32:34.284904
4525 11:32:34.288120 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4526 11:32:34.291153 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4527 11:32:34.294495 [Gating] SW calibration Done
4528 11:32:34.295223 ==
4529 11:32:34.297740 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 11:32:34.300811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 11:32:34.301236 ==
4532 11:32:34.304429 RX Vref Scan: 0
4533 11:32:34.304863
4534 11:32:34.307770 RX Vref 0 -> 0, step: 1
4535 11:32:34.308196
4536 11:32:34.311079 RX Delay -230 -> 252, step: 16
4537 11:32:34.314470 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4538 11:32:34.317463 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4539 11:32:34.320494 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4540 11:32:34.323871 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4541 11:32:34.330505 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4542 11:32:34.334623 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4543 11:32:34.337161 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4544 11:32:34.340471 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4545 11:32:34.346960 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4546 11:32:34.350355 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4547 11:32:34.353757 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4548 11:32:34.357224 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4549 11:32:34.363436 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4550 11:32:34.367321 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4551 11:32:34.370131 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4552 11:32:34.373444 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4553 11:32:34.373568 ==
4554 11:32:34.376384 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 11:32:34.383407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 11:32:34.383551 ==
4557 11:32:34.383648 DQS Delay:
4558 11:32:34.386689 DQS0 = 0, DQS1 = 0
4559 11:32:34.386812 DQM Delay:
4560 11:32:34.386907 DQM0 = 42, DQM1 = 35
4561 11:32:34.390302 DQ Delay:
4562 11:32:34.393145 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =33
4563 11:32:34.396345 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =41
4564 11:32:34.399988 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4565 11:32:34.403161 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4566 11:32:34.403274
4567 11:32:34.403359
4568 11:32:34.403450 ==
4569 11:32:34.406497 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 11:32:34.409782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:32:34.409896 ==
4572 11:32:34.409971
4573 11:32:34.410039
4574 11:32:34.413541 TX Vref Scan disable
4575 11:32:34.416459 == TX Byte 0 ==
4576 11:32:34.419992 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4577 11:32:34.422736 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4578 11:32:34.426583 == TX Byte 1 ==
4579 11:32:34.429319 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 11:32:34.432759 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 11:32:34.432836 ==
4582 11:32:34.435922 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 11:32:34.439718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 11:32:34.443093 ==
4585 11:32:34.443169
4586 11:32:34.443229
4587 11:32:34.443283 TX Vref Scan disable
4588 11:32:34.446554 == TX Byte 0 ==
4589 11:32:34.449670 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 11:32:34.456270 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 11:32:34.456349 == TX Byte 1 ==
4592 11:32:34.459638 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4593 11:32:34.466150 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4594 11:32:34.466232
4595 11:32:34.466291 [DATLAT]
4596 11:32:34.466345 Freq=600, CH1 RK0
4597 11:32:34.466398
4598 11:32:34.469478 DATLAT Default: 0x9
4599 11:32:34.472645 0, 0xFFFF, sum = 0
4600 11:32:34.472722 1, 0xFFFF, sum = 0
4601 11:32:34.476175 2, 0xFFFF, sum = 0
4602 11:32:34.476252 3, 0xFFFF, sum = 0
4603 11:32:34.479876 4, 0xFFFF, sum = 0
4604 11:32:34.479958 5, 0xFFFF, sum = 0
4605 11:32:34.482756 6, 0xFFFF, sum = 0
4606 11:32:34.482844 7, 0xFFFF, sum = 0
4607 11:32:34.486282 8, 0x0, sum = 1
4608 11:32:34.486373 9, 0x0, sum = 2
4609 11:32:34.486433 10, 0x0, sum = 3
4610 11:32:34.489590 11, 0x0, sum = 4
4611 11:32:34.489668 best_step = 9
4612 11:32:34.489726
4613 11:32:34.493029 ==
4614 11:32:34.493105 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 11:32:34.499329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:32:34.499405 ==
4617 11:32:34.499505 RX Vref Scan: 1
4618 11:32:34.499560
4619 11:32:34.502666 RX Vref 0 -> 0, step: 1
4620 11:32:34.502742
4621 11:32:34.506138 RX Delay -195 -> 252, step: 8
4622 11:32:34.506214
4623 11:32:34.509056 Set Vref, RX VrefLevel [Byte0]: 50
4624 11:32:34.512412 [Byte1]: 51
4625 11:32:34.512487
4626 11:32:34.515974 Final RX Vref Byte 0 = 50 to rank0
4627 11:32:34.519067 Final RX Vref Byte 1 = 51 to rank0
4628 11:32:34.522720 Final RX Vref Byte 0 = 50 to rank1
4629 11:32:34.525899 Final RX Vref Byte 1 = 51 to rank1==
4630 11:32:34.529183 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 11:32:34.532619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 11:32:34.535592 ==
4633 11:32:34.535667 DQS Delay:
4634 11:32:34.535726 DQS0 = 0, DQS1 = 0
4635 11:32:34.539143 DQM Delay:
4636 11:32:34.539218 DQM0 = 45, DQM1 = 33
4637 11:32:34.542179 DQ Delay:
4638 11:32:34.542254 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4639 11:32:34.545921 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4640 11:32:34.548858 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4641 11:32:34.552492 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4642 11:32:34.555614
4643 11:32:34.555690
4644 11:32:34.561954 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4645 11:32:34.565299 CH1 RK0: MR19=808, MR18=4C30
4646 11:32:34.572614 CH1_RK0: MR19=0x808, MR18=0x4C30, DQSOSC=395, MR23=63, INC=168, DEC=112
4647 11:32:34.572698
4648 11:32:34.574849 ----->DramcWriteLeveling(PI) begin...
4649 11:32:34.574932 ==
4650 11:32:34.578837 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 11:32:34.581613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 11:32:34.581690 ==
4653 11:32:34.584783 Write leveling (Byte 0): 30 => 30
4654 11:32:34.588379 Write leveling (Byte 1): 30 => 30
4655 11:32:34.591860 DramcWriteLeveling(PI) end<-----
4656 11:32:34.591936
4657 11:32:34.591994 ==
4658 11:32:34.595021 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 11:32:34.597909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 11:32:34.597986 ==
4661 11:32:34.602098 [Gating] SW mode calibration
4662 11:32:34.608595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 11:32:34.614803 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 11:32:34.618056 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 11:32:34.624525 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 11:32:34.627676 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 11:32:34.630959 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
4668 11:32:34.637804 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4669 11:32:34.641512 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 11:32:34.645013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:32:34.650983 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 11:32:34.654364 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 11:32:34.657659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:32:34.664450 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:32:34.667389 0 10 12 | B1->B0 | 3434 2e2e | 0 0 | (1 1) (0 0)
4676 11:32:34.670542 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 11:32:34.677226 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 11:32:34.680560 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:32:34.684176 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 11:32:34.690869 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:32:34.694439 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 11:32:34.697762 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:32:34.704317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4684 11:32:34.707163 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:32:34.710601 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:32:34.714172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:32:34.720767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:32:34.724239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:32:34.726851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:32:34.733658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:32:34.736971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:32:34.740505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:32:34.747336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:32:34.750453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:32:34.753766 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:32:34.760305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:32:34.763215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:32:34.766756 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:32:34.773470 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4700 11:32:34.777438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 11:32:34.779972 Total UI for P1: 0, mck2ui 16
4702 11:32:34.783192 best dqsien dly found for B0: ( 0, 13, 12)
4703 11:32:34.786658 Total UI for P1: 0, mck2ui 16
4704 11:32:34.789627 best dqsien dly found for B1: ( 0, 13, 14)
4705 11:32:34.793860 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4706 11:32:34.796548 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4707 11:32:34.796674
4708 11:32:34.799821 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4709 11:32:34.806348 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4710 11:32:34.806425 [Gating] SW calibration Done
4711 11:32:34.806485 ==
4712 11:32:34.809612 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 11:32:34.816422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 11:32:34.816516 ==
4715 11:32:34.816585 RX Vref Scan: 0
4716 11:32:34.816671
4717 11:32:34.819534 RX Vref 0 -> 0, step: 1
4718 11:32:34.819663
4719 11:32:34.822876 RX Delay -230 -> 252, step: 16
4720 11:32:34.826396 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4721 11:32:34.829776 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4722 11:32:34.836187 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4723 11:32:34.839343 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4724 11:32:34.843181 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4725 11:32:34.845984 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4726 11:32:34.852807 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4727 11:32:34.855856 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4728 11:32:34.859079 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4729 11:32:34.862448 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4730 11:32:34.865358 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4731 11:32:34.872228 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4732 11:32:34.875224 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4733 11:32:34.878635 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4734 11:32:34.881862 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4735 11:32:34.888556 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4736 11:32:34.888653 ==
4737 11:32:34.891945 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 11:32:34.895051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 11:32:34.895128 ==
4740 11:32:34.895188 DQS Delay:
4741 11:32:34.898238 DQS0 = 0, DQS1 = 0
4742 11:32:34.898314 DQM Delay:
4743 11:32:34.902371 DQM0 = 42, DQM1 = 32
4744 11:32:34.902446 DQ Delay:
4745 11:32:34.905050 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4746 11:32:34.908245 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4747 11:32:34.911734 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4748 11:32:34.914747 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =49
4749 11:32:34.914822
4750 11:32:34.914880
4751 11:32:34.914934 ==
4752 11:32:34.918305 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 11:32:34.924745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 11:32:34.924822 ==
4755 11:32:34.924884
4756 11:32:34.924938
4757 11:32:34.924989 TX Vref Scan disable
4758 11:32:34.928275 == TX Byte 0 ==
4759 11:32:34.931852 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4760 11:32:34.938264 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4761 11:32:34.938341 == TX Byte 1 ==
4762 11:32:34.941345 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 11:32:34.947979 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 11:32:34.948056 ==
4765 11:32:34.951250 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 11:32:34.954691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 11:32:34.954767 ==
4768 11:32:34.954826
4769 11:32:34.954879
4770 11:32:34.957912 TX Vref Scan disable
4771 11:32:34.960963 == TX Byte 0 ==
4772 11:32:34.964358 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4773 11:32:34.967737 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4774 11:32:34.971078 == TX Byte 1 ==
4775 11:32:34.974121 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 11:32:34.978249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 11:32:34.978325
4778 11:32:34.981438 [DATLAT]
4779 11:32:34.981513 Freq=600, CH1 RK1
4780 11:32:34.981571
4781 11:32:34.984287 DATLAT Default: 0x9
4782 11:32:34.984363 0, 0xFFFF, sum = 0
4783 11:32:34.987547 1, 0xFFFF, sum = 0
4784 11:32:34.987623 2, 0xFFFF, sum = 0
4785 11:32:34.990598 3, 0xFFFF, sum = 0
4786 11:32:34.990675 4, 0xFFFF, sum = 0
4787 11:32:34.994191 5, 0xFFFF, sum = 0
4788 11:32:34.994267 6, 0xFFFF, sum = 0
4789 11:32:34.997380 7, 0xFFFF, sum = 0
4790 11:32:34.997457 8, 0x0, sum = 1
4791 11:32:35.000427 9, 0x0, sum = 2
4792 11:32:35.000503 10, 0x0, sum = 3
4793 11:32:35.003929 11, 0x0, sum = 4
4794 11:32:35.004007 best_step = 9
4795 11:32:35.004065
4796 11:32:35.004119 ==
4797 11:32:35.007213 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 11:32:35.010410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 11:32:35.010486 ==
4800 11:32:35.013768 RX Vref Scan: 0
4801 11:32:35.013844
4802 11:32:35.017276 RX Vref 0 -> 0, step: 1
4803 11:32:35.017354
4804 11:32:35.020407 RX Delay -195 -> 252, step: 8
4805 11:32:35.023470 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4806 11:32:35.026884 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4807 11:32:35.033308 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4808 11:32:35.036733 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4809 11:32:35.040023 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4810 11:32:35.043540 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4811 11:32:35.049997 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4812 11:32:35.053356 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4813 11:32:35.057105 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4814 11:32:35.060019 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4815 11:32:35.063319 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4816 11:32:35.069945 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4817 11:32:35.072884 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4818 11:32:35.076749 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4819 11:32:35.079795 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4820 11:32:35.086496 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4821 11:32:35.086572 ==
4822 11:32:35.089685 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 11:32:35.092630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 11:32:35.092723 ==
4825 11:32:35.095940 DQS Delay:
4826 11:32:35.096028 DQS0 = 0, DQS1 = 0
4827 11:32:35.096089 DQM Delay:
4828 11:32:35.099619 DQM0 = 42, DQM1 = 34
4829 11:32:35.099695 DQ Delay:
4830 11:32:35.103085 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4831 11:32:35.105829 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4832 11:32:35.109351 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4833 11:32:35.112670 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4834 11:32:35.112745
4835 11:32:35.112803
4836 11:32:35.122461 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4837 11:32:35.122539 CH1 RK1: MR19=808, MR18=2D23
4838 11:32:35.129074 CH1_RK1: MR19=0x808, MR18=0x2D23, DQSOSC=401, MR23=63, INC=163, DEC=108
4839 11:32:35.132566 [RxdqsGatingPostProcess] freq 600
4840 11:32:35.139334 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 11:32:35.142311 Pre-setting of DQS Precalculation
4842 11:32:35.145452 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 11:32:35.155671 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 11:32:35.162099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 11:32:35.162176
4846 11:32:35.162234
4847 11:32:35.165387 [Calibration Summary] 1200 Mbps
4848 11:32:35.165463 CH 0, Rank 0
4849 11:32:35.169055 SW Impedance : PASS
4850 11:32:35.169130 DUTY Scan : NO K
4851 11:32:35.172102 ZQ Calibration : PASS
4852 11:32:35.175361 Jitter Meter : NO K
4853 11:32:35.175491 CBT Training : PASS
4854 11:32:35.179001 Write leveling : PASS
4855 11:32:35.181914 RX DQS gating : PASS
4856 11:32:35.181990 RX DQ/DQS(RDDQC) : PASS
4857 11:32:35.185574 TX DQ/DQS : PASS
4858 11:32:35.188803 RX DATLAT : PASS
4859 11:32:35.188892 RX DQ/DQS(Engine): PASS
4860 11:32:35.191868 TX OE : NO K
4861 11:32:35.191943 All Pass.
4862 11:32:35.192001
4863 11:32:35.195053 CH 0, Rank 1
4864 11:32:35.195127 SW Impedance : PASS
4865 11:32:35.198317 DUTY Scan : NO K
4866 11:32:35.201705 ZQ Calibration : PASS
4867 11:32:35.201780 Jitter Meter : NO K
4868 11:32:35.204870 CBT Training : PASS
4869 11:32:35.204962 Write leveling : PASS
4870 11:32:35.208054 RX DQS gating : PASS
4871 11:32:35.212353 RX DQ/DQS(RDDQC) : PASS
4872 11:32:35.212428 TX DQ/DQS : PASS
4873 11:32:35.215003 RX DATLAT : PASS
4874 11:32:35.218258 RX DQ/DQS(Engine): PASS
4875 11:32:35.218333 TX OE : NO K
4876 11:32:35.221538 All Pass.
4877 11:32:35.221612
4878 11:32:35.221670 CH 1, Rank 0
4879 11:32:35.224943 SW Impedance : PASS
4880 11:32:35.225019 DUTY Scan : NO K
4881 11:32:35.228210 ZQ Calibration : PASS
4882 11:32:35.231196 Jitter Meter : NO K
4883 11:32:35.231270 CBT Training : PASS
4884 11:32:35.234706 Write leveling : PASS
4885 11:32:35.238004 RX DQS gating : PASS
4886 11:32:35.238079 RX DQ/DQS(RDDQC) : PASS
4887 11:32:35.241115 TX DQ/DQS : PASS
4888 11:32:35.244649 RX DATLAT : PASS
4889 11:32:35.244724 RX DQ/DQS(Engine): PASS
4890 11:32:35.247956 TX OE : NO K
4891 11:32:35.248032 All Pass.
4892 11:32:35.248090
4893 11:32:35.251536 CH 1, Rank 1
4894 11:32:35.251612 SW Impedance : PASS
4895 11:32:35.254433 DUTY Scan : NO K
4896 11:32:35.257940 ZQ Calibration : PASS
4897 11:32:35.258015 Jitter Meter : NO K
4898 11:32:35.260870 CBT Training : PASS
4899 11:32:35.264469 Write leveling : PASS
4900 11:32:35.264544 RX DQS gating : PASS
4901 11:32:35.268108 RX DQ/DQS(RDDQC) : PASS
4902 11:32:35.270873 TX DQ/DQS : PASS
4903 11:32:35.270948 RX DATLAT : PASS
4904 11:32:35.274104 RX DQ/DQS(Engine): PASS
4905 11:32:35.274179 TX OE : NO K
4906 11:32:35.277647 All Pass.
4907 11:32:35.277722
4908 11:32:35.277780 DramC Write-DBI off
4909 11:32:35.280945 PER_BANK_REFRESH: Hybrid Mode
4910 11:32:35.284180 TX_TRACKING: ON
4911 11:32:35.290863 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 11:32:35.294130 [FAST_K] Save calibration result to emmc
4913 11:32:35.300508 dramc_set_vcore_voltage set vcore to 662500
4914 11:32:35.300584 Read voltage for 933, 3
4915 11:32:35.304173 Vio18 = 0
4916 11:32:35.304249 Vcore = 662500
4917 11:32:35.304307 Vdram = 0
4918 11:32:35.304361 Vddq = 0
4919 11:32:35.307373 Vmddr = 0
4920 11:32:35.310612 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 11:32:35.317204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 11:32:35.320474 MEM_TYPE=3, freq_sel=17
4923 11:32:35.323883 sv_algorithm_assistance_LP4_1600
4924 11:32:35.326713 ============ PULL DRAM RESETB DOWN ============
4925 11:32:35.330436 ========== PULL DRAM RESETB DOWN end =========
4926 11:32:35.333655 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 11:32:35.336779 ===================================
4928 11:32:35.340454 LPDDR4 DRAM CONFIGURATION
4929 11:32:35.343318 ===================================
4930 11:32:35.346698 EX_ROW_EN[0] = 0x0
4931 11:32:35.346773 EX_ROW_EN[1] = 0x0
4932 11:32:35.350011 LP4Y_EN = 0x0
4933 11:32:35.350086 WORK_FSP = 0x0
4934 11:32:35.353722 WL = 0x3
4935 11:32:35.353797 RL = 0x3
4936 11:32:35.357036 BL = 0x2
4937 11:32:35.357112 RPST = 0x0
4938 11:32:35.360273 RD_PRE = 0x0
4939 11:32:35.360348 WR_PRE = 0x1
4940 11:32:35.363118 WR_PST = 0x0
4941 11:32:35.366855 DBI_WR = 0x0
4942 11:32:35.366930 DBI_RD = 0x0
4943 11:32:35.369981 OTF = 0x1
4944 11:32:35.373120 ===================================
4945 11:32:35.377019 ===================================
4946 11:32:35.377094 ANA top config
4947 11:32:35.379926 ===================================
4948 11:32:35.383451 DLL_ASYNC_EN = 0
4949 11:32:35.386424 ALL_SLAVE_EN = 1
4950 11:32:35.386500 NEW_RANK_MODE = 1
4951 11:32:35.389663 DLL_IDLE_MODE = 1
4952 11:32:35.393043 LP45_APHY_COMB_EN = 1
4953 11:32:35.396194 TX_ODT_DIS = 1
4954 11:32:35.396269 NEW_8X_MODE = 1
4955 11:32:35.399647 ===================================
4956 11:32:35.402671 ===================================
4957 11:32:35.406311 data_rate = 1866
4958 11:32:35.409468 CKR = 1
4959 11:32:35.413041 DQ_P2S_RATIO = 8
4960 11:32:35.416008 ===================================
4961 11:32:35.419314 CA_P2S_RATIO = 8
4962 11:32:35.422825 DQ_CA_OPEN = 0
4963 11:32:35.426146 DQ_SEMI_OPEN = 0
4964 11:32:35.426214 CA_SEMI_OPEN = 0
4965 11:32:35.429185 CA_FULL_RATE = 0
4966 11:32:35.432577 DQ_CKDIV4_EN = 1
4967 11:32:35.435940 CA_CKDIV4_EN = 1
4968 11:32:35.439278 CA_PREDIV_EN = 0
4969 11:32:35.442292 PH8_DLY = 0
4970 11:32:35.442382 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 11:32:35.445562 DQ_AAMCK_DIV = 4
4972 11:32:35.449145 CA_AAMCK_DIV = 4
4973 11:32:35.452311 CA_ADMCK_DIV = 4
4974 11:32:35.455288 DQ_TRACK_CA_EN = 0
4975 11:32:35.458684 CA_PICK = 933
4976 11:32:35.462210 CA_MCKIO = 933
4977 11:32:35.462284 MCKIO_SEMI = 0
4978 11:32:35.465331 PLL_FREQ = 3732
4979 11:32:35.468853 DQ_UI_PI_RATIO = 32
4980 11:32:35.471985 CA_UI_PI_RATIO = 0
4981 11:32:35.475380 ===================================
4982 11:32:35.478611 ===================================
4983 11:32:35.482321 memory_type:LPDDR4
4984 11:32:35.482419 GP_NUM : 10
4985 11:32:35.485300 SRAM_EN : 1
4986 11:32:35.488562 MD32_EN : 0
4987 11:32:35.491591 ===================================
4988 11:32:35.491677 [ANA_INIT] >>>>>>>>>>>>>>
4989 11:32:35.494995 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 11:32:35.498332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 11:32:35.501886 ===================================
4992 11:32:35.504893 data_rate = 1866,PCW = 0X8f00
4993 11:32:35.508334 ===================================
4994 11:32:35.511368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 11:32:35.518129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 11:32:35.521477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 11:32:35.527694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 11:32:35.531379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 11:32:35.534489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 11:32:35.537733 [ANA_INIT] flow start
5001 11:32:35.537831 [ANA_INIT] PLL >>>>>>>>
5002 11:32:35.541096 [ANA_INIT] PLL <<<<<<<<
5003 11:32:35.544316 [ANA_INIT] MIDPI >>>>>>>>
5004 11:32:35.544378 [ANA_INIT] MIDPI <<<<<<<<
5005 11:32:35.547719 [ANA_INIT] DLL >>>>>>>>
5006 11:32:35.550753 [ANA_INIT] flow end
5007 11:32:35.554501 ============ LP4 DIFF to SE enter ============
5008 11:32:35.557296 ============ LP4 DIFF to SE exit ============
5009 11:32:35.560649 [ANA_INIT] <<<<<<<<<<<<<
5010 11:32:35.563843 [Flow] Enable top DCM control >>>>>
5011 11:32:35.567033 [Flow] Enable top DCM control <<<<<
5012 11:32:35.570728 Enable DLL master slave shuffle
5013 11:32:35.573692 ==============================================================
5014 11:32:35.577091 Gating Mode config
5015 11:32:35.583936 ==============================================================
5016 11:32:35.584005 Config description:
5017 11:32:35.593826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 11:32:35.600222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 11:32:35.606950 SELPH_MODE 0: By rank 1: By Phase
5020 11:32:35.610134 ==============================================================
5021 11:32:35.613422 GAT_TRACK_EN = 1
5022 11:32:35.616541 RX_GATING_MODE = 2
5023 11:32:35.619952 RX_GATING_TRACK_MODE = 2
5024 11:32:35.623755 SELPH_MODE = 1
5025 11:32:35.626651 PICG_EARLY_EN = 1
5026 11:32:35.629665 VALID_LAT_VALUE = 1
5027 11:32:35.636767 ==============================================================
5028 11:32:35.639415 Enter into Gating configuration >>>>
5029 11:32:35.643053 Exit from Gating configuration <<<<
5030 11:32:35.643145 Enter into DVFS_PRE_config >>>>>
5031 11:32:35.656152 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 11:32:35.659551 Exit from DVFS_PRE_config <<<<<
5033 11:32:35.662845 Enter into PICG configuration >>>>
5034 11:32:35.666040 Exit from PICG configuration <<<<
5035 11:32:35.669366 [RX_INPUT] configuration >>>>>
5036 11:32:35.669458 [RX_INPUT] configuration <<<<<
5037 11:32:35.675996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 11:32:35.682612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 11:32:35.685641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 11:32:35.692352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 11:32:35.698720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 11:32:35.705495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 11:32:35.708846 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 11:32:35.711807 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 11:32:35.718681 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 11:32:35.721865 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 11:32:35.725066 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 11:32:35.732068 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 11:32:35.735192 ===================================
5050 11:32:35.735290 LPDDR4 DRAM CONFIGURATION
5051 11:32:35.738727 ===================================
5052 11:32:35.741588 EX_ROW_EN[0] = 0x0
5053 11:32:35.745261 EX_ROW_EN[1] = 0x0
5054 11:32:35.745349 LP4Y_EN = 0x0
5055 11:32:35.748304 WORK_FSP = 0x0
5056 11:32:35.748385 WL = 0x3
5057 11:32:35.751759 RL = 0x3
5058 11:32:35.751834 BL = 0x2
5059 11:32:35.754775 RPST = 0x0
5060 11:32:35.754850 RD_PRE = 0x0
5061 11:32:35.758265 WR_PRE = 0x1
5062 11:32:35.758341 WR_PST = 0x0
5063 11:32:35.761520 DBI_WR = 0x0
5064 11:32:35.761606 DBI_RD = 0x0
5065 11:32:35.765019 OTF = 0x1
5066 11:32:35.767951 ===================================
5067 11:32:35.771501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 11:32:35.774762 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 11:32:35.781186 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 11:32:35.784701 ===================================
5071 11:32:35.784777 LPDDR4 DRAM CONFIGURATION
5072 11:32:35.787777 ===================================
5073 11:32:35.791309 EX_ROW_EN[0] = 0x10
5074 11:32:35.794523 EX_ROW_EN[1] = 0x0
5075 11:32:35.794598 LP4Y_EN = 0x0
5076 11:32:35.797617 WORK_FSP = 0x0
5077 11:32:35.797692 WL = 0x3
5078 11:32:35.800723 RL = 0x3
5079 11:32:35.800798 BL = 0x2
5080 11:32:35.804293 RPST = 0x0
5081 11:32:35.804368 RD_PRE = 0x0
5082 11:32:35.807615 WR_PRE = 0x1
5083 11:32:35.807690 WR_PST = 0x0
5084 11:32:35.811187 DBI_WR = 0x0
5085 11:32:35.811262 DBI_RD = 0x0
5086 11:32:35.813788 OTF = 0x1
5087 11:32:35.817456 ===================================
5088 11:32:35.824048 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 11:32:35.827411 nWR fixed to 30
5090 11:32:35.831015 [ModeRegInit_LP4] CH0 RK0
5091 11:32:35.831090 [ModeRegInit_LP4] CH0 RK1
5092 11:32:35.834266 [ModeRegInit_LP4] CH1 RK0
5093 11:32:35.837096 [ModeRegInit_LP4] CH1 RK1
5094 11:32:35.837172 match AC timing 9
5095 11:32:35.843472 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 11:32:35.846936 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 11:32:35.850382 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 11:32:35.856965 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 11:32:35.860172 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 11:32:35.860248 ==
5101 11:32:35.863274 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 11:32:35.866887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 11:32:35.866963 ==
5104 11:32:35.873424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 11:32:35.879927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5106 11:32:35.883489 [CA 0] Center 37 (7~68) winsize 62
5107 11:32:35.886575 [CA 1] Center 37 (7~68) winsize 62
5108 11:32:35.890039 [CA 2] Center 34 (4~65) winsize 62
5109 11:32:35.893169 [CA 3] Center 34 (4~65) winsize 62
5110 11:32:35.896542 [CA 4] Center 34 (4~64) winsize 61
5111 11:32:35.899897 [CA 5] Center 33 (3~63) winsize 61
5112 11:32:35.899971
5113 11:32:35.903131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5114 11:32:35.903205
5115 11:32:35.906451 [CATrainingPosCal] consider 1 rank data
5116 11:32:35.909854 u2DelayCellTimex100 = 270/100 ps
5117 11:32:35.912826 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 11:32:35.916044 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 11:32:35.919320 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 11:32:35.923041 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5121 11:32:35.929268 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5122 11:32:35.933227 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5123 11:32:35.933301
5124 11:32:35.936411 CA PerBit enable=1, Macro0, CA PI delay=33
5125 11:32:35.936486
5126 11:32:35.939396 [CBTSetCACLKResult] CA Dly = 33
5127 11:32:35.939550 CS Dly: 7 (0~38)
5128 11:32:35.939649 ==
5129 11:32:35.942506 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 11:32:35.949236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 11:32:35.949373 ==
5132 11:32:35.952833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 11:32:35.958802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5134 11:32:35.962441 [CA 0] Center 37 (7~68) winsize 62
5135 11:32:35.966118 [CA 1] Center 37 (7~68) winsize 62
5136 11:32:35.968956 [CA 2] Center 34 (4~65) winsize 62
5137 11:32:35.972241 [CA 3] Center 34 (4~65) winsize 62
5138 11:32:35.975640 [CA 4] Center 33 (3~64) winsize 62
5139 11:32:35.979017 [CA 5] Center 33 (3~63) winsize 61
5140 11:32:35.979092
5141 11:32:35.982152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5142 11:32:35.982251
5143 11:32:35.985702 [CATrainingPosCal] consider 2 rank data
5144 11:32:35.988492 u2DelayCellTimex100 = 270/100 ps
5145 11:32:35.991965 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5146 11:32:35.998556 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5147 11:32:36.001905 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5148 11:32:36.004967 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5149 11:32:36.008374 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5150 11:32:36.011923 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5151 11:32:36.011996
5152 11:32:36.015167 CA PerBit enable=1, Macro0, CA PI delay=33
5153 11:32:36.015260
5154 11:32:36.018518 [CBTSetCACLKResult] CA Dly = 33
5155 11:32:36.021492 CS Dly: 7 (0~39)
5156 11:32:36.021595
5157 11:32:36.025326 ----->DramcWriteLeveling(PI) begin...
5158 11:32:36.025421 ==
5159 11:32:36.028187 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 11:32:36.031687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 11:32:36.031780 ==
5162 11:32:36.034884 Write leveling (Byte 0): 32 => 32
5163 11:32:36.038612 Write leveling (Byte 1): 31 => 31
5164 11:32:36.041451 DramcWriteLeveling(PI) end<-----
5165 11:32:36.041534
5166 11:32:36.041592 ==
5167 11:32:36.045167 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 11:32:36.048169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 11:32:36.048246 ==
5170 11:32:36.051792 [Gating] SW mode calibration
5171 11:32:36.058555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 11:32:36.064647 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 11:32:36.068432 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5174 11:32:36.071882 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 11:32:36.078280 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 11:32:36.081361 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:32:36.084407 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 11:32:36.091262 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 11:32:36.094443 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 11:32:36.097620 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
5181 11:32:36.104385 0 15 0 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
5182 11:32:36.107382 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 11:32:36.110688 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 11:32:36.117445 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:32:36.120763 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 11:32:36.124188 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 11:32:36.130691 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 11:32:36.134037 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5189 11:32:36.137311 1 0 0 | B1->B0 | 3333 4343 | 1 0 | (0 0) (0 0)
5190 11:32:36.143881 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 11:32:36.147314 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:32:36.150535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:32:36.157325 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:32:36.160292 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:32:36.164124 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:32:36.170483 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5197 11:32:36.173767 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5198 11:32:36.177108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:32:36.183695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:32:36.186864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:32:36.189945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:32:36.196626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:32:36.199917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:32:36.203541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:32:36.210005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:32:36.213519 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:32:36.216661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:32:36.223222 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:32:36.226376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:32:36.229681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:32:36.236616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5212 11:32:36.239864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5213 11:32:36.243058 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5214 11:32:36.246520 Total UI for P1: 0, mck2ui 16
5215 11:32:36.249746 best dqsien dly found for B0: ( 1, 2, 26)
5216 11:32:36.256189 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 11:32:36.256265 Total UI for P1: 0, mck2ui 16
5218 11:32:36.262788 best dqsien dly found for B1: ( 1, 3, 0)
5219 11:32:36.266244 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5220 11:32:36.269198 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5221 11:32:36.269272
5222 11:32:36.272625 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5223 11:32:36.276115 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5224 11:32:36.279392 [Gating] SW calibration Done
5225 11:32:36.279503 ==
5226 11:32:36.282546 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 11:32:36.285876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 11:32:36.285951 ==
5229 11:32:36.289004 RX Vref Scan: 0
5230 11:32:36.289079
5231 11:32:36.289136 RX Vref 0 -> 0, step: 1
5232 11:32:36.289189
5233 11:32:36.292470 RX Delay -80 -> 252, step: 8
5234 11:32:36.295484 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5235 11:32:36.302874 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5236 11:32:36.305800 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5237 11:32:36.309082 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5238 11:32:36.312102 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5239 11:32:36.315418 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5240 11:32:36.318885 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5241 11:32:36.325251 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5242 11:32:36.328774 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5243 11:32:36.331775 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5244 11:32:36.335259 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5245 11:32:36.338424 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5246 11:32:36.345276 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5247 11:32:36.348191 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5248 11:32:36.351685 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5249 11:32:36.355045 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5250 11:32:36.355116 ==
5251 11:32:36.358072 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 11:32:36.364621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 11:32:36.364695 ==
5254 11:32:36.364769 DQS Delay:
5255 11:32:36.367951 DQS0 = 0, DQS1 = 0
5256 11:32:36.368018 DQM Delay:
5257 11:32:36.368116 DQM0 = 97, DQM1 = 86
5258 11:32:36.371116 DQ Delay:
5259 11:32:36.374789 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5260 11:32:36.378056 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =111
5261 11:32:36.381510 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5262 11:32:36.385112 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5263 11:32:36.385181
5264 11:32:36.385252
5265 11:32:36.385325 ==
5266 11:32:36.387967 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 11:32:36.391136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 11:32:36.391240 ==
5269 11:32:36.391333
5270 11:32:36.391414
5271 11:32:36.394547 TX Vref Scan disable
5272 11:32:36.397768 == TX Byte 0 ==
5273 11:32:36.401365 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5274 11:32:36.404475 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5275 11:32:36.407825 == TX Byte 1 ==
5276 11:32:36.411431 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5277 11:32:36.414341 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5278 11:32:36.414414 ==
5279 11:32:36.417452 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 11:32:36.420786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 11:32:36.424118 ==
5282 11:32:36.424189
5283 11:32:36.424261
5284 11:32:36.424337 TX Vref Scan disable
5285 11:32:36.427769 == TX Byte 0 ==
5286 11:32:36.431219 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5287 11:32:36.437805 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5288 11:32:36.437878 == TX Byte 1 ==
5289 11:32:36.441095 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5290 11:32:36.447679 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5291 11:32:36.447754
5292 11:32:36.447826 [DATLAT]
5293 11:32:36.447902 Freq=933, CH0 RK0
5294 11:32:36.447971
5295 11:32:36.450908 DATLAT Default: 0xd
5296 11:32:36.454223 0, 0xFFFF, sum = 0
5297 11:32:36.454296 1, 0xFFFF, sum = 0
5298 11:32:36.457336 2, 0xFFFF, sum = 0
5299 11:32:36.457411 3, 0xFFFF, sum = 0
5300 11:32:36.460565 4, 0xFFFF, sum = 0
5301 11:32:36.460634 5, 0xFFFF, sum = 0
5302 11:32:36.464375 6, 0xFFFF, sum = 0
5303 11:32:36.464451 7, 0xFFFF, sum = 0
5304 11:32:36.467384 8, 0xFFFF, sum = 0
5305 11:32:36.467515 9, 0xFFFF, sum = 0
5306 11:32:36.470369 10, 0x0, sum = 1
5307 11:32:36.470471 11, 0x0, sum = 2
5308 11:32:36.474159 12, 0x0, sum = 3
5309 11:32:36.474255 13, 0x0, sum = 4
5310 11:32:36.477204 best_step = 11
5311 11:32:36.477299
5312 11:32:36.477378 ==
5313 11:32:36.480900 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 11:32:36.483765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 11:32:36.483841 ==
5316 11:32:36.483904 RX Vref Scan: 1
5317 11:32:36.483959
5318 11:32:36.487178 RX Vref 0 -> 0, step: 1
5319 11:32:36.487242
5320 11:32:36.490429 RX Delay -61 -> 252, step: 4
5321 11:32:36.490506
5322 11:32:36.493763 Set Vref, RX VrefLevel [Byte0]: 55
5323 11:32:36.497278 [Byte1]: 49
5324 11:32:36.497348
5325 11:32:36.500658 Final RX Vref Byte 0 = 55 to rank0
5326 11:32:36.503546 Final RX Vref Byte 1 = 49 to rank0
5327 11:32:36.507352 Final RX Vref Byte 0 = 55 to rank1
5328 11:32:36.510736 Final RX Vref Byte 1 = 49 to rank1==
5329 11:32:36.513612 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 11:32:36.520052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 11:32:36.520127 ==
5332 11:32:36.520196 DQS Delay:
5333 11:32:36.520251 DQS0 = 0, DQS1 = 0
5334 11:32:36.523638 DQM Delay:
5335 11:32:36.523721 DQM0 = 97, DQM1 = 84
5336 11:32:36.527157 DQ Delay:
5337 11:32:36.530217 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5338 11:32:36.533383 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5339 11:32:36.536792 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =78
5340 11:32:36.539867 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =94
5341 11:32:36.539952
5342 11:32:36.540011
5343 11:32:36.546718 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5344 11:32:36.550199 CH0 RK0: MR19=505, MR18=2C12
5345 11:32:36.556429 CH0_RK0: MR19=0x505, MR18=0x2C12, DQSOSC=408, MR23=63, INC=65, DEC=43
5346 11:32:36.556507
5347 11:32:36.560459 ----->DramcWriteLeveling(PI) begin...
5348 11:32:36.560530 ==
5349 11:32:36.563044 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 11:32:36.566289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 11:32:36.566356 ==
5352 11:32:36.569509 Write leveling (Byte 0): 31 => 31
5353 11:32:36.573211 Write leveling (Byte 1): 32 => 32
5354 11:32:36.576173 DramcWriteLeveling(PI) end<-----
5355 11:32:36.576257
5356 11:32:36.576318 ==
5357 11:32:36.579895 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 11:32:36.582897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 11:32:36.586422 ==
5360 11:32:36.586516 [Gating] SW mode calibration
5361 11:32:36.592714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5362 11:32:36.599478 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5363 11:32:36.603022 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5364 11:32:36.609475 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 11:32:36.612762 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 11:32:36.615970 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:32:36.623147 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 11:32:36.625958 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 11:32:36.629618 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5370 11:32:36.635783 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5371 11:32:36.639041 0 15 0 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
5372 11:32:36.642625 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 11:32:36.648886 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 11:32:36.652341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:32:36.655545 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:32:36.662266 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:32:36.665350 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:32:36.668565 0 15 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
5379 11:32:36.675313 1 0 0 | B1->B0 | 3f3e 4343 | 1 0 | (0 0) (0 0)
5380 11:32:36.678346 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 11:32:36.681758 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 11:32:36.688801 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:32:36.692211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:32:36.695293 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:32:36.701691 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:32:36.705061 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5387 11:32:36.708404 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5388 11:32:36.715316 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:32:36.718322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:32:36.721578 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:32:36.728179 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:32:36.731746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:32:36.734950 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:32:36.741480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:32:36.745275 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:32:36.748000 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:32:36.754760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:32:36.758112 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:32:36.761529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:32:36.767900 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:32:36.771183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:32:36.774432 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5403 11:32:36.781515 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 11:32:36.781592 Total UI for P1: 0, mck2ui 16
5405 11:32:36.787828 best dqsien dly found for B0: ( 1, 2, 28)
5406 11:32:36.790767 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 11:32:36.794354 Total UI for P1: 0, mck2ui 16
5408 11:32:36.797678 best dqsien dly found for B1: ( 1, 3, 0)
5409 11:32:36.800583 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5410 11:32:36.804269 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5411 11:32:36.804338
5412 11:32:36.807550 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5413 11:32:36.810749 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5414 11:32:36.814018 [Gating] SW calibration Done
5415 11:32:36.814086 ==
5416 11:32:36.817386 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 11:32:36.820390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 11:32:36.820470 ==
5419 11:32:36.824266 RX Vref Scan: 0
5420 11:32:36.824335
5421 11:32:36.827118 RX Vref 0 -> 0, step: 1
5422 11:32:36.827194
5423 11:32:36.827285 RX Delay -80 -> 252, step: 8
5424 11:32:36.834116 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5425 11:32:36.837661 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5426 11:32:36.840838 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5427 11:32:36.843906 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5428 11:32:36.847302 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5429 11:32:36.850501 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5430 11:32:36.857320 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5431 11:32:36.860441 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5432 11:32:36.863598 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5433 11:32:36.866812 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5434 11:32:36.870288 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5435 11:32:36.876958 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5436 11:32:36.880085 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5437 11:32:36.883384 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5438 11:32:36.887152 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5439 11:32:36.889919 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5440 11:32:36.889989 ==
5441 11:32:36.893758 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 11:32:36.899732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 11:32:36.899815 ==
5444 11:32:36.899887 DQS Delay:
5445 11:32:36.903184 DQS0 = 0, DQS1 = 0
5446 11:32:36.903253 DQM Delay:
5447 11:32:36.903352 DQM0 = 96, DQM1 = 88
5448 11:32:36.906584 DQ Delay:
5449 11:32:36.910132 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5450 11:32:36.913229 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5451 11:32:36.916383 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5452 11:32:36.919667 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5453 11:32:36.919736
5454 11:32:36.919815
5455 11:32:36.919884 ==
5456 11:32:36.922992 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 11:32:36.926723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 11:32:36.926799 ==
5459 11:32:36.926874
5460 11:32:36.926942
5461 11:32:36.929596 TX Vref Scan disable
5462 11:32:36.933031 == TX Byte 0 ==
5463 11:32:36.936363 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5464 11:32:36.940017 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5465 11:32:36.943082 == TX Byte 1 ==
5466 11:32:36.946585 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5467 11:32:36.949936 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5468 11:32:36.950013 ==
5469 11:32:36.953383 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 11:32:36.955989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:32:36.959375 ==
5472 11:32:36.959488
5473 11:32:36.959547
5474 11:32:36.959602 TX Vref Scan disable
5475 11:32:36.963061 == TX Byte 0 ==
5476 11:32:36.966440 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5477 11:32:36.972885 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5478 11:32:36.972961 == TX Byte 1 ==
5479 11:32:36.976241 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5480 11:32:36.982898 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5481 11:32:36.982974
5482 11:32:36.983033 [DATLAT]
5483 11:32:36.983086 Freq=933, CH0 RK1
5484 11:32:36.983138
5485 11:32:36.986316 DATLAT Default: 0xb
5486 11:32:36.986392 0, 0xFFFF, sum = 0
5487 11:32:36.989469 1, 0xFFFF, sum = 0
5488 11:32:36.992538 2, 0xFFFF, sum = 0
5489 11:32:36.992614 3, 0xFFFF, sum = 0
5490 11:32:36.996032 4, 0xFFFF, sum = 0
5491 11:32:36.996108 5, 0xFFFF, sum = 0
5492 11:32:36.999736 6, 0xFFFF, sum = 0
5493 11:32:36.999813 7, 0xFFFF, sum = 0
5494 11:32:37.002675 8, 0xFFFF, sum = 0
5495 11:32:37.002800 9, 0xFFFF, sum = 0
5496 11:32:37.005697 10, 0x0, sum = 1
5497 11:32:37.005774 11, 0x0, sum = 2
5498 11:32:37.009149 12, 0x0, sum = 3
5499 11:32:37.009225 13, 0x0, sum = 4
5500 11:32:37.012646 best_step = 11
5501 11:32:37.012722
5502 11:32:37.012779 ==
5503 11:32:37.015550 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 11:32:37.019149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 11:32:37.019225 ==
5506 11:32:37.019284 RX Vref Scan: 0
5507 11:32:37.022122
5508 11:32:37.022197 RX Vref 0 -> 0, step: 1
5509 11:32:37.022255
5510 11:32:37.025674 RX Delay -61 -> 252, step: 4
5511 11:32:37.032597 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5512 11:32:37.035958 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5513 11:32:37.038781 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5514 11:32:37.041938 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5515 11:32:37.045626 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5516 11:32:37.048819 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5517 11:32:37.055464 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5518 11:32:37.059049 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5519 11:32:37.061785 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5520 11:32:37.065278 iDelay=199, Bit 9, Center 74 (-17 ~ 166) 184
5521 11:32:37.068834 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5522 11:32:37.075279 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5523 11:32:37.078237 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5524 11:32:37.081994 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5525 11:32:37.085506 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5526 11:32:37.088250 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5527 11:32:37.091612 ==
5528 11:32:37.091691 Dram Type= 6, Freq= 0, CH_0, rank 1
5529 11:32:37.098498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 11:32:37.098601 ==
5531 11:32:37.098685 DQS Delay:
5532 11:32:37.101664 DQS0 = 0, DQS1 = 0
5533 11:32:37.101734 DQM Delay:
5534 11:32:37.104792 DQM0 = 95, DQM1 = 86
5535 11:32:37.104856 DQ Delay:
5536 11:32:37.108010 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =92
5537 11:32:37.111358 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5538 11:32:37.114530 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5539 11:32:37.118327 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5540 11:32:37.118396
5541 11:32:37.118452
5542 11:32:37.124302 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5543 11:32:37.128049 CH0 RK1: MR19=504, MR18=2BFB
5544 11:32:37.134366 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5545 11:32:37.137946 [RxdqsGatingPostProcess] freq 933
5546 11:32:37.144927 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5547 11:32:37.147619 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 11:32:37.150716 best DQS1 dly(2T, 0.5T) = (0, 11)
5549 11:32:37.154046 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 11:32:37.154120 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5551 11:32:37.157728 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 11:32:37.160604 best DQS1 dly(2T, 0.5T) = (0, 11)
5553 11:32:37.164226 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 11:32:37.167314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5555 11:32:37.170566 Pre-setting of DQS Precalculation
5556 11:32:37.177215 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5557 11:32:37.177320 ==
5558 11:32:37.180707 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 11:32:37.183909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 11:32:37.183984 ==
5561 11:32:37.190488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 11:32:37.197228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5563 11:32:37.200209 [CA 0] Center 36 (6~67) winsize 62
5564 11:32:37.204035 [CA 1] Center 37 (6~68) winsize 63
5565 11:32:37.207082 [CA 2] Center 34 (4~65) winsize 62
5566 11:32:37.210506 [CA 3] Center 33 (3~64) winsize 62
5567 11:32:37.213666 [CA 4] Center 34 (4~64) winsize 61
5568 11:32:37.217032 [CA 5] Center 33 (3~64) winsize 62
5569 11:32:37.217104
5570 11:32:37.220074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5571 11:32:37.220166
5572 11:32:37.223250 [CATrainingPosCal] consider 1 rank data
5573 11:32:37.226940 u2DelayCellTimex100 = 270/100 ps
5574 11:32:37.230437 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5575 11:32:37.233482 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5576 11:32:37.236629 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 11:32:37.239780 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 11:32:37.243158 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 11:32:37.246135 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 11:32:37.246221
5581 11:32:37.252815 CA PerBit enable=1, Macro0, CA PI delay=33
5582 11:32:37.252912
5583 11:32:37.256128 [CBTSetCACLKResult] CA Dly = 33
5584 11:32:37.256218 CS Dly: 6 (0~37)
5585 11:32:37.256309 ==
5586 11:32:37.259555 Dram Type= 6, Freq= 0, CH_1, rank 1
5587 11:32:37.262914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 11:32:37.263005 ==
5589 11:32:37.269435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5590 11:32:37.276405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5591 11:32:37.279486 [CA 0] Center 36 (6~67) winsize 62
5592 11:32:37.282638 [CA 1] Center 37 (7~67) winsize 61
5593 11:32:37.285878 [CA 2] Center 34 (4~65) winsize 62
5594 11:32:37.289148 [CA 3] Center 33 (3~64) winsize 62
5595 11:32:37.292617 [CA 4] Center 34 (3~65) winsize 63
5596 11:32:37.295871 [CA 5] Center 33 (3~64) winsize 62
5597 11:32:37.295961
5598 11:32:37.299231 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5599 11:32:37.299326
5600 11:32:37.302278 [CATrainingPosCal] consider 2 rank data
5601 11:32:37.306040 u2DelayCellTimex100 = 270/100 ps
5602 11:32:37.308947 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5603 11:32:37.312498 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5604 11:32:37.315682 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5605 11:32:37.319382 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 11:32:37.325646 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5607 11:32:37.329119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 11:32:37.329212
5609 11:32:37.332316 CA PerBit enable=1, Macro0, CA PI delay=33
5610 11:32:37.332407
5611 11:32:37.335371 [CBTSetCACLKResult] CA Dly = 33
5612 11:32:37.335490 CS Dly: 7 (0~39)
5613 11:32:37.335566
5614 11:32:37.339272 ----->DramcWriteLeveling(PI) begin...
5615 11:32:37.339366 ==
5616 11:32:37.342205 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:32:37.348619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:32:37.348712 ==
5619 11:32:37.351933 Write leveling (Byte 0): 25 => 25
5620 11:32:37.355613 Write leveling (Byte 1): 30 => 30
5621 11:32:37.355682 DramcWriteLeveling(PI) end<-----
5622 11:32:37.358720
5623 11:32:37.358793 ==
5624 11:32:37.361789 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 11:32:37.365227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 11:32:37.365306 ==
5627 11:32:37.368838 [Gating] SW mode calibration
5628 11:32:37.375317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5629 11:32:37.378270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5630 11:32:37.384892 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5631 11:32:37.388384 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 11:32:37.392293 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:32:37.398315 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:32:37.401943 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 11:32:37.405007 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:32:37.411447 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 1)
5637 11:32:37.415091 0 14 28 | B1->B0 | 2f2f 2a2a | 0 0 | (1 1) (1 1)
5638 11:32:37.418300 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 11:32:37.425008 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 11:32:37.427845 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:32:37.431737 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:32:37.437988 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:32:37.441428 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:32:37.444889 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5645 11:32:37.451273 0 15 28 | B1->B0 | 3333 3b3b | 0 0 | (1 1) (0 0)
5646 11:32:37.454686 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5647 11:32:37.457863 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 11:32:37.464414 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:32:37.467655 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:32:37.471107 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:32:37.478319 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:32:37.481403 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5653 11:32:37.484014 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5654 11:32:37.490712 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:32:37.494352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:32:37.497406 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:32:37.504250 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:32:37.507323 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:32:37.510879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:32:37.517270 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:32:37.521059 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:32:37.524161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:32:37.530331 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:32:37.533719 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:32:37.537402 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:32:37.543725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:32:37.546966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:32:37.550788 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5669 11:32:37.557073 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5670 11:32:37.557174 Total UI for P1: 0, mck2ui 16
5671 11:32:37.563885 best dqsien dly found for B0: ( 1, 2, 24)
5672 11:32:37.567335 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 11:32:37.569966 Total UI for P1: 0, mck2ui 16
5674 11:32:37.573464 best dqsien dly found for B1: ( 1, 2, 28)
5675 11:32:37.576889 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5676 11:32:37.579847 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5677 11:32:37.579929
5678 11:32:37.583380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5679 11:32:37.586756 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5680 11:32:37.589971 [Gating] SW calibration Done
5681 11:32:37.590049 ==
5682 11:32:37.593158 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 11:32:37.596417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 11:32:37.599971 ==
5685 11:32:37.600047 RX Vref Scan: 0
5686 11:32:37.600122
5687 11:32:37.603447 RX Vref 0 -> 0, step: 1
5688 11:32:37.603559
5689 11:32:37.606375 RX Delay -80 -> 252, step: 8
5690 11:32:37.609923 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5691 11:32:37.612889 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5692 11:32:37.617074 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5693 11:32:37.619577 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5694 11:32:37.623076 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5695 11:32:37.629559 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5696 11:32:37.633124 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5697 11:32:37.636513 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5698 11:32:37.639316 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5699 11:32:37.642812 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5700 11:32:37.646313 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5701 11:32:37.652638 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5702 11:32:37.656207 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5703 11:32:37.659641 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5704 11:32:37.662622 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5705 11:32:37.665876 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5706 11:32:37.665963 ==
5707 11:32:37.669482 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 11:32:37.675850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 11:32:37.675940 ==
5710 11:32:37.676022 DQS Delay:
5711 11:32:37.679574 DQS0 = 0, DQS1 = 0
5712 11:32:37.679637 DQM Delay:
5713 11:32:37.682694 DQM0 = 100, DQM1 = 90
5714 11:32:37.682755 DQ Delay:
5715 11:32:37.686205 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5716 11:32:37.689036 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5717 11:32:37.692309 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5718 11:32:37.695570 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5719 11:32:37.695632
5720 11:32:37.695685
5721 11:32:37.695735 ==
5722 11:32:37.699240 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 11:32:37.702108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 11:32:37.702183 ==
5725 11:32:37.702241
5726 11:32:37.702294
5727 11:32:37.705806 TX Vref Scan disable
5728 11:32:37.708919 == TX Byte 0 ==
5729 11:32:37.712220 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5730 11:32:37.715956 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5731 11:32:37.718633 == TX Byte 1 ==
5732 11:32:37.722089 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5733 11:32:37.725821 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5734 11:32:37.725897 ==
5735 11:32:37.728975 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 11:32:37.735215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 11:32:37.735314 ==
5738 11:32:37.735399
5739 11:32:37.735505
5740 11:32:37.735557 TX Vref Scan disable
5741 11:32:37.739735 == TX Byte 0 ==
5742 11:32:37.742967 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5743 11:32:37.749208 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5744 11:32:37.749307 == TX Byte 1 ==
5745 11:32:37.752799 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5746 11:32:37.759398 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5747 11:32:37.759519
5748 11:32:37.759578 [DATLAT]
5749 11:32:37.759632 Freq=933, CH1 RK0
5750 11:32:37.759684
5751 11:32:37.762799 DATLAT Default: 0xd
5752 11:32:37.762874 0, 0xFFFF, sum = 0
5753 11:32:37.766110 1, 0xFFFF, sum = 0
5754 11:32:37.769120 2, 0xFFFF, sum = 0
5755 11:32:37.769196 3, 0xFFFF, sum = 0
5756 11:32:37.772528 4, 0xFFFF, sum = 0
5757 11:32:37.772604 5, 0xFFFF, sum = 0
5758 11:32:37.776096 6, 0xFFFF, sum = 0
5759 11:32:37.776172 7, 0xFFFF, sum = 0
5760 11:32:37.779542 8, 0xFFFF, sum = 0
5761 11:32:37.779618 9, 0xFFFF, sum = 0
5762 11:32:37.782391 10, 0x0, sum = 1
5763 11:32:37.782467 11, 0x0, sum = 2
5764 11:32:37.785754 12, 0x0, sum = 3
5765 11:32:37.785830 13, 0x0, sum = 4
5766 11:32:37.785899 best_step = 11
5767 11:32:37.785953
5768 11:32:37.789036 ==
5769 11:32:37.792574 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 11:32:37.795562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 11:32:37.795638 ==
5772 11:32:37.795696 RX Vref Scan: 1
5773 11:32:37.795750
5774 11:32:37.798971 RX Vref 0 -> 0, step: 1
5775 11:32:37.799045
5776 11:32:37.802375 RX Delay -69 -> 252, step: 4
5777 11:32:37.802474
5778 11:32:37.805571 Set Vref, RX VrefLevel [Byte0]: 50
5779 11:32:37.808711 [Byte1]: 51
5780 11:32:37.808786
5781 11:32:37.812433 Final RX Vref Byte 0 = 50 to rank0
5782 11:32:37.815400 Final RX Vref Byte 1 = 51 to rank0
5783 11:32:37.818747 Final RX Vref Byte 0 = 50 to rank1
5784 11:32:37.822481 Final RX Vref Byte 1 = 51 to rank1==
5785 11:32:37.825676 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 11:32:37.828758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 11:32:37.832080 ==
5788 11:32:37.832154 DQS Delay:
5789 11:32:37.832212 DQS0 = 0, DQS1 = 0
5790 11:32:37.835430 DQM Delay:
5791 11:32:37.835538 DQM0 = 100, DQM1 = 93
5792 11:32:37.838499 DQ Delay:
5793 11:32:37.842365 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5794 11:32:37.845508 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5795 11:32:37.848485 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
5796 11:32:37.852169 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =104
5797 11:32:37.852238
5798 11:32:37.852323
5799 11:32:37.858360 [DQSOSCAuto] RK0, (LSB)MR18= 0x1908, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5800 11:32:37.861788 CH1 RK0: MR19=505, MR18=1908
5801 11:32:37.868713 CH1_RK0: MR19=0x505, MR18=0x1908, DQSOSC=413, MR23=63, INC=63, DEC=42
5802 11:32:37.868789
5803 11:32:37.871699 ----->DramcWriteLeveling(PI) begin...
5804 11:32:37.871776 ==
5805 11:32:37.875109 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 11:32:37.878696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 11:32:37.878771 ==
5808 11:32:37.881760 Write leveling (Byte 0): 28 => 28
5809 11:32:37.884739 Write leveling (Byte 1): 28 => 28
5810 11:32:37.888424 DramcWriteLeveling(PI) end<-----
5811 11:32:37.888499
5812 11:32:37.888557 ==
5813 11:32:37.891715 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 11:32:37.894771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 11:32:37.898377 ==
5816 11:32:37.898451 [Gating] SW mode calibration
5817 11:32:37.908374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5818 11:32:37.911259 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5819 11:32:37.914815 0 14 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5820 11:32:37.921369 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 11:32:37.924817 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:32:37.927950 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:32:37.934466 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:32:37.938026 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:32:37.941438 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5826 11:32:37.948138 0 14 28 | B1->B0 | 2a2a 2f2f | 0 0 | (1 0) (0 1)
5827 11:32:37.950944 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5828 11:32:37.954574 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 11:32:37.961528 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:32:37.963979 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:32:37.967582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:32:37.973963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:32:37.977072 0 15 24 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
5834 11:32:37.980922 0 15 28 | B1->B0 | 3c3b 3131 | 1 0 | (0 0) (1 1)
5835 11:32:37.986904 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 11:32:37.990328 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:32:37.994405 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:32:38.000217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:32:38.003747 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:32:38.006801 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:32:38.013354 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5842 11:32:38.017450 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5843 11:32:38.020117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:32:38.026765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:32:38.030095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:32:38.033642 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:32:38.039703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:32:38.043343 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:32:38.046651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:32:38.053271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:32:38.056553 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:32:38.059483 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:32:38.066194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:32:38.069930 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:32:38.073004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:32:38.079589 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:32:38.083068 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5858 11:32:38.086211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 11:32:38.089420 Total UI for P1: 0, mck2ui 16
5860 11:32:38.093055 best dqsien dly found for B0: ( 1, 2, 26)
5861 11:32:38.095979 Total UI for P1: 0, mck2ui 16
5862 11:32:38.099200 best dqsien dly found for B1: ( 1, 2, 24)
5863 11:32:38.102579 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5864 11:32:38.109224 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5865 11:32:38.109299
5866 11:32:38.112673 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5867 11:32:38.116567 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5868 11:32:38.118803 [Gating] SW calibration Done
5869 11:32:38.118877 ==
5870 11:32:38.122323 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 11:32:38.125890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 11:32:38.125994 ==
5873 11:32:38.126079 RX Vref Scan: 0
5874 11:32:38.129097
5875 11:32:38.129163 RX Vref 0 -> 0, step: 1
5876 11:32:38.129218
5877 11:32:38.132232 RX Delay -80 -> 252, step: 8
5878 11:32:38.135585 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5879 11:32:38.138601 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5880 11:32:38.145538 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5881 11:32:38.148459 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5882 11:32:38.151933 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5883 11:32:38.155339 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5884 11:32:38.158631 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5885 11:32:38.161877 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5886 11:32:38.168757 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5887 11:32:38.172088 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5888 11:32:38.175447 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5889 11:32:38.178391 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5890 11:32:38.181357 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5891 11:32:38.188513 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5892 11:32:38.191733 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5893 11:32:38.194770 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5894 11:32:38.194859 ==
5895 11:32:38.198028 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 11:32:38.201368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 11:32:38.201462 ==
5898 11:32:38.204630 DQS Delay:
5899 11:32:38.204696 DQS0 = 0, DQS1 = 0
5900 11:32:38.208132 DQM Delay:
5901 11:32:38.208191 DQM0 = 100, DQM1 = 90
5902 11:32:38.208244 DQ Delay:
5903 11:32:38.211143 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5904 11:32:38.214896 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =95
5905 11:32:38.218258 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =79
5906 11:32:38.221513 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5907 11:32:38.221587
5908 11:32:38.224457
5909 11:32:38.224530 ==
5910 11:32:38.227907 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:32:38.231304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:32:38.231380 ==
5913 11:32:38.231459
5914 11:32:38.231526
5915 11:32:38.234446 TX Vref Scan disable
5916 11:32:38.234520 == TX Byte 0 ==
5917 11:32:38.241120 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5918 11:32:38.244260 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5919 11:32:38.244335 == TX Byte 1 ==
5920 11:32:38.251066 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5921 11:32:38.254144 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5922 11:32:38.254219 ==
5923 11:32:38.257335 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:32:38.260736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:32:38.260815 ==
5926 11:32:38.260875
5927 11:32:38.260929
5928 11:32:38.264265 TX Vref Scan disable
5929 11:32:38.267354 == TX Byte 0 ==
5930 11:32:38.270875 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5931 11:32:38.273733 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5932 11:32:38.277239 == TX Byte 1 ==
5933 11:32:38.281045 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5934 11:32:38.284004 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5935 11:32:38.287315
5936 11:32:38.287415 [DATLAT]
5937 11:32:38.287501 Freq=933, CH1 RK1
5938 11:32:38.287556
5939 11:32:38.290325 DATLAT Default: 0xb
5940 11:32:38.290388 0, 0xFFFF, sum = 0
5941 11:32:38.293933 1, 0xFFFF, sum = 0
5942 11:32:38.294009 2, 0xFFFF, sum = 0
5943 11:32:38.296867 3, 0xFFFF, sum = 0
5944 11:32:38.299964 4, 0xFFFF, sum = 0
5945 11:32:38.300039 5, 0xFFFF, sum = 0
5946 11:32:38.303591 6, 0xFFFF, sum = 0
5947 11:32:38.303666 7, 0xFFFF, sum = 0
5948 11:32:38.306904 8, 0xFFFF, sum = 0
5949 11:32:38.306979 9, 0xFFFF, sum = 0
5950 11:32:38.309995 10, 0x0, sum = 1
5951 11:32:38.310070 11, 0x0, sum = 2
5952 11:32:38.313160 12, 0x0, sum = 3
5953 11:32:38.313236 13, 0x0, sum = 4
5954 11:32:38.313295 best_step = 11
5955 11:32:38.313347
5956 11:32:38.316894 ==
5957 11:32:38.319904 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 11:32:38.323123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 11:32:38.323200 ==
5960 11:32:38.323349 RX Vref Scan: 0
5961 11:32:38.323438
5962 11:32:38.326640 RX Vref 0 -> 0, step: 1
5963 11:32:38.326714
5964 11:32:38.329527 RX Delay -61 -> 252, step: 4
5965 11:32:38.336357 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5966 11:32:38.339711 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5967 11:32:38.343303 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5968 11:32:38.347463 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5969 11:32:38.350022 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5970 11:32:38.353156 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5971 11:32:38.359776 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5972 11:32:38.362816 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5973 11:32:38.365983 iDelay=207, Bit 8, Center 78 (-13 ~ 170) 184
5974 11:32:38.369284 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5975 11:32:38.373014 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
5976 11:32:38.375873 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5977 11:32:38.383086 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5978 11:32:38.386502 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5979 11:32:38.389430 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5980 11:32:38.392504 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5981 11:32:38.392579 ==
5982 11:32:38.395750 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 11:32:38.402591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 11:32:38.402667 ==
5985 11:32:38.402723 DQS Delay:
5986 11:32:38.406199 DQS0 = 0, DQS1 = 0
5987 11:32:38.406273 DQM Delay:
5988 11:32:38.409608 DQM0 = 100, DQM1 = 92
5989 11:32:38.409683 DQ Delay:
5990 11:32:38.412272 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5991 11:32:38.415558 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =96
5992 11:32:38.419199 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5993 11:32:38.422474 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5994 11:32:38.422548
5995 11:32:38.422605
5996 11:32:38.429038 [DQSOSCAuto] RK1, (LSB)MR18= 0xc05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5997 11:32:38.432484 CH1 RK1: MR19=505, MR18=C05
5998 11:32:38.438602 CH1_RK1: MR19=0x505, MR18=0xC05, DQSOSC=418, MR23=63, INC=62, DEC=41
5999 11:32:38.442134 [RxdqsGatingPostProcess] freq 933
6000 11:32:38.448874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6001 11:32:38.451755 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 11:32:38.455348 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 11:32:38.458616 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 11:32:38.458692 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 11:32:38.461804 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 11:32:38.465868 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 11:32:38.468413 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 11:32:38.472507 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 11:32:38.475222 Pre-setting of DQS Precalculation
6010 11:32:38.481761 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6011 11:32:38.488369 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6012 11:32:38.495120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6013 11:32:38.495197
6014 11:32:38.495256
6015 11:32:38.498035 [Calibration Summary] 1866 Mbps
6016 11:32:38.498110 CH 0, Rank 0
6017 11:32:38.501298 SW Impedance : PASS
6018 11:32:38.504530 DUTY Scan : NO K
6019 11:32:38.504605 ZQ Calibration : PASS
6020 11:32:38.508230 Jitter Meter : NO K
6021 11:32:38.511034 CBT Training : PASS
6022 11:32:38.511110 Write leveling : PASS
6023 11:32:38.514735 RX DQS gating : PASS
6024 11:32:38.518125 RX DQ/DQS(RDDQC) : PASS
6025 11:32:38.518200 TX DQ/DQS : PASS
6026 11:32:38.521406 RX DATLAT : PASS
6027 11:32:38.524504 RX DQ/DQS(Engine): PASS
6028 11:32:38.524579 TX OE : NO K
6029 11:32:38.527690 All Pass.
6030 11:32:38.527765
6031 11:32:38.527823 CH 0, Rank 1
6032 11:32:38.530825 SW Impedance : PASS
6033 11:32:38.530900 DUTY Scan : NO K
6034 11:32:38.534821 ZQ Calibration : PASS
6035 11:32:38.537562 Jitter Meter : NO K
6036 11:32:38.537661 CBT Training : PASS
6037 11:32:38.540893 Write leveling : PASS
6038 11:32:38.544146 RX DQS gating : PASS
6039 11:32:38.544212 RX DQ/DQS(RDDQC) : PASS
6040 11:32:38.547660 TX DQ/DQS : PASS
6041 11:32:38.551113 RX DATLAT : PASS
6042 11:32:38.551202 RX DQ/DQS(Engine): PASS
6043 11:32:38.554139 TX OE : NO K
6044 11:32:38.554231 All Pass.
6045 11:32:38.554321
6046 11:32:38.557432 CH 1, Rank 0
6047 11:32:38.557504 SW Impedance : PASS
6048 11:32:38.560955 DUTY Scan : NO K
6049 11:32:38.561023 ZQ Calibration : PASS
6050 11:32:38.564312 Jitter Meter : NO K
6051 11:32:38.567352 CBT Training : PASS
6052 11:32:38.567466 Write leveling : PASS
6053 11:32:38.570960 RX DQS gating : PASS
6054 11:32:38.574146 RX DQ/DQS(RDDQC) : PASS
6055 11:32:38.574207 TX DQ/DQS : PASS
6056 11:32:38.577550 RX DATLAT : PASS
6057 11:32:38.580497 RX DQ/DQS(Engine): PASS
6058 11:32:38.580572 TX OE : NO K
6059 11:32:38.584091 All Pass.
6060 11:32:38.584165
6061 11:32:38.584224 CH 1, Rank 1
6062 11:32:38.587312 SW Impedance : PASS
6063 11:32:38.587388 DUTY Scan : NO K
6064 11:32:38.590683 ZQ Calibration : PASS
6065 11:32:38.593857 Jitter Meter : NO K
6066 11:32:38.593932 CBT Training : PASS
6067 11:32:38.597077 Write leveling : PASS
6068 11:32:38.600570 RX DQS gating : PASS
6069 11:32:38.600646 RX DQ/DQS(RDDQC) : PASS
6070 11:32:38.603861 TX DQ/DQS : PASS
6071 11:32:38.606796 RX DATLAT : PASS
6072 11:32:38.606889 RX DQ/DQS(Engine): PASS
6073 11:32:38.610764 TX OE : NO K
6074 11:32:38.610841 All Pass.
6075 11:32:38.610898
6076 11:32:38.613948 DramC Write-DBI off
6077 11:32:38.616941 PER_BANK_REFRESH: Hybrid Mode
6078 11:32:38.617006 TX_TRACKING: ON
6079 11:32:38.627288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6080 11:32:38.630022 [FAST_K] Save calibration result to emmc
6081 11:32:38.633357 dramc_set_vcore_voltage set vcore to 650000
6082 11:32:38.636717 Read voltage for 400, 6
6083 11:32:38.636790 Vio18 = 0
6084 11:32:38.636850 Vcore = 650000
6085 11:32:38.639707 Vdram = 0
6086 11:32:38.639785 Vddq = 0
6087 11:32:38.639843 Vmddr = 0
6088 11:32:38.646505 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6089 11:32:38.650128 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6090 11:32:38.653350 MEM_TYPE=3, freq_sel=20
6091 11:32:38.656854 sv_algorithm_assistance_LP4_800
6092 11:32:38.659644 ============ PULL DRAM RESETB DOWN ============
6093 11:32:38.663300 ========== PULL DRAM RESETB DOWN end =========
6094 11:32:38.669650 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6095 11:32:38.672754 ===================================
6096 11:32:38.676383 LPDDR4 DRAM CONFIGURATION
6097 11:32:38.679689 ===================================
6098 11:32:38.679766 EX_ROW_EN[0] = 0x0
6099 11:32:38.683037 EX_ROW_EN[1] = 0x0
6100 11:32:38.683140 LP4Y_EN = 0x0
6101 11:32:38.685934 WORK_FSP = 0x0
6102 11:32:38.686030 WL = 0x2
6103 11:32:38.689265 RL = 0x2
6104 11:32:38.689357 BL = 0x2
6105 11:32:38.692608 RPST = 0x0
6106 11:32:38.692677 RD_PRE = 0x0
6107 11:32:38.696406 WR_PRE = 0x1
6108 11:32:38.696470 WR_PST = 0x0
6109 11:32:38.699165 DBI_WR = 0x0
6110 11:32:38.699255 DBI_RD = 0x0
6111 11:32:38.702528 OTF = 0x1
6112 11:32:38.706276 ===================================
6113 11:32:38.709289 ===================================
6114 11:32:38.709361 ANA top config
6115 11:32:38.712478 ===================================
6116 11:32:38.715870 DLL_ASYNC_EN = 0
6117 11:32:38.719600 ALL_SLAVE_EN = 1
6118 11:32:38.722501 NEW_RANK_MODE = 1
6119 11:32:38.722577 DLL_IDLE_MODE = 1
6120 11:32:38.725898 LP45_APHY_COMB_EN = 1
6121 11:32:38.729189 TX_ODT_DIS = 1
6122 11:32:38.732510 NEW_8X_MODE = 1
6123 11:32:38.735772 ===================================
6124 11:32:38.738936 ===================================
6125 11:32:38.742727 data_rate = 800
6126 11:32:38.745836 CKR = 1
6127 11:32:38.745912 DQ_P2S_RATIO = 4
6128 11:32:38.749030 ===================================
6129 11:32:38.752800 CA_P2S_RATIO = 4
6130 11:32:38.755460 DQ_CA_OPEN = 0
6131 11:32:38.758768 DQ_SEMI_OPEN = 1
6132 11:32:38.762293 CA_SEMI_OPEN = 1
6133 11:32:38.765337 CA_FULL_RATE = 0
6134 11:32:38.765414 DQ_CKDIV4_EN = 0
6135 11:32:38.768814 CA_CKDIV4_EN = 1
6136 11:32:38.772648 CA_PREDIV_EN = 0
6137 11:32:38.775625 PH8_DLY = 0
6138 11:32:38.778836 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6139 11:32:38.781970 DQ_AAMCK_DIV = 0
6140 11:32:38.782045 CA_AAMCK_DIV = 0
6141 11:32:38.785048 CA_ADMCK_DIV = 4
6142 11:32:38.788761 DQ_TRACK_CA_EN = 0
6143 11:32:38.791735 CA_PICK = 800
6144 11:32:38.795133 CA_MCKIO = 400
6145 11:32:38.798620 MCKIO_SEMI = 400
6146 11:32:38.801859 PLL_FREQ = 3016
6147 11:32:38.804887 DQ_UI_PI_RATIO = 32
6148 11:32:38.804962 CA_UI_PI_RATIO = 32
6149 11:32:38.808549 ===================================
6150 11:32:38.811758 ===================================
6151 11:32:38.815120 memory_type:LPDDR4
6152 11:32:38.818182 GP_NUM : 10
6153 11:32:38.818256 SRAM_EN : 1
6154 11:32:38.821426 MD32_EN : 0
6155 11:32:38.824739 ===================================
6156 11:32:38.828249 [ANA_INIT] >>>>>>>>>>>>>>
6157 11:32:38.831787 <<<<<< [CONFIGURE PHASE]: ANA_TX
6158 11:32:38.834593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6159 11:32:38.839007 ===================================
6160 11:32:38.839082 data_rate = 800,PCW = 0X7400
6161 11:32:38.841202 ===================================
6162 11:32:38.844736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6163 11:32:38.851663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 11:32:38.864193 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6165 11:32:38.867474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6166 11:32:38.870508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6167 11:32:38.874380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6168 11:32:38.877176 [ANA_INIT] flow start
6169 11:32:38.877250 [ANA_INIT] PLL >>>>>>>>
6170 11:32:38.881351 [ANA_INIT] PLL <<<<<<<<
6171 11:32:38.884471 [ANA_INIT] MIDPI >>>>>>>>
6172 11:32:38.887138 [ANA_INIT] MIDPI <<<<<<<<
6173 11:32:38.887212 [ANA_INIT] DLL >>>>>>>>
6174 11:32:38.890416 [ANA_INIT] flow end
6175 11:32:38.894108 ============ LP4 DIFF to SE enter ============
6176 11:32:38.897150 ============ LP4 DIFF to SE exit ============
6177 11:32:38.900451 [ANA_INIT] <<<<<<<<<<<<<
6178 11:32:38.903692 [Flow] Enable top DCM control >>>>>
6179 11:32:38.907211 [Flow] Enable top DCM control <<<<<
6180 11:32:38.910430 Enable DLL master slave shuffle
6181 11:32:38.916779 ==============================================================
6182 11:32:38.916854 Gating Mode config
6183 11:32:38.923557 ==============================================================
6184 11:32:38.923633 Config description:
6185 11:32:38.933384 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6186 11:32:38.940119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6187 11:32:38.946623 SELPH_MODE 0: By rank 1: By Phase
6188 11:32:38.952967 ==============================================================
6189 11:32:38.953043 GAT_TRACK_EN = 0
6190 11:32:38.956783 RX_GATING_MODE = 2
6191 11:32:38.959551 RX_GATING_TRACK_MODE = 2
6192 11:32:38.962908 SELPH_MODE = 1
6193 11:32:38.966229 PICG_EARLY_EN = 1
6194 11:32:38.969515 VALID_LAT_VALUE = 1
6195 11:32:38.976116 ==============================================================
6196 11:32:38.979532 Enter into Gating configuration >>>>
6197 11:32:38.982894 Exit from Gating configuration <<<<
6198 11:32:38.986019 Enter into DVFS_PRE_config >>>>>
6199 11:32:38.996224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6200 11:32:38.999139 Exit from DVFS_PRE_config <<<<<
6201 11:32:39.002697 Enter into PICG configuration >>>>
6202 11:32:39.005745 Exit from PICG configuration <<<<
6203 11:32:39.009350 [RX_INPUT] configuration >>>>>
6204 11:32:39.012239 [RX_INPUT] configuration <<<<<
6205 11:32:39.015365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6206 11:32:39.022433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6207 11:32:39.029098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6208 11:32:39.032375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6209 11:32:39.038753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 11:32:39.045592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 11:32:39.048923 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6212 11:32:39.055074 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6213 11:32:39.058665 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6214 11:32:39.061619 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6215 11:32:39.065098 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6216 11:32:39.072176 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 11:32:39.074970 ===================================
6218 11:32:39.075073 LPDDR4 DRAM CONFIGURATION
6219 11:32:39.078494 ===================================
6220 11:32:39.081933 EX_ROW_EN[0] = 0x0
6221 11:32:39.085295 EX_ROW_EN[1] = 0x0
6222 11:32:39.085371 LP4Y_EN = 0x0
6223 11:32:39.088360 WORK_FSP = 0x0
6224 11:32:39.088435 WL = 0x2
6225 11:32:39.091952 RL = 0x2
6226 11:32:39.092030 BL = 0x2
6227 11:32:39.094724 RPST = 0x0
6228 11:32:39.094799 RD_PRE = 0x0
6229 11:32:39.098097 WR_PRE = 0x1
6230 11:32:39.098196 WR_PST = 0x0
6231 11:32:39.101851 DBI_WR = 0x0
6232 11:32:39.101926 DBI_RD = 0x0
6233 11:32:39.104829 OTF = 0x1
6234 11:32:39.108084 ===================================
6235 11:32:39.111824 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6236 11:32:39.114687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6237 11:32:39.121642 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 11:32:39.124525 ===================================
6239 11:32:39.124601 LPDDR4 DRAM CONFIGURATION
6240 11:32:39.128004 ===================================
6241 11:32:39.131251 EX_ROW_EN[0] = 0x10
6242 11:32:39.134414 EX_ROW_EN[1] = 0x0
6243 11:32:39.134490 LP4Y_EN = 0x0
6244 11:32:39.137692 WORK_FSP = 0x0
6245 11:32:39.137768 WL = 0x2
6246 11:32:39.141132 RL = 0x2
6247 11:32:39.141208 BL = 0x2
6248 11:32:39.144350 RPST = 0x0
6249 11:32:39.144426 RD_PRE = 0x0
6250 11:32:39.147740 WR_PRE = 0x1
6251 11:32:39.147816 WR_PST = 0x0
6252 11:32:39.151410 DBI_WR = 0x0
6253 11:32:39.151528 DBI_RD = 0x0
6254 11:32:39.154519 OTF = 0x1
6255 11:32:39.157538 ===================================
6256 11:32:39.164520 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6257 11:32:39.167455 nWR fixed to 30
6258 11:32:39.170753 [ModeRegInit_LP4] CH0 RK0
6259 11:32:39.170829 [ModeRegInit_LP4] CH0 RK1
6260 11:32:39.174407 [ModeRegInit_LP4] CH1 RK0
6261 11:32:39.177566 [ModeRegInit_LP4] CH1 RK1
6262 11:32:39.177641 match AC timing 19
6263 11:32:39.183934 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6264 11:32:39.187978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6265 11:32:39.190597 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6266 11:32:39.197777 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6267 11:32:39.200609 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6268 11:32:39.200685 ==
6269 11:32:39.204060 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 11:32:39.207843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 11:32:39.207918 ==
6272 11:32:39.214074 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 11:32:39.220390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6274 11:32:39.223562 [CA 0] Center 36 (8~64) winsize 57
6275 11:32:39.227295 [CA 1] Center 36 (8~64) winsize 57
6276 11:32:39.229993 [CA 2] Center 36 (8~64) winsize 57
6277 11:32:39.233914 [CA 3] Center 36 (8~64) winsize 57
6278 11:32:39.236550 [CA 4] Center 36 (8~64) winsize 57
6279 11:32:39.240243 [CA 5] Center 36 (8~64) winsize 57
6280 11:32:39.240326
6281 11:32:39.243536 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6282 11:32:39.243604
6283 11:32:39.246437 [CATrainingPosCal] consider 1 rank data
6284 11:32:39.250092 u2DelayCellTimex100 = 270/100 ps
6285 11:32:39.253285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 11:32:39.256442 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 11:32:39.259729 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:32:39.263040 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:32:39.266346 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:32:39.269914 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:32:39.270003
6292 11:32:39.273059 CA PerBit enable=1, Macro0, CA PI delay=36
6293 11:32:39.276171
6294 11:32:39.276260 [CBTSetCACLKResult] CA Dly = 36
6295 11:32:39.279415 CS Dly: 1 (0~32)
6296 11:32:39.279492 ==
6297 11:32:39.283095 Dram Type= 6, Freq= 0, CH_0, rank 1
6298 11:32:39.286340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 11:32:39.286436 ==
6300 11:32:39.292946 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 11:32:39.299319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6302 11:32:39.303129 [CA 0] Center 36 (8~64) winsize 57
6303 11:32:39.306078 [CA 1] Center 36 (8~64) winsize 57
6304 11:32:39.309706 [CA 2] Center 36 (8~64) winsize 57
6305 11:32:39.309795 [CA 3] Center 36 (8~64) winsize 57
6306 11:32:39.312801 [CA 4] Center 36 (8~64) winsize 57
6307 11:32:39.316128 [CA 5] Center 36 (8~64) winsize 57
6308 11:32:39.316218
6309 11:32:39.322429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6310 11:32:39.322522
6311 11:32:39.325739 [CATrainingPosCal] consider 2 rank data
6312 11:32:39.329119 u2DelayCellTimex100 = 270/100 ps
6313 11:32:39.332278 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 11:32:39.335702 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 11:32:39.339166 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:32:39.342564 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:32:39.345866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:32:39.348950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:32:39.349077
6320 11:32:39.352160 CA PerBit enable=1, Macro0, CA PI delay=36
6321 11:32:39.352251
6322 11:32:39.355349 [CBTSetCACLKResult] CA Dly = 36
6323 11:32:39.358804 CS Dly: 1 (0~32)
6324 11:32:39.358946
6325 11:32:39.362319 ----->DramcWriteLeveling(PI) begin...
6326 11:32:39.362408 ==
6327 11:32:39.365291 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 11:32:39.368598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 11:32:39.368697 ==
6330 11:32:39.372015 Write leveling (Byte 0): 40 => 8
6331 11:32:39.375400 Write leveling (Byte 1): 32 => 0
6332 11:32:39.380806 DramcWriteLeveling(PI) end<-----
6333 11:32:39.380918
6334 11:32:39.381003 ==
6335 11:32:39.381638 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 11:32:39.385458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 11:32:39.385539 ==
6338 11:32:39.388288 [Gating] SW mode calibration
6339 11:32:39.395011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6340 11:32:39.401546 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6341 11:32:39.404852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 11:32:39.411311 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6343 11:32:39.414649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 11:32:39.418089 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 11:32:39.424953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 11:32:39.427967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 11:32:39.431341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 11:32:39.437834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:32:39.441007 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 11:32:39.444083 Total UI for P1: 0, mck2ui 16
6351 11:32:39.447766 best dqsien dly found for B0: ( 0, 14, 24)
6352 11:32:39.450883 Total UI for P1: 0, mck2ui 16
6353 11:32:39.454136 best dqsien dly found for B1: ( 0, 14, 24)
6354 11:32:39.457164 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6355 11:32:39.460598 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6356 11:32:39.460674
6357 11:32:39.463827 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 11:32:39.467135 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6359 11:32:39.470561 [Gating] SW calibration Done
6360 11:32:39.470650 ==
6361 11:32:39.473922 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 11:32:39.480256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 11:32:39.480349 ==
6364 11:32:39.480432 RX Vref Scan: 0
6365 11:32:39.480511
6366 11:32:39.483803 RX Vref 0 -> 0, step: 1
6367 11:32:39.483893
6368 11:32:39.486834 RX Delay -410 -> 252, step: 16
6369 11:32:39.490406 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6370 11:32:39.493158 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6371 11:32:39.499977 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6372 11:32:39.503401 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6373 11:32:39.506441 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6374 11:32:39.510397 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6375 11:32:39.516627 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6376 11:32:39.519725 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6377 11:32:39.523220 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6378 11:32:39.526738 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6379 11:32:39.533394 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6380 11:32:39.536356 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6381 11:32:39.539468 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6382 11:32:39.543332 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6383 11:32:39.549392 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6384 11:32:39.552972 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6385 11:32:39.553038 ==
6386 11:32:39.556159 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:32:39.559339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:32:39.559436 ==
6389 11:32:39.562513 DQS Delay:
6390 11:32:39.562601 DQS0 = 43, DQS1 = 59
6391 11:32:39.566268 DQM Delay:
6392 11:32:39.566356 DQM0 = 10, DQM1 = 11
6393 11:32:39.569247 DQ Delay:
6394 11:32:39.569333 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6395 11:32:39.572431 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6396 11:32:39.575983 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6397 11:32:39.579233 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6398 11:32:39.579318
6399 11:32:39.579399
6400 11:32:39.579506 ==
6401 11:32:39.582852 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:32:39.589272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:32:39.589357 ==
6404 11:32:39.589440
6405 11:32:39.589518
6406 11:32:39.589594 TX Vref Scan disable
6407 11:32:39.592441 == TX Byte 0 ==
6408 11:32:39.595901 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 11:32:39.599079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 11:32:39.602124 == TX Byte 1 ==
6411 11:32:39.605442 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6412 11:32:39.612042 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6413 11:32:39.612108 ==
6414 11:32:39.615216 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 11:32:39.618735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 11:32:39.618819 ==
6417 11:32:39.618900
6418 11:32:39.618979
6419 11:32:39.622023 TX Vref Scan disable
6420 11:32:39.622084 == TX Byte 0 ==
6421 11:32:39.625429 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 11:32:39.632158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 11:32:39.632230 == TX Byte 1 ==
6424 11:32:39.635282 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6425 11:32:39.641476 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6426 11:32:39.641566
6427 11:32:39.641647 [DATLAT]
6428 11:32:39.645319 Freq=400, CH0 RK0
6429 11:32:39.645407
6430 11:32:39.645488 DATLAT Default: 0xf
6431 11:32:39.648216 0, 0xFFFF, sum = 0
6432 11:32:39.648279 1, 0xFFFF, sum = 0
6433 11:32:39.651882 2, 0xFFFF, sum = 0
6434 11:32:39.651946 3, 0xFFFF, sum = 0
6435 11:32:39.655339 4, 0xFFFF, sum = 0
6436 11:32:39.655456 5, 0xFFFF, sum = 0
6437 11:32:39.658127 6, 0xFFFF, sum = 0
6438 11:32:39.658215 7, 0xFFFF, sum = 0
6439 11:32:39.661653 8, 0xFFFF, sum = 0
6440 11:32:39.661716 9, 0xFFFF, sum = 0
6441 11:32:39.664481 10, 0xFFFF, sum = 0
6442 11:32:39.668381 11, 0xFFFF, sum = 0
6443 11:32:39.668475 12, 0xFFFF, sum = 0
6444 11:32:39.671303 13, 0x0, sum = 1
6445 11:32:39.671390 14, 0x0, sum = 2
6446 11:32:39.671520 15, 0x0, sum = 3
6447 11:32:39.674705 16, 0x0, sum = 4
6448 11:32:39.674790 best_step = 14
6449 11:32:39.674867
6450 11:32:39.677790 ==
6451 11:32:39.677874 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 11:32:39.684475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:32:39.684574 ==
6454 11:32:39.684660 RX Vref Scan: 1
6455 11:32:39.684741
6456 11:32:39.687814 RX Vref 0 -> 0, step: 1
6457 11:32:39.687874
6458 11:32:39.690971 RX Delay -359 -> 252, step: 8
6459 11:32:39.691056
6460 11:32:39.694608 Set Vref, RX VrefLevel [Byte0]: 55
6461 11:32:39.698234 [Byte1]: 49
6462 11:32:39.701626
6463 11:32:39.701712 Final RX Vref Byte 0 = 55 to rank0
6464 11:32:39.704801 Final RX Vref Byte 1 = 49 to rank0
6465 11:32:39.708113 Final RX Vref Byte 0 = 55 to rank1
6466 11:32:39.711669 Final RX Vref Byte 1 = 49 to rank1==
6467 11:32:39.714562 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 11:32:39.721521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 11:32:39.721612 ==
6470 11:32:39.721695 DQS Delay:
6471 11:32:39.724913 DQS0 = 48, DQS1 = 60
6472 11:32:39.724998 DQM Delay:
6473 11:32:39.725075 DQM0 = 11, DQM1 = 11
6474 11:32:39.727875 DQ Delay:
6475 11:32:39.731372 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6476 11:32:39.731499 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6477 11:32:39.734350 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6478 11:32:39.737969 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6479 11:32:39.741235
6480 11:32:39.741320
6481 11:32:39.747671 [DQSOSCAuto] RK0, (LSB)MR18= 0xc588, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6482 11:32:39.750912 CH0 RK0: MR19=C0C, MR18=C588
6483 11:32:39.757266 CH0_RK0: MR19=0xC0C, MR18=0xC588, DQSOSC=385, MR23=63, INC=398, DEC=265
6484 11:32:39.757359 ==
6485 11:32:39.760633 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 11:32:39.764319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 11:32:39.764408 ==
6488 11:32:39.767609 [Gating] SW mode calibration
6489 11:32:39.773969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6490 11:32:39.780474 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6491 11:32:39.783964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 11:32:39.787377 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6493 11:32:39.794131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 11:32:39.797091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 11:32:39.800300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 11:32:39.807016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 11:32:39.810486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 11:32:39.813397 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:32:39.820499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 11:32:39.820590 Total UI for P1: 0, mck2ui 16
6501 11:32:39.826904 best dqsien dly found for B0: ( 0, 14, 24)
6502 11:32:39.826995 Total UI for P1: 0, mck2ui 16
6503 11:32:39.833611 best dqsien dly found for B1: ( 0, 14, 24)
6504 11:32:39.836970 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6505 11:32:39.839882 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6506 11:32:39.839971
6507 11:32:39.843438 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 11:32:39.846750 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6509 11:32:39.849930 [Gating] SW calibration Done
6510 11:32:39.850015 ==
6511 11:32:39.853185 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 11:32:39.857280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:32:39.857373 ==
6514 11:32:39.859697 RX Vref Scan: 0
6515 11:32:39.859758
6516 11:32:39.859816 RX Vref 0 -> 0, step: 1
6517 11:32:39.862922
6518 11:32:39.863005 RX Delay -410 -> 252, step: 16
6519 11:32:39.869690 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6520 11:32:39.872965 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6521 11:32:39.876120 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6522 11:32:39.879405 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6523 11:32:39.886142 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6524 11:32:39.889307 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6525 11:32:39.892684 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6526 11:32:39.899558 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6527 11:32:39.902427 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6528 11:32:39.906228 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6529 11:32:39.909385 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6530 11:32:39.915894 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6531 11:32:39.919024 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6532 11:32:39.922307 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6533 11:32:39.925803 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6534 11:32:39.932133 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6535 11:32:39.932225 ==
6536 11:32:39.935320 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:32:39.939148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:32:39.939236 ==
6539 11:32:39.939320 DQS Delay:
6540 11:32:39.942452 DQS0 = 43, DQS1 = 59
6541 11:32:39.942538 DQM Delay:
6542 11:32:39.945379 DQM0 = 9, DQM1 = 16
6543 11:32:39.945462 DQ Delay:
6544 11:32:39.948909 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6545 11:32:39.952516 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6546 11:32:39.955168 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6547 11:32:39.958576 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6548 11:32:39.958640
6549 11:32:39.958695
6550 11:32:39.958746 ==
6551 11:32:39.961903 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 11:32:39.965114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 11:32:39.965200 ==
6554 11:32:39.965281
6555 11:32:39.965360
6556 11:32:39.969022 TX Vref Scan disable
6557 11:32:39.971852 == TX Byte 0 ==
6558 11:32:39.975125 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6559 11:32:39.978522 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6560 11:32:39.981908 == TX Byte 1 ==
6561 11:32:39.984896 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6562 11:32:39.988319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6563 11:32:39.988406 ==
6564 11:32:39.991600 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 11:32:39.995272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 11:32:39.998520 ==
6567 11:32:39.998581
6568 11:32:39.998657
6569 11:32:39.998734 TX Vref Scan disable
6570 11:32:40.001293 == TX Byte 0 ==
6571 11:32:40.004547 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6572 11:32:40.007998 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6573 11:32:40.011266 == TX Byte 1 ==
6574 11:32:40.014959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6575 11:32:40.017507 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6576 11:32:40.017595
6577 11:32:40.021081 [DATLAT]
6578 11:32:40.021167 Freq=400, CH0 RK1
6579 11:32:40.021246
6580 11:32:40.024829 DATLAT Default: 0xe
6581 11:32:40.024916 0, 0xFFFF, sum = 0
6582 11:32:40.027590 1, 0xFFFF, sum = 0
6583 11:32:40.027661 2, 0xFFFF, sum = 0
6584 11:32:40.031169 3, 0xFFFF, sum = 0
6585 11:32:40.031249 4, 0xFFFF, sum = 0
6586 11:32:40.034261 5, 0xFFFF, sum = 0
6587 11:32:40.034337 6, 0xFFFF, sum = 0
6588 11:32:40.037683 7, 0xFFFF, sum = 0
6589 11:32:40.037759 8, 0xFFFF, sum = 0
6590 11:32:40.040730 9, 0xFFFF, sum = 0
6591 11:32:40.040805 10, 0xFFFF, sum = 0
6592 11:32:40.044424 11, 0xFFFF, sum = 0
6593 11:32:40.044500 12, 0xFFFF, sum = 0
6594 11:32:40.047332 13, 0x0, sum = 1
6595 11:32:40.047408 14, 0x0, sum = 2
6596 11:32:40.050615 15, 0x0, sum = 3
6597 11:32:40.050691 16, 0x0, sum = 4
6598 11:32:40.054105 best_step = 14
6599 11:32:40.054180
6600 11:32:40.054238 ==
6601 11:32:40.057376 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 11:32:40.060579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 11:32:40.060654 ==
6604 11:32:40.064417 RX Vref Scan: 0
6605 11:32:40.064537
6606 11:32:40.064608 RX Vref 0 -> 0, step: 1
6607 11:32:40.064662
6608 11:32:40.067217 RX Delay -359 -> 252, step: 8
6609 11:32:40.075771 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6610 11:32:40.079010 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6611 11:32:40.082049 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6612 11:32:40.088774 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6613 11:32:40.092330 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6614 11:32:40.095324 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6615 11:32:40.098611 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6616 11:32:40.105235 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6617 11:32:40.108350 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6618 11:32:40.111953 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6619 11:32:40.115313 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6620 11:32:40.121571 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6621 11:32:40.124826 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6622 11:32:40.128399 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6623 11:32:40.131956 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6624 11:32:40.138277 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6625 11:32:40.138353 ==
6626 11:32:40.141116 Dram Type= 6, Freq= 0, CH_0, rank 1
6627 11:32:40.144641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 11:32:40.144716 ==
6629 11:32:40.147811 DQS Delay:
6630 11:32:40.147886 DQS0 = 44, DQS1 = 60
6631 11:32:40.147943 DQM Delay:
6632 11:32:40.151169 DQM0 = 8, DQM1 = 15
6633 11:32:40.151244 DQ Delay:
6634 11:32:40.154539 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6635 11:32:40.157575 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6636 11:32:40.161280 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6637 11:32:40.164465 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6638 11:32:40.164532
6639 11:32:40.164587
6640 11:32:40.170795 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6641 11:32:40.174518 CH0 RK1: MR19=C0C, MR18=B23E
6642 11:32:40.180810 CH0_RK1: MR19=0xC0C, MR18=0xB23E, DQSOSC=387, MR23=63, INC=394, DEC=262
6643 11:32:40.184224 [RxdqsGatingPostProcess] freq 400
6644 11:32:40.190583 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6645 11:32:40.194252 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 11:32:40.197868 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 11:32:40.200991 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 11:32:40.203914 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 11:32:40.207089 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 11:32:40.207187 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 11:32:40.210263 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 11:32:40.213787 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 11:32:40.216990 Pre-setting of DQS Precalculation
6654 11:32:40.223571 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6655 11:32:40.223640 ==
6656 11:32:40.226915 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 11:32:40.230256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 11:32:40.230347 ==
6659 11:32:40.237480 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 11:32:40.243870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6661 11:32:40.246749 [CA 0] Center 36 (8~64) winsize 57
6662 11:32:40.250447 [CA 1] Center 36 (8~64) winsize 57
6663 11:32:40.253909 [CA 2] Center 36 (8~64) winsize 57
6664 11:32:40.253998 [CA 3] Center 36 (8~64) winsize 57
6665 11:32:40.256908 [CA 4] Center 36 (8~64) winsize 57
6666 11:32:40.260070 [CA 5] Center 36 (8~64) winsize 57
6667 11:32:40.260136
6668 11:32:40.266414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6669 11:32:40.266494
6670 11:32:40.269765 [CATrainingPosCal] consider 1 rank data
6671 11:32:40.273178 u2DelayCellTimex100 = 270/100 ps
6672 11:32:40.276358 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 11:32:40.280024 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 11:32:40.283356 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:32:40.287158 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:32:40.289687 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:32:40.293659 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:32:40.293734
6679 11:32:40.296329 CA PerBit enable=1, Macro0, CA PI delay=36
6680 11:32:40.296405
6681 11:32:40.299953 [CBTSetCACLKResult] CA Dly = 36
6682 11:32:40.302891 CS Dly: 1 (0~32)
6683 11:32:40.302965 ==
6684 11:32:40.306109 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 11:32:40.309605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 11:32:40.309685 ==
6687 11:32:40.316221 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 11:32:40.322626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6689 11:32:40.325800 [CA 0] Center 36 (8~64) winsize 57
6690 11:32:40.325878 [CA 1] Center 36 (8~64) winsize 57
6691 11:32:40.329398 [CA 2] Center 36 (8~64) winsize 57
6692 11:32:40.332610 [CA 3] Center 36 (8~64) winsize 57
6693 11:32:40.335808 [CA 4] Center 36 (8~64) winsize 57
6694 11:32:40.339360 [CA 5] Center 36 (8~64) winsize 57
6695 11:32:40.339473
6696 11:32:40.342388 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6697 11:32:40.342465
6698 11:32:40.349327 [CATrainingPosCal] consider 2 rank data
6699 11:32:40.349403 u2DelayCellTimex100 = 270/100 ps
6700 11:32:40.355695 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 11:32:40.358944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 11:32:40.362300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:32:40.365592 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:32:40.368884 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:32:40.372114 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:32:40.372202
6707 11:32:40.375669 CA PerBit enable=1, Macro0, CA PI delay=36
6708 11:32:40.375759
6709 11:32:40.378896 [CBTSetCACLKResult] CA Dly = 36
6710 11:32:40.382138 CS Dly: 1 (0~32)
6711 11:32:40.382225
6712 11:32:40.385625 ----->DramcWriteLeveling(PI) begin...
6713 11:32:40.385713 ==
6714 11:32:40.388985 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 11:32:40.391909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 11:32:40.391975 ==
6717 11:32:40.395406 Write leveling (Byte 0): 40 => 8
6718 11:32:40.398826 Write leveling (Byte 1): 32 => 0
6719 11:32:40.402277 DramcWriteLeveling(PI) end<-----
6720 11:32:40.402364
6721 11:32:40.402445 ==
6722 11:32:40.405273 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 11:32:40.408366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 11:32:40.408453 ==
6725 11:32:40.411996 [Gating] SW mode calibration
6726 11:32:40.418635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6727 11:32:40.425116 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6728 11:32:40.428281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 11:32:40.431738 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6730 11:32:40.438227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 11:32:40.441363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 11:32:40.444699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 11:32:40.451334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 11:32:40.454484 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 11:32:40.458047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:32:40.464704 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 11:32:40.467858 Total UI for P1: 0, mck2ui 16
6738 11:32:40.471381 best dqsien dly found for B0: ( 0, 14, 24)
6739 11:32:40.471521 Total UI for P1: 0, mck2ui 16
6740 11:32:40.477662 best dqsien dly found for B1: ( 0, 14, 24)
6741 11:32:40.481236 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6742 11:32:40.484261 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6743 11:32:40.484363
6744 11:32:40.487834 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 11:32:40.491021 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6746 11:32:40.494739 [Gating] SW calibration Done
6747 11:32:40.494829 ==
6748 11:32:40.497480 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 11:32:40.500803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 11:32:40.500896 ==
6751 11:32:40.504382 RX Vref Scan: 0
6752 11:32:40.504483
6753 11:32:40.507326 RX Vref 0 -> 0, step: 1
6754 11:32:40.507447
6755 11:32:40.507554 RX Delay -410 -> 252, step: 16
6756 11:32:40.513809 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6757 11:32:40.517438 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6758 11:32:40.520693 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6759 11:32:40.523795 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6760 11:32:40.530532 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6761 11:32:40.533681 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6762 11:32:40.537185 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6763 11:32:40.543741 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6764 11:32:40.547165 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6765 11:32:40.550536 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6766 11:32:40.553966 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6767 11:32:40.560311 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6768 11:32:40.563618 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6769 11:32:40.566908 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6770 11:32:40.570128 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6771 11:32:40.576682 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6772 11:32:40.576780 ==
6773 11:32:40.580077 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:32:40.583288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:32:40.583380 ==
6776 11:32:40.583503 DQS Delay:
6777 11:32:40.586357 DQS0 = 43, DQS1 = 51
6778 11:32:40.586449 DQM Delay:
6779 11:32:40.589940 DQM0 = 12, DQM1 = 14
6780 11:32:40.590029 DQ Delay:
6781 11:32:40.593317 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6782 11:32:40.596338 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6783 11:32:40.599854 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6784 11:32:40.602959 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6785 11:32:40.603041
6786 11:32:40.603116
6787 11:32:40.603187 ==
6788 11:32:40.606247 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:32:40.609516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:32:40.609597 ==
6791 11:32:40.612912
6792 11:32:40.613021
6793 11:32:40.613096 TX Vref Scan disable
6794 11:32:40.616040 == TX Byte 0 ==
6795 11:32:40.619278 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 11:32:40.623099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 11:32:40.625796 == TX Byte 1 ==
6798 11:32:40.629566 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6799 11:32:40.632775 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6800 11:32:40.632875 ==
6801 11:32:40.635794 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 11:32:40.642820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 11:32:40.642899 ==
6804 11:32:40.642975
6805 11:32:40.643049
6806 11:32:40.643137 TX Vref Scan disable
6807 11:32:40.645932 == TX Byte 0 ==
6808 11:32:40.649017 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 11:32:40.652538 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 11:32:40.655865 == TX Byte 1 ==
6811 11:32:40.659012 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6812 11:32:40.662206 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6813 11:32:40.662283
6814 11:32:40.665900 [DATLAT]
6815 11:32:40.665976 Freq=400, CH1 RK0
6816 11:32:40.666053
6817 11:32:40.668922 DATLAT Default: 0xf
6818 11:32:40.668998 0, 0xFFFF, sum = 0
6819 11:32:40.672242 1, 0xFFFF, sum = 0
6820 11:32:40.672321 2, 0xFFFF, sum = 0
6821 11:32:40.675308 3, 0xFFFF, sum = 0
6822 11:32:40.675423 4, 0xFFFF, sum = 0
6823 11:32:40.678766 5, 0xFFFF, sum = 0
6824 11:32:40.678844 6, 0xFFFF, sum = 0
6825 11:32:40.682305 7, 0xFFFF, sum = 0
6826 11:32:40.685354 8, 0xFFFF, sum = 0
6827 11:32:40.685432 9, 0xFFFF, sum = 0
6828 11:32:40.688775 10, 0xFFFF, sum = 0
6829 11:32:40.688853 11, 0xFFFF, sum = 0
6830 11:32:40.692264 12, 0xFFFF, sum = 0
6831 11:32:40.692342 13, 0x0, sum = 1
6832 11:32:40.695259 14, 0x0, sum = 2
6833 11:32:40.695337 15, 0x0, sum = 3
6834 11:32:40.698289 16, 0x0, sum = 4
6835 11:32:40.698367 best_step = 14
6836 11:32:40.698443
6837 11:32:40.698515 ==
6838 11:32:40.702130 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 11:32:40.705220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:32:40.705298 ==
6841 11:32:40.708527 RX Vref Scan: 1
6842 11:32:40.708604
6843 11:32:40.712116 RX Vref 0 -> 0, step: 1
6844 11:32:40.712193
6845 11:32:40.712268 RX Delay -343 -> 252, step: 8
6846 11:32:40.715208
6847 11:32:40.715284 Set Vref, RX VrefLevel [Byte0]: 50
6848 11:32:40.718252 [Byte1]: 51
6849 11:32:40.723886
6850 11:32:40.723963 Final RX Vref Byte 0 = 50 to rank0
6851 11:32:40.727082 Final RX Vref Byte 1 = 51 to rank0
6852 11:32:40.730675 Final RX Vref Byte 0 = 50 to rank1
6853 11:32:40.734118 Final RX Vref Byte 1 = 51 to rank1==
6854 11:32:40.737384 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 11:32:40.743787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 11:32:40.743865 ==
6857 11:32:40.743941 DQS Delay:
6858 11:32:40.747302 DQS0 = 44, DQS1 = 52
6859 11:32:40.747400 DQM Delay:
6860 11:32:40.747513 DQM0 = 8, DQM1 = 9
6861 11:32:40.750563 DQ Delay:
6862 11:32:40.753564 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6863 11:32:40.753642 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6864 11:32:40.757170 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6865 11:32:40.760134 DQ12 =20, DQ13 =12, DQ14 =12, DQ15 =16
6866 11:32:40.760239
6867 11:32:40.763769
6868 11:32:40.770364 [DQSOSCAuto] RK0, (LSB)MR18= 0x9e74, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6869 11:32:40.773481 CH1 RK0: MR19=C0C, MR18=9E74
6870 11:32:40.779891 CH1_RK0: MR19=0xC0C, MR18=0x9E74, DQSOSC=390, MR23=63, INC=388, DEC=258
6871 11:32:40.779990 ==
6872 11:32:40.783442 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 11:32:40.786801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 11:32:40.786893 ==
6875 11:32:40.790123 [Gating] SW mode calibration
6876 11:32:40.796563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6877 11:32:40.802911 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6878 11:32:40.806496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 11:32:40.809414 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6880 11:32:40.816332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 11:32:40.819380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 11:32:40.822910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 11:32:40.829172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 11:32:40.832716 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 11:32:40.835791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:32:40.842461 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 11:32:40.842529 Total UI for P1: 0, mck2ui 16
6888 11:32:40.849319 best dqsien dly found for B0: ( 0, 14, 24)
6889 11:32:40.849414 Total UI for P1: 0, mck2ui 16
6890 11:32:40.855473 best dqsien dly found for B1: ( 0, 14, 24)
6891 11:32:40.859069 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6892 11:32:40.861960 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6893 11:32:40.862048
6894 11:32:40.865751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 11:32:40.868710 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6896 11:32:40.872232 [Gating] SW calibration Done
6897 11:32:40.872321 ==
6898 11:32:40.875551 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 11:32:40.879133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:32:40.879229 ==
6901 11:32:40.882336 RX Vref Scan: 0
6902 11:32:40.882433
6903 11:32:40.882490 RX Vref 0 -> 0, step: 1
6904 11:32:40.885561
6905 11:32:40.885651 RX Delay -410 -> 252, step: 16
6906 11:32:40.892140 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6907 11:32:40.895397 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6908 11:32:40.898626 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6909 11:32:40.901777 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6910 11:32:40.908350 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6911 11:32:40.911624 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6912 11:32:40.915244 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6913 11:32:40.921799 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6914 11:32:40.925075 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6915 11:32:40.928309 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6916 11:32:40.931698 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6917 11:32:40.938352 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6918 11:32:40.941590 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6919 11:32:40.944902 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6920 11:32:40.948484 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6921 11:32:40.955023 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6922 11:32:40.955099 ==
6923 11:32:40.957780 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:32:40.961390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:32:40.961485 ==
6926 11:32:40.961569 DQS Delay:
6927 11:32:40.964516 DQS0 = 51, DQS1 = 51
6928 11:32:40.964602 DQM Delay:
6929 11:32:40.968213 DQM0 = 19, DQM1 = 12
6930 11:32:40.968299 DQ Delay:
6931 11:32:40.971189 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6932 11:32:40.974417 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6933 11:32:40.977703 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6934 11:32:40.981452 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6935 11:32:40.981517
6936 11:32:40.981572
6937 11:32:40.981623 ==
6938 11:32:40.984691 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 11:32:40.988051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 11:32:40.988114 ==
6941 11:32:40.988189
6942 11:32:40.990966
6943 11:32:40.991049 TX Vref Scan disable
6944 11:32:40.994667 == TX Byte 0 ==
6945 11:32:40.997585 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6946 11:32:41.000946 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6947 11:32:41.004229 == TX Byte 1 ==
6948 11:32:41.007772 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6949 11:32:41.011051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6950 11:32:41.011139 ==
6951 11:32:41.014409 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 11:32:41.017410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 11:32:41.020821 ==
6954 11:32:41.020910
6955 11:32:41.020991
6956 11:32:41.021069 TX Vref Scan disable
6957 11:32:41.024108 == TX Byte 0 ==
6958 11:32:41.027569 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6959 11:32:41.030946 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6960 11:32:41.034048 == TX Byte 1 ==
6961 11:32:41.037603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6962 11:32:41.040701 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6963 11:32:41.040787
6964 11:32:41.040865 [DATLAT]
6965 11:32:41.044034 Freq=400, CH1 RK1
6966 11:32:41.044116
6967 11:32:41.047271 DATLAT Default: 0xe
6968 11:32:41.047357 0, 0xFFFF, sum = 0
6969 11:32:41.050609 1, 0xFFFF, sum = 0
6970 11:32:41.050695 2, 0xFFFF, sum = 0
6971 11:32:41.053886 3, 0xFFFF, sum = 0
6972 11:32:41.053972 4, 0xFFFF, sum = 0
6973 11:32:41.057473 5, 0xFFFF, sum = 0
6974 11:32:41.057560 6, 0xFFFF, sum = 0
6975 11:32:41.060527 7, 0xFFFF, sum = 0
6976 11:32:41.060614 8, 0xFFFF, sum = 0
6977 11:32:41.063737 9, 0xFFFF, sum = 0
6978 11:32:41.063824 10, 0xFFFF, sum = 0
6979 11:32:41.067348 11, 0xFFFF, sum = 0
6980 11:32:41.067458 12, 0xFFFF, sum = 0
6981 11:32:41.071355 13, 0x0, sum = 1
6982 11:32:41.071486 14, 0x0, sum = 2
6983 11:32:41.073647 15, 0x0, sum = 3
6984 11:32:41.073733 16, 0x0, sum = 4
6985 11:32:41.076853 best_step = 14
6986 11:32:41.076942
6987 11:32:41.077022 ==
6988 11:32:41.080430 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 11:32:41.083727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 11:32:41.083813 ==
6991 11:32:41.086845 RX Vref Scan: 0
6992 11:32:41.086930
6993 11:32:41.087008 RX Vref 0 -> 0, step: 1
6994 11:32:41.087084
6995 11:32:41.090029 RX Delay -343 -> 252, step: 8
6996 11:32:41.098065 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6997 11:32:41.101688 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6998 11:32:41.105103 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6999 11:32:41.111330 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7000 11:32:41.114969 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7001 11:32:41.118240 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7002 11:32:41.121621 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7003 11:32:41.128196 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7004 11:32:41.131618 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7005 11:32:41.134460 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7006 11:32:41.137827 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7007 11:32:41.144479 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7008 11:32:41.147932 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7009 11:32:41.150803 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7010 11:32:41.154099 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7011 11:32:41.160766 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
7012 11:32:41.160858 ==
7013 11:32:41.163949 Dram Type= 6, Freq= 0, CH_1, rank 1
7014 11:32:41.167177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7015 11:32:41.167265 ==
7016 11:32:41.170934 DQS Delay:
7017 11:32:41.171022 DQS0 = 48, DQS1 = 56
7018 11:32:41.171101 DQM Delay:
7019 11:32:41.173722 DQM0 = 14, DQM1 = 11
7020 11:32:41.173805 DQ Delay:
7021 11:32:41.177234 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7022 11:32:41.180541 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7023 11:32:41.183736 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7024 11:32:41.187220 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
7025 11:32:41.187305
7026 11:32:41.187385
7027 11:32:41.196814 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7028 11:32:41.196887 CH1 RK1: MR19=C0C, MR18=6B5C
7029 11:32:41.203375 CH1_RK1: MR19=0xC0C, MR18=0x6B5C, DQSOSC=396, MR23=63, INC=376, DEC=251
7030 11:32:41.206991 [RxdqsGatingPostProcess] freq 400
7031 11:32:41.213507 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7032 11:32:41.216909 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 11:32:41.220034 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 11:32:41.223230 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 11:32:41.226536 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 11:32:41.229685 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 11:32:41.233070 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 11:32:41.236581 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 11:32:41.240037 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 11:32:41.240102 Pre-setting of DQS Precalculation
7041 11:32:41.246874 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7042 11:32:41.252878 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7043 11:32:41.259460 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7044 11:32:41.259544
7045 11:32:41.259601
7046 11:32:41.262821 [Calibration Summary] 800 Mbps
7047 11:32:41.266027 CH 0, Rank 0
7048 11:32:41.266111 SW Impedance : PASS
7049 11:32:41.269325 DUTY Scan : NO K
7050 11:32:41.272606 ZQ Calibration : PASS
7051 11:32:41.272694 Jitter Meter : NO K
7052 11:32:41.276424 CBT Training : PASS
7053 11:32:41.279361 Write leveling : PASS
7054 11:32:41.279482 RX DQS gating : PASS
7055 11:32:41.282928 RX DQ/DQS(RDDQC) : PASS
7056 11:32:41.286192 TX DQ/DQS : PASS
7057 11:32:41.286280 RX DATLAT : PASS
7058 11:32:41.289288 RX DQ/DQS(Engine): PASS
7059 11:32:41.289370 TX OE : NO K
7060 11:32:41.292931 All Pass.
7061 11:32:41.293014
7062 11:32:41.293091 CH 0, Rank 1
7063 11:32:41.295861 SW Impedance : PASS
7064 11:32:41.295945 DUTY Scan : NO K
7065 11:32:41.299349 ZQ Calibration : PASS
7066 11:32:41.302353 Jitter Meter : NO K
7067 11:32:41.302440 CBT Training : PASS
7068 11:32:41.305641 Write leveling : NO K
7069 11:32:41.309120 RX DQS gating : PASS
7070 11:32:41.309208 RX DQ/DQS(RDDQC) : PASS
7071 11:32:41.312298 TX DQ/DQS : PASS
7072 11:32:41.315536 RX DATLAT : PASS
7073 11:32:41.315620 RX DQ/DQS(Engine): PASS
7074 11:32:41.319365 TX OE : NO K
7075 11:32:41.319487 All Pass.
7076 11:32:41.319542
7077 11:32:41.322460 CH 1, Rank 0
7078 11:32:41.322548 SW Impedance : PASS
7079 11:32:41.325592 DUTY Scan : NO K
7080 11:32:41.328902 ZQ Calibration : PASS
7081 11:32:41.328988 Jitter Meter : NO K
7082 11:32:41.332365 CBT Training : PASS
7083 11:32:41.335824 Write leveling : PASS
7084 11:32:41.335890 RX DQS gating : PASS
7085 11:32:41.338825 RX DQ/DQS(RDDQC) : PASS
7086 11:32:41.342137 TX DQ/DQS : PASS
7087 11:32:41.342229 RX DATLAT : PASS
7088 11:32:41.345656 RX DQ/DQS(Engine): PASS
7089 11:32:41.348752 TX OE : NO K
7090 11:32:41.348838 All Pass.
7091 11:32:41.348921
7092 11:32:41.349001 CH 1, Rank 1
7093 11:32:41.352590 SW Impedance : PASS
7094 11:32:41.355561 DUTY Scan : NO K
7095 11:32:41.355651 ZQ Calibration : PASS
7096 11:32:41.358791 Jitter Meter : NO K
7097 11:32:41.358880 CBT Training : PASS
7098 11:32:41.362016 Write leveling : NO K
7099 11:32:41.365647 RX DQS gating : PASS
7100 11:32:41.365742 RX DQ/DQS(RDDQC) : PASS
7101 11:32:41.368749 TX DQ/DQS : PASS
7102 11:32:41.371810 RX DATLAT : PASS
7103 11:32:41.371904 RX DQ/DQS(Engine): PASS
7104 11:32:41.375607 TX OE : NO K
7105 11:32:41.375699 All Pass.
7106 11:32:41.375781
7107 11:32:41.378408 DramC Write-DBI off
7108 11:32:41.381905 PER_BANK_REFRESH: Hybrid Mode
7109 11:32:41.381975 TX_TRACKING: ON
7110 11:32:41.391698 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7111 11:32:41.394905 [FAST_K] Save calibration result to emmc
7112 11:32:41.398307 dramc_set_vcore_voltage set vcore to 725000
7113 11:32:41.401443 Read voltage for 1600, 0
7114 11:32:41.401530 Vio18 = 0
7115 11:32:41.405081 Vcore = 725000
7116 11:32:41.405173 Vdram = 0
7117 11:32:41.405255 Vddq = 0
7118 11:32:41.405333 Vmddr = 0
7119 11:32:41.411560 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7120 11:32:41.418001 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7121 11:32:41.418095 MEM_TYPE=3, freq_sel=13
7122 11:32:41.421288 sv_algorithm_assistance_LP4_3733
7123 11:32:41.424444 ============ PULL DRAM RESETB DOWN ============
7124 11:32:41.431413 ========== PULL DRAM RESETB DOWN end =========
7125 11:32:41.434597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7126 11:32:41.437876 ===================================
7127 11:32:41.441194 LPDDR4 DRAM CONFIGURATION
7128 11:32:41.444916 ===================================
7129 11:32:41.445006 EX_ROW_EN[0] = 0x0
7130 11:32:41.447662 EX_ROW_EN[1] = 0x0
7131 11:32:41.451138 LP4Y_EN = 0x0
7132 11:32:41.451226 WORK_FSP = 0x1
7133 11:32:41.454188 WL = 0x5
7134 11:32:41.454275 RL = 0x5
7135 11:32:41.457996 BL = 0x2
7136 11:32:41.458085 RPST = 0x0
7137 11:32:41.460588 RD_PRE = 0x0
7138 11:32:41.460682 WR_PRE = 0x1
7139 11:32:41.463830 WR_PST = 0x1
7140 11:32:41.463919 DBI_WR = 0x0
7141 11:32:41.467592 DBI_RD = 0x0
7142 11:32:41.467654 OTF = 0x1
7143 11:32:41.470793 ===================================
7144 11:32:41.474334 ===================================
7145 11:32:41.477254 ANA top config
7146 11:32:41.480342 ===================================
7147 11:32:41.480405 DLL_ASYNC_EN = 0
7148 11:32:41.483696 ALL_SLAVE_EN = 0
7149 11:32:41.487289 NEW_RANK_MODE = 1
7150 11:32:41.490355 DLL_IDLE_MODE = 1
7151 11:32:41.493732 LP45_APHY_COMB_EN = 1
7152 11:32:41.493818 TX_ODT_DIS = 0
7153 11:32:41.496848 NEW_8X_MODE = 1
7154 11:32:41.500026 ===================================
7155 11:32:41.504429 ===================================
7156 11:32:41.507185 data_rate = 3200
7157 11:32:41.510395 CKR = 1
7158 11:32:41.513913 DQ_P2S_RATIO = 8
7159 11:32:41.516802 ===================================
7160 11:32:41.520022 CA_P2S_RATIO = 8
7161 11:32:41.520089 DQ_CA_OPEN = 0
7162 11:32:41.523327 DQ_SEMI_OPEN = 0
7163 11:32:41.527068 CA_SEMI_OPEN = 0
7164 11:32:41.529915 CA_FULL_RATE = 0
7165 11:32:41.533166 DQ_CKDIV4_EN = 0
7166 11:32:41.536836 CA_CKDIV4_EN = 0
7167 11:32:41.536923 CA_PREDIV_EN = 0
7168 11:32:41.539798 PH8_DLY = 12
7169 11:32:41.543134 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7170 11:32:41.546403 DQ_AAMCK_DIV = 4
7171 11:32:41.549997 CA_AAMCK_DIV = 4
7172 11:32:41.553290 CA_ADMCK_DIV = 4
7173 11:32:41.553378 DQ_TRACK_CA_EN = 0
7174 11:32:41.556480 CA_PICK = 1600
7175 11:32:41.559960 CA_MCKIO = 1600
7176 11:32:41.562999 MCKIO_SEMI = 0
7177 11:32:41.566221 PLL_FREQ = 3068
7178 11:32:41.569526 DQ_UI_PI_RATIO = 32
7179 11:32:41.572843 CA_UI_PI_RATIO = 0
7180 11:32:41.576461 ===================================
7181 11:32:41.579897 ===================================
7182 11:32:41.579988 memory_type:LPDDR4
7183 11:32:41.582956 GP_NUM : 10
7184 11:32:41.586163 SRAM_EN : 1
7185 11:32:41.586249 MD32_EN : 0
7186 11:32:41.590014 ===================================
7187 11:32:41.592669 [ANA_INIT] >>>>>>>>>>>>>>
7188 11:32:41.595934 <<<<<< [CONFIGURE PHASE]: ANA_TX
7189 11:32:41.599214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7190 11:32:41.602712 ===================================
7191 11:32:41.606171 data_rate = 3200,PCW = 0X7600
7192 11:32:41.609263 ===================================
7193 11:32:41.612762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7194 11:32:41.615632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 11:32:41.622317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7196 11:32:41.625804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7197 11:32:41.632447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7198 11:32:41.635373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7199 11:32:41.635486 [ANA_INIT] flow start
7200 11:32:41.638638 [ANA_INIT] PLL >>>>>>>>
7201 11:32:41.642131 [ANA_INIT] PLL <<<<<<<<
7202 11:32:41.642228 [ANA_INIT] MIDPI >>>>>>>>
7203 11:32:41.645486 [ANA_INIT] MIDPI <<<<<<<<
7204 11:32:41.648724 [ANA_INIT] DLL >>>>>>>>
7205 11:32:41.648800 [ANA_INIT] DLL <<<<<<<<
7206 11:32:41.652333 [ANA_INIT] flow end
7207 11:32:41.655127 ============ LP4 DIFF to SE enter ============
7208 11:32:41.658632 ============ LP4 DIFF to SE exit ============
7209 11:32:41.661812 [ANA_INIT] <<<<<<<<<<<<<
7210 11:32:41.665304 [Flow] Enable top DCM control >>>>>
7211 11:32:41.668329 [Flow] Enable top DCM control <<<<<
7212 11:32:41.671929 Enable DLL master slave shuffle
7213 11:32:41.678404 ==============================================================
7214 11:32:41.678481 Gating Mode config
7215 11:32:41.685094 ==============================================================
7216 11:32:41.688412 Config description:
7217 11:32:41.695053 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7218 11:32:41.701698 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7219 11:32:41.708153 SELPH_MODE 0: By rank 1: By Phase
7220 11:32:41.714519 ==============================================================
7221 11:32:41.717835 GAT_TRACK_EN = 1
7222 11:32:41.717926 RX_GATING_MODE = 2
7223 11:32:41.721446 RX_GATING_TRACK_MODE = 2
7224 11:32:41.724411 SELPH_MODE = 1
7225 11:32:41.727782 PICG_EARLY_EN = 1
7226 11:32:41.731355 VALID_LAT_VALUE = 1
7227 11:32:41.737941 ==============================================================
7228 11:32:41.741010 Enter into Gating configuration >>>>
7229 11:32:41.744479 Exit from Gating configuration <<<<
7230 11:32:41.747642 Enter into DVFS_PRE_config >>>>>
7231 11:32:41.757266 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7232 11:32:41.760621 Exit from DVFS_PRE_config <<<<<
7233 11:32:41.764014 Enter into PICG configuration >>>>
7234 11:32:41.767581 Exit from PICG configuration <<<<
7235 11:32:41.770421 [RX_INPUT] configuration >>>>>
7236 11:32:41.774146 [RX_INPUT] configuration <<<<<
7237 11:32:41.777193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7238 11:32:41.783900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7239 11:32:41.790359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7240 11:32:41.796939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7241 11:32:41.803893 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 11:32:41.807119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 11:32:41.813352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7244 11:32:41.816972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7245 11:32:41.820434 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7246 11:32:41.823263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7247 11:32:41.830274 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7248 11:32:41.833602 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 11:32:41.836654 ===================================
7250 11:32:41.839753 LPDDR4 DRAM CONFIGURATION
7251 11:32:41.843108 ===================================
7252 11:32:41.843198 EX_ROW_EN[0] = 0x0
7253 11:32:41.846356 EX_ROW_EN[1] = 0x0
7254 11:32:41.846442 LP4Y_EN = 0x0
7255 11:32:41.849498 WORK_FSP = 0x1
7256 11:32:41.849586 WL = 0x5
7257 11:32:41.852995 RL = 0x5
7258 11:32:41.853070 BL = 0x2
7259 11:32:41.856649 RPST = 0x0
7260 11:32:41.856724 RD_PRE = 0x0
7261 11:32:41.859744 WR_PRE = 0x1
7262 11:32:41.863614 WR_PST = 0x1
7263 11:32:41.863688 DBI_WR = 0x0
7264 11:32:41.866602 DBI_RD = 0x0
7265 11:32:41.866676 OTF = 0x1
7266 11:32:41.869349 ===================================
7267 11:32:41.872932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7268 11:32:41.879394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7269 11:32:41.882485 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 11:32:41.885822 ===================================
7271 11:32:41.889384 LPDDR4 DRAM CONFIGURATION
7272 11:32:41.892565 ===================================
7273 11:32:41.892689 EX_ROW_EN[0] = 0x10
7274 11:32:41.895983 EX_ROW_EN[1] = 0x0
7275 11:32:41.896072 LP4Y_EN = 0x0
7276 11:32:41.899075 WORK_FSP = 0x1
7277 11:32:41.899145 WL = 0x5
7278 11:32:41.902874 RL = 0x5
7279 11:32:41.905884 BL = 0x2
7280 11:32:41.905977 RPST = 0x0
7281 11:32:41.909167 RD_PRE = 0x0
7282 11:32:41.909230 WR_PRE = 0x1
7283 11:32:41.912153 WR_PST = 0x1
7284 11:32:41.912240 DBI_WR = 0x0
7285 11:32:41.915440 DBI_RD = 0x0
7286 11:32:41.915526 OTF = 0x1
7287 11:32:41.918972 ===================================
7288 11:32:41.925740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7289 11:32:41.925830 ==
7290 11:32:41.928613 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 11:32:41.931858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 11:32:41.931953 ==
7293 11:32:41.936086 [Duty_Offset_Calibration]
7294 11:32:41.938844 B0:1 B1:-1 CA:0
7295 11:32:41.938938
7296 11:32:41.941829 [DutyScan_Calibration_Flow] k_type=0
7297 11:32:41.950768
7298 11:32:41.950864 ==CLK 0==
7299 11:32:41.954007 Final CLK duty delay cell = 0
7300 11:32:41.957522 [0] MAX Duty = 5124%(X100), DQS PI = 22
7301 11:32:41.960754 [0] MIN Duty = 4907%(X100), DQS PI = 4
7302 11:32:41.960850 [0] AVG Duty = 5015%(X100)
7303 11:32:41.963772
7304 11:32:41.967280 CH0 CLK Duty spec in!! Max-Min= 217%
7305 11:32:41.970400 [DutyScan_Calibration_Flow] ====Done====
7306 11:32:41.970489
7307 11:32:41.974019 [DutyScan_Calibration_Flow] k_type=1
7308 11:32:41.990036
7309 11:32:41.990137 ==DQS 0 ==
7310 11:32:41.993231 Final DQS duty delay cell = -4
7311 11:32:41.996346 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7312 11:32:41.999404 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7313 11:32:42.003362 [-4] AVG Duty = 4906%(X100)
7314 11:32:42.003492
7315 11:32:42.003549 ==DQS 1 ==
7316 11:32:42.006059 Final DQS duty delay cell = 0
7317 11:32:42.009621 [0] MAX Duty = 5156%(X100), DQS PI = 2
7318 11:32:42.012760 [0] MIN Duty = 5000%(X100), DQS PI = 18
7319 11:32:42.015822 [0] AVG Duty = 5078%(X100)
7320 11:32:42.015894
7321 11:32:42.019089 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7322 11:32:42.019159
7323 11:32:42.022643 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7324 11:32:42.025710 [DutyScan_Calibration_Flow] ====Done====
7325 11:32:42.025798
7326 11:32:42.029265 [DutyScan_Calibration_Flow] k_type=3
7327 11:32:42.047433
7328 11:32:42.047523 ==DQM 0 ==
7329 11:32:42.050375 Final DQM duty delay cell = 0
7330 11:32:42.053588 [0] MAX Duty = 5124%(X100), DQS PI = 22
7331 11:32:42.057041 [0] MIN Duty = 4875%(X100), DQS PI = 10
7332 11:32:42.060365 [0] AVG Duty = 4999%(X100)
7333 11:32:42.060434
7334 11:32:42.060489 ==DQM 1 ==
7335 11:32:42.063846 Final DQM duty delay cell = 0
7336 11:32:42.067031 [0] MAX Duty = 5000%(X100), DQS PI = 8
7337 11:32:42.070351 [0] MIN Duty = 4782%(X100), DQS PI = 20
7338 11:32:42.073564 [0] AVG Duty = 4891%(X100)
7339 11:32:42.073639
7340 11:32:42.076969 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7341 11:32:42.077043
7342 11:32:42.079901 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7343 11:32:42.083049 [DutyScan_Calibration_Flow] ====Done====
7344 11:32:42.083146
7345 11:32:42.086641 [DutyScan_Calibration_Flow] k_type=2
7346 11:32:42.103562
7347 11:32:42.103629 ==DQ 0 ==
7348 11:32:42.107215 Final DQ duty delay cell = -4
7349 11:32:42.109954 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7350 11:32:42.113310 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7351 11:32:42.117002 [-4] AVG Duty = 4953%(X100)
7352 11:32:42.117076
7353 11:32:42.117130 ==DQ 1 ==
7354 11:32:42.120438 Final DQ duty delay cell = 0
7355 11:32:42.123275 [0] MAX Duty = 5125%(X100), DQS PI = 2
7356 11:32:42.126721 [0] MIN Duty = 5000%(X100), DQS PI = 36
7357 11:32:42.130248 [0] AVG Duty = 5062%(X100)
7358 11:32:42.130339
7359 11:32:42.133264 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7360 11:32:42.133356
7361 11:32:42.136877 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7362 11:32:42.140187 [DutyScan_Calibration_Flow] ====Done====
7363 11:32:42.140251 ==
7364 11:32:42.143294 Dram Type= 6, Freq= 0, CH_1, rank 0
7365 11:32:42.146284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7366 11:32:42.146376 ==
7367 11:32:42.149955 [Duty_Offset_Calibration]
7368 11:32:42.150027 B0:-1 B1:1 CA:2
7369 11:32:42.150086
7370 11:32:42.153209 [DutyScan_Calibration_Flow] k_type=0
7371 11:32:42.164058
7372 11:32:42.164126 ==CLK 0==
7373 11:32:42.167388 Final CLK duty delay cell = 0
7374 11:32:42.170689 [0] MAX Duty = 5187%(X100), DQS PI = 22
7375 11:32:42.174298 [0] MIN Duty = 4969%(X100), DQS PI = 0
7376 11:32:42.174386 [0] AVG Duty = 5078%(X100)
7377 11:32:42.177445
7378 11:32:42.180961 CH1 CLK Duty spec in!! Max-Min= 218%
7379 11:32:42.184060 [DutyScan_Calibration_Flow] ====Done====
7380 11:32:42.184124
7381 11:32:42.187238 [DutyScan_Calibration_Flow] k_type=1
7382 11:32:42.203690
7383 11:32:42.203764 ==DQS 0 ==
7384 11:32:42.206940 Final DQS duty delay cell = 0
7385 11:32:42.210555 [0] MAX Duty = 5124%(X100), DQS PI = 18
7386 11:32:42.213750 [0] MIN Duty = 4907%(X100), DQS PI = 8
7387 11:32:42.217061 [0] AVG Duty = 5015%(X100)
7388 11:32:42.217124
7389 11:32:42.217179 ==DQS 1 ==
7390 11:32:42.220551 Final DQS duty delay cell = 0
7391 11:32:42.223369 [0] MAX Duty = 5093%(X100), DQS PI = 26
7392 11:32:42.227084 [0] MIN Duty = 4969%(X100), DQS PI = 56
7393 11:32:42.230373 [0] AVG Duty = 5031%(X100)
7394 11:32:42.230459
7395 11:32:42.233376 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7396 11:32:42.233461
7397 11:32:42.236793 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7398 11:32:42.240507 [DutyScan_Calibration_Flow] ====Done====
7399 11:32:42.240579
7400 11:32:42.243041 [DutyScan_Calibration_Flow] k_type=3
7401 11:32:42.260695
7402 11:32:42.260771 ==DQM 0 ==
7403 11:32:42.263826 Final DQM duty delay cell = 0
7404 11:32:42.267372 [0] MAX Duty = 5218%(X100), DQS PI = 34
7405 11:32:42.270772 [0] MIN Duty = 5000%(X100), DQS PI = 10
7406 11:32:42.273660 [0] AVG Duty = 5109%(X100)
7407 11:32:42.273734
7408 11:32:42.273791 ==DQM 1 ==
7409 11:32:42.276984 Final DQM duty delay cell = 0
7410 11:32:42.280245 [0] MAX Duty = 5156%(X100), DQS PI = 2
7411 11:32:42.283909 [0] MIN Duty = 4938%(X100), DQS PI = 34
7412 11:32:42.287308 [0] AVG Duty = 5047%(X100)
7413 11:32:42.287383
7414 11:32:42.290404 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7415 11:32:42.290478
7416 11:32:42.293530 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7417 11:32:42.296910 [DutyScan_Calibration_Flow] ====Done====
7418 11:32:42.296985
7419 11:32:42.300381 [DutyScan_Calibration_Flow] k_type=2
7420 11:32:42.317372
7421 11:32:42.317446 ==DQ 0 ==
7422 11:32:42.321278 Final DQ duty delay cell = 0
7423 11:32:42.324025 [0] MAX Duty = 5187%(X100), DQS PI = 34
7424 11:32:42.327389 [0] MIN Duty = 4906%(X100), DQS PI = 10
7425 11:32:42.330701 [0] AVG Duty = 5046%(X100)
7426 11:32:42.330794
7427 11:32:42.330881 ==DQ 1 ==
7428 11:32:42.333719 Final DQ duty delay cell = 0
7429 11:32:42.337588 [0] MAX Duty = 5125%(X100), DQS PI = 8
7430 11:32:42.340614 [0] MIN Duty = 4969%(X100), DQS PI = 56
7431 11:32:42.340702 [0] AVG Duty = 5047%(X100)
7432 11:32:42.343690
7433 11:32:42.347069 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7434 11:32:42.347159
7435 11:32:42.350978 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7436 11:32:42.353623 [DutyScan_Calibration_Flow] ====Done====
7437 11:32:42.356895 nWR fixed to 30
7438 11:32:42.356983 [ModeRegInit_LP4] CH0 RK0
7439 11:32:42.360525 [ModeRegInit_LP4] CH0 RK1
7440 11:32:42.363652 [ModeRegInit_LP4] CH1 RK0
7441 11:32:42.367239 [ModeRegInit_LP4] CH1 RK1
7442 11:32:42.367327 match AC timing 5
7443 11:32:42.373356 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7444 11:32:42.376851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7445 11:32:42.380006 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7446 11:32:42.386938 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7447 11:32:42.390043 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7448 11:32:42.390138 [MiockJmeterHQA]
7449 11:32:42.390223
7450 11:32:42.393100 [DramcMiockJmeter] u1RxGatingPI = 0
7451 11:32:42.396529 0 : 4253, 4026
7452 11:32:42.396593 4 : 4363, 4137
7453 11:32:42.399802 8 : 4252, 4027
7454 11:32:42.399868 12 : 4252, 4027
7455 11:32:42.403326 16 : 4252, 4027
7456 11:32:42.403435 20 : 4253, 4026
7457 11:32:42.403507 24 : 4255, 4030
7458 11:32:42.406521 28 : 4252, 4027
7459 11:32:42.406606 32 : 4252, 4027
7460 11:32:42.409721 36 : 4366, 4140
7461 11:32:42.409808 40 : 4253, 4026
7462 11:32:42.413264 44 : 4254, 4029
7463 11:32:42.413350 48 : 4253, 4026
7464 11:32:42.416421 52 : 4361, 4137
7465 11:32:42.416510 56 : 4250, 4027
7466 11:32:42.416592 60 : 4360, 4137
7467 11:32:42.419920 64 : 4250, 4027
7468 11:32:42.420008 68 : 4250, 4026
7469 11:32:42.422802 72 : 4250, 4026
7470 11:32:42.422889 76 : 4252, 4030
7471 11:32:42.426395 80 : 4361, 4137
7472 11:32:42.426481 84 : 4250, 4027
7473 11:32:42.429441 88 : 4361, 4137
7474 11:32:42.429526 92 : 4250, 335
7475 11:32:42.429605 96 : 4250, 0
7476 11:32:42.432929 100 : 4250, 0
7477 11:32:42.433014 104 : 4250, 0
7478 11:32:42.433093 108 : 4250, 0
7479 11:32:42.436319 112 : 4253, 0
7480 11:32:42.436406 116 : 4361, 0
7481 11:32:42.439477 120 : 4250, 0
7482 11:32:42.439539 124 : 4250, 0
7483 11:32:42.439592 128 : 4360, 0
7484 11:32:42.442559 132 : 4361, 0
7485 11:32:42.442647 136 : 4250, 0
7486 11:32:42.446320 140 : 4250, 0
7487 11:32:42.446407 144 : 4250, 0
7488 11:32:42.446490 148 : 4363, 0
7489 11:32:42.449286 152 : 4250, 0
7490 11:32:42.449374 156 : 4250, 0
7491 11:32:42.453095 160 : 4250, 0
7492 11:32:42.453182 164 : 4252, 0
7493 11:32:42.453263 168 : 4361, 0
7494 11:32:42.455788 172 : 4250, 0
7495 11:32:42.455876 176 : 4249, 0
7496 11:32:42.459059 180 : 4250, 0
7497 11:32:42.459151 184 : 4360, 0
7498 11:32:42.459236 188 : 4360, 0
7499 11:32:42.462842 192 : 4250, 0
7500 11:32:42.462936 196 : 4250, 0
7501 11:32:42.466202 200 : 4250, 0
7502 11:32:42.466293 204 : 4252, 0
7503 11:32:42.466375 208 : 4250, 0
7504 11:32:42.469443 212 : 4250, 0
7505 11:32:42.469530 216 : 4252, 0
7506 11:32:42.469611 220 : 4361, 0
7507 11:32:42.472385 224 : 4250, 98
7508 11:32:42.472473 228 : 4250, 3293
7509 11:32:42.475860 232 : 4361, 4138
7510 11:32:42.475957 236 : 4361, 4137
7511 11:32:42.479120 240 : 4250, 4026
7512 11:32:42.479216 244 : 4250, 4027
7513 11:32:42.482259 248 : 4252, 4030
7514 11:32:42.482349 252 : 4250, 4026
7515 11:32:42.485444 256 : 4250, 4026
7516 11:32:42.485534 260 : 4250, 4027
7517 11:32:42.488715 264 : 4252, 4029
7518 11:32:42.488803 268 : 4250, 4026
7519 11:32:42.492411 272 : 4361, 4137
7520 11:32:42.492481 276 : 4361, 4137
7521 11:32:42.492538 280 : 4250, 4027
7522 11:32:42.495634 284 : 4363, 4140
7523 11:32:42.495713 288 : 4361, 4137
7524 11:32:42.498862 292 : 4250, 4026
7525 11:32:42.498959 296 : 4250, 4027
7526 11:32:42.502324 300 : 4252, 4030
7527 11:32:42.502423 304 : 4250, 4026
7528 11:32:42.505532 308 : 4250, 4026
7529 11:32:42.505623 312 : 4250, 4027
7530 11:32:42.508533 316 : 4252, 4030
7531 11:32:42.508622 320 : 4250, 4027
7532 11:32:42.511936 324 : 4361, 4137
7533 11:32:42.512027 328 : 4361, 4137
7534 11:32:42.515120 332 : 4250, 4027
7535 11:32:42.515219 336 : 4363, 3968
7536 11:32:42.518455 340 : 4361, 2090
7537 11:32:42.518530
7538 11:32:42.518587 MIOCK jitter meter ch=0
7539 11:32:42.518640
7540 11:32:42.521946 1T = (340-92) = 248 dly cells
7541 11:32:42.528466 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7542 11:32:42.528536 ==
7543 11:32:42.531896 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 11:32:42.535237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 11:32:42.535333 ==
7546 11:32:42.541614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 11:32:42.544883 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 11:32:42.548151 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 11:32:42.554784 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 11:32:42.564721 [CA 0] Center 43 (13~74) winsize 62
7551 11:32:42.567902 [CA 1] Center 43 (13~74) winsize 62
7552 11:32:42.571361 [CA 2] Center 39 (10~69) winsize 60
7553 11:32:42.574760 [CA 3] Center 39 (9~69) winsize 61
7554 11:32:42.577817 [CA 4] Center 37 (8~66) winsize 59
7555 11:32:42.581018 [CA 5] Center 36 (7~66) winsize 60
7556 11:32:42.581106
7557 11:32:42.584535 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 11:32:42.584625
7559 11:32:42.591257 [CATrainingPosCal] consider 1 rank data
7560 11:32:42.591354 u2DelayCellTimex100 = 262/100 ps
7561 11:32:42.597433 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7562 11:32:42.600801 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7563 11:32:42.603933 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7564 11:32:42.607172 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7565 11:32:42.610633 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7566 11:32:42.613843 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7567 11:32:42.613911
7568 11:32:42.617850 CA PerBit enable=1, Macro0, CA PI delay=36
7569 11:32:42.617939
7570 11:32:42.620532 [CBTSetCACLKResult] CA Dly = 36
7571 11:32:42.623841 CS Dly: 12 (0~43)
7572 11:32:42.627328 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 11:32:42.630462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 11:32:42.630557 ==
7575 11:32:42.633703 Dram Type= 6, Freq= 0, CH_0, rank 1
7576 11:32:42.640617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 11:32:42.640712 ==
7578 11:32:42.643514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 11:32:42.650057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 11:32:42.653306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 11:32:42.659883 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 11:32:42.668374 [CA 0] Center 43 (13~74) winsize 62
7583 11:32:42.671492 [CA 1] Center 44 (14~74) winsize 61
7584 11:32:42.674876 [CA 2] Center 38 (9~68) winsize 60
7585 11:32:42.677963 [CA 3] Center 38 (9~68) winsize 60
7586 11:32:42.681220 [CA 4] Center 36 (7~66) winsize 60
7587 11:32:42.685226 [CA 5] Center 36 (7~66) winsize 60
7588 11:32:42.685316
7589 11:32:42.688228 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 11:32:42.688314
7591 11:32:42.694656 [CATrainingPosCal] consider 2 rank data
7592 11:32:42.694717 u2DelayCellTimex100 = 262/100 ps
7593 11:32:42.701344 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 11:32:42.704855 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7595 11:32:42.707901 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7596 11:32:42.711163 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7597 11:32:42.714377 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7598 11:32:42.717502 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7599 11:32:42.717599
7600 11:32:42.721048 CA PerBit enable=1, Macro0, CA PI delay=36
7601 11:32:42.721140
7602 11:32:42.724455 [CBTSetCACLKResult] CA Dly = 36
7603 11:32:42.727876 CS Dly: 12 (0~44)
7604 11:32:42.730886 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 11:32:42.734295 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 11:32:42.734394
7607 11:32:42.737726 ----->DramcWriteLeveling(PI) begin...
7608 11:32:42.737823 ==
7609 11:32:42.740943 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:32:42.747419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:32:42.747604 ==
7612 11:32:42.750859 Write leveling (Byte 0): 37 => 37
7613 11:32:42.753877 Write leveling (Byte 1): 28 => 28
7614 11:32:42.757372 DramcWriteLeveling(PI) end<-----
7615 11:32:42.757463
7616 11:32:42.757546 ==
7617 11:32:42.760732 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 11:32:42.763787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 11:32:42.763886 ==
7620 11:32:42.767253 [Gating] SW mode calibration
7621 11:32:42.774183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7622 11:32:42.777449 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7623 11:32:42.783598 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 11:32:42.787354 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 11:32:42.790658 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 11:32:42.797349 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7627 11:32:42.800509 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7628 11:32:42.804063 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7629 11:32:42.810027 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7630 11:32:42.813538 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 11:32:42.816591 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 11:32:42.823806 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 11:32:42.827244 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7634 11:32:42.830061 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7635 11:32:42.836424 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7636 11:32:42.839793 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7637 11:32:42.846448 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7638 11:32:42.849814 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:32:42.853280 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:32:42.859922 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 11:32:42.863023 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7642 11:32:42.866139 1 6 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7643 11:32:42.872493 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7644 11:32:42.876066 1 6 20 | B1->B0 | 2625 4646 | 1 0 | (0 0) (0 0)
7645 11:32:42.879200 1 6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7646 11:32:42.885832 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:32:42.889027 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:32:42.893084 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 11:32:42.899275 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 11:32:42.902316 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 11:32:42.905475 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7652 11:32:42.912385 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7653 11:32:42.915452 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 11:32:42.918856 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:32:42.925525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:32:42.928445 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:32:42.932175 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:32:42.938319 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:32:42.942167 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:32:42.945541 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:32:42.951679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:32:42.955075 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:32:42.958596 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:32:42.964741 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:32:42.968856 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7666 11:32:42.971722 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7667 11:32:42.978068 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7668 11:32:42.978144 Total UI for P1: 0, mck2ui 16
7669 11:32:42.981329 best dqsien dly found for B0: ( 1, 9, 10)
7670 11:32:42.987822 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7671 11:32:42.991346 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7672 11:32:42.998285 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 11:32:42.998368 Total UI for P1: 0, mck2ui 16
7674 11:32:43.001062 best dqsien dly found for B1: ( 1, 9, 22)
7675 11:32:43.007815 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7676 11:32:43.010813 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7677 11:32:43.010890
7678 11:32:43.014533 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7679 11:32:43.017812 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7680 11:32:43.020804 [Gating] SW calibration Done
7681 11:32:43.020882 ==
7682 11:32:43.024031 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 11:32:43.027939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 11:32:43.028017 ==
7685 11:32:43.030725 RX Vref Scan: 0
7686 11:32:43.030802
7687 11:32:43.030878 RX Vref 0 -> 0, step: 1
7688 11:32:43.030949
7689 11:32:43.034536 RX Delay 0 -> 252, step: 8
7690 11:32:43.037749 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7691 11:32:43.043852 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7692 11:32:43.047348 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7693 11:32:43.050443 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7694 11:32:43.053718 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7695 11:32:43.057203 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7696 11:32:43.063637 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7697 11:32:43.067219 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7698 11:32:43.070667 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7699 11:32:43.074058 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7700 11:32:43.077808 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7701 11:32:43.084051 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7702 11:32:43.087081 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7703 11:32:43.090263 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7704 11:32:43.093783 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7705 11:32:43.100209 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7706 11:32:43.100328 ==
7707 11:32:43.103799 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 11:32:43.106925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 11:32:43.107003 ==
7710 11:32:43.107079 DQS Delay:
7711 11:32:43.110163 DQS0 = 0, DQS1 = 0
7712 11:32:43.110239 DQM Delay:
7713 11:32:43.113180 DQM0 = 135, DQM1 = 125
7714 11:32:43.113244 DQ Delay:
7715 11:32:43.116797 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7716 11:32:43.119861 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7717 11:32:43.123076 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7718 11:32:43.126361 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7719 11:32:43.126449
7720 11:32:43.126536
7721 11:32:43.129788 ==
7722 11:32:43.133204 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:32:43.136508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:32:43.136589 ==
7725 11:32:43.136665
7726 11:32:43.136754
7727 11:32:43.140108 TX Vref Scan disable
7728 11:32:43.140185 == TX Byte 0 ==
7729 11:32:43.143241 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7730 11:32:43.149495 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 11:32:43.149581 == TX Byte 1 ==
7732 11:32:43.155996 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7733 11:32:43.159148 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7734 11:32:43.159226 ==
7735 11:32:43.162749 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 11:32:43.166036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 11:32:43.166114 ==
7738 11:32:43.180118
7739 11:32:43.183369 TX Vref early break, caculate TX vref
7740 11:32:43.186924 TX Vref=16, minBit 6, minWin=22, winSum=373
7741 11:32:43.189818 TX Vref=18, minBit 3, minWin=23, winSum=385
7742 11:32:43.193057 TX Vref=20, minBit 1, minWin=23, winSum=390
7743 11:32:43.196339 TX Vref=22, minBit 2, minWin=24, winSum=399
7744 11:32:43.199765 TX Vref=24, minBit 3, minWin=24, winSum=412
7745 11:32:43.206239 TX Vref=26, minBit 1, minWin=25, winSum=417
7746 11:32:43.210317 TX Vref=28, minBit 4, minWin=24, winSum=417
7747 11:32:43.212904 TX Vref=30, minBit 7, minWin=24, winSum=415
7748 11:32:43.216421 TX Vref=32, minBit 0, minWin=24, winSum=401
7749 11:32:43.219658 TX Vref=34, minBit 5, minWin=23, winSum=391
7750 11:32:43.225906 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
7751 11:32:43.225984
7752 11:32:43.229574 Final TX Range 0 Vref 26
7753 11:32:43.229660
7754 11:32:43.229736 ==
7755 11:32:43.232622 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 11:32:43.235903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 11:32:43.235988 ==
7758 11:32:43.236065
7759 11:32:43.236136
7760 11:32:43.239362 TX Vref Scan disable
7761 11:32:43.245890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7762 11:32:43.245968 == TX Byte 0 ==
7763 11:32:43.249108 u2DelayCellOfst[0]=14 cells (4 PI)
7764 11:32:43.252534 u2DelayCellOfst[1]=18 cells (5 PI)
7765 11:32:43.255891 u2DelayCellOfst[2]=14 cells (4 PI)
7766 11:32:43.259297 u2DelayCellOfst[3]=14 cells (4 PI)
7767 11:32:43.262390 u2DelayCellOfst[4]=11 cells (3 PI)
7768 11:32:43.265443 u2DelayCellOfst[5]=0 cells (0 PI)
7769 11:32:43.269182 u2DelayCellOfst[6]=22 cells (6 PI)
7770 11:32:43.272070 u2DelayCellOfst[7]=22 cells (6 PI)
7771 11:32:43.275895 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7772 11:32:43.278706 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7773 11:32:43.282395 == TX Byte 1 ==
7774 11:32:43.285042 u2DelayCellOfst[8]=0 cells (0 PI)
7775 11:32:43.288538 u2DelayCellOfst[9]=3 cells (1 PI)
7776 11:32:43.292214 u2DelayCellOfst[10]=7 cells (2 PI)
7777 11:32:43.295199 u2DelayCellOfst[11]=0 cells (0 PI)
7778 11:32:43.295277 u2DelayCellOfst[12]=11 cells (3 PI)
7779 11:32:43.298970 u2DelayCellOfst[13]=11 cells (3 PI)
7780 11:32:43.302014 u2DelayCellOfst[14]=14 cells (4 PI)
7781 11:32:43.305109 u2DelayCellOfst[15]=11 cells (3 PI)
7782 11:32:43.311741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7783 11:32:43.315022 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7784 11:32:43.315100 DramC Write-DBI on
7785 11:32:43.318658 ==
7786 11:32:43.321701 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 11:32:43.325152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 11:32:43.325227 ==
7789 11:32:43.325300
7790 11:32:43.325355
7791 11:32:43.328371 TX Vref Scan disable
7792 11:32:43.328435 == TX Byte 0 ==
7793 11:32:43.334748 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7794 11:32:43.334843 == TX Byte 1 ==
7795 11:32:43.338477 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7796 11:32:43.341526 DramC Write-DBI off
7797 11:32:43.341593
7798 11:32:43.341650 [DATLAT]
7799 11:32:43.344805 Freq=1600, CH0 RK0
7800 11:32:43.344867
7801 11:32:43.344918 DATLAT Default: 0xf
7802 11:32:43.348061 0, 0xFFFF, sum = 0
7803 11:32:43.348123 1, 0xFFFF, sum = 0
7804 11:32:43.351325 2, 0xFFFF, sum = 0
7805 11:32:43.354474 3, 0xFFFF, sum = 0
7806 11:32:43.354571 4, 0xFFFF, sum = 0
7807 11:32:43.357964 5, 0xFFFF, sum = 0
7808 11:32:43.358059 6, 0xFFFF, sum = 0
7809 11:32:43.361050 7, 0xFFFF, sum = 0
7810 11:32:43.361119 8, 0xFFFF, sum = 0
7811 11:32:43.364469 9, 0xFFFF, sum = 0
7812 11:32:43.364532 10, 0xFFFF, sum = 0
7813 11:32:43.367829 11, 0xFFFF, sum = 0
7814 11:32:43.367926 12, 0xFFFF, sum = 0
7815 11:32:43.371364 13, 0xFFFF, sum = 0
7816 11:32:43.371487 14, 0x0, sum = 1
7817 11:32:43.374337 15, 0x0, sum = 2
7818 11:32:43.374435 16, 0x0, sum = 3
7819 11:32:43.377536 17, 0x0, sum = 4
7820 11:32:43.377627 best_step = 15
7821 11:32:43.377714
7822 11:32:43.377783 ==
7823 11:32:43.380698 Dram Type= 6, Freq= 0, CH_0, rank 0
7824 11:32:43.387282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7825 11:32:43.387359 ==
7826 11:32:43.387488 RX Vref Scan: 1
7827 11:32:43.387561
7828 11:32:43.391137 Set Vref Range= 24 -> 127
7829 11:32:43.391214
7830 11:32:43.393950 RX Vref 24 -> 127, step: 1
7831 11:32:43.394027
7832 11:32:43.394104 RX Delay 11 -> 252, step: 4
7833 11:32:43.397599
7834 11:32:43.397676 Set Vref, RX VrefLevel [Byte0]: 24
7835 11:32:43.400461 [Byte1]: 24
7836 11:32:43.404949
7837 11:32:43.405025 Set Vref, RX VrefLevel [Byte0]: 25
7838 11:32:43.408187 [Byte1]: 25
7839 11:32:43.412413
7840 11:32:43.412489 Set Vref, RX VrefLevel [Byte0]: 26
7841 11:32:43.415698 [Byte1]: 26
7842 11:32:43.419826
7843 11:32:43.419910 Set Vref, RX VrefLevel [Byte0]: 27
7844 11:32:43.423656 [Byte1]: 27
7845 11:32:43.427533
7846 11:32:43.427626 Set Vref, RX VrefLevel [Byte0]: 28
7847 11:32:43.431028 [Byte1]: 28
7848 11:32:43.435884
7849 11:32:43.435982 Set Vref, RX VrefLevel [Byte0]: 29
7850 11:32:43.438752 [Byte1]: 29
7851 11:32:43.442854
7852 11:32:43.442944 Set Vref, RX VrefLevel [Byte0]: 30
7853 11:32:43.446438 [Byte1]: 30
7854 11:32:43.451039
7855 11:32:43.451113 Set Vref, RX VrefLevel [Byte0]: 31
7856 11:32:43.454137 [Byte1]: 31
7857 11:32:43.458014
7858 11:32:43.458088 Set Vref, RX VrefLevel [Byte0]: 32
7859 11:32:43.461304 [Byte1]: 32
7860 11:32:43.465846
7861 11:32:43.465919 Set Vref, RX VrefLevel [Byte0]: 33
7862 11:32:43.469274 [Byte1]: 33
7863 11:32:43.473412
7864 11:32:43.473485 Set Vref, RX VrefLevel [Byte0]: 34
7865 11:32:43.476482 [Byte1]: 34
7866 11:32:43.481256
7867 11:32:43.481330 Set Vref, RX VrefLevel [Byte0]: 35
7868 11:32:43.484187 [Byte1]: 35
7869 11:32:43.488443
7870 11:32:43.488516 Set Vref, RX VrefLevel [Byte0]: 36
7871 11:32:43.491756 [Byte1]: 36
7872 11:32:43.496232
7873 11:32:43.496305 Set Vref, RX VrefLevel [Byte0]: 37
7874 11:32:43.499391 [Byte1]: 37
7875 11:32:43.503631
7876 11:32:43.503704 Set Vref, RX VrefLevel [Byte0]: 38
7877 11:32:43.506943 [Byte1]: 38
7878 11:32:43.511312
7879 11:32:43.511385 Set Vref, RX VrefLevel [Byte0]: 39
7880 11:32:43.514901 [Byte1]: 39
7881 11:32:43.518802
7882 11:32:43.518902 Set Vref, RX VrefLevel [Byte0]: 40
7883 11:32:43.522163 [Byte1]: 40
7884 11:32:43.526429
7885 11:32:43.526497 Set Vref, RX VrefLevel [Byte0]: 41
7886 11:32:43.529771 [Byte1]: 41
7887 11:32:43.534137
7888 11:32:43.534207 Set Vref, RX VrefLevel [Byte0]: 42
7889 11:32:43.537769 [Byte1]: 42
7890 11:32:43.541796
7891 11:32:43.541870 Set Vref, RX VrefLevel [Byte0]: 43
7892 11:32:43.545336 [Byte1]: 43
7893 11:32:43.549573
7894 11:32:43.549647 Set Vref, RX VrefLevel [Byte0]: 44
7895 11:32:43.552874 [Byte1]: 44
7896 11:32:43.557167
7897 11:32:43.557241 Set Vref, RX VrefLevel [Byte0]: 45
7898 11:32:43.560665 [Byte1]: 45
7899 11:32:43.564978
7900 11:32:43.565053 Set Vref, RX VrefLevel [Byte0]: 46
7901 11:32:43.568254 [Byte1]: 46
7902 11:32:43.572200
7903 11:32:43.572274 Set Vref, RX VrefLevel [Byte0]: 47
7904 11:32:43.575540 [Byte1]: 47
7905 11:32:43.579866
7906 11:32:43.579940 Set Vref, RX VrefLevel [Byte0]: 48
7907 11:32:43.583319 [Byte1]: 48
7908 11:32:43.587889
7909 11:32:43.587964 Set Vref, RX VrefLevel [Byte0]: 49
7910 11:32:43.590995 [Byte1]: 49
7911 11:32:43.595091
7912 11:32:43.595203 Set Vref, RX VrefLevel [Byte0]: 50
7913 11:32:43.598470 [Byte1]: 50
7914 11:32:43.602946
7915 11:32:43.603019 Set Vref, RX VrefLevel [Byte0]: 51
7916 11:32:43.605866 [Byte1]: 51
7917 11:32:43.610247
7918 11:32:43.610321 Set Vref, RX VrefLevel [Byte0]: 52
7919 11:32:43.613965 [Byte1]: 52
7920 11:32:43.617976
7921 11:32:43.618049 Set Vref, RX VrefLevel [Byte0]: 53
7922 11:32:43.621080 [Byte1]: 53
7923 11:32:43.625687
7924 11:32:43.625761 Set Vref, RX VrefLevel [Byte0]: 54
7925 11:32:43.629119 [Byte1]: 54
7926 11:32:43.633406
7927 11:32:43.633481 Set Vref, RX VrefLevel [Byte0]: 55
7928 11:32:43.636405 [Byte1]: 55
7929 11:32:43.640973
7930 11:32:43.641047 Set Vref, RX VrefLevel [Byte0]: 56
7931 11:32:43.644222 [Byte1]: 56
7932 11:32:43.648802
7933 11:32:43.648877 Set Vref, RX VrefLevel [Byte0]: 57
7934 11:32:43.651941 [Byte1]: 57
7935 11:32:43.656134
7936 11:32:43.656208 Set Vref, RX VrefLevel [Byte0]: 58
7937 11:32:43.659369 [Byte1]: 58
7938 11:32:43.663374
7939 11:32:43.663502 Set Vref, RX VrefLevel [Byte0]: 59
7940 11:32:43.666731 [Byte1]: 59
7941 11:32:43.671265
7942 11:32:43.671339 Set Vref, RX VrefLevel [Byte0]: 60
7943 11:32:43.674875 [Byte1]: 60
7944 11:32:43.678694
7945 11:32:43.678821 Set Vref, RX VrefLevel [Byte0]: 61
7946 11:32:43.682410 [Byte1]: 61
7947 11:32:43.686455
7948 11:32:43.686530 Set Vref, RX VrefLevel [Byte0]: 62
7949 11:32:43.689597 [Byte1]: 62
7950 11:32:43.694162
7951 11:32:43.694240 Set Vref, RX VrefLevel [Byte0]: 63
7952 11:32:43.697340 [Byte1]: 63
7953 11:32:43.701718
7954 11:32:43.701792 Set Vref, RX VrefLevel [Byte0]: 64
7955 11:32:43.704933 [Byte1]: 64
7956 11:32:43.709705
7957 11:32:43.709779 Set Vref, RX VrefLevel [Byte0]: 65
7958 11:32:43.712789 [Byte1]: 65
7959 11:32:43.716928
7960 11:32:43.717002 Set Vref, RX VrefLevel [Byte0]: 66
7961 11:32:43.720033 [Byte1]: 66
7962 11:32:43.724527
7963 11:32:43.724602 Set Vref, RX VrefLevel [Byte0]: 67
7964 11:32:43.728014 [Byte1]: 67
7965 11:32:43.731837
7966 11:32:43.731913 Set Vref, RX VrefLevel [Byte0]: 68
7967 11:32:43.735201 [Byte1]: 68
7968 11:32:43.739854
7969 11:32:43.739928 Set Vref, RX VrefLevel [Byte0]: 69
7970 11:32:43.742891 [Byte1]: 69
7971 11:32:43.747398
7972 11:32:43.747503 Set Vref, RX VrefLevel [Byte0]: 70
7973 11:32:43.750538 [Byte1]: 70
7974 11:32:43.754862
7975 11:32:43.754937 Set Vref, RX VrefLevel [Byte0]: 71
7976 11:32:43.758710 [Byte1]: 71
7977 11:32:43.762587
7978 11:32:43.762661 Set Vref, RX VrefLevel [Byte0]: 72
7979 11:32:43.765987 [Byte1]: 72
7980 11:32:43.770296
7981 11:32:43.770371 Set Vref, RX VrefLevel [Byte0]: 73
7982 11:32:43.773338 [Byte1]: 73
7983 11:32:43.778211
7984 11:32:43.778285 Set Vref, RX VrefLevel [Byte0]: 74
7985 11:32:43.781526 [Byte1]: 74
7986 11:32:43.785330
7987 11:32:43.785404 Set Vref, RX VrefLevel [Byte0]: 75
7988 11:32:43.789054 [Byte1]: 75
7989 11:32:43.792983
7990 11:32:43.793057 Set Vref, RX VrefLevel [Byte0]: 76
7991 11:32:43.796685 [Byte1]: 76
7992 11:32:43.800869
7993 11:32:43.800944 Set Vref, RX VrefLevel [Byte0]: 77
7994 11:32:43.804011 [Byte1]: 77
7995 11:32:43.808215
7996 11:32:43.808289 Set Vref, RX VrefLevel [Byte0]: 78
7997 11:32:43.811664 [Byte1]: 78
7998 11:32:43.815953
7999 11:32:43.816028 Set Vref, RX VrefLevel [Byte0]: 79
8000 11:32:43.819370 [Byte1]: 79
8001 11:32:43.823841
8002 11:32:43.823915 Final RX Vref Byte 0 = 64 to rank0
8003 11:32:43.826900 Final RX Vref Byte 1 = 58 to rank0
8004 11:32:43.829972 Final RX Vref Byte 0 = 64 to rank1
8005 11:32:43.833662 Final RX Vref Byte 1 = 58 to rank1==
8006 11:32:43.836457 Dram Type= 6, Freq= 0, CH_0, rank 0
8007 11:32:43.843099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 11:32:43.843174 ==
8009 11:32:43.843259 DQS Delay:
8010 11:32:43.846143 DQS0 = 0, DQS1 = 0
8011 11:32:43.846212 DQM Delay:
8012 11:32:43.849899 DQM0 = 133, DQM1 = 122
8013 11:32:43.849990 DQ Delay:
8014 11:32:43.852815 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8015 11:32:43.856236 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8016 11:32:43.859725 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =116
8017 11:32:43.862964 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =128
8018 11:32:43.863054
8019 11:32:43.863112
8020 11:32:43.863195
8021 11:32:43.865843 [DramC_TX_OE_Calibration] TA2
8022 11:32:43.869505 Original DQ_B0 (3 6) =30, OEN = 27
8023 11:32:43.872824 Original DQ_B1 (3 6) =30, OEN = 27
8024 11:32:43.875727 24, 0x0, End_B0=24 End_B1=24
8025 11:32:43.879089 25, 0x0, End_B0=25 End_B1=25
8026 11:32:43.879204 26, 0x0, End_B0=26 End_B1=26
8027 11:32:43.882723 27, 0x0, End_B0=27 End_B1=27
8028 11:32:43.886483 28, 0x0, End_B0=28 End_B1=28
8029 11:32:43.888962 29, 0x0, End_B0=29 End_B1=29
8030 11:32:43.892499 30, 0x0, End_B0=30 End_B1=30
8031 11:32:43.892577 31, 0x4141, End_B0=30 End_B1=30
8032 11:32:43.896810 Byte0 end_step=30 best_step=27
8033 11:32:43.899563 Byte1 end_step=30 best_step=27
8034 11:32:43.902920 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 11:32:43.905243 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 11:32:43.905313
8037 11:32:43.905370
8038 11:32:43.911976 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8039 11:32:43.915455 CH0 RK0: MR19=303, MR18=2415
8040 11:32:43.921995 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8041 11:32:43.922077
8042 11:32:43.925533 ----->DramcWriteLeveling(PI) begin...
8043 11:32:43.925610 ==
8044 11:32:43.928406 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 11:32:43.931884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 11:32:43.931974 ==
8047 11:32:43.935337 Write leveling (Byte 0): 38 => 38
8048 11:32:43.938605 Write leveling (Byte 1): 28 => 28
8049 11:32:43.942220 DramcWriteLeveling(PI) end<-----
8050 11:32:43.942327
8051 11:32:43.942423 ==
8052 11:32:43.944870 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 11:32:43.951649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 11:32:43.951727 ==
8055 11:32:43.951794 [Gating] SW mode calibration
8056 11:32:43.961696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8057 11:32:43.965112 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8058 11:32:43.971871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 11:32:43.974809 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 11:32:43.978223 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 11:32:43.984976 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 11:32:43.987629 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8063 11:32:43.990925 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8064 11:32:43.998059 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:32:44.001658 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 11:32:44.004457 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:32:44.011122 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:32:44.014086 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 11:32:44.017393 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 1)
8070 11:32:44.024095 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 1)
8071 11:32:44.028087 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8072 11:32:44.030726 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:32:44.036984 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:32:44.040473 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:32:44.044000 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:32:44.050590 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:32:44.054197 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8078 11:32:44.057202 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8079 11:32:44.063448 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8080 11:32:44.066979 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:32:44.070080 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 11:32:44.076869 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:32:44.079920 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:32:44.083499 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 11:32:44.090110 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 11:32:44.093629 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 11:32:44.096451 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 11:32:44.102994 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:32:44.106799 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:32:44.109570 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:32:44.116870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:32:44.119751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:32:44.123079 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:32:44.129909 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:32:44.132615 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:32:44.136511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:32:44.142758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:32:44.145746 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:32:44.149257 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:32:44.155847 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 11:32:44.158957 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8102 11:32:44.162353 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 11:32:44.166015 Total UI for P1: 0, mck2ui 16
8104 11:32:44.169143 best dqsien dly found for B0: ( 1, 9, 10)
8105 11:32:44.175707 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 11:32:44.179046 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 11:32:44.182222 Total UI for P1: 0, mck2ui 16
8108 11:32:44.185406 best dqsien dly found for B1: ( 1, 9, 18)
8109 11:32:44.189118 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8110 11:32:44.192137 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8111 11:32:44.192211
8112 11:32:44.195623 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8113 11:32:44.199092 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8114 11:32:44.201971 [Gating] SW calibration Done
8115 11:32:44.202045 ==
8116 11:32:44.206204 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 11:32:44.211871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 11:32:44.211946 ==
8119 11:32:44.212004 RX Vref Scan: 0
8120 11:32:44.212057
8121 11:32:44.215706 RX Vref 0 -> 0, step: 1
8122 11:32:44.215780
8123 11:32:44.218529 RX Delay 0 -> 252, step: 8
8124 11:32:44.221780 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8125 11:32:44.225133 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8126 11:32:44.228605 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8127 11:32:44.231920 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8128 11:32:44.238201 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8129 11:32:44.242598 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8130 11:32:44.245047 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8131 11:32:44.248241 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8132 11:32:44.251701 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8133 11:32:44.258358 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8134 11:32:44.261549 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8135 11:32:44.264997 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8136 11:32:44.268117 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8137 11:32:44.271302 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8138 11:32:44.278263 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8139 11:32:44.281693 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 11:32:44.281767 ==
8141 11:32:44.284527 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 11:32:44.287777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 11:32:44.287853 ==
8144 11:32:44.291271 DQS Delay:
8145 11:32:44.291346 DQS0 = 0, DQS1 = 0
8146 11:32:44.291404 DQM Delay:
8147 11:32:44.294721 DQM0 = 132, DQM1 = 129
8148 11:32:44.294796 DQ Delay:
8149 11:32:44.297876 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8150 11:32:44.304122 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8151 11:32:44.307728 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8152 11:32:44.310760 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8153 11:32:44.310835
8154 11:32:44.310893
8155 11:32:44.310947 ==
8156 11:32:44.314185 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 11:32:44.317334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 11:32:44.317410 ==
8159 11:32:44.317467
8160 11:32:44.317520
8161 11:32:44.321025 TX Vref Scan disable
8162 11:32:44.324087 == TX Byte 0 ==
8163 11:32:44.327239 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8164 11:32:44.330987 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8165 11:32:44.333713 == TX Byte 1 ==
8166 11:32:44.337196 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8167 11:32:44.340510 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8168 11:32:44.340586 ==
8169 11:32:44.344126 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 11:32:44.350727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 11:32:44.350814 ==
8172 11:32:44.362931
8173 11:32:44.366298 TX Vref early break, caculate TX vref
8174 11:32:44.369432 TX Vref=16, minBit 5, minWin=22, winSum=380
8175 11:32:44.372837 TX Vref=18, minBit 1, minWin=23, winSum=386
8176 11:32:44.377626 TX Vref=20, minBit 2, minWin=23, winSum=394
8177 11:32:44.379735 TX Vref=22, minBit 1, minWin=24, winSum=404
8178 11:32:44.382969 TX Vref=24, minBit 0, minWin=24, winSum=415
8179 11:32:44.389745 TX Vref=26, minBit 0, minWin=25, winSum=414
8180 11:32:44.392718 TX Vref=28, minBit 1, minWin=24, winSum=410
8181 11:32:44.396145 TX Vref=30, minBit 0, minWin=24, winSum=405
8182 11:32:44.399328 TX Vref=32, minBit 0, minWin=24, winSum=397
8183 11:32:44.402246 TX Vref=34, minBit 0, minWin=24, winSum=390
8184 11:32:44.409606 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8185 11:32:44.409682
8186 11:32:44.412475 Final TX Range 0 Vref 26
8187 11:32:44.412552
8188 11:32:44.412611 ==
8189 11:32:44.415809 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:32:44.419027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:32:44.419141 ==
8192 11:32:44.419199
8193 11:32:44.419269
8194 11:32:44.422326 TX Vref Scan disable
8195 11:32:44.428877 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8196 11:32:44.428955 == TX Byte 0 ==
8197 11:32:44.432413 u2DelayCellOfst[0]=11 cells (3 PI)
8198 11:32:44.435415 u2DelayCellOfst[1]=14 cells (4 PI)
8199 11:32:44.439000 u2DelayCellOfst[2]=11 cells (3 PI)
8200 11:32:44.442148 u2DelayCellOfst[3]=11 cells (3 PI)
8201 11:32:44.445785 u2DelayCellOfst[4]=7 cells (2 PI)
8202 11:32:44.448779 u2DelayCellOfst[5]=0 cells (0 PI)
8203 11:32:44.451963 u2DelayCellOfst[6]=14 cells (4 PI)
8204 11:32:44.455559 u2DelayCellOfst[7]=18 cells (5 PI)
8205 11:32:44.459241 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8206 11:32:44.462040 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8207 11:32:44.465066 == TX Byte 1 ==
8208 11:32:44.468372 u2DelayCellOfst[8]=0 cells (0 PI)
8209 11:32:44.471852 u2DelayCellOfst[9]=3 cells (1 PI)
8210 11:32:44.474926 u2DelayCellOfst[10]=7 cells (2 PI)
8211 11:32:44.475018 u2DelayCellOfst[11]=3 cells (1 PI)
8212 11:32:44.478274 u2DelayCellOfst[12]=14 cells (4 PI)
8213 11:32:44.481374 u2DelayCellOfst[13]=14 cells (4 PI)
8214 11:32:44.484821 u2DelayCellOfst[14]=18 cells (5 PI)
8215 11:32:44.488458 u2DelayCellOfst[15]=11 cells (3 PI)
8216 11:32:44.495140 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8217 11:32:44.498131 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8218 11:32:44.498230 DramC Write-DBI on
8219 11:32:44.501456 ==
8220 11:32:44.501534 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 11:32:44.507835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 11:32:44.507911 ==
8223 11:32:44.507969
8224 11:32:44.508022
8225 11:32:44.511230 TX Vref Scan disable
8226 11:32:44.511327 == TX Byte 0 ==
8227 11:32:44.518152 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8228 11:32:44.518227 == TX Byte 1 ==
8229 11:32:44.521282 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8230 11:32:44.524653 DramC Write-DBI off
8231 11:32:44.524728
8232 11:32:44.524785 [DATLAT]
8233 11:32:44.528171 Freq=1600, CH0 RK1
8234 11:32:44.528246
8235 11:32:44.528304 DATLAT Default: 0xf
8236 11:32:44.531356 0, 0xFFFF, sum = 0
8237 11:32:44.531485 1, 0xFFFF, sum = 0
8238 11:32:44.534351 2, 0xFFFF, sum = 0
8239 11:32:44.534427 3, 0xFFFF, sum = 0
8240 11:32:44.537542 4, 0xFFFF, sum = 0
8241 11:32:44.537621 5, 0xFFFF, sum = 0
8242 11:32:44.541088 6, 0xFFFF, sum = 0
8243 11:32:44.544091 7, 0xFFFF, sum = 0
8244 11:32:44.544193 8, 0xFFFF, sum = 0
8245 11:32:44.547616 9, 0xFFFF, sum = 0
8246 11:32:44.547746 10, 0xFFFF, sum = 0
8247 11:32:44.550893 11, 0xFFFF, sum = 0
8248 11:32:44.550969 12, 0xFFFF, sum = 0
8249 11:32:44.554071 13, 0xFFFF, sum = 0
8250 11:32:44.554149 14, 0x0, sum = 1
8251 11:32:44.557585 15, 0x0, sum = 2
8252 11:32:44.557685 16, 0x0, sum = 3
8253 11:32:44.560692 17, 0x0, sum = 4
8254 11:32:44.560781 best_step = 15
8255 11:32:44.560840
8256 11:32:44.560927 ==
8257 11:32:44.564211 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 11:32:44.567200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:32:44.570705 ==
8260 11:32:44.570806 RX Vref Scan: 0
8261 11:32:44.570909
8262 11:32:44.574125 RX Vref 0 -> 0, step: 1
8263 11:32:44.574215
8264 11:32:44.577329 RX Delay 11 -> 252, step: 4
8265 11:32:44.580543 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8266 11:32:44.584358 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8267 11:32:44.587287 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8268 11:32:44.593915 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8269 11:32:44.597173 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8270 11:32:44.600265 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8271 11:32:44.603929 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8272 11:32:44.606959 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8273 11:32:44.613442 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8274 11:32:44.617131 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8275 11:32:44.620128 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8276 11:32:44.623754 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8277 11:32:44.626685 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8278 11:32:44.633462 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8279 11:32:44.636530 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8280 11:32:44.640106 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8281 11:32:44.640184 ==
8282 11:32:44.643279 Dram Type= 6, Freq= 0, CH_0, rank 1
8283 11:32:44.649887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:32:44.649965 ==
8285 11:32:44.650042 DQS Delay:
8286 11:32:44.650113 DQS0 = 0, DQS1 = 0
8287 11:32:44.652906 DQM Delay:
8288 11:32:44.653016 DQM0 = 130, DQM1 = 125
8289 11:32:44.656507 DQ Delay:
8290 11:32:44.659513 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8291 11:32:44.662675 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8292 11:32:44.666022 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8293 11:32:44.669641 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8294 11:32:44.669717
8295 11:32:44.669773
8296 11:32:44.669827
8297 11:32:44.672504 [DramC_TX_OE_Calibration] TA2
8298 11:32:44.676256 Original DQ_B0 (3 6) =30, OEN = 27
8299 11:32:44.679301 Original DQ_B1 (3 6) =30, OEN = 27
8300 11:32:44.682527 24, 0x0, End_B0=24 End_B1=24
8301 11:32:44.682603 25, 0x0, End_B0=25 End_B1=25
8302 11:32:44.685969 26, 0x0, End_B0=26 End_B1=26
8303 11:32:44.689228 27, 0x0, End_B0=27 End_B1=27
8304 11:32:44.692783 28, 0x0, End_B0=28 End_B1=28
8305 11:32:44.695880 29, 0x0, End_B0=29 End_B1=29
8306 11:32:44.695954 30, 0x0, End_B0=30 End_B1=30
8307 11:32:44.699441 31, 0x4141, End_B0=30 End_B1=30
8308 11:32:44.702889 Byte0 end_step=30 best_step=27
8309 11:32:44.705973 Byte1 end_step=30 best_step=27
8310 11:32:44.709115 Byte0 TX OE(2T, 0.5T) = (3, 3)
8311 11:32:44.712217 Byte1 TX OE(2T, 0.5T) = (3, 3)
8312 11:32:44.712292
8313 11:32:44.712349
8314 11:32:44.719080 [DQSOSCAuto] RK1, (LSB)MR18= 0x2204, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 392 ps
8315 11:32:44.722536 CH0 RK1: MR19=303, MR18=2204
8316 11:32:44.728697 CH0_RK1: MR19=0x303, MR18=0x2204, DQSOSC=392, MR23=63, INC=24, DEC=16
8317 11:32:44.732141 [RxdqsGatingPostProcess] freq 1600
8318 11:32:44.739168 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8319 11:32:44.739244 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 11:32:44.742112 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 11:32:44.745298 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 11:32:44.748350 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 11:32:44.752089 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 11:32:44.755097 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 11:32:44.758669 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 11:32:44.761964 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 11:32:44.765060 Pre-setting of DQS Precalculation
8328 11:32:44.768630 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8329 11:32:44.768705 ==
8330 11:32:44.771549 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 11:32:44.778218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:32:44.778293 ==
8333 11:32:44.781425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 11:32:44.788267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 11:32:44.791650 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 11:32:44.798312 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 11:32:44.805671 [CA 0] Center 41 (12~71) winsize 60
8338 11:32:44.809219 [CA 1] Center 42 (12~72) winsize 61
8339 11:32:44.812312 [CA 2] Center 37 (8~66) winsize 59
8340 11:32:44.815703 [CA 3] Center 36 (7~65) winsize 59
8341 11:32:44.818884 [CA 4] Center 37 (8~66) winsize 59
8342 11:32:44.822173 [CA 5] Center 36 (7~66) winsize 60
8343 11:32:44.822247
8344 11:32:44.825831 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 11:32:44.825905
8346 11:32:44.828824 [CATrainingPosCal] consider 1 rank data
8347 11:32:44.832336 u2DelayCellTimex100 = 262/100 ps
8348 11:32:44.838787 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8349 11:32:44.842249 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8350 11:32:44.845297 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8351 11:32:44.848632 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8352 11:32:44.851986 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8353 11:32:44.855661 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8354 11:32:44.855736
8355 11:32:44.858281 CA PerBit enable=1, Macro0, CA PI delay=36
8356 11:32:44.858356
8357 11:32:44.862112 [CBTSetCACLKResult] CA Dly = 36
8358 11:32:44.864935 CS Dly: 10 (0~41)
8359 11:32:44.868264 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 11:32:44.871859 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 11:32:44.871934 ==
8362 11:32:44.874719 Dram Type= 6, Freq= 0, CH_1, rank 1
8363 11:32:44.881589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 11:32:44.881665 ==
8365 11:32:44.884877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8366 11:32:44.891383 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8367 11:32:44.895284 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8368 11:32:44.901153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8369 11:32:44.909080 [CA 0] Center 41 (12~71) winsize 60
8370 11:32:44.912516 [CA 1] Center 42 (13~72) winsize 60
8371 11:32:44.915402 [CA 2] Center 37 (8~67) winsize 60
8372 11:32:44.918983 [CA 3] Center 36 (7~66) winsize 60
8373 11:32:44.922581 [CA 4] Center 37 (8~67) winsize 60
8374 11:32:44.925622 [CA 5] Center 37 (8~67) winsize 60
8375 11:32:44.925697
8376 11:32:44.928651 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8377 11:32:44.928726
8378 11:32:44.935415 [CATrainingPosCal] consider 2 rank data
8379 11:32:44.935530 u2DelayCellTimex100 = 262/100 ps
8380 11:32:44.941786 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8381 11:32:44.945336 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8382 11:32:44.948288 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8383 11:32:44.951851 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8384 11:32:44.955320 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8385 11:32:44.958634 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8386 11:32:44.958709
8387 11:32:44.961618 CA PerBit enable=1, Macro0, CA PI delay=36
8388 11:32:44.961692
8389 11:32:44.965362 [CBTSetCACLKResult] CA Dly = 36
8390 11:32:44.968530 CS Dly: 11 (0~43)
8391 11:32:44.971632 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8392 11:32:44.975383 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8393 11:32:44.975494
8394 11:32:44.978112 ----->DramcWriteLeveling(PI) begin...
8395 11:32:44.978235 ==
8396 11:32:44.981421 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:32:44.988088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:32:44.988165 ==
8399 11:32:44.991509 Write leveling (Byte 0): 24 => 24
8400 11:32:44.994987 Write leveling (Byte 1): 26 => 26
8401 11:32:44.995062 DramcWriteLeveling(PI) end<-----
8402 11:32:44.998171
8403 11:32:44.998246 ==
8404 11:32:45.001287 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 11:32:45.004635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 11:32:45.004710 ==
8407 11:32:45.008348 [Gating] SW mode calibration
8408 11:32:45.014068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8409 11:32:45.020916 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8410 11:32:45.024059 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 11:32:45.027353 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 11:32:45.033758 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 11:32:45.037004 1 4 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
8414 11:32:45.040494 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:32:45.047199 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:32:45.050749 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:32:45.053652 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:32:45.060229 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:32:45.063421 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:32:45.067018 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8421 11:32:45.073258 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (1 0) (1 0)
8422 11:32:45.076570 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8423 11:32:45.079928 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:32:45.086344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:32:45.089686 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:32:45.093277 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:32:45.099692 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:32:45.102734 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:32:45.106299 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8430 11:32:45.112986 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:32:45.115860 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:32:45.119355 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:32:45.125815 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:32:45.129318 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:32:45.132788 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:32:45.139581 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:32:45.142933 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8438 11:32:45.145959 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8439 11:32:45.152410 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:32:45.155895 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:32:45.158747 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:32:45.165422 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:32:45.168842 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:32:45.172270 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:32:45.179036 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:32:45.182068 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:32:45.185226 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:32:45.192165 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:32:45.195252 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:32:45.198754 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:32:45.205335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:32:45.208565 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8453 11:32:45.212023 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8454 11:32:45.218392 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8455 11:32:45.218467 Total UI for P1: 0, mck2ui 16
8456 11:32:45.224880 best dqsien dly found for B0: ( 1, 9, 10)
8457 11:32:45.228663 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 11:32:45.231734 Total UI for P1: 0, mck2ui 16
8459 11:32:45.234973 best dqsien dly found for B1: ( 1, 9, 12)
8460 11:32:45.238054 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8461 11:32:45.241587 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8462 11:32:45.241690
8463 11:32:45.244900 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8464 11:32:45.248306 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8465 11:32:45.251601 [Gating] SW calibration Done
8466 11:32:45.251690 ==
8467 11:32:45.254877 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 11:32:45.258429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 11:32:45.261675 ==
8470 11:32:45.261769 RX Vref Scan: 0
8471 11:32:45.261852
8472 11:32:45.264947 RX Vref 0 -> 0, step: 1
8473 11:32:45.265038
8474 11:32:45.265120 RX Delay 0 -> 252, step: 8
8475 11:32:45.271613 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8476 11:32:45.275034 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8477 11:32:45.278238 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8478 11:32:45.282030 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8479 11:32:45.284545 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8480 11:32:45.291683 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8481 11:32:45.294430 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8482 11:32:45.297742 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8483 11:32:45.301303 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8484 11:32:45.304489 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8485 11:32:45.311332 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8486 11:32:45.314386 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8487 11:32:45.317796 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8488 11:32:45.321025 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8489 11:32:45.327818 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8490 11:32:45.331042 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8491 11:32:45.331108 ==
8492 11:32:45.334544 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:32:45.337654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:32:45.337744 ==
8495 11:32:45.341205 DQS Delay:
8496 11:32:45.341292 DQS0 = 0, DQS1 = 0
8497 11:32:45.341370 DQM Delay:
8498 11:32:45.344435 DQM0 = 138, DQM1 = 130
8499 11:32:45.344511 DQ Delay:
8500 11:32:45.347593 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8501 11:32:45.350973 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8502 11:32:45.357253 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8503 11:32:45.360389 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8504 11:32:45.360464
8505 11:32:45.360522
8506 11:32:45.360576 ==
8507 11:32:45.363836 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 11:32:45.367366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 11:32:45.367502 ==
8510 11:32:45.367577
8511 11:32:45.367657
8512 11:32:45.370331 TX Vref Scan disable
8513 11:32:45.373745 == TX Byte 0 ==
8514 11:32:45.376924 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8515 11:32:45.380469 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 11:32:45.383857 == TX Byte 1 ==
8517 11:32:45.386769 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 11:32:45.390192 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8519 11:32:45.390268 ==
8520 11:32:45.393736 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:32:45.397108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 11:32:45.400052 ==
8523 11:32:45.411005
8524 11:32:45.414433 TX Vref early break, caculate TX vref
8525 11:32:45.418049 TX Vref=16, minBit 0, minWin=21, winSum=377
8526 11:32:45.421045 TX Vref=18, minBit 5, minWin=22, winSum=388
8527 11:32:45.423953 TX Vref=20, minBit 5, minWin=23, winSum=396
8528 11:32:45.427591 TX Vref=22, minBit 5, minWin=23, winSum=404
8529 11:32:45.430858 TX Vref=24, minBit 5, minWin=24, winSum=414
8530 11:32:45.437406 TX Vref=26, minBit 5, minWin=24, winSum=416
8531 11:32:45.440914 TX Vref=28, minBit 0, minWin=25, winSum=422
8532 11:32:45.444141 TX Vref=30, minBit 1, minWin=25, winSum=417
8533 11:32:45.447294 TX Vref=32, minBit 1, minWin=23, winSum=402
8534 11:32:45.450295 TX Vref=34, minBit 0, minWin=23, winSum=395
8535 11:32:45.457214 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8536 11:32:45.457310
8537 11:32:45.460428 Final TX Range 0 Vref 28
8538 11:32:45.460496
8539 11:32:45.460566 ==
8540 11:32:45.463673 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 11:32:45.466973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 11:32:45.467070 ==
8543 11:32:45.467152
8544 11:32:45.467230
8545 11:32:45.470021 TX Vref Scan disable
8546 11:32:45.476561 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8547 11:32:45.476632 == TX Byte 0 ==
8548 11:32:45.480048 u2DelayCellOfst[0]=18 cells (5 PI)
8549 11:32:45.483736 u2DelayCellOfst[1]=11 cells (3 PI)
8550 11:32:45.486729 u2DelayCellOfst[2]=0 cells (0 PI)
8551 11:32:45.490121 u2DelayCellOfst[3]=7 cells (2 PI)
8552 11:32:45.493174 u2DelayCellOfst[4]=7 cells (2 PI)
8553 11:32:45.496509 u2DelayCellOfst[5]=22 cells (6 PI)
8554 11:32:45.499596 u2DelayCellOfst[6]=18 cells (5 PI)
8555 11:32:45.503322 u2DelayCellOfst[7]=7 cells (2 PI)
8556 11:32:45.506394 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8557 11:32:45.509396 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8558 11:32:45.512894 == TX Byte 1 ==
8559 11:32:45.516067 u2DelayCellOfst[8]=0 cells (0 PI)
8560 11:32:45.519429 u2DelayCellOfst[9]=3 cells (1 PI)
8561 11:32:45.522398 u2DelayCellOfst[10]=14 cells (4 PI)
8562 11:32:45.525747 u2DelayCellOfst[11]=3 cells (1 PI)
8563 11:32:45.528964 u2DelayCellOfst[12]=14 cells (4 PI)
8564 11:32:45.529030 u2DelayCellOfst[13]=18 cells (5 PI)
8565 11:32:45.532281 u2DelayCellOfst[14]=18 cells (5 PI)
8566 11:32:45.535801 u2DelayCellOfst[15]=18 cells (5 PI)
8567 11:32:45.542292 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8568 11:32:45.545853 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8569 11:32:45.548649 DramC Write-DBI on
8570 11:32:45.548725 ==
8571 11:32:45.551981 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 11:32:45.555560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 11:32:45.555650 ==
8574 11:32:45.555731
8575 11:32:45.555818
8576 11:32:45.558926 TX Vref Scan disable
8577 11:32:45.559018 == TX Byte 0 ==
8578 11:32:45.565313 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8579 11:32:45.565378 == TX Byte 1 ==
8580 11:32:45.569028 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8581 11:32:45.571789 DramC Write-DBI off
8582 11:32:45.571850
8583 11:32:45.571902 [DATLAT]
8584 11:32:45.575268 Freq=1600, CH1 RK0
8585 11:32:45.575351
8586 11:32:45.575434 DATLAT Default: 0xf
8587 11:32:45.578401 0, 0xFFFF, sum = 0
8588 11:32:45.578486 1, 0xFFFF, sum = 0
8589 11:32:45.581973 2, 0xFFFF, sum = 0
8590 11:32:45.585068 3, 0xFFFF, sum = 0
8591 11:32:45.585149 4, 0xFFFF, sum = 0
8592 11:32:45.588779 5, 0xFFFF, sum = 0
8593 11:32:45.588856 6, 0xFFFF, sum = 0
8594 11:32:45.591615 7, 0xFFFF, sum = 0
8595 11:32:45.591691 8, 0xFFFF, sum = 0
8596 11:32:45.594817 9, 0xFFFF, sum = 0
8597 11:32:45.594927 10, 0xFFFF, sum = 0
8598 11:32:45.598246 11, 0xFFFF, sum = 0
8599 11:32:45.598324 12, 0xFFFF, sum = 0
8600 11:32:45.601542 13, 0xFFFF, sum = 0
8601 11:32:45.601610 14, 0x0, sum = 1
8602 11:32:45.604811 15, 0x0, sum = 2
8603 11:32:45.604903 16, 0x0, sum = 3
8604 11:32:45.608142 17, 0x0, sum = 4
8605 11:32:45.608210 best_step = 15
8606 11:32:45.608265
8607 11:32:45.608317 ==
8608 11:32:45.611537 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 11:32:45.618240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 11:32:45.618312 ==
8611 11:32:45.618371 RX Vref Scan: 1
8612 11:32:45.618436
8613 11:32:45.621288 Set Vref Range= 24 -> 127
8614 11:32:45.621357
8615 11:32:45.624318 RX Vref 24 -> 127, step: 1
8616 11:32:45.624393
8617 11:32:45.624452 RX Delay 11 -> 252, step: 4
8618 11:32:45.627820
8619 11:32:45.627889 Set Vref, RX VrefLevel [Byte0]: 24
8620 11:32:45.631146 [Byte1]: 24
8621 11:32:45.635276
8622 11:32:45.635341 Set Vref, RX VrefLevel [Byte0]: 25
8623 11:32:45.638829 [Byte1]: 25
8624 11:32:45.643141
8625 11:32:45.643204 Set Vref, RX VrefLevel [Byte0]: 26
8626 11:32:45.646461 [Byte1]: 26
8627 11:32:45.650679
8628 11:32:45.650765 Set Vref, RX VrefLevel [Byte0]: 27
8629 11:32:45.653923 [Byte1]: 27
8630 11:32:45.658136
8631 11:32:45.658211 Set Vref, RX VrefLevel [Byte0]: 28
8632 11:32:45.661392 [Byte1]: 28
8633 11:32:45.665668
8634 11:32:45.665746 Set Vref, RX VrefLevel [Byte0]: 29
8635 11:32:45.669190 [Byte1]: 29
8636 11:32:45.673691
8637 11:32:45.673787 Set Vref, RX VrefLevel [Byte0]: 30
8638 11:32:45.676585 [Byte1]: 30
8639 11:32:45.681006
8640 11:32:45.681096 Set Vref, RX VrefLevel [Byte0]: 31
8641 11:32:45.684328 [Byte1]: 31
8642 11:32:45.688491
8643 11:32:45.688560 Set Vref, RX VrefLevel [Byte0]: 32
8644 11:32:45.691931 [Byte1]: 32
8645 11:32:45.696277
8646 11:32:45.696345 Set Vref, RX VrefLevel [Byte0]: 33
8647 11:32:45.699439 [Byte1]: 33
8648 11:32:45.703899
8649 11:32:45.703966 Set Vref, RX VrefLevel [Byte0]: 34
8650 11:32:45.707236 [Byte1]: 34
8651 11:32:45.711389
8652 11:32:45.711487 Set Vref, RX VrefLevel [Byte0]: 35
8653 11:32:45.714719 [Byte1]: 35
8654 11:32:45.718972
8655 11:32:45.719047 Set Vref, RX VrefLevel [Byte0]: 36
8656 11:32:45.722425 [Byte1]: 36
8657 11:32:45.726774
8658 11:32:45.726849 Set Vref, RX VrefLevel [Byte0]: 37
8659 11:32:45.730248 [Byte1]: 37
8660 11:32:45.734456
8661 11:32:45.734526 Set Vref, RX VrefLevel [Byte0]: 38
8662 11:32:45.737604 [Byte1]: 38
8663 11:32:45.741828
8664 11:32:45.741915 Set Vref, RX VrefLevel [Byte0]: 39
8665 11:32:45.745089 [Byte1]: 39
8666 11:32:45.749578
8667 11:32:45.749650 Set Vref, RX VrefLevel [Byte0]: 40
8668 11:32:45.752915 [Byte1]: 40
8669 11:32:45.757474
8670 11:32:45.757542 Set Vref, RX VrefLevel [Byte0]: 41
8671 11:32:45.760315 [Byte1]: 41
8672 11:32:45.764995
8673 11:32:45.765066 Set Vref, RX VrefLevel [Byte0]: 42
8674 11:32:45.768088 [Byte1]: 42
8675 11:32:45.772373
8676 11:32:45.772443 Set Vref, RX VrefLevel [Byte0]: 43
8677 11:32:45.775511 [Byte1]: 43
8678 11:32:45.779832
8679 11:32:45.779902 Set Vref, RX VrefLevel [Byte0]: 44
8680 11:32:45.783242 [Byte1]: 44
8681 11:32:45.787824
8682 11:32:45.787895 Set Vref, RX VrefLevel [Byte0]: 45
8683 11:32:45.790780 [Byte1]: 45
8684 11:32:45.795180
8685 11:32:45.795244 Set Vref, RX VrefLevel [Byte0]: 46
8686 11:32:45.798503 [Byte1]: 46
8687 11:32:45.802851
8688 11:32:45.802927 Set Vref, RX VrefLevel [Byte0]: 47
8689 11:32:45.806189 [Byte1]: 47
8690 11:32:45.810625
8691 11:32:45.810699 Set Vref, RX VrefLevel [Byte0]: 48
8692 11:32:45.813494 [Byte1]: 48
8693 11:32:45.817844
8694 11:32:45.817916 Set Vref, RX VrefLevel [Byte0]: 49
8695 11:32:45.821321 [Byte1]: 49
8696 11:32:45.825397
8697 11:32:45.825463 Set Vref, RX VrefLevel [Byte0]: 50
8698 11:32:45.828987 [Byte1]: 50
8699 11:32:45.833079
8700 11:32:45.833147 Set Vref, RX VrefLevel [Byte0]: 51
8701 11:32:45.836690 [Byte1]: 51
8702 11:32:45.840921
8703 11:32:45.840989 Set Vref, RX VrefLevel [Byte0]: 52
8704 11:32:45.844476 [Byte1]: 52
8705 11:32:45.848471
8706 11:32:45.848536 Set Vref, RX VrefLevel [Byte0]: 53
8707 11:32:45.851868 [Byte1]: 53
8708 11:32:45.856250
8709 11:32:45.856321 Set Vref, RX VrefLevel [Byte0]: 54
8710 11:32:45.859824 [Byte1]: 54
8711 11:32:45.864004
8712 11:32:45.864072 Set Vref, RX VrefLevel [Byte0]: 55
8713 11:32:45.867082 [Byte1]: 55
8714 11:32:45.871517
8715 11:32:45.871601 Set Vref, RX VrefLevel [Byte0]: 56
8716 11:32:45.874641 [Byte1]: 56
8717 11:32:45.878998
8718 11:32:45.879062 Set Vref, RX VrefLevel [Byte0]: 57
8719 11:32:45.882652 [Byte1]: 57
8720 11:32:45.886683
8721 11:32:45.886750 Set Vref, RX VrefLevel [Byte0]: 58
8722 11:32:45.889762 [Byte1]: 58
8723 11:32:45.894087
8724 11:32:45.894159 Set Vref, RX VrefLevel [Byte0]: 59
8725 11:32:45.897513 [Byte1]: 59
8726 11:32:45.901553
8727 11:32:45.901634 Set Vref, RX VrefLevel [Byte0]: 60
8728 11:32:45.905376 [Byte1]: 60
8729 11:32:45.909637
8730 11:32:45.909712 Set Vref, RX VrefLevel [Byte0]: 61
8731 11:32:45.912700 [Byte1]: 61
8732 11:32:45.917216
8733 11:32:45.917290 Set Vref, RX VrefLevel [Byte0]: 62
8734 11:32:45.920314 [Byte1]: 62
8735 11:32:45.924814
8736 11:32:45.924892 Set Vref, RX VrefLevel [Byte0]: 63
8737 11:32:45.928447 [Byte1]: 63
8738 11:32:45.932269
8739 11:32:45.932343 Set Vref, RX VrefLevel [Byte0]: 64
8740 11:32:45.935692 [Byte1]: 64
8741 11:32:45.939822
8742 11:32:45.939896 Set Vref, RX VrefLevel [Byte0]: 65
8743 11:32:45.943090 [Byte1]: 65
8744 11:32:45.947559
8745 11:32:45.947634 Set Vref, RX VrefLevel [Byte0]: 66
8746 11:32:45.950718 [Byte1]: 66
8747 11:32:45.955304
8748 11:32:45.955380 Set Vref, RX VrefLevel [Byte0]: 67
8749 11:32:45.958948 [Byte1]: 67
8750 11:32:45.962686
8751 11:32:45.962761 Set Vref, RX VrefLevel [Byte0]: 68
8752 11:32:45.965862 [Byte1]: 68
8753 11:32:45.970243
8754 11:32:45.970318 Set Vref, RX VrefLevel [Byte0]: 69
8755 11:32:45.973634 [Byte1]: 69
8756 11:32:45.977989
8757 11:32:45.978064 Set Vref, RX VrefLevel [Byte0]: 70
8758 11:32:45.980862 [Byte1]: 70
8759 11:32:45.985718
8760 11:32:45.985792 Set Vref, RX VrefLevel [Byte0]: 71
8761 11:32:45.988536 [Byte1]: 71
8762 11:32:45.993185
8763 11:32:45.993259 Set Vref, RX VrefLevel [Byte0]: 72
8764 11:32:45.996435 [Byte1]: 72
8765 11:32:46.000814
8766 11:32:46.000889 Final RX Vref Byte 0 = 55 to rank0
8767 11:32:46.003763 Final RX Vref Byte 1 = 60 to rank0
8768 11:32:46.007287 Final RX Vref Byte 0 = 55 to rank1
8769 11:32:46.010933 Final RX Vref Byte 1 = 60 to rank1==
8770 11:32:46.014132 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 11:32:46.020394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 11:32:46.020470 ==
8773 11:32:46.020529 DQS Delay:
8774 11:32:46.023706 DQS0 = 0, DQS1 = 0
8775 11:32:46.023781 DQM Delay:
8776 11:32:46.026973 DQM0 = 135, DQM1 = 129
8777 11:32:46.027048 DQ Delay:
8778 11:32:46.030364 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8779 11:32:46.033992 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8780 11:32:46.036896 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8781 11:32:46.039977 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8782 11:32:46.040052
8783 11:32:46.040110
8784 11:32:46.040163
8785 11:32:46.043238 [DramC_TX_OE_Calibration] TA2
8786 11:32:46.046550 Original DQ_B0 (3 6) =30, OEN = 27
8787 11:32:46.049804 Original DQ_B1 (3 6) =30, OEN = 27
8788 11:32:46.053401 24, 0x0, End_B0=24 End_B1=24
8789 11:32:46.056676 25, 0x0, End_B0=25 End_B1=25
8790 11:32:46.056753 26, 0x0, End_B0=26 End_B1=26
8791 11:32:46.060030 27, 0x0, End_B0=27 End_B1=27
8792 11:32:46.063413 28, 0x0, End_B0=28 End_B1=28
8793 11:32:46.066996 29, 0x0, End_B0=29 End_B1=29
8794 11:32:46.067072 30, 0x0, End_B0=30 End_B1=30
8795 11:32:46.069774 31, 0x4141, End_B0=30 End_B1=30
8796 11:32:46.073277 Byte0 end_step=30 best_step=27
8797 11:32:46.076376 Byte1 end_step=30 best_step=27
8798 11:32:46.079696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 11:32:46.083231 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 11:32:46.083306
8801 11:32:46.083369
8802 11:32:46.089644 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8803 11:32:46.093502 CH1 RK0: MR19=303, MR18=1B11
8804 11:32:46.099588 CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15
8805 11:32:46.099664
8806 11:32:46.102688 ----->DramcWriteLeveling(PI) begin...
8807 11:32:46.102754 ==
8808 11:32:46.106256 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 11:32:46.109832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 11:32:46.109898 ==
8811 11:32:46.112636 Write leveling (Byte 0): 24 => 24
8812 11:32:46.116002 Write leveling (Byte 1): 27 => 27
8813 11:32:46.119643 DramcWriteLeveling(PI) end<-----
8814 11:32:46.119712
8815 11:32:46.119767 ==
8816 11:32:46.122864 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 11:32:46.125973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 11:32:46.129447 ==
8819 11:32:46.129506 [Gating] SW mode calibration
8820 11:32:46.139294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 11:32:46.142662 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 11:32:46.145817 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 11:32:46.152254 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 11:32:46.155451 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 11:32:46.159240 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8826 11:32:46.165682 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:32:46.168970 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:32:46.172213 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:32:46.178732 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 11:32:46.181963 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 11:32:46.185631 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 11:32:46.192047 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8833 11:32:46.195346 1 5 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 0)
8834 11:32:46.198618 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:32:46.204975 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:32:46.208665 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:32:46.211954 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 11:32:46.218123 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 11:32:46.221375 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 11:32:46.224665 1 6 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8841 11:32:46.231275 1 6 12 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8842 11:32:46.234781 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:32:46.241191 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:32:46.244388 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:32:46.247585 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 11:32:46.254150 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 11:32:46.257597 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 11:32:46.260704 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8849 11:32:46.267938 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 11:32:46.270748 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8851 11:32:46.273921 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:32:46.280621 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:32:46.284226 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:32:46.287131 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:32:46.293959 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:32:46.296775 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:32:46.300546 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:32:46.306829 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:32:46.310120 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:32:46.314083 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:32:46.320095 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:32:46.323148 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:32:46.326834 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:32:46.333141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8865 11:32:46.336481 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 11:32:46.340155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8867 11:32:46.343284 Total UI for P1: 0, mck2ui 16
8868 11:32:46.346738 best dqsien dly found for B1: ( 1, 9, 10)
8869 11:32:46.352891 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 11:32:46.352968 Total UI for P1: 0, mck2ui 16
8871 11:32:46.356424 best dqsien dly found for B0: ( 1, 9, 14)
8872 11:32:46.363072 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8873 11:32:46.366397 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8874 11:32:46.366472
8875 11:32:46.369450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8876 11:32:46.373446 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8877 11:32:46.376129 [Gating] SW calibration Done
8878 11:32:46.376204 ==
8879 11:32:46.379123 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 11:32:46.382744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 11:32:46.382820 ==
8882 11:32:46.385686 RX Vref Scan: 0
8883 11:32:46.385761
8884 11:32:46.385820 RX Vref 0 -> 0, step: 1
8885 11:32:46.385873
8886 11:32:46.389226 RX Delay 0 -> 252, step: 8
8887 11:32:46.393230 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8888 11:32:46.398855 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8889 11:32:46.402338 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8890 11:32:46.405627 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8891 11:32:46.409070 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8892 11:32:46.412384 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8893 11:32:46.419322 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8894 11:32:46.422463 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8895 11:32:46.425790 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8896 11:32:46.428792 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8897 11:32:46.432150 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8898 11:32:46.438709 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8899 11:32:46.442428 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8900 11:32:46.445495 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8901 11:32:46.448582 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8902 11:32:46.455684 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8903 11:32:46.455761 ==
8904 11:32:46.459001 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:32:46.461931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:32:46.462007 ==
8907 11:32:46.462065 DQS Delay:
8908 11:32:46.465032 DQS0 = 0, DQS1 = 0
8909 11:32:46.465107 DQM Delay:
8910 11:32:46.468558 DQM0 = 136, DQM1 = 129
8911 11:32:46.468633 DQ Delay:
8912 11:32:46.471535 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8913 11:32:46.475298 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8914 11:32:46.478387 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8915 11:32:46.481565 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8916 11:32:46.484639
8917 11:32:46.484705
8918 11:32:46.484760 ==
8919 11:32:46.488351 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 11:32:46.491655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 11:32:46.491722 ==
8922 11:32:46.491775
8923 11:32:46.491825
8924 11:32:46.495183 TX Vref Scan disable
8925 11:32:46.495271 == TX Byte 0 ==
8926 11:32:46.501316 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 11:32:46.504749 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 11:32:46.504813 == TX Byte 1 ==
8929 11:32:46.511524 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8930 11:32:46.514743 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8931 11:32:46.514809 ==
8932 11:32:46.517956 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 11:32:46.521419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 11:32:46.521485 ==
8935 11:32:46.534924
8936 11:32:46.538286 TX Vref early break, caculate TX vref
8937 11:32:46.541894 TX Vref=16, minBit 0, minWin=22, winSum=384
8938 11:32:46.544932 TX Vref=18, minBit 0, minWin=23, winSum=393
8939 11:32:46.548111 TX Vref=20, minBit 1, minWin=24, winSum=406
8940 11:32:46.551075 TX Vref=22, minBit 1, minWin=24, winSum=411
8941 11:32:46.554419 TX Vref=24, minBit 5, minWin=25, winSum=418
8942 11:32:46.561483 TX Vref=26, minBit 0, minWin=25, winSum=423
8943 11:32:46.564559 TX Vref=28, minBit 0, minWin=25, winSum=420
8944 11:32:46.567643 TX Vref=30, minBit 0, minWin=25, winSum=415
8945 11:32:46.571169 TX Vref=32, minBit 0, minWin=24, winSum=408
8946 11:32:46.574136 TX Vref=34, minBit 0, minWin=23, winSum=395
8947 11:32:46.581095 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8948 11:32:46.581171
8949 11:32:46.584489 Final TX Range 0 Vref 26
8950 11:32:46.584564
8951 11:32:46.584622 ==
8952 11:32:46.587642 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 11:32:46.591016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 11:32:46.591092 ==
8955 11:32:46.591150
8956 11:32:46.591204
8957 11:32:46.594109 TX Vref Scan disable
8958 11:32:46.600961 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8959 11:32:46.601037 == TX Byte 0 ==
8960 11:32:46.604469 u2DelayCellOfst[0]=18 cells (5 PI)
8961 11:32:46.607902 u2DelayCellOfst[1]=11 cells (3 PI)
8962 11:32:46.610684 u2DelayCellOfst[2]=0 cells (0 PI)
8963 11:32:46.614200 u2DelayCellOfst[3]=3 cells (1 PI)
8964 11:32:46.617273 u2DelayCellOfst[4]=7 cells (2 PI)
8965 11:32:46.621003 u2DelayCellOfst[5]=22 cells (6 PI)
8966 11:32:46.624297 u2DelayCellOfst[6]=18 cells (5 PI)
8967 11:32:46.627931 u2DelayCellOfst[7]=3 cells (1 PI)
8968 11:32:46.631083 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8969 11:32:46.634136 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8970 11:32:46.637271 == TX Byte 1 ==
8971 11:32:46.637346 u2DelayCellOfst[8]=0 cells (0 PI)
8972 11:32:46.641029 u2DelayCellOfst[9]=7 cells (2 PI)
8973 11:32:46.643628 u2DelayCellOfst[10]=14 cells (4 PI)
8974 11:32:46.647151 u2DelayCellOfst[11]=7 cells (2 PI)
8975 11:32:46.650522 u2DelayCellOfst[12]=18 cells (5 PI)
8976 11:32:46.654159 u2DelayCellOfst[13]=18 cells (5 PI)
8977 11:32:46.656825 u2DelayCellOfst[14]=18 cells (5 PI)
8978 11:32:46.660669 u2DelayCellOfst[15]=18 cells (5 PI)
8979 11:32:46.663772 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8980 11:32:46.670154 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8981 11:32:46.670230 DramC Write-DBI on
8982 11:32:46.670288 ==
8983 11:32:46.673890 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 11:32:46.680440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 11:32:46.680516 ==
8986 11:32:46.680575
8987 11:32:46.680628
8988 11:32:46.680679 TX Vref Scan disable
8989 11:32:46.683908 == TX Byte 0 ==
8990 11:32:46.687115 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8991 11:32:46.690710 == TX Byte 1 ==
8992 11:32:46.693766 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8993 11:32:46.697205 DramC Write-DBI off
8994 11:32:46.697280
8995 11:32:46.697338 [DATLAT]
8996 11:32:46.697391 Freq=1600, CH1 RK1
8997 11:32:46.697443
8998 11:32:46.700415 DATLAT Default: 0xf
8999 11:32:46.703795 0, 0xFFFF, sum = 0
9000 11:32:46.703871 1, 0xFFFF, sum = 0
9001 11:32:46.706862 2, 0xFFFF, sum = 0
9002 11:32:46.706939 3, 0xFFFF, sum = 0
9003 11:32:46.710165 4, 0xFFFF, sum = 0
9004 11:32:46.710240 5, 0xFFFF, sum = 0
9005 11:32:46.713247 6, 0xFFFF, sum = 0
9006 11:32:46.713323 7, 0xFFFF, sum = 0
9007 11:32:46.716973 8, 0xFFFF, sum = 0
9008 11:32:46.717049 9, 0xFFFF, sum = 0
9009 11:32:46.720148 10, 0xFFFF, sum = 0
9010 11:32:46.720224 11, 0xFFFF, sum = 0
9011 11:32:46.723291 12, 0xFFFF, sum = 0
9012 11:32:46.723367 13, 0xFFFF, sum = 0
9013 11:32:46.726709 14, 0x0, sum = 1
9014 11:32:46.726786 15, 0x0, sum = 2
9015 11:32:46.730157 16, 0x0, sum = 3
9016 11:32:46.730233 17, 0x0, sum = 4
9017 11:32:46.733082 best_step = 15
9018 11:32:46.733156
9019 11:32:46.733214 ==
9020 11:32:46.736404 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 11:32:46.739606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 11:32:46.739682 ==
9023 11:32:46.742959 RX Vref Scan: 0
9024 11:32:46.743034
9025 11:32:46.743091 RX Vref 0 -> 0, step: 1
9026 11:32:46.743146
9027 11:32:46.746291 RX Delay 11 -> 252, step: 4
9028 11:32:46.753050 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9029 11:32:46.756366 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9030 11:32:46.759884 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9031 11:32:46.762979 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9032 11:32:46.766334 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9033 11:32:46.773143 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9034 11:32:46.776360 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9035 11:32:46.779575 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9036 11:32:46.782856 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9037 11:32:46.789305 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9038 11:32:46.792344 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
9039 11:32:46.795801 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9040 11:32:46.799557 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9041 11:32:46.802517 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9042 11:32:46.809016 iDelay=199, Bit 14, Center 132 (75 ~ 190) 116
9043 11:32:46.812436 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9044 11:32:46.812511 ==
9045 11:32:46.815485 Dram Type= 6, Freq= 0, CH_1, rank 1
9046 11:32:46.818809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9047 11:32:46.818884 ==
9048 11:32:46.822271 DQS Delay:
9049 11:32:46.822346 DQS0 = 0, DQS1 = 0
9050 11:32:46.822404 DQM Delay:
9051 11:32:46.825558 DQM0 = 134, DQM1 = 127
9052 11:32:46.825633 DQ Delay:
9053 11:32:46.828642 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9054 11:32:46.832179 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
9055 11:32:46.838898 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9056 11:32:46.841940 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9057 11:32:46.842015
9058 11:32:46.842072
9059 11:32:46.842125
9060 11:32:46.845392 [DramC_TX_OE_Calibration] TA2
9061 11:32:46.848459 Original DQ_B0 (3 6) =30, OEN = 27
9062 11:32:46.851812 Original DQ_B1 (3 6) =30, OEN = 27
9063 11:32:46.851878 24, 0x0, End_B0=24 End_B1=24
9064 11:32:46.855253 25, 0x0, End_B0=25 End_B1=25
9065 11:32:46.858246 26, 0x0, End_B0=26 End_B1=26
9066 11:32:46.861699 27, 0x0, End_B0=27 End_B1=27
9067 11:32:46.861769 28, 0x0, End_B0=28 End_B1=28
9068 11:32:46.864894 29, 0x0, End_B0=29 End_B1=29
9069 11:32:46.868133 30, 0x0, End_B0=30 End_B1=30
9070 11:32:46.871596 31, 0x4545, End_B0=30 End_B1=30
9071 11:32:46.874642 Byte0 end_step=30 best_step=27
9072 11:32:46.877966 Byte1 end_step=30 best_step=27
9073 11:32:46.878034 Byte0 TX OE(2T, 0.5T) = (3, 3)
9074 11:32:46.881214 Byte1 TX OE(2T, 0.5T) = (3, 3)
9075 11:32:46.881279
9076 11:32:46.881333
9077 11:32:46.891173 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9078 11:32:46.894330 CH1 RK1: MR19=303, MR18=E0B
9079 11:32:46.897587 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9080 11:32:46.900819 [RxdqsGatingPostProcess] freq 1600
9081 11:32:46.907677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9082 11:32:46.910950 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 11:32:46.914435 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 11:32:46.917464 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 11:32:46.920902 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 11:32:46.924196 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 11:32:46.927744 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 11:32:46.930828 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 11:32:46.934225 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 11:32:46.934288 Pre-setting of DQS Precalculation
9091 11:32:46.940846 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9092 11:32:46.947629 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9093 11:32:46.953723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 11:32:46.953792
9095 11:32:46.953848
9096 11:32:46.957312 [Calibration Summary] 3200 Mbps
9097 11:32:46.960533 CH 0, Rank 0
9098 11:32:46.960597 SW Impedance : PASS
9099 11:32:46.964117 DUTY Scan : NO K
9100 11:32:46.967182 ZQ Calibration : PASS
9101 11:32:46.967248 Jitter Meter : NO K
9102 11:32:46.970484 CBT Training : PASS
9103 11:32:46.973963 Write leveling : PASS
9104 11:32:46.974028 RX DQS gating : PASS
9105 11:32:46.976995 RX DQ/DQS(RDDQC) : PASS
9106 11:32:46.980096 TX DQ/DQS : PASS
9107 11:32:46.980165 RX DATLAT : PASS
9108 11:32:46.984279 RX DQ/DQS(Engine): PASS
9109 11:32:46.987224 TX OE : PASS
9110 11:32:46.987311 All Pass.
9111 11:32:46.987397
9112 11:32:46.987473 CH 0, Rank 1
9113 11:32:46.990454 SW Impedance : PASS
9114 11:32:46.993555 DUTY Scan : NO K
9115 11:32:46.993617 ZQ Calibration : PASS
9116 11:32:46.996487 Jitter Meter : NO K
9117 11:32:46.999905 CBT Training : PASS
9118 11:32:46.999973 Write leveling : PASS
9119 11:32:47.003048 RX DQS gating : PASS
9120 11:32:47.003111 RX DQ/DQS(RDDQC) : PASS
9121 11:32:47.006581 TX DQ/DQS : PASS
9122 11:32:47.009661 RX DATLAT : PASS
9123 11:32:47.009727 RX DQ/DQS(Engine): PASS
9124 11:32:47.013231 TX OE : PASS
9125 11:32:47.013296 All Pass.
9126 11:32:47.013348
9127 11:32:47.016432 CH 1, Rank 0
9128 11:32:47.016500 SW Impedance : PASS
9129 11:32:47.019593 DUTY Scan : NO K
9130 11:32:47.022947 ZQ Calibration : PASS
9131 11:32:47.023011 Jitter Meter : NO K
9132 11:32:47.026737 CBT Training : PASS
9133 11:32:47.029306 Write leveling : PASS
9134 11:32:47.029370 RX DQS gating : PASS
9135 11:32:47.033060 RX DQ/DQS(RDDQC) : PASS
9136 11:32:47.035990 TX DQ/DQS : PASS
9137 11:32:47.036052 RX DATLAT : PASS
9138 11:32:47.039331 RX DQ/DQS(Engine): PASS
9139 11:32:47.042904 TX OE : PASS
9140 11:32:47.042971 All Pass.
9141 11:32:47.043027
9142 11:32:47.043078 CH 1, Rank 1
9143 11:32:47.045884 SW Impedance : PASS
9144 11:32:47.049496 DUTY Scan : NO K
9145 11:32:47.049557 ZQ Calibration : PASS
9146 11:32:47.052787 Jitter Meter : NO K
9147 11:32:47.056440 CBT Training : PASS
9148 11:32:47.056509 Write leveling : PASS
9149 11:32:47.059382 RX DQS gating : PASS
9150 11:32:47.062502 RX DQ/DQS(RDDQC) : PASS
9151 11:32:47.062566 TX DQ/DQS : PASS
9152 11:32:47.065921 RX DATLAT : PASS
9153 11:32:47.069357 RX DQ/DQS(Engine): PASS
9154 11:32:47.069426 TX OE : PASS
9155 11:32:47.069483 All Pass.
9156 11:32:47.072609
9157 11:32:47.072677 DramC Write-DBI on
9158 11:32:47.075660 PER_BANK_REFRESH: Hybrid Mode
9159 11:32:47.075724 TX_TRACKING: ON
9160 11:32:47.085801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9161 11:32:47.092312 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9162 11:32:47.102555 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9163 11:32:47.105256 [FAST_K] Save calibration result to emmc
9164 11:32:47.108538 sync common calibartion params.
9165 11:32:47.108606 sync cbt_mode0:1, 1:1
9166 11:32:47.112069 dram_init: ddr_geometry: 2
9167 11:32:47.115281 dram_init: ddr_geometry: 2
9168 11:32:47.115370 dram_init: ddr_geometry: 2
9169 11:32:47.118291 0:dram_rank_size:100000000
9170 11:32:47.122376 1:dram_rank_size:100000000
9171 11:32:47.128597 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9172 11:32:47.128673 DFS_SHUFFLE_HW_MODE: ON
9173 11:32:47.132151 dramc_set_vcore_voltage set vcore to 725000
9174 11:32:47.135091 Read voltage for 1600, 0
9175 11:32:47.135166 Vio18 = 0
9176 11:32:47.138570 Vcore = 725000
9177 11:32:47.138645 Vdram = 0
9178 11:32:47.138703 Vddq = 0
9179 11:32:47.141912 Vmddr = 0
9180 11:32:47.141987 switch to 3200 Mbps bootup
9181 11:32:47.145234 [DramcRunTimeConfig]
9182 11:32:47.145313 PHYPLL
9183 11:32:47.148378 DPM_CONTROL_AFTERK: ON
9184 11:32:47.148453 PER_BANK_REFRESH: ON
9185 11:32:47.151733 REFRESH_OVERHEAD_REDUCTION: ON
9186 11:32:47.155066 CMD_PICG_NEW_MODE: OFF
9187 11:32:47.155141 XRTWTW_NEW_MODE: ON
9188 11:32:47.158249 XRTRTR_NEW_MODE: ON
9189 11:32:47.158324 TX_TRACKING: ON
9190 11:32:47.161609 RDSEL_TRACKING: OFF
9191 11:32:47.164886 DQS Precalculation for DVFS: ON
9192 11:32:47.164962 RX_TRACKING: OFF
9193 11:32:47.168263 HW_GATING DBG: ON
9194 11:32:47.168338 ZQCS_ENABLE_LP4: ON
9195 11:32:47.171889 RX_PICG_NEW_MODE: ON
9196 11:32:47.171964 TX_PICG_NEW_MODE: ON
9197 11:32:47.175273 ENABLE_RX_DCM_DPHY: ON
9198 11:32:47.178118 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9199 11:32:47.181809 DUMMY_READ_FOR_TRACKING: OFF
9200 11:32:47.181883 !!! SPM_CONTROL_AFTERK: OFF
9201 11:32:47.184728 !!! SPM could not control APHY
9202 11:32:47.187860 IMPEDANCE_TRACKING: ON
9203 11:32:47.187934 TEMP_SENSOR: ON
9204 11:32:47.191054 HW_SAVE_FOR_SR: OFF
9205 11:32:47.194445 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9206 11:32:47.197869 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9207 11:32:47.201153 Read ODT Tracking: ON
9208 11:32:47.201228 Refresh Rate DeBounce: ON
9209 11:32:47.204725 DFS_NO_QUEUE_FLUSH: ON
9210 11:32:47.208060 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9211 11:32:47.211082 ENABLE_DFS_RUNTIME_MRW: OFF
9212 11:32:47.211183 DDR_RESERVE_NEW_MODE: ON
9213 11:32:47.214196 MR_CBT_SWITCH_FREQ: ON
9214 11:32:47.217536 =========================
9215 11:32:47.235069 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9216 11:32:47.238482 dram_init: ddr_geometry: 2
9217 11:32:47.256766 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9218 11:32:47.260277 dram_init: dram init end (result: 0)
9219 11:32:47.266558 DRAM-K: Full calibration passed in 24685 msecs
9220 11:32:47.269957 MRC: failed to locate region type 0.
9221 11:32:47.270026 DRAM rank0 size:0x100000000,
9222 11:32:47.273185 DRAM rank1 size=0x100000000
9223 11:32:47.283043 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9224 11:32:47.289762 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9225 11:32:47.296433 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9226 11:32:47.302924 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9227 11:32:47.306302 DRAM rank0 size:0x100000000,
9228 11:32:47.310018 DRAM rank1 size=0x100000000
9229 11:32:47.310095 CBMEM:
9230 11:32:47.313111 IMD: root @ 0xfffff000 254 entries.
9231 11:32:47.316083 IMD: root @ 0xffffec00 62 entries.
9232 11:32:47.319826 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9233 11:32:47.326213 WARNING: RO_VPD is uninitialized or empty.
9234 11:32:47.329509 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9235 11:32:47.337372 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9236 11:32:47.349471 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9237 11:32:47.361033 BS: romstage times (exec / console): total (unknown) / 24164 ms
9238 11:32:47.361112
9239 11:32:47.361171
9240 11:32:47.370942 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9241 11:32:47.374188 ARM64: Exception handlers installed.
9242 11:32:47.377922 ARM64: Testing exception
9243 11:32:47.381163 ARM64: Done test exception
9244 11:32:47.381239 Enumerating buses...
9245 11:32:47.383997 Show all devs... Before device enumeration.
9246 11:32:47.387405 Root Device: enabled 1
9247 11:32:47.390674 CPU_CLUSTER: 0: enabled 1
9248 11:32:47.390751 CPU: 00: enabled 1
9249 11:32:47.393811 Compare with tree...
9250 11:32:47.393879 Root Device: enabled 1
9251 11:32:47.397564 CPU_CLUSTER: 0: enabled 1
9252 11:32:47.400696 CPU: 00: enabled 1
9253 11:32:47.400760 Root Device scanning...
9254 11:32:47.403725 scan_static_bus for Root Device
9255 11:32:47.407080 CPU_CLUSTER: 0 enabled
9256 11:32:47.410207 scan_static_bus for Root Device done
9257 11:32:47.414164 scan_bus: bus Root Device finished in 8 msecs
9258 11:32:47.414260 done
9259 11:32:47.420736 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9260 11:32:47.423891 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9261 11:32:47.430234 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9262 11:32:47.433789 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9263 11:32:47.437015 Allocating resources...
9264 11:32:47.440326 Reading resources...
9265 11:32:47.443682 Root Device read_resources bus 0 link: 0
9266 11:32:47.446993 DRAM rank0 size:0x100000000,
9267 11:32:47.447068 DRAM rank1 size=0x100000000
9268 11:32:47.453443 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9269 11:32:47.453519 CPU: 00 missing read_resources
9270 11:32:47.460121 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9271 11:32:47.463640 Root Device read_resources bus 0 link: 0 done
9272 11:32:47.463716 Done reading resources.
9273 11:32:47.470201 Show resources in subtree (Root Device)...After reading.
9274 11:32:47.473145 Root Device child on link 0 CPU_CLUSTER: 0
9275 11:32:47.476745 CPU_CLUSTER: 0 child on link 0 CPU: 00
9276 11:32:47.486991 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9277 11:32:47.487068 CPU: 00
9278 11:32:47.489927 Root Device assign_resources, bus 0 link: 0
9279 11:32:47.493236 CPU_CLUSTER: 0 missing set_resources
9280 11:32:47.499929 Root Device assign_resources, bus 0 link: 0 done
9281 11:32:47.500005 Done setting resources.
9282 11:32:47.506259 Show resources in subtree (Root Device)...After assigning values.
9283 11:32:47.509841 Root Device child on link 0 CPU_CLUSTER: 0
9284 11:32:47.513036 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 11:32:47.523011 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 11:32:47.523087 CPU: 00
9287 11:32:47.526023 Done allocating resources.
9288 11:32:47.532786 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9289 11:32:47.532861 Enabling resources...
9290 11:32:47.532920 done.
9291 11:32:47.539326 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9292 11:32:47.542456 Initializing devices...
9293 11:32:47.542531 Root Device init
9294 11:32:47.545901 init hardware done!
9295 11:32:47.545976 0x00000018: ctrlr->caps
9296 11:32:47.549312 52.000 MHz: ctrlr->f_max
9297 11:32:47.552267 0.400 MHz: ctrlr->f_min
9298 11:32:47.552344 0x40ff8080: ctrlr->voltages
9299 11:32:47.555644 sclk: 390625
9300 11:32:47.555719 Bus Width = 1
9301 11:32:47.559038 sclk: 390625
9302 11:32:47.559112 Bus Width = 1
9303 11:32:47.562307 Early init status = 3
9304 11:32:47.565761 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9305 11:32:47.568939 in-header: 03 fc 00 00 01 00 00 00
9306 11:32:47.572524 in-data: 00
9307 11:32:47.575402 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9308 11:32:47.579601 in-header: 03 fd 00 00 00 00 00 00
9309 11:32:47.582962 in-data:
9310 11:32:47.586381 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9311 11:32:47.589999 in-header: 03 fc 00 00 01 00 00 00
9312 11:32:47.593673 in-data: 00
9313 11:32:47.596869 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9314 11:32:47.601332 in-header: 03 fd 00 00 00 00 00 00
9315 11:32:47.604521 in-data:
9316 11:32:47.607824 [SSUSB] Setting up USB HOST controller...
9317 11:32:47.610963 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9318 11:32:47.614438 [SSUSB] phy power-on done.
9319 11:32:47.617720 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9320 11:32:47.624559 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9321 11:32:47.627541 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9322 11:32:47.633952 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9323 11:32:47.640492 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9324 11:32:47.647544 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9325 11:32:47.654043 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9326 11:32:47.661112 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9327 11:32:47.663752 SPM: binary array size = 0x9dc
9328 11:32:47.667008 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9329 11:32:47.673576 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9330 11:32:47.680182 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9331 11:32:47.686842 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9332 11:32:47.690111 configure_display: Starting display init
9333 11:32:47.724291 anx7625_power_on_init: Init interface.
9334 11:32:47.727900 anx7625_disable_pd_protocol: Disabled PD feature.
9335 11:32:47.731056 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9336 11:32:47.758900 anx7625_start_dp_work: Secure OCM version=00
9337 11:32:47.762127 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9338 11:32:47.776922 sp_tx_get_edid_block: EDID Block = 1
9339 11:32:47.879739 Extracted contents:
9340 11:32:47.882709 header: 00 ff ff ff ff ff ff 00
9341 11:32:47.886214 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9342 11:32:47.889311 version: 01 04
9343 11:32:47.892989 basic params: 95 1f 11 78 0a
9344 11:32:47.895845 chroma info: 76 90 94 55 54 90 27 21 50 54
9345 11:32:47.899463 established: 00 00 00
9346 11:32:47.905631 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9347 11:32:47.912608 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9348 11:32:47.916006 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 11:32:47.922622 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9350 11:32:47.928886 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9351 11:32:47.932409 extensions: 00
9352 11:32:47.932484 checksum: fb
9353 11:32:47.932541
9354 11:32:47.938964 Manufacturer: IVO Model 57d Serial Number 0
9355 11:32:47.939038 Made week 0 of 2020
9356 11:32:47.942196 EDID version: 1.4
9357 11:32:47.942270 Digital display
9358 11:32:47.945254 6 bits per primary color channel
9359 11:32:47.945329 DisplayPort interface
9360 11:32:47.949269 Maximum image size: 31 cm x 17 cm
9361 11:32:47.951847 Gamma: 220%
9362 11:32:47.951921 Check DPMS levels
9363 11:32:47.958857 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9364 11:32:47.961668 First detailed timing is preferred timing
9365 11:32:47.961742 Established timings supported:
9366 11:32:47.965475 Standard timings supported:
9367 11:32:47.968406 Detailed timings
9368 11:32:47.971654 Hex of detail: 383680a07038204018303c0035ae10000019
9369 11:32:47.978340 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9370 11:32:47.982163 0780 0798 07c8 0820 hborder 0
9371 11:32:47.985193 0438 043b 0447 0458 vborder 0
9372 11:32:47.988214 -hsync -vsync
9373 11:32:47.988290 Did detailed timing
9374 11:32:47.995077 Hex of detail: 000000000000000000000000000000000000
9375 11:32:47.998425 Manufacturer-specified data, tag 0
9376 11:32:48.001510 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9377 11:32:48.004700 ASCII string: InfoVision
9378 11:32:48.007917 Hex of detail: 000000fe00523134304e574635205248200a
9379 11:32:48.011548 ASCII string: R140NWF5 RH
9380 11:32:48.011618 Checksum
9381 11:32:48.014656 Checksum: 0xfb (valid)
9382 11:32:48.018363 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9383 11:32:48.021311 DSI data_rate: 832800000 bps
9384 11:32:48.028074 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9385 11:32:48.030950 anx7625_parse_edid: pixelclock(138800).
9386 11:32:48.034256 hactive(1920), hsync(48), hfp(24), hbp(88)
9387 11:32:48.037544 vactive(1080), vsync(12), vfp(3), vbp(17)
9388 11:32:48.040889 anx7625_dsi_config: config dsi.
9389 11:32:48.047779 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9390 11:32:48.061276 anx7625_dsi_config: success to config DSI
9391 11:32:48.064610 anx7625_dp_start: MIPI phy setup OK.
9392 11:32:48.067876 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9393 11:32:48.071256 mtk_ddp_mode_set invalid vrefresh 60
9394 11:32:48.074892 main_disp_path_setup
9395 11:32:48.074965 ovl_layer_smi_id_en
9396 11:32:48.078200 ovl_layer_smi_id_en
9397 11:32:48.078278 ccorr_config
9398 11:32:48.078333 aal_config
9399 11:32:48.081271 gamma_config
9400 11:32:48.081344 postmask_config
9401 11:32:48.085000 dither_config
9402 11:32:48.088185 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9403 11:32:48.094845 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9404 11:32:48.097927 Root Device init finished in 551 msecs
9405 11:32:48.101194 CPU_CLUSTER: 0 init
9406 11:32:48.108143 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9407 11:32:48.114487 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9408 11:32:48.114566 APU_MBOX 0x190000b0 = 0x10001
9409 11:32:48.117712 APU_MBOX 0x190001b0 = 0x10001
9410 11:32:48.121118 APU_MBOX 0x190005b0 = 0x10001
9411 11:32:48.124183 APU_MBOX 0x190006b0 = 0x10001
9412 11:32:48.130760 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9413 11:32:48.140582 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9414 11:32:48.152973 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9415 11:32:48.159625 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9416 11:32:48.171825 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9417 11:32:48.180454 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9418 11:32:48.183514 CPU_CLUSTER: 0 init finished in 81 msecs
9419 11:32:48.186876 Devices initialized
9420 11:32:48.190292 Show all devs... After init.
9421 11:32:48.190361 Root Device: enabled 1
9422 11:32:48.194136 CPU_CLUSTER: 0: enabled 1
9423 11:32:48.196791 CPU: 00: enabled 1
9424 11:32:48.200318 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9425 11:32:48.203288 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9426 11:32:48.206825 ELOG: NV offset 0x57f000 size 0x1000
9427 11:32:48.213636 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9428 11:32:48.219914 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9429 11:32:48.223776 ELOG: Event(17) added with size 13 at 2024-07-17 11:32:48 UTC
9430 11:32:48.230353 out: cmd=0x121: 03 db 21 01 00 00 00 00
9431 11:32:48.233149 in-header: 03 fe 00 00 2c 00 00 00
9432 11:32:48.242963 in-data: 3e 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9433 11:32:48.249917 ELOG: Event(A1) added with size 10 at 2024-07-17 11:32:48 UTC
9434 11:32:48.256476 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9435 11:32:48.262738 ELOG: Event(A0) added with size 9 at 2024-07-17 11:32:48 UTC
9436 11:32:48.266111 elog_add_boot_reason: Logged dev mode boot
9437 11:32:48.272985 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9438 11:32:48.273063 Finalize devices...
9439 11:32:48.275956 Devices finalized
9440 11:32:48.279373 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9441 11:32:48.283136 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9442 11:32:48.285986 in-header: 03 07 00 00 08 00 00 00
9443 11:32:48.289279 in-data: aa e4 47 04 13 02 00 00
9444 11:32:48.292881 Chrome EC: UHEPI supported
9445 11:32:48.299217 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9446 11:32:48.303170 in-header: 03 a9 00 00 08 00 00 00
9447 11:32:48.306017 in-data: 84 60 60 08 00 00 00 00
9448 11:32:48.312425 ELOG: Event(91) added with size 10 at 2024-07-17 11:32:48 UTC
9449 11:32:48.315821 Chrome EC: clear events_b mask to 0x0000000020004000
9450 11:32:48.322169 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9451 11:32:48.326587 in-header: 03 fd 00 00 00 00 00 00
9452 11:32:48.329654 in-data:
9453 11:32:48.333804 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9454 11:32:48.336449 Writing coreboot table at 0xffe64000
9455 11:32:48.342976 0. 000000000010a000-0000000000113fff: RAMSTAGE
9456 11:32:48.346912 1. 0000000040000000-00000000400fffff: RAM
9457 11:32:48.349723 2. 0000000040100000-000000004032afff: RAMSTAGE
9458 11:32:48.353102 3. 000000004032b000-00000000545fffff: RAM
9459 11:32:48.356141 4. 0000000054600000-000000005465ffff: BL31
9460 11:32:48.362764 5. 0000000054660000-00000000ffe63fff: RAM
9461 11:32:48.366454 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9462 11:32:48.369764 7. 0000000100000000-000000023fffffff: RAM
9463 11:32:48.372805 Passing 5 GPIOs to payload:
9464 11:32:48.376009 NAME | PORT | POLARITY | VALUE
9465 11:32:48.383034 EC in RW | 0x000000aa | low | undefined
9466 11:32:48.386046 EC interrupt | 0x00000005 | low | undefined
9467 11:32:48.393152 TPM interrupt | 0x000000ab | high | undefined
9468 11:32:48.396326 SD card detect | 0x00000011 | high | undefined
9469 11:32:48.402878 speaker enable | 0x00000093 | high | undefined
9470 11:32:48.405658 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9471 11:32:48.409113 in-header: 03 f9 00 00 02 00 00 00
9472 11:32:48.409177 in-data: 02 00
9473 11:32:48.412403 ADC[4]: Raw value=900813 ID=7
9474 11:32:48.415739 ADC[3]: Raw value=213652 ID=1
9475 11:32:48.415837 RAM Code: 0x71
9476 11:32:48.419239 ADC[6]: Raw value=75036 ID=0
9477 11:32:48.422153 ADC[5]: Raw value=212543 ID=1
9478 11:32:48.422218 SKU Code: 0x1
9479 11:32:48.428842 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 31b3
9480 11:32:48.432035 coreboot table: 964 bytes.
9481 11:32:48.435702 IMD ROOT 0. 0xfffff000 0x00001000
9482 11:32:48.438692 IMD SMALL 1. 0xffffe000 0x00001000
9483 11:32:48.441902 RO MCACHE 2. 0xffffc000 0x00001104
9484 11:32:48.445441 CONSOLE 3. 0xfff7c000 0x00080000
9485 11:32:48.448995 FMAP 4. 0xfff7b000 0x00000452
9486 11:32:48.452238 TIME STAMP 5. 0xfff7a000 0x00000910
9487 11:32:48.455137 VBOOT WORK 6. 0xfff66000 0x00014000
9488 11:32:48.458907 RAMOOPS 7. 0xffe66000 0x00100000
9489 11:32:48.462057 COREBOOT 8. 0xffe64000 0x00002000
9490 11:32:48.462134 IMD small region:
9491 11:32:48.465458 IMD ROOT 0. 0xffffec00 0x00000400
9492 11:32:48.468500 VPD 1. 0xffffeb80 0x0000006c
9493 11:32:48.471799 MMC STATUS 2. 0xffffeb60 0x00000004
9494 11:32:48.478149 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9495 11:32:48.484775 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9496 11:32:48.524211 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9497 11:32:48.527706 Checking segment from ROM address 0x40100000
9498 11:32:48.534676 Checking segment from ROM address 0x4010001c
9499 11:32:48.537325 Loading segment from ROM address 0x40100000
9500 11:32:48.537400 code (compression=0)
9501 11:32:48.547333 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9502 11:32:48.553826 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9503 11:32:48.557305 it's not compressed!
9504 11:32:48.560505 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9505 11:32:48.566885 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9506 11:32:48.584897 Loading segment from ROM address 0x4010001c
9507 11:32:48.584979 Entry Point 0x80000000
9508 11:32:48.588335 Loaded segments
9509 11:32:48.591053 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9510 11:32:48.597603 Jumping to boot code at 0x80000000(0xffe64000)
9511 11:32:48.604395 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9512 11:32:48.610959 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9513 11:32:48.619285 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9514 11:32:48.622192 Checking segment from ROM address 0x40100000
9515 11:32:48.625603 Checking segment from ROM address 0x4010001c
9516 11:32:48.632381 Loading segment from ROM address 0x40100000
9517 11:32:48.632450 code (compression=1)
9518 11:32:48.638604 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9519 11:32:48.648478 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9520 11:32:48.648550 using LZMA
9521 11:32:48.657382 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9522 11:32:48.664220 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9523 11:32:48.667444 Loading segment from ROM address 0x4010001c
9524 11:32:48.670329 Entry Point 0x54601000
9525 11:32:48.670401 Loaded segments
9526 11:32:48.673932 NOTICE: MT8192 bl31_setup
9527 11:32:48.681193 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9528 11:32:48.684515 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9529 11:32:48.687771 WARNING: region 0:
9530 11:32:48.690977 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 11:32:48.691043 WARNING: region 1:
9532 11:32:48.697696 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9533 11:32:48.700926 WARNING: region 2:
9534 11:32:48.704000 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9535 11:32:48.707384 WARNING: region 3:
9536 11:32:48.710721 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 11:32:48.714363 WARNING: region 4:
9538 11:32:48.720651 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 11:32:48.720722 WARNING: region 5:
9540 11:32:48.723951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 11:32:48.727226 WARNING: region 6:
9542 11:32:48.730401 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 11:32:48.734240 WARNING: region 7:
9544 11:32:48.737219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:32:48.743875 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9546 11:32:48.747100 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9547 11:32:48.753714 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9548 11:32:48.756989 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9549 11:32:48.760439 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9550 11:32:48.767253 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9551 11:32:48.770279 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9552 11:32:48.773677 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9553 11:32:48.780443 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9554 11:32:48.783912 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9555 11:32:48.790504 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9556 11:32:48.793306 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9557 11:32:48.796777 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9558 11:32:48.803592 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9559 11:32:48.806801 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9560 11:32:48.810427 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9561 11:32:48.816820 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9562 11:32:48.820258 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9563 11:32:48.826784 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9564 11:32:48.830189 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9565 11:32:48.833243 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9566 11:32:48.839631 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9567 11:32:48.843515 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9568 11:32:48.849663 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9569 11:32:48.852776 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9570 11:32:48.856261 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9571 11:32:48.862744 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9572 11:32:48.866159 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9573 11:32:48.872956 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9574 11:32:48.875988 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9575 11:32:48.882244 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9576 11:32:48.885751 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9577 11:32:48.889142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9578 11:32:48.892383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9579 11:32:48.899025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9580 11:32:48.902825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9581 11:32:48.905376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9582 11:32:48.909014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9583 11:32:48.915566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9584 11:32:48.918837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9585 11:32:48.921906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9586 11:32:48.925463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9587 11:32:48.932026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9588 11:32:48.935147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9589 11:32:48.938385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9590 11:32:48.945309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9591 11:32:48.948560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9592 11:32:48.951632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9593 11:32:48.958278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9594 11:32:48.961600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9595 11:32:48.965075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9596 11:32:48.971307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9597 11:32:48.974512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9598 11:32:48.981296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9599 11:32:48.984610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9600 11:32:48.991511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9601 11:32:48.994783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9602 11:32:48.997809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9603 11:32:49.004587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9604 11:32:49.007602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9605 11:32:49.014566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9606 11:32:49.017624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9607 11:32:49.025021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9608 11:32:49.027877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9609 11:32:49.034067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9610 11:32:49.037335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9611 11:32:49.044459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9612 11:32:49.047344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9613 11:32:49.050736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9614 11:32:49.057494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9615 11:32:49.061161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9616 11:32:49.067134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9617 11:32:49.070414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9618 11:32:49.076939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9619 11:32:49.080219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9620 11:32:49.087364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9621 11:32:49.090189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9622 11:32:49.093961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9623 11:32:49.100119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9624 11:32:49.103538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9625 11:32:49.110346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9626 11:32:49.113452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9627 11:32:49.119909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9628 11:32:49.123372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9629 11:32:49.129774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9630 11:32:49.133286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9631 11:32:49.136502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9632 11:32:49.143495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9633 11:32:49.146957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9634 11:32:49.153108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9635 11:32:49.156486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9636 11:32:49.163347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9637 11:32:49.166588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9638 11:32:49.172932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9639 11:32:49.176356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9640 11:32:49.179714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9641 11:32:49.186130 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9642 11:32:49.189438 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9643 11:32:49.192794 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9644 11:32:49.199214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9645 11:32:49.202478 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9646 11:32:49.205797 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9647 11:32:49.212419 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9648 11:32:49.215653 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9649 11:32:49.222392 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9650 11:32:49.225461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9651 11:32:49.229126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9652 11:32:49.235382 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9653 11:32:49.238940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9654 11:32:49.245402 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9655 11:32:49.248992 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9656 11:32:49.252101 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9657 11:32:49.258587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9658 11:32:49.261623 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9659 11:32:49.268350 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9660 11:32:49.271752 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9661 11:32:49.275082 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9662 11:32:49.281369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9663 11:32:49.284806 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9664 11:32:49.288252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9665 11:32:49.291582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9666 11:32:49.297877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9667 11:32:49.301319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9668 11:32:49.305053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9669 11:32:49.310961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9670 11:32:49.314455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9671 11:32:49.318004 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9672 11:32:49.324576 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9673 11:32:49.327886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9674 11:32:49.334350 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9675 11:32:49.337723 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9676 11:32:49.341031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9677 11:32:49.347759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9678 11:32:49.350620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9679 11:32:49.356908 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9680 11:32:49.360378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9681 11:32:49.367250 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9682 11:32:49.370421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9683 11:32:49.373508 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9684 11:32:49.380107 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9685 11:32:49.383332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9686 11:32:49.389951 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9687 11:32:49.393867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9688 11:32:49.396953 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9689 11:32:49.403607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9690 11:32:49.406536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9691 11:32:49.410228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9692 11:32:49.416348 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9693 11:32:49.419714 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9694 11:32:49.426318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9695 11:32:49.429434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9696 11:32:49.433225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9697 11:32:49.439782 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9698 11:32:49.442666 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9699 11:32:49.449510 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9700 11:32:49.452365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9701 11:32:49.459204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9702 11:32:49.462316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9703 11:32:49.466184 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9704 11:32:49.472252 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9705 11:32:49.475676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9706 11:32:49.482757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9707 11:32:49.485880 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9708 11:32:49.488940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9709 11:32:49.495310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9710 11:32:49.498857 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9711 11:32:49.502086 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9712 11:32:49.508657 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9713 11:32:49.512053 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9714 11:32:49.518752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9715 11:32:49.521840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9716 11:32:49.528749 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9717 11:32:49.531980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9718 11:32:49.535454 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9719 11:32:49.542351 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9720 11:32:49.545456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9721 11:32:49.548613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9722 11:32:49.555198 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9723 11:32:49.558326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9724 11:32:49.564744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9725 11:32:49.568364 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9726 11:32:49.571393 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9727 11:32:49.578423 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9728 11:32:49.582148 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9729 11:32:49.588955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9730 11:32:49.591370 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9731 11:32:49.594945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9732 11:32:49.601260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9733 11:32:49.604540 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9734 11:32:49.611041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9735 11:32:49.614556 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9736 11:32:49.621081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9737 11:32:49.624281 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9738 11:32:49.627720 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9739 11:32:49.634176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9740 11:32:49.637747 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9741 11:32:49.643966 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9742 11:32:49.648131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9743 11:32:49.654392 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9744 11:32:49.657175 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9745 11:32:49.660294 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9746 11:32:49.667449 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9747 11:32:49.671082 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9748 11:32:49.677072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9749 11:32:49.680809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9750 11:32:49.686855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9751 11:32:49.690289 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9752 11:32:49.693602 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9753 11:32:49.700386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9754 11:32:49.703388 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9755 11:32:49.710330 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9756 11:32:49.713264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9757 11:32:49.720109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9758 11:32:49.723041 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9759 11:32:49.726426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9760 11:32:49.733099 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9761 11:32:49.736561 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9762 11:32:49.743004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9763 11:32:49.746244 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9764 11:32:49.752739 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9765 11:32:49.756850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9766 11:32:49.759328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9767 11:32:49.765846 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9768 11:32:49.769451 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9769 11:32:49.775869 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9770 11:32:49.779383 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9771 11:32:49.786018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9772 11:32:49.789431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9773 11:32:49.792736 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9774 11:32:49.795797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9775 11:32:49.802744 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9776 11:32:49.806144 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9777 11:32:49.809166 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9778 11:32:49.812897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9779 11:32:49.819205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9780 11:32:49.822808 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9781 11:32:49.829355 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9782 11:32:49.832246 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9783 11:32:49.835802 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9784 11:32:49.842398 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9785 11:32:49.845551 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9786 11:32:49.848970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9787 11:32:49.855718 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9788 11:32:49.858995 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9789 11:32:49.862437 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9790 11:32:49.868855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9791 11:32:49.871986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9792 11:32:49.879126 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9793 11:32:49.881895 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9794 11:32:49.885232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9795 11:32:49.891782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9796 11:32:49.895025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9797 11:32:49.902078 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9798 11:32:49.905371 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9799 11:32:49.908658 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9800 11:32:49.915113 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9801 11:32:49.918263 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9802 11:32:49.921580 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9803 11:32:49.928081 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9804 11:32:49.931689 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9805 11:32:49.935024 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9806 11:32:49.941359 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9807 11:32:49.945096 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9808 11:32:49.951174 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9809 11:32:49.954552 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9810 11:32:49.957965 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9811 11:32:49.964515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9812 11:32:49.967574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9813 11:32:49.971300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9814 11:32:49.977659 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9815 11:32:49.980734 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9816 11:32:49.984232 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9817 11:32:49.987554 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9818 11:32:49.993834 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9819 11:32:49.997324 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9820 11:32:50.000540 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9821 11:32:50.003874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9822 11:32:50.010598 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9823 11:32:50.013419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9824 11:32:50.017118 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9825 11:32:50.023580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9826 11:32:50.026907 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9827 11:32:50.030432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9828 11:32:50.036879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9829 11:32:50.040016 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9830 11:32:50.046584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9831 11:32:50.050178 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9832 11:32:50.053162 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9833 11:32:50.060618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9834 11:32:50.063225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9835 11:32:50.069946 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9836 11:32:50.073632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9837 11:32:50.076672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9838 11:32:50.083573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9839 11:32:50.086380 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9840 11:32:50.092918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9841 11:32:50.096178 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9842 11:32:50.099630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9843 11:32:50.105964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9844 11:32:50.109356 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9845 11:32:50.115981 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9846 11:32:50.119297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9847 11:32:50.126026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9848 11:32:50.129546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9849 11:32:50.135681 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9850 11:32:50.139111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9851 11:32:50.142722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9852 11:32:50.149031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9853 11:32:50.152690 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9854 11:32:50.159001 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9855 11:32:50.162310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9856 11:32:50.165995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9857 11:32:50.172367 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9858 11:32:50.175832 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9859 11:32:50.182377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9860 11:32:50.185847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9861 11:32:50.188712 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9862 11:32:50.195437 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9863 11:32:50.198989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9864 11:32:50.205607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9865 11:32:50.208692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9866 11:32:50.211993 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9867 11:32:50.218515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9868 11:32:50.222338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9869 11:32:50.228419 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9870 11:32:50.232155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9871 11:32:50.238439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9872 11:32:50.241639 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9873 11:32:50.245022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9874 11:32:50.251884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9875 11:32:50.255285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9876 11:32:50.261873 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9877 11:32:50.264726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9878 11:32:50.268719 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9879 11:32:50.275014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9880 11:32:50.278147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9881 11:32:50.284507 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9882 11:32:50.287836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9883 11:32:50.291301 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9884 11:32:50.297918 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9885 11:32:50.301368 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9886 11:32:50.308031 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9887 11:32:50.311206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9888 11:32:50.317509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9889 11:32:50.321247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9890 11:32:50.324497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9891 11:32:50.330757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9892 11:32:50.334316 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9893 11:32:50.340828 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9894 11:32:50.344299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9895 11:32:50.347490 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9896 11:32:50.354325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9897 11:32:50.357274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9898 11:32:50.364100 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9899 11:32:50.367080 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9900 11:32:50.373916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9901 11:32:50.376910 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9902 11:32:50.383584 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9903 11:32:50.386706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9904 11:32:50.390164 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9905 11:32:50.396852 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9906 11:32:50.399986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9907 11:32:50.406818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9908 11:32:50.410224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9909 11:32:50.416511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9910 11:32:50.419974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9911 11:32:50.426968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9912 11:32:50.429841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9913 11:32:50.433326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9914 11:32:50.439948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9915 11:32:50.443288 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9916 11:32:50.449977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9917 11:32:50.452817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9918 11:32:50.459609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9919 11:32:50.462733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9920 11:32:50.469357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9921 11:32:50.473349 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9922 11:32:50.475946 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9923 11:32:50.482539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9924 11:32:50.485779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9925 11:32:50.492521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9926 11:32:50.496039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9927 11:32:50.502444 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9928 11:32:50.505612 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9929 11:32:50.512381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9930 11:32:50.515495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9931 11:32:50.518935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9932 11:32:50.525882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9933 11:32:50.528923 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9934 11:32:50.535291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9935 11:32:50.538740 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9936 11:32:50.545603 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9937 11:32:50.548551 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9938 11:32:50.552245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9939 11:32:50.558886 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9940 11:32:50.562335 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9941 11:32:50.569027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9942 11:32:50.572058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9943 11:32:50.578311 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9944 11:32:50.581736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9945 11:32:50.588588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9946 11:32:50.591801 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9947 11:32:50.595386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9948 11:32:50.601576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9949 11:32:50.605235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9950 11:32:50.611861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9951 11:32:50.615452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9952 11:32:50.621437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9953 11:32:50.624927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9954 11:32:50.631301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9955 11:32:50.634717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9956 11:32:50.640992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9957 11:32:50.644447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9958 11:32:50.650956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9959 11:32:50.654400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9960 11:32:50.660926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9961 11:32:50.664548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9962 11:32:50.667756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9963 11:32:50.674161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9964 11:32:50.677456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9965 11:32:50.683858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9966 11:32:50.687307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9967 11:32:50.693676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9968 11:32:50.697381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9969 11:32:50.703936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9970 11:32:50.710459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9971 11:32:50.713645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9972 11:32:50.720569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9973 11:32:50.724162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9974 11:32:50.730081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9975 11:32:50.733808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9976 11:32:50.740314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9977 11:32:50.743603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9978 11:32:50.749951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9979 11:32:50.753713 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9980 11:32:50.756232 INFO: [APUAPC] vio 0
9981 11:32:50.759698 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9982 11:32:50.763050 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9983 11:32:50.766293 INFO: [APUAPC] D0_APC_0: 0x400510
9984 11:32:50.769848 INFO: [APUAPC] D0_APC_1: 0x0
9985 11:32:50.773216 INFO: [APUAPC] D0_APC_2: 0x1540
9986 11:32:50.776645 INFO: [APUAPC] D0_APC_3: 0x0
9987 11:32:50.779562 INFO: [APUAPC] D1_APC_0: 0xffffffff
9988 11:32:50.783341 INFO: [APUAPC] D1_APC_1: 0xffffffff
9989 11:32:50.786687 INFO: [APUAPC] D1_APC_2: 0x3fffff
9990 11:32:50.789949 INFO: [APUAPC] D1_APC_3: 0x0
9991 11:32:50.792657 INFO: [APUAPC] D2_APC_0: 0xffffffff
9992 11:32:50.796447 INFO: [APUAPC] D2_APC_1: 0xffffffff
9993 11:32:50.799599 INFO: [APUAPC] D2_APC_2: 0x3fffff
9994 11:32:50.802759 INFO: [APUAPC] D2_APC_3: 0x0
9995 11:32:50.805983 INFO: [APUAPC] D3_APC_0: 0xffffffff
9996 11:32:50.809339 INFO: [APUAPC] D3_APC_1: 0xffffffff
9997 11:32:50.812800 INFO: [APUAPC] D3_APC_2: 0x3fffff
9998 11:32:50.816103 INFO: [APUAPC] D3_APC_3: 0x0
9999 11:32:50.819252 INFO: [APUAPC] D4_APC_0: 0xffffffff
10000 11:32:50.822531 INFO: [APUAPC] D4_APC_1: 0xffffffff
10001 11:32:50.825615 INFO: [APUAPC] D4_APC_2: 0x3fffff
10002 11:32:50.829209 INFO: [APUAPC] D4_APC_3: 0x0
10003 11:32:50.832588 INFO: [APUAPC] D5_APC_0: 0xffffffff
10004 11:32:50.835779 INFO: [APUAPC] D5_APC_1: 0xffffffff
10005 11:32:50.839032 INFO: [APUAPC] D5_APC_2: 0x3fffff
10006 11:32:50.842421 INFO: [APUAPC] D5_APC_3: 0x0
10007 11:32:50.845966 INFO: [APUAPC] D6_APC_0: 0xffffffff
10008 11:32:50.849089 INFO: [APUAPC] D6_APC_1: 0xffffffff
10009 11:32:50.852523 INFO: [APUAPC] D6_APC_2: 0x3fffff
10010 11:32:50.855616 INFO: [APUAPC] D6_APC_3: 0x0
10011 11:32:50.858730 INFO: [APUAPC] D7_APC_0: 0xffffffff
10012 11:32:50.862306 INFO: [APUAPC] D7_APC_1: 0xffffffff
10013 11:32:50.865295 INFO: [APUAPC] D7_APC_2: 0x3fffff
10014 11:32:50.868834 INFO: [APUAPC] D7_APC_3: 0x0
10015 11:32:50.871899 INFO: [APUAPC] D8_APC_0: 0xffffffff
10016 11:32:50.875336 INFO: [APUAPC] D8_APC_1: 0xffffffff
10017 11:32:50.878722 INFO: [APUAPC] D8_APC_2: 0x3fffff
10018 11:32:50.881774 INFO: [APUAPC] D8_APC_3: 0x0
10019 11:32:50.885155 INFO: [APUAPC] D9_APC_0: 0xffffffff
10020 11:32:50.888592 INFO: [APUAPC] D9_APC_1: 0xffffffff
10021 11:32:50.891999 INFO: [APUAPC] D9_APC_2: 0x3fffff
10022 11:32:50.894823 INFO: [APUAPC] D9_APC_3: 0x0
10023 11:32:50.898634 INFO: [APUAPC] D10_APC_0: 0xffffffff
10024 11:32:50.901619 INFO: [APUAPC] D10_APC_1: 0xffffffff
10025 11:32:50.904959 INFO: [APUAPC] D10_APC_2: 0x3fffff
10026 11:32:50.908377 INFO: [APUAPC] D10_APC_3: 0x0
10027 11:32:50.911784 INFO: [APUAPC] D11_APC_0: 0xffffffff
10028 11:32:50.915179 INFO: [APUAPC] D11_APC_1: 0xffffffff
10029 11:32:50.918307 INFO: [APUAPC] D11_APC_2: 0x3fffff
10030 11:32:50.921599 INFO: [APUAPC] D11_APC_3: 0x0
10031 11:32:50.924805 INFO: [APUAPC] D12_APC_0: 0xffffffff
10032 11:32:50.927925 INFO: [APUAPC] D12_APC_1: 0xffffffff
10033 11:32:50.931684 INFO: [APUAPC] D12_APC_2: 0x3fffff
10034 11:32:50.934808 INFO: [APUAPC] D12_APC_3: 0x0
10035 11:32:50.938193 INFO: [APUAPC] D13_APC_0: 0xffffffff
10036 11:32:50.941299 INFO: [APUAPC] D13_APC_1: 0xffffffff
10037 11:32:50.944828 INFO: [APUAPC] D13_APC_2: 0x3fffff
10038 11:32:50.947779 INFO: [APUAPC] D13_APC_3: 0x0
10039 11:32:50.951864 INFO: [APUAPC] D14_APC_0: 0xffffffff
10040 11:32:50.954900 INFO: [APUAPC] D14_APC_1: 0xffffffff
10041 11:32:50.958367 INFO: [APUAPC] D14_APC_2: 0x3fffff
10042 11:32:50.961046 INFO: [APUAPC] D14_APC_3: 0x0
10043 11:32:50.964418 INFO: [APUAPC] D15_APC_0: 0xffffffff
10044 11:32:50.968258 INFO: [APUAPC] D15_APC_1: 0xffffffff
10045 11:32:50.971132 INFO: [APUAPC] D15_APC_2: 0x3fffff
10046 11:32:50.974785 INFO: [APUAPC] D15_APC_3: 0x0
10047 11:32:50.977906 INFO: [APUAPC] APC_CON: 0x4
10048 11:32:50.981242 INFO: [NOCDAPC] D0_APC_0: 0x0
10049 11:32:50.981320 INFO: [NOCDAPC] D0_APC_1: 0x0
10050 11:32:50.984447 INFO: [NOCDAPC] D1_APC_0: 0x0
10051 11:32:50.987910 INFO: [NOCDAPC] D1_APC_1: 0xfff
10052 11:32:50.991167 INFO: [NOCDAPC] D2_APC_0: 0x0
10053 11:32:50.994229 INFO: [NOCDAPC] D2_APC_1: 0xfff
10054 11:32:50.997677 INFO: [NOCDAPC] D3_APC_0: 0x0
10055 11:32:51.001179 INFO: [NOCDAPC] D3_APC_1: 0xfff
10056 11:32:51.004080 INFO: [NOCDAPC] D4_APC_0: 0x0
10057 11:32:51.007478 INFO: [NOCDAPC] D4_APC_1: 0xfff
10058 11:32:51.011106 INFO: [NOCDAPC] D5_APC_0: 0x0
10059 11:32:51.014173 INFO: [NOCDAPC] D5_APC_1: 0xfff
10060 11:32:51.014249 INFO: [NOCDAPC] D6_APC_0: 0x0
10061 11:32:51.017587 INFO: [NOCDAPC] D6_APC_1: 0xfff
10062 11:32:51.020769 INFO: [NOCDAPC] D7_APC_0: 0x0
10063 11:32:51.024132 INFO: [NOCDAPC] D7_APC_1: 0xfff
10064 11:32:51.027268 INFO: [NOCDAPC] D8_APC_0: 0x0
10065 11:32:51.030399 INFO: [NOCDAPC] D8_APC_1: 0xfff
10066 11:32:51.034150 INFO: [NOCDAPC] D9_APC_0: 0x0
10067 11:32:51.037305 INFO: [NOCDAPC] D9_APC_1: 0xfff
10068 11:32:51.040540 INFO: [NOCDAPC] D10_APC_0: 0x0
10069 11:32:51.043772 INFO: [NOCDAPC] D10_APC_1: 0xfff
10070 11:32:51.047189 INFO: [NOCDAPC] D11_APC_0: 0x0
10071 11:32:51.050528 INFO: [NOCDAPC] D11_APC_1: 0xfff
10072 11:32:51.053783 INFO: [NOCDAPC] D12_APC_0: 0x0
10073 11:32:51.056839 INFO: [NOCDAPC] D12_APC_1: 0xfff
10074 11:32:51.056927 INFO: [NOCDAPC] D13_APC_0: 0x0
10075 11:32:51.060613 INFO: [NOCDAPC] D13_APC_1: 0xfff
10076 11:32:51.064012 INFO: [NOCDAPC] D14_APC_0: 0x0
10077 11:32:51.067329 INFO: [NOCDAPC] D14_APC_1: 0xfff
10078 11:32:51.070542 INFO: [NOCDAPC] D15_APC_0: 0x0
10079 11:32:51.073866 INFO: [NOCDAPC] D15_APC_1: 0xfff
10080 11:32:51.077285 INFO: [NOCDAPC] APC_CON: 0x4
10081 11:32:51.080604 INFO: [APUAPC] set_apusys_apc done
10082 11:32:51.083460 INFO: [DEVAPC] devapc_init done
10083 11:32:51.086888 INFO: GICv3 without legacy support detected.
10084 11:32:51.090193 INFO: ARM GICv3 driver initialized in EL3
10085 11:32:51.097012 INFO: Maximum SPI INTID supported: 639
10086 11:32:51.099852 INFO: BL31: Initializing runtime services
10087 11:32:51.106742 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10088 11:32:51.106835 INFO: SPM: enable CPC mode
10089 11:32:51.113490 INFO: mcdi ready for mcusys-off-idle and system suspend
10090 11:32:51.116458 INFO: BL31: Preparing for EL3 exit to normal world
10091 11:32:51.120015 INFO: Entry point address = 0x80000000
10092 11:32:51.123303 INFO: SPSR = 0x8
10093 11:32:51.129015
10094 11:32:51.129078
10095 11:32:51.129143
10096 11:32:51.132460 Starting depthcharge on Spherion...
10097 11:32:51.132526
10098 11:32:51.132579 Wipe memory regions:
10099 11:32:51.132642
10100 11:32:51.133284 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10101 11:32:51.133409 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10102 11:32:51.133510 Setting prompt string to ['asurada:']
10103 11:32:51.133601 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10104 11:32:51.135697 [0x00000040000000, 0x00000054600000)
10105 11:32:51.257961
10106 11:32:51.258086 [0x00000054660000, 0x00000080000000)
10107 11:32:51.519204
10108 11:32:51.519751 [0x000000821a7280, 0x000000ffe64000)
10109 11:32:52.263797
10110 11:32:52.264240 [0x00000100000000, 0x00000240000000)
10111 11:32:54.153580
10112 11:32:54.156661 Initializing XHCI USB controller at 0x11200000.
10113 11:32:55.195011
10114 11:32:55.197920 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10115 11:32:55.198016
10116 11:32:55.198100
10117 11:32:55.198389 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 11:32:55.198488 Sending line: 'tftpboot 192.168.201.1 14864571/tftp-deploy-y53ldle6/kernel/image.itb 14864571/tftp-deploy-y53ldle6/kernel/cmdline '
10120 11:32:55.298966 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 11:32:55.299072 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:15)
10122 11:32:55.302969 asurada: tftpboot 192.168.201.1 14864571/tftp-deploy-y53ldle6/kernel/image.itp-deploy-y53ldle6/kernel/cmdline
10123 11:32:55.303068
10124 11:32:55.303155 Waiting for link
10125 11:32:55.461275
10126 11:32:55.461385 R8152: Initializing
10127 11:32:55.461450
10128 11:32:55.464760 Version 6 (ocp_data = 5c30)
10129 11:32:55.464831
10130 11:32:55.467748 R8152: Done initializing
10131 11:32:55.467816
10132 11:32:55.467903 Adding net device
10133 11:32:57.373836
10134 11:32:57.373947 done.
10135 11:32:57.374007
10136 11:32:57.374062 MAC: 00:e0:4c:68:02:81
10137 11:32:57.374118
10138 11:32:57.377304 Sending DHCP discover... done.
10139 11:32:57.377375
10140 11:32:57.380481 Waiting for reply... done.
10141 11:32:57.380552
10142 11:32:57.384021 Sending DHCP request... done.
10143 11:32:57.384089
10144 11:32:57.384144 Waiting for reply... done.
10145 11:32:57.384201
10146 11:32:57.387660 My ip is 192.168.201.14
10147 11:32:57.387724
10148 11:32:57.390526 The DHCP server ip is 192.168.201.1
10149 11:32:57.390594
10150 11:32:57.393586 TFTP server IP predefined by user: 192.168.201.1
10151 11:32:57.393655
10152 11:32:57.400181 Bootfile predefined by user: 14864571/tftp-deploy-y53ldle6/kernel/image.itb
10153 11:32:57.400256
10154 11:32:57.403706 Sending tftp read request... done.
10155 11:32:57.403771
10156 11:32:57.407018 Waiting for the transfer...
10157 11:32:57.409960
10158 11:32:57.957391 00000000 ################################################################
10159 11:32:57.957526
10160 11:32:58.507203 00080000 ################################################################
10161 11:32:58.507362
10162 11:32:59.071682 00100000 ################################################################
10163 11:32:59.071796
10164 11:32:59.640514 00180000 ################################################################
10165 11:32:59.640638
10166 11:33:00.190014 00200000 ################################################################
10167 11:33:00.190129
10168 11:33:00.743865 00280000 ################################################################
10169 11:33:00.743981
10170 11:33:01.295682 00300000 ################################################################
10171 11:33:01.295801
10172 11:33:01.845346 00380000 ################################################################
10173 11:33:01.845481
10174 11:33:02.391817 00400000 ################################################################
10175 11:33:02.391930
10176 11:33:02.937882 00480000 ################################################################
10177 11:33:02.938000
10178 11:33:03.488869 00500000 ################################################################
10179 11:33:03.488983
10180 11:33:04.052736 00580000 ################################################################
10181 11:33:04.052857
10182 11:33:04.605665 00600000 ################################################################
10183 11:33:04.605788
10184 11:33:05.154213 00680000 ################################################################
10185 11:33:05.154337
10186 11:33:05.717375 00700000 ################################################################
10187 11:33:05.717495
10188 11:33:06.258908 00780000 ################################################################
10189 11:33:06.259031
10190 11:33:06.803362 00800000 ################################################################
10191 11:33:06.803520
10192 11:33:07.377020 00880000 ################################################################
10193 11:33:07.377142
10194 11:33:07.925752 00900000 ################################################################
10195 11:33:07.925875
10196 11:33:08.467576 00980000 ################################################################
10197 11:33:08.467701
10198 11:33:09.020257 00a00000 ################################################################
10199 11:33:09.020383
10200 11:33:09.615602 00a80000 ################################################################
10201 11:33:09.615730
10202 11:33:10.284556 00b00000 ################################################################
10203 11:33:10.285175
10204 11:33:10.968955 00b80000 ################################################################
10205 11:33:10.969395
10206 11:33:11.627843 00c00000 ################################################################
10207 11:33:11.627958
10208 11:33:12.200843 00c80000 ################################################################
10209 11:33:12.200980
10210 11:33:12.759931 00d00000 ################################################################
10211 11:33:12.760045
10212 11:33:13.376854 00d80000 ################################################################
10213 11:33:13.376979
10214 11:33:13.960883 00e00000 ################################################################
10215 11:33:13.961370
10216 11:33:14.585005 00e80000 ################################################################
10217 11:33:14.585120
10218 11:33:15.198080 00f00000 ################################################################
10219 11:33:15.198582
10220 11:33:15.906132 00f80000 ################################################################
10221 11:33:15.906655
10222 11:33:16.590253 01000000 ################################################################
10223 11:33:16.590471
10224 11:33:17.289866 01080000 ################################################################
10225 11:33:17.290329
10226 11:33:18.000229 01100000 ################################################################
10227 11:33:18.000699
10228 11:33:18.663784 01180000 ################################################################
10229 11:33:18.664252
10230 11:33:19.288652 01200000 ################################################################
10231 11:33:19.288831
10232 11:33:20.002657 01280000 ################################################################
10233 11:33:20.003116
10234 11:33:20.716922 01300000 ################################################################
10235 11:33:20.717449
10236 11:33:21.429885 01380000 ################################################################
10237 11:33:21.430357
10238 11:33:22.081689 01400000 ################################################################
10239 11:33:22.082161
10240 11:33:22.722989 01480000 ################################################################
10241 11:33:22.723115
10242 11:33:23.345406 01500000 ################################################################
10243 11:33:23.345979
10244 11:33:24.004767 01580000 ################################################################
10245 11:33:24.004894
10246 11:33:24.690989 01600000 ################################################################
10247 11:33:24.691488
10248 11:33:25.328642 01680000 ################################################################
10249 11:33:25.328778
10250 11:33:25.964182 01700000 ################################################################
10251 11:33:25.964301
10252 11:33:26.583936 01780000 ################################################################
10253 11:33:26.584050
10254 11:33:27.206685 01800000 ################################################################
10255 11:33:27.206814
10256 11:33:27.751818 01880000 ################################################################
10257 11:33:27.751942
10258 11:33:28.312208 01900000 ################################################################
10259 11:33:28.312338
10260 11:33:28.964270 01980000 ################################################################
10261 11:33:28.964793
10262 11:33:29.657802 01a00000 ################################################################
10263 11:33:29.658253
10264 11:33:30.321876 01a80000 ################################################################
10265 11:33:30.322498
10266 11:33:30.996602 01b00000 ################################################################
10267 11:33:30.996949
10268 11:33:31.648544 01b80000 ################################################################
10269 11:33:31.648991
10270 11:33:32.317317 01c00000 ################################################################
10271 11:33:32.317433
10272 11:33:32.874806 01c80000 ################################################################
10273 11:33:32.874986
10274 11:33:33.547011 01d00000 ################################################################
10275 11:33:33.547756
10276 11:33:34.234207 01d80000 ################################################################
10277 11:33:34.234678
10278 11:33:34.906225 01e00000 ################################################################
10279 11:33:34.906682
10280 11:33:35.595572 01e80000 ################################################################
10281 11:33:35.596038
10282 11:33:36.208495 01f00000 ################################################################
10283 11:33:36.208612
10284 11:33:36.884052 01f80000 ################################################################
10285 11:33:36.884540
10286 11:33:37.597724 02000000 ################################################################
10287 11:33:37.598178
10288 11:33:38.134050 02080000 ######################################################## done.
10289 11:33:38.134510
10290 11:33:38.137892 The bootfile was 34531322 bytes long.
10291 11:33:38.138279
10292 11:33:38.140787 Sending tftp read request... done.
10293 11:33:38.141171
10294 11:33:38.147231 Waiting for the transfer...
10295 11:33:38.147704
10296 11:33:38.147999 00000000 # done.
10297 11:33:38.148278
10298 11:33:38.153858 Command line loaded dynamically from TFTP file: 14864571/tftp-deploy-y53ldle6/kernel/cmdline
10299 11:33:38.157333
10300 11:33:38.170872 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10301 11:33:38.171354
10302 11:33:38.171719 Loading FIT.
10303 11:33:38.172001
10304 11:33:38.173477 Image ramdisk-1 has 21363744 bytes.
10305 11:33:38.173870
10306 11:33:38.176914 Image fdt-1 has 47258 bytes.
10307 11:33:38.177301
10308 11:33:38.179989 Image kernel-1 has 13118294 bytes.
10309 11:33:38.180379
10310 11:33:38.186720 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10311 11:33:38.187108
10312 11:33:38.206406 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10313 11:33:38.206880
10314 11:33:38.210103 Choosing best match conf-1 for compat google,spherion-rev2.
10315 11:33:38.215493
10316 11:33:38.219065 Connected to device vid:did:rid of 1ae0:0028:00
10317 11:33:38.226187
10318 11:33:38.230146 tpm_get_response: command 0x17b, return code 0x0
10319 11:33:38.230618
10320 11:33:38.236341 ec_init: CrosEC protocol v3 supported (256, 248)
10321 11:33:38.236804
10322 11:33:38.239404 tpm_cleanup: add release locality here.
10323 11:33:38.239910
10324 11:33:38.242888 Shutting down all USB controllers.
10325 11:33:38.243278
10326 11:33:38.246342 Removing current net device
10327 11:33:38.246822
10328 11:33:38.249458 Exiting depthcharge with code 4 at timestamp: 76624454
10329 11:33:38.249848
10330 11:33:38.255978 LZMA decompressing kernel-1 to 0x821a6718
10331 11:33:38.256368
10332 11:33:38.259305 LZMA decompressing kernel-1 to 0x40000000
10333 11:33:39.873487
10334 11:33:39.873613 jumping to kernel
10335 11:33:39.874084 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10336 11:33:39.874179 start: 2.2.5 auto-login-action (timeout 00:03:31) [common]
10337 11:33:39.874247 Setting prompt string to ['Linux version [0-9]']
10338 11:33:39.874309 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10339 11:33:39.874376 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10340 11:33:39.954057
10341 11:33:39.957661 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10342 11:33:39.960824 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10343 11:33:39.960915 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10344 11:33:39.960982 Setting prompt string to []
10345 11:33:39.961056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10346 11:33:39.961122 Using line separator: #'\n'#
10347 11:33:39.961176 No login prompt set.
10348 11:33:39.961231 Parsing kernel messages
10349 11:33:39.961282 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10350 11:33:39.961374 [login-action] Waiting for messages, (timeout 00:03:31)
10351 11:33:39.961433 Waiting using forced prompt support (timeout 00:01:45)
10352 11:33:39.980672 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10353 11:33:39.983412 [ 0.000000] random: crng init done
10354 11:33:39.986980 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10355 11:33:39.990135 [ 0.000000] efi: UEFI not found.
10356 11:33:40.000101 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10357 11:33:40.006607 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10358 11:33:40.016667 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10359 11:33:40.025987 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10360 11:33:40.032735 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10361 11:33:40.039160 [ 0.000000] printk: bootconsole [mtk8250] enabled
10362 11:33:40.045821 [ 0.000000] NUMA: No NUMA configuration found
10363 11:33:40.052964 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10364 11:33:40.055700 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10365 11:33:40.059026 [ 0.000000] Zone ranges:
10366 11:33:40.065583 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10367 11:33:40.068922 [ 0.000000] DMA32 empty
10368 11:33:40.075422 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10369 11:33:40.078876 [ 0.000000] Movable zone start for each node
10370 11:33:40.082439 [ 0.000000] Early memory node ranges
10371 11:33:40.088553 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10372 11:33:40.095278 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10373 11:33:40.101715 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10374 11:33:40.108383 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10375 11:33:40.114739 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10376 11:33:40.121577 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10377 11:33:40.178284 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10378 11:33:40.184962 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10379 11:33:40.191750 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10380 11:33:40.194683 [ 0.000000] psci: probing for conduit method from DT.
10381 11:33:40.201533 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10382 11:33:40.204525 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10383 11:33:40.210902 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10384 11:33:40.214450 [ 0.000000] psci: SMC Calling Convention v1.2
10385 11:33:40.220954 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10386 11:33:40.224155 [ 0.000000] Detected VIPT I-cache on CPU0
10387 11:33:40.230832 [ 0.000000] CPU features: detected: GIC system register CPU interface
10388 11:33:40.237210 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10389 11:33:40.243846 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10390 11:33:40.250299 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10391 11:33:40.260292 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10392 11:33:40.267217 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10393 11:33:40.270719 [ 0.000000] alternatives: applying boot alternatives
10394 11:33:40.277358 [ 0.000000] Fallback order for Node 0: 0
10395 11:33:40.284004 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10396 11:33:40.287180 [ 0.000000] Policy zone: Normal
10397 11:33:40.300421 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10398 11:33:40.310175 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10399 11:33:40.322628 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10400 11:33:40.332386 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10401 11:33:40.339215 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10402 11:33:40.343167 <6>[ 0.000000] software IO TLB: area num 8.
10403 11:33:40.399551 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10404 11:33:40.549113 <6>[ 0.000000] Memory: 7943196K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 409572K reserved, 32768K cma-reserved)
10405 11:33:40.556002 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10406 11:33:40.562709 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10407 11:33:40.566024 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10408 11:33:40.572585 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10409 11:33:40.578970 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10410 11:33:40.582591 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10411 11:33:40.592700 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10412 11:33:40.599040 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10413 11:33:40.605712 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10414 11:33:40.612197 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10415 11:33:40.615588 <6>[ 0.000000] GICv3: 608 SPIs implemented
10416 11:33:40.618992 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10417 11:33:40.625313 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10418 11:33:40.628496 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10419 11:33:40.635366 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10420 11:33:40.648573 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10421 11:33:40.661791 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10422 11:33:40.668459 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10423 11:33:40.675802 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10424 11:33:40.689414 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10425 11:33:40.695334 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10426 11:33:40.702337 <6>[ 0.009176] Console: colour dummy device 80x25
10427 11:33:40.712165 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10428 11:33:40.718795 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10429 11:33:40.722229 <6>[ 0.029286] LSM: Security Framework initializing
10430 11:33:40.728598 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 11:33:40.738735 <6>[ 0.042054] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 11:33:40.748647 <6>[ 0.051470] cblist_init_generic: Setting adjustable number of callback queues.
10433 11:33:40.752115 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10434 11:33:40.761715 <6>[ 0.065248] cblist_init_generic: Setting adjustable number of callback queues.
10435 11:33:40.768376 <6>[ 0.072676] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 11:33:40.771627 <6>[ 0.079078] rcu: Hierarchical SRCU implementation.
10437 11:33:40.777957 <6>[ 0.084117] rcu: Max phase no-delay instances is 1000.
10438 11:33:40.784741 <6>[ 0.091138] EFI services will not be available.
10439 11:33:40.788057 <6>[ 0.096124] smp: Bringing up secondary CPUs ...
10440 11:33:40.796664 <6>[ 0.101177] Detected VIPT I-cache on CPU1
10441 11:33:40.803090 <6>[ 0.101240] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10442 11:33:40.809791 <6>[ 0.101264] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10443 11:33:40.813103 <6>[ 0.101579] Detected VIPT I-cache on CPU2
10444 11:33:40.822991 <6>[ 0.101624] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10445 11:33:40.829404 <6>[ 0.101640] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10446 11:33:40.833263 <6>[ 0.101899] Detected VIPT I-cache on CPU3
10447 11:33:40.839305 <6>[ 0.101947] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10448 11:33:40.845810 <6>[ 0.101961] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10449 11:33:40.852467 <6>[ 0.102268] CPU features: detected: Spectre-v4
10450 11:33:40.856125 <6>[ 0.102274] CPU features: detected: Spectre-BHB
10451 11:33:40.859049 <6>[ 0.102280] Detected PIPT I-cache on CPU4
10452 11:33:40.869261 <6>[ 0.102339] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10453 11:33:40.875338 <6>[ 0.102356] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10454 11:33:40.878821 <6>[ 0.102648] Detected PIPT I-cache on CPU5
10455 11:33:40.885575 <6>[ 0.102711] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10456 11:33:40.891857 <6>[ 0.102727] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10457 11:33:40.895901 <6>[ 0.103010] Detected PIPT I-cache on CPU6
10458 11:33:40.905176 <6>[ 0.103076] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10459 11:33:40.911695 <6>[ 0.103091] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10460 11:33:40.915134 <6>[ 0.103390] Detected PIPT I-cache on CPU7
10461 11:33:40.922261 <6>[ 0.103455] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10462 11:33:40.928554 <6>[ 0.103471] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10463 11:33:40.931361 <6>[ 0.103518] smp: Brought up 1 node, 8 CPUs
10464 11:33:40.938365 <6>[ 0.244954] SMP: Total of 8 processors activated.
10465 11:33:40.944859 <6>[ 0.249875] CPU features: detected: 32-bit EL0 Support
10466 11:33:40.951314 <6>[ 0.255238] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10467 11:33:40.958115 <6>[ 0.264039] CPU features: detected: Common not Private translations
10468 11:33:40.964333 <6>[ 0.270555] CPU features: detected: CRC32 instructions
10469 11:33:40.971063 <6>[ 0.275906] CPU features: detected: RCpc load-acquire (LDAPR)
10470 11:33:40.974349 <6>[ 0.281903] CPU features: detected: LSE atomic instructions
10471 11:33:40.980809 <6>[ 0.287721] CPU features: detected: Privileged Access Never
10472 11:33:40.987929 <6>[ 0.293500] CPU features: detected: RAS Extension Support
10473 11:33:40.993904 <6>[ 0.299135] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10474 11:33:40.997292 <6>[ 0.306353] CPU: All CPU(s) started at EL2
10475 11:33:41.004993 <6>[ 0.310669] alternatives: applying system-wide alternatives
10476 11:33:41.014509 <6>[ 0.321496] devtmpfs: initialized
10477 11:33:41.027305 <6>[ 0.330369] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10478 11:33:41.036832 <6>[ 0.340330] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10479 11:33:41.043960 <6>[ 0.348569] pinctrl core: initialized pinctrl subsystem
10480 11:33:41.046618 <6>[ 0.355238] DMI not present or invalid.
10481 11:33:41.053144 <6>[ 0.359651] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10482 11:33:41.063013 <6>[ 0.366548] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10483 11:33:41.070565 <6>[ 0.374132] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10484 11:33:41.079758 <6>[ 0.382367] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10485 11:33:41.083219 <6>[ 0.390613] audit: initializing netlink subsys (disabled)
10486 11:33:41.093328 <5>[ 0.396306] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10487 11:33:41.099865 <6>[ 0.397019] thermal_sys: Registered thermal governor 'step_wise'
10488 11:33:41.106246 <6>[ 0.404270] thermal_sys: Registered thermal governor 'power_allocator'
10489 11:33:41.109567 <6>[ 0.410523] cpuidle: using governor menu
10490 11:33:41.116038 <6>[ 0.421482] NET: Registered PF_QIPCRTR protocol family
10491 11:33:41.122921 <6>[ 0.426969] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10492 11:33:41.129209 <6>[ 0.434071] ASID allocator initialised with 32768 entries
10493 11:33:41.132999 <6>[ 0.440652] Serial: AMBA PL011 UART driver
10494 11:33:41.143147 <4>[ 0.450020] Trying to register duplicate clock ID: 134
10495 11:33:41.202845 <6>[ 0.513170] KASLR enabled
10496 11:33:41.217618 <6>[ 0.520797] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10497 11:33:41.223724 <6>[ 0.527809] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10498 11:33:41.230375 <6>[ 0.534296] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10499 11:33:41.237484 <6>[ 0.541299] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10500 11:33:41.243552 <6>[ 0.547786] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10501 11:33:41.250181 <6>[ 0.554791] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10502 11:33:41.256751 <6>[ 0.561276] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10503 11:33:41.263435 <6>[ 0.568281] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10504 11:33:41.266442 <6>[ 0.575811] ACPI: Interpreter disabled.
10505 11:33:41.275219 <6>[ 0.582260] iommu: Default domain type: Translated
10506 11:33:41.281801 <6>[ 0.587370] iommu: DMA domain TLB invalidation policy: strict mode
10507 11:33:41.285645 <5>[ 0.594019] SCSI subsystem initialized
10508 11:33:41.291897 <6>[ 0.598188] usbcore: registered new interface driver usbfs
10509 11:33:41.298981 <6>[ 0.603919] usbcore: registered new interface driver hub
10510 11:33:41.302152 <6>[ 0.609469] usbcore: registered new device driver usb
10511 11:33:41.308861 <6>[ 0.615578] pps_core: LinuxPPS API ver. 1 registered
10512 11:33:41.318533 <6>[ 0.620773] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10513 11:33:41.321789 <6>[ 0.630116] PTP clock support registered
10514 11:33:41.324983 <6>[ 0.634359] EDAC MC: Ver: 3.0.0
10515 11:33:41.332672 <6>[ 0.639513] FPGA manager framework
10516 11:33:41.339403 <6>[ 0.643200] Advanced Linux Sound Architecture Driver Initialized.
10517 11:33:41.342530 <6>[ 0.649998] vgaarb: loaded
10518 11:33:41.349360 <6>[ 0.653165] clocksource: Switched to clocksource arch_sys_counter
10519 11:33:41.352738 <5>[ 0.659606] VFS: Disk quotas dquot_6.6.0
10520 11:33:41.359504 <6>[ 0.663792] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10521 11:33:41.362529 <6>[ 0.670981] pnp: PnP ACPI: disabled
10522 11:33:41.371172 <6>[ 0.677715] NET: Registered PF_INET protocol family
10523 11:33:41.381007 <6>[ 0.683308] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10524 11:33:41.392266 <6>[ 0.695624] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10525 11:33:41.401923 <6>[ 0.704437] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10526 11:33:41.408243 <6>[ 0.712405] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10527 11:33:41.418605 <6>[ 0.721104] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10528 11:33:41.424741 <6>[ 0.730859] TCP: Hash tables configured (established 65536 bind 65536)
10529 11:33:41.431408 <6>[ 0.737727] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 11:33:41.441106 <6>[ 0.744926] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 11:33:41.448149 <6>[ 0.752625] NET: Registered PF_UNIX/PF_LOCAL protocol family
10532 11:33:41.454773 <6>[ 0.758786] RPC: Registered named UNIX socket transport module.
10533 11:33:41.458089 <6>[ 0.764939] RPC: Registered udp transport module.
10534 11:33:41.464335 <6>[ 0.769871] RPC: Registered tcp transport module.
10535 11:33:41.471133 <6>[ 0.774804] RPC: Registered tcp NFSv4.1 backchannel transport module.
10536 11:33:41.474246 <6>[ 0.781471] PCI: CLS 0 bytes, default 64
10537 11:33:41.477436 <6>[ 0.785800] Unpacking initramfs...
10538 11:33:41.498194 <6>[ 0.801698] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10539 11:33:41.508034 <6>[ 0.810331] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10540 11:33:41.511821 <6>[ 0.819194] kvm [1]: IPA Size Limit: 40 bits
10541 11:33:41.518212 <6>[ 0.823728] kvm [1]: GICv3: no GICV resource entry
10542 11:33:41.521186 <6>[ 0.828750] kvm [1]: disabling GICv2 emulation
10543 11:33:41.527741 <6>[ 0.833436] kvm [1]: GIC system register CPU interface enabled
10544 11:33:41.531232 <6>[ 0.839602] kvm [1]: vgic interrupt IRQ18
10545 11:33:41.537802 <6>[ 0.843955] kvm [1]: VHE mode initialized successfully
10546 11:33:41.544347 <5>[ 0.850371] Initialise system trusted keyrings
10547 11:33:41.550859 <6>[ 0.855173] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10548 11:33:41.559073 <6>[ 0.865291] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10549 11:33:41.565319 <5>[ 0.871717] NFS: Registering the id_resolver key type
10550 11:33:41.568815 <5>[ 0.877030] Key type id_resolver registered
10551 11:33:41.574678 <5>[ 0.881445] Key type id_legacy registered
10552 11:33:41.581041 <6>[ 0.885725] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10553 11:33:41.587732 <6>[ 0.892646] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10554 11:33:41.594523 <6>[ 0.900395] 9p: Installing v9fs 9p2000 file system support
10555 11:33:41.632387 <5>[ 0.938999] Key type asymmetric registered
10556 11:33:41.635550 <5>[ 0.943334] Asymmetric key parser 'x509' registered
10557 11:33:41.645372 <6>[ 0.948476] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10558 11:33:41.648706 <6>[ 0.956087] io scheduler mq-deadline registered
10559 11:33:41.651813 <6>[ 0.960850] io scheduler kyber registered
10560 11:33:41.671322 <6>[ 0.978065] EINJ: ACPI disabled.
10561 11:33:41.704274 <4>[ 1.004543] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 11:33:41.714337 <4>[ 1.015272] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 11:33:41.729702 <6>[ 1.036444] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10564 11:33:41.737452 <6>[ 1.044473] printk: console [ttyS0] disabled
10565 11:33:41.765468 <6>[ 1.069106] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10566 11:33:41.772476 <6>[ 1.078584] printk: console [ttyS0] enabled
10567 11:33:41.776079 <6>[ 1.078584] printk: console [ttyS0] enabled
10568 11:33:41.781936 <6>[ 1.087479] printk: bootconsole [mtk8250] disabled
10569 11:33:41.785208 <6>[ 1.087479] printk: bootconsole [mtk8250] disabled
10570 11:33:41.791941 <6>[ 1.098770] SuperH (H)SCI(F) driver initialized
10571 11:33:41.794937 <6>[ 1.104082] msm_serial: driver initialized
10572 11:33:41.809829 <6>[ 1.113166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10573 11:33:41.819873 <6>[ 1.121719] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10574 11:33:41.826690 <6>[ 1.130261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10575 11:33:41.835842 <6>[ 1.138889] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10576 11:33:41.845687 <6>[ 1.147597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10577 11:33:41.852950 <6>[ 1.156312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10578 11:33:41.862388 <6>[ 1.164853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10579 11:33:41.868775 <6>[ 1.173655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10580 11:33:41.878724 <6>[ 1.182202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10581 11:33:41.891411 <6>[ 1.198363] loop: module loaded
10582 11:33:41.898159 <6>[ 1.204386] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10583 11:33:41.921516 <4>[ 1.227912] mtk-pmic-keys: Failed to locate of_node [id: -1]
10584 11:33:41.927712 <6>[ 1.234834] megasas: 07.719.03.00-rc1
10585 11:33:41.937483 <6>[ 1.244380] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10586 11:33:41.945886 <6>[ 1.252579] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 11:33:41.961921 <6>[ 1.268466] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 11:33:42.021736 <6>[ 1.322011] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10589 11:33:42.420397 <6>[ 1.727537] Freeing initrd memory: 20860K
10590 11:33:42.436940 <6>[ 1.743417] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 11:33:42.447809 <6>[ 1.754498] tun: Universal TUN/TAP device driver, 1.6
10592 11:33:42.451237 <6>[ 1.760568] thunder_xcv, ver 1.0
10593 11:33:42.454480 <6>[ 1.764072] thunder_bgx, ver 1.0
10594 11:33:42.457521 <6>[ 1.767571] nicpf, ver 1.0
10595 11:33:42.467733 <6>[ 1.771596] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 11:33:42.471268 <6>[ 1.779071] hns3: Copyright (c) 2017 Huawei Corporation.
10597 11:33:42.478057 <6>[ 1.784662] hclge is initializing
10598 11:33:42.481276 <6>[ 1.788243] e1000: Intel(R) PRO/1000 Network Driver
10599 11:33:42.487720 <6>[ 1.793373] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 11:33:42.491035 <6>[ 1.799391] e1000e: Intel(R) PRO/1000 Network Driver
10601 11:33:42.498072 <6>[ 1.804606] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 11:33:42.504508 <6>[ 1.810791] igb: Intel(R) Gigabit Ethernet Network Driver
10603 11:33:42.511280 <6>[ 1.816445] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 11:33:42.517799 <6>[ 1.822281] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 11:33:42.524068 <6>[ 1.828799] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 11:33:42.527564 <6>[ 1.835262] sky2: driver version 1.30
10607 11:33:42.534435 <6>[ 1.840190] usbcore: registered new device driver r8152-cfgselector
10608 11:33:42.540787 <6>[ 1.846728] usbcore: registered new interface driver r8152
10609 11:33:42.547285 <6>[ 1.852552] VFIO - User Level meta-driver version: 0.3
10610 11:33:42.553918 <6>[ 1.860775] usbcore: registered new interface driver usb-storage
10611 11:33:42.560833 <6>[ 1.867233] usbcore: registered new device driver onboard-usb-hub
10612 11:33:42.569379 <6>[ 1.876407] mt6397-rtc mt6359-rtc: registered as rtc0
10613 11:33:42.579063 <6>[ 1.881873] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:33:42 UTC (1721216022)
10614 11:33:42.582911 <6>[ 1.891440] i2c_dev: i2c /dev entries driver
10615 11:33:42.596508 <4>[ 1.903501] cpu cpu0: supply cpu not found, using dummy regulator
10616 11:33:42.603174 <4>[ 1.909928] cpu cpu1: supply cpu not found, using dummy regulator
10617 11:33:42.610526 <4>[ 1.916357] cpu cpu2: supply cpu not found, using dummy regulator
10618 11:33:42.616445 <4>[ 1.922756] cpu cpu3: supply cpu not found, using dummy regulator
10619 11:33:42.622744 <4>[ 1.929151] cpu cpu4: supply cpu not found, using dummy regulator
10620 11:33:42.629525 <4>[ 1.935552] cpu cpu5: supply cpu not found, using dummy regulator
10621 11:33:42.636245 <4>[ 1.941958] cpu cpu6: supply cpu not found, using dummy regulator
10622 11:33:42.643433 <4>[ 1.948374] cpu cpu7: supply cpu not found, using dummy regulator
10623 11:33:42.662068 <6>[ 1.969001] cpu cpu0: EM: created perf domain
10624 11:33:42.665121 <6>[ 1.973908] cpu cpu4: EM: created perf domain
10625 11:33:42.672461 <6>[ 1.979525] sdhci: Secure Digital Host Controller Interface driver
10626 11:33:42.679473 <6>[ 1.985957] sdhci: Copyright(c) Pierre Ossman
10627 11:33:42.686216 <6>[ 1.990914] Synopsys Designware Multimedia Card Interface Driver
10628 11:33:42.692575 <6>[ 1.997544] sdhci-pltfm: SDHCI platform and OF driver helper
10629 11:33:42.696275 <6>[ 1.997695] mmc0: CQHCI version 5.10
10630 11:33:42.702183 <6>[ 2.007695] ledtrig-cpu: registered to indicate activity on CPUs
10631 11:33:42.709189 <6>[ 2.014753] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 11:33:42.715361 <6>[ 2.021803] usbcore: registered new interface driver usbhid
10633 11:33:42.719151 <6>[ 2.027625] usbhid: USB HID core driver
10634 11:33:42.725360 <6>[ 2.031833] spi_master spi0: will run message pump with realtime priority
10635 11:33:42.773624 <6>[ 2.073817] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 11:33:42.793224 <6>[ 2.089599] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 11:33:42.795708 <6>[ 2.098252] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10638 11:33:42.803229 <6>[ 2.110263] cros-ec-spi spi0.0: Chrome EC device registered
10639 11:33:42.810353 <6>[ 2.116305] mmc0: Command Queue Engine enabled
10640 11:33:42.817112 <6>[ 2.121059] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10641 11:33:42.820116 <6>[ 2.128679] mmcblk0: mmc0:0001 DA4128 116 GiB
10642 11:33:42.830534 <6>[ 2.137522] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 11:33:42.838259 <6>[ 2.145040] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10644 11:33:42.844800 <6>[ 2.151148] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10645 11:33:42.851362 <6>[ 2.157431] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10646 11:33:42.861175 <6>[ 2.161353] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10647 11:33:42.867754 <6>[ 2.174404] NET: Registered PF_PACKET protocol family
10648 11:33:42.871408 <6>[ 2.179782] 9pnet: Installing 9P2000 support
10649 11:33:42.878214 <5>[ 2.184354] Key type dns_resolver registered
10650 11:33:42.881382 <6>[ 2.189536] registered taskstats version 1
10651 11:33:42.887903 <5>[ 2.193952] Loading compiled-in X.509 certificates
10652 11:33:42.917135 <4>[ 2.217523] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 11:33:42.927178 <4>[ 2.228252] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10654 11:33:42.944726 <6>[ 2.251846] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 11:33:42.951651 <6>[ 2.258700] xhci-mtk 11200000.usb: xHCI Host Controller
10656 11:33:42.958592 <6>[ 2.264218] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10657 11:33:42.968783 <6>[ 2.272079] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10658 11:33:42.975305 <6>[ 2.281521] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10659 11:33:42.981650 <6>[ 2.287693] xhci-mtk 11200000.usb: xHCI Host Controller
10660 11:33:42.988536 <6>[ 2.293189] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10661 11:33:42.995437 <6>[ 2.300843] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10662 11:33:43.001531 <6>[ 2.308702] hub 1-0:1.0: USB hub found
10663 11:33:43.005646 <6>[ 2.312730] hub 1-0:1.0: 1 port detected
10664 11:33:43.014700 <6>[ 2.317035] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 11:33:43.018035 <6>[ 2.325813] hub 2-0:1.0: USB hub found
10666 11:33:43.021763 <6>[ 2.329838] hub 2-0:1.0: 1 port detected
10667 11:33:43.029476 <6>[ 2.336459] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 11:33:43.042990 <6>[ 2.346441] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 11:33:43.052433 <6>[ 2.354829] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 11:33:43.059097 <6>[ 2.363170] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 11:33:43.069194 <6>[ 2.371517] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 11:33:43.076193 <6>[ 2.379857] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 11:33:43.085444 <6>[ 2.388196] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 11:33:43.092016 <6>[ 2.396536] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 11:33:43.101833 <6>[ 2.404875] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 11:33:43.108616 <6>[ 2.413219] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 11:33:43.119743 <6>[ 2.421557] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 11:33:43.125564 <6>[ 2.429896] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 11:33:43.135018 <6>[ 2.438242] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 11:33:43.142504 <6>[ 2.446581] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 11:33:43.151625 <6>[ 2.454920] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 11:33:43.158175 <6>[ 2.463259] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 11:33:43.165158 <6>[ 2.471975] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 11:33:43.172055 <6>[ 2.479141] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 11:33:43.179312 <6>[ 2.485906] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 11:33:43.188655 <6>[ 2.492664] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 11:33:43.195711 <6>[ 2.499599] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 11:33:43.201905 <6>[ 2.506458] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 11:33:43.212154 <6>[ 2.515590] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 11:33:43.221793 <6>[ 2.524712] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 11:33:43.231627 <6>[ 2.534007] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 11:33:43.241511 <6>[ 2.543475] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 11:33:43.251733 <6>[ 2.552946] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 11:33:43.257984 <6>[ 2.562069] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 11:33:43.268390 <6>[ 2.571536] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:33:43.278104 <6>[ 2.580655] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 11:33:43.287699 <6>[ 2.589951] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 11:33:43.297836 <6>[ 2.600111] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 11:33:43.308319 <6>[ 2.612126] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 11:33:43.429852 <6>[ 2.733471] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 11:33:43.583321 <6>[ 2.890521] hub 1-1:1.0: USB hub found
10702 11:33:43.587022 <6>[ 2.894989] hub 1-1:1.0: 4 ports detected
10703 11:33:43.597719 <6>[ 2.904719] hub 1-1:1.0: USB hub found
10704 11:33:43.600805 <6>[ 2.909042] hub 1-1:1.0: 4 ports detected
10705 11:33:43.709930 <6>[ 3.013822] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10706 11:33:43.738109 <6>[ 3.044969] hub 2-1:1.0: USB hub found
10707 11:33:43.740853 <6>[ 3.049540] hub 2-1:1.0: 3 ports detected
10708 11:33:43.753526 <6>[ 3.060777] hub 2-1:1.0: USB hub found
10709 11:33:43.757633 <6>[ 3.065247] hub 2-1:1.0: 3 ports detected
10710 11:33:43.921815 <6>[ 3.225493] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 11:33:44.054276 <6>[ 3.361256] hub 1-1.4:1.0: USB hub found
10712 11:33:44.057506 <6>[ 3.365966] hub 1-1.4:1.0: 2 ports detected
10713 11:33:44.069300 <6>[ 3.376375] hub 1-1.4:1.0: USB hub found
10714 11:33:44.072780 <6>[ 3.380885] hub 1-1.4:1.0: 2 ports detected
10715 11:33:44.141713 <6>[ 3.445563] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10716 11:33:44.250068 <6>[ 3.554089] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10717 11:33:44.286572 <4>[ 3.590487] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10718 11:33:44.296475 <4>[ 3.599634] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10719 11:33:44.331390 <6>[ 3.638526] r8152 2-1.3:1.0 eth0: v1.12.13
10720 11:33:44.381176 <6>[ 3.685288] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10721 11:33:44.577785 <6>[ 3.881479] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10722 11:33:46.075720 <6>[ 5.382961] r8152 2-1.3:1.0 eth0: carrier on
10723 11:33:48.881573 <5>[ 5.405282] Sending DHCP requests .., OK
10724 11:33:48.888401 <6>[ 8.193610] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10725 11:33:48.891835 <6>[ 8.201911] IP-Config: Complete:
10726 11:33:48.905198 <6>[ 8.205446] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10727 11:33:48.911270 <6>[ 8.216158] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10728 11:33:48.921345 <6>[ 8.224777] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10729 11:33:48.924624 <6>[ 8.224786] nameserver0=192.168.201.1
10730 11:33:48.928221 <6>[ 8.236909] clk: Disabling unused clocks
10731 11:33:48.931561 <6>[ 8.242448] ALSA device list:
10732 11:33:48.938279 <6>[ 8.245707] No soundcards found.
10733 11:33:48.946081 <6>[ 8.253355] Freeing unused kernel memory: 8512K
10734 11:33:48.949207 <6>[ 8.258343] Run /init as init process
10735 11:33:48.977740 Starting syslogd: OK
10736 11:33:48.986214 Starting klogd: OK
10737 11:33:48.993501 Running sysctl: OK
10738 11:33:49.002497 Populating /dev using udev: <30>[ 8.309095] udevd[201]: starting version 3.2.9
10739 11:33:49.010059 <27>[ 8.317747] udevd[201]: specified user 'tss' unknown
10740 11:33:49.017043 <27>[ 8.323179] udevd[201]: specified group 'tss' unknown
10741 11:33:49.023420 <30>[ 8.329788] udevd[202]: starting eudev-3.2.9
10742 11:33:49.040419 <27>[ 8.348193] udevd[202]: specified user 'tss' unknown
10743 11:33:49.047165 <27>[ 8.353571] udevd[202]: specified group 'tss' unknown
10744 11:33:49.121928 <6>[ 8.426450] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10745 11:33:49.128578 <6>[ 8.427430] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10746 11:33:49.138958 <6>[ 8.442599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10747 11:33:49.145768 <3>[ 8.444841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:33:49.155133 <6>[ 8.451086] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10749 11:33:49.158422 <6>[ 8.459644] remoteproc remoteproc0: scp is available
10750 11:33:49.168451 <3>[ 8.461474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:33:49.174881 <3>[ 8.461499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:33:49.185115 <3>[ 8.461631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:33:49.191839 <3>[ 8.461636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 11:33:49.201599 <3>[ 8.461640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 11:33:49.207727 <3>[ 8.461655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:33:49.217776 <3>[ 8.461660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:33:49.224351 <3>[ 8.461753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 11:33:49.231134 <3>[ 8.461816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:33:49.241100 <3>[ 8.461821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 11:33:49.248085 <3>[ 8.461827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 11:33:49.257330 <3>[ 8.461861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:33:49.263925 <3>[ 8.461864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 11:33:49.274154 <3>[ 8.461869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:33:49.280218 <3>[ 8.461877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:33:49.290110 <3>[ 8.461885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 11:33:49.297028 <3>[ 8.461916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 11:33:49.307192 <4>[ 8.467620] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10768 11:33:49.310524 <6>[ 8.472451] remoteproc remoteproc0: powering up scp
10769 11:33:49.320289 <6>[ 8.474832] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10770 11:33:49.326735 <6>[ 8.474885] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10771 11:33:49.336541 <6>[ 8.474894] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10772 11:33:49.343076 <6>[ 8.481261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10773 11:33:49.353032 <6>[ 8.488526] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10774 11:33:49.359604 <6>[ 8.488542] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10775 11:33:49.366047 <6>[ 8.496658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10776 11:33:49.372842 <6>[ 8.594513] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10777 11:33:49.379171 <6>[ 8.601814] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10778 11:33:49.385809 <6>[ 8.609840] pci_bus 0000:00: root bus resource [bus 00-ff]
10779 11:33:49.395848 <6>[ 8.618909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10780 11:33:49.402592 <6>[ 8.623979] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10781 11:33:49.412229 <6>[ 8.623982] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10782 11:33:49.419369 <6>[ 8.630502] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10783 11:33:49.425734 <6>[ 8.630531] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10784 11:33:49.432168 <6>[ 8.630536] remoteproc remoteproc0: remote processor scp is now up
10785 11:33:49.441936 <6>[ 8.631535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10786 11:33:49.448646 <6>[ 8.640245] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10787 11:33:49.455299 <6>[ 8.648904] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10788 11:33:49.465806 <6>[ 8.656987] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10789 11:33:49.472563 <4>[ 8.697051] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10790 11:33:49.476231 <6>[ 8.698492] mc: Linux media interface: v0.10
10791 11:33:49.479173 <6>[ 8.699515] pci 0000:00:00.0: supports D1 D2
10792 11:33:49.489552 <4>[ 8.707644] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10793 11:33:49.495846 <6>[ 8.714437] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 11:33:49.502396 <6>[ 8.725488] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10795 11:33:49.512110 <6>[ 8.732454] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10796 11:33:49.519001 <4>[ 8.750561] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10797 11:33:49.525531 <4>[ 8.750561] Fallback method does not support PEC.
10798 11:33:49.532035 <6>[ 8.754508] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10799 11:33:49.538638 <6>[ 8.762150] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10800 11:33:49.545270 <6>[ 8.769615] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10801 11:33:49.555051 <3>[ 8.776976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10802 11:33:49.565287 <6>[ 8.779852] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10803 11:33:49.572150 <6>[ 8.784381] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10804 11:33:49.578222 <3>[ 8.797702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10805 11:33:49.588652 <6>[ 8.800721] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10806 11:33:49.598434 <6>[ 8.817773] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10807 11:33:49.601450 <6>[ 8.823563] pci 0000:01:00.0: supports D1 D2
10808 11:33:49.611359 <6>[ 8.837764] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10809 11:33:49.618044 <6>[ 8.843348] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10810 11:33:49.624842 <6>[ 8.857324] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10811 11:33:49.634495 <6>[ 8.862503] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10812 11:33:49.640962 <6>[ 8.868001] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10813 11:33:49.647719 <6>[ 8.892924] videodev: Linux video capture interface: v2.00
10814 11:33:49.654107 <6>[ 8.899944] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10815 11:33:49.664075 <6>[ 8.899956] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10816 11:33:49.667400 <6>[ 8.930941] Bluetooth: Core ver 2.22
10817 11:33:49.673798 <6>[ 8.937316] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10818 11:33:49.680549 <6>[ 8.946695] NET: Registered PF_BLUETOOTH protocol family
10819 11:33:49.690719 <6>[ 8.954700] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10820 11:33:49.697444 <6>[ 8.960426] Bluetooth: HCI device and connection manager initialized
10821 11:33:49.701024 <6>[ 8.968428] pci 0000:00:00.0: PCI bridge to [bus 01]
10822 11:33:49.707134 <6>[ 8.969805] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10823 11:33:49.720435 <6>[ 8.971581] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10824 11:33:49.726831 <6>[ 8.971683] usbcore: registered new interface driver uvcvideo
10825 11:33:49.730087 <6>[ 8.976441] Bluetooth: HCI socket layer initialized
10826 11:33:49.740171 <6>[ 8.980241] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10827 11:33:49.743488 <6>[ 8.988234] Bluetooth: L2CAP socket layer initialized
10828 11:33:49.749917 <6>[ 8.994041] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10829 11:33:49.756695 <6>[ 9.001809] Bluetooth: SCO socket layer initialized
10830 11:33:49.762856 <6>[ 9.002326] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10831 11:33:49.769917 <6>[ 9.009069] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10832 11:33:49.773092 <6>[ 9.069389] usbcore: registered new interface driver btusb
10833 11:33:49.785959 <4>[ 9.070276] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10834 11:33:49.789791 <3>[ 9.070289] Bluetooth: hci0: Failed to load firmware file (-2)
10835 11:33:49.795963 <3>[ 9.070295] Bluetooth: hci0: Failed to set up firmware (-2)
10836 11:33:49.806405 <4>[ 9.070299] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10837 11:33:49.812378 <6>[ 9.075902] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10838 11:33:49.829701 <5>[ 9.134188] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10839 11:33:49.868168 <5>[ 9.172029] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10840 11:33:49.874066 <5>[ 9.179158] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10841 11:33:49.884053 <4>[ 9.187569] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10842 11:33:49.887579 <6>[ 9.196440] cfg80211: failed to load regulatory.db
10843 11:33:49.928720 <6>[ 9.232963] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10844 11:33:49.935107 <6>[ 9.240455] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10845 11:33:49.960186 <6>[ 9.267187] mt7921e 0000:01:00.0: ASIC revision: 79610010
10846 11:33:50.060417 <6>[ 9.365119] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10847 11:33:50.063864 <6>[ 9.365119]
10848 11:33:50.075706 done
10849 11:33:50.084142 Saving random seed: OK
10850 11:33:50.095313 Starting network: ip: RTNETLINK answers: File exists
10851 11:33:50.098172 FAIL
10852 11:33:50.136036 Starting dropbear sshd: <6>[ 9.443328] NET: Registered PF_INET6 protocol family
10853 11:33:50.142828 <6>[ 9.449625] Segment Routing with IPv6
10854 11:33:50.145961 <6>[ 9.453588] In-situ OAM (IOAM) with IPv6
10855 11:33:50.148709 OK
10856 11:33:50.158089 /bin/sh: can't access tty; job control turned off
10857 11:33:50.159022 Matched prompt #10: / #
10859 11:33:50.159788 Setting prompt string to ['/ #']
10860 11:33:50.160127 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10862 11:33:50.160875 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10863 11:33:50.161236 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
10864 11:33:50.161503 Setting prompt string to ['/ #']
10865 11:33:50.161736 Forcing a shell prompt, looking for ['/ #']
10866 11:33:50.161969 Sending line: ''
10868 11:33:50.212965 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10869 11:33:50.213314 Waiting using forced prompt support (timeout 00:02:30)
10870 11:33:50.218603 / #
10871 11:33:50.219277 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10872 11:33:50.219715 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
10873 11:33:50.220109 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10874 11:33:50.220465 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
10875 11:33:50.220840 end: 2 depthcharge-action (duration 00:01:39) [common]
10876 11:33:50.221211 start: 3 lava-test-retry (timeout 00:01:00) [common]
10877 11:33:50.221587 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10878 11:33:50.221884 Using namespace: common
10879 11:33:50.222177 Sending line: '#'
10881 11:33:50.323518 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10882 11:33:50.367933 / # #<6>[ 9.632338] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10883 11:33:50.368366
10884 11:33:50.368925 Using /lava-14864571
10885 11:33:50.369208 Sending line: 'export SHELL=/bin/sh'
10887 11:33:50.475943 / # export SHELL=/bin/sh
10888 11:33:50.476591 Sending line: '. /lava-14864571/environment'
10890 11:33:50.583258 / # . /lava-14864571/environment
10891 11:33:50.584005 Sending line: '/lava-14864571/bin/lava-test-runner /lava-14864571/0'
10893 11:33:50.684945 Test shell timeout: 10s (minimum of the action and connection timeout)
10894 11:33:50.690338 / # /lava-14864571/bin/lava-test-runner /lava-14864571/0
10895 11:33:50.708008 + export 'TESTRUN_ID=0_dmesg'
10896 11:33:50.714488 +<8>[ 10.021646] <LAVA_SIGNAL_STARTRUN 0_dmesg 14864571_1.5.2.3.1>
10897 11:33:50.714739 Received signal: <STARTRUN> 0_dmesg 14864571_1.5.2.3.1
10898 11:33:50.714805 Starting test lava.0_dmesg (14864571_1.5.2.3.1)
10899 11:33:50.714880 Skipping test definition patterns.
10900 11:33:50.717707 cd /lava-14864571/0/tests/0_dmesg
10901 11:33:50.717774 + cat uuid
10902 11:33:50.721083 + UUID=14864571_1.5.2.3.1
10903 11:33:50.721171 + set +x
10904 11:33:50.727351 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10905 11:33:50.737663 <8>[ 10.040573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10906 11:33:50.737933 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10908 11:33:50.755885 <8>[ 10.060696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10909 11:33:50.756131 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10911 11:33:50.778219 <8>[ 10.082826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10912 11:33:50.778493 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10914 11:33:50.782297 + set +x
10915 11:33:50.785075 <8>[ 10.092687] <LAVA_SIGNAL_ENDRUN 0_dmesg 14864571_1.5.2.3.1>
10916 11:33:50.785345 Received signal: <ENDRUN> 0_dmesg 14864571_1.5.2.3.1
10917 11:33:50.785430 Ending use of test pattern.
10918 11:33:50.785514 Ending test lava.0_dmesg (14864571_1.5.2.3.1), duration 0.07
10920 11:33:50.788637 <LAVA_TEST_RUNNER EXIT>
10921 11:33:50.788880 ok: lava_test_shell seems to have completed
10922 11:33:50.788973 crit: pass
alert: pass
emerg: pass
10923 11:33:50.789057 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10924 11:33:50.789163 end: 3 lava-test-retry (duration 00:00:01) [common]
10925 11:33:50.789243 start: 4 finalize (timeout 00:07:49) [common]
10926 11:33:50.789396 start: 4.1 power-off (timeout 00:00:30) [common]
10927 11:33:50.789601 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
10928 11:33:52.872839 >> Command sent successfully.
10929 11:33:52.876146 Returned 0 in 2 seconds
10930 11:33:52.876288 end: 4.1 power-off (duration 00:00:02) [common]
10932 11:33:52.876478 start: 4.2 read-feedback (timeout 00:07:47) [common]
10933 11:33:52.876612 Listened to connection for namespace 'common' for up to 1s
10934 11:33:53.877656 Finalising connection for namespace 'common'
10935 11:33:53.877794 Disconnecting from shell: Finalise
10936 11:33:53.877858 / #
10937 11:33:53.978102 end: 4.2 read-feedback (duration 00:00:01) [common]
10938 11:33:53.978282 end: 4 finalize (duration 00:00:03) [common]
10939 11:33:53.978386 Cleaning after the job
10940 11:33:53.978474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/ramdisk
10941 11:33:53.981008 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/kernel
10942 11:33:53.988289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/dtb
10943 11:33:53.988476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864571/tftp-deploy-y53ldle6/modules
10944 11:33:53.994358 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864571
10945 11:33:54.033230 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864571
10946 11:33:54.033390 Job finished correctly