Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:31:03.544061 lava-dispatcher, installed at version: 2024.05
2 11:31:03.544256 start: 0 validate
3 11:31:03.544363 Start time: 2024-07-17 11:31:03.544358+00:00 (UTC)
4 11:31:03.544486 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:31:03.544624 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:31:03.798302 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:31:03.799032 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:31:04.061344 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:31:04.062208 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:31:47.196046 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:31:47.196887 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:31:47.708112 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:31:47.708751 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:31:47.973962 validate duration: 44.43
16 11:31:47.974237 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:31:47.974328 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:31:47.974403 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:31:47.974536 Not decompressing ramdisk as can be used compressed.
20 11:31:47.974617 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 11:31:47.974673 saving as /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/ramdisk/initrd.cpio.gz
22 11:31:47.974727 total size: 5628182 (5 MB)
23 11:31:50.205926 progress 0 % (0 MB)
24 11:31:50.209841 progress 5 % (0 MB)
25 11:31:50.211323 progress 10 % (0 MB)
26 11:31:50.212678 progress 15 % (0 MB)
27 11:31:50.214203 progress 20 % (1 MB)
28 11:31:50.215504 progress 25 % (1 MB)
29 11:31:50.216928 progress 30 % (1 MB)
30 11:31:50.218406 progress 35 % (1 MB)
31 11:31:50.219852 progress 40 % (2 MB)
32 11:31:50.221271 progress 45 % (2 MB)
33 11:31:50.222581 progress 50 % (2 MB)
34 11:31:50.224142 progress 55 % (2 MB)
35 11:31:50.225553 progress 60 % (3 MB)
36 11:31:50.226858 progress 65 % (3 MB)
37 11:31:50.228344 progress 70 % (3 MB)
38 11:31:50.229635 progress 75 % (4 MB)
39 11:31:50.231132 progress 80 % (4 MB)
40 11:31:50.232393 progress 85 % (4 MB)
41 11:31:50.233808 progress 90 % (4 MB)
42 11:31:50.235220 progress 95 % (5 MB)
43 11:31:50.236492 progress 100 % (5 MB)
44 11:31:50.236681 5 MB downloaded in 2.26 s (2.37 MB/s)
45 11:31:50.236819 end: 1.1.1 http-download (duration 00:00:02) [common]
47 11:31:50.237029 end: 1.1 download-retry (duration 00:00:02) [common]
48 11:31:50.237103 start: 1.2 download-retry (timeout 00:09:58) [common]
49 11:31:50.237174 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 11:31:50.237303 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:31:50.237363 saving as /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/kernel/Image
52 11:31:50.237413 total size: 54813184 (52 MB)
53 11:31:50.237464 No compression specified
54 11:31:50.238452 progress 0 % (0 MB)
55 11:31:50.251273 progress 5 % (2 MB)
56 11:31:50.264134 progress 10 % (5 MB)
57 11:31:50.277012 progress 15 % (7 MB)
58 11:31:50.290314 progress 20 % (10 MB)
59 11:31:50.303238 progress 25 % (13 MB)
60 11:31:50.315937 progress 30 % (15 MB)
61 11:31:50.328814 progress 35 % (18 MB)
62 11:31:50.341702 progress 40 % (20 MB)
63 11:31:50.354574 progress 45 % (23 MB)
64 11:31:50.367627 progress 50 % (26 MB)
65 11:31:50.380595 progress 55 % (28 MB)
66 11:31:50.393546 progress 60 % (31 MB)
67 11:31:50.406650 progress 65 % (34 MB)
68 11:31:50.419516 progress 70 % (36 MB)
69 11:31:50.432425 progress 75 % (39 MB)
70 11:31:50.445384 progress 80 % (41 MB)
71 11:31:50.458299 progress 85 % (44 MB)
72 11:31:50.471252 progress 90 % (47 MB)
73 11:31:50.484093 progress 95 % (49 MB)
74 11:31:50.496668 progress 100 % (52 MB)
75 11:31:50.496869 52 MB downloaded in 0.26 s (201.48 MB/s)
76 11:31:50.497008 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:31:50.497204 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:31:50.497279 start: 1.3 download-retry (timeout 00:09:57) [common]
80 11:31:50.497350 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 11:31:50.497477 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:31:50.497539 saving as /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/dtb/mt8192-asurada-spherion-r0.dtb
83 11:31:50.497589 total size: 47258 (0 MB)
84 11:31:50.497640 No compression specified
85 11:31:50.498754 progress 69 % (0 MB)
86 11:31:50.499061 progress 100 % (0 MB)
87 11:31:50.499223 0 MB downloaded in 0.00 s (27.62 MB/s)
88 11:31:50.499332 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:31:50.499523 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:31:50.499594 start: 1.4 download-retry (timeout 00:09:57) [common]
92 11:31:50.499665 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 11:31:50.499769 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 11:31:50.499825 saving as /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/nfsrootfs/full.rootfs.tar
95 11:31:50.499874 total size: 107552908 (102 MB)
96 11:31:50.499925 Using unxz to decompress xz
97 11:31:50.501150 progress 0 % (0 MB)
98 11:31:50.777059 progress 5 % (5 MB)
99 11:31:51.081073 progress 10 % (10 MB)
100 11:31:51.373679 progress 15 % (15 MB)
101 11:31:51.669297 progress 20 % (20 MB)
102 11:31:51.925875 progress 25 % (25 MB)
103 11:31:52.209478 progress 30 % (30 MB)
104 11:31:52.494009 progress 35 % (35 MB)
105 11:31:52.661036 progress 40 % (41 MB)
106 11:31:52.852063 progress 45 % (46 MB)
107 11:31:53.150421 progress 50 % (51 MB)
108 11:31:53.431983 progress 55 % (56 MB)
109 11:31:53.736032 progress 60 % (61 MB)
110 11:31:54.038538 progress 65 % (66 MB)
111 11:31:54.344296 progress 70 % (71 MB)
112 11:31:54.648891 progress 75 % (76 MB)
113 11:31:54.933540 progress 80 % (82 MB)
114 11:31:55.226061 progress 85 % (87 MB)
115 11:31:55.506835 progress 90 % (92 MB)
116 11:31:55.791501 progress 95 % (97 MB)
117 11:31:56.094307 progress 100 % (102 MB)
118 11:31:56.099275 102 MB downloaded in 5.60 s (18.32 MB/s)
119 11:31:56.099440 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:31:56.099676 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:31:56.099767 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:31:56.099855 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:31:56.100002 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:31:56.100089 saving as /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/modules/modules.tar
126 11:31:56.100176 total size: 8610184 (8 MB)
127 11:31:56.100265 Using unxz to decompress xz
128 11:31:56.101977 progress 0 % (0 MB)
129 11:31:56.121850 progress 5 % (0 MB)
130 11:31:56.145549 progress 10 % (0 MB)
131 11:31:56.168715 progress 15 % (1 MB)
132 11:31:56.191962 progress 20 % (1 MB)
133 11:31:56.214589 progress 25 % (2 MB)
134 11:31:56.237088 progress 30 % (2 MB)
135 11:31:56.258829 progress 35 % (2 MB)
136 11:31:56.283971 progress 40 % (3 MB)
137 11:31:56.307485 progress 45 % (3 MB)
138 11:31:56.330805 progress 50 % (4 MB)
139 11:31:56.355101 progress 55 % (4 MB)
140 11:31:56.378630 progress 60 % (4 MB)
141 11:31:56.401046 progress 65 % (5 MB)
142 11:31:56.425692 progress 70 % (5 MB)
143 11:31:56.451404 progress 75 % (6 MB)
144 11:31:56.477596 progress 80 % (6 MB)
145 11:31:56.500959 progress 85 % (7 MB)
146 11:31:56.524847 progress 90 % (7 MB)
147 11:31:56.548979 progress 95 % (7 MB)
148 11:31:56.571813 progress 100 % (8 MB)
149 11:31:56.577048 8 MB downloaded in 0.48 s (17.22 MB/s)
150 11:31:56.577192 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:31:56.577394 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:31:56.577469 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:31:56.577548 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:31:58.615046 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r
156 11:31:58.615221 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:31:58.615308 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:31:58.615473 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t
159 11:31:58.615590 makedir: /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin
160 11:31:58.615682 makedir: /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/tests
161 11:31:58.615771 makedir: /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/results
162 11:31:58.615852 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-add-keys
163 11:31:58.615977 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-add-sources
164 11:31:58.616092 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-background-process-start
165 11:31:58.616217 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-background-process-stop
166 11:31:58.616343 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-common-functions
167 11:31:58.616458 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-echo-ipv4
168 11:31:58.616569 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-install-packages
169 11:31:58.616724 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-installed-packages
170 11:31:58.616870 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-os-build
171 11:31:58.617017 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-probe-channel
172 11:31:58.617159 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-probe-ip
173 11:31:58.617302 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-target-ip
174 11:31:58.617443 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-target-mac
175 11:31:58.617586 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-target-storage
176 11:31:58.617735 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-case
177 11:31:58.617882 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-event
178 11:31:58.618028 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-feedback
179 11:31:58.618226 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-raise
180 11:31:58.618370 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-reference
181 11:31:58.618512 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-runner
182 11:31:58.618656 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-set
183 11:31:58.618800 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-test-shell
184 11:31:58.618946 Updating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-install-packages (oe)
185 11:31:58.619118 Updating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/bin/lava-installed-packages (oe)
186 11:31:58.619261 Creating /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/environment
187 11:31:58.619375 LAVA metadata
188 11:31:58.619465 - LAVA_JOB_ID=14864572
189 11:31:58.619550 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:31:58.619677 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 11:31:58.619761 skipped lava-vland-overlay
192 11:31:58.619855 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:31:58.619954 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 11:31:58.620035 skipped lava-multinode-overlay
195 11:31:58.620133 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:31:58.620234 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 11:31:58.620333 Loading test definitions
198 11:31:58.620439 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 11:31:58.620523 Using /lava-14864572 at stage 0
200 11:31:58.620974 uuid=14864572_1.6.2.3.1 testdef=None
201 11:31:58.621087 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:31:58.621190 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 11:31:58.621848 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:31:58.622219 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 11:31:58.623160 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:31:58.623499 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 11:31:58.624339 runner path: /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/0/tests/0_dmesg test_uuid 14864572_1.6.2.3.1
210 11:31:58.624512 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:31:58.624832 Creating lava-test-runner.conf files
213 11:31:58.624913 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864572/lava-overlay-22i66s0t/lava-14864572/0 for stage 0
214 11:31:58.625023 - 0_dmesg
215 11:31:58.625143 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:31:58.625245 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
217 11:31:58.633174 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:31:58.633316 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
219 11:31:58.633424 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:31:58.633531 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:31:58.633639 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
222 11:31:58.783310 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:31:58.783454 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
224 11:31:58.783528 extracting modules file /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r
225 11:31:59.015454 extracting modules file /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864572/extract-overlay-ramdisk-kj2r1kwc/ramdisk
226 11:31:59.237976 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:31:59.238130 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
228 11:31:59.238209 [common] Applying overlay to NFS
229 11:31:59.238267 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864572/compress-overlay-scfn8x6v/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r
230 11:31:59.244399 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:31:59.244505 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
232 11:31:59.244586 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:31:59.244661 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
234 11:31:59.244725 Building ramdisk /var/lib/lava/dispatcher/tmp/14864572/extract-overlay-ramdisk-kj2r1kwc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864572/extract-overlay-ramdisk-kj2r1kwc/ramdisk
235 11:31:59.515417 >> 129966 blocks
236 11:32:01.616373 rename /var/lib/lava/dispatcher/tmp/14864572/extract-overlay-ramdisk-kj2r1kwc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/ramdisk/ramdisk.cpio.gz
237 11:32:01.616538 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:32:01.616625 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
239 11:32:01.616713 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
240 11:32:01.616808 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/kernel/Image']
241 11:32:15.491193 Returned 0 in 13 seconds
242 11:32:15.491389 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/kernel/image.itb
243 11:32:15.843842 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:32:15.843969 output: Created: Wed Jul 17 12:32:15 2024
245 11:32:15.844029 output: Image 0 (kernel-1)
246 11:32:15.844084 output: Description:
247 11:32:15.844135 output: Created: Wed Jul 17 12:32:15 2024
248 11:32:15.844187 output: Type: Kernel Image
249 11:32:15.844237 output: Compression: lzma compressed
250 11:32:15.844288 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
251 11:32:15.844337 output: Architecture: AArch64
252 11:32:15.844385 output: OS: Linux
253 11:32:15.844433 output: Load Address: 0x00000000
254 11:32:15.844481 output: Entry Point: 0x00000000
255 11:32:15.844529 output: Hash algo: crc32
256 11:32:15.844579 output: Hash value: 83448d17
257 11:32:15.844627 output: Image 1 (fdt-1)
258 11:32:15.844674 output: Description: mt8192-asurada-spherion-r0
259 11:32:15.844722 output: Created: Wed Jul 17 12:32:15 2024
260 11:32:15.844770 output: Type: Flat Device Tree
261 11:32:15.844817 output: Compression: uncompressed
262 11:32:15.844865 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 11:32:15.844914 output: Architecture: AArch64
264 11:32:15.844962 output: Hash algo: crc32
265 11:32:15.845009 output: Hash value: 0f8e4d2e
266 11:32:15.845055 output: Image 2 (ramdisk-1)
267 11:32:15.845102 output: Description: unavailable
268 11:32:15.845148 output: Created: Wed Jul 17 12:32:15 2024
269 11:32:15.845195 output: Type: RAMDisk Image
270 11:32:15.845242 output: Compression: uncompressed
271 11:32:15.845289 output: Data Size: 18716598 Bytes = 18277.93 KiB = 17.85 MiB
272 11:32:15.845337 output: Architecture: AArch64
273 11:32:15.845383 output: OS: Linux
274 11:32:15.845430 output: Load Address: unavailable
275 11:32:15.845476 output: Entry Point: unavailable
276 11:32:15.845522 output: Hash algo: crc32
277 11:32:15.845569 output: Hash value: efc2d62d
278 11:32:15.845615 output: Default Configuration: 'conf-1'
279 11:32:15.845662 output: Configuration 0 (conf-1)
280 11:32:15.845708 output: Description: mt8192-asurada-spherion-r0
281 11:32:15.845754 output: Kernel: kernel-1
282 11:32:15.845801 output: Init Ramdisk: ramdisk-1
283 11:32:15.845847 output: FDT: fdt-1
284 11:32:15.845893 output: Loadables: kernel-1
285 11:32:15.845940 output:
286 11:32:15.846038 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 11:32:15.846127 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 11:32:15.846204 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 11:32:15.846278 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 11:32:15.846335 No LXC device requested
291 11:32:15.846400 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:32:15.846471 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 11:32:15.846538 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:32:15.846591 Checking files for TFTP limit of 4294967296 bytes.
295 11:32:15.847006 end: 1 tftp-deploy (duration 00:00:28) [common]
296 11:32:15.847094 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:32:15.847171 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:32:15.847260 substitutions:
299 11:32:15.847318 - {DTB}: 14864572/tftp-deploy-lyi6h__3/dtb/mt8192-asurada-spherion-r0.dtb
300 11:32:15.847373 - {INITRD}: 14864572/tftp-deploy-lyi6h__3/ramdisk/ramdisk.cpio.gz
301 11:32:15.847425 - {KERNEL}: 14864572/tftp-deploy-lyi6h__3/kernel/Image
302 11:32:15.847475 - {LAVA_MAC}: None
303 11:32:15.847525 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r
304 11:32:15.847575 - {NFS_SERVER_IP}: 192.168.201.1
305 11:32:15.847624 - {PRESEED_CONFIG}: None
306 11:32:15.847680 - {PRESEED_LOCAL}: None
307 11:32:15.847730 - {RAMDISK}: 14864572/tftp-deploy-lyi6h__3/ramdisk/ramdisk.cpio.gz
308 11:32:15.847778 - {ROOT_PART}: None
309 11:32:15.847826 - {ROOT}: None
310 11:32:15.847874 - {SERVER_IP}: 192.168.201.1
311 11:32:15.847922 - {TEE}: None
312 11:32:15.847970 Parsed boot commands:
313 11:32:15.848017 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:32:15.848152 Parsed boot commands: tftpboot 192.168.201.1 14864572/tftp-deploy-lyi6h__3/kernel/image.itb 14864572/tftp-deploy-lyi6h__3/kernel/cmdline
315 11:32:15.848231 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:32:15.848303 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:32:15.848373 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:32:15.848444 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:32:15.848497 Not connected, no need to disconnect.
320 11:32:15.848561 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:32:15.848628 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:32:15.848681 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 11:32:15.851368 Setting prompt string to ['lava-test: # ']
324 11:32:15.851663 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:32:15.851757 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:32:15.851845 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:32:15.851921 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:32:15.852151 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
329 11:32:24.969546 >> Command sent successfully.
330 11:32:24.978468 Returned 0 in 9 seconds
331 11:32:24.979004 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:32:24.979719 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:32:24.979982 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:32:24.980200 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:32:24.980367 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:32:24.980535 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:32:24.981313 [Enter `^Ec?' for help]
339 11:32:26.433599
340 11:32:26.434089
341 11:32:26.434478 F0: 102B 0000
342 11:32:26.434828
343 11:32:26.435154 F3: 1001 0000 [0200]
344 11:32:26.435449
345 11:32:26.437247 F3: 1001 0000
346 11:32:26.437764
347 11:32:26.438096 F7: 102D 0000
348 11:32:26.438475
349 11:32:26.438769 F1: 0000 0000
350 11:32:26.439076
351 11:32:26.440703 V0: 0000 0000 [0001]
352 11:32:26.441306
353 11:32:26.441659 00: 0007 8000
354 11:32:26.441974
355 11:32:26.444722 01: 0000 0000
356 11:32:26.445235
357 11:32:26.445562 BP: 0C00 0209 [0000]
358 11:32:26.445860
359 11:32:26.448087 G0: 1182 0000
360 11:32:26.448500
361 11:32:26.448822 EC: 0000 0021 [4000]
362 11:32:26.449122
363 11:32:26.451117 S7: 0000 0000 [0000]
364 11:32:26.451532
365 11:32:26.451852 CC: 0000 0000 [0001]
366 11:32:26.452149
367 11:32:26.454692 T0: 0000 0040 [010F]
368 11:32:26.455107
369 11:32:26.455428 Jump to BL
370 11:32:26.455772
371 11:32:26.479962
372 11:32:26.480457
373 11:32:26.487195 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 11:32:26.491146 ARM64: Exception handlers installed.
375 11:32:26.494700 ARM64: Testing exception
376 11:32:26.498729 ARM64: Done test exception
377 11:32:26.505591 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 11:32:26.515707 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 11:32:26.522369 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 11:32:26.532873 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 11:32:26.538915 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 11:32:26.546268 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 11:32:26.556611 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 11:32:26.563046 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 11:32:26.583244 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 11:32:26.586753 WDT: Last reset was cold boot
387 11:32:26.589597 SPI1(PAD0) initialized at 2873684 Hz
388 11:32:26.593147 SPI5(PAD0) initialized at 992727 Hz
389 11:32:26.596536 VBOOT: Loading verstage.
390 11:32:26.603342 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 11:32:26.606145 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 11:32:26.610006 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 11:32:26.612585 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 11:32:26.620659 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 11:32:26.627631 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 11:32:26.637909 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
397 11:32:26.638444
398 11:32:26.638875
399 11:32:26.647684 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 11:32:26.650993 ARM64: Exception handlers installed.
401 11:32:26.654465 ARM64: Testing exception
402 11:32:26.654906 ARM64: Done test exception
403 11:32:26.661079 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 11:32:26.664665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 11:32:26.679213 Probing TPM: . done!
406 11:32:26.679730 TPM ready after 0 ms
407 11:32:26.685396 Connected to device vid:did:rid of 1ae0:0028:00
408 11:32:26.695539 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 11:32:26.732725 Initialized TPM device CR50 revision 0
410 11:32:26.744336 tlcl_send_startup: Startup return code is 0
411 11:32:26.744843 TPM: setup succeeded
412 11:32:26.755869 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 11:32:26.765060 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 11:32:26.774439 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 11:32:26.784008 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 11:32:26.787236 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 11:32:26.790224 in-header: 03 07 00 00 08 00 00 00
418 11:32:26.794143 in-data: aa e4 47 04 13 02 00 00
419 11:32:26.797253 Chrome EC: UHEPI supported
420 11:32:26.804336 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 11:32:26.810637 in-header: 03 a9 00 00 08 00 00 00
422 11:32:26.814183 in-data: 84 60 60 08 00 00 00 00
423 11:32:26.814568 Phase 1
424 11:32:26.817644 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 11:32:26.824911 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 11:32:26.829114 VB2:vb2_check_recovery() Recovery was requested manually
427 11:32:26.836615 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 11:32:26.840243 Recovery requested (1009000e)
429 11:32:26.848156 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:32:26.853102 tlcl_extend: response is 0
431 11:32:26.863143 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:32:26.868087 tlcl_extend: response is 0
433 11:32:26.875391 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:32:26.895973 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
435 11:32:26.903032 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:32:26.903653
437 11:32:26.904010
438 11:32:26.910200 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:32:26.913607 ARM64: Exception handlers installed.
440 11:32:26.917594 ARM64: Testing exception
441 11:32:26.920915 ARM64: Done test exception
442 11:32:26.937898 pmic_efuse_setting: Set efuses in 11 msecs
443 11:32:26.946311 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:32:26.950308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:32:26.954136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:32:26.962144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:32:26.965432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:32:26.968870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:32:26.973009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:32:26.980815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:32:26.983881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:32:26.987026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:32:26.994259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:32:26.998733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:32:27.002256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:32:27.005590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:32:27.012856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:32:27.019886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:32:27.023422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:32:27.030955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:32:27.034574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:32:27.042386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:32:27.046178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:32:27.053678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:32:27.056651 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:32:27.064229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:32:27.067850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:32:27.075262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:32:27.078610 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:32:27.085625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:32:27.089558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:32:27.093344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:32:27.100166 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:32:27.104051 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:32:27.111519 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:32:27.114930 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:32:27.118884 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:32:27.126174 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:32:27.129923 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:32:27.136351 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:32:27.139496 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:32:27.142778 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:32:27.149528 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:32:27.152907 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:32:27.156764 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:32:27.162777 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:32:27.166527 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:32:27.169495 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:32:27.176586 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:32:27.179965 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:32:27.182664 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:32:27.186561 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:32:27.193547 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:32:27.196741 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:32:27.203195 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 11:32:27.213045 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:32:27.216277 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:32:27.226627 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:32:27.233795 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:32:27.236704 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:32:27.243297 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:32:27.246283 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:32:27.253447 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x37
504 11:32:27.260324 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:32:27.263353 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 11:32:27.267154 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:32:27.278088 [RTC]rtc_get_frequency_meter,154: input=15, output=794
508 11:32:27.281511 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 11:32:27.288317 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 11:32:27.291766 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
511 11:32:27.294371 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 11:32:27.298354 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
513 11:32:27.301031 ADC[4]: Raw value=897040 ID=7
514 11:32:27.305055 ADC[3]: Raw value=213440 ID=1
515 11:32:27.305563 RAM Code: 0x71
516 11:32:27.311719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 11:32:27.314588 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 11:32:27.324771 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 11:32:27.331180 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 11:32:27.334945 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 11:32:27.338530 in-header: 03 07 00 00 08 00 00 00
522 11:32:27.341554 in-data: aa e4 47 04 13 02 00 00
523 11:32:27.345119 Chrome EC: UHEPI supported
524 11:32:27.351225 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 11:32:27.354804 in-header: 03 a9 00 00 08 00 00 00
526 11:32:27.358333 in-data: 84 60 60 08 00 00 00 00
527 11:32:27.361371 MRC: failed to locate region type 0.
528 11:32:27.367798 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 11:32:27.370876 DRAM-K: Running full calibration
530 11:32:27.374694 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 11:32:27.378335 header.status = 0x0
532 11:32:27.381212 header.version = 0x6 (expected: 0x6)
533 11:32:27.384672 header.size = 0xd00 (expected: 0xd00)
534 11:32:27.387926 header.flags = 0x0
535 11:32:27.391256 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 11:32:27.410292 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
537 11:32:27.417378 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 11:32:27.420089 dram_init: ddr_geometry: 2
539 11:32:27.423302 [EMI] MDL number = 2
540 11:32:27.423798 [EMI] Get MDL freq = 0
541 11:32:27.426465 dram_init: ddr_type: 0
542 11:32:27.426896 is_discrete_lpddr4: 1
543 11:32:27.430062 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 11:32:27.430634
545 11:32:27.430971
546 11:32:27.433398 [Bian_co] ETT version 0.0.0.1
547 11:32:27.440463 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 11:32:27.440961
549 11:32:27.443652 dramc_set_vcore_voltage set vcore to 650000
550 11:32:27.444156 Read voltage for 800, 4
551 11:32:27.446941 Vio18 = 0
552 11:32:27.447368 Vcore = 650000
553 11:32:27.447797 Vdram = 0
554 11:32:27.450209 Vddq = 0
555 11:32:27.450636 Vmddr = 0
556 11:32:27.453643 dram_init: config_dvfs: 1
557 11:32:27.457310 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 11:32:27.463466 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 11:32:27.466987 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 11:32:27.470341 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 11:32:27.473900 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 11:32:27.476849 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 11:32:27.480527 MEM_TYPE=3, freq_sel=18
564 11:32:27.483702 sv_algorithm_assistance_LP4_1600
565 11:32:27.487007 ============ PULL DRAM RESETB DOWN ============
566 11:32:27.490517 ========== PULL DRAM RESETB DOWN end =========
567 11:32:27.496956 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 11:32:27.500306 ===================================
569 11:32:27.500811 LPDDR4 DRAM CONFIGURATION
570 11:32:27.503891 ===================================
571 11:32:27.507074 EX_ROW_EN[0] = 0x0
572 11:32:27.510675 EX_ROW_EN[1] = 0x0
573 11:32:27.511177 LP4Y_EN = 0x0
574 11:32:27.513430 WORK_FSP = 0x0
575 11:32:27.513932 WL = 0x2
576 11:32:27.516958 RL = 0x2
577 11:32:27.517608 BL = 0x2
578 11:32:27.520675 RPST = 0x0
579 11:32:27.521098 RD_PRE = 0x0
580 11:32:27.523936 WR_PRE = 0x1
581 11:32:27.524444 WR_PST = 0x0
582 11:32:27.527089 DBI_WR = 0x0
583 11:32:27.527511 DBI_RD = 0x0
584 11:32:27.530841 OTF = 0x1
585 11:32:27.533827 ===================================
586 11:32:27.537019 ===================================
587 11:32:27.537521 ANA top config
588 11:32:27.540279 ===================================
589 11:32:27.543220 DLL_ASYNC_EN = 0
590 11:32:27.546951 ALL_SLAVE_EN = 1
591 11:32:27.550400 NEW_RANK_MODE = 1
592 11:32:27.550909 DLL_IDLE_MODE = 1
593 11:32:27.553396 LP45_APHY_COMB_EN = 1
594 11:32:27.557101 TX_ODT_DIS = 1
595 11:32:27.560461 NEW_8X_MODE = 1
596 11:32:27.563302 ===================================
597 11:32:27.567118 ===================================
598 11:32:27.570338 data_rate = 1600
599 11:32:27.570863 CKR = 1
600 11:32:27.573718 DQ_P2S_RATIO = 8
601 11:32:27.576647 ===================================
602 11:32:27.580206 CA_P2S_RATIO = 8
603 11:32:27.583541 DQ_CA_OPEN = 0
604 11:32:27.586988 DQ_SEMI_OPEN = 0
605 11:32:27.590244 CA_SEMI_OPEN = 0
606 11:32:27.590747 CA_FULL_RATE = 0
607 11:32:27.593641 DQ_CKDIV4_EN = 1
608 11:32:27.596932 CA_CKDIV4_EN = 1
609 11:32:27.600074 CA_PREDIV_EN = 0
610 11:32:27.603385 PH8_DLY = 0
611 11:32:27.603815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 11:32:27.606443 DQ_AAMCK_DIV = 4
613 11:32:27.610057 CA_AAMCK_DIV = 4
614 11:32:27.613538 CA_ADMCK_DIV = 4
615 11:32:27.616844 DQ_TRACK_CA_EN = 0
616 11:32:27.619911 CA_PICK = 800
617 11:32:27.622966 CA_MCKIO = 800
618 11:32:27.623390 MCKIO_SEMI = 0
619 11:32:27.626446 PLL_FREQ = 3068
620 11:32:27.630160 DQ_UI_PI_RATIO = 32
621 11:32:27.633272 CA_UI_PI_RATIO = 0
622 11:32:27.636996 ===================================
623 11:32:27.639928 ===================================
624 11:32:27.643105 memory_type:LPDDR4
625 11:32:27.643531 GP_NUM : 10
626 11:32:27.647149 SRAM_EN : 1
627 11:32:27.647655 MD32_EN : 0
628 11:32:27.649993 ===================================
629 11:32:27.653618 [ANA_INIT] >>>>>>>>>>>>>>
630 11:32:27.656589 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 11:32:27.660581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 11:32:27.663690 ===================================
633 11:32:27.667079 data_rate = 1600,PCW = 0X7600
634 11:32:27.670308 ===================================
635 11:32:27.673703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 11:32:27.677311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 11:32:27.683637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 11:32:27.690238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 11:32:27.693715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 11:32:27.696873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 11:32:27.697303 [ANA_INIT] flow start
642 11:32:27.699963 [ANA_INIT] PLL >>>>>>>>
643 11:32:27.703536 [ANA_INIT] PLL <<<<<<<<
644 11:32:27.704097 [ANA_INIT] MIDPI >>>>>>>>
645 11:32:27.706821 [ANA_INIT] MIDPI <<<<<<<<
646 11:32:27.710299 [ANA_INIT] DLL >>>>>>>>
647 11:32:27.710804 [ANA_INIT] flow end
648 11:32:27.713627 ============ LP4 DIFF to SE enter ============
649 11:32:27.720737 ============ LP4 DIFF to SE exit ============
650 11:32:27.721231 [ANA_INIT] <<<<<<<<<<<<<
651 11:32:27.724273 [Flow] Enable top DCM control >>>>>
652 11:32:27.727965 [Flow] Enable top DCM control <<<<<
653 11:32:27.731799 Enable DLL master slave shuffle
654 11:32:27.735184 ==============================================================
655 11:32:27.738992 Gating Mode config
656 11:32:27.745622 ==============================================================
657 11:32:27.746230 Config description:
658 11:32:27.756526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 11:32:27.763071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 11:32:27.766256 SELPH_MODE 0: By rank 1: By Phase
661 11:32:27.773260 ==============================================================
662 11:32:27.776576 GAT_TRACK_EN = 1
663 11:32:27.779387 RX_GATING_MODE = 2
664 11:32:27.782773 RX_GATING_TRACK_MODE = 2
665 11:32:27.783278 SELPH_MODE = 1
666 11:32:27.786615 PICG_EARLY_EN = 1
667 11:32:27.789384 VALID_LAT_VALUE = 1
668 11:32:27.796461 ==============================================================
669 11:32:27.799606 Enter into Gating configuration >>>>
670 11:32:27.803316 Exit from Gating configuration <<<<
671 11:32:27.806752 Enter into DVFS_PRE_config >>>>>
672 11:32:27.816948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 11:32:27.819566 Exit from DVFS_PRE_config <<<<<
674 11:32:27.823255 Enter into PICG configuration >>>>
675 11:32:27.826194 Exit from PICG configuration <<<<
676 11:32:27.829568 [RX_INPUT] configuration >>>>>
677 11:32:27.832932 [RX_INPUT] configuration <<<<<
678 11:32:27.835974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 11:32:27.842723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 11:32:27.849359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 11:32:27.855776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 11:32:27.862370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 11:32:27.866213 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 11:32:27.872471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 11:32:27.876311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 11:32:27.879084 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 11:32:27.882399 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 11:32:27.885694 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 11:32:27.892287 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 11:32:27.895639 ===================================
691 11:32:27.898941 LPDDR4 DRAM CONFIGURATION
692 11:32:27.902808 ===================================
693 11:32:27.903320 EX_ROW_EN[0] = 0x0
694 11:32:27.905856 EX_ROW_EN[1] = 0x0
695 11:32:27.906455 LP4Y_EN = 0x0
696 11:32:27.909026 WORK_FSP = 0x0
697 11:32:27.909456 WL = 0x2
698 11:32:27.912393 RL = 0x2
699 11:32:27.912827 BL = 0x2
700 11:32:27.915535 RPST = 0x0
701 11:32:27.915973 RD_PRE = 0x0
702 11:32:27.918857 WR_PRE = 0x1
703 11:32:27.919287 WR_PST = 0x0
704 11:32:27.922354 DBI_WR = 0x0
705 11:32:27.922830 DBI_RD = 0x0
706 11:32:27.925856 OTF = 0x1
707 11:32:27.928968 ===================================
708 11:32:27.931953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 11:32:27.935471 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 11:32:27.942018 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 11:32:27.945166 ===================================
712 11:32:27.945775 LPDDR4 DRAM CONFIGURATION
713 11:32:27.948809 ===================================
714 11:32:27.951875 EX_ROW_EN[0] = 0x10
715 11:32:27.955197 EX_ROW_EN[1] = 0x0
716 11:32:27.955719 LP4Y_EN = 0x0
717 11:32:27.958938 WORK_FSP = 0x0
718 11:32:27.959365 WL = 0x2
719 11:32:27.962046 RL = 0x2
720 11:32:27.962821 BL = 0x2
721 11:32:27.965532 RPST = 0x0
722 11:32:27.965916 RD_PRE = 0x0
723 11:32:27.969282 WR_PRE = 0x1
724 11:32:27.969663 WR_PST = 0x0
725 11:32:27.972172 DBI_WR = 0x0
726 11:32:27.972555 DBI_RD = 0x0
727 11:32:27.975657 OTF = 0x1
728 11:32:27.978936 ===================================
729 11:32:27.985959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 11:32:27.988844 nWR fixed to 40
731 11:32:27.989243 [ModeRegInit_LP4] CH0 RK0
732 11:32:27.992467 [ModeRegInit_LP4] CH0 RK1
733 11:32:27.995857 [ModeRegInit_LP4] CH1 RK0
734 11:32:27.998721 [ModeRegInit_LP4] CH1 RK1
735 11:32:27.999107 match AC timing 13
736 11:32:28.005435 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 11:32:28.009197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 11:32:28.012070 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 11:32:28.018817 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 11:32:28.021884 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 11:32:28.022341 [EMI DOE] emi_dcm 0
742 11:32:28.028738 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 11:32:28.029171 ==
744 11:32:28.032503 Dram Type= 6, Freq= 0, CH_0, rank 0
745 11:32:28.035483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 11:32:28.035869 ==
747 11:32:28.042423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 11:32:28.045432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 11:32:28.055885 [CA 0] Center 38 (7~69) winsize 63
750 11:32:28.059051 [CA 1] Center 37 (7~68) winsize 62
751 11:32:28.062597 [CA 2] Center 35 (5~66) winsize 62
752 11:32:28.066273 [CA 3] Center 35 (5~66) winsize 62
753 11:32:28.069159 [CA 4] Center 34 (4~65) winsize 62
754 11:32:28.072507 [CA 5] Center 34 (4~65) winsize 62
755 11:32:28.072893
756 11:32:28.076032 [CmdBusTrainingLP45] Vref(ca) range 1: 32
757 11:32:28.076500
758 11:32:28.079580 [CATrainingPosCal] consider 1 rank data
759 11:32:28.082623 u2DelayCellTimex100 = 270/100 ps
760 11:32:28.085782 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 11:32:28.089637 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
762 11:32:28.092877 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 11:32:28.099228 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 11:32:28.102711 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 11:32:28.105818 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
766 11:32:28.106243
767 11:32:28.109597 CA PerBit enable=1, Macro0, CA PI delay=34
768 11:32:28.110043
769 11:32:28.112851 [CBTSetCACLKResult] CA Dly = 34
770 11:32:28.113238 CS Dly: 6 (0~37)
771 11:32:28.113534 ==
772 11:32:28.116081 Dram Type= 6, Freq= 0, CH_0, rank 1
773 11:32:28.122970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:32:28.123459 ==
775 11:32:28.126641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 11:32:28.133404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 11:32:28.142258 [CA 0] Center 38 (7~69) winsize 63
778 11:32:28.145812 [CA 1] Center 38 (7~69) winsize 63
779 11:32:28.149305 [CA 2] Center 35 (5~66) winsize 62
780 11:32:28.151797 [CA 3] Center 35 (5~66) winsize 62
781 11:32:28.155254 [CA 4] Center 34 (4~65) winsize 62
782 11:32:28.159036 [CA 5] Center 34 (3~65) winsize 63
783 11:32:28.159422
784 11:32:28.162272 [CmdBusTrainingLP45] Vref(ca) range 1: 34
785 11:32:28.162656
786 11:32:28.165279 [CATrainingPosCal] consider 2 rank data
787 11:32:28.168486 u2DelayCellTimex100 = 270/100 ps
788 11:32:28.171981 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 11:32:28.176151 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
790 11:32:28.178984 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 11:32:28.185881 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 11:32:28.189231 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 11:32:28.193074 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 11:32:28.193546
795 11:32:28.196316 CA PerBit enable=1, Macro0, CA PI delay=34
796 11:32:28.196774
797 11:32:28.199369 [CBTSetCACLKResult] CA Dly = 34
798 11:32:28.199752 CS Dly: 6 (0~38)
799 11:32:28.200051
800 11:32:28.202397 ----->DramcWriteLeveling(PI) begin...
801 11:32:28.202782 ==
802 11:32:28.206462 Dram Type= 6, Freq= 0, CH_0, rank 0
803 11:32:28.212653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:32:28.213121 ==
805 11:32:28.215973 Write leveling (Byte 0): 33 => 33
806 11:32:28.219279 Write leveling (Byte 1): 30 => 30
807 11:32:28.219664 DramcWriteLeveling(PI) end<-----
808 11:32:28.219962
809 11:32:28.222655 ==
810 11:32:28.226500 Dram Type= 6, Freq= 0, CH_0, rank 0
811 11:32:28.229331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 11:32:28.229746 ==
813 11:32:28.232614 [Gating] SW mode calibration
814 11:32:28.238891 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 11:32:28.242266 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 11:32:28.249607 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 11:32:28.252303 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
818 11:32:28.255724 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
819 11:32:28.262173 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
820 11:32:28.265611 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:32:28.269126 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:32:28.275618 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:32:28.278917 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:32:28.282489 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:32:28.288999 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:32:28.292357 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:32:28.296287 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:32:28.299820 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:32:28.306638 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:32:28.309798 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:32:28.313101 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:32:28.319454 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:32:28.323203 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:32:28.325990 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
835 11:32:28.330064 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:32:28.336483 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:32:28.339934 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:32:28.343019 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:32:28.349724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:32:28.352842 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:32:28.356236 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:32:28.363456 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
843 11:32:28.366527 0 9 12 | B1->B0 | 2424 3030 | 1 0 | (1 1) (0 0)
844 11:32:28.369602 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 11:32:28.376148 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 11:32:28.379581 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 11:32:28.382960 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 11:32:28.389411 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 11:32:28.392998 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 11:32:28.396355 0 10 8 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
851 11:32:28.402867 0 10 12 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
852 11:32:28.406450 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:32:28.409976 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:32:28.416192 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:32:28.419726 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:32:28.423014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:32:28.426976 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:32:28.433196 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
859 11:32:28.436419 0 11 12 | B1->B0 | 3434 4343 | 0 1 | (1 1) (1 1)
860 11:32:28.439735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 11:32:28.446649 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 11:32:28.450062 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 11:32:28.453188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 11:32:28.460073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 11:32:28.463138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 11:32:28.466530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
867 11:32:28.473025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
868 11:32:28.476574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 11:32:28.480415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 11:32:28.486325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 11:32:28.489875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 11:32:28.492829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 11:32:28.499574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 11:32:28.502803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:32:28.506475 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:32:28.513010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:32:28.516315 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:32:28.519754 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:32:28.526548 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:32:28.529848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:32:28.532767 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:32:28.539709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
883 11:32:28.542977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:32:28.546086 Total UI for P1: 0, mck2ui 16
885 11:32:28.549706 best dqsien dly found for B0: ( 0, 14, 8)
886 11:32:28.552891 Total UI for P1: 0, mck2ui 16
887 11:32:28.556160 best dqsien dly found for B1: ( 0, 14, 10)
888 11:32:28.559414 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
889 11:32:28.563043 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
890 11:32:28.563473
891 11:32:28.566029 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
892 11:32:28.569882 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
893 11:32:28.572959 [Gating] SW calibration Done
894 11:32:28.573381 ==
895 11:32:28.576104 Dram Type= 6, Freq= 0, CH_0, rank 0
896 11:32:28.579321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
897 11:32:28.579752 ==
898 11:32:28.582852 RX Vref Scan: 0
899 11:32:28.583274
900 11:32:28.583602 RX Vref 0 -> 0, step: 1
901 11:32:28.583908
902 11:32:28.586270 RX Delay -130 -> 252, step: 16
903 11:32:28.592929 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
904 11:32:28.596528 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
905 11:32:28.599554 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
906 11:32:28.603210 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
907 11:32:28.606538 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
908 11:32:28.612749 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
909 11:32:28.616366 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
910 11:32:28.619796 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
911 11:32:28.622769 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
912 11:32:28.625982 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
913 11:32:28.629328 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
914 11:32:28.636469 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
915 11:32:28.639246 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
916 11:32:28.642595 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
917 11:32:28.646225 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
918 11:32:28.652998 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
919 11:32:28.653559 ==
920 11:32:28.656022 Dram Type= 6, Freq= 0, CH_0, rank 0
921 11:32:28.659547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 11:32:28.660114 ==
923 11:32:28.660534 DQS Delay:
924 11:32:28.663146 DQS0 = 0, DQS1 = 0
925 11:32:28.663696 DQM Delay:
926 11:32:28.665998 DQM0 = 81, DQM1 = 70
927 11:32:28.666592 DQ Delay:
928 11:32:28.669347 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
929 11:32:28.672784 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
930 11:32:28.675889 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
931 11:32:28.679224 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
932 11:32:28.679608
933 11:32:28.679981
934 11:32:28.680261 ==
935 11:32:28.682836 Dram Type= 6, Freq= 0, CH_0, rank 0
936 11:32:28.685953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 11:32:28.686429 ==
938 11:32:28.686733
939 11:32:28.687005
940 11:32:28.689383 TX Vref Scan disable
941 11:32:28.693002 == TX Byte 0 ==
942 11:32:28.696074 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
943 11:32:28.699370 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
944 11:32:28.702750 == TX Byte 1 ==
945 11:32:28.705707 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 11:32:28.709052 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 11:32:28.709438 ==
948 11:32:28.712875 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:32:28.719113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:32:28.719189 ==
951 11:32:28.730702 TX Vref=22, minBit 3, minWin=26, winSum=433
952 11:32:28.733836 TX Vref=24, minBit 15, minWin=26, winSum=434
953 11:32:28.737186 TX Vref=26, minBit 2, minWin=27, winSum=442
954 11:32:28.740509 TX Vref=28, minBit 4, minWin=27, winSum=442
955 11:32:28.744036 TX Vref=30, minBit 10, minWin=27, winSum=442
956 11:32:28.750656 TX Vref=32, minBit 9, minWin=26, winSum=438
957 11:32:28.754239 [TxChooseVref] Worse bit 2, Min win 27, Win sum 442, Final Vref 26
958 11:32:28.754360
959 11:32:28.757254 Final TX Range 1 Vref 26
960 11:32:28.757368
961 11:32:28.757435 ==
962 11:32:28.760877 Dram Type= 6, Freq= 0, CH_0, rank 0
963 11:32:28.763625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 11:32:28.767327 ==
965 11:32:28.767429
966 11:32:28.767507
967 11:32:28.767580 TX Vref Scan disable
968 11:32:28.770891 == TX Byte 0 ==
969 11:32:28.773954 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
970 11:32:28.777344 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
971 11:32:28.780847 == TX Byte 1 ==
972 11:32:28.784343 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 11:32:28.787867 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 11:32:28.790979
975 11:32:28.791248 [DATLAT]
976 11:32:28.791404 Freq=800, CH0 RK0
977 11:32:28.791540
978 11:32:28.794495 DATLAT Default: 0xa
979 11:32:28.794787 0, 0xFFFF, sum = 0
980 11:32:28.797600 1, 0xFFFF, sum = 0
981 11:32:28.797676 2, 0xFFFF, sum = 0
982 11:32:28.800923 3, 0xFFFF, sum = 0
983 11:32:28.800999 4, 0xFFFF, sum = 0
984 11:32:28.804250 5, 0xFFFF, sum = 0
985 11:32:28.804326 6, 0xFFFF, sum = 0
986 11:32:28.807538 7, 0xFFFF, sum = 0
987 11:32:28.810750 8, 0xFFFF, sum = 0
988 11:32:28.810827 9, 0x0, sum = 1
989 11:32:28.810886 10, 0x0, sum = 2
990 11:32:28.813965 11, 0x0, sum = 3
991 11:32:28.814073 12, 0x0, sum = 4
992 11:32:28.817738 best_step = 10
993 11:32:28.817818
994 11:32:28.817880 ==
995 11:32:28.820926 Dram Type= 6, Freq= 0, CH_0, rank 0
996 11:32:28.824187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 11:32:28.824282 ==
998 11:32:28.827927 RX Vref Scan: 1
999 11:32:28.828045
1000 11:32:28.828131 Set Vref Range= 32 -> 127
1001 11:32:28.828212
1002 11:32:28.830974 RX Vref 32 -> 127, step: 1
1003 11:32:28.831075
1004 11:32:28.834111 RX Delay -111 -> 252, step: 8
1005 11:32:28.834224
1006 11:32:28.837489 Set Vref, RX VrefLevel [Byte0]: 32
1007 11:32:28.840915 [Byte1]: 32
1008 11:32:28.841075
1009 11:32:28.844563 Set Vref, RX VrefLevel [Byte0]: 33
1010 11:32:28.847610 [Byte1]: 33
1011 11:32:28.851142
1012 11:32:28.851342 Set Vref, RX VrefLevel [Byte0]: 34
1013 11:32:28.854861 [Byte1]: 34
1014 11:32:28.858917
1015 11:32:28.859114 Set Vref, RX VrefLevel [Byte0]: 35
1016 11:32:28.862306 [Byte1]: 35
1017 11:32:28.867045
1018 11:32:28.867263 Set Vref, RX VrefLevel [Byte0]: 36
1019 11:32:28.870008 [Byte1]: 36
1020 11:32:28.874152
1021 11:32:28.874374 Set Vref, RX VrefLevel [Byte0]: 37
1022 11:32:28.877916 [Byte1]: 37
1023 11:32:28.882032
1024 11:32:28.882335 Set Vref, RX VrefLevel [Byte0]: 38
1025 11:32:28.885587 [Byte1]: 38
1026 11:32:28.890001
1027 11:32:28.890263 Set Vref, RX VrefLevel [Byte0]: 39
1028 11:32:28.893062 [Byte1]: 39
1029 11:32:28.897370
1030 11:32:28.897580 Set Vref, RX VrefLevel [Byte0]: 40
1031 11:32:28.900424 [Byte1]: 40
1032 11:32:28.905223
1033 11:32:28.905468 Set Vref, RX VrefLevel [Byte0]: 41
1034 11:32:28.908563 [Byte1]: 41
1035 11:32:28.912622
1036 11:32:28.912819 Set Vref, RX VrefLevel [Byte0]: 42
1037 11:32:28.919118 [Byte1]: 42
1038 11:32:28.919461
1039 11:32:28.922481 Set Vref, RX VrefLevel [Byte0]: 43
1040 11:32:28.925973 [Byte1]: 43
1041 11:32:28.926475
1042 11:32:28.929283 Set Vref, RX VrefLevel [Byte0]: 44
1043 11:32:28.933007 [Byte1]: 44
1044 11:32:28.933392
1045 11:32:28.935929 Set Vref, RX VrefLevel [Byte0]: 45
1046 11:32:28.939489 [Byte1]: 45
1047 11:32:28.943315
1048 11:32:28.943775 Set Vref, RX VrefLevel [Byte0]: 46
1049 11:32:28.946765 [Byte1]: 46
1050 11:32:28.950912
1051 11:32:28.951422 Set Vref, RX VrefLevel [Byte0]: 47
1052 11:32:28.954482 [Byte1]: 47
1053 11:32:28.958715
1054 11:32:28.959083 Set Vref, RX VrefLevel [Byte0]: 48
1055 11:32:28.962346 [Byte1]: 48
1056 11:32:28.966309
1057 11:32:28.966696 Set Vref, RX VrefLevel [Byte0]: 49
1058 11:32:28.969682 [Byte1]: 49
1059 11:32:28.974291
1060 11:32:28.974669 Set Vref, RX VrefLevel [Byte0]: 50
1061 11:32:28.977259 [Byte1]: 50
1062 11:32:28.981237
1063 11:32:28.981594 Set Vref, RX VrefLevel [Byte0]: 51
1064 11:32:28.988203 [Byte1]: 51
1065 11:32:28.988615
1066 11:32:28.991435 Set Vref, RX VrefLevel [Byte0]: 52
1067 11:32:28.994581 [Byte1]: 52
1068 11:32:28.994976
1069 11:32:28.998052 Set Vref, RX VrefLevel [Byte0]: 53
1070 11:32:29.002352 [Byte1]: 53
1071 11:32:29.002790
1072 11:32:29.004683 Set Vref, RX VrefLevel [Byte0]: 54
1073 11:32:29.008049 [Byte1]: 54
1074 11:32:29.012106
1075 11:32:29.012586 Set Vref, RX VrefLevel [Byte0]: 55
1076 11:32:29.015580 [Byte1]: 55
1077 11:32:29.023495
1078 11:32:29.023851 Set Vref, RX VrefLevel [Byte0]: 56
1079 11:32:29.024095 [Byte1]: 56
1080 11:32:29.027765
1081 11:32:29.027937 Set Vref, RX VrefLevel [Byte0]: 57
1082 11:32:29.030490 [Byte1]: 57
1083 11:32:29.035080
1084 11:32:29.035247 Set Vref, RX VrefLevel [Byte0]: 58
1085 11:32:29.038077 [Byte1]: 58
1086 11:32:29.042804
1087 11:32:29.043035 Set Vref, RX VrefLevel [Byte0]: 59
1088 11:32:29.046074 [Byte1]: 59
1089 11:32:29.050162
1090 11:32:29.050464 Set Vref, RX VrefLevel [Byte0]: 60
1091 11:32:29.053995 [Byte1]: 60
1092 11:32:29.057734
1093 11:32:29.058161 Set Vref, RX VrefLevel [Byte0]: 61
1094 11:32:29.061067 [Byte1]: 61
1095 11:32:29.065457
1096 11:32:29.065919 Set Vref, RX VrefLevel [Byte0]: 62
1097 11:32:29.069111 [Byte1]: 62
1098 11:32:29.073536
1099 11:32:29.074018 Set Vref, RX VrefLevel [Byte0]: 63
1100 11:32:29.076569 [Byte1]: 63
1101 11:32:29.080861
1102 11:32:29.084216 Set Vref, RX VrefLevel [Byte0]: 64
1103 11:32:29.084752 [Byte1]: 64
1104 11:32:29.088537
1105 11:32:29.088929 Set Vref, RX VrefLevel [Byte0]: 65
1106 11:32:29.091724 [Byte1]: 65
1107 11:32:29.096092
1108 11:32:29.096618 Set Vref, RX VrefLevel [Byte0]: 66
1109 11:32:29.099715 [Byte1]: 66
1110 11:32:29.104219
1111 11:32:29.104745 Set Vref, RX VrefLevel [Byte0]: 67
1112 11:32:29.107626 [Byte1]: 67
1113 11:32:29.111601
1114 11:32:29.112063 Set Vref, RX VrefLevel [Byte0]: 68
1115 11:32:29.114799 [Byte1]: 68
1116 11:32:29.119125
1117 11:32:29.119487 Set Vref, RX VrefLevel [Byte0]: 69
1118 11:32:29.122778 [Byte1]: 69
1119 11:32:29.126743
1120 11:32:29.127251 Set Vref, RX VrefLevel [Byte0]: 70
1121 11:32:29.130524 [Byte1]: 70
1122 11:32:29.134684
1123 11:32:29.135082 Set Vref, RX VrefLevel [Byte0]: 71
1124 11:32:29.137731 [Byte1]: 71
1125 11:32:29.142134
1126 11:32:29.142637 Set Vref, RX VrefLevel [Byte0]: 72
1127 11:32:29.145667 [Byte1]: 72
1128 11:32:29.149703
1129 11:32:29.150208 Set Vref, RX VrefLevel [Byte0]: 73
1130 11:32:29.152902 [Byte1]: 73
1131 11:32:29.157433
1132 11:32:29.157817 Set Vref, RX VrefLevel [Byte0]: 74
1133 11:32:29.160386 [Byte1]: 74
1134 11:32:29.165523
1135 11:32:29.166042 Set Vref, RX VrefLevel [Byte0]: 75
1136 11:32:29.168722 [Byte1]: 75
1137 11:32:29.172480
1138 11:32:29.172971 Set Vref, RX VrefLevel [Byte0]: 76
1139 11:32:29.175845 [Byte1]: 76
1140 11:32:29.180634
1141 11:32:29.181152 Set Vref, RX VrefLevel [Byte0]: 77
1142 11:32:29.184058 [Byte1]: 77
1143 11:32:29.188095
1144 11:32:29.188510 Set Vref, RX VrefLevel [Byte0]: 78
1145 11:32:29.191258 [Byte1]: 78
1146 11:32:29.195632
1147 11:32:29.196147 Final RX Vref Byte 0 = 62 to rank0
1148 11:32:29.199163 Final RX Vref Byte 1 = 56 to rank0
1149 11:32:29.202261 Final RX Vref Byte 0 = 62 to rank1
1150 11:32:29.205463 Final RX Vref Byte 1 = 56 to rank1==
1151 11:32:29.209108 Dram Type= 6, Freq= 0, CH_0, rank 0
1152 11:32:29.212789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 11:32:29.216042 ==
1154 11:32:29.216594 DQS Delay:
1155 11:32:29.217061 DQS0 = 0, DQS1 = 0
1156 11:32:29.219339 DQM Delay:
1157 11:32:29.219783 DQM0 = 81, DQM1 = 67
1158 11:32:29.222358 DQ Delay:
1159 11:32:29.222739 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1160 11:32:29.226311 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1161 11:32:29.229248 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1162 11:32:29.232363 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1163 11:32:29.232745
1164 11:32:29.236102
1165 11:32:29.242436 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1166 11:32:29.245753 CH0 RK0: MR19=606, MR18=2928
1167 11:32:29.252497 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1168 11:32:29.253004
1169 11:32:29.255628 ----->DramcWriteLeveling(PI) begin...
1170 11:32:29.256077 ==
1171 11:32:29.259518 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 11:32:29.262191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 11:32:29.262702 ==
1174 11:32:29.265947 Write leveling (Byte 0): 33 => 33
1175 11:32:29.269320 Write leveling (Byte 1): 31 => 31
1176 11:32:29.272290 DramcWriteLeveling(PI) end<-----
1177 11:32:29.272678
1178 11:32:29.272976 ==
1179 11:32:29.275778 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 11:32:29.279058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 11:32:29.279447 ==
1182 11:32:29.282557 [Gating] SW mode calibration
1183 11:32:29.288914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1184 11:32:29.295770 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1185 11:32:29.299167 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1186 11:32:29.302838 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1187 11:32:29.309144 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1188 11:32:29.312803 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:32:29.316136 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:32:29.322566 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:32:29.325439 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:32:29.328887 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:32:29.336153 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:32:29.339030 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:32:29.342917 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:32:29.349212 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:32:29.352136 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:32:29.355716 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:32:29.399913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:32:29.400668 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:32:29.401028 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:32:29.401322 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1203 11:32:29.401615 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1204 11:32:29.401998 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1205 11:32:29.402494 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:32:29.403021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:32:29.403462 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:32:29.403918 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:32:29.443856 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:32:29.444555 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:32:29.444931 0 9 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1212 11:32:29.445234 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1213 11:32:29.445512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 11:32:29.445823 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 11:32:29.446181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 11:32:29.446513 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 11:32:29.446788 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 11:32:29.447098 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1219 11:32:29.462177 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 0)
1220 11:32:29.462607 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1221 11:32:29.463461 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:32:29.463813 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:32:29.466198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:32:29.469155 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:32:29.475585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:32:29.479100 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:32:29.482507 0 11 8 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (1 1)
1228 11:32:29.488930 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1229 11:32:29.492355 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 11:32:29.495889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 11:32:29.502482 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 11:32:29.505625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 11:32:29.509494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 11:32:29.516209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 11:32:29.519232 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1236 11:32:29.522311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 11:32:29.526152 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 11:32:29.532517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 11:32:29.535711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 11:32:29.538906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 11:32:29.546569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 11:32:29.549220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 11:32:29.552633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 11:32:29.559826 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 11:32:29.562508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 11:32:29.565772 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:32:29.572804 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:32:29.576376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:32:29.579390 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:32:29.585965 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1251 11:32:29.589437 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1252 11:32:29.592957 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 11:32:29.596246 Total UI for P1: 0, mck2ui 16
1254 11:32:29.599256 best dqsien dly found for B0: ( 0, 14, 6)
1255 11:32:29.602898 Total UI for P1: 0, mck2ui 16
1256 11:32:29.605787 best dqsien dly found for B1: ( 0, 14, 8)
1257 11:32:29.609605 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1258 11:32:29.612587 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1259 11:32:29.612978
1260 11:32:29.616154 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1261 11:32:29.619578 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1262 11:32:29.622647 [Gating] SW calibration Done
1263 11:32:29.623039 ==
1264 11:32:29.626423 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 11:32:29.632962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 11:32:29.633358 ==
1267 11:32:29.633678 RX Vref Scan: 0
1268 11:32:29.633959
1269 11:32:29.636347 RX Vref 0 -> 0, step: 1
1270 11:32:29.636733
1271 11:32:29.639664 RX Delay -130 -> 252, step: 16
1272 11:32:29.642646 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1273 11:32:29.646363 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1274 11:32:29.649589 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1275 11:32:29.653018 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1276 11:32:29.659206 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1277 11:32:29.663011 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1278 11:32:29.665752 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1279 11:32:29.669374 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1280 11:32:29.672575 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1281 11:32:29.679537 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1282 11:32:29.683094 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1283 11:32:29.686526 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1284 11:32:29.689600 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1285 11:32:29.692901 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1286 11:32:29.699272 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1287 11:32:29.702513 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1288 11:32:29.703070 ==
1289 11:32:29.706143 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 11:32:29.709239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 11:32:29.709673 ==
1292 11:32:29.712755 DQS Delay:
1293 11:32:29.713190 DQS0 = 0, DQS1 = 0
1294 11:32:29.713596 DQM Delay:
1295 11:32:29.715824 DQM0 = 78, DQM1 = 70
1296 11:32:29.716303 DQ Delay:
1297 11:32:29.719704 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1298 11:32:29.722624 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1299 11:32:29.726141 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =61
1300 11:32:29.729131 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1301 11:32:29.729561
1302 11:32:29.729865
1303 11:32:29.730206 ==
1304 11:32:29.732878 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 11:32:29.739098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 11:32:29.739508 ==
1307 11:32:29.739812
1308 11:32:29.740086
1309 11:32:29.740397 TX Vref Scan disable
1310 11:32:29.742908 == TX Byte 0 ==
1311 11:32:29.746062 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1312 11:32:29.753136 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1313 11:32:29.753526 == TX Byte 1 ==
1314 11:32:29.756131 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1315 11:32:29.759444 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1316 11:32:29.762728 ==
1317 11:32:29.766218 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:32:29.769548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:32:29.769930 ==
1320 11:32:29.782260 TX Vref=22, minBit 2, minWin=26, winSum=432
1321 11:32:29.785473 TX Vref=24, minBit 11, minWin=26, winSum=438
1322 11:32:29.788371 TX Vref=26, minBit 1, minWin=27, winSum=439
1323 11:32:29.791876 TX Vref=28, minBit 1, minWin=27, winSum=440
1324 11:32:29.795436 TX Vref=30, minBit 1, minWin=27, winSum=440
1325 11:32:29.801912 TX Vref=32, minBit 10, minWin=27, winSum=445
1326 11:32:29.805258 [TxChooseVref] Worse bit 10, Min win 27, Win sum 445, Final Vref 32
1327 11:32:29.805679
1328 11:32:29.808599 Final TX Range 1 Vref 32
1329 11:32:29.809107
1330 11:32:29.809435 ==
1331 11:32:29.812003 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:32:29.815598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:32:29.816046 ==
1334 11:32:29.818900
1335 11:32:29.819319
1336 11:32:29.819741 TX Vref Scan disable
1337 11:32:29.822030 == TX Byte 0 ==
1338 11:32:29.825460 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1339 11:32:29.829003 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1340 11:32:29.831918 == TX Byte 1 ==
1341 11:32:29.835373 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1342 11:32:29.841880 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1343 11:32:29.842310
1344 11:32:29.842610 [DATLAT]
1345 11:32:29.842888 Freq=800, CH0 RK1
1346 11:32:29.843170
1347 11:32:29.845203 DATLAT Default: 0xa
1348 11:32:29.845584 0, 0xFFFF, sum = 0
1349 11:32:29.848666 1, 0xFFFF, sum = 0
1350 11:32:29.849111 2, 0xFFFF, sum = 0
1351 11:32:29.852564 3, 0xFFFF, sum = 0
1352 11:32:29.855145 4, 0xFFFF, sum = 0
1353 11:32:29.855644 5, 0xFFFF, sum = 0
1354 11:32:29.858789 6, 0xFFFF, sum = 0
1355 11:32:29.859063 7, 0xFFFF, sum = 0
1356 11:32:29.861686 8, 0xFFFF, sum = 0
1357 11:32:29.861962 9, 0x0, sum = 1
1358 11:32:29.862204 10, 0x0, sum = 2
1359 11:32:29.865379 11, 0x0, sum = 3
1360 11:32:29.865652 12, 0x0, sum = 4
1361 11:32:29.868333 best_step = 10
1362 11:32:29.868655
1363 11:32:29.868923 ==
1364 11:32:29.872220 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 11:32:29.874848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 11:32:29.875120 ==
1367 11:32:29.878671 RX Vref Scan: 0
1368 11:32:29.878963
1369 11:32:29.879270 RX Vref 0 -> 0, step: 1
1370 11:32:29.879546
1371 11:32:29.881704 RX Delay -111 -> 252, step: 8
1372 11:32:29.888598 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1373 11:32:29.892028 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1374 11:32:29.895422 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1375 11:32:29.898500 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1376 11:32:29.901785 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1377 11:32:29.908914 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1378 11:32:29.912641 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1379 11:32:29.915868 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1380 11:32:29.919141 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1381 11:32:29.922999 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1382 11:32:29.928904 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1383 11:32:29.932961 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1384 11:32:29.935649 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1385 11:32:29.939715 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1386 11:32:29.942211 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1387 11:32:29.949208 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1388 11:32:29.949714 ==
1389 11:32:29.952675 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 11:32:29.955785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 11:32:29.956216 ==
1392 11:32:29.956544 DQS Delay:
1393 11:32:29.959464 DQS0 = 0, DQS1 = 0
1394 11:32:29.959981 DQM Delay:
1395 11:32:29.963085 DQM0 = 79, DQM1 = 69
1396 11:32:29.963587 DQ Delay:
1397 11:32:29.965889 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =76
1398 11:32:29.969705 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1399 11:32:29.972922 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1400 11:32:29.976375 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1401 11:32:29.976801
1402 11:32:29.977126
1403 11:32:29.982427 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1404 11:32:29.985901 CH0 RK1: MR19=606, MR18=4924
1405 11:32:29.992705 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1406 11:32:29.996220 [RxdqsGatingPostProcess] freq 800
1407 11:32:30.002638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1408 11:32:30.003064 Pre-setting of DQS Precalculation
1409 11:32:30.009176 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1410 11:32:30.009723 ==
1411 11:32:30.013251 Dram Type= 6, Freq= 0, CH_1, rank 0
1412 11:32:30.016697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 11:32:30.017201 ==
1414 11:32:30.022738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 11:32:30.028968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 11:32:30.037834 [CA 0] Center 36 (6~66) winsize 61
1417 11:32:30.040827 [CA 1] Center 36 (6~67) winsize 62
1418 11:32:30.043747 [CA 2] Center 34 (5~64) winsize 60
1419 11:32:30.047396 [CA 3] Center 33 (3~64) winsize 62
1420 11:32:30.050957 [CA 4] Center 34 (4~64) winsize 61
1421 11:32:30.054400 [CA 5] Center 33 (3~64) winsize 62
1422 11:32:30.054823
1423 11:32:30.057221 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1424 11:32:30.057640
1425 11:32:30.060639 [CATrainingPosCal] consider 1 rank data
1426 11:32:30.064609 u2DelayCellTimex100 = 270/100 ps
1427 11:32:30.067773 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1428 11:32:30.070933 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1429 11:32:30.077522 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1430 11:32:30.080911 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 11:32:30.084153 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1432 11:32:30.087725 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1433 11:32:30.088227
1434 11:32:30.090743 CA PerBit enable=1, Macro0, CA PI delay=33
1435 11:32:30.091247
1436 11:32:30.094612 [CBTSetCACLKResult] CA Dly = 33
1437 11:32:30.095113 CS Dly: 5 (0~36)
1438 11:32:30.095443 ==
1439 11:32:30.097862 Dram Type= 6, Freq= 0, CH_1, rank 1
1440 11:32:30.103895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:32:30.104327 ==
1442 11:32:30.107892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 11:32:30.114012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 11:32:30.123428 [CA 0] Center 36 (6~67) winsize 62
1445 11:32:30.127091 [CA 1] Center 36 (6~67) winsize 62
1446 11:32:30.130073 [CA 2] Center 34 (4~65) winsize 62
1447 11:32:30.133506 [CA 3] Center 33 (3~64) winsize 62
1448 11:32:30.136865 [CA 4] Center 34 (4~64) winsize 61
1449 11:32:30.140376 [CA 5] Center 33 (3~64) winsize 62
1450 11:32:30.140887
1451 11:32:30.143310 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1452 11:32:30.143738
1453 11:32:30.146961 [CATrainingPosCal] consider 2 rank data
1454 11:32:30.150359 u2DelayCellTimex100 = 270/100 ps
1455 11:32:30.153693 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1456 11:32:30.156895 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1457 11:32:30.163470 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1458 11:32:30.166855 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 11:32:30.170533 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1460 11:32:30.173599 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1461 11:32:30.174095
1462 11:32:30.176642 CA PerBit enable=1, Macro0, CA PI delay=33
1463 11:32:30.177068
1464 11:32:30.180542 [CBTSetCACLKResult] CA Dly = 33
1465 11:32:30.181047 CS Dly: 6 (0~38)
1466 11:32:30.181381
1467 11:32:30.183686 ----->DramcWriteLeveling(PI) begin...
1468 11:32:30.187077 ==
1469 11:32:30.187577 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 11:32:30.193900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 11:32:30.194627 ==
1472 11:32:30.196855 Write leveling (Byte 0): 30 => 30
1473 11:32:30.200334 Write leveling (Byte 1): 30 => 30
1474 11:32:30.203463 DramcWriteLeveling(PI) end<-----
1475 11:32:30.203961
1476 11:32:30.204294 ==
1477 11:32:30.206833 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 11:32:30.210322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 11:32:30.210824 ==
1480 11:32:30.213194 [Gating] SW mode calibration
1481 11:32:30.220216 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1482 11:32:30.223489 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1483 11:32:30.229844 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1484 11:32:30.233323 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1485 11:32:30.236621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1486 11:32:30.243137 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:32:30.246067 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:32:30.249800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:32:30.256317 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:32:30.259460 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:32:30.262950 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:32:30.269600 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:32:30.272764 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:32:30.276515 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:32:30.282932 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:32:30.286787 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:32:30.289589 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:32:30.296184 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:32:30.299995 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:32:30.302966 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:32:30.306643 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1502 11:32:30.313103 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:32:30.316368 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:32:30.319635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:32:30.326268 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:32:30.329667 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:32:30.333205 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:32:30.339525 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:32:30.343228 0 9 8 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
1510 11:32:30.346483 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 11:32:30.353251 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 11:32:30.356276 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 11:32:30.360046 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 11:32:30.366694 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 11:32:30.369686 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 11:32:30.373338 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1517 11:32:30.379642 0 10 8 | B1->B0 | 2828 2e2e | 0 1 | (0 0) (1 0)
1518 11:32:30.383160 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:32:30.386325 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:32:30.389606 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:32:30.396532 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:32:30.400191 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:32:30.403207 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:32:30.409616 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1525 11:32:30.413290 0 11 8 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
1526 11:32:30.416953 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 11:32:30.423049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 11:32:30.426587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 11:32:30.430137 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 11:32:30.436717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 11:32:30.439640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 11:32:30.443104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 11:32:30.449958 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1534 11:32:30.453195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1535 11:32:30.456442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 11:32:30.463130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 11:32:30.466219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 11:32:30.469740 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 11:32:30.476392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 11:32:30.479760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 11:32:30.483110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 11:32:30.486398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 11:32:30.493149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 11:32:30.496825 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:32:30.499957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:32:30.506438 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:32:30.509603 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:32:30.513596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:32:30.519534 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1550 11:32:30.522881 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 11:32:30.526239 Total UI for P1: 0, mck2ui 16
1552 11:32:30.529296 best dqsien dly found for B0: ( 0, 14, 8)
1553 11:32:30.532670 Total UI for P1: 0, mck2ui 16
1554 11:32:30.536857 best dqsien dly found for B1: ( 0, 14, 8)
1555 11:32:30.539522 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1556 11:32:30.543230 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1557 11:32:30.543306
1558 11:32:30.546153 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1559 11:32:30.550209 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1560 11:32:30.552897 [Gating] SW calibration Done
1561 11:32:30.552972 ==
1562 11:32:30.556131 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 11:32:30.559825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 11:32:30.562915 ==
1565 11:32:30.563018 RX Vref Scan: 0
1566 11:32:30.563091
1567 11:32:30.566342 RX Vref 0 -> 0, step: 1
1568 11:32:30.566418
1569 11:32:30.569367 RX Delay -130 -> 252, step: 16
1570 11:32:30.573183 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1571 11:32:30.576370 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1572 11:32:30.579955 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1573 11:32:30.583262 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1574 11:32:30.586568 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1575 11:32:30.593000 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1576 11:32:30.596657 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1577 11:32:30.599599 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1578 11:32:30.603296 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1579 11:32:30.606562 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1580 11:32:30.612998 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1581 11:32:30.616299 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1582 11:32:30.619747 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1583 11:32:30.623258 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1584 11:32:30.629916 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1585 11:32:30.633191 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1586 11:32:30.633294 ==
1587 11:32:30.636891 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 11:32:30.639806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 11:32:30.639906 ==
1590 11:32:30.639967 DQS Delay:
1591 11:32:30.642840 DQS0 = 0, DQS1 = 0
1592 11:32:30.642913 DQM Delay:
1593 11:32:30.646550 DQM0 = 81, DQM1 = 71
1594 11:32:30.646624 DQ Delay:
1595 11:32:30.649970 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1596 11:32:30.652830 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1597 11:32:30.656031 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1598 11:32:30.659476 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1599 11:32:30.659570
1600 11:32:30.659642
1601 11:32:30.659710 ==
1602 11:32:30.662674 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 11:32:30.666097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 11:32:30.669600 ==
1605 11:32:30.669701
1606 11:32:30.669779
1607 11:32:30.669851 TX Vref Scan disable
1608 11:32:30.672884 == TX Byte 0 ==
1609 11:32:30.676026 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1610 11:32:30.679307 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1611 11:32:30.682646 == TX Byte 1 ==
1612 11:32:30.686541 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1613 11:32:30.689725 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1614 11:32:30.693539 ==
1615 11:32:30.693693 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 11:32:30.699300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 11:32:30.699413 ==
1618 11:32:30.711526 TX Vref=22, minBit 8, minWin=27, winSum=445
1619 11:32:30.714786 TX Vref=24, minBit 8, minWin=27, winSum=447
1620 11:32:30.717920 TX Vref=26, minBit 8, minWin=27, winSum=446
1621 11:32:30.721488 TX Vref=28, minBit 1, minWin=28, winSum=454
1622 11:32:30.725004 TX Vref=30, minBit 1, minWin=28, winSum=453
1623 11:32:30.728413 TX Vref=32, minBit 9, minWin=27, winSum=453
1624 11:32:30.735001 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 28
1625 11:32:30.735129
1626 11:32:30.738738 Final TX Range 1 Vref 28
1627 11:32:30.739168
1628 11:32:30.739497 ==
1629 11:32:30.742333 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:32:30.745889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:32:30.746377 ==
1632 11:32:30.746809
1633 11:32:30.748412
1634 11:32:30.748844 TX Vref Scan disable
1635 11:32:30.752115 == TX Byte 0 ==
1636 11:32:30.755994 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1637 11:32:30.758883 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1638 11:32:30.762074 == TX Byte 1 ==
1639 11:32:30.765262 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 11:32:30.768847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 11:32:30.769360
1642 11:32:30.772503 [DATLAT]
1643 11:32:30.773022 Freq=800, CH1 RK0
1644 11:32:30.773461
1645 11:32:30.775216 DATLAT Default: 0xa
1646 11:32:30.775650 0, 0xFFFF, sum = 0
1647 11:32:30.778605 1, 0xFFFF, sum = 0
1648 11:32:30.779043 2, 0xFFFF, sum = 0
1649 11:32:30.781929 3, 0xFFFF, sum = 0
1650 11:32:30.782405 4, 0xFFFF, sum = 0
1651 11:32:30.785798 5, 0xFFFF, sum = 0
1652 11:32:30.786361 6, 0xFFFF, sum = 0
1653 11:32:30.788891 7, 0xFFFF, sum = 0
1654 11:32:30.792177 8, 0xFFFF, sum = 0
1655 11:32:30.792709 9, 0x0, sum = 1
1656 11:32:30.793153 10, 0x0, sum = 2
1657 11:32:30.795734 11, 0x0, sum = 3
1658 11:32:30.796252 12, 0x0, sum = 4
1659 11:32:30.798874 best_step = 10
1660 11:32:30.799396
1661 11:32:30.799839 ==
1662 11:32:30.802042 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 11:32:30.805095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 11:32:30.805619 ==
1665 11:32:30.808302 RX Vref Scan: 1
1666 11:32:30.808728
1667 11:32:30.809058 Set Vref Range= 32 -> 127
1668 11:32:30.809365
1669 11:32:30.812171 RX Vref 32 -> 127, step: 1
1670 11:32:30.812835
1671 11:32:30.815090 RX Delay -111 -> 252, step: 8
1672 11:32:30.815516
1673 11:32:30.818831 Set Vref, RX VrefLevel [Byte0]: 32
1674 11:32:30.822279 [Byte1]: 32
1675 11:32:30.822778
1676 11:32:30.825947 Set Vref, RX VrefLevel [Byte0]: 33
1677 11:32:30.828444 [Byte1]: 33
1678 11:32:30.832209
1679 11:32:30.832717 Set Vref, RX VrefLevel [Byte0]: 34
1680 11:32:30.835422 [Byte1]: 34
1681 11:32:30.840518
1682 11:32:30.841023 Set Vref, RX VrefLevel [Byte0]: 35
1683 11:32:30.843238 [Byte1]: 35
1684 11:32:30.847580
1685 11:32:30.848016 Set Vref, RX VrefLevel [Byte0]: 36
1686 11:32:30.851546 [Byte1]: 36
1687 11:32:30.855409
1688 11:32:30.855841 Set Vref, RX VrefLevel [Byte0]: 37
1689 11:32:30.858459 [Byte1]: 37
1690 11:32:30.863876
1691 11:32:30.864391 Set Vref, RX VrefLevel [Byte0]: 38
1692 11:32:30.866050 [Byte1]: 38
1693 11:32:30.870589
1694 11:32:30.871114 Set Vref, RX VrefLevel [Byte0]: 39
1695 11:32:30.873966 [Byte1]: 39
1696 11:32:30.877900
1697 11:32:30.878419 Set Vref, RX VrefLevel [Byte0]: 40
1698 11:32:30.881495 [Byte1]: 40
1699 11:32:30.886374
1700 11:32:30.886872 Set Vref, RX VrefLevel [Byte0]: 41
1701 11:32:30.889773 [Byte1]: 41
1702 11:32:30.893553
1703 11:32:30.894045 Set Vref, RX VrefLevel [Byte0]: 42
1704 11:32:30.896993 [Byte1]: 42
1705 11:32:30.901152
1706 11:32:30.901571 Set Vref, RX VrefLevel [Byte0]: 43
1707 11:32:30.905046 [Byte1]: 43
1708 11:32:30.908818
1709 11:32:30.909316 Set Vref, RX VrefLevel [Byte0]: 44
1710 11:32:30.912128 [Byte1]: 44
1711 11:32:30.917010
1712 11:32:30.917507 Set Vref, RX VrefLevel [Byte0]: 45
1713 11:32:30.919538 [Byte1]: 45
1714 11:32:30.923933
1715 11:32:30.924408 Set Vref, RX VrefLevel [Byte0]: 46
1716 11:32:30.927535 [Byte1]: 46
1717 11:32:30.931579
1718 11:32:30.932006 Set Vref, RX VrefLevel [Byte0]: 47
1719 11:32:30.935317 [Byte1]: 47
1720 11:32:30.939505
1721 11:32:30.940017 Set Vref, RX VrefLevel [Byte0]: 48
1722 11:32:30.942481 [Byte1]: 48
1723 11:32:30.947138
1724 11:32:30.947562 Set Vref, RX VrefLevel [Byte0]: 49
1725 11:32:30.950753 [Byte1]: 49
1726 11:32:30.954575
1727 11:32:30.955087 Set Vref, RX VrefLevel [Byte0]: 50
1728 11:32:30.958321 [Byte1]: 50
1729 11:32:30.962414
1730 11:32:30.962842 Set Vref, RX VrefLevel [Byte0]: 51
1731 11:32:30.965725 [Byte1]: 51
1732 11:32:30.969841
1733 11:32:30.970395 Set Vref, RX VrefLevel [Byte0]: 52
1734 11:32:30.973334 [Byte1]: 52
1735 11:32:30.977825
1736 11:32:30.978305 Set Vref, RX VrefLevel [Byte0]: 53
1737 11:32:30.980842 [Byte1]: 53
1738 11:32:30.985145
1739 11:32:30.985570 Set Vref, RX VrefLevel [Byte0]: 54
1740 11:32:30.988435 [Byte1]: 54
1741 11:32:30.993271
1742 11:32:30.993780 Set Vref, RX VrefLevel [Byte0]: 55
1743 11:32:30.996080 [Byte1]: 55
1744 11:32:31.000533
1745 11:32:31.000959 Set Vref, RX VrefLevel [Byte0]: 56
1746 11:32:31.004026 [Byte1]: 56
1747 11:32:31.008398
1748 11:32:31.008823 Set Vref, RX VrefLevel [Byte0]: 57
1749 11:32:31.011243 [Byte1]: 57
1750 11:32:31.016066
1751 11:32:31.016568 Set Vref, RX VrefLevel [Byte0]: 58
1752 11:32:31.018983 [Byte1]: 58
1753 11:32:31.023481
1754 11:32:31.023980 Set Vref, RX VrefLevel [Byte0]: 59
1755 11:32:31.026668 [Byte1]: 59
1756 11:32:31.030956
1757 11:32:31.031382 Set Vref, RX VrefLevel [Byte0]: 60
1758 11:32:31.034331 [Byte1]: 60
1759 11:32:31.039073
1760 11:32:31.039704 Set Vref, RX VrefLevel [Byte0]: 61
1761 11:32:31.042389 [Byte1]: 61
1762 11:32:31.046236
1763 11:32:31.046666 Set Vref, RX VrefLevel [Byte0]: 62
1764 11:32:31.050203 [Byte1]: 62
1765 11:32:31.054150
1766 11:32:31.054656 Set Vref, RX VrefLevel [Byte0]: 63
1767 11:32:31.057883 [Byte1]: 63
1768 11:32:31.061815
1769 11:32:31.062377 Set Vref, RX VrefLevel [Byte0]: 64
1770 11:32:31.065410 [Byte1]: 64
1771 11:32:31.069635
1772 11:32:31.070196 Set Vref, RX VrefLevel [Byte0]: 65
1773 11:32:31.073063 [Byte1]: 65
1774 11:32:31.077071
1775 11:32:31.077548 Set Vref, RX VrefLevel [Byte0]: 66
1776 11:32:31.080345 [Byte1]: 66
1777 11:32:31.084640
1778 11:32:31.085135 Set Vref, RX VrefLevel [Byte0]: 67
1779 11:32:31.087933 [Byte1]: 67
1780 11:32:31.092569
1781 11:32:31.093064 Set Vref, RX VrefLevel [Byte0]: 68
1782 11:32:31.095870 [Byte1]: 68
1783 11:32:31.100182
1784 11:32:31.100677 Set Vref, RX VrefLevel [Byte0]: 69
1785 11:32:31.103370 [Byte1]: 69
1786 11:32:31.107504
1787 11:32:31.107922 Set Vref, RX VrefLevel [Byte0]: 70
1788 11:32:31.111527 [Byte1]: 70
1789 11:32:31.115540
1790 11:32:31.116037 Set Vref, RX VrefLevel [Byte0]: 71
1791 11:32:31.118415 [Byte1]: 71
1792 11:32:31.122833
1793 11:32:31.123401 Set Vref, RX VrefLevel [Byte0]: 72
1794 11:32:31.126533 [Byte1]: 72
1795 11:32:31.130598
1796 11:32:31.131027 Set Vref, RX VrefLevel [Byte0]: 73
1797 11:32:31.134146 [Byte1]: 73
1798 11:32:31.138226
1799 11:32:31.138747 Set Vref, RX VrefLevel [Byte0]: 74
1800 11:32:31.141387 [Byte1]: 74
1801 11:32:31.146045
1802 11:32:31.146501 Set Vref, RX VrefLevel [Byte0]: 75
1803 11:32:31.148872 [Byte1]: 75
1804 11:32:31.153913
1805 11:32:31.154459 Set Vref, RX VrefLevel [Byte0]: 76
1806 11:32:31.156842 [Byte1]: 76
1807 11:32:31.161386
1808 11:32:31.161896 Set Vref, RX VrefLevel [Byte0]: 77
1809 11:32:31.164255 [Byte1]: 77
1810 11:32:31.169171
1811 11:32:31.169680 Set Vref, RX VrefLevel [Byte0]: 78
1812 11:32:31.172205 [Byte1]: 78
1813 11:32:31.176797
1814 11:32:31.177298 Final RX Vref Byte 0 = 57 to rank0
1815 11:32:31.179898 Final RX Vref Byte 1 = 52 to rank0
1816 11:32:31.182693 Final RX Vref Byte 0 = 57 to rank1
1817 11:32:31.186823 Final RX Vref Byte 1 = 52 to rank1==
1818 11:32:31.190426 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 11:32:31.196305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 11:32:31.196832 ==
1821 11:32:31.197168 DQS Delay:
1822 11:32:31.197478 DQS0 = 0, DQS1 = 0
1823 11:32:31.199527 DQM Delay:
1824 11:32:31.199952 DQM0 = 80, DQM1 = 70
1825 11:32:31.202974 DQ Delay:
1826 11:32:31.206385 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1827 11:32:31.209849 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1828 11:32:31.210405 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1829 11:32:31.216541 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1830 11:32:31.217046
1831 11:32:31.217378
1832 11:32:31.223369 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1833 11:32:31.226445 CH1 RK0: MR19=606, MR18=151F
1834 11:32:31.232696 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1835 11:32:31.233173
1836 11:32:31.236371 ----->DramcWriteLeveling(PI) begin...
1837 11:32:31.236950 ==
1838 11:32:31.239559 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 11:32:31.243107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 11:32:31.243537 ==
1841 11:32:31.246649 Write leveling (Byte 0): 28 => 28
1842 11:32:31.249665 Write leveling (Byte 1): 31 => 31
1843 11:32:31.252945 DramcWriteLeveling(PI) end<-----
1844 11:32:31.253459
1845 11:32:31.253790 ==
1846 11:32:31.256216 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 11:32:31.260089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 11:32:31.260598 ==
1849 11:32:31.262931 [Gating] SW mode calibration
1850 11:32:31.269654 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 11:32:31.276743 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 11:32:31.279686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1853 11:32:31.283066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1854 11:32:31.289879 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:32:31.292872 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:32:31.296609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:32:31.302633 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:32:31.306067 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:32:31.309092 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:32:31.316309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:32:31.319157 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:32:31.322945 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:32:31.329298 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:32:31.332803 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:32:31.335672 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:32:31.342757 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:32:31.346228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:32:31.349711 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:32:31.352653 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1870 11:32:31.359542 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 11:32:31.362924 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:32:31.366065 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:32:31.372975 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:32:31.376177 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:32:31.379806 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:32:31.385801 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:32:31.389598 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1878 11:32:31.392866 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1879 11:32:31.399210 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 11:32:31.402600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 11:32:31.406247 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 11:32:31.412405 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 11:32:31.415569 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 11:32:31.418691 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 11:32:31.425182 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 1)
1886 11:32:31.428896 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:32:31.432563 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:32:31.438739 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:32:31.442061 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:32:31.445288 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:32:31.451820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:32:31.455576 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:32:31.458868 0 11 4 | B1->B0 | 3131 4040 | 0 0 | (0 0) (1 1)
1894 11:32:31.465119 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1895 11:32:31.468979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 11:32:31.472103 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 11:32:31.478792 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 11:32:31.481978 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 11:32:31.485461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 11:32:31.488835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 11:32:31.495362 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1902 11:32:31.498905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1903 11:32:31.502144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:32:31.508426 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:32:31.511887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:32:31.515455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:32:31.521790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:32:31.525000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:32:31.528856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:32:31.535061 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:32:31.538312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:32:31.541820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:32:31.548288 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:32:31.551811 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:32:31.555065 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:32:31.562400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:32:31.565522 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1918 11:32:31.568650 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1919 11:32:31.571734 Total UI for P1: 0, mck2ui 16
1920 11:32:31.574946 best dqsien dly found for B0: ( 0, 14, 4)
1921 11:32:31.578395 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:32:31.581921 Total UI for P1: 0, mck2ui 16
1923 11:32:31.585533 best dqsien dly found for B1: ( 0, 14, 6)
1924 11:32:31.588468 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1925 11:32:31.595441 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1926 11:32:31.595516
1927 11:32:31.598300 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1928 11:32:31.601910 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1929 11:32:31.604908 [Gating] SW calibration Done
1930 11:32:31.604984 ==
1931 11:32:31.608465 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:32:31.611751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:32:31.611827 ==
1934 11:32:31.611886 RX Vref Scan: 0
1935 11:32:31.611940
1936 11:32:31.614979 RX Vref 0 -> 0, step: 1
1937 11:32:31.615054
1938 11:32:31.618484 RX Delay -130 -> 252, step: 16
1939 11:32:31.621674 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1940 11:32:31.625070 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1941 11:32:31.631807 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1942 11:32:31.635275 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1943 11:32:31.638485 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1944 11:32:31.641978 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1945 11:32:31.645176 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1946 11:32:31.651960 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1947 11:32:31.655176 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1948 11:32:31.658695 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1949 11:32:31.661694 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1950 11:32:31.664982 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1951 11:32:31.671472 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1952 11:32:31.675106 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1953 11:32:31.678730 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1954 11:32:31.681767 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1955 11:32:31.681843 ==
1956 11:32:31.685145 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:32:31.691707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:32:31.691783 ==
1959 11:32:31.691841 DQS Delay:
1960 11:32:31.691895 DQS0 = 0, DQS1 = 0
1961 11:32:31.695213 DQM Delay:
1962 11:32:31.695289 DQM0 = 78, DQM1 = 74
1963 11:32:31.698472 DQ Delay:
1964 11:32:31.701754 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1965 11:32:31.705071 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1966 11:32:31.708242 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1967 11:32:31.711612 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1968 11:32:31.711686
1969 11:32:31.711744
1970 11:32:31.711798 ==
1971 11:32:31.715012 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:32:31.718489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:32:31.718565 ==
1974 11:32:31.718623
1975 11:32:31.718676
1976 11:32:31.721908 TX Vref Scan disable
1977 11:32:31.721984 == TX Byte 0 ==
1978 11:32:31.728241 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 11:32:31.731606 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 11:32:31.731682 == TX Byte 1 ==
1981 11:32:31.738341 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1982 11:32:31.741489 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1983 11:32:31.741564 ==
1984 11:32:31.745092 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:32:31.748487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:32:31.748562 ==
1987 11:32:31.762325 TX Vref=22, minBit 0, minWin=28, winSum=452
1988 11:32:31.765348 TX Vref=24, minBit 0, minWin=28, winSum=453
1989 11:32:31.769059 TX Vref=26, minBit 0, minWin=28, winSum=456
1990 11:32:31.772355 TX Vref=28, minBit 3, minWin=28, winSum=458
1991 11:32:31.775665 TX Vref=30, minBit 8, minWin=28, winSum=458
1992 11:32:31.779042 TX Vref=32, minBit 2, minWin=28, winSum=457
1993 11:32:31.785771 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 28
1994 11:32:31.785847
1995 11:32:31.789020 Final TX Range 1 Vref 28
1996 11:32:31.789096
1997 11:32:31.789154 ==
1998 11:32:31.792003 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 11:32:31.795755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 11:32:31.795855 ==
2001 11:32:31.795917
2002 11:32:31.798894
2003 11:32:31.798969 TX Vref Scan disable
2004 11:32:31.802261 == TX Byte 0 ==
2005 11:32:31.805686 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 11:32:31.809075 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 11:32:31.812637 == TX Byte 1 ==
2008 11:32:31.815476 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2009 11:32:31.818965 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2010 11:32:31.822416
2011 11:32:31.822491 [DATLAT]
2012 11:32:31.822548 Freq=800, CH1 RK1
2013 11:32:31.822603
2014 11:32:31.825633 DATLAT Default: 0xa
2015 11:32:31.825709 0, 0xFFFF, sum = 0
2016 11:32:31.829102 1, 0xFFFF, sum = 0
2017 11:32:31.829180 2, 0xFFFF, sum = 0
2018 11:32:31.832616 3, 0xFFFF, sum = 0
2019 11:32:31.832693 4, 0xFFFF, sum = 0
2020 11:32:31.836043 5, 0xFFFF, sum = 0
2021 11:32:31.836119 6, 0xFFFF, sum = 0
2022 11:32:31.838786 7, 0xFFFF, sum = 0
2023 11:32:31.838861 8, 0xFFFF, sum = 0
2024 11:32:31.842485 9, 0x0, sum = 1
2025 11:32:31.842561 10, 0x0, sum = 2
2026 11:32:31.845434 11, 0x0, sum = 3
2027 11:32:31.845510 12, 0x0, sum = 4
2028 11:32:31.848778 best_step = 10
2029 11:32:31.848853
2030 11:32:31.848912 ==
2031 11:32:31.852359 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:32:31.855577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:32:31.855652 ==
2034 11:32:31.859143 RX Vref Scan: 0
2035 11:32:31.859218
2036 11:32:31.859276 RX Vref 0 -> 0, step: 1
2037 11:32:31.859349
2038 11:32:31.861951 RX Delay -111 -> 252, step: 8
2039 11:32:31.869190 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2040 11:32:31.872089 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2041 11:32:31.875593 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2042 11:32:31.879315 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2043 11:32:31.882410 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2044 11:32:31.889451 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2045 11:32:31.892490 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2046 11:32:31.895878 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2047 11:32:31.899152 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2048 11:32:31.902264 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2049 11:32:31.909190 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2050 11:32:31.912540 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2051 11:32:31.915806 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2052 11:32:31.919334 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2053 11:32:31.922375 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2054 11:32:31.928938 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2055 11:32:31.929013 ==
2056 11:32:31.932612 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 11:32:31.935843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 11:32:31.935918 ==
2059 11:32:31.935977 DQS Delay:
2060 11:32:31.939102 DQS0 = 0, DQS1 = 0
2061 11:32:31.939176 DQM Delay:
2062 11:32:31.942357 DQM0 = 77, DQM1 = 72
2063 11:32:31.942432 DQ Delay:
2064 11:32:31.945706 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2065 11:32:31.948993 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2066 11:32:31.952458 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2067 11:32:31.955802 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2068 11:32:31.955876
2069 11:32:31.955934
2070 11:32:31.962246 [DQSOSCAuto] RK1, (LSB)MR18= 0x263e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2071 11:32:31.965914 CH1 RK1: MR19=606, MR18=263E
2072 11:32:31.972428 CH1_RK1: MR19=0x606, MR18=0x263E, DQSOSC=394, MR23=63, INC=95, DEC=63
2073 11:32:31.975783 [RxdqsGatingPostProcess] freq 800
2074 11:32:31.983107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 11:32:31.983183 Pre-setting of DQS Precalculation
2076 11:32:31.989472 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 11:32:31.995891 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 11:32:32.002521 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 11:32:32.002596
2080 11:32:32.002654
2081 11:32:32.006023 [Calibration Summary] 1600 Mbps
2082 11:32:32.009576 CH 0, Rank 0
2083 11:32:32.009651 SW Impedance : PASS
2084 11:32:32.012697 DUTY Scan : NO K
2085 11:32:32.015775 ZQ Calibration : PASS
2086 11:32:32.015850 Jitter Meter : NO K
2087 11:32:32.019340 CBT Training : PASS
2088 11:32:32.019416 Write leveling : PASS
2089 11:32:32.022776 RX DQS gating : PASS
2090 11:32:32.025885 RX DQ/DQS(RDDQC) : PASS
2091 11:32:32.025959 TX DQ/DQS : PASS
2092 11:32:32.029328 RX DATLAT : PASS
2093 11:32:32.032884 RX DQ/DQS(Engine): PASS
2094 11:32:32.032958 TX OE : NO K
2095 11:32:32.036348 All Pass.
2096 11:32:32.036423
2097 11:32:32.036480 CH 0, Rank 1
2098 11:32:32.039427 SW Impedance : PASS
2099 11:32:32.039502 DUTY Scan : NO K
2100 11:32:32.042887 ZQ Calibration : PASS
2101 11:32:32.045864 Jitter Meter : NO K
2102 11:32:32.045939 CBT Training : PASS
2103 11:32:32.049204 Write leveling : PASS
2104 11:32:32.052660 RX DQS gating : PASS
2105 11:32:32.052734 RX DQ/DQS(RDDQC) : PASS
2106 11:32:32.055986 TX DQ/DQS : PASS
2107 11:32:32.056062 RX DATLAT : PASS
2108 11:32:32.059521 RX DQ/DQS(Engine): PASS
2109 11:32:32.062705 TX OE : NO K
2110 11:32:32.062781 All Pass.
2111 11:32:32.062839
2112 11:32:32.062892 CH 1, Rank 0
2113 11:32:32.066021 SW Impedance : PASS
2114 11:32:32.069230 DUTY Scan : NO K
2115 11:32:32.069305 ZQ Calibration : PASS
2116 11:32:32.072503 Jitter Meter : NO K
2117 11:32:32.076445 CBT Training : PASS
2118 11:32:32.076520 Write leveling : PASS
2119 11:32:32.079262 RX DQS gating : PASS
2120 11:32:32.082741 RX DQ/DQS(RDDQC) : PASS
2121 11:32:32.082816 TX DQ/DQS : PASS
2122 11:32:32.086404 RX DATLAT : PASS
2123 11:32:32.089441 RX DQ/DQS(Engine): PASS
2124 11:32:32.089516 TX OE : NO K
2125 11:32:32.089574 All Pass.
2126 11:32:32.089628
2127 11:32:32.092839 CH 1, Rank 1
2128 11:32:32.096363 SW Impedance : PASS
2129 11:32:32.096438 DUTY Scan : NO K
2130 11:32:32.099780 ZQ Calibration : PASS
2131 11:32:32.099855 Jitter Meter : NO K
2132 11:32:32.103234 CBT Training : PASS
2133 11:32:32.106135 Write leveling : PASS
2134 11:32:32.106223 RX DQS gating : PASS
2135 11:32:32.109572 RX DQ/DQS(RDDQC) : PASS
2136 11:32:32.113178 TX DQ/DQS : PASS
2137 11:32:32.113254 RX DATLAT : PASS
2138 11:32:32.115921 RX DQ/DQS(Engine): PASS
2139 11:32:32.119330 TX OE : NO K
2140 11:32:32.119405 All Pass.
2141 11:32:32.119464
2142 11:32:32.119518 DramC Write-DBI off
2143 11:32:32.123232 PER_BANK_REFRESH: Hybrid Mode
2144 11:32:32.126503 TX_TRACKING: ON
2145 11:32:32.129358 [GetDramInforAfterCalByMRR] Vendor 6.
2146 11:32:32.132914 [GetDramInforAfterCalByMRR] Revision 606.
2147 11:32:32.136117 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 11:32:32.136193 MR0 0x3b3b
2149 11:32:32.139628 MR8 0x5151
2150 11:32:32.143112 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 11:32:32.143187
2152 11:32:32.143245 MR0 0x3b3b
2153 11:32:32.143299 MR8 0x5151
2154 11:32:32.149573 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 11:32:32.149649
2156 11:32:32.156449 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 11:32:32.159676 [FAST_K] Save calibration result to emmc
2158 11:32:32.162780 [FAST_K] Save calibration result to emmc
2159 11:32:32.166755 dram_init: config_dvfs: 1
2160 11:32:32.169650 dramc_set_vcore_voltage set vcore to 662500
2161 11:32:32.173211 Read voltage for 1200, 2
2162 11:32:32.173285 Vio18 = 0
2163 11:32:32.176302 Vcore = 662500
2164 11:32:32.176377 Vdram = 0
2165 11:32:32.176436 Vddq = 0
2166 11:32:32.176490 Vmddr = 0
2167 11:32:32.182811 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 11:32:32.190212 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 11:32:32.190289 MEM_TYPE=3, freq_sel=15
2170 11:32:32.193042 sv_algorithm_assistance_LP4_1600
2171 11:32:32.196397 ============ PULL DRAM RESETB DOWN ============
2172 11:32:32.202980 ========== PULL DRAM RESETB DOWN end =========
2173 11:32:32.206381 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 11:32:32.209992 ===================================
2175 11:32:32.212913 LPDDR4 DRAM CONFIGURATION
2176 11:32:32.216539 ===================================
2177 11:32:32.216615 EX_ROW_EN[0] = 0x0
2178 11:32:32.219483 EX_ROW_EN[1] = 0x0
2179 11:32:32.219558 LP4Y_EN = 0x0
2180 11:32:32.222788 WORK_FSP = 0x0
2181 11:32:32.222864 WL = 0x4
2182 11:32:32.226113 RL = 0x4
2183 11:32:32.226189 BL = 0x2
2184 11:32:32.229586 RPST = 0x0
2185 11:32:32.229662 RD_PRE = 0x0
2186 11:32:32.233373 WR_PRE = 0x1
2187 11:32:32.236423 WR_PST = 0x0
2188 11:32:32.236498 DBI_WR = 0x0
2189 11:32:32.239548 DBI_RD = 0x0
2190 11:32:32.239623 OTF = 0x1
2191 11:32:32.242761 ===================================
2192 11:32:32.246020 ===================================
2193 11:32:32.246096 ANA top config
2194 11:32:32.249844 ===================================
2195 11:32:32.252722 DLL_ASYNC_EN = 0
2196 11:32:32.256136 ALL_SLAVE_EN = 0
2197 11:32:32.259945 NEW_RANK_MODE = 1
2198 11:32:32.262649 DLL_IDLE_MODE = 1
2199 11:32:32.262725 LP45_APHY_COMB_EN = 1
2200 11:32:32.266114 TX_ODT_DIS = 1
2201 11:32:32.269832 NEW_8X_MODE = 1
2202 11:32:32.272737 ===================================
2203 11:32:32.276103 ===================================
2204 11:32:32.279679 data_rate = 2400
2205 11:32:32.283432 CKR = 1
2206 11:32:32.283507 DQ_P2S_RATIO = 8
2207 11:32:32.286322 ===================================
2208 11:32:32.289767 CA_P2S_RATIO = 8
2209 11:32:32.292673 DQ_CA_OPEN = 0
2210 11:32:32.296101 DQ_SEMI_OPEN = 0
2211 11:32:32.299878 CA_SEMI_OPEN = 0
2212 11:32:32.299953 CA_FULL_RATE = 0
2213 11:32:32.302717 DQ_CKDIV4_EN = 0
2214 11:32:32.306268 CA_CKDIV4_EN = 0
2215 11:32:32.309826 CA_PREDIV_EN = 0
2216 11:32:32.313075 PH8_DLY = 17
2217 11:32:32.316177 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 11:32:32.316253 DQ_AAMCK_DIV = 4
2219 11:32:32.319686 CA_AAMCK_DIV = 4
2220 11:32:32.323043 CA_ADMCK_DIV = 4
2221 11:32:32.326415 DQ_TRACK_CA_EN = 0
2222 11:32:32.329613 CA_PICK = 1200
2223 11:32:32.333309 CA_MCKIO = 1200
2224 11:32:32.336575 MCKIO_SEMI = 0
2225 11:32:32.336651 PLL_FREQ = 2366
2226 11:32:32.339591 DQ_UI_PI_RATIO = 32
2227 11:32:32.342833 CA_UI_PI_RATIO = 0
2228 11:32:32.346658 ===================================
2229 11:32:32.350278 ===================================
2230 11:32:32.353005 memory_type:LPDDR4
2231 11:32:32.353080 GP_NUM : 10
2232 11:32:32.356736 SRAM_EN : 1
2233 11:32:32.359670 MD32_EN : 0
2234 11:32:32.363049 ===================================
2235 11:32:32.363124 [ANA_INIT] >>>>>>>>>>>>>>
2236 11:32:32.366079 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 11:32:32.369677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 11:32:32.372719 ===================================
2239 11:32:32.376090 data_rate = 2400,PCW = 0X5b00
2240 11:32:32.379729 ===================================
2241 11:32:32.382884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 11:32:32.389527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 11:32:32.392871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 11:32:32.399802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 11:32:32.402724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 11:32:32.406341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 11:32:32.406450 [ANA_INIT] flow start
2248 11:32:32.410133 [ANA_INIT] PLL >>>>>>>>
2249 11:32:32.413113 [ANA_INIT] PLL <<<<<<<<
2250 11:32:32.416285 [ANA_INIT] MIDPI >>>>>>>>
2251 11:32:32.416360 [ANA_INIT] MIDPI <<<<<<<<
2252 11:32:32.419815 [ANA_INIT] DLL >>>>>>>>
2253 11:32:32.422820 [ANA_INIT] DLL <<<<<<<<
2254 11:32:32.422894 [ANA_INIT] flow end
2255 11:32:32.425931 ============ LP4 DIFF to SE enter ============
2256 11:32:32.432614 ============ LP4 DIFF to SE exit ============
2257 11:32:32.432691 [ANA_INIT] <<<<<<<<<<<<<
2258 11:32:32.435799 [Flow] Enable top DCM control >>>>>
2259 11:32:32.439301 [Flow] Enable top DCM control <<<<<
2260 11:32:32.442741 Enable DLL master slave shuffle
2261 11:32:32.449035 ==============================================================
2262 11:32:32.449110 Gating Mode config
2263 11:32:32.456073 ==============================================================
2264 11:32:32.459091 Config description:
2265 11:32:32.469010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 11:32:32.475689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 11:32:32.479005 SELPH_MODE 0: By rank 1: By Phase
2268 11:32:32.485844 ==============================================================
2269 11:32:32.489303 GAT_TRACK_EN = 1
2270 11:32:32.489379 RX_GATING_MODE = 2
2271 11:32:32.492389 RX_GATING_TRACK_MODE = 2
2272 11:32:32.495906 SELPH_MODE = 1
2273 11:32:32.499233 PICG_EARLY_EN = 1
2274 11:32:32.502786 VALID_LAT_VALUE = 1
2275 11:32:32.509377 ==============================================================
2276 11:32:32.512428 Enter into Gating configuration >>>>
2277 11:32:32.515697 Exit from Gating configuration <<<<
2278 11:32:32.519663 Enter into DVFS_PRE_config >>>>>
2279 11:32:32.528891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 11:32:32.532657 Exit from DVFS_PRE_config <<<<<
2281 11:32:32.535811 Enter into PICG configuration >>>>
2282 11:32:32.539260 Exit from PICG configuration <<<<
2283 11:32:32.542610 [RX_INPUT] configuration >>>>>
2284 11:32:32.545504 [RX_INPUT] configuration <<<<<
2285 11:32:32.549097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 11:32:32.555896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 11:32:32.562234 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 11:32:32.566001 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 11:32:32.572870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 11:32:32.579515 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 11:32:32.582550 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 11:32:32.585865 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 11:32:32.592244 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 11:32:32.595773 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 11:32:32.598929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 11:32:32.605910 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 11:32:32.609130 ===================================
2298 11:32:32.609246 LPDDR4 DRAM CONFIGURATION
2299 11:32:32.612451 ===================================
2300 11:32:32.615712 EX_ROW_EN[0] = 0x0
2301 11:32:32.615818 EX_ROW_EN[1] = 0x0
2302 11:32:32.619529 LP4Y_EN = 0x0
2303 11:32:32.622134 WORK_FSP = 0x0
2304 11:32:32.622223 WL = 0x4
2305 11:32:32.625686 RL = 0x4
2306 11:32:32.625761 BL = 0x2
2307 11:32:32.629094 RPST = 0x0
2308 11:32:32.629169 RD_PRE = 0x0
2309 11:32:32.632527 WR_PRE = 0x1
2310 11:32:32.632603 WR_PST = 0x0
2311 11:32:32.635429 DBI_WR = 0x0
2312 11:32:32.635505 DBI_RD = 0x0
2313 11:32:32.639265 OTF = 0x1
2314 11:32:32.642084 ===================================
2315 11:32:32.645902 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 11:32:32.648973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 11:32:32.655818 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 11:32:32.655894 ===================================
2319 11:32:32.659098 LPDDR4 DRAM CONFIGURATION
2320 11:32:32.662776 ===================================
2321 11:32:32.666310 EX_ROW_EN[0] = 0x10
2322 11:32:32.666386 EX_ROW_EN[1] = 0x0
2323 11:32:32.669099 LP4Y_EN = 0x0
2324 11:32:32.669174 WORK_FSP = 0x0
2325 11:32:32.672526 WL = 0x4
2326 11:32:32.672601 RL = 0x4
2327 11:32:32.676242 BL = 0x2
2328 11:32:32.676317 RPST = 0x0
2329 11:32:32.679022 RD_PRE = 0x0
2330 11:32:32.682331 WR_PRE = 0x1
2331 11:32:32.682406 WR_PST = 0x0
2332 11:32:32.685756 DBI_WR = 0x0
2333 11:32:32.685830 DBI_RD = 0x0
2334 11:32:32.689221 OTF = 0x1
2335 11:32:32.692089 ===================================
2336 11:32:32.695929 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 11:32:32.698784 ==
2338 11:32:32.698858 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 11:32:32.705695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 11:32:32.705771 ==
2341 11:32:32.708984 [Duty_Offset_Calibration]
2342 11:32:32.709063 B0:2 B1:0 CA:3
2343 11:32:32.709124
2344 11:32:32.712241 [DutyScan_Calibration_Flow] k_type=0
2345 11:32:32.721979
2346 11:32:32.722185 ==CLK 0==
2347 11:32:32.724947 Final CLK duty delay cell = 0
2348 11:32:32.728698 [0] MAX Duty = 5062%(X100), DQS PI = 20
2349 11:32:32.731739 [0] MIN Duty = 4875%(X100), DQS PI = 58
2350 11:32:32.731814 [0] AVG Duty = 4968%(X100)
2351 11:32:32.734965
2352 11:32:32.738596 CH0 CLK Duty spec in!! Max-Min= 187%
2353 11:32:32.741850 [DutyScan_Calibration_Flow] ====Done====
2354 11:32:32.741925
2355 11:32:32.744943 [DutyScan_Calibration_Flow] k_type=1
2356 11:32:32.760080
2357 11:32:32.760158 ==DQS 0 ==
2358 11:32:32.763498 Final DQS duty delay cell = 0
2359 11:32:32.766929 [0] MAX Duty = 5062%(X100), DQS PI = 18
2360 11:32:32.770044 [0] MIN Duty = 4907%(X100), DQS PI = 2
2361 11:32:32.770124 [0] AVG Duty = 4984%(X100)
2362 11:32:32.773592
2363 11:32:32.773665 ==DQS 1 ==
2364 11:32:32.777052 Final DQS duty delay cell = -4
2365 11:32:32.780260 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2366 11:32:32.783673 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2367 11:32:32.787220 [-4] AVG Duty = 4922%(X100)
2368 11:32:32.787295
2369 11:32:32.790242 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2370 11:32:32.790317
2371 11:32:32.793435 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2372 11:32:32.796625 [DutyScan_Calibration_Flow] ====Done====
2373 11:32:32.796699
2374 11:32:32.800085 [DutyScan_Calibration_Flow] k_type=3
2375 11:32:32.817497
2376 11:32:32.817571 ==DQM 0 ==
2377 11:32:32.820728 Final DQM duty delay cell = 0
2378 11:32:32.824258 [0] MAX Duty = 5124%(X100), DQS PI = 28
2379 11:32:32.827634 [0] MIN Duty = 4876%(X100), DQS PI = 0
2380 11:32:32.827709 [0] AVG Duty = 5000%(X100)
2381 11:32:32.831049
2382 11:32:32.831123 ==DQM 1 ==
2383 11:32:32.834559 Final DQM duty delay cell = 4
2384 11:32:32.837663 [4] MAX Duty = 5124%(X100), DQS PI = 50
2385 11:32:32.841246 [4] MIN Duty = 5000%(X100), DQS PI = 10
2386 11:32:32.841321 [4] AVG Duty = 5062%(X100)
2387 11:32:32.844100
2388 11:32:32.847426 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2389 11:32:32.847501
2390 11:32:32.851146 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2391 11:32:32.854874 [DutyScan_Calibration_Flow] ====Done====
2392 11:32:32.854949
2393 11:32:32.857609 [DutyScan_Calibration_Flow] k_type=2
2394 11:32:32.872867
2395 11:32:32.872942 ==DQ 0 ==
2396 11:32:32.876132 Final DQ duty delay cell = -4
2397 11:32:32.879632 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2398 11:32:32.882316 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2399 11:32:32.885789 [-4] AVG Duty = 4969%(X100)
2400 11:32:32.885863
2401 11:32:32.885921 ==DQ 1 ==
2402 11:32:32.888982 Final DQ duty delay cell = -4
2403 11:32:32.892392 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2404 11:32:32.895746 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2405 11:32:32.898991 [-4] AVG Duty = 4938%(X100)
2406 11:32:32.899065
2407 11:32:32.902237 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2408 11:32:32.902312
2409 11:32:32.905681 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2410 11:32:32.908934 [DutyScan_Calibration_Flow] ====Done====
2411 11:32:32.909008 ==
2412 11:32:32.912495 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 11:32:32.915853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 11:32:32.915929 ==
2415 11:32:32.919472 [Duty_Offset_Calibration]
2416 11:32:32.919547 B0:1 B1:-2 CA:0
2417 11:32:32.919605
2418 11:32:32.922582 [DutyScan_Calibration_Flow] k_type=0
2419 11:32:32.933077
2420 11:32:32.933151 ==CLK 0==
2421 11:32:32.936494 Final CLK duty delay cell = 0
2422 11:32:32.939703 [0] MAX Duty = 5031%(X100), DQS PI = 18
2423 11:32:32.943167 [0] MIN Duty = 4844%(X100), DQS PI = 58
2424 11:32:32.943242 [0] AVG Duty = 4937%(X100)
2425 11:32:32.946496
2426 11:32:32.949745 CH1 CLK Duty spec in!! Max-Min= 187%
2427 11:32:32.953319 [DutyScan_Calibration_Flow] ====Done====
2428 11:32:32.953393
2429 11:32:32.956604 [DutyScan_Calibration_Flow] k_type=1
2430 11:32:32.971790
2431 11:32:32.971864 ==DQS 0 ==
2432 11:32:32.974987 Final DQS duty delay cell = -4
2433 11:32:32.978323 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2434 11:32:32.981841 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2435 11:32:32.985262 [-4] AVG Duty = 4938%(X100)
2436 11:32:32.985348
2437 11:32:32.985438 ==DQS 1 ==
2438 11:32:32.988233 Final DQS duty delay cell = 0
2439 11:32:32.991526 [0] MAX Duty = 5062%(X100), DQS PI = 0
2440 11:32:32.995025 [0] MIN Duty = 4875%(X100), DQS PI = 26
2441 11:32:32.998138 [0] AVG Duty = 4968%(X100)
2442 11:32:32.998213
2443 11:32:33.001492 CH1 DQS 0 Duty spec in!! Max-Min= 62%
2444 11:32:33.001568
2445 11:32:33.004863 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2446 11:32:33.008409 [DutyScan_Calibration_Flow] ====Done====
2447 11:32:33.008488
2448 11:32:33.011604 [DutyScan_Calibration_Flow] k_type=3
2449 11:32:33.028394
2450 11:32:33.028485 ==DQM 0 ==
2451 11:32:33.031221 Final DQM duty delay cell = 0
2452 11:32:33.034888 [0] MAX Duty = 5000%(X100), DQS PI = 22
2453 11:32:33.038328 [0] MIN Duty = 4876%(X100), DQS PI = 0
2454 11:32:33.038394 [0] AVG Duty = 4938%(X100)
2455 11:32:33.041829
2456 11:32:33.041914 ==DQM 1 ==
2457 11:32:33.044736 Final DQM duty delay cell = 0
2458 11:32:33.048004 [0] MAX Duty = 5031%(X100), DQS PI = 36
2459 11:32:33.051607 [0] MIN Duty = 4907%(X100), DQS PI = 4
2460 11:32:33.051687 [0] AVG Duty = 4969%(X100)
2461 11:32:33.054936
2462 11:32:33.058228 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2463 11:32:33.058293
2464 11:32:33.061437 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2465 11:32:33.064856 [DutyScan_Calibration_Flow] ====Done====
2466 11:32:33.064921
2467 11:32:33.068037 [DutyScan_Calibration_Flow] k_type=2
2468 11:32:33.084229
2469 11:32:33.084321 ==DQ 0 ==
2470 11:32:33.087935 Final DQ duty delay cell = 0
2471 11:32:33.091365 [0] MAX Duty = 5062%(X100), DQS PI = 12
2472 11:32:33.094255 [0] MIN Duty = 4907%(X100), DQS PI = 56
2473 11:32:33.094344 [0] AVG Duty = 4984%(X100)
2474 11:32:33.098205
2475 11:32:33.098289 ==DQ 1 ==
2476 11:32:33.100822 Final DQ duty delay cell = 0
2477 11:32:33.104509 [0] MAX Duty = 5125%(X100), DQS PI = 36
2478 11:32:33.107590 [0] MIN Duty = 4969%(X100), DQS PI = 26
2479 11:32:33.107684 [0] AVG Duty = 5047%(X100)
2480 11:32:33.107768
2481 11:32:33.114373 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2482 11:32:33.114445
2483 11:32:33.117512 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2484 11:32:33.121287 [DutyScan_Calibration_Flow] ====Done====
2485 11:32:33.124181 nWR fixed to 30
2486 11:32:33.124292 [ModeRegInit_LP4] CH0 RK0
2487 11:32:33.127837 [ModeRegInit_LP4] CH0 RK1
2488 11:32:33.131092 [ModeRegInit_LP4] CH1 RK0
2489 11:32:33.134590 [ModeRegInit_LP4] CH1 RK1
2490 11:32:33.134721 match AC timing 7
2491 11:32:33.137458 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 11:32:33.144065 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 11:32:33.147638 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 11:32:33.150731 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 11:32:33.157441 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 11:32:33.157532 ==
2497 11:32:33.160778 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 11:32:33.164580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 11:32:33.164664 ==
2500 11:32:33.170903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 11:32:33.177589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 11:32:33.184466 [CA 0] Center 40 (10~71) winsize 62
2503 11:32:33.187825 [CA 1] Center 39 (9~70) winsize 62
2504 11:32:33.191290 [CA 2] Center 36 (6~66) winsize 61
2505 11:32:33.194734 [CA 3] Center 35 (5~66) winsize 62
2506 11:32:33.197716 [CA 4] Center 34 (4~65) winsize 62
2507 11:32:33.201042 [CA 5] Center 33 (3~63) winsize 61
2508 11:32:33.201117
2509 11:32:33.204524 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2510 11:32:33.204600
2511 11:32:33.207986 [CATrainingPosCal] consider 1 rank data
2512 11:32:33.211322 u2DelayCellTimex100 = 270/100 ps
2513 11:32:33.214180 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2514 11:32:33.221019 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 11:32:33.224458 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2516 11:32:33.228082 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 11:32:33.231130 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2518 11:32:33.234472 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 11:32:33.234549
2520 11:32:33.237963 CA PerBit enable=1, Macro0, CA PI delay=33
2521 11:32:33.238054
2522 11:32:33.241358 [CBTSetCACLKResult] CA Dly = 33
2523 11:32:33.241433 CS Dly: 7 (0~38)
2524 11:32:33.244402 ==
2525 11:32:33.248016 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 11:32:33.250943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 11:32:33.251019 ==
2528 11:32:33.254427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 11:32:33.261226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 11:32:33.270371 [CA 0] Center 40 (10~71) winsize 62
2531 11:32:33.273816 [CA 1] Center 40 (10~70) winsize 61
2532 11:32:33.277196 [CA 2] Center 35 (5~66) winsize 62
2533 11:32:33.280636 [CA 3] Center 35 (5~66) winsize 62
2534 11:32:33.283880 [CA 4] Center 34 (4~65) winsize 62
2535 11:32:33.287200 [CA 5] Center 33 (3~63) winsize 61
2536 11:32:33.287275
2537 11:32:33.290438 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2538 11:32:33.290513
2539 11:32:33.293779 [CATrainingPosCal] consider 2 rank data
2540 11:32:33.297166 u2DelayCellTimex100 = 270/100 ps
2541 11:32:33.300990 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2542 11:32:33.307385 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2543 11:32:33.310735 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2544 11:32:33.314097 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 11:32:33.317510 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2546 11:32:33.320969 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 11:32:33.321044
2548 11:32:33.323975 CA PerBit enable=1, Macro0, CA PI delay=33
2549 11:32:33.324050
2550 11:32:33.327523 [CBTSetCACLKResult] CA Dly = 33
2551 11:32:33.327598 CS Dly: 8 (0~40)
2552 11:32:33.330622
2553 11:32:33.334230 ----->DramcWriteLeveling(PI) begin...
2554 11:32:33.334330 ==
2555 11:32:33.337225 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 11:32:33.340729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 11:32:33.340805 ==
2558 11:32:33.343901 Write leveling (Byte 0): 33 => 33
2559 11:32:33.347106 Write leveling (Byte 1): 29 => 29
2560 11:32:33.350711 DramcWriteLeveling(PI) end<-----
2561 11:32:33.350790
2562 11:32:33.350886 ==
2563 11:32:33.354010 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 11:32:33.357331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 11:32:33.357407 ==
2566 11:32:33.360736 [Gating] SW mode calibration
2567 11:32:33.367743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 11:32:33.374015 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 11:32:33.377015 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 11:32:33.380392 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2571 11:32:33.387035 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 11:32:33.390603 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 11:32:33.393778 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 11:32:33.397392 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 11:32:33.404056 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 11:32:33.407593 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
2577 11:32:33.410841 1 0 0 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 1)
2578 11:32:33.417305 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 11:32:33.420822 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 11:32:33.424184 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 11:32:33.430617 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 11:32:33.434064 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 11:32:33.437471 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 11:32:33.444486 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2585 11:32:33.447560 1 1 0 | B1->B0 | 2929 3939 | 1 0 | (0 0) (0 0)
2586 11:32:33.451252 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
2587 11:32:33.457241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 11:32:33.460682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 11:32:33.464132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 11:32:33.471034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 11:32:33.474478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 11:32:33.477280 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 11:32:33.481017 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2594 11:32:33.487377 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2595 11:32:33.490985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:32:33.493795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:32:33.500699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:32:33.504003 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:32:33.507285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:32:33.514421 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:32:33.517534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:32:33.520530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:32:33.527301 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:32:33.531028 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:32:33.534094 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 11:32:33.540587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:32:33.544280 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:32:33.547629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2609 11:32:33.554049 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2610 11:32:33.558041 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2611 11:32:33.560635 Total UI for P1: 0, mck2ui 16
2612 11:32:33.564247 best dqsien dly found for B0: ( 1, 3, 30)
2613 11:32:33.567636 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:32:33.570862 Total UI for P1: 0, mck2ui 16
2615 11:32:33.574369 best dqsien dly found for B1: ( 1, 4, 2)
2616 11:32:33.577356 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2617 11:32:33.580713 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2618 11:32:33.580788
2619 11:32:33.583993 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2620 11:32:33.591148 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2621 11:32:33.591224 [Gating] SW calibration Done
2622 11:32:33.591282 ==
2623 11:32:33.594270 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 11:32:33.600585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 11:32:33.600661 ==
2626 11:32:33.600720 RX Vref Scan: 0
2627 11:32:33.600774
2628 11:32:33.603833 RX Vref 0 -> 0, step: 1
2629 11:32:33.603908
2630 11:32:33.607364 RX Delay -40 -> 252, step: 8
2631 11:32:33.610863 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2632 11:32:33.614268 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2633 11:32:33.617734 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2634 11:32:33.620916 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2635 11:32:33.627277 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2636 11:32:33.630886 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2637 11:32:33.634055 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2638 11:32:33.637370 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2639 11:32:33.640875 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2640 11:32:33.644198 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2641 11:32:33.650859 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2642 11:32:33.653955 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2643 11:32:33.657618 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2644 11:32:33.660900 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2645 11:32:33.667116 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2646 11:32:33.670498 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2647 11:32:33.670594 ==
2648 11:32:33.673914 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:32:33.677580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:32:33.677672 ==
2651 11:32:33.677755 DQS Delay:
2652 11:32:33.680827 DQS0 = 0, DQS1 = 0
2653 11:32:33.680915 DQM Delay:
2654 11:32:33.684409 DQM0 = 112, DQM1 = 102
2655 11:32:33.684499 DQ Delay:
2656 11:32:33.687696 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2657 11:32:33.690611 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2658 11:32:33.693769 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2659 11:32:33.697082 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2660 11:32:33.697161
2661 11:32:33.697218
2662 11:32:33.700888 ==
2663 11:32:33.704225 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 11:32:33.707840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 11:32:33.707936 ==
2666 11:32:33.708019
2667 11:32:33.708098
2668 11:32:33.710468 TX Vref Scan disable
2669 11:32:33.710532 == TX Byte 0 ==
2670 11:32:33.713922 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2671 11:32:33.720460 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2672 11:32:33.720557 == TX Byte 1 ==
2673 11:32:33.723758 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2674 11:32:33.730623 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2675 11:32:33.730718 ==
2676 11:32:33.733895 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:32:33.736994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:32:33.737085 ==
2679 11:32:33.750027 TX Vref=22, minBit 0, minWin=26, winSum=418
2680 11:32:33.753252 TX Vref=24, minBit 1, minWin=25, winSum=420
2681 11:32:33.756471 TX Vref=26, minBit 4, minWin=26, winSum=430
2682 11:32:33.759687 TX Vref=28, minBit 8, minWin=26, winSum=434
2683 11:32:33.763140 TX Vref=30, minBit 2, minWin=26, winSum=428
2684 11:32:33.765973 TX Vref=32, minBit 8, minWin=26, winSum=429
2685 11:32:33.773041 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2686 11:32:33.773135
2687 11:32:33.776508 Final TX Range 1 Vref 28
2688 11:32:33.776602
2689 11:32:33.776684 ==
2690 11:32:33.779327 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:32:33.782794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:32:33.782887 ==
2693 11:32:33.785808
2694 11:32:33.785895
2695 11:32:33.785975 TX Vref Scan disable
2696 11:32:33.789172 == TX Byte 0 ==
2697 11:32:33.792561 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2698 11:32:33.799178 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2699 11:32:33.799247 == TX Byte 1 ==
2700 11:32:33.802894 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2701 11:32:33.809161 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2702 11:32:33.809241
2703 11:32:33.809300 [DATLAT]
2704 11:32:33.809353 Freq=1200, CH0 RK0
2705 11:32:33.809405
2706 11:32:33.813065 DATLAT Default: 0xd
2707 11:32:33.813127 0, 0xFFFF, sum = 0
2708 11:32:33.816346 1, 0xFFFF, sum = 0
2709 11:32:33.816409 2, 0xFFFF, sum = 0
2710 11:32:33.819557 3, 0xFFFF, sum = 0
2711 11:32:33.822531 4, 0xFFFF, sum = 0
2712 11:32:33.822624 5, 0xFFFF, sum = 0
2713 11:32:33.825787 6, 0xFFFF, sum = 0
2714 11:32:33.825879 7, 0xFFFF, sum = 0
2715 11:32:33.829183 8, 0xFFFF, sum = 0
2716 11:32:33.829273 9, 0xFFFF, sum = 0
2717 11:32:33.832303 10, 0xFFFF, sum = 0
2718 11:32:33.832392 11, 0xFFFF, sum = 0
2719 11:32:33.835660 12, 0x0, sum = 1
2720 11:32:33.835756 13, 0x0, sum = 2
2721 11:32:33.839184 14, 0x0, sum = 3
2722 11:32:33.839277 15, 0x0, sum = 4
2723 11:32:33.839360 best_step = 13
2724 11:32:33.842577
2725 11:32:33.842661 ==
2726 11:32:33.845959 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 11:32:33.848998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 11:32:33.849085 ==
2729 11:32:33.849165 RX Vref Scan: 1
2730 11:32:33.849253
2731 11:32:33.852734 Set Vref Range= 32 -> 127
2732 11:32:33.852820
2733 11:32:33.855771 RX Vref 32 -> 127, step: 1
2734 11:32:33.855859
2735 11:32:33.858904 RX Delay -37 -> 252, step: 4
2736 11:32:33.858966
2737 11:32:33.862332 Set Vref, RX VrefLevel [Byte0]: 32
2738 11:32:33.866194 [Byte1]: 32
2739 11:32:33.866312
2740 11:32:33.869299 Set Vref, RX VrefLevel [Byte0]: 33
2741 11:32:33.872212 [Byte1]: 33
2742 11:32:33.876275
2743 11:32:33.876362 Set Vref, RX VrefLevel [Byte0]: 34
2744 11:32:33.879379 [Byte1]: 34
2745 11:32:33.884261
2746 11:32:33.884334 Set Vref, RX VrefLevel [Byte0]: 35
2747 11:32:33.887216 [Byte1]: 35
2748 11:32:33.892013
2749 11:32:33.892097 Set Vref, RX VrefLevel [Byte0]: 36
2750 11:32:33.895214 [Byte1]: 36
2751 11:32:33.900076
2752 11:32:33.900152 Set Vref, RX VrefLevel [Byte0]: 37
2753 11:32:33.903409 [Byte1]: 37
2754 11:32:33.908092
2755 11:32:33.908181 Set Vref, RX VrefLevel [Byte0]: 38
2756 11:32:33.911573 [Byte1]: 38
2757 11:32:33.916094
2758 11:32:33.916157 Set Vref, RX VrefLevel [Byte0]: 39
2759 11:32:33.919488 [Byte1]: 39
2760 11:32:33.924031
2761 11:32:33.924114 Set Vref, RX VrefLevel [Byte0]: 40
2762 11:32:33.927667 [Byte1]: 40
2763 11:32:33.932041
2764 11:32:33.932103 Set Vref, RX VrefLevel [Byte0]: 41
2765 11:32:33.935378 [Byte1]: 41
2766 11:32:33.940159
2767 11:32:33.940246 Set Vref, RX VrefLevel [Byte0]: 42
2768 11:32:33.943549 [Byte1]: 42
2769 11:32:33.947736
2770 11:32:33.947821 Set Vref, RX VrefLevel [Byte0]: 43
2771 11:32:33.954305 [Byte1]: 43
2772 11:32:33.954369
2773 11:32:33.957566 Set Vref, RX VrefLevel [Byte0]: 44
2774 11:32:33.960970 [Byte1]: 44
2775 11:32:33.961059
2776 11:32:33.964272 Set Vref, RX VrefLevel [Byte0]: 45
2777 11:32:33.967582 [Byte1]: 45
2778 11:32:33.971761
2779 11:32:33.971822 Set Vref, RX VrefLevel [Byte0]: 46
2780 11:32:33.975187 [Byte1]: 46
2781 11:32:33.979825
2782 11:32:33.979913 Set Vref, RX VrefLevel [Byte0]: 47
2783 11:32:33.983444 [Byte1]: 47
2784 11:32:33.988064
2785 11:32:33.988152 Set Vref, RX VrefLevel [Byte0]: 48
2786 11:32:33.991218 [Byte1]: 48
2787 11:32:33.996275
2788 11:32:33.996368 Set Vref, RX VrefLevel [Byte0]: 49
2789 11:32:33.999536 [Byte1]: 49
2790 11:32:34.003846
2791 11:32:34.003908 Set Vref, RX VrefLevel [Byte0]: 50
2792 11:32:34.007121 [Byte1]: 50
2793 11:32:34.012141
2794 11:32:34.012203 Set Vref, RX VrefLevel [Byte0]: 51
2795 11:32:34.015148 [Byte1]: 51
2796 11:32:34.019839
2797 11:32:34.019925 Set Vref, RX VrefLevel [Byte0]: 52
2798 11:32:34.023328 [Byte1]: 52
2799 11:32:34.028200
2800 11:32:34.028259 Set Vref, RX VrefLevel [Byte0]: 53
2801 11:32:34.031381 [Byte1]: 53
2802 11:32:34.036454
2803 11:32:34.036542 Set Vref, RX VrefLevel [Byte0]: 54
2804 11:32:34.039593 [Byte1]: 54
2805 11:32:34.044216
2806 11:32:34.044304 Set Vref, RX VrefLevel [Byte0]: 55
2807 11:32:34.047125 [Byte1]: 55
2808 11:32:34.051777
2809 11:32:34.051865 Set Vref, RX VrefLevel [Byte0]: 56
2810 11:32:34.055503 [Byte1]: 56
2811 11:32:34.059872
2812 11:32:34.059967 Set Vref, RX VrefLevel [Byte0]: 57
2813 11:32:34.063279 [Byte1]: 57
2814 11:32:34.068305
2815 11:32:34.068399 Set Vref, RX VrefLevel [Byte0]: 58
2816 11:32:34.071212 [Byte1]: 58
2817 11:32:34.076155
2818 11:32:34.076242 Set Vref, RX VrefLevel [Byte0]: 59
2819 11:32:34.079455 [Byte1]: 59
2820 11:32:34.083991
2821 11:32:34.084081 Set Vref, RX VrefLevel [Byte0]: 60
2822 11:32:34.087241 [Byte1]: 60
2823 11:32:34.092121
2824 11:32:34.092212 Set Vref, RX VrefLevel [Byte0]: 61
2825 11:32:34.095193 [Byte1]: 61
2826 11:32:34.100384
2827 11:32:34.100453 Set Vref, RX VrefLevel [Byte0]: 62
2828 11:32:34.103456 [Byte1]: 62
2829 11:32:34.108772
2830 11:32:34.108863 Set Vref, RX VrefLevel [Byte0]: 63
2831 11:32:34.111097 [Byte1]: 63
2832 11:32:34.115842
2833 11:32:34.115902 Set Vref, RX VrefLevel [Byte0]: 64
2834 11:32:34.119387 [Byte1]: 64
2835 11:32:34.123859
2836 11:32:34.123953 Set Vref, RX VrefLevel [Byte0]: 65
2837 11:32:34.127149 [Byte1]: 65
2838 11:32:34.131939
2839 11:32:34.132024 Set Vref, RX VrefLevel [Byte0]: 66
2840 11:32:34.135275 [Byte1]: 66
2841 11:32:34.139966
2842 11:32:34.140028 Set Vref, RX VrefLevel [Byte0]: 67
2843 11:32:34.143256 [Byte1]: 67
2844 11:32:34.148148
2845 11:32:34.148238 Set Vref, RX VrefLevel [Byte0]: 68
2846 11:32:34.151143 [Byte1]: 68
2847 11:32:34.155892
2848 11:32:34.155956 Set Vref, RX VrefLevel [Byte0]: 69
2849 11:32:34.159682 [Byte1]: 69
2850 11:32:34.164081
2851 11:32:34.164170 Set Vref, RX VrefLevel [Byte0]: 70
2852 11:32:34.167335 [Byte1]: 70
2853 11:32:34.171886
2854 11:32:34.171956 Set Vref, RX VrefLevel [Byte0]: 71
2855 11:32:34.175697 [Byte1]: 71
2856 11:32:34.180043
2857 11:32:34.180128 Set Vref, RX VrefLevel [Byte0]: 72
2858 11:32:34.183630 [Byte1]: 72
2859 11:32:34.187763
2860 11:32:34.187860 Set Vref, RX VrefLevel [Byte0]: 73
2861 11:32:34.191448 [Byte1]: 73
2862 11:32:34.195766
2863 11:32:34.195862 Set Vref, RX VrefLevel [Byte0]: 74
2864 11:32:34.199666 [Byte1]: 74
2865 11:32:34.203993
2866 11:32:34.204080 Final RX Vref Byte 0 = 61 to rank0
2867 11:32:34.207618 Final RX Vref Byte 1 = 53 to rank0
2868 11:32:34.210713 Final RX Vref Byte 0 = 61 to rank1
2869 11:32:34.214219 Final RX Vref Byte 1 = 53 to rank1==
2870 11:32:34.217818 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 11:32:34.220782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 11:32:34.223914 ==
2873 11:32:34.224002 DQS Delay:
2874 11:32:34.224084 DQS0 = 0, DQS1 = 0
2875 11:32:34.227147 DQM Delay:
2876 11:32:34.227224 DQM0 = 112, DQM1 = 101
2877 11:32:34.230660 DQ Delay:
2878 11:32:34.234342 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2879 11:32:34.237721 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2880 11:32:34.240643 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2881 11:32:34.243905 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2882 11:32:34.243997
2883 11:32:34.244088
2884 11:32:34.250610 [DQSOSCAuto] RK0, (LSB)MR18= 0xffff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2885 11:32:34.254344 CH0 RK0: MR19=303, MR18=FFFF
2886 11:32:34.260861 CH0_RK0: MR19=0x303, MR18=0xFFFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2887 11:32:34.260951
2888 11:32:34.263998 ----->DramcWriteLeveling(PI) begin...
2889 11:32:34.264099 ==
2890 11:32:34.267268 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 11:32:34.270662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 11:32:34.270726 ==
2893 11:32:34.274248 Write leveling (Byte 0): 32 => 32
2894 11:32:34.277301 Write leveling (Byte 1): 30 => 30
2895 11:32:34.280672 DramcWriteLeveling(PI) end<-----
2896 11:32:34.280759
2897 11:32:34.280850 ==
2898 11:32:34.284215 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 11:32:34.287397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 11:32:34.290786 ==
2901 11:32:34.290870 [Gating] SW mode calibration
2902 11:32:34.301126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 11:32:34.304143 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 11:32:34.307363 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2905 11:32:34.313766 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:32:34.317343 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:32:34.320587 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:32:34.327547 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:32:34.330594 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:32:34.333737 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2911 11:32:34.340980 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2912 11:32:34.344348 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2913 11:32:34.347299 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:32:34.354110 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:32:34.357062 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:32:34.360624 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:32:34.367228 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:32:34.370211 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2919 11:32:34.373980 1 0 28 | B1->B0 | 2323 4343 | 0 1 | (0 0) (0 0)
2920 11:32:34.380441 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2921 11:32:34.384025 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:32:34.386736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:32:34.393472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:32:34.396818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:32:34.400472 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:32:34.407147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 11:32:34.410109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 11:32:34.413602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2929 11:32:34.417202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:32:34.423555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:32:34.426807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:32:34.430436 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:32:34.436909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:32:34.440076 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:32:34.443849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:32:34.450938 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:32:34.453909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:32:34.457431 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:32:34.463600 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:32:34.467130 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:32:34.470437 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:32:34.476853 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:32:34.480162 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 11:32:34.484020 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:32:34.487439 Total UI for P1: 0, mck2ui 16
2946 11:32:34.490345 best dqsien dly found for B0: ( 1, 3, 28)
2947 11:32:34.493666 Total UI for P1: 0, mck2ui 16
2948 11:32:34.496834 best dqsien dly found for B1: ( 1, 3, 30)
2949 11:32:34.500415 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2950 11:32:34.503779 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2951 11:32:34.503854
2952 11:32:34.506837 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 11:32:34.513638 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2954 11:32:34.513713 [Gating] SW calibration Done
2955 11:32:34.513771 ==
2956 11:32:34.517241 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:32:34.523502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:32:34.523581 ==
2959 11:32:34.523642 RX Vref Scan: 0
2960 11:32:34.523697
2961 11:32:34.526873 RX Vref 0 -> 0, step: 1
2962 11:32:34.526936
2963 11:32:34.530662 RX Delay -40 -> 252, step: 8
2964 11:32:34.533602 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2965 11:32:34.537437 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2966 11:32:34.540500 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2967 11:32:34.546731 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2968 11:32:34.550358 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2969 11:32:34.553621 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2970 11:32:34.556850 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2971 11:32:34.560256 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2972 11:32:34.563664 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2973 11:32:34.570333 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2974 11:32:34.573282 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2975 11:32:34.576719 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2976 11:32:34.580612 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2977 11:32:34.583543 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2978 11:32:34.590058 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2979 11:32:34.593583 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2980 11:32:34.593643 ==
2981 11:32:34.596717 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:32:34.599969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:32:34.600041 ==
2984 11:32:34.603610 DQS Delay:
2985 11:32:34.603670 DQS0 = 0, DQS1 = 0
2986 11:32:34.603722 DQM Delay:
2987 11:32:34.607114 DQM0 = 111, DQM1 = 101
2988 11:32:34.607180 DQ Delay:
2989 11:32:34.610115 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2990 11:32:34.613500 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2991 11:32:34.617257 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2992 11:32:34.620142 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2993 11:32:34.623385
2994 11:32:34.623449
2995 11:32:34.623504 ==
2996 11:32:34.626797 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:32:34.630502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:32:34.630575 ==
2999 11:32:34.630632
3000 11:32:34.630688
3001 11:32:34.633779 TX Vref Scan disable
3002 11:32:34.633843 == TX Byte 0 ==
3003 11:32:34.640158 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3004 11:32:34.643564 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3005 11:32:34.643629 == TX Byte 1 ==
3006 11:32:34.649986 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3007 11:32:34.653812 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3008 11:32:34.653883 ==
3009 11:32:34.657001 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:32:34.660173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:32:34.660239 ==
3012 11:32:34.672589 TX Vref=22, minBit 1, minWin=26, winSum=426
3013 11:32:34.676072 TX Vref=24, minBit 1, minWin=26, winSum=431
3014 11:32:34.679524 TX Vref=26, minBit 5, minWin=26, winSum=433
3015 11:32:34.682291 TX Vref=28, minBit 1, minWin=27, winSum=439
3016 11:32:34.685679 TX Vref=30, minBit 14, minWin=26, winSum=439
3017 11:32:34.692502 TX Vref=32, minBit 8, minWin=26, winSum=436
3018 11:32:34.696031 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 28
3019 11:32:34.696099
3020 11:32:34.699082 Final TX Range 1 Vref 28
3021 11:32:34.699144
3022 11:32:34.699197 ==
3023 11:32:34.702189 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:32:34.705855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:32:34.708960 ==
3026 11:32:34.709035
3027 11:32:34.709094
3028 11:32:34.709149 TX Vref Scan disable
3029 11:32:34.712191 == TX Byte 0 ==
3030 11:32:34.715444 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3031 11:32:34.722526 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3032 11:32:34.722592 == TX Byte 1 ==
3033 11:32:34.725504 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3034 11:32:34.732405 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3035 11:32:34.732474
3036 11:32:34.732530 [DATLAT]
3037 11:32:34.732591 Freq=1200, CH0 RK1
3038 11:32:34.732645
3039 11:32:34.735660 DATLAT Default: 0xd
3040 11:32:34.735723 0, 0xFFFF, sum = 0
3041 11:32:34.738890 1, 0xFFFF, sum = 0
3042 11:32:34.742620 2, 0xFFFF, sum = 0
3043 11:32:34.742689 3, 0xFFFF, sum = 0
3044 11:32:34.745525 4, 0xFFFF, sum = 0
3045 11:32:34.745588 5, 0xFFFF, sum = 0
3046 11:32:34.748724 6, 0xFFFF, sum = 0
3047 11:32:34.748789 7, 0xFFFF, sum = 0
3048 11:32:34.752155 8, 0xFFFF, sum = 0
3049 11:32:34.752219 9, 0xFFFF, sum = 0
3050 11:32:34.755545 10, 0xFFFF, sum = 0
3051 11:32:34.755611 11, 0xFFFF, sum = 0
3052 11:32:34.759066 12, 0x0, sum = 1
3053 11:32:34.759132 13, 0x0, sum = 2
3054 11:32:34.762436 14, 0x0, sum = 3
3055 11:32:34.762500 15, 0x0, sum = 4
3056 11:32:34.765568 best_step = 13
3057 11:32:34.765631
3058 11:32:34.765683 ==
3059 11:32:34.768872 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 11:32:34.771969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 11:32:34.772029 ==
3062 11:32:34.772087 RX Vref Scan: 0
3063 11:32:34.775395
3064 11:32:34.775460 RX Vref 0 -> 0, step: 1
3065 11:32:34.775515
3066 11:32:34.778448 RX Delay -37 -> 252, step: 4
3067 11:32:34.785613 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3068 11:32:34.788384 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3069 11:32:34.791806 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3070 11:32:34.795308 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3071 11:32:34.799006 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3072 11:32:34.805477 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3073 11:32:34.808335 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3074 11:32:34.811939 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3075 11:32:34.814770 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3076 11:32:34.818007 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3077 11:32:34.825002 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3078 11:32:34.828074 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3079 11:32:34.831752 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3080 11:32:34.834722 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3081 11:32:34.837936 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3082 11:32:34.844927 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3083 11:32:34.845005 ==
3084 11:32:34.848161 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:32:34.851644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:32:34.851719 ==
3087 11:32:34.851777 DQS Delay:
3088 11:32:34.854873 DQS0 = 0, DQS1 = 0
3089 11:32:34.854951 DQM Delay:
3090 11:32:34.858053 DQM0 = 110, DQM1 = 101
3091 11:32:34.858208 DQ Delay:
3092 11:32:34.861158 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3093 11:32:34.864464 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3094 11:32:34.867826 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3095 11:32:34.871475 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3096 11:32:34.871550
3097 11:32:34.871606
3098 11:32:34.881427 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3099 11:32:34.884443 CH0 RK1: MR19=403, MR18=13FA
3100 11:32:34.887733 CH0_RK1: MR19=0x403, MR18=0x13FA, DQSOSC=402, MR23=63, INC=40, DEC=27
3101 11:32:34.891215 [RxdqsGatingPostProcess] freq 1200
3102 11:32:34.897636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 11:32:34.901121 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 11:32:34.904783 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 11:32:34.908077 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 11:32:34.911291 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 11:32:34.914311 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 11:32:34.918231 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 11:32:34.921403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 11:32:34.924461 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 11:32:34.927785 Pre-setting of DQS Precalculation
3112 11:32:34.931018 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 11:32:34.931125 ==
3114 11:32:34.934784 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:32:34.938059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:32:34.938183 ==
3117 11:32:34.944510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 11:32:34.950843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3119 11:32:34.959071 [CA 0] Center 37 (7~67) winsize 61
3120 11:32:34.962330 [CA 1] Center 37 (7~68) winsize 62
3121 11:32:34.965730 [CA 2] Center 34 (4~64) winsize 61
3122 11:32:34.968733 [CA 3] Center 34 (4~64) winsize 61
3123 11:32:34.971841 [CA 4] Center 34 (4~64) winsize 61
3124 11:32:34.975220 [CA 5] Center 33 (3~63) winsize 61
3125 11:32:34.975293
3126 11:32:34.978416 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3127 11:32:34.978490
3128 11:32:34.981853 [CATrainingPosCal] consider 1 rank data
3129 11:32:34.985349 u2DelayCellTimex100 = 270/100 ps
3130 11:32:34.988431 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3131 11:32:34.995456 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 11:32:34.998447 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 11:32:35.002055 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:32:35.005401 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 11:32:35.008332 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 11:32:35.008406
3137 11:32:35.011769 CA PerBit enable=1, Macro0, CA PI delay=33
3138 11:32:35.011843
3139 11:32:35.015356 [CBTSetCACLKResult] CA Dly = 33
3140 11:32:35.015430 CS Dly: 6 (0~37)
3141 11:32:35.018076 ==
3142 11:32:35.021700 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 11:32:35.025200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 11:32:35.025274 ==
3145 11:32:35.028304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 11:32:35.035197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 11:32:35.044271 [CA 0] Center 37 (7~67) winsize 61
3148 11:32:35.047890 [CA 1] Center 37 (7~68) winsize 62
3149 11:32:35.051599 [CA 2] Center 34 (4~65) winsize 62
3150 11:32:35.054630 [CA 3] Center 33 (3~64) winsize 62
3151 11:32:35.057660 [CA 4] Center 34 (4~65) winsize 62
3152 11:32:35.060825 [CA 5] Center 32 (2~63) winsize 62
3153 11:32:35.060898
3154 11:32:35.064148 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 11:32:35.064222
3156 11:32:35.067452 [CATrainingPosCal] consider 2 rank data
3157 11:32:35.071117 u2DelayCellTimex100 = 270/100 ps
3158 11:32:35.074264 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3159 11:32:35.081067 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 11:32:35.084558 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 11:32:35.087430 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 11:32:35.090855 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 11:32:35.094032 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 11:32:35.094135
3165 11:32:35.097678 CA PerBit enable=1, Macro0, CA PI delay=33
3166 11:32:35.097753
3167 11:32:35.100541 [CBTSetCACLKResult] CA Dly = 33
3168 11:32:35.100615 CS Dly: 7 (0~39)
3169 11:32:35.103592
3170 11:32:35.107633 ----->DramcWriteLeveling(PI) begin...
3171 11:32:35.107732 ==
3172 11:32:35.110338 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 11:32:35.113714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 11:32:35.113788 ==
3175 11:32:35.117149 Write leveling (Byte 0): 25 => 25
3176 11:32:35.121019 Write leveling (Byte 1): 28 => 28
3177 11:32:35.124003 DramcWriteLeveling(PI) end<-----
3178 11:32:35.124077
3179 11:32:35.124134 ==
3180 11:32:35.127438 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 11:32:35.130136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:32:35.130224 ==
3183 11:32:35.133806 [Gating] SW mode calibration
3184 11:32:35.140372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 11:32:35.147096 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 11:32:35.150172 0 15 0 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (0 0)
3187 11:32:35.153353 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:32:35.160054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:32:35.163271 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:32:35.166980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:32:35.173769 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:32:35.176521 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 11:32:35.180148 0 15 28 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 0)
3194 11:32:35.186439 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:32:35.189919 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:32:35.193110 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:32:35.200201 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:32:35.203401 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:32:35.206487 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:32:35.213488 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3201 11:32:35.216601 1 0 28 | B1->B0 | 3c3c 3837 | 1 1 | (0 0) (0 0)
3202 11:32:35.219520 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:32:35.226596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:32:35.229707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:32:35.233318 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:32:35.239676 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:32:35.242945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:32:35.246764 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:32:35.249798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 11:32:35.256239 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3211 11:32:35.259742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:32:35.262909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:32:35.269544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:32:35.273042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:32:35.275944 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:32:35.282999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:32:35.285859 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:32:35.289831 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:32:35.295971 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:32:35.299450 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:32:35.302889 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:32:35.309505 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:32:35.312751 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:32:35.315867 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:32:35.322732 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 11:32:35.326011 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 11:32:35.329241 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:32:35.332500 Total UI for P1: 0, mck2ui 16
3229 11:32:35.335719 best dqsien dly found for B0: ( 1, 3, 30)
3230 11:32:35.339104 Total UI for P1: 0, mck2ui 16
3231 11:32:35.342453 best dqsien dly found for B1: ( 1, 3, 30)
3232 11:32:35.345530 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3233 11:32:35.348790 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3234 11:32:35.348864
3235 11:32:35.355336 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3236 11:32:35.358955 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3237 11:32:35.362866 [Gating] SW calibration Done
3238 11:32:35.362939 ==
3239 11:32:35.365540 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 11:32:35.368868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 11:32:35.368943 ==
3242 11:32:35.369000 RX Vref Scan: 0
3243 11:32:35.369053
3244 11:32:35.372313 RX Vref 0 -> 0, step: 1
3245 11:32:35.372387
3246 11:32:35.375517 RX Delay -40 -> 252, step: 8
3247 11:32:35.378793 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3248 11:32:35.382044 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3249 11:32:35.388671 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3250 11:32:35.392358 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3251 11:32:35.395673 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3252 11:32:35.398646 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3253 11:32:35.402008 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3254 11:32:35.408836 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3255 11:32:35.411782 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3256 11:32:35.415485 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3257 11:32:35.418899 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3258 11:32:35.421973 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3259 11:32:35.428499 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3260 11:32:35.431804 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3261 11:32:35.435566 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3262 11:32:35.438708 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3263 11:32:35.438782 ==
3264 11:32:35.442054 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 11:32:35.445099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 11:32:35.448654 ==
3267 11:32:35.448727 DQS Delay:
3268 11:32:35.448785 DQS0 = 0, DQS1 = 0
3269 11:32:35.451915 DQM Delay:
3270 11:32:35.451988 DQM0 = 113, DQM1 = 105
3271 11:32:35.455379 DQ Delay:
3272 11:32:35.458613 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3273 11:32:35.461493 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3274 11:32:35.464879 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3275 11:32:35.468130 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3276 11:32:35.468204
3277 11:32:35.468262
3278 11:32:35.468314 ==
3279 11:32:35.471718 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:32:35.475206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:32:35.475280 ==
3282 11:32:35.475337
3283 11:32:35.478407
3284 11:32:35.478480 TX Vref Scan disable
3285 11:32:35.481458 == TX Byte 0 ==
3286 11:32:35.484927 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3287 11:32:35.488642 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3288 11:32:35.491446 == TX Byte 1 ==
3289 11:32:35.494994 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3290 11:32:35.498184 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3291 11:32:35.498259 ==
3292 11:32:35.501714 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 11:32:35.507774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 11:32:35.507849 ==
3295 11:32:35.518715 TX Vref=22, minBit 8, minWin=24, winSum=407
3296 11:32:35.522026 TX Vref=24, minBit 3, minWin=25, winSum=410
3297 11:32:35.525406 TX Vref=26, minBit 10, minWin=24, winSum=415
3298 11:32:35.528453 TX Vref=28, minBit 10, minWin=25, winSum=426
3299 11:32:35.531916 TX Vref=30, minBit 9, minWin=25, winSum=425
3300 11:32:35.538564 TX Vref=32, minBit 9, minWin=25, winSum=425
3301 11:32:35.541973 [TxChooseVref] Worse bit 10, Min win 25, Win sum 426, Final Vref 28
3302 11:32:35.542048
3303 11:32:35.545796 Final TX Range 1 Vref 28
3304 11:32:35.545870
3305 11:32:35.545926 ==
3306 11:32:35.548620 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 11:32:35.552018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 11:32:35.555322 ==
3309 11:32:35.555396
3310 11:32:35.555453
3311 11:32:35.555506 TX Vref Scan disable
3312 11:32:35.558953 == TX Byte 0 ==
3313 11:32:35.561699 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3314 11:32:35.565296 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3315 11:32:35.569197 == TX Byte 1 ==
3316 11:32:35.571559 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3317 11:32:35.578277 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3318 11:32:35.578351
3319 11:32:35.578408 [DATLAT]
3320 11:32:35.578461 Freq=1200, CH1 RK0
3321 11:32:35.578511
3322 11:32:35.582243 DATLAT Default: 0xd
3323 11:32:35.582324 0, 0xFFFF, sum = 0
3324 11:32:35.585099 1, 0xFFFF, sum = 0
3325 11:32:35.585174 2, 0xFFFF, sum = 0
3326 11:32:35.588707 3, 0xFFFF, sum = 0
3327 11:32:35.591814 4, 0xFFFF, sum = 0
3328 11:32:35.591889 5, 0xFFFF, sum = 0
3329 11:32:35.595345 6, 0xFFFF, sum = 0
3330 11:32:35.595419 7, 0xFFFF, sum = 0
3331 11:32:35.598398 8, 0xFFFF, sum = 0
3332 11:32:35.598473 9, 0xFFFF, sum = 0
3333 11:32:35.601830 10, 0xFFFF, sum = 0
3334 11:32:35.601904 11, 0xFFFF, sum = 0
3335 11:32:35.604674 12, 0x0, sum = 1
3336 11:32:35.604749 13, 0x0, sum = 2
3337 11:32:35.608440 14, 0x0, sum = 3
3338 11:32:35.608515 15, 0x0, sum = 4
3339 11:32:35.611519 best_step = 13
3340 11:32:35.611593
3341 11:32:35.611648 ==
3342 11:32:35.614548 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 11:32:35.618258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 11:32:35.618333 ==
3345 11:32:35.618390 RX Vref Scan: 1
3346 11:32:35.621598
3347 11:32:35.621670 Set Vref Range= 32 -> 127
3348 11:32:35.621727
3349 11:32:35.624819 RX Vref 32 -> 127, step: 1
3350 11:32:35.624891
3351 11:32:35.628002 RX Delay -21 -> 252, step: 4
3352 11:32:35.628075
3353 11:32:35.631795 Set Vref, RX VrefLevel [Byte0]: 32
3354 11:32:35.634724 [Byte1]: 32
3355 11:32:35.634797
3356 11:32:35.638035 Set Vref, RX VrefLevel [Byte0]: 33
3357 11:32:35.641267 [Byte1]: 33
3358 11:32:35.645040
3359 11:32:35.645112 Set Vref, RX VrefLevel [Byte0]: 34
3360 11:32:35.648220 [Byte1]: 34
3361 11:32:35.652779
3362 11:32:35.652852 Set Vref, RX VrefLevel [Byte0]: 35
3363 11:32:35.656117 [Byte1]: 35
3364 11:32:35.661038
3365 11:32:35.661111 Set Vref, RX VrefLevel [Byte0]: 36
3366 11:32:35.664213 [Byte1]: 36
3367 11:32:35.669039
3368 11:32:35.669111 Set Vref, RX VrefLevel [Byte0]: 37
3369 11:32:35.672034 [Byte1]: 37
3370 11:32:35.676872
3371 11:32:35.676968 Set Vref, RX VrefLevel [Byte0]: 38
3372 11:32:35.680115 [Byte1]: 38
3373 11:32:35.684360
3374 11:32:35.684432 Set Vref, RX VrefLevel [Byte0]: 39
3375 11:32:35.688544 [Byte1]: 39
3376 11:32:35.692476
3377 11:32:35.692549 Set Vref, RX VrefLevel [Byte0]: 40
3378 11:32:35.695574 [Byte1]: 40
3379 11:32:35.700209
3380 11:32:35.700282 Set Vref, RX VrefLevel [Byte0]: 41
3381 11:32:35.703783 [Byte1]: 41
3382 11:32:35.708417
3383 11:32:35.708514 Set Vref, RX VrefLevel [Byte0]: 42
3384 11:32:35.712015 [Byte1]: 42
3385 11:32:35.716511
3386 11:32:35.716595 Set Vref, RX VrefLevel [Byte0]: 43
3387 11:32:35.719673 [Byte1]: 43
3388 11:32:35.724274
3389 11:32:35.724340 Set Vref, RX VrefLevel [Byte0]: 44
3390 11:32:35.727625 [Byte1]: 44
3391 11:32:35.732511
3392 11:32:35.732584 Set Vref, RX VrefLevel [Byte0]: 45
3393 11:32:35.735574 [Byte1]: 45
3394 11:32:35.739969
3395 11:32:35.740042 Set Vref, RX VrefLevel [Byte0]: 46
3396 11:32:35.743580 [Byte1]: 46
3397 11:32:35.748133
3398 11:32:35.748206 Set Vref, RX VrefLevel [Byte0]: 47
3399 11:32:35.751281 [Byte1]: 47
3400 11:32:35.756039
3401 11:32:35.756112 Set Vref, RX VrefLevel [Byte0]: 48
3402 11:32:35.759070 [Byte1]: 48
3403 11:32:35.763748
3404 11:32:35.763821 Set Vref, RX VrefLevel [Byte0]: 49
3405 11:32:35.767706 [Byte1]: 49
3406 11:32:35.771681
3407 11:32:35.771755 Set Vref, RX VrefLevel [Byte0]: 50
3408 11:32:35.775339 [Byte1]: 50
3409 11:32:35.780074
3410 11:32:35.780147 Set Vref, RX VrefLevel [Byte0]: 51
3411 11:32:35.782940 [Byte1]: 51
3412 11:32:35.787852
3413 11:32:35.787925 Set Vref, RX VrefLevel [Byte0]: 52
3414 11:32:35.790723 [Byte1]: 52
3415 11:32:35.795320
3416 11:32:35.795393 Set Vref, RX VrefLevel [Byte0]: 53
3417 11:32:35.798591 [Byte1]: 53
3418 11:32:35.803220
3419 11:32:35.803294 Set Vref, RX VrefLevel [Byte0]: 54
3420 11:32:35.807010 [Byte1]: 54
3421 11:32:35.811467
3422 11:32:35.811540 Set Vref, RX VrefLevel [Byte0]: 55
3423 11:32:35.814449 [Byte1]: 55
3424 11:32:35.819588
3425 11:32:35.819662 Set Vref, RX VrefLevel [Byte0]: 56
3426 11:32:35.822443 [Byte1]: 56
3427 11:32:35.827487
3428 11:32:35.827560 Set Vref, RX VrefLevel [Byte0]: 57
3429 11:32:35.830400 [Byte1]: 57
3430 11:32:35.835313
3431 11:32:35.835386 Set Vref, RX VrefLevel [Byte0]: 58
3432 11:32:35.838339 [Byte1]: 58
3433 11:32:35.842911
3434 11:32:35.842981 Set Vref, RX VrefLevel [Byte0]: 59
3435 11:32:35.846348 [Byte1]: 59
3436 11:32:35.850863
3437 11:32:35.850925 Set Vref, RX VrefLevel [Byte0]: 60
3438 11:32:35.854516 [Byte1]: 60
3439 11:32:35.858922
3440 11:32:35.858989 Set Vref, RX VrefLevel [Byte0]: 61
3441 11:32:35.862276 [Byte1]: 61
3442 11:32:35.866850
3443 11:32:35.866920 Set Vref, RX VrefLevel [Byte0]: 62
3444 11:32:35.870028 [Byte1]: 62
3445 11:32:35.874750
3446 11:32:35.874817 Set Vref, RX VrefLevel [Byte0]: 63
3447 11:32:35.877781 [Byte1]: 63
3448 11:32:35.882698
3449 11:32:35.882768 Set Vref, RX VrefLevel [Byte0]: 64
3450 11:32:35.886037 [Byte1]: 64
3451 11:32:35.890598
3452 11:32:35.890664 Set Vref, RX VrefLevel [Byte0]: 65
3453 11:32:35.893802 [Byte1]: 65
3454 11:32:35.898736
3455 11:32:35.898806 Set Vref, RX VrefLevel [Byte0]: 66
3456 11:32:35.901616 [Byte1]: 66
3457 11:32:35.906445
3458 11:32:35.906518 Set Vref, RX VrefLevel [Byte0]: 67
3459 11:32:35.909995 [Byte1]: 67
3460 11:32:35.914649
3461 11:32:35.914721 Set Vref, RX VrefLevel [Byte0]: 68
3462 11:32:35.917925 [Byte1]: 68
3463 11:32:35.922276
3464 11:32:35.922349 Final RX Vref Byte 0 = 56 to rank0
3465 11:32:35.925537 Final RX Vref Byte 1 = 53 to rank0
3466 11:32:35.928811 Final RX Vref Byte 0 = 56 to rank1
3467 11:32:35.932151 Final RX Vref Byte 1 = 53 to rank1==
3468 11:32:35.935483 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 11:32:35.942235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 11:32:35.942314 ==
3471 11:32:35.942376 DQS Delay:
3472 11:32:35.942430 DQS0 = 0, DQS1 = 0
3473 11:32:35.945593 DQM Delay:
3474 11:32:35.945659 DQM0 = 114, DQM1 = 106
3475 11:32:35.948776 DQ Delay:
3476 11:32:35.952329 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3477 11:32:35.955271 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3478 11:32:35.958923 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3479 11:32:35.962392 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
3480 11:32:35.962458
3481 11:32:35.962518
3482 11:32:35.968748 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 415 ps
3483 11:32:35.972351 CH1 RK0: MR19=303, MR18=F2F8
3484 11:32:35.978590 CH1_RK0: MR19=0x303, MR18=0xF2F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3485 11:32:35.978661
3486 11:32:35.981670 ----->DramcWriteLeveling(PI) begin...
3487 11:32:35.981738 ==
3488 11:32:35.985142 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 11:32:35.991929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 11:32:35.992003 ==
3491 11:32:35.995551 Write leveling (Byte 0): 25 => 25
3492 11:32:35.995621 Write leveling (Byte 1): 29 => 29
3493 11:32:35.998871 DramcWriteLeveling(PI) end<-----
3494 11:32:35.998945
3495 11:32:35.999026 ==
3496 11:32:36.001572 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 11:32:36.008578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 11:32:36.008684 ==
3499 11:32:36.011934 [Gating] SW mode calibration
3500 11:32:36.018513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 11:32:36.021951 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 11:32:36.028546 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 11:32:36.031964 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 11:32:36.035154 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 11:32:36.042089 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 11:32:36.044764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 11:32:36.048371 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 11:32:36.055186 0 15 24 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
3509 11:32:36.058340 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3510 11:32:36.061601 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 11:32:36.068231 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 11:32:36.071485 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 11:32:36.075063 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 11:32:36.078388 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 11:32:36.084598 1 0 20 | B1->B0 | 2424 2727 | 1 0 | (0 0) (0 0)
3516 11:32:36.088128 1 0 24 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
3517 11:32:36.091318 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3518 11:32:36.097841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 11:32:36.101180 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 11:32:36.104456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 11:32:36.111317 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 11:32:36.114301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 11:32:36.117926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:32:36.124636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3525 11:32:36.128107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:32:36.131221 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:32:36.138373 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:32:36.141078 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:32:36.144280 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:32:36.151564 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:32:36.154636 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:32:36.157968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:32:36.164124 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:32:36.167413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:32:36.170768 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:32:36.178008 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:32:36.181298 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:32:36.184717 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:32:36.190846 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:32:36.194018 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 11:32:36.197353 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:32:36.200613 Total UI for P1: 0, mck2ui 16
3543 11:32:36.203997 best dqsien dly found for B0: ( 1, 3, 24)
3544 11:32:36.207727 Total UI for P1: 0, mck2ui 16
3545 11:32:36.210730 best dqsien dly found for B1: ( 1, 3, 24)
3546 11:32:36.214452 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3547 11:32:36.217612 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3548 11:32:36.217686
3549 11:32:36.224184 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3550 11:32:36.227215 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3551 11:32:36.227289 [Gating] SW calibration Done
3552 11:32:36.230960 ==
3553 11:32:36.231048 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 11:32:36.237475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 11:32:36.237550 ==
3556 11:32:36.237608 RX Vref Scan: 0
3557 11:32:36.237661
3558 11:32:36.240411 RX Vref 0 -> 0, step: 1
3559 11:32:36.240484
3560 11:32:36.244040 RX Delay -40 -> 252, step: 8
3561 11:32:36.247368 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3562 11:32:36.250289 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3563 11:32:36.254289 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3564 11:32:36.260892 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3565 11:32:36.263601 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3566 11:32:36.267223 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3567 11:32:36.270482 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3568 11:32:36.273859 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3569 11:32:36.280205 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3570 11:32:36.283772 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3571 11:32:36.287206 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3572 11:32:36.290477 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3573 11:32:36.294007 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3574 11:32:36.300434 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3575 11:32:36.303514 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3576 11:32:36.307086 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3577 11:32:36.307160 ==
3578 11:32:36.310458 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 11:32:36.313470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 11:32:36.313548 ==
3581 11:32:36.317342 DQS Delay:
3582 11:32:36.317416 DQS0 = 0, DQS1 = 0
3583 11:32:36.320198 DQM Delay:
3584 11:32:36.320273 DQM0 = 110, DQM1 = 108
3585 11:32:36.323667 DQ Delay:
3586 11:32:36.326579 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3587 11:32:36.330042 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3588 11:32:36.333676 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3589 11:32:36.336944 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3590 11:32:36.337018
3591 11:32:36.337075
3592 11:32:36.337130 ==
3593 11:32:36.340260 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 11:32:36.343474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 11:32:36.343548 ==
3596 11:32:36.343605
3597 11:32:36.343658
3598 11:32:36.346816 TX Vref Scan disable
3599 11:32:36.349788 == TX Byte 0 ==
3600 11:32:36.353205 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 11:32:36.356810 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 11:32:36.360108 == TX Byte 1 ==
3603 11:32:36.363401 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3604 11:32:36.366863 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3605 11:32:36.367013 ==
3606 11:32:36.370258 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 11:32:36.373371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 11:32:36.376876 ==
3609 11:32:36.387220 TX Vref=22, minBit 0, minWin=26, winSum=423
3610 11:32:36.390020 TX Vref=24, minBit 0, minWin=26, winSum=427
3611 11:32:36.393751 TX Vref=26, minBit 8, minWin=26, winSum=434
3612 11:32:36.397355 TX Vref=28, minBit 8, minWin=26, winSum=434
3613 11:32:36.400296 TX Vref=30, minBit 0, minWin=27, winSum=436
3614 11:32:36.404208 TX Vref=32, minBit 1, minWin=26, winSum=432
3615 11:32:36.410247 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30
3616 11:32:36.410316
3617 11:32:36.413720 Final TX Range 1 Vref 30
3618 11:32:36.413784
3619 11:32:36.413837 ==
3620 11:32:36.417408 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 11:32:36.420092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 11:32:36.420169 ==
3623 11:32:36.420227
3624 11:32:36.423663
3625 11:32:36.423737 TX Vref Scan disable
3626 11:32:36.426934 == TX Byte 0 ==
3627 11:32:36.430263 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 11:32:36.436515 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 11:32:36.436589 == TX Byte 1 ==
3630 11:32:36.439976 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3631 11:32:36.446391 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3632 11:32:36.446465
3633 11:32:36.446522 [DATLAT]
3634 11:32:36.446575 Freq=1200, CH1 RK1
3635 11:32:36.446625
3636 11:32:36.449719 DATLAT Default: 0xd
3637 11:32:36.449793 0, 0xFFFF, sum = 0
3638 11:32:36.453100 1, 0xFFFF, sum = 0
3639 11:32:36.456564 2, 0xFFFF, sum = 0
3640 11:32:36.456664 3, 0xFFFF, sum = 0
3641 11:32:36.459607 4, 0xFFFF, sum = 0
3642 11:32:36.459684 5, 0xFFFF, sum = 0
3643 11:32:36.463137 6, 0xFFFF, sum = 0
3644 11:32:36.463212 7, 0xFFFF, sum = 0
3645 11:32:36.466052 8, 0xFFFF, sum = 0
3646 11:32:36.466150 9, 0xFFFF, sum = 0
3647 11:32:36.469506 10, 0xFFFF, sum = 0
3648 11:32:36.469596 11, 0xFFFF, sum = 0
3649 11:32:36.472833 12, 0x0, sum = 1
3650 11:32:36.472908 13, 0x0, sum = 2
3651 11:32:36.476760 14, 0x0, sum = 3
3652 11:32:36.476835 15, 0x0, sum = 4
3653 11:32:36.479401 best_step = 13
3654 11:32:36.479468
3655 11:32:36.479523 ==
3656 11:32:36.482797 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 11:32:36.486279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 11:32:36.486353 ==
3659 11:32:36.486411 RX Vref Scan: 0
3660 11:32:36.489232
3661 11:32:36.489306 RX Vref 0 -> 0, step: 1
3662 11:32:36.489362
3663 11:32:36.493095 RX Delay -21 -> 252, step: 4
3664 11:32:36.499385 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3665 11:32:36.502906 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3666 11:32:36.506049 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3667 11:32:36.509295 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3668 11:32:36.512932 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3669 11:32:36.519382 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3670 11:32:36.522614 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3671 11:32:36.526244 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3672 11:32:36.528885 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3673 11:32:36.532284 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3674 11:32:36.539293 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3675 11:32:36.542616 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3676 11:32:36.545508 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3677 11:32:36.549111 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3678 11:32:36.552313 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3679 11:32:36.558763 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3680 11:32:36.558838 ==
3681 11:32:36.562233 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 11:32:36.565397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 11:32:36.565471 ==
3684 11:32:36.565528 DQS Delay:
3685 11:32:36.568711 DQS0 = 0, DQS1 = 0
3686 11:32:36.568785 DQM Delay:
3687 11:32:36.572245 DQM0 = 111, DQM1 = 110
3688 11:32:36.572319 DQ Delay:
3689 11:32:36.575508 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3690 11:32:36.578610 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3691 11:32:36.582129 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3692 11:32:36.585826 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3693 11:32:36.585924
3694 11:32:36.588632
3695 11:32:36.595444 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3696 11:32:36.598889 CH1 RK1: MR19=304, MR18=FC0C
3697 11:32:36.605162 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3698 11:32:36.608474 [RxdqsGatingPostProcess] freq 1200
3699 11:32:36.612078 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 11:32:36.615229 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 11:32:36.618749 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 11:32:36.621990 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 11:32:36.625108 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 11:32:36.628344 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 11:32:36.631457 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 11:32:36.635182 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 11:32:36.638206 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 11:32:36.641568 Pre-setting of DQS Precalculation
3709 11:32:36.645240 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 11:32:36.651341 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 11:32:36.661535 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 11:32:36.661610
3713 11:32:36.661667
3714 11:32:36.665192 [Calibration Summary] 2400 Mbps
3715 11:32:36.665266 CH 0, Rank 0
3716 11:32:36.668483 SW Impedance : PASS
3717 11:32:36.668558 DUTY Scan : NO K
3718 11:32:36.671589 ZQ Calibration : PASS
3719 11:32:36.674654 Jitter Meter : NO K
3720 11:32:36.674728 CBT Training : PASS
3721 11:32:36.678116 Write leveling : PASS
3722 11:32:36.681724 RX DQS gating : PASS
3723 11:32:36.681798 RX DQ/DQS(RDDQC) : PASS
3724 11:32:36.684515 TX DQ/DQS : PASS
3725 11:32:36.684589 RX DATLAT : PASS
3726 11:32:36.687623 RX DQ/DQS(Engine): PASS
3727 11:32:36.691085 TX OE : NO K
3728 11:32:36.691160 All Pass.
3729 11:32:36.691218
3730 11:32:36.694351 CH 0, Rank 1
3731 11:32:36.694425 SW Impedance : PASS
3732 11:32:36.698184 DUTY Scan : NO K
3733 11:32:36.698258 ZQ Calibration : PASS
3734 11:32:36.701190 Jitter Meter : NO K
3735 11:32:36.704594 CBT Training : PASS
3736 11:32:36.704668 Write leveling : PASS
3737 11:32:36.707506 RX DQS gating : PASS
3738 11:32:36.710692 RX DQ/DQS(RDDQC) : PASS
3739 11:32:36.710766 TX DQ/DQS : PASS
3740 11:32:36.714236 RX DATLAT : PASS
3741 11:32:36.717922 RX DQ/DQS(Engine): PASS
3742 11:32:36.717995 TX OE : NO K
3743 11:32:36.720772 All Pass.
3744 11:32:36.720846
3745 11:32:36.720903 CH 1, Rank 0
3746 11:32:36.724252 SW Impedance : PASS
3747 11:32:36.724326 DUTY Scan : NO K
3748 11:32:36.727252 ZQ Calibration : PASS
3749 11:32:36.730714 Jitter Meter : NO K
3750 11:32:36.730788 CBT Training : PASS
3751 11:32:36.734092 Write leveling : PASS
3752 11:32:36.737625 RX DQS gating : PASS
3753 11:32:36.737698 RX DQ/DQS(RDDQC) : PASS
3754 11:32:36.740665 TX DQ/DQS : PASS
3755 11:32:36.744071 RX DATLAT : PASS
3756 11:32:36.744145 RX DQ/DQS(Engine): PASS
3757 11:32:36.747496 TX OE : NO K
3758 11:32:36.747569 All Pass.
3759 11:32:36.747626
3760 11:32:36.750718 CH 1, Rank 1
3761 11:32:36.750791 SW Impedance : PASS
3762 11:32:36.753821 DUTY Scan : NO K
3763 11:32:36.753897 ZQ Calibration : PASS
3764 11:32:36.757265 Jitter Meter : NO K
3765 11:32:36.760655 CBT Training : PASS
3766 11:32:36.760729 Write leveling : PASS
3767 11:32:36.763936 RX DQS gating : PASS
3768 11:32:36.767520 RX DQ/DQS(RDDQC) : PASS
3769 11:32:36.767594 TX DQ/DQS : PASS
3770 11:32:36.770822 RX DATLAT : PASS
3771 11:32:36.774330 RX DQ/DQS(Engine): PASS
3772 11:32:36.774405 TX OE : NO K
3773 11:32:36.776944 All Pass.
3774 11:32:36.777017
3775 11:32:36.777075 DramC Write-DBI off
3776 11:32:36.780417 PER_BANK_REFRESH: Hybrid Mode
3777 11:32:36.780491 TX_TRACKING: ON
3778 11:32:36.790549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 11:32:36.794322 [FAST_K] Save calibration result to emmc
3780 11:32:36.797455 dramc_set_vcore_voltage set vcore to 650000
3781 11:32:36.800299 Read voltage for 600, 5
3782 11:32:36.800373 Vio18 = 0
3783 11:32:36.803675 Vcore = 650000
3784 11:32:36.803749 Vdram = 0
3785 11:32:36.803807 Vddq = 0
3786 11:32:36.807362 Vmddr = 0
3787 11:32:36.810566 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 11:32:36.817157 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 11:32:36.817232 MEM_TYPE=3, freq_sel=19
3790 11:32:36.820813 sv_algorithm_assistance_LP4_1600
3791 11:32:36.826755 ============ PULL DRAM RESETB DOWN ============
3792 11:32:36.830114 ========== PULL DRAM RESETB DOWN end =========
3793 11:32:36.833712 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 11:32:36.837061 ===================================
3795 11:32:36.840429 LPDDR4 DRAM CONFIGURATION
3796 11:32:36.843954 ===================================
3797 11:32:36.844029 EX_ROW_EN[0] = 0x0
3798 11:32:36.846521 EX_ROW_EN[1] = 0x0
3799 11:32:36.850228 LP4Y_EN = 0x0
3800 11:32:36.850303 WORK_FSP = 0x0
3801 11:32:36.853429 WL = 0x2
3802 11:32:36.853502 RL = 0x2
3803 11:32:36.857221 BL = 0x2
3804 11:32:36.857296 RPST = 0x0
3805 11:32:36.860112 RD_PRE = 0x0
3806 11:32:36.860187 WR_PRE = 0x1
3807 11:32:36.863356 WR_PST = 0x0
3808 11:32:36.863431 DBI_WR = 0x0
3809 11:32:36.866472 DBI_RD = 0x0
3810 11:32:36.866546 OTF = 0x1
3811 11:32:36.869906 ===================================
3812 11:32:36.873307 ===================================
3813 11:32:36.876775 ANA top config
3814 11:32:36.880006 ===================================
3815 11:32:36.880080 DLL_ASYNC_EN = 0
3816 11:32:36.883421 ALL_SLAVE_EN = 1
3817 11:32:36.886408 NEW_RANK_MODE = 1
3818 11:32:36.889925 DLL_IDLE_MODE = 1
3819 11:32:36.893058 LP45_APHY_COMB_EN = 1
3820 11:32:36.893132 TX_ODT_DIS = 1
3821 11:32:36.896566 NEW_8X_MODE = 1
3822 11:32:36.899779 ===================================
3823 11:32:36.903103 ===================================
3824 11:32:36.906460 data_rate = 1200
3825 11:32:36.910051 CKR = 1
3826 11:32:36.913421 DQ_P2S_RATIO = 8
3827 11:32:36.916390 ===================================
3828 11:32:36.919723 CA_P2S_RATIO = 8
3829 11:32:36.919798 DQ_CA_OPEN = 0
3830 11:32:36.922850 DQ_SEMI_OPEN = 0
3831 11:32:36.927095 CA_SEMI_OPEN = 0
3832 11:32:36.929803 CA_FULL_RATE = 0
3833 11:32:36.932973 DQ_CKDIV4_EN = 1
3834 11:32:36.933047 CA_CKDIV4_EN = 1
3835 11:32:36.936316 CA_PREDIV_EN = 0
3836 11:32:36.939969 PH8_DLY = 0
3837 11:32:36.943280 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 11:32:36.946414 DQ_AAMCK_DIV = 4
3839 11:32:36.949540 CA_AAMCK_DIV = 4
3840 11:32:36.949614 CA_ADMCK_DIV = 4
3841 11:32:36.953215 DQ_TRACK_CA_EN = 0
3842 11:32:36.956459 CA_PICK = 600
3843 11:32:36.959722 CA_MCKIO = 600
3844 11:32:36.963313 MCKIO_SEMI = 0
3845 11:32:36.966072 PLL_FREQ = 2288
3846 11:32:36.969419 DQ_UI_PI_RATIO = 32
3847 11:32:36.969516 CA_UI_PI_RATIO = 0
3848 11:32:36.972925 ===================================
3849 11:32:36.976096 ===================================
3850 11:32:36.979603 memory_type:LPDDR4
3851 11:32:36.982741 GP_NUM : 10
3852 11:32:36.982814 SRAM_EN : 1
3853 11:32:36.986089 MD32_EN : 0
3854 11:32:36.989739 ===================================
3855 11:32:36.992833 [ANA_INIT] >>>>>>>>>>>>>>
3856 11:32:36.996093 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 11:32:36.999490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 11:32:37.002748 ===================================
3859 11:32:37.002822 data_rate = 1200,PCW = 0X5800
3860 11:32:37.006029 ===================================
3861 11:32:37.009696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 11:32:37.015939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 11:32:37.022852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 11:32:37.025855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 11:32:37.029392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 11:32:37.032707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 11:32:37.036062 [ANA_INIT] flow start
3868 11:32:37.039121 [ANA_INIT] PLL >>>>>>>>
3869 11:32:37.039195 [ANA_INIT] PLL <<<<<<<<
3870 11:32:37.042800 [ANA_INIT] MIDPI >>>>>>>>
3871 11:32:37.046061 [ANA_INIT] MIDPI <<<<<<<<
3872 11:32:37.046178 [ANA_INIT] DLL >>>>>>>>
3873 11:32:37.049013 [ANA_INIT] flow end
3874 11:32:37.053276 ============ LP4 DIFF to SE enter ============
3875 11:32:37.055842 ============ LP4 DIFF to SE exit ============
3876 11:32:37.058933 [ANA_INIT] <<<<<<<<<<<<<
3877 11:32:37.062200 [Flow] Enable top DCM control >>>>>
3878 11:32:37.065853 [Flow] Enable top DCM control <<<<<
3879 11:32:37.069225 Enable DLL master slave shuffle
3880 11:32:37.075551 ==============================================================
3881 11:32:37.075628 Gating Mode config
3882 11:32:37.082420 ==============================================================
3883 11:32:37.085395 Config description:
3884 11:32:37.092321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 11:32:37.099024 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 11:32:37.105566 SELPH_MODE 0: By rank 1: By Phase
3887 11:32:37.112209 ==============================================================
3888 11:32:37.112284 GAT_TRACK_EN = 1
3889 11:32:37.115354 RX_GATING_MODE = 2
3890 11:32:37.118787 RX_GATING_TRACK_MODE = 2
3891 11:32:37.122181 SELPH_MODE = 1
3892 11:32:37.125199 PICG_EARLY_EN = 1
3893 11:32:37.128826 VALID_LAT_VALUE = 1
3894 11:32:37.135106 ==============================================================
3895 11:32:37.139030 Enter into Gating configuration >>>>
3896 11:32:37.142011 Exit from Gating configuration <<<<
3897 11:32:37.145171 Enter into DVFS_PRE_config >>>>>
3898 11:32:37.155704 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 11:32:37.158494 Exit from DVFS_PRE_config <<<<<
3900 11:32:37.161856 Enter into PICG configuration >>>>
3901 11:32:37.165179 Exit from PICG configuration <<<<
3902 11:32:37.168887 [RX_INPUT] configuration >>>>>
3903 11:32:37.168961 [RX_INPUT] configuration <<<<<
3904 11:32:37.175188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 11:32:37.181928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 11:32:37.185174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 11:32:37.191930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 11:32:37.198284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 11:32:37.204750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 11:32:37.207979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 11:32:37.211751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 11:32:37.218264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 11:32:37.221580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 11:32:37.224608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 11:32:37.231747 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 11:32:37.234725 ===================================
3917 11:32:37.234803 LPDDR4 DRAM CONFIGURATION
3918 11:32:37.238433 ===================================
3919 11:32:37.241217 EX_ROW_EN[0] = 0x0
3920 11:32:37.244609 EX_ROW_EN[1] = 0x0
3921 11:32:37.244674 LP4Y_EN = 0x0
3922 11:32:37.248024 WORK_FSP = 0x0
3923 11:32:37.248089 WL = 0x2
3924 11:32:37.251012 RL = 0x2
3925 11:32:37.251072 BL = 0x2
3926 11:32:37.254661 RPST = 0x0
3927 11:32:37.254727 RD_PRE = 0x0
3928 11:32:37.258040 WR_PRE = 0x1
3929 11:32:37.258128 WR_PST = 0x0
3930 11:32:37.260959 DBI_WR = 0x0
3931 11:32:37.261029 DBI_RD = 0x0
3932 11:32:37.264272 OTF = 0x1
3933 11:32:37.267822 ===================================
3934 11:32:37.270912 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 11:32:37.274463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 11:32:37.280918 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 11:32:37.284068 ===================================
3938 11:32:37.284129 LPDDR4 DRAM CONFIGURATION
3939 11:32:37.287486 ===================================
3940 11:32:37.290980 EX_ROW_EN[0] = 0x10
3941 11:32:37.294398 EX_ROW_EN[1] = 0x0
3942 11:32:37.294465 LP4Y_EN = 0x0
3943 11:32:37.297515 WORK_FSP = 0x0
3944 11:32:37.297577 WL = 0x2
3945 11:32:37.300836 RL = 0x2
3946 11:32:37.300905 BL = 0x2
3947 11:32:37.304046 RPST = 0x0
3948 11:32:37.304110 RD_PRE = 0x0
3949 11:32:37.307514 WR_PRE = 0x1
3950 11:32:37.307575 WR_PST = 0x0
3951 11:32:37.310492 DBI_WR = 0x0
3952 11:32:37.310553 DBI_RD = 0x0
3953 11:32:37.314465 OTF = 0x1
3954 11:32:37.317617 ===================================
3955 11:32:37.324603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 11:32:37.327152 nWR fixed to 30
3957 11:32:37.327248 [ModeRegInit_LP4] CH0 RK0
3958 11:32:37.330475 [ModeRegInit_LP4] CH0 RK1
3959 11:32:37.334012 [ModeRegInit_LP4] CH1 RK0
3960 11:32:37.334097 [ModeRegInit_LP4] CH1 RK1
3961 11:32:37.337034 match AC timing 17
3962 11:32:37.340610 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 11:32:37.347224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 11:32:37.350828 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 11:32:37.353892 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 11:32:37.360559 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 11:32:37.360634 ==
3968 11:32:37.363607 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 11:32:37.367009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 11:32:37.367086 ==
3971 11:32:37.373731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 11:32:37.380325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3973 11:32:37.384120 [CA 0] Center 37 (7~67) winsize 61
3974 11:32:37.386827 [CA 1] Center 37 (7~67) winsize 61
3975 11:32:37.390202 [CA 2] Center 35 (5~65) winsize 61
3976 11:32:37.393480 [CA 3] Center 34 (4~65) winsize 62
3977 11:32:37.396811 [CA 4] Center 34 (4~64) winsize 61
3978 11:32:37.400092 [CA 5] Center 34 (4~64) winsize 61
3979 11:32:37.400167
3980 11:32:37.403564 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3981 11:32:37.403639
3982 11:32:37.406667 [CATrainingPosCal] consider 1 rank data
3983 11:32:37.410199 u2DelayCellTimex100 = 270/100 ps
3984 11:32:37.413612 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3985 11:32:37.416260 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3986 11:32:37.419623 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3987 11:32:37.423235 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3988 11:32:37.426648 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3989 11:32:37.430097 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3990 11:32:37.430211
3991 11:32:37.436237 CA PerBit enable=1, Macro0, CA PI delay=34
3992 11:32:37.436305
3993 11:32:37.440015 [CBTSetCACLKResult] CA Dly = 34
3994 11:32:37.440081 CS Dly: 5 (0~36)
3995 11:32:37.440137 ==
3996 11:32:37.442661 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 11:32:37.446327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 11:32:37.446391 ==
3999 11:32:37.453004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 11:32:37.459515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4001 11:32:37.462936 [CA 0] Center 37 (7~67) winsize 61
4002 11:32:37.466268 [CA 1] Center 36 (6~67) winsize 62
4003 11:32:37.469229 [CA 2] Center 35 (5~65) winsize 61
4004 11:32:37.472467 [CA 3] Center 35 (5~65) winsize 61
4005 11:32:37.476448 [CA 4] Center 34 (4~65) winsize 62
4006 11:32:37.479884 [CA 5] Center 34 (3~65) winsize 63
4007 11:32:37.479948
4008 11:32:37.482580 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4009 11:32:37.482644
4010 11:32:37.486422 [CATrainingPosCal] consider 2 rank data
4011 11:32:37.489649 u2DelayCellTimex100 = 270/100 ps
4012 11:32:37.492278 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4013 11:32:37.495797 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4014 11:32:37.499358 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4015 11:32:37.502379 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4016 11:32:37.508976 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4017 11:32:37.512151 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4018 11:32:37.512222
4019 11:32:37.515550 CA PerBit enable=1, Macro0, CA PI delay=34
4020 11:32:37.515622
4021 11:32:37.519047 [CBTSetCACLKResult] CA Dly = 34
4022 11:32:37.519110 CS Dly: 5 (0~37)
4023 11:32:37.519163
4024 11:32:37.522034 ----->DramcWriteLeveling(PI) begin...
4025 11:32:37.522127 ==
4026 11:32:37.525856 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 11:32:37.532226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 11:32:37.532293 ==
4029 11:32:37.535909 Write leveling (Byte 0): 31 => 31
4030 11:32:37.538711 Write leveling (Byte 1): 30 => 30
4031 11:32:37.538781 DramcWriteLeveling(PI) end<-----
4032 11:32:37.538839
4033 11:32:37.541993 ==
4034 11:32:37.545657 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 11:32:37.548833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 11:32:37.548913 ==
4037 11:32:37.551949 [Gating] SW mode calibration
4038 11:32:37.558924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 11:32:37.562162 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 11:32:37.568861 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 11:32:37.572137 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 11:32:37.574946 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 11:32:37.581546 0 9 12 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
4044 11:32:37.584990 0 9 16 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (0 0)
4045 11:32:37.588227 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4046 11:32:37.594672 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 11:32:37.598553 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 11:32:37.601580 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 11:32:37.608458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 11:32:37.611691 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 11:32:37.614967 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4052 11:32:37.621688 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4053 11:32:37.624867 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4054 11:32:37.628385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 11:32:37.635097 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 11:32:37.638707 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 11:32:37.641302 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 11:32:37.648141 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 11:32:37.651105 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 11:32:37.654504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:32:37.661712 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:32:37.664691 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:32:37.667848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:32:37.674716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:32:37.677953 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:32:37.680935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:32:37.687678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:32:37.691399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:32:37.694252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:32:37.701427 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:32:37.704597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:32:37.707597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:32:37.713903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:32:37.717791 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:32:37.720388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4076 11:32:37.727746 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4077 11:32:37.727819 Total UI for P1: 0, mck2ui 16
4078 11:32:37.733652 best dqsien dly found for B0: ( 0, 13, 12)
4079 11:32:37.737212 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 11:32:37.740855 Total UI for P1: 0, mck2ui 16
4081 11:32:37.743687 best dqsien dly found for B1: ( 0, 13, 16)
4082 11:32:37.747081 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 11:32:37.750772 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4084 11:32:37.750838
4085 11:32:37.754031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 11:32:37.756930 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4087 11:32:37.760809 [Gating] SW calibration Done
4088 11:32:37.760877 ==
4089 11:32:37.763677 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 11:32:37.767208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 11:32:37.770110 ==
4092 11:32:37.770190 RX Vref Scan: 0
4093 11:32:37.770262
4094 11:32:37.773547 RX Vref 0 -> 0, step: 1
4095 11:32:37.773610
4096 11:32:37.776744 RX Delay -230 -> 252, step: 16
4097 11:32:37.780120 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4098 11:32:37.783507 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4099 11:32:37.786638 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4100 11:32:37.793527 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4101 11:32:37.796438 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4102 11:32:37.799688 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4103 11:32:37.803168 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4104 11:32:37.806423 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4105 11:32:37.812935 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 11:32:37.816398 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4107 11:32:37.819735 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4108 11:32:37.823184 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4109 11:32:37.829447 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4110 11:32:37.833195 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4111 11:32:37.836037 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4112 11:32:37.839897 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4113 11:32:37.843127 ==
4114 11:32:37.843198 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 11:32:37.849398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 11:32:37.849464 ==
4117 11:32:37.849525 DQS Delay:
4118 11:32:37.852865 DQS0 = 0, DQS1 = 0
4119 11:32:37.852951 DQM Delay:
4120 11:32:37.855900 DQM0 = 38, DQM1 = 31
4121 11:32:37.855961 DQ Delay:
4122 11:32:37.859185 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4123 11:32:37.862833 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4124 11:32:37.865752 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4125 11:32:37.869456 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4126 11:32:37.869544
4127 11:32:37.869623
4128 11:32:37.869699 ==
4129 11:32:37.872414 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 11:32:37.876232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 11:32:37.876317 ==
4132 11:32:37.876394
4133 11:32:37.876469
4134 11:32:37.879159 TX Vref Scan disable
4135 11:32:37.882889 == TX Byte 0 ==
4136 11:32:37.885890 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4137 11:32:37.889015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4138 11:32:37.892635 == TX Byte 1 ==
4139 11:32:37.895589 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4140 11:32:37.898967 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4141 11:32:37.899056 ==
4142 11:32:37.902067 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 11:32:37.908967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 11:32:37.909055 ==
4145 11:32:37.909135
4146 11:32:37.909217
4147 11:32:37.909299 TX Vref Scan disable
4148 11:32:37.913239 == TX Byte 0 ==
4149 11:32:37.916592 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4150 11:32:37.923192 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4151 11:32:37.923280 == TX Byte 1 ==
4152 11:32:37.926769 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 11:32:37.933060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 11:32:37.933148
4155 11:32:37.933229 [DATLAT]
4156 11:32:37.933307 Freq=600, CH0 RK0
4157 11:32:37.933378
4158 11:32:37.936364 DATLAT Default: 0x9
4159 11:32:37.936452 0, 0xFFFF, sum = 0
4160 11:32:37.939610 1, 0xFFFF, sum = 0
4161 11:32:37.939702 2, 0xFFFF, sum = 0
4162 11:32:37.942861 3, 0xFFFF, sum = 0
4163 11:32:37.946229 4, 0xFFFF, sum = 0
4164 11:32:37.946316 5, 0xFFFF, sum = 0
4165 11:32:37.949611 6, 0xFFFF, sum = 0
4166 11:32:37.949698 7, 0xFFFF, sum = 0
4167 11:32:37.953095 8, 0x0, sum = 1
4168 11:32:37.953180 9, 0x0, sum = 2
4169 11:32:37.953333 10, 0x0, sum = 3
4170 11:32:37.956354 11, 0x0, sum = 4
4171 11:32:37.956418 best_step = 9
4172 11:32:37.956497
4173 11:32:37.956573 ==
4174 11:32:37.959864 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 11:32:37.966619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 11:32:37.966704 ==
4177 11:32:37.966785 RX Vref Scan: 1
4178 11:32:37.966864
4179 11:32:37.969360 RX Vref 0 -> 0, step: 1
4180 11:32:37.969443
4181 11:32:37.972750 RX Delay -195 -> 252, step: 8
4182 11:32:37.972833
4183 11:32:37.975771 Set Vref, RX VrefLevel [Byte0]: 61
4184 11:32:37.979090 [Byte1]: 53
4185 11:32:37.979173
4186 11:32:37.982621 Final RX Vref Byte 0 = 61 to rank0
4187 11:32:37.986231 Final RX Vref Byte 1 = 53 to rank0
4188 11:32:37.989529 Final RX Vref Byte 0 = 61 to rank1
4189 11:32:37.992487 Final RX Vref Byte 1 = 53 to rank1==
4190 11:32:37.995983 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 11:32:37.999601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 11:32:37.999664 ==
4193 11:32:38.002694 DQS Delay:
4194 11:32:38.002761 DQS0 = 0, DQS1 = 0
4195 11:32:38.005793 DQM Delay:
4196 11:32:38.005880 DQM0 = 34, DQM1 = 28
4197 11:32:38.005959 DQ Delay:
4198 11:32:38.009159 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4199 11:32:38.012375 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4200 11:32:38.015901 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4201 11:32:38.019485 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4202 11:32:38.019574
4203 11:32:38.019659
4204 11:32:38.029350 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4205 11:32:38.032457 CH0 RK0: MR19=808, MR18=3F3E
4206 11:32:38.039442 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4207 11:32:38.039534
4208 11:32:38.042214 ----->DramcWriteLeveling(PI) begin...
4209 11:32:38.042306 ==
4210 11:32:38.045779 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 11:32:38.048877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 11:32:38.048965 ==
4213 11:32:38.052743 Write leveling (Byte 0): 32 => 32
4214 11:32:38.055394 Write leveling (Byte 1): 31 => 31
4215 11:32:38.059371 DramcWriteLeveling(PI) end<-----
4216 11:32:38.059440
4217 11:32:38.059522 ==
4218 11:32:38.062189 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 11:32:38.066007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:32:38.066105 ==
4221 11:32:38.069000 [Gating] SW mode calibration
4222 11:32:38.075758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 11:32:38.082313 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 11:32:38.085321 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 11:32:38.088732 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 11:32:38.095543 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4227 11:32:38.098862 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
4228 11:32:38.102549 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
4229 11:32:38.108655 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:32:38.112278 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 11:32:38.115281 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 11:32:38.122365 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 11:32:38.125941 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 11:32:38.128433 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:32:38.135208 0 10 12 | B1->B0 | 2626 3737 | 1 0 | (0 0) (0 0)
4236 11:32:38.138899 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4237 11:32:38.142136 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 11:32:38.148696 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:32:38.151698 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 11:32:38.155163 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 11:32:38.161892 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 11:32:38.165630 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:32:38.168602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4244 11:32:38.171843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:32:38.178566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:32:38.181895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:32:38.185246 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:32:38.191843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:32:38.195623 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:32:38.200136 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:32:38.205347 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:32:38.208245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:32:38.211853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:32:38.218069 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:32:38.221425 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:32:38.224953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:32:38.232131 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:32:38.235260 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:32:38.238017 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4260 11:32:38.244589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4261 11:32:38.247865 Total UI for P1: 0, mck2ui 16
4262 11:32:38.251600 best dqsien dly found for B0: ( 0, 13, 12)
4263 11:32:38.255014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 11:32:38.258197 Total UI for P1: 0, mck2ui 16
4265 11:32:38.261477 best dqsien dly found for B1: ( 0, 13, 16)
4266 11:32:38.264826 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4267 11:32:38.267959 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4268 11:32:38.268034
4269 11:32:38.271685 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4270 11:32:38.274681 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4271 11:32:38.278432 [Gating] SW calibration Done
4272 11:32:38.278506 ==
4273 11:32:38.281364 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 11:32:38.287659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 11:32:38.287759 ==
4276 11:32:38.287844 RX Vref Scan: 0
4277 11:32:38.287932
4278 11:32:38.291129 RX Vref 0 -> 0, step: 1
4279 11:32:38.291215
4280 11:32:38.294381 RX Delay -230 -> 252, step: 16
4281 11:32:38.297896 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4282 11:32:38.301076 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4283 11:32:38.304227 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4284 11:32:38.311375 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4285 11:32:38.313985 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4286 11:32:38.318225 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4287 11:32:38.321241 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4288 11:32:38.327607 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4289 11:32:38.330697 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4290 11:32:38.334473 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4291 11:32:38.337575 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4292 11:32:38.344099 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4293 11:32:38.347505 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4294 11:32:38.350696 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4295 11:32:38.353728 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4296 11:32:38.360632 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4297 11:32:38.360707 ==
4298 11:32:38.363620 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 11:32:38.367181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 11:32:38.367256 ==
4301 11:32:38.367314 DQS Delay:
4302 11:32:38.370359 DQS0 = 0, DQS1 = 0
4303 11:32:38.370433 DQM Delay:
4304 11:32:38.373480 DQM0 = 35, DQM1 = 27
4305 11:32:38.373554 DQ Delay:
4306 11:32:38.376879 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4307 11:32:38.380503 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4308 11:32:38.383556 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4309 11:32:38.386666 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4310 11:32:38.386742
4311 11:32:38.386800
4312 11:32:38.386854 ==
4313 11:32:38.390085 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 11:32:38.393436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 11:32:38.393512 ==
4316 11:32:38.393570
4317 11:32:38.396813
4318 11:32:38.396887 TX Vref Scan disable
4319 11:32:38.400146 == TX Byte 0 ==
4320 11:32:38.403571 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4321 11:32:38.406493 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4322 11:32:38.409720 == TX Byte 1 ==
4323 11:32:38.413228 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4324 11:32:38.416797 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4325 11:32:38.416872 ==
4326 11:32:38.419759 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 11:32:38.426513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 11:32:38.426589 ==
4329 11:32:38.426647
4330 11:32:38.426701
4331 11:32:38.426752 TX Vref Scan disable
4332 11:32:38.431504 == TX Byte 0 ==
4333 11:32:38.434454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4334 11:32:38.441046 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4335 11:32:38.441122 == TX Byte 1 ==
4336 11:32:38.444409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 11:32:38.451135 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 11:32:38.451211
4339 11:32:38.451269 [DATLAT]
4340 11:32:38.451323 Freq=600, CH0 RK1
4341 11:32:38.451374
4342 11:32:38.454711 DATLAT Default: 0x9
4343 11:32:38.454785 0, 0xFFFF, sum = 0
4344 11:32:38.457841 1, 0xFFFF, sum = 0
4345 11:32:38.457932 2, 0xFFFF, sum = 0
4346 11:32:38.460903 3, 0xFFFF, sum = 0
4347 11:32:38.464307 4, 0xFFFF, sum = 0
4348 11:32:38.464384 5, 0xFFFF, sum = 0
4349 11:32:38.467479 6, 0xFFFF, sum = 0
4350 11:32:38.467555 7, 0xFFFF, sum = 0
4351 11:32:38.470953 8, 0x0, sum = 1
4352 11:32:38.471028 9, 0x0, sum = 2
4353 11:32:38.471087 10, 0x0, sum = 3
4354 11:32:38.474544 11, 0x0, sum = 4
4355 11:32:38.474619 best_step = 9
4356 11:32:38.474677
4357 11:32:38.474730 ==
4358 11:32:38.477969 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 11:32:38.484254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 11:32:38.484328 ==
4361 11:32:38.484386 RX Vref Scan: 0
4362 11:32:38.484440
4363 11:32:38.487907 RX Vref 0 -> 0, step: 1
4364 11:32:38.487981
4365 11:32:38.490782 RX Delay -195 -> 252, step: 8
4366 11:32:38.494270 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4367 11:32:38.500599 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4368 11:32:38.504116 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4369 11:32:38.507697 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4370 11:32:38.510670 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4371 11:32:38.517197 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4372 11:32:38.520571 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4373 11:32:38.524119 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4374 11:32:38.527372 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4375 11:32:38.530740 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4376 11:32:38.537151 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4377 11:32:38.540874 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4378 11:32:38.543904 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4379 11:32:38.547682 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4380 11:32:38.553980 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4381 11:32:38.557005 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4382 11:32:38.557071 ==
4383 11:32:38.560472 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 11:32:38.563725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 11:32:38.563788 ==
4386 11:32:38.567079 DQS Delay:
4387 11:32:38.567154 DQS0 = 0, DQS1 = 0
4388 11:32:38.567208 DQM Delay:
4389 11:32:38.570478 DQM0 = 33, DQM1 = 28
4390 11:32:38.570540 DQ Delay:
4391 11:32:38.573537 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4392 11:32:38.576825 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4393 11:32:38.580285 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4394 11:32:38.583677 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4395 11:32:38.583743
4396 11:32:38.583797
4397 11:32:38.593585 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4398 11:32:38.596747 CH0 RK1: MR19=808, MR18=6D3B
4399 11:32:38.600355 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4400 11:32:38.603573 [RxdqsGatingPostProcess] freq 600
4401 11:32:38.610078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 11:32:38.613388 Pre-setting of DQS Precalculation
4403 11:32:38.616821 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 11:32:38.616896 ==
4405 11:32:38.620139 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 11:32:38.627087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 11:32:38.627163 ==
4408 11:32:38.629805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 11:32:38.636392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4410 11:32:38.640102 [CA 0] Center 35 (5~66) winsize 62
4411 11:32:38.643461 [CA 1] Center 36 (6~66) winsize 61
4412 11:32:38.646546 [CA 2] Center 34 (4~65) winsize 62
4413 11:32:38.649978 [CA 3] Center 34 (4~65) winsize 62
4414 11:32:38.653163 [CA 4] Center 34 (4~65) winsize 62
4415 11:32:38.656521 [CA 5] Center 33 (3~64) winsize 62
4416 11:32:38.656596
4417 11:32:38.660133 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4418 11:32:38.660207
4419 11:32:38.663673 [CATrainingPosCal] consider 1 rank data
4420 11:32:38.666828 u2DelayCellTimex100 = 270/100 ps
4421 11:32:38.670267 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 11:32:38.677079 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4423 11:32:38.680211 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 11:32:38.683127 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 11:32:38.686584 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 11:32:38.690321 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 11:32:38.690397
4428 11:32:38.693151 CA PerBit enable=1, Macro0, CA PI delay=33
4429 11:32:38.693226
4430 11:32:38.696529 [CBTSetCACLKResult] CA Dly = 33
4431 11:32:38.696603 CS Dly: 4 (0~35)
4432 11:32:38.700203 ==
4433 11:32:38.703130 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 11:32:38.706441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 11:32:38.706516 ==
4436 11:32:38.709614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 11:32:38.716339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4438 11:32:38.720122 [CA 0] Center 35 (5~66) winsize 62
4439 11:32:38.723560 [CA 1] Center 35 (5~66) winsize 62
4440 11:32:38.726861 [CA 2] Center 34 (4~65) winsize 62
4441 11:32:38.729977 [CA 3] Center 34 (4~65) winsize 62
4442 11:32:38.733491 [CA 4] Center 34 (4~65) winsize 62
4443 11:32:38.736720 [CA 5] Center 33 (3~64) winsize 62
4444 11:32:38.736796
4445 11:32:38.739829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4446 11:32:38.739905
4447 11:32:38.743215 [CATrainingPosCal] consider 2 rank data
4448 11:32:38.746706 u2DelayCellTimex100 = 270/100 ps
4449 11:32:38.749784 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4450 11:32:38.756765 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4451 11:32:38.760323 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 11:32:38.763506 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 11:32:38.766537 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 11:32:38.769893 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 11:32:38.769968
4456 11:32:38.772645 CA PerBit enable=1, Macro0, CA PI delay=33
4457 11:32:38.772720
4458 11:32:38.776080 [CBTSetCACLKResult] CA Dly = 33
4459 11:32:38.779722 CS Dly: 5 (0~37)
4460 11:32:38.779797
4461 11:32:38.782961 ----->DramcWriteLeveling(PI) begin...
4462 11:32:38.783037 ==
4463 11:32:38.785907 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 11:32:38.789296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 11:32:38.789372 ==
4466 11:32:38.792689 Write leveling (Byte 0): 30 => 30
4467 11:32:38.796432 Write leveling (Byte 1): 31 => 31
4468 11:32:38.799452 DramcWriteLeveling(PI) end<-----
4469 11:32:38.799527
4470 11:32:38.799585 ==
4471 11:32:38.802818 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 11:32:38.805778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 11:32:38.805853 ==
4474 11:32:38.809211 [Gating] SW mode calibration
4475 11:32:38.815706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 11:32:38.822465 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 11:32:38.825589 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 11:32:38.829115 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 11:32:38.835523 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 11:32:38.839147 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 1)
4481 11:32:38.842688 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (1 0) (0 0)
4482 11:32:38.848954 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 11:32:38.852081 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 11:32:38.855803 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 11:32:38.861869 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 11:32:38.865513 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:32:38.868517 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:32:38.875317 0 10 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4489 11:32:38.878533 0 10 16 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
4490 11:32:38.882153 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 11:32:38.888446 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 11:32:38.892095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:32:38.895081 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 11:32:38.902026 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:32:38.904781 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:32:38.908325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:32:38.915152 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4498 11:32:38.918070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:32:38.921681 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:32:38.928190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:32:38.931654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:32:38.934640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:32:38.941406 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:32:38.944529 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:32:38.948011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:32:38.954491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:32:38.957859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:32:38.961285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:32:38.968178 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:32:38.971271 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:32:38.974460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:32:38.980999 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4513 11:32:38.984273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4514 11:32:38.987813 Total UI for P1: 0, mck2ui 16
4515 11:32:38.991138 best dqsien dly found for B0: ( 0, 13, 12)
4516 11:32:38.994928 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 11:32:38.997770 Total UI for P1: 0, mck2ui 16
4518 11:32:39.001232 best dqsien dly found for B1: ( 0, 13, 14)
4519 11:32:39.004245 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4520 11:32:39.007425 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4521 11:32:39.007489
4522 11:32:39.014316 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4523 11:32:39.017853 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4524 11:32:39.020692 [Gating] SW calibration Done
4525 11:32:39.020771 ==
4526 11:32:39.024026 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 11:32:39.027647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 11:32:39.027714 ==
4529 11:32:39.027770 RX Vref Scan: 0
4530 11:32:39.027822
4531 11:32:39.030730 RX Vref 0 -> 0, step: 1
4532 11:32:39.030804
4533 11:32:39.034081 RX Delay -230 -> 252, step: 16
4534 11:32:39.036978 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4535 11:32:39.043593 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4536 11:32:39.047338 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4537 11:32:39.050392 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4538 11:32:39.053653 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4539 11:32:39.057401 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4540 11:32:39.063584 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4541 11:32:39.066695 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4542 11:32:39.070307 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4543 11:32:39.073782 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4544 11:32:39.080080 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4545 11:32:39.083367 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4546 11:32:39.086712 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4547 11:32:39.090324 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4548 11:32:39.096535 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4549 11:32:39.100234 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4550 11:32:39.100310 ==
4551 11:32:39.103170 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 11:32:39.106829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:32:39.106905 ==
4554 11:32:39.109914 DQS Delay:
4555 11:32:39.109989 DQS0 = 0, DQS1 = 0
4556 11:32:39.110047 DQM Delay:
4557 11:32:39.113213 DQM0 = 38, DQM1 = 28
4558 11:32:39.113287 DQ Delay:
4559 11:32:39.116544 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4560 11:32:39.119558 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4561 11:32:39.122953 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4562 11:32:39.126678 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4563 11:32:39.126757
4564 11:32:39.126815
4565 11:32:39.126869 ==
4566 11:32:39.129456 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:32:39.136179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:32:39.136254 ==
4569 11:32:39.136313
4570 11:32:39.136366
4571 11:32:39.136417 TX Vref Scan disable
4572 11:32:39.139670 == TX Byte 0 ==
4573 11:32:39.143219 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4574 11:32:39.149843 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4575 11:32:39.149918 == TX Byte 1 ==
4576 11:32:39.153076 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4577 11:32:39.159958 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4578 11:32:39.160034 ==
4579 11:32:39.163126 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 11:32:39.166424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 11:32:39.166499 ==
4582 11:32:39.166557
4583 11:32:39.166611
4584 11:32:39.169614 TX Vref Scan disable
4585 11:32:39.173223 == TX Byte 0 ==
4586 11:32:39.176258 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4587 11:32:39.179796 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4588 11:32:39.183007 == TX Byte 1 ==
4589 11:32:39.186131 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 11:32:39.189850 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 11:32:39.189926
4592 11:32:39.189985 [DATLAT]
4593 11:32:39.192810 Freq=600, CH1 RK0
4594 11:32:39.192886
4595 11:32:39.192943 DATLAT Default: 0x9
4596 11:32:39.196305 0, 0xFFFF, sum = 0
4597 11:32:39.199828 1, 0xFFFF, sum = 0
4598 11:32:39.199904 2, 0xFFFF, sum = 0
4599 11:32:39.202834 3, 0xFFFF, sum = 0
4600 11:32:39.202910 4, 0xFFFF, sum = 0
4601 11:32:39.206334 5, 0xFFFF, sum = 0
4602 11:32:39.206410 6, 0xFFFF, sum = 0
4603 11:32:39.209750 7, 0xFFFF, sum = 0
4604 11:32:39.209825 8, 0x0, sum = 1
4605 11:32:39.212694 9, 0x0, sum = 2
4606 11:32:39.212791 10, 0x0, sum = 3
4607 11:32:39.212853 11, 0x0, sum = 4
4608 11:32:39.215988 best_step = 9
4609 11:32:39.216062
4610 11:32:39.216120 ==
4611 11:32:39.219455 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 11:32:39.222694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 11:32:39.222770 ==
4614 11:32:39.226402 RX Vref Scan: 1
4615 11:32:39.226476
4616 11:32:39.226534 RX Vref 0 -> 0, step: 1
4617 11:32:39.226588
4618 11:32:39.229700 RX Delay -195 -> 252, step: 8
4619 11:32:39.229775
4620 11:32:39.233071 Set Vref, RX VrefLevel [Byte0]: 56
4621 11:32:39.236037 [Byte1]: 53
4622 11:32:39.240669
4623 11:32:39.240743 Final RX Vref Byte 0 = 56 to rank0
4624 11:32:39.243768 Final RX Vref Byte 1 = 53 to rank0
4625 11:32:39.246821 Final RX Vref Byte 0 = 56 to rank1
4626 11:32:39.250396 Final RX Vref Byte 1 = 53 to rank1==
4627 11:32:39.253785 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 11:32:39.260239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 11:32:39.260315 ==
4630 11:32:39.260375 DQS Delay:
4631 11:32:39.260429 DQS0 = 0, DQS1 = 0
4632 11:32:39.263339 DQM Delay:
4633 11:32:39.263415 DQM0 = 40, DQM1 = 28
4634 11:32:39.267227 DQ Delay:
4635 11:32:39.270113 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4636 11:32:39.273446 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4637 11:32:39.273521 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4638 11:32:39.280127 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4639 11:32:39.280202
4640 11:32:39.280260
4641 11:32:39.287066 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4642 11:32:39.290072 CH1 RK0: MR19=808, MR18=2D39
4643 11:32:39.296857 CH1_RK0: MR19=0x808, MR18=0x2D39, DQSOSC=399, MR23=63, INC=164, DEC=109
4644 11:32:39.296933
4645 11:32:39.300240 ----->DramcWriteLeveling(PI) begin...
4646 11:32:39.300316 ==
4647 11:32:39.303513 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 11:32:39.306850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 11:32:39.306926 ==
4650 11:32:39.310295 Write leveling (Byte 0): 28 => 28
4651 11:32:39.313481 Write leveling (Byte 1): 31 => 31
4652 11:32:39.316528 DramcWriteLeveling(PI) end<-----
4653 11:32:39.316603
4654 11:32:39.316661 ==
4655 11:32:39.319947 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 11:32:39.323436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 11:32:39.323522 ==
4658 11:32:39.326646 [Gating] SW mode calibration
4659 11:32:39.333111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4660 11:32:39.339973 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4661 11:32:39.342863 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 11:32:39.349526 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 11:32:39.352918 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4664 11:32:39.356389 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 1)
4665 11:32:39.362961 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4666 11:32:39.366391 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 11:32:39.369847 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 11:32:39.376489 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 11:32:39.379349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 11:32:39.382676 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:32:39.386218 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4672 11:32:39.392951 0 10 12 | B1->B0 | 3030 3d3c | 0 1 | (0 0) (0 0)
4673 11:32:39.395859 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4674 11:32:39.399668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 11:32:39.405723 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 11:32:39.409478 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 11:32:39.412582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 11:32:39.419319 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:32:39.422878 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4680 11:32:39.425774 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4681 11:32:39.432477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:32:39.435696 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:32:39.439583 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:32:39.445781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:32:39.449206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:32:39.452516 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:32:39.458823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:32:39.462261 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:32:39.465814 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:32:39.472194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:32:39.475619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:32:39.479460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:32:39.485628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:32:39.489009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:32:39.492335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4696 11:32:39.498961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4697 11:32:39.499036 Total UI for P1: 0, mck2ui 16
4698 11:32:39.505392 best dqsien dly found for B0: ( 0, 13, 10)
4699 11:32:39.508499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 11:32:39.511937 Total UI for P1: 0, mck2ui 16
4701 11:32:39.515683 best dqsien dly found for B1: ( 0, 13, 10)
4702 11:32:39.519162 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4703 11:32:39.521834 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4704 11:32:39.521908
4705 11:32:39.525766 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4706 11:32:39.528499 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4707 11:32:39.531858 [Gating] SW calibration Done
4708 11:32:39.531932 ==
4709 11:32:39.535035 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 11:32:39.538566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 11:32:39.541916 ==
4712 11:32:39.541996 RX Vref Scan: 0
4713 11:32:39.542079
4714 11:32:39.545259 RX Vref 0 -> 0, step: 1
4715 11:32:39.545332
4716 11:32:39.548611 RX Delay -230 -> 252, step: 16
4717 11:32:39.552115 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4718 11:32:39.555117 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4719 11:32:39.558456 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4720 11:32:39.565420 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4721 11:32:39.568756 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4722 11:32:39.571889 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4723 11:32:39.575459 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4724 11:32:39.578333 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4725 11:32:39.585174 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4726 11:32:39.588329 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4727 11:32:39.591688 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4728 11:32:39.594671 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4729 11:32:39.601485 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4730 11:32:39.604899 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4731 11:32:39.608082 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4732 11:32:39.611288 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4733 11:32:39.614981 ==
4734 11:32:39.615055 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 11:32:39.621141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 11:32:39.621217 ==
4737 11:32:39.621275 DQS Delay:
4738 11:32:39.624657 DQS0 = 0, DQS1 = 0
4739 11:32:39.624732 DQM Delay:
4740 11:32:39.627643 DQM0 = 36, DQM1 = 29
4741 11:32:39.627718 DQ Delay:
4742 11:32:39.631555 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4743 11:32:39.634373 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4744 11:32:39.637939 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4745 11:32:39.641270 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4746 11:32:39.641345
4747 11:32:39.641403
4748 11:32:39.641457 ==
4749 11:32:39.644367 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:32:39.647671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:32:39.647750 ==
4752 11:32:39.647808
4753 11:32:39.647861
4754 11:32:39.651024 TX Vref Scan disable
4755 11:32:39.654268 == TX Byte 0 ==
4756 11:32:39.657369 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 11:32:39.661001 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 11:32:39.664336 == TX Byte 1 ==
4759 11:32:39.667635 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4760 11:32:39.670917 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4761 11:32:39.670993 ==
4762 11:32:39.674311 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 11:32:39.680927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 11:32:39.681002 ==
4765 11:32:39.681060
4766 11:32:39.681113
4767 11:32:39.681163 TX Vref Scan disable
4768 11:32:39.684922 == TX Byte 0 ==
4769 11:32:39.688343 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4770 11:32:39.695165 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4771 11:32:39.695241 == TX Byte 1 ==
4772 11:32:39.698047 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4773 11:32:39.704975 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4774 11:32:39.705050
4775 11:32:39.705108 [DATLAT]
4776 11:32:39.705161 Freq=600, CH1 RK1
4777 11:32:39.705213
4778 11:32:39.707969 DATLAT Default: 0x9
4779 11:32:39.708044 0, 0xFFFF, sum = 0
4780 11:32:39.711898 1, 0xFFFF, sum = 0
4781 11:32:39.715012 2, 0xFFFF, sum = 0
4782 11:32:39.715089 3, 0xFFFF, sum = 0
4783 11:32:39.718355 4, 0xFFFF, sum = 0
4784 11:32:39.718431 5, 0xFFFF, sum = 0
4785 11:32:39.721328 6, 0xFFFF, sum = 0
4786 11:32:39.721404 7, 0xFFFF, sum = 0
4787 11:32:39.725023 8, 0x0, sum = 1
4788 11:32:39.725099 9, 0x0, sum = 2
4789 11:32:39.725159 10, 0x0, sum = 3
4790 11:32:39.728294 11, 0x0, sum = 4
4791 11:32:39.728370 best_step = 9
4792 11:32:39.728428
4793 11:32:39.728482 ==
4794 11:32:39.731273 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 11:32:39.738575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 11:32:39.738651 ==
4797 11:32:39.738710 RX Vref Scan: 0
4798 11:32:39.738764
4799 11:32:39.741250 RX Vref 0 -> 0, step: 1
4800 11:32:39.741324
4801 11:32:39.745087 RX Delay -195 -> 252, step: 8
4802 11:32:39.747965 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4803 11:32:39.754427 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4804 11:32:39.757828 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4805 11:32:39.761421 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4806 11:32:39.764898 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4807 11:32:39.771228 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4808 11:32:39.774695 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4809 11:32:39.777947 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4810 11:32:39.781290 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4811 11:32:39.784557 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4812 11:32:39.791451 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4813 11:32:39.794390 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4814 11:32:39.797671 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4815 11:32:39.801019 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4816 11:32:39.807919 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4817 11:32:39.810968 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4818 11:32:39.811043 ==
4819 11:32:39.814805 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 11:32:39.817887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 11:32:39.817962 ==
4822 11:32:39.821041 DQS Delay:
4823 11:32:39.821115 DQS0 = 0, DQS1 = 0
4824 11:32:39.825043 DQM Delay:
4825 11:32:39.825118 DQM0 = 35, DQM1 = 29
4826 11:32:39.825175 DQ Delay:
4827 11:32:39.827343 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4828 11:32:39.830882 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4829 11:32:39.834549 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4830 11:32:39.837338 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4831 11:32:39.837412
4832 11:32:39.837469
4833 11:32:39.847126 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4834 11:32:39.851207 CH1 RK1: MR19=808, MR18=3A5B
4835 11:32:39.857664 CH1_RK1: MR19=0x808, MR18=0x3A5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4836 11:32:39.857740 [RxdqsGatingPostProcess] freq 600
4837 11:32:39.864083 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4838 11:32:39.867798 Pre-setting of DQS Precalculation
4839 11:32:39.870375 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4840 11:32:39.880766 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4841 11:32:39.887133 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4842 11:32:39.887209
4843 11:32:39.887269
4844 11:32:39.890073 [Calibration Summary] 1200 Mbps
4845 11:32:39.890205 CH 0, Rank 0
4846 11:32:39.893565 SW Impedance : PASS
4847 11:32:39.893640 DUTY Scan : NO K
4848 11:32:39.896794 ZQ Calibration : PASS
4849 11:32:39.900359 Jitter Meter : NO K
4850 11:32:39.900434 CBT Training : PASS
4851 11:32:39.903546 Write leveling : PASS
4852 11:32:39.907172 RX DQS gating : PASS
4853 11:32:39.907247 RX DQ/DQS(RDDQC) : PASS
4854 11:32:39.910111 TX DQ/DQS : PASS
4855 11:32:39.914299 RX DATLAT : PASS
4856 11:32:39.914374 RX DQ/DQS(Engine): PASS
4857 11:32:39.917090 TX OE : NO K
4858 11:32:39.917165 All Pass.
4859 11:32:39.917223
4860 11:32:39.920078 CH 0, Rank 1
4861 11:32:39.920159 SW Impedance : PASS
4862 11:32:39.923591 DUTY Scan : NO K
4863 11:32:39.926858 ZQ Calibration : PASS
4864 11:32:39.926933 Jitter Meter : NO K
4865 11:32:39.930059 CBT Training : PASS
4866 11:32:39.933586 Write leveling : PASS
4867 11:32:39.933661 RX DQS gating : PASS
4868 11:32:39.936560 RX DQ/DQS(RDDQC) : PASS
4869 11:32:39.936635 TX DQ/DQS : PASS
4870 11:32:39.940404 RX DATLAT : PASS
4871 11:32:39.943537 RX DQ/DQS(Engine): PASS
4872 11:32:39.943612 TX OE : NO K
4873 11:32:39.946744 All Pass.
4874 11:32:39.946844
4875 11:32:39.946928 CH 1, Rank 0
4876 11:32:39.949746 SW Impedance : PASS
4877 11:32:39.949821 DUTY Scan : NO K
4878 11:32:39.953415 ZQ Calibration : PASS
4879 11:32:39.956406 Jitter Meter : NO K
4880 11:32:39.956481 CBT Training : PASS
4881 11:32:39.959955 Write leveling : PASS
4882 11:32:39.963473 RX DQS gating : PASS
4883 11:32:39.963548 RX DQ/DQS(RDDQC) : PASS
4884 11:32:39.966461 TX DQ/DQS : PASS
4885 11:32:39.969785 RX DATLAT : PASS
4886 11:32:39.969859 RX DQ/DQS(Engine): PASS
4887 11:32:39.972863 TX OE : NO K
4888 11:32:39.972966 All Pass.
4889 11:32:39.973051
4890 11:32:39.976896 CH 1, Rank 1
4891 11:32:39.976971 SW Impedance : PASS
4892 11:32:39.979763 DUTY Scan : NO K
4893 11:32:39.982978 ZQ Calibration : PASS
4894 11:32:39.983053 Jitter Meter : NO K
4895 11:32:39.986505 CBT Training : PASS
4896 11:32:39.989601 Write leveling : PASS
4897 11:32:39.989676 RX DQS gating : PASS
4898 11:32:39.993104 RX DQ/DQS(RDDQC) : PASS
4899 11:32:39.993204 TX DQ/DQS : PASS
4900 11:32:39.996238 RX DATLAT : PASS
4901 11:32:40.000252 RX DQ/DQS(Engine): PASS
4902 11:32:40.000327 TX OE : NO K
4903 11:32:40.003568 All Pass.
4904 11:32:40.003642
4905 11:32:40.003700 DramC Write-DBI off
4906 11:32:40.006306 PER_BANK_REFRESH: Hybrid Mode
4907 11:32:40.009514 TX_TRACKING: ON
4908 11:32:40.016429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4909 11:32:40.019786 [FAST_K] Save calibration result to emmc
4910 11:32:40.023623 dramc_set_vcore_voltage set vcore to 662500
4911 11:32:40.026560 Read voltage for 933, 3
4912 11:32:40.026635 Vio18 = 0
4913 11:32:40.029887 Vcore = 662500
4914 11:32:40.029965 Vdram = 0
4915 11:32:40.030023 Vddq = 0
4916 11:32:40.032841 Vmddr = 0
4917 11:32:40.036019 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4918 11:32:40.043060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4919 11:32:40.043136 MEM_TYPE=3, freq_sel=17
4920 11:32:40.046287 sv_algorithm_assistance_LP4_1600
4921 11:32:40.052658 ============ PULL DRAM RESETB DOWN ============
4922 11:32:40.056055 ========== PULL DRAM RESETB DOWN end =========
4923 11:32:40.059685 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4924 11:32:40.063236 ===================================
4925 11:32:40.066010 LPDDR4 DRAM CONFIGURATION
4926 11:32:40.069556 ===================================
4927 11:32:40.072539 EX_ROW_EN[0] = 0x0
4928 11:32:40.072638 EX_ROW_EN[1] = 0x0
4929 11:32:40.075936 LP4Y_EN = 0x0
4930 11:32:40.076011 WORK_FSP = 0x0
4931 11:32:40.079397 WL = 0x3
4932 11:32:40.079472 RL = 0x3
4933 11:32:40.082952 BL = 0x2
4934 11:32:40.083026 RPST = 0x0
4935 11:32:40.086089 RD_PRE = 0x0
4936 11:32:40.086173 WR_PRE = 0x1
4937 11:32:40.089573 WR_PST = 0x0
4938 11:32:40.089647 DBI_WR = 0x0
4939 11:32:40.092681 DBI_RD = 0x0
4940 11:32:40.092755 OTF = 0x1
4941 11:32:40.096076 ===================================
4942 11:32:40.099258 ===================================
4943 11:32:40.102811 ANA top config
4944 11:32:40.105819 ===================================
4945 11:32:40.109244 DLL_ASYNC_EN = 0
4946 11:32:40.109319 ALL_SLAVE_EN = 1
4947 11:32:40.112331 NEW_RANK_MODE = 1
4948 11:32:40.115569 DLL_IDLE_MODE = 1
4949 11:32:40.118964 LP45_APHY_COMB_EN = 1
4950 11:32:40.119039 TX_ODT_DIS = 1
4951 11:32:40.122572 NEW_8X_MODE = 1
4952 11:32:40.125631 ===================================
4953 11:32:40.128956 ===================================
4954 11:32:40.132474 data_rate = 1866
4955 11:32:40.135614 CKR = 1
4956 11:32:40.139098 DQ_P2S_RATIO = 8
4957 11:32:40.142089 ===================================
4958 11:32:40.145577 CA_P2S_RATIO = 8
4959 11:32:40.145651 DQ_CA_OPEN = 0
4960 11:32:40.149090 DQ_SEMI_OPEN = 0
4961 11:32:40.152429 CA_SEMI_OPEN = 0
4962 11:32:40.155580 CA_FULL_RATE = 0
4963 11:32:40.158680 DQ_CKDIV4_EN = 1
4964 11:32:40.162197 CA_CKDIV4_EN = 1
4965 11:32:40.162268 CA_PREDIV_EN = 0
4966 11:32:40.165802 PH8_DLY = 0
4967 11:32:40.168718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4968 11:32:40.172312 DQ_AAMCK_DIV = 4
4969 11:32:40.175673 CA_AAMCK_DIV = 4
4970 11:32:40.178823 CA_ADMCK_DIV = 4
4971 11:32:40.178899 DQ_TRACK_CA_EN = 0
4972 11:32:40.182429 CA_PICK = 933
4973 11:32:40.185207 CA_MCKIO = 933
4974 11:32:40.188736 MCKIO_SEMI = 0
4975 11:32:40.192098 PLL_FREQ = 3732
4976 11:32:40.195468 DQ_UI_PI_RATIO = 32
4977 11:32:40.199153 CA_UI_PI_RATIO = 0
4978 11:32:40.202579 ===================================
4979 11:32:40.205360 ===================================
4980 11:32:40.205435 memory_type:LPDDR4
4981 11:32:40.208759 GP_NUM : 10
4982 11:32:40.211663 SRAM_EN : 1
4983 11:32:40.211737 MD32_EN : 0
4984 11:32:40.215160 ===================================
4985 11:32:40.218699 [ANA_INIT] >>>>>>>>>>>>>>
4986 11:32:40.222001 <<<<<< [CONFIGURE PHASE]: ANA_TX
4987 11:32:40.225366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4988 11:32:40.228292 ===================================
4989 11:32:40.232372 data_rate = 1866,PCW = 0X8f00
4990 11:32:40.235113 ===================================
4991 11:32:40.238137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4992 11:32:40.241602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 11:32:40.248678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 11:32:40.251797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4995 11:32:40.254833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4996 11:32:40.258218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4997 11:32:40.261367 [ANA_INIT] flow start
4998 11:32:40.264599 [ANA_INIT] PLL >>>>>>>>
4999 11:32:40.264672 [ANA_INIT] PLL <<<<<<<<
5000 11:32:40.267967 [ANA_INIT] MIDPI >>>>>>>>
5001 11:32:40.271560 [ANA_INIT] MIDPI <<<<<<<<
5002 11:32:40.274415 [ANA_INIT] DLL >>>>>>>>
5003 11:32:40.274489 [ANA_INIT] flow end
5004 11:32:40.277841 ============ LP4 DIFF to SE enter ============
5005 11:32:40.284456 ============ LP4 DIFF to SE exit ============
5006 11:32:40.284531 [ANA_INIT] <<<<<<<<<<<<<
5007 11:32:40.288105 [Flow] Enable top DCM control >>>>>
5008 11:32:40.291572 [Flow] Enable top DCM control <<<<<
5009 11:32:40.294639 Enable DLL master slave shuffle
5010 11:32:40.300952 ==============================================================
5011 11:32:40.301027 Gating Mode config
5012 11:32:40.307399 ==============================================================
5013 11:32:40.311152 Config description:
5014 11:32:40.321143 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5015 11:32:40.327827 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5016 11:32:40.330900 SELPH_MODE 0: By rank 1: By Phase
5017 11:32:40.337331 ==============================================================
5018 11:32:40.340468 GAT_TRACK_EN = 1
5019 11:32:40.343968 RX_GATING_MODE = 2
5020 11:32:40.344042 RX_GATING_TRACK_MODE = 2
5021 11:32:40.347331 SELPH_MODE = 1
5022 11:32:40.350512 PICG_EARLY_EN = 1
5023 11:32:40.353693 VALID_LAT_VALUE = 1
5024 11:32:40.360284 ==============================================================
5025 11:32:40.364181 Enter into Gating configuration >>>>
5026 11:32:40.367044 Exit from Gating configuration <<<<
5027 11:32:40.370412 Enter into DVFS_PRE_config >>>>>
5028 11:32:40.380629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5029 11:32:40.383901 Exit from DVFS_PRE_config <<<<<
5030 11:32:40.386946 Enter into PICG configuration >>>>
5031 11:32:40.390081 Exit from PICG configuration <<<<
5032 11:32:40.393780 [RX_INPUT] configuration >>>>>
5033 11:32:40.396660 [RX_INPUT] configuration <<<<<
5034 11:32:40.400031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5035 11:32:40.407224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5036 11:32:40.413609 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 11:32:40.419997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 11:32:40.426835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 11:32:40.429853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 11:32:40.436667 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5041 11:32:40.440298 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5042 11:32:40.442976 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5043 11:32:40.446700 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5044 11:32:40.449885 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5045 11:32:40.456727 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 11:32:40.459599 ===================================
5047 11:32:40.463257 LPDDR4 DRAM CONFIGURATION
5048 11:32:40.466646 ===================================
5049 11:32:40.466720 EX_ROW_EN[0] = 0x0
5050 11:32:40.469632 EX_ROW_EN[1] = 0x0
5051 11:32:40.469706 LP4Y_EN = 0x0
5052 11:32:40.473256 WORK_FSP = 0x0
5053 11:32:40.473331 WL = 0x3
5054 11:32:40.476478 RL = 0x3
5055 11:32:40.476552 BL = 0x2
5056 11:32:40.479838 RPST = 0x0
5057 11:32:40.479912 RD_PRE = 0x0
5058 11:32:40.482872 WR_PRE = 0x1
5059 11:32:40.482946 WR_PST = 0x0
5060 11:32:40.486302 DBI_WR = 0x0
5061 11:32:40.486376 DBI_RD = 0x0
5062 11:32:40.489799 OTF = 0x1
5063 11:32:40.492707 ===================================
5064 11:32:40.496335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5065 11:32:40.499703 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5066 11:32:40.506049 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5067 11:32:40.509165 ===================================
5068 11:32:40.512968 LPDDR4 DRAM CONFIGURATION
5069 11:32:40.515984 ===================================
5070 11:32:40.516063 EX_ROW_EN[0] = 0x10
5071 11:32:40.519262 EX_ROW_EN[1] = 0x0
5072 11:32:40.519360 LP4Y_EN = 0x0
5073 11:32:40.523032 WORK_FSP = 0x0
5074 11:32:40.523107 WL = 0x3
5075 11:32:40.526078 RL = 0x3
5076 11:32:40.526207 BL = 0x2
5077 11:32:40.529312 RPST = 0x0
5078 11:32:40.529386 RD_PRE = 0x0
5079 11:32:40.533058 WR_PRE = 0x1
5080 11:32:40.533132 WR_PST = 0x0
5081 11:32:40.535546 DBI_WR = 0x0
5082 11:32:40.535620 DBI_RD = 0x0
5083 11:32:40.539097 OTF = 0x1
5084 11:32:40.542765 ===================================
5085 11:32:40.549473 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5086 11:32:40.552160 nWR fixed to 30
5087 11:32:40.555595 [ModeRegInit_LP4] CH0 RK0
5088 11:32:40.555668 [ModeRegInit_LP4] CH0 RK1
5089 11:32:40.559305 [ModeRegInit_LP4] CH1 RK0
5090 11:32:40.562441 [ModeRegInit_LP4] CH1 RK1
5091 11:32:40.562515 match AC timing 9
5092 11:32:40.568652 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5093 11:32:40.572439 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5094 11:32:40.575555 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5095 11:32:40.581940 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5096 11:32:40.585187 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5097 11:32:40.585262 ==
5098 11:32:40.588512 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 11:32:40.592192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 11:32:40.592267 ==
5101 11:32:40.598577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 11:32:40.605020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5103 11:32:40.608592 [CA 0] Center 38 (8~69) winsize 62
5104 11:32:40.611601 [CA 1] Center 38 (8~69) winsize 62
5105 11:32:40.615450 [CA 2] Center 35 (5~66) winsize 62
5106 11:32:40.618217 [CA 3] Center 35 (5~66) winsize 62
5107 11:32:40.621452 [CA 4] Center 34 (4~65) winsize 62
5108 11:32:40.625086 [CA 5] Center 34 (4~64) winsize 61
5109 11:32:40.625160
5110 11:32:40.628156 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5111 11:32:40.628231
5112 11:32:40.631495 [CATrainingPosCal] consider 1 rank data
5113 11:32:40.634757 u2DelayCellTimex100 = 270/100 ps
5114 11:32:40.638698 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5115 11:32:40.642024 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5116 11:32:40.644831 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5117 11:32:40.648434 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5118 11:32:40.651634 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5119 11:32:40.658650 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 11:32:40.658747
5121 11:32:40.661751 CA PerBit enable=1, Macro0, CA PI delay=34
5122 11:32:40.661825
5123 11:32:40.665289 [CBTSetCACLKResult] CA Dly = 34
5124 11:32:40.665363 CS Dly: 7 (0~38)
5125 11:32:40.665423 ==
5126 11:32:40.668367 Dram Type= 6, Freq= 0, CH_0, rank 1
5127 11:32:40.674849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 11:32:40.674925 ==
5129 11:32:40.677970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5130 11:32:40.685076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5131 11:32:40.687972 [CA 0] Center 38 (8~69) winsize 62
5132 11:32:40.691796 [CA 1] Center 38 (8~69) winsize 62
5133 11:32:40.694630 [CA 2] Center 35 (5~66) winsize 62
5134 11:32:40.697771 [CA 3] Center 35 (5~66) winsize 62
5135 11:32:40.701147 [CA 4] Center 34 (4~65) winsize 62
5136 11:32:40.704583 [CA 5] Center 33 (3~64) winsize 62
5137 11:32:40.704659
5138 11:32:40.708042 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5139 11:32:40.708117
5140 11:32:40.711483 [CATrainingPosCal] consider 2 rank data
5141 11:32:40.714806 u2DelayCellTimex100 = 270/100 ps
5142 11:32:40.717830 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5143 11:32:40.721448 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5144 11:32:40.724647 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5145 11:32:40.731649 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5146 11:32:40.734394 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5147 11:32:40.737887 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5148 11:32:40.737962
5149 11:32:40.741571 CA PerBit enable=1, Macro0, CA PI delay=34
5150 11:32:40.741646
5151 11:32:40.744217 [CBTSetCACLKResult] CA Dly = 34
5152 11:32:40.744306 CS Dly: 7 (0~39)
5153 11:32:40.744363
5154 11:32:40.747699 ----->DramcWriteLeveling(PI) begin...
5155 11:32:40.747775 ==
5156 11:32:40.751244 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 11:32:40.757564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 11:32:40.757639 ==
5159 11:32:40.760868 Write leveling (Byte 0): 31 => 31
5160 11:32:40.764174 Write leveling (Byte 1): 28 => 28
5161 11:32:40.768145 DramcWriteLeveling(PI) end<-----
5162 11:32:40.768220
5163 11:32:40.768277 ==
5164 11:32:40.771271 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 11:32:40.774375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 11:32:40.774450 ==
5167 11:32:40.777237 [Gating] SW mode calibration
5168 11:32:40.784500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5169 11:32:40.787262 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5170 11:32:40.793829 0 14 0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
5171 11:32:40.797057 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5172 11:32:40.800471 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 11:32:40.806933 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 11:32:40.810453 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 11:32:40.813978 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 11:32:40.820716 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:32:40.824216 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5178 11:32:40.827158 0 15 0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
5179 11:32:40.833491 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5180 11:32:40.836869 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 11:32:40.840601 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 11:32:40.846958 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 11:32:40.850483 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 11:32:40.854034 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:32:40.860055 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5186 11:32:40.863714 1 0 0 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
5187 11:32:40.866915 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5188 11:32:40.873362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 11:32:40.876670 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 11:32:40.880061 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 11:32:40.886743 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:32:40.890104 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:32:40.893650 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:32:40.900486 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5195 11:32:40.903333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 11:32:40.906724 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:32:40.913472 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:32:40.916917 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:32:40.920346 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:32:40.926872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:32:40.929973 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:32:40.933214 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:32:40.939430 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:32:40.942828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:32:40.946598 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:32:40.952921 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:32:40.956792 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:32:40.959417 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:32:40.966129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 11:32:40.969352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5211 11:32:40.972670 Total UI for P1: 0, mck2ui 16
5212 11:32:40.976236 best dqsien dly found for B0: ( 1, 2, 28)
5213 11:32:40.979826 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5214 11:32:40.982732 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 11:32:40.986034 Total UI for P1: 0, mck2ui 16
5216 11:32:40.989713 best dqsien dly found for B1: ( 1, 3, 2)
5217 11:32:40.992681 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5218 11:32:40.999092 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5219 11:32:40.999166
5220 11:32:41.002570 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5221 11:32:41.006071 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5222 11:32:41.009388 [Gating] SW calibration Done
5223 11:32:41.009462 ==
5224 11:32:41.012425 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 11:32:41.015820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 11:32:41.015895 ==
5227 11:32:41.019168 RX Vref Scan: 0
5228 11:32:41.019242
5229 11:32:41.019299 RX Vref 0 -> 0, step: 1
5230 11:32:41.019354
5231 11:32:41.022174 RX Delay -80 -> 252, step: 8
5232 11:32:41.025636 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5233 11:32:41.029026 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5234 11:32:41.035912 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5235 11:32:41.039208 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5236 11:32:41.042269 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5237 11:32:41.045912 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5238 11:32:41.049135 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5239 11:32:41.052573 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5240 11:32:41.058657 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5241 11:32:41.061998 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5242 11:32:41.065866 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5243 11:32:41.068716 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5244 11:32:41.075579 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5245 11:32:41.078969 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5246 11:32:41.082247 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5247 11:32:41.085928 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5248 11:32:41.086025 ==
5249 11:32:41.088812 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 11:32:41.092029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 11:32:41.095426 ==
5252 11:32:41.095501 DQS Delay:
5253 11:32:41.095558 DQS0 = 0, DQS1 = 0
5254 11:32:41.098952 DQM Delay:
5255 11:32:41.099027 DQM0 = 94, DQM1 = 82
5256 11:32:41.102436 DQ Delay:
5257 11:32:41.105423 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5258 11:32:41.108449 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5259 11:32:41.111770 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5260 11:32:41.115346 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5261 11:32:41.115420
5262 11:32:41.115477
5263 11:32:41.115530 ==
5264 11:32:41.118281 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 11:32:41.121480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 11:32:41.121555 ==
5267 11:32:41.121613
5268 11:32:41.121666
5269 11:32:41.125515 TX Vref Scan disable
5270 11:32:41.125589 == TX Byte 0 ==
5271 11:32:41.132026 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5272 11:32:41.134835 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5273 11:32:41.134909 == TX Byte 1 ==
5274 11:32:41.141618 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5275 11:32:41.145146 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5276 11:32:41.145221 ==
5277 11:32:41.148316 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 11:32:41.151391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:32:41.151467 ==
5280 11:32:41.151525
5281 11:32:41.151578
5282 11:32:41.154645 TX Vref Scan disable
5283 11:32:41.158265 == TX Byte 0 ==
5284 11:32:41.161234 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5285 11:32:41.164588 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5286 11:32:41.168215 == TX Byte 1 ==
5287 11:32:41.171749 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5288 11:32:41.174846 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5289 11:32:41.174922
5290 11:32:41.178363 [DATLAT]
5291 11:32:41.178442 Freq=933, CH0 RK0
5292 11:32:41.178506
5293 11:32:41.181544 DATLAT Default: 0xd
5294 11:32:41.181643 0, 0xFFFF, sum = 0
5295 11:32:41.184390 1, 0xFFFF, sum = 0
5296 11:32:41.184467 2, 0xFFFF, sum = 0
5297 11:32:41.188085 3, 0xFFFF, sum = 0
5298 11:32:41.188161 4, 0xFFFF, sum = 0
5299 11:32:41.191354 5, 0xFFFF, sum = 0
5300 11:32:41.191432 6, 0xFFFF, sum = 0
5301 11:32:41.194820 7, 0xFFFF, sum = 0
5302 11:32:41.197723 8, 0xFFFF, sum = 0
5303 11:32:41.197799 9, 0xFFFF, sum = 0
5304 11:32:41.201320 10, 0x0, sum = 1
5305 11:32:41.201396 11, 0x0, sum = 2
5306 11:32:41.201455 12, 0x0, sum = 3
5307 11:32:41.204680 13, 0x0, sum = 4
5308 11:32:41.204756 best_step = 11
5309 11:32:41.204814
5310 11:32:41.204868 ==
5311 11:32:41.208283 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 11:32:41.214884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 11:32:41.214961 ==
5314 11:32:41.215019 RX Vref Scan: 1
5315 11:32:41.215073
5316 11:32:41.217875 RX Vref 0 -> 0, step: 1
5317 11:32:41.217950
5318 11:32:41.220894 RX Delay -69 -> 252, step: 4
5319 11:32:41.220969
5320 11:32:41.224739 Set Vref, RX VrefLevel [Byte0]: 61
5321 11:32:41.227750 [Byte1]: 53
5322 11:32:41.227826
5323 11:32:41.231028 Final RX Vref Byte 0 = 61 to rank0
5324 11:32:41.234403 Final RX Vref Byte 1 = 53 to rank0
5325 11:32:41.237554 Final RX Vref Byte 0 = 61 to rank1
5326 11:32:41.240818 Final RX Vref Byte 1 = 53 to rank1==
5327 11:32:41.244457 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 11:32:41.247489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 11:32:41.251386 ==
5330 11:32:41.251461 DQS Delay:
5331 11:32:41.251519 DQS0 = 0, DQS1 = 0
5332 11:32:41.254355 DQM Delay:
5333 11:32:41.254430 DQM0 = 95, DQM1 = 83
5334 11:32:41.254489 DQ Delay:
5335 11:32:41.257853 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5336 11:32:41.260944 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5337 11:32:41.264122 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =78
5338 11:32:41.267684 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5339 11:32:41.267760
5340 11:32:41.271173
5341 11:32:41.277843 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5342 11:32:41.280876 CH0 RK0: MR19=505, MR18=1514
5343 11:32:41.287715 CH0_RK0: MR19=0x505, MR18=0x1514, DQSOSC=415, MR23=63, INC=62, DEC=41
5344 11:32:41.287802
5345 11:32:41.290943 ----->DramcWriteLeveling(PI) begin...
5346 11:32:41.291038 ==
5347 11:32:41.294024 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 11:32:41.297456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:32:41.297531 ==
5350 11:32:41.300963 Write leveling (Byte 0): 31 => 31
5351 11:32:41.304178 Write leveling (Byte 1): 29 => 29
5352 11:32:41.307054 DramcWriteLeveling(PI) end<-----
5353 11:32:41.307129
5354 11:32:41.307186 ==
5355 11:32:41.311674 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 11:32:41.314394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 11:32:41.314469 ==
5358 11:32:41.317463 [Gating] SW mode calibration
5359 11:32:41.323757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 11:32:41.330648 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 11:32:41.333684 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5362 11:32:41.336956 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 11:32:41.343923 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 11:32:41.347479 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 11:32:41.350797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 11:32:41.357279 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:32:41.360428 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5368 11:32:41.363698 0 14 28 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)
5369 11:32:41.370246 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5370 11:32:41.373421 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 11:32:41.376663 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 11:32:41.383418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 11:32:41.386769 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 11:32:41.390510 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:32:41.396872 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:32:41.399993 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5377 11:32:41.403476 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5378 11:32:41.410064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:32:41.413367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 11:32:41.416526 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 11:32:41.423420 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 11:32:41.426435 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:32:41.429851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:32:41.436293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5385 11:32:41.440098 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5386 11:32:41.442959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5387 11:32:41.449482 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:32:41.453028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:32:41.456173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:32:41.463158 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:32:41.466212 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:32:41.469417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:32:41.475676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:32:41.479010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:32:41.482388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:32:41.489341 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:32:41.492547 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:32:41.496017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:32:41.502359 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5400 11:32:41.506033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5401 11:32:41.509532 Total UI for P1: 0, mck2ui 16
5402 11:32:41.512310 best dqsien dly found for B0: ( 1, 2, 24)
5403 11:32:41.515984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 11:32:41.522023 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 11:32:41.522124 Total UI for P1: 0, mck2ui 16
5406 11:32:41.528928 best dqsien dly found for B1: ( 1, 3, 0)
5407 11:32:41.532277 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5408 11:32:41.535613 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5409 11:32:41.535687
5410 11:32:41.539218 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5411 11:32:41.542259 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5412 11:32:41.545691 [Gating] SW calibration Done
5413 11:32:41.545766 ==
5414 11:32:41.548751 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 11:32:41.551803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 11:32:41.551878 ==
5417 11:32:41.555119 RX Vref Scan: 0
5418 11:32:41.555193
5419 11:32:41.555252 RX Vref 0 -> 0, step: 1
5420 11:32:41.555306
5421 11:32:41.558663 RX Delay -80 -> 252, step: 8
5422 11:32:41.561711 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5423 11:32:41.568681 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5424 11:32:41.571915 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5425 11:32:41.575151 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5426 11:32:41.578489 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5427 11:32:41.581471 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5428 11:32:41.585104 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5429 11:32:41.591644 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5430 11:32:41.595071 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5431 11:32:41.598430 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5432 11:32:41.601542 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5433 11:32:41.605181 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5434 11:32:41.612473 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5435 11:32:41.614842 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5436 11:32:41.618404 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5437 11:32:41.621392 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5438 11:32:41.621465 ==
5439 11:32:41.624538 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:32:41.631212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:32:41.631386 ==
5442 11:32:41.631495 DQS Delay:
5443 11:32:41.631556 DQS0 = 0, DQS1 = 0
5444 11:32:41.634575 DQM Delay:
5445 11:32:41.634649 DQM0 = 92, DQM1 = 84
5446 11:32:41.637967 DQ Delay:
5447 11:32:41.641210 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5448 11:32:41.644711 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5449 11:32:41.648150 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =79
5450 11:32:41.651786 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5451 11:32:41.651860
5452 11:32:41.651918
5453 11:32:41.651971 ==
5454 11:32:41.654984 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:32:41.657977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:32:41.658051 ==
5457 11:32:41.658132
5458 11:32:41.658199
5459 11:32:41.661666 TX Vref Scan disable
5460 11:32:41.661740 == TX Byte 0 ==
5461 11:32:41.667839 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5462 11:32:41.671280 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5463 11:32:41.674223 == TX Byte 1 ==
5464 11:32:41.677391 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 11:32:41.681075 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 11:32:41.681151 ==
5467 11:32:41.684661 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 11:32:41.687749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 11:32:41.690979 ==
5470 11:32:41.691054
5471 11:32:41.691112
5472 11:32:41.691180 TX Vref Scan disable
5473 11:32:41.694439 == TX Byte 0 ==
5474 11:32:41.697914 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 11:32:41.704382 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 11:32:41.704480 == TX Byte 1 ==
5477 11:32:41.707438 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 11:32:41.714137 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 11:32:41.714225
5480 11:32:41.714283 [DATLAT]
5481 11:32:41.714337 Freq=933, CH0 RK1
5482 11:32:41.714389
5483 11:32:41.717820 DATLAT Default: 0xb
5484 11:32:41.717895 0, 0xFFFF, sum = 0
5485 11:32:41.720862 1, 0xFFFF, sum = 0
5486 11:32:41.720939 2, 0xFFFF, sum = 0
5487 11:32:41.724174 3, 0xFFFF, sum = 0
5488 11:32:41.724250 4, 0xFFFF, sum = 0
5489 11:32:41.727564 5, 0xFFFF, sum = 0
5490 11:32:41.731160 6, 0xFFFF, sum = 0
5491 11:32:41.731253 7, 0xFFFF, sum = 0
5492 11:32:41.734425 8, 0xFFFF, sum = 0
5493 11:32:41.734502 9, 0xFFFF, sum = 0
5494 11:32:41.737638 10, 0x0, sum = 1
5495 11:32:41.737714 11, 0x0, sum = 2
5496 11:32:41.737774 12, 0x0, sum = 3
5497 11:32:41.740806 13, 0x0, sum = 4
5498 11:32:41.740883 best_step = 11
5499 11:32:41.740941
5500 11:32:41.744394 ==
5501 11:32:41.744473 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 11:32:41.750718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 11:32:41.750794 ==
5504 11:32:41.750852 RX Vref Scan: 0
5505 11:32:41.750906
5506 11:32:41.754026 RX Vref 0 -> 0, step: 1
5507 11:32:41.754124
5508 11:32:41.757498 RX Delay -77 -> 252, step: 4
5509 11:32:41.761197 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5510 11:32:41.767595 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5511 11:32:41.770882 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5512 11:32:41.774401 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5513 11:32:41.777321 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5514 11:32:41.780808 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5515 11:32:41.784241 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5516 11:32:41.790647 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5517 11:32:41.794067 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5518 11:32:41.797358 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5519 11:32:41.800973 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5520 11:32:41.804017 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5521 11:32:41.811072 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5522 11:32:41.814072 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5523 11:32:41.817331 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5524 11:32:41.820741 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5525 11:32:41.820816 ==
5526 11:32:41.823965 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 11:32:41.830427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 11:32:41.830503 ==
5529 11:32:41.830572 DQS Delay:
5530 11:32:41.830656 DQS0 = 0, DQS1 = 0
5531 11:32:41.833819 DQM Delay:
5532 11:32:41.833893 DQM0 = 93, DQM1 = 84
5533 11:32:41.836998 DQ Delay:
5534 11:32:41.840752 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5535 11:32:41.843911 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =104
5536 11:32:41.843986 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5537 11:32:41.850385 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
5538 11:32:41.850460
5539 11:32:41.850517
5540 11:32:41.856882 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5541 11:32:41.860385 CH0 RK1: MR19=505, MR18=3314
5542 11:32:41.867012 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5543 11:32:41.870309 [RxdqsGatingPostProcess] freq 933
5544 11:32:41.873699 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 11:32:41.877024 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 11:32:41.880645 best DQS1 dly(2T, 0.5T) = (0, 11)
5547 11:32:41.883489 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 11:32:41.887303 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5549 11:32:41.890797 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 11:32:41.893458 best DQS1 dly(2T, 0.5T) = (0, 11)
5551 11:32:41.896869 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 11:32:41.900223 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5553 11:32:41.903250 Pre-setting of DQS Precalculation
5554 11:32:41.906836 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 11:32:41.906911 ==
5556 11:32:41.910277 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 11:32:41.916807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 11:32:41.916883 ==
5559 11:32:41.920504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 11:32:41.926580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5561 11:32:41.930284 [CA 0] Center 36 (7~66) winsize 60
5562 11:32:41.933436 [CA 1] Center 37 (7~67) winsize 61
5563 11:32:41.936900 [CA 2] Center 34 (5~64) winsize 60
5564 11:32:41.940283 [CA 3] Center 34 (4~64) winsize 61
5565 11:32:41.943245 [CA 4] Center 34 (5~64) winsize 60
5566 11:32:41.946935 [CA 5] Center 34 (4~64) winsize 61
5567 11:32:41.947009
5568 11:32:41.950000 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5569 11:32:41.950074
5570 11:32:41.953518 [CATrainingPosCal] consider 1 rank data
5571 11:32:41.956690 u2DelayCellTimex100 = 270/100 ps
5572 11:32:41.960173 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5573 11:32:41.962950 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5574 11:32:41.969994 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5575 11:32:41.973668 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5576 11:32:41.976283 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5577 11:32:41.980004 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5578 11:32:41.980078
5579 11:32:41.982861 CA PerBit enable=1, Macro0, CA PI delay=34
5580 11:32:41.982935
5581 11:32:41.986268 [CBTSetCACLKResult] CA Dly = 34
5582 11:32:41.986343 CS Dly: 6 (0~37)
5583 11:32:41.986400 ==
5584 11:32:41.989958 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 11:32:41.996595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 11:32:41.996669 ==
5587 11:32:41.999686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 11:32:42.006470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5589 11:32:42.009607 [CA 0] Center 37 (7~68) winsize 62
5590 11:32:42.013026 [CA 1] Center 37 (7~68) winsize 62
5591 11:32:42.016417 [CA 2] Center 35 (5~65) winsize 61
5592 11:32:42.020021 [CA 3] Center 34 (4~64) winsize 61
5593 11:32:42.022819 [CA 4] Center 34 (4~64) winsize 61
5594 11:32:42.026382 [CA 5] Center 33 (3~64) winsize 62
5595 11:32:42.026456
5596 11:32:42.030244 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5597 11:32:42.030318
5598 11:32:42.032729 [CATrainingPosCal] consider 2 rank data
5599 11:32:42.036482 u2DelayCellTimex100 = 270/100 ps
5600 11:32:42.039895 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5601 11:32:42.046136 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5602 11:32:42.049221 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5603 11:32:42.053218 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5604 11:32:42.056353 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5605 11:32:42.059410 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5606 11:32:42.059486
5607 11:32:42.063047 CA PerBit enable=1, Macro0, CA PI delay=34
5608 11:32:42.063122
5609 11:32:42.066455 [CBTSetCACLKResult] CA Dly = 34
5610 11:32:42.066530 CS Dly: 7 (0~39)
5611 11:32:42.069493
5612 11:32:42.072863 ----->DramcWriteLeveling(PI) begin...
5613 11:32:42.072939 ==
5614 11:32:42.075742 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 11:32:42.079237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 11:32:42.079313 ==
5617 11:32:42.082422 Write leveling (Byte 0): 25 => 25
5618 11:32:42.085976 Write leveling (Byte 1): 26 => 26
5619 11:32:42.089103 DramcWriteLeveling(PI) end<-----
5620 11:32:42.089179
5621 11:32:42.089237 ==
5622 11:32:42.092481 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 11:32:42.096121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 11:32:42.096197 ==
5625 11:32:42.099774 [Gating] SW mode calibration
5626 11:32:42.105887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 11:32:42.112862 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 11:32:42.116468 0 14 0 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 1)
5629 11:32:42.119272 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 11:32:42.126214 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 11:32:42.129365 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 11:32:42.132274 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:32:42.139137 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:32:42.142666 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5635 11:32:42.145720 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (0 0)
5636 11:32:42.152371 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5637 11:32:42.155764 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 11:32:42.159380 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 11:32:42.165690 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 11:32:42.169062 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:32:42.172613 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:32:42.175602 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:32:42.182406 0 15 28 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
5644 11:32:42.185972 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5645 11:32:42.188715 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 11:32:42.195732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 11:32:42.198991 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 11:32:42.202789 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:32:42.208694 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:32:42.212637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:32:42.215428 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:32:42.222228 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:32:42.225116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:32:42.228563 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:32:42.235093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:32:42.238692 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:32:42.241705 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:32:42.248875 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:32:42.251819 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:32:42.254987 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:32:42.262007 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:32:42.264961 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:32:42.268502 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:32:42.274916 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:32:42.278386 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:32:42.281393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:32:42.288538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:32:42.291508 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5669 11:32:42.294788 Total UI for P1: 0, mck2ui 16
5670 11:32:42.297979 best dqsien dly found for B0: ( 1, 2, 30)
5671 11:32:42.301501 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 11:32:42.304500 Total UI for P1: 0, mck2ui 16
5673 11:32:42.307992 best dqsien dly found for B1: ( 1, 3, 0)
5674 11:32:42.311177 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5675 11:32:42.314780 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5676 11:32:42.314859
5677 11:32:42.321584 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5678 11:32:42.324350 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5679 11:32:42.324450 [Gating] SW calibration Done
5680 11:32:42.327777 ==
5681 11:32:42.327853 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 11:32:42.334094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 11:32:42.334179 ==
5684 11:32:42.334238 RX Vref Scan: 0
5685 11:32:42.334292
5686 11:32:42.337707 RX Vref 0 -> 0, step: 1
5687 11:32:42.337782
5688 11:32:42.341352 RX Delay -80 -> 252, step: 8
5689 11:32:42.344618 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5690 11:32:42.347565 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5691 11:32:42.350993 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5692 11:32:42.357742 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5693 11:32:42.360700 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5694 11:32:42.364256 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5695 11:32:42.367890 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5696 11:32:42.371396 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5697 11:32:42.374264 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5698 11:32:42.381028 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5699 11:32:42.384102 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5700 11:32:42.387590 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5701 11:32:42.390849 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5702 11:32:42.394003 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5703 11:32:42.400791 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5704 11:32:42.404090 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5705 11:32:42.404166 ==
5706 11:32:42.407438 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 11:32:42.410490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 11:32:42.410565 ==
5709 11:32:42.410622 DQS Delay:
5710 11:32:42.414015 DQS0 = 0, DQS1 = 0
5711 11:32:42.414090 DQM Delay:
5712 11:32:42.417092 DQM0 = 94, DQM1 = 89
5713 11:32:42.417167 DQ Delay:
5714 11:32:42.420605 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5715 11:32:42.424052 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5716 11:32:42.427196 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5717 11:32:42.430375 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5718 11:32:42.430450
5719 11:32:42.430508
5720 11:32:42.430562 ==
5721 11:32:42.434285 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:32:42.440451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:32:42.440527 ==
5724 11:32:42.440584
5725 11:32:42.440637
5726 11:32:42.440688 TX Vref Scan disable
5727 11:32:42.443718 == TX Byte 0 ==
5728 11:32:42.447072 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5729 11:32:42.453866 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5730 11:32:42.453942 == TX Byte 1 ==
5731 11:32:42.457204 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 11:32:42.463392 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 11:32:42.463467 ==
5734 11:32:42.466911 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 11:32:42.470483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 11:32:42.470548 ==
5737 11:32:42.470601
5738 11:32:42.470651
5739 11:32:42.473933 TX Vref Scan disable
5740 11:32:42.474007 == TX Byte 0 ==
5741 11:32:42.480221 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5742 11:32:42.483822 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5743 11:32:42.483897 == TX Byte 1 ==
5744 11:32:42.489797 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5745 11:32:42.493296 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5746 11:32:42.493371
5747 11:32:42.493429 [DATLAT]
5748 11:32:42.496862 Freq=933, CH1 RK0
5749 11:32:42.496938
5750 11:32:42.496996 DATLAT Default: 0xd
5751 11:32:42.500010 0, 0xFFFF, sum = 0
5752 11:32:42.500087 1, 0xFFFF, sum = 0
5753 11:32:42.503315 2, 0xFFFF, sum = 0
5754 11:32:42.503391 3, 0xFFFF, sum = 0
5755 11:32:42.506694 4, 0xFFFF, sum = 0
5756 11:32:42.509786 5, 0xFFFF, sum = 0
5757 11:32:42.509862 6, 0xFFFF, sum = 0
5758 11:32:42.513032 7, 0xFFFF, sum = 0
5759 11:32:42.513109 8, 0xFFFF, sum = 0
5760 11:32:42.516520 9, 0xFFFF, sum = 0
5761 11:32:42.516596 10, 0x0, sum = 1
5762 11:32:42.520247 11, 0x0, sum = 2
5763 11:32:42.520323 12, 0x0, sum = 3
5764 11:32:42.520383 13, 0x0, sum = 4
5765 11:32:42.523793 best_step = 11
5766 11:32:42.523868
5767 11:32:42.523926 ==
5768 11:32:42.526296 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 11:32:42.529826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 11:32:42.529901 ==
5771 11:32:42.533069 RX Vref Scan: 1
5772 11:32:42.533143
5773 11:32:42.536728 RX Vref 0 -> 0, step: 1
5774 11:32:42.536803
5775 11:32:42.536862 RX Delay -61 -> 252, step: 4
5776 11:32:42.536917
5777 11:32:42.539959 Set Vref, RX VrefLevel [Byte0]: 56
5778 11:32:42.542925 [Byte1]: 53
5779 11:32:42.547773
5780 11:32:42.547847 Final RX Vref Byte 0 = 56 to rank0
5781 11:32:42.550709 Final RX Vref Byte 1 = 53 to rank0
5782 11:32:42.554350 Final RX Vref Byte 0 = 56 to rank1
5783 11:32:42.557543 Final RX Vref Byte 1 = 53 to rank1==
5784 11:32:42.560926 Dram Type= 6, Freq= 0, CH_1, rank 0
5785 11:32:42.567610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 11:32:42.567686 ==
5787 11:32:42.567744 DQS Delay:
5788 11:32:42.567798 DQS0 = 0, DQS1 = 0
5789 11:32:42.571331 DQM Delay:
5790 11:32:42.571406 DQM0 = 94, DQM1 = 87
5791 11:32:42.574255 DQ Delay:
5792 11:32:42.577714 DQ0 =100, DQ1 =90, DQ2 =82, DQ3 =90
5793 11:32:42.580651 DQ4 =92, DQ5 =104, DQ6 =106, DQ7 =92
5794 11:32:42.584187 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5795 11:32:42.587681 DQ12 =96, DQ13 =92, DQ14 =92, DQ15 =94
5796 11:32:42.587757
5797 11:32:42.587815
5798 11:32:42.594002 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5799 11:32:42.597352 CH1 RK0: MR19=505, MR18=40C
5800 11:32:42.603707 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5801 11:32:42.603783
5802 11:32:42.607135 ----->DramcWriteLeveling(PI) begin...
5803 11:32:42.607211 ==
5804 11:32:42.611145 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 11:32:42.613725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 11:32:42.613798 ==
5807 11:32:42.617670 Write leveling (Byte 0): 27 => 27
5808 11:32:42.620504 Write leveling (Byte 1): 27 => 27
5809 11:32:42.623715 DramcWriteLeveling(PI) end<-----
5810 11:32:42.623782
5811 11:32:42.623838 ==
5812 11:32:42.627186 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 11:32:42.631104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 11:32:42.631170 ==
5815 11:32:42.634012 [Gating] SW mode calibration
5816 11:32:42.640398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5817 11:32:42.647473 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5818 11:32:42.650142 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 11:32:42.657014 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 11:32:42.660553 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 11:32:42.663463 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:32:42.670479 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:32:42.673538 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5824 11:32:42.676701 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5825 11:32:42.683208 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5826 11:32:42.686491 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5827 11:32:42.689989 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 11:32:42.696920 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 11:32:42.699635 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:32:42.703632 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:32:42.709644 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:32:42.713184 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (1 1)
5833 11:32:42.716593 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5834 11:32:42.719937 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 11:32:42.726301 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 11:32:42.729844 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:32:42.733114 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:32:42.739679 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:32:42.743069 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:32:42.746368 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5841 11:32:42.752902 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5842 11:32:42.756390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:32:42.759630 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:32:42.766415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:32:42.769411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:32:42.772818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:32:42.780053 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:32:42.782999 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:32:42.786092 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:32:42.793082 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:32:42.796276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:32:42.799222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:32:42.806057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:32:42.809245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:32:42.812835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:32:42.819763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:32:42.822702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5858 11:32:42.825896 Total UI for P1: 0, mck2ui 16
5859 11:32:42.829172 best dqsien dly found for B0: ( 1, 2, 26)
5860 11:32:42.832685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 11:32:42.835759 Total UI for P1: 0, mck2ui 16
5862 11:32:42.839151 best dqsien dly found for B1: ( 1, 2, 28)
5863 11:32:42.842656 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5864 11:32:42.845879 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5865 11:32:42.845955
5866 11:32:42.852525 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5867 11:32:42.855712 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5868 11:32:42.855788 [Gating] SW calibration Done
5869 11:32:42.859177 ==
5870 11:32:42.862133 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 11:32:42.865487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 11:32:42.865563 ==
5873 11:32:42.865622 RX Vref Scan: 0
5874 11:32:42.865676
5875 11:32:42.868795 RX Vref 0 -> 0, step: 1
5876 11:32:42.868870
5877 11:32:42.872357 RX Delay -80 -> 252, step: 8
5878 11:32:42.875811 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5879 11:32:42.878573 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5880 11:32:42.882053 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5881 11:32:42.888963 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5882 11:32:42.892018 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5883 11:32:42.895498 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5884 11:32:42.898721 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5885 11:32:42.902273 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5886 11:32:42.908539 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5887 11:32:42.911994 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5888 11:32:42.915422 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5889 11:32:42.918640 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5890 11:32:42.922080 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5891 11:32:42.928567 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5892 11:32:42.931583 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5893 11:32:42.935050 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5894 11:32:42.935125 ==
5895 11:32:42.938562 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 11:32:42.941819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 11:32:42.941895 ==
5898 11:32:42.945233 DQS Delay:
5899 11:32:42.945308 DQS0 = 0, DQS1 = 0
5900 11:32:42.945366 DQM Delay:
5901 11:32:42.948552 DQM0 = 93, DQM1 = 88
5902 11:32:42.948628 DQ Delay:
5903 11:32:42.951680 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5904 11:32:42.955257 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5905 11:32:42.958366 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5906 11:32:42.961724 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5907 11:32:42.961799
5908 11:32:42.961857
5909 11:32:42.964642 ==
5910 11:32:42.968205 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:32:42.971432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:32:42.971508 ==
5913 11:32:42.971565
5914 11:32:42.971618
5915 11:32:42.974513 TX Vref Scan disable
5916 11:32:42.974588 == TX Byte 0 ==
5917 11:32:42.978065 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5918 11:32:42.984474 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5919 11:32:42.984549 == TX Byte 1 ==
5920 11:32:42.987731 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5921 11:32:42.994864 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5922 11:32:42.994940 ==
5923 11:32:42.997552 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:32:43.001280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:32:43.001356 ==
5926 11:32:43.001415
5927 11:32:43.001469
5928 11:32:43.004075 TX Vref Scan disable
5929 11:32:43.007690 == TX Byte 0 ==
5930 11:32:43.011119 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 11:32:43.014560 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 11:32:43.017935 == TX Byte 1 ==
5933 11:32:43.020776 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5934 11:32:43.024197 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5935 11:32:43.024273
5936 11:32:43.027989 [DATLAT]
5937 11:32:43.028064 Freq=933, CH1 RK1
5938 11:32:43.028122
5939 11:32:43.030981 DATLAT Default: 0xb
5940 11:32:43.031056 0, 0xFFFF, sum = 0
5941 11:32:43.034584 1, 0xFFFF, sum = 0
5942 11:32:43.034661 2, 0xFFFF, sum = 0
5943 11:32:43.037525 3, 0xFFFF, sum = 0
5944 11:32:43.037601 4, 0xFFFF, sum = 0
5945 11:32:43.040838 5, 0xFFFF, sum = 0
5946 11:32:43.040915 6, 0xFFFF, sum = 0
5947 11:32:43.044476 7, 0xFFFF, sum = 0
5948 11:32:43.044553 8, 0xFFFF, sum = 0
5949 11:32:43.047887 9, 0xFFFF, sum = 0
5950 11:32:43.047963 10, 0x0, sum = 1
5951 11:32:43.050944 11, 0x0, sum = 2
5952 11:32:43.051020 12, 0x0, sum = 3
5953 11:32:43.054453 13, 0x0, sum = 4
5954 11:32:43.054529 best_step = 11
5955 11:32:43.054587
5956 11:32:43.054640 ==
5957 11:32:43.057381 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 11:32:43.064148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 11:32:43.064224 ==
5960 11:32:43.064282 RX Vref Scan: 0
5961 11:32:43.064336
5962 11:32:43.067261 RX Vref 0 -> 0, step: 1
5963 11:32:43.067336
5964 11:32:43.070848 RX Delay -69 -> 252, step: 4
5965 11:32:43.073990 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5966 11:32:43.076712 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5967 11:32:43.083672 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5968 11:32:43.086780 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5969 11:32:43.090266 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5970 11:32:43.093624 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5971 11:32:43.097089 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5972 11:32:43.100350 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5973 11:32:43.106900 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5974 11:32:43.110358 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5975 11:32:43.113836 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5976 11:32:43.117408 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5977 11:32:43.120209 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5978 11:32:43.126871 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5979 11:32:43.130351 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5980 11:32:43.133894 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5981 11:32:43.133970 ==
5982 11:32:43.137209 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 11:32:43.140212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 11:32:43.140288 ==
5985 11:32:43.143682 DQS Delay:
5986 11:32:43.143781 DQS0 = 0, DQS1 = 0
5987 11:32:43.147228 DQM Delay:
5988 11:32:43.147303 DQM0 = 92, DQM1 = 88
5989 11:32:43.147361 DQ Delay:
5990 11:32:43.150001 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =90
5991 11:32:43.153300 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5992 11:32:43.156863 DQ8 =76, DQ9 =80, DQ10 =90, DQ11 =82
5993 11:32:43.160536 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5994 11:32:43.160611
5995 11:32:43.160670
5996 11:32:43.170051 [DQSOSCAuto] RK1, (LSB)MR18= 0x1428, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5997 11:32:43.173645 CH1 RK1: MR19=505, MR18=1428
5998 11:32:43.179835 CH1_RK1: MR19=0x505, MR18=0x1428, DQSOSC=409, MR23=63, INC=64, DEC=43
5999 11:32:43.179911 [RxdqsGatingPostProcess] freq 933
6000 11:32:43.186721 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6001 11:32:43.190044 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 11:32:43.193484 best DQS1 dly(2T, 0.5T) = (0, 11)
6003 11:32:43.196500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 11:32:43.199795 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
6005 11:32:43.203231 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 11:32:43.206815 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 11:32:43.209661 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 11:32:43.212991 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 11:32:43.216505 Pre-setting of DQS Precalculation
6010 11:32:43.220237 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6011 11:32:43.226460 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6012 11:32:43.236239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6013 11:32:43.236315
6014 11:32:43.236372
6015 11:32:43.236426 [Calibration Summary] 1866 Mbps
6016 11:32:43.239512 CH 0, Rank 0
6017 11:32:43.239587 SW Impedance : PASS
6018 11:32:43.243272 DUTY Scan : NO K
6019 11:32:43.246046 ZQ Calibration : PASS
6020 11:32:43.246160 Jitter Meter : NO K
6021 11:32:43.249634 CBT Training : PASS
6022 11:32:43.252928 Write leveling : PASS
6023 11:32:43.253003 RX DQS gating : PASS
6024 11:32:43.256008 RX DQ/DQS(RDDQC) : PASS
6025 11:32:43.259430 TX DQ/DQS : PASS
6026 11:32:43.259505 RX DATLAT : PASS
6027 11:32:43.262985 RX DQ/DQS(Engine): PASS
6028 11:32:43.265800 TX OE : NO K
6029 11:32:43.265875 All Pass.
6030 11:32:43.265933
6031 11:32:43.265986 CH 0, Rank 1
6032 11:32:43.269773 SW Impedance : PASS
6033 11:32:43.273056 DUTY Scan : NO K
6034 11:32:43.273131 ZQ Calibration : PASS
6035 11:32:43.276175 Jitter Meter : NO K
6036 11:32:43.279346 CBT Training : PASS
6037 11:32:43.279421 Write leveling : PASS
6038 11:32:43.282727 RX DQS gating : PASS
6039 11:32:43.286074 RX DQ/DQS(RDDQC) : PASS
6040 11:32:43.286197 TX DQ/DQS : PASS
6041 11:32:43.289465 RX DATLAT : PASS
6042 11:32:43.289539 RX DQ/DQS(Engine): PASS
6043 11:32:43.292731 TX OE : NO K
6044 11:32:43.292806 All Pass.
6045 11:32:43.292863
6046 11:32:43.295977 CH 1, Rank 0
6047 11:32:43.296052 SW Impedance : PASS
6048 11:32:43.299181 DUTY Scan : NO K
6049 11:32:43.302322 ZQ Calibration : PASS
6050 11:32:43.302398 Jitter Meter : NO K
6051 11:32:43.306025 CBT Training : PASS
6052 11:32:43.309107 Write leveling : PASS
6053 11:32:43.309199 RX DQS gating : PASS
6054 11:32:43.312266 RX DQ/DQS(RDDQC) : PASS
6055 11:32:43.315534 TX DQ/DQS : PASS
6056 11:32:43.315610 RX DATLAT : PASS
6057 11:32:43.319028 RX DQ/DQS(Engine): PASS
6058 11:32:43.322531 TX OE : NO K
6059 11:32:43.322607 All Pass.
6060 11:32:43.322665
6061 11:32:43.322720 CH 1, Rank 1
6062 11:32:43.325531 SW Impedance : PASS
6063 11:32:43.328804 DUTY Scan : NO K
6064 11:32:43.328879 ZQ Calibration : PASS
6065 11:32:43.332293 Jitter Meter : NO K
6066 11:32:43.335391 CBT Training : PASS
6067 11:32:43.335466 Write leveling : PASS
6068 11:32:43.339016 RX DQS gating : PASS
6069 11:32:43.342487 RX DQ/DQS(RDDQC) : PASS
6070 11:32:43.342563 TX DQ/DQS : PASS
6071 11:32:43.345521 RX DATLAT : PASS
6072 11:32:43.349070 RX DQ/DQS(Engine): PASS
6073 11:32:43.349145 TX OE : NO K
6074 11:32:43.349203 All Pass.
6075 11:32:43.352333
6076 11:32:43.352410 DramC Write-DBI off
6077 11:32:43.355393 PER_BANK_REFRESH: Hybrid Mode
6078 11:32:43.355468 TX_TRACKING: ON
6079 11:32:43.365186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6080 11:32:43.368551 [FAST_K] Save calibration result to emmc
6081 11:32:43.372103 dramc_set_vcore_voltage set vcore to 650000
6082 11:32:43.375078 Read voltage for 400, 6
6083 11:32:43.375153 Vio18 = 0
6084 11:32:43.378478 Vcore = 650000
6085 11:32:43.378553 Vdram = 0
6086 11:32:43.378611 Vddq = 0
6087 11:32:43.378665 Vmddr = 0
6088 11:32:43.384962 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6089 11:32:43.391916 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6090 11:32:43.391992 MEM_TYPE=3, freq_sel=20
6091 11:32:43.395228 sv_algorithm_assistance_LP4_800
6092 11:32:43.398229 ============ PULL DRAM RESETB DOWN ============
6093 11:32:43.405470 ========== PULL DRAM RESETB DOWN end =========
6094 11:32:43.408393 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6095 11:32:43.411827 ===================================
6096 11:32:43.415188 LPDDR4 DRAM CONFIGURATION
6097 11:32:43.418375 ===================================
6098 11:32:43.418451 EX_ROW_EN[0] = 0x0
6099 11:32:43.421356 EX_ROW_EN[1] = 0x0
6100 11:32:43.421431 LP4Y_EN = 0x0
6101 11:32:43.425357 WORK_FSP = 0x0
6102 11:32:43.425432 WL = 0x2
6103 11:32:43.428436 RL = 0x2
6104 11:32:43.431679 BL = 0x2
6105 11:32:43.431753 RPST = 0x0
6106 11:32:43.435293 RD_PRE = 0x0
6107 11:32:43.435367 WR_PRE = 0x1
6108 11:32:43.437948 WR_PST = 0x0
6109 11:32:43.438022 DBI_WR = 0x0
6110 11:32:43.441707 DBI_RD = 0x0
6111 11:32:43.441782 OTF = 0x1
6112 11:32:43.444667 ===================================
6113 11:32:43.448082 ===================================
6114 11:32:43.451294 ANA top config
6115 11:32:43.455115 ===================================
6116 11:32:43.455194 DLL_ASYNC_EN = 0
6117 11:32:43.458022 ALL_SLAVE_EN = 1
6118 11:32:43.461562 NEW_RANK_MODE = 1
6119 11:32:43.464495 DLL_IDLE_MODE = 1
6120 11:32:43.464580 LP45_APHY_COMB_EN = 1
6121 11:32:43.468009 TX_ODT_DIS = 1
6122 11:32:43.471455 NEW_8X_MODE = 1
6123 11:32:43.474339 ===================================
6124 11:32:43.478161 ===================================
6125 11:32:43.481459 data_rate = 800
6126 11:32:43.484757 CKR = 1
6127 11:32:43.487668 DQ_P2S_RATIO = 4
6128 11:32:43.491434 ===================================
6129 11:32:43.491510 CA_P2S_RATIO = 4
6130 11:32:43.494301 DQ_CA_OPEN = 0
6131 11:32:43.497699 DQ_SEMI_OPEN = 1
6132 11:32:43.501474 CA_SEMI_OPEN = 1
6133 11:32:43.504485 CA_FULL_RATE = 0
6134 11:32:43.507766 DQ_CKDIV4_EN = 0
6135 11:32:43.507842 CA_CKDIV4_EN = 1
6136 11:32:43.511151 CA_PREDIV_EN = 0
6137 11:32:43.514072 PH8_DLY = 0
6138 11:32:43.517668 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6139 11:32:43.520916 DQ_AAMCK_DIV = 0
6140 11:32:43.524108 CA_AAMCK_DIV = 0
6141 11:32:43.524183 CA_ADMCK_DIV = 4
6142 11:32:43.527598 DQ_TRACK_CA_EN = 0
6143 11:32:43.530862 CA_PICK = 800
6144 11:32:43.533894 CA_MCKIO = 400
6145 11:32:43.537437 MCKIO_SEMI = 400
6146 11:32:43.540733 PLL_FREQ = 3016
6147 11:32:43.544169 DQ_UI_PI_RATIO = 32
6148 11:32:43.547261 CA_UI_PI_RATIO = 32
6149 11:32:43.550734 ===================================
6150 11:32:43.553993 ===================================
6151 11:32:43.554092 memory_type:LPDDR4
6152 11:32:43.557121 GP_NUM : 10
6153 11:32:43.557196 SRAM_EN : 1
6154 11:32:43.560881 MD32_EN : 0
6155 11:32:43.564063 ===================================
6156 11:32:43.567102 [ANA_INIT] >>>>>>>>>>>>>>
6157 11:32:43.570787 <<<<<< [CONFIGURE PHASE]: ANA_TX
6158 11:32:43.574404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6159 11:32:43.576913 ===================================
6160 11:32:43.580480 data_rate = 800,PCW = 0X7400
6161 11:32:43.583993 ===================================
6162 11:32:43.587054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6163 11:32:43.590452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 11:32:43.603459 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6165 11:32:43.606912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6166 11:32:43.610092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6167 11:32:43.613596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6168 11:32:43.616836 [ANA_INIT] flow start
6169 11:32:43.616911 [ANA_INIT] PLL >>>>>>>>
6170 11:32:43.620351 [ANA_INIT] PLL <<<<<<<<
6171 11:32:43.623447 [ANA_INIT] MIDPI >>>>>>>>
6172 11:32:43.626925 [ANA_INIT] MIDPI <<<<<<<<
6173 11:32:43.627001 [ANA_INIT] DLL >>>>>>>>
6174 11:32:43.629784 [ANA_INIT] flow end
6175 11:32:43.633372 ============ LP4 DIFF to SE enter ============
6176 11:32:43.636923 ============ LP4 DIFF to SE exit ============
6177 11:32:43.639976 [ANA_INIT] <<<<<<<<<<<<<
6178 11:32:43.643086 [Flow] Enable top DCM control >>>>>
6179 11:32:43.646907 [Flow] Enable top DCM control <<<<<
6180 11:32:43.649860 Enable DLL master slave shuffle
6181 11:32:43.656670 ==============================================================
6182 11:32:43.656746 Gating Mode config
6183 11:32:43.663077 ==============================================================
6184 11:32:43.663152 Config description:
6185 11:32:43.673353 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6186 11:32:43.679630 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6187 11:32:43.686810 SELPH_MODE 0: By rank 1: By Phase
6188 11:32:43.689978 ==============================================================
6189 11:32:43.692680 GAT_TRACK_EN = 0
6190 11:32:43.696245 RX_GATING_MODE = 2
6191 11:32:43.699851 RX_GATING_TRACK_MODE = 2
6192 11:32:43.702948 SELPH_MODE = 1
6193 11:32:43.706455 PICG_EARLY_EN = 1
6194 11:32:43.709539 VALID_LAT_VALUE = 1
6195 11:32:43.716197 ==============================================================
6196 11:32:43.719788 Enter into Gating configuration >>>>
6197 11:32:43.722625 Exit from Gating configuration <<<<
6198 11:32:43.722700 Enter into DVFS_PRE_config >>>>>
6199 11:32:43.736061 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6200 11:32:43.739687 Exit from DVFS_PRE_config <<<<<
6201 11:32:43.742806 Enter into PICG configuration >>>>
6202 11:32:43.746038 Exit from PICG configuration <<<<
6203 11:32:43.746137 [RX_INPUT] configuration >>>>>
6204 11:32:43.749272 [RX_INPUT] configuration <<<<<
6205 11:32:43.755945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6206 11:32:43.759415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6207 11:32:43.765853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6208 11:32:43.772477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6209 11:32:43.779310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 11:32:43.786218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 11:32:43.789134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6212 11:32:43.792297 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6213 11:32:43.799475 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6214 11:32:43.802085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6215 11:32:43.805884 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6216 11:32:43.809352 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 11:32:43.812234 ===================================
6218 11:32:43.815625 LPDDR4 DRAM CONFIGURATION
6219 11:32:43.819434 ===================================
6220 11:32:43.822219 EX_ROW_EN[0] = 0x0
6221 11:32:43.822294 EX_ROW_EN[1] = 0x0
6222 11:32:43.825612 LP4Y_EN = 0x0
6223 11:32:43.825687 WORK_FSP = 0x0
6224 11:32:43.828851 WL = 0x2
6225 11:32:43.828926 RL = 0x2
6226 11:32:43.832326 BL = 0x2
6227 11:32:43.832401 RPST = 0x0
6228 11:32:43.835646 RD_PRE = 0x0
6229 11:32:43.839261 WR_PRE = 0x1
6230 11:32:43.839336 WR_PST = 0x0
6231 11:32:43.842139 DBI_WR = 0x0
6232 11:32:43.842215 DBI_RD = 0x0
6233 11:32:43.845373 OTF = 0x1
6234 11:32:43.848524 ===================================
6235 11:32:43.852250 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6236 11:32:43.855250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6237 11:32:43.858634 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 11:32:43.862031 ===================================
6239 11:32:43.865513 LPDDR4 DRAM CONFIGURATION
6240 11:32:43.869197 ===================================
6241 11:32:43.872016 EX_ROW_EN[0] = 0x10
6242 11:32:43.872092 EX_ROW_EN[1] = 0x0
6243 11:32:43.875108 LP4Y_EN = 0x0
6244 11:32:43.875188 WORK_FSP = 0x0
6245 11:32:43.878709 WL = 0x2
6246 11:32:43.878784 RL = 0x2
6247 11:32:43.882305 BL = 0x2
6248 11:32:43.882380 RPST = 0x0
6249 11:32:43.885223 RD_PRE = 0x0
6250 11:32:43.885298 WR_PRE = 0x1
6251 11:32:43.888210 WR_PST = 0x0
6252 11:32:43.891965 DBI_WR = 0x0
6253 11:32:43.892055 DBI_RD = 0x0
6254 11:32:43.895348 OTF = 0x1
6255 11:32:43.898261 ===================================
6256 11:32:43.901682 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6257 11:32:43.906871 nWR fixed to 30
6258 11:32:43.910402 [ModeRegInit_LP4] CH0 RK0
6259 11:32:43.910468 [ModeRegInit_LP4] CH0 RK1
6260 11:32:43.913977 [ModeRegInit_LP4] CH1 RK0
6261 11:32:43.916821 [ModeRegInit_LP4] CH1 RK1
6262 11:32:43.916897 match AC timing 19
6263 11:32:43.923349 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6264 11:32:43.926942 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6265 11:32:43.930193 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6266 11:32:43.937006 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6267 11:32:43.940246 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6268 11:32:43.940322 ==
6269 11:32:43.943346 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 11:32:43.946969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 11:32:43.947046 ==
6272 11:32:43.953511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 11:32:43.960041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6274 11:32:43.963365 [CA 0] Center 36 (8~64) winsize 57
6275 11:32:43.966733 [CA 1] Center 36 (8~64) winsize 57
6276 11:32:43.970042 [CA 2] Center 36 (8~64) winsize 57
6277 11:32:43.973452 [CA 3] Center 36 (8~64) winsize 57
6278 11:32:43.973527 [CA 4] Center 36 (8~64) winsize 57
6279 11:32:43.976728 [CA 5] Center 36 (8~64) winsize 57
6280 11:32:43.976804
6281 11:32:43.983145 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6282 11:32:43.983220
6283 11:32:43.986652 [CATrainingPosCal] consider 1 rank data
6284 11:32:43.989882 u2DelayCellTimex100 = 270/100 ps
6285 11:32:43.993195 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 11:32:43.996499 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 11:32:43.999556 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:32:44.002852 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:32:44.006568 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:32:44.010023 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:32:44.010105
6292 11:32:44.012829 CA PerBit enable=1, Macro0, CA PI delay=36
6293 11:32:44.012904
6294 11:32:44.016278 [CBTSetCACLKResult] CA Dly = 36
6295 11:32:44.019816 CS Dly: 1 (0~32)
6296 11:32:44.019891 ==
6297 11:32:44.022834 Dram Type= 6, Freq= 0, CH_0, rank 1
6298 11:32:44.026282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 11:32:44.026359 ==
6300 11:32:44.033220 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 11:32:44.039656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6302 11:32:44.039733 [CA 0] Center 36 (8~64) winsize 57
6303 11:32:44.042947 [CA 1] Center 36 (8~64) winsize 57
6304 11:32:44.046094 [CA 2] Center 36 (8~64) winsize 57
6305 11:32:44.049544 [CA 3] Center 36 (8~64) winsize 57
6306 11:32:44.052997 [CA 4] Center 36 (8~64) winsize 57
6307 11:32:44.056580 [CA 5] Center 36 (8~64) winsize 57
6308 11:32:44.056655
6309 11:32:44.059469 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6310 11:32:44.059544
6311 11:32:44.063031 [CATrainingPosCal] consider 2 rank data
6312 11:32:44.066367 u2DelayCellTimex100 = 270/100 ps
6313 11:32:44.069475 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 11:32:44.076127 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 11:32:44.079532 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:32:44.082475 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:32:44.086011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:32:44.089243 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:32:44.089317
6320 11:32:44.092397 CA PerBit enable=1, Macro0, CA PI delay=36
6321 11:32:44.092473
6322 11:32:44.096089 [CBTSetCACLKResult] CA Dly = 36
6323 11:32:44.096164 CS Dly: 1 (0~32)
6324 11:32:44.098992
6325 11:32:44.102570 ----->DramcWriteLeveling(PI) begin...
6326 11:32:44.102647 ==
6327 11:32:44.105743 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 11:32:44.109298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 11:32:44.109374 ==
6330 11:32:44.112160 Write leveling (Byte 0): 40 => 8
6331 11:32:44.115956 Write leveling (Byte 1): 40 => 8
6332 11:32:44.119050 DramcWriteLeveling(PI) end<-----
6333 11:32:44.119124
6334 11:32:44.119182 ==
6335 11:32:44.122517 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 11:32:44.125575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 11:32:44.125650 ==
6338 11:32:44.128999 [Gating] SW mode calibration
6339 11:32:44.135597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6340 11:32:44.142295 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6341 11:32:44.145528 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 11:32:44.148647 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6343 11:32:44.155362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 11:32:44.158797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 11:32:44.162462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 11:32:44.168785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 11:32:44.172306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 11:32:44.175326 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:32:44.181989 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 11:32:44.182064 Total UI for P1: 0, mck2ui 16
6351 11:32:44.185394 best dqsien dly found for B0: ( 0, 14, 24)
6352 11:32:44.188857 Total UI for P1: 0, mck2ui 16
6353 11:32:44.191946 best dqsien dly found for B1: ( 0, 14, 24)
6354 11:32:44.195585 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6355 11:32:44.201669 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6356 11:32:44.201744
6357 11:32:44.205138 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 11:32:44.208183 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6359 11:32:44.211831 [Gating] SW calibration Done
6360 11:32:44.211905 ==
6361 11:32:44.215155 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 11:32:44.218108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 11:32:44.218197 ==
6364 11:32:44.221678 RX Vref Scan: 0
6365 11:32:44.221751
6366 11:32:44.221810 RX Vref 0 -> 0, step: 1
6367 11:32:44.221862
6368 11:32:44.224881 RX Delay -410 -> 252, step: 16
6369 11:32:44.231564 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6370 11:32:44.234709 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6371 11:32:44.238208 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6372 11:32:44.241657 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6373 11:32:44.248255 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6374 11:32:44.251741 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6375 11:32:44.254655 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6376 11:32:44.258122 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6377 11:32:44.264899 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6378 11:32:44.268433 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6379 11:32:44.271411 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6380 11:32:44.274394 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6381 11:32:44.281436 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6382 11:32:44.284817 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6383 11:32:44.287784 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6384 11:32:44.291126 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6385 11:32:44.294532 ==
6386 11:32:44.297994 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:32:44.301196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:32:44.301270 ==
6389 11:32:44.301328 DQS Delay:
6390 11:32:44.304261 DQS0 = 59, DQS1 = 59
6391 11:32:44.304335 DQM Delay:
6392 11:32:44.307344 DQM0 = 18, DQM1 = 9
6393 11:32:44.307418 DQ Delay:
6394 11:32:44.310613 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6395 11:32:44.314037 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6396 11:32:44.317199 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6397 11:32:44.321268 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6398 11:32:44.321336
6399 11:32:44.321419
6400 11:32:44.321475 ==
6401 11:32:44.324436 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:32:44.327324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:32:44.327388 ==
6404 11:32:44.327441
6405 11:32:44.327496
6406 11:32:44.330845 TX Vref Scan disable
6407 11:32:44.330906 == TX Byte 0 ==
6408 11:32:44.337648 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 11:32:44.340532 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 11:32:44.340600 == TX Byte 1 ==
6411 11:32:44.346989 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 11:32:44.350586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 11:32:44.350652 ==
6414 11:32:44.353520 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 11:32:44.356860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 11:32:44.356933 ==
6417 11:32:44.356991
6418 11:32:44.357043
6419 11:32:44.360406 TX Vref Scan disable
6420 11:32:44.363516 == TX Byte 0 ==
6421 11:32:44.367384 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 11:32:44.370091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 11:32:44.370163 == TX Byte 1 ==
6424 11:32:44.377145 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 11:32:44.380144 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 11:32:44.380208
6427 11:32:44.380262 [DATLAT]
6428 11:32:44.383570 Freq=400, CH0 RK0
6429 11:32:44.383633
6430 11:32:44.383686 DATLAT Default: 0xf
6431 11:32:44.386943 0, 0xFFFF, sum = 0
6432 11:32:44.387006 1, 0xFFFF, sum = 0
6433 11:32:44.390427 2, 0xFFFF, sum = 0
6434 11:32:44.390495 3, 0xFFFF, sum = 0
6435 11:32:44.393622 4, 0xFFFF, sum = 0
6436 11:32:44.397222 5, 0xFFFF, sum = 0
6437 11:32:44.397294 6, 0xFFFF, sum = 0
6438 11:32:44.400248 7, 0xFFFF, sum = 0
6439 11:32:44.400312 8, 0xFFFF, sum = 0
6440 11:32:44.403403 9, 0xFFFF, sum = 0
6441 11:32:44.403468 10, 0xFFFF, sum = 0
6442 11:32:44.406411 11, 0xFFFF, sum = 0
6443 11:32:44.406480 12, 0xFFFF, sum = 0
6444 11:32:44.410338 13, 0x0, sum = 1
6445 11:32:44.410401 14, 0x0, sum = 2
6446 11:32:44.413024 15, 0x0, sum = 3
6447 11:32:44.413088 16, 0x0, sum = 4
6448 11:32:44.416643 best_step = 14
6449 11:32:44.416707
6450 11:32:44.416758 ==
6451 11:32:44.419739 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 11:32:44.423200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:32:44.423269 ==
6454 11:32:44.423324 RX Vref Scan: 1
6455 11:32:44.426169
6456 11:32:44.426232 RX Vref 0 -> 0, step: 1
6457 11:32:44.426292
6458 11:32:44.429982 RX Delay -359 -> 252, step: 8
6459 11:32:44.430075
6460 11:32:44.432906 Set Vref, RX VrefLevel [Byte0]: 61
6461 11:32:44.436523 [Byte1]: 53
6462 11:32:44.440394
6463 11:32:44.440457 Final RX Vref Byte 0 = 61 to rank0
6464 11:32:44.443754 Final RX Vref Byte 1 = 53 to rank0
6465 11:32:44.447292 Final RX Vref Byte 0 = 61 to rank1
6466 11:32:44.450704 Final RX Vref Byte 1 = 53 to rank1==
6467 11:32:44.454052 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 11:32:44.460607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 11:32:44.460677 ==
6470 11:32:44.460734 DQS Delay:
6471 11:32:44.463619 DQS0 = 60, DQS1 = 68
6472 11:32:44.463706 DQM Delay:
6473 11:32:44.463786 DQM0 = 15, DQM1 = 13
6474 11:32:44.467242 DQ Delay:
6475 11:32:44.470391 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =16
6476 11:32:44.473670 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6477 11:32:44.473736 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6478 11:32:44.476901 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6479 11:32:44.480484
6480 11:32:44.480553
6481 11:32:44.487011 [DQSOSCAuto] RK0, (LSB)MR18= 0x8786, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6482 11:32:44.490499 CH0 RK0: MR19=C0C, MR18=8786
6483 11:32:44.496945 CH0_RK0: MR19=0xC0C, MR18=0x8786, DQSOSC=392, MR23=63, INC=384, DEC=256
6484 11:32:44.497026 ==
6485 11:32:44.499998 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 11:32:44.503545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 11:32:44.503620 ==
6488 11:32:44.506900 [Gating] SW mode calibration
6489 11:32:44.513517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6490 11:32:44.519945 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6491 11:32:44.523240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 11:32:44.526532 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6493 11:32:44.533440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 11:32:44.536449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 11:32:44.539872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 11:32:44.546744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 11:32:44.549705 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 11:32:44.553053 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:32:44.559768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 11:32:44.559844 Total UI for P1: 0, mck2ui 16
6501 11:32:44.566375 best dqsien dly found for B0: ( 0, 14, 24)
6502 11:32:44.566450 Total UI for P1: 0, mck2ui 16
6503 11:32:44.569856 best dqsien dly found for B1: ( 0, 14, 24)
6504 11:32:44.576394 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6505 11:32:44.579919 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6506 11:32:44.579993
6507 11:32:44.583240 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 11:32:44.586263 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6509 11:32:44.589608 [Gating] SW calibration Done
6510 11:32:44.589683 ==
6511 11:32:44.593292 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 11:32:44.596481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:32:44.596556 ==
6514 11:32:44.599936 RX Vref Scan: 0
6515 11:32:44.600011
6516 11:32:44.600069 RX Vref 0 -> 0, step: 1
6517 11:32:44.600123
6518 11:32:44.603473 RX Delay -410 -> 252, step: 16
6519 11:32:44.609659 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6520 11:32:44.612756 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6521 11:32:44.616455 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6522 11:32:44.619588 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6523 11:32:44.626024 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6524 11:32:44.629832 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6525 11:32:44.632877 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6526 11:32:44.636131 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6527 11:32:44.642692 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6528 11:32:44.646370 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6529 11:32:44.649834 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6530 11:32:44.652742 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6531 11:32:44.659376 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6532 11:32:44.662778 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6533 11:32:44.665838 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6534 11:32:44.668935 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6535 11:32:44.672331 ==
6536 11:32:44.672406 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:32:44.679196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:32:44.679271 ==
6539 11:32:44.679330 DQS Delay:
6540 11:32:44.682659 DQS0 = 59, DQS1 = 59
6541 11:32:44.682734 DQM Delay:
6542 11:32:44.686512 DQM0 = 15, DQM1 = 10
6543 11:32:44.686587 DQ Delay:
6544 11:32:44.689331 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6545 11:32:44.692493 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6546 11:32:44.695896 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6547 11:32:44.699154 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6548 11:32:44.699229
6549 11:32:44.699287
6550 11:32:44.699340 ==
6551 11:32:44.702394 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 11:32:44.705595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 11:32:44.705672 ==
6554 11:32:44.705730
6555 11:32:44.705791
6556 11:32:44.709103 TX Vref Scan disable
6557 11:32:44.709165 == TX Byte 0 ==
6558 11:32:44.715519 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6559 11:32:44.719175 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6560 11:32:44.719245 == TX Byte 1 ==
6561 11:32:44.726073 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6562 11:32:44.728852 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6563 11:32:44.728925 ==
6564 11:32:44.732319 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 11:32:44.735337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 11:32:44.735413 ==
6567 11:32:44.735472
6568 11:32:44.735524
6569 11:32:44.738914 TX Vref Scan disable
6570 11:32:44.738975 == TX Byte 0 ==
6571 11:32:44.745592 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6572 11:32:44.749114 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6573 11:32:44.749181 == TX Byte 1 ==
6574 11:32:44.755543 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6575 11:32:44.758628 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6576 11:32:44.758696
6577 11:32:44.758752 [DATLAT]
6578 11:32:44.761808 Freq=400, CH0 RK1
6579 11:32:44.761875
6580 11:32:44.761928 DATLAT Default: 0xe
6581 11:32:44.765448 0, 0xFFFF, sum = 0
6582 11:32:44.765514 1, 0xFFFF, sum = 0
6583 11:32:44.768663 2, 0xFFFF, sum = 0
6584 11:32:44.768726 3, 0xFFFF, sum = 0
6585 11:32:44.772018 4, 0xFFFF, sum = 0
6586 11:32:44.772081 5, 0xFFFF, sum = 0
6587 11:32:44.775939 6, 0xFFFF, sum = 0
6588 11:32:44.776007 7, 0xFFFF, sum = 0
6589 11:32:44.778901 8, 0xFFFF, sum = 0
6590 11:32:44.778964 9, 0xFFFF, sum = 0
6591 11:32:44.781898 10, 0xFFFF, sum = 0
6592 11:32:44.785145 11, 0xFFFF, sum = 0
6593 11:32:44.785206 12, 0xFFFF, sum = 0
6594 11:32:44.788604 13, 0x0, sum = 1
6595 11:32:44.788666 14, 0x0, sum = 2
6596 11:32:44.792368 15, 0x0, sum = 3
6597 11:32:44.792434 16, 0x0, sum = 4
6598 11:32:44.792494 best_step = 14
6599 11:32:44.792546
6600 11:32:44.795264 ==
6601 11:32:44.798409 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 11:32:44.801648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 11:32:44.801713 ==
6604 11:32:44.801767 RX Vref Scan: 0
6605 11:32:44.801818
6606 11:32:44.805017 RX Vref 0 -> 0, step: 1
6607 11:32:44.805087
6608 11:32:44.808189 RX Delay -359 -> 252, step: 8
6609 11:32:44.815373 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6610 11:32:44.818632 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6611 11:32:44.822052 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6612 11:32:44.825247 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6613 11:32:44.832147 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6614 11:32:44.835178 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6615 11:32:44.838515 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6616 11:32:44.842176 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6617 11:32:44.848469 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6618 11:32:44.851807 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6619 11:32:44.855259 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6620 11:32:44.861430 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6621 11:32:44.864839 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6622 11:32:44.868473 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6623 11:32:44.872080 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6624 11:32:44.878689 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6625 11:32:44.878764 ==
6626 11:32:44.882156 Dram Type= 6, Freq= 0, CH_0, rank 1
6627 11:32:44.885187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 11:32:44.885263 ==
6629 11:32:44.885322 DQS Delay:
6630 11:32:44.888908 DQS0 = 60, DQS1 = 72
6631 11:32:44.888984 DQM Delay:
6632 11:32:44.891749 DQM0 = 11, DQM1 = 17
6633 11:32:44.891824 DQ Delay:
6634 11:32:44.895156 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6635 11:32:44.898366 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6636 11:32:44.901631 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8
6637 11:32:44.905077 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6638 11:32:44.905152
6639 11:32:44.905210
6640 11:32:44.911668 [DQSOSCAuto] RK1, (LSB)MR18= 0xca80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6641 11:32:44.915155 CH0 RK1: MR19=C0C, MR18=CA80
6642 11:32:44.921958 CH0_RK1: MR19=0xC0C, MR18=0xCA80, DQSOSC=384, MR23=63, INC=400, DEC=267
6643 11:32:44.924922 [RxdqsGatingPostProcess] freq 400
6644 11:32:44.931630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6645 11:32:44.934898 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 11:32:44.934977 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 11:32:44.938121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 11:32:44.941448 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 11:32:44.944663 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 11:32:44.947808 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 11:32:44.951048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 11:32:44.954405 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 11:32:44.957797 Pre-setting of DQS Precalculation
6654 11:32:44.964665 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6655 11:32:44.964742 ==
6656 11:32:44.968231 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 11:32:44.971120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 11:32:44.971222 ==
6659 11:32:44.977843 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 11:32:44.981029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6661 11:32:44.984440 [CA 0] Center 36 (8~64) winsize 57
6662 11:32:44.988037 [CA 1] Center 36 (8~64) winsize 57
6663 11:32:44.990870 [CA 2] Center 36 (8~64) winsize 57
6664 11:32:44.994402 [CA 3] Center 36 (8~64) winsize 57
6665 11:32:44.997411 [CA 4] Center 36 (8~64) winsize 57
6666 11:32:45.001003 [CA 5] Center 36 (8~64) winsize 57
6667 11:32:45.001078
6668 11:32:45.004172 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6669 11:32:45.004247
6670 11:32:45.007656 [CATrainingPosCal] consider 1 rank data
6671 11:32:45.010547 u2DelayCellTimex100 = 270/100 ps
6672 11:32:45.013707 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 11:32:45.020676 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 11:32:45.024183 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:32:45.027583 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:32:45.030489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:32:45.033959 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:32:45.034035
6679 11:32:45.037318 CA PerBit enable=1, Macro0, CA PI delay=36
6680 11:32:45.037429
6681 11:32:45.040641 [CBTSetCACLKResult] CA Dly = 36
6682 11:32:45.040713 CS Dly: 1 (0~32)
6683 11:32:45.043719 ==
6684 11:32:45.046942 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 11:32:45.050532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 11:32:45.050607 ==
6687 11:32:45.054171 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 11:32:45.060342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6689 11:32:45.063577 [CA 0] Center 36 (8~64) winsize 57
6690 11:32:45.066822 [CA 1] Center 36 (8~64) winsize 57
6691 11:32:45.070292 [CA 2] Center 36 (8~64) winsize 57
6692 11:32:45.073545 [CA 3] Center 36 (8~64) winsize 57
6693 11:32:45.076913 [CA 4] Center 36 (8~64) winsize 57
6694 11:32:45.080674 [CA 5] Center 36 (8~64) winsize 57
6695 11:32:45.080754
6696 11:32:45.083377 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6697 11:32:45.083452
6698 11:32:45.086800 [CATrainingPosCal] consider 2 rank data
6699 11:32:45.090072 u2DelayCellTimex100 = 270/100 ps
6700 11:32:45.093628 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 11:32:45.096787 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 11:32:45.100379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:32:45.103304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:32:45.109907 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:32:45.113022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:32:45.113149
6707 11:32:45.116908 CA PerBit enable=1, Macro0, CA PI delay=36
6708 11:32:45.117055
6709 11:32:45.119736 [CBTSetCACLKResult] CA Dly = 36
6710 11:32:45.119813 CS Dly: 1 (0~32)
6711 11:32:45.119904
6712 11:32:45.123425 ----->DramcWriteLeveling(PI) begin...
6713 11:32:45.123520 ==
6714 11:32:45.126270 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 11:32:45.132866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 11:32:45.132941 ==
6717 11:32:45.136324 Write leveling (Byte 0): 40 => 8
6718 11:32:45.139855 Write leveling (Byte 1): 40 => 8
6719 11:32:45.139926 DramcWriteLeveling(PI) end<-----
6720 11:32:45.139985
6721 11:32:45.143211 ==
6722 11:32:45.146269 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 11:32:45.149387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 11:32:45.149463 ==
6725 11:32:45.153639 [Gating] SW mode calibration
6726 11:32:45.159559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6727 11:32:45.163176 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6728 11:32:45.169810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 11:32:45.172704 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6730 11:32:45.176229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 11:32:45.182980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 11:32:45.186622 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 11:32:45.189258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 11:32:45.196169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 11:32:45.199466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:32:45.203000 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 11:32:45.205847 Total UI for P1: 0, mck2ui 16
6738 11:32:45.209389 best dqsien dly found for B0: ( 0, 14, 24)
6739 11:32:45.212708 Total UI for P1: 0, mck2ui 16
6740 11:32:45.215951 best dqsien dly found for B1: ( 0, 14, 24)
6741 11:32:45.219583 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6742 11:32:45.222686 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6743 11:32:45.222756
6744 11:32:45.229035 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 11:32:45.232535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6746 11:32:45.232597 [Gating] SW calibration Done
6747 11:32:45.236116 ==
6748 11:32:45.239463 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 11:32:45.242449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 11:32:45.242517 ==
6751 11:32:45.242573 RX Vref Scan: 0
6752 11:32:45.242625
6753 11:32:45.246057 RX Vref 0 -> 0, step: 1
6754 11:32:45.246159
6755 11:32:45.249246 RX Delay -410 -> 252, step: 16
6756 11:32:45.252435 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6757 11:32:45.255582 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6758 11:32:45.262907 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6759 11:32:45.265631 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6760 11:32:45.269280 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6761 11:32:45.272525 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6762 11:32:45.278914 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6763 11:32:45.282040 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6764 11:32:45.285760 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6765 11:32:45.288598 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6766 11:32:45.295233 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6767 11:32:45.298567 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6768 11:32:45.302332 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6769 11:32:45.308790 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6770 11:32:45.311925 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6771 11:32:45.315175 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6772 11:32:45.315250 ==
6773 11:32:45.318335 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:32:45.322139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:32:45.325501 ==
6776 11:32:45.325574 DQS Delay:
6777 11:32:45.325631 DQS0 = 51, DQS1 = 67
6778 11:32:45.328647 DQM Delay:
6779 11:32:45.328720 DQM0 = 12, DQM1 = 17
6780 11:32:45.331859 DQ Delay:
6781 11:32:45.331933 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6782 11:32:45.335115 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6783 11:32:45.338580 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6784 11:32:45.341769 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6785 11:32:45.341842
6786 11:32:45.341899
6787 11:32:45.345092 ==
6788 11:32:45.345165 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:32:45.352384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:32:45.352458 ==
6791 11:32:45.352516
6792 11:32:45.352569
6793 11:32:45.352619 TX Vref Scan disable
6794 11:32:45.355856 == TX Byte 0 ==
6795 11:32:45.358534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 11:32:45.362672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 11:32:45.365544 == TX Byte 1 ==
6798 11:32:45.368563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 11:32:45.372074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 11:32:45.375222 ==
6801 11:32:45.375295 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 11:32:45.381858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 11:32:45.381933 ==
6804 11:32:45.381990
6805 11:32:45.382043
6806 11:32:45.385197 TX Vref Scan disable
6807 11:32:45.385270 == TX Byte 0 ==
6808 11:32:45.388949 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 11:32:45.395099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 11:32:45.395173 == TX Byte 1 ==
6811 11:32:45.398671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:32:45.405321 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:32:45.405394
6814 11:32:45.405451 [DATLAT]
6815 11:32:45.405503 Freq=400, CH1 RK0
6816 11:32:45.405554
6817 11:32:45.408500 DATLAT Default: 0xf
6818 11:32:45.408574 0, 0xFFFF, sum = 0
6819 11:32:45.411720 1, 0xFFFF, sum = 0
6820 11:32:45.411828 2, 0xFFFF, sum = 0
6821 11:32:45.414841 3, 0xFFFF, sum = 0
6822 11:32:45.418010 4, 0xFFFF, sum = 0
6823 11:32:45.418133 5, 0xFFFF, sum = 0
6824 11:32:45.422295 6, 0xFFFF, sum = 0
6825 11:32:45.422370 7, 0xFFFF, sum = 0
6826 11:32:45.424842 8, 0xFFFF, sum = 0
6827 11:32:45.424917 9, 0xFFFF, sum = 0
6828 11:32:45.428240 10, 0xFFFF, sum = 0
6829 11:32:45.428315 11, 0xFFFF, sum = 0
6830 11:32:45.431452 12, 0xFFFF, sum = 0
6831 11:32:45.431528 13, 0x0, sum = 1
6832 11:32:45.434858 14, 0x0, sum = 2
6833 11:32:45.434933 15, 0x0, sum = 3
6834 11:32:45.438080 16, 0x0, sum = 4
6835 11:32:45.438164 best_step = 14
6836 11:32:45.438222
6837 11:32:45.438275 ==
6838 11:32:45.441778 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 11:32:45.444704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:32:45.448383 ==
6841 11:32:45.448457 RX Vref Scan: 1
6842 11:32:45.448514
6843 11:32:45.451657 RX Vref 0 -> 0, step: 1
6844 11:32:45.451730
6845 11:32:45.454914 RX Delay -375 -> 252, step: 8
6846 11:32:45.454987
6847 11:32:45.457979 Set Vref, RX VrefLevel [Byte0]: 56
6848 11:32:45.461064 [Byte1]: 53
6849 11:32:45.461138
6850 11:32:45.464492 Final RX Vref Byte 0 = 56 to rank0
6851 11:32:45.467829 Final RX Vref Byte 1 = 53 to rank0
6852 11:32:45.471596 Final RX Vref Byte 0 = 56 to rank1
6853 11:32:45.474853 Final RX Vref Byte 1 = 53 to rank1==
6854 11:32:45.477861 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 11:32:45.481850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 11:32:45.481930 ==
6857 11:32:45.484595 DQS Delay:
6858 11:32:45.484669 DQS0 = 56, DQS1 = 68
6859 11:32:45.487788 DQM Delay:
6860 11:32:45.487861 DQM0 = 13, DQM1 = 14
6861 11:32:45.487918 DQ Delay:
6862 11:32:45.491264 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6863 11:32:45.494906 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6864 11:32:45.497858 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6865 11:32:45.501172 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6866 11:32:45.501245
6867 11:32:45.501302
6868 11:32:45.511398 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6869 11:32:45.514984 CH1 RK0: MR19=C0C, MR18=5E71
6870 11:32:45.517590 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6871 11:32:45.521090 ==
6872 11:32:45.524295 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 11:32:45.527873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 11:32:45.527948 ==
6875 11:32:45.530887 [Gating] SW mode calibration
6876 11:32:45.537990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6877 11:32:45.540828 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6878 11:32:45.547253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 11:32:45.551095 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6880 11:32:45.554037 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 11:32:45.560506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 11:32:45.563954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 11:32:45.567635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 11:32:45.574140 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 11:32:45.577199 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:32:45.580639 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 11:32:45.583903 Total UI for P1: 0, mck2ui 16
6888 11:32:45.587718 best dqsien dly found for B0: ( 0, 14, 24)
6889 11:32:45.590385 Total UI for P1: 0, mck2ui 16
6890 11:32:45.593491 best dqsien dly found for B1: ( 0, 14, 24)
6891 11:32:45.597286 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6892 11:32:45.600105 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6893 11:32:45.600178
6894 11:32:45.606802 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 11:32:45.610350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6896 11:32:45.610425 [Gating] SW calibration Done
6897 11:32:45.613790 ==
6898 11:32:45.617323 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 11:32:45.620719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:32:45.620794 ==
6901 11:32:45.620852 RX Vref Scan: 0
6902 11:32:45.620906
6903 11:32:45.623492 RX Vref 0 -> 0, step: 1
6904 11:32:45.623565
6905 11:32:45.627042 RX Delay -410 -> 252, step: 16
6906 11:32:45.630005 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6907 11:32:45.636835 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6908 11:32:45.640417 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6909 11:32:45.643368 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6910 11:32:45.646837 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6911 11:32:45.653388 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6912 11:32:45.656609 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6913 11:32:45.660409 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6914 11:32:45.663202 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6915 11:32:45.670201 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6916 11:32:45.673741 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6917 11:32:45.676662 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6918 11:32:45.679761 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6919 11:32:45.686800 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6920 11:32:45.689865 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6921 11:32:45.693210 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6922 11:32:45.693284 ==
6923 11:32:45.696481 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:32:45.699890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:32:45.703678 ==
6926 11:32:45.703752 DQS Delay:
6927 11:32:45.703809 DQS0 = 59, DQS1 = 59
6928 11:32:45.706944 DQM Delay:
6929 11:32:45.707018 DQM0 = 19, DQM1 = 14
6930 11:32:45.709670 DQ Delay:
6931 11:32:45.713145 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6932 11:32:45.713220 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6933 11:32:45.716982 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6934 11:32:45.720012 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6935 11:32:45.720086
6936 11:32:45.723350
6937 11:32:45.723423 ==
6938 11:32:45.726112 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 11:32:45.730030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 11:32:45.730123 ==
6941 11:32:45.730194
6942 11:32:45.730247
6943 11:32:45.733236 TX Vref Scan disable
6944 11:32:45.733310 == TX Byte 0 ==
6945 11:32:45.737215 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6946 11:32:45.743048 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6947 11:32:45.743123 == TX Byte 1 ==
6948 11:32:45.746193 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6949 11:32:45.753606 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6950 11:32:45.753680 ==
6951 11:32:45.756552 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 11:32:45.759709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 11:32:45.759784 ==
6954 11:32:45.759841
6955 11:32:45.759894
6956 11:32:45.762710 TX Vref Scan disable
6957 11:32:45.762784 == TX Byte 0 ==
6958 11:32:45.766440 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6959 11:32:45.772872 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6960 11:32:45.772947 == TX Byte 1 ==
6961 11:32:45.776618 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6962 11:32:45.783274 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6963 11:32:45.783347
6964 11:32:45.783404 [DATLAT]
6965 11:32:45.783457 Freq=400, CH1 RK1
6966 11:32:45.783508
6967 11:32:45.786205 DATLAT Default: 0xe
6968 11:32:45.786279 0, 0xFFFF, sum = 0
6969 11:32:45.789678 1, 0xFFFF, sum = 0
6970 11:32:45.789753 2, 0xFFFF, sum = 0
6971 11:32:45.793124 3, 0xFFFF, sum = 0
6972 11:32:45.796575 4, 0xFFFF, sum = 0
6973 11:32:45.796651 5, 0xFFFF, sum = 0
6974 11:32:45.799420 6, 0xFFFF, sum = 0
6975 11:32:45.799495 7, 0xFFFF, sum = 0
6976 11:32:45.802745 8, 0xFFFF, sum = 0
6977 11:32:45.802821 9, 0xFFFF, sum = 0
6978 11:32:45.806421 10, 0xFFFF, sum = 0
6979 11:32:45.806496 11, 0xFFFF, sum = 0
6980 11:32:45.809545 12, 0xFFFF, sum = 0
6981 11:32:45.809620 13, 0x0, sum = 1
6982 11:32:45.812799 14, 0x0, sum = 2
6983 11:32:45.812874 15, 0x0, sum = 3
6984 11:32:45.816188 16, 0x0, sum = 4
6985 11:32:45.816263 best_step = 14
6986 11:32:45.816321
6987 11:32:45.816373 ==
6988 11:32:45.819168 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 11:32:45.822768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 11:32:45.825865 ==
6991 11:32:45.825938 RX Vref Scan: 0
6992 11:32:45.825995
6993 11:32:45.829281 RX Vref 0 -> 0, step: 1
6994 11:32:45.829354
6995 11:32:45.832391 RX Delay -359 -> 252, step: 8
6996 11:32:45.838962 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6997 11:32:45.842512 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6998 11:32:45.845698 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6999 11:32:45.849126 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7000 11:32:45.855420 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7001 11:32:45.858878 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7002 11:32:45.862740 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7003 11:32:45.865865 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7004 11:32:45.872213 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7005 11:32:45.875424 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7006 11:32:45.878734 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7007 11:32:45.882193 iDelay=217, Bit 11, Center -64 (-319 ~ 192) 512
7008 11:32:45.888455 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7009 11:32:45.892258 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7010 11:32:45.895271 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7011 11:32:45.901504 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7012 11:32:45.901577 ==
7013 11:32:45.905196 Dram Type= 6, Freq= 0, CH_1, rank 1
7014 11:32:45.908420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7015 11:32:45.908494 ==
7016 11:32:45.908552 DQS Delay:
7017 11:32:45.911446 DQS0 = 60, DQS1 = 64
7018 11:32:45.911520 DQM Delay:
7019 11:32:45.915192 DQM0 = 13, DQM1 = 10
7020 11:32:45.915266 DQ Delay:
7021 11:32:45.918481 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7022 11:32:45.921813 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7023 11:32:45.924993 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7024 11:32:45.928251 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7025 11:32:45.928325
7026 11:32:45.928382
7027 11:32:45.935400 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7028 11:32:45.938045 CH1 RK1: MR19=C0C, MR18=7BAD
7029 11:32:45.944855 CH1_RK1: MR19=0xC0C, MR18=0x7BAD, DQSOSC=388, MR23=63, INC=392, DEC=261
7030 11:32:45.948285 [RxdqsGatingPostProcess] freq 400
7031 11:32:45.954657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7032 11:32:45.954732 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 11:32:45.957956 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 11:32:45.961321 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 11:32:45.964813 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 11:32:45.967724 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 11:32:45.971140 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 11:32:45.974757 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 11:32:45.977751 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 11:32:45.981168 Pre-setting of DQS Precalculation
7041 11:32:45.987951 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7042 11:32:45.994462 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7043 11:32:46.001013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7044 11:32:46.001087
7045 11:32:46.001146
7046 11:32:46.004172 [Calibration Summary] 800 Mbps
7047 11:32:46.004245 CH 0, Rank 0
7048 11:32:46.007490 SW Impedance : PASS
7049 11:32:46.010676 DUTY Scan : NO K
7050 11:32:46.010750 ZQ Calibration : PASS
7051 11:32:46.013870 Jitter Meter : NO K
7052 11:32:46.017375 CBT Training : PASS
7053 11:32:46.017449 Write leveling : PASS
7054 11:32:46.020631 RX DQS gating : PASS
7055 11:32:46.020705 RX DQ/DQS(RDDQC) : PASS
7056 11:32:46.024004 TX DQ/DQS : PASS
7057 11:32:46.027467 RX DATLAT : PASS
7058 11:32:46.027541 RX DQ/DQS(Engine): PASS
7059 11:32:46.030544 TX OE : NO K
7060 11:32:46.030619 All Pass.
7061 11:32:46.030676
7062 11:32:46.034039 CH 0, Rank 1
7063 11:32:46.034152 SW Impedance : PASS
7064 11:32:46.037235 DUTY Scan : NO K
7065 11:32:46.040724 ZQ Calibration : PASS
7066 11:32:46.040798 Jitter Meter : NO K
7067 11:32:46.043867 CBT Training : PASS
7068 11:32:46.046900 Write leveling : NO K
7069 11:32:46.046975 RX DQS gating : PASS
7070 11:32:46.050486 RX DQ/DQS(RDDQC) : PASS
7071 11:32:46.054028 TX DQ/DQS : PASS
7072 11:32:46.054159 RX DATLAT : PASS
7073 11:32:46.057043 RX DQ/DQS(Engine): PASS
7074 11:32:46.060137 TX OE : NO K
7075 11:32:46.060211 All Pass.
7076 11:32:46.060267
7077 11:32:46.060319 CH 1, Rank 0
7078 11:32:46.063727 SW Impedance : PASS
7079 11:32:46.067117 DUTY Scan : NO K
7080 11:32:46.067191 ZQ Calibration : PASS
7081 11:32:46.070493 Jitter Meter : NO K
7082 11:32:46.073537 CBT Training : PASS
7083 11:32:46.073611 Write leveling : PASS
7084 11:32:46.077231 RX DQS gating : PASS
7085 11:32:46.080397 RX DQ/DQS(RDDQC) : PASS
7086 11:32:46.080471 TX DQ/DQS : PASS
7087 11:32:46.083475 RX DATLAT : PASS
7088 11:32:46.086994 RX DQ/DQS(Engine): PASS
7089 11:32:46.087067 TX OE : NO K
7090 11:32:46.087125 All Pass.
7091 11:32:46.087178
7092 11:32:46.090741 CH 1, Rank 1
7093 11:32:46.093375 SW Impedance : PASS
7094 11:32:46.093449 DUTY Scan : NO K
7095 11:32:46.097066 ZQ Calibration : PASS
7096 11:32:46.097139 Jitter Meter : NO K
7097 11:32:46.099984 CBT Training : PASS
7098 11:32:46.103137 Write leveling : NO K
7099 11:32:46.103212 RX DQS gating : PASS
7100 11:32:46.106514 RX DQ/DQS(RDDQC) : PASS
7101 11:32:46.109806 TX DQ/DQS : PASS
7102 11:32:46.109880 RX DATLAT : PASS
7103 11:32:46.113221 RX DQ/DQS(Engine): PASS
7104 11:32:46.116458 TX OE : NO K
7105 11:32:46.116533 All Pass.
7106 11:32:46.116590
7107 11:32:46.119703 DramC Write-DBI off
7108 11:32:46.119777 PER_BANK_REFRESH: Hybrid Mode
7109 11:32:46.123234 TX_TRACKING: ON
7110 11:32:46.133011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7111 11:32:46.136111 [FAST_K] Save calibration result to emmc
7112 11:32:46.139628 dramc_set_vcore_voltage set vcore to 725000
7113 11:32:46.139702 Read voltage for 1600, 0
7114 11:32:46.142796 Vio18 = 0
7115 11:32:46.142870 Vcore = 725000
7116 11:32:46.142927 Vdram = 0
7117 11:32:46.146050 Vddq = 0
7118 11:32:46.146179 Vmddr = 0
7119 11:32:46.149390 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7120 11:32:46.156315 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7121 11:32:46.159941 MEM_TYPE=3, freq_sel=13
7122 11:32:46.162954 sv_algorithm_assistance_LP4_3733
7123 11:32:46.166355 ============ PULL DRAM RESETB DOWN ============
7124 11:32:46.169933 ========== PULL DRAM RESETB DOWN end =========
7125 11:32:46.176131 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7126 11:32:46.179559 ===================================
7127 11:32:46.179634 LPDDR4 DRAM CONFIGURATION
7128 11:32:46.182603 ===================================
7129 11:32:46.186251 EX_ROW_EN[0] = 0x0
7130 11:32:46.186325 EX_ROW_EN[1] = 0x0
7131 11:32:46.189380 LP4Y_EN = 0x0
7132 11:32:46.192520 WORK_FSP = 0x1
7133 11:32:46.192594 WL = 0x5
7134 11:32:46.196210 RL = 0x5
7135 11:32:46.196306 BL = 0x2
7136 11:32:46.199242 RPST = 0x0
7137 11:32:46.199344 RD_PRE = 0x0
7138 11:32:46.202780 WR_PRE = 0x1
7139 11:32:46.202877 WR_PST = 0x1
7140 11:32:46.206023 DBI_WR = 0x0
7141 11:32:46.206156 DBI_RD = 0x0
7142 11:32:46.209322 OTF = 0x1
7143 11:32:46.212905 ===================================
7144 11:32:46.215789 ===================================
7145 11:32:46.215863 ANA top config
7146 11:32:46.219511 ===================================
7147 11:32:46.222631 DLL_ASYNC_EN = 0
7148 11:32:46.225779 ALL_SLAVE_EN = 0
7149 11:32:46.225877 NEW_RANK_MODE = 1
7150 11:32:46.228908 DLL_IDLE_MODE = 1
7151 11:32:46.232444 LP45_APHY_COMB_EN = 1
7152 11:32:46.235494 TX_ODT_DIS = 0
7153 11:32:46.238611 NEW_8X_MODE = 1
7154 11:32:46.242049 ===================================
7155 11:32:46.245389 ===================================
7156 11:32:46.249116 data_rate = 3200
7157 11:32:46.249191 CKR = 1
7158 11:32:46.252047 DQ_P2S_RATIO = 8
7159 11:32:46.255340 ===================================
7160 11:32:46.258696 CA_P2S_RATIO = 8
7161 11:32:46.261822 DQ_CA_OPEN = 0
7162 11:32:46.265187 DQ_SEMI_OPEN = 0
7163 11:32:46.268746 CA_SEMI_OPEN = 0
7164 11:32:46.268820 CA_FULL_RATE = 0
7165 11:32:46.272103 DQ_CKDIV4_EN = 0
7166 11:32:46.275877 CA_CKDIV4_EN = 0
7167 11:32:46.278678 CA_PREDIV_EN = 0
7168 11:32:46.281980 PH8_DLY = 12
7169 11:32:46.285070 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7170 11:32:46.285146 DQ_AAMCK_DIV = 4
7171 11:32:46.288379 CA_AAMCK_DIV = 4
7172 11:32:46.291990 CA_ADMCK_DIV = 4
7173 11:32:46.295152 DQ_TRACK_CA_EN = 0
7174 11:32:46.298853 CA_PICK = 1600
7175 11:32:46.301621 CA_MCKIO = 1600
7176 11:32:46.305016 MCKIO_SEMI = 0
7177 11:32:46.305090 PLL_FREQ = 3068
7178 11:32:46.308773 DQ_UI_PI_RATIO = 32
7179 11:32:46.311635 CA_UI_PI_RATIO = 0
7180 11:32:46.315413 ===================================
7181 11:32:46.318445 ===================================
7182 11:32:46.321576 memory_type:LPDDR4
7183 11:32:46.324833 GP_NUM : 10
7184 11:32:46.324907 SRAM_EN : 1
7185 11:32:46.327872 MD32_EN : 0
7186 11:32:46.331826 ===================================
7187 11:32:46.331901 [ANA_INIT] >>>>>>>>>>>>>>
7188 11:32:46.334599 <<<<<< [CONFIGURE PHASE]: ANA_TX
7189 11:32:46.338146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7190 11:32:46.341627 ===================================
7191 11:32:46.344606 data_rate = 3200,PCW = 0X7600
7192 11:32:46.347808 ===================================
7193 11:32:46.351257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7194 11:32:46.358455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 11:32:46.364258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7196 11:32:46.367689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7197 11:32:46.371173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7198 11:32:46.374383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7199 11:32:46.377823 [ANA_INIT] flow start
7200 11:32:46.377898 [ANA_INIT] PLL >>>>>>>>
7201 11:32:46.380896 [ANA_INIT] PLL <<<<<<<<
7202 11:32:46.384493 [ANA_INIT] MIDPI >>>>>>>>
7203 11:32:46.384564 [ANA_INIT] MIDPI <<<<<<<<
7204 11:32:46.387867 [ANA_INIT] DLL >>>>>>>>
7205 11:32:46.391429 [ANA_INIT] DLL <<<<<<<<
7206 11:32:46.391497 [ANA_INIT] flow end
7207 11:32:46.397354 ============ LP4 DIFF to SE enter ============
7208 11:32:46.400740 ============ LP4 DIFF to SE exit ============
7209 11:32:46.404052 [ANA_INIT] <<<<<<<<<<<<<
7210 11:32:46.407493 [Flow] Enable top DCM control >>>>>
7211 11:32:46.410572 [Flow] Enable top DCM control <<<<<
7212 11:32:46.410638 Enable DLL master slave shuffle
7213 11:32:46.417435 ==============================================================
7214 11:32:46.420796 Gating Mode config
7215 11:32:46.424169 ==============================================================
7216 11:32:46.427278 Config description:
7217 11:32:46.437318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7218 11:32:46.444174 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7219 11:32:46.447382 SELPH_MODE 0: By rank 1: By Phase
7220 11:32:46.454683 ==============================================================
7221 11:32:46.457191 GAT_TRACK_EN = 1
7222 11:32:46.460636 RX_GATING_MODE = 2
7223 11:32:46.464133 RX_GATING_TRACK_MODE = 2
7224 11:32:46.467135 SELPH_MODE = 1
7225 11:32:46.467216 PICG_EARLY_EN = 1
7226 11:32:46.470557 VALID_LAT_VALUE = 1
7227 11:32:46.476986 ==============================================================
7228 11:32:46.480321 Enter into Gating configuration >>>>
7229 11:32:46.484031 Exit from Gating configuration <<<<
7230 11:32:46.487435 Enter into DVFS_PRE_config >>>>>
7231 11:32:46.497404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7232 11:32:46.500129 Exit from DVFS_PRE_config <<<<<
7233 11:32:46.503797 Enter into PICG configuration >>>>
7234 11:32:46.507271 Exit from PICG configuration <<<<
7235 11:32:46.510089 [RX_INPUT] configuration >>>>>
7236 11:32:46.513598 [RX_INPUT] configuration <<<<<
7237 11:32:46.517239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7238 11:32:46.523947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7239 11:32:46.529913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7240 11:32:46.536647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7241 11:32:46.543464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 11:32:46.546876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 11:32:46.553482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7244 11:32:46.556519 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7245 11:32:46.560130 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7246 11:32:46.563346 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7247 11:32:46.569671 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7248 11:32:46.573148 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 11:32:46.576460 ===================================
7250 11:32:46.580364 LPDDR4 DRAM CONFIGURATION
7251 11:32:46.583582 ===================================
7252 11:32:46.583654 EX_ROW_EN[0] = 0x0
7253 11:32:46.586826 EX_ROW_EN[1] = 0x0
7254 11:32:46.586894 LP4Y_EN = 0x0
7255 11:32:46.590000 WORK_FSP = 0x1
7256 11:32:46.590072 WL = 0x5
7257 11:32:46.593369 RL = 0x5
7258 11:32:46.593434 BL = 0x2
7259 11:32:46.596398 RPST = 0x0
7260 11:32:46.599848 RD_PRE = 0x0
7261 11:32:46.599934 WR_PRE = 0x1
7262 11:32:46.603385 WR_PST = 0x1
7263 11:32:46.603459 DBI_WR = 0x0
7264 11:32:46.606377 DBI_RD = 0x0
7265 11:32:46.606452 OTF = 0x1
7266 11:32:46.610001 ===================================
7267 11:32:46.612849 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7268 11:32:46.619711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7269 11:32:46.623108 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 11:32:46.625983 ===================================
7271 11:32:46.629670 LPDDR4 DRAM CONFIGURATION
7272 11:32:46.632530 ===================================
7273 11:32:46.632605 EX_ROW_EN[0] = 0x10
7274 11:32:46.636467 EX_ROW_EN[1] = 0x0
7275 11:32:46.636540 LP4Y_EN = 0x0
7276 11:32:46.639530 WORK_FSP = 0x1
7277 11:32:46.639604 WL = 0x5
7278 11:32:46.642762 RL = 0x5
7279 11:32:46.642836 BL = 0x2
7280 11:32:46.645806 RPST = 0x0
7281 11:32:46.645879 RD_PRE = 0x0
7282 11:32:46.649543 WR_PRE = 0x1
7283 11:32:46.653029 WR_PST = 0x1
7284 11:32:46.653102 DBI_WR = 0x0
7285 11:32:46.656157 DBI_RD = 0x0
7286 11:32:46.656231 OTF = 0x1
7287 11:32:46.659352 ===================================
7288 11:32:46.665944 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7289 11:32:46.666018 ==
7290 11:32:46.669543 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 11:32:46.672712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 11:32:46.672787 ==
7293 11:32:46.676473 [Duty_Offset_Calibration]
7294 11:32:46.676547 B0:2 B1:0 CA:3
7295 11:32:46.679410
7296 11:32:46.683091 [DutyScan_Calibration_Flow] k_type=0
7297 11:32:46.690797
7298 11:32:46.690870 ==CLK 0==
7299 11:32:46.694237 Final CLK duty delay cell = 0
7300 11:32:46.697423 [0] MAX Duty = 5062%(X100), DQS PI = 20
7301 11:32:46.700784 [0] MIN Duty = 4875%(X100), DQS PI = 54
7302 11:32:46.700858 [0] AVG Duty = 4968%(X100)
7303 11:32:46.700915
7304 11:32:46.704169 CH0 CLK Duty spec in!! Max-Min= 187%
7305 11:32:46.711016 [DutyScan_Calibration_Flow] ====Done====
7306 11:32:46.711089
7307 11:32:46.714429 [DutyScan_Calibration_Flow] k_type=1
7308 11:32:46.730239
7309 11:32:46.730313 ==DQS 0 ==
7310 11:32:46.733764 Final DQS duty delay cell = 0
7311 11:32:46.737052 [0] MAX Duty = 5094%(X100), DQS PI = 14
7312 11:32:46.740245 [0] MIN Duty = 4875%(X100), DQS PI = 48
7313 11:32:46.743757 [0] AVG Duty = 4984%(X100)
7314 11:32:46.743830
7315 11:32:46.743888 ==DQS 1 ==
7316 11:32:46.746876 Final DQS duty delay cell = 0
7317 11:32:46.750260 [0] MAX Duty = 5156%(X100), DQS PI = 32
7318 11:32:46.753803 [0] MIN Duty = 5031%(X100), DQS PI = 12
7319 11:32:46.756647 [0] AVG Duty = 5093%(X100)
7320 11:32:46.756721
7321 11:32:46.759864 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7322 11:32:46.759938
7323 11:32:46.763455 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7324 11:32:46.766420 [DutyScan_Calibration_Flow] ====Done====
7325 11:32:46.766494
7326 11:32:46.769861 [DutyScan_Calibration_Flow] k_type=3
7327 11:32:46.788058
7328 11:32:46.788131 ==DQM 0 ==
7329 11:32:46.791523 Final DQM duty delay cell = 0
7330 11:32:46.795031 [0] MAX Duty = 5156%(X100), DQS PI = 30
7331 11:32:46.798041 [0] MIN Duty = 4875%(X100), DQS PI = 0
7332 11:32:46.798176 [0] AVG Duty = 5015%(X100)
7333 11:32:46.801313
7334 11:32:46.801399 ==DQM 1 ==
7335 11:32:46.804940 Final DQM duty delay cell = 4
7336 11:32:46.808413 [4] MAX Duty = 5156%(X100), DQS PI = 52
7337 11:32:46.811249 [4] MIN Duty = 5000%(X100), DQS PI = 10
7338 11:32:46.815424 [4] AVG Duty = 5078%(X100)
7339 11:32:46.815497
7340 11:32:46.818147 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7341 11:32:46.818225
7342 11:32:46.821255 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7343 11:32:46.824769 [DutyScan_Calibration_Flow] ====Done====
7344 11:32:46.824842
7345 11:32:46.828184 [DutyScan_Calibration_Flow] k_type=2
7346 11:32:46.844375
7347 11:32:46.844449 ==DQ 0 ==
7348 11:32:46.847917 Final DQ duty delay cell = -4
7349 11:32:46.850744 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7350 11:32:46.854559 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7351 11:32:46.857605 [-4] AVG Duty = 4938%(X100)
7352 11:32:46.857678
7353 11:32:46.857735 ==DQ 1 ==
7354 11:32:46.861042 Final DQ duty delay cell = 0
7355 11:32:46.864459 [0] MAX Duty = 5156%(X100), DQS PI = 60
7356 11:32:46.867893 [0] MIN Duty = 5000%(X100), DQS PI = 16
7357 11:32:46.870931 [0] AVG Duty = 5078%(X100)
7358 11:32:46.871004
7359 11:32:46.874303 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7360 11:32:46.874377
7361 11:32:46.877600 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7362 11:32:46.880909 [DutyScan_Calibration_Flow] ====Done====
7363 11:32:46.880982 ==
7364 11:32:46.884126 Dram Type= 6, Freq= 0, CH_1, rank 0
7365 11:32:46.887325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7366 11:32:46.887399 ==
7367 11:32:46.890826 [Duty_Offset_Calibration]
7368 11:32:46.890900 B0:1 B1:-2 CA:1
7369 11:32:46.890957
7370 11:32:46.894261 [DutyScan_Calibration_Flow] k_type=0
7371 11:32:46.905108
7372 11:32:46.905181 ==CLK 0==
7373 11:32:46.908184 Final CLK duty delay cell = 0
7374 11:32:46.911726 [0] MAX Duty = 5062%(X100), DQS PI = 22
7375 11:32:46.914756 [0] MIN Duty = 4813%(X100), DQS PI = 62
7376 11:32:46.914830 [0] AVG Duty = 4937%(X100)
7377 11:32:46.918416
7378 11:32:46.921399 CH1 CLK Duty spec in!! Max-Min= 249%
7379 11:32:46.924879 [DutyScan_Calibration_Flow] ====Done====
7380 11:32:46.924952
7381 11:32:46.928462 [DutyScan_Calibration_Flow] k_type=1
7382 11:32:46.944708
7383 11:32:46.944780 ==DQS 0 ==
7384 11:32:46.947600 Final DQS duty delay cell = 0
7385 11:32:46.951165 [0] MAX Duty = 5187%(X100), DQS PI = 26
7386 11:32:46.954582 [0] MIN Duty = 5031%(X100), DQS PI = 54
7387 11:32:46.958255 [0] AVG Duty = 5109%(X100)
7388 11:32:46.958327
7389 11:32:46.958384 ==DQS 1 ==
7390 11:32:46.960858 Final DQS duty delay cell = 0
7391 11:32:46.964654 [0] MAX Duty = 5093%(X100), DQS PI = 0
7392 11:32:46.967948 [0] MIN Duty = 4844%(X100), DQS PI = 26
7393 11:32:46.970793 [0] AVG Duty = 4968%(X100)
7394 11:32:46.970866
7395 11:32:46.974396 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7396 11:32:46.974470
7397 11:32:46.977674 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7398 11:32:46.980728 [DutyScan_Calibration_Flow] ====Done====
7399 11:32:46.980801
7400 11:32:46.984033 [DutyScan_Calibration_Flow] k_type=3
7401 11:32:47.001516
7402 11:32:47.001590 ==DQM 0 ==
7403 11:32:47.004395 Final DQM duty delay cell = 0
7404 11:32:47.008165 [0] MAX Duty = 5031%(X100), DQS PI = 24
7405 11:32:47.011024 [0] MIN Duty = 4813%(X100), DQS PI = 54
7406 11:32:47.014395 [0] AVG Duty = 4922%(X100)
7407 11:32:47.014470
7408 11:32:47.014527 ==DQM 1 ==
7409 11:32:47.018005 Final DQM duty delay cell = 0
7410 11:32:47.020979 [0] MAX Duty = 5062%(X100), DQS PI = 34
7411 11:32:47.024521 [0] MIN Duty = 4875%(X100), DQS PI = 26
7412 11:32:47.027714 [0] AVG Duty = 4968%(X100)
7413 11:32:47.027788
7414 11:32:47.031356 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7415 11:32:47.031431
7416 11:32:47.034365 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7417 11:32:47.037916 [DutyScan_Calibration_Flow] ====Done====
7418 11:32:47.037990
7419 11:32:47.040987 [DutyScan_Calibration_Flow] k_type=2
7420 11:32:47.058556
7421 11:32:47.058630 ==DQ 0 ==
7422 11:32:47.061401 Final DQ duty delay cell = 0
7423 11:32:47.064553 [0] MAX Duty = 5093%(X100), DQS PI = 20
7424 11:32:47.068112 [0] MIN Duty = 4907%(X100), DQS PI = 0
7425 11:32:47.068187 [0] AVG Duty = 5000%(X100)
7426 11:32:47.071475
7427 11:32:47.071549 ==DQ 1 ==
7428 11:32:47.074583 Final DQ duty delay cell = 0
7429 11:32:47.077590 [0] MAX Duty = 5125%(X100), DQS PI = 34
7430 11:32:47.081392 [0] MIN Duty = 4938%(X100), DQS PI = 24
7431 11:32:47.081467 [0] AVG Duty = 5031%(X100)
7432 11:32:47.084871
7433 11:32:47.088266 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7434 11:32:47.088340
7435 11:32:47.091411 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7436 11:32:47.094457 [DutyScan_Calibration_Flow] ====Done====
7437 11:32:47.097504 nWR fixed to 30
7438 11:32:47.097579 [ModeRegInit_LP4] CH0 RK0
7439 11:32:47.101434 [ModeRegInit_LP4] CH0 RK1
7440 11:32:47.104108 [ModeRegInit_LP4] CH1 RK0
7441 11:32:47.108161 [ModeRegInit_LP4] CH1 RK1
7442 11:32:47.108235 match AC timing 5
7443 11:32:47.114074 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7444 11:32:47.117554 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7445 11:32:47.120974 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7446 11:32:47.127338 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7447 11:32:47.131166 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7448 11:32:47.131241 [MiockJmeterHQA]
7449 11:32:47.131299
7450 11:32:47.134203 [DramcMiockJmeter] u1RxGatingPI = 0
7451 11:32:47.137293 0 : 4259, 4032
7452 11:32:47.137368 4 : 4255, 4029
7453 11:32:47.140601 8 : 4257, 4029
7454 11:32:47.140676 12 : 4257, 4032
7455 11:32:47.140736 16 : 4366, 4140
7456 11:32:47.143959 20 : 4257, 4029
7457 11:32:47.144034 24 : 4255, 4029
7458 11:32:47.147426 28 : 4257, 4029
7459 11:32:47.147500 32 : 4260, 4032
7460 11:32:47.150378 36 : 4255, 4030
7461 11:32:47.150454 40 : 4365, 4140
7462 11:32:47.153827 44 : 4254, 4029
7463 11:32:47.153902 48 : 4250, 4026
7464 11:32:47.153961 52 : 4250, 4027
7465 11:32:47.157449 56 : 4255, 4030
7466 11:32:47.157524 60 : 4365, 4139
7467 11:32:47.160557 64 : 4252, 4029
7468 11:32:47.160632 68 : 4253, 4029
7469 11:32:47.163944 72 : 4255, 4029
7470 11:32:47.164019 76 : 4255, 4029
7471 11:32:47.167198 80 : 4252, 4029
7472 11:32:47.167274 84 : 4253, 4029
7473 11:32:47.167333 88 : 4255, 4029
7474 11:32:47.170604 92 : 4252, 4029
7475 11:32:47.170680 96 : 4365, 4142
7476 11:32:47.174001 100 : 4252, 4029
7477 11:32:47.174078 104 : 4254, 3306
7478 11:32:47.177175 108 : 4258, 0
7479 11:32:47.177250 112 : 4252, 0
7480 11:32:47.177309 116 : 4365, 0
7481 11:32:47.180709 120 : 4255, 0
7482 11:32:47.180785 124 : 4363, 0
7483 11:32:47.183543 128 : 4365, 0
7484 11:32:47.183619 132 : 4250, 0
7485 11:32:47.183679 136 : 4254, 0
7486 11:32:47.186879 140 : 4252, 0
7487 11:32:47.186954 144 : 4252, 0
7488 11:32:47.190229 148 : 4258, 0
7489 11:32:47.190305 152 : 4363, 0
7490 11:32:47.190364 156 : 4252, 0
7491 11:32:47.193725 160 : 4253, 0
7492 11:32:47.193800 164 : 4252, 0
7493 11:32:47.196777 168 : 4368, 0
7494 11:32:47.196853 172 : 4253, 0
7495 11:32:47.196912 176 : 4363, 0
7496 11:32:47.200292 180 : 4252, 0
7497 11:32:47.200368 184 : 4252, 0
7498 11:32:47.200427 188 : 4253, 0
7499 11:32:47.203743 192 : 4363, 0
7500 11:32:47.203818 196 : 4252, 0
7501 11:32:47.206712 200 : 4253, 0
7502 11:32:47.206787 204 : 4252, 0
7503 11:32:47.206847 208 : 4257, 0
7504 11:32:47.210356 212 : 4253, 0
7505 11:32:47.210432 216 : 4252, 0
7506 11:32:47.213714 220 : 4252, 0
7507 11:32:47.213790 224 : 4257, 0
7508 11:32:47.213849 228 : 4252, 0
7509 11:32:47.216975 232 : 4252, 0
7510 11:32:47.217051 236 : 4368, 716
7511 11:32:47.220040 240 : 4252, 4029
7512 11:32:47.220115 244 : 4253, 4029
7513 11:32:47.223729 248 : 4257, 4032
7514 11:32:47.223804 252 : 4255, 4029
7515 11:32:47.226675 256 : 4365, 4140
7516 11:32:47.226752 260 : 4252, 4029
7517 11:32:47.226812 264 : 4252, 4029
7518 11:32:47.230053 268 : 4368, 4142
7519 11:32:47.230137 272 : 4252, 4030
7520 11:32:47.233637 276 : 4254, 4029
7521 11:32:47.233712 280 : 4363, 4140
7522 11:32:47.236576 284 : 4255, 4029
7523 11:32:47.236652 288 : 4255, 4029
7524 11:32:47.240002 292 : 4255, 4029
7525 11:32:47.240078 296 : 4363, 4140
7526 11:32:47.243013 300 : 4253, 4029
7527 11:32:47.243088 304 : 4252, 4030
7528 11:32:47.246536 308 : 4255, 4029
7529 11:32:47.246611 312 : 4252, 4030
7530 11:32:47.250070 316 : 4252, 4030
7531 11:32:47.250202 320 : 4368, 4142
7532 11:32:47.253644 324 : 4255, 4029
7533 11:32:47.253719 328 : 4363, 4139
7534 11:32:47.253778 332 : 4253, 4029
7535 11:32:47.256514 336 : 4255, 4029
7536 11:32:47.256590 340 : 4255, 4029
7537 11:32:47.259942 344 : 4252, 4029
7538 11:32:47.260017 348 : 4363, 4140
7539 11:32:47.263497 352 : 4255, 4023
7540 11:32:47.263572 356 : 4255, 2853
7541 11:32:47.266886 360 : 4366, 0
7542 11:32:47.266962
7543 11:32:47.267019 MIOCK jitter meter ch=0
7544 11:32:47.267073
7545 11:32:47.269913 1T = (360-108) = 252 dly cells
7546 11:32:47.276515 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7547 11:32:47.276590 ==
7548 11:32:47.279894 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 11:32:47.282787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 11:32:47.282862 ==
7551 11:32:47.289690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 11:32:47.293095 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 11:32:47.299466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 11:32:47.302912 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 11:32:47.312713 [CA 0] Center 44 (13~75) winsize 63
7556 11:32:47.316278 [CA 1] Center 43 (13~74) winsize 62
7557 11:32:47.319586 [CA 2] Center 39 (10~69) winsize 60
7558 11:32:47.323317 [CA 3] Center 39 (10~68) winsize 59
7559 11:32:47.326050 [CA 4] Center 37 (8~67) winsize 60
7560 11:32:47.329382 [CA 5] Center 37 (7~67) winsize 61
7561 11:32:47.329456
7562 11:32:47.332915 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 11:32:47.332989
7564 11:32:47.336225 [CATrainingPosCal] consider 1 rank data
7565 11:32:47.339565 u2DelayCellTimex100 = 258/100 ps
7566 11:32:47.346578 CA0 delay=44 (13~75),Diff = 7 PI (26 cell)
7567 11:32:47.349790 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7568 11:32:47.353159 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7569 11:32:47.355920 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7570 11:32:47.359528 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7571 11:32:47.362454 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7572 11:32:47.362529
7573 11:32:47.365893 CA PerBit enable=1, Macro0, CA PI delay=37
7574 11:32:47.366034
7575 11:32:47.369530 [CBTSetCACLKResult] CA Dly = 37
7576 11:32:47.372461 CS Dly: 11 (0~42)
7577 11:32:47.375707 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 11:32:47.379050 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 11:32:47.379147 ==
7580 11:32:47.382715 Dram Type= 6, Freq= 0, CH_0, rank 1
7581 11:32:47.388889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 11:32:47.388965 ==
7583 11:32:47.392343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7584 11:32:47.399370 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7585 11:32:47.402406 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7586 11:32:47.408751 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7587 11:32:47.416791 [CA 0] Center 44 (14~74) winsize 61
7588 11:32:47.419776 [CA 1] Center 43 (13~74) winsize 62
7589 11:32:47.423003 [CA 2] Center 39 (10~68) winsize 59
7590 11:32:47.426308 [CA 3] Center 39 (10~68) winsize 59
7591 11:32:47.429819 [CA 4] Center 36 (7~66) winsize 60
7592 11:32:47.433046 [CA 5] Center 36 (7~66) winsize 60
7593 11:32:47.433121
7594 11:32:47.436527 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7595 11:32:47.436651
7596 11:32:47.443043 [CATrainingPosCal] consider 2 rank data
7597 11:32:47.443117 u2DelayCellTimex100 = 258/100 ps
7598 11:32:47.450019 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7599 11:32:47.452964 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7600 11:32:47.456726 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7601 11:32:47.459661 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7602 11:32:47.462874 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7603 11:32:47.466233 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7604 11:32:47.466308
7605 11:32:47.469710 CA PerBit enable=1, Macro0, CA PI delay=36
7606 11:32:47.469785
7607 11:32:47.472930 [CBTSetCACLKResult] CA Dly = 36
7608 11:32:47.476666 CS Dly: 11 (0~43)
7609 11:32:47.479451 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7610 11:32:47.483438 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7611 11:32:47.483513
7612 11:32:47.486266 ----->DramcWriteLeveling(PI) begin...
7613 11:32:47.486342 ==
7614 11:32:47.489691 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 11:32:47.496600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 11:32:47.496675 ==
7617 11:32:47.499866 Write leveling (Byte 0): 34 => 34
7618 11:32:47.503101 Write leveling (Byte 1): 27 => 27
7619 11:32:47.505894 DramcWriteLeveling(PI) end<-----
7620 11:32:47.505967
7621 11:32:47.506025 ==
7622 11:32:47.509217 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 11:32:47.512662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 11:32:47.512736 ==
7625 11:32:47.516315 [Gating] SW mode calibration
7626 11:32:47.522969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7627 11:32:47.525889 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7628 11:32:47.532744 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 11:32:47.535753 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:32:47.539271 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:32:47.545854 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 11:32:47.549048 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7633 11:32:47.552457 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
7634 11:32:47.558957 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7635 11:32:47.562853 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 11:32:47.565553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:32:47.572723 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 11:32:47.575869 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:32:47.578818 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7640 11:32:47.585543 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7641 11:32:47.589311 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7642 11:32:47.592306 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7643 11:32:47.598880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:32:47.602401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 11:32:47.605540 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:32:47.612307 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:32:47.615726 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7648 11:32:47.618838 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7649 11:32:47.625354 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7650 11:32:47.628921 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7651 11:32:47.631889 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 11:32:47.638630 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:32:47.642042 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:32:47.645100 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:32:47.652034 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 11:32:47.655075 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 11:32:47.658878 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7658 11:32:47.665451 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 11:32:47.668421 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:32:47.672050 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:32:47.678731 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:32:47.681775 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:32:47.685176 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:32:47.688365 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:32:47.694997 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:32:47.698354 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:32:47.701931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:32:47.708180 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:32:47.711704 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:32:47.714652 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:32:47.721714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 11:32:47.725067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7673 11:32:47.727866 Total UI for P1: 0, mck2ui 16
7674 11:32:47.731527 best dqsien dly found for B0: ( 1, 9, 12)
7675 11:32:47.734912 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7676 11:32:47.741315 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 11:32:47.744596 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 11:32:47.748531 Total UI for P1: 0, mck2ui 16
7679 11:32:47.751485 best dqsien dly found for B1: ( 1, 9, 24)
7680 11:32:47.754724 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7681 11:32:47.758040 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7682 11:32:47.758168
7683 11:32:47.761212 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7684 11:32:47.768407 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7685 11:32:47.768482 [Gating] SW calibration Done
7686 11:32:47.768541 ==
7687 11:32:47.771686 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:32:47.777860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:32:47.777935 ==
7690 11:32:47.777994 RX Vref Scan: 0
7691 11:32:47.778048
7692 11:32:47.781265 RX Vref 0 -> 0, step: 1
7693 11:32:47.781339
7694 11:32:47.784519 RX Delay 0 -> 252, step: 8
7695 11:32:47.787899 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7696 11:32:47.790889 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7697 11:32:47.794395 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7698 11:32:47.798007 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7699 11:32:47.804640 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7700 11:32:47.807804 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7701 11:32:47.810972 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7702 11:32:47.814427 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7703 11:32:47.817410 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7704 11:32:47.824057 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7705 11:32:47.827505 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7706 11:32:47.831092 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7707 11:32:47.834429 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7708 11:32:47.840658 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7709 11:32:47.844158 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7710 11:32:47.847732 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7711 11:32:47.847807 ==
7712 11:32:47.850615 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:32:47.854037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:32:47.854156 ==
7715 11:32:47.857411 DQS Delay:
7716 11:32:47.857485 DQS0 = 0, DQS1 = 0
7717 11:32:47.860446 DQM Delay:
7718 11:32:47.860520 DQM0 = 126, DQM1 = 123
7719 11:32:47.860578 DQ Delay:
7720 11:32:47.863945 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7721 11:32:47.871040 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =135
7722 11:32:47.874110 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7723 11:32:47.877164 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7724 11:32:47.877238
7725 11:32:47.877296
7726 11:32:47.877349 ==
7727 11:32:47.880374 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 11:32:47.884585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 11:32:47.884661 ==
7730 11:32:47.884719
7731 11:32:47.884771
7732 11:32:47.887839 TX Vref Scan disable
7733 11:32:47.890533 == TX Byte 0 ==
7734 11:32:47.893695 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7735 11:32:47.897155 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7736 11:32:47.900473 == TX Byte 1 ==
7737 11:32:47.903900 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7738 11:32:47.907167 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7739 11:32:47.907241 ==
7740 11:32:47.910688 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 11:32:47.914420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 11:32:47.917324 ==
7743 11:32:47.929369
7744 11:32:47.932457 TX Vref early break, caculate TX vref
7745 11:32:47.935517 TX Vref=16, minBit 9, minWin=21, winSum=357
7746 11:32:47.939218 TX Vref=18, minBit 8, minWin=21, winSum=364
7747 11:32:47.941814 TX Vref=20, minBit 8, minWin=22, winSum=375
7748 11:32:47.945334 TX Vref=22, minBit 7, minWin=23, winSum=385
7749 11:32:47.948545 TX Vref=24, minBit 8, minWin=23, winSum=392
7750 11:32:47.955356 TX Vref=26, minBit 8, minWin=23, winSum=398
7751 11:32:47.959317 TX Vref=28, minBit 9, minWin=24, winSum=403
7752 11:32:47.962329 TX Vref=30, minBit 8, minWin=23, winSum=389
7753 11:32:47.965534 TX Vref=32, minBit 8, minWin=22, winSum=382
7754 11:32:47.968588 TX Vref=34, minBit 8, minWin=22, winSum=376
7755 11:32:47.975024 [TxChooseVref] Worse bit 9, Min win 24, Win sum 403, Final Vref 28
7756 11:32:47.975093
7757 11:32:47.978518 Final TX Range 0 Vref 28
7758 11:32:47.978592
7759 11:32:47.978651 ==
7760 11:32:47.981896 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 11:32:47.985079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 11:32:47.985140 ==
7763 11:32:47.985193
7764 11:32:47.985244
7765 11:32:47.988433 TX Vref Scan disable
7766 11:32:47.995107 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7767 11:32:47.995170 == TX Byte 0 ==
7768 11:32:47.998948 u2DelayCellOfst[0]=15 cells (4 PI)
7769 11:32:48.002004 u2DelayCellOfst[1]=18 cells (5 PI)
7770 11:32:48.005064 u2DelayCellOfst[2]=15 cells (4 PI)
7771 11:32:48.008645 u2DelayCellOfst[3]=15 cells (4 PI)
7772 11:32:48.011870 u2DelayCellOfst[4]=7 cells (2 PI)
7773 11:32:48.015161 u2DelayCellOfst[5]=0 cells (0 PI)
7774 11:32:48.019227 u2DelayCellOfst[6]=22 cells (6 PI)
7775 11:32:48.022031 u2DelayCellOfst[7]=18 cells (5 PI)
7776 11:32:48.025121 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7777 11:32:48.028427 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7778 11:32:48.031524 == TX Byte 1 ==
7779 11:32:48.031595 u2DelayCellOfst[8]=0 cells (0 PI)
7780 11:32:48.035067 u2DelayCellOfst[9]=3 cells (1 PI)
7781 11:32:48.038447 u2DelayCellOfst[10]=11 cells (3 PI)
7782 11:32:48.041487 u2DelayCellOfst[11]=7 cells (2 PI)
7783 11:32:48.045107 u2DelayCellOfst[12]=15 cells (4 PI)
7784 11:32:48.048237 u2DelayCellOfst[13]=15 cells (4 PI)
7785 11:32:48.051589 u2DelayCellOfst[14]=18 cells (5 PI)
7786 11:32:48.055326 u2DelayCellOfst[15]=15 cells (4 PI)
7787 11:32:48.058598 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7788 11:32:48.064931 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7789 11:32:48.065006 DramC Write-DBI on
7790 11:32:48.065064 ==
7791 11:32:48.068428 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 11:32:48.074899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 11:32:48.074974 ==
7794 11:32:48.075031
7795 11:32:48.075083
7796 11:32:48.075133 TX Vref Scan disable
7797 11:32:48.078582 == TX Byte 0 ==
7798 11:32:48.081732 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7799 11:32:48.085622 == TX Byte 1 ==
7800 11:32:48.088231 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7801 11:32:48.091662 DramC Write-DBI off
7802 11:32:48.091736
7803 11:32:48.091794 [DATLAT]
7804 11:32:48.091848 Freq=1600, CH0 RK0
7805 11:32:48.091900
7806 11:32:48.095212 DATLAT Default: 0xf
7807 11:32:48.095286 0, 0xFFFF, sum = 0
7808 11:32:48.098586 1, 0xFFFF, sum = 0
7809 11:32:48.098686 2, 0xFFFF, sum = 0
7810 11:32:48.101987 3, 0xFFFF, sum = 0
7811 11:32:48.105085 4, 0xFFFF, sum = 0
7812 11:32:48.105160 5, 0xFFFF, sum = 0
7813 11:32:48.108490 6, 0xFFFF, sum = 0
7814 11:32:48.108566 7, 0xFFFF, sum = 0
7815 11:32:48.111722 8, 0xFFFF, sum = 0
7816 11:32:48.111798 9, 0xFFFF, sum = 0
7817 11:32:48.115344 10, 0xFFFF, sum = 0
7818 11:32:48.115420 11, 0xFFFF, sum = 0
7819 11:32:48.118397 12, 0xFFFF, sum = 0
7820 11:32:48.118471 13, 0xEFFF, sum = 0
7821 11:32:48.121426 14, 0x0, sum = 1
7822 11:32:48.121501 15, 0x0, sum = 2
7823 11:32:48.124672 16, 0x0, sum = 3
7824 11:32:48.124751 17, 0x0, sum = 4
7825 11:32:48.128278 best_step = 15
7826 11:32:48.128351
7827 11:32:48.128409 ==
7828 11:32:48.131530 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 11:32:48.135142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 11:32:48.135217 ==
7831 11:32:48.138623 RX Vref Scan: 1
7832 11:32:48.138697
7833 11:32:48.138754 Set Vref Range= 24 -> 127
7834 11:32:48.138807
7835 11:32:48.141847 RX Vref 24 -> 127, step: 1
7836 11:32:48.141920
7837 11:32:48.144906 RX Delay 11 -> 252, step: 4
7838 11:32:48.144980
7839 11:32:48.148596 Set Vref, RX VrefLevel [Byte0]: 24
7840 11:32:48.151377 [Byte1]: 24
7841 11:32:48.151451
7842 11:32:48.154706 Set Vref, RX VrefLevel [Byte0]: 25
7843 11:32:48.158390 [Byte1]: 25
7844 11:32:48.158465
7845 11:32:48.161333 Set Vref, RX VrefLevel [Byte0]: 26
7846 11:32:48.164467 [Byte1]: 26
7847 11:32:48.169153
7848 11:32:48.169227 Set Vref, RX VrefLevel [Byte0]: 27
7849 11:32:48.172297 [Byte1]: 27
7850 11:32:48.176600
7851 11:32:48.176669 Set Vref, RX VrefLevel [Byte0]: 28
7852 11:32:48.179820 [Byte1]: 28
7853 11:32:48.183872
7854 11:32:48.183936 Set Vref, RX VrefLevel [Byte0]: 29
7855 11:32:48.187228 [Byte1]: 29
7856 11:32:48.191683
7857 11:32:48.191753 Set Vref, RX VrefLevel [Byte0]: 30
7858 11:32:48.195192 [Byte1]: 30
7859 11:32:48.199413
7860 11:32:48.199483 Set Vref, RX VrefLevel [Byte0]: 31
7861 11:32:48.202799 [Byte1]: 31
7862 11:32:48.207039
7863 11:32:48.207106 Set Vref, RX VrefLevel [Byte0]: 32
7864 11:32:48.209960 [Byte1]: 32
7865 11:32:48.214575
7866 11:32:48.214638 Set Vref, RX VrefLevel [Byte0]: 33
7867 11:32:48.218068 [Byte1]: 33
7868 11:32:48.222260
7869 11:32:48.222321 Set Vref, RX VrefLevel [Byte0]: 34
7870 11:32:48.225448 [Byte1]: 34
7871 11:32:48.229954
7872 11:32:48.230022 Set Vref, RX VrefLevel [Byte0]: 35
7873 11:32:48.233310 [Byte1]: 35
7874 11:32:48.237214
7875 11:32:48.237275 Set Vref, RX VrefLevel [Byte0]: 36
7876 11:32:48.240662 [Byte1]: 36
7877 11:32:48.245547
7878 11:32:48.245607 Set Vref, RX VrefLevel [Byte0]: 37
7879 11:32:48.248148 [Byte1]: 37
7880 11:32:48.252612
7881 11:32:48.252681 Set Vref, RX VrefLevel [Byte0]: 38
7882 11:32:48.256087 [Byte1]: 38
7883 11:32:48.260045
7884 11:32:48.260107 Set Vref, RX VrefLevel [Byte0]: 39
7885 11:32:48.263497 [Byte1]: 39
7886 11:32:48.267600
7887 11:32:48.267673 Set Vref, RX VrefLevel [Byte0]: 40
7888 11:32:48.271135 [Byte1]: 40
7889 11:32:48.275356
7890 11:32:48.275431 Set Vref, RX VrefLevel [Byte0]: 41
7891 11:32:48.278870 [Byte1]: 41
7892 11:32:48.283247
7893 11:32:48.283345 Set Vref, RX VrefLevel [Byte0]: 42
7894 11:32:48.286422 [Byte1]: 42
7895 11:32:48.290883
7896 11:32:48.290981 Set Vref, RX VrefLevel [Byte0]: 43
7897 11:32:48.293882 [Byte1]: 43
7898 11:32:48.298400
7899 11:32:48.298474 Set Vref, RX VrefLevel [Byte0]: 44
7900 11:32:48.301442 [Byte1]: 44
7901 11:32:48.305949
7902 11:32:48.306046 Set Vref, RX VrefLevel [Byte0]: 45
7903 11:32:48.309005 [Byte1]: 45
7904 11:32:48.313572
7905 11:32:48.313646 Set Vref, RX VrefLevel [Byte0]: 46
7906 11:32:48.316678 [Byte1]: 46
7907 11:32:48.321015
7908 11:32:48.321089 Set Vref, RX VrefLevel [Byte0]: 47
7909 11:32:48.324407 [Byte1]: 47
7910 11:32:48.328768
7911 11:32:48.328842 Set Vref, RX VrefLevel [Byte0]: 48
7912 11:32:48.332357 [Byte1]: 48
7913 11:32:48.336245
7914 11:32:48.336319 Set Vref, RX VrefLevel [Byte0]: 49
7915 11:32:48.339532 [Byte1]: 49
7916 11:32:48.344038
7917 11:32:48.344107 Set Vref, RX VrefLevel [Byte0]: 50
7918 11:32:48.347388 [Byte1]: 50
7919 11:32:48.351363
7920 11:32:48.351434 Set Vref, RX VrefLevel [Byte0]: 51
7921 11:32:48.354912 [Byte1]: 51
7922 11:32:48.359016
7923 11:32:48.359085 Set Vref, RX VrefLevel [Byte0]: 52
7924 11:32:48.362869 [Byte1]: 52
7925 11:32:48.367003
7926 11:32:48.367065 Set Vref, RX VrefLevel [Byte0]: 53
7927 11:32:48.370281 [Byte1]: 53
7928 11:32:48.374311
7929 11:32:48.374376 Set Vref, RX VrefLevel [Byte0]: 54
7930 11:32:48.377666 [Byte1]: 54
7931 11:32:48.381810
7932 11:32:48.381872 Set Vref, RX VrefLevel [Byte0]: 55
7933 11:32:48.385039 [Byte1]: 55
7934 11:32:48.389428
7935 11:32:48.389491 Set Vref, RX VrefLevel [Byte0]: 56
7936 11:32:48.392837 [Byte1]: 56
7937 11:32:48.397634
7938 11:32:48.397706 Set Vref, RX VrefLevel [Byte0]: 57
7939 11:32:48.400359 [Byte1]: 57
7940 11:32:48.404929
7941 11:32:48.404998 Set Vref, RX VrefLevel [Byte0]: 58
7942 11:32:48.408061 [Byte1]: 58
7943 11:32:48.412535
7944 11:32:48.412600 Set Vref, RX VrefLevel [Byte0]: 59
7945 11:32:48.415829 [Byte1]: 59
7946 11:32:48.420436
7947 11:32:48.420498 Set Vref, RX VrefLevel [Byte0]: 60
7948 11:32:48.423639 [Byte1]: 60
7949 11:32:48.427644
7950 11:32:48.427713 Set Vref, RX VrefLevel [Byte0]: 61
7951 11:32:48.431564 [Byte1]: 61
7952 11:32:48.435488
7953 11:32:48.435556 Set Vref, RX VrefLevel [Byte0]: 62
7954 11:32:48.438523 [Byte1]: 62
7955 11:32:48.443150
7956 11:32:48.443214 Set Vref, RX VrefLevel [Byte0]: 63
7957 11:32:48.446007 [Byte1]: 63
7958 11:32:48.450725
7959 11:32:48.450982 Set Vref, RX VrefLevel [Byte0]: 64
7960 11:32:48.453871 [Byte1]: 64
7961 11:32:48.457933
7962 11:32:48.458151 Set Vref, RX VrefLevel [Byte0]: 65
7963 11:32:48.461569 [Byte1]: 65
7964 11:32:48.465663
7965 11:32:48.465734 Set Vref, RX VrefLevel [Byte0]: 66
7966 11:32:48.469324 [Byte1]: 66
7967 11:32:48.473625
7968 11:32:48.473699 Set Vref, RX VrefLevel [Byte0]: 67
7969 11:32:48.476864 [Byte1]: 67
7970 11:32:48.480787
7971 11:32:48.480899 Set Vref, RX VrefLevel [Byte0]: 68
7972 11:32:48.483930 [Byte1]: 68
7973 11:32:48.488244
7974 11:32:48.488320 Set Vref, RX VrefLevel [Byte0]: 69
7975 11:32:48.492173 [Byte1]: 69
7976 11:32:48.496259
7977 11:32:48.496329 Set Vref, RX VrefLevel [Byte0]: 70
7978 11:32:48.499710 [Byte1]: 70
7979 11:32:48.504076
7980 11:32:48.504151 Set Vref, RX VrefLevel [Byte0]: 71
7981 11:32:48.507086 [Byte1]: 71
7982 11:32:48.511354
7983 11:32:48.511428 Set Vref, RX VrefLevel [Byte0]: 72
7984 11:32:48.514516 [Byte1]: 72
7985 11:32:48.519238
7986 11:32:48.519312 Set Vref, RX VrefLevel [Byte0]: 73
7987 11:32:48.522204 [Byte1]: 73
7988 11:32:48.526712
7989 11:32:48.526786 Set Vref, RX VrefLevel [Byte0]: 74
7990 11:32:48.530000 [Byte1]: 74
7991 11:32:48.534060
7992 11:32:48.534173 Set Vref, RX VrefLevel [Byte0]: 75
7993 11:32:48.537541 [Byte1]: 75
7994 11:32:48.542297
7995 11:32:48.542371 Set Vref, RX VrefLevel [Byte0]: 76
7996 11:32:48.545329 [Byte1]: 76
7997 11:32:48.549496
7998 11:32:48.549574 Set Vref, RX VrefLevel [Byte0]: 77
7999 11:32:48.552691 [Byte1]: 77
8000 11:32:48.557450
8001 11:32:48.557525 Final RX Vref Byte 0 = 63 to rank0
8002 11:32:48.560554 Final RX Vref Byte 1 = 59 to rank0
8003 11:32:48.563680 Final RX Vref Byte 0 = 63 to rank1
8004 11:32:48.567229 Final RX Vref Byte 1 = 59 to rank1==
8005 11:32:48.570603 Dram Type= 6, Freq= 0, CH_0, rank 0
8006 11:32:48.576837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 11:32:48.576914 ==
8008 11:32:48.576972 DQS Delay:
8009 11:32:48.579913 DQS0 = 0, DQS1 = 0
8010 11:32:48.579988 DQM Delay:
8011 11:32:48.580047 DQM0 = 126, DQM1 = 119
8012 11:32:48.583717 DQ Delay:
8013 11:32:48.586923 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8014 11:32:48.589918 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8015 11:32:48.593509 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8016 11:32:48.597185 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8017 11:32:48.597260
8018 11:32:48.597318
8019 11:32:48.597371
8020 11:32:48.600151 [DramC_TX_OE_Calibration] TA2
8021 11:32:48.603656 Original DQ_B0 (3 6) =30, OEN = 27
8022 11:32:48.606809 Original DQ_B1 (3 6) =30, OEN = 27
8023 11:32:48.610362 24, 0x0, End_B0=24 End_B1=24
8024 11:32:48.610439 25, 0x0, End_B0=25 End_B1=25
8025 11:32:48.613099 26, 0x0, End_B0=26 End_B1=26
8026 11:32:48.616935 27, 0x0, End_B0=27 End_B1=27
8027 11:32:48.620025 28, 0x0, End_B0=28 End_B1=28
8028 11:32:48.623077 29, 0x0, End_B0=29 End_B1=29
8029 11:32:48.623154 30, 0x0, End_B0=30 End_B1=30
8030 11:32:48.626391 31, 0x4141, End_B0=30 End_B1=30
8031 11:32:48.629924 Byte0 end_step=30 best_step=27
8032 11:32:48.633621 Byte1 end_step=30 best_step=27
8033 11:32:48.636487 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 11:32:48.640188 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 11:32:48.640263
8036 11:32:48.640321
8037 11:32:48.646488 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8038 11:32:48.649809 CH0 RK0: MR19=303, MR18=1514
8039 11:32:48.656359 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8040 11:32:48.656434
8041 11:32:48.660014 ----->DramcWriteLeveling(PI) begin...
8042 11:32:48.660091 ==
8043 11:32:48.663304 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 11:32:48.666374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 11:32:48.666450 ==
8046 11:32:48.670081 Write leveling (Byte 0): 35 => 35
8047 11:32:48.672940 Write leveling (Byte 1): 28 => 28
8048 11:32:48.676348 DramcWriteLeveling(PI) end<-----
8049 11:32:48.676423
8050 11:32:48.676480 ==
8051 11:32:48.680024 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 11:32:48.682762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 11:32:48.682837 ==
8054 11:32:48.686092 [Gating] SW mode calibration
8055 11:32:48.693061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 11:32:48.699828 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8057 11:32:48.702879 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 11:32:48.709471 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 11:32:48.713262 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 11:32:48.716531 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8061 11:32:48.722628 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8062 11:32:48.726288 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8063 11:32:48.729667 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:32:48.732641 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:32:48.739502 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 11:32:48.742444 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:32:48.746072 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8068 11:32:48.752333 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8069 11:32:48.755857 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8070 11:32:48.759074 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:32:48.765552 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:32:48.769114 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:32:48.772548 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:32:48.778973 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:32:48.782397 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8076 11:32:48.785671 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8077 11:32:48.792134 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8078 11:32:48.795669 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8079 11:32:48.798736 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:32:48.805322 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:32:48.808876 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 11:32:48.812350 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:32:48.819005 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:32:48.822560 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 11:32:48.825422 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8086 11:32:48.832689 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 11:32:48.835557 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:32:48.838334 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:32:48.845044 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:32:48.848397 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:32:48.851835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:32:48.858247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:32:48.861411 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:32:48.865227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:32:48.871523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:32:48.875320 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:32:48.878448 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:32:48.884859 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:32:48.887930 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8100 11:32:48.891295 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 11:32:48.898051 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8102 11:32:48.898133 Total UI for P1: 0, mck2ui 16
8103 11:32:48.904982 best dqsien dly found for B0: ( 1, 9, 10)
8104 11:32:48.907922 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 11:32:48.911058 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 11:32:48.914621 Total UI for P1: 0, mck2ui 16
8107 11:32:48.917840 best dqsien dly found for B1: ( 1, 9, 18)
8108 11:32:48.921452 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8109 11:32:48.924710 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8110 11:32:48.924784
8111 11:32:48.931255 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8112 11:32:48.934121 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8113 11:32:48.937432 [Gating] SW calibration Done
8114 11:32:48.937506 ==
8115 11:32:48.940704 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 11:32:48.944482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 11:32:48.944557 ==
8118 11:32:48.944615 RX Vref Scan: 0
8119 11:32:48.944669
8120 11:32:48.947579 RX Vref 0 -> 0, step: 1
8121 11:32:48.947654
8122 11:32:48.951001 RX Delay 0 -> 252, step: 8
8123 11:32:48.954368 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8124 11:32:48.957839 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8125 11:32:48.964475 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8126 11:32:48.967543 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8127 11:32:48.971100 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8128 11:32:48.973823 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8129 11:32:48.977346 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8130 11:32:48.984073 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8131 11:32:48.987407 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8132 11:32:48.990757 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8133 11:32:48.993804 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8134 11:32:48.997445 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8135 11:32:49.003937 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8136 11:32:49.006952 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8137 11:32:49.010215 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8138 11:32:49.013729 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8139 11:32:49.013826 ==
8140 11:32:49.016988 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:32:49.023505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:32:49.023580 ==
8143 11:32:49.023637 DQS Delay:
8144 11:32:49.027267 DQS0 = 0, DQS1 = 0
8145 11:32:49.027341 DQM Delay:
8146 11:32:49.027403 DQM0 = 128, DQM1 = 122
8147 11:32:49.030497 DQ Delay:
8148 11:32:49.033317 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8149 11:32:49.036716 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8150 11:32:49.040181 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8151 11:32:49.043386 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8152 11:32:49.043460
8153 11:32:49.043518
8154 11:32:49.043571 ==
8155 11:32:49.046781 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 11:32:49.053402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 11:32:49.053477 ==
8158 11:32:49.053535
8159 11:32:49.053588
8160 11:32:49.053639 TX Vref Scan disable
8161 11:32:49.056749 == TX Byte 0 ==
8162 11:32:49.059906 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8163 11:32:49.063284 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8164 11:32:49.066435 == TX Byte 1 ==
8165 11:32:49.070295 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8166 11:32:49.076727 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8167 11:32:49.076801 ==
8168 11:32:49.079887 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:32:49.083113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:32:49.083189 ==
8171 11:32:49.097666
8172 11:32:49.100616 TX Vref early break, caculate TX vref
8173 11:32:49.104672 TX Vref=16, minBit 7, minWin=22, winSum=367
8174 11:32:49.107364 TX Vref=18, minBit 8, minWin=22, winSum=376
8175 11:32:49.110769 TX Vref=20, minBit 9, minWin=22, winSum=382
8176 11:32:49.114407 TX Vref=22, minBit 9, minWin=23, winSum=394
8177 11:32:49.117493 TX Vref=24, minBit 8, minWin=23, winSum=395
8178 11:32:49.123976 TX Vref=26, minBit 8, minWin=24, winSum=407
8179 11:32:49.127324 TX Vref=28, minBit 3, minWin=24, winSum=409
8180 11:32:49.130495 TX Vref=30, minBit 8, minWin=24, winSum=408
8181 11:32:49.133962 TX Vref=32, minBit 8, minWin=23, winSum=399
8182 11:32:49.137310 TX Vref=34, minBit 8, minWin=23, winSum=390
8183 11:32:49.140576 TX Vref=36, minBit 8, minWin=22, winSum=383
8184 11:32:49.147062 [TxChooseVref] Worse bit 3, Min win 24, Win sum 409, Final Vref 28
8185 11:32:49.147138
8186 11:32:49.151120 Final TX Range 0 Vref 28
8187 11:32:49.151197
8188 11:32:49.151255 ==
8189 11:32:49.153689 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:32:49.157076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:32:49.157152 ==
8192 11:32:49.157210
8193 11:32:49.157264
8194 11:32:49.160712 TX Vref Scan disable
8195 11:32:49.167107 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8196 11:32:49.167183 == TX Byte 0 ==
8197 11:32:49.170209 u2DelayCellOfst[0]=11 cells (3 PI)
8198 11:32:49.173685 u2DelayCellOfst[1]=18 cells (5 PI)
8199 11:32:49.177159 u2DelayCellOfst[2]=11 cells (3 PI)
8200 11:32:49.180566 u2DelayCellOfst[3]=11 cells (3 PI)
8201 11:32:49.183425 u2DelayCellOfst[4]=7 cells (2 PI)
8202 11:32:49.187316 u2DelayCellOfst[5]=0 cells (0 PI)
8203 11:32:49.190319 u2DelayCellOfst[6]=15 cells (4 PI)
8204 11:32:49.193509 u2DelayCellOfst[7]=18 cells (5 PI)
8205 11:32:49.197003 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8206 11:32:49.200446 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8207 11:32:49.203831 == TX Byte 1 ==
8208 11:32:49.207028 u2DelayCellOfst[8]=0 cells (0 PI)
8209 11:32:49.210469 u2DelayCellOfst[9]=0 cells (0 PI)
8210 11:32:49.213739 u2DelayCellOfst[10]=11 cells (3 PI)
8211 11:32:49.213814 u2DelayCellOfst[11]=7 cells (2 PI)
8212 11:32:49.216773 u2DelayCellOfst[12]=15 cells (4 PI)
8213 11:32:49.220062 u2DelayCellOfst[13]=15 cells (4 PI)
8214 11:32:49.223380 u2DelayCellOfst[14]=15 cells (4 PI)
8215 11:32:49.226843 u2DelayCellOfst[15]=11 cells (3 PI)
8216 11:32:49.233261 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8217 11:32:49.236654 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8218 11:32:49.236729 DramC Write-DBI on
8219 11:32:49.236787 ==
8220 11:32:49.240318 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 11:32:49.246604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 11:32:49.246679 ==
8223 11:32:49.246737
8224 11:32:49.246790
8225 11:32:49.246841 TX Vref Scan disable
8226 11:32:49.250760 == TX Byte 0 ==
8227 11:32:49.254526 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8228 11:32:49.257396 == TX Byte 1 ==
8229 11:32:49.261030 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8230 11:32:49.264276 DramC Write-DBI off
8231 11:32:49.264352
8232 11:32:49.264410 [DATLAT]
8233 11:32:49.264464 Freq=1600, CH0 RK1
8234 11:32:49.264516
8235 11:32:49.267550 DATLAT Default: 0xf
8236 11:32:49.267625 0, 0xFFFF, sum = 0
8237 11:32:49.270639 1, 0xFFFF, sum = 0
8238 11:32:49.274042 2, 0xFFFF, sum = 0
8239 11:32:49.274182 3, 0xFFFF, sum = 0
8240 11:32:49.277326 4, 0xFFFF, sum = 0
8241 11:32:49.277403 5, 0xFFFF, sum = 0
8242 11:32:49.280822 6, 0xFFFF, sum = 0
8243 11:32:49.280899 7, 0xFFFF, sum = 0
8244 11:32:49.284354 8, 0xFFFF, sum = 0
8245 11:32:49.284431 9, 0xFFFF, sum = 0
8246 11:32:49.287337 10, 0xFFFF, sum = 0
8247 11:32:49.287413 11, 0xFFFF, sum = 0
8248 11:32:49.290767 12, 0xFFFF, sum = 0
8249 11:32:49.290843 13, 0xCFFF, sum = 0
8250 11:32:49.294085 14, 0x0, sum = 1
8251 11:32:49.294168 15, 0x0, sum = 2
8252 11:32:49.297256 16, 0x0, sum = 3
8253 11:32:49.297332 17, 0x0, sum = 4
8254 11:32:49.300695 best_step = 15
8255 11:32:49.300769
8256 11:32:49.300827 ==
8257 11:32:49.304021 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 11:32:49.307363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:32:49.307438 ==
8260 11:32:49.310888 RX Vref Scan: 0
8261 11:32:49.310963
8262 11:32:49.311021 RX Vref 0 -> 0, step: 1
8263 11:32:49.311075
8264 11:32:49.313852 RX Delay 3 -> 252, step: 4
8265 11:32:49.317684 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8266 11:32:49.323789 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8267 11:32:49.327364 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8268 11:32:49.330242 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8269 11:32:49.333587 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8270 11:32:49.337083 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8271 11:32:49.343809 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8272 11:32:49.346857 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8273 11:32:49.350640 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8274 11:32:49.353775 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8275 11:32:49.356815 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8276 11:32:49.363949 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8277 11:32:49.366879 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8278 11:32:49.370215 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8279 11:32:49.373218 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8280 11:32:49.380394 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8281 11:32:49.380469 ==
8282 11:32:49.383620 Dram Type= 6, Freq= 0, CH_0, rank 1
8283 11:32:49.387113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:32:49.387188 ==
8285 11:32:49.387247 DQS Delay:
8286 11:32:49.390058 DQS0 = 0, DQS1 = 0
8287 11:32:49.390180 DQM Delay:
8288 11:32:49.393285 DQM0 = 124, DQM1 = 118
8289 11:32:49.393359 DQ Delay:
8290 11:32:49.396493 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8291 11:32:49.399757 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8292 11:32:49.403245 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8293 11:32:49.406576 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8294 11:32:49.406651
8295 11:32:49.409503
8296 11:32:49.409577
8297 11:32:49.409636 [DramC_TX_OE_Calibration] TA2
8298 11:32:49.412790 Original DQ_B0 (3 6) =30, OEN = 27
8299 11:32:49.416266 Original DQ_B1 (3 6) =30, OEN = 27
8300 11:32:49.419682 24, 0x0, End_B0=24 End_B1=24
8301 11:32:49.422976 25, 0x0, End_B0=25 End_B1=25
8302 11:32:49.426211 26, 0x0, End_B0=26 End_B1=26
8303 11:32:49.426287 27, 0x0, End_B0=27 End_B1=27
8304 11:32:49.429403 28, 0x0, End_B0=28 End_B1=28
8305 11:32:49.433016 29, 0x0, End_B0=29 End_B1=29
8306 11:32:49.436074 30, 0x0, End_B0=30 End_B1=30
8307 11:32:49.439462 31, 0x4141, End_B0=30 End_B1=30
8308 11:32:49.439539 Byte0 end_step=30 best_step=27
8309 11:32:49.442592 Byte1 end_step=30 best_step=27
8310 11:32:49.445969 Byte0 TX OE(2T, 0.5T) = (3, 3)
8311 11:32:49.449585 Byte1 TX OE(2T, 0.5T) = (3, 3)
8312 11:32:49.449661
8313 11:32:49.449719
8314 11:32:49.459580 [DQSOSCAuto] RK1, (LSB)MR18= 0x2715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8315 11:32:49.459658 CH0 RK1: MR19=303, MR18=2715
8316 11:32:49.466060 CH0_RK1: MR19=0x303, MR18=0x2715, DQSOSC=390, MR23=63, INC=24, DEC=16
8317 11:32:49.469202 [RxdqsGatingPostProcess] freq 1600
8318 11:32:49.475749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8319 11:32:49.478860 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 11:32:49.482561 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 11:32:49.485838 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 11:32:49.489185 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 11:32:49.489261 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 11:32:49.492229 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 11:32:49.495512 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 11:32:49.498668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 11:32:49.501998 Pre-setting of DQS Precalculation
8328 11:32:49.508500 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8329 11:32:49.508577 ==
8330 11:32:49.512215 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 11:32:49.515751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:32:49.515828 ==
8333 11:32:49.522072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 11:32:49.525094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 11:32:49.528510 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 11:32:49.535084 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 11:32:49.544030 [CA 0] Center 41 (12~71) winsize 60
8338 11:32:49.547306 [CA 1] Center 42 (13~72) winsize 60
8339 11:32:49.550868 [CA 2] Center 38 (9~67) winsize 59
8340 11:32:49.554376 [CA 3] Center 37 (8~66) winsize 59
8341 11:32:49.557478 [CA 4] Center 37 (8~67) winsize 60
8342 11:32:49.560971 [CA 5] Center 36 (7~66) winsize 60
8343 11:32:49.561047
8344 11:32:49.564573 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 11:32:49.564648
8346 11:32:49.567706 [CATrainingPosCal] consider 1 rank data
8347 11:32:49.570724 u2DelayCellTimex100 = 258/100 ps
8348 11:32:49.574135 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8349 11:32:49.580746 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8350 11:32:49.584167 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8351 11:32:49.587273 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8352 11:32:49.590452 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8353 11:32:49.594011 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8354 11:32:49.594086
8355 11:32:49.597119 CA PerBit enable=1, Macro0, CA PI delay=36
8356 11:32:49.597193
8357 11:32:49.600442 [CBTSetCACLKResult] CA Dly = 36
8358 11:32:49.603545 CS Dly: 9 (0~40)
8359 11:32:49.607064 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 11:32:49.609988 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 11:32:49.610089 ==
8362 11:32:49.613431 Dram Type= 6, Freq= 0, CH_1, rank 1
8363 11:32:49.616874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 11:32:49.619999 ==
8365 11:32:49.623383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8366 11:32:49.626840 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8367 11:32:49.633391 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8368 11:32:49.639802 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8369 11:32:49.647579 [CA 0] Center 42 (13~72) winsize 60
8370 11:32:49.650534 [CA 1] Center 43 (13~73) winsize 61
8371 11:32:49.653698 [CA 2] Center 38 (9~67) winsize 59
8372 11:32:49.656768 [CA 3] Center 36 (7~66) winsize 60
8373 11:32:49.660519 [CA 4] Center 38 (8~68) winsize 61
8374 11:32:49.663503 [CA 5] Center 36 (6~67) winsize 62
8375 11:32:49.663597
8376 11:32:49.667023 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8377 11:32:49.667117
8378 11:32:49.670342 [CATrainingPosCal] consider 2 rank data
8379 11:32:49.674281 u2DelayCellTimex100 = 258/100 ps
8380 11:32:49.676864 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8381 11:32:49.683603 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8382 11:32:49.686801 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8383 11:32:49.690224 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8384 11:32:49.693634 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8385 11:32:49.697126 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8386 11:32:49.697223
8387 11:32:49.700560 CA PerBit enable=1, Macro0, CA PI delay=36
8388 11:32:49.700652
8389 11:32:49.703367 [CBTSetCACLKResult] CA Dly = 36
8390 11:32:49.706613 CS Dly: 10 (0~43)
8391 11:32:49.710096 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8392 11:32:49.713456 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8393 11:32:49.713546
8394 11:32:49.716985 ----->DramcWriteLeveling(PI) begin...
8395 11:32:49.717075 ==
8396 11:32:49.719925 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:32:49.726987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:32:49.727068 ==
8399 11:32:49.730003 Write leveling (Byte 0): 25 => 25
8400 11:32:49.730078 Write leveling (Byte 1): 27 => 27
8401 11:32:49.733272 DramcWriteLeveling(PI) end<-----
8402 11:32:49.733347
8403 11:32:49.733404 ==
8404 11:32:49.736586 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 11:32:49.743819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 11:32:49.743894 ==
8407 11:32:49.746868 [Gating] SW mode calibration
8408 11:32:49.753365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8409 11:32:49.756646 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8410 11:32:49.763250 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 11:32:49.766653 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 11:32:49.769933 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 11:32:49.776141 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8414 11:32:49.779761 1 4 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8415 11:32:49.782690 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:32:49.789391 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:32:49.792717 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:32:49.796166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:32:49.802569 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:32:49.806021 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 11:32:49.809610 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
8422 11:32:49.815804 1 5 16 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
8423 11:32:49.819297 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:32:49.822952 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:32:49.829449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:32:49.832385 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:32:49.836090 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:32:49.842493 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:32:49.845989 1 6 12 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
8430 11:32:49.849522 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:32:49.855808 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:32:49.858912 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:32:49.862402 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:32:49.865861 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:32:49.872790 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:32:49.875804 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:32:49.879338 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:32:49.885972 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8439 11:32:49.889096 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:32:49.892730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:32:49.899061 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:32:49.902304 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:32:49.905299 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:32:49.912663 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:32:49.915508 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:32:49.918678 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:32:49.925612 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:32:49.928575 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:32:49.931898 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:32:49.938755 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:32:49.942023 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:32:49.945406 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:32:49.952028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:32:49.955015 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8455 11:32:49.958668 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 11:32:49.961695 Total UI for P1: 0, mck2ui 16
8457 11:32:49.965201 best dqsien dly found for B0: ( 1, 9, 16)
8458 11:32:49.969017 Total UI for P1: 0, mck2ui 16
8459 11:32:49.971740 best dqsien dly found for B1: ( 1, 9, 16)
8460 11:32:49.975014 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8461 11:32:49.978516 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8462 11:32:49.978607
8463 11:32:49.984973 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8464 11:32:49.988414 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8465 11:32:49.991457 [Gating] SW calibration Done
8466 11:32:49.991546 ==
8467 11:32:49.994777 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 11:32:49.998604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 11:32:49.998690 ==
8470 11:32:49.998754 RX Vref Scan: 0
8471 11:32:49.998836
8472 11:32:50.001964 RX Vref 0 -> 0, step: 1
8473 11:32:50.002053
8474 11:32:50.005212 RX Delay 0 -> 252, step: 8
8475 11:32:50.008529 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8476 11:32:50.011812 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8477 11:32:50.018036 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8478 11:32:50.021326 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8479 11:32:50.024538 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8480 11:32:50.027862 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8481 11:32:50.031700 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8482 11:32:50.035043 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8483 11:32:50.041464 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8484 11:32:50.044840 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8485 11:32:50.048268 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8486 11:32:50.051454 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8487 11:32:50.057837 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8488 11:32:50.061200 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8489 11:32:50.065429 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8490 11:32:50.067643 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8491 11:32:50.067718 ==
8492 11:32:50.071074 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:32:50.077992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:32:50.078067 ==
8495 11:32:50.078168 DQS Delay:
8496 11:32:50.078223 DQS0 = 0, DQS1 = 0
8497 11:32:50.081240 DQM Delay:
8498 11:32:50.081327 DQM0 = 132, DQM1 = 126
8499 11:32:50.084498 DQ Delay:
8500 11:32:50.087611 DQ0 =135, DQ1 =127, DQ2 =123, DQ3 =131
8501 11:32:50.091016 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8502 11:32:50.094346 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8503 11:32:50.097615 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8504 11:32:50.097690
8505 11:32:50.097747
8506 11:32:50.097800 ==
8507 11:32:50.100953 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 11:32:50.104018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 11:32:50.107461 ==
8510 11:32:50.107535
8511 11:32:50.107592
8512 11:32:50.107645 TX Vref Scan disable
8513 11:32:50.110565 == TX Byte 0 ==
8514 11:32:50.114027 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8515 11:32:50.117397 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8516 11:32:50.120226 == TX Byte 1 ==
8517 11:32:50.123975 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8518 11:32:50.127170 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 11:32:50.130428 ==
8520 11:32:50.133614 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:32:50.137095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 11:32:50.137189 ==
8523 11:32:50.150441
8524 11:32:50.153623 TX Vref early break, caculate TX vref
8525 11:32:50.157518 TX Vref=16, minBit 5, minWin=22, winSum=369
8526 11:32:50.160380 TX Vref=18, minBit 12, minWin=22, winSum=376
8527 11:32:50.163844 TX Vref=20, minBit 1, minWin=23, winSum=386
8528 11:32:50.167491 TX Vref=22, minBit 12, minWin=23, winSum=396
8529 11:32:50.170400 TX Vref=24, minBit 11, minWin=24, winSum=409
8530 11:32:50.176928 TX Vref=26, minBit 5, minWin=25, winSum=414
8531 11:32:50.180338 TX Vref=28, minBit 1, minWin=25, winSum=419
8532 11:32:50.183561 TX Vref=30, minBit 1, minWin=25, winSum=419
8533 11:32:50.186918 TX Vref=32, minBit 0, minWin=24, winSum=406
8534 11:32:50.190060 TX Vref=34, minBit 0, minWin=24, winSum=398
8535 11:32:50.193736 TX Vref=36, minBit 1, minWin=23, winSum=389
8536 11:32:50.200087 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
8537 11:32:50.200158
8538 11:32:50.203772 Final TX Range 0 Vref 28
8539 11:32:50.203838
8540 11:32:50.203893 ==
8541 11:32:50.206551 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 11:32:50.209894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 11:32:50.209980 ==
8544 11:32:50.213680
8545 11:32:50.213772
8546 11:32:50.213856 TX Vref Scan disable
8547 11:32:50.219993 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8548 11:32:50.220080 == TX Byte 0 ==
8549 11:32:50.222937 u2DelayCellOfst[0]=18 cells (5 PI)
8550 11:32:50.226384 u2DelayCellOfst[1]=15 cells (4 PI)
8551 11:32:50.229844 u2DelayCellOfst[2]=0 cells (0 PI)
8552 11:32:50.233046 u2DelayCellOfst[3]=7 cells (2 PI)
8553 11:32:50.236398 u2DelayCellOfst[4]=7 cells (2 PI)
8554 11:32:50.239713 u2DelayCellOfst[5]=18 cells (5 PI)
8555 11:32:50.242859 u2DelayCellOfst[6]=18 cells (5 PI)
8556 11:32:50.246535 u2DelayCellOfst[7]=7 cells (2 PI)
8557 11:32:50.250044 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8558 11:32:50.252852 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8559 11:32:50.256253 == TX Byte 1 ==
8560 11:32:50.259539 u2DelayCellOfst[8]=0 cells (0 PI)
8561 11:32:50.263043 u2DelayCellOfst[9]=7 cells (2 PI)
8562 11:32:50.266028 u2DelayCellOfst[10]=15 cells (4 PI)
8563 11:32:50.269386 u2DelayCellOfst[11]=7 cells (2 PI)
8564 11:32:50.269474 u2DelayCellOfst[12]=18 cells (5 PI)
8565 11:32:50.272563 u2DelayCellOfst[13]=22 cells (6 PI)
8566 11:32:50.276115 u2DelayCellOfst[14]=22 cells (6 PI)
8567 11:32:50.279432 u2DelayCellOfst[15]=22 cells (6 PI)
8568 11:32:50.286376 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8569 11:32:50.289434 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8570 11:32:50.289524 DramC Write-DBI on
8571 11:32:50.292596 ==
8572 11:32:50.296136 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 11:32:50.299004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 11:32:50.299092 ==
8575 11:32:50.299172
8576 11:32:50.299227
8577 11:32:50.302664 TX Vref Scan disable
8578 11:32:50.302751 == TX Byte 0 ==
8579 11:32:50.309189 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8580 11:32:50.309280 == TX Byte 1 ==
8581 11:32:50.312594 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8582 11:32:50.315923 DramC Write-DBI off
8583 11:32:50.316012
8584 11:32:50.316092 [DATLAT]
8585 11:32:50.319053 Freq=1600, CH1 RK0
8586 11:32:50.319139
8587 11:32:50.319220 DATLAT Default: 0xf
8588 11:32:50.322279 0, 0xFFFF, sum = 0
8589 11:32:50.322370 1, 0xFFFF, sum = 0
8590 11:32:50.325642 2, 0xFFFF, sum = 0
8591 11:32:50.325732 3, 0xFFFF, sum = 0
8592 11:32:50.328955 4, 0xFFFF, sum = 0
8593 11:32:50.329047 5, 0xFFFF, sum = 0
8594 11:32:50.332372 6, 0xFFFF, sum = 0
8595 11:32:50.332466 7, 0xFFFF, sum = 0
8596 11:32:50.335604 8, 0xFFFF, sum = 0
8597 11:32:50.335694 9, 0xFFFF, sum = 0
8598 11:32:50.338858 10, 0xFFFF, sum = 0
8599 11:32:50.342217 11, 0xFFFF, sum = 0
8600 11:32:50.342286 12, 0xFFFF, sum = 0
8601 11:32:50.345868 13, 0x8FFF, sum = 0
8602 11:32:50.345957 14, 0x0, sum = 1
8603 11:32:50.348927 15, 0x0, sum = 2
8604 11:32:50.349018 16, 0x0, sum = 3
8605 11:32:50.352267 17, 0x0, sum = 4
8606 11:32:50.352359 best_step = 15
8607 11:32:50.352444
8608 11:32:50.352523 ==
8609 11:32:50.355455 Dram Type= 6, Freq= 0, CH_1, rank 0
8610 11:32:50.358580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8611 11:32:50.358669 ==
8612 11:32:50.362081 RX Vref Scan: 1
8613 11:32:50.362155
8614 11:32:50.365246 Set Vref Range= 24 -> 127
8615 11:32:50.365334
8616 11:32:50.365414 RX Vref 24 -> 127, step: 1
8617 11:32:50.365492
8618 11:32:50.368911 RX Delay 11 -> 252, step: 4
8619 11:32:50.368999
8620 11:32:50.372008 Set Vref, RX VrefLevel [Byte0]: 24
8621 11:32:50.375437 [Byte1]: 24
8622 11:32:50.378697
8623 11:32:50.378763 Set Vref, RX VrefLevel [Byte0]: 25
8624 11:32:50.382035 [Byte1]: 25
8625 11:32:50.386427
8626 11:32:50.386498 Set Vref, RX VrefLevel [Byte0]: 26
8627 11:32:50.390109 [Byte1]: 26
8628 11:32:50.394010
8629 11:32:50.394094 Set Vref, RX VrefLevel [Byte0]: 27
8630 11:32:50.397346 [Byte1]: 27
8631 11:32:50.401696
8632 11:32:50.401788 Set Vref, RX VrefLevel [Byte0]: 28
8633 11:32:50.405188 [Byte1]: 28
8634 11:32:50.409345
8635 11:32:50.409414 Set Vref, RX VrefLevel [Byte0]: 29
8636 11:32:50.412645 [Byte1]: 29
8637 11:32:50.416957
8638 11:32:50.417043 Set Vref, RX VrefLevel [Byte0]: 30
8639 11:32:50.420002 [Byte1]: 30
8640 11:32:50.424430
8641 11:32:50.424499 Set Vref, RX VrefLevel [Byte0]: 31
8642 11:32:50.427706 [Byte1]: 31
8643 11:32:50.432061
8644 11:32:50.432136 Set Vref, RX VrefLevel [Byte0]: 32
8645 11:32:50.435415 [Byte1]: 32
8646 11:32:50.439647
8647 11:32:50.439721 Set Vref, RX VrefLevel [Byte0]: 33
8648 11:32:50.442836 [Byte1]: 33
8649 11:32:50.447286
8650 11:32:50.447363 Set Vref, RX VrefLevel [Byte0]: 34
8651 11:32:50.450905 [Byte1]: 34
8652 11:32:50.454914
8653 11:32:50.454989 Set Vref, RX VrefLevel [Byte0]: 35
8654 11:32:50.458117 [Byte1]: 35
8655 11:32:50.462742
8656 11:32:50.462816 Set Vref, RX VrefLevel [Byte0]: 36
8657 11:32:50.465901 [Byte1]: 36
8658 11:32:50.470214
8659 11:32:50.470282 Set Vref, RX VrefLevel [Byte0]: 37
8660 11:32:50.473541 [Byte1]: 37
8661 11:32:50.478135
8662 11:32:50.478223 Set Vref, RX VrefLevel [Byte0]: 38
8663 11:32:50.481041 [Byte1]: 38
8664 11:32:50.485353
8665 11:32:50.485429 Set Vref, RX VrefLevel [Byte0]: 39
8666 11:32:50.488650 [Byte1]: 39
8667 11:32:50.492841
8668 11:32:50.492914 Set Vref, RX VrefLevel [Byte0]: 40
8669 11:32:50.496635 [Byte1]: 40
8670 11:32:50.500683
8671 11:32:50.500757 Set Vref, RX VrefLevel [Byte0]: 41
8672 11:32:50.503943 [Byte1]: 41
8673 11:32:50.508305
8674 11:32:50.508380 Set Vref, RX VrefLevel [Byte0]: 42
8675 11:32:50.511720 [Byte1]: 42
8676 11:32:50.516300
8677 11:32:50.516379 Set Vref, RX VrefLevel [Byte0]: 43
8678 11:32:50.519001 [Byte1]: 43
8679 11:32:50.523242
8680 11:32:50.523316 Set Vref, RX VrefLevel [Byte0]: 44
8681 11:32:50.526788 [Byte1]: 44
8682 11:32:50.531196
8683 11:32:50.531270 Set Vref, RX VrefLevel [Byte0]: 45
8684 11:32:50.534392 [Byte1]: 45
8685 11:32:50.538658
8686 11:32:50.538732 Set Vref, RX VrefLevel [Byte0]: 46
8687 11:32:50.542076 [Byte1]: 46
8688 11:32:50.546067
8689 11:32:50.546179 Set Vref, RX VrefLevel [Byte0]: 47
8690 11:32:50.550005 [Byte1]: 47
8691 11:32:50.553869
8692 11:32:50.553943 Set Vref, RX VrefLevel [Byte0]: 48
8693 11:32:50.557427 [Byte1]: 48
8694 11:32:50.561318
8695 11:32:50.561392 Set Vref, RX VrefLevel [Byte0]: 49
8696 11:32:50.564924 [Byte1]: 49
8697 11:32:50.569300
8698 11:32:50.569399 Set Vref, RX VrefLevel [Byte0]: 50
8699 11:32:50.572564 [Byte1]: 50
8700 11:32:50.577155
8701 11:32:50.577230 Set Vref, RX VrefLevel [Byte0]: 51
8702 11:32:50.580005 [Byte1]: 51
8703 11:32:50.584226
8704 11:32:50.584301 Set Vref, RX VrefLevel [Byte0]: 52
8705 11:32:50.587622 [Byte1]: 52
8706 11:32:50.591812
8707 11:32:50.591887 Set Vref, RX VrefLevel [Byte0]: 53
8708 11:32:50.595144 [Byte1]: 53
8709 11:32:50.599861
8710 11:32:50.599935 Set Vref, RX VrefLevel [Byte0]: 54
8711 11:32:50.602670 [Byte1]: 54
8712 11:32:50.607049
8713 11:32:50.607123 Set Vref, RX VrefLevel [Byte0]: 55
8714 11:32:50.610381 [Byte1]: 55
8715 11:32:50.614620
8716 11:32:50.614695 Set Vref, RX VrefLevel [Byte0]: 56
8717 11:32:50.617968 [Byte1]: 56
8718 11:32:50.622501
8719 11:32:50.622601 Set Vref, RX VrefLevel [Byte0]: 57
8720 11:32:50.626000 [Byte1]: 57
8721 11:32:50.629933
8722 11:32:50.630007 Set Vref, RX VrefLevel [Byte0]: 58
8723 11:32:50.633485 [Byte1]: 58
8724 11:32:50.637712
8725 11:32:50.637787 Set Vref, RX VrefLevel [Byte0]: 59
8726 11:32:50.640932 [Byte1]: 59
8727 11:32:50.645336
8728 11:32:50.645411 Set Vref, RX VrefLevel [Byte0]: 60
8729 11:32:50.648653 [Byte1]: 60
8730 11:32:50.653287
8731 11:32:50.653362 Set Vref, RX VrefLevel [Byte0]: 61
8732 11:32:50.656228 [Byte1]: 61
8733 11:32:50.660759
8734 11:32:50.660834 Set Vref, RX VrefLevel [Byte0]: 62
8735 11:32:50.663668 [Byte1]: 62
8736 11:32:50.668434
8737 11:32:50.668509 Set Vref, RX VrefLevel [Byte0]: 63
8738 11:32:50.671597 [Byte1]: 63
8739 11:32:50.675469
8740 11:32:50.675570 Set Vref, RX VrefLevel [Byte0]: 64
8741 11:32:50.679170 [Byte1]: 64
8742 11:32:50.683293
8743 11:32:50.683368 Set Vref, RX VrefLevel [Byte0]: 65
8744 11:32:50.686804 [Byte1]: 65
8745 11:32:50.690960
8746 11:32:50.691035 Set Vref, RX VrefLevel [Byte0]: 66
8747 11:32:50.694430 [Byte1]: 66
8748 11:32:50.698279
8749 11:32:50.698354 Set Vref, RX VrefLevel [Byte0]: 67
8750 11:32:50.701919 [Byte1]: 67
8751 11:32:50.706195
8752 11:32:50.706270 Set Vref, RX VrefLevel [Byte0]: 68
8753 11:32:50.709303 [Byte1]: 68
8754 11:32:50.714049
8755 11:32:50.714161 Set Vref, RX VrefLevel [Byte0]: 69
8756 11:32:50.717453 [Byte1]: 69
8757 11:32:50.721613
8758 11:32:50.721688 Set Vref, RX VrefLevel [Byte0]: 70
8759 11:32:50.724950 [Byte1]: 70
8760 11:32:50.729024
8761 11:32:50.729100 Set Vref, RX VrefLevel [Byte0]: 71
8762 11:32:50.732146 [Byte1]: 71
8763 11:32:50.736612
8764 11:32:50.736688 Final RX Vref Byte 0 = 60 to rank0
8765 11:32:50.740047 Final RX Vref Byte 1 = 56 to rank0
8766 11:32:50.743211 Final RX Vref Byte 0 = 60 to rank1
8767 11:32:50.747050 Final RX Vref Byte 1 = 56 to rank1==
8768 11:32:50.749505 Dram Type= 6, Freq= 0, CH_1, rank 0
8769 11:32:50.756483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 11:32:50.756561 ==
8771 11:32:50.756620 DQS Delay:
8772 11:32:50.759965 DQS0 = 0, DQS1 = 0
8773 11:32:50.760041 DQM Delay:
8774 11:32:50.760099 DQM0 = 130, DQM1 = 123
8775 11:32:50.762830 DQ Delay:
8776 11:32:50.766643 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8777 11:32:50.769485 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8778 11:32:50.773054 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8779 11:32:50.776409 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8780 11:32:50.776484
8781 11:32:50.776542
8782 11:32:50.776595
8783 11:32:50.779314 [DramC_TX_OE_Calibration] TA2
8784 11:32:50.782676 Original DQ_B0 (3 6) =30, OEN = 27
8785 11:32:50.786414 Original DQ_B1 (3 6) =30, OEN = 27
8786 11:32:50.789268 24, 0x0, End_B0=24 End_B1=24
8787 11:32:50.792490 25, 0x0, End_B0=25 End_B1=25
8788 11:32:50.792559 26, 0x0, End_B0=26 End_B1=26
8789 11:32:50.795844 27, 0x0, End_B0=27 End_B1=27
8790 11:32:50.799368 28, 0x0, End_B0=28 End_B1=28
8791 11:32:50.802387 29, 0x0, End_B0=29 End_B1=29
8792 11:32:50.802453 30, 0x0, End_B0=30 End_B1=30
8793 11:32:50.806324 31, 0x4141, End_B0=30 End_B1=30
8794 11:32:50.809348 Byte0 end_step=30 best_step=27
8795 11:32:50.812661 Byte1 end_step=30 best_step=27
8796 11:32:50.815933 Byte0 TX OE(2T, 0.5T) = (3, 3)
8797 11:32:50.820062 Byte1 TX OE(2T, 0.5T) = (3, 3)
8798 11:32:50.820132
8799 11:32:50.820189
8800 11:32:50.826203 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8801 11:32:50.828984 CH1 RK0: MR19=303, MR18=80D
8802 11:32:50.836033 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8803 11:32:50.836114
8804 11:32:50.838876 ----->DramcWriteLeveling(PI) begin...
8805 11:32:50.838986 ==
8806 11:32:50.842574 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 11:32:50.845435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 11:32:50.845538 ==
8809 11:32:50.849022 Write leveling (Byte 0): 23 => 23
8810 11:32:50.852358 Write leveling (Byte 1): 28 => 28
8811 11:32:50.855982 DramcWriteLeveling(PI) end<-----
8812 11:32:50.856082
8813 11:32:50.856171 ==
8814 11:32:50.859186 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 11:32:50.862390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:32:50.862466 ==
8817 11:32:50.865449 [Gating] SW mode calibration
8818 11:32:50.871975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8819 11:32:50.879007 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8820 11:32:50.882154 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:32:50.888561 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:32:50.891728 1 4 8 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
8823 11:32:50.895139 1 4 12 | B1->B0 | 3131 3534 | 0 1 | (0 0) (0 0)
8824 11:32:50.901992 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:32:50.905568 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:32:50.908265 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:32:50.914978 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:32:50.918479 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:32:50.921668 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8830 11:32:50.928001 1 5 8 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8831 11:32:50.931232 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8832 11:32:50.934561 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:32:50.941518 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:32:50.944976 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:32:50.948379 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:32:50.954880 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:32:50.957817 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8838 11:32:50.961486 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8839 11:32:50.967759 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8840 11:32:50.971172 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:32:50.974250 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:32:50.981053 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:32:50.984356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:32:50.987953 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:32:50.994258 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 11:32:50.997873 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8847 11:32:51.000695 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8848 11:32:51.007276 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:32:51.011024 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:32:51.014220 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:32:51.020826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:32:51.024698 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:32:51.027792 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:32:51.030698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:32:51.037592 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:32:51.040781 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:32:51.043741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:32:51.050874 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:32:51.053994 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:32:51.057542 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:32:51.064000 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:32:51.067214 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8863 11:32:51.070802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8864 11:32:51.074253 Total UI for P1: 0, mck2ui 16
8865 11:32:51.076995 best dqsien dly found for B0: ( 1, 9, 8)
8866 11:32:51.083978 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:32:51.084054 Total UI for P1: 0, mck2ui 16
8868 11:32:51.090504 best dqsien dly found for B1: ( 1, 9, 12)
8869 11:32:51.093581 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8870 11:32:51.097227 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8871 11:32:51.097302
8872 11:32:51.100242 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8873 11:32:51.103821 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8874 11:32:51.107391 [Gating] SW calibration Done
8875 11:32:51.107466 ==
8876 11:32:51.110447 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 11:32:51.113889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 11:32:51.113965 ==
8879 11:32:51.116793 RX Vref Scan: 0
8880 11:32:51.116868
8881 11:32:51.116927 RX Vref 0 -> 0, step: 1
8882 11:32:51.116981
8883 11:32:51.120437 RX Delay 0 -> 252, step: 8
8884 11:32:51.123842 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8885 11:32:51.130488 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8886 11:32:51.133830 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8887 11:32:51.137257 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8888 11:32:51.140617 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8889 11:32:51.143472 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8890 11:32:51.150407 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8891 11:32:51.154091 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8892 11:32:51.157571 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8893 11:32:51.160009 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8894 11:32:51.163488 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8895 11:32:51.170669 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8896 11:32:51.173415 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8897 11:32:51.176630 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8898 11:32:51.179976 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8899 11:32:51.183376 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8900 11:32:51.186705 ==
8901 11:32:51.190137 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:32:51.193185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:32:51.193261 ==
8904 11:32:51.193321 DQS Delay:
8905 11:32:51.196343 DQS0 = 0, DQS1 = 0
8906 11:32:51.196418 DQM Delay:
8907 11:32:51.200048 DQM0 = 132, DQM1 = 127
8908 11:32:51.200123 DQ Delay:
8909 11:32:51.203134 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8910 11:32:51.206963 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8911 11:32:51.209965 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8912 11:32:51.213059 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8913 11:32:51.213133
8914 11:32:51.213190
8915 11:32:51.213244 ==
8916 11:32:51.216558 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:32:51.223798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:32:51.223873 ==
8919 11:32:51.223931
8920 11:32:51.223984
8921 11:32:51.224034 TX Vref Scan disable
8922 11:32:51.226681 == TX Byte 0 ==
8923 11:32:51.230066 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8924 11:32:51.236771 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8925 11:32:51.236846 == TX Byte 1 ==
8926 11:32:51.240572 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8927 11:32:51.246759 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 11:32:51.246835 ==
8929 11:32:51.249861 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:32:51.253545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:32:51.253620 ==
8932 11:32:51.267051
8933 11:32:51.270993 TX Vref early break, caculate TX vref
8934 11:32:51.273690 TX Vref=16, minBit 0, minWin=22, winSum=377
8935 11:32:51.277389 TX Vref=18, minBit 0, minWin=23, winSum=391
8936 11:32:51.280518 TX Vref=20, minBit 0, minWin=23, winSum=397
8937 11:32:51.283591 TX Vref=22, minBit 0, minWin=24, winSum=403
8938 11:32:51.286889 TX Vref=24, minBit 1, minWin=24, winSum=415
8939 11:32:51.293485 TX Vref=26, minBit 0, minWin=25, winSum=417
8940 11:32:51.297284 TX Vref=28, minBit 1, minWin=25, winSum=418
8941 11:32:51.300354 TX Vref=30, minBit 5, minWin=22, winSum=416
8942 11:32:51.303741 TX Vref=32, minBit 5, minWin=23, winSum=406
8943 11:32:51.307071 TX Vref=34, minBit 0, minWin=23, winSum=397
8944 11:32:51.310547 TX Vref=36, minBit 1, minWin=22, winSum=388
8945 11:32:51.317163 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8946 11:32:51.317240
8947 11:32:51.320417 Final TX Range 0 Vref 28
8948 11:32:51.320493
8949 11:32:51.320552 ==
8950 11:32:51.323831 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 11:32:51.327020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 11:32:51.327096 ==
8953 11:32:51.327155
8954 11:32:51.327208
8955 11:32:51.330901 TX Vref Scan disable
8956 11:32:51.337047 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8957 11:32:51.337185 == TX Byte 0 ==
8958 11:32:51.340558 u2DelayCellOfst[0]=15 cells (4 PI)
8959 11:32:51.343476 u2DelayCellOfst[1]=11 cells (3 PI)
8960 11:32:51.347039 u2DelayCellOfst[2]=0 cells (0 PI)
8961 11:32:51.350450 u2DelayCellOfst[3]=3 cells (1 PI)
8962 11:32:51.353839 u2DelayCellOfst[4]=7 cells (2 PI)
8963 11:32:51.356950 u2DelayCellOfst[5]=18 cells (5 PI)
8964 11:32:51.360211 u2DelayCellOfst[6]=15 cells (4 PI)
8965 11:32:51.363564 u2DelayCellOfst[7]=3 cells (1 PI)
8966 11:32:51.366765 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8967 11:32:51.369990 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8968 11:32:51.373712 == TX Byte 1 ==
8969 11:32:51.376490 u2DelayCellOfst[8]=0 cells (0 PI)
8970 11:32:51.376571 u2DelayCellOfst[9]=7 cells (2 PI)
8971 11:32:51.380483 u2DelayCellOfst[10]=15 cells (4 PI)
8972 11:32:51.383257 u2DelayCellOfst[11]=7 cells (2 PI)
8973 11:32:51.386868 u2DelayCellOfst[12]=18 cells (5 PI)
8974 11:32:51.389836 u2DelayCellOfst[13]=18 cells (5 PI)
8975 11:32:51.393321 u2DelayCellOfst[14]=22 cells (6 PI)
8976 11:32:51.396830 u2DelayCellOfst[15]=22 cells (6 PI)
8977 11:32:51.400288 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8978 11:32:51.406840 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8979 11:32:51.406932 DramC Write-DBI on
8980 11:32:51.406993 ==
8981 11:32:51.409992 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 11:32:51.416438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 11:32:51.416515 ==
8984 11:32:51.416578
8985 11:32:51.416664
8986 11:32:51.416746 TX Vref Scan disable
8987 11:32:51.420471 == TX Byte 0 ==
8988 11:32:51.424134 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8989 11:32:51.426892 == TX Byte 1 ==
8990 11:32:51.430331 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8991 11:32:51.434056 DramC Write-DBI off
8992 11:32:51.434140
8993 11:32:51.434200 [DATLAT]
8994 11:32:51.434254 Freq=1600, CH1 RK1
8995 11:32:51.434306
8996 11:32:51.436744 DATLAT Default: 0xf
8997 11:32:51.436819 0, 0xFFFF, sum = 0
8998 11:32:51.440141 1, 0xFFFF, sum = 0
8999 11:32:51.443976 2, 0xFFFF, sum = 0
9000 11:32:51.444053 3, 0xFFFF, sum = 0
9001 11:32:51.446964 4, 0xFFFF, sum = 0
9002 11:32:51.447069 5, 0xFFFF, sum = 0
9003 11:32:51.450614 6, 0xFFFF, sum = 0
9004 11:32:51.450691 7, 0xFFFF, sum = 0
9005 11:32:51.453327 8, 0xFFFF, sum = 0
9006 11:32:51.453403 9, 0xFFFF, sum = 0
9007 11:32:51.457341 10, 0xFFFF, sum = 0
9008 11:32:51.457418 11, 0xFFFF, sum = 0
9009 11:32:51.459975 12, 0xFFFF, sum = 0
9010 11:32:51.460052 13, 0x8FFF, sum = 0
9011 11:32:51.463299 14, 0x0, sum = 1
9012 11:32:51.463376 15, 0x0, sum = 2
9013 11:32:51.466710 16, 0x0, sum = 3
9014 11:32:51.466787 17, 0x0, sum = 4
9015 11:32:51.470080 best_step = 15
9016 11:32:51.470215
9017 11:32:51.470300 ==
9018 11:32:51.473792 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 11:32:51.476612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 11:32:51.476716 ==
9021 11:32:51.479929 RX Vref Scan: 0
9022 11:32:51.480004
9023 11:32:51.480063 RX Vref 0 -> 0, step: 1
9024 11:32:51.480118
9025 11:32:51.483261 RX Delay 11 -> 252, step: 4
9026 11:32:51.486644 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9027 11:32:51.493509 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9028 11:32:51.496633 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9029 11:32:51.500430 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9030 11:32:51.503134 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9031 11:32:51.506608 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9032 11:32:51.513400 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9033 11:32:51.516706 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9034 11:32:51.520367 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9035 11:32:51.522938 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9036 11:32:51.526733 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9037 11:32:51.533182 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9038 11:32:51.536281 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9039 11:32:51.539775 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9040 11:32:51.543277 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9041 11:32:51.549730 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9042 11:32:51.549806 ==
9043 11:32:51.552846 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 11:32:51.556078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 11:32:51.556154 ==
9046 11:32:51.556225 DQS Delay:
9047 11:32:51.559707 DQS0 = 0, DQS1 = 0
9048 11:32:51.559782 DQM Delay:
9049 11:32:51.562763 DQM0 = 129, DQM1 = 125
9050 11:32:51.562839 DQ Delay:
9051 11:32:51.566351 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9052 11:32:51.569623 DQ4 =122, DQ5 =140, DQ6 =142, DQ7 =126
9053 11:32:51.573043 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9054 11:32:51.576015 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9055 11:32:51.576090
9056 11:32:51.576148
9057 11:32:51.579768
9058 11:32:51.579843 [DramC_TX_OE_Calibration] TA2
9059 11:32:51.583460 Original DQ_B0 (3 6) =30, OEN = 27
9060 11:32:51.586359 Original DQ_B1 (3 6) =30, OEN = 27
9061 11:32:51.589430 24, 0x0, End_B0=24 End_B1=24
9062 11:32:51.592842 25, 0x0, End_B0=25 End_B1=25
9063 11:32:51.595854 26, 0x0, End_B0=26 End_B1=26
9064 11:32:51.595931 27, 0x0, End_B0=27 End_B1=27
9065 11:32:51.599158 28, 0x0, End_B0=28 End_B1=28
9066 11:32:51.602584 29, 0x0, End_B0=29 End_B1=29
9067 11:32:51.606056 30, 0x0, End_B0=30 End_B1=30
9068 11:32:51.609348 31, 0x4141, End_B0=30 End_B1=30
9069 11:32:51.609425 Byte0 end_step=30 best_step=27
9070 11:32:51.612586 Byte1 end_step=30 best_step=27
9071 11:32:51.616238 Byte0 TX OE(2T, 0.5T) = (3, 3)
9072 11:32:51.619136 Byte1 TX OE(2T, 0.5T) = (3, 3)
9073 11:32:51.619213
9074 11:32:51.619272
9075 11:32:51.626047 [DQSOSCAuto] RK1, (LSB)MR18= 0x111c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9076 11:32:51.629285 CH1 RK1: MR19=303, MR18=111C
9077 11:32:51.635819 CH1_RK1: MR19=0x303, MR18=0x111C, DQSOSC=395, MR23=63, INC=23, DEC=15
9078 11:32:51.639232 [RxdqsGatingPostProcess] freq 1600
9079 11:32:51.645982 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9080 11:32:51.649156 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 11:32:51.649232 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 11:32:51.652345 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 11:32:51.655759 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 11:32:51.659482 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 11:32:51.662467 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 11:32:51.665461 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 11:32:51.668780 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 11:32:51.672544 Pre-setting of DQS Precalculation
9089 11:32:51.675614 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9090 11:32:51.685466 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9091 11:32:51.692237 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 11:32:51.692317
9093 11:32:51.692376
9094 11:32:51.695645 [Calibration Summary] 3200 Mbps
9095 11:32:51.695720 CH 0, Rank 0
9096 11:32:51.698631 SW Impedance : PASS
9097 11:32:51.698707 DUTY Scan : NO K
9098 11:32:51.702040 ZQ Calibration : PASS
9099 11:32:51.705669 Jitter Meter : NO K
9100 11:32:51.705745 CBT Training : PASS
9101 11:32:51.708688 Write leveling : PASS
9102 11:32:51.712051 RX DQS gating : PASS
9103 11:32:51.712127 RX DQ/DQS(RDDQC) : PASS
9104 11:32:51.715405 TX DQ/DQS : PASS
9105 11:32:51.718700 RX DATLAT : PASS
9106 11:32:51.718776 RX DQ/DQS(Engine): PASS
9107 11:32:51.722009 TX OE : PASS
9108 11:32:51.722147 All Pass.
9109 11:32:51.722211
9110 11:32:51.725074 CH 0, Rank 1
9111 11:32:51.725149 SW Impedance : PASS
9112 11:32:51.728432 DUTY Scan : NO K
9113 11:32:51.731924 ZQ Calibration : PASS
9114 11:32:51.731999 Jitter Meter : NO K
9115 11:32:51.735188 CBT Training : PASS
9116 11:32:51.738675 Write leveling : PASS
9117 11:32:51.738751 RX DQS gating : PASS
9118 11:32:51.741865 RX DQ/DQS(RDDQC) : PASS
9119 11:32:51.745483 TX DQ/DQS : PASS
9120 11:32:51.745559 RX DATLAT : PASS
9121 11:32:51.748791 RX DQ/DQS(Engine): PASS
9122 11:32:51.751676 TX OE : PASS
9123 11:32:51.751765 All Pass.
9124 11:32:51.751850
9125 11:32:51.751933 CH 1, Rank 0
9126 11:32:51.755317 SW Impedance : PASS
9127 11:32:51.758369 DUTY Scan : NO K
9128 11:32:51.758445 ZQ Calibration : PASS
9129 11:32:51.761793 Jitter Meter : NO K
9130 11:32:51.761868 CBT Training : PASS
9131 11:32:51.765173 Write leveling : PASS
9132 11:32:51.768118 RX DQS gating : PASS
9133 11:32:51.768194 RX DQ/DQS(RDDQC) : PASS
9134 11:32:51.771555 TX DQ/DQS : PASS
9135 11:32:51.775174 RX DATLAT : PASS
9136 11:32:51.775249 RX DQ/DQS(Engine): PASS
9137 11:32:51.778025 TX OE : PASS
9138 11:32:51.778131 All Pass.
9139 11:32:51.778193
9140 11:32:51.781668 CH 1, Rank 1
9141 11:32:51.781743 SW Impedance : PASS
9142 11:32:51.785125 DUTY Scan : NO K
9143 11:32:51.788071 ZQ Calibration : PASS
9144 11:32:51.788147 Jitter Meter : NO K
9145 11:32:51.791515 CBT Training : PASS
9146 11:32:51.794946 Write leveling : PASS
9147 11:32:51.795021 RX DQS gating : PASS
9148 11:32:51.798342 RX DQ/DQS(RDDQC) : PASS
9149 11:32:51.801254 TX DQ/DQS : PASS
9150 11:32:51.801330 RX DATLAT : PASS
9151 11:32:51.804595 RX DQ/DQS(Engine): PASS
9152 11:32:51.808478 TX OE : PASS
9153 11:32:51.808554 All Pass.
9154 11:32:51.808612
9155 11:32:51.808665 DramC Write-DBI on
9156 11:32:51.811334 PER_BANK_REFRESH: Hybrid Mode
9157 11:32:51.814550 TX_TRACKING: ON
9158 11:32:51.821404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9159 11:32:51.831153 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9160 11:32:51.837696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9161 11:32:51.841330 [FAST_K] Save calibration result to emmc
9162 11:32:51.844807 sync common calibartion params.
9163 11:32:51.844883 sync cbt_mode0:1, 1:1
9164 11:32:51.847992 dram_init: ddr_geometry: 2
9165 11:32:51.851104 dram_init: ddr_geometry: 2
9166 11:32:51.854381 dram_init: ddr_geometry: 2
9167 11:32:51.854457 0:dram_rank_size:100000000
9168 11:32:51.857802 1:dram_rank_size:100000000
9169 11:32:51.864168 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9170 11:32:51.864370 DFS_SHUFFLE_HW_MODE: ON
9171 11:32:51.871406 dramc_set_vcore_voltage set vcore to 725000
9172 11:32:51.871482 Read voltage for 1600, 0
9173 11:32:51.875091 Vio18 = 0
9174 11:32:51.875166 Vcore = 725000
9175 11:32:51.875225 Vdram = 0
9176 11:32:51.877896 Vddq = 0
9177 11:32:51.877994 Vmddr = 0
9178 11:32:51.881442 switch to 3200 Mbps bootup
9179 11:32:51.881518 [DramcRunTimeConfig]
9180 11:32:51.881576 PHYPLL
9181 11:32:51.884348 DPM_CONTROL_AFTERK: ON
9182 11:32:51.884424 PER_BANK_REFRESH: ON
9183 11:32:51.887583 REFRESH_OVERHEAD_REDUCTION: ON
9184 11:32:51.891111 CMD_PICG_NEW_MODE: OFF
9185 11:32:51.891187 XRTWTW_NEW_MODE: ON
9186 11:32:51.894474 XRTRTR_NEW_MODE: ON
9187 11:32:51.894549 TX_TRACKING: ON
9188 11:32:51.897509 RDSEL_TRACKING: OFF
9189 11:32:51.900907 DQS Precalculation for DVFS: ON
9190 11:32:51.900982 RX_TRACKING: OFF
9191 11:32:51.904388 HW_GATING DBG: ON
9192 11:32:51.904464 ZQCS_ENABLE_LP4: ON
9193 11:32:51.907319 RX_PICG_NEW_MODE: ON
9194 11:32:51.911081 TX_PICG_NEW_MODE: ON
9195 11:32:51.911157 ENABLE_RX_DCM_DPHY: ON
9196 11:32:51.914392 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9197 11:32:51.917434 DUMMY_READ_FOR_TRACKING: OFF
9198 11:32:51.920489 !!! SPM_CONTROL_AFTERK: OFF
9199 11:32:51.920565 !!! SPM could not control APHY
9200 11:32:51.924416 IMPEDANCE_TRACKING: ON
9201 11:32:51.927257 TEMP_SENSOR: ON
9202 11:32:51.927332 HW_SAVE_FOR_SR: OFF
9203 11:32:51.931179 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9204 11:32:51.934297 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9205 11:32:51.937133 Read ODT Tracking: ON
9206 11:32:51.937208 Refresh Rate DeBounce: ON
9207 11:32:51.940406 DFS_NO_QUEUE_FLUSH: ON
9208 11:32:51.943740 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9209 11:32:51.947390 ENABLE_DFS_RUNTIME_MRW: OFF
9210 11:32:51.947466 DDR_RESERVE_NEW_MODE: ON
9211 11:32:51.950518 MR_CBT_SWITCH_FREQ: ON
9212 11:32:51.953743 =========================
9213 11:32:51.972140 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9214 11:32:51.975011 dram_init: ddr_geometry: 2
9215 11:32:51.993630 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9216 11:32:51.996617 dram_init: dram init end (result: 0)
9217 11:32:52.003456 DRAM-K: Full calibration passed in 24622 msecs
9218 11:32:52.006741 MRC: failed to locate region type 0.
9219 11:32:52.006818 DRAM rank0 size:0x100000000,
9220 11:32:52.010111 DRAM rank1 size=0x100000000
9221 11:32:52.019923 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9222 11:32:52.026692 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9223 11:32:52.033170 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9224 11:32:52.039991 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9225 11:32:52.043512 DRAM rank0 size:0x100000000,
9226 11:32:52.046680 DRAM rank1 size=0x100000000
9227 11:32:52.046755 CBMEM:
9228 11:32:52.049852 IMD: root @ 0xfffff000 254 entries.
9229 11:32:52.053036 IMD: root @ 0xffffec00 62 entries.
9230 11:32:52.056405 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9231 11:32:52.063003 WARNING: RO_VPD is uninitialized or empty.
9232 11:32:52.066160 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9233 11:32:52.073460 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9234 11:32:52.086473 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9235 11:32:52.097795 BS: romstage times (exec / console): total (unknown) / 24078 ms
9236 11:32:52.097871
9237 11:32:52.097929
9238 11:32:52.107809 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9239 11:32:52.111302 ARM64: Exception handlers installed.
9240 11:32:52.114520 ARM64: Testing exception
9241 11:32:52.117707 ARM64: Done test exception
9242 11:32:52.117782 Enumerating buses...
9243 11:32:52.120580 Show all devs... Before device enumeration.
9244 11:32:52.124363 Root Device: enabled 1
9245 11:32:52.127259 CPU_CLUSTER: 0: enabled 1
9246 11:32:52.127334 CPU: 00: enabled 1
9247 11:32:52.130579 Compare with tree...
9248 11:32:52.130654 Root Device: enabled 1
9249 11:32:52.134367 CPU_CLUSTER: 0: enabled 1
9250 11:32:52.137179 CPU: 00: enabled 1
9251 11:32:52.137253 Root Device scanning...
9252 11:32:52.140529 scan_static_bus for Root Device
9253 11:32:52.144326 CPU_CLUSTER: 0 enabled
9254 11:32:52.147504 scan_static_bus for Root Device done
9255 11:32:52.150703 scan_bus: bus Root Device finished in 8 msecs
9256 11:32:52.150778 done
9257 11:32:52.157328 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9258 11:32:52.160673 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9259 11:32:52.167485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9260 11:32:52.170761 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9261 11:32:52.173977 Allocating resources...
9262 11:32:52.177445 Reading resources...
9263 11:32:52.180630 Root Device read_resources bus 0 link: 0
9264 11:32:52.183584 DRAM rank0 size:0x100000000,
9265 11:32:52.183659 DRAM rank1 size=0x100000000
9266 11:32:52.187018 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9267 11:32:52.190659 CPU: 00 missing read_resources
9268 11:32:52.196647 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9269 11:32:52.200490 Root Device read_resources bus 0 link: 0 done
9270 11:32:52.203696 Done reading resources.
9271 11:32:52.206523 Show resources in subtree (Root Device)...After reading.
9272 11:32:52.209863 Root Device child on link 0 CPU_CLUSTER: 0
9273 11:32:52.213166 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 11:32:52.223716 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 11:32:52.223792 CPU: 00
9276 11:32:52.226687 Root Device assign_resources, bus 0 link: 0
9277 11:32:52.229611 CPU_CLUSTER: 0 missing set_resources
9278 11:32:52.236643 Root Device assign_resources, bus 0 link: 0 done
9279 11:32:52.236719 Done setting resources.
9280 11:32:52.242828 Show resources in subtree (Root Device)...After assigning values.
9281 11:32:52.246136 Root Device child on link 0 CPU_CLUSTER: 0
9282 11:32:52.249654 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 11:32:52.259577 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 11:32:52.259654 CPU: 00
9285 11:32:52.262830 Done allocating resources.
9286 11:32:52.269438 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9287 11:32:52.269514 Enabling resources...
9288 11:32:52.269573 done.
9289 11:32:52.275879 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9290 11:32:52.279173 Initializing devices...
9291 11:32:52.279248 Root Device init
9292 11:32:52.282903 init hardware done!
9293 11:32:52.282978 0x00000018: ctrlr->caps
9294 11:32:52.286078 52.000 MHz: ctrlr->f_max
9295 11:32:52.289544 0.400 MHz: ctrlr->f_min
9296 11:32:52.289620 0x40ff8080: ctrlr->voltages
9297 11:32:52.292526 sclk: 390625
9298 11:32:52.292600 Bus Width = 1
9299 11:32:52.292659 sclk: 390625
9300 11:32:52.295997 Bus Width = 1
9301 11:32:52.299504 Early init status = 3
9302 11:32:52.302776 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9303 11:32:52.306235 in-header: 03 fc 00 00 01 00 00 00
9304 11:32:52.309446 in-data: 00
9305 11:32:52.312588 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9306 11:32:52.316337 in-header: 03 fd 00 00 00 00 00 00
9307 11:32:52.319699 in-data:
9308 11:32:52.322959 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9309 11:32:52.326405 in-header: 03 fc 00 00 01 00 00 00
9310 11:32:52.329717 in-data: 00
9311 11:32:52.333208 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9312 11:32:52.337412 in-header: 03 fd 00 00 00 00 00 00
9313 11:32:52.340703 in-data:
9314 11:32:52.344351 [SSUSB] Setting up USB HOST controller...
9315 11:32:52.347983 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9316 11:32:52.351037 [SSUSB] phy power-on done.
9317 11:32:52.354032 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9318 11:32:52.361384 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9319 11:32:52.364255 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9320 11:32:52.370657 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9321 11:32:52.377529 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9322 11:32:52.384296 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9323 11:32:52.390538 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9324 11:32:52.397268 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9325 11:32:52.400442 SPM: binary array size = 0x9dc
9326 11:32:52.404175 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9327 11:32:52.410782 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9328 11:32:52.417677 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9329 11:32:52.420368 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9330 11:32:52.427124 configure_display: Starting display init
9331 11:32:52.461149 anx7625_power_on_init: Init interface.
9332 11:32:52.464119 anx7625_disable_pd_protocol: Disabled PD feature.
9333 11:32:52.467364 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9334 11:32:52.495517 anx7625_start_dp_work: Secure OCM version=00
9335 11:32:52.498697 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9336 11:32:52.513571 sp_tx_get_edid_block: EDID Block = 1
9337 11:32:52.615795 Extracted contents:
9338 11:32:52.619269 header: 00 ff ff ff ff ff ff 00
9339 11:32:52.622832 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9340 11:32:52.625844 version: 01 04
9341 11:32:52.629159 basic params: 95 1f 11 78 0a
9342 11:32:52.632472 chroma info: 76 90 94 55 54 90 27 21 50 54
9343 11:32:52.635510 established: 00 00 00
9344 11:32:52.642427 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9345 11:32:52.648766 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9346 11:32:52.652480 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 11:32:52.658789 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9348 11:32:52.665489 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9349 11:32:52.668865 extensions: 00
9350 11:32:52.668938 checksum: fb
9351 11:32:52.668995
9352 11:32:52.672333 Manufacturer: IVO Model 57d Serial Number 0
9353 11:32:52.675200 Made week 0 of 2020
9354 11:32:52.678437 EDID version: 1.4
9355 11:32:52.678515 Digital display
9356 11:32:52.682035 6 bits per primary color channel
9357 11:32:52.682171 DisplayPort interface
9358 11:32:52.685326 Maximum image size: 31 cm x 17 cm
9359 11:32:52.688337 Gamma: 220%
9360 11:32:52.688411 Check DPMS levels
9361 11:32:52.692109 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9362 11:32:52.698344 First detailed timing is preferred timing
9363 11:32:52.698419 Established timings supported:
9364 11:32:52.701495 Standard timings supported:
9365 11:32:52.704894 Detailed timings
9366 11:32:52.708485 Hex of detail: 383680a07038204018303c0035ae10000019
9367 11:32:52.714879 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9368 11:32:52.718501 0780 0798 07c8 0820 hborder 0
9369 11:32:52.721222 0438 043b 0447 0458 vborder 0
9370 11:32:52.724663 -hsync -vsync
9371 11:32:52.724739 Did detailed timing
9372 11:32:52.731186 Hex of detail: 000000000000000000000000000000000000
9373 11:32:52.734702 Manufacturer-specified data, tag 0
9374 11:32:52.737704 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9375 11:32:52.741101 ASCII string: InfoVision
9376 11:32:52.744631 Hex of detail: 000000fe00523134304e574635205248200a
9377 11:32:52.747812 ASCII string: R140NWF5 RH
9378 11:32:52.747887 Checksum
9379 11:32:52.751162 Checksum: 0xfb (valid)
9380 11:32:52.754012 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9381 11:32:52.757563 DSI data_rate: 832800000 bps
9382 11:32:52.764157 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9383 11:32:52.767633 anx7625_parse_edid: pixelclock(138800).
9384 11:32:52.771355 hactive(1920), hsync(48), hfp(24), hbp(88)
9385 11:32:52.774081 vactive(1080), vsync(12), vfp(3), vbp(17)
9386 11:32:52.777254 anx7625_dsi_config: config dsi.
9387 11:32:52.784180 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9388 11:32:52.798014 anx7625_dsi_config: success to config DSI
9389 11:32:52.801282 anx7625_dp_start: MIPI phy setup OK.
9390 11:32:52.804767 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9391 11:32:52.807706 mtk_ddp_mode_set invalid vrefresh 60
9392 11:32:52.811022 main_disp_path_setup
9393 11:32:52.811096 ovl_layer_smi_id_en
9394 11:32:52.814358 ovl_layer_smi_id_en
9395 11:32:52.814431 ccorr_config
9396 11:32:52.814488 aal_config
9397 11:32:52.818244 gamma_config
9398 11:32:52.818318 postmask_config
9399 11:32:52.821063 dither_config
9400 11:32:52.824453 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9401 11:32:52.831387 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9402 11:32:52.834513 Root Device init finished in 551 msecs
9403 11:32:52.837753 CPU_CLUSTER: 0 init
9404 11:32:52.844550 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9405 11:32:52.847882 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9406 11:32:52.851398 APU_MBOX 0x190000b0 = 0x10001
9407 11:32:52.854038 APU_MBOX 0x190001b0 = 0x10001
9408 11:32:52.857786 APU_MBOX 0x190005b0 = 0x10001
9409 11:32:52.861026 APU_MBOX 0x190006b0 = 0x10001
9410 11:32:52.867337 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9411 11:32:52.876933 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9412 11:32:52.889293 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9413 11:32:52.895699 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9414 11:32:52.907875 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9415 11:32:52.916951 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9416 11:32:52.920026 CPU_CLUSTER: 0 init finished in 81 msecs
9417 11:32:52.923466 Devices initialized
9418 11:32:52.927166 Show all devs... After init.
9419 11:32:52.927240 Root Device: enabled 1
9420 11:32:52.929740 CPU_CLUSTER: 0: enabled 1
9421 11:32:52.933285 CPU: 00: enabled 1
9422 11:32:52.936739 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9423 11:32:52.939760 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9424 11:32:52.943196 ELOG: NV offset 0x57f000 size 0x1000
9425 11:32:52.949677 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9426 11:32:52.956374 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9427 11:32:52.960022 ELOG: Event(17) added with size 13 at 2024-07-17 11:32:52 UTC
9428 11:32:52.963373 out: cmd=0x121: 03 db 21 01 00 00 00 00
9429 11:32:52.967882 in-header: 03 59 00 00 2c 00 00 00
9430 11:32:52.981177 in-data: e4 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9431 11:32:52.988075 ELOG: Event(A1) added with size 10 at 2024-07-17 11:32:52 UTC
9432 11:32:52.994509 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9433 11:32:53.001586 ELOG: Event(A0) added with size 9 at 2024-07-17 11:32:52 UTC
9434 11:32:53.004226 elog_add_boot_reason: Logged dev mode boot
9435 11:32:53.007908 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9436 11:32:53.011176 Finalize devices...
9437 11:32:53.011252 Devices finalized
9438 11:32:53.017685 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9439 11:32:53.020919 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9440 11:32:53.024754 in-header: 03 07 00 00 08 00 00 00
9441 11:32:53.028076 in-data: aa e4 47 04 13 02 00 00
9442 11:32:53.031021 Chrome EC: UHEPI supported
9443 11:32:53.037482 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9444 11:32:53.040782 in-header: 03 a9 00 00 08 00 00 00
9445 11:32:53.044287 in-data: 84 60 60 08 00 00 00 00
9446 11:32:53.047346 ELOG: Event(91) added with size 10 at 2024-07-17 11:32:52 UTC
9447 11:32:53.054236 Chrome EC: clear events_b mask to 0x0000000020004000
9448 11:32:53.060728 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9449 11:32:53.064623 in-header: 03 fd 00 00 00 00 00 00
9450 11:32:53.068483 in-data:
9451 11:32:53.071226 BS: BS_WRITE_TABLES entry times (exec / console): 4 / 46 ms
9452 11:32:53.074407 Writing coreboot table at 0xffe64000
9453 11:32:53.077749 0. 000000000010a000-0000000000113fff: RAMSTAGE
9454 11:32:53.084506 1. 0000000040000000-00000000400fffff: RAM
9455 11:32:53.087767 2. 0000000040100000-000000004032afff: RAMSTAGE
9456 11:32:53.091233 3. 000000004032b000-00000000545fffff: RAM
9457 11:32:53.094597 4. 0000000054600000-000000005465ffff: BL31
9458 11:32:53.097956 5. 0000000054660000-00000000ffe63fff: RAM
9459 11:32:53.104259 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9460 11:32:53.107654 7. 0000000100000000-000000023fffffff: RAM
9461 11:32:53.110833 Passing 5 GPIOs to payload:
9462 11:32:53.114780 NAME | PORT | POLARITY | VALUE
9463 11:32:53.120792 EC in RW | 0x000000aa | low | undefined
9464 11:32:53.124588 EC interrupt | 0x00000005 | low | undefined
9465 11:32:53.127416 TPM interrupt | 0x000000ab | high | undefined
9466 11:32:53.134214 SD card detect | 0x00000011 | high | undefined
9467 11:32:53.137848 speaker enable | 0x00000093 | high | undefined
9468 11:32:53.140576 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9469 11:32:53.144065 in-header: 03 f9 00 00 02 00 00 00
9470 11:32:53.147574 in-data: 02 00
9471 11:32:53.150919 ADC[4]: Raw value=895191 ID=7
9472 11:32:53.154033 ADC[3]: Raw value=213440 ID=1
9473 11:32:53.154134 RAM Code: 0x71
9474 11:32:53.157246 ADC[6]: Raw value=74722 ID=0
9475 11:32:53.160410 ADC[5]: Raw value=211590 ID=1
9476 11:32:53.160485 SKU Code: 0x1
9477 11:32:53.166937 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 71d9
9478 11:32:53.167012 coreboot table: 964 bytes.
9479 11:32:53.170302 IMD ROOT 0. 0xfffff000 0x00001000
9480 11:32:53.173660 IMD SMALL 1. 0xffffe000 0x00001000
9481 11:32:53.176755 RO MCACHE 2. 0xffffc000 0x00001104
9482 11:32:53.180094 CONSOLE 3. 0xfff7c000 0x00080000
9483 11:32:53.183719 FMAP 4. 0xfff7b000 0x00000452
9484 11:32:53.187033 TIME STAMP 5. 0xfff7a000 0x00000910
9485 11:32:53.190064 VBOOT WORK 6. 0xfff66000 0x00014000
9486 11:32:53.193631 RAMOOPS 7. 0xffe66000 0x00100000
9487 11:32:53.196850 COREBOOT 8. 0xffe64000 0x00002000
9488 11:32:53.199797 IMD small region:
9489 11:32:53.203540 IMD ROOT 0. 0xffffec00 0x00000400
9490 11:32:53.206556 VPD 1. 0xffffeb80 0x0000006c
9491 11:32:53.210039 MMC STATUS 2. 0xffffeb60 0x00000004
9492 11:32:53.216720 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9493 11:32:53.223298 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 11:32:53.261643 read SPI 0x3990ec 0x4f1b0: 34862 us, 9294 KB/s, 74.352 Mbps
9495 11:32:53.265131 Checking segment from ROM address 0x40100000
9496 11:32:53.268295 Checking segment from ROM address 0x4010001c
9497 11:32:53.274946 Loading segment from ROM address 0x40100000
9498 11:32:53.275022 code (compression=0)
9499 11:32:53.284773 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 11:32:53.291259 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 11:32:53.291335 it's not compressed!
9502 11:32:53.298154 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 11:32:53.304647 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 11:32:53.322222 Loading segment from ROM address 0x4010001c
9505 11:32:53.322299 Entry Point 0x80000000
9506 11:32:53.325597 Loaded segments
9507 11:32:53.328559 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 11:32:53.335313 Jumping to boot code at 0x80000000(0xffe64000)
9509 11:32:53.341694 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 11:32:53.348209 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 11:32:53.356446 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 11:32:53.359753 Checking segment from ROM address 0x40100000
9513 11:32:53.363241 Checking segment from ROM address 0x4010001c
9514 11:32:53.369794 Loading segment from ROM address 0x40100000
9515 11:32:53.369869 code (compression=1)
9516 11:32:53.376189 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 11:32:53.386132 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 11:32:53.386223 using LZMA
9519 11:32:53.394905 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 11:32:53.401657 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 11:32:53.404452 Loading segment from ROM address 0x4010001c
9522 11:32:53.407995 Entry Point 0x54601000
9523 11:32:53.408070 Loaded segments
9524 11:32:53.411000 NOTICE: MT8192 bl31_setup
9525 11:32:53.418702 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 11:32:53.421456 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 11:32:53.424586 WARNING: region 0:
9528 11:32:53.428225 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 11:32:53.428295 WARNING: region 1:
9530 11:32:53.435310 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 11:32:53.438048 WARNING: region 2:
9532 11:32:53.441654 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 11:32:53.445090 WARNING: region 3:
9534 11:32:53.448253 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 11:32:53.451902 WARNING: region 4:
9536 11:32:53.458236 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 11:32:53.458311 WARNING: region 5:
9538 11:32:53.461558 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 11:32:53.465077 WARNING: region 6:
9540 11:32:53.467999 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 11:32:53.471540 WARNING: region 7:
9542 11:32:53.474571 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 11:32:53.481036 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 11:32:53.484676 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 11:32:53.487854 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 11:32:53.494736 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 11:32:53.497771 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 11:32:53.504416 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 11:32:53.507695 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 11:32:53.511083 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 11:32:53.517821 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 11:32:53.520779 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 11:32:53.527790 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 11:32:53.531138 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 11:32:53.534276 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 11:32:53.540425 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 11:32:53.543658 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 11:32:53.547378 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 11:32:53.553610 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 11:32:53.557098 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 11:32:53.564092 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 11:32:53.567176 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 11:32:53.570960 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 11:32:53.576886 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 11:32:53.580373 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 11:32:53.586744 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 11:32:53.590483 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 11:32:53.593522 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 11:32:53.600359 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 11:32:53.603399 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 11:32:53.610130 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 11:32:53.613446 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 11:32:53.616636 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 11:32:53.623411 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 11:32:53.626959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 11:32:53.630052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 11:32:53.633682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 11:32:53.640620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 11:32:53.643243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 11:32:53.646561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 11:32:53.649783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 11:32:53.656481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 11:32:53.660085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 11:32:53.663003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 11:32:53.670003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 11:32:53.673423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 11:32:53.676381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 11:32:53.679509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 11:32:53.686299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 11:32:53.689341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 11:32:53.692615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 11:32:53.699457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 11:32:53.703113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 11:32:53.709280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 11:32:53.712959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 11:32:53.719194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 11:32:53.722823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 11:32:53.726034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 11:32:53.732988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 11:32:53.735693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 11:32:53.742134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 11:32:53.745840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 11:32:53.752444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 11:32:53.755741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 11:32:53.762042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 11:32:53.765634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 11:32:53.772109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 11:32:53.775730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 11:32:53.778542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 11:32:53.785110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 11:32:53.788586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 11:32:53.795308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 11:32:53.798733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 11:32:53.805037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 11:32:53.808429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 11:32:53.811337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 11:32:53.817905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 11:32:53.821945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 11:32:53.827865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 11:32:53.831231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 11:32:53.837681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 11:32:53.841545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 11:32:53.847886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 11:32:53.850870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 11:32:53.857504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 11:32:53.860686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 11:32:53.864458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 11:32:53.871197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 11:32:53.874095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 11:32:53.880582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 11:32:53.884150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 11:32:53.890631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 11:32:53.893854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 11:32:53.900632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 11:32:53.903788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 11:32:53.907171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 11:32:53.913892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 11:32:53.916953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 11:32:53.923357 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 11:32:53.927063 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 11:32:53.930694 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 11:32:53.933478 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 11:32:53.939832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 11:32:53.943455 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 11:32:53.949868 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 11:32:53.953643 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 11:32:53.957050 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 11:32:53.962941 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 11:32:53.966739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 11:32:53.973432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 11:32:53.976442 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 11:32:53.982754 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 11:32:53.985981 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 11:32:53.989324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 11:32:53.995937 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 11:32:53.999389 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 11:32:54.005849 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 11:32:54.009260 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 11:32:54.012276 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 11:32:54.015819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 11:32:54.022028 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 11:32:54.025579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 11:32:54.028942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 11:32:54.035550 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 11:32:54.038961 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 11:32:54.041921 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 11:32:54.048597 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 11:32:54.052034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 11:32:54.055232 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 11:32:54.062032 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 11:32:54.064982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 11:32:54.072414 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 11:32:54.075278 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 11:32:54.078524 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 11:32:54.084986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 11:32:54.088304 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 11:32:54.095213 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 11:32:54.098017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 11:32:54.101450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 11:32:54.108461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 11:32:54.111463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 11:32:54.118018 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 11:32:54.121136 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 11:32:54.124908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 11:32:54.131153 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 11:32:54.134824 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 11:32:54.137635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 11:32:54.144301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 11:32:54.147857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 11:32:54.154221 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 11:32:54.157800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 11:32:54.164165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 11:32:54.167994 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 11:32:54.170544 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 11:32:54.177215 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 11:32:54.180474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 11:32:54.187169 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 11:32:54.190457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 11:32:54.193723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 11:32:54.200545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 11:32:54.203780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 11:32:54.207009 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 11:32:54.213557 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 11:32:54.216972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 11:32:54.223440 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 11:32:54.227151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 11:32:54.233421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 11:32:54.236689 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 11:32:54.239948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 11:32:54.246373 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 11:32:54.249605 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 11:32:54.256393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 11:32:54.260231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 11:32:54.263162 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 11:32:54.269706 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 11:32:54.272718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 11:32:54.279363 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 11:32:54.282682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 11:32:54.285961 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 11:32:54.292783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 11:32:54.295953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 11:32:54.302341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 11:32:54.305800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 11:32:54.308974 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 11:32:54.316035 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 11:32:54.319216 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 11:32:54.325897 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 11:32:54.329046 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 11:32:54.332865 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 11:32:54.339056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 11:32:54.341980 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 11:32:54.348541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 11:32:54.351996 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 11:32:54.355398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 11:32:54.362227 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 11:32:54.365688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 11:32:54.372471 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 11:32:54.375499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 11:32:54.381683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 11:32:54.384954 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 11:32:54.388104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 11:32:54.394784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 11:32:54.398632 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 11:32:54.405406 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 11:32:54.408449 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 11:32:54.415193 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 11:32:54.417788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 11:32:54.421296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 11:32:54.427950 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 11:32:54.431353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 11:32:54.438008 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 11:32:54.441040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 11:32:54.447707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 11:32:54.451352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 11:32:54.454351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 11:32:54.460849 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 11:32:54.464386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 11:32:54.470706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 11:32:54.474013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 11:32:54.480662 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 11:32:54.484141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 11:32:54.487200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 11:32:54.494075 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 11:32:54.497463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 11:32:54.504143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 11:32:54.507410 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 11:32:54.510536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 11:32:54.516851 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 11:32:54.520353 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 11:32:54.527030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 11:32:54.529933 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 11:32:54.533808 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 11:32:54.540172 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 11:32:54.543699 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 11:32:54.547198 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 11:32:54.550135 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 11:32:54.556385 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 11:32:54.559634 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 11:32:54.566638 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 11:32:54.569997 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 11:32:54.572892 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 11:32:54.579686 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 11:32:54.583061 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 11:32:54.586051 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 11:32:54.592946 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 11:32:54.596252 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 11:32:54.602464 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 11:32:54.606095 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 11:32:54.609182 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 11:32:54.616129 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 11:32:54.618922 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 11:32:54.622680 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 11:32:54.629257 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 11:32:54.632240 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 11:32:54.638665 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 11:32:54.642025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 11:32:54.645133 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 11:32:54.651818 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 11:32:54.655303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 11:32:54.662090 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 11:32:54.664840 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 11:32:54.668110 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 11:32:54.675190 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 11:32:54.678004 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 11:32:54.684781 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 11:32:54.687634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 11:32:54.690980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 11:32:54.698022 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 11:32:54.701443 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 11:32:54.704515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 11:32:54.710793 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 11:32:54.714446 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 11:32:54.717477 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 11:32:54.721079 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 11:32:54.727169 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 11:32:54.730902 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 11:32:54.734182 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 11:32:54.737497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 11:32:54.744187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 11:32:54.747081 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 11:32:54.750614 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 11:32:54.754010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 11:32:54.760407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 11:32:54.764325 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 11:32:54.767362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 11:32:54.773766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 11:32:54.776816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 11:32:54.783882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 11:32:54.786649 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 11:32:54.793699 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 11:32:54.796675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 11:32:54.800152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 11:32:54.806587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 11:32:54.809954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 11:32:54.816384 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 11:32:54.819519 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 11:32:54.822971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 11:32:54.829831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 11:32:54.833018 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 11:32:54.839462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 11:32:54.842676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 11:32:54.849247 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 11:32:54.852590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 11:32:54.856044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 11:32:54.862459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 11:32:54.865879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 11:32:54.872617 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 11:32:54.875645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 11:32:54.879038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 11:32:54.885899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 11:32:54.889277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 11:32:54.895487 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 11:32:54.898988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 11:32:54.905369 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 11:32:54.909455 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 11:32:54.911922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 11:32:54.918858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 11:32:54.922338 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 11:32:54.928576 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 11:32:54.932251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 11:32:54.935415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 11:32:54.941638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 11:32:54.944939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 11:32:54.951646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 11:32:54.954764 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 11:32:54.961798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 11:32:54.965441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 11:32:54.968159 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 11:32:54.974974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 11:32:54.978397 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 11:32:54.984988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 11:32:54.988044 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 11:32:54.991586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 11:32:54.997912 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 11:32:55.001065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 11:32:55.007761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 11:32:55.011359 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 11:32:55.017650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 11:32:55.020986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 11:32:55.024284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 11:32:55.031000 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 11:32:55.034472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 11:32:55.040658 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 11:32:55.044107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 11:32:55.047631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 11:32:55.054372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 11:32:55.057507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 11:32:55.064478 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 11:32:55.067560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 11:32:55.071031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 11:32:55.077232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 11:32:55.080438 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 11:32:55.087236 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 11:32:55.090550 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 11:32:55.097571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 11:32:55.100191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 11:32:55.103669 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 11:32:55.110239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 11:32:55.113605 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 11:32:55.120159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 11:32:55.123655 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 11:32:55.130133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 11:32:55.133526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 11:32:55.136571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 11:32:55.143558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 11:32:55.146480 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 11:32:55.153498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 11:32:55.156927 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 11:32:55.163295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 11:32:55.166455 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 11:32:55.173106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 11:32:55.176534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 11:32:55.179513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 11:32:55.186218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 11:32:55.189742 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 11:32:55.196444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 11:32:55.199612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 11:32:55.206238 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 11:32:55.209766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 11:32:55.213122 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 11:32:55.219454 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 11:32:55.223056 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 11:32:55.229272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 11:32:55.232315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 11:32:55.239133 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 11:32:55.242290 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 11:32:55.249113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 11:32:55.252561 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 11:32:55.255699 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 11:32:55.262420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 11:32:55.265899 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 11:32:55.272522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 11:32:55.275957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 11:32:55.282523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 11:32:55.285883 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 11:32:55.289272 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 11:32:55.296190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 11:32:55.299527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 11:32:55.306062 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 11:32:55.309155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 11:32:55.315651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 11:32:55.319403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 11:32:55.325804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 11:32:55.329115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 11:32:55.332408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 11:32:55.338674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 11:32:55.342238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 11:32:55.348999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 11:32:55.351823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 11:32:55.359080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 11:32:55.362911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 11:32:55.368748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 11:32:55.371963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 11:32:55.378494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 11:32:55.381666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 11:32:55.388289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 11:32:55.391844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 11:32:55.394930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 11:32:55.401605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 11:32:55.404815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 11:32:55.411714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 11:32:55.415496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 11:32:55.421331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 11:32:55.425008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 11:32:55.431451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 11:32:55.434445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 11:32:55.441168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 11:32:55.444545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 11:32:55.450926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 11:32:55.454681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 11:32:55.460935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 11:32:55.467890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 11:32:55.471076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 11:32:55.477875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 11:32:55.481055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 11:32:55.487354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 11:32:55.491002 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 11:32:55.491074 INFO: [APUAPC] vio 0
9979 11:32:55.498657 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 11:32:55.501622 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 11:32:55.504807 INFO: [APUAPC] D0_APC_0: 0x400510
9982 11:32:55.508576 INFO: [APUAPC] D0_APC_1: 0x0
9983 11:32:55.511542 INFO: [APUAPC] D0_APC_2: 0x1540
9984 11:32:55.514722 INFO: [APUAPC] D0_APC_3: 0x0
9985 11:32:55.518027 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 11:32:55.521797 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 11:32:55.525236 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 11:32:55.528004 INFO: [APUAPC] D1_APC_3: 0x0
9989 11:32:55.531425 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 11:32:55.535029 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 11:32:55.538372 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 11:32:55.541320 INFO: [APUAPC] D2_APC_3: 0x0
9993 11:32:55.544825 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 11:32:55.548164 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 11:32:55.551148 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 11:32:55.554749 INFO: [APUAPC] D3_APC_3: 0x0
9997 11:32:55.557849 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 11:32:55.561036 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 11:32:55.564606 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 11:32:55.567738 INFO: [APUAPC] D4_APC_3: 0x0
10001 11:32:55.571033 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 11:32:55.574095 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 11:32:55.577660 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 11:32:55.577733 INFO: [APUAPC] D5_APC_3: 0x0
10005 11:32:55.584419 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 11:32:55.587881 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 11:32:55.590891 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 11:32:55.590965 INFO: [APUAPC] D6_APC_3: 0x0
10009 11:32:55.594019 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 11:32:55.600552 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 11:32:55.604037 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 11:32:55.604109 INFO: [APUAPC] D7_APC_3: 0x0
10013 11:32:55.606984 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 11:32:55.610737 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 11:32:55.613661 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 11:32:55.616812 INFO: [APUAPC] D8_APC_3: 0x0
10017 11:32:55.620472 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 11:32:55.623813 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 11:32:55.627019 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 11:32:55.630354 INFO: [APUAPC] D9_APC_3: 0x0
10021 11:32:55.633433 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 11:32:55.636737 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 11:32:55.640196 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 11:32:55.643525 INFO: [APUAPC] D10_APC_3: 0x0
10025 11:32:55.647016 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 11:32:55.649788 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 11:32:55.653302 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 11:32:55.656675 INFO: [APUAPC] D11_APC_3: 0x0
10029 11:32:55.660397 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 11:32:55.666327 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 11:32:55.669818 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 11:32:55.669885 INFO: [APUAPC] D12_APC_3: 0x0
10033 11:32:55.672977 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 11:32:55.679862 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 11:32:55.682874 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 11:32:55.682952 INFO: [APUAPC] D13_APC_3: 0x0
10037 11:32:55.689818 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 11:32:55.692685 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 11:32:55.696444 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 11:32:55.699452 INFO: [APUAPC] D14_APC_3: 0x0
10041 11:32:55.702969 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 11:32:55.706418 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 11:32:55.709439 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 11:32:55.712586 INFO: [APUAPC] D15_APC_3: 0x0
10045 11:32:55.712657 INFO: [APUAPC] APC_CON: 0x4
10046 11:32:55.715790 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 11:32:55.719196 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 11:32:55.722844 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 11:32:55.725841 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 11:32:55.729305 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 11:32:55.732338 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 11:32:55.735786 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 11:32:55.738906 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 11:32:55.742196 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 11:32:55.745452 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 11:32:55.745520 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 11:32:55.748734 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 11:32:55.752234 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 11:32:55.755881 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 11:32:55.758945 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 11:32:55.762009 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 11:32:55.765239 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 11:32:55.769111 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 11:32:55.772027 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 11:32:55.775460 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 11:32:55.778607 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 11:32:55.781824 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 11:32:55.781898 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 11:32:55.785095 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 11:32:55.788605 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 11:32:55.792156 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 11:32:55.795689 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 11:32:55.798660 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 11:32:55.801922 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 11:32:55.805077 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 11:32:55.808566 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 11:32:55.811565 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 11:32:55.814839 INFO: [NOCDAPC] APC_CON: 0x4
10079 11:32:55.818355 INFO: [APUAPC] set_apusys_apc done
10080 11:32:55.821315 INFO: [DEVAPC] devapc_init done
10081 11:32:55.824907 INFO: GICv3 without legacy support detected.
10082 11:32:55.828553 INFO: ARM GICv3 driver initialized in EL3
10083 11:32:55.831402 INFO: Maximum SPI INTID supported: 639
10084 11:32:55.837899 INFO: BL31: Initializing runtime services
10085 11:32:55.840975 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 11:32:55.844875 INFO: SPM: enable CPC mode
10087 11:32:55.851045 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 11:32:55.854774 INFO: BL31: Preparing for EL3 exit to normal world
10089 11:32:55.857527 INFO: Entry point address = 0x80000000
10090 11:32:55.860704 INFO: SPSR = 0x8
10091 11:32:55.866526
10092 11:32:55.866599
10093 11:32:55.866657
10094 11:32:55.869693 Starting depthcharge on Spherion...
10095 11:32:55.869778
10096 11:32:55.869835 Wipe memory regions:
10097 11:32:55.869893
10098 11:32:55.870567 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10099 11:32:55.870657 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10100 11:32:55.870728 Setting prompt string to ['asurada:']
10101 11:32:55.870790 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10102 11:32:55.872781 [0x00000040000000, 0x00000054600000)
10103 11:32:55.994630
10104 11:32:55.994723 [0x00000054660000, 0x00000080000000)
10105 11:32:56.255119
10106 11:32:56.258284 [0x000000821a7280, 0x000000ffe64000)
10107 11:32:56.999609
10108 11:32:56.999732 [0x00000100000000, 0x00000240000000)
10109 11:32:58.889842
10110 11:32:58.892928 Initializing XHCI USB controller at 0x11200000.
10111 11:32:59.932800
10112 11:32:59.936019 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 11:32:59.936449
10114 11:32:59.936782
10115 11:32:59.937476 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 11:32:59.937857 Sending line: 'tftpboot 192.168.201.1 14864572/tftp-deploy-lyi6h__3/kernel/image.itb 14864572/tftp-deploy-lyi6h__3/kernel/cmdline '
10118 11:33:00.039232 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10119 11:33:00.039636 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10120 11:33:00.043969 asurada: tftpboot 192.168.201.1 14864572/tftp-deploy-lyi6h__3/kernel/image.itp-deploy-lyi6h__3/kernel/cmdline
10121 11:33:00.044405
10122 11:33:00.044964 Waiting for link
10123 11:33:00.202175
10124 11:33:00.202667 R8152: Initializing
10125 11:33:00.203000
10126 11:33:00.205678 Version 6 (ocp_data = 5c30)
10127 11:33:00.206145
10128 11:33:00.208440 R8152: Done initializing
10129 11:33:00.208880
10130 11:33:00.209216 Adding net device
10131 11:33:02.112038
10132 11:33:02.112163 done.
10133 11:33:02.112223
10134 11:33:02.112277 MAC: 00:24:32:30:78:ff
10135 11:33:02.112328
10136 11:33:02.114873 Sending DHCP discover... done.
10137 11:33:02.114972
10138 11:33:02.118457 Waiting for reply... done.
10139 11:33:02.118538
10140 11:33:02.122031 Sending DHCP request... done.
10141 11:33:02.122118
10142 11:33:02.126767 Waiting for reply... done.
10143 11:33:02.126866
10144 11:33:02.126949 My ip is 192.168.201.21
10145 11:33:02.127029
10146 11:33:02.129327 The DHCP server ip is 192.168.201.1
10147 11:33:02.129425
10148 11:33:02.136639 TFTP server IP predefined by user: 192.168.201.1
10149 11:33:02.136715
10150 11:33:02.142660 Bootfile predefined by user: 14864572/tftp-deploy-lyi6h__3/kernel/image.itb
10151 11:33:02.142735
10152 11:33:02.142793 Sending tftp read request... done.
10153 11:33:02.145845
10154 11:33:02.149810 Waiting for the transfer...
10155 11:33:02.149908
10156 11:33:02.732756 00000000 ################################################################
10157 11:33:02.732883
10158 11:33:03.296031 00080000 ################################################################
10159 11:33:03.296155
10160 11:33:03.851098 00100000 ################################################################
10161 11:33:03.851211
10162 11:33:04.406243 00180000 ################################################################
10163 11:33:04.406453
10164 11:33:04.976019 00200000 ################################################################
10165 11:33:04.976145
10166 11:33:05.567063 00280000 ################################################################
10167 11:33:05.567190
10168 11:33:06.174489 00300000 ################################################################
10169 11:33:06.174997
10170 11:33:06.899485 00380000 ################################################################
10171 11:33:06.900007
10172 11:33:07.631587 00400000 ################################################################
10173 11:33:07.632101
10174 11:33:08.349579 00480000 ################################################################
10175 11:33:08.350137
10176 11:33:09.048466 00500000 ################################################################
10177 11:33:09.048914
10178 11:33:09.690848 00580000 ################################################################
10179 11:33:09.690959
10180 11:33:10.270752 00600000 ################################################################
10181 11:33:10.270867
10182 11:33:10.864362 00680000 ################################################################
10183 11:33:10.864476
10184 11:33:11.559657 00700000 ################################################################
10185 11:33:11.560181
10186 11:33:12.194057 00780000 ################################################################
10187 11:33:12.194210
10188 11:33:12.821732 00800000 ################################################################
10189 11:33:12.822180
10190 11:33:13.539229 00880000 ################################################################
10191 11:33:13.539429
10192 11:33:14.250839 00900000 ################################################################
10193 11:33:14.251354
10194 11:33:14.971095 00980000 ################################################################
10195 11:33:14.971590
10196 11:33:15.700397 00a00000 ################################################################
10197 11:33:15.700894
10198 11:33:16.425760 00a80000 ################################################################
10199 11:33:16.426382
10200 11:33:17.149472 00b00000 ################################################################
10201 11:33:17.149806
10202 11:33:17.884372 00b80000 ################################################################
10203 11:33:17.884889
10204 11:33:18.571273 00c00000 ################################################################
10205 11:33:18.571896
10206 11:33:19.221918 00c80000 ################################################################
10207 11:33:19.222056
10208 11:33:19.889526 00d00000 ################################################################
10209 11:33:19.890041
10210 11:33:20.571246 00d80000 ################################################################
10211 11:33:20.571770
10212 11:33:21.267551 00e00000 ################################################################
10213 11:33:21.267757
10214 11:33:21.910457 00e80000 ################################################################
10215 11:33:21.911008
10216 11:33:22.507308 00f00000 ################################################################
10217 11:33:22.507612
10218 11:33:23.197568 00f80000 ################################################################
10219 11:33:23.198148
10220 11:33:23.893400 01000000 ################################################################
10221 11:33:23.893922
10222 11:33:24.645641 01080000 ################################################################
10223 11:33:24.646197
10224 11:33:25.376804 01100000 ################################################################
10225 11:33:25.377321
10226 11:33:26.109337 01180000 ################################################################
10227 11:33:26.109799
10228 11:33:26.840595 01200000 ################################################################
10229 11:33:26.841208
10230 11:33:27.569699 01280000 ################################################################
10231 11:33:27.570306
10232 11:33:28.302813 01300000 ################################################################
10233 11:33:28.303367
10234 11:33:29.027355 01380000 ################################################################
10235 11:33:29.027878
10236 11:33:29.766537 01400000 ################################################################
10237 11:33:29.767076
10238 11:33:30.494205 01480000 ################################################################
10239 11:33:30.494670
10240 11:33:31.218553 01500000 ################################################################
10241 11:33:31.219035
10242 11:33:31.926237 01580000 ################################################################
10243 11:33:31.926791
10244 11:33:32.650728 01600000 ################################################################
10245 11:33:32.651272
10246 11:33:33.357621 01680000 ################################################################
10247 11:33:33.358216
10248 11:33:34.074943 01700000 ################################################################
10249 11:33:34.075540
10250 11:33:34.787602 01780000 ################################################################
10251 11:33:34.787983
10252 11:33:35.417707 01800000 ################################################################
10253 11:33:35.418218
10254 11:33:36.100041 01880000 ################################################################
10255 11:33:36.100557
10256 11:33:36.788156 01900000 ################################################################
10257 11:33:36.788616
10258 11:33:37.512782 01980000 ################################################################
10259 11:33:37.513310
10260 11:33:38.207943 01a00000 ################################################################
10261 11:33:38.208225
10262 11:33:38.916568 01a80000 ################################################################
10263 11:33:38.917090
10264 11:33:39.618425 01b00000 ################################################################
10265 11:33:39.618940
10266 11:33:40.339616 01b80000 ################################################################
10267 11:33:40.340126
10268 11:33:41.073688 01c00000 ################################################################
10269 11:33:41.074223
10270 11:33:41.780815 01c80000 ################################################################
10271 11:33:41.781342
10272 11:33:42.511031 01d00000 ################################################################
10273 11:33:42.511587
10274 11:33:43.244445 01d80000 ################################################################
10275 11:33:43.245093
10276 11:33:43.800813 01e00000 ##################################################### done.
10277 11:33:43.801378
10278 11:33:43.804592 The bootfile was 31884178 bytes long.
10279 11:33:43.805106
10280 11:33:43.807269 Sending tftp read request... done.
10281 11:33:43.807702
10282 11:33:43.810620 Waiting for the transfer...
10283 11:33:43.811058
10284 11:33:43.814092 00000000 # done.
10285 11:33:43.814577
10286 11:33:43.820792 Command line loaded dynamically from TFTP file: 14864572/tftp-deploy-lyi6h__3/kernel/cmdline
10287 11:33:43.821309
10288 11:33:43.843906 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10289 11:33:43.844478
10290 11:33:43.844820 Loading FIT.
10291 11:33:43.845132
10292 11:33:43.846826 Image ramdisk-1 has 18716598 bytes.
10293 11:33:43.847260
10294 11:33:43.851070 Image fdt-1 has 47258 bytes.
10295 11:33:43.851582
10296 11:33:43.853501 Image kernel-1 has 13118294 bytes.
10297 11:33:43.853932
10298 11:33:43.863673 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10299 11:33:43.864112
10300 11:33:43.880257 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10301 11:33:43.880800
10302 11:33:43.886856 Choosing best match conf-1 for compat google,spherion-rev2.
10303 11:33:43.887372
10304 11:33:43.894344 Connected to device vid:did:rid of 1ae0:0028:00
10305 11:33:43.900922
10306 11:33:43.904424 tpm_get_response: command 0x17b, return code 0x0
10307 11:33:43.904943
10308 11:33:43.908004 ec_init: CrosEC protocol v3 supported (256, 248)
10309 11:33:43.911773
10310 11:33:43.914723 tpm_cleanup: add release locality here.
10311 11:33:43.915158
10312 11:33:43.915493 Shutting down all USB controllers.
10313 11:33:43.918300
10314 11:33:43.918740 Removing current net device
10315 11:33:43.919089
10316 11:33:43.925421 Exiting depthcharge with code 4 at timestamp: 77441060
10317 11:33:43.925940
10318 11:33:43.927940 LZMA decompressing kernel-1 to 0x821a6718
10319 11:33:43.928374
10320 11:33:43.931622 LZMA decompressing kernel-1 to 0x40000000
10321 11:33:45.547176
10322 11:33:45.547682 jumping to kernel
10323 11:33:45.549545 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10324 11:33:45.550215 start: 2.2.5 auto-login-action (timeout 00:03:30) [common]
10325 11:33:45.550763 Setting prompt string to ['Linux version [0-9]']
10326 11:33:45.551133 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10327 11:33:45.551485 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10328 11:33:45.627500
10329 11:33:45.630945 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10330 11:33:45.635216 start: 2.2.5.1 login-action (timeout 00:03:30) [common]
10331 11:33:45.635780 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10332 11:33:45.636149 Setting prompt string to []
10333 11:33:45.636553 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10334 11:33:45.636974 Using line separator: #'\n'#
10335 11:33:45.637300 No login prompt set.
10336 11:33:45.637611 Parsing kernel messages
10337 11:33:45.637890 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10338 11:33:45.638476 [login-action] Waiting for messages, (timeout 00:03:30)
10339 11:33:45.638813 Waiting using forced prompt support (timeout 00:01:45)
10340 11:33:45.653966 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10341 11:33:45.657410 [ 0.000000] random: crng init done
10342 11:33:45.660843 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10343 11:33:45.663554 [ 0.000000] efi: UEFI not found.
10344 11:33:45.673473 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10345 11:33:45.680356 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10346 11:33:45.690449 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10347 11:33:45.700170 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10348 11:33:45.706567 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10349 11:33:45.710490 [ 0.000000] printk: bootconsole [mtk8250] enabled
10350 11:33:45.718784 [ 0.000000] NUMA: No NUMA configuration found
10351 11:33:45.725072 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10352 11:33:45.732103 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10353 11:33:45.732604 [ 0.000000] Zone ranges:
10354 11:33:45.738185 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10355 11:33:45.741639 [ 0.000000] DMA32 empty
10356 11:33:45.748228 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10357 11:33:45.751000 [ 0.000000] Movable zone start for each node
10358 11:33:45.754931 [ 0.000000] Early memory node ranges
10359 11:33:45.761582 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10360 11:33:45.768162 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10361 11:33:45.774662 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10362 11:33:45.780987 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10363 11:33:45.787651 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10364 11:33:45.794193 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10365 11:33:45.851291 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10366 11:33:45.857896 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10367 11:33:45.865068 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10368 11:33:45.868019 [ 0.000000] psci: probing for conduit method from DT.
10369 11:33:45.874746 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10370 11:33:45.878280 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10371 11:33:45.884860 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10372 11:33:45.887750 [ 0.000000] psci: SMC Calling Convention v1.2
10373 11:33:45.894594 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10374 11:33:45.898167 [ 0.000000] Detected VIPT I-cache on CPU0
10375 11:33:45.904668 [ 0.000000] CPU features: detected: GIC system register CPU interface
10376 11:33:45.911596 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10377 11:33:45.918195 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10378 11:33:45.924257 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10379 11:33:45.931511 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10380 11:33:45.937840 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10381 11:33:45.944831 [ 0.000000] alternatives: applying boot alternatives
10382 11:33:45.948347 [ 0.000000] Fallback order for Node 0: 0
10383 11:33:45.958146 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10384 11:33:45.958578 [ 0.000000] Policy zone: Normal
10385 11:33:45.984649 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10386 11:33:45.994278 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10387 11:33:46.004290 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10388 11:33:46.014084 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10389 11:33:46.021041 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10390 11:33:46.023698 <6>[ 0.000000] software IO TLB: area num 8.
10391 11:33:46.081013 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10392 11:33:46.230461 <6>[ 0.000000] Memory: 7945784K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406984K reserved, 32768K cma-reserved)
10393 11:33:46.237193 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10394 11:33:46.243466 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10395 11:33:46.247024 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10396 11:33:46.253441 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10397 11:33:46.260287 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10398 11:33:46.263118 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10399 11:33:46.273920 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10400 11:33:46.280306 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10401 11:33:46.286739 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10402 11:33:46.293719 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10403 11:33:46.296372 <6>[ 0.000000] GICv3: 608 SPIs implemented
10404 11:33:46.300347 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10405 11:33:46.306573 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10406 11:33:46.309656 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10407 11:33:46.316073 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10408 11:33:46.329713 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10409 11:33:46.343042 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10410 11:33:46.349467 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10411 11:33:46.356872 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10412 11:33:46.370296 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10413 11:33:46.377137 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10414 11:33:46.383707 <6>[ 0.009181] Console: colour dummy device 80x25
10415 11:33:46.393429 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10416 11:33:46.399776 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10417 11:33:46.403673 <6>[ 0.029224] LSM: Security Framework initializing
10418 11:33:46.410318 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 11:33:46.420134 <6>[ 0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 11:33:46.426985 <6>[ 0.051439] cblist_init_generic: Setting adjustable number of callback queues.
10421 11:33:46.433733 <6>[ 0.058880] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 11:33:46.443671 <6>[ 0.065260] cblist_init_generic: Setting adjustable number of callback queues.
10423 11:33:46.447069 <6>[ 0.072686] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 11:33:46.453130 <6>[ 0.079077] rcu: Hierarchical SRCU implementation.
10425 11:33:46.459908 <6>[ 0.084093] rcu: Max phase no-delay instances is 1000.
10426 11:33:46.466315 <6>[ 0.091120] EFI services will not be available.
10427 11:33:46.470162 <6>[ 0.096105] smp: Bringing up secondary CPUs ...
10428 11:33:46.477779 <6>[ 0.101189] Detected VIPT I-cache on CPU1
10429 11:33:46.484315 <6>[ 0.101261] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 11:33:46.490673 <6>[ 0.101293] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 11:33:46.494680 <6>[ 0.101642] Detected VIPT I-cache on CPU2
10432 11:33:46.500680 <6>[ 0.101697] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 11:33:46.511057 <6>[ 0.101714] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 11:33:46.514486 <6>[ 0.101976] Detected VIPT I-cache on CPU3
10435 11:33:46.520780 <6>[ 0.102024] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 11:33:46.527949 <6>[ 0.102039] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 11:33:46.530850 <6>[ 0.102346] CPU features: detected: Spectre-v4
10438 11:33:46.537121 <6>[ 0.102353] CPU features: detected: Spectre-BHB
10439 11:33:46.540912 <6>[ 0.102359] Detected PIPT I-cache on CPU4
10440 11:33:46.547044 <6>[ 0.102421] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 11:33:46.553994 <6>[ 0.102438] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 11:33:46.560400 <6>[ 0.102732] Detected PIPT I-cache on CPU5
10443 11:33:46.567566 <6>[ 0.102796] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 11:33:46.573960 <6>[ 0.102812] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 11:33:46.577214 <6>[ 0.103096] Detected PIPT I-cache on CPU6
10446 11:33:46.583836 <6>[ 0.103163] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 11:33:46.590012 <6>[ 0.103178] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 11:33:46.596727 <6>[ 0.103481] Detected PIPT I-cache on CPU7
10449 11:33:46.603391 <6>[ 0.103546] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 11:33:46.610313 <6>[ 0.103561] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 11:33:46.613638 <6>[ 0.103610] smp: Brought up 1 node, 8 CPUs
10452 11:33:46.620067 <6>[ 0.244993] SMP: Total of 8 processors activated.
10453 11:33:46.623218 <6>[ 0.249945] CPU features: detected: 32-bit EL0 Support
10454 11:33:46.632943 <6>[ 0.255308] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 11:33:46.639944 <6>[ 0.264109] CPU features: detected: Common not Private translations
10456 11:33:46.646666 <6>[ 0.270585] CPU features: detected: CRC32 instructions
10457 11:33:46.649590 <6>[ 0.275936] CPU features: detected: RCpc load-acquire (LDAPR)
10458 11:33:46.656426 <6>[ 0.281896] CPU features: detected: LSE atomic instructions
10459 11:33:46.663364 <6>[ 0.287713] CPU features: detected: Privileged Access Never
10460 11:33:46.669660 <6>[ 0.293493] CPU features: detected: RAS Extension Support
10461 11:33:46.676271 <6>[ 0.299137] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 11:33:46.680128 <6>[ 0.306357] CPU: All CPU(s) started at EL2
10463 11:33:46.686518 <6>[ 0.310700] alternatives: applying system-wide alternatives
10464 11:33:46.695390 <6>[ 0.321581] devtmpfs: initialized
10465 11:33:46.707865 <6>[ 0.330336] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 11:33:46.717616 <6>[ 0.340297] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10467 11:33:46.724075 <6>[ 0.348538] pinctrl core: initialized pinctrl subsystem
10468 11:33:46.727760 <6>[ 0.355211] DMI not present or invalid.
10469 11:33:46.734084 <6>[ 0.359622] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10470 11:33:46.744693 <6>[ 0.366522] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10471 11:33:46.751522 <6>[ 0.374110] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10472 11:33:46.761125 <6>[ 0.382343] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10473 11:33:46.763966 <6>[ 0.390586] audit: initializing netlink subsys (disabled)
10474 11:33:46.773747 <5>[ 0.396280] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10475 11:33:46.780583 <6>[ 0.396988] thermal_sys: Registered thermal governor 'step_wise'
10476 11:33:46.787801 <6>[ 0.404248] thermal_sys: Registered thermal governor 'power_allocator'
10477 11:33:46.790627 <6>[ 0.410502] cpuidle: using governor menu
10478 11:33:46.797120 <6>[ 0.421462] NET: Registered PF_QIPCRTR protocol family
10479 11:33:46.803717 <6>[ 0.426962] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10480 11:33:46.810452 <6>[ 0.434065] ASID allocator initialised with 32768 entries
10481 11:33:46.814193 <6>[ 0.440638] Serial: AMBA PL011 UART driver
10482 11:33:46.823800 <4>[ 0.449986] Trying to register duplicate clock ID: 134
10483 11:33:46.882041 <6>[ 0.511321] KASLR enabled
10484 11:33:46.896403 <6>[ 0.518919] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10485 11:33:46.902979 <6>[ 0.525930] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10486 11:33:46.909624 <6>[ 0.532418] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10487 11:33:46.916801 <6>[ 0.539424] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10488 11:33:46.922686 <6>[ 0.545909] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10489 11:33:46.929618 <6>[ 0.552915] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10490 11:33:46.936223 <6>[ 0.559402] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10491 11:33:46.943397 <6>[ 0.566407] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10492 11:33:46.946133 <6>[ 0.573868] ACPI: Interpreter disabled.
10493 11:33:46.954416 <6>[ 0.580306] iommu: Default domain type: Translated
10494 11:33:46.960688 <6>[ 0.585458] iommu: DMA domain TLB invalidation policy: strict mode
10495 11:33:46.964112 <5>[ 0.592110] SCSI subsystem initialized
10496 11:33:46.970537 <6>[ 0.596353] usbcore: registered new interface driver usbfs
10497 11:33:46.977729 <6>[ 0.602082] usbcore: registered new interface driver hub
10498 11:33:46.981002 <6>[ 0.607631] usbcore: registered new device driver usb
10499 11:33:46.987552 <6>[ 0.613752] pps_core: LinuxPPS API ver. 1 registered
10500 11:33:46.997909 <6>[ 0.618944] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10501 11:33:47.000938 <6>[ 0.628282] PTP clock support registered
10502 11:33:47.004187 <6>[ 0.632522] EDAC MC: Ver: 3.0.0
10503 11:33:47.011656 <6>[ 0.637720] FPGA manager framework
10504 11:33:47.018632 <6>[ 0.641399] Advanced Linux Sound Architecture Driver Initialized.
10505 11:33:47.021489 <6>[ 0.648188] vgaarb: loaded
10506 11:33:47.027926 <6>[ 0.651374] clocksource: Switched to clocksource arch_sys_counter
10507 11:33:47.031795 <5>[ 0.657822] VFS: Disk quotas dquot_6.6.0
10508 11:33:47.038560 <6>[ 0.662007] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10509 11:33:47.041621 <6>[ 0.669197] pnp: PnP ACPI: disabled
10510 11:33:47.049760 <6>[ 0.675887] NET: Registered PF_INET protocol family
10511 11:33:47.059778 <6>[ 0.681475] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10512 11:33:47.071425 <6>[ 0.693789] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10513 11:33:47.080764 <6>[ 0.702603] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10514 11:33:47.087610 <6>[ 0.710576] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10515 11:33:47.097244 <6>[ 0.719277] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10516 11:33:47.103866 <6>[ 0.729035] TCP: Hash tables configured (established 65536 bind 65536)
10517 11:33:47.110474 <6>[ 0.735905] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 11:33:47.120687 <6>[ 0.743104] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 11:33:47.126869 <6>[ 0.750811] NET: Registered PF_UNIX/PF_LOCAL protocol family
10520 11:33:47.133298 <6>[ 0.756957] RPC: Registered named UNIX socket transport module.
10521 11:33:47.136816 <6>[ 0.763112] RPC: Registered udp transport module.
10522 11:33:47.143610 <6>[ 0.768044] RPC: Registered tcp transport module.
10523 11:33:47.150041 <6>[ 0.772975] RPC: Registered tcp NFSv4.1 backchannel transport module.
10524 11:33:47.153355 <6>[ 0.779639] PCI: CLS 0 bytes, default 64
10525 11:33:47.156446 <6>[ 0.783958] Unpacking initramfs...
10526 11:33:47.166364 <6>[ 0.788121] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10527 11:33:47.173021 <6>[ 0.796753] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10528 11:33:47.180381 <6>[ 0.805562] kvm [1]: IPA Size Limit: 40 bits
10529 11:33:47.183331 <6>[ 0.810087] kvm [1]: GICv3: no GICV resource entry
10530 11:33:47.189187 <6>[ 0.815106] kvm [1]: disabling GICv2 emulation
10531 11:33:47.196491 <6>[ 0.819793] kvm [1]: GIC system register CPU interface enabled
10532 11:33:47.199214 <6>[ 0.825956] kvm [1]: vgic interrupt IRQ18
10533 11:33:47.206265 <6>[ 0.831438] kvm [1]: VHE mode initialized successfully
10534 11:33:47.212563 <5>[ 0.837791] Initialise system trusted keyrings
10535 11:33:47.219181 <6>[ 0.842580] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10536 11:33:47.226673 <6>[ 0.852483] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10537 11:33:47.233109 <5>[ 0.858846] NFS: Registering the id_resolver key type
10538 11:33:47.236938 <5>[ 0.864143] Key type id_resolver registered
10539 11:33:47.243357 <5>[ 0.868557] Key type id_legacy registered
10540 11:33:47.250025 <6>[ 0.872835] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10541 11:33:47.256021 <6>[ 0.879755] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10542 11:33:47.262801 <6>[ 0.887456] 9p: Installing v9fs 9p2000 file system support
10543 11:33:47.299712 <5>[ 0.925522] Key type asymmetric registered
10544 11:33:47.302612 <5>[ 0.929851] Asymmetric key parser 'x509' registered
10545 11:33:47.313304 <6>[ 0.934985] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10546 11:33:47.315971 <6>[ 0.942599] io scheduler mq-deadline registered
10547 11:33:47.318937 <6>[ 0.947359] io scheduler kyber registered
10548 11:33:47.339011 <6>[ 0.964457] EINJ: ACPI disabled.
10549 11:33:47.371688 <4>[ 0.991050] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 11:33:47.381518 <4>[ 1.001686] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 11:33:47.396592 <6>[ 1.022501] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10552 11:33:47.404959 <6>[ 1.030642] printk: console [ttyS0] disabled
10553 11:33:47.432665 <6>[ 1.055279] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10554 11:33:47.439196 <6>[ 1.064752] printk: console [ttyS0] enabled
10555 11:33:47.442776 <6>[ 1.064752] printk: console [ttyS0] enabled
10556 11:33:47.449942 <6>[ 1.073645] printk: bootconsole [mtk8250] disabled
10557 11:33:47.452301 <6>[ 1.073645] printk: bootconsole [mtk8250] disabled
10558 11:33:47.458945 <6>[ 1.084706] SuperH (H)SCI(F) driver initialized
10559 11:33:47.462762 <6>[ 1.089992] msm_serial: driver initialized
10560 11:33:47.476631 <6>[ 1.098988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10561 11:33:47.486829 <6>[ 1.107534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10562 11:33:47.493529 <6>[ 1.116076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10563 11:33:47.502846 <6>[ 1.124704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10564 11:33:47.509989 <6>[ 1.133410] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10565 11:33:47.519470 <6>[ 1.142123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10566 11:33:47.529372 <6>[ 1.150663] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10567 11:33:47.535923 <6>[ 1.159466] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10568 11:33:47.545947 <6>[ 1.168008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10569 11:33:47.557389 <6>[ 1.183289] loop: module loaded
10570 11:33:47.564139 <6>[ 1.189331] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10571 11:33:47.586814 <4>[ 1.212576] mtk-pmic-keys: Failed to locate of_node [id: -1]
10572 11:33:47.593109 <6>[ 1.219270] megasas: 07.719.03.00-rc1
10573 11:33:47.602862 <6>[ 1.228946] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10574 11:33:47.609918 <6>[ 1.234764] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10575 11:33:47.625909 <6>[ 1.251596] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10576 11:33:47.682508 <6>[ 1.301675] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10577 11:33:47.956616 <6>[ 1.582264] Freeing initrd memory: 18272K
10578 11:33:47.967495 <6>[ 1.593848] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10579 11:33:47.979038 <6>[ 1.604732] tun: Universal TUN/TAP device driver, 1.6
10580 11:33:47.982055 <6>[ 1.610805] thunder_xcv, ver 1.0
10581 11:33:47.986253 <6>[ 1.614310] thunder_bgx, ver 1.0
10582 11:33:47.989145 <6>[ 1.617808] nicpf, ver 1.0
10583 11:33:47.999860 <6>[ 1.621835] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10584 11:33:48.002661 <6>[ 1.629311] hns3: Copyright (c) 2017 Huawei Corporation.
10585 11:33:48.006071 <6>[ 1.634900] hclge is initializing
10586 11:33:48.012533 <6>[ 1.638475] e1000: Intel(R) PRO/1000 Network Driver
10587 11:33:48.019413 <6>[ 1.643604] e1000: Copyright (c) 1999-2006 Intel Corporation.
10588 11:33:48.022810 <6>[ 1.649617] e1000e: Intel(R) PRO/1000 Network Driver
10589 11:33:48.029192 <6>[ 1.654833] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10590 11:33:48.035906 <6>[ 1.661021] igb: Intel(R) Gigabit Ethernet Network Driver
10591 11:33:48.042610 <6>[ 1.666671] igb: Copyright (c) 2007-2014 Intel Corporation.
10592 11:33:48.049577 <6>[ 1.672508] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10593 11:33:48.055990 <6>[ 1.679027] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10594 11:33:48.058644 <6>[ 1.685489] sky2: driver version 1.30
10595 11:33:48.065604 <6>[ 1.690425] usbcore: registered new device driver r8152-cfgselector
10596 11:33:48.072024 <6>[ 1.696961] usbcore: registered new interface driver r8152
10597 11:33:48.075643 <6>[ 1.702780] VFIO - User Level meta-driver version: 0.3
10598 11:33:48.085310 <6>[ 1.711033] usbcore: registered new interface driver usb-storage
10599 11:33:48.091967 <6>[ 1.717480] usbcore: registered new device driver onboard-usb-hub
10600 11:33:48.100826 <6>[ 1.726663] mt6397-rtc mt6359-rtc: registered as rtc0
10601 11:33:48.110587 <6>[ 1.732130] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:33:47 UTC (1721216027)
10602 11:33:48.113859 <6>[ 1.741690] i2c_dev: i2c /dev entries driver
10603 11:33:48.127743 <4>[ 1.753649] cpu cpu0: supply cpu not found, using dummy regulator
10604 11:33:48.134790 <4>[ 1.760072] cpu cpu1: supply cpu not found, using dummy regulator
10605 11:33:48.140960 <4>[ 1.766475] cpu cpu2: supply cpu not found, using dummy regulator
10606 11:33:48.148126 <4>[ 1.772879] cpu cpu3: supply cpu not found, using dummy regulator
10607 11:33:48.154081 <4>[ 1.779292] cpu cpu4: supply cpu not found, using dummy regulator
10608 11:33:48.160931 <4>[ 1.785686] cpu cpu5: supply cpu not found, using dummy regulator
10609 11:33:48.167715 <4>[ 1.792103] cpu cpu6: supply cpu not found, using dummy regulator
10610 11:33:48.174280 <4>[ 1.798501] cpu cpu7: supply cpu not found, using dummy regulator
10611 11:33:48.194276 <6>[ 1.820139] cpu cpu0: EM: created perf domain
10612 11:33:48.197731 <6>[ 1.825067] cpu cpu4: EM: created perf domain
10613 11:33:48.205013 <6>[ 1.830658] sdhci: Secure Digital Host Controller Interface driver
10614 11:33:48.211148 <6>[ 1.837092] sdhci: Copyright(c) Pierre Ossman
10615 11:33:48.218678 <6>[ 1.842054] Synopsys Designware Multimedia Card Interface Driver
10616 11:33:48.224600 <6>[ 1.848692] sdhci-pltfm: SDHCI platform and OF driver helper
10617 11:33:48.228103 <6>[ 1.848740] mmc0: CQHCI version 5.10
10618 11:33:48.235044 <6>[ 1.858657] ledtrig-cpu: registered to indicate activity on CPUs
10619 11:33:48.241136 <6>[ 1.865633] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10620 11:33:48.248103 <6>[ 1.872697] usbcore: registered new interface driver usbhid
10621 11:33:48.251219 <6>[ 1.878519] usbhid: USB HID core driver
10622 11:33:48.257472 <6>[ 1.882717] spi_master spi0: will run message pump with realtime priority
10623 11:33:48.300163 <6>[ 1.919735] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10624 11:33:48.319237 <6>[ 1.934931] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10625 11:33:48.325987 <6>[ 1.949387] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10626 11:33:48.329074 <6>[ 1.955662] cros-ec-spi spi0.0: Chrome EC device registered
10627 11:33:48.336325 <6>[ 1.961683] mmc0: Command Queue Engine enabled
10628 11:33:48.343012 <6>[ 1.966432] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10629 11:33:48.346369 <6>[ 1.974118] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 11:33:48.357681 <6>[ 1.983491] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10631 11:33:48.365414 <6>[ 1.991345] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10632 11:33:48.375856 <6>[ 1.995154] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10633 11:33:48.378436 <6>[ 1.997281] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10634 11:33:48.385549 <6>[ 2.007084] NET: Registered PF_PACKET protocol family
10635 11:33:48.392371 <6>[ 2.011866] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 11:33:48.395382 <6>[ 2.016481] 9pnet: Installing 9P2000 support
10637 11:33:48.402097 <5>[ 2.027500] Key type dns_resolver registered
10638 11:33:48.405747 <6>[ 2.032524] registered taskstats version 1
10639 11:33:48.412860 <5>[ 2.036910] Loading compiled-in X.509 certificates
10640 11:33:48.439707 <4>[ 2.059325] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 11:33:48.450202 <4>[ 2.070087] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 11:33:48.465300 <6>[ 2.091259] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10643 11:33:48.472101 <6>[ 2.098179] xhci-mtk 11200000.usb: xHCI Host Controller
10644 11:33:48.478466 <6>[ 2.103703] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10645 11:33:48.489752 <6>[ 2.111572] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10646 11:33:48.496080 <6>[ 2.121003] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10647 11:33:48.502253 <6>[ 2.127161] xhci-mtk 11200000.usb: xHCI Host Controller
10648 11:33:48.508974 <6>[ 2.132655] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10649 11:33:48.515822 <6>[ 2.140304] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10650 11:33:48.522405 <6>[ 2.148136] hub 1-0:1.0: USB hub found
10651 11:33:48.525991 <6>[ 2.152161] hub 1-0:1.0: 1 port detected
10652 11:33:48.532193 <6>[ 2.156449] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10653 11:33:48.539417 <6>[ 2.165193] hub 2-0:1.0: USB hub found
10654 11:33:48.542496 <6>[ 2.169217] hub 2-0:1.0: 1 port detected
10655 11:33:48.549880 <6>[ 2.175510] mtk-msdc 11f70000.mmc: Got CD GPIO
10656 11:33:48.563997 <6>[ 2.186143] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10657 11:33:48.570168 <6>[ 2.194528] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10658 11:33:48.579872 <6>[ 2.202871] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10659 11:33:48.587600 <6>[ 2.211211] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10660 11:33:48.596955 <6>[ 2.219555] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10661 11:33:48.603896 <6>[ 2.227894] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10662 11:33:48.613908 <6>[ 2.236235] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10663 11:33:48.623947 <6>[ 2.244579] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10664 11:33:48.630274 <6>[ 2.252921] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10665 11:33:48.640654 <6>[ 2.261260] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10666 11:33:48.646979 <6>[ 2.269598] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10667 11:33:48.656572 <6>[ 2.277943] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10668 11:33:48.663088 <6>[ 2.286282] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10669 11:33:48.673446 <6>[ 2.294620] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10670 11:33:48.679969 <6>[ 2.302958] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10671 11:33:48.686905 <6>[ 2.311669] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10672 11:33:48.693277 <6>[ 2.318838] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10673 11:33:48.699773 <6>[ 2.325609] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10674 11:33:48.706637 <6>[ 2.332377] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10675 11:33:48.716739 <6>[ 2.339307] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10676 11:33:48.723495 <6>[ 2.346151] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10677 11:33:48.733040 <6>[ 2.355283] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10678 11:33:48.743544 <6>[ 2.364406] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10679 11:33:48.753222 <6>[ 2.373704] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10680 11:33:48.763534 <6>[ 2.383174] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10681 11:33:48.769369 <6>[ 2.392644] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10682 11:33:48.779841 <6>[ 2.401764] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10683 11:33:48.789544 <6>[ 2.411233] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10684 11:33:48.799271 <6>[ 2.420353] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10685 11:33:48.809423 <6>[ 2.429649] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10686 11:33:48.819155 <6>[ 2.439811] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10687 11:33:48.828841 <6>[ 2.451131] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10688 11:33:48.836009 <6>[ 2.462238] Trying to probe devices needed for running init ...
10689 11:33:48.846417 <3>[ 2.469400] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10690 11:33:48.945012 <6>[ 2.567640] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10691 11:33:49.098814 <6>[ 2.724751] hub 1-1:1.0: USB hub found
10692 11:33:49.102621 <6>[ 2.729222] hub 1-1:1.0: 4 ports detected
10693 11:33:49.113405 <6>[ 2.739178] hub 1-1:1.0: USB hub found
10694 11:33:49.116405 <6>[ 2.743585] hub 1-1:1.0: 4 ports detected
10695 11:33:49.225143 <6>[ 2.848068] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 11:33:49.252455 <6>[ 2.878599] hub 2-1:1.0: USB hub found
10697 11:33:49.255578 <6>[ 2.883029] hub 2-1:1.0: 3 ports detected
10698 11:33:49.269137 <6>[ 2.894915] hub 2-1:1.0: USB hub found
10699 11:33:49.271861 <6>[ 2.899402] hub 2-1:1.0: 3 ports detected
10700 11:33:49.436764 <6>[ 3.059685] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10701 11:33:49.569174 <6>[ 3.195287] hub 1-1.4:1.0: USB hub found
10702 11:33:49.572354 <6>[ 3.199963] hub 1-1.4:1.0: 2 ports detected
10703 11:33:49.584648 <6>[ 3.211077] hub 1-1.4:1.0: USB hub found
10704 11:33:49.587979 <6>[ 3.215744] hub 1-1.4:1.0: 2 ports detected
10705 11:33:49.649125 <6>[ 3.271799] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10706 11:33:49.757186 <6>[ 3.380313] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 11:33:49.793704 <4>[ 3.416923] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10708 11:33:49.804446 <4>[ 3.426032] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10709 11:33:49.842919 <6>[ 3.469198] r8152 2-1.3:1.0 eth0: v1.12.13
10710 11:33:49.888671 <6>[ 3.511435] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10711 11:33:50.080812 <6>[ 3.703535] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10712 11:33:51.547730 <6>[ 5.174392] r8152 2-1.3:1.0 eth0: carrier on
10713 11:33:53.752780 <5>[ 5.195448] Sending DHCP requests .., OK
10714 11:33:53.759842 <6>[ 7.383962] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10715 11:33:53.763253 <6>[ 7.392264] IP-Config: Complete:
10716 11:33:53.776372 <6>[ 7.395758] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10717 11:33:53.782813 <6>[ 7.406464] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10718 11:33:53.789636 <6>[ 7.415078] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10719 11:33:53.796143 <6>[ 7.415088] nameserver0=192.168.201.1
10720 11:33:53.799438 <6>[ 7.427256] clk: Disabling unused clocks
10721 11:33:53.802957 <6>[ 7.432831] ALSA device list:
10722 11:33:53.809563 <6>[ 7.436110] No soundcards found.
10723 11:33:53.817193 <6>[ 7.443992] Freeing unused kernel memory: 8512K
10724 11:33:53.820262 <6>[ 7.448880] Run /init as init process
10725 11:33:53.830673 Loading, please wait...
10726 11:33:53.856040 Starting systemd-udevd version 252.22-1~deb12u1
10727 11:33:54.121252 <6>[ 7.744579] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10728 11:33:54.141435 <6>[ 7.765134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10729 11:33:54.148654 <6>[ 7.773311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10730 11:33:54.158316 <4>[ 7.781335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10731 11:33:54.168330 <6>[ 7.791099] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10732 11:33:54.174785 <6>[ 7.799305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10733 11:33:54.181414 <6>[ 7.803197] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10734 11:33:54.194743 <6>[ 7.818296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10735 11:33:54.201590 <6>[ 7.826261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10736 11:33:54.211322 <6>[ 7.834081] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10737 11:33:54.214894 <6>[ 7.836913] remoteproc remoteproc0: scp is available
10738 11:33:54.224728 <6>[ 7.837312] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10739 11:33:54.231130 <6>[ 7.837339] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10740 11:33:54.240836 <6>[ 7.837347] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10741 11:33:54.251176 <6>[ 7.841899] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10742 11:33:54.254244 <6>[ 7.881490] remoteproc remoteproc0: powering up scp
10743 11:33:54.264106 <6>[ 7.886685] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10744 11:33:54.270842 <4>[ 7.889485] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10745 11:33:54.277643 <6>[ 7.895131] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10746 11:33:54.287078 <3>[ 7.909772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 11:33:54.294331 <4>[ 7.913751] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10748 11:33:54.297576 <6>[ 7.913816] mc: Linux media interface: v0.10
10749 11:33:54.306955 <3>[ 7.917996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 11:33:54.314550 <3>[ 7.938052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:33:54.337240 <3>[ 7.960720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:33:54.343838 <3>[ 7.968957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:33:54.350739 <6>[ 7.971855] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10754 11:33:54.360396 <3>[ 7.977050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 11:33:54.367018 <3>[ 7.977062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:33:54.376952 <3>[ 7.977069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:33:54.383887 <6>[ 8.008514] pci_bus 0000:00: root bus resource [bus 00-ff]
10758 11:33:54.390418 <6>[ 8.014280] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10759 11:33:54.400234 <6>[ 8.016979] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10760 11:33:54.410468 <6>[ 8.021435] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10761 11:33:54.416714 <6>[ 8.033526] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10762 11:33:54.426992 <6>[ 8.033584] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10763 11:33:54.433873 <6>[ 8.033594] remoteproc remoteproc0: remote processor scp is now up
10764 11:33:54.436903 <6>[ 8.041471] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10765 11:33:54.446963 <3>[ 8.049540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 11:33:54.453477 <6>[ 8.057023] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10767 11:33:54.456432 <6>[ 8.057103] pci 0000:00:00.0: supports D1 D2
10768 11:33:54.466908 <6>[ 8.064295] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10769 11:33:54.472909 <6>[ 8.069708] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10770 11:33:54.479780 <6>[ 8.070743] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10771 11:33:54.490176 <6>[ 8.087719] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10772 11:33:54.499716 <3>[ 8.089114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 11:33:54.506368 <3>[ 8.089128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:33:54.515986 <3>[ 8.089133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 11:33:54.519267 <6>[ 8.139687] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10776 11:33:54.529469 <3>[ 8.139704] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 11:33:54.535884 <3>[ 8.139728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 11:33:54.545635 <3>[ 8.139789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 11:33:54.552393 <3>[ 8.139807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 11:33:54.562261 <3>[ 8.139815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 11:33:54.568971 <4>[ 8.155604] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10782 11:33:54.575146 <4>[ 8.155604] Fallback method does not support PEC.
10783 11:33:54.582217 <6>[ 8.161104] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 11:33:54.589425 <3>[ 8.161362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 11:33:54.599077 <6>[ 8.161912] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10786 11:33:54.606481 <6>[ 8.186101] videodev: Linux video capture interface: v2.00
10787 11:33:54.613365 <6>[ 8.193011] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10788 11:33:54.619672 <6>[ 8.193027] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10789 11:33:54.629397 <6>[ 8.208712] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10790 11:33:54.632864 <6>[ 8.214270] pci 0000:01:00.0: supports D1 D2
10791 11:33:54.635838 <6>[ 8.214750] Bluetooth: Core ver 2.22
10792 11:33:54.642304 <6>[ 8.214810] NET: Registered PF_BLUETOOTH protocol family
10793 11:33:54.649247 <6>[ 8.214814] Bluetooth: HCI device and connection manager initialized
10794 11:33:54.655630 <6>[ 8.214838] Bluetooth: HCI socket layer initialized
10795 11:33:54.659524 <6>[ 8.214845] Bluetooth: L2CAP socket layer initialized
10796 11:33:54.665808 <6>[ 8.214852] Bluetooth: SCO socket layer initialized
10797 11:33:54.672985 <3>[ 8.221148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 11:33:54.682280 <3>[ 8.241985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 11:33:54.688788 <6>[ 8.244463] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10800 11:33:54.698670 <6>[ 8.246100] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10801 11:33:54.706011 <6>[ 8.255503] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10802 11:33:54.708912 <6>[ 8.266631] usbcore: registered new interface driver btusb
10803 11:33:54.722390 <4>[ 8.267630] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10804 11:33:54.725882 <3>[ 8.267638] Bluetooth: hci0: Failed to load firmware file (-2)
10805 11:33:54.732477 <3>[ 8.267640] Bluetooth: hci0: Failed to set up firmware (-2)
10806 11:33:54.741724 <4>[ 8.267643] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 11:33:54.748189 <6>[ 8.267829] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10808 11:33:54.758634 <6>[ 8.268752] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10809 11:33:54.771342 <6>[ 8.269315] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10810 11:33:54.778722 <6>[ 8.269459] usbcore: registered new interface driver uvcvideo
10811 11:33:54.781112 <6>[ 8.275191] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10812 11:33:54.791339 <6>[ 8.280899] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10813 11:33:54.797789 <6>[ 8.280918] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10814 11:33:54.808001 <6>[ 8.280931] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10815 11:33:54.815129 <6>[ 8.280944] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10816 11:33:54.821167 <6>[ 8.446671] pci 0000:00:00.0: PCI bridge to [bus 01]
10817 11:33:54.828394 <6>[ 8.451918] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10818 11:33:54.834147 <6>[ 8.460078] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10819 11:33:54.840848 <6>[ 8.466888] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10820 11:33:54.847541 <6>[ 8.473560] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10821 11:33:54.864643 <5>[ 8.487701] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10822 11:33:54.888862 <5>[ 8.512542] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 11:33:54.895500 <5>[ 8.519667] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10824 11:33:54.905825 <4>[ 8.528094] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 11:33:54.908647 <6>[ 8.536986] cfg80211: failed to load regulatory.db
10826 11:33:54.959415 <6>[ 8.582993] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 11:33:54.966376 <6>[ 8.590589] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 11:33:54.988758 <6>[ 8.615744] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 11:33:55.092519 <6>[ 8.715782] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10830 11:33:55.095706 <6>[ 8.715782]
10831 11:33:55.103000 Begin: Loading essential drivers ... done.
10832 11:33:55.106644 Begin: Running /scripts/init-premount ... done.
10833 11:33:55.112793 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10834 11:33:55.123008 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10835 11:33:55.126186 Device /sys/class/net/eth0 found
10836 11:33:55.126607 done.
10837 11:33:55.153496 Begin: Waiting up to 180 secs for any network device to become available ... done.
10838 11:33:55.204387 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10839 11:33:55.212473 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10840 11:33:55.219509 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10841 11:33:55.226040 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10842 11:33:55.232994 host : mt8192-asurada-spherion-r0-cbg-8
10843 11:33:55.239175 domain : lava-rack
10844 11:33:55.242388 rootserver: 192.168.201.1 rootpath:
10845 11:33:55.245539 filename :
10846 11:33:55.308306 done.
10847 11:33:55.316599 Begin: Running /scripts/nfs-bottom ... done.
10848 11:33:55.329072 Begin: Running /scripts/init-bottom ... done.
10849 11:33:55.363441 <6>[ 8.987489] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10850 11:33:56.756982 <6>[ 10.383974] NET: Registered PF_INET6 protocol family
10851 11:33:56.765158 <6>[ 10.391554] Segment Routing with IPv6
10852 11:33:56.768057 <6>[ 10.395562] In-situ OAM (IOAM) with IPv6
10853 11:33:56.956235 <30>[ 10.556961] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10854 11:33:56.963395 <30>[ 10.590253] systemd[1]: Detected architecture arm64.
10855 11:33:56.983970
10856 11:33:56.987369 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10857 11:33:56.987963
10858 11:33:57.010358 <30>[ 10.637426] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10859 11:33:58.240335 <30>[ 11.864632] systemd[1]: Queued start job for default target graphical.target.
10860 11:33:58.276780 <30>[ 11.900579] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10861 11:33:58.283083 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10862 11:33:58.305292 <30>[ 11.929418] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10863 11:33:58.315668 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10864 11:33:58.333678 <30>[ 11.957379] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10865 11:33:58.343285 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10866 11:33:58.361048 <30>[ 11.985053] systemd[1]: Created slice user.slice - User and Session Slice.
10867 11:33:58.368067 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10868 11:33:58.391869 <30>[ 12.012543] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10869 11:33:58.402257 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10870 11:33:58.419540 <30>[ 12.039922] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10871 11:33:58.426247 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10872 11:33:58.454644 <30>[ 12.068309] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10873 11:33:58.464923 <30>[ 12.088218] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10874 11:33:58.470823 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10875 11:33:58.488349 <30>[ 12.112446] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10876 11:33:58.498724 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10877 11:33:58.515728 <30>[ 12.139572] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10878 11:33:58.525517 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10879 11:33:58.540744 <30>[ 12.167772] systemd[1]: Reached target paths.target - Path Units.
10880 11:33:58.550269 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10881 11:33:58.568593 <30>[ 12.192150] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10882 11:33:58.574849 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10883 11:33:58.588384 <30>[ 12.215668] systemd[1]: Reached target slices.target - Slice Units.
10884 11:33:58.598803 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10885 11:33:58.612432 <30>[ 12.239717] systemd[1]: Reached target swap.target - Swaps.
10886 11:33:58.619624 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10887 11:33:58.640586 <30>[ 12.264185] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10888 11:33:58.649818 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10889 11:33:58.668907 <30>[ 12.292632] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10890 11:33:58.678689 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10891 11:33:58.699395 <30>[ 12.323361] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10892 11:33:58.709187 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10893 11:33:58.725274 <30>[ 12.349379] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10894 11:33:58.735463 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10895 11:33:58.752441 <30>[ 12.376347] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10896 11:33:58.759013 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10897 11:33:58.777282 <30>[ 12.401444] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10898 11:33:58.787417 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10899 11:33:58.808711 <30>[ 12.432177] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10900 11:33:58.817968 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10901 11:33:58.836241 <30>[ 12.460203] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10902 11:33:58.845978 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10903 11:33:58.903863 <30>[ 12.527887] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10904 11:33:58.910557 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10905 11:33:58.932511 <30>[ 12.556226] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10906 11:33:58.938890 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10907 11:33:58.964307 <30>[ 12.588398] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10908 11:33:58.970920 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10909 11:33:58.998504 <30>[ 12.615960] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10910 11:33:59.048696 <30>[ 12.672311] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10911 11:33:59.057995 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10912 11:33:59.081309 <30>[ 12.705164] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10913 11:33:59.087812 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10914 11:33:59.111258 <30>[ 12.735418] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10915 11:33:59.117863 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10916 11:33:59.139819 <30>[ 12.763770] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10917 11:33:59.146075 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10918 11:33:59.162965 <6>[ 12.786875] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10919 11:33:59.177284 <30>[ 12.801026] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10920 11:33:59.186683 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10921 11:33:59.208087 <30>[ 12.831820] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10922 11:33:59.214263 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10923 11:33:59.235542 <30>[ 12.859501] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10924 11:33:59.242078 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10925 11:33:59.253451 <6>[ 12.880558] fuse: init (API version 7.37)
10926 11:33:59.300584 <30>[ 12.924589] systemd[1]: Starting systemd-journald.service - Journal Service...
10927 11:33:59.307816 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10928 11:33:59.343710 <30>[ 12.967312] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10929 11:33:59.349728 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10930 11:33:59.374770 <30>[ 12.995337] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10931 11:33:59.381255 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10932 11:33:59.406623 <30>[ 13.030819] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10933 11:33:59.417573 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10934 11:33:59.440267 <30>[ 13.064548] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10935 11:33:59.450241 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10936 11:33:59.474385 <30>[ 13.098011] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10937 11:33:59.480538 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10938 11:33:59.500488 <30>[ 13.124436] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10939 11:33:59.507175 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10940 11:33:59.528860 <30>[ 13.152723] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10941 11:33:59.535657 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10942 11:33:59.547897 <3>[ 13.171827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:33:59.557955 <30>[ 13.181551] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10944 11:33:59.567948 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10945 11:33:59.579028 <3>[ 13.203303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 11:33:59.589516 <30>[ 13.213501] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10947 11:33:59.596305 <30>[ 13.221501] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10948 11:33:59.606211 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10949 11:33:59.625184 <30>[ 13.248922] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10950 11:33:59.632061 <3>[ 13.249871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 11:33:59.641272 <30>[ 13.256714] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10952 11:33:59.648330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10953 11:33:59.662158 <3>[ 13.285560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:33:59.672306 <30>[ 13.296172] systemd[1]: modprobe@drm.service: Deactivated successfully.
10955 11:33:59.679551 <30>[ 13.303583] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10956 11:33:59.695943 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.317333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 11:33:59.696452 ule drm.
10958 11:33:59.713546 <30>[ 13.337129] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10959 11:33:59.720105 <30>[ 13.345159] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10960 11:33:59.730316 <3>[ 13.348418] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 11:33:59.740324 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10962 11:33:59.758207 <30>[ 13.381585] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10963 11:33:59.764761 <3>[ 13.386598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:33:59.774539 <30>[ 13.389417] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10965 11:33:59.781088 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10966 11:33:59.796091 <3>[ 13.419778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:33:59.806817 <30>[ 13.430694] systemd[1]: modprobe@loop.service: Deactivated successfully.
10968 11:33:59.813815 <30>[ 13.438773] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10969 11:33:59.830232 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m <3>[ 13.452039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:33:59.830796 - Load Kernel Module loop.
10971 11:33:59.849471 <30>[ 13.473139] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10972 11:33:59.859404 [[0;32m OK [0m] Finished [0<3>[ 13.483643] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 11:33:59.865735 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10974 11:33:59.888447 <30>[ 13.508578] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10975 11:33:59.898787 [[0;32m OK [<3>[ 13.519845] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 11:33:59.905562 0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10977 11:33:59.917297 <3>[ 13.540742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:33:59.934196 <4>[ 13.549549] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10979 11:33:59.940746 <30>[ 13.550966] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10980 11:33:59.951197 <3>[ 13.565180] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10981 11:33:59.957848 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10982 11:33:59.976405 <30>[ 13.600664] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10983 11:33:59.986668 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10984 11:34:00.003816 <30>[ 13.628184] systemd[1]: Started systemd-journald.service - Journal Service.
10985 11:34:00.010716 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10986 11:34:00.037503 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10987 11:34:00.088391 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10988 11:34:00.109979 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10989 11:34:00.136984 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10990 11:34:00.165265 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10991 11:34:00.202506 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10992 11:34:00.213367 <46>[ 13.837638] systemd-journald[310]: Received client request to flush runtime journal.
10993 11:34:00.228764 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10994 11:34:00.259576 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10995 11:34:00.280279 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10996 11:34:00.300572 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10997 11:34:00.457915 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10998 11:34:01.328442 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10999 11:34:01.372436 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11000 11:34:01.634728 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11001 11:34:01.762975 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11002 11:34:01.784233 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11003 11:34:01.803851 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11004 11:34:01.856644 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11005 11:34:01.879372 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11006 11:34:02.153883 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11007 11:34:02.219355 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11008 11:34:02.245199 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11009 11:34:02.556203 <6>[ 16.184028] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11010 11:34:02.590060 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11011 11:34:02.637706 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11012 11:34:02.659391 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11013 11:34:02.693740 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11014 11:34:02.816371 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11015 11:34:02.841118 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11016 11:34:02.868606 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11017 11:34:02.910139 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11018 11:34:02.940809 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11019 11:34:02.973718 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11020 11:34:02.993046 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11021 11:34:03.045646 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11022 11:34:03.065178 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11023 11:34:03.084625 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11024 11:34:03.104114 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11025 11:34:03.123130 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11026 11:34:03.147226 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11027 11:34:03.171401 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11028 11:34:03.192139 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11029 11:34:03.211682 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11030 11:34:03.232196 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11031 11:34:03.251358 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11032 11:34:03.270294 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11033 11:34:03.287372 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11034 11:34:03.303974 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11035 11:34:03.345081 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11036 11:34:03.380673 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11037 11:34:03.500110 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11038 11:34:03.525718 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11039 11:34:03.544063 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11040 11:34:03.567501 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11041 11:34:03.613633 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11042 11:34:03.639884 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11043 11:34:03.665242 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11044 11:34:03.680690 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11045 11:34:03.740339 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11046 11:34:03.891351 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11047 11:34:03.917205 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11048 11:34:03.941553 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11049 11:34:04.002028 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11050 11:34:04.085804 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11051 11:34:04.186254
11052 11:34:04.188926 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11053 11:34:04.189369
11054 11:34:04.192258 debian-bookworm-arm64 login: root (automatic login)
11055 11:34:04.192701
11056 11:34:04.488543 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11057 11:34:04.489035
11058 11:34:04.495159 The programs included with the Debian GNU/Linux system are free software;
11059 11:34:04.501830 the exact distribution terms for each program are described in the
11060 11:34:04.504797 individual files in /usr/share/doc/*/copyright.
11061 11:34:04.505252
11062 11:34:04.511683 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11063 11:34:04.514833 permitted by applicable law.
11064 11:34:04.647993 Matched prompt #10: / #
11066 11:34:04.649016 Setting prompt string to ['/ #']
11067 11:34:04.649424 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11069 11:34:04.650378 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11070 11:34:04.650790 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
11071 11:34:04.651114 Setting prompt string to ['/ #']
11072 11:34:04.651396 Forcing a shell prompt, looking for ['/ #']
11073 11:34:04.651701 Sending line: ''
11075 11:34:04.703413 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11076 11:34:04.703914 Waiting using forced prompt support (timeout 00:02:30)
11077 11:34:04.709038 / #
11078 11:34:04.710197 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11079 11:34:04.711030 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
11080 11:34:04.711448 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r'"
11082 11:34:04.818724 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864572/extract-nfsrootfs-qjpl3y4r'
11083 11:34:04.819516 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11085 11:34:04.927261 / # export NFS_SERVER_IP='192.168.201.1'
11086 11:34:04.928132 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11087 11:34:04.928669 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
11088 11:34:04.929145 end: 2 depthcharge-action (duration 00:01:49) [common]
11089 11:34:04.929616 start: 3 lava-test-retry (timeout 00:01:00) [common]
11090 11:34:04.930060 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11091 11:34:04.930475 Using namespace: common
11092 11:34:04.930830 Sending line: '#'
11094 11:34:05.032439 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11095 11:34:05.038639 / # #
11096 11:34:05.039457 Using /lava-14864572
11097 11:34:05.039815 Sending line: 'export SHELL=/bin/sh'
11099 11:34:05.147400 / # export SHELL=/bin/sh
11100 11:34:05.148153 Sending line: '. /lava-14864572/environment'
11102 11:34:05.255775 / # . /lava-14864572/environment
11103 11:34:05.263067 Sending line: '/lava-14864572/bin/lava-test-runner /lava-14864572/0'
11105 11:34:05.364352 Test shell timeout: 10s (minimum of the action and connection timeout)
11106 11:34:05.370293 / # /lava-14864572/bin/lava-test-runner /lava-14864572/0
11107 11:34:05.650012 + export TESTRUN_ID=0_dmesg
11108 11:34:05.653287 + cd /lava-14864572/0/tests/0_dmesg
11109 11:34:05.656895 + cat uuid
11110 11:34:05.675803 + UUID=14864572_1.<8>[ 19.300779] <LAVA_SIGNAL_STARTRUN 0_dmesg 14864572_1.6.2.3.1>
11111 11:34:05.676300 6.2.3.1
11112 11:34:05.676644 + set +x
11113 11:34:05.677236 Received signal: <STARTRUN> 0_dmesg 14864572_1.6.2.3.1
11114 11:34:05.677608 Starting test lava.0_dmesg (14864572_1.6.2.3.1)
11115 11:34:05.677996 Skipping test definition patterns.
11116 11:34:05.682256 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11117 11:34:05.818652 <8>[ 19.443737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11118 11:34:05.819343 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11120 11:34:05.923238 <8>[ 19.547592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11121 11:34:05.924005 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11123 11:34:06.027344 <8>[ 19.651682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11124 11:34:06.028171 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11126 11:34:06.030144 + set +x
11127 11:34:06.033545 Received signal: <ENDRUN> 0_dmesg 14864572_1.6.2.3.1
11128 11:34:06.034038 Ending use of test pattern.
11129 11:34:06.034475 Ending test lava.0_dmesg (14864572_1.6.2.3.1), duration 0.36
11131 11:34:06.036434 <8>[ 19.661628] <LAVA_SIGNAL_ENDRUN 0_dmesg 14864572_1.6.2.3.1>
11132 11:34:06.044892 <LAVA_TEST_RUNNER EXIT>
11133 11:34:06.045555 ok: lava_test_shell seems to have completed
11134 11:34:06.046083 crit: pass
alert: pass
emerg: pass
11135 11:34:06.046572 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11136 11:34:06.047024 end: 3 lava-test-retry (duration 00:00:01) [common]
11137 11:34:06.047459 start: 4 finalize (timeout 00:07:42) [common]
11138 11:34:06.047899 start: 4.1 power-off (timeout 00:00:30) [common]
11139 11:34:06.048541 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11140 11:34:08.166221 >> Command sent successfully.
11141 11:34:08.180062 Returned 0 in 2 seconds
11142 11:34:08.180623 end: 4.1 power-off (duration 00:00:02) [common]
11144 11:34:08.181628 start: 4.2 read-feedback (timeout 00:07:40) [common]
11145 11:34:08.182440 Listened to connection for namespace 'common' for up to 1s
11146 11:34:09.182343 Finalising connection for namespace 'common'
11147 11:34:09.182910 Disconnecting from shell: Finalise
11148 11:34:09.183265 / #
11149 11:34:09.284272 end: 4.2 read-feedback (duration 00:00:01) [common]
11150 11:34:09.284871 end: 4 finalize (duration 00:00:03) [common]
11151 11:34:09.285403 Cleaning after the job
11152 11:34:09.285895 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/ramdisk
11153 11:34:09.290799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/kernel
11154 11:34:09.300907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/dtb
11155 11:34:09.301062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/nfsrootfs
11156 11:34:09.356919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864572/tftp-deploy-lyi6h__3/modules
11157 11:34:09.362322 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864572
11158 11:34:09.678719 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864572
11159 11:34:09.678887 Job finished correctly