Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:36:02.327424 lava-dispatcher, installed at version: 2024.05
2 11:36:02.327616 start: 0 validate
3 11:36:02.327744 Start time: 2024-07-17 11:36:02.327734+00:00 (UTC)
4 11:36:02.327866 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:36:02.328005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:36:02.857892 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:36:02.858100 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:36:03.115920 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:36:03.116090 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:36:03.374227 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:36:03.374359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:36:03.633858 validate duration: 1.31
14 11:36:03.634097 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:36:03.634195 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:36:03.634275 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:36:03.634427 Not decompressing ramdisk as can be used compressed.
18 11:36:03.634511 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 11:36:03.634572 saving as /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/ramdisk/rootfs.cpio.gz
20 11:36:03.634629 total size: 39026414 (37 MB)
21 11:36:03.635960 progress 0 % (0 MB)
22 11:36:03.645954 progress 5 % (1 MB)
23 11:36:03.655746 progress 10 % (3 MB)
24 11:36:03.665506 progress 15 % (5 MB)
25 11:36:03.675268 progress 20 % (7 MB)
26 11:36:03.684957 progress 25 % (9 MB)
27 11:36:03.694665 progress 30 % (11 MB)
28 11:36:03.704275 progress 35 % (13 MB)
29 11:36:03.713957 progress 40 % (14 MB)
30 11:36:03.723550 progress 45 % (16 MB)
31 11:36:03.733454 progress 50 % (18 MB)
32 11:36:03.743521 progress 55 % (20 MB)
33 11:36:03.753226 progress 60 % (22 MB)
34 11:36:03.763028 progress 65 % (24 MB)
35 11:36:03.772696 progress 70 % (26 MB)
36 11:36:03.782688 progress 75 % (27 MB)
37 11:36:03.792444 progress 80 % (29 MB)
38 11:36:03.802350 progress 85 % (31 MB)
39 11:36:03.811894 progress 90 % (33 MB)
40 11:36:03.821492 progress 95 % (35 MB)
41 11:36:03.830946 progress 100 % (37 MB)
42 11:36:03.831192 37 MB downloaded in 0.20 s (189.35 MB/s)
43 11:36:03.831337 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:36:03.831550 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:36:03.831627 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:36:03.831700 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:36:03.831828 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:36:03.831897 saving as /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/kernel/Image
50 11:36:03.831949 total size: 54813184 (52 MB)
51 11:36:03.832002 No compression specified
52 11:36:03.833057 progress 0 % (0 MB)
53 11:36:03.846714 progress 5 % (2 MB)
54 11:36:03.860559 progress 10 % (5 MB)
55 11:36:03.873989 progress 15 % (7 MB)
56 11:36:03.887649 progress 20 % (10 MB)
57 11:36:03.901527 progress 25 % (13 MB)
58 11:36:03.915148 progress 30 % (15 MB)
59 11:36:03.928793 progress 35 % (18 MB)
60 11:36:03.942546 progress 40 % (20 MB)
61 11:36:03.955954 progress 45 % (23 MB)
62 11:36:03.969734 progress 50 % (26 MB)
63 11:36:03.983434 progress 55 % (28 MB)
64 11:36:03.996908 progress 60 % (31 MB)
65 11:36:04.010602 progress 65 % (34 MB)
66 11:36:04.024263 progress 70 % (36 MB)
67 11:36:04.038015 progress 75 % (39 MB)
68 11:36:04.051649 progress 80 % (41 MB)
69 11:36:04.065060 progress 85 % (44 MB)
70 11:36:04.078681 progress 90 % (47 MB)
71 11:36:04.092337 progress 95 % (49 MB)
72 11:36:04.105652 progress 100 % (52 MB)
73 11:36:04.105863 52 MB downloaded in 0.27 s (190.84 MB/s)
74 11:36:04.106007 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:36:04.106210 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:36:04.106287 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:36:04.106360 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:36:04.106484 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:36:04.106548 saving as /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/dtb/mt8192-asurada-spherion-r0.dtb
81 11:36:04.106599 total size: 47258 (0 MB)
82 11:36:04.106651 No compression specified
83 11:36:04.107695 progress 69 % (0 MB)
84 11:36:04.107947 progress 100 % (0 MB)
85 11:36:04.108092 0 MB downloaded in 0.00 s (30.25 MB/s)
86 11:36:04.108201 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:36:04.108394 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:36:04.108467 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:36:04.108539 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:36:04.108639 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:36:04.108699 saving as /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/modules/modules.tar
93 11:36:04.108751 total size: 8610184 (8 MB)
94 11:36:04.108804 Using unxz to decompress xz
95 11:36:04.110104 progress 0 % (0 MB)
96 11:36:04.130680 progress 5 % (0 MB)
97 11:36:04.155502 progress 10 % (0 MB)
98 11:36:04.179528 progress 15 % (1 MB)
99 11:36:04.203853 progress 20 % (1 MB)
100 11:36:04.227452 progress 25 % (2 MB)
101 11:36:04.250995 progress 30 % (2 MB)
102 11:36:04.273501 progress 35 % (2 MB)
103 11:36:04.299568 progress 40 % (3 MB)
104 11:36:04.324090 progress 45 % (3 MB)
105 11:36:04.348322 progress 50 % (4 MB)
106 11:36:04.373120 progress 55 % (4 MB)
107 11:36:04.397396 progress 60 % (4 MB)
108 11:36:04.420630 progress 65 % (5 MB)
109 11:36:04.446529 progress 70 % (5 MB)
110 11:36:04.473587 progress 75 % (6 MB)
111 11:36:04.501882 progress 80 % (6 MB)
112 11:36:04.526082 progress 85 % (7 MB)
113 11:36:04.549687 progress 90 % (7 MB)
114 11:36:04.573279 progress 95 % (7 MB)
115 11:36:04.596229 progress 100 % (8 MB)
116 11:36:04.601721 8 MB downloaded in 0.49 s (16.66 MB/s)
117 11:36:04.601869 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:36:04.602075 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:36:04.602152 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:36:04.602226 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:36:04.602300 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:36:04.602370 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:36:04.602533 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1
125 11:36:04.602648 makedir: /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin
126 11:36:04.602751 makedir: /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/tests
127 11:36:04.602837 makedir: /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/results
128 11:36:04.602922 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-add-keys
129 11:36:04.603051 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-add-sources
130 11:36:04.603168 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-background-process-start
131 11:36:04.603281 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-background-process-stop
132 11:36:04.603405 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-common-functions
133 11:36:04.603519 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-echo-ipv4
134 11:36:04.603631 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-install-packages
135 11:36:04.603741 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-installed-packages
136 11:36:04.603871 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-os-build
137 11:36:04.603995 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-probe-channel
138 11:36:04.604105 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-probe-ip
139 11:36:04.604213 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-target-ip
140 11:36:04.604320 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-target-mac
141 11:36:04.604429 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-target-storage
142 11:36:04.604540 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-case
143 11:36:04.604650 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-event
144 11:36:04.604758 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-feedback
145 11:36:04.604865 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-raise
146 11:36:04.604972 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-reference
147 11:36:04.605081 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-runner
148 11:36:04.605230 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-set
149 11:36:04.605341 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-test-shell
150 11:36:04.605453 Updating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-install-packages (oe)
151 11:36:04.605588 Updating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/bin/lava-installed-packages (oe)
152 11:36:04.605714 Creating /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/environment
153 11:36:04.605831 LAVA metadata
154 11:36:04.605914 - LAVA_JOB_ID=14864646
155 11:36:04.605972 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:36:04.606061 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:36:04.606119 skipped lava-vland-overlay
158 11:36:04.606184 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:36:04.606252 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:36:04.606303 skipped lava-multinode-overlay
161 11:36:04.606365 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:36:04.606432 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:36:04.606494 Loading test definitions
164 11:36:04.606566 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:36:04.606625 Using /lava-14864646 at stage 0
166 11:36:04.606906 uuid=14864646_1.5.2.3.1 testdef=None
167 11:36:04.606982 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:36:04.607055 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:36:04.607476 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:36:04.607666 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:36:04.608203 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:36:04.608403 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:36:04.608986 runner path: /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/0/tests/0_cros-ec test_uuid 14864646_1.5.2.3.1
176 11:36:04.609192 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:36:04.609380 Creating lava-test-runner.conf files
179 11:36:04.609434 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864646/lava-overlay-ms_06pv1/lava-14864646/0 for stage 0
180 11:36:04.609512 - 0_cros-ec
181 11:36:04.609600 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:36:04.609672 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:36:04.615612 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:36:04.615703 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:36:04.615778 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:36:04.615869 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:36:04.616021 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:36:05.805951 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:36:05.806082 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:36:05.806155 extracting modules file /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864646/extract-overlay-ramdisk-t6ri4qxc/ramdisk
191 11:36:06.042777 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:36:06.042906 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:36:06.042982 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864646/compress-overlay-s2920e_x/overlay-1.5.2.4.tar.gz to ramdisk
194 11:36:06.043051 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864646/compress-overlay-s2920e_x/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864646/extract-overlay-ramdisk-t6ri4qxc/ramdisk
195 11:36:06.049404 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:36:06.049501 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:36:06.049582 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:36:06.049658 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:36:06.049740 Building ramdisk /var/lib/lava/dispatcher/tmp/14864646/extract-overlay-ramdisk-t6ri4qxc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864646/extract-overlay-ramdisk-t6ri4qxc/ramdisk
200 11:36:07.251526 >> 335502 blocks
201 11:36:12.937104 rename /var/lib/lava/dispatcher/tmp/14864646/extract-overlay-ramdisk-t6ri4qxc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/ramdisk/ramdisk.cpio.gz
202 11:36:12.937306 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:36:12.937396 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 11:36:12.937472 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 11:36:12.937544 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/kernel/Image']
206 11:36:26.364538 Returned 0 in 13 seconds
207 11:36:26.364696 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/kernel/image.itb
208 11:36:27.488571 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:36:27.488685 output: Created: Wed Jul 17 12:36:27 2024
210 11:36:27.488746 output: Image 0 (kernel-1)
211 11:36:27.488813 output: Description:
212 11:36:27.488868 output: Created: Wed Jul 17 12:36:27 2024
213 11:36:27.488919 output: Type: Kernel Image
214 11:36:27.488967 output: Compression: lzma compressed
215 11:36:27.489018 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:36:27.489098 output: Architecture: AArch64
217 11:36:27.489215 output: OS: Linux
218 11:36:27.489295 output: Load Address: 0x00000000
219 11:36:27.489352 output: Entry Point: 0x00000000
220 11:36:27.489400 output: Hash algo: crc32
221 11:36:27.489446 output: Hash value: 83448d17
222 11:36:27.489493 output: Image 1 (fdt-1)
223 11:36:27.489544 output: Description: mt8192-asurada-spherion-r0
224 11:36:27.489599 output: Created: Wed Jul 17 12:36:27 2024
225 11:36:27.489646 output: Type: Flat Device Tree
226 11:36:27.489692 output: Compression: uncompressed
227 11:36:27.489738 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:36:27.489785 output: Architecture: AArch64
229 11:36:27.489844 output: Hash algo: crc32
230 11:36:27.489891 output: Hash value: 0f8e4d2e
231 11:36:27.489939 output: Image 2 (ramdisk-1)
232 11:36:27.489985 output: Description: unavailable
233 11:36:27.490031 output: Created: Wed Jul 17 12:36:27 2024
234 11:36:27.490091 output: Type: RAMDisk Image
235 11:36:27.490137 output: Compression: uncompressed
236 11:36:27.490184 output: Data Size: 52130564 Bytes = 50908.75 KiB = 49.72 MiB
237 11:36:27.490230 output: Architecture: AArch64
238 11:36:27.490276 output: OS: Linux
239 11:36:27.490338 output: Load Address: unavailable
240 11:36:27.490385 output: Entry Point: unavailable
241 11:36:27.490430 output: Hash algo: crc32
242 11:36:27.490475 output: Hash value: c5f27123
243 11:36:27.490521 output: Default Configuration: 'conf-1'
244 11:36:27.490583 output: Configuration 0 (conf-1)
245 11:36:27.490631 output: Description: mt8192-asurada-spherion-r0
246 11:36:27.490678 output: Kernel: kernel-1
247 11:36:27.490724 output: Init Ramdisk: ramdisk-1
248 11:36:27.490770 output: FDT: fdt-1
249 11:36:27.490832 output: Loadables: kernel-1
250 11:36:27.490880 output:
251 11:36:27.490977 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:36:27.491057 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:36:27.491159 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 11:36:27.491257 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 11:36:27.491345 No LXC device requested
256 11:36:27.491441 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:36:27.491540 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 11:36:27.491639 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:36:27.491717 Checking files for TFTP limit of 4294967296 bytes.
260 11:36:27.492206 end: 1 tftp-deploy (duration 00:00:24) [common]
261 11:36:27.492315 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:36:27.492420 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:36:27.492547 substitutions:
264 11:36:27.492629 - {DTB}: 14864646/tftp-deploy-5majoj1q/dtb/mt8192-asurada-spherion-r0.dtb
265 11:36:27.492709 - {INITRD}: 14864646/tftp-deploy-5majoj1q/ramdisk/ramdisk.cpio.gz
266 11:36:27.492786 - {KERNEL}: 14864646/tftp-deploy-5majoj1q/kernel/Image
267 11:36:27.492862 - {LAVA_MAC}: None
268 11:36:27.492938 - {PRESEED_CONFIG}: None
269 11:36:27.493013 - {PRESEED_LOCAL}: None
270 11:36:27.493088 - {RAMDISK}: 14864646/tftp-deploy-5majoj1q/ramdisk/ramdisk.cpio.gz
271 11:36:27.493211 - {ROOT_PART}: None
272 11:36:27.493287 - {ROOT}: None
273 11:36:27.493362 - {SERVER_IP}: 192.168.201.1
274 11:36:27.493437 - {TEE}: None
275 11:36:27.493511 Parsed boot commands:
276 11:36:27.493590 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:36:27.493732 Parsed boot commands: tftpboot 192.168.201.1 14864646/tftp-deploy-5majoj1q/kernel/image.itb 14864646/tftp-deploy-5majoj1q/kernel/cmdline
278 11:36:27.493808 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:36:27.493878 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:36:27.493949 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:36:27.494031 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:36:27.494085 Not connected, no need to disconnect.
283 11:36:27.494148 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:36:27.494221 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:36:27.494279 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 11:36:27.497229 Setting prompt string to ['lava-test: # ']
287 11:36:27.497531 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:36:27.497619 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:36:27.497717 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:36:27.497798 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:36:27.498037 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=reboot']
292 11:36:36.614348 >> Command sent successfully.
293 11:36:36.617434 Returned 0 in 9 seconds
294 11:36:36.617570 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:36:36.617770 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:36:36.617855 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:36:36.617927 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:36:36.617983 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:36:36.618048 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:36:36.618384 [Enter `^Ec?' for help]
302 11:36:38.229730
303 11:36:38.229843
304 11:36:38.229906 F0: 102B 0000
305 11:36:38.229964
306 11:36:38.230017 F3: 1001 0000 [0200]
307 11:36:38.233053
308 11:36:38.233162 F3: 1001 0000
309 11:36:38.233232
310 11:36:38.233285 F7: 102D 0000
311 11:36:38.233336
312 11:36:38.233385 F1: 0000 0000
313 11:36:38.237077
314 11:36:38.237193 V0: 0000 0000 [0001]
315 11:36:38.237250
316 11:36:38.237300 00: 0007 8000
317 11:36:38.237350
318 11:36:38.240488 01: 0000 0000
319 11:36:38.240575
320 11:36:38.240650 BP: 0C00 0209 [0000]
321 11:36:38.240725
322 11:36:38.244876 G0: 1182 0000
323 11:36:38.244960
324 11:36:38.245035 EC: 0000 0021 [4000]
325 11:36:38.245110
326 11:36:38.248327 S7: 0000 0000 [0000]
327 11:36:38.248401
328 11:36:38.248452 CC: 0000 0000 [0001]
329 11:36:38.248500
330 11:36:38.251561 T0: 0000 0040 [010F]
331 11:36:38.251650
332 11:36:38.251730 Jump to BL
333 11:36:38.251805
334 11:36:38.276482
335 11:36:38.276559
336 11:36:38.283469 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:36:38.286785 ARM64: Exception handlers installed.
338 11:36:38.289831 ARM64: Testing exception
339 11:36:38.293869 ARM64: Done test exception
340 11:36:38.299735 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:36:38.309680 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:36:38.316417 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:36:38.326990 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:36:38.333732 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:36:38.344265 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:36:38.353884 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:36:38.360810 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:36:38.378922 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:36:38.382333 WDT: Last reset was cold boot
350 11:36:38.386118 SPI1(PAD0) initialized at 2873684 Hz
351 11:36:38.388849 SPI5(PAD0) initialized at 992727 Hz
352 11:36:38.392237 VBOOT: Loading verstage.
353 11:36:38.399108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:36:38.402329 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:36:38.406018 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:36:38.408814 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:36:38.416610 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:36:38.423131 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:36:38.433864 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:36:38.433939
361 11:36:38.434001
362 11:36:38.443857 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:36:38.447418 ARM64: Exception handlers installed.
364 11:36:38.450496 ARM64: Testing exception
365 11:36:38.450589 ARM64: Done test exception
366 11:36:38.457221 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:36:38.461256 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:36:38.475022 Probing TPM: . done!
369 11:36:38.475117 TPM ready after 0 ms
370 11:36:38.481846 Connected to device vid:did:rid of 1ae0:0028:00
371 11:36:38.491734 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
372 11:36:38.527826 Initialized TPM device CR50 revision 0
373 11:36:38.539063 tlcl_send_startup: Startup return code is 0
374 11:36:38.539162 TPM: setup succeeded
375 11:36:38.551081 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:36:38.559708 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:36:38.569809 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:36:38.578659 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:36:38.582002 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:36:38.585441 in-header: 03 07 00 00 08 00 00 00
381 11:36:38.588517 in-data: aa e4 47 04 13 02 00 00
382 11:36:38.592205 Chrome EC: UHEPI supported
383 11:36:38.598518 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:36:38.602230 in-header: 03 a9 00 00 08 00 00 00
385 11:36:38.605906 in-data: 84 60 60 08 00 00 00 00
386 11:36:38.605967 Phase 1
387 11:36:38.608593 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:36:38.615345 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:36:38.621584 VB2:vb2_check_recovery() Recovery was requested manually
390 11:36:38.625197 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:36:38.628299 Recovery requested (1009000e)
392 11:36:38.636708 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:36:38.642022 tlcl_extend: response is 0
394 11:36:38.650049 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:36:38.655379 tlcl_extend: response is 0
396 11:36:38.662098 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:36:38.682908 read SPI 0x210d4 0x2173b: 15139 us, 9050 KB/s, 72.400 Mbps
398 11:36:38.689790 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:36:38.689863
400 11:36:38.689924
401 11:36:38.699527 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:36:38.703080 ARM64: Exception handlers installed.
403 11:36:38.706968 ARM64: Testing exception
404 11:36:38.707035 ARM64: Done test exception
405 11:36:38.728556 pmic_efuse_setting: Set efuses in 11 msecs
406 11:36:38.732045 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:36:38.739369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:36:38.742770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:36:38.745998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:36:38.752807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:36:38.755802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:36:38.762565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:36:38.765597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:36:38.772136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:36:38.775538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:36:38.782414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:36:38.785802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:36:38.788952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:36:38.795641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:36:38.802179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:36:38.805989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:36:38.811997 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:36:38.818601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:36:38.822060 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:36:38.828805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:36:38.835568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:36:38.838507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:36:38.845516 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:36:38.852065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:36:38.855494 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:36:38.862313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:36:38.868573 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:36:38.872491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:36:38.878736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:36:38.881759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:36:38.888474 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:36:38.891754 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:36:38.898369 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:36:38.901593 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:36:38.908286 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:36:38.911795 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:36:38.918220 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:36:38.921792 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:36:38.928505 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:36:38.932395 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:36:38.935830 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:36:38.939118 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:36:38.945629 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:36:38.949054 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:36:38.952236 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:36:38.959043 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:36:38.962126 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:36:38.965675 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:36:38.972225 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:36:38.975405 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:36:38.978816 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:36:38.982454 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:36:38.992364 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:36:38.998584 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:36:39.005260 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:36:39.011714 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:36:39.022006 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:36:39.025098 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:36:39.028723 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:36:39.035460 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:36:39.041937 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2
467 11:36:39.048840 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:36:39.051641 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:36:39.054910 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:36:39.065780 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 11:36:39.075173 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 11:36:39.084607 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 11:36:39.093837 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 11:36:39.103646 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 11:36:39.113203 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 11:36:39.122977 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 11:36:39.125825 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:36:39.133118 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:36:39.136330 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:36:39.140211 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:36:39.146382 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:36:39.149991 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:36:39.153303 ADC[4]: Raw value=903694 ID=7
484 11:36:39.153378 ADC[3]: Raw value=213916 ID=1
485 11:36:39.156289 RAM Code: 0x71
486 11:36:39.160151 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:36:39.166494 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:36:39.173324 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:36:39.179812 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:36:39.183123 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:36:39.186255 in-header: 03 07 00 00 08 00 00 00
492 11:36:39.189545 in-data: aa e4 47 04 13 02 00 00
493 11:36:39.193293 Chrome EC: UHEPI supported
494 11:36:39.199387 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:36:39.203045 in-header: 03 a9 00 00 08 00 00 00
496 11:36:39.205755 in-data: 84 60 60 08 00 00 00 00
497 11:36:39.209740 MRC: failed to locate region type 0.
498 11:36:39.216025 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:36:39.219210 DRAM-K: Running full calibration
500 11:36:39.225980 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:36:39.226056 header.status = 0x0
502 11:36:39.229033 header.version = 0x6 (expected: 0x6)
503 11:36:39.232503 header.size = 0xd00 (expected: 0xd00)
504 11:36:39.235507 header.flags = 0x0
505 11:36:39.242253 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:36:39.259187 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:36:39.265680 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:36:39.269413 dram_init: ddr_geometry: 2
509 11:36:39.272297 [EMI] MDL number = 2
510 11:36:39.272372 [EMI] Get MDL freq = 0
511 11:36:39.275785 dram_init: ddr_type: 0
512 11:36:39.275860 is_discrete_lpddr4: 1
513 11:36:39.279484 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:36:39.279560
515 11:36:39.279622
516 11:36:39.282811 [Bian_co] ETT version 0.0.0.1
517 11:36:39.289332 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:36:39.289408
519 11:36:39.292762 dramc_set_vcore_voltage set vcore to 650000
520 11:36:39.292838 Read voltage for 800, 4
521 11:36:39.295727 Vio18 = 0
522 11:36:39.295802 Vcore = 650000
523 11:36:39.295860 Vdram = 0
524 11:36:39.299314 Vddq = 0
525 11:36:39.299411 Vmddr = 0
526 11:36:39.302599 dram_init: config_dvfs: 1
527 11:36:39.305900 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:36:39.312856 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:36:39.315903 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:36:39.319224 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:36:39.322339 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:36:39.326075 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:36:39.328957 MEM_TYPE=3, freq_sel=18
534 11:36:39.332733 sv_algorithm_assistance_LP4_1600
535 11:36:39.335837 ============ PULL DRAM RESETB DOWN ============
536 11:36:39.342433 ========== PULL DRAM RESETB DOWN end =========
537 11:36:39.345530 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:36:39.349059 ===================================
539 11:36:39.352412 LPDDR4 DRAM CONFIGURATION
540 11:36:39.355975 ===================================
541 11:36:39.356054 EX_ROW_EN[0] = 0x0
542 11:36:39.358799 EX_ROW_EN[1] = 0x0
543 11:36:39.358876 LP4Y_EN = 0x0
544 11:36:39.362426 WORK_FSP = 0x0
545 11:36:39.362501 WL = 0x2
546 11:36:39.365931 RL = 0x2
547 11:36:39.366028 BL = 0x2
548 11:36:39.369083 RPST = 0x0
549 11:36:39.369214 RD_PRE = 0x0
550 11:36:39.372516 WR_PRE = 0x1
551 11:36:39.372626 WR_PST = 0x0
552 11:36:39.376127 DBI_WR = 0x0
553 11:36:39.376225 DBI_RD = 0x0
554 11:36:39.380214 OTF = 0x1
555 11:36:39.383899 ===================================
556 11:36:39.383975 ===================================
557 11:36:39.388051 ANA top config
558 11:36:39.391366 ===================================
559 11:36:39.391441 DLL_ASYNC_EN = 0
560 11:36:39.395403 ALL_SLAVE_EN = 1
561 11:36:39.398634 NEW_RANK_MODE = 1
562 11:36:39.402078 DLL_IDLE_MODE = 1
563 11:36:39.402154 LP45_APHY_COMB_EN = 1
564 11:36:39.405678 TX_ODT_DIS = 1
565 11:36:39.409681 NEW_8X_MODE = 1
566 11:36:39.412660 ===================================
567 11:36:39.415662 ===================================
568 11:36:39.419243 data_rate = 1600
569 11:36:39.419318 CKR = 1
570 11:36:39.423074 DQ_P2S_RATIO = 8
571 11:36:39.426265 ===================================
572 11:36:39.429472 CA_P2S_RATIO = 8
573 11:36:39.432244 DQ_CA_OPEN = 0
574 11:36:39.435904 DQ_SEMI_OPEN = 0
575 11:36:39.435979 CA_SEMI_OPEN = 0
576 11:36:39.439282 CA_FULL_RATE = 0
577 11:36:39.442537 DQ_CKDIV4_EN = 1
578 11:36:39.445989 CA_CKDIV4_EN = 1
579 11:36:39.449113 CA_PREDIV_EN = 0
580 11:36:39.452409 PH8_DLY = 0
581 11:36:39.452484 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:36:39.456029 DQ_AAMCK_DIV = 4
583 11:36:39.459820 CA_AAMCK_DIV = 4
584 11:36:39.462483 CA_ADMCK_DIV = 4
585 11:36:39.466302 DQ_TRACK_CA_EN = 0
586 11:36:39.469588 CA_PICK = 800
587 11:36:39.469663 CA_MCKIO = 800
588 11:36:39.472685 MCKIO_SEMI = 0
589 11:36:39.475788 PLL_FREQ = 3068
590 11:36:39.479460 DQ_UI_PI_RATIO = 32
591 11:36:39.482156 CA_UI_PI_RATIO = 0
592 11:36:39.485901 ===================================
593 11:36:39.489177 ===================================
594 11:36:39.492328 memory_type:LPDDR4
595 11:36:39.492403 GP_NUM : 10
596 11:36:39.495599 SRAM_EN : 1
597 11:36:39.498756 MD32_EN : 0
598 11:36:39.502125 ===================================
599 11:36:39.502217 [ANA_INIT] >>>>>>>>>>>>>>
600 11:36:39.505669 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:36:39.508978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:36:39.512533 ===================================
603 11:36:39.515285 data_rate = 1600,PCW = 0X7600
604 11:36:39.518561 ===================================
605 11:36:39.521987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:36:39.528781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:36:39.532202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:36:39.538810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:36:39.541942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:36:39.545571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:36:39.545647 [ANA_INIT] flow start
612 11:36:39.548620 [ANA_INIT] PLL >>>>>>>>
613 11:36:39.552115 [ANA_INIT] PLL <<<<<<<<
614 11:36:39.555349 [ANA_INIT] MIDPI >>>>>>>>
615 11:36:39.555425 [ANA_INIT] MIDPI <<<<<<<<
616 11:36:39.558777 [ANA_INIT] DLL >>>>>>>>
617 11:36:39.561591 [ANA_INIT] flow end
618 11:36:39.564967 ============ LP4 DIFF to SE enter ============
619 11:36:39.568219 ============ LP4 DIFF to SE exit ============
620 11:36:39.571715 [ANA_INIT] <<<<<<<<<<<<<
621 11:36:39.574996 [Flow] Enable top DCM control >>>>>
622 11:36:39.578303 [Flow] Enable top DCM control <<<<<
623 11:36:39.582122 Enable DLL master slave shuffle
624 11:36:39.585172 ==============================================================
625 11:36:39.588319 Gating Mode config
626 11:36:39.591296 ==============================================================
627 11:36:39.595113 Config description:
628 11:36:39.604869 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:36:39.611399 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:36:39.615243 SELPH_MODE 0: By rank 1: By Phase
631 11:36:39.621846 ==============================================================
632 11:36:39.624966 GAT_TRACK_EN = 1
633 11:36:39.628023 RX_GATING_MODE = 2
634 11:36:39.631726 RX_GATING_TRACK_MODE = 2
635 11:36:39.635030 SELPH_MODE = 1
636 11:36:39.638152 PICG_EARLY_EN = 1
637 11:36:39.638221 VALID_LAT_VALUE = 1
638 11:36:39.644822 ==============================================================
639 11:36:39.647969 Enter into Gating configuration >>>>
640 11:36:39.651356 Exit from Gating configuration <<<<
641 11:36:39.654845 Enter into DVFS_PRE_config >>>>>
642 11:36:39.664366 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:36:39.668154 Exit from DVFS_PRE_config <<<<<
644 11:36:39.671220 Enter into PICG configuration >>>>
645 11:36:39.674424 Exit from PICG configuration <<<<
646 11:36:39.677643 [RX_INPUT] configuration >>>>>
647 11:36:39.680827 [RX_INPUT] configuration <<<<<
648 11:36:39.687803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:36:39.691106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:36:39.697983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:36:39.704478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:36:39.711003 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:36:39.717457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:36:39.720858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:36:39.724425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:36:39.727712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:36:39.734181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:36:39.737484 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:36:39.741193 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:36:39.744191 ===================================
661 11:36:39.747303 LPDDR4 DRAM CONFIGURATION
662 11:36:39.750718 ===================================
663 11:36:39.750794 EX_ROW_EN[0] = 0x0
664 11:36:39.754033 EX_ROW_EN[1] = 0x0
665 11:36:39.757913 LP4Y_EN = 0x0
666 11:36:39.757988 WORK_FSP = 0x0
667 11:36:39.760678 WL = 0x2
668 11:36:39.760752 RL = 0x2
669 11:36:39.763829 BL = 0x2
670 11:36:39.763931 RPST = 0x0
671 11:36:39.767651 RD_PRE = 0x0
672 11:36:39.767753 WR_PRE = 0x1
673 11:36:39.770679 WR_PST = 0x0
674 11:36:39.770770 DBI_WR = 0x0
675 11:36:39.774439 DBI_RD = 0x0
676 11:36:39.774529 OTF = 0x1
677 11:36:39.777422 ===================================
678 11:36:39.780886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:36:39.787110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:36:39.790941 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:36:39.794072 ===================================
682 11:36:39.797458 LPDDR4 DRAM CONFIGURATION
683 11:36:39.800593 ===================================
684 11:36:39.800667 EX_ROW_EN[0] = 0x10
685 11:36:39.803899 EX_ROW_EN[1] = 0x0
686 11:36:39.803974 LP4Y_EN = 0x0
687 11:36:39.807358 WORK_FSP = 0x0
688 11:36:39.810687 WL = 0x2
689 11:36:39.810761 RL = 0x2
690 11:36:39.813934 BL = 0x2
691 11:36:39.814008 RPST = 0x0
692 11:36:39.817624 RD_PRE = 0x0
693 11:36:39.817698 WR_PRE = 0x1
694 11:36:39.820413 WR_PST = 0x0
695 11:36:39.820488 DBI_WR = 0x0
696 11:36:39.823650 DBI_RD = 0x0
697 11:36:39.823724 OTF = 0x1
698 11:36:39.827109 ===================================
699 11:36:39.833758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:36:39.837562 nWR fixed to 40
701 11:36:39.841088 [ModeRegInit_LP4] CH0 RK0
702 11:36:39.841205 [ModeRegInit_LP4] CH0 RK1
703 11:36:39.844066 [ModeRegInit_LP4] CH1 RK0
704 11:36:39.847457 [ModeRegInit_LP4] CH1 RK1
705 11:36:39.847531 match AC timing 13
706 11:36:39.854359 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:36:39.857526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:36:39.861145 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:36:39.867772 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:36:39.871180 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:36:39.874128 [EMI DOE] emi_dcm 0
712 11:36:39.877175 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:36:39.877250 ==
714 11:36:39.880671 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:36:39.883957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:36:39.884032 ==
717 11:36:39.890845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:36:39.897771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:36:39.905527 [CA 0] Center 37 (7~68) winsize 62
720 11:36:39.908946 [CA 1] Center 37 (6~68) winsize 63
721 11:36:39.911754 [CA 2] Center 34 (4~65) winsize 62
722 11:36:39.915481 [CA 3] Center 35 (4~66) winsize 63
723 11:36:39.918835 [CA 4] Center 34 (3~65) winsize 63
724 11:36:39.921847 [CA 5] Center 33 (3~64) winsize 62
725 11:36:39.921911
726 11:36:39.924930 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:36:39.924992
728 11:36:39.928681 [CATrainingPosCal] consider 1 rank data
729 11:36:39.932626 u2DelayCellTimex100 = 270/100 ps
730 11:36:39.935731 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:36:39.938760 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:36:39.942964 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:36:39.945451 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 11:36:39.952239 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:36:39.956042 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:36:39.956116
737 11:36:39.959960 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:36:39.960035
739 11:36:39.963283 [CBTSetCACLKResult] CA Dly = 33
740 11:36:39.963358 CS Dly: 5 (0~36)
741 11:36:39.963417 ==
742 11:36:39.966063 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:36:39.969557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:36:39.969635 ==
745 11:36:39.976133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:36:39.983101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:36:39.991266 [CA 0] Center 38 (7~69) winsize 63
748 11:36:39.994741 [CA 1] Center 37 (7~68) winsize 62
749 11:36:39.997968 [CA 2] Center 35 (4~66) winsize 63
750 11:36:40.001292 [CA 3] Center 35 (4~66) winsize 63
751 11:36:40.004732 [CA 4] Center 34 (3~65) winsize 63
752 11:36:40.008017 [CA 5] Center 33 (3~64) winsize 62
753 11:36:40.008091
754 11:36:40.011243 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:36:40.011318
756 11:36:40.014738 [CATrainingPosCal] consider 2 rank data
757 11:36:40.018493 u2DelayCellTimex100 = 270/100 ps
758 11:36:40.021395 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:36:40.024986 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:36:40.031393 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:36:40.034707 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 11:36:40.037881 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:36:40.041562 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:36:40.041637
765 11:36:40.044957 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:36:40.045032
767 11:36:40.048237 [CBTSetCACLKResult] CA Dly = 33
768 11:36:40.048312 CS Dly: 6 (0~38)
769 11:36:40.048386
770 11:36:40.051488 ----->DramcWriteLeveling(PI) begin...
771 11:36:40.054837 ==
772 11:36:40.057911 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:36:40.061077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:36:40.061194 ==
775 11:36:40.064455 Write leveling (Byte 0): 33 => 33
776 11:36:40.067792 Write leveling (Byte 1): 26 => 26
777 11:36:40.071001 DramcWriteLeveling(PI) end<-----
778 11:36:40.071075
779 11:36:40.071143 ==
780 11:36:40.074452 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:36:40.077855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:36:40.077930 ==
783 11:36:40.081275 [Gating] SW mode calibration
784 11:36:40.087719 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:36:40.094042 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:36:40.097675 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 11:36:40.100606 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:36:40.107660 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:36:40.110721 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:36:40.113969 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:36:40.120433 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:36:40.124032 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:36:40.127605 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:36:40.134520 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:36:40.137517 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:36:40.140596 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:36:40.147501 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:36:40.150545 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:36:40.154020 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:36:40.157523 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:36:40.164228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:36:40.167574 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:36:40.170490 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:36:40.177070 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 11:36:40.180271 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:36:40.183893 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:36:40.190731 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:36:40.193525 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:36:40.197417 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:36:40.204073 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:36:40.206891 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:36:40.210483 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
813 11:36:40.217008 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 11:36:40.219911 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:36:40.223435 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:36:40.230125 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:36:40.234044 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:36:40.236730 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:36:40.243189 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 11:36:40.246354 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (1 1)
821 11:36:40.249888 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
822 11:36:40.256131 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:36:40.259777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:36:40.263455 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:36:40.269713 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:36:40.273040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:36:40.276241 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 11:36:40.282936 0 11 8 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
829 11:36:40.286457 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
830 11:36:40.289390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:36:40.296337 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:36:40.299427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:36:40.303133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:36:40.309402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:36:40.312850 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:36:40.316234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 11:36:40.322660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:36:40.325831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:36:40.329451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:36:40.336165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:36:40.339265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:36:40.343109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:36:40.349321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:36:40.352745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:36:40.356361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:36:40.362325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:36:40.366279 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:36:40.369339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:36:40.375735 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:36:40.379318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:36:40.382413 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:36:40.388901 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 11:36:40.392121 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 11:36:40.395528 Total UI for P1: 0, mck2ui 16
855 11:36:40.398856 best dqsien dly found for B0: ( 0, 14, 8)
856 11:36:40.402182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 11:36:40.405396 Total UI for P1: 0, mck2ui 16
858 11:36:40.408771 best dqsien dly found for B1: ( 0, 14, 12)
859 11:36:40.412136 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 11:36:40.415241 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 11:36:40.415306
862 11:36:40.419237 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:36:40.422267 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 11:36:40.425702 [Gating] SW calibration Done
865 11:36:40.425776 ==
866 11:36:40.429224 Dram Type= 6, Freq= 0, CH_0, rank 0
867 11:36:40.435396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 11:36:40.435468 ==
869 11:36:40.435524 RX Vref Scan: 0
870 11:36:40.435585
871 11:36:40.438917 RX Vref 0 -> 0, step: 1
872 11:36:40.438987
873 11:36:40.442430 RX Delay -130 -> 252, step: 16
874 11:36:40.445710 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 11:36:40.448887 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 11:36:40.452502 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 11:36:40.455520 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 11:36:40.462289 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 11:36:40.465624 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 11:36:40.469089 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 11:36:40.472930 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 11:36:40.475538 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 11:36:40.482071 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
884 11:36:40.485705 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 11:36:40.489108 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 11:36:40.492392 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
887 11:36:40.498933 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 11:36:40.501684 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 11:36:40.505169 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 11:36:40.505249 ==
891 11:36:40.508418 Dram Type= 6, Freq= 0, CH_0, rank 0
892 11:36:40.511794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 11:36:40.511869 ==
894 11:36:40.515187 DQS Delay:
895 11:36:40.515261 DQS0 = 0, DQS1 = 0
896 11:36:40.518416 DQM Delay:
897 11:36:40.518490 DQM0 = 88, DQM1 = 75
898 11:36:40.518546 DQ Delay:
899 11:36:40.522108 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
900 11:36:40.525205 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
901 11:36:40.528477 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
902 11:36:40.532099 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
903 11:36:40.532175
904 11:36:40.532232
905 11:36:40.535016 ==
906 11:36:40.538506 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:36:40.541719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:36:40.541786 ==
909 11:36:40.541847
910 11:36:40.541899
911 11:36:40.544774 TX Vref Scan disable
912 11:36:40.544835 == TX Byte 0 ==
913 11:36:40.551477 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 11:36:40.554784 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 11:36:40.554855 == TX Byte 1 ==
916 11:36:40.561115 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
917 11:36:40.564529 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
918 11:36:40.564599 ==
919 11:36:40.568011 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:36:40.571415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:36:40.571481 ==
922 11:36:40.585683 TX Vref=22, minBit 1, minWin=27, winSum=438
923 11:36:40.588863 TX Vref=24, minBit 4, minWin=26, winSum=444
924 11:36:40.592451 TX Vref=26, minBit 1, minWin=27, winSum=447
925 11:36:40.595885 TX Vref=28, minBit 1, minWin=27, winSum=450
926 11:36:40.599414 TX Vref=30, minBit 0, minWin=28, winSum=452
927 11:36:40.605580 TX Vref=32, minBit 2, minWin=27, winSum=449
928 11:36:40.608765 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
929 11:36:40.608831
930 11:36:40.612272 Final TX Range 1 Vref 30
931 11:36:40.612335
932 11:36:40.612386 ==
933 11:36:40.615417 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:36:40.619166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:36:40.619232 ==
936 11:36:40.622162
937 11:36:40.622231
938 11:36:40.622284 TX Vref Scan disable
939 11:36:40.625878 == TX Byte 0 ==
940 11:36:40.629324 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 11:36:40.636069 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 11:36:40.636149 == TX Byte 1 ==
943 11:36:40.638818 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
944 11:36:40.645727 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
945 11:36:40.645800
946 11:36:40.645862 [DATLAT]
947 11:36:40.645916 Freq=800, CH0 RK0
948 11:36:40.645970
949 11:36:40.649116 DATLAT Default: 0xa
950 11:36:40.649218 0, 0xFFFF, sum = 0
951 11:36:40.652699 1, 0xFFFF, sum = 0
952 11:36:40.652762 2, 0xFFFF, sum = 0
953 11:36:40.655854 3, 0xFFFF, sum = 0
954 11:36:40.659062 4, 0xFFFF, sum = 0
955 11:36:40.659134 5, 0xFFFF, sum = 0
956 11:36:40.662249 6, 0xFFFF, sum = 0
957 11:36:40.662320 7, 0xFFFF, sum = 0
958 11:36:40.665876 8, 0xFFFF, sum = 0
959 11:36:40.665945 9, 0x0, sum = 1
960 11:36:40.666001 10, 0x0, sum = 2
961 11:36:40.669006 11, 0x0, sum = 3
962 11:36:40.669115 12, 0x0, sum = 4
963 11:36:40.672315 best_step = 10
964 11:36:40.672386
965 11:36:40.672441 ==
966 11:36:40.675497 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:36:40.679357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:36:40.679425 ==
969 11:36:40.682615 RX Vref Scan: 1
970 11:36:40.682685
971 11:36:40.685580 Set Vref Range= 32 -> 127
972 11:36:40.685646
973 11:36:40.685699 RX Vref 32 -> 127, step: 1
974 11:36:40.685749
975 11:36:40.689002 RX Delay -95 -> 252, step: 8
976 11:36:40.689090
977 11:36:40.692276 Set Vref, RX VrefLevel [Byte0]: 32
978 11:36:40.695153 [Byte1]: 32
979 11:36:40.695224
980 11:36:40.698574 Set Vref, RX VrefLevel [Byte0]: 33
981 11:36:40.701828 [Byte1]: 33
982 11:36:40.706209
983 11:36:40.706274 Set Vref, RX VrefLevel [Byte0]: 34
984 11:36:40.709104 [Byte1]: 34
985 11:36:40.713872
986 11:36:40.713934 Set Vref, RX VrefLevel [Byte0]: 35
987 11:36:40.717254 [Byte1]: 35
988 11:36:40.721270
989 11:36:40.721340 Set Vref, RX VrefLevel [Byte0]: 36
990 11:36:40.724465 [Byte1]: 36
991 11:36:40.729121
992 11:36:40.729229 Set Vref, RX VrefLevel [Byte0]: 37
993 11:36:40.731995 [Byte1]: 37
994 11:36:40.736427
995 11:36:40.736493 Set Vref, RX VrefLevel [Byte0]: 38
996 11:36:40.739805 [Byte1]: 38
997 11:36:40.744175
998 11:36:40.744243 Set Vref, RX VrefLevel [Byte0]: 39
999 11:36:40.747511 [Byte1]: 39
1000 11:36:40.751782
1001 11:36:40.751876 Set Vref, RX VrefLevel [Byte0]: 40
1002 11:36:40.755048 [Byte1]: 40
1003 11:36:40.759816
1004 11:36:40.759882 Set Vref, RX VrefLevel [Byte0]: 41
1005 11:36:40.762351 [Byte1]: 41
1006 11:36:40.766783
1007 11:36:40.766852 Set Vref, RX VrefLevel [Byte0]: 42
1008 11:36:40.769814 [Byte1]: 42
1009 11:36:40.774639
1010 11:36:40.774729 Set Vref, RX VrefLevel [Byte0]: 43
1011 11:36:40.777452 [Byte1]: 43
1012 11:36:40.781936
1013 11:36:40.782006 Set Vref, RX VrefLevel [Byte0]: 44
1014 11:36:40.785368 [Byte1]: 44
1015 11:36:40.790017
1016 11:36:40.790107 Set Vref, RX VrefLevel [Byte0]: 45
1017 11:36:40.792541 [Byte1]: 45
1018 11:36:40.797288
1019 11:36:40.797360 Set Vref, RX VrefLevel [Byte0]: 46
1020 11:36:40.800155 [Byte1]: 46
1021 11:36:40.804677
1022 11:36:40.804795 Set Vref, RX VrefLevel [Byte0]: 47
1023 11:36:40.807978 [Byte1]: 47
1024 11:36:40.812660
1025 11:36:40.812754 Set Vref, RX VrefLevel [Byte0]: 48
1026 11:36:40.815433 [Byte1]: 48
1027 11:36:40.820500
1028 11:36:40.820594 Set Vref, RX VrefLevel [Byte0]: 49
1029 11:36:40.823025 [Byte1]: 49
1030 11:36:40.827650
1031 11:36:40.827719 Set Vref, RX VrefLevel [Byte0]: 50
1032 11:36:40.830619 [Byte1]: 50
1033 11:36:40.835355
1034 11:36:40.835428 Set Vref, RX VrefLevel [Byte0]: 51
1035 11:36:40.838208 [Byte1]: 51
1036 11:36:40.842605
1037 11:36:40.842672 Set Vref, RX VrefLevel [Byte0]: 52
1038 11:36:40.845789 [Byte1]: 52
1039 11:36:40.850250
1040 11:36:40.850321 Set Vref, RX VrefLevel [Byte0]: 53
1041 11:36:40.853667 [Byte1]: 53
1042 11:36:40.857886
1043 11:36:40.857953 Set Vref, RX VrefLevel [Byte0]: 54
1044 11:36:40.861235 [Byte1]: 54
1045 11:36:40.865385
1046 11:36:40.865451 Set Vref, RX VrefLevel [Byte0]: 55
1047 11:36:40.868934 [Byte1]: 55
1048 11:36:40.872944
1049 11:36:40.873018 Set Vref, RX VrefLevel [Byte0]: 56
1050 11:36:40.876684 [Byte1]: 56
1051 11:36:40.880787
1052 11:36:40.880860 Set Vref, RX VrefLevel [Byte0]: 57
1053 11:36:40.884483 [Byte1]: 57
1054 11:36:40.888295
1055 11:36:40.888357 Set Vref, RX VrefLevel [Byte0]: 58
1056 11:36:40.891737 [Byte1]: 58
1057 11:36:40.896094
1058 11:36:40.896159 Set Vref, RX VrefLevel [Byte0]: 59
1059 11:36:40.899294 [Byte1]: 59
1060 11:36:40.903186
1061 11:36:40.903261 Set Vref, RX VrefLevel [Byte0]: 60
1062 11:36:40.906809 [Byte1]: 60
1063 11:36:40.911118
1064 11:36:40.911192 Set Vref, RX VrefLevel [Byte0]: 61
1065 11:36:40.914647 [Byte1]: 61
1066 11:36:40.918896
1067 11:36:40.918971 Set Vref, RX VrefLevel [Byte0]: 62
1068 11:36:40.921999 [Byte1]: 62
1069 11:36:40.926095
1070 11:36:40.926195 Set Vref, RX VrefLevel [Byte0]: 63
1071 11:36:40.932774 [Byte1]: 63
1072 11:36:40.932844
1073 11:36:40.936049 Set Vref, RX VrefLevel [Byte0]: 64
1074 11:36:40.939032 [Byte1]: 64
1075 11:36:40.939100
1076 11:36:40.942789 Set Vref, RX VrefLevel [Byte0]: 65
1077 11:36:40.945963 [Byte1]: 65
1078 11:36:40.946034
1079 11:36:40.949367 Set Vref, RX VrefLevel [Byte0]: 66
1080 11:36:40.952618 [Byte1]: 66
1081 11:36:40.956658
1082 11:36:40.956740 Set Vref, RX VrefLevel [Byte0]: 67
1083 11:36:40.959952 [Byte1]: 67
1084 11:36:40.964458
1085 11:36:40.964522 Set Vref, RX VrefLevel [Byte0]: 68
1086 11:36:40.967729 [Byte1]: 68
1087 11:36:40.971992
1088 11:36:40.972065 Set Vref, RX VrefLevel [Byte0]: 69
1089 11:36:40.975063 [Byte1]: 69
1090 11:36:40.979286
1091 11:36:40.979359 Set Vref, RX VrefLevel [Byte0]: 70
1092 11:36:40.982976 [Byte1]: 70
1093 11:36:40.987116
1094 11:36:40.987190 Set Vref, RX VrefLevel [Byte0]: 71
1095 11:36:40.990254 [Byte1]: 71
1096 11:36:40.994405
1097 11:36:40.994478 Set Vref, RX VrefLevel [Byte0]: 72
1098 11:36:40.997789 [Byte1]: 72
1099 11:36:41.002203
1100 11:36:41.002276 Set Vref, RX VrefLevel [Byte0]: 73
1101 11:36:41.005466 [Byte1]: 73
1102 11:36:41.009706
1103 11:36:41.009777 Set Vref, RX VrefLevel [Byte0]: 74
1104 11:36:41.012949 [Byte1]: 74
1105 11:36:41.017455
1106 11:36:41.017524 Set Vref, RX VrefLevel [Byte0]: 75
1107 11:36:41.021022 [Byte1]: 75
1108 11:36:41.024778
1109 11:36:41.024883 Final RX Vref Byte 0 = 57 to rank0
1110 11:36:41.028063 Final RX Vref Byte 1 = 59 to rank0
1111 11:36:41.031959 Final RX Vref Byte 0 = 57 to rank1
1112 11:36:41.035279 Final RX Vref Byte 1 = 59 to rank1==
1113 11:36:41.038815 Dram Type= 6, Freq= 0, CH_0, rank 0
1114 11:36:41.045063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1115 11:36:41.045143 ==
1116 11:36:41.045220 DQS Delay:
1117 11:36:41.047875 DQS0 = 0, DQS1 = 0
1118 11:36:41.047939 DQM Delay:
1119 11:36:41.047999 DQM0 = 88, DQM1 = 76
1120 11:36:41.051471 DQ Delay:
1121 11:36:41.054893 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1122 11:36:41.058202 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1123 11:36:41.060969 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1124 11:36:41.064598 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1125 11:36:41.064697
1126 11:36:41.064778
1127 11:36:41.071295 [DQSOSCAuto] RK0, (LSB)MR18= 0x302a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1128 11:36:41.074630 CH0 RK0: MR19=606, MR18=302A
1129 11:36:41.081162 CH0_RK0: MR19=0x606, MR18=0x302A, DQSOSC=397, MR23=63, INC=93, DEC=62
1130 11:36:41.081268
1131 11:36:41.084409 ----->DramcWriteLeveling(PI) begin...
1132 11:36:41.084489 ==
1133 11:36:41.087775 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 11:36:41.091077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 11:36:41.091195 ==
1136 11:36:41.094617 Write leveling (Byte 0): 31 => 31
1137 11:36:41.097761 Write leveling (Byte 1): 24 => 24
1138 11:36:41.101730 DramcWriteLeveling(PI) end<-----
1139 11:36:41.101827
1140 11:36:41.101910 ==
1141 11:36:41.104581 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:36:41.107955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:36:41.108029 ==
1144 11:36:41.110780 [Gating] SW mode calibration
1145 11:36:41.117556 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1146 11:36:41.123969 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1147 11:36:41.127799 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 11:36:41.134160 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1149 11:36:41.137467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 11:36:41.140794 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:36:41.184831 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:36:41.185189 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:36:41.185260 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:36:41.185644 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:36:41.185710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:36:41.185994 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:36:41.186836 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:36:41.187161 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:36:41.187226 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:36:41.187278 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:36:41.200792 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:36:41.201075 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:36:41.203874 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1164 11:36:41.206944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1165 11:36:41.207015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1166 11:36:41.210810 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:36:41.217335 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:36:41.220038 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:36:41.223583 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:36:41.230315 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:36:41.233641 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:36:41.236739 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1173 11:36:41.243282 0 9 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
1174 11:36:41.246703 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1175 11:36:41.249691 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 11:36:41.256831 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 11:36:41.259576 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:36:41.263177 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:36:41.269409 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:36:41.273079 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1181 11:36:41.276031 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1182 11:36:41.283229 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:36:41.286214 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:36:41.289529 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:36:41.296394 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:36:41.299433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:36:41.303057 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:36:41.309817 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1189 11:36:41.313127 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1190 11:36:41.316332 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 11:36:41.323232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 11:36:41.326658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 11:36:41.329530 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:36:41.336274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:36:41.339903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:36:41.342909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 11:36:41.350042 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1198 11:36:41.352510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:36:41.356332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:36:41.362900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:36:41.366229 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:36:41.369544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:36:41.376023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:36:41.379434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:36:41.382735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:36:41.386389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:36:41.392416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:36:41.396100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:36:41.399268 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:36:41.405903 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:36:41.408837 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1212 11:36:41.412229 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:36:41.419239 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1214 11:36:41.422347 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 11:36:41.425756 Total UI for P1: 0, mck2ui 16
1216 11:36:41.429344 best dqsien dly found for B0: ( 0, 14, 8)
1217 11:36:41.432250 Total UI for P1: 0, mck2ui 16
1218 11:36:41.435701 best dqsien dly found for B1: ( 0, 14, 8)
1219 11:36:41.438971 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1220 11:36:41.442484 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1221 11:36:41.442557
1222 11:36:41.445260 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 11:36:41.448547 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1224 11:36:41.452238 [Gating] SW calibration Done
1225 11:36:41.452312 ==
1226 11:36:41.455369 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 11:36:41.461924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 11:36:41.461998 ==
1229 11:36:41.462055 RX Vref Scan: 0
1230 11:36:41.462108
1231 11:36:41.465302 RX Vref 0 -> 0, step: 1
1232 11:36:41.465368
1233 11:36:41.468920 RX Delay -130 -> 252, step: 16
1234 11:36:41.471746 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1235 11:36:41.475353 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1236 11:36:41.478432 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1237 11:36:41.485348 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1238 11:36:41.488169 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1239 11:36:41.491828 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1240 11:36:41.495284 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1241 11:36:41.498318 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1242 11:36:41.505089 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1243 11:36:41.508123 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1244 11:36:41.511902 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1245 11:36:41.515082 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1246 11:36:41.518164 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1247 11:36:41.524763 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1248 11:36:41.528114 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1249 11:36:41.531411 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1250 11:36:41.531509 ==
1251 11:36:41.534782 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 11:36:41.538167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 11:36:41.538242 ==
1254 11:36:41.541325 DQS Delay:
1255 11:36:41.541400 DQS0 = 0, DQS1 = 0
1256 11:36:41.544525 DQM Delay:
1257 11:36:41.544600 DQM0 = 88, DQM1 = 77
1258 11:36:41.544658 DQ Delay:
1259 11:36:41.547889 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1260 11:36:41.551314 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1261 11:36:41.554592 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1262 11:36:41.557941 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1263 11:36:41.558017
1264 11:36:41.558075
1265 11:36:41.561566 ==
1266 11:36:41.561642 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 11:36:41.568269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 11:36:41.568345 ==
1269 11:36:41.568404
1270 11:36:41.568458
1271 11:36:41.571493 TX Vref Scan disable
1272 11:36:41.571569 == TX Byte 0 ==
1273 11:36:41.578293 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1274 11:36:41.580974 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1275 11:36:41.581072 == TX Byte 1 ==
1276 11:36:41.584419 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1277 11:36:41.591225 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1278 11:36:41.591302 ==
1279 11:36:41.594574 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 11:36:41.597878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 11:36:41.597954 ==
1282 11:36:41.612288 TX Vref=22, minBit 1, minWin=27, winSum=444
1283 11:36:41.615421 TX Vref=24, minBit 1, minWin=27, winSum=447
1284 11:36:41.618950 TX Vref=26, minBit 1, minWin=27, winSum=447
1285 11:36:41.622054 TX Vref=28, minBit 2, minWin=27, winSum=450
1286 11:36:41.625273 TX Vref=30, minBit 0, minWin=28, winSum=452
1287 11:36:41.628975 TX Vref=32, minBit 1, minWin=27, winSum=450
1288 11:36:41.635154 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1289 11:36:41.635231
1290 11:36:41.638670 Final TX Range 1 Vref 30
1291 11:36:41.638745
1292 11:36:41.638803 ==
1293 11:36:41.641881 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 11:36:41.645335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 11:36:41.645411 ==
1296 11:36:41.645470
1297 11:36:41.648896
1298 11:36:41.648970 TX Vref Scan disable
1299 11:36:41.652856 == TX Byte 0 ==
1300 11:36:41.655177 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1301 11:36:41.662396 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1302 11:36:41.662472 == TX Byte 1 ==
1303 11:36:41.665342 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1304 11:36:41.671860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1305 11:36:41.671938
1306 11:36:41.671996 [DATLAT]
1307 11:36:41.672049 Freq=800, CH0 RK1
1308 11:36:41.672101
1309 11:36:41.675482 DATLAT Default: 0xa
1310 11:36:41.675557 0, 0xFFFF, sum = 0
1311 11:36:41.678444 1, 0xFFFF, sum = 0
1312 11:36:41.678519 2, 0xFFFF, sum = 0
1313 11:36:41.681799 3, 0xFFFF, sum = 0
1314 11:36:41.685045 4, 0xFFFF, sum = 0
1315 11:36:41.685121 5, 0xFFFF, sum = 0
1316 11:36:41.688414 6, 0xFFFF, sum = 0
1317 11:36:41.688489 7, 0xFFFF, sum = 0
1318 11:36:41.691901 8, 0xFFFF, sum = 0
1319 11:36:41.691976 9, 0x0, sum = 1
1320 11:36:41.692036 10, 0x0, sum = 2
1321 11:36:41.695151 11, 0x0, sum = 3
1322 11:36:41.695227 12, 0x0, sum = 4
1323 11:36:41.698391 best_step = 10
1324 11:36:41.698466
1325 11:36:41.698523 ==
1326 11:36:41.701413 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 11:36:41.705042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 11:36:41.705147 ==
1329 11:36:41.708118 RX Vref Scan: 0
1330 11:36:41.708192
1331 11:36:41.708249 RX Vref 0 -> 0, step: 1
1332 11:36:41.711767
1333 11:36:41.711841 RX Delay -95 -> 252, step: 8
1334 11:36:41.718712 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1335 11:36:41.722214 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1336 11:36:41.725000 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1337 11:36:41.729212 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1338 11:36:41.731744 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1339 11:36:41.738322 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1340 11:36:41.741842 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1341 11:36:41.745045 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1342 11:36:41.748351 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1343 11:36:41.751900 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1344 11:36:41.758757 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1345 11:36:41.761944 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1346 11:36:41.765057 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1347 11:36:41.768203 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1348 11:36:41.774673 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1349 11:36:41.778027 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1350 11:36:41.778093 ==
1351 11:36:41.781394 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 11:36:41.784763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 11:36:41.784851 ==
1354 11:36:41.788017 DQS Delay:
1355 11:36:41.788092 DQS0 = 0, DQS1 = 0
1356 11:36:41.788150 DQM Delay:
1357 11:36:41.791471 DQM0 = 86, DQM1 = 77
1358 11:36:41.791556 DQ Delay:
1359 11:36:41.795064 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1360 11:36:41.798112 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1361 11:36:41.801289 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1362 11:36:41.804733 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1363 11:36:41.804809
1364 11:36:41.804866
1365 11:36:41.815433 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1366 11:36:41.815508 CH0 RK1: MR19=606, MR18=2E2A
1367 11:36:41.821401 CH0_RK1: MR19=0x606, MR18=0x2E2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1368 11:36:41.825066 [RxdqsGatingPostProcess] freq 800
1369 11:36:41.831448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 11:36:41.834657 Pre-setting of DQS Precalculation
1371 11:36:41.838070 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 11:36:41.838146 ==
1373 11:36:41.841444 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 11:36:41.847941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 11:36:41.848017 ==
1376 11:36:41.851707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 11:36:41.858247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 11:36:41.867107 [CA 0] Center 36 (6~67) winsize 62
1379 11:36:41.870126 [CA 1] Center 37 (6~68) winsize 63
1380 11:36:41.873829 [CA 2] Center 35 (5~65) winsize 61
1381 11:36:41.877045 [CA 3] Center 34 (4~65) winsize 62
1382 11:36:41.880725 [CA 4] Center 34 (4~65) winsize 62
1383 11:36:41.883311 [CA 5] Center 33 (3~64) winsize 62
1384 11:36:41.883389
1385 11:36:41.887025 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1386 11:36:41.887099
1387 11:36:41.890575 [CATrainingPosCal] consider 1 rank data
1388 11:36:41.893787 u2DelayCellTimex100 = 270/100 ps
1389 11:36:41.896767 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1390 11:36:41.903459 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1391 11:36:41.906580 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1392 11:36:41.910279 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 11:36:41.913322 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 11:36:41.916501 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 11:36:41.916575
1396 11:36:41.920314 CA PerBit enable=1, Macro0, CA PI delay=33
1397 11:36:41.920390
1398 11:36:41.923087 [CBTSetCACLKResult] CA Dly = 33
1399 11:36:41.926504 CS Dly: 4 (0~35)
1400 11:36:41.926580 ==
1401 11:36:41.930198 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 11:36:41.933105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 11:36:41.933226 ==
1404 11:36:41.936517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 11:36:41.943186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 11:36:41.953346 [CA 0] Center 36 (6~67) winsize 62
1407 11:36:41.956790 [CA 1] Center 37 (6~68) winsize 63
1408 11:36:41.959767 [CA 2] Center 34 (4~65) winsize 62
1409 11:36:41.963051 [CA 3] Center 34 (3~65) winsize 63
1410 11:36:41.967179 [CA 4] Center 34 (3~65) winsize 63
1411 11:36:41.970326 [CA 5] Center 34 (3~65) winsize 63
1412 11:36:41.970401
1413 11:36:41.973094 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1414 11:36:41.973217
1415 11:36:41.976610 [CATrainingPosCal] consider 2 rank data
1416 11:36:41.979657 u2DelayCellTimex100 = 270/100 ps
1417 11:36:41.983231 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1418 11:36:41.986251 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1419 11:36:41.993195 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1420 11:36:41.996802 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 11:36:41.999949 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 11:36:42.003274 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 11:36:42.003348
1424 11:36:42.006280 CA PerBit enable=1, Macro0, CA PI delay=33
1425 11:36:42.006356
1426 11:36:42.009702 [CBTSetCACLKResult] CA Dly = 33
1427 11:36:42.009778 CS Dly: 5 (0~38)
1428 11:36:42.013039
1429 11:36:42.016415 ----->DramcWriteLeveling(PI) begin...
1430 11:36:42.016493 ==
1431 11:36:42.019578 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 11:36:42.023248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 11:36:42.023324 ==
1434 11:36:42.026390 Write leveling (Byte 0): 26 => 26
1435 11:36:42.029595 Write leveling (Byte 1): 26 => 26
1436 11:36:42.033089 DramcWriteLeveling(PI) end<-----
1437 11:36:42.033215
1438 11:36:42.033274 ==
1439 11:36:42.036782 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:36:42.039862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:36:42.039937 ==
1442 11:36:42.042945 [Gating] SW mode calibration
1443 11:36:42.049519 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 11:36:42.055939 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 11:36:42.059393 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 11:36:42.062459 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1447 11:36:42.069417 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:36:42.073069 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:36:42.076207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:36:42.082844 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:36:42.085592 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:36:42.089372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:36:42.095543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:36:42.098985 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:36:42.102486 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:36:42.108927 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:36:42.112270 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:36:42.115789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:36:42.119206 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:36:42.126125 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:36:42.129283 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:36:42.132540 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:36:42.139327 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1464 11:36:42.142130 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:36:42.145827 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:36:42.152279 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:36:42.155269 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:36:42.158909 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:36:42.165306 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:36:42.168589 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1471 11:36:42.171856 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1472 11:36:42.179243 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:36:42.181990 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:36:42.185189 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 11:36:42.191863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 11:36:42.195244 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 11:36:42.198417 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 11:36:42.205499 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
1479 11:36:42.208441 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1480 11:36:42.212309 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:36:42.218619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:36:42.221873 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:36:42.225493 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:36:42.231675 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:36:42.235326 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:36:42.238441 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1487 11:36:42.245575 0 11 8 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (0 0)
1488 11:36:42.248330 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 11:36:42.252127 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:36:42.257960 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:36:42.261730 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 11:36:42.264584 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:36:42.271374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:36:42.274740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1495 11:36:42.278399 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:36:42.284829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:36:42.288320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:36:42.291436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:36:42.294843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:36:42.301488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:36:42.304600 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:36:42.308223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:36:42.314985 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:36:42.318028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:36:42.321257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:36:42.328154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:36:42.331766 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:36:42.334339 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:36:42.340974 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:36:42.344567 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 11:36:42.347567 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1512 11:36:42.351000 Total UI for P1: 0, mck2ui 16
1513 11:36:42.354611 best dqsien dly found for B0: ( 0, 14, 4)
1514 11:36:42.361349 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 11:36:42.361420 Total UI for P1: 0, mck2ui 16
1516 11:36:42.367900 best dqsien dly found for B1: ( 0, 14, 8)
1517 11:36:42.371024 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 11:36:42.375027 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1519 11:36:42.375117
1520 11:36:42.377841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 11:36:42.381228 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 11:36:42.384364 [Gating] SW calibration Done
1523 11:36:42.384431 ==
1524 11:36:42.388043 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 11:36:42.391141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 11:36:42.391234 ==
1527 11:36:42.394835 RX Vref Scan: 0
1528 11:36:42.394925
1529 11:36:42.395008 RX Vref 0 -> 0, step: 1
1530 11:36:42.395087
1531 11:36:42.397447 RX Delay -130 -> 252, step: 16
1532 11:36:42.401242 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 11:36:42.407685 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1534 11:36:42.410712 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1535 11:36:42.414249 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1536 11:36:42.417363 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1537 11:36:42.420564 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1538 11:36:42.427203 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1539 11:36:42.431137 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1540 11:36:42.433816 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1541 11:36:42.437413 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1542 11:36:42.440637 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1543 11:36:42.447369 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1544 11:36:42.451300 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 11:36:42.453898 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 11:36:42.457084 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 11:36:42.464147 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 11:36:42.464253 ==
1549 11:36:42.467194 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 11:36:42.470912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 11:36:42.471005 ==
1552 11:36:42.471091 DQS Delay:
1553 11:36:42.473594 DQS0 = 0, DQS1 = 0
1554 11:36:42.473658 DQM Delay:
1555 11:36:42.477870 DQM0 = 85, DQM1 = 78
1556 11:36:42.477942 DQ Delay:
1557 11:36:42.480402 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1558 11:36:42.483821 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =77
1559 11:36:42.487089 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1560 11:36:42.490554 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 11:36:42.490645
1562 11:36:42.490726
1563 11:36:42.490804 ==
1564 11:36:42.493578 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 11:36:42.496812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 11:36:42.496910 ==
1567 11:36:42.500069
1568 11:36:42.500160
1569 11:36:42.500244 TX Vref Scan disable
1570 11:36:42.503395 == TX Byte 0 ==
1571 11:36:42.506660 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1572 11:36:42.509904 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1573 11:36:42.513514 == TX Byte 1 ==
1574 11:36:42.516980 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1575 11:36:42.519768 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1576 11:36:42.523194 ==
1577 11:36:42.523288 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 11:36:42.529481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 11:36:42.529554 ==
1580 11:36:42.541993 TX Vref=22, minBit 1, minWin=27, winSum=443
1581 11:36:42.545225 TX Vref=24, minBit 0, minWin=27, winSum=447
1582 11:36:42.548326 TX Vref=26, minBit 2, minWin=27, winSum=453
1583 11:36:42.551901 TX Vref=28, minBit 6, minWin=27, winSum=458
1584 11:36:42.555013 TX Vref=30, minBit 5, minWin=27, winSum=455
1585 11:36:42.561808 TX Vref=32, minBit 0, minWin=27, winSum=452
1586 11:36:42.565351 [TxChooseVref] Worse bit 6, Min win 27, Win sum 458, Final Vref 28
1587 11:36:42.565428
1588 11:36:42.568467 Final TX Range 1 Vref 28
1589 11:36:42.568558
1590 11:36:42.568641 ==
1591 11:36:42.571895 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 11:36:42.575202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 11:36:42.575291 ==
1594 11:36:42.578800
1595 11:36:42.578889
1596 11:36:42.578969 TX Vref Scan disable
1597 11:36:42.581495 == TX Byte 0 ==
1598 11:36:42.585048 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1599 11:36:42.591219 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1600 11:36:42.591312 == TX Byte 1 ==
1601 11:36:42.595111 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1602 11:36:42.601292 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1603 11:36:42.601383
1604 11:36:42.601465 [DATLAT]
1605 11:36:42.601528 Freq=800, CH1 RK0
1606 11:36:42.601581
1607 11:36:42.605041 DATLAT Default: 0xa
1608 11:36:42.605129 0, 0xFFFF, sum = 0
1609 11:36:42.608350 1, 0xFFFF, sum = 0
1610 11:36:42.611376 2, 0xFFFF, sum = 0
1611 11:36:42.611464 3, 0xFFFF, sum = 0
1612 11:36:42.614651 4, 0xFFFF, sum = 0
1613 11:36:42.614740 5, 0xFFFF, sum = 0
1614 11:36:42.617907 6, 0xFFFF, sum = 0
1615 11:36:42.617967 7, 0xFFFF, sum = 0
1616 11:36:42.621782 8, 0xFFFF, sum = 0
1617 11:36:42.621874 9, 0x0, sum = 1
1618 11:36:42.624979 10, 0x0, sum = 2
1619 11:36:42.625073 11, 0x0, sum = 3
1620 11:36:42.625197 12, 0x0, sum = 4
1621 11:36:42.628196 best_step = 10
1622 11:36:42.628258
1623 11:36:42.628310 ==
1624 11:36:42.631322 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:36:42.634680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:36:42.634774 ==
1627 11:36:42.637768 RX Vref Scan: 1
1628 11:36:42.637858
1629 11:36:42.641028 Set Vref Range= 32 -> 127
1630 11:36:42.641145
1631 11:36:42.641216 RX Vref 32 -> 127, step: 1
1632 11:36:42.641273
1633 11:36:42.644282 RX Delay -95 -> 252, step: 8
1634 11:36:42.644367
1635 11:36:42.647586 Set Vref, RX VrefLevel [Byte0]: 32
1636 11:36:42.651329 [Byte1]: 32
1637 11:36:42.654474
1638 11:36:42.654558 Set Vref, RX VrefLevel [Byte0]: 33
1639 11:36:42.657499 [Byte1]: 33
1640 11:36:42.662296
1641 11:36:42.662361 Set Vref, RX VrefLevel [Byte0]: 34
1642 11:36:42.665481 [Byte1]: 34
1643 11:36:42.669589
1644 11:36:42.669681 Set Vref, RX VrefLevel [Byte0]: 35
1645 11:36:42.673036 [Byte1]: 35
1646 11:36:42.677439
1647 11:36:42.677502 Set Vref, RX VrefLevel [Byte0]: 36
1648 11:36:42.681008 [Byte1]: 36
1649 11:36:42.684749
1650 11:36:42.684840 Set Vref, RX VrefLevel [Byte0]: 37
1651 11:36:42.688250 [Byte1]: 37
1652 11:36:42.692607
1653 11:36:42.692671 Set Vref, RX VrefLevel [Byte0]: 38
1654 11:36:42.695560 [Byte1]: 38
1655 11:36:42.700289
1656 11:36:42.700354 Set Vref, RX VrefLevel [Byte0]: 39
1657 11:36:42.703592 [Byte1]: 39
1658 11:36:42.707821
1659 11:36:42.707912 Set Vref, RX VrefLevel [Byte0]: 40
1660 11:36:42.710833 [Byte1]: 40
1661 11:36:42.715290
1662 11:36:42.715378 Set Vref, RX VrefLevel [Byte0]: 41
1663 11:36:42.718873 [Byte1]: 41
1664 11:36:42.723133
1665 11:36:42.723220 Set Vref, RX VrefLevel [Byte0]: 42
1666 11:36:42.726071 [Byte1]: 42
1667 11:36:42.730450
1668 11:36:42.730541 Set Vref, RX VrefLevel [Byte0]: 43
1669 11:36:42.733856 [Byte1]: 43
1670 11:36:42.738068
1671 11:36:42.738140 Set Vref, RX VrefLevel [Byte0]: 44
1672 11:36:42.741072 [Byte1]: 44
1673 11:36:42.745991
1674 11:36:42.746078 Set Vref, RX VrefLevel [Byte0]: 45
1675 11:36:42.748723 [Byte1]: 45
1676 11:36:42.753731
1677 11:36:42.753822 Set Vref, RX VrefLevel [Byte0]: 46
1678 11:36:42.756559 [Byte1]: 46
1679 11:36:42.761079
1680 11:36:42.761182 Set Vref, RX VrefLevel [Byte0]: 47
1681 11:36:42.764122 [Byte1]: 47
1682 11:36:42.768223
1683 11:36:42.768311 Set Vref, RX VrefLevel [Byte0]: 48
1684 11:36:42.771814 [Byte1]: 48
1685 11:36:42.776144
1686 11:36:42.776232 Set Vref, RX VrefLevel [Byte0]: 49
1687 11:36:42.779203 [Byte1]: 49
1688 11:36:42.783733
1689 11:36:42.783826 Set Vref, RX VrefLevel [Byte0]: 50
1690 11:36:42.786837 [Byte1]: 50
1691 11:36:42.791538
1692 11:36:42.791632 Set Vref, RX VrefLevel [Byte0]: 51
1693 11:36:42.794377 [Byte1]: 51
1694 11:36:42.799042
1695 11:36:42.799140 Set Vref, RX VrefLevel [Byte0]: 52
1696 11:36:42.802178 [Byte1]: 52
1697 11:36:42.806553
1698 11:36:42.806647 Set Vref, RX VrefLevel [Byte0]: 53
1699 11:36:42.809752 [Byte1]: 53
1700 11:36:42.813795
1701 11:36:42.813885 Set Vref, RX VrefLevel [Byte0]: 54
1702 11:36:42.817572 [Byte1]: 54
1703 11:36:42.822063
1704 11:36:42.822149 Set Vref, RX VrefLevel [Byte0]: 55
1705 11:36:42.824805 [Byte1]: 55
1706 11:36:42.829252
1707 11:36:42.829320 Set Vref, RX VrefLevel [Byte0]: 56
1708 11:36:42.832523 [Byte1]: 56
1709 11:36:42.837115
1710 11:36:42.837215 Set Vref, RX VrefLevel [Byte0]: 57
1711 11:36:42.840439 [Byte1]: 57
1712 11:36:42.844337
1713 11:36:42.844401 Set Vref, RX VrefLevel [Byte0]: 58
1714 11:36:42.847934 [Byte1]: 58
1715 11:36:42.852320
1716 11:36:42.852407 Set Vref, RX VrefLevel [Byte0]: 59
1717 11:36:42.855656 [Byte1]: 59
1718 11:36:42.859504
1719 11:36:42.859571 Set Vref, RX VrefLevel [Byte0]: 60
1720 11:36:42.862830 [Byte1]: 60
1721 11:36:42.867157
1722 11:36:42.867243 Set Vref, RX VrefLevel [Byte0]: 61
1723 11:36:42.870559 [Byte1]: 61
1724 11:36:42.874564
1725 11:36:42.874656 Set Vref, RX VrefLevel [Byte0]: 62
1726 11:36:42.881479 [Byte1]: 62
1727 11:36:42.881571
1728 11:36:42.884694 Set Vref, RX VrefLevel [Byte0]: 63
1729 11:36:42.887684 [Byte1]: 63
1730 11:36:42.887770
1731 11:36:42.891419 Set Vref, RX VrefLevel [Byte0]: 64
1732 11:36:42.894520 [Byte1]: 64
1733 11:36:42.894611
1734 11:36:42.897745 Set Vref, RX VrefLevel [Byte0]: 65
1735 11:36:42.901523 [Byte1]: 65
1736 11:36:42.904991
1737 11:36:42.905104 Set Vref, RX VrefLevel [Byte0]: 66
1738 11:36:42.908422 [Byte1]: 66
1739 11:36:42.912542
1740 11:36:42.912604 Set Vref, RX VrefLevel [Byte0]: 67
1741 11:36:42.916400 [Byte1]: 67
1742 11:36:42.920249
1743 11:36:42.920327 Set Vref, RX VrefLevel [Byte0]: 68
1744 11:36:42.924165 [Byte1]: 68
1745 11:36:42.927729
1746 11:36:42.927816 Set Vref, RX VrefLevel [Byte0]: 69
1747 11:36:42.931211 [Byte1]: 69
1748 11:36:42.936022
1749 11:36:42.936110 Set Vref, RX VrefLevel [Byte0]: 70
1750 11:36:42.939168 [Byte1]: 70
1751 11:36:42.943135
1752 11:36:42.943222 Set Vref, RX VrefLevel [Byte0]: 71
1753 11:36:42.946367 [Byte1]: 71
1754 11:36:42.951043
1755 11:36:42.951129 Set Vref, RX VrefLevel [Byte0]: 72
1756 11:36:42.953740 [Byte1]: 72
1757 11:36:42.958243
1758 11:36:42.958335 Set Vref, RX VrefLevel [Byte0]: 73
1759 11:36:42.961763 [Byte1]: 73
1760 11:36:42.966191
1761 11:36:42.966254 Set Vref, RX VrefLevel [Byte0]: 74
1762 11:36:42.969492 [Byte1]: 74
1763 11:36:42.973619
1764 11:36:42.973690 Set Vref, RX VrefLevel [Byte0]: 75
1765 11:36:42.977207 [Byte1]: 75
1766 11:36:42.980900
1767 11:36:42.980993 Set Vref, RX VrefLevel [Byte0]: 76
1768 11:36:42.984313 [Byte1]: 76
1769 11:36:42.988722
1770 11:36:42.988811 Final RX Vref Byte 0 = 54 to rank0
1771 11:36:42.992263 Final RX Vref Byte 1 = 57 to rank0
1772 11:36:42.995522 Final RX Vref Byte 0 = 54 to rank1
1773 11:36:42.998519 Final RX Vref Byte 1 = 57 to rank1==
1774 11:36:43.001956 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 11:36:43.008565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 11:36:43.008644 ==
1777 11:36:43.008728 DQS Delay:
1778 11:36:43.012123 DQS0 = 0, DQS1 = 0
1779 11:36:43.012208 DQM Delay:
1780 11:36:43.012283 DQM0 = 85, DQM1 = 80
1781 11:36:43.015158 DQ Delay:
1782 11:36:43.018366 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1783 11:36:43.021933 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1784 11:36:43.024939 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1785 11:36:43.028168 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1786 11:36:43.028238
1787 11:36:43.028291
1788 11:36:43.034983 [DQSOSCAuto] RK0, (LSB)MR18= 0x192c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1789 11:36:43.038575 CH1 RK0: MR19=606, MR18=192C
1790 11:36:43.045033 CH1_RK0: MR19=0x606, MR18=0x192C, DQSOSC=398, MR23=63, INC=93, DEC=62
1791 11:36:43.045129
1792 11:36:43.048695 ----->DramcWriteLeveling(PI) begin...
1793 11:36:43.048786 ==
1794 11:36:43.052093 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 11:36:43.054808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 11:36:43.054901 ==
1797 11:36:43.058340 Write leveling (Byte 0): 26 => 26
1798 11:36:43.061332 Write leveling (Byte 1): 30 => 30
1799 11:36:43.064723 DramcWriteLeveling(PI) end<-----
1800 11:36:43.064808
1801 11:36:43.064890 ==
1802 11:36:43.067910 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 11:36:43.071448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 11:36:43.071551 ==
1805 11:36:43.074840 [Gating] SW mode calibration
1806 11:36:43.081057 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 11:36:43.087867 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 11:36:43.091511 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 11:36:43.097844 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 11:36:43.101334 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:36:43.104613 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:36:43.110994 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:36:43.114353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:36:43.117704 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:36:43.124111 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:36:43.127461 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:36:43.131072 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:36:43.137247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:36:43.140793 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:36:43.143859 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:36:43.150789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:36:43.154269 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:36:43.157279 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:36:43.163814 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:36:43.167211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1826 11:36:43.170143 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:36:43.177050 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:36:43.180327 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:36:43.184178 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:36:43.190165 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:36:43.193781 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:36:43.197049 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:36:43.203247 0 9 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1834 11:36:43.206883 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1835 11:36:43.209867 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:36:43.216688 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:36:43.220424 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:36:43.223094 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:36:43.230171 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:36:43.233041 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:36:43.236789 0 10 4 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
1842 11:36:43.239844 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
1843 11:36:43.246519 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:36:43.249609 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:36:43.253023 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:36:43.259769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:36:43.263137 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:36:43.266247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:36:43.272863 0 11 4 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (1 1)
1850 11:36:43.275958 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1851 11:36:43.279449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:36:43.285992 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:36:43.289392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:36:43.292911 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:36:43.299837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:36:43.302788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:36:43.306052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1858 11:36:43.312859 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:36:43.315859 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:36:43.319199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:36:43.325973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:36:43.329146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:36:43.332236 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:36:43.339054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:36:43.342641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:36:43.345495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:36:43.352770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:36:43.355664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:36:43.358741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:36:43.365784 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:36:43.368769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:36:43.372070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:36:43.378717 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1874 11:36:43.381887 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1875 11:36:43.385339 Total UI for P1: 0, mck2ui 16
1876 11:36:43.388849 best dqsien dly found for B0: ( 0, 14, 4)
1877 11:36:43.392138 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 11:36:43.395010 Total UI for P1: 0, mck2ui 16
1879 11:36:43.398658 best dqsien dly found for B1: ( 0, 14, 8)
1880 11:36:43.401867 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1881 11:36:43.405118 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1882 11:36:43.405216
1883 11:36:43.411757 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1884 11:36:43.415089 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1885 11:36:43.415164 [Gating] SW calibration Done
1886 11:36:43.418301 ==
1887 11:36:43.422234 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 11:36:43.425656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 11:36:43.425733 ==
1890 11:36:43.425791 RX Vref Scan: 0
1891 11:36:43.425845
1892 11:36:43.428518 RX Vref 0 -> 0, step: 1
1893 11:36:43.428592
1894 11:36:43.431756 RX Delay -130 -> 252, step: 16
1895 11:36:43.435556 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1896 11:36:43.438653 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1897 11:36:43.441820 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1898 11:36:43.448385 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1899 11:36:43.452012 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1900 11:36:43.455304 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1901 11:36:43.459122 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1902 11:36:43.461470 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1903 11:36:43.468670 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1904 11:36:43.471325 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1905 11:36:43.475027 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1906 11:36:43.478175 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1907 11:36:43.484656 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1908 11:36:43.488084 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1909 11:36:43.491466 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1910 11:36:43.494570 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1911 11:36:43.494645 ==
1912 11:36:43.498097 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 11:36:43.504573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 11:36:43.504672 ==
1915 11:36:43.504760 DQS Delay:
1916 11:36:43.504842 DQS0 = 0, DQS1 = 0
1917 11:36:43.507998 DQM Delay:
1918 11:36:43.508088 DQM0 = 83, DQM1 = 80
1919 11:36:43.511490 DQ Delay:
1920 11:36:43.514705 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1921 11:36:43.514801 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1922 11:36:43.517858 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1923 11:36:43.524553 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1924 11:36:43.524642
1925 11:36:43.524730
1926 11:36:43.524810 ==
1927 11:36:43.527634 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 11:36:43.531119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 11:36:43.531214 ==
1930 11:36:43.531294
1931 11:36:43.531381
1932 11:36:43.534562 TX Vref Scan disable
1933 11:36:43.534656 == TX Byte 0 ==
1934 11:36:43.541595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 11:36:43.544456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 11:36:43.544547 == TX Byte 1 ==
1937 11:36:43.550958 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1938 11:36:43.555050 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1939 11:36:43.555139 ==
1940 11:36:43.557735 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 11:36:43.561076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 11:36:43.561171 ==
1943 11:36:43.575322 TX Vref=22, minBit 1, minWin=27, winSum=448
1944 11:36:43.578827 TX Vref=24, minBit 1, minWin=27, winSum=451
1945 11:36:43.581710 TX Vref=26, minBit 1, minWin=27, winSum=452
1946 11:36:43.585284 TX Vref=28, minBit 6, minWin=27, winSum=452
1947 11:36:43.588800 TX Vref=30, minBit 0, minWin=28, winSum=455
1948 11:36:43.595469 TX Vref=32, minBit 5, minWin=27, winSum=454
1949 11:36:43.598549 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1950 11:36:43.598655
1951 11:36:43.601876 Final TX Range 1 Vref 30
1952 11:36:43.601967
1953 11:36:43.602059 ==
1954 11:36:43.605082 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:36:43.608146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:36:43.608235 ==
1957 11:36:43.611425
1958 11:36:43.611513
1959 11:36:43.611601 TX Vref Scan disable
1960 11:36:43.615150 == TX Byte 0 ==
1961 11:36:43.618763 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1962 11:36:43.622144 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1963 11:36:43.625705 == TX Byte 1 ==
1964 11:36:43.628848 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 11:36:43.632010 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 11:36:43.635002
1967 11:36:43.635099 [DATLAT]
1968 11:36:43.635183 Freq=800, CH1 RK1
1969 11:36:43.635264
1970 11:36:43.638851 DATLAT Default: 0xa
1971 11:36:43.638924 0, 0xFFFF, sum = 0
1972 11:36:43.642254 1, 0xFFFF, sum = 0
1973 11:36:43.642322 2, 0xFFFF, sum = 0
1974 11:36:43.645506 3, 0xFFFF, sum = 0
1975 11:36:43.645582 4, 0xFFFF, sum = 0
1976 11:36:43.648543 5, 0xFFFF, sum = 0
1977 11:36:43.652165 6, 0xFFFF, sum = 0
1978 11:36:43.652266 7, 0xFFFF, sum = 0
1979 11:36:43.655463 8, 0xFFFF, sum = 0
1980 11:36:43.655539 9, 0x0, sum = 1
1981 11:36:43.655598 10, 0x0, sum = 2
1982 11:36:43.658556 11, 0x0, sum = 3
1983 11:36:43.658629 12, 0x0, sum = 4
1984 11:36:43.661790 best_step = 10
1985 11:36:43.661869
1986 11:36:43.661926 ==
1987 11:36:43.665632 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:36:43.668160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:36:43.668252 ==
1990 11:36:43.671671 RX Vref Scan: 0
1991 11:36:43.671747
1992 11:36:43.671832 RX Vref 0 -> 0, step: 1
1993 11:36:43.671911
1994 11:36:43.675143 RX Delay -95 -> 252, step: 8
1995 11:36:43.681731 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1996 11:36:43.685454 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1997 11:36:43.688651 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1998 11:36:43.691684 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1999 11:36:43.695089 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2000 11:36:43.702414 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2001 11:36:43.705118 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2002 11:36:43.708450 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2003 11:36:43.711800 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2004 11:36:43.715143 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2005 11:36:43.721956 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2006 11:36:43.725299 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2007 11:36:43.728281 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2008 11:36:43.732129 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2009 11:36:43.738522 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2010 11:36:43.741480 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2011 11:36:43.741569 ==
2012 11:36:43.745391 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:36:43.748353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:36:43.748459 ==
2015 11:36:43.748544 DQS Delay:
2016 11:36:43.751842 DQS0 = 0, DQS1 = 0
2017 11:36:43.751940 DQM Delay:
2018 11:36:43.754591 DQM0 = 87, DQM1 = 81
2019 11:36:43.754656 DQ Delay:
2020 11:36:43.758121 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =88
2021 11:36:43.761559 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2022 11:36:43.764942 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2023 11:36:43.768379 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2024 11:36:43.768446
2025 11:36:43.768501
2026 11:36:43.778158 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2027 11:36:43.778234 CH1 RK1: MR19=606, MR18=203C
2028 11:36:43.784797 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2029 11:36:43.788410 [RxdqsGatingPostProcess] freq 800
2030 11:36:43.794706 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 11:36:43.798314 Pre-setting of DQS Precalculation
2032 11:36:43.801685 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 11:36:43.808391 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 11:36:43.817973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 11:36:43.818052
2036 11:36:43.818110
2037 11:36:43.821545 [Calibration Summary] 1600 Mbps
2038 11:36:43.821620 CH 0, Rank 0
2039 11:36:43.824434 SW Impedance : PASS
2040 11:36:43.824508 DUTY Scan : NO K
2041 11:36:43.828361 ZQ Calibration : PASS
2042 11:36:43.828436 Jitter Meter : NO K
2043 11:36:43.831307 CBT Training : PASS
2044 11:36:43.834570 Write leveling : PASS
2045 11:36:43.834646 RX DQS gating : PASS
2046 11:36:43.838157 RX DQ/DQS(RDDQC) : PASS
2047 11:36:43.841250 TX DQ/DQS : PASS
2048 11:36:43.841326 RX DATLAT : PASS
2049 11:36:43.844602 RX DQ/DQS(Engine): PASS
2050 11:36:43.848300 TX OE : NO K
2051 11:36:43.848375 All Pass.
2052 11:36:43.848433
2053 11:36:43.848488 CH 0, Rank 1
2054 11:36:43.851525 SW Impedance : PASS
2055 11:36:43.854665 DUTY Scan : NO K
2056 11:36:43.854740 ZQ Calibration : PASS
2057 11:36:43.857967 Jitter Meter : NO K
2058 11:36:43.861485 CBT Training : PASS
2059 11:36:43.861560 Write leveling : PASS
2060 11:36:43.864616 RX DQS gating : PASS
2061 11:36:43.867986 RX DQ/DQS(RDDQC) : PASS
2062 11:36:43.868061 TX DQ/DQS : PASS
2063 11:36:43.871282 RX DATLAT : PASS
2064 11:36:43.871356 RX DQ/DQS(Engine): PASS
2065 11:36:43.874354 TX OE : NO K
2066 11:36:43.874429 All Pass.
2067 11:36:43.874488
2068 11:36:43.877781 CH 1, Rank 0
2069 11:36:43.877857 SW Impedance : PASS
2070 11:36:43.881410 DUTY Scan : NO K
2071 11:36:43.884840 ZQ Calibration : PASS
2072 11:36:43.884914 Jitter Meter : NO K
2073 11:36:43.888168 CBT Training : PASS
2074 11:36:43.891019 Write leveling : PASS
2075 11:36:43.891094 RX DQS gating : PASS
2076 11:36:43.894245 RX DQ/DQS(RDDQC) : PASS
2077 11:36:43.897540 TX DQ/DQS : PASS
2078 11:36:43.897615 RX DATLAT : PASS
2079 11:36:43.900720 RX DQ/DQS(Engine): PASS
2080 11:36:43.904059 TX OE : NO K
2081 11:36:43.904134 All Pass.
2082 11:36:43.904191
2083 11:36:43.904245 CH 1, Rank 1
2084 11:36:43.907425 SW Impedance : PASS
2085 11:36:43.910657 DUTY Scan : NO K
2086 11:36:43.910750 ZQ Calibration : PASS
2087 11:36:43.914241 Jitter Meter : NO K
2088 11:36:43.917093 CBT Training : PASS
2089 11:36:43.917188 Write leveling : PASS
2090 11:36:43.920767 RX DQS gating : PASS
2091 11:36:43.923683 RX DQ/DQS(RDDQC) : PASS
2092 11:36:43.923757 TX DQ/DQS : PASS
2093 11:36:43.927371 RX DATLAT : PASS
2094 11:36:43.930411 RX DQ/DQS(Engine): PASS
2095 11:36:43.930485 TX OE : NO K
2096 11:36:43.930544 All Pass.
2097 11:36:43.934004
2098 11:36:43.934078 DramC Write-DBI off
2099 11:36:43.936898 PER_BANK_REFRESH: Hybrid Mode
2100 11:36:43.936973 TX_TRACKING: ON
2101 11:36:43.940454 [GetDramInforAfterCalByMRR] Vendor 6.
2102 11:36:43.944117 [GetDramInforAfterCalByMRR] Revision 606.
2103 11:36:43.950369 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 11:36:43.950445 MR0 0x3b3b
2105 11:36:43.950503 MR8 0x5151
2106 11:36:43.954157 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 11:36:43.954232
2108 11:36:43.957185 MR0 0x3b3b
2109 11:36:43.957260 MR8 0x5151
2110 11:36:43.960639 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 11:36:43.960714
2112 11:36:43.970662 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 11:36:43.974099 [FAST_K] Save calibration result to emmc
2114 11:36:43.977186 [FAST_K] Save calibration result to emmc
2115 11:36:43.980572 dram_init: config_dvfs: 1
2116 11:36:43.984075 dramc_set_vcore_voltage set vcore to 662500
2117 11:36:43.987124 Read voltage for 1200, 2
2118 11:36:43.987199 Vio18 = 0
2119 11:36:43.987257 Vcore = 662500
2120 11:36:43.990737 Vdram = 0
2121 11:36:43.990812 Vddq = 0
2122 11:36:43.990870 Vmddr = 0
2123 11:36:43.997061 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 11:36:44.000164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 11:36:44.004460 MEM_TYPE=3, freq_sel=15
2126 11:36:44.007326 sv_algorithm_assistance_LP4_1600
2127 11:36:44.010843 ============ PULL DRAM RESETB DOWN ============
2128 11:36:44.013527 ========== PULL DRAM RESETB DOWN end =========
2129 11:36:44.020577 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 11:36:44.023540 ===================================
2131 11:36:44.023615 LPDDR4 DRAM CONFIGURATION
2132 11:36:44.026956 ===================================
2133 11:36:44.030642 EX_ROW_EN[0] = 0x0
2134 11:36:44.033815 EX_ROW_EN[1] = 0x0
2135 11:36:44.033890 LP4Y_EN = 0x0
2136 11:36:44.036677 WORK_FSP = 0x0
2137 11:36:44.036753 WL = 0x4
2138 11:36:44.040017 RL = 0x4
2139 11:36:44.040092 BL = 0x2
2140 11:36:44.043404 RPST = 0x0
2141 11:36:44.043479 RD_PRE = 0x0
2142 11:36:44.046867 WR_PRE = 0x1
2143 11:36:44.046942 WR_PST = 0x0
2144 11:36:44.049959 DBI_WR = 0x0
2145 11:36:44.050034 DBI_RD = 0x0
2146 11:36:44.053664 OTF = 0x1
2147 11:36:44.057066 ===================================
2148 11:36:44.060050 ===================================
2149 11:36:44.060129 ANA top config
2150 11:36:44.063370 ===================================
2151 11:36:44.066841 DLL_ASYNC_EN = 0
2152 11:36:44.070147 ALL_SLAVE_EN = 0
2153 11:36:44.073373 NEW_RANK_MODE = 1
2154 11:36:44.073449 DLL_IDLE_MODE = 1
2155 11:36:44.077058 LP45_APHY_COMB_EN = 1
2156 11:36:44.080003 TX_ODT_DIS = 1
2157 11:36:44.083178 NEW_8X_MODE = 1
2158 11:36:44.086340 ===================================
2159 11:36:44.089786 ===================================
2160 11:36:44.093389 data_rate = 2400
2161 11:36:44.093464 CKR = 1
2162 11:36:44.096391 DQ_P2S_RATIO = 8
2163 11:36:44.100152 ===================================
2164 11:36:44.103312 CA_P2S_RATIO = 8
2165 11:36:44.106396 DQ_CA_OPEN = 0
2166 11:36:44.110287 DQ_SEMI_OPEN = 0
2167 11:36:44.110361 CA_SEMI_OPEN = 0
2168 11:36:44.113293 CA_FULL_RATE = 0
2169 11:36:44.116594 DQ_CKDIV4_EN = 0
2170 11:36:44.120086 CA_CKDIV4_EN = 0
2171 11:36:44.123333 CA_PREDIV_EN = 0
2172 11:36:44.126253 PH8_DLY = 17
2173 11:36:44.126318 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 11:36:44.129705 DQ_AAMCK_DIV = 4
2175 11:36:44.133211 CA_AAMCK_DIV = 4
2176 11:36:44.136229 CA_ADMCK_DIV = 4
2177 11:36:44.139526 DQ_TRACK_CA_EN = 0
2178 11:36:44.142866 CA_PICK = 1200
2179 11:36:44.146223 CA_MCKIO = 1200
2180 11:36:44.146297 MCKIO_SEMI = 0
2181 11:36:44.149510 PLL_FREQ = 2366
2182 11:36:44.153289 DQ_UI_PI_RATIO = 32
2183 11:36:44.156026 CA_UI_PI_RATIO = 0
2184 11:36:44.159978 ===================================
2185 11:36:44.162906 ===================================
2186 11:36:44.166018 memory_type:LPDDR4
2187 11:36:44.166093 GP_NUM : 10
2188 11:36:44.169117 SRAM_EN : 1
2189 11:36:44.172793 MD32_EN : 0
2190 11:36:44.176020 ===================================
2191 11:36:44.176120 [ANA_INIT] >>>>>>>>>>>>>>
2192 11:36:44.179447 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 11:36:44.182721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 11:36:44.185987 ===================================
2195 11:36:44.189502 data_rate = 2400,PCW = 0X5b00
2196 11:36:44.192542 ===================================
2197 11:36:44.195649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 11:36:44.202674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 11:36:44.205970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 11:36:44.212574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 11:36:44.216044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 11:36:44.219450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 11:36:44.219526 [ANA_INIT] flow start
2204 11:36:44.222499 [ANA_INIT] PLL >>>>>>>>
2205 11:36:44.225819 [ANA_INIT] PLL <<<<<<<<
2206 11:36:44.229613 [ANA_INIT] MIDPI >>>>>>>>
2207 11:36:44.229688 [ANA_INIT] MIDPI <<<<<<<<
2208 11:36:44.232479 [ANA_INIT] DLL >>>>>>>>
2209 11:36:44.235803 [ANA_INIT] DLL <<<<<<<<
2210 11:36:44.235887 [ANA_INIT] flow end
2211 11:36:44.239231 ============ LP4 DIFF to SE enter ============
2212 11:36:44.245634 ============ LP4 DIFF to SE exit ============
2213 11:36:44.245709 [ANA_INIT] <<<<<<<<<<<<<
2214 11:36:44.249025 [Flow] Enable top DCM control >>>>>
2215 11:36:44.252430 [Flow] Enable top DCM control <<<<<
2216 11:36:44.255786 Enable DLL master slave shuffle
2217 11:36:44.262188 ==============================================================
2218 11:36:44.265381 Gating Mode config
2219 11:36:44.268580 ==============================================================
2220 11:36:44.271851 Config description:
2221 11:36:44.281819 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 11:36:44.288468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 11:36:44.291882 SELPH_MODE 0: By rank 1: By Phase
2224 11:36:44.298636 ==============================================================
2225 11:36:44.301833 GAT_TRACK_EN = 1
2226 11:36:44.304974 RX_GATING_MODE = 2
2227 11:36:44.308254 RX_GATING_TRACK_MODE = 2
2228 11:36:44.308329 SELPH_MODE = 1
2229 11:36:44.311663 PICG_EARLY_EN = 1
2230 11:36:44.315140 VALID_LAT_VALUE = 1
2231 11:36:44.321873 ==============================================================
2232 11:36:44.324731 Enter into Gating configuration >>>>
2233 11:36:44.327872 Exit from Gating configuration <<<<
2234 11:36:44.331642 Enter into DVFS_PRE_config >>>>>
2235 11:36:44.341227 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 11:36:44.344930 Exit from DVFS_PRE_config <<<<<
2237 11:36:44.348208 Enter into PICG configuration >>>>
2238 11:36:44.351383 Exit from PICG configuration <<<<
2239 11:36:44.354754 [RX_INPUT] configuration >>>>>
2240 11:36:44.357760 [RX_INPUT] configuration <<<<<
2241 11:36:44.361181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 11:36:44.367661 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 11:36:44.374129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 11:36:44.381431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 11:36:44.387754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:36:44.394185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:36:44.397790 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 11:36:44.401028 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 11:36:44.404344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 11:36:44.410580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 11:36:44.414116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 11:36:44.417326 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 11:36:44.420629 ===================================
2254 11:36:44.424134 LPDDR4 DRAM CONFIGURATION
2255 11:36:44.427138 ===================================
2256 11:36:44.427213 EX_ROW_EN[0] = 0x0
2257 11:36:44.430537 EX_ROW_EN[1] = 0x0
2258 11:36:44.430617 LP4Y_EN = 0x0
2259 11:36:44.433982 WORK_FSP = 0x0
2260 11:36:44.434057 WL = 0x4
2261 11:36:44.437132 RL = 0x4
2262 11:36:44.440722 BL = 0x2
2263 11:36:44.440797 RPST = 0x0
2264 11:36:44.443681 RD_PRE = 0x0
2265 11:36:44.443763 WR_PRE = 0x1
2266 11:36:44.447602 WR_PST = 0x0
2267 11:36:44.447677 DBI_WR = 0x0
2268 11:36:44.450674 DBI_RD = 0x0
2269 11:36:44.450749 OTF = 0x1
2270 11:36:44.453653 ===================================
2271 11:36:44.457391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 11:36:44.463516 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 11:36:44.466752 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 11:36:44.470083 ===================================
2275 11:36:44.473769 LPDDR4 DRAM CONFIGURATION
2276 11:36:44.477057 ===================================
2277 11:36:44.477132 EX_ROW_EN[0] = 0x10
2278 11:36:44.480109 EX_ROW_EN[1] = 0x0
2279 11:36:44.480183 LP4Y_EN = 0x0
2280 11:36:44.483476 WORK_FSP = 0x0
2281 11:36:44.486836 WL = 0x4
2282 11:36:44.486914 RL = 0x4
2283 11:36:44.490329 BL = 0x2
2284 11:36:44.490404 RPST = 0x0
2285 11:36:44.493883 RD_PRE = 0x0
2286 11:36:44.493982 WR_PRE = 0x1
2287 11:36:44.496669 WR_PST = 0x0
2288 11:36:44.496744 DBI_WR = 0x0
2289 11:36:44.500076 DBI_RD = 0x0
2290 11:36:44.500178 OTF = 0x1
2291 11:36:44.503621 ===================================
2292 11:36:44.510169 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 11:36:44.510269 ==
2294 11:36:44.513506 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 11:36:44.516572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 11:36:44.516646 ==
2297 11:36:44.520155 [Duty_Offset_Calibration]
2298 11:36:44.523813 B0:2 B1:0 CA:4
2299 11:36:44.523900
2300 11:36:44.526435 [DutyScan_Calibration_Flow] k_type=0
2301 11:36:44.534730
2302 11:36:44.534793 ==CLK 0==
2303 11:36:44.538272 Final CLK duty delay cell = 0
2304 11:36:44.541026 [0] MAX Duty = 5156%(X100), DQS PI = 14
2305 11:36:44.544469 [0] MIN Duty = 4969%(X100), DQS PI = 8
2306 11:36:44.544566 [0] AVG Duty = 5062%(X100)
2307 11:36:44.547782
2308 11:36:44.551401 CH0 CLK Duty spec in!! Max-Min= 187%
2309 11:36:44.554631 [DutyScan_Calibration_Flow] ====Done====
2310 11:36:44.554724
2311 11:36:44.557837 [DutyScan_Calibration_Flow] k_type=1
2312 11:36:44.573787
2313 11:36:44.573884 ==DQS 0 ==
2314 11:36:44.577371 Final DQS duty delay cell = 0
2315 11:36:44.580548 [0] MAX Duty = 5156%(X100), DQS PI = 18
2316 11:36:44.583772 [0] MIN Duty = 5093%(X100), DQS PI = 0
2317 11:36:44.583911 [0] AVG Duty = 5124%(X100)
2318 11:36:44.587361
2319 11:36:44.587516 ==DQS 1 ==
2320 11:36:44.590719 Final DQS duty delay cell = 0
2321 11:36:44.593940 [0] MAX Duty = 5125%(X100), DQS PI = 48
2322 11:36:44.596944 [0] MIN Duty = 5000%(X100), DQS PI = 0
2323 11:36:44.600418 [0] AVG Duty = 5062%(X100)
2324 11:36:44.600564
2325 11:36:44.603869 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2326 11:36:44.604090
2327 11:36:44.607416 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2328 11:36:44.611310 [DutyScan_Calibration_Flow] ====Done====
2329 11:36:44.611661
2330 11:36:44.613697 [DutyScan_Calibration_Flow] k_type=3
2331 11:36:44.630233
2332 11:36:44.630307 ==DQM 0 ==
2333 11:36:44.633494 Final DQM duty delay cell = 0
2334 11:36:44.637044 [0] MAX Duty = 5062%(X100), DQS PI = 18
2335 11:36:44.640215 [0] MIN Duty = 4844%(X100), DQS PI = 50
2336 11:36:44.643507 [0] AVG Duty = 4953%(X100)
2337 11:36:44.643604
2338 11:36:44.643687 ==DQM 1 ==
2339 11:36:44.646605 Final DQM duty delay cell = 0
2340 11:36:44.650204 [0] MAX Duty = 5000%(X100), DQS PI = 6
2341 11:36:44.653434 [0] MIN Duty = 4875%(X100), DQS PI = 20
2342 11:36:44.656732 [0] AVG Duty = 4937%(X100)
2343 11:36:44.656800
2344 11:36:44.659985 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2345 11:36:44.660052
2346 11:36:44.663687 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2347 11:36:44.666394 [DutyScan_Calibration_Flow] ====Done====
2348 11:36:44.666468
2349 11:36:44.670336 [DutyScan_Calibration_Flow] k_type=2
2350 11:36:44.686412
2351 11:36:44.686487 ==DQ 0 ==
2352 11:36:44.689843 Final DQ duty delay cell = 0
2353 11:36:44.693002 [0] MAX Duty = 5156%(X100), DQS PI = 18
2354 11:36:44.696367 [0] MIN Duty = 4969%(X100), DQS PI = 52
2355 11:36:44.696460 [0] AVG Duty = 5062%(X100)
2356 11:36:44.699729
2357 11:36:44.699822 ==DQ 1 ==
2358 11:36:44.703280 Final DQ duty delay cell = 0
2359 11:36:44.706742 [0] MAX Duty = 5156%(X100), DQS PI = 6
2360 11:36:44.709764 [0] MIN Duty = 4938%(X100), DQS PI = 16
2361 11:36:44.709827 [0] AVG Duty = 5047%(X100)
2362 11:36:44.713557
2363 11:36:44.716151 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2364 11:36:44.716226
2365 11:36:44.719822 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2366 11:36:44.722815 [DutyScan_Calibration_Flow] ====Done====
2367 11:36:44.722909 ==
2368 11:36:44.726600 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 11:36:44.729556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 11:36:44.729633 ==
2371 11:36:44.732968 [Duty_Offset_Calibration]
2372 11:36:44.733042 B0:0 B1:-1 CA:3
2373 11:36:44.733100
2374 11:36:44.736135 [DutyScan_Calibration_Flow] k_type=0
2375 11:36:44.746685
2376 11:36:44.746759 ==CLK 0==
2377 11:36:44.750065 Final CLK duty delay cell = 0
2378 11:36:44.753030 [0] MAX Duty = 5156%(X100), DQS PI = 0
2379 11:36:44.756625 [0] MIN Duty = 5000%(X100), DQS PI = 36
2380 11:36:44.756716 [0] AVG Duty = 5078%(X100)
2381 11:36:44.759813
2382 11:36:44.763021 CH1 CLK Duty spec in!! Max-Min= 156%
2383 11:36:44.766336 [DutyScan_Calibration_Flow] ====Done====
2384 11:36:44.766398
2385 11:36:44.769749 [DutyScan_Calibration_Flow] k_type=1
2386 11:36:44.785557
2387 11:36:44.785626 ==DQS 0 ==
2388 11:36:44.789349 Final DQS duty delay cell = 0
2389 11:36:44.792467 [0] MAX Duty = 5156%(X100), DQS PI = 18
2390 11:36:44.795861 [0] MIN Duty = 4907%(X100), DQS PI = 38
2391 11:36:44.798654 [0] AVG Duty = 5031%(X100)
2392 11:36:44.798748
2393 11:36:44.798830 ==DQS 1 ==
2394 11:36:44.802392 Final DQS duty delay cell = 0
2395 11:36:44.805510 [0] MAX Duty = 5156%(X100), DQS PI = 10
2396 11:36:44.808756 [0] MIN Duty = 5031%(X100), DQS PI = 24
2397 11:36:44.812441 [0] AVG Duty = 5093%(X100)
2398 11:36:44.812505
2399 11:36:44.815599 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2400 11:36:44.815687
2401 11:36:44.818871 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2402 11:36:44.822392 [DutyScan_Calibration_Flow] ====Done====
2403 11:36:44.822478
2404 11:36:44.825314 [DutyScan_Calibration_Flow] k_type=3
2405 11:36:44.843299
2406 11:36:44.843374 ==DQM 0 ==
2407 11:36:44.846233 Final DQM duty delay cell = 0
2408 11:36:44.850234 [0] MAX Duty = 5031%(X100), DQS PI = 28
2409 11:36:44.852850 [0] MIN Duty = 4782%(X100), DQS PI = 38
2410 11:36:44.856388 [0] AVG Duty = 4906%(X100)
2411 11:36:44.856457
2412 11:36:44.856540 ==DQM 1 ==
2413 11:36:44.859703 Final DQM duty delay cell = 4
2414 11:36:44.863119 [4] MAX Duty = 5187%(X100), DQS PI = 30
2415 11:36:44.866071 [4] MIN Duty = 5062%(X100), DQS PI = 2
2416 11:36:44.869439 [4] AVG Duty = 5124%(X100)
2417 11:36:44.869507
2418 11:36:44.872833 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2419 11:36:44.872904
2420 11:36:44.876085 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2421 11:36:44.879729 [DutyScan_Calibration_Flow] ====Done====
2422 11:36:44.879791
2423 11:36:44.882635 [DutyScan_Calibration_Flow] k_type=2
2424 11:36:44.899444
2425 11:36:44.899538 ==DQ 0 ==
2426 11:36:44.903058 Final DQ duty delay cell = -4
2427 11:36:44.906293 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2428 11:36:44.909442 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2429 11:36:44.912845 [-4] AVG Duty = 4922%(X100)
2430 11:36:44.912919
2431 11:36:44.912977 ==DQ 1 ==
2432 11:36:44.916568 Final DQ duty delay cell = 4
2433 11:36:44.919968 [4] MAX Duty = 5156%(X100), DQS PI = 10
2434 11:36:44.923189 [4] MIN Duty = 5031%(X100), DQS PI = 62
2435 11:36:44.923264 [4] AVG Duty = 5093%(X100)
2436 11:36:44.926445
2437 11:36:44.929694 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2438 11:36:44.929769
2439 11:36:44.933262 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2440 11:36:44.936074 [DutyScan_Calibration_Flow] ====Done====
2441 11:36:44.939935 nWR fixed to 30
2442 11:36:44.940011 [ModeRegInit_LP4] CH0 RK0
2443 11:36:44.942813 [ModeRegInit_LP4] CH0 RK1
2444 11:36:44.946295 [ModeRegInit_LP4] CH1 RK0
2445 11:36:44.949538 [ModeRegInit_LP4] CH1 RK1
2446 11:36:44.949612 match AC timing 7
2447 11:36:44.955797 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 11:36:44.959480 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 11:36:44.962555 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 11:36:44.969094 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 11:36:44.972387 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 11:36:44.972456 ==
2453 11:36:44.975928 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 11:36:44.978992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 11:36:44.979064 ==
2456 11:36:44.985745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 11:36:44.992458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2458 11:36:44.999963 [CA 0] Center 39 (9~70) winsize 62
2459 11:36:45.003221 [CA 1] Center 39 (9~70) winsize 62
2460 11:36:45.006476 [CA 2] Center 35 (5~66) winsize 62
2461 11:36:45.010054 [CA 3] Center 35 (5~66) winsize 62
2462 11:36:45.013385 [CA 4] Center 33 (3~64) winsize 62
2463 11:36:45.016195 [CA 5] Center 33 (3~63) winsize 61
2464 11:36:45.016270
2465 11:36:45.020010 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2466 11:36:45.020085
2467 11:36:45.022765 [CATrainingPosCal] consider 1 rank data
2468 11:36:45.026448 u2DelayCellTimex100 = 270/100 ps
2469 11:36:45.029988 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2470 11:36:45.036789 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2471 11:36:45.039768 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 11:36:45.043048 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2473 11:36:45.046466 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2474 11:36:45.049669 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2475 11:36:45.049744
2476 11:36:45.053072 CA PerBit enable=1, Macro0, CA PI delay=33
2477 11:36:45.053170
2478 11:36:45.056038 [CBTSetCACLKResult] CA Dly = 33
2479 11:36:45.056113 CS Dly: 7 (0~38)
2480 11:36:45.059241 ==
2481 11:36:45.062750 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 11:36:45.066342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 11:36:45.066418 ==
2484 11:36:45.069321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 11:36:45.076309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 11:36:45.085553 [CA 0] Center 39 (9~70) winsize 62
2487 11:36:45.089244 [CA 1] Center 39 (9~70) winsize 62
2488 11:36:45.092203 [CA 2] Center 35 (5~66) winsize 62
2489 11:36:45.095570 [CA 3] Center 35 (5~66) winsize 62
2490 11:36:45.099322 [CA 4] Center 34 (4~65) winsize 62
2491 11:36:45.102325 [CA 5] Center 33 (3~64) winsize 62
2492 11:36:45.102400
2493 11:36:45.105579 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 11:36:45.105653
2495 11:36:45.109302 [CATrainingPosCal] consider 2 rank data
2496 11:36:45.112132 u2DelayCellTimex100 = 270/100 ps
2497 11:36:45.115980 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2498 11:36:45.119330 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2499 11:36:45.125507 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 11:36:45.128717 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 11:36:45.132282 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2502 11:36:45.135691 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2503 11:36:45.135766
2504 11:36:45.138789 CA PerBit enable=1, Macro0, CA PI delay=33
2505 11:36:45.138864
2506 11:36:45.142317 [CBTSetCACLKResult] CA Dly = 33
2507 11:36:45.142396 CS Dly: 8 (0~41)
2508 11:36:45.142454
2509 11:36:45.145554 ----->DramcWriteLeveling(PI) begin...
2510 11:36:45.149130 ==
2511 11:36:45.151965 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 11:36:45.155493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:36:45.155570 ==
2514 11:36:45.159383 Write leveling (Byte 0): 31 => 31
2515 11:36:45.162272 Write leveling (Byte 1): 27 => 27
2516 11:36:45.165524 DramcWriteLeveling(PI) end<-----
2517 11:36:45.165599
2518 11:36:45.165656 ==
2519 11:36:45.168846 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:36:45.171769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:36:45.171845 ==
2522 11:36:45.175213 [Gating] SW mode calibration
2523 11:36:45.182227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 11:36:45.188404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 11:36:45.192177 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2526 11:36:45.194972 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2527 11:36:45.202058 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 11:36:45.205396 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 11:36:45.208276 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:36:45.215336 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:36:45.218534 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2532 11:36:45.222063 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2533 11:36:45.225253 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
2534 11:36:45.231800 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 11:36:45.234703 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:36:45.238393 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:36:45.244993 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:36:45.248225 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:36:45.251554 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2540 11:36:45.258908 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2541 11:36:45.261956 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2542 11:36:45.265059 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2543 11:36:45.272377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:36:45.274705 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:36:45.278175 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:36:45.284759 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:36:45.288580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 11:36:45.291948 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 11:36:45.298342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 11:36:45.301498 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 11:36:45.305056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:36:45.311514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:36:45.314928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:36:45.317960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:36:45.324721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:36:45.328129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:36:45.331609 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:36:45.337729 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:36:45.341122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:36:45.344857 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:36:45.348094 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:36:45.354571 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:36:45.358069 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 11:36:45.361479 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 11:36:45.368087 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 11:36:45.371545 Total UI for P1: 0, mck2ui 16
2567 11:36:45.374624 best dqsien dly found for B0: ( 1, 3, 26)
2568 11:36:45.377861 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 11:36:45.381367 Total UI for P1: 0, mck2ui 16
2570 11:36:45.385102 best dqsien dly found for B1: ( 1, 4, 0)
2571 11:36:45.387940 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2572 11:36:45.391325 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 11:36:45.391392
2574 11:36:45.394769 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2575 11:36:45.398047 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 11:36:45.401128 [Gating] SW calibration Done
2577 11:36:45.401257 ==
2578 11:36:45.404527 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:36:45.411590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:36:45.411666 ==
2581 11:36:45.411723 RX Vref Scan: 0
2582 11:36:45.411776
2583 11:36:45.414148 RX Vref 0 -> 0, step: 1
2584 11:36:45.414213
2585 11:36:45.417665 RX Delay -40 -> 252, step: 8
2586 11:36:45.421033 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2587 11:36:45.424459 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2588 11:36:45.427522 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2589 11:36:45.430794 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2590 11:36:45.437489 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2591 11:36:45.440724 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2592 11:36:45.443882 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2593 11:36:45.447268 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2594 11:36:45.450556 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2595 11:36:45.457490 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2596 11:36:45.460954 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2597 11:36:45.464475 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2598 11:36:45.467250 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2599 11:36:45.470404 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2600 11:36:45.477589 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2601 11:36:45.480857 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2602 11:36:45.480925 ==
2603 11:36:45.483943 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 11:36:45.487497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 11:36:45.487565 ==
2606 11:36:45.490868 DQS Delay:
2607 11:36:45.490936 DQS0 = 0, DQS1 = 0
2608 11:36:45.490992 DQM Delay:
2609 11:36:45.494274 DQM0 = 119, DQM1 = 106
2610 11:36:45.494344 DQ Delay:
2611 11:36:45.497772 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2612 11:36:45.500521 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2613 11:36:45.503830 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2614 11:36:45.510750 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2615 11:36:45.510825
2616 11:36:45.510882
2617 11:36:45.510936 ==
2618 11:36:45.513712 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 11:36:45.517192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 11:36:45.517268 ==
2621 11:36:45.517327
2622 11:36:45.517379
2623 11:36:45.520968 TX Vref Scan disable
2624 11:36:45.521067 == TX Byte 0 ==
2625 11:36:45.527235 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2626 11:36:45.530639 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2627 11:36:45.530715 == TX Byte 1 ==
2628 11:36:45.537023 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2629 11:36:45.540542 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2630 11:36:45.540617 ==
2631 11:36:45.543813 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 11:36:45.547235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 11:36:45.547326 ==
2634 11:36:45.560227 TX Vref=22, minBit 1, minWin=25, winSum=410
2635 11:36:45.563362 TX Vref=24, minBit 1, minWin=25, winSum=414
2636 11:36:45.566958 TX Vref=26, minBit 1, minWin=26, winSum=424
2637 11:36:45.570073 TX Vref=28, minBit 13, minWin=25, winSum=427
2638 11:36:45.573838 TX Vref=30, minBit 1, minWin=26, winSum=427
2639 11:36:45.580224 TX Vref=32, minBit 0, minWin=26, winSum=427
2640 11:36:45.583342 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2641 11:36:45.583409
2642 11:36:45.586816 Final TX Range 1 Vref 30
2643 11:36:45.586878
2644 11:36:45.586931 ==
2645 11:36:45.589855 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 11:36:45.593143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 11:36:45.596513 ==
2648 11:36:45.596575
2649 11:36:45.596629
2650 11:36:45.596679 TX Vref Scan disable
2651 11:36:45.600022 == TX Byte 0 ==
2652 11:36:45.603745 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2653 11:36:45.606692 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2654 11:36:45.610397 == TX Byte 1 ==
2655 11:36:45.613348 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2656 11:36:45.616532 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2657 11:36:45.619894
2658 11:36:45.619986 [DATLAT]
2659 11:36:45.620068 Freq=1200, CH0 RK0
2660 11:36:45.620148
2661 11:36:45.623379 DATLAT Default: 0xd
2662 11:36:45.623445 0, 0xFFFF, sum = 0
2663 11:36:45.626256 1, 0xFFFF, sum = 0
2664 11:36:45.629985 2, 0xFFFF, sum = 0
2665 11:36:45.630053 3, 0xFFFF, sum = 0
2666 11:36:45.633340 4, 0xFFFF, sum = 0
2667 11:36:45.633406 5, 0xFFFF, sum = 0
2668 11:36:45.636436 6, 0xFFFF, sum = 0
2669 11:36:45.636514 7, 0xFFFF, sum = 0
2670 11:36:45.639984 8, 0xFFFF, sum = 0
2671 11:36:45.640073 9, 0xFFFF, sum = 0
2672 11:36:45.642943 10, 0xFFFF, sum = 0
2673 11:36:45.643013 11, 0xFFFF, sum = 0
2674 11:36:45.646557 12, 0x0, sum = 1
2675 11:36:45.646623 13, 0x0, sum = 2
2676 11:36:45.650063 14, 0x0, sum = 3
2677 11:36:45.650132 15, 0x0, sum = 4
2678 11:36:45.653023 best_step = 13
2679 11:36:45.653107
2680 11:36:45.653183 ==
2681 11:36:45.656316 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 11:36:45.659791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 11:36:45.659879 ==
2684 11:36:45.659958 RX Vref Scan: 1
2685 11:36:45.660040
2686 11:36:45.662836 Set Vref Range= 32 -> 127
2687 11:36:45.662896
2688 11:36:45.666279 RX Vref 32 -> 127, step: 1
2689 11:36:45.666338
2690 11:36:45.670022 RX Delay -21 -> 252, step: 4
2691 11:36:45.670097
2692 11:36:45.672903 Set Vref, RX VrefLevel [Byte0]: 32
2693 11:36:45.676476 [Byte1]: 32
2694 11:36:45.676551
2695 11:36:45.679507 Set Vref, RX VrefLevel [Byte0]: 33
2696 11:36:45.682879 [Byte1]: 33
2697 11:36:45.686201
2698 11:36:45.686293 Set Vref, RX VrefLevel [Byte0]: 34
2699 11:36:45.689690 [Byte1]: 34
2700 11:36:45.694090
2701 11:36:45.694193 Set Vref, RX VrefLevel [Byte0]: 35
2702 11:36:45.697641 [Byte1]: 35
2703 11:36:45.702603
2704 11:36:45.702673 Set Vref, RX VrefLevel [Byte0]: 36
2705 11:36:45.705677 [Byte1]: 36
2706 11:36:45.711177
2707 11:36:45.711273 Set Vref, RX VrefLevel [Byte0]: 37
2708 11:36:45.713577 [Byte1]: 37
2709 11:36:45.718182
2710 11:36:45.718252 Set Vref, RX VrefLevel [Byte0]: 38
2711 11:36:45.722022 [Byte1]: 38
2712 11:36:45.726307
2713 11:36:45.726376 Set Vref, RX VrefLevel [Byte0]: 39
2714 11:36:45.729527 [Byte1]: 39
2715 11:36:45.734242
2716 11:36:45.734306 Set Vref, RX VrefLevel [Byte0]: 40
2717 11:36:45.737460 [Byte1]: 40
2718 11:36:45.741768
2719 11:36:45.741857 Set Vref, RX VrefLevel [Byte0]: 41
2720 11:36:45.745111 [Byte1]: 41
2721 11:36:45.749966
2722 11:36:45.750029 Set Vref, RX VrefLevel [Byte0]: 42
2723 11:36:45.753083 [Byte1]: 42
2724 11:36:45.758192
2725 11:36:45.758281 Set Vref, RX VrefLevel [Byte0]: 43
2726 11:36:45.760948 [Byte1]: 43
2727 11:36:45.765531
2728 11:36:45.765601 Set Vref, RX VrefLevel [Byte0]: 44
2729 11:36:45.769277 [Byte1]: 44
2730 11:36:45.773830
2731 11:36:45.773904 Set Vref, RX VrefLevel [Byte0]: 45
2732 11:36:45.777318 [Byte1]: 45
2733 11:36:45.781612
2734 11:36:45.781689 Set Vref, RX VrefLevel [Byte0]: 46
2735 11:36:45.784932 [Byte1]: 46
2736 11:36:45.789463
2737 11:36:45.789529 Set Vref, RX VrefLevel [Byte0]: 47
2738 11:36:45.792694 [Byte1]: 47
2739 11:36:45.797565
2740 11:36:45.797671 Set Vref, RX VrefLevel [Byte0]: 48
2741 11:36:45.800521 [Byte1]: 48
2742 11:36:45.805692
2743 11:36:45.805760 Set Vref, RX VrefLevel [Byte0]: 49
2744 11:36:45.808444 [Byte1]: 49
2745 11:36:45.813174
2746 11:36:45.813241 Set Vref, RX VrefLevel [Byte0]: 50
2747 11:36:45.816534 [Byte1]: 50
2748 11:36:45.821251
2749 11:36:45.821319 Set Vref, RX VrefLevel [Byte0]: 51
2750 11:36:45.824740 [Byte1]: 51
2751 11:36:45.829382
2752 11:36:45.829448 Set Vref, RX VrefLevel [Byte0]: 52
2753 11:36:45.832495 [Byte1]: 52
2754 11:36:45.837283
2755 11:36:45.837349 Set Vref, RX VrefLevel [Byte0]: 53
2756 11:36:45.840605 [Byte1]: 53
2757 11:36:45.844870
2758 11:36:45.844961 Set Vref, RX VrefLevel [Byte0]: 54
2759 11:36:45.848236 [Byte1]: 54
2760 11:36:45.852676
2761 11:36:45.852738 Set Vref, RX VrefLevel [Byte0]: 55
2762 11:36:45.856084 [Byte1]: 55
2763 11:36:45.861005
2764 11:36:45.861090 Set Vref, RX VrefLevel [Byte0]: 56
2765 11:36:45.864128 [Byte1]: 56
2766 11:36:45.868480
2767 11:36:45.868541 Set Vref, RX VrefLevel [Byte0]: 57
2768 11:36:45.872004 [Byte1]: 57
2769 11:36:45.876866
2770 11:36:45.876955 Set Vref, RX VrefLevel [Byte0]: 58
2771 11:36:45.879811 [Byte1]: 58
2772 11:36:45.884451
2773 11:36:45.884517 Set Vref, RX VrefLevel [Byte0]: 59
2774 11:36:45.887769 [Byte1]: 59
2775 11:36:45.892636
2776 11:36:45.892704 Set Vref, RX VrefLevel [Byte0]: 60
2777 11:36:45.895599 [Byte1]: 60
2778 11:36:45.900757
2779 11:36:45.900848 Set Vref, RX VrefLevel [Byte0]: 61
2780 11:36:45.904018 [Byte1]: 61
2781 11:36:45.908684
2782 11:36:45.908750 Set Vref, RX VrefLevel [Byte0]: 62
2783 11:36:45.912065 [Byte1]: 62
2784 11:36:45.916495
2785 11:36:45.916560 Set Vref, RX VrefLevel [Byte0]: 63
2786 11:36:45.920379 [Byte1]: 63
2787 11:36:45.924270
2788 11:36:45.924357 Set Vref, RX VrefLevel [Byte0]: 64
2789 11:36:45.927599 [Byte1]: 64
2790 11:36:45.931980
2791 11:36:45.932043 Set Vref, RX VrefLevel [Byte0]: 65
2792 11:36:45.935494 [Byte1]: 65
2793 11:36:45.939903
2794 11:36:45.939994 Set Vref, RX VrefLevel [Byte0]: 66
2795 11:36:45.943618 [Byte1]: 66
2796 11:36:45.948250
2797 11:36:45.948316 Set Vref, RX VrefLevel [Byte0]: 67
2798 11:36:45.951234 [Byte1]: 67
2799 11:36:45.955849
2800 11:36:45.955941 Set Vref, RX VrefLevel [Byte0]: 68
2801 11:36:45.959418 [Byte1]: 68
2802 11:36:45.963867
2803 11:36:45.963932 Final RX Vref Byte 0 = 55 to rank0
2804 11:36:45.967014 Final RX Vref Byte 1 = 50 to rank0
2805 11:36:45.970741 Final RX Vref Byte 0 = 55 to rank1
2806 11:36:45.973707 Final RX Vref Byte 1 = 50 to rank1==
2807 11:36:45.977397 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 11:36:45.983767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 11:36:45.983837 ==
2810 11:36:45.983938 DQS Delay:
2811 11:36:45.984021 DQS0 = 0, DQS1 = 0
2812 11:36:45.987127 DQM Delay:
2813 11:36:45.987191 DQM0 = 119, DQM1 = 105
2814 11:36:45.990369 DQ Delay:
2815 11:36:45.993504 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2816 11:36:45.997431 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
2817 11:36:46.000500 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2818 11:36:46.004116 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2819 11:36:46.004182
2820 11:36:46.004246
2821 11:36:46.010116 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2822 11:36:46.013734 CH0 RK0: MR19=403, MR18=4FF
2823 11:36:46.020432 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2824 11:36:46.020501
2825 11:36:46.023428 ----->DramcWriteLeveling(PI) begin...
2826 11:36:46.023551 ==
2827 11:36:46.026782 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 11:36:46.030316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 11:36:46.033704 ==
2830 11:36:46.033768 Write leveling (Byte 0): 31 => 31
2831 11:36:46.037152 Write leveling (Byte 1): 26 => 26
2832 11:36:46.040228 DramcWriteLeveling(PI) end<-----
2833 11:36:46.040291
2834 11:36:46.040344 ==
2835 11:36:46.043339 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 11:36:46.049959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 11:36:46.050031 ==
2838 11:36:46.050086 [Gating] SW mode calibration
2839 11:36:46.059978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 11:36:46.063507 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 11:36:46.070348 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2842 11:36:46.073480 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2843 11:36:46.076900 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 11:36:46.083476 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 11:36:46.086283 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 11:36:46.090220 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:36:46.096516 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2848 11:36:46.099969 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2849 11:36:46.103341 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2850 11:36:46.106231 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:36:46.113017 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 11:36:46.116381 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 11:36:46.119831 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 11:36:46.126374 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:36:46.129590 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2856 11:36:46.133321 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2857 11:36:46.139572 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2858 11:36:46.142788 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:36:46.146348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:36:46.153042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:36:46.156142 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:36:46.160304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2863 11:36:46.166169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2864 11:36:46.169658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 11:36:46.172897 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2866 11:36:46.179781 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:36:46.182939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:36:46.186381 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:36:46.192876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:36:46.195857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:36:46.199453 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:36:46.206197 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:36:46.209680 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:36:46.212962 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:36:46.219202 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:36:46.222378 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:36:46.225939 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:36:46.232199 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:36:46.235815 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2880 11:36:46.238825 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 11:36:46.245683 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2882 11:36:46.245764 Total UI for P1: 0, mck2ui 16
2883 11:36:46.252383 best dqsien dly found for B0: ( 1, 3, 26)
2884 11:36:46.255483 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 11:36:46.258683 Total UI for P1: 0, mck2ui 16
2886 11:36:46.262402 best dqsien dly found for B1: ( 1, 4, 0)
2887 11:36:46.265652 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2888 11:36:46.269011 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2889 11:36:46.269100
2890 11:36:46.272322 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2891 11:36:46.275502 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2892 11:36:46.278693 [Gating] SW calibration Done
2893 11:36:46.278786 ==
2894 11:36:46.281975 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:36:46.284994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:36:46.285082 ==
2897 11:36:46.288595 RX Vref Scan: 0
2898 11:36:46.288681
2899 11:36:46.291949 RX Vref 0 -> 0, step: 1
2900 11:36:46.292036
2901 11:36:46.292115 RX Delay -40 -> 252, step: 8
2902 11:36:46.298747 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2903 11:36:46.301730 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2904 11:36:46.304954 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2905 11:36:46.308421 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2906 11:36:46.315181 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2907 11:36:46.318006 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2908 11:36:46.322155 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2909 11:36:46.324720 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2910 11:36:46.328159 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2911 11:36:46.331706 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2912 11:36:46.338113 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2913 11:36:46.341202 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2914 11:36:46.344516 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2915 11:36:46.347909 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2916 11:36:46.354843 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2917 11:36:46.357852 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2918 11:36:46.357998 ==
2919 11:36:46.361054 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 11:36:46.364936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 11:36:46.365034 ==
2922 11:36:46.367927 DQS Delay:
2923 11:36:46.368027 DQS0 = 0, DQS1 = 0
2924 11:36:46.368111 DQM Delay:
2925 11:36:46.370992 DQM0 = 118, DQM1 = 106
2926 11:36:46.371092 DQ Delay:
2927 11:36:46.374206 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2928 11:36:46.377568 DQ4 =123, DQ5 =107, DQ6 =127, DQ7 =123
2929 11:36:46.381079 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2930 11:36:46.387648 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2931 11:36:46.387739
2932 11:36:46.387824
2933 11:36:46.387903 ==
2934 11:36:46.390535 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 11:36:46.393929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 11:36:46.394015 ==
2937 11:36:46.394093
2938 11:36:46.394170
2939 11:36:46.397452 TX Vref Scan disable
2940 11:36:46.397530 == TX Byte 0 ==
2941 11:36:46.403942 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2942 11:36:46.407019 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2943 11:36:46.410632 == TX Byte 1 ==
2944 11:36:46.413652 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2945 11:36:46.417514 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2946 11:36:46.417589 ==
2947 11:36:46.420169 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 11:36:46.423584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 11:36:46.427298 ==
2950 11:36:46.437681 TX Vref=22, minBit 5, minWin=25, winSum=415
2951 11:36:46.440495 TX Vref=24, minBit 4, minWin=25, winSum=416
2952 11:36:46.443948 TX Vref=26, minBit 4, minWin=25, winSum=418
2953 11:36:46.447001 TX Vref=28, minBit 0, minWin=26, winSum=421
2954 11:36:46.450240 TX Vref=30, minBit 4, minWin=26, winSum=427
2955 11:36:46.456774 TX Vref=32, minBit 15, minWin=25, winSum=423
2956 11:36:46.460340 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
2957 11:36:46.460416
2958 11:36:46.463388 Final TX Range 1 Vref 30
2959 11:36:46.463476
2960 11:36:46.463534 ==
2961 11:36:46.467025 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 11:36:46.470152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 11:36:46.473715 ==
2964 11:36:46.473790
2965 11:36:46.473847
2966 11:36:46.473900 TX Vref Scan disable
2967 11:36:46.477156 == TX Byte 0 ==
2968 11:36:46.480724 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2969 11:36:46.486733 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2970 11:36:46.486809 == TX Byte 1 ==
2971 11:36:46.490383 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2972 11:36:46.496925 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2973 11:36:46.497001
2974 11:36:46.497058 [DATLAT]
2975 11:36:46.497112 Freq=1200, CH0 RK1
2976 11:36:46.497203
2977 11:36:46.500419 DATLAT Default: 0xd
2978 11:36:46.503332 0, 0xFFFF, sum = 0
2979 11:36:46.503409 1, 0xFFFF, sum = 0
2980 11:36:46.507004 2, 0xFFFF, sum = 0
2981 11:36:46.507097 3, 0xFFFF, sum = 0
2982 11:36:46.510319 4, 0xFFFF, sum = 0
2983 11:36:46.510396 5, 0xFFFF, sum = 0
2984 11:36:46.513378 6, 0xFFFF, sum = 0
2985 11:36:46.513454 7, 0xFFFF, sum = 0
2986 11:36:46.517045 8, 0xFFFF, sum = 0
2987 11:36:46.517157 9, 0xFFFF, sum = 0
2988 11:36:46.520004 10, 0xFFFF, sum = 0
2989 11:36:46.520080 11, 0xFFFF, sum = 0
2990 11:36:46.523406 12, 0x0, sum = 1
2991 11:36:46.523482 13, 0x0, sum = 2
2992 11:36:46.526334 14, 0x0, sum = 3
2993 11:36:46.526410 15, 0x0, sum = 4
2994 11:36:46.530150 best_step = 13
2995 11:36:46.530224
2996 11:36:46.530281 ==
2997 11:36:46.533641 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:36:46.536344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:36:46.536420 ==
3000 11:36:46.539946 RX Vref Scan: 0
3001 11:36:46.540019
3002 11:36:46.540077 RX Vref 0 -> 0, step: 1
3003 11:36:46.540130
3004 11:36:46.542944 RX Delay -21 -> 252, step: 4
3005 11:36:46.549712 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3006 11:36:46.552956 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3007 11:36:46.556344 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3008 11:36:46.559774 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3009 11:36:46.562806 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3010 11:36:46.569772 iDelay=195, Bit 5, Center 110 (47 ~ 174) 128
3011 11:36:46.572986 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3012 11:36:46.576194 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3013 11:36:46.579088 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3014 11:36:46.582807 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3015 11:36:46.589050 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3016 11:36:46.592804 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3017 11:36:46.595859 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3018 11:36:46.599142 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3019 11:36:46.602574 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3020 11:36:46.609046 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3021 11:36:46.609122 ==
3022 11:36:46.612311 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:36:46.615693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:36:46.615772 ==
3025 11:36:46.615831 DQS Delay:
3026 11:36:46.618953 DQS0 = 0, DQS1 = 0
3027 11:36:46.619028 DQM Delay:
3028 11:36:46.621834 DQM0 = 117, DQM1 = 106
3029 11:36:46.621909 DQ Delay:
3030 11:36:46.625057 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3031 11:36:46.628695 DQ4 =120, DQ5 =110, DQ6 =128, DQ7 =124
3032 11:36:46.631864 DQ8 =94, DQ9 =94, DQ10 =108, DQ11 =98
3033 11:36:46.635154 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
3034 11:36:46.638308
3035 11:36:46.638382
3036 11:36:46.644923 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3037 11:36:46.648823 CH0 RK1: MR19=303, MR18=FDFB
3038 11:36:46.654951 CH0_RK1: MR19=0x303, MR18=0xFDFB, DQSOSC=411, MR23=63, INC=38, DEC=25
3039 11:36:46.658371 [RxdqsGatingPostProcess] freq 1200
3040 11:36:46.661896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 11:36:46.665068 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 11:36:46.668048 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 11:36:46.671833 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 11:36:46.674862 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 11:36:46.678153 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 11:36:46.681376 best DQS1 dly(2T, 0.5T) = (0, 12)
3047 11:36:46.684316 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 11:36:46.687516 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3049 11:36:46.691074 Pre-setting of DQS Precalculation
3050 11:36:46.694394 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 11:36:46.694470 ==
3052 11:36:46.697750 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 11:36:46.704330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 11:36:46.704406 ==
3055 11:36:46.707867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 11:36:46.714032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3057 11:36:46.723356 [CA 0] Center 38 (8~68) winsize 61
3058 11:36:46.726770 [CA 1] Center 37 (7~68) winsize 62
3059 11:36:46.729879 [CA 2] Center 35 (5~65) winsize 61
3060 11:36:46.733300 [CA 3] Center 34 (4~64) winsize 61
3061 11:36:46.736516 [CA 4] Center 34 (5~64) winsize 60
3062 11:36:46.739711 [CA 5] Center 33 (3~64) winsize 62
3063 11:36:46.739789
3064 11:36:46.742829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3065 11:36:46.742926
3066 11:36:46.746146 [CATrainingPosCal] consider 1 rank data
3067 11:36:46.749631 u2DelayCellTimex100 = 270/100 ps
3068 11:36:46.752893 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3069 11:36:46.759435 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 11:36:46.763022 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3071 11:36:46.765904 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 11:36:46.769318 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3073 11:36:46.772700 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3074 11:36:46.772777
3075 11:36:46.776058 CA PerBit enable=1, Macro0, CA PI delay=33
3076 11:36:46.776133
3077 11:36:46.779279 [CBTSetCACLKResult] CA Dly = 33
3078 11:36:46.782610 CS Dly: 4 (0~35)
3079 11:36:46.782685 ==
3080 11:36:46.785842 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 11:36:46.789548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 11:36:46.789623 ==
3083 11:36:46.795742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 11:36:46.799202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 11:36:46.808710 [CA 0] Center 37 (7~68) winsize 62
3086 11:36:46.812387 [CA 1] Center 38 (8~68) winsize 61
3087 11:36:46.815150 [CA 2] Center 35 (5~65) winsize 61
3088 11:36:46.818663 [CA 3] Center 33 (3~64) winsize 62
3089 11:36:46.822187 [CA 4] Center 34 (4~64) winsize 61
3090 11:36:46.825076 [CA 5] Center 33 (4~63) winsize 60
3091 11:36:46.825174
3092 11:36:46.828811 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3093 11:36:46.828886
3094 11:36:46.832289 [CATrainingPosCal] consider 2 rank data
3095 11:36:46.835202 u2DelayCellTimex100 = 270/100 ps
3096 11:36:46.838580 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3097 11:36:46.845080 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3098 11:36:46.848679 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3099 11:36:46.851818 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 11:36:46.854728 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3101 11:36:46.858155 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3102 11:36:46.858230
3103 11:36:46.861414 CA PerBit enable=1, Macro0, CA PI delay=33
3104 11:36:46.861488
3105 11:36:46.864535 [CBTSetCACLKResult] CA Dly = 33
3106 11:36:46.868306 CS Dly: 6 (0~39)
3107 11:36:46.868380
3108 11:36:46.871582 ----->DramcWriteLeveling(PI) begin...
3109 11:36:46.871659 ==
3110 11:36:46.874500 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 11:36:46.877915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 11:36:46.877991 ==
3113 11:36:46.881474 Write leveling (Byte 0): 26 => 26
3114 11:36:46.884844 Write leveling (Byte 1): 27 => 27
3115 11:36:46.887561 DramcWriteLeveling(PI) end<-----
3116 11:36:46.887636
3117 11:36:46.887693 ==
3118 11:36:46.891374 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 11:36:46.894498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 11:36:46.894573 ==
3121 11:36:46.897631 [Gating] SW mode calibration
3122 11:36:46.904093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 11:36:46.910726 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 11:36:46.914027 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3125 11:36:46.920677 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 11:36:46.923857 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 11:36:46.927227 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 11:36:46.933835 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:36:46.936731 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 11:36:46.940356 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3131 11:36:46.947100 0 15 28 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (1 0)
3132 11:36:46.950010 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:36:46.953809 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:36:46.960647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 11:36:46.963339 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 11:36:46.966998 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:36:46.973300 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:36:46.976619 1 0 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
3139 11:36:46.979971 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3140 11:36:46.986192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:36:46.989690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:36:46.993081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:36:46.999690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:36:47.002778 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:36:47.006223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3146 11:36:47.013577 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 11:36:47.016119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:36:47.019626 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 11:36:47.026303 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:36:47.029110 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:36:47.032584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:36:47.039211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:36:47.042590 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:36:47.046116 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:36:47.052566 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:36:47.055530 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:36:47.059400 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:36:47.065681 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:36:47.069069 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:36:47.072280 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:36:47.078860 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:36:47.082239 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 11:36:47.085372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 11:36:47.088894 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:36:47.091922 Total UI for P1: 0, mck2ui 16
3166 11:36:47.095511 best dqsien dly found for B0: ( 1, 3, 26)
3167 11:36:47.099397 Total UI for P1: 0, mck2ui 16
3168 11:36:47.102573 best dqsien dly found for B1: ( 1, 3, 26)
3169 11:36:47.105325 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3170 11:36:47.112087 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3171 11:36:47.112164
3172 11:36:47.115396 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 11:36:47.118730 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3174 11:36:47.121746 [Gating] SW calibration Done
3175 11:36:47.121821 ==
3176 11:36:47.124969 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 11:36:47.128249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 11:36:47.128324 ==
3179 11:36:47.131559 RX Vref Scan: 0
3180 11:36:47.131634
3181 11:36:47.131692 RX Vref 0 -> 0, step: 1
3182 11:36:47.131746
3183 11:36:47.135075 RX Delay -40 -> 252, step: 8
3184 11:36:47.138462 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3185 11:36:47.144612 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3186 11:36:47.148103 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3187 11:36:47.151412 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3188 11:36:47.154689 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3189 11:36:47.157820 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3190 11:36:47.165026 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3191 11:36:47.167688 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3192 11:36:47.170923 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3193 11:36:47.174019 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3194 11:36:47.177514 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3195 11:36:47.183859 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3196 11:36:47.187580 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3197 11:36:47.190719 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3198 11:36:47.194452 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3199 11:36:47.200641 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3200 11:36:47.200715 ==
3201 11:36:47.204239 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 11:36:47.207185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 11:36:47.207261 ==
3204 11:36:47.207320 DQS Delay:
3205 11:36:47.210781 DQS0 = 0, DQS1 = 0
3206 11:36:47.210856 DQM Delay:
3207 11:36:47.214081 DQM0 = 117, DQM1 = 113
3208 11:36:47.214159 DQ Delay:
3209 11:36:47.217036 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3210 11:36:47.220733 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3211 11:36:47.224113 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3212 11:36:47.227051 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3213 11:36:47.230069
3214 11:36:47.230143
3215 11:36:47.230200 ==
3216 11:36:47.233950 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 11:36:47.236949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 11:36:47.237024 ==
3219 11:36:47.237082
3220 11:36:47.237134
3221 11:36:47.240282 TX Vref Scan disable
3222 11:36:47.240357 == TX Byte 0 ==
3223 11:36:47.247120 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3224 11:36:47.250030 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3225 11:36:47.250105 == TX Byte 1 ==
3226 11:36:47.256558 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 11:36:47.259917 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 11:36:47.259992 ==
3229 11:36:47.263138 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 11:36:47.266458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 11:36:47.266533 ==
3232 11:36:47.279242 TX Vref=22, minBit 2, minWin=25, winSum=415
3233 11:36:47.282291 TX Vref=24, minBit 2, minWin=25, winSum=418
3234 11:36:47.285798 TX Vref=26, minBit 0, minWin=26, winSum=424
3235 11:36:47.288838 TX Vref=28, minBit 1, minWin=26, winSum=428
3236 11:36:47.292764 TX Vref=30, minBit 1, minWin=26, winSum=430
3237 11:36:47.298704 TX Vref=32, minBit 11, minWin=25, winSum=427
3238 11:36:47.301905 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3239 11:36:47.301981
3240 11:36:47.305074 Final TX Range 1 Vref 30
3241 11:36:47.305199
3242 11:36:47.305258 ==
3243 11:36:47.308414 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 11:36:47.312235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 11:36:47.315068 ==
3246 11:36:47.315142
3247 11:36:47.315198
3248 11:36:47.315251 TX Vref Scan disable
3249 11:36:47.319075 == TX Byte 0 ==
3250 11:36:47.322324 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3251 11:36:47.328433 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3252 11:36:47.328508 == TX Byte 1 ==
3253 11:36:47.331979 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 11:36:47.338320 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 11:36:47.338396
3256 11:36:47.338455 [DATLAT]
3257 11:36:47.338508 Freq=1200, CH1 RK0
3258 11:36:47.338560
3259 11:36:47.341750 DATLAT Default: 0xd
3260 11:36:47.344941 0, 0xFFFF, sum = 0
3261 11:36:47.345017 1, 0xFFFF, sum = 0
3262 11:36:47.348381 2, 0xFFFF, sum = 0
3263 11:36:47.348457 3, 0xFFFF, sum = 0
3264 11:36:47.351347 4, 0xFFFF, sum = 0
3265 11:36:47.351423 5, 0xFFFF, sum = 0
3266 11:36:47.354814 6, 0xFFFF, sum = 0
3267 11:36:47.354890 7, 0xFFFF, sum = 0
3268 11:36:47.358427 8, 0xFFFF, sum = 0
3269 11:36:47.358503 9, 0xFFFF, sum = 0
3270 11:36:47.361407 10, 0xFFFF, sum = 0
3271 11:36:47.361483 11, 0xFFFF, sum = 0
3272 11:36:47.364523 12, 0x0, sum = 1
3273 11:36:47.364598 13, 0x0, sum = 2
3274 11:36:47.368317 14, 0x0, sum = 3
3275 11:36:47.368393 15, 0x0, sum = 4
3276 11:36:47.371869 best_step = 13
3277 11:36:47.371943
3278 11:36:47.372009 ==
3279 11:36:47.374752 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:36:47.378177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:36:47.378253 ==
3282 11:36:47.381314 RX Vref Scan: 1
3283 11:36:47.381392
3284 11:36:47.381451 Set Vref Range= 32 -> 127
3285 11:36:47.381505
3286 11:36:47.384740 RX Vref 32 -> 127, step: 1
3287 11:36:47.384814
3288 11:36:47.387639 RX Delay -13 -> 252, step: 4
3289 11:36:47.387713
3290 11:36:47.390961 Set Vref, RX VrefLevel [Byte0]: 32
3291 11:36:47.394345 [Byte1]: 32
3292 11:36:47.394420
3293 11:36:47.397700 Set Vref, RX VrefLevel [Byte0]: 33
3294 11:36:47.400942 [Byte1]: 33
3295 11:36:47.405015
3296 11:36:47.405090 Set Vref, RX VrefLevel [Byte0]: 34
3297 11:36:47.408518 [Byte1]: 34
3298 11:36:47.413408
3299 11:36:47.413484 Set Vref, RX VrefLevel [Byte0]: 35
3300 11:36:47.419492 [Byte1]: 35
3301 11:36:47.419566
3302 11:36:47.423337 Set Vref, RX VrefLevel [Byte0]: 36
3303 11:36:47.426036 [Byte1]: 36
3304 11:36:47.426110
3305 11:36:47.429567 Set Vref, RX VrefLevel [Byte0]: 37
3306 11:36:47.432584 [Byte1]: 37
3307 11:36:47.436733
3308 11:36:47.436807 Set Vref, RX VrefLevel [Byte0]: 38
3309 11:36:47.439844 [Byte1]: 38
3310 11:36:47.444981
3311 11:36:47.445079 Set Vref, RX VrefLevel [Byte0]: 39
3312 11:36:47.448072 [Byte1]: 39
3313 11:36:47.452366
3314 11:36:47.452440 Set Vref, RX VrefLevel [Byte0]: 40
3315 11:36:47.455527 [Byte1]: 40
3316 11:36:47.460363
3317 11:36:47.460437 Set Vref, RX VrefLevel [Byte0]: 41
3318 11:36:47.463471 [Byte1]: 41
3319 11:36:47.468386
3320 11:36:47.468464 Set Vref, RX VrefLevel [Byte0]: 42
3321 11:36:47.471697 [Byte1]: 42
3322 11:36:47.476289
3323 11:36:47.476363 Set Vref, RX VrefLevel [Byte0]: 43
3324 11:36:47.479419 [Byte1]: 43
3325 11:36:47.483980
3326 11:36:47.484053 Set Vref, RX VrefLevel [Byte0]: 44
3327 11:36:47.487097 [Byte1]: 44
3328 11:36:47.491988
3329 11:36:47.492061 Set Vref, RX VrefLevel [Byte0]: 45
3330 11:36:47.495286 [Byte1]: 45
3331 11:36:47.499729
3332 11:36:47.499805 Set Vref, RX VrefLevel [Byte0]: 46
3333 11:36:47.503238 [Byte1]: 46
3334 11:36:47.507380
3335 11:36:47.507454 Set Vref, RX VrefLevel [Byte0]: 47
3336 11:36:47.510769 [Byte1]: 47
3337 11:36:47.515459
3338 11:36:47.515532 Set Vref, RX VrefLevel [Byte0]: 48
3339 11:36:47.518632 [Byte1]: 48
3340 11:36:47.523441
3341 11:36:47.523515 Set Vref, RX VrefLevel [Byte0]: 49
3342 11:36:47.526781 [Byte1]: 49
3343 11:36:47.531751
3344 11:36:47.531825 Set Vref, RX VrefLevel [Byte0]: 50
3345 11:36:47.534716 [Byte1]: 50
3346 11:36:47.539469
3347 11:36:47.539548 Set Vref, RX VrefLevel [Byte0]: 51
3348 11:36:47.542227 [Byte1]: 51
3349 11:36:47.546923
3350 11:36:47.546997 Set Vref, RX VrefLevel [Byte0]: 52
3351 11:36:47.550393 [Byte1]: 52
3352 11:36:47.554894
3353 11:36:47.554967 Set Vref, RX VrefLevel [Byte0]: 53
3354 11:36:47.558074 [Byte1]: 53
3355 11:36:47.562525
3356 11:36:47.562598 Set Vref, RX VrefLevel [Byte0]: 54
3357 11:36:47.566017 [Byte1]: 54
3358 11:36:47.570909
3359 11:36:47.570982 Set Vref, RX VrefLevel [Byte0]: 55
3360 11:36:47.573759 [Byte1]: 55
3361 11:36:47.578631
3362 11:36:47.578705 Set Vref, RX VrefLevel [Byte0]: 56
3363 11:36:47.581830 [Byte1]: 56
3364 11:36:47.586411
3365 11:36:47.586485 Set Vref, RX VrefLevel [Byte0]: 57
3366 11:36:47.589454 [Byte1]: 57
3367 11:36:47.594523
3368 11:36:47.594596 Set Vref, RX VrefLevel [Byte0]: 58
3369 11:36:47.597982 [Byte1]: 58
3370 11:36:47.602283
3371 11:36:47.602356 Set Vref, RX VrefLevel [Byte0]: 59
3372 11:36:47.605271 [Byte1]: 59
3373 11:36:47.609765
3374 11:36:47.609839 Set Vref, RX VrefLevel [Byte0]: 60
3375 11:36:47.613600 [Byte1]: 60
3376 11:36:47.617692
3377 11:36:47.617765 Set Vref, RX VrefLevel [Byte0]: 61
3378 11:36:47.621333 [Byte1]: 61
3379 11:36:47.625963
3380 11:36:47.626036 Set Vref, RX VrefLevel [Byte0]: 62
3381 11:36:47.629330 [Byte1]: 62
3382 11:36:47.633605
3383 11:36:47.633679 Set Vref, RX VrefLevel [Byte0]: 63
3384 11:36:47.637047 [Byte1]: 63
3385 11:36:47.642002
3386 11:36:47.642075 Set Vref, RX VrefLevel [Byte0]: 64
3387 11:36:47.644809 [Byte1]: 64
3388 11:36:47.649744
3389 11:36:47.649817 Set Vref, RX VrefLevel [Byte0]: 65
3390 11:36:47.652811 [Byte1]: 65
3391 11:36:47.657337
3392 11:36:47.657412 Set Vref, RX VrefLevel [Byte0]: 66
3393 11:36:47.660607 [Byte1]: 66
3394 11:36:47.665102
3395 11:36:47.665183 Final RX Vref Byte 0 = 51 to rank0
3396 11:36:47.668486 Final RX Vref Byte 1 = 51 to rank0
3397 11:36:47.672197 Final RX Vref Byte 0 = 51 to rank1
3398 11:36:47.675167 Final RX Vref Byte 1 = 51 to rank1==
3399 11:36:47.678129 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 11:36:47.685049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 11:36:47.685171 ==
3402 11:36:47.685260 DQS Delay:
3403 11:36:47.688153 DQS0 = 0, DQS1 = 0
3404 11:36:47.688229 DQM Delay:
3405 11:36:47.688306 DQM0 = 117, DQM1 = 114
3406 11:36:47.691741 DQ Delay:
3407 11:36:47.694704 DQ0 =124, DQ1 =112, DQ2 =108, DQ3 =118
3408 11:36:47.698341 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3409 11:36:47.701657 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3410 11:36:47.704609 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =124
3411 11:36:47.704685
3412 11:36:47.704776
3413 11:36:47.715097 [DQSOSCAuto] RK0, (LSB)MR18= 0xf905, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3414 11:36:47.715175 CH1 RK0: MR19=304, MR18=F905
3415 11:36:47.721389 CH1_RK0: MR19=0x304, MR18=0xF905, DQSOSC=408, MR23=63, INC=39, DEC=26
3416 11:36:47.721464
3417 11:36:47.724333 ----->DramcWriteLeveling(PI) begin...
3418 11:36:47.724409 ==
3419 11:36:47.727673 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 11:36:47.734470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 11:36:47.734546 ==
3422 11:36:47.737834 Write leveling (Byte 0): 24 => 24
3423 11:36:47.740690 Write leveling (Byte 1): 27 => 27
3424 11:36:47.744113 DramcWriteLeveling(PI) end<-----
3425 11:36:47.744187
3426 11:36:47.744245 ==
3427 11:36:47.747509 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 11:36:47.751190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 11:36:47.751265 ==
3430 11:36:47.754431 [Gating] SW mode calibration
3431 11:36:47.760757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3432 11:36:47.767052 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3433 11:36:47.770286 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 11:36:47.774018 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:36:47.780153 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:36:47.783750 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:36:47.786955 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:36:47.793720 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3439 11:36:47.796856 0 15 24 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
3440 11:36:47.800083 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
3441 11:36:47.806767 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 11:36:47.809952 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:36:47.813365 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:36:47.820167 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 11:36:47.823140 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:36:47.827370 1 0 20 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
3447 11:36:47.833730 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3448 11:36:47.836481 1 0 28 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3449 11:36:47.839712 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 11:36:47.846440 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:36:47.849706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:36:47.852619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:36:47.859358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:36:47.862863 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3455 11:36:47.865711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3456 11:36:47.872828 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3457 11:36:47.876280 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 11:36:47.878841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:36:47.885832 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:36:47.888844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:36:47.892561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:36:47.899124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:36:47.902179 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:36:47.905774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:36:47.912286 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:36:47.915199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:36:47.918894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:36:47.925561 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:36:47.928835 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:36:47.931777 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3471 11:36:47.938372 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3472 11:36:47.941629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3473 11:36:47.944757 Total UI for P1: 0, mck2ui 16
3474 11:36:47.948118 best dqsien dly found for B0: ( 1, 3, 22)
3475 11:36:47.951619 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 11:36:47.954951 Total UI for P1: 0, mck2ui 16
3477 11:36:47.957896 best dqsien dly found for B1: ( 1, 3, 26)
3478 11:36:47.961348 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3479 11:36:47.964952 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3480 11:36:47.965026
3481 11:36:47.971438 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3482 11:36:47.974647 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 11:36:47.974721 [Gating] SW calibration Done
3484 11:36:47.977793 ==
3485 11:36:47.981228 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 11:36:47.984285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 11:36:47.984361 ==
3488 11:36:47.984419 RX Vref Scan: 0
3489 11:36:47.984471
3490 11:36:47.988014 RX Vref 0 -> 0, step: 1
3491 11:36:47.988087
3492 11:36:47.990807 RX Delay -40 -> 252, step: 8
3493 11:36:47.994064 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3494 11:36:47.997713 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3495 11:36:48.004656 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3496 11:36:48.007696 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3497 11:36:48.010902 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3498 11:36:48.014186 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3499 11:36:48.017290 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3500 11:36:48.024032 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3501 11:36:48.027267 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3502 11:36:48.030391 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3503 11:36:48.033807 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3504 11:36:48.040537 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3505 11:36:48.043958 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3506 11:36:48.047073 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3507 11:36:48.050297 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3508 11:36:48.054080 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3509 11:36:48.054156 ==
3510 11:36:48.057022 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 11:36:48.063475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 11:36:48.063551 ==
3513 11:36:48.063625 DQS Delay:
3514 11:36:48.066707 DQS0 = 0, DQS1 = 0
3515 11:36:48.066783 DQM Delay:
3516 11:36:48.070288 DQM0 = 117, DQM1 = 114
3517 11:36:48.070363 DQ Delay:
3518 11:36:48.073307 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3519 11:36:48.076502 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =119
3520 11:36:48.079887 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3521 11:36:48.083307 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =123
3522 11:36:48.083383
3523 11:36:48.083458
3524 11:36:48.083527 ==
3525 11:36:48.086281 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 11:36:48.093248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 11:36:48.093324 ==
3528 11:36:48.093399
3529 11:36:48.093469
3530 11:36:48.096467 TX Vref Scan disable
3531 11:36:48.096543 == TX Byte 0 ==
3532 11:36:48.099335 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3533 11:36:48.106236 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3534 11:36:48.106313 == TX Byte 1 ==
3535 11:36:48.109590 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 11:36:48.116104 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 11:36:48.116181 ==
3538 11:36:48.119248 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 11:36:48.122947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 11:36:48.123024 ==
3541 11:36:48.134798 TX Vref=22, minBit 2, minWin=25, winSum=416
3542 11:36:48.138297 TX Vref=24, minBit 1, minWin=26, winSum=423
3543 11:36:48.140996 TX Vref=26, minBit 2, minWin=26, winSum=426
3544 11:36:48.144782 TX Vref=28, minBit 9, minWin=25, winSum=427
3545 11:36:48.147798 TX Vref=30, minBit 7, minWin=26, winSum=430
3546 11:36:48.154659 TX Vref=32, minBit 8, minWin=26, winSum=431
3547 11:36:48.157936 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 32
3548 11:36:48.158012
3549 11:36:48.161453 Final TX Range 1 Vref 32
3550 11:36:48.161576
3551 11:36:48.161637 ==
3552 11:36:48.164203 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:36:48.167929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:36:48.171332 ==
3555 11:36:48.171453
3556 11:36:48.171514
3557 11:36:48.171568 TX Vref Scan disable
3558 11:36:48.174206 == TX Byte 0 ==
3559 11:36:48.177522 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3560 11:36:48.184623 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3561 11:36:48.184760 == TX Byte 1 ==
3562 11:36:48.187272 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 11:36:48.194177 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 11:36:48.194253
3565 11:36:48.194311 [DATLAT]
3566 11:36:48.194365 Freq=1200, CH1 RK1
3567 11:36:48.194417
3568 11:36:48.197599 DATLAT Default: 0xd
3569 11:36:48.200839 0, 0xFFFF, sum = 0
3570 11:36:48.200930 1, 0xFFFF, sum = 0
3571 11:36:48.204265 2, 0xFFFF, sum = 0
3572 11:36:48.204341 3, 0xFFFF, sum = 0
3573 11:36:48.207134 4, 0xFFFF, sum = 0
3574 11:36:48.207210 5, 0xFFFF, sum = 0
3575 11:36:48.210518 6, 0xFFFF, sum = 0
3576 11:36:48.210594 7, 0xFFFF, sum = 0
3577 11:36:48.214034 8, 0xFFFF, sum = 0
3578 11:36:48.214110 9, 0xFFFF, sum = 0
3579 11:36:48.217468 10, 0xFFFF, sum = 0
3580 11:36:48.217545 11, 0xFFFF, sum = 0
3581 11:36:48.221354 12, 0x0, sum = 1
3582 11:36:48.221431 13, 0x0, sum = 2
3583 11:36:48.223733 14, 0x0, sum = 3
3584 11:36:48.223808 15, 0x0, sum = 4
3585 11:36:48.227284 best_step = 13
3586 11:36:48.227359
3587 11:36:48.227416 ==
3588 11:36:48.230736 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 11:36:48.233663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 11:36:48.233738 ==
3591 11:36:48.236795 RX Vref Scan: 0
3592 11:36:48.236870
3593 11:36:48.236928 RX Vref 0 -> 0, step: 1
3594 11:36:48.236982
3595 11:36:48.240505 RX Delay -5 -> 252, step: 4
3596 11:36:48.246759 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3597 11:36:48.250324 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3598 11:36:48.253374 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3599 11:36:48.256680 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3600 11:36:48.260614 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3601 11:36:48.267247 iDelay=195, Bit 5, Center 128 (63 ~ 194) 132
3602 11:36:48.269870 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3603 11:36:48.273666 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3604 11:36:48.276694 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3605 11:36:48.279990 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3606 11:36:48.286519 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3607 11:36:48.290179 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3608 11:36:48.293499 iDelay=195, Bit 12, Center 122 (63 ~ 182) 120
3609 11:36:48.296626 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3610 11:36:48.303192 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3611 11:36:48.306220 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3612 11:36:48.306295 ==
3613 11:36:48.309516 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 11:36:48.313206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 11:36:48.313281 ==
3616 11:36:48.313339 DQS Delay:
3617 11:36:48.316178 DQS0 = 0, DQS1 = 0
3618 11:36:48.316252 DQM Delay:
3619 11:36:48.319336 DQM0 = 116, DQM1 = 114
3620 11:36:48.319410 DQ Delay:
3621 11:36:48.322817 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3622 11:36:48.326288 DQ4 =116, DQ5 =128, DQ6 =124, DQ7 =112
3623 11:36:48.329165 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3624 11:36:48.336534 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3625 11:36:48.336608
3626 11:36:48.336664
3627 11:36:48.342980 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3628 11:36:48.345783 CH1 RK1: MR19=304, MR18=F608
3629 11:36:48.352424 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3630 11:36:48.356048 [RxdqsGatingPostProcess] freq 1200
3631 11:36:48.359425 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 11:36:48.362622 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 11:36:48.365760 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 11:36:48.368884 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 11:36:48.371965 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 11:36:48.375314 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 11:36:48.378578 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 11:36:48.382383 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 11:36:48.385341 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 11:36:48.388481 Pre-setting of DQS Precalculation
3641 11:36:48.392299 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 11:36:48.402023 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 11:36:48.408309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 11:36:48.408383
3645 11:36:48.408439
3646 11:36:48.412702 [Calibration Summary] 2400 Mbps
3647 11:36:48.412776 CH 0, Rank 0
3648 11:36:48.415451 SW Impedance : PASS
3649 11:36:48.418359 DUTY Scan : NO K
3650 11:36:48.418432 ZQ Calibration : PASS
3651 11:36:48.421731 Jitter Meter : NO K
3652 11:36:48.421804 CBT Training : PASS
3653 11:36:48.425345 Write leveling : PASS
3654 11:36:48.428468 RX DQS gating : PASS
3655 11:36:48.428542 RX DQ/DQS(RDDQC) : PASS
3656 11:36:48.431730 TX DQ/DQS : PASS
3657 11:36:48.434955 RX DATLAT : PASS
3658 11:36:48.435029 RX DQ/DQS(Engine): PASS
3659 11:36:48.438100 TX OE : NO K
3660 11:36:48.438174 All Pass.
3661 11:36:48.438231
3662 11:36:48.441546 CH 0, Rank 1
3663 11:36:48.441619 SW Impedance : PASS
3664 11:36:48.444742 DUTY Scan : NO K
3665 11:36:48.447968 ZQ Calibration : PASS
3666 11:36:48.448042 Jitter Meter : NO K
3667 11:36:48.451026 CBT Training : PASS
3668 11:36:48.454693 Write leveling : PASS
3669 11:36:48.454767 RX DQS gating : PASS
3670 11:36:48.457933 RX DQ/DQS(RDDQC) : PASS
3671 11:36:48.461101 TX DQ/DQS : PASS
3672 11:36:48.461215 RX DATLAT : PASS
3673 11:36:48.464411 RX DQ/DQS(Engine): PASS
3674 11:36:48.467810 TX OE : NO K
3675 11:36:48.467884 All Pass.
3676 11:36:48.467940
3677 11:36:48.467993 CH 1, Rank 0
3678 11:36:48.471178 SW Impedance : PASS
3679 11:36:48.474211 DUTY Scan : NO K
3680 11:36:48.474285 ZQ Calibration : PASS
3681 11:36:48.478163 Jitter Meter : NO K
3682 11:36:48.480677 CBT Training : PASS
3683 11:36:48.480751 Write leveling : PASS
3684 11:36:48.484230 RX DQS gating : PASS
3685 11:36:48.487467 RX DQ/DQS(RDDQC) : PASS
3686 11:36:48.487541 TX DQ/DQS : PASS
3687 11:36:48.491071 RX DATLAT : PASS
3688 11:36:48.494076 RX DQ/DQS(Engine): PASS
3689 11:36:48.494149 TX OE : NO K
3690 11:36:48.494206 All Pass.
3691 11:36:48.497696
3692 11:36:48.497769 CH 1, Rank 1
3693 11:36:48.500787 SW Impedance : PASS
3694 11:36:48.500860 DUTY Scan : NO K
3695 11:36:48.503910 ZQ Calibration : PASS
3696 11:36:48.503984 Jitter Meter : NO K
3697 11:36:48.507104 CBT Training : PASS
3698 11:36:48.510611 Write leveling : PASS
3699 11:36:48.510685 RX DQS gating : PASS
3700 11:36:48.513530 RX DQ/DQS(RDDQC) : PASS
3701 11:36:48.517258 TX DQ/DQS : PASS
3702 11:36:48.517332 RX DATLAT : PASS
3703 11:36:48.520303 RX DQ/DQS(Engine): PASS
3704 11:36:48.523764 TX OE : NO K
3705 11:36:48.523839 All Pass.
3706 11:36:48.523895
3707 11:36:48.527082 DramC Write-DBI off
3708 11:36:48.527155 PER_BANK_REFRESH: Hybrid Mode
3709 11:36:48.530244 TX_TRACKING: ON
3710 11:36:48.539825 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 11:36:48.543529 [FAST_K] Save calibration result to emmc
3712 11:36:48.546943 dramc_set_vcore_voltage set vcore to 650000
3713 11:36:48.550007 Read voltage for 600, 5
3714 11:36:48.550081 Vio18 = 0
3715 11:36:48.550138 Vcore = 650000
3716 11:36:48.552945 Vdram = 0
3717 11:36:48.553018 Vddq = 0
3718 11:36:48.553074 Vmddr = 0
3719 11:36:48.560135 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 11:36:48.563140 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 11:36:48.566791 MEM_TYPE=3, freq_sel=19
3722 11:36:48.569877 sv_algorithm_assistance_LP4_1600
3723 11:36:48.572863 ============ PULL DRAM RESETB DOWN ============
3724 11:36:48.576318 ========== PULL DRAM RESETB DOWN end =========
3725 11:36:48.582766 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 11:36:48.585878 ===================================
3727 11:36:48.585952 LPDDR4 DRAM CONFIGURATION
3728 11:36:48.589280 ===================================
3729 11:36:48.592639 EX_ROW_EN[0] = 0x0
3730 11:36:48.596218 EX_ROW_EN[1] = 0x0
3731 11:36:48.596292 LP4Y_EN = 0x0
3732 11:36:48.599637 WORK_FSP = 0x0
3733 11:36:48.599749 WL = 0x2
3734 11:36:48.602639 RL = 0x2
3735 11:36:48.602714 BL = 0x2
3736 11:36:48.605980 RPST = 0x0
3737 11:36:48.606054 RD_PRE = 0x0
3738 11:36:48.609377 WR_PRE = 0x1
3739 11:36:48.609488 WR_PST = 0x0
3740 11:36:48.612561 DBI_WR = 0x0
3741 11:36:48.612634 DBI_RD = 0x0
3742 11:36:48.615805 OTF = 0x1
3743 11:36:48.619017 ===================================
3744 11:36:48.622732 ===================================
3745 11:36:48.622807 ANA top config
3746 11:36:48.625746 ===================================
3747 11:36:48.629165 DLL_ASYNC_EN = 0
3748 11:36:48.632147 ALL_SLAVE_EN = 1
3749 11:36:48.635331 NEW_RANK_MODE = 1
3750 11:36:48.638873 DLL_IDLE_MODE = 1
3751 11:36:48.638946 LP45_APHY_COMB_EN = 1
3752 11:36:48.642137 TX_ODT_DIS = 1
3753 11:36:48.645219 NEW_8X_MODE = 1
3754 11:36:48.649031 ===================================
3755 11:36:48.651945 ===================================
3756 11:36:48.655016 data_rate = 1200
3757 11:36:48.658234 CKR = 1
3758 11:36:48.658312 DQ_P2S_RATIO = 8
3759 11:36:48.661723 ===================================
3760 11:36:48.665083 CA_P2S_RATIO = 8
3761 11:36:48.667940 DQ_CA_OPEN = 0
3762 11:36:48.671496 DQ_SEMI_OPEN = 0
3763 11:36:48.674801 CA_SEMI_OPEN = 0
3764 11:36:48.678170 CA_FULL_RATE = 0
3765 11:36:48.681540 DQ_CKDIV4_EN = 1
3766 11:36:48.681615 CA_CKDIV4_EN = 1
3767 11:36:48.684471 CA_PREDIV_EN = 0
3768 11:36:48.687851 PH8_DLY = 0
3769 11:36:48.691475 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 11:36:48.694525 DQ_AAMCK_DIV = 4
3771 11:36:48.697911 CA_AAMCK_DIV = 4
3772 11:36:48.697986 CA_ADMCK_DIV = 4
3773 11:36:48.701584 DQ_TRACK_CA_EN = 0
3774 11:36:48.704277 CA_PICK = 600
3775 11:36:48.707826 CA_MCKIO = 600
3776 11:36:48.710898 MCKIO_SEMI = 0
3777 11:36:48.714019 PLL_FREQ = 2288
3778 11:36:48.717247 DQ_UI_PI_RATIO = 32
3779 11:36:48.717321 CA_UI_PI_RATIO = 0
3780 11:36:48.721666 ===================================
3781 11:36:48.723931 ===================================
3782 11:36:48.727970 memory_type:LPDDR4
3783 11:36:48.730669 GP_NUM : 10
3784 11:36:48.730744 SRAM_EN : 1
3785 11:36:48.733833 MD32_EN : 0
3786 11:36:48.737491 ===================================
3787 11:36:48.740483 [ANA_INIT] >>>>>>>>>>>>>>
3788 11:36:48.744106 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 11:36:48.747157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 11:36:48.750672 ===================================
3791 11:36:48.753913 data_rate = 1200,PCW = 0X5800
3792 11:36:48.753987 ===================================
3793 11:36:48.760384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 11:36:48.764107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 11:36:48.770476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 11:36:48.773613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 11:36:48.777010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 11:36:48.780749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 11:36:48.783537 [ANA_INIT] flow start
3800 11:36:48.786800 [ANA_INIT] PLL >>>>>>>>
3801 11:36:48.786875 [ANA_INIT] PLL <<<<<<<<
3802 11:36:48.790369 [ANA_INIT] MIDPI >>>>>>>>
3803 11:36:48.793530 [ANA_INIT] MIDPI <<<<<<<<
3804 11:36:48.796546 [ANA_INIT] DLL >>>>>>>>
3805 11:36:48.796621 [ANA_INIT] flow end
3806 11:36:48.799939 ============ LP4 DIFF to SE enter ============
3807 11:36:48.806568 ============ LP4 DIFF to SE exit ============
3808 11:36:48.806643 [ANA_INIT] <<<<<<<<<<<<<
3809 11:36:48.809534 [Flow] Enable top DCM control >>>>>
3810 11:36:48.813011 [Flow] Enable top DCM control <<<<<
3811 11:36:48.816198 Enable DLL master slave shuffle
3812 11:36:48.822837 ==============================================================
3813 11:36:48.822914 Gating Mode config
3814 11:36:48.829431 ==============================================================
3815 11:36:48.832927 Config description:
3816 11:36:48.842131 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 11:36:48.849096 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 11:36:48.852297 SELPH_MODE 0: By rank 1: By Phase
3819 11:36:48.859026 ==============================================================
3820 11:36:48.862356 GAT_TRACK_EN = 1
3821 11:36:48.865523 RX_GATING_MODE = 2
3822 11:36:48.869075 RX_GATING_TRACK_MODE = 2
3823 11:36:48.869173 SELPH_MODE = 1
3824 11:36:48.872109 PICG_EARLY_EN = 1
3825 11:36:48.875247 VALID_LAT_VALUE = 1
3826 11:36:48.881976 ==============================================================
3827 11:36:48.885542 Enter into Gating configuration >>>>
3828 11:36:48.888708 Exit from Gating configuration <<<<
3829 11:36:48.892176 Enter into DVFS_PRE_config >>>>>
3830 11:36:48.902108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 11:36:48.905076 Exit from DVFS_PRE_config <<<<<
3832 11:36:48.908383 Enter into PICG configuration >>>>
3833 11:36:48.911577 Exit from PICG configuration <<<<
3834 11:36:48.915023 [RX_INPUT] configuration >>>>>
3835 11:36:48.917974 [RX_INPUT] configuration <<<<<
3836 11:36:48.921454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 11:36:48.928312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 11:36:48.935103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 11:36:48.941534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 11:36:48.947965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 11:36:48.954317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 11:36:48.957534 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 11:36:48.961482 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 11:36:48.964406 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 11:36:48.971108 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 11:36:48.974615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 11:36:48.977674 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 11:36:48.980816 ===================================
3849 11:36:48.983969 LPDDR4 DRAM CONFIGURATION
3850 11:36:48.987710 ===================================
3851 11:36:48.987785 EX_ROW_EN[0] = 0x0
3852 11:36:48.990442 EX_ROW_EN[1] = 0x0
3853 11:36:48.993791 LP4Y_EN = 0x0
3854 11:36:48.993865 WORK_FSP = 0x0
3855 11:36:48.997017 WL = 0x2
3856 11:36:48.997091 RL = 0x2
3857 11:36:49.000744 BL = 0x2
3858 11:36:49.000818 RPST = 0x0
3859 11:36:49.003959 RD_PRE = 0x0
3860 11:36:49.004034 WR_PRE = 0x1
3861 11:36:49.006815 WR_PST = 0x0
3862 11:36:49.006889 DBI_WR = 0x0
3863 11:36:49.010248 DBI_RD = 0x0
3864 11:36:49.010323 OTF = 0x1
3865 11:36:49.013564 ===================================
3866 11:36:49.017390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 11:36:49.023681 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 11:36:49.026593 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 11:36:49.030049 ===================================
3870 11:36:49.033433 LPDDR4 DRAM CONFIGURATION
3871 11:36:49.036840 ===================================
3872 11:36:49.040083 EX_ROW_EN[0] = 0x10
3873 11:36:49.040158 EX_ROW_EN[1] = 0x0
3874 11:36:49.043346 LP4Y_EN = 0x0
3875 11:36:49.043421 WORK_FSP = 0x0
3876 11:36:49.046595 WL = 0x2
3877 11:36:49.046669 RL = 0x2
3878 11:36:49.050182 BL = 0x2
3879 11:36:49.050256 RPST = 0x0
3880 11:36:49.052985 RD_PRE = 0x0
3881 11:36:49.053059 WR_PRE = 0x1
3882 11:36:49.056525 WR_PST = 0x0
3883 11:36:49.056600 DBI_WR = 0x0
3884 11:36:49.059407 DBI_RD = 0x0
3885 11:36:49.059481 OTF = 0x1
3886 11:36:49.063167 ===================================
3887 11:36:49.069668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 11:36:49.074489 nWR fixed to 30
3889 11:36:49.077872 [ModeRegInit_LP4] CH0 RK0
3890 11:36:49.077946 [ModeRegInit_LP4] CH0 RK1
3891 11:36:49.081098 [ModeRegInit_LP4] CH1 RK0
3892 11:36:49.084333 [ModeRegInit_LP4] CH1 RK1
3893 11:36:49.084407 match AC timing 17
3894 11:36:49.090889 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 11:36:49.094307 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 11:36:49.097142 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 11:36:49.104247 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 11:36:49.107019 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 11:36:49.107094 ==
3900 11:36:49.110537 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 11:36:49.114124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 11:36:49.114199 ==
3903 11:36:49.120639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 11:36:49.126894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3905 11:36:49.130514 [CA 0] Center 36 (6~67) winsize 62
3906 11:36:49.133734 [CA 1] Center 36 (6~66) winsize 61
3907 11:36:49.136678 [CA 2] Center 34 (4~65) winsize 62
3908 11:36:49.140228 [CA 3] Center 34 (4~65) winsize 62
3909 11:36:49.143358 [CA 4] Center 33 (3~64) winsize 62
3910 11:36:49.146950 [CA 5] Center 33 (2~64) winsize 63
3911 11:36:49.147025
3912 11:36:49.149938 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3913 11:36:49.150013
3914 11:36:49.153380 [CATrainingPosCal] consider 1 rank data
3915 11:36:49.156844 u2DelayCellTimex100 = 270/100 ps
3916 11:36:49.159797 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3917 11:36:49.163178 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3918 11:36:49.166783 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3919 11:36:49.173204 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 11:36:49.177047 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3921 11:36:49.179741 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3922 11:36:49.179816
3923 11:36:49.183355 CA PerBit enable=1, Macro0, CA PI delay=33
3924 11:36:49.183429
3925 11:36:49.186673 [CBTSetCACLKResult] CA Dly = 33
3926 11:36:49.186748 CS Dly: 7 (0~38)
3927 11:36:49.186804 ==
3928 11:36:49.189589 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 11:36:49.196014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 11:36:49.196089 ==
3931 11:36:49.199820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 11:36:49.206153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 11:36:49.209771 [CA 0] Center 36 (6~67) winsize 62
3934 11:36:49.213436 [CA 1] Center 36 (6~67) winsize 62
3935 11:36:49.216139 [CA 2] Center 34 (4~65) winsize 62
3936 11:36:49.219441 [CA 3] Center 34 (4~65) winsize 62
3937 11:36:49.223191 [CA 4] Center 34 (3~65) winsize 63
3938 11:36:49.226504 [CA 5] Center 34 (3~65) winsize 63
3939 11:36:49.226578
3940 11:36:49.229291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 11:36:49.229367
3942 11:36:49.232892 [CATrainingPosCal] consider 2 rank data
3943 11:36:49.235729 u2DelayCellTimex100 = 270/100 ps
3944 11:36:49.239269 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 11:36:49.245638 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 11:36:49.248809 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 11:36:49.253013 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 11:36:49.255813 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 11:36:49.258791 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 11:36:49.258866
3951 11:36:49.262700 CA PerBit enable=1, Macro0, CA PI delay=33
3952 11:36:49.262775
3953 11:36:49.266338 [CBTSetCACLKResult] CA Dly = 33
3954 11:36:49.268887 CS Dly: 6 (0~37)
3955 11:36:49.268961
3956 11:36:49.272513 ----->DramcWriteLeveling(PI) begin...
3957 11:36:49.272589 ==
3958 11:36:49.275393 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 11:36:49.278889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 11:36:49.278963 ==
3961 11:36:49.281841 Write leveling (Byte 0): 33 => 33
3962 11:36:49.285320 Write leveling (Byte 1): 29 => 29
3963 11:36:49.288681 DramcWriteLeveling(PI) end<-----
3964 11:36:49.288754
3965 11:36:49.288811 ==
3966 11:36:49.292190 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 11:36:49.295675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 11:36:49.295749 ==
3969 11:36:49.298834 [Gating] SW mode calibration
3970 11:36:49.305167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 11:36:49.312009 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 11:36:49.315034 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 11:36:49.318589 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 11:36:49.325219 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 11:36:49.328085 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
3976 11:36:49.331502 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (0 0) (0 0)
3977 11:36:49.338168 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 11:36:49.341474 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:36:49.344849 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:36:49.351542 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:36:49.354994 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:36:49.358159 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:36:49.364537 0 10 12 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
3984 11:36:49.367652 0 10 16 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
3985 11:36:49.371419 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:36:49.377899 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:36:49.381101 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:36:49.384222 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:36:49.390734 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:36:49.394399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:36:49.397451 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3992 11:36:49.404074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 11:36:49.407586 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:36:49.410772 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:36:49.417091 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:36:49.420345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:36:49.423619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:36:49.430578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:36:49.433344 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:36:49.436874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:36:49.443871 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:36:49.447098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:36:49.450020 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:36:49.456710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:36:49.460346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:36:49.463562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:36:49.469868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4008 11:36:49.473167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4009 11:36:49.476793 Total UI for P1: 0, mck2ui 16
4010 11:36:49.479547 best dqsien dly found for B0: ( 0, 13, 12)
4011 11:36:49.483255 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 11:36:49.486118 Total UI for P1: 0, mck2ui 16
4013 11:36:49.489663 best dqsien dly found for B1: ( 0, 13, 18)
4014 11:36:49.496267 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4015 11:36:49.499284 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4016 11:36:49.499357
4017 11:36:49.502873 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4018 11:36:49.505764 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4019 11:36:49.509079 [Gating] SW calibration Done
4020 11:36:49.509188 ==
4021 11:36:49.512808 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 11:36:49.515957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 11:36:49.516032 ==
4024 11:36:49.519124 RX Vref Scan: 0
4025 11:36:49.519197
4026 11:36:49.519254 RX Vref 0 -> 0, step: 1
4027 11:36:49.519307
4028 11:36:49.522530 RX Delay -230 -> 252, step: 16
4029 11:36:49.529385 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4030 11:36:49.532618 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4031 11:36:49.535813 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4032 11:36:49.538920 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4033 11:36:49.542389 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4034 11:36:49.549115 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4035 11:36:49.552445 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4036 11:36:49.555551 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4037 11:36:49.559059 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4038 11:36:49.565585 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4039 11:36:49.568412 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4040 11:36:49.571745 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4041 11:36:49.575420 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4042 11:36:49.581534 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4043 11:36:49.584928 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4044 11:36:49.588386 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4045 11:36:49.588462 ==
4046 11:36:49.591411 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 11:36:49.594847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:36:49.598535 ==
4049 11:36:49.598610 DQS Delay:
4050 11:36:49.598685 DQS0 = 0, DQS1 = 0
4051 11:36:49.601663 DQM Delay:
4052 11:36:49.601739 DQM0 = 45, DQM1 = 35
4053 11:36:49.605030 DQ Delay:
4054 11:36:49.607863 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4055 11:36:49.607939 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4056 11:36:49.611825 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4057 11:36:49.618146 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4058 11:36:49.618221
4059 11:36:49.618295
4060 11:36:49.618365 ==
4061 11:36:49.621464 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 11:36:49.624475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 11:36:49.624551 ==
4064 11:36:49.624627
4065 11:36:49.624697
4066 11:36:49.627837 TX Vref Scan disable
4067 11:36:49.627913 == TX Byte 0 ==
4068 11:36:49.634131 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4069 11:36:49.638211 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4070 11:36:49.638287 == TX Byte 1 ==
4071 11:36:49.644155 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4072 11:36:49.647567 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4073 11:36:49.647643 ==
4074 11:36:49.651239 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 11:36:49.654031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 11:36:49.654108 ==
4077 11:36:49.657255
4078 11:36:49.657331
4079 11:36:49.657405 TX Vref Scan disable
4080 11:36:49.661159 == TX Byte 0 ==
4081 11:36:49.664123 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4082 11:36:49.671197 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4083 11:36:49.671274 == TX Byte 1 ==
4084 11:36:49.673993 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4085 11:36:49.680700 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4086 11:36:49.680777
4087 11:36:49.680851 [DATLAT]
4088 11:36:49.680939 Freq=600, CH0 RK0
4089 11:36:49.681026
4090 11:36:49.684083 DATLAT Default: 0x9
4091 11:36:49.684159 0, 0xFFFF, sum = 0
4092 11:36:49.687687 1, 0xFFFF, sum = 0
4093 11:36:49.690969 2, 0xFFFF, sum = 0
4094 11:36:49.691046 3, 0xFFFF, sum = 0
4095 11:36:49.694347 4, 0xFFFF, sum = 0
4096 11:36:49.694424 5, 0xFFFF, sum = 0
4097 11:36:49.697417 6, 0xFFFF, sum = 0
4098 11:36:49.697494 7, 0xFFFF, sum = 0
4099 11:36:49.701175 8, 0x0, sum = 1
4100 11:36:49.701252 9, 0x0, sum = 2
4101 11:36:49.703995 10, 0x0, sum = 3
4102 11:36:49.704072 11, 0x0, sum = 4
4103 11:36:49.704148 best_step = 9
4104 11:36:49.704217
4105 11:36:49.707197 ==
4106 11:36:49.710476 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 11:36:49.714301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 11:36:49.714378 ==
4109 11:36:49.714454 RX Vref Scan: 1
4110 11:36:49.714523
4111 11:36:49.717274 RX Vref 0 -> 0, step: 1
4112 11:36:49.717350
4113 11:36:49.720408 RX Delay -179 -> 252, step: 8
4114 11:36:49.720484
4115 11:36:49.723781 Set Vref, RX VrefLevel [Byte0]: 55
4116 11:36:49.727200 [Byte1]: 50
4117 11:36:49.727277
4118 11:36:49.730428 Final RX Vref Byte 0 = 55 to rank0
4119 11:36:49.733344 Final RX Vref Byte 1 = 50 to rank0
4120 11:36:49.737382 Final RX Vref Byte 0 = 55 to rank1
4121 11:36:49.740133 Final RX Vref Byte 1 = 50 to rank1==
4122 11:36:49.743714 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:36:49.746689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:36:49.750196 ==
4125 11:36:49.750272 DQS Delay:
4126 11:36:49.750348 DQS0 = 0, DQS1 = 0
4127 11:36:49.753867 DQM Delay:
4128 11:36:49.753943 DQM0 = 44, DQM1 = 37
4129 11:36:49.756954 DQ Delay:
4130 11:36:49.757029 DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =40
4131 11:36:49.759927 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4132 11:36:49.763203 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4133 11:36:49.766733 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4134 11:36:49.770352
4135 11:36:49.770427
4136 11:36:49.776912 [DQSOSCAuto] RK0, (LSB)MR18= 0x4942, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4137 11:36:49.780206 CH0 RK0: MR19=808, MR18=4942
4138 11:36:49.786615 CH0_RK0: MR19=0x808, MR18=0x4942, DQSOSC=396, MR23=63, INC=167, DEC=111
4139 11:36:49.786690
4140 11:36:49.789460 ----->DramcWriteLeveling(PI) begin...
4141 11:36:49.789536 ==
4142 11:36:49.792761 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 11:36:49.796225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 11:36:49.796300 ==
4145 11:36:49.800056 Write leveling (Byte 0): 35 => 35
4146 11:36:49.802697 Write leveling (Byte 1): 32 => 32
4147 11:36:49.806091 DramcWriteLeveling(PI) end<-----
4148 11:36:49.806166
4149 11:36:49.806224 ==
4150 11:36:49.809318 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 11:36:49.812818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:36:49.812916 ==
4153 11:36:49.816632 [Gating] SW mode calibration
4154 11:36:49.822748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4155 11:36:49.828946 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4156 11:36:49.832386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 11:36:49.839079 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 11:36:49.842187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 11:36:49.845763 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
4160 11:36:49.852018 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
4161 11:36:49.855291 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 11:36:49.858810 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:36:49.865588 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:36:49.868541 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:36:49.872231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:36:49.878914 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:36:49.882321 0 10 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
4168 11:36:49.884991 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4169 11:36:49.891840 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 11:36:49.895090 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:36:49.898445 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:36:49.905021 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:36:49.907959 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:36:49.911882 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:36:49.917910 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4176 11:36:49.921096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 11:36:49.924356 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:36:49.931370 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:36:49.934847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:36:49.938219 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:36:49.944253 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:36:49.947938 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:36:49.951106 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:36:49.957779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:36:49.961045 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:36:49.964474 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:36:49.970791 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:36:49.974423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:36:49.977310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:36:49.983748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:36:49.987515 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4192 11:36:49.990784 Total UI for P1: 0, mck2ui 16
4193 11:36:49.994242 best dqsien dly found for B0: ( 0, 13, 10)
4194 11:36:49.997275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4195 11:36:50.004057 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 11:36:50.004133 Total UI for P1: 0, mck2ui 16
4197 11:36:50.010637 best dqsien dly found for B1: ( 0, 13, 14)
4198 11:36:50.013515 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4199 11:36:50.017748 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 11:36:50.017823
4201 11:36:50.019994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4202 11:36:50.023341 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 11:36:50.026934 [Gating] SW calibration Done
4204 11:36:50.027010 ==
4205 11:36:50.030230 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 11:36:50.033109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:36:50.033244 ==
4208 11:36:50.037187 RX Vref Scan: 0
4209 11:36:50.037285
4210 11:36:50.039763 RX Vref 0 -> 0, step: 1
4211 11:36:50.039838
4212 11:36:50.039895 RX Delay -230 -> 252, step: 16
4213 11:36:50.046203 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4214 11:36:50.049490 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4215 11:36:50.052762 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4216 11:36:50.056285 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4217 11:36:50.062760 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4218 11:36:50.066428 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 11:36:50.069590 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 11:36:50.072643 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 11:36:50.079147 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4222 11:36:50.082564 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4223 11:36:50.086193 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4224 11:36:50.089575 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4225 11:36:50.095677 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4226 11:36:50.099171 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4227 11:36:50.102270 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4228 11:36:50.105334 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4229 11:36:50.105409 ==
4230 11:36:50.109015 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 11:36:50.115696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 11:36:50.115772 ==
4233 11:36:50.115831 DQS Delay:
4234 11:36:50.118643 DQS0 = 0, DQS1 = 0
4235 11:36:50.118720 DQM Delay:
4236 11:36:50.121678 DQM0 = 45, DQM1 = 35
4237 11:36:50.121752 DQ Delay:
4238 11:36:50.125090 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4239 11:36:50.128673 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4240 11:36:50.131476 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4241 11:36:50.134784 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4242 11:36:50.134859
4243 11:36:50.134916
4244 11:36:50.134968 ==
4245 11:36:50.138294 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:36:50.141555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:36:50.141639 ==
4248 11:36:50.141699
4249 11:36:50.141752
4250 11:36:50.145035 TX Vref Scan disable
4251 11:36:50.148289 == TX Byte 0 ==
4252 11:36:50.151611 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 11:36:50.155036 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 11:36:50.158224 == TX Byte 1 ==
4255 11:36:50.161425 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4256 11:36:50.164807 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4257 11:36:50.164883 ==
4258 11:36:50.168280 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:36:50.174549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:36:50.174624 ==
4261 11:36:50.174680
4262 11:36:50.174732
4263 11:36:50.174782 TX Vref Scan disable
4264 11:36:50.179351 == TX Byte 0 ==
4265 11:36:50.182257 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 11:36:50.188673 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 11:36:50.188748 == TX Byte 1 ==
4268 11:36:50.192447 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4269 11:36:50.198585 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4270 11:36:50.198660
4271 11:36:50.198717 [DATLAT]
4272 11:36:50.198770 Freq=600, CH0 RK1
4273 11:36:50.198821
4274 11:36:50.202120 DATLAT Default: 0x9
4275 11:36:50.202194 0, 0xFFFF, sum = 0
4276 11:36:50.205113 1, 0xFFFF, sum = 0
4277 11:36:50.208620 2, 0xFFFF, sum = 0
4278 11:36:50.208696 3, 0xFFFF, sum = 0
4279 11:36:50.212171 4, 0xFFFF, sum = 0
4280 11:36:50.212247 5, 0xFFFF, sum = 0
4281 11:36:50.215044 6, 0xFFFF, sum = 0
4282 11:36:50.215120 7, 0xFFFF, sum = 0
4283 11:36:50.218542 8, 0x0, sum = 1
4284 11:36:50.218618 9, 0x0, sum = 2
4285 11:36:50.222039 10, 0x0, sum = 3
4286 11:36:50.222114 11, 0x0, sum = 4
4287 11:36:50.222174 best_step = 9
4288 11:36:50.222227
4289 11:36:50.225263 ==
4290 11:36:50.228625 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:36:50.231835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:36:50.231910 ==
4293 11:36:50.231969 RX Vref Scan: 0
4294 11:36:50.232022
4295 11:36:50.234943 RX Vref 0 -> 0, step: 1
4296 11:36:50.235018
4297 11:36:50.238438 RX Delay -195 -> 252, step: 8
4298 11:36:50.245089 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4299 11:36:50.247842 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4300 11:36:50.251384 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4301 11:36:50.254577 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4302 11:36:50.258026 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4303 11:36:50.264604 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4304 11:36:50.267689 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4305 11:36:50.270861 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4306 11:36:50.274446 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4307 11:36:50.281060 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4308 11:36:50.284170 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4309 11:36:50.287812 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4310 11:36:50.290974 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4311 11:36:50.297470 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4312 11:36:50.300628 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4313 11:36:50.304124 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4314 11:36:50.304198 ==
4315 11:36:50.307643 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:36:50.310508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:36:50.313794 ==
4318 11:36:50.313908 DQS Delay:
4319 11:36:50.313965 DQS0 = 0, DQS1 = 0
4320 11:36:50.317102 DQM Delay:
4321 11:36:50.317225 DQM0 = 44, DQM1 = 37
4322 11:36:50.320168 DQ Delay:
4323 11:36:50.323717 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4324 11:36:50.326710 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4325 11:36:50.329970 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4326 11:36:50.333391 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4327 11:36:50.333465
4328 11:36:50.333522
4329 11:36:50.340260 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4330 11:36:50.343257 CH0 RK1: MR19=808, MR18=3F3B
4331 11:36:50.350035 CH0_RK1: MR19=0x808, MR18=0x3F3B, DQSOSC=397, MR23=63, INC=166, DEC=110
4332 11:36:50.353690 [RxdqsGatingPostProcess] freq 600
4333 11:36:50.356873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 11:36:50.359651 Pre-setting of DQS Precalculation
4335 11:36:50.366468 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 11:36:50.366549 ==
4337 11:36:50.369841 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 11:36:50.372975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:36:50.373069 ==
4340 11:36:50.380283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 11:36:50.386312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4342 11:36:50.389673 [CA 0] Center 35 (5~66) winsize 62
4343 11:36:50.393030 [CA 1] Center 36 (6~66) winsize 61
4344 11:36:50.396012 [CA 2] Center 34 (4~65) winsize 62
4345 11:36:50.399543 [CA 3] Center 34 (4~65) winsize 62
4346 11:36:50.402870 [CA 4] Center 34 (4~65) winsize 62
4347 11:36:50.406128 [CA 5] Center 34 (3~65) winsize 63
4348 11:36:50.406202
4349 11:36:50.409128 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4350 11:36:50.409221
4351 11:36:50.412426 [CATrainingPosCal] consider 1 rank data
4352 11:36:50.416059 u2DelayCellTimex100 = 270/100 ps
4353 11:36:50.419319 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4354 11:36:50.422325 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4355 11:36:50.425795 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 11:36:50.429259 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 11:36:50.432090 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 11:36:50.435548 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4359 11:36:50.435621
4360 11:36:50.442343 CA PerBit enable=1, Macro0, CA PI delay=34
4361 11:36:50.442418
4362 11:36:50.445508 [CBTSetCACLKResult] CA Dly = 34
4363 11:36:50.445582 CS Dly: 3 (0~34)
4364 11:36:50.445640 ==
4365 11:36:50.448695 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 11:36:50.452193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 11:36:50.452269 ==
4368 11:36:50.458685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 11:36:50.465153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4370 11:36:50.468574 [CA 0] Center 35 (5~66) winsize 62
4371 11:36:50.471680 [CA 1] Center 36 (6~66) winsize 61
4372 11:36:50.475167 [CA 2] Center 34 (4~65) winsize 62
4373 11:36:50.478508 [CA 3] Center 34 (3~65) winsize 63
4374 11:36:50.481538 [CA 4] Center 34 (4~65) winsize 62
4375 11:36:50.484988 [CA 5] Center 33 (3~64) winsize 62
4376 11:36:50.485085
4377 11:36:50.488428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4378 11:36:50.488502
4379 11:36:50.491802 [CATrainingPosCal] consider 2 rank data
4380 11:36:50.494651 u2DelayCellTimex100 = 270/100 ps
4381 11:36:50.498339 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 11:36:50.501257 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4383 11:36:50.504704 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 11:36:50.511272 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 11:36:50.515026 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 11:36:50.518039 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 11:36:50.518132
4388 11:36:50.521384 CA PerBit enable=1, Macro0, CA PI delay=33
4389 11:36:50.521460
4390 11:36:50.524657 [CBTSetCACLKResult] CA Dly = 33
4391 11:36:50.524732 CS Dly: 4 (0~37)
4392 11:36:50.524790
4393 11:36:50.528023 ----->DramcWriteLeveling(PI) begin...
4394 11:36:50.528099 ==
4395 11:36:50.530975 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:36:50.538127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:36:50.538208 ==
4398 11:36:50.540724 Write leveling (Byte 0): 26 => 26
4399 11:36:50.544485 Write leveling (Byte 1): 29 => 29
4400 11:36:50.547863 DramcWriteLeveling(PI) end<-----
4401 11:36:50.547937
4402 11:36:50.547995 ==
4403 11:36:50.550593 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:36:50.554182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:36:50.554258 ==
4406 11:36:50.557791 [Gating] SW mode calibration
4407 11:36:50.563840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 11:36:50.570535 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 11:36:50.573931 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 11:36:50.577587 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 11:36:50.580358 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 11:36:50.587055 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (0 1) (1 0)
4413 11:36:50.590988 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:36:50.593816 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:36:50.600880 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:36:50.604114 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:36:50.607368 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:36:50.613353 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:36:50.617439 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:36:50.619967 0 10 12 | B1->B0 | 2e2e 3535 | 0 0 | (1 1) (0 0)
4421 11:36:50.626740 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:36:50.630172 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:36:50.636304 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:36:50.639924 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:36:50.643018 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:36:50.649586 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:36:50.652931 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:36:50.656475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4429 11:36:50.663171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:36:50.666263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:36:50.669531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:36:50.672930 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:36:50.679405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:36:50.682951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:36:50.686272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:36:50.692641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:36:50.695968 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:36:50.698988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:36:50.705830 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:36:50.709651 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:36:50.712693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:36:50.719286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:36:50.722493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:36:50.728766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 11:36:50.728948 Total UI for P1: 0, mck2ui 16
4446 11:36:50.732083 best dqsien dly found for B0: ( 0, 13, 10)
4447 11:36:50.735223 Total UI for P1: 0, mck2ui 16
4448 11:36:50.738942 best dqsien dly found for B1: ( 0, 13, 10)
4449 11:36:50.745525 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4450 11:36:50.748785 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4451 11:36:50.748854
4452 11:36:50.751631 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4453 11:36:50.755119 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4454 11:36:50.758994 [Gating] SW calibration Done
4455 11:36:50.759060 ==
4456 11:36:50.761883 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 11:36:50.765053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 11:36:50.765120 ==
4459 11:36:50.768340 RX Vref Scan: 0
4460 11:36:50.768404
4461 11:36:50.768458 RX Vref 0 -> 0, step: 1
4462 11:36:50.768509
4463 11:36:50.771578 RX Delay -230 -> 252, step: 16
4464 11:36:50.777947 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4465 11:36:50.781103 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4466 11:36:50.785045 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4467 11:36:50.788007 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4468 11:36:50.794558 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4469 11:36:50.797531 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4470 11:36:50.801351 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4471 11:36:50.804286 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4472 11:36:50.807725 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4473 11:36:50.813947 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4474 11:36:50.817986 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4475 11:36:50.820755 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4476 11:36:50.824377 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4477 11:36:50.830903 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4478 11:36:50.834102 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4479 11:36:50.837473 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4480 11:36:50.837612 ==
4481 11:36:50.840781 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 11:36:50.847306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 11:36:50.847489 ==
4484 11:36:50.847594 DQS Delay:
4485 11:36:50.850636 DQS0 = 0, DQS1 = 0
4486 11:36:50.850762 DQM Delay:
4487 11:36:50.850890 DQM0 = 45, DQM1 = 39
4488 11:36:50.853656 DQ Delay:
4489 11:36:50.857129 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4490 11:36:50.860676 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4491 11:36:50.863570 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4492 11:36:50.867181 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4493 11:36:50.867449
4494 11:36:50.867635
4495 11:36:50.867798 ==
4496 11:36:50.870826 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 11:36:50.873489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 11:36:50.873764 ==
4499 11:36:50.873974
4500 11:36:50.874167
4501 11:36:50.877261 TX Vref Scan disable
4502 11:36:50.877614 == TX Byte 0 ==
4503 11:36:50.883621 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4504 11:36:50.886973 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4505 11:36:50.890751 == TX Byte 1 ==
4506 11:36:50.893513 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4507 11:36:50.896806 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4508 11:36:50.897243 ==
4509 11:36:50.899999 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 11:36:50.903755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 11:36:50.906730 ==
4512 11:36:50.907115
4513 11:36:50.907409
4514 11:36:50.907680 TX Vref Scan disable
4515 11:36:50.910533 == TX Byte 0 ==
4516 11:36:50.913817 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4517 11:36:50.920872 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4518 11:36:50.921398 == TX Byte 1 ==
4519 11:36:50.923756 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 11:36:50.930785 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 11:36:50.931241
4522 11:36:50.931538 [DATLAT]
4523 11:36:50.931962 Freq=600, CH1 RK0
4524 11:36:50.932263
4525 11:36:50.933815 DATLAT Default: 0x9
4526 11:36:50.937255 0, 0xFFFF, sum = 0
4527 11:36:50.937789 1, 0xFFFF, sum = 0
4528 11:36:50.940639 2, 0xFFFF, sum = 0
4529 11:36:50.941238 3, 0xFFFF, sum = 0
4530 11:36:50.943651 4, 0xFFFF, sum = 0
4531 11:36:50.944040 5, 0xFFFF, sum = 0
4532 11:36:50.946868 6, 0xFFFF, sum = 0
4533 11:36:50.947261 7, 0xFFFF, sum = 0
4534 11:36:50.950257 8, 0x0, sum = 1
4535 11:36:50.950656 9, 0x0, sum = 2
4536 11:36:50.953683 10, 0x0, sum = 3
4537 11:36:50.954077 11, 0x0, sum = 4
4538 11:36:50.954380 best_step = 9
4539 11:36:50.956852
4540 11:36:50.957263 ==
4541 11:36:50.959947 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:36:50.963289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:36:50.963670 ==
4544 11:36:50.963968 RX Vref Scan: 1
4545 11:36:50.964243
4546 11:36:50.967170 RX Vref 0 -> 0, step: 1
4547 11:36:50.967625
4548 11:36:50.969840 RX Delay -179 -> 252, step: 8
4549 11:36:50.970220
4550 11:36:50.973182 Set Vref, RX VrefLevel [Byte0]: 51
4551 11:36:50.976150 [Byte1]: 51
4552 11:36:50.979531
4553 11:36:50.979986 Final RX Vref Byte 0 = 51 to rank0
4554 11:36:50.982694 Final RX Vref Byte 1 = 51 to rank0
4555 11:36:50.986309 Final RX Vref Byte 0 = 51 to rank1
4556 11:36:50.989591 Final RX Vref Byte 1 = 51 to rank1==
4557 11:36:50.992810 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 11:36:50.999112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 11:36:50.999500 ==
4560 11:36:50.999794 DQS Delay:
4561 11:36:51.000064 DQS0 = 0, DQS1 = 0
4562 11:36:51.002558 DQM Delay:
4563 11:36:51.002940 DQM0 = 44, DQM1 = 36
4564 11:36:51.005985 DQ Delay:
4565 11:36:51.009165 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4566 11:36:51.012359 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =36
4567 11:36:51.015628 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4568 11:36:51.019259 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4569 11:36:51.019638
4570 11:36:51.019929
4571 11:36:51.025657 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4572 11:36:51.029007 CH1 RK0: MR19=808, MR18=2C46
4573 11:36:51.035331 CH1_RK0: MR19=0x808, MR18=0x2C46, DQSOSC=396, MR23=63, INC=167, DEC=111
4574 11:36:51.035758
4575 11:36:51.038535 ----->DramcWriteLeveling(PI) begin...
4576 11:36:51.038926 ==
4577 11:36:51.042172 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 11:36:51.044891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 11:36:51.045330 ==
4580 11:36:51.048508 Write leveling (Byte 0): 29 => 29
4581 11:36:51.051706 Write leveling (Byte 1): 29 => 29
4582 11:36:51.055176 DramcWriteLeveling(PI) end<-----
4583 11:36:51.055624
4584 11:36:51.055966 ==
4585 11:36:51.058230 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 11:36:51.065112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:36:51.065538 ==
4588 11:36:51.065837 [Gating] SW mode calibration
4589 11:36:51.075122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4590 11:36:51.078050 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4591 11:36:51.081801 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 11:36:51.088119 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 11:36:51.091071 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4594 11:36:51.097808 0 9 12 | B1->B0 | 3131 2929 | 0 0 | (0 1) (0 0)
4595 11:36:51.100902 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 11:36:51.104937 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 11:36:51.110717 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:36:51.113961 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:36:51.117061 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:36:51.123935 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:36:51.127167 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4602 11:36:51.130278 0 10 12 | B1->B0 | 3535 4545 | 0 0 | (1 1) (0 0)
4603 11:36:51.137110 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 11:36:51.140174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:36:51.143752 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:36:51.150112 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:36:51.153481 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:36:51.157209 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:36:51.163239 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:36:51.166762 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4611 11:36:51.170197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 11:36:51.176480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:36:51.180166 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:36:51.182896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:36:51.189557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:36:51.192917 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:36:51.196055 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:36:51.202512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:36:51.206009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:36:51.209606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:36:51.215521 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:36:51.218986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:36:51.222519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:36:51.228853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:36:51.232477 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4626 11:36:51.236039 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 11:36:51.238799 Total UI for P1: 0, mck2ui 16
4628 11:36:51.242277 best dqsien dly found for B0: ( 0, 13, 8)
4629 11:36:51.245193 Total UI for P1: 0, mck2ui 16
4630 11:36:51.248884 best dqsien dly found for B1: ( 0, 13, 10)
4631 11:36:51.252205 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4632 11:36:51.254967 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4633 11:36:51.258520
4634 11:36:51.261561 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4635 11:36:51.265622 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4636 11:36:51.268633 [Gating] SW calibration Done
4637 11:36:51.269015 ==
4638 11:36:51.271515 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 11:36:51.274631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 11:36:51.275020 ==
4641 11:36:51.275315 RX Vref Scan: 0
4642 11:36:51.277838
4643 11:36:51.278222 RX Vref 0 -> 0, step: 1
4644 11:36:51.278520
4645 11:36:51.282092 RX Delay -230 -> 252, step: 16
4646 11:36:51.284829 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4647 11:36:51.291748 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4648 11:36:51.294953 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4649 11:36:51.298089 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4650 11:36:51.301273 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4651 11:36:51.307804 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4652 11:36:51.311051 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4653 11:36:51.314182 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4654 11:36:51.317607 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4655 11:36:51.321247 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4656 11:36:51.327752 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4657 11:36:51.330731 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4658 11:36:51.334596 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4659 11:36:51.337609 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4660 11:36:51.344620 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4661 11:36:51.347109 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4662 11:36:51.347498 ==
4663 11:36:51.350894 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 11:36:51.353947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 11:36:51.354332 ==
4666 11:36:51.357614 DQS Delay:
4667 11:36:51.358005 DQS0 = 0, DQS1 = 0
4668 11:36:51.360760 DQM Delay:
4669 11:36:51.361171 DQM0 = 39, DQM1 = 39
4670 11:36:51.361560 DQ Delay:
4671 11:36:51.363631 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4672 11:36:51.366879 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4673 11:36:51.370384 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4674 11:36:51.373677 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4675 11:36:51.374055
4676 11:36:51.374343
4677 11:36:51.376911 ==
4678 11:36:51.380405 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 11:36:51.383884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 11:36:51.384266 ==
4681 11:36:51.384558
4682 11:36:51.384822
4683 11:36:51.387031 TX Vref Scan disable
4684 11:36:51.387410 == TX Byte 0 ==
4685 11:36:51.393571 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4686 11:36:51.396484 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4687 11:36:51.396865 == TX Byte 1 ==
4688 11:36:51.403200 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4689 11:36:51.406978 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4690 11:36:51.407462 ==
4691 11:36:51.409878 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 11:36:51.413661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 11:36:51.414042 ==
4694 11:36:51.414435
4695 11:36:51.414718
4696 11:36:51.416499 TX Vref Scan disable
4697 11:36:51.419640 == TX Byte 0 ==
4698 11:36:51.422942 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 11:36:51.426258 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 11:36:51.429443 == TX Byte 1 ==
4701 11:36:51.432765 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 11:36:51.439041 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 11:36:51.439482
4704 11:36:51.439780 [DATLAT]
4705 11:36:51.440057 Freq=600, CH1 RK1
4706 11:36:51.440319
4707 11:36:51.442379 DATLAT Default: 0x9
4708 11:36:51.442762 0, 0xFFFF, sum = 0
4709 11:36:51.445774 1, 0xFFFF, sum = 0
4710 11:36:51.449513 2, 0xFFFF, sum = 0
4711 11:36:51.449951 3, 0xFFFF, sum = 0
4712 11:36:51.452656 4, 0xFFFF, sum = 0
4713 11:36:51.453048 5, 0xFFFF, sum = 0
4714 11:36:51.455725 6, 0xFFFF, sum = 0
4715 11:36:51.456110 7, 0xFFFF, sum = 0
4716 11:36:51.459393 8, 0x0, sum = 1
4717 11:36:51.459779 9, 0x0, sum = 2
4718 11:36:51.462232 10, 0x0, sum = 3
4719 11:36:51.462619 11, 0x0, sum = 4
4720 11:36:51.462920 best_step = 9
4721 11:36:51.463288
4722 11:36:51.465707 ==
4723 11:36:51.466086 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:36:51.472329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:36:51.472712 ==
4726 11:36:51.473007 RX Vref Scan: 0
4727 11:36:51.473330
4728 11:36:51.475368 RX Vref 0 -> 0, step: 1
4729 11:36:51.475730
4730 11:36:51.478861 RX Delay -179 -> 252, step: 8
4731 11:36:51.485397 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4732 11:36:51.489019 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4733 11:36:51.492220 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4734 11:36:51.495400 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4735 11:36:51.498748 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4736 11:36:51.505519 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4737 11:36:51.508926 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4738 11:36:51.512069 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4739 11:36:51.514947 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4740 11:36:51.522041 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4741 11:36:51.524866 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4742 11:36:51.528398 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4743 11:36:51.531778 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4744 11:36:51.538689 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4745 11:36:51.541316 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4746 11:36:51.544625 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4747 11:36:51.545079 ==
4748 11:36:51.548359 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 11:36:51.551638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 11:36:51.554603 ==
4751 11:36:51.555069 DQS Delay:
4752 11:36:51.555489 DQS0 = 0, DQS1 = 0
4753 11:36:51.557993 DQM Delay:
4754 11:36:51.558376 DQM0 = 39, DQM1 = 38
4755 11:36:51.561259 DQ Delay:
4756 11:36:51.561644 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4757 11:36:51.564703 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4758 11:36:51.568226 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4759 11:36:51.571507 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4760 11:36:51.574499
4761 11:36:51.574882
4762 11:36:51.580811 [DQSOSCAuto] RK1, (LSB)MR18= 0x3358, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4763 11:36:51.584218 CH1 RK1: MR19=808, MR18=3358
4764 11:36:51.590918 CH1_RK1: MR19=0x808, MR18=0x3358, DQSOSC=393, MR23=63, INC=169, DEC=113
4765 11:36:51.593864 [RxdqsGatingPostProcess] freq 600
4766 11:36:51.597257 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 11:36:51.601094 Pre-setting of DQS Precalculation
4768 11:36:51.607200 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 11:36:51.614650 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 11:36:51.620463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 11:36:51.620856
4772 11:36:51.621322
4773 11:36:51.623926 [Calibration Summary] 1200 Mbps
4774 11:36:51.624385 CH 0, Rank 0
4775 11:36:51.627402 SW Impedance : PASS
4776 11:36:51.630934 DUTY Scan : NO K
4777 11:36:51.631313 ZQ Calibration : PASS
4778 11:36:51.633857 Jitter Meter : NO K
4779 11:36:51.637001 CBT Training : PASS
4780 11:36:51.637451 Write leveling : PASS
4781 11:36:51.640011 RX DQS gating : PASS
4782 11:36:51.643860 RX DQ/DQS(RDDQC) : PASS
4783 11:36:51.644237 TX DQ/DQS : PASS
4784 11:36:51.647115 RX DATLAT : PASS
4785 11:36:51.650377 RX DQ/DQS(Engine): PASS
4786 11:36:51.650754 TX OE : NO K
4787 11:36:51.653596 All Pass.
4788 11:36:51.653973
4789 11:36:51.654268 CH 0, Rank 1
4790 11:36:51.656928 SW Impedance : PASS
4791 11:36:51.657348 DUTY Scan : NO K
4792 11:36:51.659863 ZQ Calibration : PASS
4793 11:36:51.663768 Jitter Meter : NO K
4794 11:36:51.664228 CBT Training : PASS
4795 11:36:51.666729 Write leveling : PASS
4796 11:36:51.669670 RX DQS gating : PASS
4797 11:36:51.670049 RX DQ/DQS(RDDQC) : PASS
4798 11:36:51.673515 TX DQ/DQS : PASS
4799 11:36:51.673896 RX DATLAT : PASS
4800 11:36:51.676490 RX DQ/DQS(Engine): PASS
4801 11:36:51.679748 TX OE : NO K
4802 11:36:51.680141 All Pass.
4803 11:36:51.680524
4804 11:36:51.682728 CH 1, Rank 0
4805 11:36:51.683117 SW Impedance : PASS
4806 11:36:51.686447 DUTY Scan : NO K
4807 11:36:51.686827 ZQ Calibration : PASS
4808 11:36:51.689435 Jitter Meter : NO K
4809 11:36:51.692753 CBT Training : PASS
4810 11:36:51.693131 Write leveling : PASS
4811 11:36:51.695830 RX DQS gating : PASS
4812 11:36:51.699550 RX DQ/DQS(RDDQC) : PASS
4813 11:36:51.699940 TX DQ/DQS : PASS
4814 11:36:51.702431 RX DATLAT : PASS
4815 11:36:51.706065 RX DQ/DQS(Engine): PASS
4816 11:36:51.706458 TX OE : NO K
4817 11:36:51.709212 All Pass.
4818 11:36:51.709602
4819 11:36:51.709989 CH 1, Rank 1
4820 11:36:51.712641 SW Impedance : PASS
4821 11:36:51.713029 DUTY Scan : NO K
4822 11:36:51.715821 ZQ Calibration : PASS
4823 11:36:51.718946 Jitter Meter : NO K
4824 11:36:51.719293 CBT Training : PASS
4825 11:36:51.722606 Write leveling : PASS
4826 11:36:51.726052 RX DQS gating : PASS
4827 11:36:51.726508 RX DQ/DQS(RDDQC) : PASS
4828 11:36:51.728788 TX DQ/DQS : PASS
4829 11:36:51.732449 RX DATLAT : PASS
4830 11:36:51.732831 RX DQ/DQS(Engine): PASS
4831 11:36:51.735485 TX OE : NO K
4832 11:36:51.735922 All Pass.
4833 11:36:51.736225
4834 11:36:51.739000 DramC Write-DBI off
4835 11:36:51.742114 PER_BANK_REFRESH: Hybrid Mode
4836 11:36:51.742637 TX_TRACKING: ON
4837 11:36:51.751964 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 11:36:51.755223 [FAST_K] Save calibration result to emmc
4839 11:36:51.758500 dramc_set_vcore_voltage set vcore to 662500
4840 11:36:51.761800 Read voltage for 933, 3
4841 11:36:51.762189 Vio18 = 0
4842 11:36:51.762577 Vcore = 662500
4843 11:36:51.765532 Vdram = 0
4844 11:36:51.766004 Vddq = 0
4845 11:36:51.766394 Vmddr = 0
4846 11:36:51.772524 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 11:36:51.775353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 11:36:51.778998 MEM_TYPE=3, freq_sel=17
4849 11:36:51.781723 sv_algorithm_assistance_LP4_1600
4850 11:36:51.785079 ============ PULL DRAM RESETB DOWN ============
4851 11:36:51.788285 ========== PULL DRAM RESETB DOWN end =========
4852 11:36:51.795310 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 11:36:51.798142 ===================================
4854 11:36:51.801254 LPDDR4 DRAM CONFIGURATION
4855 11:36:51.804895 ===================================
4856 11:36:51.805330 EX_ROW_EN[0] = 0x0
4857 11:36:51.808413 EX_ROW_EN[1] = 0x0
4858 11:36:51.808790 LP4Y_EN = 0x0
4859 11:36:51.811503 WORK_FSP = 0x0
4860 11:36:51.811881 WL = 0x3
4861 11:36:51.814926 RL = 0x3
4862 11:36:51.815304 BL = 0x2
4863 11:36:51.817982 RPST = 0x0
4864 11:36:51.818360 RD_PRE = 0x0
4865 11:36:51.821225 WR_PRE = 0x1
4866 11:36:51.824473 WR_PST = 0x0
4867 11:36:51.824849 DBI_WR = 0x0
4868 11:36:51.828004 DBI_RD = 0x0
4869 11:36:51.828474 OTF = 0x1
4870 11:36:51.831126 ===================================
4871 11:36:51.834817 ===================================
4872 11:36:51.837301 ANA top config
4873 11:36:51.840766 ===================================
4874 11:36:51.841214 DLL_ASYNC_EN = 0
4875 11:36:51.843912 ALL_SLAVE_EN = 1
4876 11:36:51.848088 NEW_RANK_MODE = 1
4877 11:36:51.851000 DLL_IDLE_MODE = 1
4878 11:36:51.851381 LP45_APHY_COMB_EN = 1
4879 11:36:51.853650 TX_ODT_DIS = 1
4880 11:36:51.857375 NEW_8X_MODE = 1
4881 11:36:51.860627 ===================================
4882 11:36:51.863813 ===================================
4883 11:36:51.867249 data_rate = 1866
4884 11:36:51.870499 CKR = 1
4885 11:36:51.874365 DQ_P2S_RATIO = 8
4886 11:36:51.877557 ===================================
4887 11:36:51.878055 CA_P2S_RATIO = 8
4888 11:36:51.880359 DQ_CA_OPEN = 0
4889 11:36:51.883759 DQ_SEMI_OPEN = 0
4890 11:36:51.886666 CA_SEMI_OPEN = 0
4891 11:36:51.890755 CA_FULL_RATE = 0
4892 11:36:51.893584 DQ_CKDIV4_EN = 1
4893 11:36:51.894088 CA_CKDIV4_EN = 1
4894 11:36:51.896936 CA_PREDIV_EN = 0
4895 11:36:51.900201 PH8_DLY = 0
4896 11:36:51.903482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 11:36:51.906628 DQ_AAMCK_DIV = 4
4898 11:36:51.909909 CA_AAMCK_DIV = 4
4899 11:36:51.910289 CA_ADMCK_DIV = 4
4900 11:36:51.913033 DQ_TRACK_CA_EN = 0
4901 11:36:51.916457 CA_PICK = 933
4902 11:36:51.919862 CA_MCKIO = 933
4903 11:36:51.922834 MCKIO_SEMI = 0
4904 11:36:51.926107 PLL_FREQ = 3732
4905 11:36:51.930012 DQ_UI_PI_RATIO = 32
4906 11:36:51.933083 CA_UI_PI_RATIO = 0
4907 11:36:51.936348 ===================================
4908 11:36:51.939538 ===================================
4909 11:36:51.939923 memory_type:LPDDR4
4910 11:36:51.942735 GP_NUM : 10
4911 11:36:51.945884 SRAM_EN : 1
4912 11:36:51.946264 MD32_EN : 0
4913 11:36:51.949437 ===================================
4914 11:36:51.952937 [ANA_INIT] >>>>>>>>>>>>>>
4915 11:36:51.955713 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 11:36:51.959152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 11:36:51.962534 ===================================
4918 11:36:51.965952 data_rate = 1866,PCW = 0X8f00
4919 11:36:51.969691 ===================================
4920 11:36:51.972336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 11:36:51.975814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 11:36:51.982073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 11:36:51.985416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 11:36:51.988678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 11:36:51.995748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 11:36:51.996136 [ANA_INIT] flow start
4927 11:36:51.998952 [ANA_INIT] PLL >>>>>>>>
4928 11:36:52.002108 [ANA_INIT] PLL <<<<<<<<
4929 11:36:52.002487 [ANA_INIT] MIDPI >>>>>>>>
4930 11:36:52.005785 [ANA_INIT] MIDPI <<<<<<<<
4931 11:36:52.008373 [ANA_INIT] DLL >>>>>>>>
4932 11:36:52.008750 [ANA_INIT] flow end
4933 11:36:52.011615 ============ LP4 DIFF to SE enter ============
4934 11:36:52.018647 ============ LP4 DIFF to SE exit ============
4935 11:36:52.019032 [ANA_INIT] <<<<<<<<<<<<<
4936 11:36:52.021801 [Flow] Enable top DCM control >>>>>
4937 11:36:52.025381 [Flow] Enable top DCM control <<<<<
4938 11:36:52.028595 Enable DLL master slave shuffle
4939 11:36:52.034828 ==============================================================
4940 11:36:52.037981 Gating Mode config
4941 11:36:52.041624 ==============================================================
4942 11:36:52.044853 Config description:
4943 11:36:52.054698 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 11:36:52.061851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 11:36:52.064404 SELPH_MODE 0: By rank 1: By Phase
4946 11:36:52.071219 ==============================================================
4947 11:36:52.074768 GAT_TRACK_EN = 1
4948 11:36:52.077877 RX_GATING_MODE = 2
4949 11:36:52.080995 RX_GATING_TRACK_MODE = 2
4950 11:36:52.084371 SELPH_MODE = 1
4951 11:36:52.084763 PICG_EARLY_EN = 1
4952 11:36:52.088036 VALID_LAT_VALUE = 1
4953 11:36:52.094734 ==============================================================
4954 11:36:52.097928 Enter into Gating configuration >>>>
4955 11:36:52.100859 Exit from Gating configuration <<<<
4956 11:36:52.104149 Enter into DVFS_PRE_config >>>>>
4957 11:36:52.114529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 11:36:52.117480 Exit from DVFS_PRE_config <<<<<
4959 11:36:52.120357 Enter into PICG configuration >>>>
4960 11:36:52.124362 Exit from PICG configuration <<<<
4961 11:36:52.126979 [RX_INPUT] configuration >>>>>
4962 11:36:52.130719 [RX_INPUT] configuration <<<<<
4963 11:36:52.137290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 11:36:52.140643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 11:36:52.147173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 11:36:52.153694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 11:36:52.159984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:36:52.167235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:36:52.169921 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 11:36:52.173240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 11:36:52.176478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 11:36:52.182860 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 11:36:52.186192 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 11:36:52.189342 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 11:36:52.192699 ===================================
4976 11:36:52.196385 LPDDR4 DRAM CONFIGURATION
4977 11:36:52.199444 ===================================
4978 11:36:52.202767 EX_ROW_EN[0] = 0x0
4979 11:36:52.203149 EX_ROW_EN[1] = 0x0
4980 11:36:52.206079 LP4Y_EN = 0x0
4981 11:36:52.206457 WORK_FSP = 0x0
4982 11:36:52.209616 WL = 0x3
4983 11:36:52.209993 RL = 0x3
4984 11:36:52.212710 BL = 0x2
4985 11:36:52.213218 RPST = 0x0
4986 11:36:52.216334 RD_PRE = 0x0
4987 11:36:52.216791 WR_PRE = 0x1
4988 11:36:52.219279 WR_PST = 0x0
4989 11:36:52.219657 DBI_WR = 0x0
4990 11:36:52.222714 DBI_RD = 0x0
4991 11:36:52.223170 OTF = 0x1
4992 11:36:52.226408 ===================================
4993 11:36:52.232843 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 11:36:52.235803 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 11:36:52.239326 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 11:36:52.242313 ===================================
4997 11:36:52.245563 LPDDR4 DRAM CONFIGURATION
4998 11:36:52.249008 ===================================
4999 11:36:52.252121 EX_ROW_EN[0] = 0x10
5000 11:36:52.252499 EX_ROW_EN[1] = 0x0
5001 11:36:52.255566 LP4Y_EN = 0x0
5002 11:36:52.255943 WORK_FSP = 0x0
5003 11:36:52.259046 WL = 0x3
5004 11:36:52.259424 RL = 0x3
5005 11:36:52.262002 BL = 0x2
5006 11:36:52.262381 RPST = 0x0
5007 11:36:52.265624 RD_PRE = 0x0
5008 11:36:52.266002 WR_PRE = 0x1
5009 11:36:52.268428 WR_PST = 0x0
5010 11:36:52.268805 DBI_WR = 0x0
5011 11:36:52.271934 DBI_RD = 0x0
5012 11:36:52.272313 OTF = 0x1
5013 11:36:52.275670 ===================================
5014 11:36:52.281806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 11:36:52.286497 nWR fixed to 30
5016 11:36:52.289840 [ModeRegInit_LP4] CH0 RK0
5017 11:36:52.290358 [ModeRegInit_LP4] CH0 RK1
5018 11:36:52.293288 [ModeRegInit_LP4] CH1 RK0
5019 11:36:52.296463 [ModeRegInit_LP4] CH1 RK1
5020 11:36:52.296816 match AC timing 9
5021 11:36:52.303105 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 11:36:52.306090 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 11:36:52.309468 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 11:36:52.315870 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 11:36:52.319024 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 11:36:52.319145 ==
5027 11:36:52.322591 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 11:36:52.325652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 11:36:52.329088 ==
5030 11:36:52.332303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 11:36:52.338812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5032 11:36:52.342409 [CA 0] Center 38 (7~69) winsize 63
5033 11:36:52.345201 [CA 1] Center 37 (7~68) winsize 62
5034 11:36:52.348592 [CA 2] Center 34 (4~65) winsize 62
5035 11:36:52.352004 [CA 3] Center 34 (4~65) winsize 62
5036 11:36:52.355139 [CA 4] Center 33 (3~64) winsize 62
5037 11:36:52.358742 [CA 5] Center 33 (3~63) winsize 61
5038 11:36:52.358835
5039 11:36:52.361764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5040 11:36:52.361866
5041 11:36:52.365320 [CATrainingPosCal] consider 1 rank data
5042 11:36:52.368600 u2DelayCellTimex100 = 270/100 ps
5043 11:36:52.371555 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5044 11:36:52.374707 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5045 11:36:52.381456 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5046 11:36:52.384927 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5047 11:36:52.388391 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5048 11:36:52.391718 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5049 11:36:52.391873
5050 11:36:52.394687 CA PerBit enable=1, Macro0, CA PI delay=33
5051 11:36:52.394810
5052 11:36:52.398182 [CBTSetCACLKResult] CA Dly = 33
5053 11:36:52.398289 CS Dly: 6 (0~37)
5054 11:36:52.400994 ==
5055 11:36:52.404524 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 11:36:52.407781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 11:36:52.407873 ==
5058 11:36:52.411060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 11:36:52.417434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 11:36:52.421786 [CA 0] Center 38 (7~69) winsize 63
5061 11:36:52.424577 [CA 1] Center 38 (7~69) winsize 63
5062 11:36:52.428247 [CA 2] Center 35 (5~65) winsize 61
5063 11:36:52.431290 [CA 3] Center 34 (4~65) winsize 62
5064 11:36:52.434518 [CA 4] Center 33 (3~64) winsize 62
5065 11:36:52.438032 [CA 5] Center 33 (3~63) winsize 61
5066 11:36:52.438108
5067 11:36:52.441088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 11:36:52.441200
5069 11:36:52.444790 [CATrainingPosCal] consider 2 rank data
5070 11:36:52.447915 u2DelayCellTimex100 = 270/100 ps
5071 11:36:52.454579 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 11:36:52.457603 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5073 11:36:52.460602 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5074 11:36:52.464425 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5075 11:36:52.467196 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 11:36:52.470427 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5077 11:36:52.470506
5078 11:36:52.474023 CA PerBit enable=1, Macro0, CA PI delay=33
5079 11:36:52.474099
5080 11:36:52.477109 [CBTSetCACLKResult] CA Dly = 33
5081 11:36:52.480408 CS Dly: 7 (0~39)
5082 11:36:52.480486
5083 11:36:52.484274 ----->DramcWriteLeveling(PI) begin...
5084 11:36:52.484351 ==
5085 11:36:52.486993 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 11:36:52.490620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 11:36:52.490705 ==
5088 11:36:52.493771 Write leveling (Byte 0): 30 => 30
5089 11:36:52.497166 Write leveling (Byte 1): 28 => 28
5090 11:36:52.500344 DramcWriteLeveling(PI) end<-----
5091 11:36:52.500428
5092 11:36:52.500486 ==
5093 11:36:52.504085 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 11:36:52.507156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 11:36:52.507238 ==
5096 11:36:52.510231 [Gating] SW mode calibration
5097 11:36:52.516999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 11:36:52.523319 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 11:36:52.526510 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5100 11:36:52.533546 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5101 11:36:52.536483 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 11:36:52.539781 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:36:52.546193 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:36:52.549738 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:36:52.552685 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:36:52.559454 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5107 11:36:52.563235 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5108 11:36:52.566171 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5109 11:36:52.572531 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 11:36:52.575984 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:36:52.579165 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:36:52.585643 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:36:52.588873 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:36:52.592259 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5115 11:36:52.599527 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5116 11:36:52.602398 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:36:52.605485 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 11:36:52.612327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:36:52.615566 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:36:52.618987 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:36:52.625313 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:36:52.628960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 11:36:52.631894 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 11:36:52.639060 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 11:36:52.641823 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:36:52.645450 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:36:52.651852 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:36:52.655092 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:36:52.658554 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:36:52.665044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:36:52.669053 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:36:52.671346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:36:52.678227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:36:52.681108 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:36:52.684579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:36:52.691271 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:36:52.694472 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 11:36:52.697408 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5139 11:36:52.701022 Total UI for P1: 0, mck2ui 16
5140 11:36:52.704201 best dqsien dly found for B0: ( 1, 2, 24)
5141 11:36:52.710660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 11:36:52.713927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 11:36:52.717244 Total UI for P1: 0, mck2ui 16
5144 11:36:52.720491 best dqsien dly found for B1: ( 1, 3, 0)
5145 11:36:52.724338 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5146 11:36:52.727188 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5147 11:36:52.727630
5148 11:36:52.730582 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5149 11:36:52.733828 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5150 11:36:52.737277 [Gating] SW calibration Done
5151 11:36:52.737656 ==
5152 11:36:52.740412 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 11:36:52.747303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 11:36:52.747684 ==
5155 11:36:52.747974 RX Vref Scan: 0
5156 11:36:52.748244
5157 11:36:52.750324 RX Vref 0 -> 0, step: 1
5158 11:36:52.750698
5159 11:36:52.753544 RX Delay -80 -> 252, step: 8
5160 11:36:52.756889 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5161 11:36:52.760250 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5162 11:36:52.763879 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5163 11:36:52.766915 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5164 11:36:52.773503 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5165 11:36:52.776933 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5166 11:36:52.780138 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5167 11:36:52.783247 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5168 11:36:52.786495 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5169 11:36:52.793408 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5170 11:36:52.796794 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5171 11:36:52.800022 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5172 11:36:52.803228 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5173 11:36:52.806338 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5174 11:36:52.812710 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5175 11:36:52.816395 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5176 11:36:52.816773 ==
5177 11:36:52.819645 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:36:52.823374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:36:52.823754 ==
5180 11:36:52.825894 DQS Delay:
5181 11:36:52.826297 DQS0 = 0, DQS1 = 0
5182 11:36:52.826598 DQM Delay:
5183 11:36:52.829195 DQM0 = 102, DQM1 = 88
5184 11:36:52.829585 DQ Delay:
5185 11:36:52.832704 DQ0 =107, DQ1 =107, DQ2 =95, DQ3 =95
5186 11:36:52.836174 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5187 11:36:52.839295 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5188 11:36:52.842430 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5189 11:36:52.842806
5190 11:36:52.843094
5191 11:36:52.845776 ==
5192 11:36:52.849058 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 11:36:52.852417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 11:36:52.852844 ==
5195 11:36:52.853164
5196 11:36:52.853465
5197 11:36:52.855732 TX Vref Scan disable
5198 11:36:52.856106 == TX Byte 0 ==
5199 11:36:52.859198 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5200 11:36:52.865630 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5201 11:36:52.866010 == TX Byte 1 ==
5202 11:36:52.872245 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5203 11:36:52.875068 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5204 11:36:52.875502 ==
5205 11:36:52.878430 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 11:36:52.882116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 11:36:52.882530 ==
5208 11:36:52.882824
5209 11:36:52.883092
5210 11:36:52.884953 TX Vref Scan disable
5211 11:36:52.888287 == TX Byte 0 ==
5212 11:36:52.891710 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5213 11:36:52.894838 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5214 11:36:52.898966 == TX Byte 1 ==
5215 11:36:52.901533 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5216 11:36:52.905069 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5217 11:36:52.905492
5218 11:36:52.908349 [DATLAT]
5219 11:36:52.908721 Freq=933, CH0 RK0
5220 11:36:52.909012
5221 11:36:52.912076 DATLAT Default: 0xd
5222 11:36:52.912454 0, 0xFFFF, sum = 0
5223 11:36:52.914533 1, 0xFFFF, sum = 0
5224 11:36:52.914917 2, 0xFFFF, sum = 0
5225 11:36:52.917989 3, 0xFFFF, sum = 0
5226 11:36:52.918372 4, 0xFFFF, sum = 0
5227 11:36:52.921406 5, 0xFFFF, sum = 0
5228 11:36:52.921787 6, 0xFFFF, sum = 0
5229 11:36:52.924431 7, 0xFFFF, sum = 0
5230 11:36:52.924813 8, 0xFFFF, sum = 0
5231 11:36:52.928066 9, 0xFFFF, sum = 0
5232 11:36:52.928449 10, 0x0, sum = 1
5233 11:36:52.931316 11, 0x0, sum = 2
5234 11:36:52.931701 12, 0x0, sum = 3
5235 11:36:52.934426 13, 0x0, sum = 4
5236 11:36:52.934808 best_step = 11
5237 11:36:52.935098
5238 11:36:52.935363 ==
5239 11:36:52.937927 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 11:36:52.944562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 11:36:52.945006 ==
5242 11:36:52.945352 RX Vref Scan: 1
5243 11:36:52.945631
5244 11:36:52.948158 RX Vref 0 -> 0, step: 1
5245 11:36:52.948535
5246 11:36:52.951073 RX Delay -61 -> 252, step: 4
5247 11:36:52.951449
5248 11:36:52.954483 Set Vref, RX VrefLevel [Byte0]: 55
5249 11:36:52.957836 [Byte1]: 50
5250 11:36:52.958213
5251 11:36:52.960961 Final RX Vref Byte 0 = 55 to rank0
5252 11:36:52.964592 Final RX Vref Byte 1 = 50 to rank0
5253 11:36:52.967562 Final RX Vref Byte 0 = 55 to rank1
5254 11:36:52.971117 Final RX Vref Byte 1 = 50 to rank1==
5255 11:36:52.974165 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 11:36:52.977429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 11:36:52.977815 ==
5258 11:36:52.980753 DQS Delay:
5259 11:36:52.981292 DQS0 = 0, DQS1 = 0
5260 11:36:52.983928 DQM Delay:
5261 11:36:52.984303 DQM0 = 102, DQM1 = 90
5262 11:36:52.987343 DQ Delay:
5263 11:36:52.990432 DQ0 =102, DQ1 =102, DQ2 =98, DQ3 =100
5264 11:36:52.993794 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5265 11:36:52.997269 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =86
5266 11:36:53.000246 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5267 11:36:53.000621
5268 11:36:53.000909
5269 11:36:53.006858 [DQSOSCAuto] RK0, (LSB)MR18= 0x1914, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5270 11:36:53.010262 CH0 RK0: MR19=505, MR18=1914
5271 11:36:53.016643 CH0_RK0: MR19=0x505, MR18=0x1914, DQSOSC=413, MR23=63, INC=63, DEC=42
5272 11:36:53.017019
5273 11:36:53.019954 ----->DramcWriteLeveling(PI) begin...
5274 11:36:53.020334 ==
5275 11:36:53.023395 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 11:36:53.026799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 11:36:53.027179 ==
5278 11:36:53.030088 Write leveling (Byte 0): 34 => 34
5279 11:36:53.032820 Write leveling (Byte 1): 27 => 27
5280 11:36:53.036514 DramcWriteLeveling(PI) end<-----
5281 11:36:53.036888
5282 11:36:53.037209 ==
5283 11:36:53.039964 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 11:36:53.043613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:36:53.046462 ==
5286 11:36:53.046836 [Gating] SW mode calibration
5287 11:36:53.056519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 11:36:53.059642 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 11:36:53.062887 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
5290 11:36:53.069607 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 11:36:53.073253 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 11:36:53.076055 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:36:53.082502 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:36:53.085799 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:36:53.089753 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5296 11:36:53.095923 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 0)
5297 11:36:53.098959 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (1 0) (0 0)
5298 11:36:53.102259 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 11:36:53.109493 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 11:36:53.112176 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:36:53.115648 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:36:53.122259 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:36:53.125554 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:36:53.129230 0 15 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5305 11:36:53.135777 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5306 11:36:53.138439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 11:36:53.141976 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 11:36:53.148729 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:36:53.152271 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:36:53.155283 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:36:53.161496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5312 11:36:53.164958 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5313 11:36:53.168486 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5314 11:36:53.175297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 11:36:53.178551 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:36:53.181134 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:36:53.187703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:36:53.190928 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:36:53.194165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:36:53.200670 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:36:53.203995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:36:53.207514 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:36:53.214467 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:36:53.217191 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:36:53.220648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:36:53.227526 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:36:53.230405 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5328 11:36:53.233658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5329 11:36:53.236905 Total UI for P1: 0, mck2ui 16
5330 11:36:53.240491 best dqsien dly found for B0: ( 1, 2, 24)
5331 11:36:53.247154 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:36:53.250403 Total UI for P1: 0, mck2ui 16
5333 11:36:53.253619 best dqsien dly found for B1: ( 1, 2, 30)
5334 11:36:53.257586 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5335 11:36:53.260163 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5336 11:36:53.260262
5337 11:36:53.263386 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5338 11:36:53.267192 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5339 11:36:53.269805 [Gating] SW calibration Done
5340 11:36:53.269902 ==
5341 11:36:53.273148 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 11:36:53.276383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 11:36:53.276458 ==
5344 11:36:53.279968 RX Vref Scan: 0
5345 11:36:53.280068
5346 11:36:53.283524 RX Vref 0 -> 0, step: 1
5347 11:36:53.283611
5348 11:36:53.283692 RX Delay -80 -> 252, step: 8
5349 11:36:53.289523 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5350 11:36:53.292949 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5351 11:36:53.296394 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5352 11:36:53.299688 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5353 11:36:53.302915 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5354 11:36:53.306504 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5355 11:36:53.312866 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5356 11:36:53.315936 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5357 11:36:53.319330 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5358 11:36:53.323108 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5359 11:36:53.326220 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5360 11:36:53.332439 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5361 11:36:53.335928 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5362 11:36:53.339148 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5363 11:36:53.342846 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5364 11:36:53.345718 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5365 11:36:53.345784 ==
5366 11:36:53.348925 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 11:36:53.355499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 11:36:53.355590 ==
5369 11:36:53.355672 DQS Delay:
5370 11:36:53.359138 DQS0 = 0, DQS1 = 0
5371 11:36:53.359248 DQM Delay:
5372 11:36:53.362948 DQM0 = 100, DQM1 = 89
5373 11:36:53.363047 DQ Delay:
5374 11:36:53.365728 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =95
5375 11:36:53.369255 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5376 11:36:53.371863 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5377 11:36:53.375270 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5378 11:36:53.375331
5379 11:36:53.375383
5380 11:36:53.375433 ==
5381 11:36:53.378655 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 11:36:53.381768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 11:36:53.381829 ==
5384 11:36:53.381880
5385 11:36:53.381930
5386 11:36:53.385419 TX Vref Scan disable
5387 11:36:53.388432 == TX Byte 0 ==
5388 11:36:53.391971 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5389 11:36:53.394917 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5390 11:36:53.398300 == TX Byte 1 ==
5391 11:36:53.402337 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5392 11:36:53.405439 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5393 11:36:53.405520 ==
5394 11:36:53.408290 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 11:36:53.414942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 11:36:53.415037 ==
5397 11:36:53.415109
5398 11:36:53.415174
5399 11:36:53.415238 TX Vref Scan disable
5400 11:36:53.419343 == TX Byte 0 ==
5401 11:36:53.422698 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5402 11:36:53.429402 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5403 11:36:53.429524 == TX Byte 1 ==
5404 11:36:53.433358 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5405 11:36:53.438979 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5406 11:36:53.439142
5407 11:36:53.439269 [DATLAT]
5408 11:36:53.439387 Freq=933, CH0 RK1
5409 11:36:53.439499
5410 11:36:53.442517 DATLAT Default: 0xb
5411 11:36:53.442707 0, 0xFFFF, sum = 0
5412 11:36:53.445548 1, 0xFFFF, sum = 0
5413 11:36:53.448998 2, 0xFFFF, sum = 0
5414 11:36:53.449259 3, 0xFFFF, sum = 0
5415 11:36:53.452639 4, 0xFFFF, sum = 0
5416 11:36:53.452931 5, 0xFFFF, sum = 0
5417 11:36:53.455693 6, 0xFFFF, sum = 0
5418 11:36:53.456059 7, 0xFFFF, sum = 0
5419 11:36:53.459348 8, 0xFFFF, sum = 0
5420 11:36:53.459732 9, 0xFFFF, sum = 0
5421 11:36:53.463111 10, 0x0, sum = 1
5422 11:36:53.463494 11, 0x0, sum = 2
5423 11:36:53.465799 12, 0x0, sum = 3
5424 11:36:53.466181 13, 0x0, sum = 4
5425 11:36:53.466515 best_step = 11
5426 11:36:53.468866
5427 11:36:53.469420 ==
5428 11:36:53.472377 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 11:36:53.475427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 11:36:53.475840 ==
5431 11:36:53.476206 RX Vref Scan: 0
5432 11:36:53.476619
5433 11:36:53.479166 RX Vref 0 -> 0, step: 1
5434 11:36:53.479617
5435 11:36:53.482401 RX Delay -61 -> 252, step: 4
5436 11:36:53.488526 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5437 11:36:53.491976 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5438 11:36:53.495949 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5439 11:36:53.499067 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5440 11:36:53.502185 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5441 11:36:53.505026 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5442 11:36:53.511948 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5443 11:36:53.515468 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5444 11:36:53.518480 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5445 11:36:53.522057 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5446 11:36:53.525255 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5447 11:36:53.531672 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5448 11:36:53.534820 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5449 11:36:53.537970 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5450 11:36:53.541342 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5451 11:36:53.544752 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5452 11:36:53.547751 ==
5453 11:36:53.551031 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 11:36:53.555057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 11:36:53.555464 ==
5456 11:36:53.555760 DQS Delay:
5457 11:36:53.558065 DQS0 = 0, DQS1 = 0
5458 11:36:53.558444 DQM Delay:
5459 11:36:53.560993 DQM0 = 100, DQM1 = 90
5460 11:36:53.561401 DQ Delay:
5461 11:36:53.564297 DQ0 =98, DQ1 =102, DQ2 =96, DQ3 =98
5462 11:36:53.567775 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =106
5463 11:36:53.571821 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =84
5464 11:36:53.574850 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5465 11:36:53.575229
5466 11:36:53.575523
5467 11:36:53.580931 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5468 11:36:53.584241 CH0 RK1: MR19=505, MR18=1411
5469 11:36:53.591167 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5470 11:36:53.594244 [RxdqsGatingPostProcess] freq 933
5471 11:36:53.600728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 11:36:53.604548 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 11:36:53.607177 best DQS1 dly(2T, 0.5T) = (0, 11)
5474 11:36:53.610332 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 11:36:53.613611 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5476 11:36:53.617026 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 11:36:53.617455 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 11:36:53.620939 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 11:36:53.623974 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 11:36:53.627052 Pre-setting of DQS Precalculation
5481 11:36:53.633983 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 11:36:53.634375 ==
5483 11:36:53.636920 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 11:36:53.640016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 11:36:53.640540 ==
5486 11:36:53.647686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 11:36:53.653062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5488 11:36:53.656686 [CA 0] Center 36 (6~67) winsize 62
5489 11:36:53.660089 [CA 1] Center 36 (6~67) winsize 62
5490 11:36:53.663334 [CA 2] Center 35 (5~66) winsize 62
5491 11:36:53.666214 [CA 3] Center 34 (4~64) winsize 61
5492 11:36:53.669685 [CA 4] Center 34 (4~64) winsize 61
5493 11:36:53.673251 [CA 5] Center 33 (3~64) winsize 62
5494 11:36:53.673457
5495 11:36:53.676647 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5496 11:36:53.676853
5497 11:36:53.679759 [CATrainingPosCal] consider 1 rank data
5498 11:36:53.683134 u2DelayCellTimex100 = 270/100 ps
5499 11:36:53.686057 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 11:36:53.689588 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 11:36:53.692954 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5502 11:36:53.695920 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5503 11:36:53.699480 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5504 11:36:53.705988 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 11:36:53.706063
5506 11:36:53.708727 CA PerBit enable=1, Macro0, CA PI delay=33
5507 11:36:53.708815
5508 11:36:53.712490 [CBTSetCACLKResult] CA Dly = 33
5509 11:36:53.712564 CS Dly: 5 (0~36)
5510 11:36:53.712622 ==
5511 11:36:53.715705 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 11:36:53.718616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 11:36:53.722039 ==
5514 11:36:53.725638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 11:36:53.732333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5516 11:36:53.735338 [CA 0] Center 36 (6~67) winsize 62
5517 11:36:53.738385 [CA 1] Center 36 (6~67) winsize 62
5518 11:36:53.741753 [CA 2] Center 34 (4~65) winsize 62
5519 11:36:53.745639 [CA 3] Center 33 (3~64) winsize 62
5520 11:36:53.748595 [CA 4] Center 34 (4~65) winsize 62
5521 11:36:53.751817 [CA 5] Center 33 (3~64) winsize 62
5522 11:36:53.751902
5523 11:36:53.755373 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5524 11:36:53.755458
5525 11:36:53.758597 [CATrainingPosCal] consider 2 rank data
5526 11:36:53.761983 u2DelayCellTimex100 = 270/100 ps
5527 11:36:53.765492 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5528 11:36:53.768326 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 11:36:53.771913 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5530 11:36:53.778455 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 11:36:53.781464 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5532 11:36:53.785357 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 11:36:53.785431
5534 11:36:53.788205 CA PerBit enable=1, Macro0, CA PI delay=33
5535 11:36:53.788279
5536 11:36:53.791433 [CBTSetCACLKResult] CA Dly = 33
5537 11:36:53.791507 CS Dly: 6 (0~38)
5538 11:36:53.791565
5539 11:36:53.795122 ----->DramcWriteLeveling(PI) begin...
5540 11:36:53.798155 ==
5541 11:36:53.801292 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 11:36:53.804520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 11:36:53.804595 ==
5544 11:36:53.807695 Write leveling (Byte 0): 26 => 26
5545 11:36:53.810925 Write leveling (Byte 1): 28 => 28
5546 11:36:53.814707 DramcWriteLeveling(PI) end<-----
5547 11:36:53.814782
5548 11:36:53.814839 ==
5549 11:36:53.817793 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 11:36:53.821474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 11:36:53.821550 ==
5552 11:36:53.824091 [Gating] SW mode calibration
5553 11:36:53.831057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 11:36:53.837713 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 11:36:53.840677 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5556 11:36:53.844061 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 11:36:53.850603 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:36:53.854246 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:36:53.857618 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:36:53.863475 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:36:53.866768 0 14 24 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
5562 11:36:53.870720 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
5563 11:36:53.876874 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)
5564 11:36:53.880466 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 11:36:53.883519 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 11:36:53.890173 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:36:53.893687 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:36:53.896977 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:36:53.903098 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5570 11:36:53.906528 0 15 28 | B1->B0 | 3b3b 4242 | 0 1 | (0 0) (0 0)
5571 11:36:53.909908 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 11:36:53.916853 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 11:36:53.919865 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:36:53.923113 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:36:53.929716 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:36:53.933170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:36:53.936417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:36:53.942890 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:36:53.946292 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 11:36:53.949205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:36:53.956500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:36:53.959232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:36:53.962785 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:36:53.969197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:36:53.972536 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:36:53.975788 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:36:53.982411 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:36:53.985381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:36:53.989062 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:36:53.995764 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:36:53.998517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:36:54.002565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:36:54.008651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 11:36:54.012109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5595 11:36:54.015302 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5596 11:36:54.018520 Total UI for P1: 0, mck2ui 16
5597 11:36:54.021615 best dqsien dly found for B0: ( 1, 2, 26)
5598 11:36:54.029103 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 11:36:54.029256 Total UI for P1: 0, mck2ui 16
5600 11:36:54.035366 best dqsien dly found for B1: ( 1, 2, 28)
5601 11:36:54.038359 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5602 11:36:54.042042 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5603 11:36:54.042224
5604 11:36:54.045210 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5605 11:36:54.048293 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5606 11:36:54.051841 [Gating] SW calibration Done
5607 11:36:54.052022 ==
5608 11:36:54.055140 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 11:36:54.058779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 11:36:54.058961 ==
5611 11:36:54.061637 RX Vref Scan: 0
5612 11:36:54.061820
5613 11:36:54.061961 RX Vref 0 -> 0, step: 1
5614 11:36:54.064798
5615 11:36:54.064981 RX Delay -80 -> 252, step: 8
5616 11:36:54.071349 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5617 11:36:54.074966 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5618 11:36:54.078266 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5619 11:36:54.081296 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5620 11:36:54.084624 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5621 11:36:54.088292 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5622 11:36:54.094810 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5623 11:36:54.098452 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5624 11:36:54.101241 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5625 11:36:54.104497 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5626 11:36:54.108012 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5627 11:36:54.114021 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5628 11:36:54.117742 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5629 11:36:54.120954 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5630 11:36:54.123996 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5631 11:36:54.127638 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5632 11:36:54.127855 ==
5633 11:36:54.130727 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 11:36:54.137289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 11:36:54.137474 ==
5636 11:36:54.137616 DQS Delay:
5637 11:36:54.140519 DQS0 = 0, DQS1 = 0
5638 11:36:54.140702 DQM Delay:
5639 11:36:54.140843 DQM0 = 98, DQM1 = 93
5640 11:36:54.143680 DQ Delay:
5641 11:36:54.147243 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5642 11:36:54.150318 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5643 11:36:54.154006 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5644 11:36:54.157152 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5645 11:36:54.157386
5646 11:36:54.157530
5647 11:36:54.157661 ==
5648 11:36:54.160834 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 11:36:54.163677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 11:36:54.163862 ==
5651 11:36:54.164003
5652 11:36:54.164132
5653 11:36:54.166892 TX Vref Scan disable
5654 11:36:54.170131 == TX Byte 0 ==
5655 11:36:54.173420 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5656 11:36:54.177018 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5657 11:36:54.180554 == TX Byte 1 ==
5658 11:36:54.183004 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 11:36:54.186695 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 11:36:54.186878 ==
5661 11:36:54.189962 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 11:36:54.196461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 11:36:54.196645 ==
5664 11:36:54.196786
5665 11:36:54.196914
5666 11:36:54.197039 TX Vref Scan disable
5667 11:36:54.200504 == TX Byte 0 ==
5668 11:36:54.203661 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 11:36:54.210118 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 11:36:54.210303 == TX Byte 1 ==
5671 11:36:54.213981 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 11:36:54.220175 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 11:36:54.220358
5674 11:36:54.220498 [DATLAT]
5675 11:36:54.220626 Freq=933, CH1 RK0
5676 11:36:54.220751
5677 11:36:54.223531 DATLAT Default: 0xd
5678 11:36:54.223711 0, 0xFFFF, sum = 0
5679 11:36:54.226930 1, 0xFFFF, sum = 0
5680 11:36:54.230201 2, 0xFFFF, sum = 0
5681 11:36:54.230386 3, 0xFFFF, sum = 0
5682 11:36:54.233394 4, 0xFFFF, sum = 0
5683 11:36:54.233579 5, 0xFFFF, sum = 0
5684 11:36:54.236716 6, 0xFFFF, sum = 0
5685 11:36:54.236901 7, 0xFFFF, sum = 0
5686 11:36:54.239933 8, 0xFFFF, sum = 0
5687 11:36:54.240120 9, 0xFFFF, sum = 0
5688 11:36:54.243246 10, 0x0, sum = 1
5689 11:36:54.243429 11, 0x0, sum = 2
5690 11:36:54.246778 12, 0x0, sum = 3
5691 11:36:54.246968 13, 0x0, sum = 4
5692 11:36:54.247113 best_step = 11
5693 11:36:54.249889
5694 11:36:54.250069 ==
5695 11:36:54.253417 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 11:36:54.256384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 11:36:54.256567 ==
5698 11:36:54.256709 RX Vref Scan: 1
5699 11:36:54.256838
5700 11:36:54.259662 RX Vref 0 -> 0, step: 1
5701 11:36:54.259844
5702 11:36:54.263249 RX Delay -61 -> 252, step: 4
5703 11:36:54.263433
5704 11:36:54.266486 Set Vref, RX VrefLevel [Byte0]: 51
5705 11:36:54.269714 [Byte1]: 51
5706 11:36:54.272713
5707 11:36:54.272894 Final RX Vref Byte 0 = 51 to rank0
5708 11:36:54.276254 Final RX Vref Byte 1 = 51 to rank0
5709 11:36:54.279588 Final RX Vref Byte 0 = 51 to rank1
5710 11:36:54.282691 Final RX Vref Byte 1 = 51 to rank1==
5711 11:36:54.286497 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 11:36:54.292736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 11:36:54.292919 ==
5714 11:36:54.293062 DQS Delay:
5715 11:36:54.296189 DQS0 = 0, DQS1 = 0
5716 11:36:54.296411 DQM Delay:
5717 11:36:54.296556 DQM0 = 97, DQM1 = 94
5718 11:36:54.299053 DQ Delay:
5719 11:36:54.302639 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5720 11:36:54.306068 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5721 11:36:54.308821 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =86
5722 11:36:54.313332 DQ12 =104, DQ13 =104, DQ14 =98, DQ15 =100
5723 11:36:54.313480
5724 11:36:54.313594
5725 11:36:54.318840 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5726 11:36:54.322647 CH1 RK0: MR19=505, MR18=A1A
5727 11:36:54.329069 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5728 11:36:54.329254
5729 11:36:54.332314 ----->DramcWriteLeveling(PI) begin...
5730 11:36:54.332464 ==
5731 11:36:54.335506 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 11:36:54.338526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 11:36:54.338678 ==
5734 11:36:54.342246 Write leveling (Byte 0): 27 => 27
5735 11:36:54.345113 Write leveling (Byte 1): 28 => 28
5736 11:36:54.348650 DramcWriteLeveling(PI) end<-----
5737 11:36:54.348800
5738 11:36:54.348915 ==
5739 11:36:54.351812 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 11:36:54.358473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:36:54.358623 ==
5742 11:36:54.358739 [Gating] SW mode calibration
5743 11:36:54.368303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 11:36:54.371664 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 11:36:54.378030 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 11:36:54.381373 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 11:36:54.385070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:36:54.391278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:36:54.394539 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:36:54.398003 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:36:54.404389 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
5752 11:36:54.407772 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5753 11:36:54.410739 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 11:36:54.417577 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 11:36:54.421410 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:36:54.424225 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:36:54.430650 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:36:54.434229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:36:54.437530 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5760 11:36:54.444430 0 15 28 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
5761 11:36:54.447556 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 11:36:54.451296 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 11:36:54.457402 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:36:54.460636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:36:54.464270 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:36:54.470940 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:36:54.473533 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5768 11:36:54.477280 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 11:36:54.483513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 11:36:54.486851 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:36:54.490471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:36:54.496597 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:36:54.500094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:36:54.503464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:36:54.509978 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:36:54.513678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:36:54.516829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:36:54.523934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:36:54.526711 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:36:54.529967 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:36:54.536781 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:36:54.539763 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:36:54.543261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5784 11:36:54.549793 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 11:36:54.552816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 11:36:54.556256 Total UI for P1: 0, mck2ui 16
5787 11:36:54.559806 best dqsien dly found for B0: ( 1, 2, 26)
5788 11:36:54.562795 Total UI for P1: 0, mck2ui 16
5789 11:36:54.566071 best dqsien dly found for B1: ( 1, 2, 28)
5790 11:36:54.569477 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5791 11:36:54.572718 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5792 11:36:54.573098
5793 11:36:54.575653 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5794 11:36:54.579326 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5795 11:36:54.582612 [Gating] SW calibration Done
5796 11:36:54.582991 ==
5797 11:36:54.586221 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 11:36:54.589288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 11:36:54.592665 ==
5800 11:36:54.593210 RX Vref Scan: 0
5801 11:36:54.593523
5802 11:36:54.595838 RX Vref 0 -> 0, step: 1
5803 11:36:54.596219
5804 11:36:54.599017 RX Delay -80 -> 252, step: 8
5805 11:36:54.602477 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5806 11:36:54.605794 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5807 11:36:54.608926 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5808 11:36:54.611950 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5809 11:36:54.618799 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5810 11:36:54.622079 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5811 11:36:54.625421 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5812 11:36:54.628522 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5813 11:36:54.632011 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5814 11:36:54.635215 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5815 11:36:54.641643 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5816 11:36:54.645655 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5817 11:36:54.648422 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5818 11:36:54.651479 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5819 11:36:54.654812 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5820 11:36:54.661275 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5821 11:36:54.661675 ==
5822 11:36:54.665241 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:36:54.667829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:36:54.668216 ==
5825 11:36:54.668513 DQS Delay:
5826 11:36:54.671324 DQS0 = 0, DQS1 = 0
5827 11:36:54.671709 DQM Delay:
5828 11:36:54.674468 DQM0 = 95, DQM1 = 93
5829 11:36:54.674850 DQ Delay:
5830 11:36:54.677552 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5831 11:36:54.680965 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5832 11:36:54.684259 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5833 11:36:54.687632 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5834 11:36:54.688021
5835 11:36:54.688314
5836 11:36:54.688586 ==
5837 11:36:54.690599 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 11:36:54.697543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 11:36:54.698103 ==
5840 11:36:54.698417
5841 11:36:54.698726
5842 11:36:54.699032 TX Vref Scan disable
5843 11:36:54.701527 == TX Byte 0 ==
5844 11:36:54.704320 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5845 11:36:54.710753 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5846 11:36:54.711177 == TX Byte 1 ==
5847 11:36:54.713906 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5848 11:36:54.720871 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5849 11:36:54.721385 ==
5850 11:36:54.724081 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 11:36:54.727493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 11:36:54.727875 ==
5853 11:36:54.728168
5854 11:36:54.728438
5855 11:36:54.730921 TX Vref Scan disable
5856 11:36:54.731302 == TX Byte 0 ==
5857 11:36:54.737283 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 11:36:54.740817 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 11:36:54.743879 == TX Byte 1 ==
5860 11:36:54.747565 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5861 11:36:54.750585 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5862 11:36:54.750965
5863 11:36:54.751318 [DATLAT]
5864 11:36:54.753846 Freq=933, CH1 RK1
5865 11:36:54.754226
5866 11:36:54.754520 DATLAT Default: 0xb
5867 11:36:54.757594 0, 0xFFFF, sum = 0
5868 11:36:54.761079 1, 0xFFFF, sum = 0
5869 11:36:54.761586 2, 0xFFFF, sum = 0
5870 11:36:54.763643 3, 0xFFFF, sum = 0
5871 11:36:54.764026 4, 0xFFFF, sum = 0
5872 11:36:54.767164 5, 0xFFFF, sum = 0
5873 11:36:54.767551 6, 0xFFFF, sum = 0
5874 11:36:54.770929 7, 0xFFFF, sum = 0
5875 11:36:54.771389 8, 0xFFFF, sum = 0
5876 11:36:54.774275 9, 0xFFFF, sum = 0
5877 11:36:54.774736 10, 0x0, sum = 1
5878 11:36:54.777349 11, 0x0, sum = 2
5879 11:36:54.777809 12, 0x0, sum = 3
5880 11:36:54.780402 13, 0x0, sum = 4
5881 11:36:54.780873 best_step = 11
5882 11:36:54.781227
5883 11:36:54.781687 ==
5884 11:36:54.783580 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:36:54.786956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:36:54.789969 ==
5887 11:36:54.790347 RX Vref Scan: 0
5888 11:36:54.790639
5889 11:36:54.793781 RX Vref 0 -> 0, step: 1
5890 11:36:54.794233
5891 11:36:54.794535 RX Delay -61 -> 252, step: 4
5892 11:36:54.801290 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5893 11:36:54.805118 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5894 11:36:54.807905 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5895 11:36:54.811114 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5896 11:36:54.815047 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5897 11:36:54.820966 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5898 11:36:54.824186 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5899 11:36:54.828402 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5900 11:36:54.831023 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5901 11:36:54.834398 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5902 11:36:54.837674 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5903 11:36:54.844629 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5904 11:36:54.847765 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5905 11:36:54.851024 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5906 11:36:54.854283 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5907 11:36:54.861108 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5908 11:36:54.861611 ==
5909 11:36:54.864410 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:36:54.867362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:36:54.867875 ==
5912 11:36:54.868214 DQS Delay:
5913 11:36:54.870846 DQS0 = 0, DQS1 = 0
5914 11:36:54.871346 DQM Delay:
5915 11:36:54.873994 DQM0 = 97, DQM1 = 94
5916 11:36:54.874452 DQ Delay:
5917 11:36:54.877430 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5918 11:36:54.881326 DQ4 =98, DQ5 =104, DQ6 =102, DQ7 =94
5919 11:36:54.883909 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5920 11:36:54.887531 DQ12 =102, DQ13 =102, DQ14 =98, DQ15 =100
5921 11:36:54.887955
5922 11:36:54.888282
5923 11:36:54.896873 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5924 11:36:54.897392 CH1 RK1: MR19=505, MR18=B23
5925 11:36:54.903492 CH1_RK1: MR19=0x505, MR18=0xB23, DQSOSC=410, MR23=63, INC=64, DEC=42
5926 11:36:54.906574 [RxdqsGatingPostProcess] freq 933
5927 11:36:54.913667 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 11:36:54.916868 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 11:36:54.920616 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 11:36:54.923497 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 11:36:54.926448 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 11:36:54.929994 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 11:36:54.930378 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 11:36:54.933303 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 11:36:54.936721 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 11:36:54.940161 Pre-setting of DQS Precalculation
5937 11:36:54.946457 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 11:36:54.952852 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 11:36:54.959869 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 11:36:54.960331
5941 11:36:54.960623
5942 11:36:54.963002 [Calibration Summary] 1866 Mbps
5943 11:36:54.966578 CH 0, Rank 0
5944 11:36:54.967069 SW Impedance : PASS
5945 11:36:54.969397 DUTY Scan : NO K
5946 11:36:54.972685 ZQ Calibration : PASS
5947 11:36:54.973238 Jitter Meter : NO K
5948 11:36:54.976008 CBT Training : PASS
5949 11:36:54.979624 Write leveling : PASS
5950 11:36:54.980207 RX DQS gating : PASS
5951 11:36:54.982388 RX DQ/DQS(RDDQC) : PASS
5952 11:36:54.982907 TX DQ/DQS : PASS
5953 11:36:54.986271 RX DATLAT : PASS
5954 11:36:54.990269 RX DQ/DQS(Engine): PASS
5955 11:36:54.990822 TX OE : NO K
5956 11:36:54.993364 All Pass.
5957 11:36:54.993859
5958 11:36:54.994189 CH 0, Rank 1
5959 11:36:54.995653 SW Impedance : PASS
5960 11:36:54.996087 DUTY Scan : NO K
5961 11:36:54.999093 ZQ Calibration : PASS
5962 11:36:55.002277 Jitter Meter : NO K
5963 11:36:55.002663 CBT Training : PASS
5964 11:36:55.005780 Write leveling : PASS
5965 11:36:55.009264 RX DQS gating : PASS
5966 11:36:55.009767 RX DQ/DQS(RDDQC) : PASS
5967 11:36:55.012572 TX DQ/DQS : PASS
5968 11:36:55.015592 RX DATLAT : PASS
5969 11:36:55.016020 RX DQ/DQS(Engine): PASS
5970 11:36:55.019079 TX OE : NO K
5971 11:36:55.019467 All Pass.
5972 11:36:55.019765
5973 11:36:55.022202 CH 1, Rank 0
5974 11:36:55.022585 SW Impedance : PASS
5975 11:36:55.025169 DUTY Scan : NO K
5976 11:36:55.029109 ZQ Calibration : PASS
5977 11:36:55.029622 Jitter Meter : NO K
5978 11:36:55.031920 CBT Training : PASS
5979 11:36:55.035496 Write leveling : PASS
5980 11:36:55.035960 RX DQS gating : PASS
5981 11:36:55.038637 RX DQ/DQS(RDDQC) : PASS
5982 11:36:55.041959 TX DQ/DQS : PASS
5983 11:36:55.042451 RX DATLAT : PASS
5984 11:36:55.045166 RX DQ/DQS(Engine): PASS
5985 11:36:55.048721 TX OE : NO K
5986 11:36:55.049226 All Pass.
5987 11:36:55.049539
5988 11:36:55.049814 CH 1, Rank 1
5989 11:36:55.052249 SW Impedance : PASS
5990 11:36:55.055146 DUTY Scan : NO K
5991 11:36:55.055609 ZQ Calibration : PASS
5992 11:36:55.058229 Jitter Meter : NO K
5993 11:36:55.061482 CBT Training : PASS
5994 11:36:55.061867 Write leveling : PASS
5995 11:36:55.064693 RX DQS gating : PASS
5996 11:36:55.065080 RX DQ/DQS(RDDQC) : PASS
5997 11:36:55.068049 TX DQ/DQS : PASS
5998 11:36:55.071468 RX DATLAT : PASS
5999 11:36:55.071851 RX DQ/DQS(Engine): PASS
6000 11:36:55.075071 TX OE : NO K
6001 11:36:55.075456 All Pass.
6002 11:36:55.075754
6003 11:36:55.078311 DramC Write-DBI off
6004 11:36:55.081532 PER_BANK_REFRESH: Hybrid Mode
6005 11:36:55.081916 TX_TRACKING: ON
6006 11:36:55.091479 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 11:36:55.094592 [FAST_K] Save calibration result to emmc
6008 11:36:55.098164 dramc_set_vcore_voltage set vcore to 650000
6009 11:36:55.100821 Read voltage for 400, 6
6010 11:36:55.101374 Vio18 = 0
6011 11:36:55.104148 Vcore = 650000
6012 11:36:55.104660 Vdram = 0
6013 11:36:55.104976 Vddq = 0
6014 11:36:55.105293 Vmddr = 0
6015 11:36:55.110931 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 11:36:55.117911 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 11:36:55.118379 MEM_TYPE=3, freq_sel=20
6018 11:36:55.121194 sv_algorithm_assistance_LP4_800
6019 11:36:55.124228 ============ PULL DRAM RESETB DOWN ============
6020 11:36:55.130916 ========== PULL DRAM RESETB DOWN end =========
6021 11:36:55.134474 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 11:36:55.137166 ===================================
6023 11:36:55.140664 LPDDR4 DRAM CONFIGURATION
6024 11:36:55.144169 ===================================
6025 11:36:55.144630 EX_ROW_EN[0] = 0x0
6026 11:36:55.147285 EX_ROW_EN[1] = 0x0
6027 11:36:55.147741 LP4Y_EN = 0x0
6028 11:36:55.150571 WORK_FSP = 0x0
6029 11:36:55.153901 WL = 0x2
6030 11:36:55.154280 RL = 0x2
6031 11:36:55.157019 BL = 0x2
6032 11:36:55.157463 RPST = 0x0
6033 11:36:55.160660 RD_PRE = 0x0
6034 11:36:55.161041 WR_PRE = 0x1
6035 11:36:55.163665 WR_PST = 0x0
6036 11:36:55.164045 DBI_WR = 0x0
6037 11:36:55.167294 DBI_RD = 0x0
6038 11:36:55.167678 OTF = 0x1
6039 11:36:55.170255 ===================================
6040 11:36:55.174081 ===================================
6041 11:36:55.176995 ANA top config
6042 11:36:55.180492 ===================================
6043 11:36:55.180956 DLL_ASYNC_EN = 0
6044 11:36:55.183504 ALL_SLAVE_EN = 1
6045 11:36:55.186842 NEW_RANK_MODE = 1
6046 11:36:55.190231 DLL_IDLE_MODE = 1
6047 11:36:55.193661 LP45_APHY_COMB_EN = 1
6048 11:36:55.194116 TX_ODT_DIS = 1
6049 11:36:55.197281 NEW_8X_MODE = 1
6050 11:36:55.200065 ===================================
6051 11:36:55.203334 ===================================
6052 11:36:55.206662 data_rate = 800
6053 11:36:55.209662 CKR = 1
6054 11:36:55.212904 DQ_P2S_RATIO = 4
6055 11:36:55.216728 ===================================
6056 11:36:55.220136 CA_P2S_RATIO = 4
6057 11:36:55.220597 DQ_CA_OPEN = 0
6058 11:36:55.223357 DQ_SEMI_OPEN = 1
6059 11:36:55.226293 CA_SEMI_OPEN = 1
6060 11:36:55.229814 CA_FULL_RATE = 0
6061 11:36:55.233343 DQ_CKDIV4_EN = 0
6062 11:36:55.235987 CA_CKDIV4_EN = 1
6063 11:36:55.236369 CA_PREDIV_EN = 0
6064 11:36:55.239141 PH8_DLY = 0
6065 11:36:55.242403 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 11:36:55.245792 DQ_AAMCK_DIV = 0
6067 11:36:55.249219 CA_AAMCK_DIV = 0
6068 11:36:55.252924 CA_ADMCK_DIV = 4
6069 11:36:55.255913 DQ_TRACK_CA_EN = 0
6070 11:36:55.256368 CA_PICK = 800
6071 11:36:55.259112 CA_MCKIO = 400
6072 11:36:55.262283 MCKIO_SEMI = 400
6073 11:36:55.265975 PLL_FREQ = 3016
6074 11:36:55.268795 DQ_UI_PI_RATIO = 32
6075 11:36:55.272267 CA_UI_PI_RATIO = 32
6076 11:36:55.275729 ===================================
6077 11:36:55.278701 ===================================
6078 11:36:55.282205 memory_type:LPDDR4
6079 11:36:55.282661 GP_NUM : 10
6080 11:36:55.285623 SRAM_EN : 1
6081 11:36:55.286080 MD32_EN : 0
6082 11:36:55.288464 ===================================
6083 11:36:55.292195 [ANA_INIT] >>>>>>>>>>>>>>
6084 11:36:55.296331 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 11:36:55.298361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 11:36:55.301789 ===================================
6087 11:36:55.305189 data_rate = 800,PCW = 0X7400
6088 11:36:55.308349 ===================================
6089 11:36:55.312048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 11:36:55.319232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 11:36:55.328815 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:36:55.332216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 11:36:55.334648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 11:36:55.338264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:36:55.341806 [ANA_INIT] flow start
6096 11:36:55.344891 [ANA_INIT] PLL >>>>>>>>
6097 11:36:55.345406 [ANA_INIT] PLL <<<<<<<<
6098 11:36:55.348074 [ANA_INIT] MIDPI >>>>>>>>
6099 11:36:55.351528 [ANA_INIT] MIDPI <<<<<<<<
6100 11:36:55.354523 [ANA_INIT] DLL >>>>>>>>
6101 11:36:55.354945 [ANA_INIT] flow end
6102 11:36:55.357689 ============ LP4 DIFF to SE enter ============
6103 11:36:55.364999 ============ LP4 DIFF to SE exit ============
6104 11:36:55.365536 [ANA_INIT] <<<<<<<<<<<<<
6105 11:36:55.367959 [Flow] Enable top DCM control >>>>>
6106 11:36:55.371548 [Flow] Enable top DCM control <<<<<
6107 11:36:55.374382 Enable DLL master slave shuffle
6108 11:36:55.381204 ==============================================================
6109 11:36:55.383948 Gating Mode config
6110 11:36:55.387615 ==============================================================
6111 11:36:55.390346 Config description:
6112 11:36:55.400720 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 11:36:55.407248 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 11:36:55.410347 SELPH_MODE 0: By rank 1: By Phase
6115 11:36:55.417114 ==============================================================
6116 11:36:55.420618 GAT_TRACK_EN = 0
6117 11:36:55.423527 RX_GATING_MODE = 2
6118 11:36:55.426832 RX_GATING_TRACK_MODE = 2
6119 11:36:55.430631 SELPH_MODE = 1
6120 11:36:55.431085 PICG_EARLY_EN = 1
6121 11:36:55.433749 VALID_LAT_VALUE = 1
6122 11:36:55.440198 ==============================================================
6123 11:36:55.443089 Enter into Gating configuration >>>>
6124 11:36:55.447315 Exit from Gating configuration <<<<
6125 11:36:55.449733 Enter into DVFS_PRE_config >>>>>
6126 11:36:55.459766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 11:36:55.462943 Exit from DVFS_PRE_config <<<<<
6128 11:36:55.466544 Enter into PICG configuration >>>>
6129 11:36:55.469699 Exit from PICG configuration <<<<
6130 11:36:55.472708 [RX_INPUT] configuration >>>>>
6131 11:36:55.476391 [RX_INPUT] configuration <<<<<
6132 11:36:55.482671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 11:36:55.486436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 11:36:55.492568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 11:36:55.499577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 11:36:55.505827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 11:36:55.511970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 11:36:55.515624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 11:36:55.518665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 11:36:55.521819 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 11:36:55.528401 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 11:36:55.531482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 11:36:55.534512 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 11:36:55.538115 ===================================
6145 11:36:55.541452 LPDDR4 DRAM CONFIGURATION
6146 11:36:55.545101 ===================================
6147 11:36:55.547923 EX_ROW_EN[0] = 0x0
6148 11:36:55.547998 EX_ROW_EN[1] = 0x0
6149 11:36:55.551426 LP4Y_EN = 0x0
6150 11:36:55.551503 WORK_FSP = 0x0
6151 11:36:55.554944 WL = 0x2
6152 11:36:55.555020 RL = 0x2
6153 11:36:55.558095 BL = 0x2
6154 11:36:55.558214 RPST = 0x0
6155 11:36:55.561062 RD_PRE = 0x0
6156 11:36:55.561184 WR_PRE = 0x1
6157 11:36:55.564483 WR_PST = 0x0
6158 11:36:55.564590 DBI_WR = 0x0
6159 11:36:55.567700 DBI_RD = 0x0
6160 11:36:55.567814 OTF = 0x1
6161 11:36:55.571070 ===================================
6162 11:36:55.577763 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 11:36:55.580941 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 11:36:55.584150 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 11:36:55.587510 ===================================
6166 11:36:55.590689 LPDDR4 DRAM CONFIGURATION
6167 11:36:55.594153 ===================================
6168 11:36:55.597505 EX_ROW_EN[0] = 0x10
6169 11:36:55.597624 EX_ROW_EN[1] = 0x0
6170 11:36:55.600748 LP4Y_EN = 0x0
6171 11:36:55.600861 WORK_FSP = 0x0
6172 11:36:55.604263 WL = 0x2
6173 11:36:55.604387 RL = 0x2
6174 11:36:55.607299 BL = 0x2
6175 11:36:55.607424 RPST = 0x0
6176 11:36:55.611365 RD_PRE = 0x0
6177 11:36:55.611485 WR_PRE = 0x1
6178 11:36:55.613800 WR_PST = 0x0
6179 11:36:55.613917 DBI_WR = 0x0
6180 11:36:55.617037 DBI_RD = 0x0
6181 11:36:55.617168 OTF = 0x1
6182 11:36:55.620648 ===================================
6183 11:36:55.627201 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 11:36:55.632020 nWR fixed to 30
6185 11:36:55.635418 [ModeRegInit_LP4] CH0 RK0
6186 11:36:55.635537 [ModeRegInit_LP4] CH0 RK1
6187 11:36:55.638904 [ModeRegInit_LP4] CH1 RK0
6188 11:36:55.642110 [ModeRegInit_LP4] CH1 RK1
6189 11:36:55.642233 match AC timing 19
6190 11:36:55.648823 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 11:36:55.652011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 11:36:55.655435 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 11:36:55.662086 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 11:36:55.665039 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 11:36:55.665164 ==
6196 11:36:55.668459 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 11:36:55.671500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 11:36:55.671577 ==
6199 11:36:55.678038 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 11:36:55.685126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6201 11:36:55.688024 [CA 0] Center 36 (8~64) winsize 57
6202 11:36:55.691702 [CA 1] Center 36 (8~64) winsize 57
6203 11:36:55.695074 [CA 2] Center 36 (8~64) winsize 57
6204 11:36:55.698115 [CA 3] Center 36 (8~64) winsize 57
6205 11:36:55.701132 [CA 4] Center 36 (8~64) winsize 57
6206 11:36:55.704864 [CA 5] Center 36 (8~64) winsize 57
6207 11:36:55.704939
6208 11:36:55.707983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6209 11:36:55.708059
6210 11:36:55.711264 [CATrainingPosCal] consider 1 rank data
6211 11:36:55.714968 u2DelayCellTimex100 = 270/100 ps
6212 11:36:55.718170 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 11:36:55.721429 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:36:55.725097 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:36:55.727836 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:36:55.730855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:36:55.734306 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:36:55.734382
6219 11:36:55.740976 CA PerBit enable=1, Macro0, CA PI delay=36
6220 11:36:55.741052
6221 11:36:55.741110 [CBTSetCACLKResult] CA Dly = 36
6222 11:36:55.744473 CS Dly: 1 (0~32)
6223 11:36:55.744547 ==
6224 11:36:55.747669 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 11:36:55.751182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 11:36:55.751258 ==
6227 11:36:55.757673 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 11:36:55.764303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6229 11:36:55.767158 [CA 0] Center 36 (8~64) winsize 57
6230 11:36:55.770742 [CA 1] Center 36 (8~64) winsize 57
6231 11:36:55.773783 [CA 2] Center 36 (8~64) winsize 57
6232 11:36:55.777064 [CA 3] Center 36 (8~64) winsize 57
6233 11:36:55.777166 [CA 4] Center 36 (8~64) winsize 57
6234 11:36:55.780911 [CA 5] Center 36 (8~64) winsize 57
6235 11:36:55.780985
6236 11:36:55.787487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6237 11:36:55.787564
6238 11:36:55.790295 [CATrainingPosCal] consider 2 rank data
6239 11:36:55.793897 u2DelayCellTimex100 = 270/100 ps
6240 11:36:55.796970 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:36:55.800375 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:36:55.803666 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:36:55.807008 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:36:55.810012 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:36:55.813695 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:36:55.813771
6247 11:36:55.817274 CA PerBit enable=1, Macro0, CA PI delay=36
6248 11:36:55.817350
6249 11:36:55.820237 [CBTSetCACLKResult] CA Dly = 36
6250 11:36:55.823196 CS Dly: 1 (0~32)
6251 11:36:55.823271
6252 11:36:55.826748 ----->DramcWriteLeveling(PI) begin...
6253 11:36:55.826825 ==
6254 11:36:55.830180 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:36:55.833851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:36:55.833928 ==
6257 11:36:55.836303 Write leveling (Byte 0): 40 => 8
6258 11:36:55.839781 Write leveling (Byte 1): 40 => 8
6259 11:36:55.843178 DramcWriteLeveling(PI) end<-----
6260 11:36:55.843253
6261 11:36:55.843311 ==
6262 11:36:55.846493 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:36:55.849681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:36:55.849758 ==
6265 11:36:55.852854 [Gating] SW mode calibration
6266 11:36:55.859546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 11:36:55.865849 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 11:36:55.869306 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 11:36:55.875921 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:36:55.879392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 11:36:55.882494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:36:55.889080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 11:36:55.892263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:36:55.895425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:36:55.902159 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:36:55.905555 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:36:55.909060 Total UI for P1: 0, mck2ui 16
6278 11:36:55.912031 best dqsien dly found for B0: ( 0, 14, 24)
6279 11:36:55.915930 Total UI for P1: 0, mck2ui 16
6280 11:36:55.919162 best dqsien dly found for B1: ( 0, 14, 24)
6281 11:36:55.921978 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 11:36:55.925032 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:36:55.925109
6284 11:36:55.928432 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 11:36:55.935199 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:36:55.935275 [Gating] SW calibration Done
6287 11:36:55.935333 ==
6288 11:36:55.938360 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 11:36:55.944741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:36:55.944816 ==
6291 11:36:55.944874 RX Vref Scan: 0
6292 11:36:55.944928
6293 11:36:55.948124 RX Vref 0 -> 0, step: 1
6294 11:36:55.948199
6295 11:36:55.951746 RX Delay -410 -> 252, step: 16
6296 11:36:55.954980 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6297 11:36:55.957970 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6298 11:36:55.964463 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6299 11:36:55.967774 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6300 11:36:55.971308 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6301 11:36:55.975121 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6302 11:36:55.981530 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6303 11:36:55.984712 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6304 11:36:55.987883 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6305 11:36:55.991343 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6306 11:36:55.997537 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6307 11:36:56.000919 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6308 11:36:56.004744 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6309 11:36:56.010645 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6310 11:36:56.014191 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6311 11:36:56.017652 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6312 11:36:56.017727 ==
6313 11:36:56.020952 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:36:56.024099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:36:56.027306 ==
6316 11:36:56.027382 DQS Delay:
6317 11:36:56.027439 DQS0 = 35, DQS1 = 51
6318 11:36:56.031003 DQM Delay:
6319 11:36:56.031077 DQM0 = 5, DQM1 = 10
6320 11:36:56.033771 DQ Delay:
6321 11:36:56.033845 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6322 11:36:56.037078 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6323 11:36:56.041042 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6324 11:36:56.043861 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6325 11:36:56.043935
6326 11:36:56.043992
6327 11:36:56.044045 ==
6328 11:36:56.046988 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 11:36:56.053353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 11:36:56.053443 ==
6331 11:36:56.053501
6332 11:36:56.053553
6333 11:36:56.053603 TX Vref Scan disable
6334 11:36:56.056855 == TX Byte 0 ==
6335 11:36:56.060475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:36:56.063878 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:36:56.066969 == TX Byte 1 ==
6338 11:36:56.070533 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 11:36:56.073532 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 11:36:56.077079 ==
6341 11:36:56.080305 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:36:56.083621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:36:56.083696 ==
6344 11:36:56.083753
6345 11:36:56.083806
6346 11:36:56.086891 TX Vref Scan disable
6347 11:36:56.086965 == TX Byte 0 ==
6348 11:36:56.090176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:36:56.097052 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:36:56.097175 == TX Byte 1 ==
6351 11:36:56.100368 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 11:36:56.106774 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 11:36:56.106888
6354 11:36:56.106948 [DATLAT]
6355 11:36:56.107003 Freq=400, CH0 RK0
6356 11:36:56.107055
6357 11:36:56.110072 DATLAT Default: 0xf
6358 11:36:56.110147 0, 0xFFFF, sum = 0
6359 11:36:56.113674 1, 0xFFFF, sum = 0
6360 11:36:56.116210 2, 0xFFFF, sum = 0
6361 11:36:56.116286 3, 0xFFFF, sum = 0
6362 11:36:56.119851 4, 0xFFFF, sum = 0
6363 11:36:56.119928 5, 0xFFFF, sum = 0
6364 11:36:56.123170 6, 0xFFFF, sum = 0
6365 11:36:56.123254 7, 0xFFFF, sum = 0
6366 11:36:56.126586 8, 0xFFFF, sum = 0
6367 11:36:56.126662 9, 0xFFFF, sum = 0
6368 11:36:56.129530 10, 0xFFFF, sum = 0
6369 11:36:56.129606 11, 0xFFFF, sum = 0
6370 11:36:56.132930 12, 0xFFFF, sum = 0
6371 11:36:56.133007 13, 0x0, sum = 1
6372 11:36:56.136159 14, 0x0, sum = 2
6373 11:36:56.136236 15, 0x0, sum = 3
6374 11:36:56.139899 16, 0x0, sum = 4
6375 11:36:56.139975 best_step = 14
6376 11:36:56.140032
6377 11:36:56.140085 ==
6378 11:36:56.142591 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:36:56.149130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:36:56.149243 ==
6381 11:36:56.149301 RX Vref Scan: 1
6382 11:36:56.149355
6383 11:36:56.152552 RX Vref 0 -> 0, step: 1
6384 11:36:56.152627
6385 11:36:56.156280 RX Delay -343 -> 252, step: 8
6386 11:36:56.156354
6387 11:36:56.159614 Set Vref, RX VrefLevel [Byte0]: 55
6388 11:36:56.162620 [Byte1]: 50
6389 11:36:56.162735
6390 11:36:56.166336 Final RX Vref Byte 0 = 55 to rank0
6391 11:36:56.169707 Final RX Vref Byte 1 = 50 to rank0
6392 11:36:56.172826 Final RX Vref Byte 0 = 55 to rank1
6393 11:36:56.175794 Final RX Vref Byte 1 = 50 to rank1==
6394 11:36:56.179297 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:36:56.185612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:36:56.185744 ==
6397 11:36:56.185808 DQS Delay:
6398 11:36:56.188910 DQS0 = 40, DQS1 = 60
6399 11:36:56.189045 DQM Delay:
6400 11:36:56.189107 DQM0 = 7, DQM1 = 17
6401 11:36:56.192088 DQ Delay:
6402 11:36:56.195537 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =0
6403 11:36:56.195676 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6404 11:36:56.198772 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6405 11:36:56.201893 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6406 11:36:56.202028
6407 11:36:56.202101
6408 11:36:56.212099 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a8e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6409 11:36:56.215394 CH0 RK0: MR19=C0C, MR18=9A8E
6410 11:36:56.221651 CH0_RK0: MR19=0xC0C, MR18=0x9A8E, DQSOSC=390, MR23=63, INC=388, DEC=258
6411 11:36:56.221793 ==
6412 11:36:56.224928 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 11:36:56.228247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:36:56.228374 ==
6415 11:36:56.231428 [Gating] SW mode calibration
6416 11:36:56.238207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 11:36:56.244834 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 11:36:56.248114 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 11:36:56.251510 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:36:56.258058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 11:36:56.261448 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:36:56.264926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 11:36:56.271299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:36:56.274942 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:36:56.278430 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:36:56.285261 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:36:56.285728 Total UI for P1: 0, mck2ui 16
6428 11:36:56.291646 best dqsien dly found for B0: ( 0, 14, 24)
6429 11:36:56.292183 Total UI for P1: 0, mck2ui 16
6430 11:36:56.298438 best dqsien dly found for B1: ( 0, 14, 24)
6431 11:36:56.301198 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 11:36:56.304560 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:36:56.304986
6434 11:36:56.307868 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 11:36:56.311538 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:36:56.314516 [Gating] SW calibration Done
6437 11:36:56.315018 ==
6438 11:36:56.317578 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 11:36:56.321323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 11:36:56.321837 ==
6441 11:36:56.324514 RX Vref Scan: 0
6442 11:36:56.325013
6443 11:36:56.325406 RX Vref 0 -> 0, step: 1
6444 11:36:56.327470
6445 11:36:56.327889 RX Delay -410 -> 252, step: 16
6446 11:36:56.333667 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6447 11:36:56.337734 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6448 11:36:56.340626 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6449 11:36:56.344039 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6450 11:36:56.350864 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6451 11:36:56.353509 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6452 11:36:56.357429 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6453 11:36:56.360434 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6454 11:36:56.367058 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6455 11:36:56.370287 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6456 11:36:56.373371 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6457 11:36:56.380044 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6458 11:36:56.383158 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6459 11:36:56.386498 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6460 11:36:56.390059 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6461 11:36:56.397457 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6462 11:36:56.397960 ==
6463 11:36:56.400042 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:36:56.403247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:36:56.403722 ==
6466 11:36:56.404072 DQS Delay:
6467 11:36:56.406495 DQS0 = 35, DQS1 = 59
6468 11:36:56.406875 DQM Delay:
6469 11:36:56.409798 DQM0 = 5, DQM1 = 17
6470 11:36:56.410181 DQ Delay:
6471 11:36:56.413074 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6472 11:36:56.416322 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6473 11:36:56.419628 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6474 11:36:56.422972 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6475 11:36:56.423473
6476 11:36:56.423817
6477 11:36:56.424206 ==
6478 11:36:56.425948 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 11:36:56.430109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:36:56.430586 ==
6481 11:36:56.430888
6482 11:36:56.432677
6483 11:36:56.433170 TX Vref Scan disable
6484 11:36:56.436215 == TX Byte 0 ==
6485 11:36:56.439810 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6486 11:36:56.443023 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6487 11:36:56.445956 == TX Byte 1 ==
6488 11:36:56.449383 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 11:36:56.452506 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 11:36:56.452932 ==
6491 11:36:56.455589 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 11:36:56.459430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:36:56.462245 ==
6494 11:36:56.462778
6495 11:36:56.463114
6496 11:36:56.463441 TX Vref Scan disable
6497 11:36:56.466143 == TX Byte 0 ==
6498 11:36:56.468378 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6499 11:36:56.472215 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6500 11:36:56.476005 == TX Byte 1 ==
6501 11:36:56.478475 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 11:36:56.482099 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 11:36:56.482569
6504 11:36:56.485354 [DATLAT]
6505 11:36:56.485750 Freq=400, CH0 RK1
6506 11:36:56.486049
6507 11:36:56.488533 DATLAT Default: 0xe
6508 11:36:56.488951 0, 0xFFFF, sum = 0
6509 11:36:56.491874 1, 0xFFFF, sum = 0
6510 11:36:56.492370 2, 0xFFFF, sum = 0
6511 11:36:56.495668 3, 0xFFFF, sum = 0
6512 11:36:56.496141 4, 0xFFFF, sum = 0
6513 11:36:56.499159 5, 0xFFFF, sum = 0
6514 11:36:56.499549 6, 0xFFFF, sum = 0
6515 11:36:56.502311 7, 0xFFFF, sum = 0
6516 11:36:56.502745 8, 0xFFFF, sum = 0
6517 11:36:56.505303 9, 0xFFFF, sum = 0
6518 11:36:56.505695 10, 0xFFFF, sum = 0
6519 11:36:56.508455 11, 0xFFFF, sum = 0
6520 11:36:56.508932 12, 0xFFFF, sum = 0
6521 11:36:56.512038 13, 0x0, sum = 1
6522 11:36:56.512507 14, 0x0, sum = 2
6523 11:36:56.515644 15, 0x0, sum = 3
6524 11:36:56.516115 16, 0x0, sum = 4
6525 11:36:56.518128 best_step = 14
6526 11:36:56.518509
6527 11:36:56.518808 ==
6528 11:36:56.521833 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:36:56.525733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:36:56.526202 ==
6531 11:36:56.528434 RX Vref Scan: 0
6532 11:36:56.528895
6533 11:36:56.529233 RX Vref 0 -> 0, step: 1
6534 11:36:56.529517
6535 11:36:56.531638 RX Delay -359 -> 252, step: 8
6536 11:36:56.540212 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6537 11:36:56.543683 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6538 11:36:56.546565 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6539 11:36:56.553198 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6540 11:36:56.556469 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6541 11:36:56.559908 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6542 11:36:56.563288 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6543 11:36:56.569599 iDelay=209, Bit 7, Center -32 (-271 ~ 208) 480
6544 11:36:56.573300 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6545 11:36:56.576571 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6546 11:36:56.580042 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6547 11:36:56.586034 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6548 11:36:56.589353 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6549 11:36:56.593118 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6550 11:36:56.596513 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6551 11:36:56.602833 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6552 11:36:56.603344 ==
6553 11:36:56.606440 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:36:56.608947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:36:56.609378 ==
6556 11:36:56.609684 DQS Delay:
6557 11:36:56.612368 DQS0 = 44, DQS1 = 60
6558 11:36:56.612827 DQM Delay:
6559 11:36:56.616164 DQM0 = 8, DQM1 = 13
6560 11:36:56.616545 DQ Delay:
6561 11:36:56.619004 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6562 11:36:56.622393 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =12
6563 11:36:56.625848 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6564 11:36:56.628983 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6565 11:36:56.629480
6566 11:36:56.629777
6567 11:36:56.635796 [DQSOSCAuto] RK1, (LSB)MR18= 0x8881, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6568 11:36:56.638684 CH0 RK1: MR19=C0C, MR18=8881
6569 11:36:56.645336 CH0_RK1: MR19=0xC0C, MR18=0x8881, DQSOSC=392, MR23=63, INC=384, DEC=256
6570 11:36:56.648371 [RxdqsGatingPostProcess] freq 400
6571 11:36:56.654905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 11:36:56.658270 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 11:36:56.661426 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 11:36:56.664960 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 11:36:56.668402 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 11:36:56.668784 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 11:36:56.671449 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 11:36:56.675099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 11:36:56.678177 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 11:36:56.681422 Pre-setting of DQS Precalculation
6581 11:36:56.687856 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 11:36:56.688299 ==
6583 11:36:56.691623 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 11:36:56.694921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:36:56.695313 ==
6586 11:36:56.701088 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 11:36:56.707909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6588 11:36:56.711341 [CA 0] Center 36 (8~64) winsize 57
6589 11:36:56.714502 [CA 1] Center 36 (8~64) winsize 57
6590 11:36:56.717661 [CA 2] Center 36 (8~64) winsize 57
6591 11:36:56.718045 [CA 3] Center 36 (8~64) winsize 57
6592 11:36:56.721132 [CA 4] Center 36 (8~64) winsize 57
6593 11:36:56.724898 [CA 5] Center 36 (8~64) winsize 57
6594 11:36:56.725413
6595 11:36:56.731000 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6596 11:36:56.731382
6597 11:36:56.734593 [CATrainingPosCal] consider 1 rank data
6598 11:36:56.737584 u2DelayCellTimex100 = 270/100 ps
6599 11:36:56.741079 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 11:36:56.743975 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:36:56.747454 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:36:56.751524 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:36:56.753963 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:36:56.757089 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:36:56.757514
6606 11:36:56.760723 CA PerBit enable=1, Macro0, CA PI delay=36
6607 11:36:56.761222
6608 11:36:56.764120 [CBTSetCACLKResult] CA Dly = 36
6609 11:36:56.767557 CS Dly: 1 (0~32)
6610 11:36:56.768008 ==
6611 11:36:56.770446 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 11:36:56.773637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:36:56.774023 ==
6614 11:36:56.780829 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 11:36:56.786927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6616 11:36:56.790266 [CA 0] Center 36 (8~64) winsize 57
6617 11:36:56.790734 [CA 1] Center 36 (8~64) winsize 57
6618 11:36:56.794418 [CA 2] Center 36 (8~64) winsize 57
6619 11:36:56.797109 [CA 3] Center 36 (8~64) winsize 57
6620 11:36:56.800056 [CA 4] Center 36 (8~64) winsize 57
6621 11:36:56.803619 [CA 5] Center 36 (8~64) winsize 57
6622 11:36:56.804045
6623 11:36:56.807499 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6624 11:36:56.807940
6625 11:36:56.813253 [CATrainingPosCal] consider 2 rank data
6626 11:36:56.813782 u2DelayCellTimex100 = 270/100 ps
6627 11:36:56.819704 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:36:56.823279 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:36:56.826535 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:36:56.829795 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:36:56.832888 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:36:56.836852 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:36:56.837362
6634 11:36:56.840045 CA PerBit enable=1, Macro0, CA PI delay=36
6635 11:36:56.840471
6636 11:36:56.842950 [CBTSetCACLKResult] CA Dly = 36
6637 11:36:56.846524 CS Dly: 1 (0~32)
6638 11:36:56.847061
6639 11:36:56.849596 ----->DramcWriteLeveling(PI) begin...
6640 11:36:56.849991 ==
6641 11:36:56.852902 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:36:56.856449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:36:56.856940 ==
6644 11:36:56.859651 Write leveling (Byte 0): 40 => 8
6645 11:36:56.862551 Write leveling (Byte 1): 40 => 8
6646 11:36:56.866582 DramcWriteLeveling(PI) end<-----
6647 11:36:56.867052
6648 11:36:56.867354 ==
6649 11:36:56.869317 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:36:56.873107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:36:56.873757 ==
6652 11:36:56.876532 [Gating] SW mode calibration
6653 11:36:56.883183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 11:36:56.889326 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 11:36:56.892652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 11:36:56.895968 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:36:56.902241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 11:36:56.905692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:36:56.909103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:36:56.915815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:36:56.919056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:36:56.921986 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:36:56.928348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:36:56.931632 Total UI for P1: 0, mck2ui 16
6665 11:36:56.935042 best dqsien dly found for B0: ( 0, 14, 24)
6666 11:36:56.938808 Total UI for P1: 0, mck2ui 16
6667 11:36:56.941536 best dqsien dly found for B1: ( 0, 14, 24)
6668 11:36:56.945233 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 11:36:56.948466 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:36:56.949005
6671 11:36:56.951871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 11:36:56.954722 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:36:56.958170 [Gating] SW calibration Done
6674 11:36:56.958550 ==
6675 11:36:56.961592 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 11:36:56.965038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:36:56.968808 ==
6678 11:36:56.969354 RX Vref Scan: 0
6679 11:36:56.969690
6680 11:36:56.971413 RX Vref 0 -> 0, step: 1
6681 11:36:56.971922
6682 11:36:56.974957 RX Delay -410 -> 252, step: 16
6683 11:36:56.978078 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6684 11:36:56.981663 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6685 11:36:56.984946 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6686 11:36:56.991824 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6687 11:36:56.994765 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6688 11:36:56.997886 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6689 11:36:57.001516 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6690 11:36:57.007370 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6691 11:36:57.011100 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6692 11:36:57.014702 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6693 11:36:57.017802 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6694 11:36:57.024285 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6695 11:36:57.027631 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6696 11:36:57.031270 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6697 11:36:57.037387 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6698 11:36:57.040245 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6699 11:36:57.040673 ==
6700 11:36:57.043737 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:36:57.047625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:36:57.048135 ==
6703 11:36:57.050501 DQS Delay:
6704 11:36:57.051027 DQS0 = 43, DQS1 = 51
6705 11:36:57.053474 DQM Delay:
6706 11:36:57.053896 DQM0 = 13, DQM1 = 13
6707 11:36:57.054224 DQ Delay:
6708 11:36:57.056884 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6709 11:36:57.060911 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6710 11:36:57.063524 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 11:36:57.067491 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6712 11:36:57.067953
6713 11:36:57.068344
6714 11:36:57.068627 ==
6715 11:36:57.070342 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 11:36:57.076817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 11:36:57.077299 ==
6718 11:36:57.077606
6719 11:36:57.077882
6720 11:36:57.078141 TX Vref Scan disable
6721 11:36:57.080549 == TX Byte 0 ==
6722 11:36:57.083229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:36:57.087080 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:36:57.090262 == TX Byte 1 ==
6725 11:36:57.093613 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 11:36:57.096494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 11:36:57.096962 ==
6728 11:36:57.099962 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:36:57.106368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:36:57.106861 ==
6731 11:36:57.107194
6732 11:36:57.107499
6733 11:36:57.107836 TX Vref Scan disable
6734 11:36:57.109831 == TX Byte 0 ==
6735 11:36:57.113228 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:36:57.116459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:36:57.119630 == TX Byte 1 ==
6738 11:36:57.123196 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 11:36:57.126872 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 11:36:57.129521
6741 11:36:57.129902 [DATLAT]
6742 11:36:57.130202 Freq=400, CH1 RK0
6743 11:36:57.130480
6744 11:36:57.133175 DATLAT Default: 0xf
6745 11:36:57.133661 0, 0xFFFF, sum = 0
6746 11:36:57.136604 1, 0xFFFF, sum = 0
6747 11:36:57.137077 2, 0xFFFF, sum = 0
6748 11:36:57.139448 3, 0xFFFF, sum = 0
6749 11:36:57.139917 4, 0xFFFF, sum = 0
6750 11:36:57.142544 5, 0xFFFF, sum = 0
6751 11:36:57.146292 6, 0xFFFF, sum = 0
6752 11:36:57.146684 7, 0xFFFF, sum = 0
6753 11:36:57.149029 8, 0xFFFF, sum = 0
6754 11:36:57.149512 9, 0xFFFF, sum = 0
6755 11:36:57.152963 10, 0xFFFF, sum = 0
6756 11:36:57.153556 11, 0xFFFF, sum = 0
6757 11:36:57.155953 12, 0xFFFF, sum = 0
6758 11:36:57.156344 13, 0x0, sum = 1
6759 11:36:57.159251 14, 0x0, sum = 2
6760 11:36:57.159640 15, 0x0, sum = 3
6761 11:36:57.163131 16, 0x0, sum = 4
6762 11:36:57.163607 best_step = 14
6763 11:36:57.163994
6764 11:36:57.164278 ==
6765 11:36:57.165823 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:36:57.169295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:36:57.171953 ==
6768 11:36:57.172536 RX Vref Scan: 1
6769 11:36:57.173099
6770 11:36:57.175993 RX Vref 0 -> 0, step: 1
6771 11:36:57.176459
6772 11:36:57.179315 RX Delay -343 -> 252, step: 8
6773 11:36:57.179776
6774 11:36:57.182602 Set Vref, RX VrefLevel [Byte0]: 51
6775 11:36:57.185958 [Byte1]: 51
6776 11:36:57.186477
6777 11:36:57.189235 Final RX Vref Byte 0 = 51 to rank0
6778 11:36:57.192365 Final RX Vref Byte 1 = 51 to rank0
6779 11:36:57.195674 Final RX Vref Byte 0 = 51 to rank1
6780 11:36:57.198866 Final RX Vref Byte 1 = 51 to rank1==
6781 11:36:57.201787 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:36:57.205125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:36:57.205666 ==
6784 11:36:57.208679 DQS Delay:
6785 11:36:57.209062 DQS0 = 44, DQS1 = 52
6786 11:36:57.212393 DQM Delay:
6787 11:36:57.212778 DQM0 = 10, DQM1 = 10
6788 11:36:57.215303 DQ Delay:
6789 11:36:57.215766 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6790 11:36:57.218775 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6791 11:36:57.221468 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6792 11:36:57.225169 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6793 11:36:57.225639
6794 11:36:57.225957
6795 11:36:57.235559 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6796 11:36:57.238560 CH1 RK0: MR19=C0C, MR18=6A90
6797 11:36:57.241340 CH1_RK0: MR19=0xC0C, MR18=0x6A90, DQSOSC=391, MR23=63, INC=386, DEC=257
6798 11:36:57.245182 ==
6799 11:36:57.248550 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 11:36:57.251508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:36:57.252007 ==
6802 11:36:57.255125 [Gating] SW mode calibration
6803 11:36:57.261549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 11:36:57.265088 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 11:36:57.271102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 11:36:57.274716 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:36:57.278452 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 11:36:57.285031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:36:57.287598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 11:36:57.291315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:36:57.297662 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:36:57.301031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:36:57.304266 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:36:57.307382 Total UI for P1: 0, mck2ui 16
6815 11:36:57.310566 best dqsien dly found for B0: ( 0, 14, 24)
6816 11:36:57.313948 Total UI for P1: 0, mck2ui 16
6817 11:36:57.317198 best dqsien dly found for B1: ( 0, 14, 24)
6818 11:36:57.320741 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 11:36:57.327618 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:36:57.328136
6821 11:36:57.330644 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 11:36:57.333818 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:36:57.336844 [Gating] SW calibration Done
6824 11:36:57.337256 ==
6825 11:36:57.340113 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 11:36:57.344357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 11:36:57.344838 ==
6828 11:36:57.346921 RX Vref Scan: 0
6829 11:36:57.347306
6830 11:36:57.347603 RX Vref 0 -> 0, step: 1
6831 11:36:57.347881
6832 11:36:57.350368 RX Delay -410 -> 252, step: 16
6833 11:36:57.356887 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6834 11:36:57.360463 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6835 11:36:57.363714 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6836 11:36:57.367179 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6837 11:36:57.373550 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6838 11:36:57.376608 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6839 11:36:57.380510 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6840 11:36:57.383221 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6841 11:36:57.389997 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6842 11:36:57.393115 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6843 11:36:57.396156 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6844 11:36:57.399761 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6845 11:36:57.406250 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6846 11:36:57.409553 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6847 11:36:57.413114 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6848 11:36:57.419659 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6849 11:36:57.420161 ==
6850 11:36:57.422417 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:36:57.425965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:36:57.426405 ==
6853 11:36:57.426788 DQS Delay:
6854 11:36:57.429488 DQS0 = 43, DQS1 = 51
6855 11:36:57.429956 DQM Delay:
6856 11:36:57.432991 DQM0 = 9, DQM1 = 14
6857 11:36:57.433559 DQ Delay:
6858 11:36:57.436058 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6859 11:36:57.438714 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6860 11:36:57.442589 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6861 11:36:57.446005 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6862 11:36:57.446390
6863 11:36:57.446686
6864 11:36:57.446962 ==
6865 11:36:57.448918 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 11:36:57.452456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:36:57.452935 ==
6868 11:36:57.453295
6869 11:36:57.453586
6870 11:36:57.455768 TX Vref Scan disable
6871 11:36:57.456150 == TX Byte 0 ==
6872 11:36:57.462254 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6873 11:36:57.465561 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6874 11:36:57.466043 == TX Byte 1 ==
6875 11:36:57.472034 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 11:36:57.475610 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 11:36:57.476116 ==
6878 11:36:57.479220 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 11:36:57.482445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:36:57.482952 ==
6881 11:36:57.483347
6882 11:36:57.483669
6883 11:36:57.485042 TX Vref Scan disable
6884 11:36:57.488719 == TX Byte 0 ==
6885 11:36:57.492038 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6886 11:36:57.495244 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6887 11:36:57.498837 == TX Byte 1 ==
6888 11:36:57.501612 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 11:36:57.504836 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 11:36:57.505259
6891 11:36:57.505576 [DATLAT]
6892 11:36:57.508264 Freq=400, CH1 RK1
6893 11:36:57.508650
6894 11:36:57.508946 DATLAT Default: 0xe
6895 11:36:57.511424 0, 0xFFFF, sum = 0
6896 11:36:57.511852 1, 0xFFFF, sum = 0
6897 11:36:57.514695 2, 0xFFFF, sum = 0
6898 11:36:57.518240 3, 0xFFFF, sum = 0
6899 11:36:57.518631 4, 0xFFFF, sum = 0
6900 11:36:57.521639 5, 0xFFFF, sum = 0
6901 11:36:57.522127 6, 0xFFFF, sum = 0
6902 11:36:57.525201 7, 0xFFFF, sum = 0
6903 11:36:57.525596 8, 0xFFFF, sum = 0
6904 11:36:57.528240 9, 0xFFFF, sum = 0
6905 11:36:57.528705 10, 0xFFFF, sum = 0
6906 11:36:57.531726 11, 0xFFFF, sum = 0
6907 11:36:57.532113 12, 0xFFFF, sum = 0
6908 11:36:57.534629 13, 0x0, sum = 1
6909 11:36:57.535022 14, 0x0, sum = 2
6910 11:36:57.538430 15, 0x0, sum = 3
6911 11:36:57.538851 16, 0x0, sum = 4
6912 11:36:57.541789 best_step = 14
6913 11:36:57.542170
6914 11:36:57.542464 ==
6915 11:36:57.544683 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:36:57.548025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:36:57.548493 ==
6918 11:36:57.551725 RX Vref Scan: 0
6919 11:36:57.552189
6920 11:36:57.552489 RX Vref 0 -> 0, step: 1
6921 11:36:57.552768
6922 11:36:57.554370 RX Delay -343 -> 252, step: 8
6923 11:36:57.562599 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6924 11:36:57.565593 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6925 11:36:57.568997 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6926 11:36:57.575347 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6927 11:36:57.578473 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6928 11:36:57.582288 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6929 11:36:57.585311 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6930 11:36:57.591689 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6931 11:36:57.594852 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6932 11:36:57.598539 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6933 11:36:57.601667 iDelay=217, Bit 10, Center -36 (-279 ~ 208) 488
6934 11:36:57.608421 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6935 11:36:57.611381 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6936 11:36:57.614418 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6937 11:36:57.618465 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6938 11:36:57.624377 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6939 11:36:57.624767 ==
6940 11:36:57.627566 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:36:57.631108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:36:57.631632 ==
6943 11:36:57.634443 DQS Delay:
6944 11:36:57.634825 DQS0 = 48, DQS1 = 56
6945 11:36:57.635120 DQM Delay:
6946 11:36:57.637465 DQM0 = 11, DQM1 = 14
6947 11:36:57.637852 DQ Delay:
6948 11:36:57.640874 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6949 11:36:57.644321 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6950 11:36:57.648140 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6951 11:36:57.650603 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6952 11:36:57.650989
6953 11:36:57.651283
6954 11:36:57.660880 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6955 11:36:57.661383 CH1 RK1: MR19=C0C, MR18=7EB5
6956 11:36:57.667460 CH1_RK1: MR19=0xC0C, MR18=0x7EB5, DQSOSC=387, MR23=63, INC=394, DEC=262
6957 11:36:57.670653 [RxdqsGatingPostProcess] freq 400
6958 11:36:57.677431 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 11:36:57.680596 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 11:36:57.684570 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 11:36:57.686853 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 11:36:57.690487 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 11:36:57.693416 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 11:36:57.696891 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 11:36:57.700290 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 11:36:57.703840 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 11:36:57.704234 Pre-setting of DQS Precalculation
6968 11:36:57.710353 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 11:36:57.716524 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 11:36:57.723516 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 11:36:57.724012
6972 11:36:57.726259
6973 11:36:57.726640 [Calibration Summary] 800 Mbps
6974 11:36:57.729605 CH 0, Rank 0
6975 11:36:57.730049 SW Impedance : PASS
6976 11:36:57.732835 DUTY Scan : NO K
6977 11:36:57.736091 ZQ Calibration : PASS
6978 11:36:57.736489 Jitter Meter : NO K
6979 11:36:57.739731 CBT Training : PASS
6980 11:36:57.743134 Write leveling : PASS
6981 11:36:57.743522 RX DQS gating : PASS
6982 11:36:57.746133 RX DQ/DQS(RDDQC) : PASS
6983 11:36:57.749422 TX DQ/DQS : PASS
6984 11:36:57.749822 RX DATLAT : PASS
6985 11:36:57.752953 RX DQ/DQS(Engine): PASS
6986 11:36:57.755957 TX OE : NO K
6987 11:36:57.756354 All Pass.
6988 11:36:57.756810
6989 11:36:57.757300 CH 0, Rank 1
6990 11:36:57.759295 SW Impedance : PASS
6991 11:36:57.762422 DUTY Scan : NO K
6992 11:36:57.762819 ZQ Calibration : PASS
6993 11:36:57.766049 Jitter Meter : NO K
6994 11:36:57.768740 CBT Training : PASS
6995 11:36:57.769022 Write leveling : NO K
6996 11:36:57.771916 RX DQS gating : PASS
6997 11:36:57.775308 RX DQ/DQS(RDDQC) : PASS
6998 11:36:57.775522 TX DQ/DQS : PASS
6999 11:36:57.778722 RX DATLAT : PASS
7000 11:36:57.778935 RX DQ/DQS(Engine): PASS
7001 11:36:57.781861 TX OE : NO K
7002 11:36:57.781999 All Pass.
7003 11:36:57.782105
7004 11:36:57.785443 CH 1, Rank 0
7005 11:36:57.788309 SW Impedance : PASS
7006 11:36:57.788427 DUTY Scan : NO K
7007 11:36:57.791948 ZQ Calibration : PASS
7008 11:36:57.792052 Jitter Meter : NO K
7009 11:36:57.795525 CBT Training : PASS
7010 11:36:57.798118 Write leveling : PASS
7011 11:36:57.798211 RX DQS gating : PASS
7012 11:36:57.801381 RX DQ/DQS(RDDQC) : PASS
7013 11:36:57.805142 TX DQ/DQS : PASS
7014 11:36:57.805236 RX DATLAT : PASS
7015 11:36:57.808206 RX DQ/DQS(Engine): PASS
7016 11:36:57.811613 TX OE : NO K
7017 11:36:57.811707 All Pass.
7018 11:36:57.811779
7019 11:36:57.811845 CH 1, Rank 1
7020 11:36:57.815192 SW Impedance : PASS
7021 11:36:57.818208 DUTY Scan : NO K
7022 11:36:57.818301 ZQ Calibration : PASS
7023 11:36:57.821291 Jitter Meter : NO K
7024 11:36:57.825027 CBT Training : PASS
7025 11:36:57.825120 Write leveling : NO K
7026 11:36:57.828004 RX DQS gating : PASS
7027 11:36:57.831473 RX DQ/DQS(RDDQC) : PASS
7028 11:36:57.831566 TX DQ/DQS : PASS
7029 11:36:57.834690 RX DATLAT : PASS
7030 11:36:57.838006 RX DQ/DQS(Engine): PASS
7031 11:36:57.838100 TX OE : NO K
7032 11:36:57.841159 All Pass.
7033 11:36:57.841252
7034 11:36:57.841323 DramC Write-DBI off
7035 11:36:57.844692 PER_BANK_REFRESH: Hybrid Mode
7036 11:36:57.844786 TX_TRACKING: ON
7037 11:36:57.854712 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 11:36:57.857668 [FAST_K] Save calibration result to emmc
7039 11:36:57.860852 dramc_set_vcore_voltage set vcore to 725000
7040 11:36:57.864083 Read voltage for 1600, 0
7041 11:36:57.864176 Vio18 = 0
7042 11:36:57.867752 Vcore = 725000
7043 11:36:57.867845 Vdram = 0
7044 11:36:57.867917 Vddq = 0
7045 11:36:57.870772 Vmddr = 0
7046 11:36:57.874064 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 11:36:57.881047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 11:36:57.881149 MEM_TYPE=3, freq_sel=13
7049 11:36:57.883780 sv_algorithm_assistance_LP4_3733
7050 11:36:57.890373 ============ PULL DRAM RESETB DOWN ============
7051 11:36:57.893656 ========== PULL DRAM RESETB DOWN end =========
7052 11:36:57.897237 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 11:36:57.901093 ===================================
7054 11:36:57.904117 LPDDR4 DRAM CONFIGURATION
7055 11:36:57.907301 ===================================
7056 11:36:57.910942 EX_ROW_EN[0] = 0x0
7057 11:36:57.911429 EX_ROW_EN[1] = 0x0
7058 11:36:57.914185 LP4Y_EN = 0x0
7059 11:36:57.914568 WORK_FSP = 0x1
7060 11:36:57.917467 WL = 0x5
7061 11:36:57.917853 RL = 0x5
7062 11:36:57.920447 BL = 0x2
7063 11:36:57.920911 RPST = 0x0
7064 11:36:57.923771 RD_PRE = 0x0
7065 11:36:57.924176 WR_PRE = 0x1
7066 11:36:57.927555 WR_PST = 0x1
7067 11:36:57.928047 DBI_WR = 0x0
7068 11:36:57.930789 DBI_RD = 0x0
7069 11:36:57.933376 OTF = 0x1
7070 11:36:57.937229 ===================================
7071 11:36:57.940579 ===================================
7072 11:36:57.941043 ANA top config
7073 11:36:57.944069 ===================================
7074 11:36:57.947361 DLL_ASYNC_EN = 0
7075 11:36:57.947827 ALL_SLAVE_EN = 0
7076 11:36:57.950407 NEW_RANK_MODE = 1
7077 11:36:57.953445 DLL_IDLE_MODE = 1
7078 11:36:57.957039 LP45_APHY_COMB_EN = 1
7079 11:36:57.959999 TX_ODT_DIS = 0
7080 11:36:57.960465 NEW_8X_MODE = 1
7081 11:36:57.963517 ===================================
7082 11:36:57.966873 ===================================
7083 11:36:57.969545 data_rate = 3200
7084 11:36:57.973604 CKR = 1
7085 11:36:57.976783 DQ_P2S_RATIO = 8
7086 11:36:57.979601 ===================================
7087 11:36:57.983176 CA_P2S_RATIO = 8
7088 11:36:57.986055 DQ_CA_OPEN = 0
7089 11:36:57.986471 DQ_SEMI_OPEN = 0
7090 11:36:57.989263 CA_SEMI_OPEN = 0
7091 11:36:57.993276 CA_FULL_RATE = 0
7092 11:36:57.996221 DQ_CKDIV4_EN = 0
7093 11:36:57.999308 CA_CKDIV4_EN = 0
7094 11:36:58.002574 CA_PREDIV_EN = 0
7095 11:36:58.006060 PH8_DLY = 12
7096 11:36:58.006442 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 11:36:58.009059 DQ_AAMCK_DIV = 4
7098 11:36:58.012685 CA_AAMCK_DIV = 4
7099 11:36:58.015846 CA_ADMCK_DIV = 4
7100 11:36:58.019216 DQ_TRACK_CA_EN = 0
7101 11:36:58.022464 CA_PICK = 1600
7102 11:36:58.025192 CA_MCKIO = 1600
7103 11:36:58.025408 MCKIO_SEMI = 0
7104 11:36:58.028700 PLL_FREQ = 3068
7105 11:36:58.032438 DQ_UI_PI_RATIO = 32
7106 11:36:58.035641 CA_UI_PI_RATIO = 0
7107 11:36:58.038950 ===================================
7108 11:36:58.042173 ===================================
7109 11:36:58.045085 memory_type:LPDDR4
7110 11:36:58.045220 GP_NUM : 10
7111 11:36:58.048776 SRAM_EN : 1
7112 11:36:58.051638 MD32_EN : 0
7113 11:36:58.055060 ===================================
7114 11:36:58.055179 [ANA_INIT] >>>>>>>>>>>>>>
7115 11:36:58.058276 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 11:36:58.061458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 11:36:58.065121 ===================================
7118 11:36:58.068164 data_rate = 3200,PCW = 0X7600
7119 11:36:58.071378 ===================================
7120 11:36:58.075073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 11:36:58.081686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 11:36:58.084884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:36:58.091205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 11:36:58.095006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 11:36:58.097692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:36:58.101061 [ANA_INIT] flow start
7127 11:36:58.101171 [ANA_INIT] PLL >>>>>>>>
7128 11:36:58.104659 [ANA_INIT] PLL <<<<<<<<
7129 11:36:58.107434 [ANA_INIT] MIDPI >>>>>>>>
7130 11:36:58.107531 [ANA_INIT] MIDPI <<<<<<<<
7131 11:36:58.111077 [ANA_INIT] DLL >>>>>>>>
7132 11:36:58.114355 [ANA_INIT] DLL <<<<<<<<
7133 11:36:58.114429 [ANA_INIT] flow end
7134 11:36:58.121345 ============ LP4 DIFF to SE enter ============
7135 11:36:58.124732 ============ LP4 DIFF to SE exit ============
7136 11:36:58.127403 [ANA_INIT] <<<<<<<<<<<<<
7137 11:36:58.130456 [Flow] Enable top DCM control >>>>>
7138 11:36:58.134042 [Flow] Enable top DCM control <<<<<
7139 11:36:58.134117 Enable DLL master slave shuffle
7140 11:36:58.140569 ==============================================================
7141 11:36:58.143992 Gating Mode config
7142 11:36:58.147087 ==============================================================
7143 11:36:58.150392 Config description:
7144 11:36:58.160187 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 11:36:58.166654 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 11:36:58.170376 SELPH_MODE 0: By rank 1: By Phase
7147 11:36:58.176853 ==============================================================
7148 11:36:58.180493 GAT_TRACK_EN = 1
7149 11:36:58.183580 RX_GATING_MODE = 2
7150 11:36:58.187088 RX_GATING_TRACK_MODE = 2
7151 11:36:58.190185 SELPH_MODE = 1
7152 11:36:58.193468 PICG_EARLY_EN = 1
7153 11:36:58.196686 VALID_LAT_VALUE = 1
7154 11:36:58.200157 ==============================================================
7155 11:36:58.203388 Enter into Gating configuration >>>>
7156 11:36:58.206588 Exit from Gating configuration <<<<
7157 11:36:58.209758 Enter into DVFS_PRE_config >>>>>
7158 11:36:58.220164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 11:36:58.223454 Exit from DVFS_PRE_config <<<<<
7160 11:36:58.226534 Enter into PICG configuration >>>>
7161 11:36:58.229458 Exit from PICG configuration <<<<
7162 11:36:58.233309 [RX_INPUT] configuration >>>>>
7163 11:36:58.236770 [RX_INPUT] configuration <<<<<
7164 11:36:58.242622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 11:36:58.246167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 11:36:58.253437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 11:36:58.259541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 11:36:58.265902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 11:36:58.272949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 11:36:58.276365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 11:36:58.279370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 11:36:58.282590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 11:36:58.288857 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 11:36:58.292826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 11:36:58.295543 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 11:36:58.299031 ===================================
7177 11:36:58.302241 LPDDR4 DRAM CONFIGURATION
7178 11:36:58.305527 ===================================
7179 11:36:58.308861 EX_ROW_EN[0] = 0x0
7180 11:36:58.309269 EX_ROW_EN[1] = 0x0
7181 11:36:58.312213 LP4Y_EN = 0x0
7182 11:36:58.312712 WORK_FSP = 0x1
7183 11:36:58.315450 WL = 0x5
7184 11:36:58.315834 RL = 0x5
7185 11:36:58.318417 BL = 0x2
7186 11:36:58.318801 RPST = 0x0
7187 11:36:58.322356 RD_PRE = 0x0
7188 11:36:58.322940 WR_PRE = 0x1
7189 11:36:58.325189 WR_PST = 0x1
7190 11:36:58.328273 DBI_WR = 0x0
7191 11:36:58.328727 DBI_RD = 0x0
7192 11:36:58.331732 OTF = 0x1
7193 11:36:58.335019 ===================================
7194 11:36:58.338378 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 11:36:58.341936 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 11:36:58.344810 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 11:36:58.348249 ===================================
7198 11:36:58.351694 LPDDR4 DRAM CONFIGURATION
7199 11:36:58.354948 ===================================
7200 11:36:58.358058 EX_ROW_EN[0] = 0x10
7201 11:36:58.358439 EX_ROW_EN[1] = 0x0
7202 11:36:58.361112 LP4Y_EN = 0x0
7203 11:36:58.361531 WORK_FSP = 0x1
7204 11:36:58.364884 WL = 0x5
7205 11:36:58.365315 RL = 0x5
7206 11:36:58.367806 BL = 0x2
7207 11:36:58.368181 RPST = 0x0
7208 11:36:58.371198 RD_PRE = 0x0
7209 11:36:58.371622 WR_PRE = 0x1
7210 11:36:58.375182 WR_PST = 0x1
7211 11:36:58.377868 DBI_WR = 0x0
7212 11:36:58.378251 DBI_RD = 0x0
7213 11:36:58.381788 OTF = 0x1
7214 11:36:58.384990 ===================================
7215 11:36:58.387817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 11:36:58.390859 ==
7217 11:36:58.394291 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 11:36:58.397876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 11:36:58.398265 ==
7220 11:36:58.401154 [Duty_Offset_Calibration]
7221 11:36:58.401622 B0:2 B1:0 CA:4
7222 11:36:58.401923
7223 11:36:58.404342 [DutyScan_Calibration_Flow] k_type=0
7224 11:36:58.413732
7225 11:36:58.414232 ==CLK 0==
7226 11:36:58.416903 Final CLK duty delay cell = -4
7227 11:36:58.420897 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7228 11:36:58.423520 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7229 11:36:58.426935 [-4] AVG Duty = 4937%(X100)
7230 11:36:58.427457
7231 11:36:58.430148 CH0 CLK Duty spec in!! Max-Min= 187%
7232 11:36:58.433088 [DutyScan_Calibration_Flow] ====Done====
7233 11:36:58.433517
7234 11:36:58.436758 [DutyScan_Calibration_Flow] k_type=1
7235 11:36:58.453852
7236 11:36:58.454380 ==DQS 0 ==
7237 11:36:58.456770 Final DQS duty delay cell = 0
7238 11:36:58.459921 [0] MAX Duty = 5218%(X100), DQS PI = 38
7239 11:36:58.463731 [0] MIN Duty = 5093%(X100), DQS PI = 6
7240 11:36:58.466923 [0] AVG Duty = 5155%(X100)
7241 11:36:58.467309
7242 11:36:58.467610 ==DQS 1 ==
7243 11:36:58.469923 Final DQS duty delay cell = 0
7244 11:36:58.473838 [0] MAX Duty = 5187%(X100), DQS PI = 2
7245 11:36:58.477166 [0] MIN Duty = 4969%(X100), DQS PI = 12
7246 11:36:58.480274 [0] AVG Duty = 5078%(X100)
7247 11:36:58.480728
7248 11:36:58.484159 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7249 11:36:58.484655
7250 11:36:58.486841 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7251 11:36:58.490503 [DutyScan_Calibration_Flow] ====Done====
7252 11:36:58.491004
7253 11:36:58.493654 [DutyScan_Calibration_Flow] k_type=3
7254 11:36:58.511230
7255 11:36:58.511721 ==DQM 0 ==
7256 11:36:58.514193 Final DQM duty delay cell = 0
7257 11:36:58.517335 [0] MAX Duty = 5124%(X100), DQS PI = 20
7258 11:36:58.520769 [0] MIN Duty = 4844%(X100), DQS PI = 56
7259 11:36:58.524259 [0] AVG Duty = 4984%(X100)
7260 11:36:58.524750
7261 11:36:58.525083 ==DQM 1 ==
7262 11:36:58.527523 Final DQM duty delay cell = 0
7263 11:36:58.530881 [0] MAX Duty = 5000%(X100), DQS PI = 4
7264 11:36:58.534538 [0] MIN Duty = 4844%(X100), DQS PI = 14
7265 11:36:58.537552 [0] AVG Duty = 4922%(X100)
7266 11:36:58.538048
7267 11:36:58.540553 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7268 11:36:58.540977
7269 11:36:58.543628 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7270 11:36:58.547257 [DutyScan_Calibration_Flow] ====Done====
7271 11:36:58.547666
7272 11:36:58.550526 [DutyScan_Calibration_Flow] k_type=2
7273 11:36:58.568062
7274 11:36:58.568524 ==DQ 0 ==
7275 11:36:58.570962 Final DQ duty delay cell = 0
7276 11:36:58.574350 [0] MAX Duty = 5156%(X100), DQS PI = 26
7277 11:36:58.577903 [0] MIN Duty = 4938%(X100), DQS PI = 12
7278 11:36:58.578287 [0] AVG Duty = 5047%(X100)
7279 11:36:58.581243
7280 11:36:58.581694 ==DQ 1 ==
7281 11:36:58.584752 Final DQ duty delay cell = 0
7282 11:36:58.587851 [0] MAX Duty = 5187%(X100), DQS PI = 2
7283 11:36:58.590846 [0] MIN Duty = 4907%(X100), DQS PI = 34
7284 11:36:58.591229 [0] AVG Duty = 5047%(X100)
7285 11:36:58.594416
7286 11:36:58.597526 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7287 11:36:58.597909
7288 11:36:58.601000 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7289 11:36:58.603848 [DutyScan_Calibration_Flow] ====Done====
7290 11:36:58.604268 ==
7291 11:36:58.607593 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 11:36:58.610519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 11:36:58.610907 ==
7294 11:36:58.614293 [Duty_Offset_Calibration]
7295 11:36:58.614751 B0:0 B1:-1 CA:3
7296 11:36:58.615098
7297 11:36:58.617541 [DutyScan_Calibration_Flow] k_type=0
7298 11:36:58.627982
7299 11:36:58.628422 ==CLK 0==
7300 11:36:58.631265 Final CLK duty delay cell = 0
7301 11:36:58.634468 [0] MAX Duty = 5187%(X100), DQS PI = 4
7302 11:36:58.637968 [0] MIN Duty = 5000%(X100), DQS PI = 54
7303 11:36:58.641310 [0] AVG Duty = 5093%(X100)
7304 11:36:58.641693
7305 11:36:58.644783 CH1 CLK Duty spec in!! Max-Min= 187%
7306 11:36:58.647565 [DutyScan_Calibration_Flow] ====Done====
7307 11:36:58.647945
7308 11:36:58.651156 [DutyScan_Calibration_Flow] k_type=1
7309 11:36:58.667210
7310 11:36:58.667662 ==DQS 0 ==
7311 11:36:58.670011 Final DQS duty delay cell = 0
7312 11:36:58.673783 [0] MAX Duty = 5218%(X100), DQS PI = 20
7313 11:36:58.677085 [0] MIN Duty = 4938%(X100), DQS PI = 40
7314 11:36:58.681339 [0] AVG Duty = 5078%(X100)
7315 11:36:58.681793
7316 11:36:58.682268 ==DQS 1 ==
7317 11:36:58.683042 Final DQS duty delay cell = -4
7318 11:36:58.687217 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7319 11:36:58.690110 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7320 11:36:58.693309 [-4] AVG Duty = 4906%(X100)
7321 11:36:58.693792
7322 11:36:58.696684 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7323 11:36:58.697065
7324 11:36:58.699983 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7325 11:36:58.703015 [DutyScan_Calibration_Flow] ====Done====
7326 11:36:58.703576
7327 11:36:58.706683 [DutyScan_Calibration_Flow] k_type=3
7328 11:36:58.723951
7329 11:36:58.724328 ==DQM 0 ==
7330 11:36:58.727343 Final DQM duty delay cell = 0
7331 11:36:58.730562 [0] MAX Duty = 5031%(X100), DQS PI = 30
7332 11:36:58.733877 [0] MIN Duty = 4750%(X100), DQS PI = 40
7333 11:36:58.737191 [0] AVG Duty = 4890%(X100)
7334 11:36:58.737593
7335 11:36:58.737925 ==DQM 1 ==
7336 11:36:58.740535 Final DQM duty delay cell = 0
7337 11:36:58.743595 [0] MAX Duty = 4969%(X100), DQS PI = 30
7338 11:36:58.747416 [0] MIN Duty = 4813%(X100), DQS PI = 62
7339 11:36:58.751031 [0] AVG Duty = 4891%(X100)
7340 11:36:58.751312
7341 11:36:58.753338 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7342 11:36:58.753610
7343 11:36:58.756732 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7344 11:36:58.759859 [DutyScan_Calibration_Flow] ====Done====
7345 11:36:58.760228
7346 11:36:58.763286 [DutyScan_Calibration_Flow] k_type=2
7347 11:36:58.779691
7348 11:36:58.779966 ==DQ 0 ==
7349 11:36:58.783283 Final DQ duty delay cell = -4
7350 11:36:58.786628 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7351 11:36:58.789923 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7352 11:36:58.792937 [-4] AVG Duty = 4891%(X100)
7353 11:36:58.793099
7354 11:36:58.793249 ==DQ 1 ==
7355 11:36:58.796334 Final DQ duty delay cell = 0
7356 11:36:58.799546 [0] MAX Duty = 5031%(X100), DQS PI = 32
7357 11:36:58.802784 [0] MIN Duty = 4844%(X100), DQS PI = 58
7358 11:36:58.806555 [0] AVG Duty = 4937%(X100)
7359 11:36:58.806697
7360 11:36:58.809526 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7361 11:36:58.809663
7362 11:36:58.812836 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7363 11:36:58.815759 [DutyScan_Calibration_Flow] ====Done====
7364 11:36:58.819700 nWR fixed to 30
7365 11:36:58.822579 [ModeRegInit_LP4] CH0 RK0
7366 11:36:58.822762 [ModeRegInit_LP4] CH0 RK1
7367 11:36:58.826364 [ModeRegInit_LP4] CH1 RK0
7368 11:36:58.828988 [ModeRegInit_LP4] CH1 RK1
7369 11:36:58.829109 match AC timing 5
7370 11:36:58.835868 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 11:36:58.838868 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 11:36:58.842412 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 11:36:58.849414 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 11:36:58.852339 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 11:36:58.855551 [MiockJmeterHQA]
7376 11:36:58.855687
7377 11:36:58.858931 [DramcMiockJmeter] u1RxGatingPI = 0
7378 11:36:58.859068 0 : 4257, 4029
7379 11:36:58.859176 4 : 4252, 4027
7380 11:36:58.862254 8 : 4258, 4031
7381 11:36:58.862393 12 : 4253, 4026
7382 11:36:58.865596 16 : 4255, 4029
7383 11:36:58.865735 20 : 4253, 4026
7384 11:36:58.868547 24 : 4252, 4027
7385 11:36:58.868686 28 : 4365, 4140
7386 11:36:58.868794 32 : 4255, 4030
7387 11:36:58.871854 36 : 4252, 4027
7388 11:36:58.871993 40 : 4253, 4026
7389 11:36:58.875336 44 : 4365, 4140
7390 11:36:58.875476 48 : 4365, 4140
7391 11:36:58.878568 52 : 4253, 4026
7392 11:36:58.878716 56 : 4252, 4027
7393 11:36:58.881907 60 : 4255, 4030
7394 11:36:58.882026 64 : 4253, 4029
7395 11:36:58.884999 68 : 4255, 4029
7396 11:36:58.885119 72 : 4363, 4140
7397 11:36:58.885227 76 : 4250, 4026
7398 11:36:58.888212 80 : 4250, 4027
7399 11:36:58.888333 84 : 4250, 4027
7400 11:36:58.891757 88 : 4252, 4029
7401 11:36:58.891879 92 : 4250, 4027
7402 11:36:58.895228 96 : 4360, 2640
7403 11:36:58.895350 100 : 4250, 0
7404 11:36:58.895444 104 : 4249, 0
7405 11:36:58.898525 108 : 4361, 0
7406 11:36:58.898646 112 : 4360, 0
7407 11:36:58.901559 116 : 4250, 0
7408 11:36:58.901680 120 : 4250, 0
7409 11:36:58.901775 124 : 4250, 0
7410 11:36:58.904719 128 : 4252, 0
7411 11:36:58.904839 132 : 4250, 0
7412 11:36:58.908239 136 : 4250, 0
7413 11:36:58.908360 140 : 4252, 0
7414 11:36:58.908454 144 : 4361, 0
7415 11:36:58.911486 148 : 4250, 0
7416 11:36:58.911607 152 : 4361, 0
7417 11:36:58.914779 156 : 4250, 0
7418 11:36:58.914942 160 : 4361, 0
7419 11:36:58.915109 164 : 4250, 0
7420 11:36:58.918355 168 : 4249, 0
7421 11:36:58.918515 172 : 4250, 0
7422 11:36:58.918652 176 : 4250, 0
7423 11:36:58.921669 180 : 4250, 0
7424 11:36:58.921790 184 : 4249, 0
7425 11:36:58.924620 188 : 4250, 0
7426 11:36:58.924741 192 : 4252, 0
7427 11:36:58.924834 196 : 4363, 0
7428 11:36:58.927995 200 : 4250, 0
7429 11:36:58.928156 204 : 4361, 0
7430 11:36:58.931107 208 : 4249, 0
7431 11:36:58.931231 212 : 4360, 0
7432 11:36:58.931334 216 : 4250, 0
7433 11:36:58.934597 220 : 4250, 458
7434 11:36:58.934718 224 : 4250, 3997
7435 11:36:58.937859 228 : 4363, 4140
7436 11:36:58.937980 232 : 4360, 4137
7437 11:36:58.941270 236 : 4250, 4027
7438 11:36:58.941405 240 : 4250, 4027
7439 11:36:58.944588 244 : 4360, 4138
7440 11:36:58.944730 248 : 4250, 4026
7441 11:36:58.948109 252 : 4250, 4027
7442 11:36:58.948314 256 : 4250, 4027
7443 11:36:58.951276 260 : 4250, 4027
7444 11:36:58.951452 264 : 4250, 4027
7445 11:36:58.951587 268 : 4250, 4027
7446 11:36:58.954402 272 : 4250, 4027
7447 11:36:58.954578 276 : 4250, 4026
7448 11:36:58.957807 280 : 4361, 4137
7449 11:36:58.958017 284 : 4361, 4137
7450 11:36:58.961403 288 : 4250, 4027
7451 11:36:58.961734 292 : 4250, 4027
7452 11:36:58.964635 296 : 4360, 4138
7453 11:36:58.964960 300 : 4254, 4030
7454 11:36:58.968239 304 : 4250, 4027
7455 11:36:58.968643 308 : 4366, 4142
7456 11:36:58.971651 312 : 4250, 4027
7457 11:36:58.972123 316 : 4250, 4026
7458 11:36:58.974385 320 : 4250, 4027
7459 11:36:58.974774 324 : 4250, 4027
7460 11:36:58.978058 328 : 4250, 4027
7461 11:36:58.978525 332 : 4360, 4067
7462 11:36:58.978829 336 : 4361, 1621
7463 11:36:58.981429
7464 11:36:58.981811 MIOCK jitter meter ch=0
7465 11:36:58.982109
7466 11:36:58.984726 1T = (336-100) = 236 dly cells
7467 11:36:58.991304 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7468 11:36:58.991721 ==
7469 11:36:58.995069 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 11:36:58.997777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 11:36:58.998170 ==
7472 11:36:59.003899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 11:36:59.007519 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 11:36:59.010654 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 11:36:59.017429 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 11:36:59.027077 [CA 0] Center 44 (14~74) winsize 61
7477 11:36:59.029819 [CA 1] Center 43 (13~74) winsize 62
7478 11:36:59.033539 [CA 2] Center 38 (9~68) winsize 60
7479 11:36:59.036774 [CA 3] Center 38 (9~68) winsize 60
7480 11:36:59.040094 [CA 4] Center 36 (7~66) winsize 60
7481 11:36:59.043423 [CA 5] Center 36 (6~66) winsize 61
7482 11:36:59.043805
7483 11:36:59.046724 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 11:36:59.047108
7485 11:36:59.049632 [CATrainingPosCal] consider 1 rank data
7486 11:36:59.053458 u2DelayCellTimex100 = 275/100 ps
7487 11:36:59.059942 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7488 11:36:59.063457 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7489 11:36:59.066829 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7490 11:36:59.069604 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7491 11:36:59.072666 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7492 11:36:59.076055 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7493 11:36:59.076565
7494 11:36:59.079651 CA PerBit enable=1, Macro0, CA PI delay=36
7495 11:36:59.080195
7496 11:36:59.082862 [CBTSetCACLKResult] CA Dly = 36
7497 11:36:59.086365 CS Dly: 11 (0~42)
7498 11:36:59.089592 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 11:36:59.092672 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 11:36:59.092944 ==
7501 11:36:59.096242 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 11:36:59.103052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 11:36:59.103270 ==
7504 11:36:59.105668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 11:36:59.112572 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 11:36:59.115464 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 11:36:59.122712 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 11:36:59.129708 [CA 0] Center 43 (13~74) winsize 62
7509 11:36:59.133087 [CA 1] Center 43 (13~74) winsize 62
7510 11:36:59.136780 [CA 2] Center 38 (9~68) winsize 60
7511 11:36:59.139797 [CA 3] Center 38 (9~68) winsize 60
7512 11:36:59.143336 [CA 4] Center 36 (6~66) winsize 61
7513 11:36:59.146408 [CA 5] Center 36 (6~66) winsize 61
7514 11:36:59.146512
7515 11:36:59.149738 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 11:36:59.149843
7517 11:36:59.156044 [CATrainingPosCal] consider 2 rank data
7518 11:36:59.156149 u2DelayCellTimex100 = 275/100 ps
7519 11:36:59.162949 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7520 11:36:59.166017 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7521 11:36:59.169499 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7522 11:36:59.172654 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7523 11:36:59.176211 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 11:36:59.179303 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7525 11:36:59.179409
7526 11:36:59.182504 CA PerBit enable=1, Macro0, CA PI delay=36
7527 11:36:59.182615
7528 11:36:59.185801 [CBTSetCACLKResult] CA Dly = 36
7529 11:36:59.189184 CS Dly: 12 (0~44)
7530 11:36:59.192251 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 11:36:59.195765 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 11:36:59.195869
7533 11:36:59.199103 ----->DramcWriteLeveling(PI) begin...
7534 11:36:59.199209 ==
7535 11:36:59.202208 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 11:36:59.209390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 11:36:59.209495 ==
7538 11:36:59.211900 Write leveling (Byte 0): 34 => 34
7539 11:36:59.215206 Write leveling (Byte 1): 27 => 27
7540 11:36:59.219011 DramcWriteLeveling(PI) end<-----
7541 11:36:59.219116
7542 11:36:59.219195 ==
7543 11:36:59.222119 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 11:36:59.225102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 11:36:59.225214 ==
7546 11:36:59.228684 [Gating] SW mode calibration
7547 11:36:59.235508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 11:36:59.242400 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 11:36:59.245233 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 11:36:59.248833 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 11:36:59.255521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 11:36:59.258226 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7553 11:36:59.261721 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7554 11:36:59.268362 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7555 11:36:59.271857 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 11:36:59.274713 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 11:36:59.281770 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:36:59.285326 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 11:36:59.289377 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7560 11:36:59.295116 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7561 11:36:59.298167 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7562 11:36:59.301874 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7563 11:36:59.305316 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7564 11:36:59.312043 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 11:36:59.314818 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:36:59.318293 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:36:59.324487 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7568 11:36:59.327741 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 11:36:59.334757 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7570 11:36:59.337757 1 6 20 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
7571 11:36:59.341084 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 11:36:59.347666 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 11:36:59.351439 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:36:59.354716 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:36:59.360713 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:36:59.364295 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 11:36:59.367228 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7578 11:36:59.374320 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 11:36:59.377396 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 11:36:59.381544 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:36:59.387560 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:36:59.390365 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:36:59.393502 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:36:59.400462 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:36:59.403680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:36:59.407032 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:36:59.413619 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:36:59.416867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:36:59.420550 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:36:59.426755 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:36:59.429660 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 11:36:59.433252 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 11:36:59.439320 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7594 11:36:59.439401 Total UI for P1: 0, mck2ui 16
7595 11:36:59.446433 best dqsien dly found for B0: ( 1, 9, 10)
7596 11:36:59.449194 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 11:36:59.452290 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 11:36:59.456162 Total UI for P1: 0, mck2ui 16
7599 11:36:59.459323 best dqsien dly found for B1: ( 1, 9, 20)
7600 11:36:59.463004 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 11:36:59.465885 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7602 11:36:59.466051
7603 11:36:59.472882 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 11:36:59.475830 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7605 11:36:59.479258 [Gating] SW calibration Done
7606 11:36:59.479477 ==
7607 11:36:59.482329 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 11:36:59.485564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 11:36:59.485791 ==
7610 11:36:59.485941 RX Vref Scan: 0
7611 11:36:59.486077
7612 11:36:59.488864 RX Vref 0 -> 0, step: 1
7613 11:36:59.489174
7614 11:36:59.492005 RX Delay 0 -> 252, step: 8
7615 11:36:59.495726 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7616 11:36:59.498771 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7617 11:36:59.505841 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7618 11:36:59.509252 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7619 11:36:59.512255 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7620 11:36:59.515556 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7621 11:36:59.518868 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7622 11:36:59.525110 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7623 11:36:59.528721 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7624 11:36:59.532305 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7625 11:36:59.535584 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7626 11:36:59.539101 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7627 11:36:59.545303 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7628 11:36:59.548546 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7629 11:36:59.551237 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7630 11:36:59.554779 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7631 11:36:59.558024 ==
7632 11:36:59.558423 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 11:36:59.564283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 11:36:59.564670 ==
7635 11:36:59.564967 DQS Delay:
7636 11:36:59.568025 DQS0 = 0, DQS1 = 0
7637 11:36:59.568444 DQM Delay:
7638 11:36:59.571033 DQM0 = 131, DQM1 = 125
7639 11:36:59.571418 DQ Delay:
7640 11:36:59.574485 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7641 11:36:59.577827 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7642 11:36:59.581528 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7643 11:36:59.584542 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7644 11:36:59.584954
7645 11:36:59.585314
7646 11:36:59.585598 ==
7647 11:36:59.588517 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 11:36:59.594320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 11:36:59.594709 ==
7650 11:36:59.595008
7651 11:36:59.595282
7652 11:36:59.595541 TX Vref Scan disable
7653 11:36:59.598184 == TX Byte 0 ==
7654 11:36:59.601276 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7655 11:36:59.607976 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7656 11:36:59.608424 == TX Byte 1 ==
7657 11:36:59.611112 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7658 11:36:59.617700 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7659 11:36:59.618288 ==
7660 11:36:59.621047 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 11:36:59.624455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 11:36:59.624910 ==
7663 11:36:59.637870
7664 11:36:59.641206 TX Vref early break, caculate TX vref
7665 11:36:59.644565 TX Vref=16, minBit 1, minWin=22, winSum=368
7666 11:36:59.647453 TX Vref=18, minBit 8, minWin=22, winSum=386
7667 11:36:59.650767 TX Vref=20, minBit 1, minWin=23, winSum=389
7668 11:36:59.654056 TX Vref=22, minBit 1, minWin=24, winSum=403
7669 11:36:59.657292 TX Vref=24, minBit 0, minWin=25, winSum=412
7670 11:36:59.664020 TX Vref=26, minBit 1, minWin=25, winSum=419
7671 11:36:59.667189 TX Vref=28, minBit 2, minWin=25, winSum=421
7672 11:36:59.670312 TX Vref=30, minBit 2, minWin=25, winSum=420
7673 11:36:59.673394 TX Vref=32, minBit 4, minWin=24, winSum=410
7674 11:36:59.677370 TX Vref=34, minBit 0, minWin=24, winSum=397
7675 11:36:59.683676 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7676 11:36:59.684176
7677 11:36:59.686443 Final TX Range 0 Vref 28
7678 11:36:59.686826
7679 11:36:59.687120 ==
7680 11:36:59.689614 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 11:36:59.693174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 11:36:59.693611 ==
7683 11:36:59.694013
7684 11:36:59.696353
7685 11:36:59.696801 TX Vref Scan disable
7686 11:36:59.703457 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7687 11:36:59.703941 == TX Byte 0 ==
7688 11:36:59.706644 u2DelayCellOfst[0]=10 cells (3 PI)
7689 11:36:59.709383 u2DelayCellOfst[1]=14 cells (4 PI)
7690 11:36:59.713360 u2DelayCellOfst[2]=7 cells (2 PI)
7691 11:36:59.716095 u2DelayCellOfst[3]=10 cells (3 PI)
7692 11:36:59.719660 u2DelayCellOfst[4]=7 cells (2 PI)
7693 11:36:59.722758 u2DelayCellOfst[5]=0 cells (0 PI)
7694 11:36:59.726223 u2DelayCellOfst[6]=14 cells (4 PI)
7695 11:36:59.729666 u2DelayCellOfst[7]=14 cells (4 PI)
7696 11:36:59.733022 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7697 11:36:59.736469 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7698 11:36:59.739246 == TX Byte 1 ==
7699 11:36:59.742653 u2DelayCellOfst[8]=0 cells (0 PI)
7700 11:36:59.745674 u2DelayCellOfst[9]=0 cells (0 PI)
7701 11:36:59.749477 u2DelayCellOfst[10]=7 cells (2 PI)
7702 11:36:59.752179 u2DelayCellOfst[11]=3 cells (1 PI)
7703 11:36:59.756356 u2DelayCellOfst[12]=7 cells (2 PI)
7704 11:36:59.756812 u2DelayCellOfst[13]=10 cells (3 PI)
7705 11:36:59.759231 u2DelayCellOfst[14]=14 cells (4 PI)
7706 11:36:59.762234 u2DelayCellOfst[15]=10 cells (3 PI)
7707 11:36:59.769248 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7708 11:36:59.772353 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7709 11:36:59.775699 DramC Write-DBI on
7710 11:36:59.776132 ==
7711 11:36:59.778807 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 11:36:59.781945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 11:36:59.782332 ==
7714 11:36:59.782628
7715 11:36:59.782896
7716 11:36:59.785274 TX Vref Scan disable
7717 11:36:59.785660 == TX Byte 0 ==
7718 11:36:59.792037 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7719 11:36:59.792492 == TX Byte 1 ==
7720 11:36:59.795231 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7721 11:36:59.798446 DramC Write-DBI off
7722 11:36:59.798829
7723 11:36:59.799126 [DATLAT]
7724 11:36:59.801432 Freq=1600, CH0 RK0
7725 11:36:59.801900
7726 11:36:59.802349 DATLAT Default: 0xf
7727 11:36:59.804820 0, 0xFFFF, sum = 0
7728 11:36:59.808452 1, 0xFFFF, sum = 0
7729 11:36:59.808842 2, 0xFFFF, sum = 0
7730 11:36:59.811716 3, 0xFFFF, sum = 0
7731 11:36:59.812105 4, 0xFFFF, sum = 0
7732 11:36:59.814819 5, 0xFFFF, sum = 0
7733 11:36:59.815208 6, 0xFFFF, sum = 0
7734 11:36:59.818002 7, 0xFFFF, sum = 0
7735 11:36:59.818388 8, 0xFFFF, sum = 0
7736 11:36:59.821486 9, 0xFFFF, sum = 0
7737 11:36:59.821879 10, 0xFFFF, sum = 0
7738 11:36:59.825064 11, 0xFFFF, sum = 0
7739 11:36:59.825572 12, 0xFFFF, sum = 0
7740 11:36:59.828633 13, 0xFFFF, sum = 0
7741 11:36:59.829093 14, 0x0, sum = 1
7742 11:36:59.831595 15, 0x0, sum = 2
7743 11:36:59.832168 16, 0x0, sum = 3
7744 11:36:59.834982 17, 0x0, sum = 4
7745 11:36:59.835447 best_step = 15
7746 11:36:59.835745
7747 11:36:59.836022 ==
7748 11:36:59.837729 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 11:36:59.844773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 11:36:59.845267 ==
7751 11:36:59.845575 RX Vref Scan: 1
7752 11:36:59.845851
7753 11:36:59.847685 Set Vref Range= 24 -> 127
7754 11:36:59.848064
7755 11:36:59.850835 RX Vref 24 -> 127, step: 1
7756 11:36:59.851218
7757 11:36:59.854260 RX Delay 11 -> 252, step: 4
7758 11:36:59.854645
7759 11:36:59.854941 Set Vref, RX VrefLevel [Byte0]: 24
7760 11:36:59.858105 [Byte1]: 24
7761 11:36:59.862226
7762 11:36:59.862682 Set Vref, RX VrefLevel [Byte0]: 25
7763 11:36:59.865611 [Byte1]: 25
7764 11:36:59.869828
7765 11:36:59.870213 Set Vref, RX VrefLevel [Byte0]: 26
7766 11:36:59.872942 [Byte1]: 26
7767 11:36:59.877628
7768 11:36:59.878011 Set Vref, RX VrefLevel [Byte0]: 27
7769 11:36:59.880295 [Byte1]: 27
7770 11:36:59.885040
7771 11:36:59.885535 Set Vref, RX VrefLevel [Byte0]: 28
7772 11:36:59.887955 [Byte1]: 28
7773 11:36:59.892482
7774 11:36:59.893006 Set Vref, RX VrefLevel [Byte0]: 29
7775 11:36:59.895905 [Byte1]: 29
7776 11:36:59.899735
7777 11:36:59.900122 Set Vref, RX VrefLevel [Byte0]: 30
7778 11:36:59.903377 [Byte1]: 30
7779 11:36:59.907439
7780 11:36:59.907822 Set Vref, RX VrefLevel [Byte0]: 31
7781 11:36:59.910666 [Byte1]: 31
7782 11:36:59.915563
7783 11:36:59.915946 Set Vref, RX VrefLevel [Byte0]: 32
7784 11:36:59.918287 [Byte1]: 32
7785 11:36:59.923006
7786 11:36:59.923520 Set Vref, RX VrefLevel [Byte0]: 33
7787 11:36:59.926221 [Byte1]: 33
7788 11:36:59.930515
7789 11:36:59.930966 Set Vref, RX VrefLevel [Byte0]: 34
7790 11:36:59.933825 [Byte1]: 34
7791 11:36:59.938434
7792 11:36:59.938891 Set Vref, RX VrefLevel [Byte0]: 35
7793 11:36:59.941407 [Byte1]: 35
7794 11:36:59.946256
7795 11:36:59.946710 Set Vref, RX VrefLevel [Byte0]: 36
7796 11:36:59.949287 [Byte1]: 36
7797 11:36:59.953234
7798 11:36:59.953691 Set Vref, RX VrefLevel [Byte0]: 37
7799 11:36:59.956764 [Byte1]: 37
7800 11:36:59.960933
7801 11:36:59.961441 Set Vref, RX VrefLevel [Byte0]: 38
7802 11:36:59.964328 [Byte1]: 38
7803 11:36:59.968659
7804 11:36:59.969217 Set Vref, RX VrefLevel [Byte0]: 39
7805 11:36:59.971779 [Byte1]: 39
7806 11:36:59.976642
7807 11:36:59.977025 Set Vref, RX VrefLevel [Byte0]: 40
7808 11:36:59.982607 [Byte1]: 40
7809 11:36:59.982991
7810 11:36:59.985981 Set Vref, RX VrefLevel [Byte0]: 41
7811 11:36:59.989226 [Byte1]: 41
7812 11:36:59.989685
7813 11:36:59.992498 Set Vref, RX VrefLevel [Byte0]: 42
7814 11:36:59.996122 [Byte1]: 42
7815 11:36:59.999405
7816 11:36:59.999862 Set Vref, RX VrefLevel [Byte0]: 43
7817 11:37:00.002836 [Byte1]: 43
7818 11:37:00.007529
7819 11:37:00.007985 Set Vref, RX VrefLevel [Byte0]: 44
7820 11:37:00.009827 [Byte1]: 44
7821 11:37:00.014319
7822 11:37:00.014714 Set Vref, RX VrefLevel [Byte0]: 45
7823 11:37:00.017573 [Byte1]: 45
7824 11:37:00.021906
7825 11:37:00.022360 Set Vref, RX VrefLevel [Byte0]: 46
7826 11:37:00.025254 [Byte1]: 46
7827 11:37:00.029524
7828 11:37:00.029985 Set Vref, RX VrefLevel [Byte0]: 47
7829 11:37:00.032711 [Byte1]: 47
7830 11:37:00.036815
7831 11:37:00.037235 Set Vref, RX VrefLevel [Byte0]: 48
7832 11:37:00.040618 [Byte1]: 48
7833 11:37:00.044853
7834 11:37:00.045353 Set Vref, RX VrefLevel [Byte0]: 49
7835 11:37:00.048478 [Byte1]: 49
7836 11:37:00.052852
7837 11:37:00.053360 Set Vref, RX VrefLevel [Byte0]: 50
7838 11:37:00.055506 [Byte1]: 50
7839 11:37:00.059639
7840 11:37:00.060022 Set Vref, RX VrefLevel [Byte0]: 51
7841 11:37:00.063402 [Byte1]: 51
7842 11:37:00.067866
7843 11:37:00.068325 Set Vref, RX VrefLevel [Byte0]: 52
7844 11:37:00.070784 [Byte1]: 52
7845 11:37:00.075249
7846 11:37:00.075703 Set Vref, RX VrefLevel [Byte0]: 53
7847 11:37:00.078509 [Byte1]: 53
7848 11:37:00.082837
7849 11:37:00.083221 Set Vref, RX VrefLevel [Byte0]: 54
7850 11:37:00.086240 [Byte1]: 54
7851 11:37:00.090461
7852 11:37:00.090913 Set Vref, RX VrefLevel [Byte0]: 55
7853 11:37:00.093711 [Byte1]: 55
7854 11:37:00.098064
7855 11:37:00.098517 Set Vref, RX VrefLevel [Byte0]: 56
7856 11:37:00.101272 [Byte1]: 56
7857 11:37:00.105875
7858 11:37:00.106330 Set Vref, RX VrefLevel [Byte0]: 57
7859 11:37:00.109243 [Byte1]: 57
7860 11:37:00.113786
7861 11:37:00.114177 Set Vref, RX VrefLevel [Byte0]: 58
7862 11:37:00.116745 [Byte1]: 58
7863 11:37:00.120701
7864 11:37:00.121250 Set Vref, RX VrefLevel [Byte0]: 59
7865 11:37:00.124269 [Byte1]: 59
7866 11:37:00.128614
7867 11:37:00.129109 Set Vref, RX VrefLevel [Byte0]: 60
7868 11:37:00.132371 [Byte1]: 60
7869 11:37:00.136110
7870 11:37:00.136600 Set Vref, RX VrefLevel [Byte0]: 61
7871 11:37:00.139779 [Byte1]: 61
7872 11:37:00.144091
7873 11:37:00.146545 Set Vref, RX VrefLevel [Byte0]: 62
7874 11:37:00.150134 [Byte1]: 62
7875 11:37:00.150531
7876 11:37:00.153414 Set Vref, RX VrefLevel [Byte0]: 63
7877 11:37:00.157180 [Byte1]: 63
7878 11:37:00.157819
7879 11:37:00.160060 Set Vref, RX VrefLevel [Byte0]: 64
7880 11:37:00.163457 [Byte1]: 64
7881 11:37:00.163837
7882 11:37:00.166623 Set Vref, RX VrefLevel [Byte0]: 65
7883 11:37:00.170085 [Byte1]: 65
7884 11:37:00.174927
7885 11:37:00.175383 Set Vref, RX VrefLevel [Byte0]: 66
7886 11:37:00.177594 [Byte1]: 66
7887 11:37:00.181862
7888 11:37:00.182244 Set Vref, RX VrefLevel [Byte0]: 67
7889 11:37:00.185094 [Byte1]: 67
7890 11:37:00.189994
7891 11:37:00.190506 Set Vref, RX VrefLevel [Byte0]: 68
7892 11:37:00.192488 [Byte1]: 68
7893 11:37:00.197224
7894 11:37:00.197691 Set Vref, RX VrefLevel [Byte0]: 69
7895 11:37:00.200815 [Byte1]: 69
7896 11:37:00.204768
7897 11:37:00.205176 Set Vref, RX VrefLevel [Byte0]: 70
7898 11:37:00.207657 [Byte1]: 70
7899 11:37:00.211962
7900 11:37:00.212348 Set Vref, RX VrefLevel [Byte0]: 71
7901 11:37:00.215154 [Byte1]: 71
7902 11:37:00.219693
7903 11:37:00.220074 Set Vref, RX VrefLevel [Byte0]: 72
7904 11:37:00.223312 [Byte1]: 72
7905 11:37:00.227510
7906 11:37:00.227957 Set Vref, RX VrefLevel [Byte0]: 73
7907 11:37:00.230416 [Byte1]: 73
7908 11:37:00.235115
7909 11:37:00.235498 Set Vref, RX VrefLevel [Byte0]: 74
7910 11:37:00.237968 [Byte1]: 74
7911 11:37:00.243200
7912 11:37:00.246121 Set Vref, RX VrefLevel [Byte0]: 75
7913 11:37:00.246678 [Byte1]: 75
7914 11:37:00.250517
7915 11:37:00.250970 Set Vref, RX VrefLevel [Byte0]: 76
7916 11:37:00.253819 [Byte1]: 76
7917 11:37:00.257609
7918 11:37:00.257993 Set Vref, RX VrefLevel [Byte0]: 77
7919 11:37:00.261032 [Byte1]: 77
7920 11:37:00.265801
7921 11:37:00.266184 Final RX Vref Byte 0 = 55 to rank0
7922 11:37:00.269028 Final RX Vref Byte 1 = 58 to rank0
7923 11:37:00.271948 Final RX Vref Byte 0 = 55 to rank1
7924 11:37:00.275260 Final RX Vref Byte 1 = 58 to rank1==
7925 11:37:00.278474 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 11:37:00.285472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 11:37:00.285949 ==
7928 11:37:00.286253 DQS Delay:
7929 11:37:00.288448 DQS0 = 0, DQS1 = 0
7930 11:37:00.288905 DQM Delay:
7931 11:37:00.291778 DQM0 = 128, DQM1 = 124
7932 11:37:00.292231 DQ Delay:
7933 11:37:00.295164 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7934 11:37:00.298620 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7935 11:37:00.301549 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7936 11:37:00.304953 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7937 11:37:00.305452
7938 11:37:00.305752
7939 11:37:00.306027
7940 11:37:00.308178 [DramC_TX_OE_Calibration] TA2
7941 11:37:00.311366 Original DQ_B0 (3 6) =30, OEN = 27
7942 11:37:00.315486 Original DQ_B1 (3 6) =30, OEN = 27
7943 11:37:00.317949 24, 0x0, End_B0=24 End_B1=24
7944 11:37:00.321614 25, 0x0, End_B0=25 End_B1=25
7945 11:37:00.322017 26, 0x0, End_B0=26 End_B1=26
7946 11:37:00.324811 27, 0x0, End_B0=27 End_B1=27
7947 11:37:00.328000 28, 0x0, End_B0=28 End_B1=28
7948 11:37:00.331048 29, 0x0, End_B0=29 End_B1=29
7949 11:37:00.331494 30, 0x0, End_B0=30 End_B1=30
7950 11:37:00.334825 31, 0x4545, End_B0=30 End_B1=30
7951 11:37:00.337804 Byte0 end_step=30 best_step=27
7952 11:37:00.341599 Byte1 end_step=30 best_step=27
7953 11:37:00.344840 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 11:37:00.347934 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 11:37:00.348329
7956 11:37:00.348623
7957 11:37:00.354489 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
7958 11:37:00.358504 CH0 RK0: MR19=303, MR18=1B18
7959 11:37:00.364613 CH0_RK0: MR19=0x303, MR18=0x1B18, DQSOSC=396, MR23=63, INC=23, DEC=15
7960 11:37:00.364998
7961 11:37:00.367570 ----->DramcWriteLeveling(PI) begin...
7962 11:37:00.367958 ==
7963 11:37:00.370740 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 11:37:00.373384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 11:37:00.373810 ==
7966 11:37:00.376926 Write leveling (Byte 0): 36 => 36
7967 11:37:00.380112 Write leveling (Byte 1): 28 => 28
7968 11:37:00.383843 DramcWriteLeveling(PI) end<-----
7969 11:37:00.384367
7970 11:37:00.384793 ==
7971 11:37:00.386902 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 11:37:00.393338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 11:37:00.393730 ==
7974 11:37:00.394028 [Gating] SW mode calibration
7975 11:37:00.404296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 11:37:00.407264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 11:37:00.413273 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 11:37:00.416781 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 11:37:00.419956 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7980 11:37:00.427296 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7981 11:37:00.429932 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7982 11:37:00.434294 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 11:37:00.439998 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 11:37:00.443284 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 11:37:00.446820 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 11:37:00.453041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7987 11:37:00.456910 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7988 11:37:00.459771 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7989 11:37:00.466654 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7990 11:37:00.469519 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7991 11:37:00.472950 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 11:37:00.478949 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 11:37:00.482720 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 11:37:00.485943 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7995 11:37:00.492879 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7996 11:37:00.496032 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7997 11:37:00.499029 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7998 11:37:00.506006 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7999 11:37:00.509206 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 11:37:00.512655 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 11:37:00.518856 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 11:37:00.522080 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 11:37:00.525327 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8004 11:37:00.532174 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8005 11:37:00.535121 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8006 11:37:00.538231 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8007 11:37:00.544712 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8008 11:37:00.548026 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:37:00.552420 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:37:00.558745 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:37:00.561165 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:37:00.564865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:37:00.571162 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:37:00.574551 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:37:00.577429 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:37:00.584788 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:37:00.587989 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:37:00.590795 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8019 11:37:00.597983 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 11:37:00.600963 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8021 11:37:00.604310 Total UI for P1: 0, mck2ui 16
8022 11:37:00.607330 best dqsien dly found for B0: ( 1, 9, 6)
8023 11:37:00.610601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8024 11:37:00.617753 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 11:37:00.620629 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 11:37:00.623779 Total UI for P1: 0, mck2ui 16
8027 11:37:00.627054 best dqsien dly found for B1: ( 1, 9, 18)
8028 11:37:00.630524 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8029 11:37:00.633578 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8030 11:37:00.633965
8031 11:37:00.636567 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8032 11:37:00.640373 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8033 11:37:00.643952 [Gating] SW calibration Done
8034 11:37:00.644408 ==
8035 11:37:00.646855 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 11:37:00.653370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 11:37:00.653828 ==
8038 11:37:00.654132 RX Vref Scan: 0
8039 11:37:00.654409
8040 11:37:00.657114 RX Vref 0 -> 0, step: 1
8041 11:37:00.657533
8042 11:37:00.660624 RX Delay 0 -> 252, step: 8
8043 11:37:00.663386 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8044 11:37:00.666472 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8045 11:37:00.670070 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8046 11:37:00.676413 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8047 11:37:00.679994 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8048 11:37:00.683284 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8049 11:37:00.686522 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8050 11:37:00.689705 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8051 11:37:00.696450 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8052 11:37:00.699938 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8053 11:37:00.703201 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8054 11:37:00.706069 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8055 11:37:00.709057 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8056 11:37:00.715552 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8057 11:37:00.718885 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8058 11:37:00.722465 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8059 11:37:00.722882 ==
8060 11:37:00.725726 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 11:37:00.728850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 11:37:00.732722 ==
8063 11:37:00.733105 DQS Delay:
8064 11:37:00.733447 DQS0 = 0, DQS1 = 0
8065 11:37:00.735585 DQM Delay:
8066 11:37:00.735990 DQM0 = 131, DQM1 = 124
8067 11:37:00.738746 DQ Delay:
8068 11:37:00.742107 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8069 11:37:00.745360 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8070 11:37:00.748834 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8071 11:37:00.752463 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8072 11:37:00.752922
8073 11:37:00.753262
8074 11:37:00.753547 ==
8075 11:37:00.755287 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 11:37:00.759136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 11:37:00.759600 ==
8078 11:37:00.761872
8079 11:37:00.762254
8080 11:37:00.762550 TX Vref Scan disable
8081 11:37:00.765370 == TX Byte 0 ==
8082 11:37:00.768671 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8083 11:37:00.772674 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8084 11:37:00.775051 == TX Byte 1 ==
8085 11:37:00.778334 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8086 11:37:00.781950 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8087 11:37:00.782340 ==
8088 11:37:00.785223 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 11:37:00.791599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 11:37:00.792046 ==
8091 11:37:00.804953
8092 11:37:00.808039 TX Vref early break, caculate TX vref
8093 11:37:00.810874 TX Vref=16, minBit 2, minWin=23, winSum=382
8094 11:37:00.814193 TX Vref=18, minBit 3, minWin=23, winSum=390
8095 11:37:00.818028 TX Vref=20, minBit 3, minWin=23, winSum=394
8096 11:37:00.820948 TX Vref=22, minBit 4, minWin=24, winSum=404
8097 11:37:00.824362 TX Vref=24, minBit 1, minWin=25, winSum=415
8098 11:37:00.831105 TX Vref=26, minBit 3, minWin=25, winSum=421
8099 11:37:00.834038 TX Vref=28, minBit 3, minWin=25, winSum=418
8100 11:37:00.837429 TX Vref=30, minBit 1, minWin=25, winSum=419
8101 11:37:00.840878 TX Vref=32, minBit 0, minWin=24, winSum=406
8102 11:37:00.844338 TX Vref=34, minBit 0, minWin=24, winSum=398
8103 11:37:00.850968 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 26
8104 11:37:00.851424
8105 11:37:00.853809 Final TX Range 0 Vref 26
8106 11:37:00.854195
8107 11:37:00.854494 ==
8108 11:37:00.857342 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:37:00.860692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:37:00.861206 ==
8111 11:37:00.861521
8112 11:37:00.861796
8113 11:37:00.864030 TX Vref Scan disable
8114 11:37:00.870632 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8115 11:37:00.871091 == TX Byte 0 ==
8116 11:37:00.874170 u2DelayCellOfst[0]=10 cells (3 PI)
8117 11:37:00.877199 u2DelayCellOfst[1]=14 cells (4 PI)
8118 11:37:00.880623 u2DelayCellOfst[2]=7 cells (2 PI)
8119 11:37:00.883703 u2DelayCellOfst[3]=10 cells (3 PI)
8120 11:37:00.887592 u2DelayCellOfst[4]=7 cells (2 PI)
8121 11:37:00.890615 u2DelayCellOfst[5]=0 cells (0 PI)
8122 11:37:00.894010 u2DelayCellOfst[6]=14 cells (4 PI)
8123 11:37:00.896755 u2DelayCellOfst[7]=14 cells (4 PI)
8124 11:37:00.900344 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8125 11:37:00.903545 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8126 11:37:00.906459 == TX Byte 1 ==
8127 11:37:00.910023 u2DelayCellOfst[8]=3 cells (1 PI)
8128 11:37:00.913021 u2DelayCellOfst[9]=0 cells (0 PI)
8129 11:37:00.913443 u2DelayCellOfst[10]=7 cells (2 PI)
8130 11:37:00.916958 u2DelayCellOfst[11]=7 cells (2 PI)
8131 11:37:00.920238 u2DelayCellOfst[12]=14 cells (4 PI)
8132 11:37:00.923279 u2DelayCellOfst[13]=14 cells (4 PI)
8133 11:37:00.926672 u2DelayCellOfst[14]=17 cells (5 PI)
8134 11:37:00.929833 u2DelayCellOfst[15]=14 cells (4 PI)
8135 11:37:00.936526 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8136 11:37:00.940026 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8137 11:37:00.940412 DramC Write-DBI on
8138 11:37:00.940712 ==
8139 11:37:00.943141 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 11:37:00.949481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 11:37:00.950007 ==
8142 11:37:00.950373
8143 11:37:00.950656
8144 11:37:00.950919 TX Vref Scan disable
8145 11:37:00.953668 == TX Byte 0 ==
8146 11:37:00.957018 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8147 11:37:00.960557 == TX Byte 1 ==
8148 11:37:00.963760 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8149 11:37:00.967197 DramC Write-DBI off
8150 11:37:00.967662
8151 11:37:00.967967 [DATLAT]
8152 11:37:00.968246 Freq=1600, CH0 RK1
8153 11:37:00.968514
8154 11:37:00.970331 DATLAT Default: 0xf
8155 11:37:00.973402 0, 0xFFFF, sum = 0
8156 11:37:00.973788 1, 0xFFFF, sum = 0
8157 11:37:00.977095 2, 0xFFFF, sum = 0
8158 11:37:00.977612 3, 0xFFFF, sum = 0
8159 11:37:00.980289 4, 0xFFFF, sum = 0
8160 11:37:00.980674 5, 0xFFFF, sum = 0
8161 11:37:00.983842 6, 0xFFFF, sum = 0
8162 11:37:00.984303 7, 0xFFFF, sum = 0
8163 11:37:00.987040 8, 0xFFFF, sum = 0
8164 11:37:00.987509 9, 0xFFFF, sum = 0
8165 11:37:00.989994 10, 0xFFFF, sum = 0
8166 11:37:00.990382 11, 0xFFFF, sum = 0
8167 11:37:00.993498 12, 0xFFFF, sum = 0
8168 11:37:00.993887 13, 0xFFFF, sum = 0
8169 11:37:00.996877 14, 0x0, sum = 1
8170 11:37:00.997287 15, 0x0, sum = 2
8171 11:37:01.000580 16, 0x0, sum = 3
8172 11:37:01.001054 17, 0x0, sum = 4
8173 11:37:01.003466 best_step = 15
8174 11:37:01.003918
8175 11:37:01.004214 ==
8176 11:37:01.006671 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 11:37:01.010373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 11:37:01.010777 ==
8179 11:37:01.013513 RX Vref Scan: 0
8180 11:37:01.013956
8181 11:37:01.014261 RX Vref 0 -> 0, step: 1
8182 11:37:01.014541
8183 11:37:01.016344 RX Delay 11 -> 252, step: 4
8184 11:37:01.023823 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8185 11:37:01.026023 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8186 11:37:01.029637 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8187 11:37:01.032913 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8188 11:37:01.036431 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8189 11:37:01.043405 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8190 11:37:01.046371 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8191 11:37:01.049550 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8192 11:37:01.052787 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8193 11:37:01.056017 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8194 11:37:01.062752 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8195 11:37:01.065537 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8196 11:37:01.069310 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8197 11:37:01.072183 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8198 11:37:01.079126 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8199 11:37:01.082971 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8200 11:37:01.083444 ==
8201 11:37:01.085796 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 11:37:01.089069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 11:37:01.089571 ==
8204 11:37:01.092343 DQS Delay:
8205 11:37:01.092799 DQS0 = 0, DQS1 = 0
8206 11:37:01.093099 DQM Delay:
8207 11:37:01.095961 DQM0 = 128, DQM1 = 124
8208 11:37:01.096417 DQ Delay:
8209 11:37:01.099110 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8210 11:37:01.102440 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8211 11:37:01.105417 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
8212 11:37:01.111794 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8213 11:37:01.112239
8214 11:37:01.112536
8215 11:37:01.112809
8216 11:37:01.115193 [DramC_TX_OE_Calibration] TA2
8217 11:37:01.118408 Original DQ_B0 (3 6) =30, OEN = 27
8218 11:37:01.118795 Original DQ_B1 (3 6) =30, OEN = 27
8219 11:37:01.121821 24, 0x0, End_B0=24 End_B1=24
8220 11:37:01.125308 25, 0x0, End_B0=25 End_B1=25
8221 11:37:01.128493 26, 0x0, End_B0=26 End_B1=26
8222 11:37:01.131621 27, 0x0, End_B0=27 End_B1=27
8223 11:37:01.132081 28, 0x0, End_B0=28 End_B1=28
8224 11:37:01.134848 29, 0x0, End_B0=29 End_B1=29
8225 11:37:01.137924 30, 0x0, End_B0=30 End_B1=30
8226 11:37:01.141704 31, 0x4141, End_B0=30 End_B1=30
8227 11:37:01.144857 Byte0 end_step=30 best_step=27
8228 11:37:01.148296 Byte1 end_step=30 best_step=27
8229 11:37:01.148752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8230 11:37:01.151474 Byte1 TX OE(2T, 0.5T) = (3, 3)
8231 11:37:01.151859
8232 11:37:01.152154
8233 11:37:01.161717 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8234 11:37:01.164644 CH0 RK1: MR19=303, MR18=1512
8235 11:37:01.168245 CH0_RK1: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
8236 11:37:01.171390 [RxdqsGatingPostProcess] freq 1600
8237 11:37:01.177763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8238 11:37:01.181261 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 11:37:01.184723 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 11:37:01.188062 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 11:37:01.191467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 11:37:01.194751 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 11:37:01.197649 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 11:37:01.200887 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 11:37:01.201399 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 11:37:01.204388 Pre-setting of DQS Precalculation
8247 11:37:01.210705 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8248 11:37:01.211149 ==
8249 11:37:01.213790 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 11:37:01.217093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 11:37:01.217520 ==
8252 11:37:01.223814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8253 11:37:01.227208 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8254 11:37:01.233653 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8255 11:37:01.237205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8256 11:37:01.247605 [CA 0] Center 42 (12~72) winsize 61
8257 11:37:01.250388 [CA 1] Center 42 (12~72) winsize 61
8258 11:37:01.253097 [CA 2] Center 38 (9~67) winsize 59
8259 11:37:01.257080 [CA 3] Center 37 (8~66) winsize 59
8260 11:37:01.260104 [CA 4] Center 38 (8~68) winsize 61
8261 11:37:01.263405 [CA 5] Center 36 (7~66) winsize 60
8262 11:37:01.263791
8263 11:37:01.266545 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8264 11:37:01.266933
8265 11:37:01.273516 [CATrainingPosCal] consider 1 rank data
8266 11:37:01.273966 u2DelayCellTimex100 = 275/100 ps
8267 11:37:01.279609 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8268 11:37:01.283259 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8269 11:37:01.286334 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8270 11:37:01.289471 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8271 11:37:01.293485 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8272 11:37:01.295940 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8273 11:37:01.296398
8274 11:37:01.300263 CA PerBit enable=1, Macro0, CA PI delay=36
8275 11:37:01.300736
8276 11:37:01.303096 [CBTSetCACLKResult] CA Dly = 36
8277 11:37:01.305861 CS Dly: 8 (0~39)
8278 11:37:01.309471 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8279 11:37:01.312314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8280 11:37:01.312699 ==
8281 11:37:01.315610 Dram Type= 6, Freq= 0, CH_1, rank 1
8282 11:37:01.322392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 11:37:01.322781 ==
8284 11:37:01.325942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 11:37:01.332890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 11:37:01.335790 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 11:37:01.342445 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 11:37:01.350461 [CA 0] Center 42 (12~72) winsize 61
8289 11:37:01.353206 [CA 1] Center 42 (13~71) winsize 59
8290 11:37:01.356695 [CA 2] Center 37 (8~67) winsize 60
8291 11:37:01.360368 [CA 3] Center 36 (7~66) winsize 60
8292 11:37:01.363101 [CA 4] Center 37 (7~67) winsize 61
8293 11:37:01.366425 [CA 5] Center 36 (7~66) winsize 60
8294 11:37:01.366813
8295 11:37:01.369842 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 11:37:01.370295
8297 11:37:01.376856 [CATrainingPosCal] consider 2 rank data
8298 11:37:01.377357 u2DelayCellTimex100 = 275/100 ps
8299 11:37:01.382764 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8300 11:37:01.386220 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8301 11:37:01.389378 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8302 11:37:01.393064 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 11:37:01.395799 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8304 11:37:01.399062 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8305 11:37:01.399474
8306 11:37:01.402327 CA PerBit enable=1, Macro0, CA PI delay=36
8307 11:37:01.402708
8308 11:37:01.405399 [CBTSetCACLKResult] CA Dly = 36
8309 11:37:01.408914 CS Dly: 9 (0~42)
8310 11:37:01.412039 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 11:37:01.415658 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 11:37:01.416039
8313 11:37:01.419132 ----->DramcWriteLeveling(PI) begin...
8314 11:37:01.419520 ==
8315 11:37:01.422183 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 11:37:01.428722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 11:37:01.429107 ==
8318 11:37:01.432375 Write leveling (Byte 0): 23 => 23
8319 11:37:01.435708 Write leveling (Byte 1): 26 => 26
8320 11:37:01.438673 DramcWriteLeveling(PI) end<-----
8321 11:37:01.439052
8322 11:37:01.439452 ==
8323 11:37:01.442362 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 11:37:01.445509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 11:37:01.446036 ==
8326 11:37:01.448345 [Gating] SW mode calibration
8327 11:37:01.455450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8328 11:37:01.462058 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8329 11:37:01.465069 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 11:37:01.468363 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:37:01.475248 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:37:01.478023 1 4 12 | B1->B0 | 2424 3232 | 1 1 | (1 1) (1 1)
8333 11:37:01.481552 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8334 11:37:01.488089 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 11:37:01.491331 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 11:37:01.494681 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 11:37:01.501440 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 11:37:01.504774 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 11:37:01.508041 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8340 11:37:01.514489 1 5 12 | B1->B0 | 3131 2424 | 0 0 | (1 0) (0 0)
8341 11:37:01.517533 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8342 11:37:01.520786 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 11:37:01.527140 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:37:01.530411 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:37:01.533961 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:37:01.540411 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:37:01.544088 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8348 11:37:01.547257 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8349 11:37:01.553881 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 11:37:01.557463 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 11:37:01.560244 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 11:37:01.566884 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:37:01.570293 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:37:01.574065 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 11:37:01.580152 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:37:01.583682 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8357 11:37:01.586906 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8358 11:37:01.593330 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:37:01.596505 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:37:01.600046 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:37:01.606392 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:37:01.609848 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:37:01.613324 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:37:01.619802 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:37:01.622902 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:37:01.625963 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:37:01.632716 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 11:37:01.635993 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 11:37:01.639349 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:37:01.645883 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:37:01.649559 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8372 11:37:01.652458 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8373 11:37:01.659515 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 11:37:01.662185 Total UI for P1: 0, mck2ui 16
8375 11:37:01.665263 best dqsien dly found for B0: ( 1, 9, 10)
8376 11:37:01.665651 Total UI for P1: 0, mck2ui 16
8377 11:37:01.672528 best dqsien dly found for B1: ( 1, 9, 12)
8378 11:37:01.675819 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8379 11:37:01.678608 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8380 11:37:01.678993
8381 11:37:01.682248 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8382 11:37:01.685743 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8383 11:37:01.688992 [Gating] SW calibration Done
8384 11:37:01.689490 ==
8385 11:37:01.692428 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 11:37:01.695592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 11:37:01.696034 ==
8388 11:37:01.698563 RX Vref Scan: 0
8389 11:37:01.698944
8390 11:37:01.701966 RX Vref 0 -> 0, step: 1
8391 11:37:01.702429
8392 11:37:01.702729 RX Delay 0 -> 252, step: 8
8393 11:37:01.708819 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8394 11:37:01.712145 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8395 11:37:01.715192 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8396 11:37:01.718396 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8397 11:37:01.721843 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8398 11:37:01.728549 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8399 11:37:01.731612 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8400 11:37:01.735198 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8401 11:37:01.737787 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8402 11:37:01.741613 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8403 11:37:01.748298 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8404 11:37:01.751345 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8405 11:37:01.754586 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8406 11:37:01.757989 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8407 11:37:01.764123 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8408 11:37:01.767647 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8409 11:37:01.768111 ==
8410 11:37:01.770529 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 11:37:01.774151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 11:37:01.774616 ==
8413 11:37:01.777642 DQS Delay:
8414 11:37:01.778024 DQS0 = 0, DQS1 = 0
8415 11:37:01.778322 DQM Delay:
8416 11:37:01.780440 DQM0 = 135, DQM1 = 131
8417 11:37:01.780824 DQ Delay:
8418 11:37:01.784393 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8419 11:37:01.787458 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8420 11:37:01.794146 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8421 11:37:01.796812 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =139
8422 11:37:01.797370
8423 11:37:01.797849
8424 11:37:01.798317 ==
8425 11:37:01.800424 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 11:37:01.803577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 11:37:01.803967 ==
8428 11:37:01.804266
8429 11:37:01.804537
8430 11:37:01.807105 TX Vref Scan disable
8431 11:37:01.810143 == TX Byte 0 ==
8432 11:37:01.813432 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8433 11:37:01.817306 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8434 11:37:01.819841 == TX Byte 1 ==
8435 11:37:01.823520 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8436 11:37:01.826829 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8437 11:37:01.827290 ==
8438 11:37:01.829784 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 11:37:01.833481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 11:37:01.836257 ==
8441 11:37:01.849193
8442 11:37:01.852140 TX Vref early break, caculate TX vref
8443 11:37:01.855469 TX Vref=16, minBit 8, minWin=21, winSum=369
8444 11:37:01.858815 TX Vref=18, minBit 6, minWin=23, winSum=381
8445 11:37:01.862011 TX Vref=20, minBit 8, minWin=23, winSum=384
8446 11:37:01.865460 TX Vref=22, minBit 8, minWin=23, winSum=396
8447 11:37:01.868587 TX Vref=24, minBit 9, minWin=24, winSum=403
8448 11:37:01.875268 TX Vref=26, minBit 9, minWin=24, winSum=412
8449 11:37:01.878473 TX Vref=28, minBit 9, minWin=25, winSum=416
8450 11:37:01.882307 TX Vref=30, minBit 0, minWin=25, winSum=414
8451 11:37:01.885279 TX Vref=32, minBit 9, minWin=23, winSum=407
8452 11:37:01.888598 TX Vref=34, minBit 9, minWin=23, winSum=396
8453 11:37:01.895211 TX Vref=36, minBit 11, minWin=22, winSum=387
8454 11:37:01.898218 [TxChooseVref] Worse bit 9, Min win 25, Win sum 416, Final Vref 28
8455 11:37:01.898689
8456 11:37:01.902058 Final TX Range 0 Vref 28
8457 11:37:01.902536
8458 11:37:01.902835 ==
8459 11:37:01.905291 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 11:37:01.908305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 11:37:01.911611 ==
8462 11:37:01.912069
8463 11:37:01.912364
8464 11:37:01.912631 TX Vref Scan disable
8465 11:37:01.918156 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8466 11:37:01.918577 == TX Byte 0 ==
8467 11:37:01.921658 u2DelayCellOfst[0]=14 cells (4 PI)
8468 11:37:01.925329 u2DelayCellOfst[1]=7 cells (2 PI)
8469 11:37:01.928435 u2DelayCellOfst[2]=0 cells (0 PI)
8470 11:37:01.932332 u2DelayCellOfst[3]=3 cells (1 PI)
8471 11:37:01.934708 u2DelayCellOfst[4]=7 cells (2 PI)
8472 11:37:01.938100 u2DelayCellOfst[5]=14 cells (4 PI)
8473 11:37:01.941769 u2DelayCellOfst[6]=14 cells (4 PI)
8474 11:37:01.945065 u2DelayCellOfst[7]=3 cells (1 PI)
8475 11:37:01.947838 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8476 11:37:01.951020 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8477 11:37:01.954331 == TX Byte 1 ==
8478 11:37:01.957775 u2DelayCellOfst[8]=0 cells (0 PI)
8479 11:37:01.960804 u2DelayCellOfst[9]=3 cells (1 PI)
8480 11:37:01.964215 u2DelayCellOfst[10]=10 cells (3 PI)
8481 11:37:01.967823 u2DelayCellOfst[11]=3 cells (1 PI)
8482 11:37:01.970922 u2DelayCellOfst[12]=14 cells (4 PI)
8483 11:37:01.974388 u2DelayCellOfst[13]=14 cells (4 PI)
8484 11:37:01.977209 u2DelayCellOfst[14]=17 cells (5 PI)
8485 11:37:01.977600 u2DelayCellOfst[15]=17 cells (5 PI)
8486 11:37:01.984114 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8487 11:37:01.987133 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8488 11:37:01.990479 DramC Write-DBI on
8489 11:37:01.991093 ==
8490 11:37:01.993460 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 11:37:01.997299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 11:37:01.997713 ==
8493 11:37:01.998013
8494 11:37:01.998285
8495 11:37:02.000481 TX Vref Scan disable
8496 11:37:02.000861 == TX Byte 0 ==
8497 11:37:02.007032 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8498 11:37:02.007488 == TX Byte 1 ==
8499 11:37:02.010460 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8500 11:37:02.013483 DramC Write-DBI off
8501 11:37:02.013862
8502 11:37:02.014158 [DATLAT]
8503 11:37:02.016782 Freq=1600, CH1 RK0
8504 11:37:02.017390
8505 11:37:02.017730 DATLAT Default: 0xf
8506 11:37:02.020328 0, 0xFFFF, sum = 0
8507 11:37:02.020719 1, 0xFFFF, sum = 0
8508 11:37:02.023564 2, 0xFFFF, sum = 0
8509 11:37:02.026821 3, 0xFFFF, sum = 0
8510 11:37:02.027284 4, 0xFFFF, sum = 0
8511 11:37:02.030535 5, 0xFFFF, sum = 0
8512 11:37:02.030922 6, 0xFFFF, sum = 0
8513 11:37:02.033250 7, 0xFFFF, sum = 0
8514 11:37:02.033635 8, 0xFFFF, sum = 0
8515 11:37:02.036989 9, 0xFFFF, sum = 0
8516 11:37:02.037495 10, 0xFFFF, sum = 0
8517 11:37:02.040269 11, 0xFFFF, sum = 0
8518 11:37:02.040747 12, 0xFFFF, sum = 0
8519 11:37:02.043494 13, 0xFFFF, sum = 0
8520 11:37:02.043880 14, 0x0, sum = 1
8521 11:37:02.046979 15, 0x0, sum = 2
8522 11:37:02.047448 16, 0x0, sum = 3
8523 11:37:02.049839 17, 0x0, sum = 4
8524 11:37:02.050225 best_step = 15
8525 11:37:02.050516
8526 11:37:02.050785 ==
8527 11:37:02.053728 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 11:37:02.059661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 11:37:02.060050 ==
8530 11:37:02.060343 RX Vref Scan: 1
8531 11:37:02.060617
8532 11:37:02.063122 Set Vref Range= 24 -> 127
8533 11:37:02.063501
8534 11:37:02.066029 RX Vref 24 -> 127, step: 1
8535 11:37:02.066412
8536 11:37:02.066706 RX Delay 19 -> 252, step: 4
8537 11:37:02.069712
8538 11:37:02.070088 Set Vref, RX VrefLevel [Byte0]: 24
8539 11:37:02.072834 [Byte1]: 24
8540 11:37:02.077010
8541 11:37:02.077419 Set Vref, RX VrefLevel [Byte0]: 25
8542 11:37:02.080433 [Byte1]: 25
8543 11:37:02.084987
8544 11:37:02.085480 Set Vref, RX VrefLevel [Byte0]: 26
8545 11:37:02.087671 [Byte1]: 26
8546 11:37:02.092245
8547 11:37:02.092697 Set Vref, RX VrefLevel [Byte0]: 27
8548 11:37:02.096003 [Byte1]: 27
8549 11:37:02.099518
8550 11:37:02.099899 Set Vref, RX VrefLevel [Byte0]: 28
8551 11:37:02.103166 [Byte1]: 28
8552 11:37:02.107541
8553 11:37:02.107995 Set Vref, RX VrefLevel [Byte0]: 29
8554 11:37:02.110753 [Byte1]: 29
8555 11:37:02.114861
8556 11:37:02.115242 Set Vref, RX VrefLevel [Byte0]: 30
8557 11:37:02.117925 [Byte1]: 30
8558 11:37:02.122528
8559 11:37:02.122918 Set Vref, RX VrefLevel [Byte0]: 31
8560 11:37:02.126352 [Byte1]: 31
8561 11:37:02.130230
8562 11:37:02.130694 Set Vref, RX VrefLevel [Byte0]: 32
8563 11:37:02.133314 [Byte1]: 32
8564 11:37:02.137823
8565 11:37:02.138278 Set Vref, RX VrefLevel [Byte0]: 33
8566 11:37:02.141344 [Byte1]: 33
8567 11:37:02.145086
8568 11:37:02.145506 Set Vref, RX VrefLevel [Byte0]: 34
8569 11:37:02.148938 [Byte1]: 34
8570 11:37:02.152930
8571 11:37:02.153447 Set Vref, RX VrefLevel [Byte0]: 35
8572 11:37:02.156175 [Byte1]: 35
8573 11:37:02.160570
8574 11:37:02.161019 Set Vref, RX VrefLevel [Byte0]: 36
8575 11:37:02.163798 [Byte1]: 36
8576 11:37:02.168309
8577 11:37:02.168764 Set Vref, RX VrefLevel [Byte0]: 37
8578 11:37:02.171180 [Byte1]: 37
8579 11:37:02.175990
8580 11:37:02.176444 Set Vref, RX VrefLevel [Byte0]: 38
8581 11:37:02.178855 [Byte1]: 38
8582 11:37:02.183652
8583 11:37:02.184108 Set Vref, RX VrefLevel [Byte0]: 39
8584 11:37:02.186470 [Byte1]: 39
8585 11:37:02.190683
8586 11:37:02.191136 Set Vref, RX VrefLevel [Byte0]: 40
8587 11:37:02.194108 [Byte1]: 40
8588 11:37:02.198399
8589 11:37:02.198852 Set Vref, RX VrefLevel [Byte0]: 41
8590 11:37:02.201841 [Byte1]: 41
8591 11:37:02.205773
8592 11:37:02.206231 Set Vref, RX VrefLevel [Byte0]: 42
8593 11:37:02.209445 [Byte1]: 42
8594 11:37:02.213549
8595 11:37:02.213999 Set Vref, RX VrefLevel [Byte0]: 43
8596 11:37:02.216663 [Byte1]: 43
8597 11:37:02.220803
8598 11:37:02.221218 Set Vref, RX VrefLevel [Byte0]: 44
8599 11:37:02.224209 [Byte1]: 44
8600 11:37:02.228848
8601 11:37:02.229367 Set Vref, RX VrefLevel [Byte0]: 45
8602 11:37:02.231637 [Byte1]: 45
8603 11:37:02.236479
8604 11:37:02.236934 Set Vref, RX VrefLevel [Byte0]: 46
8605 11:37:02.239248 [Byte1]: 46
8606 11:37:02.244118
8607 11:37:02.244499 Set Vref, RX VrefLevel [Byte0]: 47
8608 11:37:02.246983 [Byte1]: 47
8609 11:37:02.251677
8610 11:37:02.252131 Set Vref, RX VrefLevel [Byte0]: 48
8611 11:37:02.254386 [Byte1]: 48
8612 11:37:02.258902
8613 11:37:02.259283 Set Vref, RX VrefLevel [Byte0]: 49
8614 11:37:02.262205 [Byte1]: 49
8615 11:37:02.266328
8616 11:37:02.266781 Set Vref, RX VrefLevel [Byte0]: 50
8617 11:37:02.269499 [Byte1]: 50
8618 11:37:02.273990
8619 11:37:02.274458 Set Vref, RX VrefLevel [Byte0]: 51
8620 11:37:02.277643 [Byte1]: 51
8621 11:37:02.281689
8622 11:37:02.282068 Set Vref, RX VrefLevel [Byte0]: 52
8623 11:37:02.284890 [Byte1]: 52
8624 11:37:02.289022
8625 11:37:02.289525 Set Vref, RX VrefLevel [Byte0]: 53
8626 11:37:02.292884 [Byte1]: 53
8627 11:37:02.296577
8628 11:37:02.296956 Set Vref, RX VrefLevel [Byte0]: 54
8629 11:37:02.299899 [Byte1]: 54
8630 11:37:02.304640
8631 11:37:02.305091 Set Vref, RX VrefLevel [Byte0]: 55
8632 11:37:02.307364 [Byte1]: 55
8633 11:37:02.312059
8634 11:37:02.312517 Set Vref, RX VrefLevel [Byte0]: 56
8635 11:37:02.318268 [Byte1]: 56
8636 11:37:02.318722
8637 11:37:02.322330 Set Vref, RX VrefLevel [Byte0]: 57
8638 11:37:02.325224 [Byte1]: 57
8639 11:37:02.325682
8640 11:37:02.328756 Set Vref, RX VrefLevel [Byte0]: 58
8641 11:37:02.331510 [Byte1]: 58
8642 11:37:02.331901
8643 11:37:02.334551 Set Vref, RX VrefLevel [Byte0]: 59
8644 11:37:02.339067 [Byte1]: 59
8645 11:37:02.342434
8646 11:37:02.342892 Set Vref, RX VrefLevel [Byte0]: 60
8647 11:37:02.345251 [Byte1]: 60
8648 11:37:02.350101
8649 11:37:02.350562 Set Vref, RX VrefLevel [Byte0]: 61
8650 11:37:02.352740 [Byte1]: 61
8651 11:37:02.357332
8652 11:37:02.357790 Set Vref, RX VrefLevel [Byte0]: 62
8653 11:37:02.361382 [Byte1]: 62
8654 11:37:02.364983
8655 11:37:02.365392 Set Vref, RX VrefLevel [Byte0]: 63
8656 11:37:02.368340 [Byte1]: 63
8657 11:37:02.372766
8658 11:37:02.373262 Set Vref, RX VrefLevel [Byte0]: 64
8659 11:37:02.375714 [Byte1]: 64
8660 11:37:02.379983
8661 11:37:02.380443 Set Vref, RX VrefLevel [Byte0]: 65
8662 11:37:02.383381 [Byte1]: 65
8663 11:37:02.387863
8664 11:37:02.388322 Set Vref, RX VrefLevel [Byte0]: 66
8665 11:37:02.391146 [Byte1]: 66
8666 11:37:02.395135
8667 11:37:02.395628 Set Vref, RX VrefLevel [Byte0]: 67
8668 11:37:02.398318 [Byte1]: 67
8669 11:37:02.403032
8670 11:37:02.403510 Set Vref, RX VrefLevel [Byte0]: 68
8671 11:37:02.406273 [Byte1]: 68
8672 11:37:02.410609
8673 11:37:02.411084 Set Vref, RX VrefLevel [Byte0]: 69
8674 11:37:02.413727 [Byte1]: 69
8675 11:37:02.417813
8676 11:37:02.418203 Set Vref, RX VrefLevel [Byte0]: 70
8677 11:37:02.421425 [Byte1]: 70
8678 11:37:02.425531
8679 11:37:02.426010 Set Vref, RX VrefLevel [Byte0]: 71
8680 11:37:02.428726 [Byte1]: 71
8681 11:37:02.432937
8682 11:37:02.433375 Set Vref, RX VrefLevel [Byte0]: 72
8683 11:37:02.436173 [Byte1]: 72
8684 11:37:02.440638
8685 11:37:02.441015 Final RX Vref Byte 0 = 56 to rank0
8686 11:37:02.443762 Final RX Vref Byte 1 = 61 to rank0
8687 11:37:02.447375 Final RX Vref Byte 0 = 56 to rank1
8688 11:37:02.450668 Final RX Vref Byte 1 = 61 to rank1==
8689 11:37:02.453750 Dram Type= 6, Freq= 0, CH_1, rank 0
8690 11:37:02.460418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8691 11:37:02.460896 ==
8692 11:37:02.461270 DQS Delay:
8693 11:37:02.463860 DQS0 = 0, DQS1 = 0
8694 11:37:02.464317 DQM Delay:
8695 11:37:02.466685 DQM0 = 133, DQM1 = 128
8696 11:37:02.467078 DQ Delay:
8697 11:37:02.470295 DQ0 =140, DQ1 =130, DQ2 =120, DQ3 =132
8698 11:37:02.473338 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =128
8699 11:37:02.477084 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8700 11:37:02.480489 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8701 11:37:02.480894
8702 11:37:02.481356
8703 11:37:02.481724
8704 11:37:02.483623 [DramC_TX_OE_Calibration] TA2
8705 11:37:02.486769 Original DQ_B0 (3 6) =30, OEN = 27
8706 11:37:02.490014 Original DQ_B1 (3 6) =30, OEN = 27
8707 11:37:02.493310 24, 0x0, End_B0=24 End_B1=24
8708 11:37:02.496748 25, 0x0, End_B0=25 End_B1=25
8709 11:37:02.497276 26, 0x0, End_B0=26 End_B1=26
8710 11:37:02.500026 27, 0x0, End_B0=27 End_B1=27
8711 11:37:02.503141 28, 0x0, End_B0=28 End_B1=28
8712 11:37:02.506448 29, 0x0, End_B0=29 End_B1=29
8713 11:37:02.506848 30, 0x0, End_B0=30 End_B1=30
8714 11:37:02.509802 31, 0x4545, End_B0=30 End_B1=30
8715 11:37:02.513330 Byte0 end_step=30 best_step=27
8716 11:37:02.516258 Byte1 end_step=30 best_step=27
8717 11:37:02.519524 Byte0 TX OE(2T, 0.5T) = (3, 3)
8718 11:37:02.522575 Byte1 TX OE(2T, 0.5T) = (3, 3)
8719 11:37:02.522957
8720 11:37:02.523252
8721 11:37:02.529252 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
8722 11:37:02.532662 CH1 RK0: MR19=303, MR18=1019
8723 11:37:02.539024 CH1_RK0: MR19=0x303, MR18=0x1019, DQSOSC=397, MR23=63, INC=23, DEC=15
8724 11:37:02.539477
8725 11:37:02.542359 ----->DramcWriteLeveling(PI) begin...
8726 11:37:02.542828 ==
8727 11:37:02.545684 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 11:37:02.549095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 11:37:02.549526 ==
8730 11:37:02.552290 Write leveling (Byte 0): 24 => 24
8731 11:37:02.555785 Write leveling (Byte 1): 24 => 24
8732 11:37:02.558991 DramcWriteLeveling(PI) end<-----
8733 11:37:02.559373
8734 11:37:02.559664 ==
8735 11:37:02.562314 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 11:37:02.568977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 11:37:02.569503 ==
8738 11:37:02.571748 [Gating] SW mode calibration
8739 11:37:02.579340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8740 11:37:02.581974 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8741 11:37:02.588505 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 11:37:02.591742 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 11:37:02.595621 1 4 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8744 11:37:02.602209 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8745 11:37:02.605488 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 11:37:02.608660 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 11:37:02.614939 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 11:37:02.618687 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 11:37:02.621414 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 11:37:02.628306 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
8751 11:37:02.631510 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8752 11:37:02.634629 1 5 12 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8753 11:37:02.640884 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:37:02.644761 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 11:37:02.648110 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 11:37:02.654387 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 11:37:02.657539 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 11:37:02.660922 1 6 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8759 11:37:02.667717 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8760 11:37:02.671345 1 6 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8761 11:37:02.674033 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8762 11:37:02.681211 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 11:37:02.684163 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 11:37:02.687378 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 11:37:02.693901 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 11:37:02.697023 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8767 11:37:02.700492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8768 11:37:02.707356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8769 11:37:02.710443 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 11:37:02.713443 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:37:02.720316 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:37:02.723505 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:37:02.727023 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:37:02.733207 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:37:02.737097 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:37:02.740368 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:37:02.746750 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:37:02.749953 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:37:02.753209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:37:02.759814 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:37:02.763252 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:37:02.766459 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8783 11:37:02.773314 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8784 11:37:02.776162 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8785 11:37:02.779169 Total UI for P1: 0, mck2ui 16
8786 11:37:02.782388 best dqsien dly found for B0: ( 1, 9, 6)
8787 11:37:02.786262 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 11:37:02.789568 Total UI for P1: 0, mck2ui 16
8789 11:37:02.792556 best dqsien dly found for B1: ( 1, 9, 12)
8790 11:37:02.796131 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8791 11:37:02.799082 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8792 11:37:02.799470
8793 11:37:02.806203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8794 11:37:02.809466 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8795 11:37:02.809855 [Gating] SW calibration Done
8796 11:37:02.812829 ==
8797 11:37:02.815725 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 11:37:02.818808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 11:37:02.819209 ==
8800 11:37:02.819508 RX Vref Scan: 0
8801 11:37:02.819782
8802 11:37:02.822572 RX Vref 0 -> 0, step: 1
8803 11:37:02.822954
8804 11:37:02.825527 RX Delay 0 -> 252, step: 8
8805 11:37:02.829057 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8806 11:37:02.832358 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8807 11:37:02.836275 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8808 11:37:02.842580 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8809 11:37:02.845520 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8810 11:37:02.848817 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8811 11:37:02.852240 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8812 11:37:02.856002 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8813 11:37:02.861893 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8814 11:37:02.865710 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8815 11:37:02.868399 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8816 11:37:02.871758 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8817 11:37:02.878484 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8818 11:37:02.881620 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8819 11:37:02.885205 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8820 11:37:02.888430 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8821 11:37:02.888892 ==
8822 11:37:02.891694 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 11:37:02.898184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 11:37:02.898578 ==
8825 11:37:02.898876 DQS Delay:
8826 11:37:02.901647 DQS0 = 0, DQS1 = 0
8827 11:37:02.902032 DQM Delay:
8828 11:37:02.902327 DQM0 = 134, DQM1 = 131
8829 11:37:02.905234 DQ Delay:
8830 11:37:02.908103 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8831 11:37:02.912191 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8832 11:37:02.914905 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8833 11:37:02.917807 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8834 11:37:02.918192
8835 11:37:02.918487
8836 11:37:02.918762 ==
8837 11:37:02.921392 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 11:37:02.928480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 11:37:02.928943 ==
8840 11:37:02.929290
8841 11:37:02.929576
8842 11:37:02.929843 TX Vref Scan disable
8843 11:37:02.931093 == TX Byte 0 ==
8844 11:37:02.934603 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8845 11:37:02.938231 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8846 11:37:02.941455 == TX Byte 1 ==
8847 11:37:02.944876 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8848 11:37:02.951014 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8849 11:37:02.951480 ==
8850 11:37:02.954304 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 11:37:02.957740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 11:37:02.958203 ==
8853 11:37:02.969697
8854 11:37:02.973040 TX Vref early break, caculate TX vref
8855 11:37:02.975956 TX Vref=16, minBit 5, minWin=22, winSum=382
8856 11:37:02.979771 TX Vref=18, minBit 9, minWin=23, winSum=392
8857 11:37:02.982535 TX Vref=20, minBit 9, minWin=23, winSum=396
8858 11:37:02.986095 TX Vref=22, minBit 9, minWin=24, winSum=400
8859 11:37:02.989603 TX Vref=24, minBit 9, minWin=24, winSum=412
8860 11:37:02.996178 TX Vref=26, minBit 3, minWin=25, winSum=419
8861 11:37:02.999591 TX Vref=28, minBit 0, minWin=26, winSum=426
8862 11:37:03.002599 TX Vref=30, minBit 9, minWin=25, winSum=421
8863 11:37:03.005854 TX Vref=32, minBit 0, minWin=25, winSum=413
8864 11:37:03.009329 TX Vref=34, minBit 0, minWin=24, winSum=402
8865 11:37:03.015461 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8866 11:37:03.015917
8867 11:37:03.019544 Final TX Range 0 Vref 28
8868 11:37:03.020009
8869 11:37:03.020316 ==
8870 11:37:03.022245 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 11:37:03.025810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 11:37:03.026196 ==
8873 11:37:03.026494
8874 11:37:03.026762
8875 11:37:03.028822 TX Vref Scan disable
8876 11:37:03.035700 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8877 11:37:03.036148 == TX Byte 0 ==
8878 11:37:03.039012 u2DelayCellOfst[0]=14 cells (4 PI)
8879 11:37:03.042793 u2DelayCellOfst[1]=10 cells (3 PI)
8880 11:37:03.045402 u2DelayCellOfst[2]=0 cells (0 PI)
8881 11:37:03.049391 u2DelayCellOfst[3]=3 cells (1 PI)
8882 11:37:03.052443 u2DelayCellOfst[4]=7 cells (2 PI)
8883 11:37:03.055665 u2DelayCellOfst[5]=14 cells (4 PI)
8884 11:37:03.058472 u2DelayCellOfst[6]=14 cells (4 PI)
8885 11:37:03.061619 u2DelayCellOfst[7]=7 cells (2 PI)
8886 11:37:03.065431 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8887 11:37:03.068227 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8888 11:37:03.071557 == TX Byte 1 ==
8889 11:37:03.075445 u2DelayCellOfst[8]=0 cells (0 PI)
8890 11:37:03.077938 u2DelayCellOfst[9]=0 cells (0 PI)
8891 11:37:03.081190 u2DelayCellOfst[10]=10 cells (3 PI)
8892 11:37:03.081583 u2DelayCellOfst[11]=3 cells (1 PI)
8893 11:37:03.084592 u2DelayCellOfst[12]=14 cells (4 PI)
8894 11:37:03.087960 u2DelayCellOfst[13]=14 cells (4 PI)
8895 11:37:03.091330 u2DelayCellOfst[14]=17 cells (5 PI)
8896 11:37:03.095011 u2DelayCellOfst[15]=17 cells (5 PI)
8897 11:37:03.101346 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8898 11:37:03.104523 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8899 11:37:03.104988 DramC Write-DBI on
8900 11:37:03.108168 ==
8901 11:37:03.111346 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:37:03.114346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:37:03.114741 ==
8904 11:37:03.115107
8905 11:37:03.115382
8906 11:37:03.118062 TX Vref Scan disable
8907 11:37:03.118442 == TX Byte 0 ==
8908 11:37:03.124829 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8909 11:37:03.125322 == TX Byte 1 ==
8910 11:37:03.127691 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8911 11:37:03.131300 DramC Write-DBI off
8912 11:37:03.131765
8913 11:37:03.132066 [DATLAT]
8914 11:37:03.133774 Freq=1600, CH1 RK1
8915 11:37:03.134162
8916 11:37:03.134460 DATLAT Default: 0xf
8917 11:37:03.137528 0, 0xFFFF, sum = 0
8918 11:37:03.137994 1, 0xFFFF, sum = 0
8919 11:37:03.140965 2, 0xFFFF, sum = 0
8920 11:37:03.141490 3, 0xFFFF, sum = 0
8921 11:37:03.144176 4, 0xFFFF, sum = 0
8922 11:37:03.144639 5, 0xFFFF, sum = 0
8923 11:37:03.147080 6, 0xFFFF, sum = 0
8924 11:37:03.150396 7, 0xFFFF, sum = 0
8925 11:37:03.150797 8, 0xFFFF, sum = 0
8926 11:37:03.153953 9, 0xFFFF, sum = 0
8927 11:37:03.154353 10, 0xFFFF, sum = 0
8928 11:37:03.157088 11, 0xFFFF, sum = 0
8929 11:37:03.157507 12, 0xFFFF, sum = 0
8930 11:37:03.160395 13, 0xFFFF, sum = 0
8931 11:37:03.160860 14, 0x0, sum = 1
8932 11:37:03.163974 15, 0x0, sum = 2
8933 11:37:03.164437 16, 0x0, sum = 3
8934 11:37:03.166697 17, 0x0, sum = 4
8935 11:37:03.167112 best_step = 15
8936 11:37:03.167448
8937 11:37:03.167727 ==
8938 11:37:03.170193 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:37:03.173745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:37:03.176938 ==
8941 11:37:03.177370 RX Vref Scan: 0
8942 11:37:03.177670
8943 11:37:03.180231 RX Vref 0 -> 0, step: 1
8944 11:37:03.180616
8945 11:37:03.183712 RX Delay 19 -> 252, step: 4
8946 11:37:03.186529 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8947 11:37:03.189878 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8948 11:37:03.193477 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8949 11:37:03.199761 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8950 11:37:03.203246 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8951 11:37:03.206955 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8952 11:37:03.210461 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8953 11:37:03.213488 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8954 11:37:03.219801 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8955 11:37:03.223525 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8956 11:37:03.226803 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8957 11:37:03.229562 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8958 11:37:03.233090 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8959 11:37:03.239771 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8960 11:37:03.243682 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8961 11:37:03.245986 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8962 11:37:03.246376 ==
8963 11:37:03.249524 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 11:37:03.253001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 11:37:03.256367 ==
8966 11:37:03.256820 DQS Delay:
8967 11:37:03.257118 DQS0 = 0, DQS1 = 0
8968 11:37:03.259519 DQM Delay:
8969 11:37:03.259903 DQM0 = 131, DQM1 = 128
8970 11:37:03.262440 DQ Delay:
8971 11:37:03.266091 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8972 11:37:03.269586 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
8973 11:37:03.272842 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8974 11:37:03.276207 DQ12 =138, DQ13 =136, DQ14 =132, DQ15 =136
8975 11:37:03.276594
8976 11:37:03.276886
8977 11:37:03.277189
8978 11:37:03.278940 [DramC_TX_OE_Calibration] TA2
8979 11:37:03.282188 Original DQ_B0 (3 6) =30, OEN = 27
8980 11:37:03.285492 Original DQ_B1 (3 6) =30, OEN = 27
8981 11:37:03.289181 24, 0x0, End_B0=24 End_B1=24
8982 11:37:03.289664 25, 0x0, End_B0=25 End_B1=25
8983 11:37:03.292472 26, 0x0, End_B0=26 End_B1=26
8984 11:37:03.295831 27, 0x0, End_B0=27 End_B1=27
8985 11:37:03.299165 28, 0x0, End_B0=28 End_B1=28
8986 11:37:03.302433 29, 0x0, End_B0=29 End_B1=29
8987 11:37:03.302827 30, 0x0, End_B0=30 End_B1=30
8988 11:37:03.305591 31, 0x4141, End_B0=30 End_B1=30
8989 11:37:03.308625 Byte0 end_step=30 best_step=27
8990 11:37:03.312180 Byte1 end_step=30 best_step=27
8991 11:37:03.314888 Byte0 TX OE(2T, 0.5T) = (3, 3)
8992 11:37:03.318834 Byte1 TX OE(2T, 0.5T) = (3, 3)
8993 11:37:03.319296
8994 11:37:03.319596
8995 11:37:03.325186 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8996 11:37:03.328648 CH1 RK1: MR19=303, MR18=E1D
8997 11:37:03.335465 CH1_RK1: MR19=0x303, MR18=0xE1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8998 11:37:03.338575 [RxdqsGatingPostProcess] freq 1600
8999 11:37:03.341332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9000 11:37:03.344961 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 11:37:03.348683 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 11:37:03.352035 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 11:37:03.355021 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 11:37:03.358106 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 11:37:03.361509 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 11:37:03.364252 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 11:37:03.367998 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 11:37:03.371078 Pre-setting of DQS Precalculation
9009 11:37:03.374908 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9010 11:37:03.381195 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9011 11:37:03.391447 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9012 11:37:03.391905
9013 11:37:03.392202
9014 11:37:03.394306 [Calibration Summary] 3200 Mbps
9015 11:37:03.394691 CH 0, Rank 0
9016 11:37:03.397616 SW Impedance : PASS
9017 11:37:03.398000 DUTY Scan : NO K
9018 11:37:03.400793 ZQ Calibration : PASS
9019 11:37:03.404452 Jitter Meter : NO K
9020 11:37:03.404911 CBT Training : PASS
9021 11:37:03.408327 Write leveling : PASS
9022 11:37:03.410982 RX DQS gating : PASS
9023 11:37:03.411442 RX DQ/DQS(RDDQC) : PASS
9024 11:37:03.414223 TX DQ/DQS : PASS
9025 11:37:03.414687 RX DATLAT : PASS
9026 11:37:03.417505 RX DQ/DQS(Engine): PASS
9027 11:37:03.420663 TX OE : PASS
9028 11:37:03.421120 All Pass.
9029 11:37:03.421599
9030 11:37:03.423919 CH 0, Rank 1
9031 11:37:03.424376 SW Impedance : PASS
9032 11:37:03.427596 DUTY Scan : NO K
9033 11:37:03.428060 ZQ Calibration : PASS
9034 11:37:03.430942 Jitter Meter : NO K
9035 11:37:03.433919 CBT Training : PASS
9036 11:37:03.434377 Write leveling : PASS
9037 11:37:03.437129 RX DQS gating : PASS
9038 11:37:03.440658 RX DQ/DQS(RDDQC) : PASS
9039 11:37:03.441113 TX DQ/DQS : PASS
9040 11:37:03.443825 RX DATLAT : PASS
9041 11:37:03.447361 RX DQ/DQS(Engine): PASS
9042 11:37:03.447819 TX OE : PASS
9043 11:37:03.450332 All Pass.
9044 11:37:03.450714
9045 11:37:03.451010 CH 1, Rank 0
9046 11:37:03.453505 SW Impedance : PASS
9047 11:37:03.453892 DUTY Scan : NO K
9048 11:37:03.456686 ZQ Calibration : PASS
9049 11:37:03.460096 Jitter Meter : NO K
9050 11:37:03.460728 CBT Training : PASS
9051 11:37:03.463335 Write leveling : PASS
9052 11:37:03.466538 RX DQS gating : PASS
9053 11:37:03.467053 RX DQ/DQS(RDDQC) : PASS
9054 11:37:03.470357 TX DQ/DQS : PASS
9055 11:37:03.473222 RX DATLAT : PASS
9056 11:37:03.473608 RX DQ/DQS(Engine): PASS
9057 11:37:03.476720 TX OE : PASS
9058 11:37:03.477111 All Pass.
9059 11:37:03.477471
9060 11:37:03.479674 CH 1, Rank 1
9061 11:37:03.480099 SW Impedance : PASS
9062 11:37:03.483496 DUTY Scan : NO K
9063 11:37:03.486697 ZQ Calibration : PASS
9064 11:37:03.487132 Jitter Meter : NO K
9065 11:37:03.489598 CBT Training : PASS
9066 11:37:03.493364 Write leveling : PASS
9067 11:37:03.493750 RX DQS gating : PASS
9068 11:37:03.496430 RX DQ/DQS(RDDQC) : PASS
9069 11:37:03.499230 TX DQ/DQS : PASS
9070 11:37:03.499634 RX DATLAT : PASS
9071 11:37:03.502985 RX DQ/DQS(Engine): PASS
9072 11:37:03.506330 TX OE : PASS
9073 11:37:03.506803 All Pass.
9074 11:37:03.507104
9075 11:37:03.507380 DramC Write-DBI on
9076 11:37:03.509504 PER_BANK_REFRESH: Hybrid Mode
9077 11:37:03.512676 TX_TRACKING: ON
9078 11:37:03.519384 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9079 11:37:03.529072 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9080 11:37:03.536434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 11:37:03.539409 [FAST_K] Save calibration result to emmc
9082 11:37:03.542770 sync common calibartion params.
9083 11:37:03.545904 sync cbt_mode0:1, 1:1
9084 11:37:03.546284 dram_init: ddr_geometry: 2
9085 11:37:03.549479 dram_init: ddr_geometry: 2
9086 11:37:03.552352 dram_init: ddr_geometry: 2
9087 11:37:03.552733 0:dram_rank_size:100000000
9088 11:37:03.556304 1:dram_rank_size:100000000
9089 11:37:03.562511 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9090 11:37:03.565643 DFS_SHUFFLE_HW_MODE: ON
9091 11:37:03.569051 dramc_set_vcore_voltage set vcore to 725000
9092 11:37:03.569564 Read voltage for 1600, 0
9093 11:37:03.572524 Vio18 = 0
9094 11:37:03.572981 Vcore = 725000
9095 11:37:03.573341 Vdram = 0
9096 11:37:03.575561 Vddq = 0
9097 11:37:03.575938 Vmddr = 0
9098 11:37:03.579181 switch to 3200 Mbps bootup
9099 11:37:03.579560 [DramcRunTimeConfig]
9100 11:37:03.579856 PHYPLL
9101 11:37:03.582038 DPM_CONTROL_AFTERK: ON
9102 11:37:03.585961 PER_BANK_REFRESH: ON
9103 11:37:03.586416 REFRESH_OVERHEAD_REDUCTION: ON
9104 11:37:03.588889 CMD_PICG_NEW_MODE: OFF
9105 11:37:03.591883 XRTWTW_NEW_MODE: ON
9106 11:37:03.592266 XRTRTR_NEW_MODE: ON
9107 11:37:03.595232 TX_TRACKING: ON
9108 11:37:03.595617 RDSEL_TRACKING: OFF
9109 11:37:03.598455 DQS Precalculation for DVFS: ON
9110 11:37:03.598852 RX_TRACKING: OFF
9111 11:37:03.602090 HW_GATING DBG: ON
9112 11:37:03.605452 ZQCS_ENABLE_LP4: ON
9113 11:37:03.605918 RX_PICG_NEW_MODE: ON
9114 11:37:03.608960 TX_PICG_NEW_MODE: ON
9115 11:37:03.609472 ENABLE_RX_DCM_DPHY: ON
9116 11:37:03.611707 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9117 11:37:03.615380 DUMMY_READ_FOR_TRACKING: OFF
9118 11:37:03.618137 !!! SPM_CONTROL_AFTERK: OFF
9119 11:37:03.621734 !!! SPM could not control APHY
9120 11:37:03.622194 IMPEDANCE_TRACKING: ON
9121 11:37:03.625566 TEMP_SENSOR: ON
9122 11:37:03.626052 HW_SAVE_FOR_SR: OFF
9123 11:37:03.628317 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9124 11:37:03.631980 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9125 11:37:03.635085 Read ODT Tracking: ON
9126 11:37:03.638346 Refresh Rate DeBounce: ON
9127 11:37:03.638803 DFS_NO_QUEUE_FLUSH: ON
9128 11:37:03.641660 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9129 11:37:03.645020 ENABLE_DFS_RUNTIME_MRW: OFF
9130 11:37:03.648144 DDR_RESERVE_NEW_MODE: ON
9131 11:37:03.648597 MR_CBT_SWITCH_FREQ: ON
9132 11:37:03.651463 =========================
9133 11:37:03.670062 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9134 11:37:03.673378 dram_init: ddr_geometry: 2
9135 11:37:03.691600 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9136 11:37:03.695051 dram_init: dram init end (result: 0)
9137 11:37:03.701464 DRAM-K: Full calibration passed in 24470 msecs
9138 11:37:03.704942 MRC: failed to locate region type 0.
9139 11:37:03.705489 DRAM rank0 size:0x100000000,
9140 11:37:03.708161 DRAM rank1 size=0x100000000
9141 11:37:03.718017 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9142 11:37:03.724464 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9143 11:37:03.731559 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9144 11:37:03.738154 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9145 11:37:03.741198 DRAM rank0 size:0x100000000,
9146 11:37:03.744515 DRAM rank1 size=0x100000000
9147 11:37:03.744899 CBMEM:
9148 11:37:03.747638 IMD: root @ 0xfffff000 254 entries.
9149 11:37:03.751305 IMD: root @ 0xffffec00 62 entries.
9150 11:37:03.754319 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9151 11:37:03.761036 WARNING: RO_VPD is uninitialized or empty.
9152 11:37:03.764391 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9153 11:37:03.772044 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9154 11:37:03.784168 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9155 11:37:03.795802 BS: romstage times (exec / console): total (unknown) / 23990 ms
9156 11:37:03.796303
9157 11:37:03.796609
9158 11:37:03.805828 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9159 11:37:03.808932 ARM64: Exception handlers installed.
9160 11:37:03.812315 ARM64: Testing exception
9161 11:37:03.815305 ARM64: Done test exception
9162 11:37:03.815723 Enumerating buses...
9163 11:37:03.818794 Show all devs... Before device enumeration.
9164 11:37:03.822288 Root Device: enabled 1
9165 11:37:03.825753 CPU_CLUSTER: 0: enabled 1
9166 11:37:03.826211 CPU: 00: enabled 1
9167 11:37:03.828913 Compare with tree...
9168 11:37:03.829427 Root Device: enabled 1
9169 11:37:03.832237 CPU_CLUSTER: 0: enabled 1
9170 11:37:03.835297 CPU: 00: enabled 1
9171 11:37:03.835750 Root Device scanning...
9172 11:37:03.839074 scan_static_bus for Root Device
9173 11:37:03.841740 CPU_CLUSTER: 0 enabled
9174 11:37:03.845308 scan_static_bus for Root Device done
9175 11:37:03.849010 scan_bus: bus Root Device finished in 8 msecs
9176 11:37:03.849509 done
9177 11:37:03.855653 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9178 11:37:03.858728 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9179 11:37:03.865075 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9180 11:37:03.872091 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9181 11:37:03.872582 Allocating resources...
9182 11:37:03.874982 Reading resources...
9183 11:37:03.878528 Root Device read_resources bus 0 link: 0
9184 11:37:03.881521 DRAM rank0 size:0x100000000,
9185 11:37:03.881901 DRAM rank1 size=0x100000000
9186 11:37:03.887992 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9187 11:37:03.888445 CPU: 00 missing read_resources
9188 11:37:03.894712 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9189 11:37:03.898028 Root Device read_resources bus 0 link: 0 done
9190 11:37:03.901334 Done reading resources.
9191 11:37:03.904618 Show resources in subtree (Root Device)...After reading.
9192 11:37:03.907859 Root Device child on link 0 CPU_CLUSTER: 0
9193 11:37:03.911116 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 11:37:03.921128 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 11:37:03.921759 CPU: 00
9196 11:37:03.927599 Root Device assign_resources, bus 0 link: 0
9197 11:37:03.931117 CPU_CLUSTER: 0 missing set_resources
9198 11:37:03.934233 Root Device assign_resources, bus 0 link: 0 done
9199 11:37:03.937760 Done setting resources.
9200 11:37:03.940437 Show resources in subtree (Root Device)...After assigning values.
9201 11:37:03.943944 Root Device child on link 0 CPU_CLUSTER: 0
9202 11:37:03.950608 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 11:37:03.957175 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 11:37:03.960545 CPU: 00
9205 11:37:03.960996 Done allocating resources.
9206 11:37:03.966937 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9207 11:37:03.967399 Enabling resources...
9208 11:37:03.970463 done.
9209 11:37:03.973670 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9210 11:37:03.976976 Initializing devices...
9211 11:37:03.977500 Root Device init
9212 11:37:03.980178 init hardware done!
9213 11:37:03.980558 0x00000018: ctrlr->caps
9214 11:37:03.983504 52.000 MHz: ctrlr->f_max
9215 11:37:03.986725 0.400 MHz: ctrlr->f_min
9216 11:37:03.989984 0x40ff8080: ctrlr->voltages
9217 11:37:03.990371 sclk: 390625
9218 11:37:03.990663 Bus Width = 1
9219 11:37:03.993675 sclk: 390625
9220 11:37:03.994141 Bus Width = 1
9221 11:37:03.996568 Early init status = 3
9222 11:37:04.000621 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9223 11:37:04.003326 in-header: 03 fc 00 00 01 00 00 00
9224 11:37:04.006736 in-data: 00
9225 11:37:04.010138 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9226 11:37:04.014748 in-header: 03 fd 00 00 00 00 00 00
9227 11:37:04.017703 in-data:
9228 11:37:04.020879 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9229 11:37:04.025075 in-header: 03 fc 00 00 01 00 00 00
9230 11:37:04.028112 in-data: 00
9231 11:37:04.031362 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9232 11:37:04.036886 in-header: 03 fd 00 00 00 00 00 00
9233 11:37:04.039906 in-data:
9234 11:37:04.043043 [SSUSB] Setting up USB HOST controller...
9235 11:37:04.046369 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9236 11:37:04.049797 [SSUSB] phy power-on done.
9237 11:37:04.052721 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9238 11:37:04.059525 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9239 11:37:04.062751 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9240 11:37:04.069098 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9241 11:37:04.075703 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9242 11:37:04.082871 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9243 11:37:04.089508 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9244 11:37:04.095796 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9245 11:37:04.099199 SPM: binary array size = 0x9dc
9246 11:37:04.102063 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9247 11:37:04.109214 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9248 11:37:04.116189 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9249 11:37:04.122380 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9250 11:37:04.125599 configure_display: Starting display init
9251 11:37:04.159950 anx7625_power_on_init: Init interface.
9252 11:37:04.162776 anx7625_disable_pd_protocol: Disabled PD feature.
9253 11:37:04.166416 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9254 11:37:04.194779 anx7625_start_dp_work: Secure OCM version=00
9255 11:37:04.197696 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9256 11:37:04.212389 sp_tx_get_edid_block: EDID Block = 1
9257 11:37:04.314930 Extracted contents:
9258 11:37:04.318812 header: 00 ff ff ff ff ff ff 00
9259 11:37:04.321869 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9260 11:37:04.324679 version: 01 04
9261 11:37:04.328282 basic params: 95 1f 11 78 0a
9262 11:37:04.331377 chroma info: 76 90 94 55 54 90 27 21 50 54
9263 11:37:04.334952 established: 00 00 00
9264 11:37:04.341475 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9265 11:37:04.347815 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9266 11:37:04.351072 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9267 11:37:04.358045 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9268 11:37:04.364690 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9269 11:37:04.367512 extensions: 00
9270 11:37:04.368135 checksum: fb
9271 11:37:04.368474
9272 11:37:04.374303 Manufacturer: IVO Model 57d Serial Number 0
9273 11:37:04.374828 Made week 0 of 2020
9274 11:37:04.377180 EDID version: 1.4
9275 11:37:04.377602 Digital display
9276 11:37:04.380611 6 bits per primary color channel
9277 11:37:04.383952 DisplayPort interface
9278 11:37:04.384335 Maximum image size: 31 cm x 17 cm
9279 11:37:04.387981 Gamma: 220%
9280 11:37:04.388436 Check DPMS levels
9281 11:37:04.394208 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9282 11:37:04.397330 First detailed timing is preferred timing
9283 11:37:04.400525 Established timings supported:
9284 11:37:04.400982 Standard timings supported:
9285 11:37:04.403776 Detailed timings
9286 11:37:04.407164 Hex of detail: 383680a07038204018303c0035ae10000019
9287 11:37:04.414573 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9288 11:37:04.417019 0780 0798 07c8 0820 hborder 0
9289 11:37:04.420597 0438 043b 0447 0458 vborder 0
9290 11:37:04.423822 -hsync -vsync
9291 11:37:04.424243 Did detailed timing
9292 11:37:04.430616 Hex of detail: 000000000000000000000000000000000000
9293 11:37:04.433864 Manufacturer-specified data, tag 0
9294 11:37:04.437396 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9295 11:37:04.440324 ASCII string: InfoVision
9296 11:37:04.443556 Hex of detail: 000000fe00523134304e574635205248200a
9297 11:37:04.446834 ASCII string: R140NWF5 RH
9298 11:37:04.447342 Checksum
9299 11:37:04.450469 Checksum: 0xfb (valid)
9300 11:37:04.454183 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9301 11:37:04.457258 DSI data_rate: 832800000 bps
9302 11:37:04.463449 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9303 11:37:04.466420 anx7625_parse_edid: pixelclock(138800).
9304 11:37:04.469649 hactive(1920), hsync(48), hfp(24), hbp(88)
9305 11:37:04.473167 vactive(1080), vsync(12), vfp(3), vbp(17)
9306 11:37:04.475962 anx7625_dsi_config: config dsi.
9307 11:37:04.482918 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9308 11:37:04.496478 anx7625_dsi_config: success to config DSI
9309 11:37:04.500318 anx7625_dp_start: MIPI phy setup OK.
9310 11:37:04.503127 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9311 11:37:04.506535 mtk_ddp_mode_set invalid vrefresh 60
9312 11:37:04.509604 main_disp_path_setup
9313 11:37:04.509836 ovl_layer_smi_id_en
9314 11:37:04.512729 ovl_layer_smi_id_en
9315 11:37:04.512913 ccorr_config
9316 11:37:04.513057 aal_config
9317 11:37:04.516457 gamma_config
9318 11:37:04.516879 postmask_config
9319 11:37:04.519620 dither_config
9320 11:37:04.523075 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9321 11:37:04.529467 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9322 11:37:04.533227 Root Device init finished in 552 msecs
9323 11:37:04.536346 CPU_CLUSTER: 0 init
9324 11:37:04.543004 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9325 11:37:04.546144 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9326 11:37:04.549970 APU_MBOX 0x190000b0 = 0x10001
9327 11:37:04.553534 APU_MBOX 0x190001b0 = 0x10001
9328 11:37:04.556447 APU_MBOX 0x190005b0 = 0x10001
9329 11:37:04.559953 APU_MBOX 0x190006b0 = 0x10001
9330 11:37:04.565913 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9331 11:37:04.575900 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9332 11:37:04.588584 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9333 11:37:04.594949 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9334 11:37:04.607179 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9335 11:37:04.615749 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9336 11:37:04.618681 CPU_CLUSTER: 0 init finished in 81 msecs
9337 11:37:04.621833 Devices initialized
9338 11:37:04.625660 Show all devs... After init.
9339 11:37:04.626117 Root Device: enabled 1
9340 11:37:04.628806 CPU_CLUSTER: 0: enabled 1
9341 11:37:04.632273 CPU: 00: enabled 1
9342 11:37:04.635752 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9343 11:37:04.638926 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9344 11:37:04.641881 ELOG: NV offset 0x57f000 size 0x1000
9345 11:37:04.648516 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9346 11:37:04.655345 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9347 11:37:04.659355 ELOG: Event(17) added with size 13 at 2024-07-17 11:37:04 UTC
9348 11:37:04.662659 out: cmd=0x121: 03 db 21 01 00 00 00 00
9349 11:37:04.666152 in-header: 03 ba 00 00 2c 00 00 00
9350 11:37:04.679246 in-data: 83 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 11:37:04.685870 ELOG: Event(A1) added with size 10 at 2024-07-17 11:37:04 UTC
9352 11:37:04.692852 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9353 11:37:04.699847 ELOG: Event(A0) added with size 9 at 2024-07-17 11:37:04 UTC
9354 11:37:04.702475 elog_add_boot_reason: Logged dev mode boot
9355 11:37:04.706079 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9356 11:37:04.709114 Finalize devices...
9357 11:37:04.709652 Devices finalized
9358 11:37:04.715047 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9359 11:37:04.718721 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9360 11:37:04.721695 in-header: 03 07 00 00 08 00 00 00
9361 11:37:04.725017 in-data: aa e4 47 04 13 02 00 00
9362 11:37:04.728469 Chrome EC: UHEPI supported
9363 11:37:04.734796 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9364 11:37:04.738404 in-header: 03 a9 00 00 08 00 00 00
9365 11:37:04.741791 in-data: 84 60 60 08 00 00 00 00
9366 11:37:04.748695 ELOG: Event(91) added with size 10 at 2024-07-17 11:37:04 UTC
9367 11:37:04.751675 Chrome EC: clear events_b mask to 0x0000000020004000
9368 11:37:04.757876 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9369 11:37:04.761609 in-header: 03 fd 00 00 00 00 00 00
9370 11:37:04.765306 in-data:
9371 11:37:04.768245 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9372 11:37:04.771975 Writing coreboot table at 0xffe64000
9373 11:37:04.775029 0. 000000000010a000-0000000000113fff: RAMSTAGE
9374 11:37:04.781592 1. 0000000040000000-00000000400fffff: RAM
9375 11:37:04.784926 2. 0000000040100000-000000004032afff: RAMSTAGE
9376 11:37:04.787930 3. 000000004032b000-00000000545fffff: RAM
9377 11:37:04.791502 4. 0000000054600000-000000005465ffff: BL31
9378 11:37:04.794512 5. 0000000054660000-00000000ffe63fff: RAM
9379 11:37:04.801187 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9380 11:37:04.804674 7. 0000000100000000-000000023fffffff: RAM
9381 11:37:04.807682 Passing 5 GPIOs to payload:
9382 11:37:04.811554 NAME | PORT | POLARITY | VALUE
9383 11:37:04.817808 EC in RW | 0x000000aa | low | undefined
9384 11:37:04.821039 EC interrupt | 0x00000005 | low | undefined
9385 11:37:04.827273 TPM interrupt | 0x000000ab | high | undefined
9386 11:37:04.830876 SD card detect | 0x00000011 | high | undefined
9387 11:37:04.833641 speaker enable | 0x00000093 | high | undefined
9388 11:37:04.837431 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9389 11:37:04.840901 in-header: 03 f9 00 00 02 00 00 00
9390 11:37:04.843971 in-data: 02 00
9391 11:37:04.847261 ADC[4]: Raw value=902955 ID=7
9392 11:37:04.850538 ADC[3]: Raw value=213916 ID=1
9393 11:37:04.850805 RAM Code: 0x71
9394 11:37:04.854036 ADC[6]: Raw value=74630 ID=0
9395 11:37:04.857218 ADC[5]: Raw value=213546 ID=1
9396 11:37:04.857488 SKU Code: 0x1
9397 11:37:04.864126 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5e9b
9398 11:37:04.864395 coreboot table: 964 bytes.
9399 11:37:04.867647 IMD ROOT 0. 0xfffff000 0x00001000
9400 11:37:04.870457 IMD SMALL 1. 0xffffe000 0x00001000
9401 11:37:04.873699 RO MCACHE 2. 0xffffc000 0x00001104
9402 11:37:04.877248 CONSOLE 3. 0xfff7c000 0x00080000
9403 11:37:04.880492 FMAP 4. 0xfff7b000 0x00000452
9404 11:37:04.883693 TIME STAMP 5. 0xfff7a000 0x00000910
9405 11:37:04.887416 VBOOT WORK 6. 0xfff66000 0x00014000
9406 11:37:04.890224 RAMOOPS 7. 0xffe66000 0x00100000
9407 11:37:04.894089 COREBOOT 8. 0xffe64000 0x00002000
9408 11:37:04.896632 IMD small region:
9409 11:37:04.900011 IMD ROOT 0. 0xffffec00 0x00000400
9410 11:37:04.903432 VPD 1. 0xffffeb80 0x0000006c
9411 11:37:04.906919 MMC STATUS 2. 0xffffeb60 0x00000004
9412 11:37:04.914371 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9413 11:37:04.919729 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9414 11:37:04.958331 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9415 11:37:04.961691 Checking segment from ROM address 0x40100000
9416 11:37:04.965037 Checking segment from ROM address 0x4010001c
9417 11:37:04.971452 Loading segment from ROM address 0x40100000
9418 11:37:04.971723 code (compression=0)
9419 11:37:04.981212 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9420 11:37:04.988646 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9421 11:37:04.988918 it's not compressed!
9422 11:37:04.995022 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9423 11:37:05.001567 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9424 11:37:05.018718 Loading segment from ROM address 0x4010001c
9425 11:37:05.019236 Entry Point 0x80000000
9426 11:37:05.022338 Loaded segments
9427 11:37:05.025855 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9428 11:37:05.032344 Jumping to boot code at 0x80000000(0xffe64000)
9429 11:37:05.038912 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9430 11:37:05.045243 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9431 11:37:05.053664 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9432 11:37:05.056780 Checking segment from ROM address 0x40100000
9433 11:37:05.060395 Checking segment from ROM address 0x4010001c
9434 11:37:05.066732 Loading segment from ROM address 0x40100000
9435 11:37:05.067116 code (compression=1)
9436 11:37:05.073514 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9437 11:37:05.083291 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9438 11:37:05.083734 using LZMA
9439 11:37:05.092217 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9440 11:37:05.098927 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9441 11:37:05.101994 Loading segment from ROM address 0x4010001c
9442 11:37:05.102498 Entry Point 0x54601000
9443 11:37:05.104981 Loaded segments
9444 11:37:05.108276 NOTICE: MT8192 bl31_setup
9445 11:37:05.115896 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9446 11:37:05.118985 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9447 11:37:05.121830 WARNING: region 0:
9448 11:37:05.125069 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 11:37:05.125471 WARNING: region 1:
9450 11:37:05.132366 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9451 11:37:05.135136 WARNING: region 2:
9452 11:37:05.138770 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9453 11:37:05.141656 WARNING: region 3:
9454 11:37:05.145298 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 11:37:05.148103 WARNING: region 4:
9456 11:37:05.155194 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 11:37:05.155593 WARNING: region 5:
9458 11:37:05.158493 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 11:37:05.161972 WARNING: region 6:
9460 11:37:05.165027 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 11:37:05.168585 WARNING: region 7:
9462 11:37:05.171761 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 11:37:05.178435 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9464 11:37:05.181591 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9465 11:37:05.187593 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9466 11:37:05.191156 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9467 11:37:05.194316 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9468 11:37:05.201069 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9469 11:37:05.204759 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9470 11:37:05.207902 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9471 11:37:05.214167 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9472 11:37:05.217603 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9473 11:37:05.223736 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9474 11:37:05.227533 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9475 11:37:05.230603 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9476 11:37:05.237020 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9477 11:37:05.240800 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9478 11:37:05.247127 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9479 11:37:05.250315 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9480 11:37:05.253599 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9481 11:37:05.260129 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9482 11:37:05.263346 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9483 11:37:05.270565 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9484 11:37:05.273934 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9485 11:37:05.276714 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9486 11:37:05.283374 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9487 11:37:05.286818 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9488 11:37:05.293060 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9489 11:37:05.296394 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9490 11:37:05.299591 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9491 11:37:05.306340 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9492 11:37:05.309663 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9493 11:37:05.316190 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9494 11:37:05.319404 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9495 11:37:05.323203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9496 11:37:05.329115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9497 11:37:05.332468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9498 11:37:05.336049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9499 11:37:05.338825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9500 11:37:05.345944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9501 11:37:05.349154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9502 11:37:05.352248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9503 11:37:05.355737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9504 11:37:05.361804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9505 11:37:05.365060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9506 11:37:05.368520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9507 11:37:05.372203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9508 11:37:05.378846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9509 11:37:05.382054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9510 11:37:05.385551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9511 11:37:05.391572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9512 11:37:05.394850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9513 11:37:05.401793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9514 11:37:05.405113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9515 11:37:05.408579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9516 11:37:05.415093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9517 11:37:05.418415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9518 11:37:05.424922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9519 11:37:05.428081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9520 11:37:05.434555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9521 11:37:05.437928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9522 11:37:05.444978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9523 11:37:05.448350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9524 11:37:05.454469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9525 11:37:05.457501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9526 11:37:05.461068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9527 11:37:05.467347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9528 11:37:05.470899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9529 11:37:05.477567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9530 11:37:05.481011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9531 11:37:05.487294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9532 11:37:05.491059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9533 11:37:05.494584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9534 11:37:05.500609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9535 11:37:05.503886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9536 11:37:05.511188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9537 11:37:05.513950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9538 11:37:05.520843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9539 11:37:05.523640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9540 11:37:05.530656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9541 11:37:05.533785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9542 11:37:05.540330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9543 11:37:05.543271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9544 11:37:05.546649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9545 11:37:05.553289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9546 11:37:05.556391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9547 11:37:05.563271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9548 11:37:05.566336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9549 11:37:05.573191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9550 11:37:05.576552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9551 11:37:05.582787 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9552 11:37:05.586272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9553 11:37:05.589460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9554 11:37:05.595922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9555 11:37:05.599752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9556 11:37:05.606050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9557 11:37:05.609795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9558 11:37:05.616621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9559 11:37:05.619328 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9560 11:37:05.622290 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9561 11:37:05.628843 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9562 11:37:05.632593 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9563 11:37:05.636026 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9564 11:37:05.638886 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9565 11:37:05.645636 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9566 11:37:05.649246 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9567 11:37:05.655699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9568 11:37:05.658628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9569 11:37:05.665565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9570 11:37:05.668567 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9571 11:37:05.672399 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9572 11:37:05.679257 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9573 11:37:05.682919 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9574 11:37:05.688555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9575 11:37:05.692296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9576 11:37:05.695257 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9577 11:37:05.701691 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9578 11:37:05.705489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9579 11:37:05.708797 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9580 11:37:05.714839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9581 11:37:05.718672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9582 11:37:05.721509 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9583 11:37:05.728242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9584 11:37:05.731839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9585 11:37:05.735168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9586 11:37:05.738206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9587 11:37:05.744694 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9588 11:37:05.747830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9589 11:37:05.754513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9590 11:37:05.757839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9591 11:37:05.761297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9592 11:37:05.767744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9593 11:37:05.771193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9594 11:37:05.777403 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9595 11:37:05.781251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9596 11:37:05.784539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9597 11:37:05.791034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9598 11:37:05.793853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9599 11:37:05.801022 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9600 11:37:05.803920 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9601 11:37:05.807231 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9602 11:37:05.813962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9603 11:37:05.817012 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9604 11:37:05.823893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9605 11:37:05.827183 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9606 11:37:05.830385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9607 11:37:05.837587 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9608 11:37:05.840176 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9609 11:37:05.847452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9610 11:37:05.850049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9611 11:37:05.854343 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9612 11:37:05.860478 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9613 11:37:05.863461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9614 11:37:05.870505 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9615 11:37:05.872894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9616 11:37:05.876279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9617 11:37:05.883547 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9618 11:37:05.886437 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9619 11:37:05.893463 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9620 11:37:05.896801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9621 11:37:05.899784 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9622 11:37:05.906388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9623 11:37:05.909849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9624 11:37:05.915940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9625 11:37:05.919511 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9626 11:37:05.922840 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9627 11:37:05.929437 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9628 11:37:05.933221 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9629 11:37:05.939407 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9630 11:37:05.942460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9631 11:37:05.945886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9632 11:37:05.952779 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9633 11:37:05.955567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9634 11:37:05.962432 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9635 11:37:05.965422 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9636 11:37:05.968722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9637 11:37:05.975559 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9638 11:37:05.978508 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9639 11:37:05.985043 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9640 11:37:05.988758 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9641 11:37:05.995226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9642 11:37:05.998442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9643 11:37:06.002089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9644 11:37:06.008479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9645 11:37:06.011801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9646 11:37:06.018633 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9647 11:37:06.021345 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9648 11:37:06.025470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9649 11:37:06.031624 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9650 11:37:06.034961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9651 11:37:06.041503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9652 11:37:06.044467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9653 11:37:06.048692 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9654 11:37:06.054874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9655 11:37:06.058049 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9656 11:37:06.064673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9657 11:37:06.067660 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9658 11:37:06.074295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9659 11:37:06.077520 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9660 11:37:06.081473 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9661 11:37:06.087421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9662 11:37:06.090831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9663 11:37:06.097777 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9664 11:37:06.100722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9665 11:37:06.107497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9666 11:37:06.110563 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9667 11:37:06.114007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9668 11:37:06.120547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9669 11:37:06.123407 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9670 11:37:06.130216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9671 11:37:06.133781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9672 11:37:06.140658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9673 11:37:06.143352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9674 11:37:06.146669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9675 11:37:06.153205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9676 11:37:06.156886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9677 11:37:06.163177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9678 11:37:06.166197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9679 11:37:06.172887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9680 11:37:06.176321 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9681 11:37:06.179723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9682 11:37:06.186155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9683 11:37:06.189126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9684 11:37:06.195817 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9685 11:37:06.199438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9686 11:37:06.205769 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9687 11:37:06.209221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9688 11:37:06.212323 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9689 11:37:06.219384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9690 11:37:06.222503 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9691 11:37:06.228932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9692 11:37:06.231982 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9693 11:37:06.235371 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9694 11:37:06.239244 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9695 11:37:06.245839 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9696 11:37:06.248405 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9697 11:37:06.251943 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9698 11:37:06.258661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9699 11:37:06.262329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9700 11:37:06.265060 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9701 11:37:06.271827 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9702 11:37:06.275359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9703 11:37:06.278550 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9704 11:37:06.285411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9705 11:37:06.288418 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9706 11:37:06.294660 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9707 11:37:06.298634 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9708 11:37:06.301765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9709 11:37:06.308497 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9710 11:37:06.311699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9711 11:37:06.315027 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9712 11:37:06.321705 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9713 11:37:06.324848 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9714 11:37:06.331807 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9715 11:37:06.335079 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9716 11:37:06.337850 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9717 11:37:06.344443 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9718 11:37:06.347401 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9719 11:37:06.351478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9720 11:37:06.357682 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9721 11:37:06.360833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9722 11:37:06.368039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9723 11:37:06.370750 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9724 11:37:06.373988 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9725 11:37:06.381228 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9726 11:37:06.383748 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9727 11:37:06.387895 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9728 11:37:06.393875 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9729 11:37:06.397208 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9730 11:37:06.403734 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9731 11:37:06.406966 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9732 11:37:06.410448 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9733 11:37:06.413685 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9734 11:37:06.420930 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9735 11:37:06.423610 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9736 11:37:06.427152 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9737 11:37:06.430811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9738 11:37:06.437227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9739 11:37:06.440066 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9740 11:37:06.443480 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9741 11:37:06.446658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9742 11:37:06.453226 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9743 11:37:06.457104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9744 11:37:06.460134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9745 11:37:06.466370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9746 11:37:06.469815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9747 11:37:06.476934 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9748 11:37:06.479667 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9749 11:37:06.482733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9750 11:37:06.489525 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9751 11:37:06.492610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9752 11:37:06.499281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9753 11:37:06.502614 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9754 11:37:06.505838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9755 11:37:06.512537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9756 11:37:06.515671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9757 11:37:06.522514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9758 11:37:06.525434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9759 11:37:06.532283 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9760 11:37:06.536046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9761 11:37:06.538987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9762 11:37:06.545344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9763 11:37:06.548576 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9764 11:37:06.555761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9765 11:37:06.558559 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9766 11:37:06.565466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9767 11:37:06.568423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9768 11:37:06.571788 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9769 11:37:06.578099 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9770 11:37:06.581708 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9771 11:37:06.588609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9772 11:37:06.591823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9773 11:37:06.595337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9774 11:37:06.601570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9775 11:37:06.604916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9776 11:37:06.611741 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9777 11:37:06.614848 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9778 11:37:06.617828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9779 11:37:06.624507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9780 11:37:06.627883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9781 11:37:06.635040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9782 11:37:06.637734 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9783 11:37:06.644448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9784 11:37:06.648027 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9785 11:37:06.651768 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9786 11:37:06.657556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9787 11:37:06.660730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9788 11:37:06.667578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9789 11:37:06.671326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9790 11:37:06.677511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9791 11:37:06.681050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9792 11:37:06.684041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9793 11:37:06.691154 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9794 11:37:06.693916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9795 11:37:06.700806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9796 11:37:06.703808 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9797 11:37:06.707623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9798 11:37:06.713968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9799 11:37:06.717048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9800 11:37:06.723662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9801 11:37:06.726782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9802 11:37:06.730326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9803 11:37:06.736884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9804 11:37:06.740369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9805 11:37:06.746962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9806 11:37:06.750367 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9807 11:37:06.756550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9808 11:37:06.759835 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9809 11:37:06.763282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9810 11:37:06.770081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9811 11:37:06.773366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9812 11:37:06.779761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9813 11:37:06.783011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9814 11:37:06.789784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9815 11:37:06.793009 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9816 11:37:06.796547 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9817 11:37:06.803389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9818 11:37:06.806112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9819 11:37:06.813308 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9820 11:37:06.816854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9821 11:37:06.822770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9822 11:37:06.826154 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9823 11:37:06.829185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9824 11:37:06.836099 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9825 11:37:06.838805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9826 11:37:06.845988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9827 11:37:06.849434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9828 11:37:06.855786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9829 11:37:06.859721 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9830 11:37:06.865536 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9831 11:37:06.869197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9832 11:37:06.872978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9833 11:37:06.879238 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9834 11:37:06.882315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9835 11:37:06.888707 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9836 11:37:06.892123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9837 11:37:06.898990 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9838 11:37:06.902060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9839 11:37:06.908590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9840 11:37:06.911968 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9841 11:37:06.915379 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9842 11:37:06.921550 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9843 11:37:06.925244 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9844 11:37:06.932049 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9845 11:37:06.935198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9846 11:37:06.941382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9847 11:37:06.944994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9848 11:37:06.947718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9849 11:37:06.954500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9850 11:37:06.958043 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9851 11:37:06.964475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9852 11:37:06.967638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9853 11:37:06.974918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9854 11:37:06.978061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9855 11:37:06.984268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9856 11:37:06.987406 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9857 11:37:06.991360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9858 11:37:06.997592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9859 11:37:07.001200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9860 11:37:07.007063 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9861 11:37:07.009900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9862 11:37:07.017447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9863 11:37:07.020919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9864 11:37:07.026903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9865 11:37:07.030603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9866 11:37:07.033619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9867 11:37:07.040829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9868 11:37:07.043665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9869 11:37:07.049928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9870 11:37:07.053489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9871 11:37:07.059919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9872 11:37:07.063589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9873 11:37:07.070271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9874 11:37:07.073956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9875 11:37:07.079872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9876 11:37:07.082966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9877 11:37:07.089933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9878 11:37:07.092743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9879 11:37:07.100063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9880 11:37:07.103048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9881 11:37:07.109701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9882 11:37:07.112754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9883 11:37:07.119575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9884 11:37:07.122202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9885 11:37:07.129226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9886 11:37:07.132602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9887 11:37:07.139022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9888 11:37:07.142507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9889 11:37:07.149191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9890 11:37:07.152354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9891 11:37:07.158400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9892 11:37:07.161971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9893 11:37:07.168750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9894 11:37:07.172256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9895 11:37:07.178391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9896 11:37:07.181568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9897 11:37:07.187924 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9898 11:37:07.188428 INFO: [APUAPC] vio 0
9899 11:37:07.194995 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9900 11:37:07.198629 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9901 11:37:07.201857 INFO: [APUAPC] D0_APC_0: 0x400510
9902 11:37:07.204950 INFO: [APUAPC] D0_APC_1: 0x0
9903 11:37:07.208764 INFO: [APUAPC] D0_APC_2: 0x1540
9904 11:37:07.211837 INFO: [APUAPC] D0_APC_3: 0x0
9905 11:37:07.215553 INFO: [APUAPC] D1_APC_0: 0xffffffff
9906 11:37:07.218407 INFO: [APUAPC] D1_APC_1: 0xffffffff
9907 11:37:07.221668 INFO: [APUAPC] D1_APC_2: 0x3fffff
9908 11:37:07.224762 INFO: [APUAPC] D1_APC_3: 0x0
9909 11:37:07.228317 INFO: [APUAPC] D2_APC_0: 0xffffffff
9910 11:37:07.232286 INFO: [APUAPC] D2_APC_1: 0xffffffff
9911 11:37:07.235160 INFO: [APUAPC] D2_APC_2: 0x3fffff
9912 11:37:07.238561 INFO: [APUAPC] D2_APC_3: 0x0
9913 11:37:07.241912 INFO: [APUAPC] D3_APC_0: 0xffffffff
9914 11:37:07.245002 INFO: [APUAPC] D3_APC_1: 0xffffffff
9915 11:37:07.248042 INFO: [APUAPC] D3_APC_2: 0x3fffff
9916 11:37:07.250978 INFO: [APUAPC] D3_APC_3: 0x0
9917 11:37:07.255057 INFO: [APUAPC] D4_APC_0: 0xffffffff
9918 11:37:07.258406 INFO: [APUAPC] D4_APC_1: 0xffffffff
9919 11:37:07.261192 INFO: [APUAPC] D4_APC_2: 0x3fffff
9920 11:37:07.264911 INFO: [APUAPC] D4_APC_3: 0x0
9921 11:37:07.267784 INFO: [APUAPC] D5_APC_0: 0xffffffff
9922 11:37:07.271255 INFO: [APUAPC] D5_APC_1: 0xffffffff
9923 11:37:07.274364 INFO: [APUAPC] D5_APC_2: 0x3fffff
9924 11:37:07.274757 INFO: [APUAPC] D5_APC_3: 0x0
9925 11:37:07.281512 INFO: [APUAPC] D6_APC_0: 0xffffffff
9926 11:37:07.284650 INFO: [APUAPC] D6_APC_1: 0xffffffff
9927 11:37:07.287847 INFO: [APUAPC] D6_APC_2: 0x3fffff
9928 11:37:07.288353 INFO: [APUAPC] D6_APC_3: 0x0
9929 11:37:07.292172 INFO: [APUAPC] D7_APC_0: 0xffffffff
9930 11:37:07.297903 INFO: [APUAPC] D7_APC_1: 0xffffffff
9931 11:37:07.301544 INFO: [APUAPC] D7_APC_2: 0x3fffff
9932 11:37:07.302001 INFO: [APUAPC] D7_APC_3: 0x0
9933 11:37:07.304701 INFO: [APUAPC] D8_APC_0: 0xffffffff
9934 11:37:07.307427 INFO: [APUAPC] D8_APC_1: 0xffffffff
9935 11:37:07.310979 INFO: [APUAPC] D8_APC_2: 0x3fffff
9936 11:37:07.314176 INFO: [APUAPC] D8_APC_3: 0x0
9937 11:37:07.317842 INFO: [APUAPC] D9_APC_0: 0xffffffff
9938 11:37:07.321178 INFO: [APUAPC] D9_APC_1: 0xffffffff
9939 11:37:07.323584 INFO: [APUAPC] D9_APC_2: 0x3fffff
9940 11:37:07.327480 INFO: [APUAPC] D9_APC_3: 0x0
9941 11:37:07.330535 INFO: [APUAPC] D10_APC_0: 0xffffffff
9942 11:37:07.333926 INFO: [APUAPC] D10_APC_1: 0xffffffff
9943 11:37:07.337459 INFO: [APUAPC] D10_APC_2: 0x3fffff
9944 11:37:07.341002 INFO: [APUAPC] D10_APC_3: 0x0
9945 11:37:07.343603 INFO: [APUAPC] D11_APC_0: 0xffffffff
9946 11:37:07.347348 INFO: [APUAPC] D11_APC_1: 0xffffffff
9947 11:37:07.350501 INFO: [APUAPC] D11_APC_2: 0x3fffff
9948 11:37:07.354202 INFO: [APUAPC] D11_APC_3: 0x0
9949 11:37:07.357223 INFO: [APUAPC] D12_APC_0: 0xffffffff
9950 11:37:07.360875 INFO: [APUAPC] D12_APC_1: 0xffffffff
9951 11:37:07.363663 INFO: [APUAPC] D12_APC_2: 0x3fffff
9952 11:37:07.366908 INFO: [APUAPC] D12_APC_3: 0x0
9953 11:37:07.370126 INFO: [APUAPC] D13_APC_0: 0xffffffff
9954 11:37:07.373974 INFO: [APUAPC] D13_APC_1: 0xffffffff
9955 11:37:07.380367 INFO: [APUAPC] D13_APC_2: 0x3fffff
9956 11:37:07.380838 INFO: [APUAPC] D13_APC_3: 0x0
9957 11:37:07.383768 INFO: [APUAPC] D14_APC_0: 0xffffffff
9958 11:37:07.389957 INFO: [APUAPC] D14_APC_1: 0xffffffff
9959 11:37:07.393618 INFO: [APUAPC] D14_APC_2: 0x3fffff
9960 11:37:07.394053 INFO: [APUAPC] D14_APC_3: 0x0
9961 11:37:07.399996 INFO: [APUAPC] D15_APC_0: 0xffffffff
9962 11:37:07.403680 INFO: [APUAPC] D15_APC_1: 0xffffffff
9963 11:37:07.406717 INFO: [APUAPC] D15_APC_2: 0x3fffff
9964 11:37:07.409803 INFO: [APUAPC] D15_APC_3: 0x0
9965 11:37:07.410202 INFO: [APUAPC] APC_CON: 0x4
9966 11:37:07.413262 INFO: [NOCDAPC] D0_APC_0: 0x0
9967 11:37:07.416711 INFO: [NOCDAPC] D0_APC_1: 0x0
9968 11:37:07.420061 INFO: [NOCDAPC] D1_APC_0: 0x0
9969 11:37:07.423170 INFO: [NOCDAPC] D1_APC_1: 0xfff
9970 11:37:07.426200 INFO: [NOCDAPC] D2_APC_0: 0x0
9971 11:37:07.429660 INFO: [NOCDAPC] D2_APC_1: 0xfff
9972 11:37:07.433441 INFO: [NOCDAPC] D3_APC_0: 0x0
9973 11:37:07.436169 INFO: [NOCDAPC] D3_APC_1: 0xfff
9974 11:37:07.439297 INFO: [NOCDAPC] D4_APC_0: 0x0
9975 11:37:07.439699 INFO: [NOCDAPC] D4_APC_1: 0xfff
9976 11:37:07.442641 INFO: [NOCDAPC] D5_APC_0: 0x0
9977 11:37:07.446370 INFO: [NOCDAPC] D5_APC_1: 0xfff
9978 11:37:07.449289 INFO: [NOCDAPC] D6_APC_0: 0x0
9979 11:37:07.452476 INFO: [NOCDAPC] D6_APC_1: 0xfff
9980 11:37:07.455614 INFO: [NOCDAPC] D7_APC_0: 0x0
9981 11:37:07.459532 INFO: [NOCDAPC] D7_APC_1: 0xfff
9982 11:37:07.462460 INFO: [NOCDAPC] D8_APC_0: 0x0
9983 11:37:07.465702 INFO: [NOCDAPC] D8_APC_1: 0xfff
9984 11:37:07.469270 INFO: [NOCDAPC] D9_APC_0: 0x0
9985 11:37:07.472597 INFO: [NOCDAPC] D9_APC_1: 0xfff
9986 11:37:07.476023 INFO: [NOCDAPC] D10_APC_0: 0x0
9987 11:37:07.479248 INFO: [NOCDAPC] D10_APC_1: 0xfff
9988 11:37:07.479632 INFO: [NOCDAPC] D11_APC_0: 0x0
9989 11:37:07.482047 INFO: [NOCDAPC] D11_APC_1: 0xfff
9990 11:37:07.485733 INFO: [NOCDAPC] D12_APC_0: 0x0
9991 11:37:07.488800 INFO: [NOCDAPC] D12_APC_1: 0xfff
9992 11:37:07.492253 INFO: [NOCDAPC] D13_APC_0: 0x0
9993 11:37:07.495540 INFO: [NOCDAPC] D13_APC_1: 0xfff
9994 11:37:07.499386 INFO: [NOCDAPC] D14_APC_0: 0x0
9995 11:37:07.501958 INFO: [NOCDAPC] D14_APC_1: 0xfff
9996 11:37:07.505734 INFO: [NOCDAPC] D15_APC_0: 0x0
9997 11:37:07.508719 INFO: [NOCDAPC] D15_APC_1: 0xfff
9998 11:37:07.512643 INFO: [NOCDAPC] APC_CON: 0x4
9999 11:37:07.515489 INFO: [APUAPC] set_apusys_apc done
10000 11:37:07.518408 INFO: [DEVAPC] devapc_init done
10001 11:37:07.521881 INFO: GICv3 without legacy support detected.
10002 11:37:07.525383 INFO: ARM GICv3 driver initialized in EL3
10003 11:37:07.528229 INFO: Maximum SPI INTID supported: 639
10004 11:37:07.535225 INFO: BL31: Initializing runtime services
10005 11:37:07.538153 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10006 11:37:07.542174 INFO: SPM: enable CPC mode
10007 11:37:07.548464 INFO: mcdi ready for mcusys-off-idle and system suspend
10008 11:37:07.551512 INFO: BL31: Preparing for EL3 exit to normal world
10009 11:37:07.554939 INFO: Entry point address = 0x80000000
10010 11:37:07.558017 INFO: SPSR = 0x8
10011 11:37:07.563498
10012 11:37:07.563951
10013 11:37:07.564245
10014 11:37:07.567071 Starting depthcharge on Spherion...
10015 11:37:07.567451
10016 11:37:07.567745 Wipe memory regions:
10017 11:37:07.568015
10018 11:37:07.570184 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10019 11:37:07.570634 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10020 11:37:07.570989 Setting prompt string to ['asurada:']
10021 11:37:07.571305 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10022 11:37:07.571873 [0x00000040000000, 0x00000054600000)
10023 11:37:07.692880
10024 11:37:07.693499 [0x00000054660000, 0x00000080000000)
10025 11:37:07.953031
10026 11:37:07.953520 [0x000000821a7280, 0x000000ffe64000)
10027 11:37:08.698053
10028 11:37:08.698511 [0x00000100000000, 0x00000240000000)
10029 11:37:10.587903
10030 11:37:10.591362 Initializing XHCI USB controller at 0x11200000.
10031 11:37:11.629600
10032 11:37:11.632731 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10033 11:37:11.633177
10034 11:37:11.633513
10035 11:37:11.634281 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 11:37:11.634681 Sending line: 'tftpboot 192.168.201.1 14864646/tftp-deploy-5majoj1q/kernel/image.itb 14864646/tftp-deploy-5majoj1q/kernel/cmdline '
10038 11:37:11.736184 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 11:37:11.736668 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10040 11:37:11.741075 asurada: tftpboot 192.168.201.1 14864646/tftp-deploy-5majoj1q/kernel/image.itp-deploy-5majoj1q/kernel/cmdline
10041 11:37:11.741556
10042 11:37:11.741887 Waiting for link
10043 11:37:11.899391
10044 11:37:11.899883 R8152: Initializing
10045 11:37:11.900213
10046 11:37:11.902499 Version 6 (ocp_data = 5c30)
10047 11:37:11.902962
10048 11:37:11.905660 R8152: Done initializing
10049 11:37:11.906103
10050 11:37:11.906631 Adding net device
10051 11:37:13.950115
10052 11:37:13.950607 done.
10053 11:37:13.950932
10054 11:37:13.951230 MAC: 00:24:32:30:7c:7b
10055 11:37:13.951518
10056 11:37:13.952624 Sending DHCP discover... done.
10057 11:37:13.953039
10058 11:37:17.161278 Waiting for reply... done.
10059 11:37:17.161714
10060 11:37:17.162009 Sending DHCP request... done.
10061 11:37:17.163617
10062 11:37:17.163997 Waiting for reply... done.
10063 11:37:17.164290
10064 11:37:17.167384 My ip is 192.168.201.14
10065 11:37:17.167810
10066 11:37:17.170235 The DHCP server ip is 192.168.201.1
10067 11:37:17.170610
10068 11:37:17.173815 TFTP server IP predefined by user: 192.168.201.1
10069 11:37:17.174194
10070 11:37:17.180635 Bootfile predefined by user: 14864646/tftp-deploy-5majoj1q/kernel/image.itb
10071 11:37:17.181015
10072 11:37:17.183529 Sending tftp read request... done.
10073 11:37:17.183906
10074 11:37:17.192097 Waiting for the transfer...
10075 11:37:17.192479
10076 11:37:17.906388 00000000 ################################################################
10077 11:37:17.906867
10078 11:37:18.630274 00080000 ################################################################
10079 11:37:18.630748
10080 11:37:19.348468 00100000 ################################################################
10081 11:37:19.348928
10082 11:37:20.070610 00180000 ################################################################
10083 11:37:20.071127
10084 11:37:20.792826 00200000 ################################################################
10085 11:37:20.793368
10086 11:37:21.504967 00280000 ################################################################
10087 11:37:21.505505
10088 11:37:22.212023 00300000 ################################################################
10089 11:37:22.212500
10090 11:37:22.915743 00380000 ################################################################
10091 11:37:22.916248
10092 11:37:23.583190 00400000 ################################################################
10093 11:37:23.583671
10094 11:37:24.299501 00480000 ################################################################
10095 11:37:24.299979
10096 11:37:25.013543 00500000 ################################################################
10097 11:37:25.014046
10098 11:37:25.730012 00580000 ################################################################
10099 11:37:25.730511
10100 11:37:26.451370 00600000 ################################################################
10101 11:37:26.451888
10102 11:37:27.172162 00680000 ################################################################
10103 11:37:27.172643
10104 11:37:27.888906 00700000 ################################################################
10105 11:37:27.889482
10106 11:37:28.604216 00780000 ################################################################
10107 11:37:28.604722
10108 11:37:29.300725 00800000 ################################################################
10109 11:37:29.301274
10110 11:37:30.003201 00880000 ################################################################
10111 11:37:30.003677
10112 11:37:30.713802 00900000 ################################################################
10113 11:37:30.714279
10114 11:37:31.445462 00980000 ################################################################
10115 11:37:31.445929
10116 11:37:32.181959 00a00000 ################################################################
10117 11:37:32.182440
10118 11:37:32.903543 00a80000 ################################################################
10119 11:37:32.904032
10120 11:37:33.621079 00b00000 ################################################################
10121 11:37:33.621567
10122 11:37:34.334522 00b80000 ################################################################
10123 11:37:34.335059
10124 11:37:35.046816 00c00000 ################################################################
10125 11:37:35.047274
10126 11:37:35.733285 00c80000 ################################################################
10127 11:37:35.733834
10128 11:37:36.437821 00d00000 ################################################################
10129 11:37:36.438287
10130 11:37:37.164447 00d80000 ################################################################
10131 11:37:37.164953
10132 11:37:37.888274 00e00000 ################################################################
10133 11:37:37.888802
10134 11:37:38.602751 00e80000 ################################################################
10135 11:37:38.603210
10136 11:37:39.307353 00f00000 ################################################################
10137 11:37:39.307847
10138 11:37:40.017571 00f80000 ################################################################
10139 11:37:40.018065
10140 11:37:40.731634 01000000 ################################################################
10141 11:37:40.732208
10142 11:37:41.422382 01080000 ################################################################
10143 11:37:41.422852
10144 11:37:42.130144 01100000 ################################################################
10145 11:37:42.130626
10146 11:37:42.849069 01180000 ################################################################
10147 11:37:42.849604
10148 11:37:43.573904 01200000 ################################################################
10149 11:37:43.574351
10150 11:37:44.264926 01280000 ################################################################
10151 11:37:44.265429
10152 11:37:44.959020 01300000 ################################################################
10153 11:37:44.959488
10154 11:37:45.682522 01380000 ################################################################
10155 11:37:45.682985
10156 11:37:46.386262 01400000 ################################################################
10157 11:37:46.386748
10158 11:37:47.101197 01480000 ################################################################
10159 11:37:47.101664
10160 11:37:47.776181 01500000 ################################################################
10161 11:37:47.776635
10162 11:37:48.494555 01580000 ################################################################
10163 11:37:48.495051
10164 11:37:49.208892 01600000 ################################################################
10165 11:37:49.209397
10166 11:37:49.935654 01680000 ################################################################
10167 11:37:49.936112
10168 11:37:50.653918 01700000 ################################################################
10169 11:37:50.654396
10170 11:37:51.367763 01780000 ################################################################
10171 11:37:51.368224
10172 11:37:52.070141 01800000 ################################################################
10173 11:37:52.070600
10174 11:37:52.760295 01880000 ################################################################
10175 11:37:52.760761
10176 11:37:53.428218 01900000 ################################################################
10177 11:37:53.428703
10178 11:37:54.159248 01980000 ################################################################
10179 11:37:54.159729
10180 11:37:54.889760 01a00000 ################################################################
10181 11:37:54.890237
10182 11:37:55.606269 01a80000 ################################################################
10183 11:37:55.606737
10184 11:37:56.316093 01b00000 ################################################################
10185 11:37:56.316587
10186 11:37:57.040538 01b80000 ################################################################
10187 11:37:57.041127
10188 11:37:57.758516 01c00000 ################################################################
10189 11:37:57.759048
10190 11:37:58.475096 01c80000 ################################################################
10191 11:37:58.475577
10192 11:37:59.172380 01d00000 ################################################################
10193 11:37:59.172503
10194 11:37:59.865033 01d80000 ################################################################
10195 11:37:59.865614
10196 11:38:00.506605 01e00000 ################################################################
10197 11:38:00.506726
10198 11:38:01.199840 01e80000 ################################################################
10199 11:38:01.199988
10200 11:38:01.889312 01f00000 ################################################################
10201 11:38:01.889787
10202 11:38:02.526623 01f80000 ################################################################
10203 11:38:02.527245
10204 11:38:03.226224 02000000 ################################################################
10205 11:38:03.226849
10206 11:38:03.907965 02080000 ################################################################
10207 11:38:03.908428
10208 11:38:04.612617 02100000 ################################################################
10209 11:38:04.613116
10210 11:38:05.293498 02180000 ################################################################
10211 11:38:05.293656
10212 11:38:05.866477 02200000 ################################################################
10213 11:38:05.866595
10214 11:38:06.571556 02280000 ################################################################
10215 11:38:06.572109
10216 11:38:07.279378 02300000 ################################################################
10217 11:38:07.279862
10218 11:38:07.995381 02380000 ################################################################
10219 11:38:07.995854
10220 11:38:08.712918 02400000 ################################################################
10221 11:38:08.713444
10222 11:38:09.425830 02480000 ################################################################
10223 11:38:09.426372
10224 11:38:10.160529 02500000 ################################################################
10225 11:38:10.160993
10226 11:38:10.882693 02580000 ################################################################
10227 11:38:10.883170
10228 11:38:11.580974 02600000 ################################################################
10229 11:38:11.581503
10230 11:38:12.301250 02680000 ################################################################
10231 11:38:12.301771
10232 11:38:13.018741 02700000 ################################################################
10233 11:38:13.019368
10234 11:38:13.729090 02780000 ################################################################
10235 11:38:13.729639
10236 11:38:14.440858 02800000 ################################################################
10237 11:38:14.441379
10238 11:38:15.152906 02880000 ################################################################
10239 11:38:15.153415
10240 11:38:15.859806 02900000 ################################################################
10241 11:38:15.860278
10242 11:38:16.565964 02980000 ################################################################
10243 11:38:16.566442
10244 11:38:17.240076 02a00000 ################################################################
10245 11:38:17.240512
10246 11:38:17.941874 02a80000 ################################################################
10247 11:38:17.942333
10248 11:38:18.636525 02b00000 ################################################################
10249 11:38:18.636990
10250 11:38:19.344249 02b80000 ################################################################
10251 11:38:19.344758
10252 11:38:20.047091 02c00000 ################################################################
10253 11:38:20.047641
10254 11:38:20.739897 02c80000 ################################################################
10255 11:38:20.740400
10256 11:38:21.456390 02d00000 ################################################################
10257 11:38:21.456884
10258 11:38:22.174657 02d80000 ################################################################
10259 11:38:22.175106
10260 11:38:22.892308 02e00000 ################################################################
10261 11:38:22.892858
10262 11:38:23.591884 02e80000 ################################################################
10263 11:38:23.592400
10264 11:38:24.297058 02f00000 ################################################################
10265 11:38:24.297601
10266 11:38:25.003697 02f80000 ################################################################
10267 11:38:25.004180
10268 11:38:25.710042 03000000 ################################################################
10269 11:38:25.710572
10270 11:38:26.412868 03080000 ################################################################
10271 11:38:26.413472
10272 11:38:27.114059 03100000 ################################################################
10273 11:38:27.114566
10274 11:38:27.822388 03180000 ################################################################
10275 11:38:27.822845
10276 11:38:28.527677 03200000 ################################################################
10277 11:38:28.528194
10278 11:38:29.216273 03280000 ################################################################
10279 11:38:29.216715
10280 11:38:29.922540 03300000 ################################################################
10281 11:38:29.922991
10282 11:38:30.627399 03380000 ################################################################
10283 11:38:30.627876
10284 11:38:31.341225 03400000 ################################################################
10285 11:38:31.341690
10286 11:38:32.050744 03480000 ################################################################
10287 11:38:32.051192
10288 11:38:32.754233 03500000 ################################################################
10289 11:38:32.754716
10290 11:38:33.460828 03580000 ################################################################
10291 11:38:33.461338
10292 11:38:34.170707 03600000 ################################################################
10293 11:38:34.171166
10294 11:38:34.874486 03680000 ################################################################
10295 11:38:34.874990
10296 11:38:35.572970 03700000 ################################################################
10297 11:38:35.573469
10298 11:38:36.291127 03780000 ################################################################
10299 11:38:36.291595
10300 11:38:37.002855 03800000 ################################################################
10301 11:38:37.003317
10302 11:38:37.692763 03880000 ################################################################
10303 11:38:37.693255
10304 11:38:38.398498 03900000 ################################################################
10305 11:38:38.398943
10306 11:38:39.102033 03980000 ################################################################
10307 11:38:39.102508
10308 11:38:39.805619 03a00000 ################################################################
10309 11:38:39.806089
10310 11:38:40.507013 03a80000 ################################################################
10311 11:38:40.507473
10312 11:38:41.207392 03b00000 ################################################################
10313 11:38:41.207860
10314 11:38:41.906661 03b80000 ################################################################
10315 11:38:41.907125
10316 11:38:42.503751 03c00000 ################################################################
10317 11:38:42.503935
10318 11:38:43.061908 03c80000 ################################################################
10319 11:38:43.062093
10320 11:38:43.629951 03d00000 ################################################################
10321 11:38:43.630085
10322 11:38:44.195786 03d80000 ################################################################
10323 11:38:44.195918
10324 11:38:44.496787 03e00000 ################################### done.
10325 11:38:44.496922
10326 11:38:44.499894 The bootfile was 65298142 bytes long.
10327 11:38:44.500050
10328 11:38:44.503280 Sending tftp read request... done.
10329 11:38:44.503405
10330 11:38:44.503465 Waiting for the transfer...
10331 11:38:44.503519
10332 11:38:44.506380 00000000 # done.
10333 11:38:44.506530
10334 11:38:44.513044 Command line loaded dynamically from TFTP file: 14864646/tftp-deploy-5majoj1q/kernel/cmdline
10335 11:38:44.513231
10336 11:38:44.526549 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10337 11:38:44.526676
10338 11:38:44.529673 Loading FIT.
10339 11:38:44.529793
10340 11:38:44.533349 Image ramdisk-1 has 52130564 bytes.
10341 11:38:44.533445
10342 11:38:44.533505 Image fdt-1 has 47258 bytes.
10343 11:38:44.533560
10344 11:38:44.536134 Image kernel-1 has 13118294 bytes.
10345 11:38:44.536249
10346 11:38:44.546164 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10347 11:38:44.546321
10348 11:38:44.563086 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10349 11:38:44.563220
10350 11:38:44.569677 Choosing best match conf-1 for compat google,spherion-rev2.
10351 11:38:44.573758
10352 11:38:44.578304 Connected to device vid:did:rid of 1ae0:0028:00
10353 11:38:44.585911
10354 11:38:44.588476 tpm_get_response: command 0x17b, return code 0x0
10355 11:38:44.588581
10356 11:38:44.591745 ec_init: CrosEC protocol v3 supported (256, 248)
10357 11:38:44.596702
10358 11:38:44.599961 tpm_cleanup: add release locality here.
10359 11:38:44.600135
10360 11:38:44.600261 Shutting down all USB controllers.
10361 11:38:44.603673
10362 11:38:44.603784 Removing current net device
10363 11:38:44.603844
10364 11:38:44.610552 Exiting depthcharge with code 4 at timestamp: 126329729
10365 11:38:44.610679
10366 11:38:44.613331 LZMA decompressing kernel-1 to 0x821a6718
10367 11:38:44.613429
10368 11:38:44.616979 LZMA decompressing kernel-1 to 0x40000000
10369 11:38:46.231553
10370 11:38:46.231677 jumping to kernel
10371 11:38:46.232205 end: 2.2.4 bootloader-commands (duration 00:01:39) [common]
10372 11:38:46.232297 start: 2.2.5 auto-login-action (timeout 00:02:41) [common]
10373 11:38:46.232366 Setting prompt string to ['Linux version [0-9]']
10374 11:38:46.232426 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10375 11:38:46.232486 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10376 11:38:46.312385
10377 11:38:46.315520 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10378 11:38:46.318967 start: 2.2.5.1 login-action (timeout 00:02:41) [common]
10379 11:38:46.319054 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10380 11:38:46.319120 Setting prompt string to []
10381 11:38:46.319192 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10382 11:38:46.319255 Using line separator: #'\n'#
10383 11:38:46.319307 No login prompt set.
10384 11:38:46.319362 Parsing kernel messages
10385 11:38:46.319412 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10386 11:38:46.319504 [login-action] Waiting for messages, (timeout 00:02:41)
10387 11:38:46.319564 Waiting using forced prompt support (timeout 00:01:21)
10388 11:38:46.338851 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10389 11:38:46.341893 [ 0.000000] random: crng init done
10390 11:38:46.345118 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10391 11:38:46.348661 [ 0.000000] efi: UEFI not found.
10392 11:38:46.358882 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10393 11:38:46.365369 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10394 11:38:46.375174 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10395 11:38:46.385035 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10396 11:38:46.391687 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10397 11:38:46.394797 [ 0.000000] printk: bootconsole [mtk8250] enabled
10398 11:38:46.403751 [ 0.000000] NUMA: No NUMA configuration found
10399 11:38:46.410539 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10400 11:38:46.417250 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10401 11:38:46.417326 [ 0.000000] Zone ranges:
10402 11:38:46.423253 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10403 11:38:46.426637 [ 0.000000] DMA32 empty
10404 11:38:46.433174 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10405 11:38:46.436444 [ 0.000000] Movable zone start for each node
10406 11:38:46.439685 [ 0.000000] Early memory node ranges
10407 11:38:46.446581 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10408 11:38:46.453393 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10409 11:38:46.459703 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10410 11:38:46.467008 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10411 11:38:46.472786 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10412 11:38:46.479757 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10413 11:38:46.537084 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10414 11:38:46.543510 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10415 11:38:46.550338 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10416 11:38:46.553568 [ 0.000000] psci: probing for conduit method from DT.
10417 11:38:46.560213 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10418 11:38:46.563305 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10419 11:38:46.569818 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10420 11:38:46.573091 [ 0.000000] psci: SMC Calling Convention v1.2
10421 11:38:46.580061 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10422 11:38:46.583524 [ 0.000000] Detected VIPT I-cache on CPU0
10423 11:38:46.589791 [ 0.000000] CPU features: detected: GIC system register CPU interface
10424 11:38:46.596606 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10425 11:38:46.603021 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10426 11:38:46.610101 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10427 11:38:46.619997 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10428 11:38:46.625862 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10429 11:38:46.629050 [ 0.000000] alternatives: applying boot alternatives
10430 11:38:46.635957 [ 0.000000] Fallback order for Node 0: 0
10431 11:38:46.642737 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10432 11:38:46.646023 [ 0.000000] Policy zone: Normal
10433 11:38:46.659225 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10434 11:38:46.668675 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10435 11:38:46.681046 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10436 11:38:46.691563 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10437 11:38:46.697721 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10438 11:38:46.700814 <6>[ 0.000000] software IO TLB: area num 8.
10439 11:38:46.758018 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10440 11:38:46.907560 <6>[ 0.000000] Memory: 7913148K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 439620K reserved, 32768K cma-reserved)
10441 11:38:46.914034 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10442 11:38:46.920438 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10443 11:38:46.923832 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10444 11:38:46.930781 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10445 11:38:46.936918 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10446 11:38:46.940348 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10447 11:38:46.950318 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10448 11:38:46.956929 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10449 11:38:46.963455 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10450 11:38:46.970010 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10451 11:38:46.973593 <6>[ 0.000000] GICv3: 608 SPIs implemented
10452 11:38:46.976585 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10453 11:38:46.983230 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10454 11:38:46.986881 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10455 11:38:46.993592 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10456 11:38:47.006519 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10457 11:38:47.016036 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10458 11:38:47.026103 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10459 11:38:47.033171 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10460 11:38:47.046785 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10461 11:38:47.053105 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10462 11:38:47.059683 <6>[ 0.009175] Console: colour dummy device 80x25
10463 11:38:47.069682 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10464 11:38:47.076504 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10465 11:38:47.080092 <6>[ 0.029224] LSM: Security Framework initializing
10466 11:38:47.086287 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10467 11:38:47.096391 <6>[ 0.042054] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10468 11:38:47.105927 <6>[ 0.051486] cblist_init_generic: Setting adjustable number of callback queues.
10469 11:38:47.109102 <6>[ 0.058928] cblist_init_generic: Setting shift to 3 and lim to 1.
10470 11:38:47.119515 <6>[ 0.065306] cblist_init_generic: Setting adjustable number of callback queues.
10471 11:38:47.125885 <6>[ 0.072733] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 11:38:47.129108 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10473 11:38:47.135762 <6>[ 0.084150] rcu: Max phase no-delay instances is 1000.
10474 11:38:47.142639 <6>[ 0.091169] EFI services will not be available.
10475 11:38:47.146327 <6>[ 0.096131] smp: Bringing up secondary CPUs ...
10476 11:38:47.154861 <6>[ 0.101184] Detected VIPT I-cache on CPU1
10477 11:38:47.160965 <6>[ 0.101255] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10478 11:38:47.167487 <6>[ 0.101288] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10479 11:38:47.170641 <6>[ 0.101631] Detected VIPT I-cache on CPU2
10480 11:38:47.180814 <6>[ 0.101686] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10481 11:38:47.187467 <6>[ 0.101704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10482 11:38:47.191005 <6>[ 0.101970] Detected VIPT I-cache on CPU3
10483 11:38:47.197611 <6>[ 0.102019] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10484 11:38:47.203864 <6>[ 0.102036] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10485 11:38:47.206993 <6>[ 0.102344] CPU features: detected: Spectre-v4
10486 11:38:47.213802 <6>[ 0.102351] CPU features: detected: Spectre-BHB
10487 11:38:47.217576 <6>[ 0.102356] Detected PIPT I-cache on CPU4
10488 11:38:47.223922 <6>[ 0.102418] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10489 11:38:47.230548 <6>[ 0.102436] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10490 11:38:47.236950 <6>[ 0.102733] Detected PIPT I-cache on CPU5
10491 11:38:47.244156 <6>[ 0.102798] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10492 11:38:47.250558 <6>[ 0.102814] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10493 11:38:47.253681 <6>[ 0.103098] Detected PIPT I-cache on CPU6
10494 11:38:47.260119 <6>[ 0.103165] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10495 11:38:47.267372 <6>[ 0.103181] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10496 11:38:47.273237 <6>[ 0.103483] Detected PIPT I-cache on CPU7
10497 11:38:47.280642 <6>[ 0.103550] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10498 11:38:47.286460 <6>[ 0.103566] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10499 11:38:47.290257 <6>[ 0.103615] smp: Brought up 1 node, 8 CPUs
10500 11:38:47.296548 <6>[ 0.245037] SMP: Total of 8 processors activated.
10501 11:38:47.300094 <6>[ 0.249988] CPU features: detected: 32-bit EL0 Support
10502 11:38:47.309875 <6>[ 0.255351] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10503 11:38:47.316245 <6>[ 0.264189] CPU features: detected: Common not Private translations
10504 11:38:47.323085 <6>[ 0.270665] CPU features: detected: CRC32 instructions
10505 11:38:47.329984 <6>[ 0.276050] CPU features: detected: RCpc load-acquire (LDAPR)
10506 11:38:47.333074 <6>[ 0.282047] CPU features: detected: LSE atomic instructions
10507 11:38:47.339664 <6>[ 0.287828] CPU features: detected: Privileged Access Never
10508 11:38:47.346408 <6>[ 0.293643] CPU features: detected: RAS Extension Support
10509 11:38:47.352552 <6>[ 0.299252] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10510 11:38:47.355888 <6>[ 0.306471] CPU: All CPU(s) started at EL2
10511 11:38:47.362529 <6>[ 0.310788] alternatives: applying system-wide alternatives
10512 11:38:47.372173 <6>[ 0.321667] devtmpfs: initialized
10513 11:38:47.387834 <6>[ 0.330531] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10514 11:38:47.394383 <6>[ 0.340496] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10515 11:38:47.400936 <6>[ 0.348411] pinctrl core: initialized pinctrl subsystem
10516 11:38:47.404165 <6>[ 0.355088] DMI not present or invalid.
10517 11:38:47.410934 <6>[ 0.359510] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10518 11:38:47.420614 <6>[ 0.366418] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10519 11:38:47.427201 <6>[ 0.374002] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10520 11:38:47.437560 <6>[ 0.382218] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10521 11:38:47.440849 <6>[ 0.390465] audit: initializing netlink subsys (disabled)
10522 11:38:47.450548 <5>[ 0.396162] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10523 11:38:47.457082 <6>[ 0.396891] thermal_sys: Registered thermal governor 'step_wise'
10524 11:38:47.463827 <6>[ 0.404127] thermal_sys: Registered thermal governor 'power_allocator'
10525 11:38:47.467155 <6>[ 0.410383] cpuidle: using governor menu
10526 11:38:47.473621 <6>[ 0.421345] NET: Registered PF_QIPCRTR protocol family
10527 11:38:47.480447 <6>[ 0.426874] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10528 11:38:47.486814 <6>[ 0.433978] ASID allocator initialised with 32768 entries
10529 11:38:47.489816 <6>[ 0.440569] Serial: AMBA PL011 UART driver
10530 11:38:47.500963 <4>[ 0.449941] Trying to register duplicate clock ID: 134
10531 11:38:47.559284 <6>[ 0.511379] KASLR enabled
10532 11:38:47.573676 <6>[ 0.519064] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10533 11:38:47.579561 <6>[ 0.526076] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10534 11:38:47.586144 <6>[ 0.532567] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10535 11:38:47.593265 <6>[ 0.539573] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10536 11:38:47.599843 <6>[ 0.546058] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10537 11:38:47.606041 <6>[ 0.553064] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10538 11:38:47.612636 <6>[ 0.559550] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10539 11:38:47.619329 <6>[ 0.566554] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10540 11:38:47.622416 <6>[ 0.574060] ACPI: Interpreter disabled.
10541 11:38:47.631445 <6>[ 0.580482] iommu: Default domain type: Translated
10542 11:38:47.637652 <6>[ 0.585594] iommu: DMA domain TLB invalidation policy: strict mode
10543 11:38:47.641930 <5>[ 0.592247] SCSI subsystem initialized
10544 11:38:47.647543 <6>[ 0.596413] usbcore: registered new interface driver usbfs
10545 11:38:47.654168 <6>[ 0.602143] usbcore: registered new interface driver hub
10546 11:38:47.657725 <6>[ 0.607693] usbcore: registered new device driver usb
10547 11:38:47.664965 <6>[ 0.613798] pps_core: LinuxPPS API ver. 1 registered
10548 11:38:47.674212 <6>[ 0.618989] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10549 11:38:47.677587 <6>[ 0.628335] PTP clock support registered
10550 11:38:47.680746 <6>[ 0.632577] EDAC MC: Ver: 3.0.0
10551 11:38:47.688304 <6>[ 0.637748] FPGA manager framework
10552 11:38:47.694647 <6>[ 0.641437] Advanced Linux Sound Architecture Driver Initialized.
10553 11:38:47.698106 <6>[ 0.648232] vgaarb: loaded
10554 11:38:47.704619 <6>[ 0.651398] clocksource: Switched to clocksource arch_sys_counter
10555 11:38:47.708081 <5>[ 0.657836] VFS: Disk quotas dquot_6.6.0
10556 11:38:47.714721 <6>[ 0.662023] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10557 11:38:47.717972 <6>[ 0.669212] pnp: PnP ACPI: disabled
10558 11:38:47.726587 <6>[ 0.675955] NET: Registered PF_INET protocol family
10559 11:38:47.736184 <6>[ 0.681543] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10560 11:38:47.747550 <6>[ 0.693843] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10561 11:38:47.757395 <6>[ 0.702659] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10562 11:38:47.764354 <6>[ 0.710628] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10563 11:38:47.774700 <6>[ 0.719327] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10564 11:38:47.780671 <6>[ 0.729086] TCP: Hash tables configured (established 65536 bind 65536)
10565 11:38:47.787471 <6>[ 0.735956] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 11:38:47.797961 <6>[ 0.743152] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10567 11:38:47.804287 <6>[ 0.750827] NET: Registered PF_UNIX/PF_LOCAL protocol family
10568 11:38:47.810233 <6>[ 0.756981] RPC: Registered named UNIX socket transport module.
10569 11:38:47.813720 <6>[ 0.763135] RPC: Registered udp transport module.
10570 11:38:47.820304 <6>[ 0.768068] RPC: Registered tcp transport module.
10571 11:38:47.827049 <6>[ 0.772998] RPC: Registered tcp NFSv4.1 backchannel transport module.
10572 11:38:47.829956 <6>[ 0.779663] PCI: CLS 0 bytes, default 64
10573 11:38:47.833094 <6>[ 0.783981] Unpacking initramfs...
10574 11:38:47.843163 <6>[ 0.788109] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10575 11:38:47.849719 <6>[ 0.796774] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10576 11:38:47.856400 <6>[ 0.805632] kvm [1]: IPA Size Limit: 40 bits
10577 11:38:47.859819 <6>[ 0.810160] kvm [1]: GICv3: no GICV resource entry
10578 11:38:47.866224 <6>[ 0.815179] kvm [1]: disabling GICv2 emulation
10579 11:38:47.872653 <6>[ 0.819864] kvm [1]: GIC system register CPU interface enabled
10580 11:38:47.876577 <6>[ 0.826040] kvm [1]: vgic interrupt IRQ18
10581 11:38:47.882683 <6>[ 0.831506] kvm [1]: VHE mode initialized successfully
10582 11:38:47.889089 <5>[ 0.837912] Initialise system trusted keyrings
10583 11:38:47.895610 <6>[ 0.842726] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10584 11:38:47.903290 <6>[ 0.852640] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10585 11:38:47.909861 <5>[ 0.859051] NFS: Registering the id_resolver key type
10586 11:38:47.913049 <5>[ 0.864376] Key type id_resolver registered
10587 11:38:47.919609 <5>[ 0.868791] Key type id_legacy registered
10588 11:38:47.926079 <6>[ 0.873067] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10589 11:38:47.933243 <6>[ 0.879987] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10590 11:38:47.939737 <6>[ 0.887712] 9p: Installing v9fs 9p2000 file system support
10591 11:38:47.975597 <5>[ 0.924981] Key type asymmetric registered
10592 11:38:47.979619 <5>[ 0.929312] Asymmetric key parser 'x509' registered
10593 11:38:47.988725 <6>[ 0.934448] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10594 11:38:47.992255 <6>[ 0.942061] io scheduler mq-deadline registered
10595 11:38:47.995503 <6>[ 0.946836] io scheduler kyber registered
10596 11:38:48.014309 <6>[ 0.963754] EINJ: ACPI disabled.
10597 11:38:48.047047 <4>[ 0.989617] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 11:38:48.057019 <4>[ 1.000243] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 11:38:48.071677 <6>[ 1.021179] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10600 11:38:48.079898 <6>[ 1.029178] printk: console [ttyS0] disabled
10601 11:38:48.107810 <6>[ 1.053807] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10602 11:38:48.114350 <6>[ 1.063277] printk: console [ttyS0] enabled
10603 11:38:48.117555 <6>[ 1.063277] printk: console [ttyS0] enabled
10604 11:38:48.124666 <6>[ 1.072172] printk: bootconsole [mtk8250] disabled
10605 11:38:48.127522 <6>[ 1.072172] printk: bootconsole [mtk8250] disabled
10606 11:38:48.134297 <6>[ 1.083200] SuperH (H)SCI(F) driver initialized
10607 11:38:48.137112 <6>[ 1.088481] msm_serial: driver initialized
10608 11:38:48.151674 <6>[ 1.097400] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10609 11:38:48.161317 <6>[ 1.105945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10610 11:38:48.168335 <6>[ 1.114486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10611 11:38:48.178100 <6>[ 1.123114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10612 11:38:48.187924 <6>[ 1.131821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10613 11:38:48.194129 <6>[ 1.140535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10614 11:38:48.204036 <6>[ 1.149081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10615 11:38:48.210603 <6>[ 1.157876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10616 11:38:48.220566 <6>[ 1.166419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10617 11:38:48.232485 <6>[ 1.181846] loop: module loaded
10618 11:38:48.238921 <6>[ 1.187636] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10619 11:38:48.261642 <4>[ 1.210863] mtk-pmic-keys: Failed to locate of_node [id: -1]
10620 11:38:48.268275 <6>[ 1.217651] megasas: 07.719.03.00-rc1
10621 11:38:48.278258 <6>[ 1.227301] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10622 11:38:48.285603 <6>[ 1.234798] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 11:38:48.301884 <6>[ 1.251357] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10624 11:38:48.358852 <6>[ 1.301176] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10625 11:38:50.072550 <6>[ 3.022165] Freeing initrd memory: 50904K
10626 11:38:50.084369 <6>[ 3.033917] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10627 11:38:50.095361 <6>[ 3.045043] tun: Universal TUN/TAP device driver, 1.6
10628 11:38:50.098678 <6>[ 3.051123] thunder_xcv, ver 1.0
10629 11:38:50.101960 <6>[ 3.054632] thunder_bgx, ver 1.0
10630 11:38:50.105325 <6>[ 3.058130] nicpf, ver 1.0
10631 11:38:50.115696 <6>[ 3.062152] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10632 11:38:50.119205 <6>[ 3.069628] hns3: Copyright (c) 2017 Huawei Corporation.
10633 11:38:50.125639 <6>[ 3.075222] hclge is initializing
10634 11:38:50.128916 <6>[ 3.078809] e1000: Intel(R) PRO/1000 Network Driver
10635 11:38:50.136030 <6>[ 3.083938] e1000: Copyright (c) 1999-2006 Intel Corporation.
10636 11:38:50.138743 <6>[ 3.089951] e1000e: Intel(R) PRO/1000 Network Driver
10637 11:38:50.145953 <6>[ 3.095166] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10638 11:38:50.152434 <6>[ 3.101353] igb: Intel(R) Gigabit Ethernet Network Driver
10639 11:38:50.159482 <6>[ 3.107002] igb: Copyright (c) 2007-2014 Intel Corporation.
10640 11:38:50.165237 <6>[ 3.112838] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10641 11:38:50.171869 <6>[ 3.119356] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10642 11:38:50.175652 <6>[ 3.125821] sky2: driver version 1.30
10643 11:38:50.181879 <6>[ 3.130746] usbcore: registered new device driver r8152-cfgselector
10644 11:38:50.188831 <6>[ 3.137285] usbcore: registered new interface driver r8152
10645 11:38:50.195118 <6>[ 3.143104] VFIO - User Level meta-driver version: 0.3
10646 11:38:50.201683 <6>[ 3.151333] usbcore: registered new interface driver usb-storage
10647 11:38:50.208321 <6>[ 3.157785] usbcore: registered new device driver onboard-usb-hub
10648 11:38:50.217424 <6>[ 3.166964] mt6397-rtc mt6359-rtc: registered as rtc0
10649 11:38:50.227001 <6>[ 3.172431] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:38:50 UTC (1721216330)
10650 11:38:50.231302 <6>[ 3.181996] i2c_dev: i2c /dev entries driver
10651 11:38:50.244541 <4>[ 3.194093] cpu cpu0: supply cpu not found, using dummy regulator
10652 11:38:50.251081 <4>[ 3.200513] cpu cpu1: supply cpu not found, using dummy regulator
10653 11:38:50.257817 <4>[ 3.206923] cpu cpu2: supply cpu not found, using dummy regulator
10654 11:38:50.264465 <4>[ 3.213323] cpu cpu3: supply cpu not found, using dummy regulator
10655 11:38:50.270828 <4>[ 3.219737] cpu cpu4: supply cpu not found, using dummy regulator
10656 11:38:50.277272 <4>[ 3.226134] cpu cpu5: supply cpu not found, using dummy regulator
10657 11:38:50.283894 <4>[ 3.232530] cpu cpu6: supply cpu not found, using dummy regulator
10658 11:38:50.290570 <4>[ 3.238930] cpu cpu7: supply cpu not found, using dummy regulator
10659 11:38:50.311624 <6>[ 3.260580] cpu cpu0: EM: created perf domain
10660 11:38:50.314169 <6>[ 3.265506] cpu cpu4: EM: created perf domain
10661 11:38:50.321488 <6>[ 3.271120] sdhci: Secure Digital Host Controller Interface driver
10662 11:38:50.328233 <6>[ 3.277552] sdhci: Copyright(c) Pierre Ossman
10663 11:38:50.334713 <6>[ 3.282507] Synopsys Designware Multimedia Card Interface Driver
10664 11:38:50.341427 <6>[ 3.289144] sdhci-pltfm: SDHCI platform and OF driver helper
10665 11:38:50.344644 <6>[ 3.289166] mmc0: CQHCI version 5.10
10666 11:38:50.351232 <6>[ 3.299169] ledtrig-cpu: registered to indicate activity on CPUs
10667 11:38:50.357622 <6>[ 3.306134] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10668 11:38:50.364409 <6>[ 3.313193] usbcore: registered new interface driver usbhid
10669 11:38:50.367630 <6>[ 3.319014] usbhid: USB HID core driver
10670 11:38:50.373995 <6>[ 3.323221] spi_master spi0: will run message pump with realtime priority
10671 11:38:50.419269 <6>[ 3.362055] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10672 11:38:50.437538 <6>[ 3.377009] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10673 11:38:50.441093 <6>[ 3.388453] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10674 11:38:50.448524 <6>[ 3.397828] cros-ec-spi spi0.0: Chrome EC device registered
10675 11:38:50.455142 <6>[ 3.403827] mmc0: Command Queue Engine enabled
10676 11:38:50.461252 <6>[ 3.408551] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10677 11:38:50.464441 <6>[ 3.415964] mmcblk0: mmc0:0001 DA4128 116 GiB
10678 11:38:50.474786 <6>[ 3.424593] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10679 11:38:50.482157 <6>[ 3.431941] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10680 11:38:50.493571 <6>[ 3.436292] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10681 11:38:50.495743 <6>[ 3.437816] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10682 11:38:50.502184 <6>[ 3.447634] NET: Registered PF_PACKET protocol family
10683 11:38:50.508879 <6>[ 3.452350] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10684 11:38:50.512138 <6>[ 3.457092] 9pnet: Installing 9P2000 support
10685 11:38:50.518551 <5>[ 3.468076] Key type dns_resolver registered
10686 11:38:50.521992 <6>[ 3.473033] registered taskstats version 1
10687 11:38:50.528800 <5>[ 3.477415] Loading compiled-in X.509 certificates
10688 11:38:50.556734 <4>[ 3.499311] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 11:38:50.566172 <4>[ 3.510037] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10690 11:38:50.580682 <6>[ 3.530514] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 11:38:50.588664 <6>[ 3.537702] xhci-mtk 11200000.usb: xHCI Host Controller
10692 11:38:50.594669 <6>[ 3.543207] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 11:38:50.604859 <6>[ 3.551068] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 11:38:50.611351 <6>[ 3.560507] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 11:38:50.618016 <6>[ 3.566622] xhci-mtk 11200000.usb: xHCI Host Controller
10696 11:38:50.624547 <6>[ 3.572228] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 11:38:50.630841 <6>[ 3.579905] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 11:38:50.638067 <6>[ 3.587803] hub 1-0:1.0: USB hub found
10699 11:38:50.641609 <6>[ 3.591833] hub 1-0:1.0: 1 port detected
10700 11:38:50.651276 <6>[ 3.596136] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 11:38:50.654545 <6>[ 3.604894] hub 2-0:1.0: USB hub found
10702 11:38:50.657899 <6>[ 3.608919] hub 2-0:1.0: 1 port detected
10703 11:38:50.666407 <6>[ 3.615946] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 11:38:50.680548 <6>[ 3.626623] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10705 11:38:50.690534 <6>[ 3.635011] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10706 11:38:50.696977 <6>[ 3.643355] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10707 11:38:50.706641 <6>[ 3.651699] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10708 11:38:50.713377 <6>[ 3.660041] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10709 11:38:50.723336 <6>[ 3.668381] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10710 11:38:50.729906 <6>[ 3.676720] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10711 11:38:50.739498 <6>[ 3.685059] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10712 11:38:50.746585 <6>[ 3.693398] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10713 11:38:50.756006 <6>[ 3.701737] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10714 11:38:50.763214 <6>[ 3.710075] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10715 11:38:50.772728 <6>[ 3.718419] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10716 11:38:50.779699 <6>[ 3.726758] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10717 11:38:50.789499 <6>[ 3.735096] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10718 11:38:50.796014 <6>[ 3.743442] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10719 11:38:50.802440 <6>[ 3.752144] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10720 11:38:50.809576 <6>[ 3.759273] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10721 11:38:50.816799 <6>[ 3.766032] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10722 11:38:50.826826 <6>[ 3.772831] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10723 11:38:50.833116 <6>[ 3.779761] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10724 11:38:50.840994 <6>[ 3.786638] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10725 11:38:50.849720 <6>[ 3.795775] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10726 11:38:50.859726 <6>[ 3.804900] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10727 11:38:50.869485 <6>[ 3.814194] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10728 11:38:50.879422 <6>[ 3.823662] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10729 11:38:50.886144 <6>[ 3.833129] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10730 11:38:50.895970 <6>[ 3.842250] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10731 11:38:50.906147 <6>[ 3.851717] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10732 11:38:50.915524 <6>[ 3.860838] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10733 11:38:50.925699 <6>[ 3.870136] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10734 11:38:50.935399 <6>[ 3.880297] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10735 11:38:50.945424 <6>[ 3.892005] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10736 11:38:51.073161 <6>[ 4.019701] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10737 11:38:51.227654 <6>[ 4.177573] hub 1-1:1.0: USB hub found
10738 11:38:51.231077 <6>[ 4.182112] hub 1-1:1.0: 4 ports detected
10739 11:38:51.243374 <6>[ 4.193141] hub 1-1:1.0: USB hub found
10740 11:38:51.246759 <6>[ 4.197581] hub 1-1:1.0: 4 ports detected
10741 11:38:51.353706 <6>[ 4.300009] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 11:38:51.379648 <6>[ 4.329518] hub 2-1:1.0: USB hub found
10743 11:38:51.382877 <6>[ 4.334019] hub 2-1:1.0: 3 ports detected
10744 11:38:51.395556 <6>[ 4.345133] hub 2-1:1.0: USB hub found
10745 11:38:51.398882 <6>[ 4.349574] hub 2-1:1.0: 3 ports detected
10746 11:38:51.569098 <6>[ 4.515719] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10747 11:38:51.702411 <6>[ 4.651607] hub 1-1.4:1.0: USB hub found
10748 11:38:51.705370 <6>[ 4.656315] hub 1-1.4:1.0: 2 ports detected
10749 11:38:51.717976 <6>[ 4.667791] hub 1-1.4:1.0: USB hub found
10750 11:38:51.721723 <6>[ 4.672367] hub 1-1.4:1.0: 2 ports detected
10751 11:38:51.781450 <6>[ 4.727931] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 11:38:51.889598 <6>[ 4.836369] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10753 11:38:51.926104 <4>[ 4.872545] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10754 11:38:51.936024 <4>[ 4.881635] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10755 11:38:51.975784 <6>[ 4.925135] r8152 2-1.3:1.0 eth0: v1.12.13
10756 11:38:52.016776 <6>[ 4.963538] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10757 11:38:52.208951 <6>[ 5.155566] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10758 11:38:53.679652 <6>[ 6.629798] r8152 2-1.3:1.0 eth0: carrier on
10759 11:38:56.789617 <5>[ 6.659780] Sending DHCP requests .., OK
10760 11:38:56.795792 <6>[ 9.743863] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10761 11:38:56.799607 <6>[ 9.752163] IP-Config: Complete:
10762 11:38:56.812343 <6>[ 9.755659] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10763 11:38:56.818918 <6>[ 9.766395] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10764 11:38:56.825703 <6>[ 9.775015] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10765 11:38:56.832070 <6>[ 9.775024] nameserver0=192.168.201.1
10766 11:38:56.835256 <6>[ 9.787175] clk: Disabling unused clocks
10767 11:38:56.838812 <6>[ 9.792744] ALSA device list:
10768 11:38:56.845432 <6>[ 9.796017] No soundcards found.
10769 11:38:56.853563 <6>[ 9.803921] Freeing unused kernel memory: 8512K
10770 11:38:56.856722 <6>[ 9.808809] Run /init as init process
10771 11:38:56.887508 <6>[ 9.837612] NET: Registered PF_INET6 protocol family
10772 11:38:56.894007 <6>[ 9.844096] Segment Routing with IPv6
10773 11:38:56.896868 <6>[ 9.848038] In-situ OAM (IOAM) with IPv6
10774 11:38:56.937969 <30>[ 9.861839] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10775 11:38:56.944719 <30>[ 9.894900] systemd[1]: Detected architecture arm64.
10776 11:38:56.944849
10777 11:38:56.951271 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10778 11:38:56.951364
10779 11:38:56.965497 <30>[ 9.915728] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10780 11:38:57.106089 <30>[ 10.053134] systemd[1]: Queued start job for default target graphical.target.
10781 11:38:57.157948 <30>[ 10.105162] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10782 11:38:57.164828 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10783 11:38:57.184943 <30>[ 10.132156] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10784 11:38:57.195028 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10785 11:38:57.217741 <30>[ 10.164740] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10786 11:38:57.227868 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10787 11:38:57.246635 <30>[ 10.193282] systemd[1]: Created slice user.slice - User and Session Slice.
10788 11:38:57.252866 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10789 11:38:57.276259 <30>[ 10.219957] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10790 11:38:57.286033 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10791 11:38:57.304237 <30>[ 10.247911] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10792 11:38:57.310949 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10793 11:38:57.338917 <30>[ 10.276275] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10794 11:38:57.349032 <30>[ 10.296198] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10795 11:38:57.355847 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10796 11:38:57.372443 <30>[ 10.319707] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10797 11:38:57.379250 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10798 11:38:57.396714 <30>[ 10.343763] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10799 11:38:57.407099 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10800 11:38:57.421334 <30>[ 10.371809] systemd[1]: Reached target paths.target - Path Units.
10801 11:38:57.431701 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10802 11:38:57.448965 <30>[ 10.396137] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10803 11:38:57.455213 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10804 11:38:57.469185 <30>[ 10.419684] systemd[1]: Reached target slices.target - Slice Units.
10805 11:38:57.479416 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10806 11:38:57.493514 <30>[ 10.444186] systemd[1]: Reached target swap.target - Swaps.
10807 11:38:57.500256 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10808 11:38:57.521443 <30>[ 10.468211] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10809 11:38:57.530863 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10810 11:38:57.549460 <30>[ 10.496640] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10811 11:38:57.559800 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10812 11:38:57.578371 <30>[ 10.525600] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10813 11:38:57.588372 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10814 11:38:57.605089 <30>[ 10.552326] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10815 11:38:57.614973 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10816 11:38:57.633192 <30>[ 10.580318] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10817 11:38:57.639479 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10818 11:38:57.657127 <30>[ 10.604371] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10819 11:38:57.667380 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10820 11:38:57.685865 <30>[ 10.633028] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10821 11:38:57.696359 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10822 11:38:57.713778 <30>[ 10.660844] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10823 11:38:57.723648 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10824 11:38:57.772761 <30>[ 10.720011] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10825 11:38:57.779428 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10826 11:38:57.799798 <30>[ 10.746725] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10827 11:38:57.806287 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10828 11:38:57.826533 <30>[ 10.773702] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10829 11:38:57.832900 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10830 11:38:57.859243 <30>[ 10.799939] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10831 11:38:57.872519 <30>[ 10.818935] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10832 11:38:57.881557 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10833 11:38:57.905436 <30>[ 10.852265] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10834 11:38:57.912008 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10835 11:38:57.937712 <30>[ 10.885080] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10836 11:38:57.948078 Startin<6>[ 10.894462] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10837 11:38:57.954480 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10838 11:38:58.005362 <30>[ 10.952405] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10839 11:38:58.011726 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10840 11:38:58.038056 <30>[ 10.985013] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10841 11:38:58.047401 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10842 11:38:58.069907 <30>[ 11.017085] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10843 11:38:58.076411 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10844 11:38:58.105093 <30>[ 11.052530] systemd[1]: Starting systemd-journald.service - Journal Service...
10845 11:38:58.112382 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10846 11:38:58.131406 <30>[ 11.078512] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10847 11:38:58.137804 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10848 11:38:58.197090 <30>[ 11.140404] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10849 11:38:58.203360 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10850 11:38:58.225579 <30>[ 11.172597] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10851 11:38:58.235670 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10852 11:38:58.255755 <30>[ 11.202989] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10853 11:38:58.263107 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10854 11:38:58.285852 <30>[ 11.232751] systemd[1]: Started systemd-journald.service - Journal Service.
10855 11:38:58.292190 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10856 11:38:58.315059 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10857 11:38:58.337316 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10858 11:38:58.361201 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10859 11:38:58.382525 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10860 11:38:58.403829 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10861 11:38:58.427987 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10862 11:38:58.449096 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10863 11:38:58.472059 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10864 11:38:58.499666 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10865 11:38:58.519065 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10866 11:38:58.538397 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10867 11:38:58.559119 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10868 11:38:58.573194 See 'systemctl status systemd-remount-fs.service' for details.
10869 11:38:58.594351 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10870 11:38:58.615219 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10871 11:38:58.660991 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10872 11:38:58.680992 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10873 11:38:58.703135 <46>[ 11.649707] systemd-journald[192]: Received client request to flush runtime journal.
10874 11:38:58.708917 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10875 11:38:58.731385 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10876 11:38:58.752527 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10877 11:38:58.774994 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10878 11:38:58.794390 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10879 11:38:58.814116 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10880 11:38:58.834172 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10881 11:38:58.853608 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10882 11:38:58.896882 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10883 11:38:58.920088 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10884 11:38:58.937177 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10885 11:38:58.952470 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10886 11:38:59.001450 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10887 11:38:59.025169 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10888 11:38:59.048800 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10889 11:38:59.091709 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10890 11:38:59.121778 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10891 11:38:59.144037 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10892 11:38:59.182948 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10893 11:38:59.205469 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10894 11:38:59.227546 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10895 11:38:59.361213 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10896 11:38:59.385709 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10897 11:38:59.410845 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10898 11:38:59.434038 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10899 11:38:59.462090 [[0;32m OK [0m] Reached targ<6>[ 12.407600] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10900 11:38:59.465458 et [0;1;39mtimers.target[0m - Timer Units.
10901 11:38:59.472064 <6>[ 12.419507] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10902 11:38:59.481706 <6>[ 12.428157] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10903 11:38:59.488587 <6>[ 12.436963] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10904 11:38:59.494860 <6>[ 12.445133] remoteproc remoteproc0: scp is available
10905 11:38:59.505002 <3>[ 12.448357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 11:38:59.508156 <6>[ 12.453116] remoteproc remoteproc0: powering up scp
10907 11:38:59.518023 <3>[ 12.462751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 11:38:59.524856 <6>[ 12.464136] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10909 11:38:59.534733 <6>[ 12.465110] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10910 11:38:59.541541 <6>[ 12.468828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10911 11:38:59.547753 <6>[ 12.468834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10912 11:38:59.557606 <4>[ 12.468935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10913 11:38:59.564886 <6>[ 12.469430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10914 11:38:59.574731 <6>[ 12.469432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10915 11:38:59.581212 <6>[ 12.469642] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10916 11:38:59.591567 <6>[ 12.469668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10917 11:38:59.597687 <6>[ 12.469687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10918 11:38:59.604646 <6>[ 12.469692] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10919 11:38:59.614085 <6>[ 12.469698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10920 11:38:59.625382 <3>[ 12.472225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 11:38:59.628491 <6>[ 12.482086] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10922 11:38:59.638403 <4>[ 12.493223] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 11:38:59.641388 <4>[ 12.493223] Fallback method does not support PEC.
10924 11:38:59.651787 <3>[ 12.503850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 11:38:59.655302 <6>[ 12.515851] mc: Linux media interface: v0.10
10926 11:38:59.664679 <3>[ 12.522009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 11:38:59.671782 <3>[ 12.522099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 11:38:59.678444 <4>[ 12.560113] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10929 11:38:59.688303 <3>[ 12.561576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 11:38:59.694441 <4>[ 12.574142] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10931 11:38:59.697914 <6>[ 12.574657] Bluetooth: Core ver 2.22
10932 11:38:59.704597 <6>[ 12.575153] NET: Registered PF_BLUETOOTH protocol family
10933 11:38:59.710932 <6>[ 12.575161] Bluetooth: HCI device and connection manager initialized
10934 11:38:59.714338 <6>[ 12.575182] Bluetooth: HCI socket layer initialized
10935 11:38:59.721093 <6>[ 12.575186] Bluetooth: L2CAP socket layer initialized
10936 11:38:59.727751 <6>[ 12.575220] Bluetooth: SCO socket layer initialized
10937 11:38:59.731037 <6>[ 12.578264] videodev: Linux video capture interface: v2.00
10938 11:38:59.741250 <3>[ 12.578806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10939 11:38:59.747196 <3>[ 12.578811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10940 11:38:59.757569 <3>[ 12.581715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:38:59.764015 <3>[ 12.591344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10942 11:38:59.773698 <6>[ 12.600204] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10943 11:38:59.780794 <3>[ 12.616337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 11:38:59.787636 <6>[ 12.619739] pci_bus 0000:00: root bus resource [bus 00-ff]
10945 11:38:59.793860 <3>[ 12.627747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 11:38:59.803773 <3>[ 12.627751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 11:38:59.810340 <3>[ 12.627814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 11:38:59.817099 <6>[ 12.635143] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10949 11:38:59.826955 <6>[ 12.643167] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10950 11:38:59.833673 <6>[ 12.643177] remoteproc remoteproc0: remote processor scp is now up
10951 11:38:59.840646 <3>[ 12.643195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 11:38:59.847331 <6>[ 12.650797] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10953 11:38:59.857238 <3>[ 12.654471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10954 11:38:59.867084 <6>[ 12.660000] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10955 11:38:59.875064 <3>[ 12.666564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10956 11:38:59.880715 <3>[ 12.666571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 11:38:59.890936 <3>[ 12.666606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 11:38:59.897886 <6>[ 12.671765] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10959 11:38:59.904429 <6>[ 12.758328] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10960 11:38:59.913988 <6>[ 12.766190] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10961 11:38:59.920585 <6>[ 12.767701] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10962 11:38:59.931032 <6>[ 12.768336] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10963 11:38:59.940413 <6>[ 12.769109] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10964 11:38:59.946987 <6>[ 12.771705] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10965 11:38:59.957110 <3>[ 12.793741] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:38:59.960163 <6>[ 12.797282] pci 0000:00:00.0: supports D1 D2
10967 11:38:59.967121 <6>[ 12.838887] usbcore: registered new interface driver btusb
10968 11:38:59.973577 <6>[ 12.838955] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10969 11:38:59.983291 <4>[ 12.839480] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10970 11:38:59.990361 <3>[ 12.839488] Bluetooth: hci0: Failed to load firmware file (-2)
10971 11:38:59.997072 <3>[ 12.839491] Bluetooth: hci0: Failed to set up firmware (-2)
10972 11:39:00.006800 <4>[ 12.839495] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10973 11:39:00.019655 <6>[ 12.840343] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10974 11:39:00.026294 <6>[ 12.840431] usbcore: registered new interface driver uvcvideo
10975 11:39:00.033124 <3>[ 12.840865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 11:39:00.043243 <6>[ 12.845550] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10977 11:39:00.049489 <6>[ 12.847189] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10978 11:39:00.056252 <6>[ 12.861782] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10979 11:39:00.062732 <6>[ 12.868734] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10980 11:39:00.069120 <6>[ 13.018179] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10981 11:39:00.079274 <6>[ 13.018197] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10982 11:39:00.085575 <6>[ 13.018212] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10983 11:39:00.089131 <6>[ 13.018319] pci 0000:01:00.0: supports D1 D2
10984 11:39:00.095407 <6>[ 13.045191] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10985 11:39:00.106180 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10986 11:39:00.112522 <6>[ 13.061485] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10987 11:39:00.121888 <6>[ 13.068386] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10988 11:39:00.128849 <6>[ 13.076473] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10989 11:39:00.135413 <6>[ 13.084473] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10990 11:39:00.145089 <6>[ 13.084486] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10991 11:39:00.151574 <6>[ 13.084499] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10992 11:39:00.158116 <6>[ 13.084511] pci 0000:00:00.0: PCI bridge to [bus 01]
10993 11:39:00.164913 <6>[ 13.084517] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10994 11:39:00.171461 <6>[ 13.084678] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10995 11:39:00.181692 [[0;32m OK [<6>[ 13.128628] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10996 11:39:00.188115 0m] Reached targ<6>[ 13.135885] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10997 11:39:00.191497 et [0;1;39msockets.target[0m - Socket Units.
10998 11:39:00.206076 <5>[ 13.153606] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10999 11:39:00.220956 <3>[ 13.168286] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:39:00.227685 <5>[ 13.176021] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11001 11:39:00.238155 <5>[ 13.184428] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11002 11:39:00.244958 <4>[ 13.192897] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11003 11:39:00.254874 <3>[ 13.198468] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 11:39:00.258633 <6>[ 13.201820] cfg80211: failed to load regulatory.db
11005 11:39:00.268667 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11006 11:39:00.296853 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<3>[ 13.241844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 11:39:00.296983 asic System.
11008 11:39:00.303255 <6>[ 13.250981] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11009 11:39:00.309484 <6>[ 13.260043] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11010 11:39:00.316374 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11011 11:39:00.327375 <3>[ 13.274756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 11:39:00.336817 <6>[ 13.287511] mt7921e 0000:01:00.0: ASIC revision: 79610010
11013 11:39:00.349301 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11014 11:39:00.368327 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11015 11:39:00.401555 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11016 11:39:00.441502 <6>[ 13.388780] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11017 11:39:00.444401 <6>[ 13.388780]
11018 11:39:00.455320 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11019 11:39:00.472963 <3>[ 13.420185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 11:39:00.486186 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11021 11:39:00.504939 <3>[ 13.452015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 11:39:00.514114 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11023 11:39:00.530057 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11024 11:39:00.550350 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11025 11:39:00.588153 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11026 11:39:00.612096 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11027 11:39:00.638788 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11028 11:39:00.664635 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11029 11:39:00.713405 <6>[ 13.660759] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11030 11:39:00.730713 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11031 11:39:00.779783 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11032 11:39:00.799833 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11033 11:39:00.816249 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11034 11:39:00.832261 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11035 11:39:00.878780 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11036 11:39:00.903409 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11037 11:39:00.924644 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11038 11:39:00.963815 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11039 11:39:01.007078
11040 11:39:01.010929 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11041 11:39:01.011021
11042 11:39:01.013338 debian-bookworm-arm64 login: root (automatic login)
11043 11:39:01.013416
11044 11:39:01.032749 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11045 11:39:01.032876
11046 11:39:01.039923 The programs included with the Debian GNU/Linux system are free software;
11047 11:39:01.045832 the exact distribution terms for each program are described in the
11048 11:39:01.049296 individual files in /usr/share/doc/*/copyright.
11049 11:39:01.049391
11050 11:39:01.055796 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11051 11:39:01.059224 permitted by applicable law.
11052 11:39:01.059607 Matched prompt #10: / #
11054 11:39:01.059800 Setting prompt string to ['/ #']
11055 11:39:01.059889 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11057 11:39:01.060063 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11058 11:39:01.060142 start: 2.2.6 expect-shell-connection (timeout 00:02:26) [common]
11059 11:39:01.060205 Setting prompt string to ['/ #']
11060 11:39:01.060259 Forcing a shell prompt, looking for ['/ #']
11061 11:39:01.060312 Sending line: ''
11063 11:39:01.110693 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11064 11:39:01.110823 Waiting using forced prompt support (timeout 00:02:30)
11065 11:39:01.115530 / #
11066 11:39:01.115832 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11067 11:39:01.115946 start: 2.2.7 export-device-env (timeout 00:02:26) [common]
11068 11:39:01.116059 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11069 11:39:01.116167 end: 2.2 depthcharge-retry (duration 00:02:34) [common]
11070 11:39:01.116274 end: 2 depthcharge-action (duration 00:02:34) [common]
11071 11:39:01.116391 start: 3 lava-test-retry (timeout 00:05:00) [common]
11072 11:39:01.116509 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11073 11:39:01.116607 Using namespace: common
11074 11:39:01.116702 Sending line: '#'
11076 11:39:01.217259 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11077 11:39:01.222338 / # #
11078 11:39:01.222606 Using /lava-14864646
11079 11:39:01.222668 Sending line: 'export SHELL=/bin/sh'
11081 11:39:01.328041 / # export SHELL=/bin/sh
11082 11:39:01.328309 Sending line: '. /lava-14864646/environment'
11084 11:39:01.433632 / # . /lava-14864646/environment
11085 11:39:01.433920 Sending line: '/lava-14864646/bin/lava-test-runner /lava-14864646/0'
11087 11:39:01.534380 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 11:39:01.539165 / # /lava-14864646/bin/lava-test-runner /lava-14864646/0
11089 11:39:01.564288 + export TESTRUN_ID=0_cros-ec
11090 11:39:01.570329 + c<8>[ 14.520275] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14864646_1.5.2.3.1>
11091 11:39:01.570620 Received signal: <STARTRUN> 0_cros-ec 14864646_1.5.2.3.1
11092 11:39:01.570689 Starting test lava.0_cros-ec (14864646_1.5.2.3.1)
11093 11:39:01.570761 Skipping test definition patterns.
11094 11:39:01.573846 d /lava-14864646/0/tests/0_cros-ec
11095 11:39:01.577130 + cat uuid
11096 11:39:01.577270 + UUID=14864646_1.5.2.3.1
11097 11:39:01.577361 + set +x
11098 11:39:01.586761 + python3 -<6>[ 14.534755] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11099 11:39:01.586873 m cros.runners.lava_runner -v
11100 11:39:02.051723 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11101 11:39:02.058539 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11102 11:39:02.058674
11103 11:39:02.065091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11104 11:39:02.065408 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11106 11:39:02.075102 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11107 11:39:02.084770 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11108 11:39:02.084882
11109 11:39:02.091897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11110 11:39:02.092162 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11112 11:39:02.101906 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11113 11:39:02.108374 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11114 11:39:02.108475
11115 11:39:02.114411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11116 11:39:02.114671 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11118 11:39:02.121095 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11119 11:39:02.124839 Checks the standard ABI for the main Embedded Controller. ... ok
11120 11:39:02.127582
11121 11:39:02.130939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11122 11:39:02.131193 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11124 11:39:02.138021 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11125 11:39:02.144471 Checks the main Embedded controller character device. ... ok
11126 11:39:02.144566
11127 11:39:02.150918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11128 11:39:02.151182 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11130 11:39:02.157839 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11131 11:39:02.164234 Checks basic comunication with the main Embedded controller. ... ok
11132 11:39:02.164343
11133 11:39:02.170522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11134 11:39:02.170789 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11136 11:39:02.177244 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11137 11:39:02.184057 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11138 11:39:02.184154
11139 11:39:02.190576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11140 11:39:02.190843 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11142 11:39:02.197067 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11143 11:39:02.203690 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11144 11:39:02.203784
11145 11:39:02.210349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11146 11:39:02.210614 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11148 11:39:02.216848 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11149 11:39:02.223963 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11150 11:39:02.224064
11151 11:39:02.230369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11152 11:39:02.230671 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11154 11:39:02.236693 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11155 11:39:02.247357 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11156 11:39:02.247467
11157 11:39:02.249706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11158 11:39:02.249952 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11160 11:39:02.256600 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11161 11:39:02.266286 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11162 11:39:02.266396
11163 11:39:02.272945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11164 11:39:02.273225 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11166 11:39:02.279437 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11167 11:39:02.286263 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11168 11:39:02.286363
11169 11:39:02.293104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11170 11:39:02.293378 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11172 11:39:02.299287 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11173 11:39:02.305911 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11174 11:39:02.306037
11175 11:39:02.312873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11176 11:39:02.313144 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11178 11:39:02.322871 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11179 11:39:02.329420 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11180 11:39:02.329543
11181 11:39:02.336222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11182 11:39:02.336492 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11184 11:39:02.345642 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11185 11:39:02.348846 Check the cros battery ABI. ... skipped 'No BAT found'
11186 11:39:02.348933
11187 11:39:02.355387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11188 11:39:02.355651 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11190 11:39:02.365389 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11191 11:39:02.371874 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11192 11:39:02.371976
11193 11:39:02.378617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11194 11:39:02.378882 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11196 11:39:02.384972 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11197 11:39:02.395004 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11198 11:39:02.395115
11199 11:39:02.398153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11200 11:39:02.398402 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11202 11:39:02.408282 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11203 11:39:02.415211 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11204 11:39:02.415313
11205 11:39:02.422000 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8
11206 11:39:02.422113 Bad test result: ski<8
11207 11:39:02.428371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=ski<8>[ 15.377082] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14864646_1.5.2.3.1>
11208 11:39:02.428468 p>
11209 11:39:02.428527
11210 11:39:02.428749 Received signal: <ENDRUN> 0_cros-ec 14864646_1.5.2.3.1
11211 11:39:02.428820 Ending use of test pattern.
11212 11:39:02.428873 Ending test lava.0_cros-ec (14864646_1.5.2.3.1), duration 0.86
11214 11:39:02.434865 ----------------------------------------------------------------------
11215 11:39:02.438627 Ran 18 tests in 0.329s
11216 11:39:02.438709
11217 11:39:02.438766 OK (skipped=15)
11218 11:39:02.438820 + set +x
11219 11:39:02.441358 <LAVA_TEST_RUNNER EXIT>
11220 11:39:02.441604 ok: lava_test_shell seems to have completed
11221 11:39:02.441766 test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_abi: pass
test_cros_ec_chardev: pass
test_cros_ec_hello: pass
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
test_cros_ec_pwm_backlight: skip
test_cros_ec_battery_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_ec_rtc_abi: skip
11222 11:39:02.441859 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11223 11:39:02.441936 end: 3 lava-test-retry (duration 00:00:01) [common]
11224 11:39:02.442012 start: 4 finalize (timeout 00:07:01) [common]
11225 11:39:02.442094 start: 4.1 power-off (timeout 00:00:30) [common]
11226 11:39:02.442218 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11227 11:39:04.506589 >> Command sent successfully.
11228 11:39:04.511063 Returned 0 in 2 seconds
11229 11:39:04.511253 end: 4.1 power-off (duration 00:00:02) [common]
11231 11:39:04.511460 start: 4.2 read-feedback (timeout 00:06:59) [common]
11232 11:39:04.511594 Listened to connection for namespace 'common' for up to 1s
11233 11:39:05.511671 Finalising connection for namespace 'common'
11234 11:39:05.511827 Disconnecting from shell: Finalise
11235 11:39:05.511896 / #
11236 11:39:05.612117 end: 4.2 read-feedback (duration 00:00:01) [common]
11237 11:39:05.612295 end: 4 finalize (duration 00:00:03) [common]
11238 11:39:05.612426 Cleaning after the job
11239 11:39:05.612551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/ramdisk
11240 11:39:05.618570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/kernel
11241 11:39:05.633915 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/dtb
11242 11:39:05.634177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864646/tftp-deploy-5majoj1q/modules
11243 11:39:05.640048 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864646
11244 11:39:05.743990 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864646
11245 11:39:05.744195 Job finished correctly