Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 11:37:44.705789 lava-dispatcher, installed at version: 2024.05
2 11:37:44.705983 start: 0 validate
3 11:37:44.706102 Start time: 2024-07-17 11:37:44.706096+00:00 (UTC)
4 11:37:44.706232 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:37:44.706379 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 11:37:44.973093 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:37:44.973862 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:37:45.237905 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:37:45.238834 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:37:45.501885 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:37:45.502726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
12 11:37:45.770425 validate duration: 1.06
14 11:37:45.771630 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:37:45.772139 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:37:45.772599 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:37:45.773386 Not decompressing ramdisk as can be used compressed.
18 11:37:45.773857 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 11:37:45.774213 saving as /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/ramdisk/rootfs.cpio.gz
20 11:37:45.774541 total size: 47897469 (45 MB)
21 11:37:45.779240 progress 0 % (0 MB)
22 11:37:45.819807 progress 5 % (2 MB)
23 11:37:45.835656 progress 10 % (4 MB)
24 11:37:45.847665 progress 15 % (6 MB)
25 11:37:45.859248 progress 20 % (9 MB)
26 11:37:45.870621 progress 25 % (11 MB)
27 11:37:45.882035 progress 30 % (13 MB)
28 11:37:45.893295 progress 35 % (16 MB)
29 11:37:45.904927 progress 40 % (18 MB)
30 11:37:45.916964 progress 45 % (20 MB)
31 11:37:45.929208 progress 50 % (22 MB)
32 11:37:45.940862 progress 55 % (25 MB)
33 11:37:45.953010 progress 60 % (27 MB)
34 11:37:45.964826 progress 65 % (29 MB)
35 11:37:45.977097 progress 70 % (32 MB)
36 11:37:45.989107 progress 75 % (34 MB)
37 11:37:46.001108 progress 80 % (36 MB)
38 11:37:46.013009 progress 85 % (38 MB)
39 11:37:46.025183 progress 90 % (41 MB)
40 11:37:46.036863 progress 95 % (43 MB)
41 11:37:46.048540 progress 100 % (45 MB)
42 11:37:46.048745 45 MB downloaded in 0.27 s (166.58 MB/s)
43 11:37:46.048903 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:37:46.049121 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:37:46.049200 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:37:46.049316 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:37:46.049447 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
49 11:37:46.049508 saving as /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/kernel/Image
50 11:37:46.049561 total size: 54813184 (52 MB)
51 11:37:46.049614 No compression specified
52 11:37:46.050746 progress 0 % (0 MB)
53 11:37:46.064174 progress 5 % (2 MB)
54 11:37:46.077774 progress 10 % (5 MB)
55 11:37:46.091462 progress 15 % (7 MB)
56 11:37:46.105731 progress 20 % (10 MB)
57 11:37:46.119430 progress 25 % (13 MB)
58 11:37:46.133099 progress 30 % (15 MB)
59 11:37:46.147033 progress 35 % (18 MB)
60 11:37:46.160629 progress 40 % (20 MB)
61 11:37:46.174200 progress 45 % (23 MB)
62 11:37:46.187691 progress 50 % (26 MB)
63 11:37:46.201023 progress 55 % (28 MB)
64 11:37:46.214261 progress 60 % (31 MB)
65 11:37:46.227617 progress 65 % (34 MB)
66 11:37:46.240771 progress 70 % (36 MB)
67 11:37:46.253884 progress 75 % (39 MB)
68 11:37:46.267217 progress 80 % (41 MB)
69 11:37:46.280180 progress 85 % (44 MB)
70 11:37:46.293274 progress 90 % (47 MB)
71 11:37:46.306577 progress 95 % (49 MB)
72 11:37:46.319469 progress 100 % (52 MB)
73 11:37:46.319673 52 MB downloaded in 0.27 s (193.53 MB/s)
74 11:37:46.319821 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:37:46.320027 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:37:46.320107 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:37:46.320183 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:37:46.320313 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:37:46.320378 saving as /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/dtb/mt8192-asurada-spherion-r0.dtb
81 11:37:46.320430 total size: 47258 (0 MB)
82 11:37:46.320482 No compression specified
83 11:37:46.321536 progress 69 % (0 MB)
84 11:37:46.321790 progress 100 % (0 MB)
85 11:37:46.321933 0 MB downloaded in 0.00 s (30.02 MB/s)
86 11:37:46.322045 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:37:46.322241 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:37:46.322316 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:37:46.322388 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:37:46.322492 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
92 11:37:46.322552 saving as /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/modules/modules.tar
93 11:37:46.322604 total size: 8610184 (8 MB)
94 11:37:46.322657 Using unxz to decompress xz
95 11:37:46.323976 progress 0 % (0 MB)
96 11:37:46.343800 progress 5 % (0 MB)
97 11:37:46.367440 progress 10 % (0 MB)
98 11:37:46.390066 progress 15 % (1 MB)
99 11:37:46.413161 progress 20 % (1 MB)
100 11:37:46.435326 progress 25 % (2 MB)
101 11:37:46.457744 progress 30 % (2 MB)
102 11:37:46.478982 progress 35 % (2 MB)
103 11:37:46.503694 progress 40 % (3 MB)
104 11:37:46.526832 progress 45 % (3 MB)
105 11:37:46.549547 progress 50 % (4 MB)
106 11:37:46.572824 progress 55 % (4 MB)
107 11:37:46.595734 progress 60 % (4 MB)
108 11:37:46.618047 progress 65 % (5 MB)
109 11:37:46.642109 progress 70 % (5 MB)
110 11:37:46.667290 progress 75 % (6 MB)
111 11:37:46.693466 progress 80 % (6 MB)
112 11:37:46.716423 progress 85 % (7 MB)
113 11:37:46.738502 progress 90 % (7 MB)
114 11:37:46.760502 progress 95 % (7 MB)
115 11:37:46.781818 progress 100 % (8 MB)
116 11:37:46.786962 8 MB downloaded in 0.46 s (17.68 MB/s)
117 11:37:46.787102 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:37:46.787306 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:37:46.787385 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:37:46.787460 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:37:46.787533 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:37:46.787604 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:37:46.787770 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65
125 11:37:46.787885 makedir: /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin
126 11:37:46.787972 makedir: /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/tests
127 11:37:46.788058 makedir: /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/results
128 11:37:46.788141 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-add-keys
129 11:37:46.788264 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-add-sources
130 11:37:46.788378 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-background-process-start
131 11:37:46.788499 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-background-process-stop
132 11:37:46.788621 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-common-functions
133 11:37:46.788734 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-echo-ipv4
134 11:37:46.788844 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-install-packages
135 11:37:46.788954 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-installed-packages
136 11:37:46.789062 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-os-build
137 11:37:46.789170 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-probe-channel
138 11:37:46.789315 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-probe-ip
139 11:37:46.789424 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-target-ip
140 11:37:46.789541 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-target-mac
141 11:37:46.789651 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-target-storage
142 11:37:46.789762 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-case
143 11:37:46.789872 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-event
144 11:37:46.789980 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-feedback
145 11:37:46.790088 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-raise
146 11:37:46.790199 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-reference
147 11:37:46.790307 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-runner
148 11:37:46.790514 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-set
149 11:37:46.790702 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-test-shell
150 11:37:46.790817 Updating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-install-packages (oe)
151 11:37:46.790955 Updating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/bin/lava-installed-packages (oe)
152 11:37:46.791064 Creating /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/environment
153 11:37:46.791153 LAVA metadata
154 11:37:46.791215 - LAVA_JOB_ID=14864651
155 11:37:46.791270 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:37:46.791356 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:37:46.791414 skipped lava-vland-overlay
158 11:37:46.791480 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:37:46.791549 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:37:46.791600 skipped lava-multinode-overlay
161 11:37:46.791662 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:37:46.791728 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:37:46.791791 Loading test definitions
164 11:37:46.791864 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:37:46.791921 Using /lava-14864651 at stage 0
166 11:37:46.792203 uuid=14864651_1.5.2.3.1 testdef=None
167 11:37:46.792281 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:37:46.792393 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:37:46.792841 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:37:46.793031 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:37:46.793624 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:37:46.793825 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:37:46.794945 runner path: /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/0/tests/0_igt-gpu-panfrost test_uuid 14864651_1.5.2.3.1
176 11:37:46.795090 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:37:46.795275 Creating lava-test-runner.conf files
179 11:37:46.795330 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864651/lava-overlay-ifffmn65/lava-14864651/0 for stage 0
180 11:37:46.795408 - 0_igt-gpu-panfrost
181 11:37:46.795494 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:37:46.795568 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:37:46.801643 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:37:46.801735 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:37:46.801811 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:37:46.801887 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:37:46.801961 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:37:48.313527 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:37:48.313673 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:37:48.313747 extracting modules file /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864651/extract-overlay-ramdisk-ye6tlpdo/ramdisk
191 11:37:48.546376 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:37:48.546519 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:37:48.546598 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864651/compress-overlay-c6cm8r9c/overlay-1.5.2.4.tar.gz to ramdisk
194 11:37:48.546658 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864651/compress-overlay-c6cm8r9c/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864651/extract-overlay-ramdisk-ye6tlpdo/ramdisk
195 11:37:48.552991 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:37:48.553085 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:37:48.553168 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:37:48.553256 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:37:48.553321 Building ramdisk /var/lib/lava/dispatcher/tmp/14864651/extract-overlay-ramdisk-ye6tlpdo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864651/extract-overlay-ramdisk-ye6tlpdo/ramdisk
200 11:37:49.541475 >> 465549 blocks
201 11:37:55.723486 rename /var/lib/lava/dispatcher/tmp/14864651/extract-overlay-ramdisk-ye6tlpdo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/ramdisk/ramdisk.cpio.gz
202 11:37:55.723670 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:37:55.723766 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 11:37:55.723857 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 11:37:55.723944 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/kernel/Image']
206 11:38:08.939331 Returned 0 in 13 seconds
207 11:38:08.939500 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/kernel/image.itb
208 11:38:09.774245 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:38:09.774367 output: Created: Wed Jul 17 12:38:09 2024
210 11:38:09.774427 output: Image 0 (kernel-1)
211 11:38:09.774486 output: Description:
212 11:38:09.774549 output: Created: Wed Jul 17 12:38:09 2024
213 11:38:09.774601 output: Type: Kernel Image
214 11:38:09.774650 output: Compression: lzma compressed
215 11:38:09.774699 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
216 11:38:09.774748 output: Architecture: AArch64
217 11:38:09.774796 output: OS: Linux
218 11:38:09.774843 output: Load Address: 0x00000000
219 11:38:09.774890 output: Entry Point: 0x00000000
220 11:38:09.774937 output: Hash algo: crc32
221 11:38:09.774984 output: Hash value: 83448d17
222 11:38:09.775031 output: Image 1 (fdt-1)
223 11:38:09.775077 output: Description: mt8192-asurada-spherion-r0
224 11:38:09.775125 output: Created: Wed Jul 17 12:38:09 2024
225 11:38:09.775172 output: Type: Flat Device Tree
226 11:38:09.775220 output: Compression: uncompressed
227 11:38:09.775266 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 11:38:09.775313 output: Architecture: AArch64
229 11:38:09.775359 output: Hash algo: crc32
230 11:38:09.775406 output: Hash value: 0f8e4d2e
231 11:38:09.775453 output: Image 2 (ramdisk-1)
232 11:38:09.775499 output: Description: unavailable
233 11:38:09.775546 output: Created: Wed Jul 17 12:38:09 2024
234 11:38:09.775592 output: Type: RAMDisk Image
235 11:38:09.775638 output: Compression: uncompressed
236 11:38:09.775684 output: Data Size: 60985909 Bytes = 59556.55 KiB = 58.16 MiB
237 11:38:09.775731 output: Architecture: AArch64
238 11:38:09.775793 output: OS: Linux
239 11:38:09.775840 output: Load Address: unavailable
240 11:38:09.775887 output: Entry Point: unavailable
241 11:38:09.775946 output: Hash algo: crc32
242 11:38:09.775991 output: Hash value: 37816897
243 11:38:09.776038 output: Default Configuration: 'conf-1'
244 11:38:09.776084 output: Configuration 0 (conf-1)
245 11:38:09.776144 output: Description: mt8192-asurada-spherion-r0
246 11:38:09.776192 output: Kernel: kernel-1
247 11:38:09.776238 output: Init Ramdisk: ramdisk-1
248 11:38:09.776298 output: FDT: fdt-1
249 11:38:09.776345 output: Loadables: kernel-1
250 11:38:09.776406 output:
251 11:38:09.776513 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:38:09.776584 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:38:09.776656 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 11:38:09.776728 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 11:38:09.776784 No LXC device requested
256 11:38:09.776851 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:38:09.776919 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 11:38:09.776985 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:38:09.777038 Checking files for TFTP limit of 4294967296 bytes.
260 11:38:09.777451 end: 1 tftp-deploy (duration 00:00:24) [common]
261 11:38:09.777537 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:38:09.777612 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:38:09.777699 substitutions:
264 11:38:09.777756 - {DTB}: 14864651/tftp-deploy-lbt7ol7e/dtb/mt8192-asurada-spherion-r0.dtb
265 11:38:09.777809 - {INITRD}: 14864651/tftp-deploy-lbt7ol7e/ramdisk/ramdisk.cpio.gz
266 11:38:09.777860 - {KERNEL}: 14864651/tftp-deploy-lbt7ol7e/kernel/Image
267 11:38:09.777909 - {LAVA_MAC}: None
268 11:38:09.777958 - {PRESEED_CONFIG}: None
269 11:38:09.778005 - {PRESEED_LOCAL}: None
270 11:38:09.778053 - {RAMDISK}: 14864651/tftp-deploy-lbt7ol7e/ramdisk/ramdisk.cpio.gz
271 11:38:09.778120 - {ROOT_PART}: None
272 11:38:09.778182 - {ROOT}: None
273 11:38:09.778229 - {SERVER_IP}: 192.168.201.1
274 11:38:09.778276 - {TEE}: None
275 11:38:09.778323 Parsed boot commands:
276 11:38:09.778369 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:38:09.778508 Parsed boot commands: tftpboot 192.168.201.1 14864651/tftp-deploy-lbt7ol7e/kernel/image.itb 14864651/tftp-deploy-lbt7ol7e/kernel/cmdline
278 11:38:09.778585 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:38:09.778656 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:38:09.778726 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:38:09.778795 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:38:09.778847 Not connected, no need to disconnect.
283 11:38:09.778910 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:38:09.778975 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:38:09.779028 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:38:09.781933 Setting prompt string to ['lava-test: # ']
287 11:38:09.782253 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:38:09.782339 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:38:09.782425 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:38:09.782545 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:38:09.782740 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 11:38:18.964304 >> Command sent successfully.
293 11:38:18.977831 Returned 0 in 9 seconds
294 11:38:18.978474 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 11:38:18.979588 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 11:38:18.980076 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 11:38:18.980569 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:38:18.980909 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:38:18.981323 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:38:18.983202 [Enter `^Ec?' for help]
302 11:38:20.342454
303 11:38:20.343001
304 11:38:20.343492 F0: 102B 0000
305 11:38:20.343850
306 11:38:20.344148 F3: 1001 0000 [0200]
307 11:38:20.344460
308 11:38:20.345048 F3: 1001 0000
309 11:38:20.345411
310 11:38:20.345702 F7: 102D 0000
311 11:38:20.345982
312 11:38:20.348204 F1: 0000 0000
313 11:38:20.348635
314 11:38:20.348954 V0: 0000 0000 [0001]
315 11:38:20.349302
316 11:38:20.349601 00: 0007 8000
317 11:38:20.349893
318 11:38:20.351943 01: 0000 0000
319 11:38:20.352370
320 11:38:20.352690 BP: 0C00 0209 [0000]
321 11:38:20.352988
322 11:38:20.355670 G0: 1182 0000
323 11:38:20.356087
324 11:38:20.356458 EC: 0000 0021 [4000]
325 11:38:20.356760
326 11:38:20.360756 S7: 0000 0000 [0000]
327 11:38:20.361170
328 11:38:20.361732 CC: 0000 0000 [0001]
329 11:38:20.362058
330 11:38:20.363398 T0: 0000 0040 [010F]
331 11:38:20.363832
332 11:38:20.364173 Jump to BL
333 11:38:20.364472
334 11:38:20.389155
335 11:38:20.389884
336 11:38:20.395227 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:38:20.399043 ARM64: Exception handlers installed.
338 11:38:20.402970 ARM64: Testing exception
339 11:38:20.406318 ARM64: Done test exception
340 11:38:20.413517 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:38:20.422850 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:38:20.430423 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:38:20.437882 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:38:20.445404 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:38:20.452274 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:38:20.465028 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:38:20.472393 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:38:20.491628 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:38:20.496026 WDT: Last reset was cold boot
350 11:38:20.498786 SPI1(PAD0) initialized at 2873684 Hz
351 11:38:20.502768 SPI5(PAD0) initialized at 992727 Hz
352 11:38:20.502890 VBOOT: Loading verstage.
353 11:38:20.510288 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:38:20.514439 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:38:20.517191 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:38:20.520840 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:38:20.528902 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:38:20.535741 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:38:20.546418 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 11:38:20.546498
361 11:38:20.546556
362 11:38:20.557388 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:38:20.557504 ARM64: Exception handlers installed.
364 11:38:20.561573 ARM64: Testing exception
365 11:38:20.564939 ARM64: Done test exception
366 11:38:20.569377 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:38:20.572765 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:38:20.587659 Probing TPM: . done!
369 11:38:20.587760 TPM ready after 0 ms
370 11:38:20.594873 Connected to device vid:did:rid of 1ae0:0028:00
371 11:38:20.601698 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 11:38:20.653971 Initialized TPM device CR50 revision 0
373 11:38:20.664592 tlcl_send_startup: Startup return code is 0
374 11:38:20.664704 TPM: setup succeeded
375 11:38:20.676699 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:38:20.685797 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:38:20.695238 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:38:20.703978 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:38:20.707523 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:38:20.710765 in-header: 03 07 00 00 08 00 00 00
381 11:38:20.714440 in-data: aa e4 47 04 13 02 00 00
382 11:38:20.717666 Chrome EC: UHEPI supported
383 11:38:20.724146 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:38:20.728532 in-header: 03 a9 00 00 08 00 00 00
385 11:38:20.730931 in-data: 84 60 60 08 00 00 00 00
386 11:38:20.734180 Phase 1
387 11:38:20.737607 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:38:20.744024 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:38:20.748261 VB2:vb2_check_recovery() Recovery was requested manually
390 11:38:20.754368 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 11:38:20.757547 Recovery requested (1009000e)
392 11:38:20.764345 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:38:20.769482 tlcl_extend: response is 0
394 11:38:20.779301 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:38:20.782864 tlcl_extend: response is 0
396 11:38:20.789515 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:38:20.810303 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:38:20.817261 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:38:20.817706
400 11:38:20.817982
401 11:38:20.827054 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:38:20.830605 ARM64: Exception handlers installed.
403 11:38:20.833856 ARM64: Testing exception
404 11:38:20.834355 ARM64: Done test exception
405 11:38:20.857075 pmic_efuse_setting: Set efuses in 11 msecs
406 11:38:20.859498 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:38:20.866287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:38:20.869152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:38:20.876380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:38:20.879287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:38:20.886961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:38:20.889180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:38:20.892855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:38:20.899102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:38:20.902559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:38:20.909841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:38:20.912920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:38:20.915800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:38:20.922343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:38:20.929818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:38:20.932755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:38:20.939484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:38:20.946061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:38:20.949956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:38:20.955968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:38:20.962398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:38:20.966901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:38:20.972984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:38:20.979106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:38:20.982562 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:38:20.989326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:38:20.996135 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:38:20.999505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:38:21.005899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:38:21.010099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:38:21.015779 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:38:21.019297 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:38:21.027054 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:38:21.030068 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:38:21.036033 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:38:21.039579 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:38:21.045918 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:38:21.049949 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:38:21.052857 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:38:21.060221 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:38:21.064342 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:38:21.067434 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:38:21.071268 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:38:21.078536 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:38:21.080912 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:38:21.084195 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:38:21.091411 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:38:21.095443 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:38:21.097865 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:38:21.101798 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:38:21.107858 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:38:21.111641 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:38:21.118186 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 11:38:21.128557 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:38:21.131863 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:38:21.141857 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:38:21.148970 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:38:21.152079 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:38:21.158191 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:38:21.162888 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:38:21.168799 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
467 11:38:21.176912 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:38:21.179525 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:38:21.181962 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:38:21.193621 [RTC]rtc_get_frequency_meter,154: input=15, output=763
471 11:38:21.202960 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 11:38:21.212825 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 11:38:21.221694 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 11:38:21.231309 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:38:21.240698 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 11:38:21.250133 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 11:38:21.253453 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:38:21.260859 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:38:21.264164 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:38:21.267047 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:38:21.274049 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:38:21.277603 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:38:21.280697 ADC[4]: Raw value=670432 ID=5
484 11:38:21.281201 ADC[3]: Raw value=212549 ID=1
485 11:38:21.284119 RAM Code: 0x51
486 11:38:21.286839 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:38:21.293846 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:38:21.300636 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:38:21.307139 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:38:21.311136 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:38:21.313938 in-header: 03 07 00 00 08 00 00 00
492 11:38:21.316772 in-data: aa e4 47 04 13 02 00 00
493 11:38:21.320903 Chrome EC: UHEPI supported
494 11:38:21.326753 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:38:21.330337 in-header: 03 a9 00 00 08 00 00 00
496 11:38:21.333387 in-data: 84 60 60 08 00 00 00 00
497 11:38:21.336968 MRC: failed to locate region type 0.
498 11:38:21.343616 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:38:21.344134 DRAM-K: Running full calibration
500 11:38:21.350191 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:38:21.353965 header.status = 0x0
502 11:38:21.356981 header.version = 0x6 (expected: 0x6)
503 11:38:21.360986 header.size = 0xd00 (expected: 0xd00)
504 11:38:21.361604 header.flags = 0x0
505 11:38:21.366878 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:38:21.385812 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:38:21.392421 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:38:21.394932 dram_init: ddr_geometry: 0
509 11:38:21.398347 [EMI] MDL number = 0
510 11:38:21.398775 [EMI] Get MDL freq = 0
511 11:38:21.402184 dram_init: ddr_type: 0
512 11:38:21.402695 is_discrete_lpddr4: 1
513 11:38:21.405038 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:38:21.405506
515 11:38:21.405837
516 11:38:21.408405 [Bian_co] ETT version 0.0.0.1
517 11:38:21.415047 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:38:21.415547
519 11:38:21.418116 dramc_set_vcore_voltage set vcore to 650000
520 11:38:21.418688 Read voltage for 800, 4
521 11:38:21.422153 Vio18 = 0
522 11:38:21.422577 Vcore = 650000
523 11:38:21.422907 Vdram = 0
524 11:38:21.424733 Vddq = 0
525 11:38:21.425154 Vmddr = 0
526 11:38:21.428692 dram_init: config_dvfs: 1
527 11:38:21.432412 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:38:21.438698 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:38:21.441440 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:38:21.445341 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:38:21.448734 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:38:21.451565 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:38:21.454765 MEM_TYPE=3, freq_sel=18
534 11:38:21.458354 sv_algorithm_assistance_LP4_1600
535 11:38:21.462064 ============ PULL DRAM RESETB DOWN ============
536 11:38:21.464982 ========== PULL DRAM RESETB DOWN end =========
537 11:38:21.471668 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:38:21.475639 ===================================
539 11:38:21.478598 LPDDR4 DRAM CONFIGURATION
540 11:38:21.482129 ===================================
541 11:38:21.482641 EX_ROW_EN[0] = 0x0
542 11:38:21.485347 EX_ROW_EN[1] = 0x0
543 11:38:21.485860 LP4Y_EN = 0x0
544 11:38:21.488584 WORK_FSP = 0x0
545 11:38:21.489086 WL = 0x2
546 11:38:21.491638 RL = 0x2
547 11:38:21.492065 BL = 0x2
548 11:38:21.494699 RPST = 0x0
549 11:38:21.495169 RD_PRE = 0x0
550 11:38:21.498231 WR_PRE = 0x1
551 11:38:21.498655 WR_PST = 0x0
552 11:38:21.501447 DBI_WR = 0x0
553 11:38:21.501875 DBI_RD = 0x0
554 11:38:21.505563 OTF = 0x1
555 11:38:21.509186 ===================================
556 11:38:21.511701 ===================================
557 11:38:21.512131 ANA top config
558 11:38:21.514704 ===================================
559 11:38:21.519074 DLL_ASYNC_EN = 0
560 11:38:21.521607 ALL_SLAVE_EN = 1
561 11:38:21.524986 NEW_RANK_MODE = 1
562 11:38:21.525515 DLL_IDLE_MODE = 1
563 11:38:21.528333 LP45_APHY_COMB_EN = 1
564 11:38:21.531651 TX_ODT_DIS = 1
565 11:38:21.535316 NEW_8X_MODE = 1
566 11:38:21.538442 ===================================
567 11:38:21.541734 ===================================
568 11:38:21.545416 data_rate = 1600
569 11:38:21.545920 CKR = 1
570 11:38:21.548451 DQ_P2S_RATIO = 8
571 11:38:21.551393 ===================================
572 11:38:21.555723 CA_P2S_RATIO = 8
573 11:38:21.558280 DQ_CA_OPEN = 0
574 11:38:21.561826 DQ_SEMI_OPEN = 0
575 11:38:21.565329 CA_SEMI_OPEN = 0
576 11:38:21.565836 CA_FULL_RATE = 0
577 11:38:21.567900 DQ_CKDIV4_EN = 1
578 11:38:21.571958 CA_CKDIV4_EN = 1
579 11:38:21.575370 CA_PREDIV_EN = 0
580 11:38:21.578188 PH8_DLY = 0
581 11:38:21.581813 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:38:21.582438 DQ_AAMCK_DIV = 4
583 11:38:21.584756 CA_AAMCK_DIV = 4
584 11:38:21.588674 CA_ADMCK_DIV = 4
585 11:38:21.591234 DQ_TRACK_CA_EN = 0
586 11:38:21.594818 CA_PICK = 800
587 11:38:21.598583 CA_MCKIO = 800
588 11:38:21.599085 MCKIO_SEMI = 0
589 11:38:21.601858 PLL_FREQ = 3068
590 11:38:21.605274 DQ_UI_PI_RATIO = 32
591 11:38:21.608789 CA_UI_PI_RATIO = 0
592 11:38:21.611631 ===================================
593 11:38:21.615271 ===================================
594 11:38:21.618377 memory_type:LPDDR4
595 11:38:21.618815 GP_NUM : 10
596 11:38:21.621657 SRAM_EN : 1
597 11:38:21.624643 MD32_EN : 0
598 11:38:21.627765 ===================================
599 11:38:21.628268 [ANA_INIT] >>>>>>>>>>>>>>
600 11:38:21.631872 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:38:21.635560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:38:21.639127 ===================================
603 11:38:21.641842 data_rate = 1600,PCW = 0X7600
604 11:38:21.644736 ===================================
605 11:38:21.648157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:38:21.654509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:38:21.657981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:38:21.665115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:38:21.667846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:38:21.671458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:38:21.672005 [ANA_INIT] flow start
612 11:38:21.675192 [ANA_INIT] PLL >>>>>>>>
613 11:38:21.678198 [ANA_INIT] PLL <<<<<<<<
614 11:38:21.678619 [ANA_INIT] MIDPI >>>>>>>>
615 11:38:21.681699 [ANA_INIT] MIDPI <<<<<<<<
616 11:38:21.685551 [ANA_INIT] DLL >>>>>>>>
617 11:38:21.686155 [ANA_INIT] flow end
618 11:38:21.691751 ============ LP4 DIFF to SE enter ============
619 11:38:21.695484 ============ LP4 DIFF to SE exit ============
620 11:38:21.699244 [ANA_INIT] <<<<<<<<<<<<<
621 11:38:21.701442 [Flow] Enable top DCM control >>>>>
622 11:38:21.704880 [Flow] Enable top DCM control <<<<<
623 11:38:21.705419 Enable DLL master slave shuffle
624 11:38:21.711409 ==============================================================
625 11:38:21.715519 Gating Mode config
626 11:38:21.718375 ==============================================================
627 11:38:21.722162 Config description:
628 11:38:21.729190 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:38:21.736697 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:38:21.743249 SELPH_MODE 0: By rank 1: By Phase
631 11:38:21.747901 ==============================================================
632 11:38:21.751028 GAT_TRACK_EN = 1
633 11:38:21.755271 RX_GATING_MODE = 2
634 11:38:21.757602 RX_GATING_TRACK_MODE = 2
635 11:38:21.758045 SELPH_MODE = 1
636 11:38:21.760978 PICG_EARLY_EN = 1
637 11:38:21.764672 VALID_LAT_VALUE = 1
638 11:38:21.771094 ==============================================================
639 11:38:21.774452 Enter into Gating configuration >>>>
640 11:38:21.778670 Exit from Gating configuration <<<<
641 11:38:21.781791 Enter into DVFS_PRE_config >>>>>
642 11:38:21.791342 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:38:21.794782 Exit from DVFS_PRE_config <<<<<
644 11:38:21.798239 Enter into PICG configuration >>>>
645 11:38:21.801701 Exit from PICG configuration <<<<
646 11:38:21.805196 [RX_INPUT] configuration >>>>>
647 11:38:21.807997 [RX_INPUT] configuration <<<<<
648 11:38:21.811656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:38:21.818431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:38:21.825092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:38:21.828384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:38:21.834723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:38:21.842321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:38:21.845546 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:38:21.851690 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:38:21.855102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:38:21.858339 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:38:21.861478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:38:21.868657 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:38:21.872030 ===================================
661 11:38:21.872535 LPDDR4 DRAM CONFIGURATION
662 11:38:21.874485 ===================================
663 11:38:21.879156 EX_ROW_EN[0] = 0x0
664 11:38:21.882229 EX_ROW_EN[1] = 0x0
665 11:38:21.882774 LP4Y_EN = 0x0
666 11:38:21.885129 WORK_FSP = 0x0
667 11:38:21.885675 WL = 0x2
668 11:38:21.888208 RL = 0x2
669 11:38:21.888661 BL = 0x2
670 11:38:21.891434 RPST = 0x0
671 11:38:21.891856 RD_PRE = 0x0
672 11:38:21.895114 WR_PRE = 0x1
673 11:38:21.895615 WR_PST = 0x0
674 11:38:21.898617 DBI_WR = 0x0
675 11:38:21.899043 DBI_RD = 0x0
676 11:38:21.901391 OTF = 0x1
677 11:38:21.904636 ===================================
678 11:38:21.908515 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:38:21.912235 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:38:21.918175 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:38:21.918689 ===================================
682 11:38:21.921700 LPDDR4 DRAM CONFIGURATION
683 11:38:21.924646 ===================================
684 11:38:21.928111 EX_ROW_EN[0] = 0x10
685 11:38:21.928539 EX_ROW_EN[1] = 0x0
686 11:38:21.931459 LP4Y_EN = 0x0
687 11:38:21.931959 WORK_FSP = 0x0
688 11:38:21.935526 WL = 0x2
689 11:38:21.936024 RL = 0x2
690 11:38:21.937942 BL = 0x2
691 11:38:21.941878 RPST = 0x0
692 11:38:21.942377 RD_PRE = 0x0
693 11:38:21.945014 WR_PRE = 0x1
694 11:38:21.945564 WR_PST = 0x0
695 11:38:21.948788 DBI_WR = 0x0
696 11:38:21.949214 DBI_RD = 0x0
697 11:38:21.951775 OTF = 0x1
698 11:38:21.955080 ===================================
699 11:38:21.958181 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:38:21.964076 nWR fixed to 40
701 11:38:21.966587 [ModeRegInit_LP4] CH0 RK0
702 11:38:21.967015 [ModeRegInit_LP4] CH0 RK1
703 11:38:21.970867 [ModeRegInit_LP4] CH1 RK0
704 11:38:21.975116 [ModeRegInit_LP4] CH1 RK1
705 11:38:21.975544 match AC timing 12
706 11:38:21.980292 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:38:21.984144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:38:21.987077 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:38:21.993351 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:38:21.996775 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:38:21.997327 [EMI DOE] emi_dcm 0
712 11:38:22.003353 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:38:22.003792 ==
714 11:38:22.006622 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:38:22.010408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:38:22.010915 ==
717 11:38:22.016993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:38:22.023296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:38:22.031516 [CA 0] Center 37 (7~68) winsize 62
720 11:38:22.033894 [CA 1] Center 37 (7~68) winsize 62
721 11:38:22.037939 [CA 2] Center 35 (5~66) winsize 62
722 11:38:22.040789 [CA 3] Center 35 (5~66) winsize 62
723 11:38:22.043910 [CA 4] Center 34 (4~65) winsize 62
724 11:38:22.048125 [CA 5] Center 33 (3~64) winsize 62
725 11:38:22.048651
726 11:38:22.052170 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:38:22.052695
728 11:38:22.055012 [CATrainingPosCal] consider 1 rank data
729 11:38:22.059771 u2DelayCellTimex100 = 270/100 ps
730 11:38:22.061702 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:38:22.064946 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:38:22.068715 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:38:22.074947 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 11:38:22.078222 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 11:38:22.081588 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:38:22.082092
737 11:38:22.085055 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:38:22.085596
739 11:38:22.088040 [CBTSetCACLKResult] CA Dly = 33
740 11:38:22.088468 CS Dly: 5 (0~36)
741 11:38:22.088797 ==
742 11:38:22.091429 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:38:22.098233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:38:22.098729 ==
745 11:38:22.101127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:38:22.107953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:38:22.116563 [CA 0] Center 37 (7~68) winsize 62
748 11:38:22.120253 [CA 1] Center 37 (7~68) winsize 62
749 11:38:22.123936 [CA 2] Center 35 (4~66) winsize 63
750 11:38:22.126966 [CA 3] Center 35 (4~66) winsize 63
751 11:38:22.129991 [CA 4] Center 33 (3~64) winsize 62
752 11:38:22.133280 [CA 5] Center 34 (3~65) winsize 63
753 11:38:22.133712
754 11:38:22.137780 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:38:22.138281
756 11:38:22.140370 [CATrainingPosCal] consider 2 rank data
757 11:38:22.143264 u2DelayCellTimex100 = 270/100 ps
758 11:38:22.147293 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:38:22.149786 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:38:22.156346 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:38:22.160159 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
762 11:38:22.163326 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 11:38:22.166758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:38:22.167239
765 11:38:22.170311 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:38:22.170738
767 11:38:22.173281 [CBTSetCACLKResult] CA Dly = 33
768 11:38:22.173712 CS Dly: 5 (0~37)
769 11:38:22.174046
770 11:38:22.176435 ----->DramcWriteLeveling(PI) begin...
771 11:38:22.179966 ==
772 11:38:22.183550 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:38:22.186365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:38:22.186749 ==
775 11:38:22.190193 Write leveling (Byte 0): 32 => 32
776 11:38:22.193736 Write leveling (Byte 1): 26 => 26
777 11:38:22.196708 DramcWriteLeveling(PI) end<-----
778 11:38:22.197085
779 11:38:22.197417 ==
780 11:38:22.200369 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:38:22.203496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:38:22.203877 ==
783 11:38:22.206491 [Gating] SW mode calibration
784 11:38:22.213026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:38:22.216798 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:38:22.223889 0 6 0 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 0)
787 11:38:22.226583 0 6 4 | B1->B0 | 2727 2424 | 1 0 | (1 0) (1 0)
788 11:38:22.229980 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:38:22.237024 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:38:22.240749 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:38:22.243414 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:38:22.250391 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:38:22.253152 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:38:22.256862 0 7 0 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
795 11:38:22.264568 0 7 4 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
796 11:38:22.266801 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:38:22.269962 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:38:22.276167 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:38:22.280005 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:38:22.284583 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:38:22.290254 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:38:22.293654 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 11:38:22.296504 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:38:22.299818 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:38:22.307258 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:38:22.310633 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:38:22.313625 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:38:22.320236 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:38:22.324236 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:38:22.327079 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:38:22.333635 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:38:22.337096 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:38:22.340160 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:38:22.346816 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:38:22.350187 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:38:22.353462 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:38:22.360587 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 11:38:22.363805 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 11:38:22.366869 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 11:38:22.370882 Total UI for P1: 0, mck2ui 16
821 11:38:22.373459 best dqsien dly found for B0: ( 0, 10, 2)
822 11:38:22.376586 Total UI for P1: 0, mck2ui 16
823 11:38:22.381107 best dqsien dly found for B1: ( 0, 10, 0)
824 11:38:22.383600 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 11:38:22.386606 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 11:38:22.387025
827 11:38:22.390797 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 11:38:22.396998 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 11:38:22.397530 [Gating] SW calibration Done
830 11:38:22.397864 ==
831 11:38:22.400399 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:38:22.406730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:38:22.407215 ==
834 11:38:22.407542 RX Vref Scan: 0
835 11:38:22.407846
836 11:38:22.410179 RX Vref 0 -> 0, step: 1
837 11:38:22.410597
838 11:38:22.413485 RX Delay -130 -> 252, step: 16
839 11:38:22.417123 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 11:38:22.420398 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:38:22.423667 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 11:38:22.430026 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:38:22.433673 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 11:38:22.436463 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:38:22.440506 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 11:38:22.443346 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 11:38:22.450305 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:38:22.453452 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 11:38:22.457050 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:38:22.460306 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:38:22.464038 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:38:22.470058 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 11:38:22.473819 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:38:22.477923 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:38:22.478422 ==
856 11:38:22.480888 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:38:22.483207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:38:22.483654 ==
859 11:38:22.487241 DQS Delay:
860 11:38:22.487748 DQS0 = 0, DQS1 = 0
861 11:38:22.490615 DQM Delay:
862 11:38:22.491121 DQM0 = 82, DQM1 = 74
863 11:38:22.491456 DQ Delay:
864 11:38:22.493163 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 11:38:22.497465 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 11:38:22.499745 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 11:38:22.503207 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 11:38:22.503636
869 11:38:22.503965
870 11:38:22.504272 ==
871 11:38:22.506987 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:38:22.513523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:38:22.514033 ==
874 11:38:22.514371
875 11:38:22.514675
876 11:38:22.514966 TX Vref Scan disable
877 11:38:22.518879 == TX Byte 0 ==
878 11:38:22.521139 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
879 11:38:22.528202 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
880 11:38:22.528708 == TX Byte 1 ==
881 11:38:22.531187 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
882 11:38:22.533828 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
883 11:38:22.537331 ==
884 11:38:22.540678 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:38:22.544141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:38:22.544644 ==
887 11:38:22.556917 TX Vref=22, minBit 2, minWin=27, winSum=441
888 11:38:22.560389 TX Vref=24, minBit 9, minWin=27, winSum=448
889 11:38:22.564264 TX Vref=26, minBit 11, minWin=27, winSum=453
890 11:38:22.566846 TX Vref=28, minBit 11, minWin=27, winSum=455
891 11:38:22.570465 TX Vref=30, minBit 2, minWin=28, winSum=455
892 11:38:22.577450 TX Vref=32, minBit 13, minWin=27, winSum=451
893 11:38:22.580385 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
894 11:38:22.580886
895 11:38:22.583313 Final TX Range 1 Vref 30
896 11:38:22.583743
897 11:38:22.584070 ==
898 11:38:22.587605 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:38:22.590235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:38:22.590666 ==
901 11:38:22.593785
902 11:38:22.594206
903 11:38:22.594535 TX Vref Scan disable
904 11:38:22.597505 == TX Byte 0 ==
905 11:38:22.600408 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 11:38:22.607213 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 11:38:22.607716 == TX Byte 1 ==
908 11:38:22.610304 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
909 11:38:22.618376 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
910 11:38:22.618876
911 11:38:22.619205 [DATLAT]
912 11:38:22.619508 Freq=800, CH0 RK0
913 11:38:22.619801
914 11:38:22.620436 DATLAT Default: 0xa
915 11:38:22.620760 0, 0xFFFF, sum = 0
916 11:38:22.623659 1, 0xFFFF, sum = 0
917 11:38:22.627212 2, 0xFFFF, sum = 0
918 11:38:22.627639 3, 0xFFFF, sum = 0
919 11:38:22.630476 4, 0xFFFF, sum = 0
920 11:38:22.630908 5, 0xFFFF, sum = 0
921 11:38:22.634110 6, 0xFFFF, sum = 0
922 11:38:22.634615 7, 0xFFFF, sum = 0
923 11:38:22.636959 8, 0x0, sum = 1
924 11:38:22.637524 9, 0x0, sum = 2
925 11:38:22.637866 10, 0x0, sum = 3
926 11:38:22.640873 11, 0x0, sum = 4
927 11:38:22.641433 best_step = 9
928 11:38:22.641774
929 11:38:22.642076 ==
930 11:38:22.643678 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:38:22.650370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:38:22.650866 ==
933 11:38:22.651201 RX Vref Scan: 1
934 11:38:22.651503
935 11:38:22.654493 Set Vref Range= 32 -> 127
936 11:38:22.654994
937 11:38:22.656813 RX Vref 32 -> 127, step: 1
938 11:38:22.657342
939 11:38:22.660809 RX Delay -111 -> 252, step: 8
940 11:38:22.661352
941 11:38:22.663699 Set Vref, RX VrefLevel [Byte0]: 32
942 11:38:22.666901 [Byte1]: 32
943 11:38:22.667319
944 11:38:22.669910 Set Vref, RX VrefLevel [Byte0]: 33
945 11:38:22.673302 [Byte1]: 33
946 11:38:22.673800
947 11:38:22.676918 Set Vref, RX VrefLevel [Byte0]: 34
948 11:38:22.680554 [Byte1]: 34
949 11:38:22.683501
950 11:38:22.683922 Set Vref, RX VrefLevel [Byte0]: 35
951 11:38:22.686722 [Byte1]: 35
952 11:38:22.692061
953 11:38:22.692568 Set Vref, RX VrefLevel [Byte0]: 36
954 11:38:22.694475 [Byte1]: 36
955 11:38:22.698971
956 11:38:22.699471 Set Vref, RX VrefLevel [Byte0]: 37
957 11:38:22.702439 [Byte1]: 37
958 11:38:22.706426
959 11:38:22.706864 Set Vref, RX VrefLevel [Byte0]: 38
960 11:38:22.709714 [Byte1]: 38
961 11:38:22.715055
962 11:38:22.715494 Set Vref, RX VrefLevel [Byte0]: 39
963 11:38:22.717477 [Byte1]: 39
964 11:38:22.722087
965 11:38:22.722607 Set Vref, RX VrefLevel [Byte0]: 40
966 11:38:22.725299 [Byte1]: 40
967 11:38:22.729352
968 11:38:22.729795 Set Vref, RX VrefLevel [Byte0]: 41
969 11:38:22.732880 [Byte1]: 41
970 11:38:22.737053
971 11:38:22.737518 Set Vref, RX VrefLevel [Byte0]: 42
972 11:38:22.740732 [Byte1]: 42
973 11:38:22.745026
974 11:38:22.745585 Set Vref, RX VrefLevel [Byte0]: 43
975 11:38:22.748529 [Byte1]: 43
976 11:38:22.753862
977 11:38:22.754366 Set Vref, RX VrefLevel [Byte0]: 44
978 11:38:22.755889 [Byte1]: 44
979 11:38:22.760348
980 11:38:22.760884 Set Vref, RX VrefLevel [Byte0]: 45
981 11:38:22.763411 [Byte1]: 45
982 11:38:22.767812
983 11:38:22.768253 Set Vref, RX VrefLevel [Byte0]: 46
984 11:38:22.770905 [Byte1]: 46
985 11:38:22.775794
986 11:38:22.776314 Set Vref, RX VrefLevel [Byte0]: 47
987 11:38:22.778806 [Byte1]: 47
988 11:38:22.783221
989 11:38:22.783741 Set Vref, RX VrefLevel [Byte0]: 48
990 11:38:22.787431 [Byte1]: 48
991 11:38:22.790800
992 11:38:22.791320 Set Vref, RX VrefLevel [Byte0]: 49
993 11:38:22.794166 [Byte1]: 49
994 11:38:22.798519
995 11:38:22.799035 Set Vref, RX VrefLevel [Byte0]: 50
996 11:38:22.801347 [Byte1]: 50
997 11:38:22.806326
998 11:38:22.806851 Set Vref, RX VrefLevel [Byte0]: 51
999 11:38:22.809797 [Byte1]: 51
1000 11:38:22.813982
1001 11:38:22.814511 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:38:22.817149 [Byte1]: 52
1003 11:38:22.821321
1004 11:38:22.821822 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:38:22.824767 [Byte1]: 53
1006 11:38:22.828846
1007 11:38:22.829382 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:38:22.832238 [Byte1]: 54
1009 11:38:22.836310
1010 11:38:22.836733 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:38:22.839971 [Byte1]: 55
1012 11:38:22.843850
1013 11:38:22.844269 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:38:22.848097 [Byte1]: 56
1015 11:38:22.852357
1016 11:38:22.852863 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:38:22.855229 [Byte1]: 57
1018 11:38:22.859628
1019 11:38:22.860048 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:38:22.863837 [Byte1]: 58
1021 11:38:22.867199
1022 11:38:22.867628 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:38:22.870170 [Byte1]: 59
1024 11:38:22.875190
1025 11:38:22.875683 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:38:22.878909 [Byte1]: 60
1027 11:38:22.883015
1028 11:38:22.883515 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:38:22.885942 [Byte1]: 61
1030 11:38:22.890359
1031 11:38:22.890864 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:38:22.893738 [Byte1]: 62
1033 11:38:22.897709
1034 11:38:22.898131 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:38:22.900680 [Byte1]: 63
1036 11:38:22.906365
1037 11:38:22.906967 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:38:22.909176 [Byte1]: 64
1039 11:38:22.913163
1040 11:38:22.913710 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:38:22.916303 [Byte1]: 65
1042 11:38:22.920809
1043 11:38:22.921360 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:38:22.924301 [Byte1]: 66
1045 11:38:22.929010
1046 11:38:22.929540 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:38:22.931819 [Byte1]: 67
1048 11:38:22.935652
1049 11:38:22.936071 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:38:22.940480 [Byte1]: 68
1051 11:38:22.943996
1052 11:38:22.944421 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:38:22.946486 [Byte1]: 69
1054 11:38:22.951083
1055 11:38:22.951500 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:38:22.954320 [Byte1]: 70
1057 11:38:22.958924
1058 11:38:22.959346 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:38:22.962020 [Byte1]: 71
1060 11:38:22.966841
1061 11:38:22.967338 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:38:22.969558 [Byte1]: 72
1063 11:38:22.974248
1064 11:38:22.974747 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:38:22.977071 [Byte1]: 73
1066 11:38:22.982034
1067 11:38:22.982537 Set Vref, RX VrefLevel [Byte0]: 74
1068 11:38:22.985092 [Byte1]: 74
1069 11:38:22.989736
1070 11:38:22.990235 Set Vref, RX VrefLevel [Byte0]: 75
1071 11:38:22.993199 [Byte1]: 75
1072 11:38:22.997023
1073 11:38:22.997589 Set Vref, RX VrefLevel [Byte0]: 76
1074 11:38:23.000196 [Byte1]: 76
1075 11:38:23.004838
1076 11:38:23.005527 Final RX Vref Byte 0 = 50 to rank0
1077 11:38:23.008973 Final RX Vref Byte 1 = 55 to rank0
1078 11:38:23.011034 Final RX Vref Byte 0 = 50 to rank1
1079 11:38:23.014795 Final RX Vref Byte 1 = 55 to rank1==
1080 11:38:23.018119 Dram Type= 6, Freq= 0, CH_0, rank 0
1081 11:38:23.025402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1082 11:38:23.025913 ==
1083 11:38:23.026249 DQS Delay:
1084 11:38:23.026559 DQS0 = 0, DQS1 = 0
1085 11:38:23.027536 DQM Delay:
1086 11:38:23.027962 DQM0 = 84, DQM1 = 73
1087 11:38:23.031840 DQ Delay:
1088 11:38:23.034618 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1089 11:38:23.035048 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1090 11:38:23.038138 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1091 11:38:23.044307 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1092 11:38:23.044801
1093 11:38:23.045134
1094 11:38:23.051224 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1095 11:38:23.054671 CH0 RK0: MR19=606, MR18=3A3A
1096 11:38:23.061369 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1097 11:38:23.061886
1098 11:38:23.064227 ----->DramcWriteLeveling(PI) begin...
1099 11:38:23.064659 ==
1100 11:38:23.068496 Dram Type= 6, Freq= 0, CH_0, rank 1
1101 11:38:23.071059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1102 11:38:23.071486 ==
1103 11:38:23.075391 Write leveling (Byte 0): 30 => 30
1104 11:38:23.077879 Write leveling (Byte 1): 30 => 30
1105 11:38:23.081484 DramcWriteLeveling(PI) end<-----
1106 11:38:23.082142
1107 11:38:23.082490 ==
1108 11:38:23.084964 Dram Type= 6, Freq= 0, CH_0, rank 1
1109 11:38:23.088501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1110 11:38:23.089003 ==
1111 11:38:23.091779 [Gating] SW mode calibration
1112 11:38:23.098203 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1113 11:38:23.105196 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1114 11:38:23.108478 0 6 0 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
1115 11:38:23.111653 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1116 11:38:23.117992 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 11:38:23.121960 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 11:38:23.124748 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 11:38:23.131353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 11:38:23.134865 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 11:38:23.137927 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1122 11:38:23.144439 0 7 0 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1123 11:38:23.148350 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1124 11:38:23.152544 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 11:38:23.155639 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 11:38:23.161542 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 11:38:23.165031 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 11:38:23.167871 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 11:38:23.174467 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1130 11:38:23.178091 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1131 11:38:23.181384 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:38:23.188312 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:38:23.191788 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:38:23.195235 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:38:23.201671 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:38:23.205272 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:38:23.208173 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:38:23.215282 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:38:23.217972 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:38:23.221974 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 11:38:23.228650 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 11:38:23.232555 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 11:38:23.234597 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 11:38:23.241011 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 11:38:23.244584 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1146 11:38:23.248029 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1147 11:38:23.254570 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1148 11:38:23.255065 Total UI for P1: 0, mck2ui 16
1149 11:38:23.258783 best dqsien dly found for B0: ( 0, 9, 30)
1150 11:38:23.264264 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1151 11:38:23.308552 Total UI for P1: 0, mck2ui 16
1152 11:38:23.309101 best dqsien dly found for B1: ( 0, 10, 4)
1153 11:38:23.309600 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1154 11:38:23.310406 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1155 11:38:23.310755
1156 11:38:23.311063 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1157 11:38:23.311363 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1158 11:38:23.311657 [Gating] SW calibration Done
1159 11:38:23.311957 ==
1160 11:38:23.312260 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 11:38:23.312931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 11:38:23.313489 ==
1163 11:38:23.313799 RX Vref Scan: 0
1164 11:38:23.314087
1165 11:38:23.314365 RX Vref 0 -> 0, step: 1
1166 11:38:23.314641
1167 11:38:23.314915 RX Delay -130 -> 252, step: 16
1168 11:38:23.315194 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1169 11:38:23.325202 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1170 11:38:23.325754 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1171 11:38:23.326095 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1172 11:38:23.327734 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1173 11:38:23.328176 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1174 11:38:23.331548 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1175 11:38:23.334510 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1176 11:38:23.337811 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1177 11:38:23.340904 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1178 11:38:23.348025 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1179 11:38:23.351229 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1180 11:38:23.354471 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1181 11:38:23.357896 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1182 11:38:23.361468 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1183 11:38:23.367578 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1184 11:38:23.367998 ==
1185 11:38:23.371528 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 11:38:23.374612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1187 11:38:23.375072 ==
1188 11:38:23.375371 DQS Delay:
1189 11:38:23.378131 DQS0 = 0, DQS1 = 0
1190 11:38:23.378508 DQM Delay:
1191 11:38:23.380963 DQM0 = 81, DQM1 = 73
1192 11:38:23.381387 DQ Delay:
1193 11:38:23.384619 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1194 11:38:23.387443 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1195 11:38:23.390771 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1196 11:38:23.395454 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1197 11:38:23.395915
1198 11:38:23.396210
1199 11:38:23.396485 ==
1200 11:38:23.397423 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 11:38:23.401088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1202 11:38:23.401547 ==
1203 11:38:23.401934
1204 11:38:23.404975
1205 11:38:23.405592 TX Vref Scan disable
1206 11:38:23.407528 == TX Byte 0 ==
1207 11:38:23.411302 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1208 11:38:23.414296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1209 11:38:23.417595 == TX Byte 1 ==
1210 11:38:23.420865 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1211 11:38:23.423833 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1212 11:38:23.424226 ==
1213 11:38:23.427953 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:38:23.433927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1215 11:38:23.434386 ==
1216 11:38:23.445572 TX Vref=22, minBit 5, minWin=27, winSum=449
1217 11:38:23.449520 TX Vref=24, minBit 0, minWin=28, winSum=453
1218 11:38:23.453210 TX Vref=26, minBit 0, minWin=27, winSum=455
1219 11:38:23.456276 TX Vref=28, minBit 2, minWin=28, winSum=457
1220 11:38:23.458808 TX Vref=30, minBit 2, minWin=28, winSum=460
1221 11:38:23.462400 TX Vref=32, minBit 2, minWin=28, winSum=458
1222 11:38:23.470025 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1223 11:38:23.470457
1224 11:38:23.472977 Final TX Range 1 Vref 30
1225 11:38:23.473425
1226 11:38:23.473860 ==
1227 11:38:23.475867 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 11:38:23.478963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1229 11:38:23.479345 ==
1230 11:38:23.479638
1231 11:38:23.479906
1232 11:38:23.482885 TX Vref Scan disable
1233 11:38:23.485942 == TX Byte 0 ==
1234 11:38:23.489398 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1235 11:38:23.492894 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1236 11:38:23.496028 == TX Byte 1 ==
1237 11:38:23.499373 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1238 11:38:23.502415 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1239 11:38:23.502794
1240 11:38:23.505988 [DATLAT]
1241 11:38:23.506380 Freq=800, CH0 RK1
1242 11:38:23.506767
1243 11:38:23.509513 DATLAT Default: 0x9
1244 11:38:23.509983 0, 0xFFFF, sum = 0
1245 11:38:23.513793 1, 0xFFFF, sum = 0
1246 11:38:23.514190 2, 0xFFFF, sum = 0
1247 11:38:23.517136 3, 0xFFFF, sum = 0
1248 11:38:23.517664 4, 0xFFFF, sum = 0
1249 11:38:23.519635 5, 0xFFFF, sum = 0
1250 11:38:23.520035 6, 0xFFFF, sum = 0
1251 11:38:23.523626 7, 0xFFFF, sum = 0
1252 11:38:23.524139 8, 0x0, sum = 1
1253 11:38:23.525935 9, 0x0, sum = 2
1254 11:38:23.526356 10, 0x0, sum = 3
1255 11:38:23.531084 11, 0x0, sum = 4
1256 11:38:23.531562 best_step = 9
1257 11:38:23.531959
1258 11:38:23.532344 ==
1259 11:38:23.533198 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:38:23.539029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1261 11:38:23.539424 ==
1262 11:38:23.539815 RX Vref Scan: 0
1263 11:38:23.540176
1264 11:38:23.542227 RX Vref 0 -> 0, step: 1
1265 11:38:23.542616
1266 11:38:23.546324 RX Delay -111 -> 252, step: 8
1267 11:38:23.549353 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1268 11:38:23.552837 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1269 11:38:23.559360 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1270 11:38:23.562422 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1271 11:38:23.565918 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1272 11:38:23.568817 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1273 11:38:23.573586 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1274 11:38:23.576407 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1275 11:38:23.582478 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1276 11:38:23.586161 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1277 11:38:23.589907 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1278 11:38:23.592407 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1279 11:38:23.595838 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1280 11:38:23.602370 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1281 11:38:23.605829 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1282 11:38:23.609008 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1283 11:38:23.609478 ==
1284 11:38:23.612648 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 11:38:23.616104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1286 11:38:23.616531 ==
1287 11:38:23.619275 DQS Delay:
1288 11:38:23.619696 DQS0 = 0, DQS1 = 0
1289 11:38:23.623047 DQM Delay:
1290 11:38:23.623558 DQM0 = 84, DQM1 = 73
1291 11:38:23.623895 DQ Delay:
1292 11:38:23.625994 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1293 11:38:23.629431 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1294 11:38:23.632920 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1295 11:38:23.636291 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1296 11:38:23.636919
1297 11:38:23.637304
1298 11:38:23.646570 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1299 11:38:23.649737 CH0 RK1: MR19=606, MR18=4C4C
1300 11:38:23.653894 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1301 11:38:23.656321 [RxdqsGatingPostProcess] freq 800
1302 11:38:23.662826 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1303 11:38:23.665729 Pre-setting of DQS Precalculation
1304 11:38:23.669103 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1305 11:38:23.669576 ==
1306 11:38:23.672721 Dram Type= 6, Freq= 0, CH_1, rank 0
1307 11:38:23.679346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1308 11:38:23.679765 ==
1309 11:38:23.682241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1310 11:38:23.688893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1311 11:38:23.698197 [CA 0] Center 36 (6~67) winsize 62
1312 11:38:23.701675 [CA 1] Center 36 (5~67) winsize 63
1313 11:38:23.705355 [CA 2] Center 34 (4~65) winsize 62
1314 11:38:23.708543 [CA 3] Center 34 (4~65) winsize 62
1315 11:38:23.711356 [CA 4] Center 32 (2~63) winsize 62
1316 11:38:23.715040 [CA 5] Center 33 (3~63) winsize 61
1317 11:38:23.715295
1318 11:38:23.718370 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1319 11:38:23.718651
1320 11:38:23.721756 [CATrainingPosCal] consider 1 rank data
1321 11:38:23.725631 u2DelayCellTimex100 = 270/100 ps
1322 11:38:23.728592 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
1323 11:38:23.732479 CA1 delay=36 (5~67),Diff = 4 PI (28 cell)
1324 11:38:23.739922 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
1325 11:38:23.741989 CA3 delay=34 (4~65),Diff = 2 PI (14 cell)
1326 11:38:23.746379 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
1327 11:38:23.748989 CA5 delay=33 (3~63),Diff = 1 PI (7 cell)
1328 11:38:23.749522
1329 11:38:23.752367 CA PerBit enable=1, Macro0, CA PI delay=32
1330 11:38:23.752865
1331 11:38:23.755904 [CBTSetCACLKResult] CA Dly = 32
1332 11:38:23.756399 CS Dly: 4 (0~35)
1333 11:38:23.756724 ==
1334 11:38:23.758649 Dram Type= 6, Freq= 0, CH_1, rank 1
1335 11:38:23.765662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1336 11:38:23.766157 ==
1337 11:38:23.768650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1338 11:38:23.775043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1339 11:38:23.785050 [CA 0] Center 36 (5~67) winsize 63
1340 11:38:23.788328 [CA 1] Center 36 (5~67) winsize 63
1341 11:38:23.791430 [CA 2] Center 34 (3~65) winsize 63
1342 11:38:23.794789 [CA 3] Center 33 (3~64) winsize 62
1343 11:38:23.797742 [CA 4] Center 33 (3~63) winsize 61
1344 11:38:23.801974 [CA 5] Center 33 (3~63) winsize 61
1345 11:38:23.802485
1346 11:38:23.804263 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1347 11:38:23.804682
1348 11:38:23.808704 [CATrainingPosCal] consider 2 rank data
1349 11:38:23.811993 u2DelayCellTimex100 = 270/100 ps
1350 11:38:23.814649 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1351 11:38:23.818788 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1352 11:38:23.824809 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1353 11:38:23.827436 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1354 11:38:23.831594 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1355 11:38:23.834842 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1356 11:38:23.835348
1357 11:38:23.838107 CA PerBit enable=1, Macro0, CA PI delay=33
1358 11:38:23.838533
1359 11:38:23.841214 [CBTSetCACLKResult] CA Dly = 33
1360 11:38:23.841765 CS Dly: 4 (0~36)
1361 11:38:23.842097
1362 11:38:23.845273 ----->DramcWriteLeveling(PI) begin...
1363 11:38:23.848285 ==
1364 11:38:23.848790 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 11:38:23.854745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 11:38:23.855250 ==
1367 11:38:23.857877 Write leveling (Byte 0): 25 => 25
1368 11:38:23.861291 Write leveling (Byte 1): 25 => 25
1369 11:38:23.861807 DramcWriteLeveling(PI) end<-----
1370 11:38:23.864652
1371 11:38:23.865067 ==
1372 11:38:23.868671 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 11:38:23.871013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1374 11:38:23.871447 ==
1375 11:38:23.874668 [Gating] SW mode calibration
1376 11:38:23.881558 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1377 11:38:23.884857 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1378 11:38:23.891185 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1379 11:38:23.895458 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 11:38:23.897414 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 11:38:23.904626 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 11:38:23.907630 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 11:38:23.911337 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1384 11:38:23.917624 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1385 11:38:23.921979 0 6 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
1386 11:38:23.924868 0 7 0 | B1->B0 | 2e2e 4242 | 1 1 | (0 0) (0 0)
1387 11:38:23.932005 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1388 11:38:23.934610 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 11:38:23.937506 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 11:38:23.944206 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 11:38:23.948729 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1392 11:38:23.951244 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1393 11:38:23.957880 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1394 11:38:23.961144 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1395 11:38:23.963888 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:38:23.970676 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:38:23.974738 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:38:23.977774 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:38:23.983038 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:38:23.988881 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:38:23.991868 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:38:23.994217 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 11:38:24.001286 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 11:38:24.004369 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 11:38:24.007332 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 11:38:24.013912 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 11:38:24.017460 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 11:38:24.021076 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 11:38:24.027780 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1410 11:38:24.031270 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1411 11:38:24.033974 Total UI for P1: 0, mck2ui 16
1412 11:38:24.038055 best dqsien dly found for B0: ( 0, 9, 28)
1413 11:38:24.041398 Total UI for P1: 0, mck2ui 16
1414 11:38:24.044579 best dqsien dly found for B1: ( 0, 9, 30)
1415 11:38:24.048736 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1416 11:38:24.051356 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1417 11:38:24.051870
1418 11:38:24.055077 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1419 11:38:24.058083 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1420 11:38:24.060896 [Gating] SW calibration Done
1421 11:38:24.061438 ==
1422 11:38:24.064162 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 11:38:24.067823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 11:38:24.068332 ==
1425 11:38:24.070899 RX Vref Scan: 0
1426 11:38:24.071321
1427 11:38:24.074109 RX Vref 0 -> 0, step: 1
1428 11:38:24.074616
1429 11:38:24.078582 RX Delay -130 -> 252, step: 16
1430 11:38:24.082607 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1431 11:38:24.085058 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1432 11:38:24.089045 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1433 11:38:24.091334 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1434 11:38:24.094659 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1435 11:38:24.101420 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1436 11:38:24.104391 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1437 11:38:24.107286 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1438 11:38:24.111021 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1439 11:38:24.115489 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1440 11:38:24.120669 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1441 11:38:24.124460 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1442 11:38:24.127815 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1443 11:38:24.130666 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1444 11:38:24.137446 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1445 11:38:24.141465 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1446 11:38:24.142083 ==
1447 11:38:24.144060 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:38:24.147451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1449 11:38:24.147959 ==
1450 11:38:24.152262 DQS Delay:
1451 11:38:24.152806 DQS0 = 0, DQS1 = 0
1452 11:38:24.153153 DQM Delay:
1453 11:38:24.154151 DQM0 = 81, DQM1 = 69
1454 11:38:24.154580 DQ Delay:
1455 11:38:24.157856 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1456 11:38:24.161196 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1457 11:38:24.163963 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1458 11:38:24.167687 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1459 11:38:24.168198
1460 11:38:24.168538
1461 11:38:24.168846 ==
1462 11:38:24.170555 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 11:38:24.174285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1464 11:38:24.178148 ==
1465 11:38:24.178652
1466 11:38:24.178978
1467 11:38:24.179276 TX Vref Scan disable
1468 11:38:24.180668 == TX Byte 0 ==
1469 11:38:24.183748 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1470 11:38:24.187711 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1471 11:38:24.190418 == TX Byte 1 ==
1472 11:38:24.195631 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1473 11:38:24.197474 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1474 11:38:24.201287 ==
1475 11:38:24.204456 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 11:38:24.206885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1477 11:38:24.207310 ==
1478 11:38:24.219219 TX Vref=22, minBit 10, minWin=27, winSum=447
1479 11:38:24.222241 TX Vref=24, minBit 0, minWin=28, winSum=450
1480 11:38:24.226000 TX Vref=26, minBit 0, minWin=28, winSum=453
1481 11:38:24.229078 TX Vref=28, minBit 0, minWin=28, winSum=454
1482 11:38:24.232470 TX Vref=30, minBit 2, minWin=28, winSum=456
1483 11:38:24.236275 TX Vref=32, minBit 2, minWin=28, winSum=457
1484 11:38:24.243176 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 32
1485 11:38:24.243640
1486 11:38:24.246344 Final TX Range 1 Vref 32
1487 11:38:24.246724
1488 11:38:24.247015 ==
1489 11:38:24.249633 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 11:38:24.253408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 11:38:24.253866 ==
1492 11:38:24.254165
1493 11:38:24.256809
1494 11:38:24.257315 TX Vref Scan disable
1495 11:38:24.259507 == TX Byte 0 ==
1496 11:38:24.262485 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1497 11:38:24.269458 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1498 11:38:24.269924 == TX Byte 1 ==
1499 11:38:24.272915 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1500 11:38:24.279006 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1501 11:38:24.279455
1502 11:38:24.279752 [DATLAT]
1503 11:38:24.280028 Freq=800, CH1 RK0
1504 11:38:24.280304
1505 11:38:24.282084 DATLAT Default: 0xa
1506 11:38:24.282549 0, 0xFFFF, sum = 0
1507 11:38:24.285834 1, 0xFFFF, sum = 0
1508 11:38:24.286349 2, 0xFFFF, sum = 0
1509 11:38:24.289508 3, 0xFFFF, sum = 0
1510 11:38:24.289977 4, 0xFFFF, sum = 0
1511 11:38:24.292596 5, 0xFFFF, sum = 0
1512 11:38:24.296208 6, 0xFFFF, sum = 0
1513 11:38:24.296682 7, 0xFFFF, sum = 0
1514 11:38:24.296987 8, 0x0, sum = 1
1515 11:38:24.299066 9, 0x0, sum = 2
1516 11:38:24.299536 10, 0x0, sum = 3
1517 11:38:24.302455 11, 0x0, sum = 4
1518 11:38:24.302840 best_step = 9
1519 11:38:24.303136
1520 11:38:24.303407 ==
1521 11:38:24.306526 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 11:38:24.312507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 11:38:24.312928 ==
1524 11:38:24.313261 RX Vref Scan: 1
1525 11:38:24.313555
1526 11:38:24.316280 Set Vref Range= 32 -> 127
1527 11:38:24.316657
1528 11:38:24.319492 RX Vref 32 -> 127, step: 1
1529 11:38:24.319951
1530 11:38:24.323601 RX Delay -111 -> 252, step: 8
1531 11:38:24.324063
1532 11:38:24.325909 Set Vref, RX VrefLevel [Byte0]: 32
1533 11:38:24.328677 [Byte1]: 32
1534 11:38:24.329116
1535 11:38:24.332162 Set Vref, RX VrefLevel [Byte0]: 33
1536 11:38:24.335923 [Byte1]: 33
1537 11:38:24.336301
1538 11:38:24.339765 Set Vref, RX VrefLevel [Byte0]: 34
1539 11:38:24.342024 [Byte1]: 34
1540 11:38:24.345860
1541 11:38:24.346319 Set Vref, RX VrefLevel [Byte0]: 35
1542 11:38:24.348707 [Byte1]: 35
1543 11:38:24.353151
1544 11:38:24.353661 Set Vref, RX VrefLevel [Byte0]: 36
1545 11:38:24.356780 [Byte1]: 36
1546 11:38:24.360612
1547 11:38:24.361077 Set Vref, RX VrefLevel [Byte0]: 37
1548 11:38:24.363914 [Byte1]: 37
1549 11:38:24.368885
1550 11:38:24.369374 Set Vref, RX VrefLevel [Byte0]: 38
1551 11:38:24.371439 [Byte1]: 38
1552 11:38:24.375517
1553 11:38:24.375898 Set Vref, RX VrefLevel [Byte0]: 39
1554 11:38:24.381086 [Byte1]: 39
1555 11:38:24.383916
1556 11:38:24.384375 Set Vref, RX VrefLevel [Byte0]: 40
1557 11:38:24.387141 [Byte1]: 40
1558 11:38:24.391657
1559 11:38:24.392125 Set Vref, RX VrefLevel [Byte0]: 41
1560 11:38:24.394416 [Byte1]: 41
1561 11:38:24.399163
1562 11:38:24.399679 Set Vref, RX VrefLevel [Byte0]: 42
1563 11:38:24.402360 [Byte1]: 42
1564 11:38:24.407126
1565 11:38:24.407633 Set Vref, RX VrefLevel [Byte0]: 43
1566 11:38:24.409915 [Byte1]: 43
1567 11:38:24.414591
1568 11:38:24.415013 Set Vref, RX VrefLevel [Byte0]: 44
1569 11:38:24.417842 [Byte1]: 44
1570 11:38:24.421735
1571 11:38:24.422236 Set Vref, RX VrefLevel [Byte0]: 45
1572 11:38:24.425419 [Byte1]: 45
1573 11:38:24.429973
1574 11:38:24.430482 Set Vref, RX VrefLevel [Byte0]: 46
1575 11:38:24.432563 [Byte1]: 46
1576 11:38:24.437276
1577 11:38:24.437791 Set Vref, RX VrefLevel [Byte0]: 47
1578 11:38:24.441321 [Byte1]: 47
1579 11:38:24.444801
1580 11:38:24.445336 Set Vref, RX VrefLevel [Byte0]: 48
1581 11:38:24.448379 [Byte1]: 48
1582 11:38:24.452930
1583 11:38:24.453470 Set Vref, RX VrefLevel [Byte0]: 49
1584 11:38:24.456309 [Byte1]: 49
1585 11:38:24.460960
1586 11:38:24.461530 Set Vref, RX VrefLevel [Byte0]: 50
1587 11:38:24.464418 [Byte1]: 50
1588 11:38:24.467998
1589 11:38:24.468504 Set Vref, RX VrefLevel [Byte0]: 51
1590 11:38:24.470922 [Byte1]: 51
1591 11:38:24.475891
1592 11:38:24.476351 Set Vref, RX VrefLevel [Byte0]: 52
1593 11:38:24.478998 [Byte1]: 52
1594 11:38:24.483318
1595 11:38:24.483783 Set Vref, RX VrefLevel [Byte0]: 53
1596 11:38:24.486777 [Byte1]: 53
1597 11:38:24.491324
1598 11:38:24.491885 Set Vref, RX VrefLevel [Byte0]: 54
1599 11:38:24.493912 [Byte1]: 54
1600 11:38:24.498176
1601 11:38:24.498554 Set Vref, RX VrefLevel [Byte0]: 55
1602 11:38:24.501690 [Byte1]: 55
1603 11:38:24.505829
1604 11:38:24.506205 Set Vref, RX VrefLevel [Byte0]: 56
1605 11:38:24.509277 [Byte1]: 56
1606 11:38:24.513319
1607 11:38:24.513860 Set Vref, RX VrefLevel [Byte0]: 57
1608 11:38:24.517132 [Byte1]: 57
1609 11:38:24.522067
1610 11:38:24.522456 Set Vref, RX VrefLevel [Byte0]: 58
1611 11:38:24.524509 [Byte1]: 58
1612 11:38:24.528996
1613 11:38:24.529482 Set Vref, RX VrefLevel [Byte0]: 59
1614 11:38:24.532074 [Byte1]: 59
1615 11:38:24.536187
1616 11:38:24.536608 Set Vref, RX VrefLevel [Byte0]: 60
1617 11:38:24.539774 [Byte1]: 60
1618 11:38:24.544433
1619 11:38:24.544874 Set Vref, RX VrefLevel [Byte0]: 61
1620 11:38:24.547508 [Byte1]: 61
1621 11:38:24.552083
1622 11:38:24.552466 Set Vref, RX VrefLevel [Byte0]: 62
1623 11:38:24.555212 [Byte1]: 62
1624 11:38:24.559375
1625 11:38:24.559793 Set Vref, RX VrefLevel [Byte0]: 63
1626 11:38:24.563188 [Byte1]: 63
1627 11:38:24.567560
1628 11:38:24.568049 Set Vref, RX VrefLevel [Byte0]: 64
1629 11:38:24.570544 [Byte1]: 64
1630 11:38:24.575124
1631 11:38:24.575509 Set Vref, RX VrefLevel [Byte0]: 65
1632 11:38:24.578547 [Byte1]: 65
1633 11:38:24.582404
1634 11:38:24.582793 Set Vref, RX VrefLevel [Byte0]: 66
1635 11:38:24.585715 [Byte1]: 66
1636 11:38:24.590456
1637 11:38:24.590920 Set Vref, RX VrefLevel [Byte0]: 67
1638 11:38:24.593354 [Byte1]: 67
1639 11:38:24.597575
1640 11:38:24.598057 Set Vref, RX VrefLevel [Byte0]: 68
1641 11:38:24.600745 [Byte1]: 68
1642 11:38:24.605753
1643 11:38:24.606143 Set Vref, RX VrefLevel [Byte0]: 69
1644 11:38:24.608649 [Byte1]: 69
1645 11:38:24.613283
1646 11:38:24.613810 Set Vref, RX VrefLevel [Byte0]: 70
1647 11:38:24.616693 [Byte1]: 70
1648 11:38:24.620894
1649 11:38:24.621320 Set Vref, RX VrefLevel [Byte0]: 71
1650 11:38:24.623988 [Byte1]: 71
1651 11:38:24.628288
1652 11:38:24.628666 Set Vref, RX VrefLevel [Byte0]: 72
1653 11:38:24.631581 [Byte1]: 72
1654 11:38:24.636015
1655 11:38:24.636473 Set Vref, RX VrefLevel [Byte0]: 73
1656 11:38:24.639968 [Byte1]: 73
1657 11:38:24.643538
1658 11:38:24.643992 Set Vref, RX VrefLevel [Byte0]: 74
1659 11:38:24.646866 [Byte1]: 74
1660 11:38:24.651295
1661 11:38:24.651752 Set Vref, RX VrefLevel [Byte0]: 75
1662 11:38:24.654494 [Byte1]: 75
1663 11:38:24.658808
1664 11:38:24.659262 Set Vref, RX VrefLevel [Byte0]: 76
1665 11:38:24.662253 [Byte1]: 76
1666 11:38:24.666561
1667 11:38:24.666955 Set Vref, RX VrefLevel [Byte0]: 77
1668 11:38:24.669988 [Byte1]: 77
1669 11:38:24.674991
1670 11:38:24.675489 Final RX Vref Byte 0 = 59 to rank0
1671 11:38:24.677880 Final RX Vref Byte 1 = 53 to rank0
1672 11:38:24.681091 Final RX Vref Byte 0 = 59 to rank1
1673 11:38:24.684317 Final RX Vref Byte 1 = 53 to rank1==
1674 11:38:24.687732 Dram Type= 6, Freq= 0, CH_1, rank 0
1675 11:38:24.694072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1676 11:38:24.694509 ==
1677 11:38:24.694840 DQS Delay:
1678 11:38:24.695147 DQS0 = 0, DQS1 = 0
1679 11:38:24.698777 DQM Delay:
1680 11:38:24.699283 DQM0 = 79, DQM1 = 71
1681 11:38:24.701118 DQ Delay:
1682 11:38:24.704456 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1683 11:38:24.704966 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1684 11:38:24.708381 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1685 11:38:24.714195 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1686 11:38:24.714702
1687 11:38:24.715030
1688 11:38:24.721435 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1689 11:38:24.724673 CH1 RK0: MR19=606, MR18=5454
1690 11:38:24.730861 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1691 11:38:24.731353
1692 11:38:24.734036 ----->DramcWriteLeveling(PI) begin...
1693 11:38:24.734511 ==
1694 11:38:24.737158 Dram Type= 6, Freq= 0, CH_1, rank 1
1695 11:38:24.740914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1696 11:38:24.741388 ==
1697 11:38:24.744573 Write leveling (Byte 0): 24 => 24
1698 11:38:24.747317 Write leveling (Byte 1): 23 => 23
1699 11:38:24.750712 DramcWriteLeveling(PI) end<-----
1700 11:38:24.751384
1701 11:38:24.751735 ==
1702 11:38:24.753902 Dram Type= 6, Freq= 0, CH_1, rank 1
1703 11:38:24.757809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1704 11:38:24.758318 ==
1705 11:38:24.761050 [Gating] SW mode calibration
1706 11:38:24.767466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1707 11:38:24.773934 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1708 11:38:24.777037 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1709 11:38:24.780476 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 11:38:24.787564 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 11:38:24.790569 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 11:38:24.794730 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 11:38:24.801439 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 11:38:24.803605 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 11:38:24.807141 0 6 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1716 11:38:24.813883 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1717 11:38:24.816779 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 11:38:24.820555 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 11:38:24.827511 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 11:38:24.830440 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 11:38:24.833906 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 11:38:24.840801 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1723 11:38:24.843774 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1724 11:38:24.846887 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1725 11:38:24.853698 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 11:38:24.856839 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 11:38:24.860521 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 11:38:24.867444 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 11:38:24.870929 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 11:38:24.873635 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 11:38:24.877531 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 11:38:24.883704 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 11:38:24.887539 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 11:38:24.890663 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 11:38:24.897212 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 11:38:24.901107 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 11:38:24.904528 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 11:38:24.911122 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 11:38:24.914145 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1740 11:38:24.916917 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1741 11:38:24.920876 Total UI for P1: 0, mck2ui 16
1742 11:38:24.923771 best dqsien dly found for B0: ( 0, 9, 28)
1743 11:38:24.927572 Total UI for P1: 0, mck2ui 16
1744 11:38:24.930236 best dqsien dly found for B1: ( 0, 9, 30)
1745 11:38:24.934131 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1746 11:38:24.938215 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1747 11:38:24.938719
1748 11:38:24.944050 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1749 11:38:24.947778 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1750 11:38:24.948284 [Gating] SW calibration Done
1751 11:38:24.951744 ==
1752 11:38:24.953769 Dram Type= 6, Freq= 0, CH_1, rank 1
1753 11:38:24.958095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1754 11:38:24.958602 ==
1755 11:38:24.958939 RX Vref Scan: 0
1756 11:38:24.959245
1757 11:38:24.960510 RX Vref 0 -> 0, step: 1
1758 11:38:24.960937
1759 11:38:24.963481 RX Delay -130 -> 252, step: 16
1760 11:38:24.966762 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1761 11:38:24.971045 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1762 11:38:24.977003 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1763 11:38:24.980317 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1764 11:38:24.983627 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1765 11:38:24.988040 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1766 11:38:24.990432 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1767 11:38:24.993695 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1768 11:38:25.000296 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1769 11:38:25.003759 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1770 11:38:25.007438 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1771 11:38:25.010302 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1772 11:38:25.013607 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1773 11:38:25.020129 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1774 11:38:25.024072 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1775 11:38:25.027578 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1776 11:38:25.028082 ==
1777 11:38:25.030373 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 11:38:25.034303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1779 11:38:25.037165 ==
1780 11:38:25.037622 DQS Delay:
1781 11:38:25.037956 DQS0 = 0, DQS1 = 0
1782 11:38:25.040848 DQM Delay:
1783 11:38:25.041393 DQM0 = 80, DQM1 = 71
1784 11:38:25.041767 DQ Delay:
1785 11:38:25.043526 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1786 11:38:25.047552 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1787 11:38:25.050374 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1788 11:38:25.053851 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1789 11:38:25.054094
1790 11:38:25.054255
1791 11:38:25.056939 ==
1792 11:38:25.060775 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 11:38:25.064392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1794 11:38:25.064767 ==
1795 11:38:25.065007
1796 11:38:25.065221
1797 11:38:25.067277 TX Vref Scan disable
1798 11:38:25.067574 == TX Byte 0 ==
1799 11:38:25.070838 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1800 11:38:25.077218 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1801 11:38:25.077793 == TX Byte 1 ==
1802 11:38:25.081069 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1803 11:38:25.087502 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1804 11:38:25.088002 ==
1805 11:38:25.090920 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 11:38:25.093846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 11:38:25.094297 ==
1808 11:38:25.106821 TX Vref=22, minBit 0, minWin=28, winSum=453
1809 11:38:25.110384 TX Vref=24, minBit 0, minWin=28, winSum=454
1810 11:38:25.113601 TX Vref=26, minBit 0, minWin=28, winSum=456
1811 11:38:25.117269 TX Vref=28, minBit 0, minWin=28, winSum=461
1812 11:38:25.121003 TX Vref=30, minBit 0, minWin=28, winSum=461
1813 11:38:25.127229 TX Vref=32, minBit 0, minWin=28, winSum=457
1814 11:38:25.130417 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 28
1815 11:38:25.130927
1816 11:38:25.134206 Final TX Range 1 Vref 28
1817 11:38:25.134708
1818 11:38:25.135039 ==
1819 11:38:25.136754 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 11:38:25.140617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1821 11:38:25.141119 ==
1822 11:38:25.143444
1823 11:38:25.143943
1824 11:38:25.144341 TX Vref Scan disable
1825 11:38:25.147126 == TX Byte 0 ==
1826 11:38:25.150847 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1827 11:38:25.153676 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1828 11:38:25.157155 == TX Byte 1 ==
1829 11:38:25.160561 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1830 11:38:25.163769 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1831 11:38:25.167943
1832 11:38:25.168452 [DATLAT]
1833 11:38:25.168786 Freq=800, CH1 RK1
1834 11:38:25.169088
1835 11:38:25.170280 DATLAT Default: 0x9
1836 11:38:25.170703 0, 0xFFFF, sum = 0
1837 11:38:25.173550 1, 0xFFFF, sum = 0
1838 11:38:25.173981 2, 0xFFFF, sum = 0
1839 11:38:25.177055 3, 0xFFFF, sum = 0
1840 11:38:25.177572 4, 0xFFFF, sum = 0
1841 11:38:25.180380 5, 0xFFFF, sum = 0
1842 11:38:25.180885 6, 0xFFFF, sum = 0
1843 11:38:25.183473 7, 0xFFFF, sum = 0
1844 11:38:25.183905 8, 0x0, sum = 1
1845 11:38:25.186815 9, 0x0, sum = 2
1846 11:38:25.187319 10, 0x0, sum = 3
1847 11:38:25.190073 11, 0x0, sum = 4
1848 11:38:25.190577 best_step = 9
1849 11:38:25.190915
1850 11:38:25.191220 ==
1851 11:38:25.194069 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 11:38:25.200927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1853 11:38:25.201493 ==
1854 11:38:25.201838 RX Vref Scan: 0
1855 11:38:25.202145
1856 11:38:25.203974 RX Vref 0 -> 0, step: 1
1857 11:38:25.204473
1858 11:38:25.207149 RX Delay -111 -> 252, step: 8
1859 11:38:25.210278 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1860 11:38:25.213424 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1861 11:38:25.220201 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1862 11:38:25.223267 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1863 11:38:25.226464 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1864 11:38:25.230234 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1865 11:38:25.233435 iDelay=217, Bit 6, Center 88 (-31 ~ 208) 240
1866 11:38:25.240371 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1867 11:38:25.244199 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1868 11:38:25.247197 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1869 11:38:25.249946 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1870 11:38:25.253690 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1871 11:38:25.260798 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1872 11:38:25.263494 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1873 11:38:25.266536 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1874 11:38:25.270056 iDelay=217, Bit 15, Center 76 (-39 ~ 192) 232
1875 11:38:25.270551 ==
1876 11:38:25.273186 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 11:38:25.276785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 11:38:25.280409 ==
1879 11:38:25.280906 DQS Delay:
1880 11:38:25.281324 DQS0 = 0, DQS1 = 0
1881 11:38:25.283232 DQM Delay:
1882 11:38:25.283653 DQM0 = 82, DQM1 = 71
1883 11:38:25.287337 DQ Delay:
1884 11:38:25.287834 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1885 11:38:25.290210 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =80
1886 11:38:25.294027 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1887 11:38:25.297506 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =76
1888 11:38:25.298007
1889 11:38:25.298340
1890 11:38:25.307054 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1891 11:38:25.310187 CH1 RK1: MR19=606, MR18=4444
1892 11:38:25.317178 CH1_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1893 11:38:25.317719 [RxdqsGatingPostProcess] freq 800
1894 11:38:25.323141 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1895 11:38:25.327849 Pre-setting of DQS Precalculation
1896 11:38:25.330392 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1897 11:38:25.340257 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1898 11:38:25.346465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1899 11:38:25.346955
1900 11:38:25.347314
1901 11:38:25.350528 [Calibration Summary] 1600 Mbps
1902 11:38:25.351032 CH 0, Rank 0
1903 11:38:25.353633 SW Impedance : PASS
1904 11:38:25.354127 DUTY Scan : NO K
1905 11:38:25.356949 ZQ Calibration : PASS
1906 11:38:25.360228 Jitter Meter : NO K
1907 11:38:25.360723 CBT Training : PASS
1908 11:38:25.363494 Write leveling : PASS
1909 11:38:25.367068 RX DQS gating : PASS
1910 11:38:25.367496 RX DQ/DQS(RDDQC) : PASS
1911 11:38:25.369841 TX DQ/DQS : PASS
1912 11:38:25.374231 RX DATLAT : PASS
1913 11:38:25.374658 RX DQ/DQS(Engine): PASS
1914 11:38:25.376963 TX OE : NO K
1915 11:38:25.377434 All Pass.
1916 11:38:25.377768
1917 11:38:25.379825 CH 0, Rank 1
1918 11:38:25.380247 SW Impedance : PASS
1919 11:38:25.383193 DUTY Scan : NO K
1920 11:38:25.383617 ZQ Calibration : PASS
1921 11:38:25.387293 Jitter Meter : NO K
1922 11:38:25.390041 CBT Training : PASS
1923 11:38:25.390463 Write leveling : PASS
1924 11:38:25.394087 RX DQS gating : PASS
1925 11:38:25.396967 RX DQ/DQS(RDDQC) : PASS
1926 11:38:25.397438 TX DQ/DQS : PASS
1927 11:38:25.401008 RX DATLAT : PASS
1928 11:38:25.403647 RX DQ/DQS(Engine): PASS
1929 11:38:25.404095 TX OE : NO K
1930 11:38:25.407816 All Pass.
1931 11:38:25.408316
1932 11:38:25.408826 CH 1, Rank 0
1933 11:38:25.410626 SW Impedance : PASS
1934 11:38:25.411048 DUTY Scan : NO K
1935 11:38:25.413445 ZQ Calibration : PASS
1936 11:38:25.417842 Jitter Meter : NO K
1937 11:38:25.418350 CBT Training : PASS
1938 11:38:25.419923 Write leveling : PASS
1939 11:38:25.423665 RX DQS gating : PASS
1940 11:38:25.424081 RX DQ/DQS(RDDQC) : PASS
1941 11:38:25.426993 TX DQ/DQS : PASS
1942 11:38:25.427497 RX DATLAT : PASS
1943 11:38:25.429954 RX DQ/DQS(Engine): PASS
1944 11:38:25.433442 TX OE : NO K
1945 11:38:25.433940 All Pass.
1946 11:38:25.434300
1947 11:38:25.434607 CH 1, Rank 1
1948 11:38:25.436628 SW Impedance : PASS
1949 11:38:25.440886 DUTY Scan : NO K
1950 11:38:25.441365 ZQ Calibration : PASS
1951 11:38:25.443734 Jitter Meter : NO K
1952 11:38:25.446907 CBT Training : PASS
1953 11:38:25.447335 Write leveling : PASS
1954 11:38:25.450352 RX DQS gating : PASS
1955 11:38:25.453447 RX DQ/DQS(RDDQC) : PASS
1956 11:38:25.453944 TX DQ/DQS : PASS
1957 11:38:25.456477 RX DATLAT : PASS
1958 11:38:25.460304 RX DQ/DQS(Engine): PASS
1959 11:38:25.460802 TX OE : NO K
1960 11:38:25.461141 All Pass.
1961 11:38:25.464040
1962 11:38:25.464534 DramC Write-DBI off
1963 11:38:25.467274 PER_BANK_REFRESH: Hybrid Mode
1964 11:38:25.467705 TX_TRACKING: ON
1965 11:38:25.469948 [GetDramInforAfterCalByMRR] Vendor 6.
1966 11:38:25.473409 [GetDramInforAfterCalByMRR] Revision 606.
1967 11:38:25.480437 [GetDramInforAfterCalByMRR] Revision 2 0.
1968 11:38:25.480937 MR0 0x3939
1969 11:38:25.481328 MR8 0x1111
1970 11:38:25.483774 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1971 11:38:25.484275
1972 11:38:25.487059 MR0 0x3939
1973 11:38:25.487560 MR8 0x1111
1974 11:38:25.490106 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1975 11:38:25.490612
1976 11:38:25.500171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1977 11:38:25.503399 [FAST_K] Save calibration result to emmc
1978 11:38:25.506488 [FAST_K] Save calibration result to emmc
1979 11:38:25.510172 dram_init: config_dvfs: 1
1980 11:38:25.512986 dramc_set_vcore_voltage set vcore to 662500
1981 11:38:25.516870 Read voltage for 1200, 2
1982 11:38:25.517335 Vio18 = 0
1983 11:38:25.517678 Vcore = 662500
1984 11:38:25.519441 Vdram = 0
1985 11:38:25.519880 Vddq = 0
1986 11:38:25.520211 Vmddr = 0
1987 11:38:25.526370 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1988 11:38:25.530050 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1989 11:38:25.532943 MEM_TYPE=3, freq_sel=15
1990 11:38:25.536554 sv_algorithm_assistance_LP4_1600
1991 11:38:25.539880 ============ PULL DRAM RESETB DOWN ============
1992 11:38:25.543187 ========== PULL DRAM RESETB DOWN end =========
1993 11:38:25.550238 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1994 11:38:25.553129 ===================================
1995 11:38:25.553831 LPDDR4 DRAM CONFIGURATION
1996 11:38:25.556627 ===================================
1997 11:38:25.559739 EX_ROW_EN[0] = 0x0
1998 11:38:25.563350 EX_ROW_EN[1] = 0x0
1999 11:38:25.563797 LP4Y_EN = 0x0
2000 11:38:25.566352 WORK_FSP = 0x0
2001 11:38:25.566774 WL = 0x4
2002 11:38:25.570228 RL = 0x4
2003 11:38:25.570843 BL = 0x2
2004 11:38:25.572731 RPST = 0x0
2005 11:38:25.573157 RD_PRE = 0x0
2006 11:38:25.575995 WR_PRE = 0x1
2007 11:38:25.576418 WR_PST = 0x0
2008 11:38:25.580531 DBI_WR = 0x0
2009 11:38:25.581029 DBI_RD = 0x0
2010 11:38:25.583605 OTF = 0x1
2011 11:38:25.586550 ===================================
2012 11:38:25.589799 ===================================
2013 11:38:25.590301 ANA top config
2014 11:38:25.593371 ===================================
2015 11:38:25.596305 DLL_ASYNC_EN = 0
2016 11:38:25.599485 ALL_SLAVE_EN = 0
2017 11:38:25.599908 NEW_RANK_MODE = 1
2018 11:38:25.603332 DLL_IDLE_MODE = 1
2019 11:38:25.606970 LP45_APHY_COMB_EN = 1
2020 11:38:25.610165 TX_ODT_DIS = 1
2021 11:38:25.613330 NEW_8X_MODE = 1
2022 11:38:25.616137 ===================================
2023 11:38:25.620235 ===================================
2024 11:38:25.620655 data_rate = 2400
2025 11:38:25.623337 CKR = 1
2026 11:38:25.627224 DQ_P2S_RATIO = 8
2027 11:38:25.629870 ===================================
2028 11:38:25.632972 CA_P2S_RATIO = 8
2029 11:38:25.636778 DQ_CA_OPEN = 0
2030 11:38:25.639735 DQ_SEMI_OPEN = 0
2031 11:38:25.640185 CA_SEMI_OPEN = 0
2032 11:38:25.643381 CA_FULL_RATE = 0
2033 11:38:25.646488 DQ_CKDIV4_EN = 0
2034 11:38:25.649705 CA_CKDIV4_EN = 0
2035 11:38:25.653340 CA_PREDIV_EN = 0
2036 11:38:25.656628 PH8_DLY = 17
2037 11:38:25.657144 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2038 11:38:25.660050 DQ_AAMCK_DIV = 4
2039 11:38:25.663382 CA_AAMCK_DIV = 4
2040 11:38:25.666533 CA_ADMCK_DIV = 4
2041 11:38:25.669874 DQ_TRACK_CA_EN = 0
2042 11:38:25.672829 CA_PICK = 1200
2043 11:38:25.673342 CA_MCKIO = 1200
2044 11:38:25.676459 MCKIO_SEMI = 0
2045 11:38:25.679664 PLL_FREQ = 2366
2046 11:38:25.684155 DQ_UI_PI_RATIO = 32
2047 11:38:25.686573 CA_UI_PI_RATIO = 0
2048 11:38:25.689715 ===================================
2049 11:38:25.692811 ===================================
2050 11:38:25.696341 memory_type:LPDDR4
2051 11:38:25.696720 GP_NUM : 10
2052 11:38:25.700019 SRAM_EN : 1
2053 11:38:25.700501 MD32_EN : 0
2054 11:38:25.703643 ===================================
2055 11:38:25.706751 [ANA_INIT] >>>>>>>>>>>>>>
2056 11:38:25.709612 <<<<<< [CONFIGURE PHASE]: ANA_TX
2057 11:38:25.713304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2058 11:38:25.716089 ===================================
2059 11:38:25.719418 data_rate = 2400,PCW = 0X5b00
2060 11:38:25.723352 ===================================
2061 11:38:25.726386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2062 11:38:25.730366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2063 11:38:25.736006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2064 11:38:25.742790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2065 11:38:25.746143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2066 11:38:25.749600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2067 11:38:25.749983 [ANA_INIT] flow start
2068 11:38:25.752904 [ANA_INIT] PLL >>>>>>>>
2069 11:38:25.756585 [ANA_INIT] PLL <<<<<<<<
2070 11:38:25.756962 [ANA_INIT] MIDPI >>>>>>>>
2071 11:38:25.759152 [ANA_INIT] MIDPI <<<<<<<<
2072 11:38:25.762621 [ANA_INIT] DLL >>>>>>>>
2073 11:38:25.763114 [ANA_INIT] DLL <<<<<<<<
2074 11:38:25.766288 [ANA_INIT] flow end
2075 11:38:25.770339 ============ LP4 DIFF to SE enter ============
2076 11:38:25.772901 ============ LP4 DIFF to SE exit ============
2077 11:38:25.776104 [ANA_INIT] <<<<<<<<<<<<<
2078 11:38:25.780238 [Flow] Enable top DCM control >>>>>
2079 11:38:25.782542 [Flow] Enable top DCM control <<<<<
2080 11:38:25.786519 Enable DLL master slave shuffle
2081 11:38:25.793143 ==============================================================
2082 11:38:25.793887 Gating Mode config
2083 11:38:25.799224 ==============================================================
2084 11:38:25.799632 Config description:
2085 11:38:25.809187 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2086 11:38:25.816196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2087 11:38:25.822879 SELPH_MODE 0: By rank 1: By Phase
2088 11:38:25.825806 ==============================================================
2089 11:38:25.829416 GAT_TRACK_EN = 1
2090 11:38:25.832364 RX_GATING_MODE = 2
2091 11:38:25.836330 RX_GATING_TRACK_MODE = 2
2092 11:38:25.839553 SELPH_MODE = 1
2093 11:38:25.842981 PICG_EARLY_EN = 1
2094 11:38:25.846313 VALID_LAT_VALUE = 1
2095 11:38:25.852610 ==============================================================
2096 11:38:25.856559 Enter into Gating configuration >>>>
2097 11:38:25.860202 Exit from Gating configuration <<<<
2098 11:38:25.860711 Enter into DVFS_PRE_config >>>>>
2099 11:38:25.872663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2100 11:38:25.876539 Exit from DVFS_PRE_config <<<<<
2101 11:38:25.879354 Enter into PICG configuration >>>>
2102 11:38:25.882745 Exit from PICG configuration <<<<
2103 11:38:25.883238 [RX_INPUT] configuration >>>>>
2104 11:38:25.886536 [RX_INPUT] configuration <<<<<
2105 11:38:25.893060 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2106 11:38:25.896349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2107 11:38:25.902559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2108 11:38:25.909503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2109 11:38:25.916033 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2110 11:38:25.922694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2111 11:38:25.926080 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2112 11:38:25.929485 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2113 11:38:25.932974 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2114 11:38:25.940507 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2115 11:38:25.943295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2116 11:38:25.945932 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 11:38:25.949221 ===================================
2118 11:38:25.953408 LPDDR4 DRAM CONFIGURATION
2119 11:38:25.955966 ===================================
2120 11:38:25.959566 EX_ROW_EN[0] = 0x0
2121 11:38:25.959994 EX_ROW_EN[1] = 0x0
2122 11:38:25.962989 LP4Y_EN = 0x0
2123 11:38:25.963489 WORK_FSP = 0x0
2124 11:38:25.965842 WL = 0x4
2125 11:38:25.966358 RL = 0x4
2126 11:38:25.968932 BL = 0x2
2127 11:38:25.969402 RPST = 0x0
2128 11:38:25.972791 RD_PRE = 0x0
2129 11:38:25.973211 WR_PRE = 0x1
2130 11:38:25.975692 WR_PST = 0x0
2131 11:38:25.976107 DBI_WR = 0x0
2132 11:38:25.979199 DBI_RD = 0x0
2133 11:38:25.979622 OTF = 0x1
2134 11:38:25.982471 ===================================
2135 11:38:25.989289 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2136 11:38:25.992963 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2137 11:38:25.996056 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 11:38:25.999161 ===================================
2139 11:38:26.002823 LPDDR4 DRAM CONFIGURATION
2140 11:38:26.005864 ===================================
2141 11:38:26.009121 EX_ROW_EN[0] = 0x10
2142 11:38:26.009688 EX_ROW_EN[1] = 0x0
2143 11:38:26.013478 LP4Y_EN = 0x0
2144 11:38:26.013974 WORK_FSP = 0x0
2145 11:38:26.015662 WL = 0x4
2146 11:38:26.016083 RL = 0x4
2147 11:38:26.019040 BL = 0x2
2148 11:38:26.019463 RPST = 0x0
2149 11:38:26.022945 RD_PRE = 0x0
2150 11:38:26.023369 WR_PRE = 0x1
2151 11:38:26.026865 WR_PST = 0x0
2152 11:38:26.027367 DBI_WR = 0x0
2153 11:38:26.029259 DBI_RD = 0x0
2154 11:38:26.029689 OTF = 0x1
2155 11:38:26.032565 ===================================
2156 11:38:26.039558 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2157 11:38:26.040051 ==
2158 11:38:26.042947 Dram Type= 6, Freq= 0, CH_0, rank 0
2159 11:38:26.046434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2160 11:38:26.046955 ==
2161 11:38:26.048930 [Duty_Offset_Calibration]
2162 11:38:26.052731 B0:0 B1:2 CA:1
2163 11:38:26.053264
2164 11:38:26.056827 [DutyScan_Calibration_Flow] k_type=0
2165 11:38:26.064814
2166 11:38:26.065363 ==CLK 0==
2167 11:38:26.067862 Final CLK duty delay cell = 0
2168 11:38:26.071029 [0] MAX Duty = 5093%(X100), DQS PI = 12
2169 11:38:26.073930 [0] MIN Duty = 4938%(X100), DQS PI = 54
2170 11:38:26.074448 [0] AVG Duty = 5015%(X100)
2171 11:38:26.077195
2172 11:38:26.080932 CH0 CLK Duty spec in!! Max-Min= 155%
2173 11:38:26.084506 [DutyScan_Calibration_Flow] ====Done====
2174 11:38:26.084947
2175 11:38:26.088234 [DutyScan_Calibration_Flow] k_type=1
2176 11:38:26.103542
2177 11:38:26.104040 ==DQS 0 ==
2178 11:38:26.107294 Final DQS duty delay cell = 0
2179 11:38:26.110160 [0] MAX Duty = 5125%(X100), DQS PI = 32
2180 11:38:26.113215 [0] MIN Duty = 5031%(X100), DQS PI = 4
2181 11:38:26.113773 [0] AVG Duty = 5078%(X100)
2182 11:38:26.118349
2183 11:38:26.118845 ==DQS 1 ==
2184 11:38:26.120013 Final DQS duty delay cell = 0
2185 11:38:26.123187 [0] MAX Duty = 5031%(X100), DQS PI = 54
2186 11:38:26.126846 [0] MIN Duty = 4906%(X100), DQS PI = 16
2187 11:38:26.127344 [0] AVG Duty = 4968%(X100)
2188 11:38:26.130460
2189 11:38:26.133426 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2190 11:38:26.133857
2191 11:38:26.136679 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2192 11:38:26.140661 [DutyScan_Calibration_Flow] ====Done====
2193 11:38:26.141183
2194 11:38:26.143574 [DutyScan_Calibration_Flow] k_type=3
2195 11:38:26.160530
2196 11:38:26.161030 ==DQM 0 ==
2197 11:38:26.163589 Final DQM duty delay cell = 0
2198 11:38:26.167160 [0] MAX Duty = 5156%(X100), DQS PI = 20
2199 11:38:26.170259 [0] MIN Duty = 4969%(X100), DQS PI = 42
2200 11:38:26.174235 [0] AVG Duty = 5062%(X100)
2201 11:38:26.174731
2202 11:38:26.175059 ==DQM 1 ==
2203 11:38:26.177007 Final DQM duty delay cell = 4
2204 11:38:26.180463 [4] MAX Duty = 5187%(X100), DQS PI = 56
2205 11:38:26.184318 [4] MIN Duty = 5000%(X100), DQS PI = 18
2206 11:38:26.188141 [4] AVG Duty = 5093%(X100)
2207 11:38:26.188646
2208 11:38:26.191328 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2209 11:38:26.191825
2210 11:38:26.193680 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2211 11:38:26.197021 [DutyScan_Calibration_Flow] ====Done====
2212 11:38:26.197478
2213 11:38:26.201672 [DutyScan_Calibration_Flow] k_type=2
2214 11:38:26.216513
2215 11:38:26.217011 ==DQ 0 ==
2216 11:38:26.218913 Final DQ duty delay cell = -4
2217 11:38:26.222385 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2218 11:38:26.225908 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2219 11:38:26.229480 [-4] AVG Duty = 4937%(X100)
2220 11:38:26.229975
2221 11:38:26.230311 ==DQ 1 ==
2222 11:38:26.233028 Final DQ duty delay cell = -4
2223 11:38:26.235674 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2224 11:38:26.239543 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2225 11:38:26.242412 [-4] AVG Duty = 4984%(X100)
2226 11:38:26.242913
2227 11:38:26.245813 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2228 11:38:26.246312
2229 11:38:26.249001 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2230 11:38:26.251800 [DutyScan_Calibration_Flow] ====Done====
2231 11:38:26.252223 ==
2232 11:38:26.255348 Dram Type= 6, Freq= 0, CH_1, rank 0
2233 11:38:26.259123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2234 11:38:26.259629 ==
2235 11:38:26.261913 [Duty_Offset_Calibration]
2236 11:38:26.262337 B0:0 B1:4 CA:-5
2237 11:38:26.262665
2238 11:38:26.266202 [DutyScan_Calibration_Flow] k_type=0
2239 11:38:26.276079
2240 11:38:26.276570 ==CLK 0==
2241 11:38:26.279568 Final CLK duty delay cell = 0
2242 11:38:26.282795 [0] MAX Duty = 5094%(X100), DQS PI = 24
2243 11:38:26.286103 [0] MIN Duty = 4876%(X100), DQS PI = 52
2244 11:38:26.286604 [0] AVG Duty = 4985%(X100)
2245 11:38:26.289895
2246 11:38:26.292990 CH1 CLK Duty spec in!! Max-Min= 218%
2247 11:38:26.296574 [DutyScan_Calibration_Flow] ====Done====
2248 11:38:26.296997
2249 11:38:26.300269 [DutyScan_Calibration_Flow] k_type=1
2250 11:38:26.315269
2251 11:38:26.315762 ==DQS 0 ==
2252 11:38:26.318062 Final DQS duty delay cell = 0
2253 11:38:26.321400 [0] MAX Duty = 5125%(X100), DQS PI = 16
2254 11:38:26.324537 [0] MIN Duty = 4875%(X100), DQS PI = 40
2255 11:38:26.324965 [0] AVG Duty = 5000%(X100)
2256 11:38:26.328310
2257 11:38:26.328800 ==DQS 1 ==
2258 11:38:26.331990 Final DQS duty delay cell = -4
2259 11:38:26.334491 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2260 11:38:26.338393 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2261 11:38:26.341894 [-4] AVG Duty = 4953%(X100)
2262 11:38:26.342471
2263 11:38:26.345055 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2264 11:38:26.345599
2265 11:38:26.347903 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2266 11:38:26.351705 [DutyScan_Calibration_Flow] ====Done====
2267 11:38:26.352131
2268 11:38:26.354519 [DutyScan_Calibration_Flow] k_type=3
2269 11:38:26.369861
2270 11:38:26.370357 ==DQM 0 ==
2271 11:38:26.372937 Final DQM duty delay cell = -4
2272 11:38:26.377195 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2273 11:38:26.380074 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2274 11:38:26.383184 [-4] AVG Duty = 4984%(X100)
2275 11:38:26.383607
2276 11:38:26.383938 ==DQM 1 ==
2277 11:38:26.386414 Final DQM duty delay cell = -4
2278 11:38:26.389958 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2279 11:38:26.393334 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2280 11:38:26.396401 [-4] AVG Duty = 4984%(X100)
2281 11:38:26.396825
2282 11:38:26.400757 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2283 11:38:26.401317
2284 11:38:26.403434 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2285 11:38:26.406932 [DutyScan_Calibration_Flow] ====Done====
2286 11:38:26.407360
2287 11:38:26.409804 [DutyScan_Calibration_Flow] k_type=2
2288 11:38:26.427167
2289 11:38:26.427663 ==DQ 0 ==
2290 11:38:26.430024 Final DQ duty delay cell = 0
2291 11:38:26.433690 [0] MAX Duty = 5062%(X100), DQS PI = 0
2292 11:38:26.437753 [0] MIN Duty = 4938%(X100), DQS PI = 44
2293 11:38:26.438251 [0] AVG Duty = 5000%(X100)
2294 11:38:26.438580
2295 11:38:26.440713 ==DQ 1 ==
2296 11:38:26.443505 Final DQ duty delay cell = 0
2297 11:38:26.447229 [0] MAX Duty = 5031%(X100), DQS PI = 6
2298 11:38:26.450328 [0] MIN Duty = 4875%(X100), DQS PI = 18
2299 11:38:26.450831 [0] AVG Duty = 4953%(X100)
2300 11:38:26.451242
2301 11:38:26.453276 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2302 11:38:26.453707
2303 11:38:26.459742 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2304 11:38:26.463198 [DutyScan_Calibration_Flow] ====Done====
2305 11:38:26.467237 nWR fixed to 30
2306 11:38:26.467658 [ModeRegInit_LP4] CH0 RK0
2307 11:38:26.470385 [ModeRegInit_LP4] CH0 RK1
2308 11:38:26.473191 [ModeRegInit_LP4] CH1 RK0
2309 11:38:26.473653 [ModeRegInit_LP4] CH1 RK1
2310 11:38:26.476901 match AC timing 6
2311 11:38:26.480444 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2312 11:38:26.483485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2313 11:38:26.490320 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2314 11:38:26.493902 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2315 11:38:26.500568 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2316 11:38:26.501029 ==
2317 11:38:26.507356 Dram Type= 6, Freq= 0, CH_0, rank 0
2318 11:38:26.507829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2319 11:38:26.508134 ==
2320 11:38:26.514166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2321 11:38:26.516840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2322 11:38:26.526315 [CA 0] Center 39 (9~70) winsize 62
2323 11:38:26.530672 [CA 1] Center 39 (8~70) winsize 63
2324 11:38:26.533156 [CA 2] Center 36 (5~67) winsize 63
2325 11:38:26.537093 [CA 3] Center 35 (4~66) winsize 63
2326 11:38:26.540049 [CA 4] Center 34 (3~65) winsize 63
2327 11:38:26.543654 [CA 5] Center 33 (3~64) winsize 62
2328 11:38:26.544076
2329 11:38:26.546740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2330 11:38:26.547238
2331 11:38:26.550206 [CATrainingPosCal] consider 1 rank data
2332 11:38:26.553339 u2DelayCellTimex100 = 270/100 ps
2333 11:38:26.556584 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2334 11:38:26.559462 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2335 11:38:26.566639 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2336 11:38:26.569535 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2337 11:38:26.572993 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2338 11:38:26.576717 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2339 11:38:26.577211
2340 11:38:26.579852 CA PerBit enable=1, Macro0, CA PI delay=33
2341 11:38:26.580277
2342 11:38:26.582633 [CBTSetCACLKResult] CA Dly = 33
2343 11:38:26.583071 CS Dly: 7 (0~38)
2344 11:38:26.586302 ==
2345 11:38:26.589630 Dram Type= 6, Freq= 0, CH_0, rank 1
2346 11:38:26.592806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2347 11:38:26.593353 ==
2348 11:38:26.596612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2349 11:38:26.602450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2350 11:38:26.612266 [CA 0] Center 39 (8~70) winsize 63
2351 11:38:26.616123 [CA 1] Center 39 (8~70) winsize 63
2352 11:38:26.619406 [CA 2] Center 36 (5~67) winsize 63
2353 11:38:26.621623 [CA 3] Center 35 (4~66) winsize 63
2354 11:38:26.624977 [CA 4] Center 33 (3~64) winsize 62
2355 11:38:26.628143 [CA 5] Center 34 (3~65) winsize 63
2356 11:38:26.628568
2357 11:38:26.632246 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2358 11:38:26.632744
2359 11:38:26.634903 [CATrainingPosCal] consider 2 rank data
2360 11:38:26.638783 u2DelayCellTimex100 = 270/100 ps
2361 11:38:26.642197 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2362 11:38:26.645051 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2363 11:38:26.651758 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2364 11:38:26.655638 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2365 11:38:26.658875 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2366 11:38:26.662109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2367 11:38:26.662601
2368 11:38:26.665197 CA PerBit enable=1, Macro0, CA PI delay=33
2369 11:38:26.665647
2370 11:38:26.668474 [CBTSetCACLKResult] CA Dly = 33
2371 11:38:26.668895 CS Dly: 7 (0~39)
2372 11:38:26.669222
2373 11:38:26.672340 ----->DramcWriteLeveling(PI) begin...
2374 11:38:26.675521 ==
2375 11:38:26.678922 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 11:38:26.681723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 11:38:26.682220 ==
2378 11:38:26.685743 Write leveling (Byte 0): 28 => 28
2379 11:38:26.688273 Write leveling (Byte 1): 28 => 28
2380 11:38:26.692198 DramcWriteLeveling(PI) end<-----
2381 11:38:26.692717
2382 11:38:26.693046 ==
2383 11:38:26.694895 Dram Type= 6, Freq= 0, CH_0, rank 0
2384 11:38:26.698339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2385 11:38:26.698789 ==
2386 11:38:26.701984 [Gating] SW mode calibration
2387 11:38:26.708215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2388 11:38:26.715053 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2389 11:38:26.718361 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 11:38:26.721743 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 11:38:26.728522 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 11:38:26.731614 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2393 11:38:26.734997 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2394 11:38:26.741221 0 11 20 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
2395 11:38:26.744594 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2396 11:38:26.748298 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 11:38:26.751758 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 11:38:26.758077 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 11:38:26.761385 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 11:38:26.764649 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 11:38:26.771455 0 12 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2402 11:38:26.775289 0 12 20 | B1->B0 | 3e3e 4444 | 1 0 | (0 0) (0 0)
2403 11:38:26.777757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 11:38:26.784709 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 11:38:26.788087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 11:38:26.792459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 11:38:26.798252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 11:38:26.801387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 11:38:26.804917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 11:38:26.811698 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2411 11:38:26.814567 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 11:38:26.817911 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 11:38:26.825739 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 11:38:26.827863 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 11:38:26.831452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 11:38:26.838007 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 11:38:26.841328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 11:38:26.844801 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 11:38:26.849080 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 11:38:26.854371 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 11:38:26.857919 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 11:38:26.862250 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 11:38:26.868074 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 11:38:26.871237 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 11:38:26.874496 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2426 11:38:26.881094 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2427 11:38:26.884711 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2428 11:38:26.887687 Total UI for P1: 0, mck2ui 16
2429 11:38:26.891456 best dqsien dly found for B0: ( 0, 15, 20)
2430 11:38:26.895210 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2431 11:38:26.898840 Total UI for P1: 0, mck2ui 16
2432 11:38:26.901135 best dqsien dly found for B1: ( 0, 15, 20)
2433 11:38:26.904436 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2434 11:38:26.907776 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2435 11:38:26.911582
2436 11:38:26.914433 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2437 11:38:26.917533 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2438 11:38:26.921090 [Gating] SW calibration Done
2439 11:38:26.921570 ==
2440 11:38:26.924485 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 11:38:26.927736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2442 11:38:26.928123 ==
2443 11:38:26.928421 RX Vref Scan: 0
2444 11:38:26.928697
2445 11:38:26.931152 RX Vref 0 -> 0, step: 1
2446 11:38:26.931535
2447 11:38:26.935317 RX Delay -40 -> 252, step: 8
2448 11:38:26.938051 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2449 11:38:26.941075 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2450 11:38:26.947709 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2451 11:38:26.951442 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2452 11:38:26.954443 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2453 11:38:26.957574 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2454 11:38:26.961107 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2455 11:38:26.967517 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2456 11:38:26.970961 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2457 11:38:26.974178 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2458 11:38:26.977928 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2459 11:38:26.981218 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2460 11:38:26.987601 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2461 11:38:26.991264 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2462 11:38:26.995195 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2463 11:38:26.997641 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2464 11:38:26.998123 ==
2465 11:38:27.000897 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 11:38:27.006262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 11:38:27.008062 ==
2468 11:38:27.008487 DQS Delay:
2469 11:38:27.008813 DQS0 = 0, DQS1 = 0
2470 11:38:27.010853 DQM Delay:
2471 11:38:27.011278 DQM0 = 115, DQM1 = 106
2472 11:38:27.014893 DQ Delay:
2473 11:38:27.017875 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2474 11:38:27.021600 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2475 11:38:27.024287 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2476 11:38:27.027859 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2477 11:38:27.028308
2478 11:38:27.028645
2479 11:38:27.028952 ==
2480 11:38:27.030849 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 11:38:27.034466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2482 11:38:27.034899 ==
2483 11:38:27.035245
2484 11:38:27.035550
2485 11:38:27.037515 TX Vref Scan disable
2486 11:38:27.042020 == TX Byte 0 ==
2487 11:38:27.044821 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2488 11:38:27.047910 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2489 11:38:27.051205 == TX Byte 1 ==
2490 11:38:27.054679 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2491 11:38:27.057794 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2492 11:38:27.058217 ==
2493 11:38:27.061305 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 11:38:27.064900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2495 11:38:27.067816 ==
2496 11:38:27.077312 TX Vref=22, minBit 8, minWin=25, winSum=422
2497 11:38:27.081497 TX Vref=24, minBit 7, minWin=26, winSum=428
2498 11:38:27.084358 TX Vref=26, minBit 8, minWin=26, winSum=433
2499 11:38:27.087408 TX Vref=28, minBit 9, minWin=26, winSum=439
2500 11:38:27.091188 TX Vref=30, minBit 1, minWin=27, winSum=443
2501 11:38:27.097764 TX Vref=32, minBit 13, minWin=26, winSum=438
2502 11:38:27.100933 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
2503 11:38:27.101414
2504 11:38:27.104797 Final TX Range 1 Vref 30
2505 11:38:27.105220
2506 11:38:27.105591 ==
2507 11:38:27.107709 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 11:38:27.111333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2509 11:38:27.111760 ==
2510 11:38:27.114447
2511 11:38:27.114864
2512 11:38:27.115189 TX Vref Scan disable
2513 11:38:27.117834 == TX Byte 0 ==
2514 11:38:27.121730 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2515 11:38:27.124536 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2516 11:38:27.127713 == TX Byte 1 ==
2517 11:38:27.131626 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2518 11:38:27.134291 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2519 11:38:27.134719
2520 11:38:27.137391 [DATLAT]
2521 11:38:27.137776 Freq=1200, CH0 RK0
2522 11:38:27.138075
2523 11:38:27.141630 DATLAT Default: 0xd
2524 11:38:27.142096 0, 0xFFFF, sum = 0
2525 11:38:27.145308 1, 0xFFFF, sum = 0
2526 11:38:27.145784 2, 0xFFFF, sum = 0
2527 11:38:27.147331 3, 0xFFFF, sum = 0
2528 11:38:27.147719 4, 0xFFFF, sum = 0
2529 11:38:27.150933 5, 0xFFFF, sum = 0
2530 11:38:27.151563 6, 0xFFFF, sum = 0
2531 11:38:27.154034 7, 0xFFFF, sum = 0
2532 11:38:27.158034 8, 0xFFFF, sum = 0
2533 11:38:27.158509 9, 0xFFFF, sum = 0
2534 11:38:27.161148 10, 0xFFFF, sum = 0
2535 11:38:27.161652 11, 0x0, sum = 1
2536 11:38:27.161964 12, 0x0, sum = 2
2537 11:38:27.164649 13, 0x0, sum = 3
2538 11:38:27.165118 14, 0x0, sum = 4
2539 11:38:27.167475 best_step = 12
2540 11:38:27.167857
2541 11:38:27.168157 ==
2542 11:38:27.170973 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 11:38:27.174629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 11:38:27.175094 ==
2545 11:38:27.177802 RX Vref Scan: 1
2546 11:38:27.178185
2547 11:38:27.178589 Set Vref Range= 32 -> 127
2548 11:38:27.181939
2549 11:38:27.182405 RX Vref 32 -> 127, step: 1
2550 11:38:27.182707
2551 11:38:27.184529 RX Delay -21 -> 252, step: 4
2552 11:38:27.184994
2553 11:38:27.187578 Set Vref, RX VrefLevel [Byte0]: 32
2554 11:38:27.191634 [Byte1]: 32
2555 11:38:27.193990
2556 11:38:27.194375 Set Vref, RX VrefLevel [Byte0]: 33
2557 11:38:27.197937 [Byte1]: 33
2558 11:38:27.203236
2559 11:38:27.203705 Set Vref, RX VrefLevel [Byte0]: 34
2560 11:38:27.205442 [Byte1]: 34
2561 11:38:27.210125
2562 11:38:27.210592 Set Vref, RX VrefLevel [Byte0]: 35
2563 11:38:27.213073 [Byte1]: 35
2564 11:38:27.218317
2565 11:38:27.218783 Set Vref, RX VrefLevel [Byte0]: 36
2566 11:38:27.221863 [Byte1]: 36
2567 11:38:27.225943
2568 11:38:27.226594 Set Vref, RX VrefLevel [Byte0]: 37
2569 11:38:27.229209 [Byte1]: 37
2570 11:38:27.233921
2571 11:38:27.234344 Set Vref, RX VrefLevel [Byte0]: 38
2572 11:38:27.236839 [Byte1]: 38
2573 11:38:27.241737
2574 11:38:27.242240 Set Vref, RX VrefLevel [Byte0]: 39
2575 11:38:27.245461 [Byte1]: 39
2576 11:38:27.250649
2577 11:38:27.251109 Set Vref, RX VrefLevel [Byte0]: 40
2578 11:38:27.252655 [Byte1]: 40
2579 11:38:27.257640
2580 11:38:27.258175 Set Vref, RX VrefLevel [Byte0]: 41
2581 11:38:27.261397 [Byte1]: 41
2582 11:38:27.265453
2583 11:38:27.265967 Set Vref, RX VrefLevel [Byte0]: 42
2584 11:38:27.269086 [Byte1]: 42
2585 11:38:27.274205
2586 11:38:27.274723 Set Vref, RX VrefLevel [Byte0]: 43
2587 11:38:27.276723 [Byte1]: 43
2588 11:38:27.281034
2589 11:38:27.281510 Set Vref, RX VrefLevel [Byte0]: 44
2590 11:38:27.284611 [Byte1]: 44
2591 11:38:27.289925
2592 11:38:27.290371 Set Vref, RX VrefLevel [Byte0]: 45
2593 11:38:27.293117 [Byte1]: 45
2594 11:38:27.297042
2595 11:38:27.297606 Set Vref, RX VrefLevel [Byte0]: 46
2596 11:38:27.300522 [Byte1]: 46
2597 11:38:27.306214
2598 11:38:27.306732 Set Vref, RX VrefLevel [Byte0]: 47
2599 11:38:27.308874 [Byte1]: 47
2600 11:38:27.313578
2601 11:38:27.314102 Set Vref, RX VrefLevel [Byte0]: 48
2602 11:38:27.316655 [Byte1]: 48
2603 11:38:27.320873
2604 11:38:27.321444 Set Vref, RX VrefLevel [Byte0]: 49
2605 11:38:27.324479 [Byte1]: 49
2606 11:38:27.329297
2607 11:38:27.329827 Set Vref, RX VrefLevel [Byte0]: 50
2608 11:38:27.332191 [Byte1]: 50
2609 11:38:27.337496
2610 11:38:27.338021 Set Vref, RX VrefLevel [Byte0]: 51
2611 11:38:27.340236 [Byte1]: 51
2612 11:38:27.345204
2613 11:38:27.345765 Set Vref, RX VrefLevel [Byte0]: 52
2614 11:38:27.348340 [Byte1]: 52
2615 11:38:27.354334
2616 11:38:27.354838 Set Vref, RX VrefLevel [Byte0]: 53
2617 11:38:27.357837 [Byte1]: 53
2618 11:38:27.360800
2619 11:38:27.361335 Set Vref, RX VrefLevel [Byte0]: 54
2620 11:38:27.363625 [Byte1]: 54
2621 11:38:27.368806
2622 11:38:27.369368 Set Vref, RX VrefLevel [Byte0]: 55
2623 11:38:27.371542 [Byte1]: 55
2624 11:38:27.376617
2625 11:38:27.377221 Set Vref, RX VrefLevel [Byte0]: 56
2626 11:38:27.380031 [Byte1]: 56
2627 11:38:27.384408
2628 11:38:27.384929 Set Vref, RX VrefLevel [Byte0]: 57
2629 11:38:27.387613 [Byte1]: 57
2630 11:38:27.392250
2631 11:38:27.392768 Set Vref, RX VrefLevel [Byte0]: 58
2632 11:38:27.396225 [Byte1]: 58
2633 11:38:27.399874
2634 11:38:27.400392 Set Vref, RX VrefLevel [Byte0]: 59
2635 11:38:27.404419 [Byte1]: 59
2636 11:38:27.408605
2637 11:38:27.409128 Set Vref, RX VrefLevel [Byte0]: 60
2638 11:38:27.411509 [Byte1]: 60
2639 11:38:27.416187
2640 11:38:27.416714 Set Vref, RX VrefLevel [Byte0]: 61
2641 11:38:27.419734 [Byte1]: 61
2642 11:38:27.423601
2643 11:38:27.424043 Set Vref, RX VrefLevel [Byte0]: 62
2644 11:38:27.426943 [Byte1]: 62
2645 11:38:27.431714
2646 11:38:27.432154 Set Vref, RX VrefLevel [Byte0]: 63
2647 11:38:27.435819 [Byte1]: 63
2648 11:38:27.440138
2649 11:38:27.440632 Set Vref, RX VrefLevel [Byte0]: 64
2650 11:38:27.443141 [Byte1]: 64
2651 11:38:27.448336
2652 11:38:27.448839 Set Vref, RX VrefLevel [Byte0]: 65
2653 11:38:27.451565 [Byte1]: 65
2654 11:38:27.456042
2655 11:38:27.456548 Set Vref, RX VrefLevel [Byte0]: 66
2656 11:38:27.458842 [Byte1]: 66
2657 11:38:27.464326
2658 11:38:27.464823 Set Vref, RX VrefLevel [Byte0]: 67
2659 11:38:27.467364 [Byte1]: 67
2660 11:38:27.471056
2661 11:38:27.471486 Final RX Vref Byte 0 = 50 to rank0
2662 11:38:27.474703 Final RX Vref Byte 1 = 46 to rank0
2663 11:38:27.477880 Final RX Vref Byte 0 = 50 to rank1
2664 11:38:27.481626 Final RX Vref Byte 1 = 46 to rank1==
2665 11:38:27.485390 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 11:38:27.491709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2667 11:38:27.492211 ==
2668 11:38:27.492548 DQS Delay:
2669 11:38:27.492861 DQS0 = 0, DQS1 = 0
2670 11:38:27.495509 DQM Delay:
2671 11:38:27.496006 DQM0 = 114, DQM1 = 104
2672 11:38:27.497826 DQ Delay:
2673 11:38:27.501689 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2674 11:38:27.504744 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2675 11:38:27.508183 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2676 11:38:27.512172 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
2677 11:38:27.512694
2678 11:38:27.513137
2679 11:38:27.518233 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2680 11:38:27.521447 CH0 RK0: MR19=404, MR18=B0B
2681 11:38:27.528323 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2682 11:38:27.528855
2683 11:38:27.531673 ----->DramcWriteLeveling(PI) begin...
2684 11:38:27.532134 ==
2685 11:38:27.534723 Dram Type= 6, Freq= 0, CH_0, rank 1
2686 11:38:27.538935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2687 11:38:27.539444 ==
2688 11:38:27.543044 Write leveling (Byte 0): 28 => 28
2689 11:38:27.544733 Write leveling (Byte 1): 25 => 25
2690 11:38:27.548414 DramcWriteLeveling(PI) end<-----
2691 11:38:27.548940
2692 11:38:27.549341 ==
2693 11:38:27.551503 Dram Type= 6, Freq= 0, CH_0, rank 1
2694 11:38:27.554643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2695 11:38:27.558476 ==
2696 11:38:27.558989 [Gating] SW mode calibration
2697 11:38:27.568332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2698 11:38:27.570932 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2699 11:38:27.574763 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 11:38:27.580926 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2701 11:38:27.584297 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2702 11:38:27.588363 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2703 11:38:27.594412 0 11 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2704 11:38:27.598355 0 11 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2705 11:38:27.601520 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 11:38:27.608419 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 11:38:27.611467 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 11:38:27.614380 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 11:38:27.621583 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2710 11:38:27.624188 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2711 11:38:27.627951 0 12 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2712 11:38:27.634855 0 12 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2713 11:38:27.637804 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 11:38:27.641831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 11:38:27.648443 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 11:38:27.651475 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 11:38:27.654376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 11:38:27.657888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 11:38:27.664718 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 11:38:27.668093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2721 11:38:27.671324 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 11:38:27.678579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 11:38:27.681426 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 11:38:27.685264 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 11:38:27.691873 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 11:38:27.694805 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 11:38:27.698691 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 11:38:27.705202 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 11:38:27.708162 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 11:38:27.711493 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 11:38:27.717760 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 11:38:27.721961 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 11:38:27.724851 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 11:38:27.728448 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2735 11:38:27.734984 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 11:38:27.738618 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2737 11:38:27.742200 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2738 11:38:27.746076 Total UI for P1: 0, mck2ui 16
2739 11:38:27.747820 best dqsien dly found for B0: ( 0, 15, 20)
2740 11:38:27.751044 Total UI for P1: 0, mck2ui 16
2741 11:38:27.754960 best dqsien dly found for B1: ( 0, 15, 20)
2742 11:38:27.758722 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2743 11:38:27.762139 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2744 11:38:27.765892
2745 11:38:27.768581 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2746 11:38:27.771235 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2747 11:38:27.774723 [Gating] SW calibration Done
2748 11:38:27.775220 ==
2749 11:38:27.778571 Dram Type= 6, Freq= 0, CH_0, rank 1
2750 11:38:27.780839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2751 11:38:27.781304 ==
2752 11:38:27.781770 RX Vref Scan: 0
2753 11:38:27.784705
2754 11:38:27.785200 RX Vref 0 -> 0, step: 1
2755 11:38:27.785591
2756 11:38:27.788105 RX Delay -40 -> 252, step: 8
2757 11:38:27.791817 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2758 11:38:27.794778 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2759 11:38:27.801497 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2760 11:38:27.804862 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2761 11:38:27.807507 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2762 11:38:27.811581 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2763 11:38:27.814823 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2764 11:38:27.821694 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2765 11:38:27.824149 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2766 11:38:27.827464 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2767 11:38:27.830969 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2768 11:38:27.834254 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2769 11:38:27.841194 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2770 11:38:27.845781 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2771 11:38:27.848670 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2772 11:38:27.851223 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2773 11:38:27.851654 ==
2774 11:38:27.854509 Dram Type= 6, Freq= 0, CH_0, rank 1
2775 11:38:27.861192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2776 11:38:27.861746 ==
2777 11:38:27.862080 DQS Delay:
2778 11:38:27.862387 DQS0 = 0, DQS1 = 0
2779 11:38:27.864687 DQM Delay:
2780 11:38:27.865192 DQM0 = 114, DQM1 = 106
2781 11:38:27.868576 DQ Delay:
2782 11:38:27.870998 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =107
2783 11:38:27.874519 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2784 11:38:27.877466 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2785 11:38:27.881398 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2786 11:38:27.881890
2787 11:38:27.882234
2788 11:38:27.882538 ==
2789 11:38:27.884887 Dram Type= 6, Freq= 0, CH_0, rank 1
2790 11:38:27.887859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2791 11:38:27.888362 ==
2792 11:38:27.888694
2793 11:38:27.888996
2794 11:38:27.891553 TX Vref Scan disable
2795 11:38:27.895049 == TX Byte 0 ==
2796 11:38:27.898092 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2797 11:38:27.901263 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2798 11:38:27.905532 == TX Byte 1 ==
2799 11:38:27.907843 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2800 11:38:27.911108 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2801 11:38:27.911614 ==
2802 11:38:27.914972 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 11:38:27.917966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 11:38:27.921631 ==
2805 11:38:27.931711 TX Vref=22, minBit 10, minWin=24, winSum=418
2806 11:38:27.935766 TX Vref=24, minBit 8, minWin=25, winSum=424
2807 11:38:27.938763 TX Vref=26, minBit 1, minWin=26, winSum=429
2808 11:38:27.941482 TX Vref=28, minBit 9, minWin=26, winSum=431
2809 11:38:27.944997 TX Vref=30, minBit 9, minWin=26, winSum=435
2810 11:38:27.951585 TX Vref=32, minBit 8, minWin=26, winSum=434
2811 11:38:27.954750 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
2812 11:38:27.955176
2813 11:38:27.958020 Final TX Range 1 Vref 30
2814 11:38:27.958449
2815 11:38:27.958864 ==
2816 11:38:27.961527 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 11:38:27.964569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2818 11:38:27.964998 ==
2819 11:38:27.968196
2820 11:38:27.968578
2821 11:38:27.968871 TX Vref Scan disable
2822 11:38:27.971438 == TX Byte 0 ==
2823 11:38:27.974266 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2824 11:38:27.977748 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2825 11:38:27.980937 == TX Byte 1 ==
2826 11:38:27.984411 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2827 11:38:27.988352 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2828 11:38:27.988755
2829 11:38:27.991813 [DATLAT]
2830 11:38:27.992252 Freq=1200, CH0 RK1
2831 11:38:27.992823
2832 11:38:27.994594 DATLAT Default: 0xc
2833 11:38:27.995151 0, 0xFFFF, sum = 0
2834 11:38:27.997966 1, 0xFFFF, sum = 0
2835 11:38:27.998693 2, 0xFFFF, sum = 0
2836 11:38:28.001193 3, 0xFFFF, sum = 0
2837 11:38:28.001652 4, 0xFFFF, sum = 0
2838 11:38:28.004693 5, 0xFFFF, sum = 0
2839 11:38:28.005273 6, 0xFFFF, sum = 0
2840 11:38:28.007809 7, 0xFFFF, sum = 0
2841 11:38:28.008222 8, 0xFFFF, sum = 0
2842 11:38:28.011124 9, 0xFFFF, sum = 0
2843 11:38:28.015129 10, 0xFFFF, sum = 0
2844 11:38:28.015522 11, 0x0, sum = 1
2845 11:38:28.015824 12, 0x0, sum = 2
2846 11:38:28.018232 13, 0x0, sum = 3
2847 11:38:28.018766 14, 0x0, sum = 4
2848 11:38:28.021061 best_step = 12
2849 11:38:28.021565
2850 11:38:28.021986 ==
2851 11:38:28.025128 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 11:38:28.027864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2853 11:38:28.028365 ==
2854 11:38:28.031641 RX Vref Scan: 0
2855 11:38:28.032042
2856 11:38:28.032347 RX Vref 0 -> 0, step: 1
2857 11:38:28.034241
2858 11:38:28.034630 RX Delay -21 -> 252, step: 4
2859 11:38:28.041350 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2860 11:38:28.045642 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2861 11:38:28.048984 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2862 11:38:28.052108 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2863 11:38:28.055299 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2864 11:38:28.062092 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2865 11:38:28.065003 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2866 11:38:28.068280 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2867 11:38:28.071808 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2868 11:38:28.075271 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2869 11:38:28.081670 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2870 11:38:28.084714 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2871 11:38:28.088908 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2872 11:38:28.091480 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2873 11:38:28.095707 iDelay=199, Bit 14, Center 114 (51 ~ 178) 128
2874 11:38:28.101988 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2875 11:38:28.102389 ==
2876 11:38:28.105057 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 11:38:28.108044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2878 11:38:28.108428 ==
2879 11:38:28.108731 DQS Delay:
2880 11:38:28.111476 DQS0 = 0, DQS1 = 0
2881 11:38:28.111884 DQM Delay:
2882 11:38:28.115193 DQM0 = 114, DQM1 = 104
2883 11:38:28.115579 DQ Delay:
2884 11:38:28.118841 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2885 11:38:28.121819 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2886 11:38:28.124877 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2887 11:38:28.128114 DQ12 =110, DQ13 =112, DQ14 =114, DQ15 =114
2888 11:38:28.128500
2889 11:38:28.128796
2890 11:38:28.138377 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2891 11:38:28.141255 CH0 RK1: MR19=404, MR18=E0E
2892 11:38:28.144799 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2893 11:38:28.147996 [RxdqsGatingPostProcess] freq 1200
2894 11:38:28.154837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2895 11:38:28.158234 Pre-setting of DQS Precalculation
2896 11:38:28.161391 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2897 11:38:28.161782 ==
2898 11:38:28.164986 Dram Type= 6, Freq= 0, CH_1, rank 0
2899 11:38:28.171321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2900 11:38:28.171722 ==
2901 11:38:28.175016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2902 11:38:28.181270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2903 11:38:28.190020 [CA 0] Center 37 (7~68) winsize 62
2904 11:38:28.193301 [CA 1] Center 37 (6~68) winsize 63
2905 11:38:28.196763 [CA 2] Center 34 (4~65) winsize 62
2906 11:38:28.200399 [CA 3] Center 33 (3~64) winsize 62
2907 11:38:28.203778 [CA 4] Center 32 (2~63) winsize 62
2908 11:38:28.207051 [CA 5] Center 32 (2~63) winsize 62
2909 11:38:28.207553
2910 11:38:28.210295 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2911 11:38:28.210722
2912 11:38:28.214414 [CATrainingPosCal] consider 1 rank data
2913 11:38:28.216761 u2DelayCellTimex100 = 270/100 ps
2914 11:38:28.219976 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2915 11:38:28.223779 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2916 11:38:28.230768 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2917 11:38:28.233608 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2918 11:38:28.237296 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2919 11:38:28.240091 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2920 11:38:28.240519
2921 11:38:28.243327 CA PerBit enable=1, Macro0, CA PI delay=32
2922 11:38:28.243830
2923 11:38:28.246808 [CBTSetCACLKResult] CA Dly = 32
2924 11:38:28.247261 CS Dly: 6 (0~37)
2925 11:38:28.247730 ==
2926 11:38:28.250343 Dram Type= 6, Freq= 0, CH_1, rank 1
2927 11:38:28.256718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2928 11:38:28.257190 ==
2929 11:38:28.260788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2930 11:38:28.267521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2931 11:38:28.276640 [CA 0] Center 37 (6~68) winsize 63
2932 11:38:28.279630 [CA 1] Center 37 (6~68) winsize 63
2933 11:38:28.282126 [CA 2] Center 34 (3~65) winsize 63
2934 11:38:28.285711 [CA 3] Center 33 (3~64) winsize 62
2935 11:38:28.289217 [CA 4] Center 32 (2~63) winsize 62
2936 11:38:28.292401 [CA 5] Center 31 (1~62) winsize 62
2937 11:38:28.292903
2938 11:38:28.295935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2939 11:38:28.296437
2940 11:38:28.298366 [CATrainingPosCal] consider 2 rank data
2941 11:38:28.303145 u2DelayCellTimex100 = 270/100 ps
2942 11:38:28.305440 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2943 11:38:28.308837 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2944 11:38:28.315296 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2945 11:38:28.319124 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2946 11:38:28.322124 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2947 11:38:28.325740 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2948 11:38:28.326246
2949 11:38:28.328818 CA PerBit enable=1, Macro0, CA PI delay=32
2950 11:38:28.329368
2951 11:38:28.331680 [CBTSetCACLKResult] CA Dly = 32
2952 11:38:28.332106 CS Dly: 6 (0~38)
2953 11:38:28.332479
2954 11:38:28.335446 ----->DramcWriteLeveling(PI) begin...
2955 11:38:28.338304 ==
2956 11:38:28.338730 Dram Type= 6, Freq= 0, CH_1, rank 0
2957 11:38:28.345305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2958 11:38:28.345817 ==
2959 11:38:28.348275 Write leveling (Byte 0): 22 => 22
2960 11:38:28.352074 Write leveling (Byte 1): 22 => 22
2961 11:38:28.355415 DramcWriteLeveling(PI) end<-----
2962 11:38:28.355914
2963 11:38:28.356247 ==
2964 11:38:28.359085 Dram Type= 6, Freq= 0, CH_1, rank 0
2965 11:38:28.362289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2966 11:38:28.362718 ==
2967 11:38:28.366086 [Gating] SW mode calibration
2968 11:38:28.372041 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2969 11:38:28.375478 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2970 11:38:28.381953 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2971 11:38:28.386022 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 11:38:28.388678 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 11:38:28.395542 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2974 11:38:28.398703 0 11 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 1)
2975 11:38:28.402071 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2976 11:38:28.409337 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 11:38:28.411879 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 11:38:28.415293 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 11:38:28.422160 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 11:38:28.425200 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 11:38:28.428112 0 12 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2982 11:38:28.435290 0 12 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
2983 11:38:28.438261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 11:38:28.442981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 11:38:28.448671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 11:38:28.452033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 11:38:28.455496 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 11:38:28.461621 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 11:38:28.465071 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 11:38:28.468687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2991 11:38:28.472566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2992 11:38:28.479039 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 11:38:28.483594 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 11:38:28.485770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 11:38:28.491905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 11:38:28.496221 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 11:38:28.498467 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 11:38:28.505122 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 11:38:28.508180 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 11:38:28.512198 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 11:38:28.518727 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 11:38:28.522626 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 11:38:28.525083 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 11:38:28.532155 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 11:38:28.535333 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 11:38:28.538229 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3007 11:38:28.545884 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3008 11:38:28.546394 Total UI for P1: 0, mck2ui 16
3009 11:38:28.552171 best dqsien dly found for B0: ( 0, 15, 16)
3010 11:38:28.555034 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3011 11:38:28.558884 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3012 11:38:28.561954 Total UI for P1: 0, mck2ui 16
3013 11:38:28.565347 best dqsien dly found for B1: ( 0, 15, 22)
3014 11:38:28.568655 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3015 11:38:28.572472 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
3016 11:38:28.572974
3017 11:38:28.574932 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3018 11:38:28.581455 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
3019 11:38:28.581952 [Gating] SW calibration Done
3020 11:38:28.585577 ==
3021 11:38:28.586008 Dram Type= 6, Freq= 0, CH_1, rank 0
3022 11:38:28.592225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3023 11:38:28.592732 ==
3024 11:38:28.593068 RX Vref Scan: 0
3025 11:38:28.593520
3026 11:38:28.594834 RX Vref 0 -> 0, step: 1
3027 11:38:28.595260
3028 11:38:28.598370 RX Delay -40 -> 252, step: 8
3029 11:38:28.601989 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3030 11:38:28.605832 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3031 11:38:28.608379 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3032 11:38:28.615209 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3033 11:38:28.619050 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3034 11:38:28.622087 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3035 11:38:28.625286 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3036 11:38:28.628417 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3037 11:38:28.632524 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3038 11:38:28.638435 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3039 11:38:28.642086 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3040 11:38:28.645266 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3041 11:38:28.648758 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3042 11:38:28.655075 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3043 11:38:28.658572 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3044 11:38:28.661714 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3045 11:38:28.662142 ==
3046 11:38:28.666227 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 11:38:28.668320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3048 11:38:28.668826 ==
3049 11:38:28.671325 DQS Delay:
3050 11:38:28.671755 DQS0 = 0, DQS1 = 0
3051 11:38:28.675895 DQM Delay:
3052 11:38:28.676400 DQM0 = 116, DQM1 = 109
3053 11:38:28.676737 DQ Delay:
3054 11:38:28.678754 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3055 11:38:28.684473 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3056 11:38:28.687807 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =103
3057 11:38:28.691387 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3058 11:38:28.691819
3059 11:38:28.692155
3060 11:38:28.692461 ==
3061 11:38:28.695057 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 11:38:28.698198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3063 11:38:28.698702 ==
3064 11:38:28.699034
3065 11:38:28.699337
3066 11:38:28.701311 TX Vref Scan disable
3067 11:38:28.704554 == TX Byte 0 ==
3068 11:38:28.707536 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3069 11:38:28.711689 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3070 11:38:28.714645 == TX Byte 1 ==
3071 11:38:28.717868 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3072 11:38:28.721494 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3073 11:38:28.721999 ==
3074 11:38:28.724788 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 11:38:28.728051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3076 11:38:28.730841 ==
3077 11:38:28.741148 TX Vref=22, minBit 8, minWin=25, winSum=419
3078 11:38:28.744547 TX Vref=24, minBit 8, minWin=25, winSum=423
3079 11:38:28.748059 TX Vref=26, minBit 1, minWin=26, winSum=430
3080 11:38:28.751160 TX Vref=28, minBit 0, minWin=26, winSum=431
3081 11:38:28.754171 TX Vref=30, minBit 8, minWin=26, winSum=430
3082 11:38:28.761201 TX Vref=32, minBit 8, minWin=26, winSum=429
3083 11:38:28.765087 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
3084 11:38:28.765649
3085 11:38:28.767035 Final TX Range 1 Vref 28
3086 11:38:28.767460
3087 11:38:28.767787 ==
3088 11:38:28.770908 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 11:38:28.774067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3090 11:38:28.777344 ==
3091 11:38:28.777844
3092 11:38:28.778174
3093 11:38:28.778480 TX Vref Scan disable
3094 11:38:28.780563 == TX Byte 0 ==
3095 11:38:28.783995 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3096 11:38:28.790518 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3097 11:38:28.791020 == TX Byte 1 ==
3098 11:38:28.794079 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3099 11:38:28.800365 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3100 11:38:28.800889
3101 11:38:28.801221 [DATLAT]
3102 11:38:28.801574 Freq=1200, CH1 RK0
3103 11:38:28.801870
3104 11:38:28.803708 DATLAT Default: 0xd
3105 11:38:28.804132 0, 0xFFFF, sum = 0
3106 11:38:28.807363 1, 0xFFFF, sum = 0
3107 11:38:28.810245 2, 0xFFFF, sum = 0
3108 11:38:28.810718 3, 0xFFFF, sum = 0
3109 11:38:28.813989 4, 0xFFFF, sum = 0
3110 11:38:28.814418 5, 0xFFFF, sum = 0
3111 11:38:28.817213 6, 0xFFFF, sum = 0
3112 11:38:28.817894 7, 0xFFFF, sum = 0
3113 11:38:28.820593 8, 0xFFFF, sum = 0
3114 11:38:28.821038 9, 0xFFFF, sum = 0
3115 11:38:28.823274 10, 0xFFFF, sum = 0
3116 11:38:28.823655 11, 0x0, sum = 1
3117 11:38:28.826794 12, 0x0, sum = 2
3118 11:38:28.827180 13, 0x0, sum = 3
3119 11:38:28.830940 14, 0x0, sum = 4
3120 11:38:28.831405 best_step = 12
3121 11:38:28.831700
3122 11:38:28.832001 ==
3123 11:38:28.833589 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 11:38:28.837129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3125 11:38:28.837557 ==
3126 11:38:28.840388 RX Vref Scan: 1
3127 11:38:28.840847
3128 11:38:28.843569 Set Vref Range= 32 -> 127
3129 11:38:28.844061
3130 11:38:28.844361 RX Vref 32 -> 127, step: 1
3131 11:38:28.846935
3132 11:38:28.847395 RX Delay -21 -> 252, step: 4
3133 11:38:28.847694
3134 11:38:28.850183 Set Vref, RX VrefLevel [Byte0]: 32
3135 11:38:28.853060 [Byte1]: 32
3136 11:38:28.857208
3137 11:38:28.857625 Set Vref, RX VrefLevel [Byte0]: 33
3138 11:38:28.860417 [Byte1]: 33
3139 11:38:28.865899
3140 11:38:28.866373 Set Vref, RX VrefLevel [Byte0]: 34
3141 11:38:28.868871 [Byte1]: 34
3142 11:38:28.873004
3143 11:38:28.873438 Set Vref, RX VrefLevel [Byte0]: 35
3144 11:38:28.877120 [Byte1]: 35
3145 11:38:28.881360
3146 11:38:28.881847 Set Vref, RX VrefLevel [Byte0]: 36
3147 11:38:28.884628 [Byte1]: 36
3148 11:38:28.889385
3149 11:38:28.889843 Set Vref, RX VrefLevel [Byte0]: 37
3150 11:38:28.892226 [Byte1]: 37
3151 11:38:28.897380
3152 11:38:28.897839 Set Vref, RX VrefLevel [Byte0]: 38
3153 11:38:28.900107 [Byte1]: 38
3154 11:38:28.904973
3155 11:38:28.905478 Set Vref, RX VrefLevel [Byte0]: 39
3156 11:38:28.908015 [Byte1]: 39
3157 11:38:28.912537
3158 11:38:28.913046 Set Vref, RX VrefLevel [Byte0]: 40
3159 11:38:28.916855 [Byte1]: 40
3160 11:38:28.920617
3161 11:38:28.921013 Set Vref, RX VrefLevel [Byte0]: 41
3162 11:38:28.924029 [Byte1]: 41
3163 11:38:28.928361
3164 11:38:28.928815 Set Vref, RX VrefLevel [Byte0]: 42
3165 11:38:28.931558 [Byte1]: 42
3166 11:38:28.936735
3167 11:38:28.937149 Set Vref, RX VrefLevel [Byte0]: 43
3168 11:38:28.940136 [Byte1]: 43
3169 11:38:28.944769
3170 11:38:28.945264 Set Vref, RX VrefLevel [Byte0]: 44
3171 11:38:28.947715 [Byte1]: 44
3172 11:38:28.952630
3173 11:38:28.953096 Set Vref, RX VrefLevel [Byte0]: 45
3174 11:38:28.955564 [Byte1]: 45
3175 11:38:28.960453
3176 11:38:28.960942 Set Vref, RX VrefLevel [Byte0]: 46
3177 11:38:28.964007 [Byte1]: 46
3178 11:38:28.968555
3179 11:38:28.969042 Set Vref, RX VrefLevel [Byte0]: 47
3180 11:38:28.971477 [Byte1]: 47
3181 11:38:28.975880
3182 11:38:28.976263 Set Vref, RX VrefLevel [Byte0]: 48
3183 11:38:28.979695 [Byte1]: 48
3184 11:38:28.984971
3185 11:38:28.985392 Set Vref, RX VrefLevel [Byte0]: 49
3186 11:38:28.986978 [Byte1]: 49
3187 11:38:28.992177
3188 11:38:28.992636 Set Vref, RX VrefLevel [Byte0]: 50
3189 11:38:28.995952 [Byte1]: 50
3190 11:38:28.999757
3191 11:38:29.000215 Set Vref, RX VrefLevel [Byte0]: 51
3192 11:38:29.003147 [Byte1]: 51
3193 11:38:29.007839
3194 11:38:29.008296 Set Vref, RX VrefLevel [Byte0]: 52
3195 11:38:29.010673 [Byte1]: 52
3196 11:38:29.015777
3197 11:38:29.016237 Set Vref, RX VrefLevel [Byte0]: 53
3198 11:38:29.018673 [Byte1]: 53
3199 11:38:29.024105
3200 11:38:29.024572 Set Vref, RX VrefLevel [Byte0]: 54
3201 11:38:29.026784 [Byte1]: 54
3202 11:38:29.031625
3203 11:38:29.032130 Set Vref, RX VrefLevel [Byte0]: 55
3204 11:38:29.034819 [Byte1]: 55
3205 11:38:29.039459
3206 11:38:29.039881 Set Vref, RX VrefLevel [Byte0]: 56
3207 11:38:29.043693 [Byte1]: 56
3208 11:38:29.048605
3209 11:38:29.049112 Set Vref, RX VrefLevel [Byte0]: 57
3210 11:38:29.050660 [Byte1]: 57
3211 11:38:29.055703
3212 11:38:29.056202 Set Vref, RX VrefLevel [Byte0]: 58
3213 11:38:29.058500 [Byte1]: 58
3214 11:38:29.063181
3215 11:38:29.063679 Set Vref, RX VrefLevel [Byte0]: 59
3216 11:38:29.066564 [Byte1]: 59
3217 11:38:29.072073
3218 11:38:29.072569 Set Vref, RX VrefLevel [Byte0]: 60
3219 11:38:29.074510 [Byte1]: 60
3220 11:38:29.078970
3221 11:38:29.079493 Set Vref, RX VrefLevel [Byte0]: 61
3222 11:38:29.082316 [Byte1]: 61
3223 11:38:29.087383
3224 11:38:29.087882 Set Vref, RX VrefLevel [Byte0]: 62
3225 11:38:29.089946 [Byte1]: 62
3226 11:38:29.094721
3227 11:38:29.095218 Set Vref, RX VrefLevel [Byte0]: 63
3228 11:38:29.098169 [Byte1]: 63
3229 11:38:29.102983
3230 11:38:29.103481 Set Vref, RX VrefLevel [Byte0]: 64
3231 11:38:29.106572 [Byte1]: 64
3232 11:38:29.110602
3233 11:38:29.111103 Set Vref, RX VrefLevel [Byte0]: 65
3234 11:38:29.114099 [Byte1]: 65
3235 11:38:29.118664
3236 11:38:29.119165 Set Vref, RX VrefLevel [Byte0]: 66
3237 11:38:29.121858 [Byte1]: 66
3238 11:38:29.127306
3239 11:38:29.127729 Set Vref, RX VrefLevel [Byte0]: 67
3240 11:38:29.130131 [Byte1]: 67
3241 11:38:29.134719
3242 11:38:29.135216 Final RX Vref Byte 0 = 53 to rank0
3243 11:38:29.137877 Final RX Vref Byte 1 = 49 to rank0
3244 11:38:29.140878 Final RX Vref Byte 0 = 53 to rank1
3245 11:38:29.144559 Final RX Vref Byte 1 = 49 to rank1==
3246 11:38:29.148604 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 11:38:29.155881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3248 11:38:29.156387 ==
3249 11:38:29.156758 DQS Delay:
3250 11:38:29.157952 DQS0 = 0, DQS1 = 0
3251 11:38:29.158372 DQM Delay:
3252 11:38:29.158728 DQM0 = 115, DQM1 = 105
3253 11:38:29.160515 DQ Delay:
3254 11:38:29.164247 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3255 11:38:29.167294 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3256 11:38:29.171399 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3257 11:38:29.174322 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3258 11:38:29.174818
3259 11:38:29.175148
3260 11:38:29.184777 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3261 11:38:29.185341 CH1 RK0: MR19=404, MR18=1717
3262 11:38:29.190853 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3263 11:38:29.191343
3264 11:38:29.194166 ----->DramcWriteLeveling(PI) begin...
3265 11:38:29.194668 ==
3266 11:38:29.197631 Dram Type= 6, Freq= 0, CH_1, rank 1
3267 11:38:29.204266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3268 11:38:29.204783 ==
3269 11:38:29.207781 Write leveling (Byte 0): 22 => 22
3270 11:38:29.208309 Write leveling (Byte 1): 22 => 22
3271 11:38:29.211082 DramcWriteLeveling(PI) end<-----
3272 11:38:29.211606
3273 11:38:29.211935 ==
3274 11:38:29.214489 Dram Type= 6, Freq= 0, CH_1, rank 1
3275 11:38:29.220662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3276 11:38:29.221155 ==
3277 11:38:29.224112 [Gating] SW mode calibration
3278 11:38:29.231243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3279 11:38:29.234411 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3280 11:38:29.240479 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3281 11:38:29.243550 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3282 11:38:29.247320 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3283 11:38:29.254064 0 11 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3284 11:38:29.256862 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3285 11:38:29.260275 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3286 11:38:29.267218 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3287 11:38:29.271033 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3288 11:38:29.274004 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3289 11:38:29.280570 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3290 11:38:29.284635 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3291 11:38:29.287222 0 12 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
3292 11:38:29.290891 0 12 16 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3293 11:38:29.297287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3294 11:38:29.300186 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 11:38:29.303997 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3296 11:38:29.310043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3297 11:38:29.315246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3298 11:38:29.317172 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 11:38:29.323190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3300 11:38:29.326414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3301 11:38:29.330414 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3302 11:38:29.337192 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 11:38:29.339937 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 11:38:29.342809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 11:38:29.350034 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 11:38:29.353796 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 11:38:29.356458 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 11:38:29.362993 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 11:38:29.366194 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3310 11:38:29.369560 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3311 11:38:29.376153 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3312 11:38:29.379512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3313 11:38:29.382712 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3314 11:38:29.389178 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3315 11:38:29.392787 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3316 11:38:29.396687 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3317 11:38:29.399687 Total UI for P1: 0, mck2ui 16
3318 11:38:29.403593 best dqsien dly found for B0: ( 0, 15, 12)
3319 11:38:29.409640 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3320 11:38:29.410093 Total UI for P1: 0, mck2ui 16
3321 11:38:29.416006 best dqsien dly found for B1: ( 0, 15, 14)
3322 11:38:29.419087 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3323 11:38:29.422896 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3324 11:38:29.423349
3325 11:38:29.426178 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3326 11:38:29.429956 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3327 11:38:29.435110 [Gating] SW calibration Done
3328 11:38:29.435568 ==
3329 11:38:29.436735 Dram Type= 6, Freq= 0, CH_1, rank 1
3330 11:38:29.439398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3331 11:38:29.439970 ==
3332 11:38:29.442583 RX Vref Scan: 0
3333 11:38:29.442958
3334 11:38:29.443249 RX Vref 0 -> 0, step: 1
3335 11:38:29.443523
3336 11:38:29.446190 RX Delay -40 -> 252, step: 8
3337 11:38:29.449604 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3338 11:38:29.456318 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3339 11:38:29.459394 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3340 11:38:29.462421 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3341 11:38:29.465977 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3342 11:38:29.472821 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3343 11:38:29.476272 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3344 11:38:29.479695 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3345 11:38:29.482465 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3346 11:38:29.485409 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3347 11:38:29.492631 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3348 11:38:29.495507 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3349 11:38:29.498980 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3350 11:38:29.502294 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3351 11:38:29.505550 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3352 11:38:29.512708 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3353 11:38:29.513212 ==
3354 11:38:29.515694 Dram Type= 6, Freq= 0, CH_1, rank 1
3355 11:38:29.518596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3356 11:38:29.519025 ==
3357 11:38:29.519353 DQS Delay:
3358 11:38:29.523234 DQS0 = 0, DQS1 = 0
3359 11:38:29.523724 DQM Delay:
3360 11:38:29.525115 DQM0 = 116, DQM1 = 106
3361 11:38:29.525606 DQ Delay:
3362 11:38:29.528316 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =119
3363 11:38:29.532088 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3364 11:38:29.535650 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3365 11:38:29.538505 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3366 11:38:29.538940
3367 11:38:29.539265
3368 11:38:29.543101 ==
3369 11:38:29.543524 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 11:38:29.549193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 11:38:29.549728 ==
3372 11:38:29.550062
3373 11:38:29.550364
3374 11:38:29.551559 TX Vref Scan disable
3375 11:38:29.551981 == TX Byte 0 ==
3376 11:38:29.555496 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3377 11:38:29.562586 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3378 11:38:29.563093 == TX Byte 1 ==
3379 11:38:29.565480 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3380 11:38:29.572128 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3381 11:38:29.572648 ==
3382 11:38:29.575832 Dram Type= 6, Freq= 0, CH_1, rank 1
3383 11:38:29.579758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3384 11:38:29.580185 ==
3385 11:38:29.590618 TX Vref=22, minBit 0, minWin=25, winSum=422
3386 11:38:29.593982 TX Vref=24, minBit 9, minWin=25, winSum=425
3387 11:38:29.597140 TX Vref=26, minBit 3, minWin=26, winSum=428
3388 11:38:29.600317 TX Vref=28, minBit 3, minWin=26, winSum=430
3389 11:38:29.603229 TX Vref=30, minBit 0, minWin=26, winSum=431
3390 11:38:29.610358 TX Vref=32, minBit 0, minWin=26, winSum=434
3391 11:38:29.615187 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 32
3392 11:38:29.615690
3393 11:38:29.617473 Final TX Range 1 Vref 32
3394 11:38:29.617975
3395 11:38:29.618304 ==
3396 11:38:29.619948 Dram Type= 6, Freq= 0, CH_1, rank 1
3397 11:38:29.623795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3398 11:38:29.624296 ==
3399 11:38:29.626085
3400 11:38:29.626532
3401 11:38:29.626859 TX Vref Scan disable
3402 11:38:29.629434 == TX Byte 0 ==
3403 11:38:29.634177 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3404 11:38:29.640171 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3405 11:38:29.640607 == TX Byte 1 ==
3406 11:38:29.643030 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3407 11:38:29.649898 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3408 11:38:29.650398
3409 11:38:29.650725 [DATLAT]
3410 11:38:29.651027 Freq=1200, CH1 RK1
3411 11:38:29.651346
3412 11:38:29.652795 DATLAT Default: 0xc
3413 11:38:29.653214 0, 0xFFFF, sum = 0
3414 11:38:29.656248 1, 0xFFFF, sum = 0
3415 11:38:29.659748 2, 0xFFFF, sum = 0
3416 11:38:29.660198 3, 0xFFFF, sum = 0
3417 11:38:29.663210 4, 0xFFFF, sum = 0
3418 11:38:29.663713 5, 0xFFFF, sum = 0
3419 11:38:29.666112 6, 0xFFFF, sum = 0
3420 11:38:29.666616 7, 0xFFFF, sum = 0
3421 11:38:29.669004 8, 0xFFFF, sum = 0
3422 11:38:29.669629 9, 0xFFFF, sum = 0
3423 11:38:29.672441 10, 0xFFFF, sum = 0
3424 11:38:29.672942 11, 0x0, sum = 1
3425 11:38:29.675704 12, 0x0, sum = 2
3426 11:38:29.676139 13, 0x0, sum = 3
3427 11:38:29.680604 14, 0x0, sum = 4
3428 11:38:29.681142 best_step = 12
3429 11:38:29.681545
3430 11:38:29.681850 ==
3431 11:38:29.682535 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:38:29.686176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3433 11:38:29.686597 ==
3434 11:38:29.689738 RX Vref Scan: 0
3435 11:38:29.690235
3436 11:38:29.692676 RX Vref 0 -> 0, step: 1
3437 11:38:29.693168
3438 11:38:29.693601 RX Delay -29 -> 252, step: 4
3439 11:38:29.700274 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3440 11:38:29.703016 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3441 11:38:29.706819 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3442 11:38:29.710539 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3443 11:38:29.713381 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3444 11:38:29.720319 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3445 11:38:29.723312 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3446 11:38:29.726785 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3447 11:38:29.730178 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3448 11:38:29.733473 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3449 11:38:29.739876 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3450 11:38:29.743028 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3451 11:38:29.746638 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3452 11:38:29.750033 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3453 11:38:29.756597 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3454 11:38:29.760026 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3455 11:38:29.760451 ==
3456 11:38:29.762598 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 11:38:29.766021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3458 11:38:29.766528 ==
3459 11:38:29.769514 DQS Delay:
3460 11:38:29.770015 DQS0 = 0, DQS1 = 0
3461 11:38:29.770345 DQM Delay:
3462 11:38:29.773737 DQM0 = 114, DQM1 = 103
3463 11:38:29.774238 DQ Delay:
3464 11:38:29.776006 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3465 11:38:29.779334 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3466 11:38:29.783390 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3467 11:38:29.786648 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3468 11:38:29.789146
3469 11:38:29.789611
3470 11:38:29.796153 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3471 11:38:29.799278 CH1 RK1: MR19=404, MR18=A0A
3472 11:38:29.805837 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3473 11:38:29.806345 [RxdqsGatingPostProcess] freq 1200
3474 11:38:29.812870 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3475 11:38:29.816352 Pre-setting of DQS Precalculation
3476 11:38:29.822513 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3477 11:38:29.830775 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3478 11:38:29.836163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3479 11:38:29.836666
3480 11:38:29.836994
3481 11:38:29.839039 [Calibration Summary] 2400 Mbps
3482 11:38:29.839461 CH 0, Rank 0
3483 11:38:29.843189 SW Impedance : PASS
3484 11:38:29.845959 DUTY Scan : NO K
3485 11:38:29.846455 ZQ Calibration : PASS
3486 11:38:29.849400 Jitter Meter : NO K
3487 11:38:29.849901 CBT Training : PASS
3488 11:38:29.852801 Write leveling : PASS
3489 11:38:29.855857 RX DQS gating : PASS
3490 11:38:29.856361 RX DQ/DQS(RDDQC) : PASS
3491 11:38:29.860058 TX DQ/DQS : PASS
3492 11:38:29.863149 RX DATLAT : PASS
3493 11:38:29.863568 RX DQ/DQS(Engine): PASS
3494 11:38:29.866238 TX OE : NO K
3495 11:38:29.866744 All Pass.
3496 11:38:29.867073
3497 11:38:29.869794 CH 0, Rank 1
3498 11:38:29.870292 SW Impedance : PASS
3499 11:38:29.872143 DUTY Scan : NO K
3500 11:38:29.876929 ZQ Calibration : PASS
3501 11:38:29.877484 Jitter Meter : NO K
3502 11:38:29.879546 CBT Training : PASS
3503 11:38:29.883478 Write leveling : PASS
3504 11:38:29.883906 RX DQS gating : PASS
3505 11:38:29.886649 RX DQ/DQS(RDDQC) : PASS
3506 11:38:29.888988 TX DQ/DQS : PASS
3507 11:38:29.889570 RX DATLAT : PASS
3508 11:38:29.892848 RX DQ/DQS(Engine): PASS
3509 11:38:29.893403 TX OE : NO K
3510 11:38:29.896442 All Pass.
3511 11:38:29.896956
3512 11:38:29.897347 CH 1, Rank 0
3513 11:38:29.899075 SW Impedance : PASS
3514 11:38:29.899572 DUTY Scan : NO K
3515 11:38:29.902454 ZQ Calibration : PASS
3516 11:38:29.905598 Jitter Meter : NO K
3517 11:38:29.906022 CBT Training : PASS
3518 11:38:29.908688 Write leveling : PASS
3519 11:38:29.912391 RX DQS gating : PASS
3520 11:38:29.912884 RX DQ/DQS(RDDQC) : PASS
3521 11:38:29.915786 TX DQ/DQS : PASS
3522 11:38:29.918836 RX DATLAT : PASS
3523 11:38:29.919333 RX DQ/DQS(Engine): PASS
3524 11:38:29.921934 TX OE : NO K
3525 11:38:29.922357 All Pass.
3526 11:38:29.922685
3527 11:38:29.925614 CH 1, Rank 1
3528 11:38:29.926107 SW Impedance : PASS
3529 11:38:29.928911 DUTY Scan : NO K
3530 11:38:29.932296 ZQ Calibration : PASS
3531 11:38:29.932791 Jitter Meter : NO K
3532 11:38:29.935630 CBT Training : PASS
3533 11:38:29.939262 Write leveling : PASS
3534 11:38:29.939710 RX DQS gating : PASS
3535 11:38:29.942176 RX DQ/DQS(RDDQC) : PASS
3536 11:38:29.945402 TX DQ/DQS : PASS
3537 11:38:29.945837 RX DATLAT : PASS
3538 11:38:29.949725 RX DQ/DQS(Engine): PASS
3539 11:38:29.952235 TX OE : NO K
3540 11:38:29.952756 All Pass.
3541 11:38:29.953125
3542 11:38:29.953504 DramC Write-DBI off
3543 11:38:29.955469 PER_BANK_REFRESH: Hybrid Mode
3544 11:38:29.958358 TX_TRACKING: ON
3545 11:38:29.965567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3546 11:38:29.969183 [FAST_K] Save calibration result to emmc
3547 11:38:29.975172 dramc_set_vcore_voltage set vcore to 650000
3548 11:38:29.975597 Read voltage for 600, 5
3549 11:38:29.978394 Vio18 = 0
3550 11:38:29.978899 Vcore = 650000
3551 11:38:29.979231 Vdram = 0
3552 11:38:29.982397 Vddq = 0
3553 11:38:29.982814 Vmddr = 0
3554 11:38:29.985083 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3555 11:38:29.992552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3556 11:38:29.994658 MEM_TYPE=3, freq_sel=19
3557 11:38:29.998560 sv_algorithm_assistance_LP4_1600
3558 11:38:30.001796 ============ PULL DRAM RESETB DOWN ============
3559 11:38:30.005590 ========== PULL DRAM RESETB DOWN end =========
3560 11:38:30.008892 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3561 11:38:30.011885 ===================================
3562 11:38:30.015664 LPDDR4 DRAM CONFIGURATION
3563 11:38:30.018368 ===================================
3564 11:38:30.021352 EX_ROW_EN[0] = 0x0
3565 11:38:30.021776 EX_ROW_EN[1] = 0x0
3566 11:38:30.025380 LP4Y_EN = 0x0
3567 11:38:30.025876 WORK_FSP = 0x0
3568 11:38:30.027999 WL = 0x2
3569 11:38:30.028576 RL = 0x2
3570 11:38:30.031636 BL = 0x2
3571 11:38:30.032056 RPST = 0x0
3572 11:38:30.035718 RD_PRE = 0x0
3573 11:38:30.036216 WR_PRE = 0x1
3574 11:38:30.037982 WR_PST = 0x0
3575 11:38:30.041459 DBI_WR = 0x0
3576 11:38:30.041896 DBI_RD = 0x0
3577 11:38:30.045443 OTF = 0x1
3578 11:38:30.049891 ===================================
3579 11:38:30.051029 ===================================
3580 11:38:30.051193 ANA top config
3581 11:38:30.054709 ===================================
3582 11:38:30.057425 DLL_ASYNC_EN = 0
3583 11:38:30.057657 ALL_SLAVE_EN = 1
3584 11:38:30.060963 NEW_RANK_MODE = 1
3585 11:38:30.065261 DLL_IDLE_MODE = 1
3586 11:38:30.067997 LP45_APHY_COMB_EN = 1
3587 11:38:30.071145 TX_ODT_DIS = 1
3588 11:38:30.071376 NEW_8X_MODE = 1
3589 11:38:30.074252 ===================================
3590 11:38:30.077910 ===================================
3591 11:38:30.081369 data_rate = 1200
3592 11:38:30.084239 CKR = 1
3593 11:38:30.088705 DQ_P2S_RATIO = 8
3594 11:38:30.090762 ===================================
3595 11:38:30.094447 CA_P2S_RATIO = 8
3596 11:38:30.098518 DQ_CA_OPEN = 0
3597 11:38:30.099016 DQ_SEMI_OPEN = 0
3598 11:38:30.100877 CA_SEMI_OPEN = 0
3599 11:38:30.104643 CA_FULL_RATE = 0
3600 11:38:30.107500 DQ_CKDIV4_EN = 1
3601 11:38:30.112337 CA_CKDIV4_EN = 1
3602 11:38:30.114550 CA_PREDIV_EN = 0
3603 11:38:30.115052 PH8_DLY = 0
3604 11:38:30.117781 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3605 11:38:30.121280 DQ_AAMCK_DIV = 4
3606 11:38:30.123998 CA_AAMCK_DIV = 4
3607 11:38:30.127135 CA_ADMCK_DIV = 4
3608 11:38:30.131200 DQ_TRACK_CA_EN = 0
3609 11:38:30.135510 CA_PICK = 600
3610 11:38:30.136016 CA_MCKIO = 600
3611 11:38:30.137337 MCKIO_SEMI = 0
3612 11:38:30.140621 PLL_FREQ = 2288
3613 11:38:30.144233 DQ_UI_PI_RATIO = 32
3614 11:38:30.148325 CA_UI_PI_RATIO = 0
3615 11:38:30.150494 ===================================
3616 11:38:30.154172 ===================================
3617 11:38:30.157373 memory_type:LPDDR4
3618 11:38:30.157876 GP_NUM : 10
3619 11:38:30.160677 SRAM_EN : 1
3620 11:38:30.161097 MD32_EN : 0
3621 11:38:30.164554 ===================================
3622 11:38:30.167194 [ANA_INIT] >>>>>>>>>>>>>>
3623 11:38:30.170225 <<<<<< [CONFIGURE PHASE]: ANA_TX
3624 11:38:30.173882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3625 11:38:30.177857 ===================================
3626 11:38:30.180297 data_rate = 1200,PCW = 0X5800
3627 11:38:30.184257 ===================================
3628 11:38:30.187005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3629 11:38:30.194217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3630 11:38:30.197014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3631 11:38:30.203731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3632 11:38:30.207230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3633 11:38:30.210806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3634 11:38:30.211309 [ANA_INIT] flow start
3635 11:38:30.213790 [ANA_INIT] PLL >>>>>>>>
3636 11:38:30.216797 [ANA_INIT] PLL <<<<<<<<
3637 11:38:30.217269 [ANA_INIT] MIDPI >>>>>>>>
3638 11:38:30.220358 [ANA_INIT] MIDPI <<<<<<<<
3639 11:38:30.223488 [ANA_INIT] DLL >>>>>>>>
3640 11:38:30.223999 [ANA_INIT] flow end
3641 11:38:30.230045 ============ LP4 DIFF to SE enter ============
3642 11:38:30.234401 ============ LP4 DIFF to SE exit ============
3643 11:38:30.234918 [ANA_INIT] <<<<<<<<<<<<<
3644 11:38:30.236732 [Flow] Enable top DCM control >>>>>
3645 11:38:30.239754 [Flow] Enable top DCM control <<<<<
3646 11:38:30.243342 Enable DLL master slave shuffle
3647 11:38:30.250550 ==============================================================
3648 11:38:30.250995 Gating Mode config
3649 11:38:30.257189 ==============================================================
3650 11:38:30.260058 Config description:
3651 11:38:30.270225 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3652 11:38:30.277004 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3653 11:38:30.280354 SELPH_MODE 0: By rank 1: By Phase
3654 11:38:30.286756 ==============================================================
3655 11:38:30.290142 GAT_TRACK_EN = 1
3656 11:38:30.293235 RX_GATING_MODE = 2
3657 11:38:30.293398 RX_GATING_TRACK_MODE = 2
3658 11:38:30.297048 SELPH_MODE = 1
3659 11:38:30.299579 PICG_EARLY_EN = 1
3660 11:38:30.303205 VALID_LAT_VALUE = 1
3661 11:38:30.309274 ==============================================================
3662 11:38:30.312897 Enter into Gating configuration >>>>
3663 11:38:30.316827 Exit from Gating configuration <<<<
3664 11:38:30.319330 Enter into DVFS_PRE_config >>>>>
3665 11:38:30.329731 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3666 11:38:30.333081 Exit from DVFS_PRE_config <<<<<
3667 11:38:30.336160 Enter into PICG configuration >>>>
3668 11:38:30.339441 Exit from PICG configuration <<<<
3669 11:38:30.343454 [RX_INPUT] configuration >>>>>
3670 11:38:30.347594 [RX_INPUT] configuration <<<<<
3671 11:38:30.349479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3672 11:38:30.356794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3673 11:38:30.362828 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3674 11:38:30.369885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3675 11:38:30.373185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3676 11:38:30.380572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3677 11:38:30.383093 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3678 11:38:30.389517 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3679 11:38:30.393164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3680 11:38:30.396300 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3681 11:38:30.400511 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3682 11:38:30.406846 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3683 11:38:30.409730 ===================================
3684 11:38:30.410163 LPDDR4 DRAM CONFIGURATION
3685 11:38:30.412965 ===================================
3686 11:38:30.416485 EX_ROW_EN[0] = 0x0
3687 11:38:30.419843 EX_ROW_EN[1] = 0x0
3688 11:38:30.420403 LP4Y_EN = 0x0
3689 11:38:30.424183 WORK_FSP = 0x0
3690 11:38:30.424614 WL = 0x2
3691 11:38:30.426347 RL = 0x2
3692 11:38:30.426767 BL = 0x2
3693 11:38:30.429532 RPST = 0x0
3694 11:38:30.429956 RD_PRE = 0x0
3695 11:38:30.432677 WR_PRE = 0x1
3696 11:38:30.433058 WR_PST = 0x0
3697 11:38:30.436196 DBI_WR = 0x0
3698 11:38:30.436576 DBI_RD = 0x0
3699 11:38:30.439443 OTF = 0x1
3700 11:38:30.442326 ===================================
3701 11:38:30.446063 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3702 11:38:30.449295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3703 11:38:30.455728 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3704 11:38:30.459333 ===================================
3705 11:38:30.459770 LPDDR4 DRAM CONFIGURATION
3706 11:38:30.462398 ===================================
3707 11:38:30.465468 EX_ROW_EN[0] = 0x10
3708 11:38:30.468887 EX_ROW_EN[1] = 0x0
3709 11:38:30.469426 LP4Y_EN = 0x0
3710 11:38:30.473303 WORK_FSP = 0x0
3711 11:38:30.473690 WL = 0x2
3712 11:38:30.475291 RL = 0x2
3713 11:38:30.475704 BL = 0x2
3714 11:38:30.478741 RPST = 0x0
3715 11:38:30.479124 RD_PRE = 0x0
3716 11:38:30.482283 WR_PRE = 0x1
3717 11:38:30.482662 WR_PST = 0x0
3718 11:38:30.485324 DBI_WR = 0x0
3719 11:38:30.485710 DBI_RD = 0x0
3720 11:38:30.488778 OTF = 0x1
3721 11:38:30.491981 ===================================
3722 11:38:30.498453 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3723 11:38:30.501885 nWR fixed to 30
3724 11:38:30.505110 [ModeRegInit_LP4] CH0 RK0
3725 11:38:30.505642 [ModeRegInit_LP4] CH0 RK1
3726 11:38:30.508465 [ModeRegInit_LP4] CH1 RK0
3727 11:38:30.512353 [ModeRegInit_LP4] CH1 RK1
3728 11:38:30.512735 match AC timing 16
3729 11:38:30.518402 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3730 11:38:30.521675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3731 11:38:30.525736 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3732 11:38:30.532307 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3733 11:38:30.534982 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3734 11:38:30.535444 ==
3735 11:38:30.538759 Dram Type= 6, Freq= 0, CH_0, rank 0
3736 11:38:30.541927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3737 11:38:30.542363 ==
3738 11:38:30.548658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3739 11:38:30.554603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3740 11:38:30.559142 [CA 0] Center 35 (5~66) winsize 62
3741 11:38:30.561380 [CA 1] Center 35 (5~66) winsize 62
3742 11:38:30.564788 [CA 2] Center 34 (4~65) winsize 62
3743 11:38:30.569176 [CA 3] Center 34 (4~65) winsize 62
3744 11:38:30.572489 [CA 4] Center 33 (3~64) winsize 62
3745 11:38:30.574745 [CA 5] Center 33 (3~64) winsize 62
3746 11:38:30.575176
3747 11:38:30.577728 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3748 11:38:30.578181
3749 11:38:30.581663 [CATrainingPosCal] consider 1 rank data
3750 11:38:30.584460 u2DelayCellTimex100 = 270/100 ps
3751 11:38:30.587817 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3752 11:38:30.591417 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3753 11:38:30.594764 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3754 11:38:30.597615 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3755 11:38:30.601589 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3756 11:38:30.607932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3757 11:38:30.608437
3758 11:38:30.612064 CA PerBit enable=1, Macro0, CA PI delay=33
3759 11:38:30.612568
3760 11:38:30.615511 [CBTSetCACLKResult] CA Dly = 33
3761 11:38:30.616011 CS Dly: 4 (0~35)
3762 11:38:30.616345 ==
3763 11:38:30.617557 Dram Type= 6, Freq= 0, CH_0, rank 1
3764 11:38:30.625063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3765 11:38:30.625616 ==
3766 11:38:30.627536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3767 11:38:30.634158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3768 11:38:30.637610 [CA 0] Center 36 (6~66) winsize 61
3769 11:38:30.640873 [CA 1] Center 36 (6~66) winsize 61
3770 11:38:30.643881 [CA 2] Center 34 (4~65) winsize 62
3771 11:38:30.647050 [CA 3] Center 34 (4~65) winsize 62
3772 11:38:30.651164 [CA 4] Center 33 (3~64) winsize 62
3773 11:38:30.654614 [CA 5] Center 33 (3~64) winsize 62
3774 11:38:30.655040
3775 11:38:30.657179 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3776 11:38:30.657655
3777 11:38:30.662363 [CATrainingPosCal] consider 2 rank data
3778 11:38:30.663801 u2DelayCellTimex100 = 270/100 ps
3779 11:38:30.667295 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3780 11:38:30.670702 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3781 11:38:30.676989 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3782 11:38:30.680811 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3783 11:38:30.684699 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3784 11:38:30.687551 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3785 11:38:30.688051
3786 11:38:30.690629 CA PerBit enable=1, Macro0, CA PI delay=33
3787 11:38:30.691056
3788 11:38:30.693673 [CBTSetCACLKResult] CA Dly = 33
3789 11:38:30.694187 CS Dly: 4 (0~36)
3790 11:38:30.694520
3791 11:38:30.697881 ----->DramcWriteLeveling(PI) begin...
3792 11:38:30.700739 ==
3793 11:38:30.703467 Dram Type= 6, Freq= 0, CH_0, rank 0
3794 11:38:30.706867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3795 11:38:30.707295 ==
3796 11:38:30.709767 Write leveling (Byte 0): 32 => 32
3797 11:38:30.713701 Write leveling (Byte 1): 29 => 29
3798 11:38:30.716959 DramcWriteLeveling(PI) end<-----
3799 11:38:30.717522
3800 11:38:30.717861 ==
3801 11:38:30.720468 Dram Type= 6, Freq= 0, CH_0, rank 0
3802 11:38:30.723493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3803 11:38:30.724006 ==
3804 11:38:30.727194 [Gating] SW mode calibration
3805 11:38:30.734223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3806 11:38:30.740094 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3807 11:38:30.743178 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3808 11:38:30.746732 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3809 11:38:30.753583 0 5 8 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)
3810 11:38:30.756570 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3811 11:38:30.760434 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3812 11:38:30.766189 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3813 11:38:30.769928 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3814 11:38:30.773493 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3815 11:38:30.779750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3816 11:38:30.783009 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3817 11:38:30.786352 0 6 8 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
3818 11:38:30.792732 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3819 11:38:30.796420 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3820 11:38:30.799196 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 11:38:30.806298 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3822 11:38:30.809773 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3823 11:38:30.812331 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3824 11:38:30.819494 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3825 11:38:30.822401 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3826 11:38:30.825901 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 11:38:30.832531 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 11:38:30.837012 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 11:38:30.838636 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 11:38:30.845734 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 11:38:30.849070 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 11:38:30.852522 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 11:38:30.858730 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 11:38:30.862766 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 11:38:30.865104 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 11:38:30.868985 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 11:38:30.875435 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3838 11:38:30.879367 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3839 11:38:30.881962 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3840 11:38:30.888922 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3841 11:38:30.892428 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3842 11:38:30.895119 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3843 11:38:30.898508 Total UI for P1: 0, mck2ui 16
3844 11:38:30.902920 best dqsien dly found for B0: ( 0, 9, 10)
3845 11:38:30.906642 Total UI for P1: 0, mck2ui 16
3846 11:38:30.908080 best dqsien dly found for B1: ( 0, 9, 10)
3847 11:38:30.911920 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3848 11:38:30.918448 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3849 11:38:30.918957
3850 11:38:30.921356 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3851 11:38:30.926044 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3852 11:38:30.928490 [Gating] SW calibration Done
3853 11:38:30.928992 ==
3854 11:38:30.931613 Dram Type= 6, Freq= 0, CH_0, rank 0
3855 11:38:30.934934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3856 11:38:30.935362 ==
3857 11:38:30.938362 RX Vref Scan: 0
3858 11:38:30.938873
3859 11:38:30.939206 RX Vref 0 -> 0, step: 1
3860 11:38:30.939515
3861 11:38:30.941195 RX Delay -230 -> 252, step: 16
3862 11:38:30.944870 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3863 11:38:30.951323 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3864 11:38:30.954582 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3865 11:38:30.958193 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3866 11:38:30.961679 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3867 11:38:30.967490 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3868 11:38:30.971591 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3869 11:38:30.975053 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3870 11:38:30.977956 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3871 11:38:30.981109 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3872 11:38:30.987231 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3873 11:38:30.990657 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3874 11:38:30.993946 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3875 11:38:31.000663 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3876 11:38:31.003977 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3877 11:38:31.008035 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3878 11:38:31.008544 ==
3879 11:38:31.011006 Dram Type= 6, Freq= 0, CH_0, rank 0
3880 11:38:31.014158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3881 11:38:31.014587 ==
3882 11:38:31.017899 DQS Delay:
3883 11:38:31.018406 DQS0 = 0, DQS1 = 0
3884 11:38:31.020604 DQM Delay:
3885 11:38:31.021109 DQM0 = 40, DQM1 = 33
3886 11:38:31.021515 DQ Delay:
3887 11:38:31.024031 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3888 11:38:31.027364 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3889 11:38:31.030519 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3890 11:38:31.033777 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3891 11:38:31.034283
3892 11:38:31.034612
3893 11:38:31.036915 ==
3894 11:38:31.040411 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 11:38:31.044049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3896 11:38:31.044481 ==
3897 11:38:31.044814
3898 11:38:31.045118
3899 11:38:31.047267 TX Vref Scan disable
3900 11:38:31.047693 == TX Byte 0 ==
3901 11:38:31.053491 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3902 11:38:31.057472 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3903 11:38:31.057899 == TX Byte 1 ==
3904 11:38:31.063716 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3905 11:38:31.067385 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3906 11:38:31.067818 ==
3907 11:38:31.070688 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 11:38:31.073872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3909 11:38:31.074382 ==
3910 11:38:31.074721
3911 11:38:31.075029
3912 11:38:31.077075 TX Vref Scan disable
3913 11:38:31.080965 == TX Byte 0 ==
3914 11:38:31.083896 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3915 11:38:31.088255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3916 11:38:31.090748 == TX Byte 1 ==
3917 11:38:31.093284 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3918 11:38:31.096776 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3919 11:38:31.097274
3920 11:38:31.100373 [DATLAT]
3921 11:38:31.100878 Freq=600, CH0 RK0
3922 11:38:31.101429
3923 11:38:31.103463 DATLAT Default: 0x9
3924 11:38:31.103891 0, 0xFFFF, sum = 0
3925 11:38:31.106868 1, 0xFFFF, sum = 0
3926 11:38:31.107299 2, 0xFFFF, sum = 0
3927 11:38:31.109593 3, 0xFFFF, sum = 0
3928 11:38:31.110025 4, 0xFFFF, sum = 0
3929 11:38:31.114565 5, 0xFFFF, sum = 0
3930 11:38:31.115067 6, 0xFFFF, sum = 0
3931 11:38:31.117823 7, 0x0, sum = 1
3932 11:38:31.118259 8, 0x0, sum = 2
3933 11:38:31.120123 9, 0x0, sum = 3
3934 11:38:31.120633 10, 0x0, sum = 4
3935 11:38:31.123188 best_step = 8
3936 11:38:31.123697
3937 11:38:31.124030 ==
3938 11:38:31.126637 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 11:38:31.130399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 11:38:31.130903 ==
3941 11:38:31.133181 RX Vref Scan: 1
3942 11:38:31.133659
3943 11:38:31.133994 RX Vref 0 -> 0, step: 1
3944 11:38:31.134304
3945 11:38:31.136544 RX Delay -195 -> 252, step: 8
3946 11:38:31.136972
3947 11:38:31.140055 Set Vref, RX VrefLevel [Byte0]: 50
3948 11:38:31.143088 [Byte1]: 46
3949 11:38:31.148301
3950 11:38:31.148729 Final RX Vref Byte 0 = 50 to rank0
3951 11:38:31.150180 Final RX Vref Byte 1 = 46 to rank0
3952 11:38:31.153769 Final RX Vref Byte 0 = 50 to rank1
3953 11:38:31.156994 Final RX Vref Byte 1 = 46 to rank1==
3954 11:38:31.160228 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 11:38:31.166348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 11:38:31.166838 ==
3957 11:38:31.167179 DQS Delay:
3958 11:38:31.169907 DQS0 = 0, DQS1 = 0
3959 11:38:31.170408 DQM Delay:
3960 11:38:31.170743 DQM0 = 39, DQM1 = 30
3961 11:38:31.173350 DQ Delay:
3962 11:38:31.176845 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
3963 11:38:31.180276 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3964 11:38:31.182868 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3965 11:38:31.186421 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3966 11:38:31.186851
3967 11:38:31.187183
3968 11:38:31.193251 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3969 11:38:31.197169 CH0 RK0: MR19=808, MR18=5D5D
3970 11:38:31.203098 CH0_RK0: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
3971 11:38:31.203611
3972 11:38:31.206193 ----->DramcWriteLeveling(PI) begin...
3973 11:38:31.206705 ==
3974 11:38:31.209486 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 11:38:31.212416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3976 11:38:31.212848 ==
3977 11:38:31.216488 Write leveling (Byte 0): 29 => 29
3978 11:38:31.221589 Write leveling (Byte 1): 29 => 29
3979 11:38:31.223017 DramcWriteLeveling(PI) end<-----
3980 11:38:31.223448
3981 11:38:31.223779 ==
3982 11:38:31.226172 Dram Type= 6, Freq= 0, CH_0, rank 1
3983 11:38:31.229596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3984 11:38:31.233076 ==
3985 11:38:31.233653 [Gating] SW mode calibration
3986 11:38:31.242219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 11:38:31.246313 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3988 11:38:31.248955 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 11:38:31.255842 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 11:38:31.259298 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 0)
3991 11:38:31.262382 0 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3992 11:38:31.270904 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:38:31.272022 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:38:31.277123 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:38:31.281903 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 11:38:31.286275 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 11:38:31.288243 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 11:38:31.295639 0 6 8 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
3999 11:38:31.299420 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4000 11:38:31.301772 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:38:31.308819 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:38:31.311870 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:38:31.315206 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 11:38:31.321677 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 11:38:31.324942 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 11:38:31.329014 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4007 11:38:31.335405 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4008 11:38:31.339644 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:38:31.341940 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:38:31.348034 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:38:31.352200 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:38:31.354950 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:38:31.361945 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:38:31.365054 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:38:31.368396 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:38:31.375078 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:38:31.378658 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:38:31.381590 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:38:31.388614 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:38:31.390935 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:38:31.394990 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:38:31.401517 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4023 11:38:31.401945 Total UI for P1: 0, mck2ui 16
4024 11:38:31.405568 best dqsien dly found for B1: ( 0, 9, 6)
4025 11:38:31.411085 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 11:38:31.414494 Total UI for P1: 0, mck2ui 16
4027 11:38:31.418079 best dqsien dly found for B0: ( 0, 9, 8)
4028 11:38:31.421369 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4029 11:38:31.424720 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4030 11:38:31.425219
4031 11:38:31.427709 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4032 11:38:31.432304 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4033 11:38:31.434876 [Gating] SW calibration Done
4034 11:38:31.435304 ==
4035 11:38:31.437652 Dram Type= 6, Freq= 0, CH_0, rank 1
4036 11:38:31.441567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4037 11:38:31.442070 ==
4038 11:38:31.444460 RX Vref Scan: 0
4039 11:38:31.444885
4040 11:38:31.447905 RX Vref 0 -> 0, step: 1
4041 11:38:31.448467
4042 11:38:31.448809 RX Delay -230 -> 252, step: 16
4043 11:38:31.454808 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4044 11:38:31.457939 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4045 11:38:31.460633 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4046 11:38:31.464597 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4047 11:38:31.471184 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4048 11:38:31.473879 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4049 11:38:31.477788 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4050 11:38:31.480841 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4051 11:38:31.484273 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4052 11:38:31.490511 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4053 11:38:31.493691 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4054 11:38:31.497474 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4055 11:38:31.501026 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4056 11:38:31.507439 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4057 11:38:31.510515 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4058 11:38:31.513807 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4059 11:38:31.514315 ==
4060 11:38:31.516940 Dram Type= 6, Freq= 0, CH_0, rank 1
4061 11:38:31.520873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4062 11:38:31.523502 ==
4063 11:38:31.523931 DQS Delay:
4064 11:38:31.524268 DQS0 = 0, DQS1 = 0
4065 11:38:31.528039 DQM Delay:
4066 11:38:31.528541 DQM0 = 42, DQM1 = 31
4067 11:38:31.530610 DQ Delay:
4068 11:38:31.533575 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4069 11:38:31.534156 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4070 11:38:31.537397 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =17
4071 11:38:31.540814 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4072 11:38:31.543769
4073 11:38:31.544198
4074 11:38:31.544528 ==
4075 11:38:31.547874 Dram Type= 6, Freq= 0, CH_0, rank 1
4076 11:38:31.551017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4077 11:38:31.551499 ==
4078 11:38:31.551835
4079 11:38:31.552141
4080 11:38:31.553713 TX Vref Scan disable
4081 11:38:31.554142 == TX Byte 0 ==
4082 11:38:31.560264 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4083 11:38:31.563429 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4084 11:38:31.563869 == TX Byte 1 ==
4085 11:38:31.570419 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4086 11:38:31.573619 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4087 11:38:31.574043 ==
4088 11:38:31.577021 Dram Type= 6, Freq= 0, CH_0, rank 1
4089 11:38:31.580923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4090 11:38:31.581555 ==
4091 11:38:31.582135
4092 11:38:31.582673
4093 11:38:31.583356 TX Vref Scan disable
4094 11:38:31.586587 == TX Byte 0 ==
4095 11:38:31.590032 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4096 11:38:31.593417 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4097 11:38:31.596550 == TX Byte 1 ==
4098 11:38:31.599609 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4099 11:38:31.603440 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4100 11:38:31.606960
4101 11:38:31.607395 [DATLAT]
4102 11:38:31.607726 Freq=600, CH0 RK1
4103 11:38:31.608116
4104 11:38:31.609593 DATLAT Default: 0x8
4105 11:38:31.610018 0, 0xFFFF, sum = 0
4106 11:38:31.613200 1, 0xFFFF, sum = 0
4107 11:38:31.613820 2, 0xFFFF, sum = 0
4108 11:38:31.617153 3, 0xFFFF, sum = 0
4109 11:38:31.617631 4, 0xFFFF, sum = 0
4110 11:38:31.619490 5, 0xFFFF, sum = 0
4111 11:38:31.622871 6, 0xFFFF, sum = 0
4112 11:38:31.623302 7, 0x0, sum = 1
4113 11:38:31.623678 8, 0x0, sum = 2
4114 11:38:31.626486 9, 0x0, sum = 3
4115 11:38:31.626917 10, 0x0, sum = 4
4116 11:38:31.629740 best_step = 8
4117 11:38:31.630131
4118 11:38:31.630430 ==
4119 11:38:31.633041 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 11:38:31.636098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 11:38:31.636485 ==
4122 11:38:31.640283 RX Vref Scan: 0
4123 11:38:31.640777
4124 11:38:31.641078 RX Vref 0 -> 0, step: 1
4125 11:38:31.641426
4126 11:38:31.642761 RX Delay -195 -> 252, step: 8
4127 11:38:31.650034 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4128 11:38:31.653087 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4129 11:38:31.656442 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4130 11:38:31.660176 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4131 11:38:31.667273 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4132 11:38:31.669916 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4133 11:38:31.674418 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4134 11:38:31.677408 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4135 11:38:31.679974 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4136 11:38:31.686034 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4137 11:38:31.689816 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4138 11:38:31.693124 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4139 11:38:31.696232 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4140 11:38:31.702955 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4141 11:38:31.706206 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4142 11:38:31.709737 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4143 11:38:31.710212 ==
4144 11:38:31.712647 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 11:38:31.719646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4146 11:38:31.720076 ==
4147 11:38:31.720412 DQS Delay:
4148 11:38:31.720724 DQS0 = 0, DQS1 = 0
4149 11:38:31.722891 DQM Delay:
4150 11:38:31.723389 DQM0 = 42, DQM1 = 32
4151 11:38:31.725778 DQ Delay:
4152 11:38:31.729490 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4153 11:38:31.729880 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4154 11:38:31.732380 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4155 11:38:31.739702 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4156 11:38:31.740252
4157 11:38:31.740728
4158 11:38:31.745757 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4159 11:38:31.749018 CH0 RK1: MR19=808, MR18=6565
4160 11:38:31.757689 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4161 11:38:31.759721 [RxdqsGatingPostProcess] freq 600
4162 11:38:31.762639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4163 11:38:31.765891 Pre-setting of DQS Precalculation
4164 11:38:31.772995 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4165 11:38:31.773478 ==
4166 11:38:31.776470 Dram Type= 6, Freq= 0, CH_1, rank 0
4167 11:38:31.778947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4168 11:38:31.779435 ==
4169 11:38:31.785839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4170 11:38:31.789012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4171 11:38:31.793835 [CA 0] Center 35 (5~66) winsize 62
4172 11:38:31.797129 [CA 1] Center 35 (5~65) winsize 61
4173 11:38:31.800752 [CA 2] Center 33 (3~64) winsize 62
4174 11:38:31.803334 [CA 3] Center 33 (3~64) winsize 62
4175 11:38:31.807699 [CA 4] Center 32 (2~63) winsize 62
4176 11:38:31.810199 [CA 5] Center 33 (2~64) winsize 63
4177 11:38:31.810627
4178 11:38:31.813770 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4179 11:38:31.814198
4180 11:38:31.817640 [CATrainingPosCal] consider 1 rank data
4181 11:38:31.822029 u2DelayCellTimex100 = 270/100 ps
4182 11:38:31.823531 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4183 11:38:31.830452 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4184 11:38:31.833036 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4185 11:38:31.836646 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4186 11:38:31.840685 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4187 11:38:31.844051 CA5 delay=33 (2~64),Diff = 1 PI (9 cell)
4188 11:38:31.844514
4189 11:38:31.847258 CA PerBit enable=1, Macro0, CA PI delay=32
4190 11:38:31.847760
4191 11:38:31.849688 [CBTSetCACLKResult] CA Dly = 32
4192 11:38:31.850286 CS Dly: 4 (0~35)
4193 11:38:31.853398 ==
4194 11:38:31.856212 Dram Type= 6, Freq= 0, CH_1, rank 1
4195 11:38:31.859612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4196 11:38:31.860099 ==
4197 11:38:31.863302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4198 11:38:31.869573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4199 11:38:31.873397 [CA 0] Center 35 (5~66) winsize 62
4200 11:38:31.876369 [CA 1] Center 34 (4~65) winsize 62
4201 11:38:31.880258 [CA 2] Center 33 (3~64) winsize 62
4202 11:38:31.883495 [CA 3] Center 33 (3~64) winsize 62
4203 11:38:31.887216 [CA 4] Center 32 (2~63) winsize 62
4204 11:38:31.890484 [CA 5] Center 32 (2~63) winsize 62
4205 11:38:31.890922
4206 11:38:31.893278 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4207 11:38:31.893782
4208 11:38:31.896939 [CATrainingPosCal] consider 2 rank data
4209 11:38:31.899785 u2DelayCellTimex100 = 270/100 ps
4210 11:38:31.903567 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4211 11:38:31.909699 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4212 11:38:31.913279 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4213 11:38:31.916519 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4214 11:38:31.920198 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4215 11:38:31.924297 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4216 11:38:31.924807
4217 11:38:31.926245 CA PerBit enable=1, Macro0, CA PI delay=32
4218 11:38:31.926678
4219 11:38:31.929949 [CBTSetCACLKResult] CA Dly = 32
4220 11:38:31.932822 CS Dly: 4 (0~36)
4221 11:38:31.933199
4222 11:38:31.936295 ----->DramcWriteLeveling(PI) begin...
4223 11:38:31.936822 ==
4224 11:38:31.939611 Dram Type= 6, Freq= 0, CH_1, rank 0
4225 11:38:31.942583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4226 11:38:31.943018 ==
4227 11:38:31.946192 Write leveling (Byte 0): 29 => 29
4228 11:38:31.949387 Write leveling (Byte 1): 28 => 28
4229 11:38:31.953478 DramcWriteLeveling(PI) end<-----
4230 11:38:31.953987
4231 11:38:31.954324 ==
4232 11:38:31.955630 Dram Type= 6, Freq= 0, CH_1, rank 0
4233 11:38:31.959625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4234 11:38:31.960289 ==
4235 11:38:31.963269 [Gating] SW mode calibration
4236 11:38:31.969011 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 11:38:31.975511 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4238 11:38:31.979048 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4239 11:38:31.982793 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4240 11:38:31.989165 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4241 11:38:31.992226 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:38:31.995850 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:38:32.002680 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:38:32.005628 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 11:38:32.008735 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:38:32.016079 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:38:32.019607 0 6 4 | B1->B0 | 2323 2f2f | 1 0 | (0 0) (0 0)
4248 11:38:32.022550 0 6 8 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4249 11:38:32.029176 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:38:32.032540 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:38:32.036686 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:38:32.042202 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 11:38:32.045520 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:38:32.049185 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:38:32.055571 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:38:32.059316 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4257 11:38:32.063142 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:38:32.069002 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:38:32.072742 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:38:32.075849 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:38:32.081913 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:38:32.085097 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:38:32.088704 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:38:32.092181 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:38:32.099339 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:38:32.102045 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:38:32.105441 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:38:32.111567 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:38:32.115104 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:38:32.119387 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:38:32.125270 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4272 11:38:32.128706 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:38:32.132570 Total UI for P1: 0, mck2ui 16
4274 11:38:32.135717 best dqsien dly found for B0: ( 0, 9, 4)
4275 11:38:32.138846 Total UI for P1: 0, mck2ui 16
4276 11:38:32.142103 best dqsien dly found for B1: ( 0, 9, 6)
4277 11:38:32.145297 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4278 11:38:32.148702 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4279 11:38:32.149204
4280 11:38:32.151359 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4281 11:38:32.155282 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4282 11:38:32.158474 [Gating] SW calibration Done
4283 11:38:32.158982 ==
4284 11:38:32.161886 Dram Type= 6, Freq= 0, CH_1, rank 0
4285 11:38:32.168763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4286 11:38:32.169323 ==
4287 11:38:32.169667 RX Vref Scan: 0
4288 11:38:32.169979
4289 11:38:32.171229 RX Vref 0 -> 0, step: 1
4290 11:38:32.171657
4291 11:38:32.175260 RX Delay -230 -> 252, step: 16
4292 11:38:32.178027 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4293 11:38:32.181817 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4294 11:38:32.184579 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4295 11:38:32.191331 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4296 11:38:32.195353 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4297 11:38:32.198649 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4298 11:38:32.201287 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4299 11:38:32.205206 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4300 11:38:32.211511 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4301 11:38:32.214712 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4302 11:38:32.217598 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4303 11:38:32.220902 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4304 11:38:32.227905 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4305 11:38:32.231876 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4306 11:38:32.234633 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4307 11:38:32.238998 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4308 11:38:32.240747 ==
4309 11:38:32.241131 Dram Type= 6, Freq= 0, CH_1, rank 0
4310 11:38:32.247799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4311 11:38:32.248265 ==
4312 11:38:32.248563 DQS Delay:
4313 11:38:32.251033 DQS0 = 0, DQS1 = 0
4314 11:38:32.251433 DQM Delay:
4315 11:38:32.254221 DQM0 = 43, DQM1 = 35
4316 11:38:32.254599 DQ Delay:
4317 11:38:32.257611 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4318 11:38:32.261607 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4319 11:38:32.264729 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4320 11:38:32.267707 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4321 11:38:32.268146
4322 11:38:32.268444
4323 11:38:32.268716 ==
4324 11:38:32.271937 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 11:38:32.275597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4326 11:38:32.276166 ==
4327 11:38:32.276498
4328 11:38:32.276795
4329 11:38:32.278288 TX Vref Scan disable
4330 11:38:32.280647 == TX Byte 0 ==
4331 11:38:32.284125 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4332 11:38:32.287401 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4333 11:38:32.291720 == TX Byte 1 ==
4334 11:38:32.294076 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4335 11:38:32.297186 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4336 11:38:32.297666 ==
4337 11:38:32.300755 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 11:38:32.304015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4339 11:38:32.307238 ==
4340 11:38:32.307650
4341 11:38:32.308003
4342 11:38:32.308313 TX Vref Scan disable
4343 11:38:32.312719 == TX Byte 0 ==
4344 11:38:32.314753 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4345 11:38:32.321706 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4346 11:38:32.322244 == TX Byte 1 ==
4347 11:38:32.324600 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4348 11:38:32.332398 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4349 11:38:32.332896
4350 11:38:32.333220 [DATLAT]
4351 11:38:32.333657 Freq=600, CH1 RK0
4352 11:38:32.334024
4353 11:38:32.334666 DATLAT Default: 0x9
4354 11:38:32.334983 0, 0xFFFF, sum = 0
4355 11:38:32.337726 1, 0xFFFF, sum = 0
4356 11:38:32.341049 2, 0xFFFF, sum = 0
4357 11:38:32.341530 3, 0xFFFF, sum = 0
4358 11:38:32.344302 4, 0xFFFF, sum = 0
4359 11:38:32.344720 5, 0xFFFF, sum = 0
4360 11:38:32.347390 6, 0xFFFF, sum = 0
4361 11:38:32.347831 7, 0x0, sum = 1
4362 11:38:32.348162 8, 0x0, sum = 2
4363 11:38:32.351093 9, 0x0, sum = 3
4364 11:38:32.351632 10, 0x0, sum = 4
4365 11:38:32.354138 best_step = 8
4366 11:38:32.354551
4367 11:38:32.354871 ==
4368 11:38:32.357466 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 11:38:32.361205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 11:38:32.361826 ==
4371 11:38:32.364413 RX Vref Scan: 1
4372 11:38:32.364906
4373 11:38:32.365286 RX Vref 0 -> 0, step: 1
4374 11:38:32.365670
4375 11:38:32.367833 RX Delay -195 -> 252, step: 8
4376 11:38:32.368340
4377 11:38:32.371409 Set Vref, RX VrefLevel [Byte0]: 53
4378 11:38:32.374240 [Byte1]: 49
4379 11:38:32.378330
4380 11:38:32.378768 Final RX Vref Byte 0 = 53 to rank0
4381 11:38:32.381606 Final RX Vref Byte 1 = 49 to rank0
4382 11:38:32.385395 Final RX Vref Byte 0 = 53 to rank1
4383 11:38:32.388139 Final RX Vref Byte 1 = 49 to rank1==
4384 11:38:32.392282 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 11:38:32.399114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4386 11:38:32.399648 ==
4387 11:38:32.399987 DQS Delay:
4388 11:38:32.400291 DQS0 = 0, DQS1 = 0
4389 11:38:32.401390 DQM Delay:
4390 11:38:32.401822 DQM0 = 37, DQM1 = 30
4391 11:38:32.405026 DQ Delay:
4392 11:38:32.407970 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4393 11:38:32.411744 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4394 11:38:32.415382 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4395 11:38:32.419739 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4396 11:38:32.420239
4397 11:38:32.420568
4398 11:38:32.424937 [DQSOSCAuto] RK0, (LSB)MR18= 0x7a7a, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4399 11:38:32.428112 CH1 RK0: MR19=808, MR18=7A7A
4400 11:38:32.434721 CH1_RK0: MR19=0x808, MR18=0x7A7A, DQSOSC=387, MR23=63, INC=175, DEC=116
4401 11:38:32.435209
4402 11:38:32.439025 ----->DramcWriteLeveling(PI) begin...
4403 11:38:32.439525 ==
4404 11:38:32.441299 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 11:38:32.445185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 11:38:32.445734 ==
4407 11:38:32.447936 Write leveling (Byte 0): 28 => 28
4408 11:38:32.451184 Write leveling (Byte 1): 28 => 28
4409 11:38:32.454430 DramcWriteLeveling(PI) end<-----
4410 11:38:32.454859
4411 11:38:32.455188 ==
4412 11:38:32.458081 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 11:38:32.461089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4414 11:38:32.461624 ==
4415 11:38:32.464410 [Gating] SW mode calibration
4416 11:38:32.470943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 11:38:32.477699 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4418 11:38:32.480660 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 11:38:32.487616 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4420 11:38:32.490872 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4421 11:38:32.493997 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:38:32.501031 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:38:32.504642 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:38:32.507352 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:38:32.513915 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:38:32.517327 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:38:32.520990 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
4428 11:38:32.527651 0 6 8 | B1->B0 | 3333 4242 | 1 0 | (0 0) (0 0)
4429 11:38:32.531296 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:38:32.533841 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:38:32.540856 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:38:32.544045 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:38:32.546855 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:38:32.554225 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:38:32.557406 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4436 11:38:32.560739 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4437 11:38:32.563783 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:38:32.570998 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:38:32.573352 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:38:32.577518 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:38:32.583369 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:38:32.586761 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:38:32.593343 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:38:32.597484 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:38:32.600036 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:38:32.604009 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:38:32.609770 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:38:32.613949 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:38:32.616630 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:38:32.623777 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:38:32.626791 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4452 11:38:32.629937 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4453 11:38:32.633945 Total UI for P1: 0, mck2ui 16
4454 11:38:32.636600 best dqsien dly found for B0: ( 0, 9, 4)
4455 11:38:32.643571 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:38:32.644082 Total UI for P1: 0, mck2ui 16
4457 11:38:32.650382 best dqsien dly found for B1: ( 0, 9, 8)
4458 11:38:32.654053 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4459 11:38:32.656115 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4460 11:38:32.656541
4461 11:38:32.659617 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4462 11:38:32.663214 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4463 11:38:32.667210 [Gating] SW calibration Done
4464 11:38:32.667715 ==
4465 11:38:32.669923 Dram Type= 6, Freq= 0, CH_1, rank 1
4466 11:38:32.673506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4467 11:38:32.674012 ==
4468 11:38:32.676429 RX Vref Scan: 0
4469 11:38:32.676931
4470 11:38:32.677326 RX Vref 0 -> 0, step: 1
4471 11:38:32.677652
4472 11:38:32.679452 RX Delay -230 -> 252, step: 16
4473 11:38:32.686787 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4474 11:38:32.689744 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4475 11:38:32.692371 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4476 11:38:32.696016 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4477 11:38:32.699317 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4478 11:38:32.705907 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4479 11:38:32.709298 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4480 11:38:32.712570 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4481 11:38:32.715779 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4482 11:38:32.723111 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4483 11:38:32.726025 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4484 11:38:32.728857 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4485 11:38:32.732678 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4486 11:38:32.738586 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4487 11:38:32.742657 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4488 11:38:32.745586 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4489 11:38:32.746018 ==
4490 11:38:32.748648 Dram Type= 6, Freq= 0, CH_1, rank 1
4491 11:38:32.752855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4492 11:38:32.755912 ==
4493 11:38:32.756335 DQS Delay:
4494 11:38:32.756662 DQS0 = 0, DQS1 = 0
4495 11:38:32.758864 DQM Delay:
4496 11:38:32.759282 DQM0 = 40, DQM1 = 32
4497 11:38:32.762448 DQ Delay:
4498 11:38:32.763074 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4499 11:38:32.765190 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4500 11:38:32.769000 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4501 11:38:32.772503 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4502 11:38:32.775155
4503 11:38:32.775578
4504 11:38:32.775900 ==
4505 11:38:32.778534 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 11:38:32.781806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 11:38:32.782192 ==
4508 11:38:32.782483
4509 11:38:32.782750
4510 11:38:32.785786 TX Vref Scan disable
4511 11:38:32.786428 == TX Byte 0 ==
4512 11:38:32.791886 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 11:38:32.795423 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 11:38:32.795886 == TX Byte 1 ==
4515 11:38:32.801216 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 11:38:32.805121 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 11:38:32.805558 ==
4518 11:38:32.808181 Dram Type= 6, Freq= 0, CH_1, rank 1
4519 11:38:32.811110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4520 11:38:32.811496 ==
4521 11:38:32.811791
4522 11:38:32.812066
4523 11:38:32.814383 TX Vref Scan disable
4524 11:38:32.818276 == TX Byte 0 ==
4525 11:38:32.821093 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4526 11:38:32.828860 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4527 11:38:32.829375 == TX Byte 1 ==
4528 11:38:32.830941 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4529 11:38:32.838309 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4530 11:38:32.838694
4531 11:38:32.838995 [DATLAT]
4532 11:38:32.839270 Freq=600, CH1 RK1
4533 11:38:32.839537
4534 11:38:32.841059 DATLAT Default: 0x8
4535 11:38:32.844880 0, 0xFFFF, sum = 0
4536 11:38:32.845321 1, 0xFFFF, sum = 0
4537 11:38:32.847846 2, 0xFFFF, sum = 0
4538 11:38:32.848230 3, 0xFFFF, sum = 0
4539 11:38:32.852400 4, 0xFFFF, sum = 0
4540 11:38:32.853466 5, 0xFFFF, sum = 0
4541 11:38:32.854402 6, 0xFFFF, sum = 0
4542 11:38:32.854752 7, 0x0, sum = 1
4543 11:38:32.857527 8, 0x0, sum = 2
4544 11:38:32.857913 9, 0x0, sum = 3
4545 11:38:32.858220 10, 0x0, sum = 4
4546 11:38:32.860708 best_step = 8
4547 11:38:32.861101
4548 11:38:32.861480 ==
4549 11:38:32.864041 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 11:38:32.867570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 11:38:32.868046 ==
4552 11:38:32.871529 RX Vref Scan: 0
4553 11:38:32.871990
4554 11:38:32.872290 RX Vref 0 -> 0, step: 1
4555 11:38:32.874652
4556 11:38:32.875032 RX Delay -195 -> 252, step: 8
4557 11:38:32.881958 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4558 11:38:32.885636 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4559 11:38:32.888869 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4560 11:38:32.891672 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4561 11:38:32.898310 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4562 11:38:32.901767 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4563 11:38:32.905053 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4564 11:38:32.907923 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4565 11:38:32.911660 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4566 11:38:32.918738 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4567 11:38:32.921479 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4568 11:38:32.924929 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4569 11:38:32.928633 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4570 11:38:32.935007 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4571 11:38:32.937942 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4572 11:38:32.941697 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4573 11:38:32.942224 ==
4574 11:38:32.944940 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 11:38:32.951533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4576 11:38:32.952052 ==
4577 11:38:32.952387 DQS Delay:
4578 11:38:32.952693 DQS0 = 0, DQS1 = 0
4579 11:38:32.954895 DQM Delay:
4580 11:38:32.955338 DQM0 = 37, DQM1 = 29
4581 11:38:32.957791 DQ Delay:
4582 11:38:32.961530 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4583 11:38:32.962038 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4584 11:38:32.964762 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4585 11:38:32.971270 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4586 11:38:32.971778
4587 11:38:32.972115
4588 11:38:32.977867 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4589 11:38:32.981255 CH1 RK1: MR19=808, MR18=5D5D
4590 11:38:32.988744 CH1_RK1: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4591 11:38:32.991227 [RxdqsGatingPostProcess] freq 600
4592 11:38:32.994201 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4593 11:38:32.998013 Pre-setting of DQS Precalculation
4594 11:38:33.004903 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4595 11:38:33.011359 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4596 11:38:33.017654 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4597 11:38:33.018174
4598 11:38:33.018508
4599 11:38:33.020871 [Calibration Summary] 1200 Mbps
4600 11:38:33.021421 CH 0, Rank 0
4601 11:38:33.024010 SW Impedance : PASS
4602 11:38:33.027897 DUTY Scan : NO K
4603 11:38:33.028325 ZQ Calibration : PASS
4604 11:38:33.030892 Jitter Meter : NO K
4605 11:38:33.034621 CBT Training : PASS
4606 11:38:33.035126 Write leveling : PASS
4607 11:38:33.037624 RX DQS gating : PASS
4608 11:38:33.041412 RX DQ/DQS(RDDQC) : PASS
4609 11:38:33.041916 TX DQ/DQS : PASS
4610 11:38:33.044332 RX DATLAT : PASS
4611 11:38:33.047204 RX DQ/DQS(Engine): PASS
4612 11:38:33.047634 TX OE : NO K
4613 11:38:33.047967 All Pass.
4614 11:38:33.050588
4615 11:38:33.051016 CH 0, Rank 1
4616 11:38:33.053681 SW Impedance : PASS
4617 11:38:33.054106 DUTY Scan : NO K
4618 11:38:33.057330 ZQ Calibration : PASS
4619 11:38:33.057890 Jitter Meter : NO K
4620 11:38:33.060241 CBT Training : PASS
4621 11:38:33.064035 Write leveling : PASS
4622 11:38:33.064531 RX DQS gating : PASS
4623 11:38:33.066830 RX DQ/DQS(RDDQC) : PASS
4624 11:38:33.070534 TX DQ/DQS : PASS
4625 11:38:33.070969 RX DATLAT : PASS
4626 11:38:33.074329 RX DQ/DQS(Engine): PASS
4627 11:38:33.077485 TX OE : NO K
4628 11:38:33.078153 All Pass.
4629 11:38:33.078679
4630 11:38:33.079003 CH 1, Rank 0
4631 11:38:33.081948 SW Impedance : PASS
4632 11:38:33.083589 DUTY Scan : NO K
4633 11:38:33.084009 ZQ Calibration : PASS
4634 11:38:33.087447 Jitter Meter : NO K
4635 11:38:33.091441 CBT Training : PASS
4636 11:38:33.091915 Write leveling : PASS
4637 11:38:33.094653 RX DQS gating : PASS
4638 11:38:33.096918 RX DQ/DQS(RDDQC) : PASS
4639 11:38:33.097376 TX DQ/DQS : PASS
4640 11:38:33.100447 RX DATLAT : PASS
4641 11:38:33.100945 RX DQ/DQS(Engine): PASS
4642 11:38:33.104157 TX OE : NO K
4643 11:38:33.104652 All Pass.
4644 11:38:33.104981
4645 11:38:33.106838 CH 1, Rank 1
4646 11:38:33.107261 SW Impedance : PASS
4647 11:38:33.111149 DUTY Scan : NO K
4648 11:38:33.113764 ZQ Calibration : PASS
4649 11:38:33.114199 Jitter Meter : NO K
4650 11:38:33.116776 CBT Training : PASS
4651 11:38:33.120294 Write leveling : PASS
4652 11:38:33.120772 RX DQS gating : PASS
4653 11:38:33.123739 RX DQ/DQS(RDDQC) : PASS
4654 11:38:33.127172 TX DQ/DQS : PASS
4655 11:38:33.127596 RX DATLAT : PASS
4656 11:38:33.130449 RX DQ/DQS(Engine): PASS
4657 11:38:33.133530 TX OE : NO K
4658 11:38:33.133976 All Pass.
4659 11:38:33.134306
4660 11:38:33.137004 DramC Write-DBI off
4661 11:38:33.137572 PER_BANK_REFRESH: Hybrid Mode
4662 11:38:33.140304 TX_TRACKING: ON
4663 11:38:33.147064 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4664 11:38:33.153748 [FAST_K] Save calibration result to emmc
4665 11:38:33.156813 dramc_set_vcore_voltage set vcore to 662500
4666 11:38:33.157279 Read voltage for 933, 3
4667 11:38:33.159853 Vio18 = 0
4668 11:38:33.160274 Vcore = 662500
4669 11:38:33.160600 Vdram = 0
4670 11:38:33.163110 Vddq = 0
4671 11:38:33.163536 Vmddr = 0
4672 11:38:33.166958 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4673 11:38:33.173560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4674 11:38:33.176968 MEM_TYPE=3, freq_sel=17
4675 11:38:33.180120 sv_algorithm_assistance_LP4_1600
4676 11:38:33.183398 ============ PULL DRAM RESETB DOWN ============
4677 11:38:33.187651 ========== PULL DRAM RESETB DOWN end =========
4678 11:38:33.189819 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4679 11:38:33.193214 ===================================
4680 11:38:33.197868 LPDDR4 DRAM CONFIGURATION
4681 11:38:33.199824 ===================================
4682 11:38:33.203101 EX_ROW_EN[0] = 0x0
4683 11:38:33.203524 EX_ROW_EN[1] = 0x0
4684 11:38:33.206472 LP4Y_EN = 0x0
4685 11:38:33.206973 WORK_FSP = 0x0
4686 11:38:33.209732 WL = 0x3
4687 11:38:33.210158 RL = 0x3
4688 11:38:33.212631 BL = 0x2
4689 11:38:33.213051 RPST = 0x0
4690 11:38:33.215787 RD_PRE = 0x0
4691 11:38:33.219445 WR_PRE = 0x1
4692 11:38:33.219585 WR_PST = 0x0
4693 11:38:33.223300 DBI_WR = 0x0
4694 11:38:33.223452 DBI_RD = 0x0
4695 11:38:33.226269 OTF = 0x1
4696 11:38:33.229549 ===================================
4697 11:38:33.232797 ===================================
4698 11:38:33.232931 ANA top config
4699 11:38:33.236314 ===================================
4700 11:38:33.239075 DLL_ASYNC_EN = 0
4701 11:38:33.242593 ALL_SLAVE_EN = 1
4702 11:38:33.242749 NEW_RANK_MODE = 1
4703 11:38:33.246211 DLL_IDLE_MODE = 1
4704 11:38:33.248963 LP45_APHY_COMB_EN = 1
4705 11:38:33.253039 TX_ODT_DIS = 1
4706 11:38:33.253215 NEW_8X_MODE = 1
4707 11:38:33.256093 ===================================
4708 11:38:33.259378 ===================================
4709 11:38:33.262415 data_rate = 1866
4710 11:38:33.266251 CKR = 1
4711 11:38:33.269744 DQ_P2S_RATIO = 8
4712 11:38:33.272877 ===================================
4713 11:38:33.275818 CA_P2S_RATIO = 8
4714 11:38:33.279023 DQ_CA_OPEN = 0
4715 11:38:33.279334 DQ_SEMI_OPEN = 0
4716 11:38:33.283598 CA_SEMI_OPEN = 0
4717 11:38:33.286448 CA_FULL_RATE = 0
4718 11:38:33.289430 DQ_CKDIV4_EN = 1
4719 11:38:33.293212 CA_CKDIV4_EN = 1
4720 11:38:33.296536 CA_PREDIV_EN = 0
4721 11:38:33.297035 PH8_DLY = 0
4722 11:38:33.300575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4723 11:38:33.303344 DQ_AAMCK_DIV = 4
4724 11:38:33.305777 CA_AAMCK_DIV = 4
4725 11:38:33.310179 CA_ADMCK_DIV = 4
4726 11:38:33.312668 DQ_TRACK_CA_EN = 0
4727 11:38:33.313174 CA_PICK = 933
4728 11:38:33.316482 CA_MCKIO = 933
4729 11:38:33.319261 MCKIO_SEMI = 0
4730 11:38:33.322290 PLL_FREQ = 3732
4731 11:38:33.326575 DQ_UI_PI_RATIO = 32
4732 11:38:33.329155 CA_UI_PI_RATIO = 0
4733 11:38:33.332573 ===================================
4734 11:38:33.336071 ===================================
4735 11:38:33.339502 memory_type:LPDDR4
4736 11:38:33.340008 GP_NUM : 10
4737 11:38:33.342568 SRAM_EN : 1
4738 11:38:33.342991 MD32_EN : 0
4739 11:38:33.346210 ===================================
4740 11:38:33.349175 [ANA_INIT] >>>>>>>>>>>>>>
4741 11:38:33.353170 <<<<<< [CONFIGURE PHASE]: ANA_TX
4742 11:38:33.355811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4743 11:38:33.359581 ===================================
4744 11:38:33.362235 data_rate = 1866,PCW = 0X8f00
4745 11:38:33.365598 ===================================
4746 11:38:33.368842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4747 11:38:33.372683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4748 11:38:33.379085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4749 11:38:33.385478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4750 11:38:33.388753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4751 11:38:33.392019 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4752 11:38:33.392447 [ANA_INIT] flow start
4753 11:38:33.395296 [ANA_INIT] PLL >>>>>>>>
4754 11:38:33.398511 [ANA_INIT] PLL <<<<<<<<
4755 11:38:33.399024 [ANA_INIT] MIDPI >>>>>>>>
4756 11:38:33.401837 [ANA_INIT] MIDPI <<<<<<<<
4757 11:38:33.405274 [ANA_INIT] DLL >>>>>>>>
4758 11:38:33.405784 [ANA_INIT] flow end
4759 11:38:33.411748 ============ LP4 DIFF to SE enter ============
4760 11:38:33.415106 ============ LP4 DIFF to SE exit ============
4761 11:38:33.418621 [ANA_INIT] <<<<<<<<<<<<<
4762 11:38:33.422421 [Flow] Enable top DCM control >>>>>
4763 11:38:33.425645 [Flow] Enable top DCM control <<<<<
4764 11:38:33.426148 Enable DLL master slave shuffle
4765 11:38:33.432032 ==============================================================
4766 11:38:33.435205 Gating Mode config
4767 11:38:33.438652 ==============================================================
4768 11:38:33.441767 Config description:
4769 11:38:33.452000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4770 11:38:33.457887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4771 11:38:33.461154 SELPH_MODE 0: By rank 1: By Phase
4772 11:38:33.468064 ==============================================================
4773 11:38:33.471540 GAT_TRACK_EN = 1
4774 11:38:33.474793 RX_GATING_MODE = 2
4775 11:38:33.478188 RX_GATING_TRACK_MODE = 2
4776 11:38:33.481669 SELPH_MODE = 1
4777 11:38:33.482113 PICG_EARLY_EN = 1
4778 11:38:33.484621 VALID_LAT_VALUE = 1
4779 11:38:33.491564 ==============================================================
4780 11:38:33.494947 Enter into Gating configuration >>>>
4781 11:38:33.498193 Exit from Gating configuration <<<<
4782 11:38:33.501485 Enter into DVFS_PRE_config >>>>>
4783 11:38:33.511646 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4784 11:38:33.514990 Exit from DVFS_PRE_config <<<<<
4785 11:38:33.518153 Enter into PICG configuration >>>>
4786 11:38:33.521549 Exit from PICG configuration <<<<
4787 11:38:33.524762 [RX_INPUT] configuration >>>>>
4788 11:38:33.528257 [RX_INPUT] configuration <<<<<
4789 11:38:33.531450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4790 11:38:33.537682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4791 11:38:33.545381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4792 11:38:33.551582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4793 11:38:33.558110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4794 11:38:33.560852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4795 11:38:33.567721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4796 11:38:33.570878 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4797 11:38:33.575906 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4798 11:38:33.577573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4799 11:38:33.584177 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4800 11:38:33.587445 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4801 11:38:33.590438 ===================================
4802 11:38:33.594121 LPDDR4 DRAM CONFIGURATION
4803 11:38:33.597578 ===================================
4804 11:38:33.598089 EX_ROW_EN[0] = 0x0
4805 11:38:33.601176 EX_ROW_EN[1] = 0x0
4806 11:38:33.601727 LP4Y_EN = 0x0
4807 11:38:33.603564 WORK_FSP = 0x0
4808 11:38:33.603990 WL = 0x3
4809 11:38:33.607304 RL = 0x3
4810 11:38:33.607811 BL = 0x2
4811 11:38:33.610989 RPST = 0x0
4812 11:38:33.613856 RD_PRE = 0x0
4813 11:38:33.614279 WR_PRE = 0x1
4814 11:38:33.617040 WR_PST = 0x0
4815 11:38:33.617499 DBI_WR = 0x0
4816 11:38:33.621113 DBI_RD = 0x0
4817 11:38:33.621673 OTF = 0x1
4818 11:38:33.624050 ===================================
4819 11:38:33.626804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4820 11:38:33.634061 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4821 11:38:33.637551 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4822 11:38:33.640788 ===================================
4823 11:38:33.643949 LPDDR4 DRAM CONFIGURATION
4824 11:38:33.647336 ===================================
4825 11:38:33.647886 EX_ROW_EN[0] = 0x10
4826 11:38:33.650086 EX_ROW_EN[1] = 0x0
4827 11:38:33.650510 LP4Y_EN = 0x0
4828 11:38:33.653515 WORK_FSP = 0x0
4829 11:38:33.654027 WL = 0x3
4830 11:38:33.656489 RL = 0x3
4831 11:38:33.656913 BL = 0x2
4832 11:38:33.660226 RPST = 0x0
4833 11:38:33.663769 RD_PRE = 0x0
4834 11:38:33.664276 WR_PRE = 0x1
4835 11:38:33.666495 WR_PST = 0x0
4836 11:38:33.666916 DBI_WR = 0x0
4837 11:38:33.670847 DBI_RD = 0x0
4838 11:38:33.671352 OTF = 0x1
4839 11:38:33.673449 ===================================
4840 11:38:33.679918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4841 11:38:33.683539 nWR fixed to 30
4842 11:38:33.687166 [ModeRegInit_LP4] CH0 RK0
4843 11:38:33.687669 [ModeRegInit_LP4] CH0 RK1
4844 11:38:33.690031 [ModeRegInit_LP4] CH1 RK0
4845 11:38:33.694307 [ModeRegInit_LP4] CH1 RK1
4846 11:38:33.694728 match AC timing 8
4847 11:38:33.700436 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4848 11:38:33.704415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4849 11:38:33.707373 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4850 11:38:33.713740 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4851 11:38:33.716868 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4852 11:38:33.717397 ==
4853 11:38:33.720562 Dram Type= 6, Freq= 0, CH_0, rank 0
4854 11:38:33.723462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4855 11:38:33.723891 ==
4856 11:38:33.730424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4857 11:38:33.737095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4858 11:38:33.741060 [CA 0] Center 39 (8~70) winsize 63
4859 11:38:33.743561 [CA 1] Center 38 (8~69) winsize 62
4860 11:38:33.746736 [CA 2] Center 36 (6~67) winsize 62
4861 11:38:33.750095 [CA 3] Center 36 (6~67) winsize 62
4862 11:38:33.753704 [CA 4] Center 35 (4~66) winsize 63
4863 11:38:33.756877 [CA 5] Center 34 (4~65) winsize 62
4864 11:38:33.757423
4865 11:38:33.759668 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4866 11:38:33.760090
4867 11:38:33.763767 [CATrainingPosCal] consider 1 rank data
4868 11:38:33.766903 u2DelayCellTimex100 = 270/100 ps
4869 11:38:33.770428 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4870 11:38:33.773073 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4871 11:38:33.776917 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4872 11:38:33.779949 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4873 11:38:33.782856 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
4874 11:38:33.789441 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4875 11:38:33.789867
4876 11:38:33.792849 CA PerBit enable=1, Macro0, CA PI delay=34
4877 11:38:33.793321
4878 11:38:33.796226 [CBTSetCACLKResult] CA Dly = 34
4879 11:38:33.796644 CS Dly: 7 (0~38)
4880 11:38:33.796973 ==
4881 11:38:33.799742 Dram Type= 6, Freq= 0, CH_0, rank 1
4882 11:38:33.802706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4883 11:38:33.806418 ==
4884 11:38:33.810035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4885 11:38:33.816614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4886 11:38:33.819333 [CA 0] Center 38 (8~69) winsize 62
4887 11:38:33.822561 [CA 1] Center 38 (8~69) winsize 62
4888 11:38:33.825888 [CA 2] Center 36 (6~67) winsize 62
4889 11:38:33.829219 [CA 3] Center 35 (5~66) winsize 62
4890 11:38:33.832926 [CA 4] Center 34 (3~65) winsize 63
4891 11:38:33.835709 [CA 5] Center 34 (4~65) winsize 62
4892 11:38:33.836091
4893 11:38:33.839519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4894 11:38:33.839902
4895 11:38:33.842780 [CATrainingPosCal] consider 2 rank data
4896 11:38:33.846529 u2DelayCellTimex100 = 270/100 ps
4897 11:38:33.849145 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4898 11:38:33.853058 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4899 11:38:33.856179 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4900 11:38:33.862768 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4901 11:38:33.865846 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4902 11:38:33.869488 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4903 11:38:33.869950
4904 11:38:33.872490 CA PerBit enable=1, Macro0, CA PI delay=34
4905 11:38:33.872965
4906 11:38:33.875740 [CBTSetCACLKResult] CA Dly = 34
4907 11:38:33.876122 CS Dly: 7 (0~38)
4908 11:38:33.876418
4909 11:38:33.879138 ----->DramcWriteLeveling(PI) begin...
4910 11:38:33.882356 ==
4911 11:38:33.882758 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 11:38:33.888869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 11:38:33.889333 ==
4914 11:38:33.892562 Write leveling (Byte 0): 30 => 30
4915 11:38:33.895554 Write leveling (Byte 1): 28 => 28
4916 11:38:33.899001 DramcWriteLeveling(PI) end<-----
4917 11:38:33.899428
4918 11:38:33.899761 ==
4919 11:38:33.902166 Dram Type= 6, Freq= 0, CH_0, rank 0
4920 11:38:33.905217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4921 11:38:33.905797 ==
4922 11:38:33.908698 [Gating] SW mode calibration
4923 11:38:33.915136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4924 11:38:33.922891 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4925 11:38:33.926830 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4926 11:38:33.930030 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4927 11:38:33.935704 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4928 11:38:33.938500 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4929 11:38:33.942434 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4930 11:38:33.948157 0 10 20 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
4931 11:38:33.951939 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4932 11:38:33.955362 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 11:38:33.958174 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4934 11:38:33.964953 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4935 11:38:33.968323 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4936 11:38:33.971801 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4937 11:38:33.979087 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4938 11:38:33.981307 0 11 20 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
4939 11:38:33.984674 0 11 24 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4940 11:38:33.992052 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 11:38:33.994848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 11:38:34.001756 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 11:38:34.004646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4944 11:38:34.007750 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4945 11:38:34.011023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4946 11:38:34.018122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4947 11:38:34.021332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4948 11:38:34.024309 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 11:38:34.030754 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 11:38:34.034533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 11:38:34.037628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 11:38:34.044081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 11:38:34.047200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 11:38:34.050717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 11:38:34.057184 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 11:38:34.060590 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 11:38:34.064414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 11:38:34.070922 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 11:38:34.074080 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4960 11:38:34.077030 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4961 11:38:34.084144 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4962 11:38:34.088504 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4963 11:38:34.090670 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4964 11:38:34.093624 Total UI for P1: 0, mck2ui 16
4965 11:38:34.097591 best dqsien dly found for B0: ( 0, 14, 20)
4966 11:38:34.100185 Total UI for P1: 0, mck2ui 16
4967 11:38:34.104578 best dqsien dly found for B1: ( 0, 14, 20)
4968 11:38:34.107787 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4969 11:38:34.110363 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4970 11:38:34.114528
4971 11:38:34.117100 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4972 11:38:34.120446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4973 11:38:34.124382 [Gating] SW calibration Done
4974 11:38:34.124840 ==
4975 11:38:34.127677 Dram Type= 6, Freq= 0, CH_0, rank 0
4976 11:38:34.130015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4977 11:38:34.130399 ==
4978 11:38:34.130696 RX Vref Scan: 0
4979 11:38:34.133203
4980 11:38:34.133662 RX Vref 0 -> 0, step: 1
4981 11:38:34.134060
4982 11:38:34.136867 RX Delay -80 -> 252, step: 8
4983 11:38:34.140563 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4984 11:38:34.143210 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4985 11:38:34.149961 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4986 11:38:34.153092 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4987 11:38:34.156483 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4988 11:38:34.161060 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4989 11:38:34.163942 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4990 11:38:34.167059 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4991 11:38:34.172908 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4992 11:38:34.176910 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4993 11:38:34.179833 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4994 11:38:34.183203 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4995 11:38:34.186373 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
4996 11:38:34.193814 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4997 11:38:34.196543 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4998 11:38:34.200199 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4999 11:38:34.200720 ==
5000 11:38:34.203251 Dram Type= 6, Freq= 0, CH_0, rank 0
5001 11:38:34.206431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5002 11:38:34.206876 ==
5003 11:38:34.209681 DQS Delay:
5004 11:38:34.210121 DQS0 = 0, DQS1 = 0
5005 11:38:34.213522 DQM Delay:
5006 11:38:34.213961 DQM0 = 95, DQM1 = 86
5007 11:38:34.214390 DQ Delay:
5008 11:38:34.216439 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5009 11:38:34.220031 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5010 11:38:34.222747 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5011 11:38:34.226748 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =91
5012 11:38:34.227271
5013 11:38:34.227711
5014 11:38:34.229413 ==
5015 11:38:34.233112 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 11:38:34.236348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 11:38:34.236877 ==
5018 11:38:34.237427
5019 11:38:34.237844
5020 11:38:34.239424 TX Vref Scan disable
5021 11:38:34.239867 == TX Byte 0 ==
5022 11:38:34.247973 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5023 11:38:34.249361 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5024 11:38:34.249806 == TX Byte 1 ==
5025 11:38:34.256277 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5026 11:38:34.259627 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5027 11:38:34.260153 ==
5028 11:38:34.262206 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 11:38:34.265789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5030 11:38:34.266233 ==
5031 11:38:34.266670
5032 11:38:34.267075
5033 11:38:34.269565 TX Vref Scan disable
5034 11:38:34.272665 == TX Byte 0 ==
5035 11:38:34.275667 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5036 11:38:34.279655 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5037 11:38:34.283280 == TX Byte 1 ==
5038 11:38:34.285924 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5039 11:38:34.289144 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5040 11:38:34.289614
5041 11:38:34.292605 [DATLAT]
5042 11:38:34.293057 Freq=933, CH0 RK0
5043 11:38:34.293449
5044 11:38:34.296588 DATLAT Default: 0xd
5045 11:38:34.297015 0, 0xFFFF, sum = 0
5046 11:38:34.299257 1, 0xFFFF, sum = 0
5047 11:38:34.299769 2, 0xFFFF, sum = 0
5048 11:38:34.302683 3, 0xFFFF, sum = 0
5049 11:38:34.303202 4, 0xFFFF, sum = 0
5050 11:38:34.305790 5, 0xFFFF, sum = 0
5051 11:38:34.306222 6, 0xFFFF, sum = 0
5052 11:38:34.309703 7, 0xFFFF, sum = 0
5053 11:38:34.310222 8, 0xFFFF, sum = 0
5054 11:38:34.312159 9, 0xFFFF, sum = 0
5055 11:38:34.312674 10, 0x0, sum = 1
5056 11:38:34.315975 11, 0x0, sum = 2
5057 11:38:34.316497 12, 0x0, sum = 3
5058 11:38:34.318752 13, 0x0, sum = 4
5059 11:38:34.319186 best_step = 11
5060 11:38:34.319517
5061 11:38:34.319825 ==
5062 11:38:34.322493 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 11:38:34.329023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5064 11:38:34.329599 ==
5065 11:38:34.329993 RX Vref Scan: 1
5066 11:38:34.330309
5067 11:38:34.332435 RX Vref 0 -> 0, step: 1
5068 11:38:34.332867
5069 11:38:34.335621 RX Delay -61 -> 252, step: 4
5070 11:38:34.336131
5071 11:38:34.338739 Set Vref, RX VrefLevel [Byte0]: 50
5072 11:38:34.343004 [Byte1]: 46
5073 11:38:34.343515
5074 11:38:34.345520 Final RX Vref Byte 0 = 50 to rank0
5075 11:38:34.348868 Final RX Vref Byte 1 = 46 to rank0
5076 11:38:34.352437 Final RX Vref Byte 0 = 50 to rank1
5077 11:38:34.355873 Final RX Vref Byte 1 = 46 to rank1==
5078 11:38:34.358696 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 11:38:34.362523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5080 11:38:34.362973 ==
5081 11:38:34.365586 DQS Delay:
5082 11:38:34.366099 DQS0 = 0, DQS1 = 0
5083 11:38:34.366433 DQM Delay:
5084 11:38:34.368540 DQM0 = 97, DQM1 = 86
5085 11:38:34.368967 DQ Delay:
5086 11:38:34.372172 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5087 11:38:34.376211 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =102
5088 11:38:34.379842 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5089 11:38:34.383263 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5090 11:38:34.383692
5091 11:38:34.384031
5092 11:38:34.392496 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5093 11:38:34.394923 CH0 RK0: MR19=505, MR18=2121
5094 11:38:34.402115 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5095 11:38:34.402647
5096 11:38:34.406640 ----->DramcWriteLeveling(PI) begin...
5097 11:38:34.407158 ==
5098 11:38:34.407959 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 11:38:34.411820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 11:38:34.412350 ==
5101 11:38:34.415176 Write leveling (Byte 0): 30 => 30
5102 11:38:34.418496 Write leveling (Byte 1): 25 => 25
5103 11:38:34.421789 DramcWriteLeveling(PI) end<-----
5104 11:38:34.422333
5105 11:38:34.422775 ==
5106 11:38:34.425071 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 11:38:34.428811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5108 11:38:34.429383 ==
5109 11:38:34.431445 [Gating] SW mode calibration
5110 11:38:34.438009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5111 11:38:34.444525 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5112 11:38:34.448143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:38:34.451059 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:38:34.458768 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:38:34.461588 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:38:34.464460 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:38:34.471196 0 10 20 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 0)
5118 11:38:34.474680 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5119 11:38:34.477968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:38:34.484593 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:38:34.489179 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:38:34.490835 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:38:34.498127 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:38:34.501439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:38:34.504300 0 11 20 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
5126 11:38:34.511429 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5127 11:38:34.514453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:38:34.517472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:38:34.524294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:38:34.528610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:38:34.531497 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:38:34.537920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:38:34.540775 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5134 11:38:34.544816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 11:38:34.550572 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:38:34.554447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:38:34.557857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:38:34.564562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:38:34.567782 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:38:34.570943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:38:34.573713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:38:34.580932 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:38:34.584441 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:38:34.587052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:38:34.593790 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:38:34.597853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:38:34.601053 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:38:34.607514 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:38:34.610806 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5150 11:38:34.613503 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:38:34.616770 Total UI for P1: 0, mck2ui 16
5152 11:38:34.621164 best dqsien dly found for B0: ( 0, 14, 20)
5153 11:38:34.623487 Total UI for P1: 0, mck2ui 16
5154 11:38:34.626491 best dqsien dly found for B1: ( 0, 14, 20)
5155 11:38:34.630089 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5156 11:38:34.637127 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5157 11:38:34.637680
5158 11:38:34.640484 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5159 11:38:34.643904 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5160 11:38:34.647762 [Gating] SW calibration Done
5161 11:38:34.648285 ==
5162 11:38:34.649968 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 11:38:34.653360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 11:38:34.653891 ==
5165 11:38:34.654339 RX Vref Scan: 0
5166 11:38:34.656714
5167 11:38:34.657270 RX Vref 0 -> 0, step: 1
5168 11:38:34.657722
5169 11:38:34.659689 RX Delay -80 -> 252, step: 8
5170 11:38:34.663137 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5171 11:38:34.666740 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5172 11:38:34.673606 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5173 11:38:34.676883 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5174 11:38:34.680605 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5175 11:38:34.683382 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5176 11:38:34.686705 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5177 11:38:34.690151 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 11:38:34.696928 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5179 11:38:34.700161 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5180 11:38:34.702981 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5181 11:38:34.706301 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5182 11:38:34.709507 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5183 11:38:34.716929 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5184 11:38:34.720002 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5185 11:38:34.722839 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5186 11:38:34.723286 ==
5187 11:38:34.726167 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 11:38:34.729605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 11:38:34.730132 ==
5190 11:38:34.732890 DQS Delay:
5191 11:38:34.733443 DQS0 = 0, DQS1 = 0
5192 11:38:34.737213 DQM Delay:
5193 11:38:34.737764 DQM0 = 95, DQM1 = 83
5194 11:38:34.738101 DQ Delay:
5195 11:38:34.739385 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5196 11:38:34.742589 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5197 11:38:34.746178 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5198 11:38:34.749612 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5199 11:38:34.750138
5200 11:38:34.750483
5201 11:38:34.752875 ==
5202 11:38:34.753432 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 11:38:34.759458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 11:38:34.759951 ==
5205 11:38:34.760280
5206 11:38:34.760580
5207 11:38:34.762720 TX Vref Scan disable
5208 11:38:34.763146 == TX Byte 0 ==
5209 11:38:34.765939 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5210 11:38:34.773513 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5211 11:38:34.774021 == TX Byte 1 ==
5212 11:38:34.775743 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5213 11:38:34.782944 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5214 11:38:34.783467 ==
5215 11:38:34.786105 Dram Type= 6, Freq= 0, CH_0, rank 1
5216 11:38:34.789375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5217 11:38:34.789806 ==
5218 11:38:34.790132
5219 11:38:34.790433
5220 11:38:34.793017 TX Vref Scan disable
5221 11:38:34.796267 == TX Byte 0 ==
5222 11:38:34.799351 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5223 11:38:34.802780 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5224 11:38:34.805958 == TX Byte 1 ==
5225 11:38:34.809627 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5226 11:38:34.812888 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5227 11:38:34.813439
5228 11:38:34.813776 [DATLAT]
5229 11:38:34.815927 Freq=933, CH0 RK1
5230 11:38:34.816352
5231 11:38:34.819505 DATLAT Default: 0xb
5232 11:38:34.820038 0, 0xFFFF, sum = 0
5233 11:38:34.823614 1, 0xFFFF, sum = 0
5234 11:38:34.824049 2, 0xFFFF, sum = 0
5235 11:38:34.825919 3, 0xFFFF, sum = 0
5236 11:38:34.826354 4, 0xFFFF, sum = 0
5237 11:38:34.829885 5, 0xFFFF, sum = 0
5238 11:38:34.830403 6, 0xFFFF, sum = 0
5239 11:38:34.832412 7, 0xFFFF, sum = 0
5240 11:38:34.832848 8, 0xFFFF, sum = 0
5241 11:38:34.836510 9, 0xFFFF, sum = 0
5242 11:38:34.837029 10, 0x0, sum = 1
5243 11:38:34.839234 11, 0x0, sum = 2
5244 11:38:34.839672 12, 0x0, sum = 3
5245 11:38:34.842562 13, 0x0, sum = 4
5246 11:38:34.842995 best_step = 11
5247 11:38:34.843321
5248 11:38:34.843627 ==
5249 11:38:34.846547 Dram Type= 6, Freq= 0, CH_0, rank 1
5250 11:38:34.849429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5251 11:38:34.852709 ==
5252 11:38:34.853138 RX Vref Scan: 0
5253 11:38:34.853518
5254 11:38:34.856206 RX Vref 0 -> 0, step: 1
5255 11:38:34.856714
5256 11:38:34.859135 RX Delay -69 -> 252, step: 4
5257 11:38:34.862444 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5258 11:38:34.865527 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5259 11:38:34.868880 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5260 11:38:34.876211 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5261 11:38:34.879189 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5262 11:38:34.882602 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5263 11:38:34.885992 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5264 11:38:34.889865 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5265 11:38:34.895758 iDelay=203, Bit 8, Center 76 (-9 ~ 162) 172
5266 11:38:34.898851 iDelay=203, Bit 9, Center 74 (-13 ~ 162) 176
5267 11:38:34.902519 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5268 11:38:34.905469 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5269 11:38:34.908914 iDelay=203, Bit 12, Center 92 (7 ~ 178) 172
5270 11:38:34.915377 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5271 11:38:34.919091 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5272 11:38:34.921719 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5273 11:38:34.922206 ==
5274 11:38:34.925477 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 11:38:34.928776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 11:38:34.929322 ==
5277 11:38:34.931895 DQS Delay:
5278 11:38:34.932409 DQS0 = 0, DQS1 = 0
5279 11:38:34.932745 DQM Delay:
5280 11:38:34.935519 DQM0 = 97, DQM1 = 86
5281 11:38:34.936028 DQ Delay:
5282 11:38:34.938927 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5283 11:38:34.941619 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5284 11:38:34.945063 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5285 11:38:34.948896 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =96
5286 11:38:34.949452
5287 11:38:34.949797
5288 11:38:34.958076 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5289 11:38:34.961202 CH0 RK1: MR19=505, MR18=2A2A
5290 11:38:34.968389 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5291 11:38:34.968919 [RxdqsGatingPostProcess] freq 933
5292 11:38:34.974596 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5293 11:38:34.978869 Pre-setting of DQS Precalculation
5294 11:38:34.984981 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5295 11:38:34.985536 ==
5296 11:38:34.987923 Dram Type= 6, Freq= 0, CH_1, rank 0
5297 11:38:34.990921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5298 11:38:34.991355 ==
5299 11:38:34.999184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5300 11:38:35.001283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5301 11:38:35.004921 [CA 0] Center 37 (7~68) winsize 62
5302 11:38:35.008189 [CA 1] Center 37 (6~68) winsize 63
5303 11:38:35.011209 [CA 2] Center 34 (4~65) winsize 62
5304 11:38:35.014651 [CA 3] Center 34 (3~65) winsize 63
5305 11:38:35.018692 [CA 4] Center 32 (2~63) winsize 62
5306 11:38:35.021944 [CA 5] Center 33 (3~64) winsize 62
5307 11:38:35.022368
5308 11:38:35.024868 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5309 11:38:35.025325
5310 11:38:35.027713 [CATrainingPosCal] consider 1 rank data
5311 11:38:35.031156 u2DelayCellTimex100 = 270/100 ps
5312 11:38:35.035213 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5313 11:38:35.042710 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5314 11:38:35.044770 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5315 11:38:35.048037 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5316 11:38:35.052088 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5317 11:38:35.054779 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5318 11:38:35.055073
5319 11:38:35.057916 CA PerBit enable=1, Macro0, CA PI delay=32
5320 11:38:35.058141
5321 11:38:35.061117 [CBTSetCACLKResult] CA Dly = 32
5322 11:38:35.064262 CS Dly: 5 (0~36)
5323 11:38:35.064438 ==
5324 11:38:35.067155 Dram Type= 6, Freq= 0, CH_1, rank 1
5325 11:38:35.071201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5326 11:38:35.071399 ==
5327 11:38:35.078161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5328 11:38:35.081132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5329 11:38:35.084753 [CA 0] Center 37 (6~68) winsize 63
5330 11:38:35.088161 [CA 1] Center 37 (6~68) winsize 63
5331 11:38:35.091952 [CA 2] Center 34 (4~65) winsize 62
5332 11:38:35.094630 [CA 3] Center 33 (3~64) winsize 62
5333 11:38:35.098178 [CA 4] Center 33 (3~64) winsize 62
5334 11:38:35.101958 [CA 5] Center 33 (2~64) winsize 63
5335 11:38:35.102465
5336 11:38:35.105084 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5337 11:38:35.105631
5338 11:38:35.108308 [CATrainingPosCal] consider 2 rank data
5339 11:38:35.111413 u2DelayCellTimex100 = 270/100 ps
5340 11:38:35.116233 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5341 11:38:35.121343 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5342 11:38:35.124723 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5343 11:38:35.127941 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5344 11:38:35.132457 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5345 11:38:35.135014 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5346 11:38:35.135521
5347 11:38:35.138032 CA PerBit enable=1, Macro0, CA PI delay=33
5348 11:38:35.138458
5349 11:38:35.140991 [CBTSetCACLKResult] CA Dly = 33
5350 11:38:35.141439 CS Dly: 6 (0~38)
5351 11:38:35.144931
5352 11:38:35.148098 ----->DramcWriteLeveling(PI) begin...
5353 11:38:35.148526 ==
5354 11:38:35.151195 Dram Type= 6, Freq= 0, CH_1, rank 0
5355 11:38:35.154558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5356 11:38:35.155072 ==
5357 11:38:35.157901 Write leveling (Byte 0): 26 => 26
5358 11:38:35.160912 Write leveling (Byte 1): 27 => 27
5359 11:38:35.164138 DramcWriteLeveling(PI) end<-----
5360 11:38:35.164559
5361 11:38:35.164884 ==
5362 11:38:35.168397 Dram Type= 6, Freq= 0, CH_1, rank 0
5363 11:38:35.172108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5364 11:38:35.172541 ==
5365 11:38:35.174185 [Gating] SW mode calibration
5366 11:38:35.181516 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 11:38:35.187726 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5368 11:38:35.190679 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 11:38:35.194236 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:38:35.200627 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:38:35.204735 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:38:35.207775 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5373 11:38:35.214721 0 10 20 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
5374 11:38:35.217100 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5375 11:38:35.220896 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:38:35.227373 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:38:35.230886 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:38:35.233840 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:38:35.240407 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:38:35.243969 0 11 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5381 11:38:35.247343 0 11 20 | B1->B0 | 2e2e 4545 | 0 0 | (1 1) (0 0)
5382 11:38:35.250908 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5383 11:38:35.257722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:38:35.260636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:38:35.264160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:38:35.270701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:38:35.273913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:38:35.277417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5389 11:38:35.283579 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:38:35.287372 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:38:35.290905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:38:35.297167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:38:35.300361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:38:35.304544 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:38:35.310856 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:38:35.313839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:38:35.316813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:38:35.323363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:38:35.327211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:38:35.330266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:38:35.337033 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:38:35.340898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:38:35.343589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5404 11:38:35.350633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5405 11:38:35.353446 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 11:38:35.356916 Total UI for P1: 0, mck2ui 16
5407 11:38:35.360035 best dqsien dly found for B0: ( 0, 14, 14)
5408 11:38:35.363892 Total UI for P1: 0, mck2ui 16
5409 11:38:35.366594 best dqsien dly found for B1: ( 0, 14, 16)
5410 11:38:35.370392 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5411 11:38:35.373886 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5412 11:38:35.374347
5413 11:38:35.377332 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5414 11:38:35.380440 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5415 11:38:35.383710 [Gating] SW calibration Done
5416 11:38:35.384177 ==
5417 11:38:35.386562 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 11:38:35.393156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 11:38:35.393637 ==
5420 11:38:35.393938 RX Vref Scan: 0
5421 11:38:35.394212
5422 11:38:35.396672 RX Vref 0 -> 0, step: 1
5423 11:38:35.397054
5424 11:38:35.399689 RX Delay -80 -> 252, step: 8
5425 11:38:35.403014 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5426 11:38:35.406009 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5427 11:38:35.409572 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5428 11:38:35.412936 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5429 11:38:35.419487 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5430 11:38:35.422757 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5431 11:38:35.426157 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5432 11:38:35.429468 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5433 11:38:35.432946 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5434 11:38:35.436387 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5435 11:38:35.443360 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5436 11:38:35.445940 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5437 11:38:35.449723 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5438 11:38:35.452411 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5439 11:38:35.455972 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5440 11:38:35.462785 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5441 11:38:35.463291 ==
5442 11:38:35.465911 Dram Type= 6, Freq= 0, CH_1, rank 0
5443 11:38:35.469658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5444 11:38:35.470164 ==
5445 11:38:35.470494 DQS Delay:
5446 11:38:35.473120 DQS0 = 0, DQS1 = 0
5447 11:38:35.473580 DQM Delay:
5448 11:38:35.476411 DQM0 = 95, DQM1 = 88
5449 11:38:35.476910 DQ Delay:
5450 11:38:35.481378 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5451 11:38:35.482577 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5452 11:38:35.485913 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5453 11:38:35.489366 DQ12 =95, DQ13 =103, DQ14 =95, DQ15 =99
5454 11:38:35.489873
5455 11:38:35.490203
5456 11:38:35.490505 ==
5457 11:38:35.492592 Dram Type= 6, Freq= 0, CH_1, rank 0
5458 11:38:35.496380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5459 11:38:35.496892 ==
5460 11:38:35.499538
5461 11:38:35.500020
5462 11:38:35.500350 TX Vref Scan disable
5463 11:38:35.502131 == TX Byte 0 ==
5464 11:38:35.506405 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5465 11:38:35.508845 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5466 11:38:35.512490 == TX Byte 1 ==
5467 11:38:35.515532 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5468 11:38:35.518857 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5469 11:38:35.519359 ==
5470 11:38:35.522518 Dram Type= 6, Freq= 0, CH_1, rank 0
5471 11:38:35.528688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5472 11:38:35.529190 ==
5473 11:38:35.529575
5474 11:38:35.529878
5475 11:38:35.532963 TX Vref Scan disable
5476 11:38:35.533430 == TX Byte 0 ==
5477 11:38:35.539090 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5478 11:38:35.541930 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5479 11:38:35.542362 == TX Byte 1 ==
5480 11:38:35.548705 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5481 11:38:35.551781 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5482 11:38:35.552215
5483 11:38:35.552552 [DATLAT]
5484 11:38:35.555474 Freq=933, CH1 RK0
5485 11:38:35.555908
5486 11:38:35.556244 DATLAT Default: 0xd
5487 11:38:35.558845 0, 0xFFFF, sum = 0
5488 11:38:35.559363 1, 0xFFFF, sum = 0
5489 11:38:35.562132 2, 0xFFFF, sum = 0
5490 11:38:35.562645 3, 0xFFFF, sum = 0
5491 11:38:35.565309 4, 0xFFFF, sum = 0
5492 11:38:35.565829 5, 0xFFFF, sum = 0
5493 11:38:35.569010 6, 0xFFFF, sum = 0
5494 11:38:35.569739 7, 0xFFFF, sum = 0
5495 11:38:35.573090 8, 0xFFFF, sum = 0
5496 11:38:35.575242 9, 0xFFFF, sum = 0
5497 11:38:35.575677 10, 0x0, sum = 1
5498 11:38:35.576015 11, 0x0, sum = 2
5499 11:38:35.578543 12, 0x0, sum = 3
5500 11:38:35.579058 13, 0x0, sum = 4
5501 11:38:35.581517 best_step = 11
5502 11:38:35.581944
5503 11:38:35.582274 ==
5504 11:38:35.585191 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 11:38:35.589065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 11:38:35.589642 ==
5507 11:38:35.591743 RX Vref Scan: 1
5508 11:38:35.592168
5509 11:38:35.592499 RX Vref 0 -> 0, step: 1
5510 11:38:35.592808
5511 11:38:35.595499 RX Delay -69 -> 252, step: 4
5512 11:38:35.595924
5513 11:38:35.598382 Set Vref, RX VrefLevel [Byte0]: 53
5514 11:38:35.601217 [Byte1]: 49
5515 11:38:35.605916
5516 11:38:35.606424 Final RX Vref Byte 0 = 53 to rank0
5517 11:38:35.609090 Final RX Vref Byte 1 = 49 to rank0
5518 11:38:35.612513 Final RX Vref Byte 0 = 53 to rank1
5519 11:38:35.616074 Final RX Vref Byte 1 = 49 to rank1==
5520 11:38:35.620084 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 11:38:35.625649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5522 11:38:35.626084 ==
5523 11:38:35.626419 DQS Delay:
5524 11:38:35.626730 DQS0 = 0, DQS1 = 0
5525 11:38:35.629376 DQM Delay:
5526 11:38:35.629877 DQM0 = 94, DQM1 = 88
5527 11:38:35.632651 DQ Delay:
5528 11:38:35.635892 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5529 11:38:35.639691 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5530 11:38:35.643375 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5531 11:38:35.646523 DQ12 =94, DQ13 =100, DQ14 =98, DQ15 =98
5532 11:38:35.647031
5533 11:38:35.647362
5534 11:38:35.652478 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5535 11:38:35.655488 CH1 RK0: MR19=505, MR18=3434
5536 11:38:35.662069 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5537 11:38:35.662572
5538 11:38:35.665400 ----->DramcWriteLeveling(PI) begin...
5539 11:38:35.665918 ==
5540 11:38:35.669630 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 11:38:35.672247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5542 11:38:35.672761 ==
5543 11:38:35.675418 Write leveling (Byte 0): 26 => 26
5544 11:38:35.678794 Write leveling (Byte 1): 26 => 26
5545 11:38:35.682105 DramcWriteLeveling(PI) end<-----
5546 11:38:35.682536
5547 11:38:35.682869 ==
5548 11:38:35.685510 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 11:38:35.688760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5550 11:38:35.689210 ==
5551 11:38:35.692094 [Gating] SW mode calibration
5552 11:38:35.698934 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5553 11:38:35.705417 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5554 11:38:35.708592 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 11:38:35.714868 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 11:38:35.718287 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 11:38:35.721780 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5558 11:38:35.728205 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 1)
5559 11:38:35.731454 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5560 11:38:35.735475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 11:38:35.742030 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 11:38:35.745084 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 11:38:35.748337 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 11:38:35.756071 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 11:38:35.758868 0 11 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5566 11:38:35.761223 0 11 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5567 11:38:35.768398 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5568 11:38:35.771553 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 11:38:35.775264 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 11:38:35.781639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 11:38:35.784530 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 11:38:35.787761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 11:38:35.796004 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:38:35.797570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5575 11:38:35.801629 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5576 11:38:35.808747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:38:35.812291 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 11:38:35.814100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:38:35.820967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 11:38:35.824615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:38:35.827938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:38:35.834178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:38:35.837928 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:38:35.841366 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:38:35.844097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:38:35.850817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:38:35.855248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:38:35.857254 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:38:35.864031 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:38:35.867677 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:38:35.871260 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5592 11:38:35.877610 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 11:38:35.881353 Total UI for P1: 0, mck2ui 16
5594 11:38:35.883997 best dqsien dly found for B0: ( 0, 14, 20)
5595 11:38:35.888003 Total UI for P1: 0, mck2ui 16
5596 11:38:35.891555 best dqsien dly found for B1: ( 0, 14, 20)
5597 11:38:35.893785 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5598 11:38:35.897288 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5599 11:38:35.897712
5600 11:38:35.900430 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5601 11:38:35.903924 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5602 11:38:35.907289 [Gating] SW calibration Done
5603 11:38:35.907790 ==
5604 11:38:35.910744 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 11:38:35.914118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 11:38:35.914616 ==
5607 11:38:35.917292 RX Vref Scan: 0
5608 11:38:35.917712
5609 11:38:35.920626 RX Vref 0 -> 0, step: 1
5610 11:38:35.921046
5611 11:38:35.921428 RX Delay -80 -> 252, step: 8
5612 11:38:35.926727 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5613 11:38:35.930135 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5614 11:38:35.933876 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5615 11:38:35.936880 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5616 11:38:35.940710 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5617 11:38:35.943758 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5618 11:38:35.950121 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5619 11:38:35.953160 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5620 11:38:35.956667 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5621 11:38:35.960304 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5622 11:38:35.963316 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5623 11:38:35.969931 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5624 11:38:35.973810 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5625 11:38:35.976835 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5626 11:38:35.979867 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5627 11:38:35.983508 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5628 11:38:35.984010 ==
5629 11:38:35.986777 Dram Type= 6, Freq= 0, CH_1, rank 1
5630 11:38:35.993430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5631 11:38:35.993939 ==
5632 11:38:35.994272 DQS Delay:
5633 11:38:35.996585 DQS0 = 0, DQS1 = 0
5634 11:38:35.997101 DQM Delay:
5635 11:38:35.997474 DQM0 = 95, DQM1 = 86
5636 11:38:36.000550 DQ Delay:
5637 11:38:36.003699 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5638 11:38:36.006461 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5639 11:38:36.010101 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5640 11:38:36.013625 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5641 11:38:36.014124
5642 11:38:36.014451
5643 11:38:36.014751 ==
5644 11:38:36.017492 Dram Type= 6, Freq= 0, CH_1, rank 1
5645 11:38:36.019300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5646 11:38:36.019727 ==
5647 11:38:36.020050
5648 11:38:36.020348
5649 11:38:36.023246 TX Vref Scan disable
5650 11:38:36.026658 == TX Byte 0 ==
5651 11:38:36.029647 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5652 11:38:36.033079 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5653 11:38:36.036299 == TX Byte 1 ==
5654 11:38:36.039805 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5655 11:38:36.042751 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5656 11:38:36.043178 ==
5657 11:38:36.046391 Dram Type= 6, Freq= 0, CH_1, rank 1
5658 11:38:36.049871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5659 11:38:36.050375 ==
5660 11:38:36.053756
5661 11:38:36.054256
5662 11:38:36.054593 TX Vref Scan disable
5663 11:38:36.056925 == TX Byte 0 ==
5664 11:38:36.060113 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 11:38:36.063606 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 11:38:36.066078 == TX Byte 1 ==
5667 11:38:36.071474 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5668 11:38:36.075988 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5669 11:38:36.076428
5670 11:38:36.076762 [DATLAT]
5671 11:38:36.077070 Freq=933, CH1 RK1
5672 11:38:36.077428
5673 11:38:36.079662 DATLAT Default: 0xb
5674 11:38:36.080172 0, 0xFFFF, sum = 0
5675 11:38:36.083942 1, 0xFFFF, sum = 0
5676 11:38:36.084459 2, 0xFFFF, sum = 0
5677 11:38:36.086231 3, 0xFFFF, sum = 0
5678 11:38:36.086667 4, 0xFFFF, sum = 0
5679 11:38:36.089455 5, 0xFFFF, sum = 0
5680 11:38:36.093429 6, 0xFFFF, sum = 0
5681 11:38:36.093868 7, 0xFFFF, sum = 0
5682 11:38:36.096700 8, 0xFFFF, sum = 0
5683 11:38:36.097285 9, 0xFFFF, sum = 0
5684 11:38:36.100018 10, 0x0, sum = 1
5685 11:38:36.100535 11, 0x0, sum = 2
5686 11:38:36.103439 12, 0x0, sum = 3
5687 11:38:36.103956 13, 0x0, sum = 4
5688 11:38:36.104296 best_step = 11
5689 11:38:36.104601
5690 11:38:36.105755 ==
5691 11:38:36.109444 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 11:38:36.112816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 11:38:36.113366 ==
5694 11:38:36.113706 RX Vref Scan: 0
5695 11:38:36.114015
5696 11:38:36.115681 RX Vref 0 -> 0, step: 1
5697 11:38:36.116110
5698 11:38:36.119147 RX Delay -77 -> 252, step: 4
5699 11:38:36.123484 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5700 11:38:36.129992 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5701 11:38:36.132405 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5702 11:38:36.135811 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5703 11:38:36.139263 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5704 11:38:36.142353 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5705 11:38:36.149331 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5706 11:38:36.153207 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5707 11:38:36.157013 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5708 11:38:36.158740 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5709 11:38:36.162319 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5710 11:38:36.166023 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5711 11:38:36.172086 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5712 11:38:36.175912 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5713 11:38:36.179209 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5714 11:38:36.181925 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5715 11:38:36.182359 ==
5716 11:38:36.185866 Dram Type= 6, Freq= 0, CH_1, rank 1
5717 11:38:36.189437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5718 11:38:36.193523 ==
5719 11:38:36.194033 DQS Delay:
5720 11:38:36.194480 DQS0 = 0, DQS1 = 0
5721 11:38:36.195703 DQM Delay:
5722 11:38:36.196128 DQM0 = 96, DQM1 = 87
5723 11:38:36.198689 DQ Delay:
5724 11:38:36.202739 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5725 11:38:36.203250 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5726 11:38:36.205835 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5727 11:38:36.212627 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5728 11:38:36.213130
5729 11:38:36.213529
5730 11:38:36.218972 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5731 11:38:36.221991 CH1 RK1: MR19=505, MR18=2525
5732 11:38:36.229021 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5733 11:38:36.232307 [RxdqsGatingPostProcess] freq 933
5734 11:38:36.235909 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5735 11:38:36.239650 Pre-setting of DQS Precalculation
5736 11:38:36.245589 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5737 11:38:36.251723 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5738 11:38:36.259847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5739 11:38:36.260355
5740 11:38:36.260687
5741 11:38:36.262091 [Calibration Summary] 1866 Mbps
5742 11:38:36.262512 CH 0, Rank 0
5743 11:38:36.265402 SW Impedance : PASS
5744 11:38:36.269622 DUTY Scan : NO K
5745 11:38:36.270130 ZQ Calibration : PASS
5746 11:38:36.271676 Jitter Meter : NO K
5747 11:38:36.275181 CBT Training : PASS
5748 11:38:36.275604 Write leveling : PASS
5749 11:38:36.278916 RX DQS gating : PASS
5750 11:38:36.281690 RX DQ/DQS(RDDQC) : PASS
5751 11:38:36.282136 TX DQ/DQS : PASS
5752 11:38:36.285379 RX DATLAT : PASS
5753 11:38:36.288425 RX DQ/DQS(Engine): PASS
5754 11:38:36.288856 TX OE : NO K
5755 11:38:36.289190 All Pass.
5756 11:38:36.289563
5757 11:38:36.291799 CH 0, Rank 1
5758 11:38:36.296236 SW Impedance : PASS
5759 11:38:36.296666 DUTY Scan : NO K
5760 11:38:36.298683 ZQ Calibration : PASS
5761 11:38:36.299112 Jitter Meter : NO K
5762 11:38:36.302913 CBT Training : PASS
5763 11:38:36.305846 Write leveling : PASS
5764 11:38:36.306533 RX DQS gating : PASS
5765 11:38:36.308721 RX DQ/DQS(RDDQC) : PASS
5766 11:38:36.311677 TX DQ/DQS : PASS
5767 11:38:36.312188 RX DATLAT : PASS
5768 11:38:36.315276 RX DQ/DQS(Engine): PASS
5769 11:38:36.318567 TX OE : NO K
5770 11:38:36.319098 All Pass.
5771 11:38:36.319438
5772 11:38:36.319750 CH 1, Rank 0
5773 11:38:36.321934 SW Impedance : PASS
5774 11:38:36.325077 DUTY Scan : NO K
5775 11:38:36.325618 ZQ Calibration : PASS
5776 11:38:36.328614 Jitter Meter : NO K
5777 11:38:36.332452 CBT Training : PASS
5778 11:38:36.332966 Write leveling : PASS
5779 11:38:36.335398 RX DQS gating : PASS
5780 11:38:36.338666 RX DQ/DQS(RDDQC) : PASS
5781 11:38:36.339172 TX DQ/DQS : PASS
5782 11:38:36.341208 RX DATLAT : PASS
5783 11:38:36.341671 RX DQ/DQS(Engine): PASS
5784 11:38:36.345030 TX OE : NO K
5785 11:38:36.345510 All Pass.
5786 11:38:36.345846
5787 11:38:36.348371 CH 1, Rank 1
5788 11:38:36.348851 SW Impedance : PASS
5789 11:38:36.351045 DUTY Scan : NO K
5790 11:38:36.354294 ZQ Calibration : PASS
5791 11:38:36.354726 Jitter Meter : NO K
5792 11:38:36.357789 CBT Training : PASS
5793 11:38:36.360995 Write leveling : PASS
5794 11:38:36.361457 RX DQS gating : PASS
5795 11:38:36.365105 RX DQ/DQS(RDDQC) : PASS
5796 11:38:36.367547 TX DQ/DQS : PASS
5797 11:38:36.368018 RX DATLAT : PASS
5798 11:38:36.371890 RX DQ/DQS(Engine): PASS
5799 11:38:36.374227 TX OE : NO K
5800 11:38:36.374877 All Pass.
5801 11:38:36.375246
5802 11:38:36.378497 DramC Write-DBI off
5803 11:38:36.378924 PER_BANK_REFRESH: Hybrid Mode
5804 11:38:36.381174 TX_TRACKING: ON
5805 11:38:36.388220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5806 11:38:36.394669 [FAST_K] Save calibration result to emmc
5807 11:38:36.397440 dramc_set_vcore_voltage set vcore to 650000
5808 11:38:36.397901 Read voltage for 400, 6
5809 11:38:36.401512 Vio18 = 0
5810 11:38:36.401893 Vcore = 650000
5811 11:38:36.402199 Vdram = 0
5812 11:38:36.404203 Vddq = 0
5813 11:38:36.404704 Vmddr = 0
5814 11:38:36.407509 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5815 11:38:36.414935 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5816 11:38:36.417393 MEM_TYPE=3, freq_sel=20
5817 11:38:36.420723 sv_algorithm_assistance_LP4_800
5818 11:38:36.424624 ============ PULL DRAM RESETB DOWN ============
5819 11:38:36.427080 ========== PULL DRAM RESETB DOWN end =========
5820 11:38:36.434085 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5821 11:38:36.437487 ===================================
5822 11:38:36.438000 LPDDR4 DRAM CONFIGURATION
5823 11:38:36.440297 ===================================
5824 11:38:36.444706 EX_ROW_EN[0] = 0x0
5825 11:38:36.445133 EX_ROW_EN[1] = 0x0
5826 11:38:36.447505 LP4Y_EN = 0x0
5827 11:38:36.448007 WORK_FSP = 0x0
5828 11:38:36.450610 WL = 0x2
5829 11:38:36.453758 RL = 0x2
5830 11:38:36.454180 BL = 0x2
5831 11:38:36.457096 RPST = 0x0
5832 11:38:36.457615 RD_PRE = 0x0
5833 11:38:36.460303 WR_PRE = 0x1
5834 11:38:36.460747 WR_PST = 0x0
5835 11:38:36.464617 DBI_WR = 0x0
5836 11:38:36.465090 DBI_RD = 0x0
5837 11:38:36.467703 OTF = 0x1
5838 11:38:36.471638 ===================================
5839 11:38:36.473606 ===================================
5840 11:38:36.474029 ANA top config
5841 11:38:36.477110 ===================================
5842 11:38:36.480587 DLL_ASYNC_EN = 0
5843 11:38:36.484291 ALL_SLAVE_EN = 1
5844 11:38:36.484831 NEW_RANK_MODE = 1
5845 11:38:36.486677 DLL_IDLE_MODE = 1
5846 11:38:36.490522 LP45_APHY_COMB_EN = 1
5847 11:38:36.493515 TX_ODT_DIS = 1
5848 11:38:36.497071 NEW_8X_MODE = 1
5849 11:38:36.497563 ===================================
5850 11:38:36.500658 ===================================
5851 11:38:36.503676 data_rate = 800
5852 11:38:36.506845 CKR = 1
5853 11:38:36.511002 DQ_P2S_RATIO = 4
5854 11:38:36.513488 ===================================
5855 11:38:36.517063 CA_P2S_RATIO = 4
5856 11:38:36.521351 DQ_CA_OPEN = 0
5857 11:38:36.524208 DQ_SEMI_OPEN = 1
5858 11:38:36.524683 CA_SEMI_OPEN = 1
5859 11:38:36.526819 CA_FULL_RATE = 0
5860 11:38:36.530355 DQ_CKDIV4_EN = 0
5861 11:38:36.533733 CA_CKDIV4_EN = 1
5862 11:38:36.537312 CA_PREDIV_EN = 0
5863 11:38:36.537698 PH8_DLY = 0
5864 11:38:36.540364 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5865 11:38:36.544346 DQ_AAMCK_DIV = 0
5866 11:38:36.546855 CA_AAMCK_DIV = 0
5867 11:38:36.550228 CA_ADMCK_DIV = 4
5868 11:38:36.553456 DQ_TRACK_CA_EN = 0
5869 11:38:36.557372 CA_PICK = 800
5870 11:38:36.557841 CA_MCKIO = 400
5871 11:38:36.560377 MCKIO_SEMI = 400
5872 11:38:36.563501 PLL_FREQ = 3016
5873 11:38:36.567481 DQ_UI_PI_RATIO = 32
5874 11:38:36.570915 CA_UI_PI_RATIO = 32
5875 11:38:36.573562 ===================================
5876 11:38:36.577178 ===================================
5877 11:38:36.579803 memory_type:LPDDR4
5878 11:38:36.580239 GP_NUM : 10
5879 11:38:36.583285 SRAM_EN : 1
5880 11:38:36.583708 MD32_EN : 0
5881 11:38:36.586865 ===================================
5882 11:38:36.589936 [ANA_INIT] >>>>>>>>>>>>>>
5883 11:38:36.593658 <<<<<< [CONFIGURE PHASE]: ANA_TX
5884 11:38:36.596618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5885 11:38:36.600454 ===================================
5886 11:38:36.603081 data_rate = 800,PCW = 0X7400
5887 11:38:36.607995 ===================================
5888 11:38:36.610243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5889 11:38:36.616377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5890 11:38:36.626848 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5891 11:38:36.629545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5892 11:38:36.632822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5893 11:38:36.639529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5894 11:38:36.640050 [ANA_INIT] flow start
5895 11:38:36.643260 [ANA_INIT] PLL >>>>>>>>
5896 11:38:36.647353 [ANA_INIT] PLL <<<<<<<<
5897 11:38:36.647773 [ANA_INIT] MIDPI >>>>>>>>
5898 11:38:36.650017 [ANA_INIT] MIDPI <<<<<<<<
5899 11:38:36.654128 [ANA_INIT] DLL >>>>>>>>
5900 11:38:36.654633 [ANA_INIT] flow end
5901 11:38:36.656000 ============ LP4 DIFF to SE enter ============
5902 11:38:36.662863 ============ LP4 DIFF to SE exit ============
5903 11:38:36.663376 [ANA_INIT] <<<<<<<<<<<<<
5904 11:38:36.666497 [Flow] Enable top DCM control >>>>>
5905 11:38:36.669690 [Flow] Enable top DCM control <<<<<
5906 11:38:36.672866 Enable DLL master slave shuffle
5907 11:38:36.679775 ==============================================================
5908 11:38:36.680280 Gating Mode config
5909 11:38:36.685941 ==============================================================
5910 11:38:36.689448 Config description:
5911 11:38:36.699251 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5912 11:38:36.705711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5913 11:38:36.709609 SELPH_MODE 0: By rank 1: By Phase
5914 11:38:36.716516 ==============================================================
5915 11:38:36.719357 GAT_TRACK_EN = 0
5916 11:38:36.722816 RX_GATING_MODE = 2
5917 11:38:36.723326 RX_GATING_TRACK_MODE = 2
5918 11:38:36.726061 SELPH_MODE = 1
5919 11:38:36.729867 PICG_EARLY_EN = 1
5920 11:38:36.732982 VALID_LAT_VALUE = 1
5921 11:38:36.739400 ==============================================================
5922 11:38:36.743178 Enter into Gating configuration >>>>
5923 11:38:36.745825 Exit from Gating configuration <<<<
5924 11:38:36.749437 Enter into DVFS_PRE_config >>>>>
5925 11:38:36.760439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5926 11:38:36.762450 Exit from DVFS_PRE_config <<<<<
5927 11:38:36.765945 Enter into PICG configuration >>>>
5928 11:38:36.769051 Exit from PICG configuration <<<<
5929 11:38:36.772339 [RX_INPUT] configuration >>>>>
5930 11:38:36.775323 [RX_INPUT] configuration <<<<<
5931 11:38:36.779990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5932 11:38:36.786005 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5933 11:38:36.792149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5934 11:38:36.799068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5935 11:38:36.802084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5936 11:38:36.808942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5937 11:38:36.811605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5938 11:38:36.818472 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5939 11:38:36.821606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5940 11:38:36.825584 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5941 11:38:36.828968 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5942 11:38:36.835519 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5943 11:38:36.838501 ===================================
5944 11:38:36.842433 LPDDR4 DRAM CONFIGURATION
5945 11:38:36.845388 ===================================
5946 11:38:36.845896 EX_ROW_EN[0] = 0x0
5947 11:38:36.850127 EX_ROW_EN[1] = 0x0
5948 11:38:36.850624 LP4Y_EN = 0x0
5949 11:38:36.851467 WORK_FSP = 0x0
5950 11:38:36.852066 WL = 0x2
5951 11:38:36.854870 RL = 0x2
5952 11:38:36.855291 BL = 0x2
5953 11:38:36.858757 RPST = 0x0
5954 11:38:36.859264 RD_PRE = 0x0
5955 11:38:36.861930 WR_PRE = 0x1
5956 11:38:36.862437 WR_PST = 0x0
5957 11:38:36.865799 DBI_WR = 0x0
5958 11:38:36.866321 DBI_RD = 0x0
5959 11:38:36.868256 OTF = 0x1
5960 11:38:36.871465 ===================================
5961 11:38:36.875229 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5962 11:38:36.877878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5963 11:38:36.885002 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5964 11:38:36.889377 ===================================
5965 11:38:36.891129 LPDDR4 DRAM CONFIGURATION
5966 11:38:36.891555 ===================================
5967 11:38:36.894612 EX_ROW_EN[0] = 0x10
5968 11:38:36.898625 EX_ROW_EN[1] = 0x0
5969 11:38:36.899154 LP4Y_EN = 0x0
5970 11:38:36.901307 WORK_FSP = 0x0
5971 11:38:36.901737 WL = 0x2
5972 11:38:36.904265 RL = 0x2
5973 11:38:36.904689 BL = 0x2
5974 11:38:36.907782 RPST = 0x0
5975 11:38:36.908291 RD_PRE = 0x0
5976 11:38:36.911036 WR_PRE = 0x1
5977 11:38:36.911458 WR_PST = 0x0
5978 11:38:36.914918 DBI_WR = 0x0
5979 11:38:36.915538 DBI_RD = 0x0
5980 11:38:36.918292 OTF = 0x1
5981 11:38:36.920878 ===================================
5982 11:38:36.927971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5983 11:38:36.931514 nWR fixed to 30
5984 11:38:36.934713 [ModeRegInit_LP4] CH0 RK0
5985 11:38:36.935223 [ModeRegInit_LP4] CH0 RK1
5986 11:38:36.937520 [ModeRegInit_LP4] CH1 RK0
5987 11:38:36.940609 [ModeRegInit_LP4] CH1 RK1
5988 11:38:36.941114 match AC timing 18
5989 11:38:36.947617 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5990 11:38:36.950976 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5991 11:38:36.954678 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5992 11:38:36.960636 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5993 11:38:36.964273 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5994 11:38:36.964783 ==
5995 11:38:36.967350 Dram Type= 6, Freq= 0, CH_0, rank 0
5996 11:38:36.970681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5997 11:38:36.971187 ==
5998 11:38:36.976938 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5999 11:38:36.984304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6000 11:38:36.987179 [CA 0] Center 36 (8~64) winsize 57
6001 11:38:36.990275 [CA 1] Center 36 (8~64) winsize 57
6002 11:38:36.993980 [CA 2] Center 36 (8~64) winsize 57
6003 11:38:36.998044 [CA 3] Center 36 (8~64) winsize 57
6004 11:38:37.000019 [CA 4] Center 36 (8~64) winsize 57
6005 11:38:37.000452 [CA 5] Center 36 (8~64) winsize 57
6006 11:38:37.003326
6007 11:38:37.007153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6008 11:38:37.007661
6009 11:38:37.009912 [CATrainingPosCal] consider 1 rank data
6010 11:38:37.014298 u2DelayCellTimex100 = 270/100 ps
6011 11:38:37.016888 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 11:38:37.020337 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 11:38:37.023340 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 11:38:37.026937 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 11:38:37.030179 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 11:38:37.033881 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 11:38:37.034394
6018 11:38:37.037177 CA PerBit enable=1, Macro0, CA PI delay=36
6019 11:38:37.037721
6020 11:38:37.039944 [CBTSetCACLKResult] CA Dly = 36
6021 11:38:37.043969 CS Dly: 1 (0~32)
6022 11:38:37.044568 ==
6023 11:38:37.046520 Dram Type= 6, Freq= 0, CH_0, rank 1
6024 11:38:37.050387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6025 11:38:37.050899 ==
6026 11:38:37.057170 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6027 11:38:37.064149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6028 11:38:37.067163 [CA 0] Center 36 (8~64) winsize 57
6029 11:38:37.067673 [CA 1] Center 36 (8~64) winsize 57
6030 11:38:37.069928 [CA 2] Center 36 (8~64) winsize 57
6031 11:38:37.073504 [CA 3] Center 36 (8~64) winsize 57
6032 11:38:37.076638 [CA 4] Center 36 (8~64) winsize 57
6033 11:38:37.080387 [CA 5] Center 36 (8~64) winsize 57
6034 11:38:37.080903
6035 11:38:37.083331 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6036 11:38:37.083839
6037 11:38:37.089686 [CATrainingPosCal] consider 2 rank data
6038 11:38:37.090198 u2DelayCellTimex100 = 270/100 ps
6039 11:38:37.096382 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 11:38:37.099746 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 11:38:37.103174 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 11:38:37.106511 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 11:38:37.110000 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6044 11:38:37.113147 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6045 11:38:37.113685
6046 11:38:37.116625 CA PerBit enable=1, Macro0, CA PI delay=36
6047 11:38:37.117131
6048 11:38:37.119682 [CBTSetCACLKResult] CA Dly = 36
6049 11:38:37.123134 CS Dly: 1 (0~32)
6050 11:38:37.123759
6051 11:38:37.125963 ----->DramcWriteLeveling(PI) begin...
6052 11:38:37.126433 ==
6053 11:38:37.129668 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 11:38:37.132848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 11:38:37.133394 ==
6056 11:38:37.136430 Write leveling (Byte 0): 32 => 0
6057 11:38:37.139698 Write leveling (Byte 1): 32 => 0
6058 11:38:37.143046 DramcWriteLeveling(PI) end<-----
6059 11:38:37.143471
6060 11:38:37.143801 ==
6061 11:38:37.146261 Dram Type= 6, Freq= 0, CH_0, rank 0
6062 11:38:37.149550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6063 11:38:37.150154 ==
6064 11:38:37.153527 [Gating] SW mode calibration
6065 11:38:37.159671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6066 11:38:37.166548 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6067 11:38:37.170092 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6068 11:38:37.172662 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6069 11:38:37.179688 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6070 11:38:37.182676 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6071 11:38:37.186152 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6072 11:38:37.192886 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6073 11:38:37.195689 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6074 11:38:37.199020 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6075 11:38:37.202478 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6076 11:38:37.206557 Total UI for P1: 0, mck2ui 16
6077 11:38:37.209509 best dqsien dly found for B0: ( 0, 10, 16)
6078 11:38:37.212406 Total UI for P1: 0, mck2ui 16
6079 11:38:37.216209 best dqsien dly found for B1: ( 0, 10, 24)
6080 11:38:37.219108 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6081 11:38:37.226561 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6082 11:38:37.227068
6083 11:38:37.229036 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6084 11:38:37.232725 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6085 11:38:37.236510 [Gating] SW calibration Done
6086 11:38:37.237017 ==
6087 11:38:37.239635 Dram Type= 6, Freq= 0, CH_0, rank 0
6088 11:38:37.242185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6089 11:38:37.242613 ==
6090 11:38:37.245369 RX Vref Scan: 0
6091 11:38:37.245788
6092 11:38:37.246116 RX Vref 0 -> 0, step: 1
6093 11:38:37.246425
6094 11:38:37.249197 RX Delay -410 -> 252, step: 16
6095 11:38:37.255817 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6096 11:38:37.258755 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6097 11:38:37.262660 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6098 11:38:37.265531 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6099 11:38:37.271916 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6100 11:38:37.275322 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6101 11:38:37.278258 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6102 11:38:37.281848 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6103 11:38:37.289506 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6104 11:38:37.291917 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6105 11:38:37.295713 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6106 11:38:37.298447 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6107 11:38:37.305384 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6108 11:38:37.308481 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6109 11:38:37.312459 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6110 11:38:37.315798 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6111 11:38:37.318149 ==
6112 11:38:37.321630 Dram Type= 6, Freq= 0, CH_0, rank 0
6113 11:38:37.325376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6114 11:38:37.325883 ==
6115 11:38:37.326216 DQS Delay:
6116 11:38:37.328744 DQS0 = 51, DQS1 = 59
6117 11:38:37.329165 DQM Delay:
6118 11:38:37.332219 DQM0 = 12, DQM1 = 16
6119 11:38:37.332764 DQ Delay:
6120 11:38:37.335169 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6121 11:38:37.337942 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6122 11:38:37.341774 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6123 11:38:37.344812 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6124 11:38:37.345372
6125 11:38:37.345711
6126 11:38:37.346016 ==
6127 11:38:37.348252 Dram Type= 6, Freq= 0, CH_0, rank 0
6128 11:38:37.351575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6129 11:38:37.352086 ==
6130 11:38:37.352414
6131 11:38:37.352716
6132 11:38:37.354473 TX Vref Scan disable
6133 11:38:37.354898 == TX Byte 0 ==
6134 11:38:37.361389 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 11:38:37.365759 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 11:38:37.366264 == TX Byte 1 ==
6137 11:38:37.371599 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6138 11:38:37.374820 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6139 11:38:37.375249 ==
6140 11:38:37.379378 Dram Type= 6, Freq= 0, CH_0, rank 0
6141 11:38:37.381753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6142 11:38:37.382187 ==
6143 11:38:37.382522
6144 11:38:37.382825
6145 11:38:37.384495 TX Vref Scan disable
6146 11:38:37.384919 == TX Byte 0 ==
6147 11:38:37.391650 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6148 11:38:37.394599 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6149 11:38:37.398434 == TX Byte 1 ==
6150 11:38:37.401123 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6151 11:38:37.404848 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6152 11:38:37.405568
6153 11:38:37.405925 [DATLAT]
6154 11:38:37.407710 Freq=400, CH0 RK0
6155 11:38:37.408211
6156 11:38:37.410724 DATLAT Default: 0xf
6157 11:38:37.411145 0, 0xFFFF, sum = 0
6158 11:38:37.414516 1, 0xFFFF, sum = 0
6159 11:38:37.415025 2, 0xFFFF, sum = 0
6160 11:38:37.417764 3, 0xFFFF, sum = 0
6161 11:38:37.418273 4, 0xFFFF, sum = 0
6162 11:38:37.421320 5, 0xFFFF, sum = 0
6163 11:38:37.421827 6, 0xFFFF, sum = 0
6164 11:38:37.424257 7, 0xFFFF, sum = 0
6165 11:38:37.424765 8, 0xFFFF, sum = 0
6166 11:38:37.427455 9, 0xFFFF, sum = 0
6167 11:38:37.427971 10, 0xFFFF, sum = 0
6168 11:38:37.430958 11, 0xFFFF, sum = 0
6169 11:38:37.431471 12, 0x0, sum = 1
6170 11:38:37.434298 13, 0x0, sum = 2
6171 11:38:37.434724 14, 0x0, sum = 3
6172 11:38:37.437168 15, 0x0, sum = 4
6173 11:38:37.437633 best_step = 13
6174 11:38:37.437963
6175 11:38:37.438263 ==
6176 11:38:37.441324 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 11:38:37.444646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 11:38:37.447342 ==
6179 11:38:37.447771 RX Vref Scan: 1
6180 11:38:37.448097
6181 11:38:37.450305 RX Vref 0 -> 0, step: 1
6182 11:38:37.450729
6183 11:38:37.454527 RX Delay -359 -> 252, step: 8
6184 11:38:37.455033
6185 11:38:37.457605 Set Vref, RX VrefLevel [Byte0]: 50
6186 11:38:37.460811 [Byte1]: 46
6187 11:38:37.461362
6188 11:38:37.463961 Final RX Vref Byte 0 = 50 to rank0
6189 11:38:37.467793 Final RX Vref Byte 1 = 46 to rank0
6190 11:38:37.471126 Final RX Vref Byte 0 = 50 to rank1
6191 11:38:37.474125 Final RX Vref Byte 1 = 46 to rank1==
6192 11:38:37.478163 Dram Type= 6, Freq= 0, CH_0, rank 0
6193 11:38:37.482071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6194 11:38:37.482497 ==
6195 11:38:37.483666 DQS Delay:
6196 11:38:37.484087 DQS0 = 52, DQS1 = 68
6197 11:38:37.487709 DQM Delay:
6198 11:38:37.488210 DQM0 = 8, DQM1 = 16
6199 11:38:37.488540 DQ Delay:
6200 11:38:37.490512 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6201 11:38:37.494296 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6202 11:38:37.497673 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6203 11:38:37.500670 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6204 11:38:37.501385
6205 11:38:37.501956
6206 11:38:37.510020 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6207 11:38:37.513524 CH0 RK0: MR19=C0C, MR18=A4A4
6208 11:38:37.517745 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6209 11:38:37.520365 ==
6210 11:38:37.520785 Dram Type= 6, Freq= 0, CH_0, rank 1
6211 11:38:37.527094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6212 11:38:37.527479 ==
6213 11:38:37.530354 [Gating] SW mode calibration
6214 11:38:37.536958 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6215 11:38:37.540217 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6216 11:38:37.547677 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6217 11:38:37.549911 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6218 11:38:37.553318 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6219 11:38:37.560219 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6220 11:38:37.563572 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6221 11:38:37.566514 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6222 11:38:37.573791 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6223 11:38:37.576554 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6224 11:38:37.579647 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6225 11:38:37.583493 Total UI for P1: 0, mck2ui 16
6226 11:38:37.586651 best dqsien dly found for B0: ( 0, 10, 16)
6227 11:38:37.589408 Total UI for P1: 0, mck2ui 16
6228 11:38:37.593265 best dqsien dly found for B1: ( 0, 10, 16)
6229 11:38:37.597174 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6230 11:38:37.599959 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6231 11:38:37.600400
6232 11:38:37.605828 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6233 11:38:37.609934 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6234 11:38:37.613209 [Gating] SW calibration Done
6235 11:38:37.613643 ==
6236 11:38:37.616146 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 11:38:37.619688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6238 11:38:37.620080 ==
6239 11:38:37.620384 RX Vref Scan: 0
6240 11:38:37.622895
6241 11:38:37.623280 RX Vref 0 -> 0, step: 1
6242 11:38:37.623578
6243 11:38:37.625936 RX Delay -410 -> 252, step: 16
6244 11:38:37.629767 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6245 11:38:37.635547 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6246 11:38:37.638983 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6247 11:38:37.642824 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6248 11:38:37.645797 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6249 11:38:37.652451 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6250 11:38:37.656303 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6251 11:38:37.658955 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6252 11:38:37.662408 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6253 11:38:37.668712 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6254 11:38:37.671877 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6255 11:38:37.676443 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6256 11:38:37.678896 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6257 11:38:37.685393 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6258 11:38:37.688806 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6259 11:38:37.691884 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6260 11:38:37.692388 ==
6261 11:38:37.695249 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 11:38:37.702330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6263 11:38:37.702757 ==
6264 11:38:37.703088 DQS Delay:
6265 11:38:37.705413 DQS0 = 51, DQS1 = 59
6266 11:38:37.705835 DQM Delay:
6267 11:38:37.709265 DQM0 = 13, DQM1 = 15
6268 11:38:37.709780 DQ Delay:
6269 11:38:37.712123 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6270 11:38:37.715856 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6271 11:38:37.716361 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6272 11:38:37.718599 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6273 11:38:37.722419
6274 11:38:37.722919
6275 11:38:37.723250 ==
6276 11:38:37.725474 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 11:38:37.728680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6278 11:38:37.729106 ==
6279 11:38:37.729505
6280 11:38:37.729818
6281 11:38:37.733209 TX Vref Scan disable
6282 11:38:37.733773 == TX Byte 0 ==
6283 11:38:37.734905 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6284 11:38:37.742172 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6285 11:38:37.742673 == TX Byte 1 ==
6286 11:38:37.745840 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6287 11:38:37.751746 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6288 11:38:37.752256 ==
6289 11:38:37.755205 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 11:38:37.758826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6291 11:38:37.759334 ==
6292 11:38:37.759669
6293 11:38:37.759974
6294 11:38:37.761717 TX Vref Scan disable
6295 11:38:37.762146 == TX Byte 0 ==
6296 11:38:37.768347 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6297 11:38:37.771486 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6298 11:38:37.771916 == TX Byte 1 ==
6299 11:38:37.774608 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6300 11:38:37.781163 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6301 11:38:37.781659
6302 11:38:37.781995 [DATLAT]
6303 11:38:37.784703 Freq=400, CH0 RK1
6304 11:38:37.785124
6305 11:38:37.785504 DATLAT Default: 0xd
6306 11:38:37.788192 0, 0xFFFF, sum = 0
6307 11:38:37.788625 1, 0xFFFF, sum = 0
6308 11:38:37.791235 2, 0xFFFF, sum = 0
6309 11:38:37.791665 3, 0xFFFF, sum = 0
6310 11:38:37.794655 4, 0xFFFF, sum = 0
6311 11:38:37.795081 5, 0xFFFF, sum = 0
6312 11:38:37.797811 6, 0xFFFF, sum = 0
6313 11:38:37.798241 7, 0xFFFF, sum = 0
6314 11:38:37.802105 8, 0xFFFF, sum = 0
6315 11:38:37.802557 9, 0xFFFF, sum = 0
6316 11:38:37.804820 10, 0xFFFF, sum = 0
6317 11:38:37.805310 11, 0xFFFF, sum = 0
6318 11:38:37.807808 12, 0x0, sum = 1
6319 11:38:37.808193 13, 0x0, sum = 2
6320 11:38:37.811823 14, 0x0, sum = 3
6321 11:38:37.812281 15, 0x0, sum = 4
6322 11:38:37.814641 best_step = 13
6323 11:38:37.815021
6324 11:38:37.815315 ==
6325 11:38:37.819321 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 11:38:37.821770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 11:38:37.822155 ==
6328 11:38:37.824450 RX Vref Scan: 0
6329 11:38:37.824827
6330 11:38:37.825118 RX Vref 0 -> 0, step: 1
6331 11:38:37.825504
6332 11:38:37.827838 RX Delay -359 -> 252, step: 8
6333 11:38:37.836369 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6334 11:38:37.839063 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6335 11:38:37.843108 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6336 11:38:37.846495 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6337 11:38:37.853407 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6338 11:38:37.856128 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6339 11:38:37.859134 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6340 11:38:37.862525 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6341 11:38:37.869512 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6342 11:38:37.872722 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6343 11:38:37.875715 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6344 11:38:37.882138 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6345 11:38:37.886638 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6346 11:38:37.889549 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6347 11:38:37.892261 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6348 11:38:37.899706 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6349 11:38:37.900212 ==
6350 11:38:37.902492 Dram Type= 6, Freq= 0, CH_0, rank 1
6351 11:38:37.905670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6352 11:38:37.906171 ==
6353 11:38:37.906502 DQS Delay:
6354 11:38:37.909146 DQS0 = 52, DQS1 = 68
6355 11:38:37.909694 DQM Delay:
6356 11:38:37.911767 DQM0 = 10, DQM1 = 17
6357 11:38:37.912186 DQ Delay:
6358 11:38:37.915892 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6359 11:38:37.918642 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6360 11:38:37.922393 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6361 11:38:37.925548 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6362 11:38:37.926046
6363 11:38:37.926371
6364 11:38:37.931719 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6365 11:38:37.935267 CH0 RK1: MR19=C0C, MR18=CECE
6366 11:38:37.942221 CH0_RK1: MR19=0xC0C, MR18=0xCECE, DQSOSC=384, MR23=63, INC=400, DEC=267
6367 11:38:37.945847 [RxdqsGatingPostProcess] freq 400
6368 11:38:37.952164 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6369 11:38:37.955138 Pre-setting of DQS Precalculation
6370 11:38:37.958336 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6371 11:38:37.958758 ==
6372 11:38:37.961523 Dram Type= 6, Freq= 0, CH_1, rank 0
6373 11:38:37.965266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6374 11:38:37.965779 ==
6375 11:38:37.971984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6376 11:38:37.979114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6377 11:38:37.981442 [CA 0] Center 36 (8~64) winsize 57
6378 11:38:37.985451 [CA 1] Center 36 (8~64) winsize 57
6379 11:38:37.988114 [CA 2] Center 36 (8~64) winsize 57
6380 11:38:37.991221 [CA 3] Center 36 (8~64) winsize 57
6381 11:38:37.994508 [CA 4] Center 36 (8~64) winsize 57
6382 11:38:37.994930 [CA 5] Center 36 (8~64) winsize 57
6383 11:38:37.998924
6384 11:38:38.001522 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6385 11:38:38.002034
6386 11:38:38.005643 [CATrainingPosCal] consider 1 rank data
6387 11:38:38.008067 u2DelayCellTimex100 = 270/100 ps
6388 11:38:38.011152 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 11:38:38.014779 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 11:38:38.018931 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 11:38:38.021104 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 11:38:38.025269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 11:38:38.027751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 11:38:38.028260
6395 11:38:38.031894 CA PerBit enable=1, Macro0, CA PI delay=36
6396 11:38:38.032400
6397 11:38:38.035544 [CBTSetCACLKResult] CA Dly = 36
6398 11:38:38.037723 CS Dly: 1 (0~32)
6399 11:38:38.038146 ==
6400 11:38:38.041449 Dram Type= 6, Freq= 0, CH_1, rank 1
6401 11:38:38.044655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6402 11:38:38.045155 ==
6403 11:38:38.051444 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6404 11:38:38.059161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6405 11:38:38.062081 [CA 0] Center 36 (8~64) winsize 57
6406 11:38:38.064603 [CA 1] Center 36 (8~64) winsize 57
6407 11:38:38.065100 [CA 2] Center 36 (8~64) winsize 57
6408 11:38:38.068415 [CA 3] Center 36 (8~64) winsize 57
6409 11:38:38.071530 [CA 4] Center 36 (8~64) winsize 57
6410 11:38:38.074272 [CA 5] Center 36 (8~64) winsize 57
6411 11:38:38.074697
6412 11:38:38.077914 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6413 11:38:38.078419
6414 11:38:38.084057 [CATrainingPosCal] consider 2 rank data
6415 11:38:38.084479 u2DelayCellTimex100 = 270/100 ps
6416 11:38:38.088160 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 11:38:38.095095 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 11:38:38.098633 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 11:38:38.100940 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6420 11:38:38.104766 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6421 11:38:38.107616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6422 11:38:38.108125
6423 11:38:38.111552 CA PerBit enable=1, Macro0, CA PI delay=36
6424 11:38:38.112052
6425 11:38:38.114435 [CBTSetCACLKResult] CA Dly = 36
6426 11:38:38.114865 CS Dly: 1 (0~32)
6427 11:38:38.117699
6428 11:38:38.121386 ----->DramcWriteLeveling(PI) begin...
6429 11:38:38.121892 ==
6430 11:38:38.124616 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 11:38:38.128234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 11:38:38.128749 ==
6433 11:38:38.131901 Write leveling (Byte 0): 32 => 0
6434 11:38:38.135326 Write leveling (Byte 1): 32 => 0
6435 11:38:38.137897 DramcWriteLeveling(PI) end<-----
6436 11:38:38.138330
6437 11:38:38.138660 ==
6438 11:38:38.140657 Dram Type= 6, Freq= 0, CH_1, rank 0
6439 11:38:38.144004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6440 11:38:38.144433 ==
6441 11:38:38.148037 [Gating] SW mode calibration
6442 11:38:38.153933 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 11:38:38.160947 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6444 11:38:38.163968 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 11:38:38.166972 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 11:38:38.174018 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 11:38:38.177062 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6448 11:38:38.179973 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 11:38:38.187074 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 11:38:38.190401 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 11:38:38.193969 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6452 11:38:38.200284 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 11:38:38.200792 Total UI for P1: 0, mck2ui 16
6454 11:38:38.206634 best dqsien dly found for B0: ( 0, 10, 16)
6455 11:38:38.207114 Total UI for P1: 0, mck2ui 16
6456 11:38:38.214537 best dqsien dly found for B1: ( 0, 10, 16)
6457 11:38:38.216656 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6458 11:38:38.220192 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6459 11:38:38.220692
6460 11:38:38.223457 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6461 11:38:38.226809 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6462 11:38:38.229661 [Gating] SW calibration Done
6463 11:38:38.230130 ==
6464 11:38:38.233790 Dram Type= 6, Freq= 0, CH_1, rank 0
6465 11:38:38.236528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6466 11:38:38.237037 ==
6467 11:38:38.239842 RX Vref Scan: 0
6468 11:38:38.240268
6469 11:38:38.240602 RX Vref 0 -> 0, step: 1
6470 11:38:38.243947
6471 11:38:38.244448 RX Delay -410 -> 252, step: 16
6472 11:38:38.249844 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6473 11:38:38.253605 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 11:38:38.256598 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 11:38:38.259706 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6476 11:38:38.266045 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 11:38:38.269698 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6478 11:38:38.272438 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6479 11:38:38.275830 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6480 11:38:38.282680 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 11:38:38.286119 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6482 11:38:38.289806 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 11:38:38.293001 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6484 11:38:38.299283 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6485 11:38:38.302562 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6486 11:38:38.305932 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6487 11:38:38.313257 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6488 11:38:38.313781 ==
6489 11:38:38.315992 Dram Type= 6, Freq= 0, CH_1, rank 0
6490 11:38:38.319357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6491 11:38:38.319792 ==
6492 11:38:38.320123 DQS Delay:
6493 11:38:38.322730 DQS0 = 43, DQS1 = 59
6494 11:38:38.323226 DQM Delay:
6495 11:38:38.326576 DQM0 = 6, DQM1 = 14
6496 11:38:38.327077 DQ Delay:
6497 11:38:38.329473 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6498 11:38:38.332449 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6499 11:38:38.336346 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6500 11:38:38.338841 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6501 11:38:38.339263
6502 11:38:38.339588
6503 11:38:38.339889 ==
6504 11:38:38.342205 Dram Type= 6, Freq= 0, CH_1, rank 0
6505 11:38:38.346075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6506 11:38:38.346576 ==
6507 11:38:38.346915
6508 11:38:38.347313
6509 11:38:38.348662 TX Vref Scan disable
6510 11:38:38.349085 == TX Byte 0 ==
6511 11:38:38.355741 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 11:38:38.358754 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 11:38:38.359182 == TX Byte 1 ==
6514 11:38:38.365473 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6515 11:38:38.368756 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6516 11:38:38.369295 ==
6517 11:38:38.372117 Dram Type= 6, Freq= 0, CH_1, rank 0
6518 11:38:38.375397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6519 11:38:38.375907 ==
6520 11:38:38.376241
6521 11:38:38.379430
6522 11:38:38.379928 TX Vref Scan disable
6523 11:38:38.382442 == TX Byte 0 ==
6524 11:38:38.385776 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6525 11:38:38.388096 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6526 11:38:38.391676 == TX Byte 1 ==
6527 11:38:38.394989 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6528 11:38:38.398111 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6529 11:38:38.398538
6530 11:38:38.402447 [DATLAT]
6531 11:38:38.402870 Freq=400, CH1 RK0
6532 11:38:38.403200
6533 11:38:38.404634 DATLAT Default: 0xf
6534 11:38:38.405063 0, 0xFFFF, sum = 0
6535 11:38:38.408706 1, 0xFFFF, sum = 0
6536 11:38:38.409211 2, 0xFFFF, sum = 0
6537 11:38:38.411696 3, 0xFFFF, sum = 0
6538 11:38:38.412203 4, 0xFFFF, sum = 0
6539 11:38:38.414666 5, 0xFFFF, sum = 0
6540 11:38:38.415274 6, 0xFFFF, sum = 0
6541 11:38:38.418131 7, 0xFFFF, sum = 0
6542 11:38:38.418695 8, 0xFFFF, sum = 0
6543 11:38:38.422979 9, 0xFFFF, sum = 0
6544 11:38:38.423485 10, 0xFFFF, sum = 0
6545 11:38:38.425381 11, 0xFFFF, sum = 0
6546 11:38:38.425890 12, 0x0, sum = 1
6547 11:38:38.428408 13, 0x0, sum = 2
6548 11:38:38.428839 14, 0x0, sum = 3
6549 11:38:38.431938 15, 0x0, sum = 4
6550 11:38:38.432454 best_step = 13
6551 11:38:38.432783
6552 11:38:38.433088 ==
6553 11:38:38.434775 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 11:38:38.441863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 11:38:38.442363 ==
6556 11:38:38.442696 RX Vref Scan: 1
6557 11:38:38.443005
6558 11:38:38.444757 RX Vref 0 -> 0, step: 1
6559 11:38:38.445178
6560 11:38:38.448851 RX Delay -359 -> 252, step: 8
6561 11:38:38.449380
6562 11:38:38.451655 Set Vref, RX VrefLevel [Byte0]: 53
6563 11:38:38.456241 [Byte1]: 49
6564 11:38:38.457937
6565 11:38:38.458375 Final RX Vref Byte 0 = 53 to rank0
6566 11:38:38.461181 Final RX Vref Byte 1 = 49 to rank0
6567 11:38:38.464889 Final RX Vref Byte 0 = 53 to rank1
6568 11:38:38.467641 Final RX Vref Byte 1 = 49 to rank1==
6569 11:38:38.471354 Dram Type= 6, Freq= 0, CH_1, rank 0
6570 11:38:38.478290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6571 11:38:38.478798 ==
6572 11:38:38.479133 DQS Delay:
6573 11:38:38.480827 DQS0 = 48, DQS1 = 64
6574 11:38:38.481282 DQM Delay:
6575 11:38:38.481622 DQM0 = 9, DQM1 = 16
6576 11:38:38.484580 DQ Delay:
6577 11:38:38.487391 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6578 11:38:38.487829 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6579 11:38:38.490970 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6580 11:38:38.494579 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6581 11:38:38.495086
6582 11:38:38.495422
6583 11:38:38.504189 [DQSOSCAuto] RK0, (LSB)MR18= 0xdede, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6584 11:38:38.507672 CH1 RK0: MR19=C0C, MR18=DEDE
6585 11:38:38.514455 CH1_RK0: MR19=0xC0C, MR18=0xDEDE, DQSOSC=382, MR23=63, INC=404, DEC=269
6586 11:38:38.514982 ==
6587 11:38:38.517545 Dram Type= 6, Freq= 0, CH_1, rank 1
6588 11:38:38.520789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6589 11:38:38.521220 ==
6590 11:38:38.524370 [Gating] SW mode calibration
6591 11:38:38.530412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6592 11:38:38.538489 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6593 11:38:38.540541 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6594 11:38:38.544022 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6595 11:38:38.550404 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6596 11:38:38.553787 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6597 11:38:38.557200 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6598 11:38:38.560793 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6599 11:38:38.567231 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6600 11:38:38.570655 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6601 11:38:38.573529 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6602 11:38:38.577333 Total UI for P1: 0, mck2ui 16
6603 11:38:38.580644 best dqsien dly found for B0: ( 0, 10, 16)
6604 11:38:38.583363 Total UI for P1: 0, mck2ui 16
6605 11:38:38.586793 best dqsien dly found for B1: ( 0, 10, 16)
6606 11:38:38.593397 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6607 11:38:38.596771 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6608 11:38:38.597196
6609 11:38:38.600062 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6610 11:38:38.603568 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6611 11:38:38.606351 [Gating] SW calibration Done
6612 11:38:38.606777 ==
6613 11:38:38.609875 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 11:38:38.614263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6615 11:38:38.614760 ==
6616 11:38:38.616355 RX Vref Scan: 0
6617 11:38:38.616778
6618 11:38:38.617107 RX Vref 0 -> 0, step: 1
6619 11:38:38.617453
6620 11:38:38.619894 RX Delay -410 -> 252, step: 16
6621 11:38:38.626321 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6622 11:38:38.630160 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6623 11:38:38.632902 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6624 11:38:38.636273 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6625 11:38:38.643123 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6626 11:38:38.646148 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6627 11:38:38.649488 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6628 11:38:38.652925 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6629 11:38:38.659638 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6630 11:38:38.662606 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6631 11:38:38.666541 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6632 11:38:38.669119 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6633 11:38:38.676439 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6634 11:38:38.679463 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6635 11:38:38.683420 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6636 11:38:38.689518 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6637 11:38:38.689951 ==
6638 11:38:38.692782 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 11:38:38.695666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6640 11:38:38.696176 ==
6641 11:38:38.696508 DQS Delay:
6642 11:38:38.699716 DQS0 = 35, DQS1 = 59
6643 11:38:38.700140 DQM Delay:
6644 11:38:38.702609 DQM0 = 3, DQM1 = 17
6645 11:38:38.703039 DQ Delay:
6646 11:38:38.705709 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6647 11:38:38.709044 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6648 11:38:38.712275 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6649 11:38:38.715583 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6650 11:38:38.716012
6651 11:38:38.716346
6652 11:38:38.716966 ==
6653 11:38:38.719137 Dram Type= 6, Freq= 0, CH_1, rank 1
6654 11:38:38.721733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6655 11:38:38.722183 ==
6656 11:38:38.722517
6657 11:38:38.722821
6658 11:38:38.725374 TX Vref Scan disable
6659 11:38:38.725808 == TX Byte 0 ==
6660 11:38:38.732217 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6661 11:38:38.736167 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6662 11:38:38.736662 == TX Byte 1 ==
6663 11:38:38.743044 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6664 11:38:38.745464 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6665 11:38:38.745901 ==
6666 11:38:38.748339 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 11:38:38.752044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6668 11:38:38.752550 ==
6669 11:38:38.752884
6670 11:38:38.753184
6671 11:38:38.755405 TX Vref Scan disable
6672 11:38:38.755829 == TX Byte 0 ==
6673 11:38:38.761711 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6674 11:38:38.765205 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6675 11:38:38.765675 == TX Byte 1 ==
6676 11:38:38.771953 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6677 11:38:38.776636 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6678 11:38:38.777063
6679 11:38:38.777526 [DATLAT]
6680 11:38:38.778540 Freq=400, CH1 RK1
6681 11:38:38.778932
6682 11:38:38.779231 DATLAT Default: 0xd
6683 11:38:38.782211 0, 0xFFFF, sum = 0
6684 11:38:38.782605 1, 0xFFFF, sum = 0
6685 11:38:38.784916 2, 0xFFFF, sum = 0
6686 11:38:38.785350 3, 0xFFFF, sum = 0
6687 11:38:38.788326 4, 0xFFFF, sum = 0
6688 11:38:38.788717 5, 0xFFFF, sum = 0
6689 11:38:38.791300 6, 0xFFFF, sum = 0
6690 11:38:38.791692 7, 0xFFFF, sum = 0
6691 11:38:38.796827 8, 0xFFFF, sum = 0
6692 11:38:38.797359 9, 0xFFFF, sum = 0
6693 11:38:38.798091 10, 0xFFFF, sum = 0
6694 11:38:38.801783 11, 0xFFFF, sum = 0
6695 11:38:38.802177 12, 0x0, sum = 1
6696 11:38:38.802483 13, 0x0, sum = 2
6697 11:38:38.805202 14, 0x0, sum = 3
6698 11:38:38.805628 15, 0x0, sum = 4
6699 11:38:38.808163 best_step = 13
6700 11:38:38.808547
6701 11:38:38.808842 ==
6702 11:38:38.812134 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 11:38:38.815202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 11:38:38.815670 ==
6705 11:38:38.817945 RX Vref Scan: 0
6706 11:38:38.818329
6707 11:38:38.818627 RX Vref 0 -> 0, step: 1
6708 11:38:38.821411
6709 11:38:38.821796 RX Delay -359 -> 252, step: 8
6710 11:38:38.829799 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6711 11:38:38.833087 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6712 11:38:38.836852 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6713 11:38:38.841279 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6714 11:38:38.846377 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6715 11:38:38.849884 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6716 11:38:38.852799 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6717 11:38:38.856396 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6718 11:38:38.863099 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6719 11:38:38.867198 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6720 11:38:38.871131 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6721 11:38:38.876165 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6722 11:38:38.880856 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6723 11:38:38.883217 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6724 11:38:38.887148 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6725 11:38:38.892769 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6726 11:38:38.893356 ==
6727 11:38:38.896089 Dram Type= 6, Freq= 0, CH_1, rank 1
6728 11:38:38.899302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6729 11:38:38.899733 ==
6730 11:38:38.900064 DQS Delay:
6731 11:38:38.902867 DQS0 = 44, DQS1 = 64
6732 11:38:38.903293 DQM Delay:
6733 11:38:38.906989 DQM0 = 6, DQM1 = 15
6734 11:38:38.907500 DQ Delay:
6735 11:38:38.909914 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =0
6736 11:38:38.912754 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6737 11:38:38.916004 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6738 11:38:38.919364 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6739 11:38:38.919884
6740 11:38:38.920220
6741 11:38:38.927113 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6742 11:38:38.929163 CH1 RK1: MR19=C0C, MR18=BABA
6743 11:38:38.935744 CH1_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6744 11:38:38.939170 [RxdqsGatingPostProcess] freq 400
6745 11:38:38.946284 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6746 11:38:38.946790 Pre-setting of DQS Precalculation
6747 11:38:38.952773 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6748 11:38:38.959115 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6749 11:38:38.966956 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6750 11:38:38.967485
6751 11:38:38.967824
6752 11:38:38.968972 [Calibration Summary] 800 Mbps
6753 11:38:38.972398 CH 0, Rank 0
6754 11:38:38.972904 SW Impedance : PASS
6755 11:38:38.975914 DUTY Scan : NO K
6756 11:38:38.979957 ZQ Calibration : PASS
6757 11:38:38.980473 Jitter Meter : NO K
6758 11:38:38.982526 CBT Training : PASS
6759 11:38:38.985632 Write leveling : PASS
6760 11:38:38.986146 RX DQS gating : PASS
6761 11:38:38.989076 RX DQ/DQS(RDDQC) : PASS
6762 11:38:38.989548 TX DQ/DQS : PASS
6763 11:38:38.991953 RX DATLAT : PASS
6764 11:38:38.995913 RX DQ/DQS(Engine): PASS
6765 11:38:38.996418 TX OE : NO K
6766 11:38:38.998596 All Pass.
6767 11:38:38.999036
6768 11:38:38.999369 CH 0, Rank 1
6769 11:38:39.002397 SW Impedance : PASS
6770 11:38:39.002905 DUTY Scan : NO K
6771 11:38:39.006338 ZQ Calibration : PASS
6772 11:38:39.009344 Jitter Meter : NO K
6773 11:38:39.009771 CBT Training : PASS
6774 11:38:39.012214 Write leveling : NO K
6775 11:38:39.016385 RX DQS gating : PASS
6776 11:38:39.016893 RX DQ/DQS(RDDQC) : PASS
6777 11:38:39.019102 TX DQ/DQS : PASS
6778 11:38:39.022469 RX DATLAT : PASS
6779 11:38:39.022900 RX DQ/DQS(Engine): PASS
6780 11:38:39.025792 TX OE : NO K
6781 11:38:39.026301 All Pass.
6782 11:38:39.026738
6783 11:38:39.028658 CH 1, Rank 0
6784 11:38:39.029083 SW Impedance : PASS
6785 11:38:39.031731 DUTY Scan : NO K
6786 11:38:39.036012 ZQ Calibration : PASS
6787 11:38:39.036523 Jitter Meter : NO K
6788 11:38:39.038408 CBT Training : PASS
6789 11:38:39.041924 Write leveling : PASS
6790 11:38:39.042354 RX DQS gating : PASS
6791 11:38:39.045291 RX DQ/DQS(RDDQC) : PASS
6792 11:38:39.045721 TX DQ/DQS : PASS
6793 11:38:39.049000 RX DATLAT : PASS
6794 11:38:39.051744 RX DQ/DQS(Engine): PASS
6795 11:38:39.052170 TX OE : NO K
6796 11:38:39.055806 All Pass.
6797 11:38:39.056339
6798 11:38:39.056676 CH 1, Rank 1
6799 11:38:39.058621 SW Impedance : PASS
6800 11:38:39.059049 DUTY Scan : NO K
6801 11:38:39.062508 ZQ Calibration : PASS
6802 11:38:39.065728 Jitter Meter : NO K
6803 11:38:39.066230 CBT Training : PASS
6804 11:38:39.068643 Write leveling : NO K
6805 11:38:39.072453 RX DQS gating : PASS
6806 11:38:39.072961 RX DQ/DQS(RDDQC) : PASS
6807 11:38:39.075478 TX DQ/DQS : PASS
6808 11:38:39.078412 RX DATLAT : PASS
6809 11:38:39.078923 RX DQ/DQS(Engine): PASS
6810 11:38:39.082078 TX OE : NO K
6811 11:38:39.082524 All Pass.
6812 11:38:39.082854
6813 11:38:39.085474 DramC Write-DBI off
6814 11:38:39.088395 PER_BANK_REFRESH: Hybrid Mode
6815 11:38:39.089005 TX_TRACKING: ON
6816 11:38:39.099454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6817 11:38:39.101891 [FAST_K] Save calibration result to emmc
6818 11:38:39.105179 dramc_set_vcore_voltage set vcore to 725000
6819 11:38:39.108110 Read voltage for 1600, 0
6820 11:38:39.108545 Vio18 = 0
6821 11:38:39.108877 Vcore = 725000
6822 11:38:39.111801 Vdram = 0
6823 11:38:39.112307 Vddq = 0
6824 11:38:39.112637 Vmddr = 0
6825 11:38:39.118980 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6826 11:38:39.121722 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6827 11:38:39.125975 MEM_TYPE=3, freq_sel=13
6828 11:38:39.128556 sv_algorithm_assistance_LP4_3733
6829 11:38:39.132584 ============ PULL DRAM RESETB DOWN ============
6830 11:38:39.134783 ========== PULL DRAM RESETB DOWN end =========
6831 11:38:39.141493 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6832 11:38:39.144698 ===================================
6833 11:38:39.148070 LPDDR4 DRAM CONFIGURATION
6834 11:38:39.151460 ===================================
6835 11:38:39.151988 EX_ROW_EN[0] = 0x0
6836 11:38:39.154767 EX_ROW_EN[1] = 0x0
6837 11:38:39.155191 LP4Y_EN = 0x0
6838 11:38:39.157635 WORK_FSP = 0x1
6839 11:38:39.158063 WL = 0x5
6840 11:38:39.161432 RL = 0x5
6841 11:38:39.161956 BL = 0x2
6842 11:38:39.164441 RPST = 0x0
6843 11:38:39.164946 RD_PRE = 0x0
6844 11:38:39.168154 WR_PRE = 0x1
6845 11:38:39.168682 WR_PST = 0x1
6846 11:38:39.171137 DBI_WR = 0x0
6847 11:38:39.171642 DBI_RD = 0x0
6848 11:38:39.174580 OTF = 0x1
6849 11:38:39.177729 ===================================
6850 11:38:39.181390 ===================================
6851 11:38:39.181899 ANA top config
6852 11:38:39.184113 ===================================
6853 11:38:39.187549 DLL_ASYNC_EN = 0
6854 11:38:39.191033 ALL_SLAVE_EN = 0
6855 11:38:39.194173 NEW_RANK_MODE = 1
6856 11:38:39.198199 DLL_IDLE_MODE = 1
6857 11:38:39.198705 LP45_APHY_COMB_EN = 1
6858 11:38:39.201118 TX_ODT_DIS = 0
6859 11:38:39.204612 NEW_8X_MODE = 1
6860 11:38:39.207824 ===================================
6861 11:38:39.210489 ===================================
6862 11:38:39.214690 data_rate = 3200
6863 11:38:39.217461 CKR = 1
6864 11:38:39.217975 DQ_P2S_RATIO = 8
6865 11:38:39.221477 ===================================
6866 11:38:39.223797 CA_P2S_RATIO = 8
6867 11:38:39.227210 DQ_CA_OPEN = 0
6868 11:38:39.231272 DQ_SEMI_OPEN = 0
6869 11:38:39.234718 CA_SEMI_OPEN = 0
6870 11:38:39.237218 CA_FULL_RATE = 0
6871 11:38:39.237752 DQ_CKDIV4_EN = 0
6872 11:38:39.241015 CA_CKDIV4_EN = 0
6873 11:38:39.244127 CA_PREDIV_EN = 0
6874 11:38:39.247179 PH8_DLY = 12
6875 11:38:39.250766 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6876 11:38:39.253472 DQ_AAMCK_DIV = 4
6877 11:38:39.253901 CA_AAMCK_DIV = 4
6878 11:38:39.256919 CA_ADMCK_DIV = 4
6879 11:38:39.260557 DQ_TRACK_CA_EN = 0
6880 11:38:39.264066 CA_PICK = 1600
6881 11:38:39.267028 CA_MCKIO = 1600
6882 11:38:39.270066 MCKIO_SEMI = 0
6883 11:38:39.273810 PLL_FREQ = 3068
6884 11:38:39.277640 DQ_UI_PI_RATIO = 32
6885 11:38:39.278073 CA_UI_PI_RATIO = 0
6886 11:38:39.280676 ===================================
6887 11:38:39.284229 ===================================
6888 11:38:39.287183 memory_type:LPDDR4
6889 11:38:39.289771 GP_NUM : 10
6890 11:38:39.290359 SRAM_EN : 1
6891 11:38:39.293138 MD32_EN : 0
6892 11:38:39.296587 ===================================
6893 11:38:39.300281 [ANA_INIT] >>>>>>>>>>>>>>
6894 11:38:39.303070 <<<<<< [CONFIGURE PHASE]: ANA_TX
6895 11:38:39.306645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6896 11:38:39.309917 ===================================
6897 11:38:39.310348 data_rate = 3200,PCW = 0X7600
6898 11:38:39.313765 ===================================
6899 11:38:39.316334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6900 11:38:39.323216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6901 11:38:39.330272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6902 11:38:39.332863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6903 11:38:39.336144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6904 11:38:39.339808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6905 11:38:39.343415 [ANA_INIT] flow start
6906 11:38:39.346694 [ANA_INIT] PLL >>>>>>>>
6907 11:38:39.347199 [ANA_INIT] PLL <<<<<<<<
6908 11:38:39.349814 [ANA_INIT] MIDPI >>>>>>>>
6909 11:38:39.352463 [ANA_INIT] MIDPI <<<<<<<<
6910 11:38:39.352891 [ANA_INIT] DLL >>>>>>>>
6911 11:38:39.356132 [ANA_INIT] DLL <<<<<<<<
6912 11:38:39.359645 [ANA_INIT] flow end
6913 11:38:39.362783 ============ LP4 DIFF to SE enter ============
6914 11:38:39.366388 ============ LP4 DIFF to SE exit ============
6915 11:38:39.369524 [ANA_INIT] <<<<<<<<<<<<<
6916 11:38:39.372730 [Flow] Enable top DCM control >>>>>
6917 11:38:39.376584 [Flow] Enable top DCM control <<<<<
6918 11:38:39.379497 Enable DLL master slave shuffle
6919 11:38:39.382409 ==============================================================
6920 11:38:39.386095 Gating Mode config
6921 11:38:39.392730 ==============================================================
6922 11:38:39.393293 Config description:
6923 11:38:39.402327 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6924 11:38:39.409368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6925 11:38:39.415934 SELPH_MODE 0: By rank 1: By Phase
6926 11:38:39.419437 ==============================================================
6927 11:38:39.422780 GAT_TRACK_EN = 1
6928 11:38:39.426050 RX_GATING_MODE = 2
6929 11:38:39.428979 RX_GATING_TRACK_MODE = 2
6930 11:38:39.432719 SELPH_MODE = 1
6931 11:38:39.436042 PICG_EARLY_EN = 1
6932 11:38:39.438959 VALID_LAT_VALUE = 1
6933 11:38:39.442213 ==============================================================
6934 11:38:39.445440 Enter into Gating configuration >>>>
6935 11:38:39.449026 Exit from Gating configuration <<<<
6936 11:38:39.452112 Enter into DVFS_PRE_config >>>>>
6937 11:38:39.465275 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6938 11:38:39.468854 Exit from DVFS_PRE_config <<<<<
6939 11:38:39.471759 Enter into PICG configuration >>>>
6940 11:38:39.472269 Exit from PICG configuration <<<<
6941 11:38:39.475225 [RX_INPUT] configuration >>>>>
6942 11:38:39.478186 [RX_INPUT] configuration <<<<<
6943 11:38:39.485864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6944 11:38:39.488861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6945 11:38:39.494639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6946 11:38:39.501538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6947 11:38:39.507898 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6948 11:38:39.515111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6949 11:38:39.518469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6950 11:38:39.521796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6951 11:38:39.528841 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6952 11:38:39.531455 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6953 11:38:39.535189 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6954 11:38:39.537783 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6955 11:38:39.541690 ===================================
6956 11:38:39.544389 LPDDR4 DRAM CONFIGURATION
6957 11:38:39.547803 ===================================
6958 11:38:39.551065 EX_ROW_EN[0] = 0x0
6959 11:38:39.551572 EX_ROW_EN[1] = 0x0
6960 11:38:39.554407 LP4Y_EN = 0x0
6961 11:38:39.554911 WORK_FSP = 0x1
6962 11:38:39.557817 WL = 0x5
6963 11:38:39.558240 RL = 0x5
6964 11:38:39.561615 BL = 0x2
6965 11:38:39.562122 RPST = 0x0
6966 11:38:39.565285 RD_PRE = 0x0
6967 11:38:39.565715 WR_PRE = 0x1
6968 11:38:39.567789 WR_PST = 0x1
6969 11:38:39.568293 DBI_WR = 0x0
6970 11:38:39.571101 DBI_RD = 0x0
6971 11:38:39.574573 OTF = 0x1
6972 11:38:39.577727 ===================================
6973 11:38:39.581184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6974 11:38:39.584723 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6975 11:38:39.588061 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6976 11:38:39.590836 ===================================
6977 11:38:39.594459 LPDDR4 DRAM CONFIGURATION
6978 11:38:39.598023 ===================================
6979 11:38:39.600996 EX_ROW_EN[0] = 0x10
6980 11:38:39.601456 EX_ROW_EN[1] = 0x0
6981 11:38:39.604034 LP4Y_EN = 0x0
6982 11:38:39.604494 WORK_FSP = 0x1
6983 11:38:39.607555 WL = 0x5
6984 11:38:39.608057 RL = 0x5
6985 11:38:39.610743 BL = 0x2
6986 11:38:39.611166 RPST = 0x0
6987 11:38:39.614212 RD_PRE = 0x0
6988 11:38:39.614638 WR_PRE = 0x1
6989 11:38:39.617468 WR_PST = 0x1
6990 11:38:39.621196 DBI_WR = 0x0
6991 11:38:39.621656 DBI_RD = 0x0
6992 11:38:39.624042 OTF = 0x1
6993 11:38:39.627257 ===================================
6994 11:38:39.630852 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6995 11:38:39.634454 ==
6996 11:38:39.634954 Dram Type= 6, Freq= 0, CH_0, rank 0
6997 11:38:39.640545 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6998 11:38:39.641048 ==
6999 11:38:39.643330 [Duty_Offset_Calibration]
7000 11:38:39.643773 B0:0 B1:2 CA:1
7001 11:38:39.644103
7002 11:38:39.647144 [DutyScan_Calibration_Flow] k_type=0
7003 11:38:39.657007
7004 11:38:39.657572 ==CLK 0==
7005 11:38:39.660155 Final CLK duty delay cell = 0
7006 11:38:39.664001 [0] MAX Duty = 5156%(X100), DQS PI = 22
7007 11:38:39.666850 [0] MIN Duty = 4907%(X100), DQS PI = 54
7008 11:38:39.670810 [0] AVG Duty = 5031%(X100)
7009 11:38:39.671312
7010 11:38:39.673274 CH0 CLK Duty spec in!! Max-Min= 249%
7011 11:38:39.676385 [DutyScan_Calibration_Flow] ====Done====
7012 11:38:39.676813
7013 11:38:39.680207 [DutyScan_Calibration_Flow] k_type=1
7014 11:38:39.697465
7015 11:38:39.697963 ==DQS 0 ==
7016 11:38:39.700389 Final DQS duty delay cell = 0
7017 11:38:39.703600 [0] MAX Duty = 5156%(X100), DQS PI = 32
7018 11:38:39.707018 [0] MIN Duty = 5031%(X100), DQS PI = 10
7019 11:38:39.710094 [0] AVG Duty = 5093%(X100)
7020 11:38:39.710517
7021 11:38:39.710845 ==DQS 1 ==
7022 11:38:39.713120 Final DQS duty delay cell = 0
7023 11:38:39.717300 [0] MAX Duty = 5031%(X100), DQS PI = 46
7024 11:38:39.720375 [0] MIN Duty = 4876%(X100), DQS PI = 16
7025 11:38:39.723651 [0] AVG Duty = 4953%(X100)
7026 11:38:39.724152
7027 11:38:39.727289 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7028 11:38:39.727717
7029 11:38:39.729823 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7030 11:38:39.733076 [DutyScan_Calibration_Flow] ====Done====
7031 11:38:39.733642
7032 11:38:39.736823 [DutyScan_Calibration_Flow] k_type=3
7033 11:38:39.754529
7034 11:38:39.755028 ==DQM 0 ==
7035 11:38:39.757436 Final DQM duty delay cell = 0
7036 11:38:39.760569 [0] MAX Duty = 5187%(X100), DQS PI = 22
7037 11:38:39.763917 [0] MIN Duty = 4876%(X100), DQS PI = 56
7038 11:38:39.768368 [0] AVG Duty = 5031%(X100)
7039 11:38:39.768868
7040 11:38:39.769200 ==DQM 1 ==
7041 11:38:39.770483 Final DQM duty delay cell = 0
7042 11:38:39.774475 [0] MAX Duty = 5031%(X100), DQS PI = 50
7043 11:38:39.777873 [0] MIN Duty = 4782%(X100), DQS PI = 14
7044 11:38:39.780958 [0] AVG Duty = 4906%(X100)
7045 11:38:39.781594
7046 11:38:39.783733 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7047 11:38:39.784158
7048 11:38:39.788085 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7049 11:38:39.790852 [DutyScan_Calibration_Flow] ====Done====
7050 11:38:39.791410
7051 11:38:39.794199 [DutyScan_Calibration_Flow] k_type=2
7052 11:38:39.810218
7053 11:38:39.810729 ==DQ 0 ==
7054 11:38:39.813423 Final DQ duty delay cell = 0
7055 11:38:39.817735 [0] MAX Duty = 5218%(X100), DQS PI = 18
7056 11:38:39.820055 [0] MIN Duty = 4938%(X100), DQS PI = 56
7057 11:38:39.820560 [0] AVG Duty = 5078%(X100)
7058 11:38:39.823915
7059 11:38:39.824409 ==DQ 1 ==
7060 11:38:39.827682 Final DQ duty delay cell = -4
7061 11:38:39.829953 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7062 11:38:39.834186 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7063 11:38:39.837420 [-4] AVG Duty = 4953%(X100)
7064 11:38:39.837843
7065 11:38:39.840810 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7066 11:38:39.841366
7067 11:38:39.843854 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7068 11:38:39.846901 [DutyScan_Calibration_Flow] ====Done====
7069 11:38:39.847329 ==
7070 11:38:39.850473 Dram Type= 6, Freq= 0, CH_1, rank 0
7071 11:38:39.853966 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7072 11:38:39.854639 ==
7073 11:38:39.857078 [Duty_Offset_Calibration]
7074 11:38:39.857920 B0:0 B1:4 CA:-5
7075 11:38:39.858501
7076 11:38:39.860594 [DutyScan_Calibration_Flow] k_type=0
7077 11:38:39.871138
7078 11:38:39.871631 ==CLK 0==
7079 11:38:39.874131 Final CLK duty delay cell = 0
7080 11:38:39.877557 [0] MAX Duty = 5156%(X100), DQS PI = 22
7081 11:38:39.881021 [0] MIN Duty = 4875%(X100), DQS PI = 54
7082 11:38:39.884866 [0] AVG Duty = 5015%(X100)
7083 11:38:39.885589
7084 11:38:39.887626 CH1 CLK Duty spec in!! Max-Min= 281%
7085 11:38:39.891332 [DutyScan_Calibration_Flow] ====Done====
7086 11:38:39.891753
7087 11:38:39.893636 [DutyScan_Calibration_Flow] k_type=1
7088 11:38:39.910195
7089 11:38:39.910690 ==DQS 0 ==
7090 11:38:39.912983 Final DQS duty delay cell = 0
7091 11:38:39.916688 [0] MAX Duty = 5187%(X100), DQS PI = 18
7092 11:38:39.920697 [0] MIN Duty = 4876%(X100), DQS PI = 42
7093 11:38:39.923061 [0] AVG Duty = 5031%(X100)
7094 11:38:39.923478
7095 11:38:39.923853 ==DQS 1 ==
7096 11:38:39.926173 Final DQS duty delay cell = -4
7097 11:38:39.929851 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7098 11:38:39.933800 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7099 11:38:39.937367 [-4] AVG Duty = 4922%(X100)
7100 11:38:39.937865
7101 11:38:39.940166 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7102 11:38:39.940696
7103 11:38:39.943263 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7104 11:38:39.946461 [DutyScan_Calibration_Flow] ====Done====
7105 11:38:39.946888
7106 11:38:39.950057 [DutyScan_Calibration_Flow] k_type=3
7107 11:38:39.965674
7108 11:38:39.966100 ==DQM 0 ==
7109 11:38:39.968595 Final DQM duty delay cell = -4
7110 11:38:39.972331 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7111 11:38:39.976031 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7112 11:38:39.978979 [-4] AVG Duty = 4922%(X100)
7113 11:38:39.979404
7114 11:38:39.979732 ==DQM 1 ==
7115 11:38:39.981973 Final DQM duty delay cell = -4
7116 11:38:39.985182 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7117 11:38:39.989173 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7118 11:38:39.992020 [-4] AVG Duty = 4984%(X100)
7119 11:38:39.992404
7120 11:38:39.995560 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7121 11:38:39.995947
7122 11:38:39.998434 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7123 11:38:40.002651 [DutyScan_Calibration_Flow] ====Done====
7124 11:38:40.003112
7125 11:38:40.005459 [DutyScan_Calibration_Flow] k_type=2
7126 11:38:40.023514
7127 11:38:40.024015 ==DQ 0 ==
7128 11:38:40.026631 Final DQ duty delay cell = 0
7129 11:38:40.029822 [0] MAX Duty = 5093%(X100), DQS PI = 34
7130 11:38:40.033388 [0] MIN Duty = 4938%(X100), DQS PI = 48
7131 11:38:40.036827 [0] AVG Duty = 5015%(X100)
7132 11:38:40.037363
7133 11:38:40.037704 ==DQ 1 ==
7134 11:38:40.039344 Final DQ duty delay cell = 0
7135 11:38:40.043238 [0] MAX Duty = 5031%(X100), DQS PI = 2
7136 11:38:40.046297 [0] MIN Duty = 4876%(X100), DQS PI = 28
7137 11:38:40.046802 [0] AVG Duty = 4953%(X100)
7138 11:38:40.050013
7139 11:38:40.052474 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7140 11:38:40.052945
7141 11:38:40.055887 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7142 11:38:40.059390 [DutyScan_Calibration_Flow] ====Done====
7143 11:38:40.062490 nWR fixed to 30
7144 11:38:40.062722 [ModeRegInit_LP4] CH0 RK0
7145 11:38:40.066138 [ModeRegInit_LP4] CH0 RK1
7146 11:38:40.070184 [ModeRegInit_LP4] CH1 RK0
7147 11:38:40.073037 [ModeRegInit_LP4] CH1 RK1
7148 11:38:40.073335 match AC timing 4
7149 11:38:40.079058 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7150 11:38:40.082912 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7151 11:38:40.087036 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7152 11:38:40.092546 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7153 11:38:40.096373 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7154 11:38:40.096803 [MiockJmeterHQA]
7155 11:38:40.097130
7156 11:38:40.098751 [DramcMiockJmeter] u1RxGatingPI = 0
7157 11:38:40.102045 0 : 4252, 4027
7158 11:38:40.102477 4 : 4253, 4026
7159 11:38:40.105366 8 : 4253, 4026
7160 11:38:40.105743 12 : 4253, 4027
7161 11:38:40.108729 16 : 4254, 4029
7162 11:38:40.109278 20 : 4363, 4137
7163 11:38:40.109633 24 : 4364, 4137
7164 11:38:40.112522 28 : 4252, 4027
7165 11:38:40.113023 32 : 4253, 4026
7166 11:38:40.117389 36 : 4253, 4026
7167 11:38:40.117893 40 : 4250, 4027
7168 11:38:40.118681 44 : 4255, 4030
7169 11:38:40.119044 48 : 4361, 4138
7170 11:38:40.122804 52 : 4253, 4027
7171 11:38:40.123310 56 : 4250, 4026
7172 11:38:40.123653 60 : 4252, 4027
7173 11:38:40.125417 64 : 4252, 4029
7174 11:38:40.125921 68 : 4250, 4026
7175 11:38:40.128555 72 : 4360, 4138
7176 11:38:40.128986 76 : 4361, 4137
7177 11:38:40.132933 80 : 4250, 4027
7178 11:38:40.133501 84 : 4250, 4027
7179 11:38:40.133843 88 : 4250, 4027
7180 11:38:40.135439 92 : 4250, 4027
7181 11:38:40.135871 96 : 4253, 4029
7182 11:38:40.138503 100 : 4361, 2055
7183 11:38:40.138935 104 : 4253, 0
7184 11:38:40.142187 108 : 4253, 0
7185 11:38:40.142691 112 : 4250, 0
7186 11:38:40.143030 116 : 4253, 0
7187 11:38:40.145804 120 : 4250, 0
7188 11:38:40.146238 124 : 4364, 0
7189 11:38:40.148666 128 : 4363, 0
7190 11:38:40.149166 132 : 4252, 0
7191 11:38:40.149566 136 : 4361, 0
7192 11:38:40.151991 140 : 4250, 0
7193 11:38:40.152499 144 : 4250, 0
7194 11:38:40.155382 148 : 4250, 0
7195 11:38:40.155889 152 : 4250, 0
7196 11:38:40.156229 156 : 4250, 0
7197 11:38:40.158651 160 : 4250, 0
7198 11:38:40.159156 164 : 4253, 0
7199 11:38:40.159498 168 : 4252, 0
7200 11:38:40.161989 172 : 4250, 0
7201 11:38:40.162420 176 : 4253, 0
7202 11:38:40.165118 180 : 4250, 0
7203 11:38:40.165590 184 : 4360, 0
7204 11:38:40.165929 188 : 4361, 0
7205 11:38:40.169062 192 : 4250, 0
7206 11:38:40.169618 196 : 4250, 0
7207 11:38:40.171782 200 : 4250, 0
7208 11:38:40.172288 204 : 4252, 0
7209 11:38:40.172624 208 : 4252, 0
7210 11:38:40.175915 212 : 4250, 0
7211 11:38:40.176420 216 : 4253, 0
7212 11:38:40.178224 220 : 4250, 199
7213 11:38:40.178654 224 : 4361, 4051
7214 11:38:40.181947 228 : 4250, 4027
7215 11:38:40.182449 232 : 4250, 4027
7216 11:38:40.182785 236 : 4250, 4026
7217 11:38:40.185427 240 : 4253, 4029
7218 11:38:40.185993 244 : 4250, 4027
7219 11:38:40.188324 248 : 4250, 4027
7220 11:38:40.188754 252 : 4363, 4137
7221 11:38:40.191807 256 : 4250, 4027
7222 11:38:40.192243 260 : 4250, 4026
7223 11:38:40.195437 264 : 4361, 4138
7224 11:38:40.195871 268 : 4250, 4027
7225 11:38:40.200545 272 : 4253, 4026
7226 11:38:40.200977 276 : 4363, 4140
7227 11:38:40.202235 280 : 4250, 4026
7228 11:38:40.202672 284 : 4250, 4027
7229 11:38:40.205367 288 : 4250, 4027
7230 11:38:40.205872 292 : 4253, 4029
7231 11:38:40.206208 296 : 4250, 4026
7232 11:38:40.208422 300 : 4250, 4027
7233 11:38:40.208858 304 : 4360, 4137
7234 11:38:40.212398 308 : 4249, 4027
7235 11:38:40.212897 312 : 4250, 4027
7236 11:38:40.215396 316 : 4361, 4138
7237 11:38:40.215830 320 : 4250, 4027
7238 11:38:40.219154 324 : 4250, 4026
7239 11:38:40.219665 328 : 4364, 4140
7240 11:38:40.221873 332 : 4252, 4029
7241 11:38:40.222379 336 : 4250, 3969
7242 11:38:40.225545 340 : 4250, 2125
7243 11:38:40.226050 344 : 4253, 0
7244 11:38:40.226388
7245 11:38:40.229191 MIOCK jitter meter ch=0
7246 11:38:40.229761
7247 11:38:40.232014 1T = (344-100) = 244 dly cells
7248 11:38:40.234745 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 266/100 ps
7249 11:38:40.235177 ==
7250 11:38:40.238650 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 11:38:40.244947 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7252 11:38:40.245482 ==
7253 11:38:40.248313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7254 11:38:40.254969 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7255 11:38:40.258503 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7256 11:38:40.265352 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7257 11:38:40.271984 [CA 0] Center 42 (12~73) winsize 62
7258 11:38:40.275569 [CA 1] Center 42 (12~73) winsize 62
7259 11:38:40.278239 [CA 2] Center 39 (9~69) winsize 61
7260 11:38:40.282133 [CA 3] Center 38 (9~68) winsize 60
7261 11:38:40.285582 [CA 4] Center 37 (7~67) winsize 61
7262 11:38:40.288849 [CA 5] Center 36 (6~66) winsize 61
7263 11:38:40.289427
7264 11:38:40.292169 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7265 11:38:40.292594
7266 11:38:40.294717 [CATrainingPosCal] consider 1 rank data
7267 11:38:40.298384 u2DelayCellTimex100 = 266/100 ps
7268 11:38:40.301733 CA0 delay=42 (12~73),Diff = 6 PI (22 cell)
7269 11:38:40.308126 CA1 delay=42 (12~73),Diff = 6 PI (22 cell)
7270 11:38:40.311456 CA2 delay=39 (9~69),Diff = 3 PI (11 cell)
7271 11:38:40.314937 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7272 11:38:40.318095 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7273 11:38:40.322172 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7274 11:38:40.322672
7275 11:38:40.324534 CA PerBit enable=1, Macro0, CA PI delay=36
7276 11:38:40.324963
7277 11:38:40.327822 [CBTSetCACLKResult] CA Dly = 36
7278 11:38:40.332613 CS Dly: 10 (0~41)
7279 11:38:40.335468 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7280 11:38:40.338511 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7281 11:38:40.339105 ==
7282 11:38:40.341409 Dram Type= 6, Freq= 0, CH_0, rank 1
7283 11:38:40.344434 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7284 11:38:40.348155 ==
7285 11:38:40.351198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7286 11:38:40.354391 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7287 11:38:40.361385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7288 11:38:40.367997 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7289 11:38:40.374972 [CA 0] Center 42 (12~73) winsize 62
7290 11:38:40.377931 [CA 1] Center 42 (12~73) winsize 62
7291 11:38:40.381453 [CA 2] Center 38 (9~68) winsize 60
7292 11:38:40.384771 [CA 3] Center 38 (9~67) winsize 59
7293 11:38:40.388568 [CA 4] Center 36 (6~66) winsize 61
7294 11:38:40.391241 [CA 5] Center 36 (6~66) winsize 61
7295 11:38:40.391738
7296 11:38:40.395288 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7297 11:38:40.395852
7298 11:38:40.398020 [CATrainingPosCal] consider 2 rank data
7299 11:38:40.400746 u2DelayCellTimex100 = 266/100 ps
7300 11:38:40.404651 CA0 delay=42 (12~73),Diff = 6 PI (22 cell)
7301 11:38:40.410971 CA1 delay=42 (12~73),Diff = 6 PI (22 cell)
7302 11:38:40.414456 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7303 11:38:40.417585 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7304 11:38:40.421030 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7305 11:38:40.424330 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7306 11:38:40.424745
7307 11:38:40.428053 CA PerBit enable=1, Macro0, CA PI delay=36
7308 11:38:40.428468
7309 11:38:40.431130 [CBTSetCACLKResult] CA Dly = 36
7310 11:38:40.433833 CS Dly: 10 (0~42)
7311 11:38:40.437483 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7312 11:38:40.441016 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7313 11:38:40.441466
7314 11:38:40.444136 ----->DramcWriteLeveling(PI) begin...
7315 11:38:40.444593 ==
7316 11:38:40.447487 Dram Type= 6, Freq= 0, CH_0, rank 0
7317 11:38:40.454152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7318 11:38:40.454717 ==
7319 11:38:40.457310 Write leveling (Byte 0): 29 => 29
7320 11:38:40.457727 Write leveling (Byte 1): 29 => 29
7321 11:38:40.461055 DramcWriteLeveling(PI) end<-----
7322 11:38:40.461620
7323 11:38:40.464204 ==
7324 11:38:40.464812 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 11:38:40.471290 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7326 11:38:40.471805 ==
7327 11:38:40.473355 [Gating] SW mode calibration
7328 11:38:40.480185 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7329 11:38:40.484472 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7330 11:38:40.491601 0 12 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7331 11:38:40.494438 0 12 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7332 11:38:40.496720 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 11:38:40.503790 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7334 11:38:40.507616 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7335 11:38:40.510827 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7336 11:38:40.517159 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7337 11:38:40.520427 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7338 11:38:40.523437 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7339 11:38:40.530035 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7340 11:38:40.533562 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7341 11:38:40.536777 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 11:38:40.543260 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7343 11:38:40.546847 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7344 11:38:40.549766 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7345 11:38:40.556710 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7346 11:38:40.560016 0 14 0 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7347 11:38:40.563263 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7348 11:38:40.572680 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 11:38:40.573695 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 11:38:40.576435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 11:38:40.584084 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 11:38:40.587485 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7353 11:38:40.589558 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7354 11:38:40.596336 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7355 11:38:40.599803 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7356 11:38:40.602717 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7357 11:38:40.609901 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 11:38:40.613051 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 11:38:40.618133 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 11:38:40.622985 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 11:38:40.626137 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 11:38:40.629751 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 11:38:40.635510 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 11:38:40.639408 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 11:38:40.643074 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 11:38:40.649743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 11:38:40.652465 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7368 11:38:40.656273 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7369 11:38:40.662625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7370 11:38:40.666184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7371 11:38:40.669116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7372 11:38:40.672547 Total UI for P1: 0, mck2ui 16
7373 11:38:40.675226 best dqsien dly found for B0: ( 1, 1, 0)
7374 11:38:40.680302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7375 11:38:40.683126 Total UI for P1: 0, mck2ui 16
7376 11:38:40.685347 best dqsien dly found for B1: ( 1, 1, 4)
7377 11:38:40.689368 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7378 11:38:40.691733 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7379 11:38:40.695440
7380 11:38:40.698934 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7381 11:38:40.702306 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7382 11:38:40.705477 [Gating] SW calibration Done
7383 11:38:40.705965 ==
7384 11:38:40.709073 Dram Type= 6, Freq= 0, CH_0, rank 0
7385 11:38:40.711992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7386 11:38:40.712589 ==
7387 11:38:40.712943 RX Vref Scan: 0
7388 11:38:40.713270
7389 11:38:40.714919 RX Vref 0 -> 0, step: 1
7390 11:38:40.715508
7391 11:38:40.718148 RX Delay 0 -> 252, step: 8
7392 11:38:40.721762 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7393 11:38:40.725557 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7394 11:38:40.731485 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7395 11:38:40.734900 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7396 11:38:40.738295 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7397 11:38:40.742392 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7398 11:38:40.744813 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7399 11:38:40.748806 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7400 11:38:40.755064 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7401 11:38:40.758370 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7402 11:38:40.761635 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7403 11:38:40.765149 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7404 11:38:40.771586 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7405 11:38:40.774443 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7406 11:38:40.778308 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7407 11:38:40.781641 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7408 11:38:40.782117 ==
7409 11:38:40.784979 Dram Type= 6, Freq= 0, CH_0, rank 0
7410 11:38:40.791337 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7411 11:38:40.791840 ==
7412 11:38:40.792174 DQS Delay:
7413 11:38:40.792480 DQS0 = 0, DQS1 = 0
7414 11:38:40.794866 DQM Delay:
7415 11:38:40.795341 DQM0 = 130, DQM1 = 124
7416 11:38:40.798357 DQ Delay:
7417 11:38:40.801365 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7418 11:38:40.804564 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7419 11:38:40.808298 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7420 11:38:40.811210 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7421 11:38:40.811724
7422 11:38:40.812060
7423 11:38:40.812364 ==
7424 11:38:40.815446 Dram Type= 6, Freq= 0, CH_0, rank 0
7425 11:38:40.818521 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7426 11:38:40.821095 ==
7427 11:38:40.821583
7428 11:38:40.821913
7429 11:38:40.822216 TX Vref Scan disable
7430 11:38:40.824668 == TX Byte 0 ==
7431 11:38:40.827942 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7432 11:38:40.830889 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7433 11:38:40.834671 == TX Byte 1 ==
7434 11:38:40.837596 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7435 11:38:40.841510 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7436 11:38:40.844511 ==
7437 11:38:40.847901 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 11:38:40.851301 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 11:38:40.851818 ==
7440 11:38:40.862907
7441 11:38:40.866021 TX Vref early break, caculate TX vref
7442 11:38:40.869505 TX Vref=16, minBit 8, minWin=22, winSum=376
7443 11:38:40.873274 TX Vref=18, minBit 4, minWin=23, winSum=385
7444 11:38:40.875781 TX Vref=20, minBit 4, minWin=24, winSum=397
7445 11:38:40.879126 TX Vref=22, minBit 4, minWin=24, winSum=406
7446 11:38:40.882862 TX Vref=24, minBit 0, minWin=25, winSum=414
7447 11:38:40.889360 TX Vref=26, minBit 7, minWin=25, winSum=420
7448 11:38:40.892470 TX Vref=28, minBit 0, minWin=25, winSum=420
7449 11:38:40.896094 TX Vref=30, minBit 0, minWin=25, winSum=417
7450 11:38:40.899075 TX Vref=32, minBit 6, minWin=24, winSum=407
7451 11:38:40.902396 TX Vref=34, minBit 3, minWin=24, winSum=398
7452 11:38:40.909457 [TxChooseVref] Worse bit 7, Min win 25, Win sum 420, Final Vref 26
7453 11:38:40.910021
7454 11:38:40.912222 Final TX Range 0 Vref 26
7455 11:38:40.912640
7456 11:38:40.912965 ==
7457 11:38:40.916417 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 11:38:40.918971 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7459 11:38:40.919688 ==
7460 11:38:40.920039
7461 11:38:40.920341
7462 11:38:40.922253 TX Vref Scan disable
7463 11:38:40.930127 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7464 11:38:40.930630 == TX Byte 0 ==
7465 11:38:40.932683 u2DelayCellOfst[0]=18 cells (5 PI)
7466 11:38:40.936241 u2DelayCellOfst[1]=22 cells (6 PI)
7467 11:38:40.939644 u2DelayCellOfst[2]=18 cells (5 PI)
7468 11:38:40.942059 u2DelayCellOfst[3]=14 cells (4 PI)
7469 11:38:40.945348 u2DelayCellOfst[4]=11 cells (3 PI)
7470 11:38:40.949779 u2DelayCellOfst[5]=0 cells (0 PI)
7471 11:38:40.952691 u2DelayCellOfst[6]=18 cells (5 PI)
7472 11:38:40.955767 u2DelayCellOfst[7]=18 cells (5 PI)
7473 11:38:40.959399 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7474 11:38:40.962162 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7475 11:38:40.965662 == TX Byte 1 ==
7476 11:38:40.966092 u2DelayCellOfst[8]=3 cells (1 PI)
7477 11:38:40.969304 u2DelayCellOfst[9]=0 cells (0 PI)
7478 11:38:40.972376 u2DelayCellOfst[10]=11 cells (3 PI)
7479 11:38:40.975966 u2DelayCellOfst[11]=3 cells (1 PI)
7480 11:38:40.979261 u2DelayCellOfst[12]=14 cells (4 PI)
7481 11:38:40.982125 u2DelayCellOfst[13]=14 cells (4 PI)
7482 11:38:40.985532 u2DelayCellOfst[14]=18 cells (5 PI)
7483 11:38:40.988602 u2DelayCellOfst[15]=14 cells (4 PI)
7484 11:38:40.992257 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7485 11:38:40.998494 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7486 11:38:40.999023 DramC Write-DBI on
7487 11:38:40.999554 ==
7488 11:38:41.001672 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 11:38:41.008113 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7490 11:38:41.008685 ==
7491 11:38:41.009021
7492 11:38:41.009382
7493 11:38:41.009678 TX Vref Scan disable
7494 11:38:41.012304 == TX Byte 0 ==
7495 11:38:41.016076 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7496 11:38:41.018932 == TX Byte 1 ==
7497 11:38:41.022049 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7498 11:38:41.025636 DramC Write-DBI off
7499 11:38:41.026296
7500 11:38:41.026860 [DATLAT]
7501 11:38:41.027203 Freq=1600, CH0 RK0
7502 11:38:41.027791
7503 11:38:41.028677 DATLAT Default: 0xf
7504 11:38:41.029021 0, 0xFFFF, sum = 0
7505 11:38:41.032267 1, 0xFFFF, sum = 0
7506 11:38:41.035151 2, 0xFFFF, sum = 0
7507 11:38:41.035584 3, 0xFFFF, sum = 0
7508 11:38:41.038654 4, 0xFFFF, sum = 0
7509 11:38:41.039085 5, 0xFFFF, sum = 0
7510 11:38:41.041820 6, 0xFFFF, sum = 0
7511 11:38:41.042251 7, 0xFFFF, sum = 0
7512 11:38:41.044804 8, 0xFFFF, sum = 0
7513 11:38:41.045277 9, 0xFFFF, sum = 0
7514 11:38:41.048252 10, 0xFFFF, sum = 0
7515 11:38:41.048822 11, 0xFFFF, sum = 0
7516 11:38:41.051889 12, 0xBFF, sum = 0
7517 11:38:41.052497 13, 0x0, sum = 1
7518 11:38:41.056082 14, 0x0, sum = 2
7519 11:38:41.056513 15, 0x0, sum = 3
7520 11:38:41.058424 16, 0x0, sum = 4
7521 11:38:41.058925 best_step = 14
7522 11:38:41.059256
7523 11:38:41.059557 ==
7524 11:38:41.061484 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 11:38:41.065558 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7526 11:38:41.068363 ==
7527 11:38:41.068873 RX Vref Scan: 1
7528 11:38:41.069204
7529 11:38:41.071467 Set Vref Range= 24 -> 127
7530 11:38:41.072265
7531 11:38:41.075312 RX Vref 24 -> 127, step: 1
7532 11:38:41.075809
7533 11:38:41.076255 RX Delay 11 -> 252, step: 4
7534 11:38:41.076572
7535 11:38:41.078164 Set Vref, RX VrefLevel [Byte0]: 24
7536 11:38:41.081096 [Byte1]: 24
7537 11:38:41.085434
7538 11:38:41.085854 Set Vref, RX VrefLevel [Byte0]: 25
7539 11:38:41.088757 [Byte1]: 25
7540 11:38:41.093052
7541 11:38:41.093679 Set Vref, RX VrefLevel [Byte0]: 26
7542 11:38:41.095917 [Byte1]: 26
7543 11:38:41.100492
7544 11:38:41.100910 Set Vref, RX VrefLevel [Byte0]: 27
7545 11:38:41.103722 [Byte1]: 27
7546 11:38:41.108304
7547 11:38:41.108822 Set Vref, RX VrefLevel [Byte0]: 28
7548 11:38:41.111420 [Byte1]: 28
7549 11:38:41.116689
7550 11:38:41.117181 Set Vref, RX VrefLevel [Byte0]: 29
7551 11:38:41.118973 [Byte1]: 29
7552 11:38:41.123176
7553 11:38:41.123596 Set Vref, RX VrefLevel [Byte0]: 30
7554 11:38:41.126606 [Byte1]: 30
7555 11:38:41.131479
7556 11:38:41.131901 Set Vref, RX VrefLevel [Byte0]: 31
7557 11:38:41.134027 [Byte1]: 31
7558 11:38:41.139295
7559 11:38:41.139790 Set Vref, RX VrefLevel [Byte0]: 32
7560 11:38:41.142712 [Byte1]: 32
7561 11:38:41.146161
7562 11:38:41.146585 Set Vref, RX VrefLevel [Byte0]: 33
7563 11:38:41.149922 [Byte1]: 33
7564 11:38:41.153792
7565 11:38:41.154235 Set Vref, RX VrefLevel [Byte0]: 34
7566 11:38:41.157535 [Byte1]: 34
7567 11:38:41.161812
7568 11:38:41.162234 Set Vref, RX VrefLevel [Byte0]: 35
7569 11:38:41.164670 [Byte1]: 35
7570 11:38:41.169040
7571 11:38:41.169492 Set Vref, RX VrefLevel [Byte0]: 36
7572 11:38:41.172705 [Byte1]: 36
7573 11:38:41.176882
7574 11:38:41.177336 Set Vref, RX VrefLevel [Byte0]: 37
7575 11:38:41.179921 [Byte1]: 37
7576 11:38:41.183782
7577 11:38:41.184073 Set Vref, RX VrefLevel [Byte0]: 38
7578 11:38:41.186902 [Byte1]: 38
7579 11:38:41.191967
7580 11:38:41.192040 Set Vref, RX VrefLevel [Byte0]: 39
7581 11:38:41.194286 [Byte1]: 39
7582 11:38:41.198623
7583 11:38:41.198697 Set Vref, RX VrefLevel [Byte0]: 40
7584 11:38:41.201882 [Byte1]: 40
7585 11:38:41.206310
7586 11:38:41.206384 Set Vref, RX VrefLevel [Byte0]: 41
7587 11:38:41.209600 [Byte1]: 41
7588 11:38:41.214307
7589 11:38:41.214382 Set Vref, RX VrefLevel [Byte0]: 42
7590 11:38:41.217636 [Byte1]: 42
7591 11:38:41.222058
7592 11:38:41.222132 Set Vref, RX VrefLevel [Byte0]: 43
7593 11:38:41.225223 [Byte1]: 43
7594 11:38:41.229513
7595 11:38:41.229587 Set Vref, RX VrefLevel [Byte0]: 44
7596 11:38:41.233254 [Byte1]: 44
7597 11:38:41.237308
7598 11:38:41.237692 Set Vref, RX VrefLevel [Byte0]: 45
7599 11:38:41.240519 [Byte1]: 45
7600 11:38:41.245034
7601 11:38:41.245451 Set Vref, RX VrefLevel [Byte0]: 46
7602 11:38:41.248669 [Byte1]: 46
7603 11:38:41.252913
7604 11:38:41.253557 Set Vref, RX VrefLevel [Byte0]: 47
7605 11:38:41.255755 [Byte1]: 47
7606 11:38:41.260430
7607 11:38:41.260879 Set Vref, RX VrefLevel [Byte0]: 48
7608 11:38:41.263875 [Byte1]: 48
7609 11:38:41.268016
7610 11:38:41.268506 Set Vref, RX VrefLevel [Byte0]: 49
7611 11:38:41.271502 [Byte1]: 49
7612 11:38:41.275884
7613 11:38:41.276304 Set Vref, RX VrefLevel [Byte0]: 50
7614 11:38:41.279031 [Byte1]: 50
7615 11:38:41.283440
7616 11:38:41.283932 Set Vref, RX VrefLevel [Byte0]: 51
7617 11:38:41.286421 [Byte1]: 51
7618 11:38:41.291543
7619 11:38:41.292040 Set Vref, RX VrefLevel [Byte0]: 52
7620 11:38:41.294026 [Byte1]: 52
7621 11:38:41.298479
7622 11:38:41.298899 Set Vref, RX VrefLevel [Byte0]: 53
7623 11:38:41.301833 [Byte1]: 53
7624 11:38:41.306417
7625 11:38:41.306838 Set Vref, RX VrefLevel [Byte0]: 54
7626 11:38:41.309022 [Byte1]: 54
7627 11:38:41.313474
7628 11:38:41.313969 Set Vref, RX VrefLevel [Byte0]: 55
7629 11:38:41.316958 [Byte1]: 55
7630 11:38:41.321607
7631 11:38:41.322123 Set Vref, RX VrefLevel [Byte0]: 56
7632 11:38:41.324809 [Byte1]: 56
7633 11:38:41.329191
7634 11:38:41.329744 Set Vref, RX VrefLevel [Byte0]: 57
7635 11:38:41.331882 [Byte1]: 57
7636 11:38:41.336072
7637 11:38:41.336544 Set Vref, RX VrefLevel [Byte0]: 58
7638 11:38:41.340263 [Byte1]: 58
7639 11:38:41.344524
7640 11:38:41.345031 Set Vref, RX VrefLevel [Byte0]: 59
7641 11:38:41.347257 [Byte1]: 59
7642 11:38:41.352246
7643 11:38:41.352742 Set Vref, RX VrefLevel [Byte0]: 60
7644 11:38:41.355184 [Byte1]: 60
7645 11:38:41.360436
7646 11:38:41.360930 Set Vref, RX VrefLevel [Byte0]: 61
7647 11:38:41.362606 [Byte1]: 61
7648 11:38:41.367101
7649 11:38:41.367636 Set Vref, RX VrefLevel [Byte0]: 62
7650 11:38:41.370263 [Byte1]: 62
7651 11:38:41.374494
7652 11:38:41.374989 Set Vref, RX VrefLevel [Byte0]: 63
7653 11:38:41.377731 [Byte1]: 63
7654 11:38:41.382549
7655 11:38:41.383043 Set Vref, RX VrefLevel [Byte0]: 64
7656 11:38:41.385836 [Byte1]: 64
7657 11:38:41.390149
7658 11:38:41.390646 Set Vref, RX VrefLevel [Byte0]: 65
7659 11:38:41.393360 [Byte1]: 65
7660 11:38:41.397441
7661 11:38:41.397937 Set Vref, RX VrefLevel [Byte0]: 66
7662 11:38:41.401166 [Byte1]: 66
7663 11:38:41.405455
7664 11:38:41.405955 Set Vref, RX VrefLevel [Byte0]: 67
7665 11:38:41.408867 [Byte1]: 67
7666 11:38:41.412754
7667 11:38:41.413290 Set Vref, RX VrefLevel [Byte0]: 68
7668 11:38:41.416332 [Byte1]: 68
7669 11:38:41.420301
7670 11:38:41.420797 Set Vref, RX VrefLevel [Byte0]: 69
7671 11:38:41.423752 [Byte1]: 69
7672 11:38:41.427601
7673 11:38:41.428021 Set Vref, RX VrefLevel [Byte0]: 70
7674 11:38:41.431171 [Byte1]: 70
7675 11:38:41.435950
7676 11:38:41.436448 Set Vref, RX VrefLevel [Byte0]: 71
7677 11:38:41.439284 [Byte1]: 71
7678 11:38:41.443219
7679 11:38:41.443714 Final RX Vref Byte 0 = 54 to rank0
7680 11:38:41.446829 Final RX Vref Byte 1 = 54 to rank0
7681 11:38:41.450540 Final RX Vref Byte 0 = 54 to rank1
7682 11:38:41.453909 Final RX Vref Byte 1 = 54 to rank1==
7683 11:38:41.456187 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 11:38:41.462983 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7685 11:38:41.463516 ==
7686 11:38:41.463853 DQS Delay:
7687 11:38:41.466347 DQS0 = 0, DQS1 = 0
7688 11:38:41.466845 DQM Delay:
7689 11:38:41.467180 DQM0 = 126, DQM1 = 121
7690 11:38:41.470858 DQ Delay:
7691 11:38:41.472936 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7692 11:38:41.475762 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7693 11:38:41.480389 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7694 11:38:41.483602 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =134
7695 11:38:41.484098
7696 11:38:41.484462
7697 11:38:41.484774
7698 11:38:41.485940 [DramC_TX_OE_Calibration] TA2
7699 11:38:41.489377 Original DQ_B0 (3 6) =30, OEN = 27
7700 11:38:41.492710 Original DQ_B1 (3 6) =30, OEN = 27
7701 11:38:41.496104 24, 0x0, End_B0=24 End_B1=24
7702 11:38:41.496733 25, 0x0, End_B0=25 End_B1=25
7703 11:38:41.499111 26, 0x0, End_B0=26 End_B1=26
7704 11:38:41.503484 27, 0x0, End_B0=27 End_B1=27
7705 11:38:41.506145 28, 0x0, End_B0=28 End_B1=28
7706 11:38:41.509450 29, 0x0, End_B0=29 End_B1=29
7707 11:38:41.509952 30, 0x0, End_B0=30 End_B1=30
7708 11:38:41.512505 31, 0x4141, End_B0=30 End_B1=30
7709 11:38:41.516112 Byte0 end_step=30 best_step=27
7710 11:38:41.519370 Byte1 end_step=30 best_step=27
7711 11:38:41.522154 Byte0 TX OE(2T, 0.5T) = (3, 3)
7712 11:38:41.526765 Byte1 TX OE(2T, 0.5T) = (3, 3)
7713 11:38:41.527259
7714 11:38:41.527592
7715 11:38:41.532229 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7716 11:38:41.535414 CH0 RK0: MR19=303, MR18=1A1A
7717 11:38:41.542289 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7718 11:38:41.542800
7719 11:38:41.545508 ----->DramcWriteLeveling(PI) begin...
7720 11:38:41.546011 ==
7721 11:38:41.549152 Dram Type= 6, Freq= 0, CH_0, rank 1
7722 11:38:41.552449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7723 11:38:41.552974 ==
7724 11:38:41.555261 Write leveling (Byte 0): 30 => 30
7725 11:38:41.558598 Write leveling (Byte 1): 27 => 27
7726 11:38:41.562653 DramcWriteLeveling(PI) end<-----
7727 11:38:41.563276
7728 11:38:41.563737 ==
7729 11:38:41.565503 Dram Type= 6, Freq= 0, CH_0, rank 1
7730 11:38:41.568700 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7731 11:38:41.569129 ==
7732 11:38:41.572413 [Gating] SW mode calibration
7733 11:38:41.578393 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7734 11:38:41.585270 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7735 11:38:41.588371 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7736 11:38:41.595169 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7737 11:38:41.599085 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7738 11:38:41.601547 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7739 11:38:41.608280 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7740 11:38:41.611379 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7741 11:38:41.614778 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7742 11:38:41.622213 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7743 11:38:41.624827 0 13 0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
7744 11:38:41.628507 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7745 11:38:41.634603 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7746 11:38:41.637828 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7747 11:38:41.641630 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7748 11:38:41.648045 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7749 11:38:41.651446 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7750 11:38:41.654873 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7751 11:38:41.661827 0 14 0 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
7752 11:38:41.664111 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7753 11:38:41.668061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 11:38:41.674510 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7755 11:38:41.677138 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7756 11:38:41.680858 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7757 11:38:41.687585 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 11:38:41.691056 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7759 11:38:41.694216 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7760 11:38:41.700731 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7761 11:38:41.704509 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7762 11:38:41.707315 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 11:38:41.714247 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 11:38:41.717215 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 11:38:41.720610 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 11:38:41.727166 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 11:38:41.730450 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 11:38:41.733892 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 11:38:41.741189 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 11:38:41.744230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 11:38:41.747009 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 11:38:41.754111 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 11:38:41.756663 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 11:38:41.760261 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7775 11:38:41.767225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7776 11:38:41.770311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7777 11:38:41.773067 Total UI for P1: 0, mck2ui 16
7778 11:38:41.776926 best dqsien dly found for B0: ( 1, 0, 30)
7779 11:38:41.780265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7780 11:38:41.784108 Total UI for P1: 0, mck2ui 16
7781 11:38:41.787707 best dqsien dly found for B1: ( 1, 1, 2)
7782 11:38:41.790051 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7783 11:38:41.793321 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7784 11:38:41.793823
7785 11:38:41.797209 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7786 11:38:41.802835 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7787 11:38:41.803541 [Gating] SW calibration Done
7788 11:38:41.803903 ==
7789 11:38:41.806665 Dram Type= 6, Freq= 0, CH_0, rank 1
7790 11:38:41.813381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7791 11:38:41.813888 ==
7792 11:38:41.814223 RX Vref Scan: 0
7793 11:38:41.814529
7794 11:38:41.815946 RX Vref 0 -> 0, step: 1
7795 11:38:41.816366
7796 11:38:41.819663 RX Delay 0 -> 252, step: 8
7797 11:38:41.823008 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7798 11:38:41.826226 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7799 11:38:41.829864 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7800 11:38:41.837582 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7801 11:38:41.839505 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7802 11:38:41.842830 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7803 11:38:41.846293 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7804 11:38:41.849525 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7805 11:38:41.856258 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7806 11:38:41.859378 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7807 11:38:41.862941 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7808 11:38:41.865975 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7809 11:38:41.869636 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7810 11:38:41.877021 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7811 11:38:41.879443 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7812 11:38:41.883178 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7813 11:38:41.883605 ==
7814 11:38:41.885589 Dram Type= 6, Freq= 0, CH_0, rank 1
7815 11:38:41.889092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7816 11:38:41.892313 ==
7817 11:38:41.892736 DQS Delay:
7818 11:38:41.893063 DQS0 = 0, DQS1 = 0
7819 11:38:41.896496 DQM Delay:
7820 11:38:41.897013 DQM0 = 130, DQM1 = 124
7821 11:38:41.898994 DQ Delay:
7822 11:38:41.901890 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7823 11:38:41.906110 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7824 11:38:41.909453 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7825 11:38:41.911954 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7826 11:38:41.912381
7827 11:38:41.912710
7828 11:38:41.913014 ==
7829 11:38:41.915432 Dram Type= 6, Freq= 0, CH_0, rank 1
7830 11:38:41.918719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7831 11:38:41.919165 ==
7832 11:38:41.919499
7833 11:38:41.921996
7834 11:38:41.922500 TX Vref Scan disable
7835 11:38:41.925923 == TX Byte 0 ==
7836 11:38:41.929207 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7837 11:38:41.931871 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7838 11:38:41.935549 == TX Byte 1 ==
7839 11:38:41.938351 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7840 11:38:41.942000 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7841 11:38:41.942511 ==
7842 11:38:41.945145 Dram Type= 6, Freq= 0, CH_0, rank 1
7843 11:38:41.952074 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7844 11:38:41.952589 ==
7845 11:38:41.965660
7846 11:38:41.968353 TX Vref early break, caculate TX vref
7847 11:38:41.971170 TX Vref=16, minBit 11, minWin=22, winSum=373
7848 11:38:41.975048 TX Vref=18, minBit 8, minWin=22, winSum=378
7849 11:38:41.977923 TX Vref=20, minBit 8, minWin=22, winSum=390
7850 11:38:41.981279 TX Vref=22, minBit 1, minWin=24, winSum=397
7851 11:38:41.984662 TX Vref=24, minBit 8, minWin=23, winSum=400
7852 11:38:41.991078 TX Vref=26, minBit 6, minWin=24, winSum=405
7853 11:38:41.994818 TX Vref=28, minBit 8, minWin=24, winSum=415
7854 11:38:41.997803 TX Vref=30, minBit 1, minWin=24, winSum=411
7855 11:38:42.000830 TX Vref=32, minBit 1, minWin=24, winSum=406
7856 11:38:42.004222 TX Vref=34, minBit 1, minWin=24, winSum=397
7857 11:38:42.007776 TX Vref=36, minBit 7, minWin=23, winSum=391
7858 11:38:42.014195 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 28
7859 11:38:42.014697
7860 11:38:42.017376 Final TX Range 0 Vref 28
7861 11:38:42.017797
7862 11:38:42.018119 ==
7863 11:38:42.021355 Dram Type= 6, Freq= 0, CH_0, rank 1
7864 11:38:42.024595 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7865 11:38:42.025096 ==
7866 11:38:42.025633
7867 11:38:42.028243
7868 11:38:42.028739 TX Vref Scan disable
7869 11:38:42.034575 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7870 11:38:42.035074 == TX Byte 0 ==
7871 11:38:42.037485 u2DelayCellOfst[0]=11 cells (3 PI)
7872 11:38:42.041038 u2DelayCellOfst[1]=14 cells (4 PI)
7873 11:38:42.044408 u2DelayCellOfst[2]=7 cells (2 PI)
7874 11:38:42.047791 u2DelayCellOfst[3]=11 cells (3 PI)
7875 11:38:42.050752 u2DelayCellOfst[4]=7 cells (2 PI)
7876 11:38:42.054566 u2DelayCellOfst[5]=0 cells (0 PI)
7877 11:38:42.057673 u2DelayCellOfst[6]=18 cells (5 PI)
7878 11:38:42.060913 u2DelayCellOfst[7]=14 cells (4 PI)
7879 11:38:42.064593 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7880 11:38:42.067669 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7881 11:38:42.070504 == TX Byte 1 ==
7882 11:38:42.074785 u2DelayCellOfst[8]=3 cells (1 PI)
7883 11:38:42.077329 u2DelayCellOfst[9]=0 cells (0 PI)
7884 11:38:42.080439 u2DelayCellOfst[10]=14 cells (4 PI)
7885 11:38:42.083871 u2DelayCellOfst[11]=11 cells (3 PI)
7886 11:38:42.084297 u2DelayCellOfst[12]=18 cells (5 PI)
7887 11:38:42.088502 u2DelayCellOfst[13]=18 cells (5 PI)
7888 11:38:42.091089 u2DelayCellOfst[14]=22 cells (6 PI)
7889 11:38:42.094123 u2DelayCellOfst[15]=18 cells (5 PI)
7890 11:38:42.100568 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7891 11:38:42.103621 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7892 11:38:42.104048 DramC Write-DBI on
7893 11:38:42.107243 ==
7894 11:38:42.107671 Dram Type= 6, Freq= 0, CH_0, rank 1
7895 11:38:42.113597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7896 11:38:42.114044 ==
7897 11:38:42.114386
7898 11:38:42.114695
7899 11:38:42.117087 TX Vref Scan disable
7900 11:38:42.117646 == TX Byte 0 ==
7901 11:38:42.123874 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7902 11:38:42.124369 == TX Byte 1 ==
7903 11:38:42.126676 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7904 11:38:42.130286 DramC Write-DBI off
7905 11:38:42.130784
7906 11:38:42.131122 [DATLAT]
7907 11:38:42.133785 Freq=1600, CH0 RK1
7908 11:38:42.134296
7909 11:38:42.134727 DATLAT Default: 0xe
7910 11:38:42.136570 0, 0xFFFF, sum = 0
7911 11:38:42.137005 1, 0xFFFF, sum = 0
7912 11:38:42.140179 2, 0xFFFF, sum = 0
7913 11:38:42.140609 3, 0xFFFF, sum = 0
7914 11:38:42.143527 4, 0xFFFF, sum = 0
7915 11:38:42.144040 5, 0xFFFF, sum = 0
7916 11:38:42.146350 6, 0xFFFF, sum = 0
7917 11:38:42.149986 7, 0xFFFF, sum = 0
7918 11:38:42.150501 8, 0xFFFF, sum = 0
7919 11:38:42.153602 9, 0xFFFF, sum = 0
7920 11:38:42.154117 10, 0xFFFF, sum = 0
7921 11:38:42.156402 11, 0xFFFF, sum = 0
7922 11:38:42.156833 12, 0x8FFF, sum = 0
7923 11:38:42.159591 13, 0x0, sum = 1
7924 11:38:42.160023 14, 0x0, sum = 2
7925 11:38:42.163580 15, 0x0, sum = 3
7926 11:38:42.164013 16, 0x0, sum = 4
7927 11:38:42.164348 best_step = 14
7928 11:38:42.167405
7929 11:38:42.167908 ==
7930 11:38:42.170079 Dram Type= 6, Freq= 0, CH_0, rank 1
7931 11:38:42.173154 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7932 11:38:42.173616 ==
7933 11:38:42.173953 RX Vref Scan: 0
7934 11:38:42.174260
7935 11:38:42.176398 RX Vref 0 -> 0, step: 1
7936 11:38:42.176824
7937 11:38:42.180146 RX Delay 11 -> 252, step: 4
7938 11:38:42.182868 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7939 11:38:42.189564 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7940 11:38:42.193302 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7941 11:38:42.196551 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7942 11:38:42.199276 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7943 11:38:42.202544 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7944 11:38:42.209144 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7945 11:38:42.212806 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7946 11:38:42.216255 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7947 11:38:42.219598 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7948 11:38:42.222683 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7949 11:38:42.229293 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7950 11:38:42.232825 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7951 11:38:42.236274 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7952 11:38:42.239269 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7953 11:38:42.245642 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7954 11:38:42.246157 ==
7955 11:38:42.248709 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 11:38:42.252419 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7957 11:38:42.252930 ==
7958 11:38:42.253302 DQS Delay:
7959 11:38:42.255546 DQS0 = 0, DQS1 = 0
7960 11:38:42.255969 DQM Delay:
7961 11:38:42.258826 DQM0 = 129, DQM1 = 120
7962 11:38:42.259392 DQ Delay:
7963 11:38:42.261953 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7964 11:38:42.265602 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7965 11:38:42.269497 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7966 11:38:42.272192 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
7967 11:38:42.272698
7968 11:38:42.273029
7969 11:38:42.273376
7970 11:38:42.275750 [DramC_TX_OE_Calibration] TA2
7971 11:38:42.279155 Original DQ_B0 (3 6) =30, OEN = 27
7972 11:38:42.282776 Original DQ_B1 (3 6) =30, OEN = 27
7973 11:38:42.285677 24, 0x0, End_B0=24 End_B1=24
7974 11:38:42.289127 25, 0x0, End_B0=25 End_B1=25
7975 11:38:42.292783 26, 0x0, End_B0=26 End_B1=26
7976 11:38:42.293333 27, 0x0, End_B0=27 End_B1=27
7977 11:38:42.295386 28, 0x0, End_B0=28 End_B1=28
7978 11:38:42.299522 29, 0x0, End_B0=29 End_B1=29
7979 11:38:42.301734 30, 0x0, End_B0=30 End_B1=30
7980 11:38:42.305176 31, 0x4141, End_B0=30 End_B1=30
7981 11:38:42.305704 Byte0 end_step=30 best_step=27
7982 11:38:42.308611 Byte1 end_step=30 best_step=27
7983 11:38:42.311762 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 11:38:42.316768 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 11:38:42.317187
7986 11:38:42.317757
7987 11:38:42.321331 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7988 11:38:42.324741 CH0 RK1: MR19=303, MR18=2020
7989 11:38:42.331950 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
7990 11:38:42.335448 [RxdqsGatingPostProcess] freq 1600
7991 11:38:42.341362 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7992 11:38:42.344925 Pre-setting of DQS Precalculation
7993 11:38:42.348357 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7994 11:38:42.348864 ==
7995 11:38:42.351561 Dram Type= 6, Freq= 0, CH_1, rank 0
7996 11:38:42.354922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7997 11:38:42.358465 ==
7998 11:38:42.361487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7999 11:38:42.365267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8000 11:38:42.371499 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8001 11:38:42.374975 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8002 11:38:42.384226 [CA 0] Center 42 (12~72) winsize 61
8003 11:38:42.387958 [CA 1] Center 41 (10~72) winsize 63
8004 11:38:42.390865 [CA 2] Center 37 (8~67) winsize 60
8005 11:38:42.394701 [CA 3] Center 36 (7~66) winsize 60
8006 11:38:42.397630 [CA 4] Center 34 (4~64) winsize 61
8007 11:38:42.401385 [CA 5] Center 34 (4~64) winsize 61
8008 11:38:42.401885
8009 11:38:42.403743 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8010 11:38:42.404240
8011 11:38:42.407628 [CATrainingPosCal] consider 1 rank data
8012 11:38:42.410312 u2DelayCellTimex100 = 266/100 ps
8013 11:38:42.414141 CA0 delay=42 (12~72),Diff = 8 PI (29 cell)
8014 11:38:42.420321 CA1 delay=41 (10~72),Diff = 7 PI (25 cell)
8015 11:38:42.424048 CA2 delay=37 (8~67),Diff = 3 PI (11 cell)
8016 11:38:42.427429 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8017 11:38:42.430203 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8018 11:38:42.433436 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8019 11:38:42.433860
8020 11:38:42.437145 CA PerBit enable=1, Macro0, CA PI delay=34
8021 11:38:42.437605
8022 11:38:42.440304 [CBTSetCACLKResult] CA Dly = 34
8023 11:38:42.443660 CS Dly: 8 (0~39)
8024 11:38:42.447267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8025 11:38:42.451814 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8026 11:38:42.452236 ==
8027 11:38:42.454017 Dram Type= 6, Freq= 0, CH_1, rank 1
8028 11:38:42.457533 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8029 11:38:42.460005 ==
8030 11:38:42.463676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8031 11:38:42.466865 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8032 11:38:42.474423 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8033 11:38:42.480886 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8034 11:38:42.486802 [CA 0] Center 40 (10~70) winsize 61
8035 11:38:42.489648 [CA 1] Center 39 (9~70) winsize 62
8036 11:38:42.493851 [CA 2] Center 35 (6~65) winsize 60
8037 11:38:42.496548 [CA 3] Center 35 (5~65) winsize 61
8038 11:38:42.499788 [CA 4] Center 32 (3~62) winsize 60
8039 11:38:42.503184 [CA 5] Center 33 (3~63) winsize 61
8040 11:38:42.503682
8041 11:38:42.506597 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8042 11:38:42.507033
8043 11:38:42.509622 [CATrainingPosCal] consider 2 rank data
8044 11:38:42.513160 u2DelayCellTimex100 = 266/100 ps
8045 11:38:42.516533 CA0 delay=41 (12~70),Diff = 8 PI (29 cell)
8046 11:38:42.523447 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8047 11:38:42.526228 CA2 delay=36 (8~65),Diff = 3 PI (11 cell)
8048 11:38:42.530231 CA3 delay=36 (7~65),Diff = 3 PI (11 cell)
8049 11:38:42.532949 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8050 11:38:42.535963 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8051 11:38:42.536385
8052 11:38:42.539244 CA PerBit enable=1, Macro0, CA PI delay=33
8053 11:38:42.539668
8054 11:38:42.543302 [CBTSetCACLKResult] CA Dly = 33
8055 11:38:42.547037 CS Dly: 9 (0~41)
8056 11:38:42.549750 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8057 11:38:42.553380 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8058 11:38:42.553879
8059 11:38:42.556366 ----->DramcWriteLeveling(PI) begin...
8060 11:38:42.556880 ==
8061 11:38:42.559288 Dram Type= 6, Freq= 0, CH_1, rank 0
8062 11:38:42.566312 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8063 11:38:42.566820 ==
8064 11:38:42.569872 Write leveling (Byte 0): 21 => 21
8065 11:38:42.570378 Write leveling (Byte 1): 19 => 19
8066 11:38:42.573284 DramcWriteLeveling(PI) end<-----
8067 11:38:42.573708
8068 11:38:42.574038 ==
8069 11:38:42.576352 Dram Type= 6, Freq= 0, CH_1, rank 0
8070 11:38:42.582879 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8071 11:38:42.583383 ==
8072 11:38:42.585704 [Gating] SW mode calibration
8073 11:38:42.592598 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8074 11:38:42.595726 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8075 11:38:42.602561 0 12 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
8076 11:38:42.606103 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 11:38:42.608834 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 11:38:42.616155 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 11:38:42.618981 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 11:38:42.622922 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 11:38:42.628756 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 11:38:42.633463 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8083 11:38:42.635832 0 13 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
8084 11:38:42.641692 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8085 11:38:42.645540 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 11:38:42.648565 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 11:38:42.655974 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 11:38:42.658278 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 11:38:42.661969 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 11:38:42.668198 0 13 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8091 11:38:42.672715 0 14 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8092 11:38:42.675761 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 11:38:42.681611 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 11:38:42.685175 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 11:38:42.688360 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 11:38:42.694601 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 11:38:42.698117 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:38:42.702126 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 11:38:42.707768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 11:38:42.711218 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 11:38:42.714815 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:38:42.721296 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:38:42.724427 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:38:42.727571 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:38:42.734431 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:38:42.738565 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:38:42.740993 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:38:42.747652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:38:42.751792 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:38:42.753882 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:38:42.761088 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:38:42.764274 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:38:42.767427 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:38:42.774763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8115 11:38:42.777614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 11:38:42.780855 Total UI for P1: 0, mck2ui 16
8117 11:38:42.784154 best dqsien dly found for B0: ( 1, 0, 28)
8118 11:38:42.788144 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 11:38:42.790357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 11:38:42.795069 Total UI for P1: 0, mck2ui 16
8121 11:38:42.797960 best dqsien dly found for B1: ( 1, 1, 0)
8122 11:38:42.800796 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8123 11:38:42.806990 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8124 11:38:42.807476
8125 11:38:42.810696 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8126 11:38:42.813679 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8127 11:38:42.817095 [Gating] SW calibration Done
8128 11:38:42.817554 ==
8129 11:38:42.820449 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 11:38:42.824084 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 11:38:42.824588 ==
8132 11:38:42.824917 RX Vref Scan: 0
8133 11:38:42.827172
8134 11:38:42.827591 RX Vref 0 -> 0, step: 1
8135 11:38:42.827915
8136 11:38:42.830384 RX Delay 0 -> 252, step: 8
8137 11:38:42.834274 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8138 11:38:42.836672 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8139 11:38:42.844306 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8140 11:38:42.847168 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8141 11:38:42.849828 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8142 11:38:42.853644 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8143 11:38:42.856723 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8144 11:38:42.863280 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8145 11:38:42.867712 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8146 11:38:42.870133 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8147 11:38:42.873217 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8148 11:38:42.880083 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8149 11:38:42.883479 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8150 11:38:42.886402 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8151 11:38:42.890257 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8152 11:38:42.893567 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8153 11:38:42.896688 ==
8154 11:38:42.897187 Dram Type= 6, Freq= 0, CH_1, rank 0
8155 11:38:42.902997 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8156 11:38:42.903422 ==
8157 11:38:42.903757 DQS Delay:
8158 11:38:42.906180 DQS0 = 0, DQS1 = 0
8159 11:38:42.906700 DQM Delay:
8160 11:38:42.909720 DQM0 = 130, DQM1 = 126
8161 11:38:42.910182 DQ Delay:
8162 11:38:42.913672 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8163 11:38:42.916344 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8164 11:38:42.919360 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =115
8165 11:38:42.923024 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8166 11:38:42.923531
8167 11:38:42.923865
8168 11:38:42.924173 ==
8169 11:38:42.925915 Dram Type= 6, Freq= 0, CH_1, rank 0
8170 11:38:42.932713 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8171 11:38:42.933160 ==
8172 11:38:42.933542
8173 11:38:42.933851
8174 11:38:42.935674 TX Vref Scan disable
8175 11:38:42.936099 == TX Byte 0 ==
8176 11:38:42.939136 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8177 11:38:42.946202 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8178 11:38:42.946711 == TX Byte 1 ==
8179 11:38:42.949139 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8180 11:38:42.955958 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8181 11:38:42.956468 ==
8182 11:38:42.959395 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 11:38:42.962647 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 11:38:42.963158 ==
8185 11:38:42.975263
8186 11:38:42.978613 TX Vref early break, caculate TX vref
8187 11:38:42.981853 TX Vref=16, minBit 3, minWin=21, winSum=373
8188 11:38:42.985333 TX Vref=18, minBit 3, minWin=22, winSum=382
8189 11:38:42.989743 TX Vref=20, minBit 3, minWin=22, winSum=393
8190 11:38:42.991742 TX Vref=22, minBit 3, minWin=23, winSum=402
8191 11:38:42.995004 TX Vref=24, minBit 0, minWin=24, winSum=403
8192 11:38:43.001133 TX Vref=26, minBit 3, minWin=24, winSum=418
8193 11:38:43.004835 TX Vref=28, minBit 3, minWin=24, winSum=415
8194 11:38:43.008006 TX Vref=30, minBit 3, minWin=23, winSum=411
8195 11:38:43.011259 TX Vref=32, minBit 1, minWin=24, winSum=401
8196 11:38:43.014853 TX Vref=34, minBit 3, minWin=23, winSum=392
8197 11:38:43.021873 [TxChooseVref] Worse bit 3, Min win 24, Win sum 418, Final Vref 26
8198 11:38:43.022387
8199 11:38:43.024558 Final TX Range 0 Vref 26
8200 11:38:43.024978
8201 11:38:43.025350 ==
8202 11:38:43.028130 Dram Type= 6, Freq= 0, CH_1, rank 0
8203 11:38:43.031489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8204 11:38:43.031921 ==
8205 11:38:43.032242
8206 11:38:43.032539
8207 11:38:43.034883 TX Vref Scan disable
8208 11:38:43.041135 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8209 11:38:43.041666 == TX Byte 0 ==
8210 11:38:43.044174 u2DelayCellOfst[0]=18 cells (5 PI)
8211 11:38:43.048108 u2DelayCellOfst[1]=11 cells (3 PI)
8212 11:38:43.050938 u2DelayCellOfst[2]=0 cells (0 PI)
8213 11:38:43.054312 u2DelayCellOfst[3]=7 cells (2 PI)
8214 11:38:43.058178 u2DelayCellOfst[4]=7 cells (2 PI)
8215 11:38:43.060926 u2DelayCellOfst[5]=18 cells (5 PI)
8216 11:38:43.064543 u2DelayCellOfst[6]=18 cells (5 PI)
8217 11:38:43.065041 u2DelayCellOfst[7]=7 cells (2 PI)
8218 11:38:43.071007 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8219 11:38:43.074384 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8220 11:38:43.074809 == TX Byte 1 ==
8221 11:38:43.077586 u2DelayCellOfst[8]=0 cells (0 PI)
8222 11:38:43.080576 u2DelayCellOfst[9]=3 cells (1 PI)
8223 11:38:43.084388 u2DelayCellOfst[10]=11 cells (3 PI)
8224 11:38:43.087843 u2DelayCellOfst[11]=3 cells (1 PI)
8225 11:38:43.091266 u2DelayCellOfst[12]=14 cells (4 PI)
8226 11:38:43.094447 u2DelayCellOfst[13]=14 cells (4 PI)
8227 11:38:43.097364 u2DelayCellOfst[14]=18 cells (5 PI)
8228 11:38:43.100876 u2DelayCellOfst[15]=14 cells (4 PI)
8229 11:38:43.104274 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8230 11:38:43.111394 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8231 11:38:43.111821 DramC Write-DBI on
8232 11:38:43.112146 ==
8233 11:38:43.114648 Dram Type= 6, Freq= 0, CH_1, rank 0
8234 11:38:43.117189 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8235 11:38:43.120910 ==
8236 11:38:43.121452
8237 11:38:43.121781
8238 11:38:43.122083 TX Vref Scan disable
8239 11:38:43.125621 == TX Byte 0 ==
8240 11:38:43.128199 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8241 11:38:43.130299 == TX Byte 1 ==
8242 11:38:43.134602 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8243 11:38:43.137668 DramC Write-DBI off
8244 11:38:43.138172
8245 11:38:43.138496 [DATLAT]
8246 11:38:43.138801 Freq=1600, CH1 RK0
8247 11:38:43.139094
8248 11:38:43.140721 DATLAT Default: 0xf
8249 11:38:43.141136 0, 0xFFFF, sum = 0
8250 11:38:43.144206 1, 0xFFFF, sum = 0
8251 11:38:43.144632 2, 0xFFFF, sum = 0
8252 11:38:43.147183 3, 0xFFFF, sum = 0
8253 11:38:43.150819 4, 0xFFFF, sum = 0
8254 11:38:43.151327 5, 0xFFFF, sum = 0
8255 11:38:43.153771 6, 0xFFFF, sum = 0
8256 11:38:43.154242 7, 0xFFFF, sum = 0
8257 11:38:43.157267 8, 0xFFFF, sum = 0
8258 11:38:43.157785 9, 0xFFFF, sum = 0
8259 11:38:43.160513 10, 0xFFFF, sum = 0
8260 11:38:43.160942 11, 0xFFFF, sum = 0
8261 11:38:43.163928 12, 0xF7F, sum = 0
8262 11:38:43.164633 13, 0x0, sum = 1
8263 11:38:43.167143 14, 0x0, sum = 2
8264 11:38:43.167589 15, 0x0, sum = 3
8265 11:38:43.170495 16, 0x0, sum = 4
8266 11:38:43.171009 best_step = 14
8267 11:38:43.171339
8268 11:38:43.171637 ==
8269 11:38:43.174205 Dram Type= 6, Freq= 0, CH_1, rank 0
8270 11:38:43.177210 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8271 11:38:43.177764 ==
8272 11:38:43.181450 RX Vref Scan: 1
8273 11:38:43.181952
8274 11:38:43.183646 Set Vref Range= 24 -> 127
8275 11:38:43.184143
8276 11:38:43.184474 RX Vref 24 -> 127, step: 1
8277 11:38:43.184779
8278 11:38:43.187900 RX Delay 3 -> 252, step: 4
8279 11:38:43.188401
8280 11:38:43.190707 Set Vref, RX VrefLevel [Byte0]: 24
8281 11:38:43.194215 [Byte1]: 24
8282 11:38:43.197320
8283 11:38:43.197820 Set Vref, RX VrefLevel [Byte0]: 25
8284 11:38:43.200447 [Byte1]: 25
8285 11:38:43.205059
8286 11:38:43.205609 Set Vref, RX VrefLevel [Byte0]: 26
8287 11:38:43.207986 [Byte1]: 26
8288 11:38:43.212340
8289 11:38:43.212836 Set Vref, RX VrefLevel [Byte0]: 27
8290 11:38:43.215414 [Byte1]: 27
8291 11:38:43.220342
8292 11:38:43.220842 Set Vref, RX VrefLevel [Byte0]: 28
8293 11:38:43.223482 [Byte1]: 28
8294 11:38:43.228602
8295 11:38:43.229097 Set Vref, RX VrefLevel [Byte0]: 29
8296 11:38:43.231679 [Byte1]: 29
8297 11:38:43.235939
8298 11:38:43.236437 Set Vref, RX VrefLevel [Byte0]: 30
8299 11:38:43.239424 [Byte1]: 30
8300 11:38:43.243493
8301 11:38:43.243995 Set Vref, RX VrefLevel [Byte0]: 31
8302 11:38:43.247152 [Byte1]: 31
8303 11:38:43.250678
8304 11:38:43.251116 Set Vref, RX VrefLevel [Byte0]: 32
8305 11:38:43.254414 [Byte1]: 32
8306 11:38:43.258912
8307 11:38:43.259326 Set Vref, RX VrefLevel [Byte0]: 33
8308 11:38:43.261539 [Byte1]: 33
8309 11:38:43.265904
8310 11:38:43.266353 Set Vref, RX VrefLevel [Byte0]: 34
8311 11:38:43.269036 [Byte1]: 34
8312 11:38:43.273727
8313 11:38:43.274145 Set Vref, RX VrefLevel [Byte0]: 35
8314 11:38:43.277413 [Byte1]: 35
8315 11:38:43.281342
8316 11:38:43.281708 Set Vref, RX VrefLevel [Byte0]: 36
8317 11:38:43.284689 [Byte1]: 36
8318 11:38:43.288640
8319 11:38:43.289017 Set Vref, RX VrefLevel [Byte0]: 37
8320 11:38:43.292151 [Byte1]: 37
8321 11:38:43.296573
8322 11:38:43.296942 Set Vref, RX VrefLevel [Byte0]: 38
8323 11:38:43.300378 [Byte1]: 38
8324 11:38:43.304989
8325 11:38:43.305402 Set Vref, RX VrefLevel [Byte0]: 39
8326 11:38:43.308036 [Byte1]: 39
8327 11:38:43.311485
8328 11:38:43.312098 Set Vref, RX VrefLevel [Byte0]: 40
8329 11:38:43.315403 [Byte1]: 40
8330 11:38:43.319387
8331 11:38:43.319799 Set Vref, RX VrefLevel [Byte0]: 41
8332 11:38:43.322835 [Byte1]: 41
8333 11:38:43.326985
8334 11:38:43.327401 Set Vref, RX VrefLevel [Byte0]: 42
8335 11:38:43.331339 [Byte1]: 42
8336 11:38:43.335175
8337 11:38:43.335694 Set Vref, RX VrefLevel [Byte0]: 43
8338 11:38:43.338577 [Byte1]: 43
8339 11:38:43.344361
8340 11:38:43.344857 Set Vref, RX VrefLevel [Byte0]: 44
8341 11:38:43.346713 [Byte1]: 44
8342 11:38:43.349832
8343 11:38:43.350249 Set Vref, RX VrefLevel [Byte0]: 45
8344 11:38:43.353631 [Byte1]: 45
8345 11:38:43.357922
8346 11:38:43.358528 Set Vref, RX VrefLevel [Byte0]: 46
8347 11:38:43.361518 [Byte1]: 46
8348 11:38:43.366025
8349 11:38:43.366523 Set Vref, RX VrefLevel [Byte0]: 47
8350 11:38:43.369126 [Byte1]: 47
8351 11:38:43.373165
8352 11:38:43.373710 Set Vref, RX VrefLevel [Byte0]: 48
8353 11:38:43.376353 [Byte1]: 48
8354 11:38:43.380828
8355 11:38:43.381350 Set Vref, RX VrefLevel [Byte0]: 49
8356 11:38:43.384635 [Byte1]: 49
8357 11:38:43.388750
8358 11:38:43.389297 Set Vref, RX VrefLevel [Byte0]: 50
8359 11:38:43.391807 [Byte1]: 50
8360 11:38:43.396278
8361 11:38:43.396776 Set Vref, RX VrefLevel [Byte0]: 51
8362 11:38:43.399958 [Byte1]: 51
8363 11:38:43.403983
8364 11:38:43.404480 Set Vref, RX VrefLevel [Byte0]: 52
8365 11:38:43.407335 [Byte1]: 52
8366 11:38:43.411335
8367 11:38:43.411882 Set Vref, RX VrefLevel [Byte0]: 53
8368 11:38:43.414728 [Byte1]: 53
8369 11:38:43.419254
8370 11:38:43.419666 Set Vref, RX VrefLevel [Byte0]: 54
8371 11:38:43.422505 [Byte1]: 54
8372 11:38:43.426806
8373 11:38:43.427299 Set Vref, RX VrefLevel [Byte0]: 55
8374 11:38:43.429902 [Byte1]: 55
8375 11:38:43.434307
8376 11:38:43.434884 Set Vref, RX VrefLevel [Byte0]: 56
8377 11:38:43.437553 [Byte1]: 56
8378 11:38:43.442256
8379 11:38:43.442743 Set Vref, RX VrefLevel [Byte0]: 57
8380 11:38:43.445058 [Byte1]: 57
8381 11:38:43.449579
8382 11:38:43.450079 Set Vref, RX VrefLevel [Byte0]: 58
8383 11:38:43.454426 [Byte1]: 58
8384 11:38:43.458719
8385 11:38:43.459231 Set Vref, RX VrefLevel [Byte0]: 59
8386 11:38:43.461720 [Byte1]: 59
8387 11:38:43.464889
8388 11:38:43.465327 Set Vref, RX VrefLevel [Byte0]: 60
8389 11:38:43.468133 [Byte1]: 60
8390 11:38:43.473837
8391 11:38:43.474335 Set Vref, RX VrefLevel [Byte0]: 61
8392 11:38:43.476259 [Byte1]: 61
8393 11:38:43.480813
8394 11:38:43.481375 Set Vref, RX VrefLevel [Byte0]: 62
8395 11:38:43.484356 [Byte1]: 62
8396 11:38:43.488245
8397 11:38:43.488744 Set Vref, RX VrefLevel [Byte0]: 63
8398 11:38:43.491373 [Byte1]: 63
8399 11:38:43.496243
8400 11:38:43.496727 Set Vref, RX VrefLevel [Byte0]: 64
8401 11:38:43.499486 [Byte1]: 64
8402 11:38:43.503515
8403 11:38:43.504088 Set Vref, RX VrefLevel [Byte0]: 65
8404 11:38:43.506304 [Byte1]: 65
8405 11:38:43.510823
8406 11:38:43.511257 Set Vref, RX VrefLevel [Byte0]: 66
8407 11:38:43.513828 [Byte1]: 66
8408 11:38:43.518285
8409 11:38:43.518705 Set Vref, RX VrefLevel [Byte0]: 67
8410 11:38:43.521963 [Byte1]: 67
8411 11:38:43.525797
8412 11:38:43.526218 Set Vref, RX VrefLevel [Byte0]: 68
8413 11:38:43.529911 [Byte1]: 68
8414 11:38:43.534146
8415 11:38:43.534634 Set Vref, RX VrefLevel [Byte0]: 69
8416 11:38:43.537160 [Byte1]: 69
8417 11:38:43.541048
8418 11:38:43.541565 Set Vref, RX VrefLevel [Byte0]: 70
8419 11:38:43.545436 [Byte1]: 70
8420 11:38:43.548844
8421 11:38:43.549305 Set Vref, RX VrefLevel [Byte0]: 71
8422 11:38:43.553563 [Byte1]: 71
8423 11:38:43.556547
8424 11:38:43.557093 Set Vref, RX VrefLevel [Byte0]: 72
8425 11:38:43.560097 [Byte1]: 72
8426 11:38:43.564506
8427 11:38:43.564923 Set Vref, RX VrefLevel [Byte0]: 73
8428 11:38:43.568573 [Byte1]: 73
8429 11:38:43.572567
8430 11:38:43.573080 Set Vref, RX VrefLevel [Byte0]: 74
8431 11:38:43.576345 [Byte1]: 74
8432 11:38:43.579816
8433 11:38:43.580232 Set Vref, RX VrefLevel [Byte0]: 75
8434 11:38:43.583476 [Byte1]: 75
8435 11:38:43.588226
8436 11:38:43.588719 Final RX Vref Byte 0 = 61 to rank0
8437 11:38:43.590921 Final RX Vref Byte 1 = 53 to rank0
8438 11:38:43.594566 Final RX Vref Byte 0 = 61 to rank1
8439 11:38:43.597532 Final RX Vref Byte 1 = 53 to rank1==
8440 11:38:43.601041 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:38:43.607443 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8442 11:38:43.607951 ==
8443 11:38:43.608283 DQS Delay:
8444 11:38:43.610068 DQS0 = 0, DQS1 = 0
8445 11:38:43.610484 DQM Delay:
8446 11:38:43.610813 DQM0 = 128, DQM1 = 124
8447 11:38:43.613486 DQ Delay:
8448 11:38:43.617845 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8449 11:38:43.621303 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8450 11:38:43.623543 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8451 11:38:43.627332 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8452 11:38:43.627830
8453 11:38:43.628155
8454 11:38:43.628449
8455 11:38:43.630381 [DramC_TX_OE_Calibration] TA2
8456 11:38:43.633620 Original DQ_B0 (3 6) =30, OEN = 27
8457 11:38:43.636782 Original DQ_B1 (3 6) =30, OEN = 27
8458 11:38:43.641160 24, 0x0, End_B0=24 End_B1=24
8459 11:38:43.643275 25, 0x0, End_B0=25 End_B1=25
8460 11:38:43.643702 26, 0x0, End_B0=26 End_B1=26
8461 11:38:43.647175 27, 0x0, End_B0=27 End_B1=27
8462 11:38:43.650335 28, 0x0, End_B0=28 End_B1=28
8463 11:38:43.653574 29, 0x0, End_B0=29 End_B1=29
8464 11:38:43.654078 30, 0x0, End_B0=30 End_B1=30
8465 11:38:43.656578 31, 0x4141, End_B0=30 End_B1=30
8466 11:38:43.659963 Byte0 end_step=30 best_step=27
8467 11:38:43.663424 Byte1 end_step=30 best_step=27
8468 11:38:43.666659 Byte0 TX OE(2T, 0.5T) = (3, 3)
8469 11:38:43.669902 Byte1 TX OE(2T, 0.5T) = (3, 3)
8470 11:38:43.670395
8471 11:38:43.670731
8472 11:38:43.676727 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8473 11:38:43.680499 CH1 RK0: MR19=303, MR18=2626
8474 11:38:43.686868 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8475 11:38:43.687367
8476 11:38:43.690704 ----->DramcWriteLeveling(PI) begin...
8477 11:38:43.691223 ==
8478 11:38:43.694261 Dram Type= 6, Freq= 0, CH_1, rank 1
8479 11:38:43.696857 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8480 11:38:43.697327 ==
8481 11:38:43.700052 Write leveling (Byte 0): 20 => 20
8482 11:38:43.703802 Write leveling (Byte 1): 19 => 19
8483 11:38:43.706399 DramcWriteLeveling(PI) end<-----
8484 11:38:43.706822
8485 11:38:43.707151 ==
8486 11:38:43.709916 Dram Type= 6, Freq= 0, CH_1, rank 1
8487 11:38:43.713209 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8488 11:38:43.713691 ==
8489 11:38:43.716837 [Gating] SW mode calibration
8490 11:38:43.723184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8491 11:38:43.729692 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8492 11:38:43.733172 0 12 0 | B1->B0 | 2f2f 3534 | 1 1 | (1 1) (1 1)
8493 11:38:43.739306 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 11:38:43.743158 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 11:38:43.746674 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8496 11:38:43.752614 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8497 11:38:43.756212 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8498 11:38:43.759580 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8499 11:38:43.766443 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8500 11:38:43.769341 0 13 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8501 11:38:43.773311 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 11:38:43.778954 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8503 11:38:43.782851 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8504 11:38:43.785914 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8505 11:38:43.792791 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8506 11:38:43.796313 0 13 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8507 11:38:43.798853 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8508 11:38:43.805773 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8509 11:38:43.809206 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 11:38:43.813540 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 11:38:43.816810 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 11:38:43.823146 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8513 11:38:43.825742 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8514 11:38:43.830513 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8515 11:38:43.835671 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8516 11:38:43.838767 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8517 11:38:43.842770 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8518 11:38:43.848964 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 11:38:43.852735 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 11:38:43.855332 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 11:38:43.862056 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 11:38:43.865754 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 11:38:43.868713 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 11:38:43.875793 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 11:38:43.878906 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 11:38:43.882871 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 11:38:43.888742 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 11:38:43.892272 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 11:38:43.895841 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8530 11:38:43.901614 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8531 11:38:43.904939 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8532 11:38:43.908459 Total UI for P1: 0, mck2ui 16
8533 11:38:43.912162 best dqsien dly found for B0: ( 1, 0, 22)
8534 11:38:43.915003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8535 11:38:43.921718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8536 11:38:43.922202 Total UI for P1: 0, mck2ui 16
8537 11:38:43.928205 best dqsien dly found for B1: ( 1, 0, 30)
8538 11:38:43.931527 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8539 11:38:43.934872 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8540 11:38:43.935370
8541 11:38:43.940719 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8542 11:38:43.943867 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8543 11:38:43.944915 [Gating] SW calibration Done
8544 11:38:43.945403 ==
8545 11:38:43.948773 Dram Type= 6, Freq= 0, CH_1, rank 1
8546 11:38:43.952396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8547 11:38:43.953007 ==
8548 11:38:43.955432 RX Vref Scan: 0
8549 11:38:43.955910
8550 11:38:43.956231 RX Vref 0 -> 0, step: 1
8551 11:38:43.956529
8552 11:38:43.958565 RX Delay 0 -> 252, step: 8
8553 11:38:43.961648 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8554 11:38:43.968617 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8555 11:38:43.971516 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8556 11:38:43.975260 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8557 11:38:43.978414 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8558 11:38:43.981316 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8559 11:38:43.989262 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8560 11:38:43.991948 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8561 11:38:43.994842 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8562 11:38:43.997829 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8563 11:38:44.001291 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8564 11:38:44.007936 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8565 11:38:44.011324 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8566 11:38:44.014886 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8567 11:38:44.017826 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8568 11:38:44.024982 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8569 11:38:44.025523 ==
8570 11:38:44.028352 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 11:38:44.031776 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 11:38:44.032275 ==
8573 11:38:44.032605 DQS Delay:
8574 11:38:44.034387 DQS0 = 0, DQS1 = 0
8575 11:38:44.034883 DQM Delay:
8576 11:38:44.037541 DQM0 = 131, DQM1 = 124
8577 11:38:44.038032 DQ Delay:
8578 11:38:44.040919 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8579 11:38:44.044108 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8580 11:38:44.047647 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8581 11:38:44.050969 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8582 11:38:44.051401
8583 11:38:44.051733
8584 11:38:44.054337 ==
8585 11:38:44.058183 Dram Type= 6, Freq= 0, CH_1, rank 1
8586 11:38:44.060670 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8587 11:38:44.061164 ==
8588 11:38:44.061560
8589 11:38:44.061868
8590 11:38:44.063965 TX Vref Scan disable
8591 11:38:44.064458 == TX Byte 0 ==
8592 11:38:44.067744 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8593 11:38:44.074731 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8594 11:38:44.075376 == TX Byte 1 ==
8595 11:38:44.077309 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8596 11:38:44.084285 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8597 11:38:44.084780 ==
8598 11:38:44.087179 Dram Type= 6, Freq= 0, CH_1, rank 1
8599 11:38:44.090522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8600 11:38:44.091019 ==
8601 11:38:44.104719
8602 11:38:44.107668 TX Vref early break, caculate TX vref
8603 11:38:44.110898 TX Vref=16, minBit 7, minWin=22, winSum=387
8604 11:38:44.114574 TX Vref=18, minBit 1, minWin=23, winSum=393
8605 11:38:44.117353 TX Vref=20, minBit 8, minWin=23, winSum=402
8606 11:38:44.121310 TX Vref=22, minBit 2, minWin=24, winSum=405
8607 11:38:44.124109 TX Vref=24, minBit 1, minWin=25, winSum=416
8608 11:38:44.130619 TX Vref=26, minBit 7, minWin=25, winSum=421
8609 11:38:44.133911 TX Vref=28, minBit 0, minWin=26, winSum=425
8610 11:38:44.137321 TX Vref=30, minBit 0, minWin=25, winSum=421
8611 11:38:44.141054 TX Vref=32, minBit 0, minWin=24, winSum=419
8612 11:38:44.144010 TX Vref=34, minBit 0, minWin=24, winSum=411
8613 11:38:44.147513 TX Vref=36, minBit 0, minWin=23, winSum=398
8614 11:38:44.153879 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8615 11:38:44.154395
8616 11:38:44.157442 Final TX Range 0 Vref 28
8617 11:38:44.157934
8618 11:38:44.158262 ==
8619 11:38:44.160453 Dram Type= 6, Freq= 0, CH_1, rank 1
8620 11:38:44.163963 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8621 11:38:44.164465 ==
8622 11:38:44.164790
8623 11:38:44.167808
8624 11:38:44.168222 TX Vref Scan disable
8625 11:38:44.173878 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8626 11:38:44.174375 == TX Byte 0 ==
8627 11:38:44.177291 u2DelayCellOfst[0]=14 cells (4 PI)
8628 11:38:44.180379 u2DelayCellOfst[1]=11 cells (3 PI)
8629 11:38:44.183665 u2DelayCellOfst[2]=0 cells (0 PI)
8630 11:38:44.186897 u2DelayCellOfst[3]=7 cells (2 PI)
8631 11:38:44.190776 u2DelayCellOfst[4]=7 cells (2 PI)
8632 11:38:44.194276 u2DelayCellOfst[5]=14 cells (4 PI)
8633 11:38:44.198247 u2DelayCellOfst[6]=14 cells (4 PI)
8634 11:38:44.200568 u2DelayCellOfst[7]=7 cells (2 PI)
8635 11:38:44.203851 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8636 11:38:44.206539 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8637 11:38:44.209997 == TX Byte 1 ==
8638 11:38:44.213760 u2DelayCellOfst[8]=0 cells (0 PI)
8639 11:38:44.216562 u2DelayCellOfst[9]=7 cells (2 PI)
8640 11:38:44.216985 u2DelayCellOfst[10]=11 cells (3 PI)
8641 11:38:44.220378 u2DelayCellOfst[11]=7 cells (2 PI)
8642 11:38:44.223439 u2DelayCellOfst[12]=14 cells (4 PI)
8643 11:38:44.227731 u2DelayCellOfst[13]=18 cells (5 PI)
8644 11:38:44.230180 u2DelayCellOfst[14]=18 cells (5 PI)
8645 11:38:44.233943 u2DelayCellOfst[15]=18 cells (5 PI)
8646 11:38:44.240491 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8647 11:38:44.242951 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8648 11:38:44.243419 DramC Write-DBI on
8649 11:38:44.243752 ==
8650 11:38:44.246665 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 11:38:44.253804 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 11:38:44.254300 ==
8653 11:38:44.254636
8654 11:38:44.254936
8655 11:38:44.255226 TX Vref Scan disable
8656 11:38:44.258150 == TX Byte 0 ==
8657 11:38:44.260422 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8658 11:38:44.263842 == TX Byte 1 ==
8659 11:38:44.267121 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8660 11:38:44.270134 DramC Write-DBI off
8661 11:38:44.270557
8662 11:38:44.270886 [DATLAT]
8663 11:38:44.271187 Freq=1600, CH1 RK1
8664 11:38:44.271486
8665 11:38:44.274384 DATLAT Default: 0xe
8666 11:38:44.277880 0, 0xFFFF, sum = 0
8667 11:38:44.278381 1, 0xFFFF, sum = 0
8668 11:38:44.280897 2, 0xFFFF, sum = 0
8669 11:38:44.281441 3, 0xFFFF, sum = 0
8670 11:38:44.283637 4, 0xFFFF, sum = 0
8671 11:38:44.284137 5, 0xFFFF, sum = 0
8672 11:38:44.287205 6, 0xFFFF, sum = 0
8673 11:38:44.287640 7, 0xFFFF, sum = 0
8674 11:38:44.290094 8, 0xFFFF, sum = 0
8675 11:38:44.290598 9, 0xFFFF, sum = 0
8676 11:38:44.293745 10, 0xFFFF, sum = 0
8677 11:38:44.294249 11, 0xFFFF, sum = 0
8678 11:38:44.297673 12, 0xF5F, sum = 0
8679 11:38:44.298179 13, 0x0, sum = 1
8680 11:38:44.300424 14, 0x0, sum = 2
8681 11:38:44.300925 15, 0x0, sum = 3
8682 11:38:44.303297 16, 0x0, sum = 4
8683 11:38:44.303727 best_step = 14
8684 11:38:44.304051
8685 11:38:44.304351 ==
8686 11:38:44.306617 Dram Type= 6, Freq= 0, CH_1, rank 1
8687 11:38:44.314462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8688 11:38:44.314959 ==
8689 11:38:44.315292 RX Vref Scan: 0
8690 11:38:44.315705
8691 11:38:44.316498 RX Vref 0 -> 0, step: 1
8692 11:38:44.316831
8693 11:38:44.320065 RX Delay 3 -> 252, step: 4
8694 11:38:44.322989 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8695 11:38:44.326518 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8696 11:38:44.332761 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8697 11:38:44.336004 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8698 11:38:44.339380 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8699 11:38:44.343234 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8700 11:38:44.346074 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8701 11:38:44.350095 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8702 11:38:44.355779 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8703 11:38:44.359828 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8704 11:38:44.363162 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8705 11:38:44.365943 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8706 11:38:44.373261 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8707 11:38:44.376126 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8708 11:38:44.379156 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8709 11:38:44.382322 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8710 11:38:44.382736 ==
8711 11:38:44.385728 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 11:38:44.392774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8713 11:38:44.393318 ==
8714 11:38:44.393651 DQS Delay:
8715 11:38:44.393950 DQS0 = 0, DQS1 = 0
8716 11:38:44.396847 DQM Delay:
8717 11:38:44.397291 DQM0 = 127, DQM1 = 122
8718 11:38:44.398637 DQ Delay:
8719 11:38:44.402338 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8720 11:38:44.405523 DQ4 =126, DQ5 =140, DQ6 =136, DQ7 =126
8721 11:38:44.409264 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =112
8722 11:38:44.412085 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8723 11:38:44.412577
8724 11:38:44.412900
8725 11:38:44.413195
8726 11:38:44.415074 [DramC_TX_OE_Calibration] TA2
8727 11:38:44.418684 Original DQ_B0 (3 6) =30, OEN = 27
8728 11:38:44.422003 Original DQ_B1 (3 6) =30, OEN = 27
8729 11:38:44.426119 24, 0x0, End_B0=24 End_B1=24
8730 11:38:44.426628 25, 0x0, End_B0=25 End_B1=25
8731 11:38:44.428378 26, 0x0, End_B0=26 End_B1=26
8732 11:38:44.431770 27, 0x0, End_B0=27 End_B1=27
8733 11:38:44.436641 28, 0x0, End_B0=28 End_B1=28
8734 11:38:44.439817 29, 0x0, End_B0=29 End_B1=29
8735 11:38:44.440314 30, 0x0, End_B0=30 End_B1=30
8736 11:38:44.441433 31, 0x4141, End_B0=30 End_B1=30
8737 11:38:44.445092 Byte0 end_step=30 best_step=27
8738 11:38:44.448969 Byte1 end_step=30 best_step=27
8739 11:38:44.452368 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 11:38:44.455272 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 11:38:44.455690
8742 11:38:44.456011
8743 11:38:44.461695 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8744 11:38:44.464926 CH1 RK1: MR19=303, MR18=1E1E
8745 11:38:44.471570 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8746 11:38:44.475530 [RxdqsGatingPostProcess] freq 1600
8747 11:38:44.477907 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8748 11:38:44.481959 Pre-setting of DQS Precalculation
8749 11:38:44.488070 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8750 11:38:44.495015 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8751 11:38:44.501592 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8752 11:38:44.502099
8753 11:38:44.502428
8754 11:38:44.504716 [Calibration Summary] 3200 Mbps
8755 11:38:44.508813 CH 0, Rank 0
8756 11:38:44.509370 SW Impedance : PASS
8757 11:38:44.511306 DUTY Scan : NO K
8758 11:38:44.511797 ZQ Calibration : PASS
8759 11:38:44.515301 Jitter Meter : NO K
8760 11:38:44.518045 CBT Training : PASS
8761 11:38:44.518467 Write leveling : PASS
8762 11:38:44.522021 RX DQS gating : PASS
8763 11:38:44.524934 RX DQ/DQS(RDDQC) : PASS
8764 11:38:44.525482 TX DQ/DQS : PASS
8765 11:38:44.528231 RX DATLAT : PASS
8766 11:38:44.531249 RX DQ/DQS(Engine): PASS
8767 11:38:44.531669 TX OE : PASS
8768 11:38:44.535028 All Pass.
8769 11:38:44.535519
8770 11:38:44.535848 CH 0, Rank 1
8771 11:38:44.537863 SW Impedance : PASS
8772 11:38:44.538361 DUTY Scan : NO K
8773 11:38:44.540850 ZQ Calibration : PASS
8774 11:38:44.544353 Jitter Meter : NO K
8775 11:38:44.544774 CBT Training : PASS
8776 11:38:44.547840 Write leveling : PASS
8777 11:38:44.552112 RX DQS gating : PASS
8778 11:38:44.552611 RX DQ/DQS(RDDQC) : PASS
8779 11:38:44.554293 TX DQ/DQS : PASS
8780 11:38:44.559650 RX DATLAT : PASS
8781 11:38:44.560160 RX DQ/DQS(Engine): PASS
8782 11:38:44.560838 TX OE : PASS
8783 11:38:44.561203 All Pass.
8784 11:38:44.561636
8785 11:38:44.564995 CH 1, Rank 0
8786 11:38:44.565547 SW Impedance : PASS
8787 11:38:44.568278 DUTY Scan : NO K
8788 11:38:44.568780 ZQ Calibration : PASS
8789 11:38:44.571217 Jitter Meter : NO K
8790 11:38:44.574518 CBT Training : PASS
8791 11:38:44.574934 Write leveling : PASS
8792 11:38:44.577873 RX DQS gating : PASS
8793 11:38:44.580843 RX DQ/DQS(RDDQC) : PASS
8794 11:38:44.581411 TX DQ/DQS : PASS
8795 11:38:44.584597 RX DATLAT : PASS
8796 11:38:44.587660 RX DQ/DQS(Engine): PASS
8797 11:38:44.588165 TX OE : PASS
8798 11:38:44.590894 All Pass.
8799 11:38:44.591384
8800 11:38:44.591710 CH 1, Rank 1
8801 11:38:44.594835 SW Impedance : PASS
8802 11:38:44.595326 DUTY Scan : NO K
8803 11:38:44.597448 ZQ Calibration : PASS
8804 11:38:44.601300 Jitter Meter : NO K
8805 11:38:44.601802 CBT Training : PASS
8806 11:38:44.604202 Write leveling : PASS
8807 11:38:44.607400 RX DQS gating : PASS
8808 11:38:44.607819 RX DQ/DQS(RDDQC) : PASS
8809 11:38:44.610505 TX DQ/DQS : PASS
8810 11:38:44.613897 RX DATLAT : PASS
8811 11:38:44.614407 RX DQ/DQS(Engine): PASS
8812 11:38:44.617353 TX OE : PASS
8813 11:38:44.617859 All Pass.
8814 11:38:44.618190
8815 11:38:44.620320 DramC Write-DBI on
8816 11:38:44.623991 PER_BANK_REFRESH: Hybrid Mode
8817 11:38:44.624489 TX_TRACKING: ON
8818 11:38:44.633955 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8819 11:38:44.640812 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8820 11:38:44.647473 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8821 11:38:44.651309 [FAST_K] Save calibration result to emmc
8822 11:38:44.653834 sync common calibartion params.
8823 11:38:44.657440 sync cbt_mode0:0, 1:0
8824 11:38:44.661539 dram_init: ddr_geometry: 0
8825 11:38:44.662034 dram_init: ddr_geometry: 0
8826 11:38:44.663851 dram_init: ddr_geometry: 0
8827 11:38:44.667373 0:dram_rank_size:80000000
8828 11:38:44.667817 1:dram_rank_size:80000000
8829 11:38:44.674181 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8830 11:38:44.677795 DFS_SHUFFLE_HW_MODE: ON
8831 11:38:44.680726 dramc_set_vcore_voltage set vcore to 725000
8832 11:38:44.683805 Read voltage for 1600, 0
8833 11:38:44.684300 Vio18 = 0
8834 11:38:44.684630 Vcore = 725000
8835 11:38:44.687850 Vdram = 0
8836 11:38:44.688387 Vddq = 0
8837 11:38:44.688717 Vmddr = 0
8838 11:38:44.689862 switch to 3200 Mbps bootup
8839 11:38:44.690284 [DramcRunTimeConfig]
8840 11:38:44.693189 PHYPLL
8841 11:38:44.693720 DPM_CONTROL_AFTERK: ON
8842 11:38:44.696422 PER_BANK_REFRESH: ON
8843 11:38:44.700190 REFRESH_OVERHEAD_REDUCTION: ON
8844 11:38:44.700613 CMD_PICG_NEW_MODE: OFF
8845 11:38:44.703775 XRTWTW_NEW_MODE: ON
8846 11:38:44.704211 XRTRTR_NEW_MODE: ON
8847 11:38:44.706430 TX_TRACKING: ON
8848 11:38:44.706852 RDSEL_TRACKING: OFF
8849 11:38:44.709609 DQS Precalculation for DVFS: ON
8850 11:38:44.712957 RX_TRACKING: OFF
8851 11:38:44.713409 HW_GATING DBG: ON
8852 11:38:44.716391 ZQCS_ENABLE_LP4: ON
8853 11:38:44.716882 RX_PICG_NEW_MODE: ON
8854 11:38:44.719843 TX_PICG_NEW_MODE: ON
8855 11:38:44.722764 ENABLE_RX_DCM_DPHY: ON
8856 11:38:44.723187 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8857 11:38:44.726106 DUMMY_READ_FOR_TRACKING: OFF
8858 11:38:44.729510 !!! SPM_CONTROL_AFTERK: OFF
8859 11:38:44.732906 !!! SPM could not control APHY
8860 11:38:44.733410 IMPEDANCE_TRACKING: ON
8861 11:38:44.736313 TEMP_SENSOR: ON
8862 11:38:44.736732 HW_SAVE_FOR_SR: OFF
8863 11:38:44.739335 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8864 11:38:44.743137 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8865 11:38:44.746147 Read ODT Tracking: ON
8866 11:38:44.750072 Refresh Rate DeBounce: ON
8867 11:38:44.750454 DFS_NO_QUEUE_FLUSH: ON
8868 11:38:44.752767 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8869 11:38:44.755879 ENABLE_DFS_RUNTIME_MRW: OFF
8870 11:38:44.759855 DDR_RESERVE_NEW_MODE: ON
8871 11:38:44.760362 MR_CBT_SWITCH_FREQ: ON
8872 11:38:44.762396 =========================
8873 11:38:44.781502 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8874 11:38:44.784983 dram_init: ddr_geometry: 0
8875 11:38:44.803305 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8876 11:38:44.806668 dram_init: dram init end (result: 0)
8877 11:38:44.813080 DRAM-K: Full calibration passed in 23456 msecs
8878 11:38:44.817421 MRC: failed to locate region type 0.
8879 11:38:44.817924 DRAM rank0 size:0x80000000,
8880 11:38:44.819830 DRAM rank1 size=0x80000000
8881 11:38:44.830825 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8882 11:38:44.835974 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8883 11:38:44.843070 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8884 11:38:44.849779 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8885 11:38:44.852796 DRAM rank0 size:0x80000000,
8886 11:38:44.855859 DRAM rank1 size=0x80000000
8887 11:38:44.856305 CBMEM:
8888 11:38:44.860171 IMD: root @ 0xfffff000 254 entries.
8889 11:38:44.863254 IMD: root @ 0xffffec00 62 entries.
8890 11:38:44.866295 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8891 11:38:44.869689 WARNING: RO_VPD is uninitialized or empty.
8892 11:38:44.876317 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8893 11:38:44.882702 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8894 11:38:44.896447 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8895 11:38:44.907178 BS: romstage times (exec / console): total (unknown) / 22988 ms
8896 11:38:44.907665
8897 11:38:44.907991
8898 11:38:44.917321 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8899 11:38:44.919840 ARM64: Exception handlers installed.
8900 11:38:44.923301 ARM64: Testing exception
8901 11:38:44.926818 ARM64: Done test exception
8902 11:38:44.927236 Enumerating buses...
8903 11:38:44.930632 Show all devs... Before device enumeration.
8904 11:38:44.933616 Root Device: enabled 1
8905 11:38:44.936863 CPU_CLUSTER: 0: enabled 1
8906 11:38:44.937418 CPU: 00: enabled 1
8907 11:38:44.940418 Compare with tree...
8908 11:38:44.940859 Root Device: enabled 1
8909 11:38:44.943396 CPU_CLUSTER: 0: enabled 1
8910 11:38:44.946787 CPU: 00: enabled 1
8911 11:38:44.947205 Root Device scanning...
8912 11:38:44.950327 scan_static_bus for Root Device
8913 11:38:44.953521 CPU_CLUSTER: 0 enabled
8914 11:38:44.957366 scan_static_bus for Root Device done
8915 11:38:44.959871 scan_bus: bus Root Device finished in 8 msecs
8916 11:38:44.960372 done
8917 11:38:44.966651 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8918 11:38:44.969693 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8919 11:38:44.977062 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8920 11:38:44.979573 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8921 11:38:44.982844 Allocating resources...
8922 11:38:44.986507 Reading resources...
8923 11:38:44.989826 Root Device read_resources bus 0 link: 0
8924 11:38:44.990328 DRAM rank0 size:0x80000000,
8925 11:38:44.993405 DRAM rank1 size=0x80000000
8926 11:38:44.997107 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8927 11:38:44.999830 CPU: 00 missing read_resources
8928 11:38:45.006504 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8929 11:38:45.011454 Root Device read_resources bus 0 link: 0 done
8930 11:38:45.011956 Done reading resources.
8931 11:38:45.016099 Show resources in subtree (Root Device)...After reading.
8932 11:38:45.020137 Root Device child on link 0 CPU_CLUSTER: 0
8933 11:38:45.022699 CPU_CLUSTER: 0 child on link 0 CPU: 00
8934 11:38:45.032908 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8935 11:38:45.033447 CPU: 00
8936 11:38:45.036211 Root Device assign_resources, bus 0 link: 0
8937 11:38:45.040094 CPU_CLUSTER: 0 missing set_resources
8938 11:38:45.042868 Root Device assign_resources, bus 0 link: 0 done
8939 11:38:45.046243 Done setting resources.
8940 11:38:45.052400 Show resources in subtree (Root Device)...After assigning values.
8941 11:38:45.056319 Root Device child on link 0 CPU_CLUSTER: 0
8942 11:38:45.059940 CPU_CLUSTER: 0 child on link 0 CPU: 00
8943 11:38:48.033854 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8944 11:38:48.034021 CPU: 00
8945 11:38:48.034133 Done allocating resources.
8946 11:38:48.034237 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8947 11:38:48.034328 Enabling resources...
8948 11:38:48.034415 done.
8949 11:38:48.034502 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8950 11:38:48.034590 Initializing devices...
8951 11:38:48.034675 Root Device init
8952 11:38:48.034760 init hardware done!
8953 11:38:48.034846 0x00000018: ctrlr->caps
8954 11:38:48.034934 52.000 MHz: ctrlr->f_max
8955 11:38:48.035022 0.400 MHz: ctrlr->f_min
8956 11:38:48.035111 0x40ff8080: ctrlr->voltages
8957 11:38:48.035220 sclk: 390625
8958 11:38:48.035320 Bus Width = 1
8959 11:38:48.035405 sclk: 390625
8960 11:38:48.035490 Bus Width = 1
8961 11:38:48.035574 Early init status = 3
8962 11:38:48.035659 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8963 11:38:48.035746 in-header: 03 fc 00 00 01 00 00 00
8964 11:38:48.035833 in-data: 00
8965 11:38:48.035921 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8966 11:38:48.036008 in-header: 03 fd 00 00 00 00 00 00
8967 11:38:48.036092 in-data:
8968 11:38:48.036176 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8969 11:38:48.036262 in-header: 03 fc 00 00 01 00 00 00
8970 11:38:48.036346 in-data: 00
8971 11:38:48.036430 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8972 11:38:48.036515 in-header: 03 fd 00 00 00 00 00 00
8973 11:38:48.036599 in-data:
8974 11:38:48.036683 [SSUSB] Setting up USB HOST controller...
8975 11:38:48.036767 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8976 11:38:48.036851 [SSUSB] phy power-on done.
8977 11:38:48.036935 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8978 11:38:48.037021 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8979 11:38:48.037106 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8980 11:38:48.037192 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8981 11:38:48.037336 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8982 11:38:48.037423 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8983 11:38:48.037508 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8984 11:38:48.037595 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8985 11:38:48.037680 SPM: binary array size = 0x9dc
8986 11:38:48.037765 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8987 11:38:48.037850 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8988 11:38:48.037934 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8989 11:38:48.038020 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8990 11:38:48.038103 configure_display: Starting display init
8991 11:38:48.038188 anx7625_power_on_init: Init interface.
8992 11:38:48.038272 anx7625_disable_pd_protocol: Disabled PD feature.
8993 11:38:48.038357 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8994 11:38:48.038441 anx7625_start_dp_work: Secure OCM version=00
8995 11:38:48.038523 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8996 11:38:48.038607 sp_tx_get_edid_block: EDID Block = 1
8997 11:38:48.038691 Extracted contents:
8998 11:38:48.038774 header: 00 ff ff ff ff ff ff 00
8999 11:38:48.038860 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9000 11:38:48.038943 version: 01 04
9001 11:38:48.039027 basic params: 95 1f 11 78 0a
9002 11:38:48.039111 chroma info: 76 90 94 55 54 90 27 21 50 54
9003 11:38:48.039195 established: 00 00 00
9004 11:38:48.039278 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9005 11:38:48.039362 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9006 11:38:48.039447 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9007 11:38:48.039530 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9008 11:38:48.039614 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9009 11:38:48.039697 extensions: 00
9010 11:38:48.039780 checksum: fb
9011 11:38:48.039863
9012 11:38:48.039946 Manufacturer: IVO Model 57d Serial Number 0
9013 11:38:48.040031 Made week 0 of 2020
9014 11:38:48.040115 EDID version: 1.4
9015 11:38:48.040236 Digital display
9016 11:38:48.040372 6 bits per primary color channel
9017 11:38:48.040537 DisplayPort interface
9018 11:38:48.040622 Maximum image size: 31 cm x 17 cm
9019 11:38:48.040705 Gamma: 220%
9020 11:38:48.040792 Check DPMS levels
9021 11:38:48.040876 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9022 11:38:48.040961 First detailed timing is preferred timing
9023 11:38:48.041045 Established timings supported:
9024 11:38:48.041129 Standard timings supported:
9025 11:38:48.041212 Detailed timings
9026 11:38:48.041337 Hex of detail: 383680a07038204018303c0035ae10000019
9027 11:38:48.041422 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9028 11:38:48.041506 0780 0798 07c8 0820 hborder 0
9029 11:38:48.041590 0438 043b 0447 0458 vborder 0
9030 11:38:48.041673 -hsync -vsync
9031 11:38:48.041757 Did detailed timing
9032 11:38:48.041840 Hex of detail: 000000000000000000000000000000000000
9033 11:38:48.041925 Manufacturer-specified data, tag 0
9034 11:38:48.042009 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9035 11:38:48.042093 ASCII string: InfoVision
9036 11:38:48.042197 Hex of detail: 000000fe00523134304e574635205248200a
9037 11:38:48.042294 ASCII string: R140NWF5 RH
9038 11:38:48.042377 Checksum
9039 11:38:48.042460 Checksum: 0xfb (valid)
9040 11:38:48.042544 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9041 11:38:48.042629 DSI data_rate: 832800000 bps
9042 11:38:48.042712 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9043 11:38:48.042797 anx7625_parse_edid: pixelclock(138800).
9044 11:38:48.042861 hactive(1920), hsync(48), hfp(24), hbp(88)
9045 11:38:48.042927 vactive(1080), vsync(12), vfp(3), vbp(17)
9046 11:38:48.042993 anx7625_dsi_config: config dsi.
9047 11:38:48.043248 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9048 11:38:48.043337 anx7625_dsi_config: success to config DSI
9049 11:38:48.043404 anx7625_dp_start: MIPI phy setup OK.
9050 11:38:48.043470 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9051 11:38:48.043552 mtk_ddp_mode_set invalid vrefresh 60
9052 11:38:48.043635 main_disp_path_setup
9053 11:38:48.043717 ovl_layer_smi_id_en
9054 11:38:48.043800 ovl_layer_smi_id_en
9055 11:38:48.043882 ccorr_config
9056 11:38:48.043963 aal_config
9057 11:38:48.044044 gamma_config
9058 11:38:48.044126 postmask_config
9059 11:38:48.044261 dither_config
9060 11:38:48.044356 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9061 11:38:48.044438 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9062 11:38:48.044521 Root Device init finished in 554 msecs
9063 11:38:48.044603 CPU_CLUSTER: 0 init
9064 11:38:48.044685 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9065 11:38:48.044768 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9066 11:38:48.044851 APU_MBOX 0x190000b0 = 0x10001
9067 11:38:48.044932 APU_MBOX 0x190001b0 = 0x10001
9068 11:38:48.045014 APU_MBOX 0x190005b0 = 0x10001
9069 11:38:48.045096 APU_MBOX 0x190006b0 = 0x10001
9070 11:38:48.045177 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9071 11:38:48.045319 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9072 11:38:48.045403 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9073 11:38:48.045486 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9074 11:38:48.045569 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9075 11:38:48.045651 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9076 11:38:48.045734 CPU_CLUSTER: 0 init finished in 81 msecs
9077 11:38:48.045816 Devices initialized
9078 11:38:48.045898 Show all devs... After init.
9079 11:38:48.045980 Root Device: enabled 1
9080 11:38:48.046061 CPU_CLUSTER: 0: enabled 1
9081 11:38:48.046143 CPU: 00: enabled 1
9082 11:38:48.046226 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9083 11:38:48.046308 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9084 11:38:48.046391 ELOG: NV offset 0x57f000 size 0x1000
9085 11:38:48.046473 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9086 11:38:48.046556 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9087 11:38:48.046638 ELOG: Event(17) added with size 13 at 2024-07-17 11:38:45 UTC
9088 11:38:48.046720 out: cmd=0x121: 03 db 21 01 00 00 00 00
9089 11:38:48.046803 in-header: 03 59 00 00 2c 00 00 00
9090 11:38:48.046885 in-data: e9 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9091 11:38:48.046970 ELOG: Event(A1) added with size 10 at 2024-07-17 11:38:45 UTC
9092 11:38:48.047053 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9093 11:38:48.047135 ELOG: Event(A0) added with size 9 at 2024-07-17 11:38:45 UTC
9094 11:38:48.047217 elog_add_boot_reason: Logged dev mode boot
9095 11:38:48.047300 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9096 11:38:48.047382 Finalize devices...
9097 11:38:48.047464 Devices finalized
9098 11:38:48.047546 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9099 11:38:48.047628 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9100 11:38:48.047711 in-header: 03 07 00 00 08 00 00 00
9101 11:38:48.047794 in-data: aa e4 47 04 13 02 00 00
9102 11:38:48.047876 Chrome EC: UHEPI supported
9103 11:38:48.047958 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9104 11:38:48.048041 in-header: 03 a9 00 00 08 00 00 00
9105 11:38:48.048123 in-data: 84 60 60 08 00 00 00 00
9106 11:38:48.048252 ELOG: Event(91) added with size 10 at 2024-07-17 11:38:45 UTC
9107 11:38:48.048404 Chrome EC: clear events_b mask to 0x0000000020004000
9108 11:38:48.048486 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9109 11:38:48.048570 in-header: 03 fd 00 00 00 00 00 00
9110 11:38:48.048652 in-data:
9111 11:38:48.048733 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9112 11:38:48.048816 Writing coreboot table at 0xffe64000
9113 11:38:48.048898 0. 000000000010a000-0000000000113fff: RAMSTAGE
9114 11:38:48.048980 1. 0000000040000000-00000000400fffff: RAM
9115 11:38:48.049062 2. 0000000040100000-000000004032afff: RAMSTAGE
9116 11:38:48.049145 3. 000000004032b000-00000000545fffff: RAM
9117 11:38:48.049231 4. 0000000054600000-000000005465ffff: BL31
9118 11:38:48.049354 5. 0000000054660000-00000000ffe63fff: RAM
9119 11:38:48.049436 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9120 11:38:48.049518 7. 0000000100000000-000000013fffffff: RAM
9121 11:38:48.049600 Passing 5 GPIOs to payload:
9122 11:38:48.049682 NAME | PORT | POLARITY | VALUE
9123 11:38:48.049765 EC in RW | 0x000000aa | low | undefined
9124 11:38:48.049847 EC interrupt | 0x00000005 | low | undefined
9125 11:38:48.049929 TPM interrupt | 0x000000ab | high | undefined
9126 11:38:48.050011 SD card detect | 0x00000011 | high | undefined
9127 11:38:48.050093 speaker enable | 0x00000093 | high | undefined
9128 11:38:48.050175 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9129 11:38:48.050258 in-header: 03 f8 00 00 02 00 00 00
9130 11:38:48.050340 in-data: 03 00
9131 11:38:48.050421 ADC[4]: Raw value=668958 ID=5
9132 11:38:48.050503 ADC[3]: Raw value=212549 ID=1
9133 11:38:48.050584 RAM Code: 0x51
9134 11:38:48.050666 ADC[6]: Raw value=74410 ID=0
9135 11:38:48.050747 ADC[5]: Raw value=211444 ID=1
9136 11:38:48.050829 SKU Code: 0x1
9137 11:38:48.050910 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fb79
9138 11:38:48.050993 coreboot table: 964 bytes.
9139 11:38:48.051075 IMD ROOT 0. 0xfffff000 0x00001000
9140 11:38:48.051348 IMD SMALL 1. 0xffffe000 0x00001000
9141 11:38:48.051430 RO MCACHE 2. 0xffffc000 0x00001104
9142 11:38:48.051513 CONSOLE 3. 0xfff7c000 0x00080000
9143 11:38:48.051595 FMAP 4. 0xfff7b000 0x00000452
9144 11:38:48.051678 TIME STAMP 5. 0xfff7a000 0x00000910
9145 11:38:48.051760 VBOOT WORK 6. 0xfff66000 0x00014000
9146 11:38:48.051842 RAMOOPS 7. 0xffe66000 0x00100000
9147 11:38:48.051926 COREBOOT 8. 0xffe64000 0x00002000
9148 11:38:48.052008 IMD small region:
9149 11:38:48.052090 IMD ROOT 0. 0xffffec00 0x00000400
9150 11:38:48.052172 VPD 1. 0xffffeb80 0x0000006c
9151 11:38:48.052254 MMC STATUS 2. 0xffffeb60 0x00000004
9152 11:38:48.052336 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9153 11:38:48.052418 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9154 11:38:48.052501 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9155 11:38:48.052583 Checking segment from ROM address 0x40100000
9156 11:38:48.052694 Checking segment from ROM address 0x4010001c
9157 11:38:48.052776 Loading segment from ROM address 0x40100000
9158 11:38:48.052858 code (compression=0)
9159 11:38:48.052940 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9160 11:38:48.053023 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9161 11:38:48.053106 it's not compressed!
9162 11:38:48.053187 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9163 11:38:48.053329 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9164 11:38:48.053424 Loading segment from ROM address 0x4010001c
9165 11:38:48.053507 Entry Point 0x80000000
9166 11:38:48.053589 Loaded segments
9167 11:38:48.053670 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9168 11:38:48.053753 Jumping to boot code at 0x80000000(0xffe64000)
9169 11:38:48.053836 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9170 11:38:48.053919 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9171 11:38:48.054002 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9172 11:38:48.054085 Checking segment from ROM address 0x40100000
9173 11:38:48.054167 Checking segment from ROM address 0x4010001c
9174 11:38:48.054249 Loading segment from ROM address 0x40100000
9175 11:38:48.054331 code (compression=1)
9176 11:38:48.054413 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9177 11:38:48.054496 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9178 11:38:48.054578 using LZMA
9179 11:38:48.054659 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9180 11:38:48.054742 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9181 11:38:48.054824 Loading segment from ROM address 0x4010001c
9182 11:38:48.054906 Entry Point 0x54601000
9183 11:38:48.054988 Loaded segments
9184 11:38:48.055070 NOTICE: MT8192 bl31_setup
9185 11:38:48.055153 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9186 11:38:48.055238 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9187 11:38:48.055322 WARNING: region 0:
9188 11:38:48.055404 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 11:38:48.055486 WARNING: region 1:
9190 11:38:48.055568 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9191 11:38:48.055650 WARNING: region 2:
9192 11:38:48.055732 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9193 11:38:48.055814 WARNING: region 3:
9194 11:38:48.055896 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9195 11:38:48.055978 WARNING: region 4:
9196 11:38:48.056059 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9197 11:38:48.056141 WARNING: region 5:
9198 11:38:48.056223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9199 11:38:48.056305 WARNING: region 6:
9200 11:38:48.056387 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9201 11:38:48.056469 WARNING: region 7:
9202 11:38:48.056550 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9203 11:38:48.056632 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9204 11:38:48.056714 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9205 11:38:48.056796 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9206 11:38:48.056878 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9207 11:38:48.056960 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9208 11:38:48.057042 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9209 11:38:48.057125 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9210 11:38:48.057207 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9211 11:38:48.057359 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9212 11:38:48.057441 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9213 11:38:48.057522 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9214 11:38:48.057636 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9215 11:38:48.057718 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9216 11:38:48.057800 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9217 11:38:48.057882 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9218 11:38:48.057963 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9219 11:38:48.058045 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9220 11:38:48.058126 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9221 11:38:48.058208 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9222 11:38:48.058290 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9223 11:38:48.058372 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9224 11:38:48.058454 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9225 11:38:48.058536 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9226 11:38:48.058617 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9227 11:38:48.058890 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9228 11:38:48.058973 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9229 11:38:48.059056 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9230 11:38:48.059138 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9231 11:38:48.059220 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9232 11:38:48.059302 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9233 11:38:48.059384 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9234 11:38:48.059466 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9235 11:38:48.059548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9236 11:38:48.059630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9237 11:38:48.059712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9238 11:38:48.059795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9239 11:38:48.059877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9240 11:38:48.059959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9241 11:38:48.060041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9242 11:38:48.060124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9243 11:38:48.060206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9244 11:38:48.060288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9245 11:38:48.060370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9246 11:38:48.060453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9247 11:38:48.060535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9248 11:38:48.060617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9249 11:38:48.060698 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9250 11:38:48.060781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9251 11:38:48.060863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9252 11:38:48.060946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9253 11:38:48.061028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9254 11:38:48.061110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9255 11:38:48.061193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9256 11:38:48.061318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9257 11:38:48.061401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9258 11:38:48.061483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9259 11:38:48.061587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9260 11:38:48.061683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9261 11:38:48.061765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9262 11:38:48.061847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9263 11:38:48.061929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9264 11:38:48.062011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9265 11:38:48.062094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9266 11:38:48.062176 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9267 11:38:48.062258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9268 11:38:48.062340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9269 11:38:48.062422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9270 11:38:48.062505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9271 11:38:48.062587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9272 11:38:48.062669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9273 11:38:48.062750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9274 11:38:48.062832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9275 11:38:48.062914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9276 11:38:48.062996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9277 11:38:48.063078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9278 11:38:48.063160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9279 11:38:48.063243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9280 11:38:48.063325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9281 11:38:48.063407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9282 11:38:48.063488 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9283 11:38:48.063571 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9284 11:38:48.063653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9285 11:38:48.063735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9286 11:38:48.063817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9287 11:38:48.063899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9288 11:38:48.063981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9289 11:38:48.064063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9290 11:38:48.064145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9291 11:38:48.064227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9292 11:38:48.064309 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9293 11:38:48.064391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9294 11:38:48.064473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9295 11:38:48.064555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9296 11:38:48.064637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9297 11:38:48.064719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9298 11:38:48.064802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9299 11:38:48.064884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9300 11:38:48.064967 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9301 11:38:48.065048 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9302 11:38:48.065129 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9303 11:38:48.065211 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9304 11:38:48.065555 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9305 11:38:48.065676 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9306 11:38:48.065755 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9307 11:38:48.065832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9308 11:38:48.065908 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9309 11:38:48.065982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9310 11:38:48.066055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9311 11:38:48.066128 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9312 11:38:48.066201 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9313 11:38:48.066273 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9314 11:38:48.066345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9315 11:38:48.066417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9316 11:38:48.066489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9317 11:38:48.066561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9318 11:38:48.066632 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9319 11:38:48.066705 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9320 11:38:48.066777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9321 11:38:48.066850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9322 11:38:48.066923 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9323 11:38:48.066995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9324 11:38:48.067067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9325 11:38:48.067140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9326 11:38:48.067211 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9327 11:38:48.067283 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9328 11:38:48.067355 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9329 11:38:48.067427 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9330 11:38:48.067499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9331 11:38:48.067571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9332 11:38:48.067642 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9333 11:38:48.067714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9334 11:38:48.067786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9335 11:38:48.067858 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9336 11:38:48.067930 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9337 11:38:48.068004 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9338 11:38:48.068076 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9339 11:38:48.068147 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9340 11:38:48.068219 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9341 11:38:48.068291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9342 11:38:48.068363 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9343 11:38:48.068435 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9344 11:38:48.068507 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9345 11:38:48.068578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9346 11:38:48.068650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9347 11:38:48.068722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9348 11:38:48.068794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9349 11:38:48.068865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9350 11:38:48.068937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9351 11:38:48.069009 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9352 11:38:48.069084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9353 11:38:48.069155 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9354 11:38:48.069234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9355 11:38:48.069356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9356 11:38:48.069428 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9357 11:38:48.069500 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9358 11:38:48.069571 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9359 11:38:48.069642 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9360 11:38:48.069714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9361 11:38:48.069785 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9362 11:38:48.069857 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9363 11:38:48.069929 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9364 11:38:48.070001 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9365 11:38:48.070073 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9366 11:38:48.070144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9367 11:38:48.070216 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9368 11:38:48.070288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9369 11:38:48.070360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9370 11:38:48.070432 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9371 11:38:48.070504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9372 11:38:48.070575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9373 11:38:48.070646 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9374 11:38:48.070718 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9375 11:38:48.070790 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9376 11:38:48.070863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9377 11:38:48.070935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9378 11:38:48.071007 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9379 11:38:48.071078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9380 11:38:48.071150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9381 11:38:48.071418 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9382 11:38:48.071500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9383 11:38:48.071575 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9384 11:38:48.071649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9385 11:38:48.071722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9386 11:38:48.071795 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9387 11:38:48.071867 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9388 11:38:48.071939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9389 11:38:48.072012 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9390 11:38:48.072084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9391 11:38:48.072155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9392 11:38:48.072227 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9393 11:38:48.072299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9394 11:38:48.072371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9395 11:38:48.072442 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9396 11:38:48.072515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9397 11:38:48.072586 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9398 11:38:48.072657 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9399 11:38:48.072728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9400 11:38:48.072798 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9401 11:38:48.072869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9402 11:38:48.072942 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9403 11:38:48.073016 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9404 11:38:48.073088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9405 11:38:48.073161 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9406 11:38:48.073240 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9407 11:38:48.073367 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9408 11:38:48.073439 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9409 11:38:48.073511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9410 11:38:48.073584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9411 11:38:48.073655 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9412 11:38:48.073729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9413 11:38:48.073802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9414 11:38:48.073875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9415 11:38:48.073948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9416 11:38:48.074028 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9417 11:38:48.074111 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9418 11:38:48.074194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9419 11:38:48.074281 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9420 11:38:48.074364 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9421 11:38:48.074450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9422 11:38:48.074546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9423 11:38:48.074630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9424 11:38:48.074709 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9425 11:38:48.074785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9426 11:38:48.074860 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9427 11:38:48.074935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9428 11:38:48.075010 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9429 11:38:48.075085 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9430 11:38:48.075159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9431 11:38:48.075234 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9432 11:38:48.075309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9433 11:38:48.075383 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9434 11:38:48.075457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9435 11:38:48.075531 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9436 11:38:48.075607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9437 11:38:48.075682 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9438 11:38:48.075756 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9439 11:38:48.075830 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9440 11:38:48.075904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9441 11:38:48.075979 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9442 11:38:48.076053 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9443 11:38:48.076127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9444 11:38:48.076201 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9445 11:38:48.076276 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9446 11:38:48.076350 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9447 11:38:48.076424 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9448 11:38:48.076499 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9449 11:38:48.076573 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9450 11:38:48.076648 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9451 11:38:48.076721 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9452 11:38:48.076798 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9453 11:38:48.076913 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9454 11:38:48.076987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9455 11:38:48.077062 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9456 11:38:48.077136 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9457 11:38:48.077399 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9458 11:38:48.077481 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9459 11:38:48.077558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9460 11:38:48.077633 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9461 11:38:48.077708 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9462 11:38:48.077783 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9463 11:38:48.077857 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9464 11:38:48.077932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9465 11:38:48.078006 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9466 11:38:48.078080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9467 11:38:48.078155 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9468 11:38:48.078229 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9469 11:38:48.078304 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9470 11:38:48.078379 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9471 11:38:48.078453 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9472 11:38:48.078527 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9473 11:38:48.078602 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9474 11:38:48.078676 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9475 11:38:48.078759 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9476 11:38:48.078812 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9477 11:38:48.078860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9478 11:38:48.078908 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9479 11:38:48.078956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9480 11:38:48.079003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9481 11:38:48.079050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9482 11:38:48.079097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9483 11:38:48.079143 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9484 11:38:48.079190 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9485 11:38:48.079237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9486 11:38:48.079284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9487 11:38:48.079331 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9488 11:38:48.079378 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9489 11:38:48.079425 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9490 11:38:48.079472 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9491 11:38:48.079518 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9492 11:38:48.079565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9493 11:38:48.079612 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9494 11:38:48.079659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9495 11:38:48.079706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9496 11:38:48.079754 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9497 11:38:48.079801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9498 11:38:48.079847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9499 11:38:48.079894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9500 11:38:48.079941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9501 11:38:48.079988 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9502 11:38:48.080036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9503 11:38:48.080083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9504 11:38:48.080130 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9505 11:38:48.080177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9506 11:38:48.080224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9507 11:38:48.080270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9508 11:38:48.080317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9509 11:38:48.080364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9510 11:38:48.080411 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9511 11:38:48.080458 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9512 11:38:48.080504 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9513 11:38:48.080552 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9514 11:38:48.080599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9515 11:38:48.080645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9516 11:38:48.080693 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9517 11:38:48.080740 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9518 11:38:48.080787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9519 11:38:48.080834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9520 11:38:48.080881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9521 11:38:48.080928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9522 11:38:48.080975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9523 11:38:48.081022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9524 11:38:48.081069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9525 11:38:48.081116 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9526 11:38:48.081164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9527 11:38:48.081212 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9528 11:38:48.081304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9529 11:38:48.081353 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9530 11:38:48.081400 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9531 11:38:48.081447 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9532 11:38:48.081493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9533 11:38:48.081540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9534 11:38:48.081588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9535 11:38:48.081821 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9536 11:38:48.081874 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9537 11:38:48.081922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9538 11:38:48.081969 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9539 11:38:48.082016 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9540 11:38:48.082064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9541 11:38:48.082111 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9542 11:38:48.082158 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9543 11:38:48.082205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9544 11:38:48.082253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9545 11:38:48.082300 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9546 11:38:48.082346 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9547 11:38:48.082393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9548 11:38:48.082439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9549 11:38:48.082486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9550 11:38:48.082533 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9551 11:38:48.082580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9552 11:38:48.082627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9553 11:38:48.082674 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9554 11:38:48.082720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9555 11:38:48.082767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9556 11:38:48.082834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9557 11:38:48.082882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9558 11:38:48.082930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9559 11:38:48.082977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9560 11:38:48.083024 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9561 11:38:48.083071 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9562 11:38:48.083118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9563 11:38:48.083165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9564 11:38:48.083212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9565 11:38:48.083259 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9566 11:38:48.083307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9567 11:38:48.083354 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9568 11:38:48.083401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9569 11:38:48.083448 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9570 11:38:48.083494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9571 11:38:48.083541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9572 11:38:48.083587 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9573 11:38:48.083634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9574 11:38:48.083681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9575 11:38:48.083727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9576 11:38:48.083774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9577 11:38:48.083821 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9578 11:38:48.083868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9579 11:38:48.083915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9580 11:38:48.083962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9581 11:38:48.084009 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9582 11:38:48.084056 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9583 11:38:48.084102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9584 11:38:48.084148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9585 11:38:48.084196 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9586 11:38:48.084242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9587 11:38:48.084288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9588 11:38:48.084335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9589 11:38:48.084382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9590 11:38:48.084428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9591 11:38:48.084474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9592 11:38:48.084532 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9593 11:38:48.085055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9594 11:38:48.088718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9595 11:38:48.095359 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9596 11:38:48.098398 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9597 11:38:48.105495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9598 11:38:48.108976 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9599 11:38:48.115550 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9600 11:38:48.118622 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9601 11:38:48.121773 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9602 11:38:48.128480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9603 11:38:48.131424 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9604 11:38:48.138839 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9605 11:38:48.141680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9606 11:38:48.148157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9607 11:38:48.151251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9608 11:38:48.155502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9609 11:38:48.162435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9610 11:38:48.164814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9611 11:38:48.171567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9612 11:38:48.175555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9613 11:38:48.182063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9614 11:38:48.185173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9615 11:38:48.192098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9616 11:38:48.194871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9617 11:38:48.203317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9618 11:38:48.204979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9619 11:38:48.211663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9620 11:38:48.214713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9621 11:38:48.221337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9622 11:38:48.224887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9623 11:38:48.231468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9624 11:38:48.234768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9625 11:38:48.241502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9626 11:38:48.245473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9627 11:38:48.251987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9628 11:38:48.254772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9629 11:38:48.261711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9630 11:38:48.264417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9631 11:38:48.271379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9632 11:38:48.274496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9633 11:38:48.280827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9634 11:38:48.284279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9635 11:38:48.291142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9636 11:38:48.294784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9637 11:38:48.300758 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9638 11:38:48.301183 INFO: [APUAPC] vio 0
9639 11:38:48.307575 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9640 11:38:48.310720 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9641 11:38:48.314364 INFO: [APUAPC] D0_APC_0: 0x400510
9642 11:38:48.317116 INFO: [APUAPC] D0_APC_1: 0x0
9643 11:38:48.320440 INFO: [APUAPC] D0_APC_2: 0x1540
9644 11:38:48.324065 INFO: [APUAPC] D0_APC_3: 0x0
9645 11:38:48.327163 INFO: [APUAPC] D1_APC_0: 0xffffffff
9646 11:38:48.330980 INFO: [APUAPC] D1_APC_1: 0xffffffff
9647 11:38:48.333658 INFO: [APUAPC] D1_APC_2: 0x3fffff
9648 11:38:48.337514 INFO: [APUAPC] D1_APC_3: 0x0
9649 11:38:48.340387 INFO: [APUAPC] D2_APC_0: 0xffffffff
9650 11:38:48.344881 INFO: [APUAPC] D2_APC_1: 0xffffffff
9651 11:38:48.347546 INFO: [APUAPC] D2_APC_2: 0x3fffff
9652 11:38:48.350631 INFO: [APUAPC] D2_APC_3: 0x0
9653 11:38:48.353612 INFO: [APUAPC] D3_APC_0: 0xffffffff
9654 11:38:48.357284 INFO: [APUAPC] D3_APC_1: 0xffffffff
9655 11:38:48.361021 INFO: [APUAPC] D3_APC_2: 0x3fffff
9656 11:38:48.363974 INFO: [APUAPC] D3_APC_3: 0x0
9657 11:38:48.367810 INFO: [APUAPC] D4_APC_0: 0xffffffff
9658 11:38:48.370372 INFO: [APUAPC] D4_APC_1: 0xffffffff
9659 11:38:48.373759 INFO: [APUAPC] D4_APC_2: 0x3fffff
9660 11:38:48.376832 INFO: [APUAPC] D4_APC_3: 0x0
9661 11:38:48.380569 INFO: [APUAPC] D5_APC_0: 0xffffffff
9662 11:38:48.384118 INFO: [APUAPC] D5_APC_1: 0xffffffff
9663 11:38:48.386930 INFO: [APUAPC] D5_APC_2: 0x3fffff
9664 11:38:48.387362 INFO: [APUAPC] D5_APC_3: 0x0
9665 11:38:48.390500 INFO: [APUAPC] D6_APC_0: 0xffffffff
9666 11:38:48.396803 INFO: [APUAPC] D6_APC_1: 0xffffffff
9667 11:38:48.397350 INFO: [APUAPC] D6_APC_2: 0x3fffff
9668 11:38:48.400474 INFO: [APUAPC] D6_APC_3: 0x0
9669 11:38:48.403263 INFO: [APUAPC] D7_APC_0: 0xffffffff
9670 11:38:48.406746 INFO: [APUAPC] D7_APC_1: 0xffffffff
9671 11:38:48.411473 INFO: [APUAPC] D7_APC_2: 0x3fffff
9672 11:38:48.413215 INFO: [APUAPC] D7_APC_3: 0x0
9673 11:38:48.417828 INFO: [APUAPC] D8_APC_0: 0xffffffff
9674 11:38:48.420087 INFO: [APUAPC] D8_APC_1: 0xffffffff
9675 11:38:48.423675 INFO: [APUAPC] D8_APC_2: 0x3fffff
9676 11:38:48.427181 INFO: [APUAPC] D8_APC_3: 0x0
9677 11:38:48.429810 INFO: [APUAPC] D9_APC_0: 0xffffffff
9678 11:38:48.433675 INFO: [APUAPC] D9_APC_1: 0xffffffff
9679 11:38:48.436534 INFO: [APUAPC] D9_APC_2: 0x3fffff
9680 11:38:48.440478 INFO: [APUAPC] D9_APC_3: 0x0
9681 11:38:48.444789 INFO: [APUAPC] D10_APC_0: 0xffffffff
9682 11:38:48.447532 INFO: [APUAPC] D10_APC_1: 0xffffffff
9683 11:38:48.450133 INFO: [APUAPC] D10_APC_2: 0x3fffff
9684 11:38:48.453676 INFO: [APUAPC] D10_APC_3: 0x0
9685 11:38:48.457585 INFO: [APUAPC] D11_APC_0: 0xffffffff
9686 11:38:48.459865 INFO: [APUAPC] D11_APC_1: 0xffffffff
9687 11:38:48.463169 INFO: [APUAPC] D11_APC_2: 0x3fffff
9688 11:38:48.466687 INFO: [APUAPC] D11_APC_3: 0x0
9689 11:38:48.470124 INFO: [APUAPC] D12_APC_0: 0xffffffff
9690 11:38:48.473379 INFO: [APUAPC] D12_APC_1: 0xffffffff
9691 11:38:48.476524 INFO: [APUAPC] D12_APC_2: 0x3fffff
9692 11:38:48.479675 INFO: [APUAPC] D12_APC_3: 0x0
9693 11:38:48.484339 INFO: [APUAPC] D13_APC_0: 0xffffffff
9694 11:38:48.486984 INFO: [APUAPC] D13_APC_1: 0xffffffff
9695 11:38:48.489440 INFO: [APUAPC] D13_APC_2: 0x3fffff
9696 11:38:48.493093 INFO: [APUAPC] D13_APC_3: 0x0
9697 11:38:48.497012 INFO: [APUAPC] D14_APC_0: 0xffffffff
9698 11:38:48.500154 INFO: [APUAPC] D14_APC_1: 0xffffffff
9699 11:38:48.503052 INFO: [APUAPC] D14_APC_2: 0x3fffff
9700 11:38:48.506223 INFO: [APUAPC] D14_APC_3: 0x0
9701 11:38:48.509683 INFO: [APUAPC] D15_APC_0: 0xffffffff
9702 11:38:48.512746 INFO: [APUAPC] D15_APC_1: 0xffffffff
9703 11:38:48.517444 INFO: [APUAPC] D15_APC_2: 0x3fffff
9704 11:38:48.519963 INFO: [APUAPC] D15_APC_3: 0x0
9705 11:38:48.523357 INFO: [APUAPC] APC_CON: 0x4
9706 11:38:48.526217 INFO: [NOCDAPC] D0_APC_0: 0x0
9707 11:38:48.529066 INFO: [NOCDAPC] D0_APC_1: 0x0
9708 11:38:48.534150 INFO: [NOCDAPC] D1_APC_0: 0x0
9709 11:38:48.537077 INFO: [NOCDAPC] D1_APC_1: 0xfff
9710 11:38:48.539361 INFO: [NOCDAPC] D2_APC_0: 0x0
9711 11:38:48.543162 INFO: [NOCDAPC] D2_APC_1: 0xfff
9712 11:38:48.543599 INFO: [NOCDAPC] D3_APC_0: 0x0
9713 11:38:48.546328 INFO: [NOCDAPC] D3_APC_1: 0xfff
9714 11:38:48.549597 INFO: [NOCDAPC] D4_APC_0: 0x0
9715 11:38:48.552517 INFO: [NOCDAPC] D4_APC_1: 0xfff
9716 11:38:48.555746 INFO: [NOCDAPC] D5_APC_0: 0x0
9717 11:38:48.559707 INFO: [NOCDAPC] D5_APC_1: 0xfff
9718 11:38:48.562896 INFO: [NOCDAPC] D6_APC_0: 0x0
9719 11:38:48.566446 INFO: [NOCDAPC] D6_APC_1: 0xfff
9720 11:38:48.569394 INFO: [NOCDAPC] D7_APC_0: 0x0
9721 11:38:48.572604 INFO: [NOCDAPC] D7_APC_1: 0xfff
9722 11:38:48.576062 INFO: [NOCDAPC] D8_APC_0: 0x0
9723 11:38:48.576562 INFO: [NOCDAPC] D8_APC_1: 0xfff
9724 11:38:48.579290 INFO: [NOCDAPC] D9_APC_0: 0x0
9725 11:38:48.583110 INFO: [NOCDAPC] D9_APC_1: 0xfff
9726 11:38:48.586684 INFO: [NOCDAPC] D10_APC_0: 0x0
9727 11:38:48.589310 INFO: [NOCDAPC] D10_APC_1: 0xfff
9728 11:38:48.592354 INFO: [NOCDAPC] D11_APC_0: 0x0
9729 11:38:48.596495 INFO: [NOCDAPC] D11_APC_1: 0xfff
9730 11:38:48.599052 INFO: [NOCDAPC] D12_APC_0: 0x0
9731 11:38:48.604023 INFO: [NOCDAPC] D12_APC_1: 0xfff
9732 11:38:48.605571 INFO: [NOCDAPC] D13_APC_0: 0x0
9733 11:38:48.609608 INFO: [NOCDAPC] D13_APC_1: 0xfff
9734 11:38:48.612600 INFO: [NOCDAPC] D14_APC_0: 0x0
9735 11:38:48.615398 INFO: [NOCDAPC] D14_APC_1: 0xfff
9736 11:38:48.618776 INFO: [NOCDAPC] D15_APC_0: 0x0
9737 11:38:48.623162 INFO: [NOCDAPC] D15_APC_1: 0xfff
9738 11:38:48.623587 INFO: [NOCDAPC] APC_CON: 0x4
9739 11:38:48.626460 INFO: [APUAPC] set_apusys_apc done
9740 11:38:48.628929 INFO: [DEVAPC] devapc_init done
9741 11:38:48.635793 INFO: GICv3 without legacy support detected.
9742 11:38:48.638479 INFO: ARM GICv3 driver initialized in EL3
9743 11:38:48.642044 INFO: Maximum SPI INTID supported: 639
9744 11:38:48.645338 INFO: BL31: Initializing runtime services
9745 11:38:48.652946 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9746 11:38:48.655220 INFO: SPM: enable CPC mode
9747 11:38:48.658820 INFO: mcdi ready for mcusys-off-idle and system suspend
9748 11:38:48.666136 INFO: BL31: Preparing for EL3 exit to normal world
9749 11:38:48.668736 INFO: Entry point address = 0x80000000
9750 11:38:48.669163 INFO: SPSR = 0x8
9751 11:38:48.675696
9752 11:38:48.676206
9753 11:38:48.676539
9754 11:38:48.678663 Starting depthcharge on Spherion...
9755 11:38:48.679090
9756 11:38:48.679422 Wipe memory regions:
9757 11:38:48.679728
9758 11:38:48.682209 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9759 11:38:48.682716 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
9760 11:38:48.683114 Setting prompt string to ['asurada:']
9761 11:38:48.683465 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
9762 11:38:48.684105 [0x00000040000000, 0x00000054600000)
9763 11:38:48.804454
9764 11:38:48.804954 [0x00000054660000, 0x00000080000000)
9765 11:38:49.065652
9766 11:38:49.066154 [0x000000821a7280, 0x000000ffe64000)
9767 11:38:49.810108
9768 11:38:49.810607 [0x00000100000000, 0x00000140000000)
9769 11:38:50.190560
9770 11:38:50.194631 Initializing XHCI USB controller at 0x11200000.
9771 11:38:51.232561
9772 11:38:51.235774 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9773 11:38:51.236198
9774 11:38:51.236543
9775 11:38:51.237289 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9776 11:38:51.237699 Sending line: 'tftpboot 192.168.201.1 14864651/tftp-deploy-lbt7ol7e/kernel/image.itb 14864651/tftp-deploy-lbt7ol7e/kernel/cmdline '
9778 11:38:51.339397 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9779 11:38:51.339904 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:18)
9780 11:38:51.345037 asurada: tftpboot 192.168.201.1 14864651/tftp-deploy-lbt7ol7e/kernel/image.itp-deploy-lbt7ol7e/kernel/cmdline
9781 11:38:51.345626
9782 11:38:51.345968 Waiting for link
9783 11:38:51.503239
9784 11:38:51.503744 R8152: Initializing
9785 11:38:51.504082
9786 11:38:51.506344 Version 9 (ocp_data = 6010)
9787 11:38:51.506849
9788 11:38:51.509318 R8152: Done initializing
9789 11:38:51.509876
9790 11:38:51.510215 Adding net device
9791 11:38:53.394127
9792 11:38:53.394631 done.
9793 11:38:53.394968
9794 11:38:53.395273 MAC: 00:e0:4c:68:03:bd
9795 11:38:53.395567
9796 11:38:53.397504 Sending DHCP discover... done.
9797 11:38:53.397926
9798 11:38:53.400091 Waiting for reply... done.
9799 11:38:53.400164
9800 11:38:53.404270 Sending DHCP request... done.
9801 11:38:53.404434
9802 11:38:53.407096 Waiting for reply... done.
9803 11:38:53.407329
9804 11:38:53.407463 My ip is 192.168.201.16
9805 11:38:53.407584
9806 11:38:53.410183 The DHCP server ip is 192.168.201.1
9807 11:38:53.410350
9808 11:38:53.417478 TFTP server IP predefined by user: 192.168.201.1
9809 11:38:53.417702
9810 11:38:53.423635 Bootfile predefined by user: 14864651/tftp-deploy-lbt7ol7e/kernel/image.itb
9811 11:38:53.423875
9812 11:38:53.424010 Sending tftp read request... done.
9813 11:38:53.427455
9814 11:38:53.432223 Waiting for the transfer...
9815 11:38:53.432419
9816 11:38:53.814378 00000000 ################################################################
9817 11:38:53.814819
9818 11:38:54.209215 00080000 ################################################################
9819 11:38:54.209788
9820 11:38:54.533884 00100000 ################################################################
9821 11:38:54.534007
9822 11:38:54.817336 00180000 ################################################################
9823 11:38:54.817460
9824 11:38:55.104290 00200000 ################################################################
9825 11:38:55.104414
9826 11:38:55.393828 00280000 ################################################################
9827 11:38:55.393955
9828 11:38:55.690152 00300000 ################################################################
9829 11:38:55.690293
9830 11:38:55.987600 00380000 ################################################################
9831 11:38:55.987720
9832 11:38:56.270098 00400000 ################################################################
9833 11:38:56.270220
9834 11:38:56.542053 00480000 ################################################################
9835 11:38:56.542172
9836 11:38:56.814268 00500000 ################################################################
9837 11:38:56.814399
9838 11:38:57.099535 00580000 ################################################################
9839 11:38:57.099655
9840 11:38:57.397671 00600000 ################################################################
9841 11:38:57.397793
9842 11:38:57.676610 00680000 ################################################################
9843 11:38:57.676737
9844 11:38:57.980804 00700000 ################################################################
9845 11:38:57.981086
9846 11:38:58.362015 00780000 ################################################################
9847 11:38:58.362476
9848 11:38:58.705129 00800000 ################################################################
9849 11:38:58.705285
9850 11:38:58.981136 00880000 ################################################################
9851 11:38:58.981265
9852 11:38:59.273010 00900000 ################################################################
9853 11:38:59.273127
9854 11:38:59.558244 00980000 ################################################################
9855 11:38:59.558363
9856 11:38:59.846925 00a00000 ################################################################
9857 11:38:59.847046
9858 11:39:00.121114 00a80000 ################################################################
9859 11:39:00.121276
9860 11:39:00.375767 00b00000 ################################################################
9861 11:39:00.375886
9862 11:39:00.668988 00b80000 ################################################################
9863 11:39:00.669107
9864 11:39:00.943698 00c00000 ################################################################
9865 11:39:00.943826
9866 11:39:01.216817 00c80000 ################################################################
9867 11:39:01.216942
9868 11:39:01.512388 00d00000 ################################################################
9869 11:39:01.512512
9870 11:39:01.780139 00d80000 ################################################################
9871 11:39:01.780261
9872 11:39:02.075347 00e00000 ################################################################
9873 11:39:02.075474
9874 11:39:02.340823 00e80000 ################################################################
9875 11:39:02.340951
9876 11:39:02.618479 00f00000 ################################################################
9877 11:39:02.618596
9878 11:39:02.905465 00f80000 ################################################################
9879 11:39:02.905585
9880 11:39:03.187924 01000000 ################################################################
9881 11:39:03.188048
9882 11:39:03.473166 01080000 ################################################################
9883 11:39:03.473305
9884 11:39:03.766884 01100000 ################################################################
9885 11:39:03.767009
9886 11:39:04.055733 01180000 ################################################################
9887 11:39:04.055860
9888 11:39:04.321585 01200000 ################################################################
9889 11:39:04.321709
9890 11:39:04.578865 01280000 ################################################################
9891 11:39:04.578984
9892 11:39:04.871371 01300000 ################################################################
9893 11:39:04.871485
9894 11:39:05.167890 01380000 ################################################################
9895 11:39:05.168020
9896 11:39:05.463932 01400000 ################################################################
9897 11:39:05.464053
9898 11:39:05.729821 01480000 ################################################################
9899 11:39:05.729945
9900 11:39:06.014369 01500000 ################################################################
9901 11:39:06.014493
9902 11:39:06.304441 01580000 ################################################################
9903 11:39:06.304566
9904 11:39:06.601457 01600000 ################################################################
9905 11:39:06.601578
9906 11:39:06.887692 01680000 ################################################################
9907 11:39:06.887829
9908 11:39:07.175448 01700000 ################################################################
9909 11:39:07.175572
9910 11:39:07.467713 01780000 ################################################################
9911 11:39:07.467835
9912 11:39:07.741413 01800000 ################################################################
9913 11:39:07.741564
9914 11:39:08.054094 01880000 ################################################################
9915 11:39:08.054624
9916 11:39:08.437933 01900000 ################################################################
9917 11:39:08.438304
9918 11:39:08.816221 01980000 ################################################################
9919 11:39:08.816684
9920 11:39:09.176163 01a00000 ################################################################
9921 11:39:09.176283
9922 11:39:09.448036 01a80000 ################################################################
9923 11:39:09.448162
9924 11:39:09.699807 01b00000 ################################################################
9925 11:39:09.699927
9926 11:39:09.985801 01b80000 ################################################################
9927 11:39:09.985927
9928 11:39:10.275004 01c00000 ################################################################
9929 11:39:10.275150
9930 11:39:10.571508 01c80000 ################################################################
9931 11:39:10.571635
9932 11:39:10.855995 01d00000 ################################################################
9933 11:39:10.856110
9934 11:39:11.127439 01d80000 ################################################################
9935 11:39:11.127562
9936 11:39:11.396756 01e00000 ################################################################
9937 11:39:11.396904
9938 11:39:11.695533 01e80000 ################################################################
9939 11:39:11.695655
9940 11:39:11.974555 01f00000 ################################################################
9941 11:39:11.974677
9942 11:39:12.264526 01f80000 ################################################################
9943 11:39:12.264648
9944 11:39:12.557094 02000000 ################################################################
9945 11:39:12.557247
9946 11:39:12.854516 02080000 ################################################################
9947 11:39:12.854644
9948 11:39:13.150927 02100000 ################################################################
9949 11:39:13.151053
9950 11:39:13.443647 02180000 ################################################################
9951 11:39:13.443767
9952 11:39:13.735208 02200000 ################################################################
9953 11:39:13.735333
9954 11:39:13.985147 02280000 ################################################################
9955 11:39:13.985304
9956 11:39:14.244514 02300000 ################################################################
9957 11:39:14.244636
9958 11:39:14.564854 02380000 ################################################################
9959 11:39:14.565325
9960 11:39:14.951666 02400000 ################################################################
9961 11:39:14.952125
9962 11:39:15.333484 02480000 ################################################################
9963 11:39:15.333962
9964 11:39:15.711476 02500000 ################################################################
9965 11:39:15.712077
9966 11:39:16.015904 02580000 ################################################################
9967 11:39:16.016029
9968 11:39:16.276725 02600000 ################################################################
9969 11:39:16.276878
9970 11:39:16.568113 02680000 ################################################################
9971 11:39:16.568231
9972 11:39:16.862700 02700000 ################################################################
9973 11:39:16.862818
9974 11:39:17.159654 02780000 ################################################################
9975 11:39:17.159779
9976 11:39:17.445992 02800000 ################################################################
9977 11:39:17.446115
9978 11:39:17.743138 02880000 ################################################################
9979 11:39:17.743251
9980 11:39:18.029125 02900000 ################################################################
9981 11:39:18.029252
9982 11:39:18.318281 02980000 ################################################################
9983 11:39:18.318426
9984 11:39:18.609460 02a00000 ################################################################
9985 11:39:18.609583
9986 11:39:18.907490 02a80000 ################################################################
9987 11:39:18.907606
9988 11:39:19.206244 02b00000 ################################################################
9989 11:39:19.206403
9990 11:39:19.491990 02b80000 ################################################################
9991 11:39:19.492110
9992 11:39:19.759493 02c00000 ################################################################
9993 11:39:19.759612
9994 11:39:20.058195 02c80000 ################################################################
9995 11:39:20.058317
9996 11:39:20.328949 02d00000 ################################################################
9997 11:39:20.329066
9998 11:39:20.617499 02d80000 ################################################################
9999 11:39:20.617627
10000 11:39:20.871195 02e00000 ################################################################
10001 11:39:20.871323
10002 11:39:21.150243 02e80000 ################################################################
10003 11:39:21.150363
10004 11:39:21.447961 02f00000 ################################################################
10005 11:39:21.448079
10006 11:39:21.734703 02f80000 ################################################################
10007 11:39:21.734827
10008 11:39:22.026940 03000000 ################################################################
10009 11:39:22.027064
10010 11:39:22.310410 03080000 ################################################################
10011 11:39:22.310527
10012 11:39:22.603294 03100000 ################################################################
10013 11:39:22.603412
10014 11:39:22.880254 03180000 ################################################################
10015 11:39:22.880380
10016 11:39:23.159915 03200000 ################################################################
10017 11:39:23.160037
10018 11:39:23.448749 03280000 ################################################################
10019 11:39:23.448873
10020 11:39:23.744212 03300000 ################################################################
10021 11:39:23.744334
10022 11:39:24.034830 03380000 ################################################################
10023 11:39:24.034966
10024 11:39:24.312396 03400000 ################################################################
10025 11:39:24.312525
10026 11:39:24.597067 03480000 ################################################################
10027 11:39:24.597191
10028 11:39:24.866673 03500000 ################################################################
10029 11:39:24.866788
10030 11:39:25.162047 03580000 ################################################################
10031 11:39:25.162175
10032 11:39:25.431471 03600000 ################################################################
10033 11:39:25.431603
10034 11:39:25.727350 03680000 ################################################################
10035 11:39:25.727502
10036 11:39:26.025576 03700000 ################################################################
10037 11:39:26.025693
10038 11:39:26.320859 03780000 ################################################################
10039 11:39:26.320994
10040 11:39:26.611077 03800000 ################################################################
10041 11:39:26.611202
10042 11:39:26.909709 03880000 ################################################################
10043 11:39:26.909834
10044 11:39:27.205817 03900000 ################################################################
10045 11:39:27.205938
10046 11:39:27.499168 03980000 ################################################################
10047 11:39:27.499292
10048 11:39:27.792924 03a00000 ################################################################
10049 11:39:27.793051
10050 11:39:28.074271 03a80000 ################################################################
10051 11:39:28.074391
10052 11:39:28.343843 03b00000 ################################################################
10053 11:39:28.343968
10054 11:39:28.634968 03b80000 ################################################################
10055 11:39:28.635094
10056 11:39:28.904726 03c00000 ################################################################
10057 11:39:28.904850
10058 11:39:29.189494 03c80000 ################################################################
10059 11:39:29.189617
10060 11:39:29.490604 03d00000 ################################################################
10061 11:39:29.490729
10062 11:39:29.783547 03d80000 ################################################################
10063 11:39:29.783675
10064 11:39:30.078297 03e00000 ################################################################
10065 11:39:30.078423
10066 11:39:30.352830 03e80000 ################################################################
10067 11:39:30.352956
10068 11:39:30.642192 03f00000 ################################################################
10069 11:39:30.642310
10070 11:39:30.904004 03f80000 ################################################################
10071 11:39:30.904151
10072 11:39:31.195051 04000000 ################################################################
10073 11:39:31.195193
10074 11:39:31.490849 04080000 ################################################################
10075 11:39:31.490975
10076 11:39:31.748697 04100000 ################################################################
10077 11:39:31.748824
10078 11:39:32.007540 04180000 ################################################################
10079 11:39:32.007663
10080 11:39:32.277777 04200000 ################################################################
10081 11:39:32.277898
10082 11:39:32.558493 04280000 ################################################################
10083 11:39:32.558619
10084 11:39:32.821051 04300000 ################################################################
10085 11:39:32.821175
10086 11:39:33.081769 04380000 ################################################################
10087 11:39:33.081894
10088 11:39:33.344027 04400000 ################################################################
10089 11:39:33.344148
10090 11:39:33.597830 04480000 ################################################################
10091 11:39:33.597952
10092 11:39:33.849484 04500000 ################################################################
10093 11:39:33.849605
10094 11:39:34.105613 04580000 ################################################################
10095 11:39:34.105740
10096 11:39:34.363457 04600000 ################################################################
10097 11:39:34.363580
10098 11:39:34.489894 04680000 ############################ done.
10099 11:39:34.490344
10100 11:39:34.493452 The bootfile was 74153490 bytes long.
10101 11:39:34.493841
10102 11:39:34.496097 Sending tftp read request... done.
10103 11:39:34.496483
10104 11:39:34.500780 Waiting for the transfer...
10105 11:39:34.501162
10106 11:39:34.501493 00000000 # done.
10107 11:39:34.501781
10108 11:39:34.507614 Command line loaded dynamically from TFTP file: 14864651/tftp-deploy-lbt7ol7e/kernel/cmdline
10109 11:39:34.508005
10110 11:39:34.521013 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10111 11:39:34.524789
10112 11:39:34.525297 Loading FIT.
10113 11:39:34.525606
10114 11:39:34.527631 Image ramdisk-1 has 60985909 bytes.
10115 11:39:34.528015
10116 11:39:34.530436 Image fdt-1 has 47258 bytes.
10117 11:39:34.530818
10118 11:39:34.533883 Image kernel-1 has 13118294 bytes.
10119 11:39:34.534266
10120 11:39:34.541008 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10121 11:39:34.541569
10122 11:39:34.561187 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10123 11:39:34.561749
10124 11:39:34.564109 Choosing best match conf-1 for compat google,spherion-rev3.
10125 11:39:34.569194
10126 11:39:34.573609 Connected to device vid:did:rid of 1ae0:0028:00
10127 11:39:34.579849
10128 11:39:34.585390 tpm_get_response: command 0x17b, return code 0x0
10129 11:39:34.585958
10130 11:39:34.587652 ec_init: CrosEC protocol v3 supported (256, 248)
10131 11:39:34.590048
10132 11:39:34.594039 tpm_cleanup: add release locality here.
10133 11:39:34.594556
10134 11:39:34.594894 Shutting down all USB controllers.
10135 11:39:34.596991
10136 11:39:34.597488 Removing current net device
10137 11:39:34.597824
10138 11:39:34.603578 Exiting depthcharge with code 4 at timestamp: 74211940
10139 11:39:34.604073
10140 11:39:34.608195 LZMA decompressing kernel-1 to 0x821a6718
10141 11:39:34.608708
10142 11:39:34.610502 LZMA decompressing kernel-1 to 0x40000000
10143 11:39:36.224484
10144 11:39:36.224996 jumping to kernel
10145 11:39:36.227283 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10146 11:39:36.227797 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10147 11:39:36.228163 Setting prompt string to ['Linux version [0-9]']
10148 11:39:36.228506 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10149 11:39:36.228852 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10150 11:39:36.275010
10151 11:39:36.278667 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10152 11:39:36.282428 start: 2.2.5.1 login-action (timeout 00:03:33) [common]
10153 11:39:36.282993 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10154 11:39:36.283369 Setting prompt string to []
10155 11:39:36.283774 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10156 11:39:36.284145 Using line separator: #'\n'#
10157 11:39:36.284463 No login prompt set.
10158 11:39:36.284814 Parsing kernel messages
10159 11:39:36.285127 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10160 11:39:36.285709 [login-action] Waiting for messages, (timeout 00:03:33)
10161 11:39:36.286031 Waiting using forced prompt support (timeout 00:01:47)
10162 11:39:36.302428 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10163 11:39:36.304781 [ 0.000000] random: crng init done
10164 11:39:36.308078 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10165 11:39:36.311416 [ 0.000000] efi: UEFI not found.
10166 11:39:36.320834 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10167 11:39:36.328631 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10168 11:39:36.337860 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10169 11:39:36.347785 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10170 11:39:36.355140 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10171 11:39:36.357355 [ 0.000000] printk: bootconsole [mtk8250] enabled
10172 11:39:36.366255 [ 0.000000] NUMA: No NUMA configuration found
10173 11:39:36.372482 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10174 11:39:36.379452 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10175 11:39:36.379881 [ 0.000000] Zone ranges:
10176 11:39:36.386102 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10177 11:39:36.389012 [ 0.000000] DMA32 empty
10178 11:39:36.397758 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10179 11:39:36.398667 [ 0.000000] Movable zone start for each node
10180 11:39:36.402853 [ 0.000000] Early memory node ranges
10181 11:39:36.408450 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10182 11:39:36.415666 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10183 11:39:36.422131 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10184 11:39:36.429105 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10185 11:39:36.436315 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10186 11:39:36.441818 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10187 11:39:36.473359 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10188 11:39:36.479634 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10189 11:39:36.485535 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10190 11:39:36.490054 [ 0.000000] psci: probing for conduit method from DT.
10191 11:39:36.495828 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10192 11:39:36.499509 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10193 11:39:36.506110 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10194 11:39:36.510052 [ 0.000000] psci: SMC Calling Convention v1.2
10195 11:39:36.515958 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10196 11:39:36.519691 [ 0.000000] Detected VIPT I-cache on CPU0
10197 11:39:36.525368 [ 0.000000] CPU features: detected: GIC system register CPU interface
10198 11:39:36.532937 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10199 11:39:36.540426 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10200 11:39:36.546183 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10201 11:39:36.555218 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10202 11:39:36.562085 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10203 11:39:36.565408 [ 0.000000] alternatives: applying boot alternatives
10204 11:39:36.572629 [ 0.000000] Fallback order for Node 0: 0
10205 11:39:36.578290 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10206 11:39:36.581993 [ 0.000000] Policy zone: Normal
10207 11:39:36.595214 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10208 11:39:36.604769 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10209 11:39:36.615628 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10210 11:39:36.625325 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10211 11:39:36.631789 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10212 11:39:36.635284 <6>[ 0.000000] software IO TLB: area num 8.
10213 11:39:36.691847 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10214 11:39:36.772204 <6>[ 0.000000] Memory: 3790084K/4191232K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 368380K reserved, 32768K cma-reserved)
10215 11:39:36.779352 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10216 11:39:36.785299 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10217 11:39:36.788819 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10218 11:39:36.795499 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10219 11:39:36.801895 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10220 11:39:36.805386 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10221 11:39:36.816046 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10222 11:39:36.821781 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10223 11:39:36.828114 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10224 11:39:36.834583 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10225 11:39:36.838249 <6>[ 0.000000] GICv3: 608 SPIs implemented
10226 11:39:36.841894 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10227 11:39:36.848384 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10228 11:39:36.851793 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10229 11:39:36.858425 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10230 11:39:36.871887 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10231 11:39:36.881549 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10232 11:39:36.891941 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10233 11:39:36.898451 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10234 11:39:36.912236 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10235 11:39:36.918587 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10236 11:39:36.924907 <6>[ 0.009174] Console: colour dummy device 80x25
10237 11:39:36.935935 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10238 11:39:36.942207 <6>[ 0.024438] pid_max: default: 32768 minimum: 301
10239 11:39:36.944480 <6>[ 0.029309] LSM: Security Framework initializing
10240 11:39:36.951120 <6>[ 0.034223] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10241 11:39:36.962017 <6>[ 0.041840] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10242 11:39:36.968385 <6>[ 0.051071] cblist_init_generic: Setting adjustable number of callback queues.
10243 11:39:36.975012 <6>[ 0.058512] cblist_init_generic: Setting shift to 3 and lim to 1.
10244 11:39:36.984890 <6>[ 0.064854] cblist_init_generic: Setting adjustable number of callback queues.
10245 11:39:36.988562 <6>[ 0.072281] cblist_init_generic: Setting shift to 3 and lim to 1.
10246 11:39:36.994530 <6>[ 0.078680] rcu: Hierarchical SRCU implementation.
10247 11:39:37.001407 <6>[ 0.083695] rcu: Max phase no-delay instances is 1000.
10248 11:39:37.007754 <6>[ 0.090742] EFI services will not be available.
10249 11:39:37.010807 <6>[ 0.095728] smp: Bringing up secondary CPUs ...
10250 11:39:37.019186 <6>[ 0.100779] Detected VIPT I-cache on CPU1
10251 11:39:37.026321 <6>[ 0.100850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10252 11:39:37.032308 <6>[ 0.100881] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10253 11:39:37.035504 <6>[ 0.101213] Detected VIPT I-cache on CPU2
10254 11:39:37.046154 <6>[ 0.101266] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10255 11:39:37.052123 <6>[ 0.101282] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10256 11:39:37.055911 <6>[ 0.101542] Detected VIPT I-cache on CPU3
10257 11:39:37.061652 <6>[ 0.101589] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10258 11:39:37.069086 <6>[ 0.101603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10259 11:39:37.072598 <6>[ 0.101908] CPU features: detected: Spectre-v4
10260 11:39:37.078887 <6>[ 0.101914] CPU features: detected: Spectre-BHB
10261 11:39:37.081619 <6>[ 0.101920] Detected PIPT I-cache on CPU4
10262 11:39:37.088129 <6>[ 0.101980] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10263 11:39:37.094706 <6>[ 0.101997] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10264 11:39:37.101465 <6>[ 0.102290] Detected PIPT I-cache on CPU5
10265 11:39:37.108173 <6>[ 0.102352] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10266 11:39:37.115134 <6>[ 0.102369] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10267 11:39:37.118401 <6>[ 0.102652] Detected PIPT I-cache on CPU6
10268 11:39:37.125626 <6>[ 0.102714] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10269 11:39:37.132425 <6>[ 0.102730] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10270 11:39:37.138026 <6>[ 0.103019] Detected PIPT I-cache on CPU7
10271 11:39:37.144722 <6>[ 0.103076] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10272 11:39:37.151379 <6>[ 0.103092] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10273 11:39:37.154568 <6>[ 0.103139] smp: Brought up 1 node, 8 CPUs
10274 11:39:37.161780 <6>[ 0.244508] SMP: Total of 8 processors activated.
10275 11:39:37.164688 <6>[ 0.249459] CPU features: detected: 32-bit EL0 Support
10276 11:39:37.174214 <6>[ 0.254822] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10277 11:39:37.181346 <6>[ 0.263623] CPU features: detected: Common not Private translations
10278 11:39:37.187296 <6>[ 0.270099] CPU features: detected: CRC32 instructions
10279 11:39:37.190734 <6>[ 0.275450] CPU features: detected: RCpc load-acquire (LDAPR)
10280 11:39:37.197191 <6>[ 0.281410] CPU features: detected: LSE atomic instructions
10281 11:39:37.204206 <6>[ 0.287192] CPU features: detected: Privileged Access Never
10282 11:39:37.210873 <6>[ 0.293001] CPU features: detected: RAS Extension Support
10283 11:39:37.217325 <6>[ 0.298609] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10284 11:39:37.220681 <6>[ 0.305873] CPU: All CPU(s) started at EL2
10285 11:39:37.227680 <6>[ 0.310190] alternatives: applying system-wide alternatives
10286 11:39:37.236114 <6>[ 0.320217] devtmpfs: initialized
10287 11:39:37.247409 <6>[ 0.328349] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10288 11:39:37.257639 <6>[ 0.338310] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10289 11:39:37.263911 <6>[ 0.346562] pinctrl core: initialized pinctrl subsystem
10290 11:39:37.267555 <6>[ 0.353297] DMI not present or invalid.
10291 11:39:37.274453 <6>[ 0.357696] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10292 11:39:37.283676 <6>[ 0.364561] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10293 11:39:37.290498 <6>[ 0.372007] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10294 11:39:37.300884 <6>[ 0.380098] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10295 11:39:37.304157 <6>[ 0.388256] audit: initializing netlink subsys (disabled)
10296 11:39:37.313461 <5>[ 0.393952] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10297 11:39:37.320721 <6>[ 0.394671] thermal_sys: Registered thermal governor 'step_wise'
10298 11:39:37.326717 <6>[ 0.401915] thermal_sys: Registered thermal governor 'power_allocator'
10299 11:39:37.330137 <6>[ 0.408169] cpuidle: using governor menu
10300 11:39:37.337001 <6>[ 0.419131] NET: Registered PF_QIPCRTR protocol family
10301 11:39:37.343411 <6>[ 0.424615] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10302 11:39:37.348510 <6>[ 0.431716] ASID allocator initialised with 32768 entries
10303 11:39:37.354203 <6>[ 0.438295] Serial: AMBA PL011 UART driver
10304 11:39:37.363919 <4>[ 0.448030] Trying to register duplicate clock ID: 134
10305 11:39:37.422519 <6>[ 0.509461] KASLR enabled
10306 11:39:37.436130 <6>[ 0.517118] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10307 11:39:37.442824 <6>[ 0.524131] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10308 11:39:37.450148 <6>[ 0.530620] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10309 11:39:37.456988 <6>[ 0.537626] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10310 11:39:37.463798 <6>[ 0.544110] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10311 11:39:37.469466 <6>[ 0.551112] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10312 11:39:37.475753 <6>[ 0.557596] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10313 11:39:37.482096 <6>[ 0.564599] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10314 11:39:37.486795 <6>[ 0.572120] ACPI: Interpreter disabled.
10315 11:39:37.494789 <6>[ 0.578548] iommu: Default domain type: Translated
10316 11:39:37.500881 <6>[ 0.583659] iommu: DMA domain TLB invalidation policy: strict mode
10317 11:39:37.504231 <5>[ 0.590307] SCSI subsystem initialized
10318 11:39:37.510857 <6>[ 0.594467] usbcore: registered new interface driver usbfs
10319 11:39:37.516961 <6>[ 0.600200] usbcore: registered new interface driver hub
10320 11:39:37.521105 <6>[ 0.605745] usbcore: registered new device driver usb
10321 11:39:37.528371 <6>[ 0.611848] pps_core: LinuxPPS API ver. 1 registered
10322 11:39:37.538125 <6>[ 0.617042] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10323 11:39:37.541407 <6>[ 0.626385] PTP clock support registered
10324 11:39:37.544158 <6>[ 0.630628] EDAC MC: Ver: 3.0.0
10325 11:39:37.551276 <6>[ 0.635799] FPGA manager framework
10326 11:39:37.557990 <6>[ 0.639478] Advanced Linux Sound Architecture Driver Initialized.
10327 11:39:37.561562 <6>[ 0.646266] vgaarb: loaded
10328 11:39:37.569397 <6>[ 0.649427] clocksource: Switched to clocksource arch_sys_counter
10329 11:39:37.571205 <5>[ 0.655854] VFS: Disk quotas dquot_6.6.0
10330 11:39:37.578099 <6>[ 0.660043] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10331 11:39:37.580984 <6>[ 0.667226] pnp: PnP ACPI: disabled
10332 11:39:37.590102 <6>[ 0.673902] NET: Registered PF_INET protocol family
10333 11:39:37.596549 <6>[ 0.679283] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10334 11:39:37.609105 <6>[ 0.689297] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10335 11:39:37.618373 <6>[ 0.698082] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10336 11:39:37.625596 <6>[ 0.706047] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10337 11:39:37.631602 <6>[ 0.714451] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10338 11:39:37.642725 <6>[ 0.723094] TCP: Hash tables configured (established 32768 bind 32768)
10339 11:39:37.649215 <6>[ 0.729950] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10340 11:39:37.656444 <6>[ 0.736973] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10341 11:39:37.662040 <6>[ 0.744491] NET: Registered PF_UNIX/PF_LOCAL protocol family
10342 11:39:37.668687 <6>[ 0.750647] RPC: Registered named UNIX socket transport module.
10343 11:39:37.671533 <6>[ 0.756802] RPC: Registered udp transport module.
10344 11:39:37.678340 <6>[ 0.761736] RPC: Registered tcp transport module.
10345 11:39:37.685394 <6>[ 0.766665] RPC: Registered tcp NFSv4.1 backchannel transport module.
10346 11:39:37.688517 <6>[ 0.773332] PCI: CLS 0 bytes, default 64
10347 11:39:37.692764 <6>[ 0.777725] Unpacking initramfs...
10348 11:39:37.701754 <6>[ 0.781409] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10349 11:39:37.708117 <6>[ 0.790037] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10350 11:39:37.714374 <6>[ 0.798889] kvm [1]: IPA Size Limit: 40 bits
10351 11:39:37.717868 <6>[ 0.803415] kvm [1]: GICv3: no GICV resource entry
10352 11:39:37.724811 <6>[ 0.808434] kvm [1]: disabling GICv2 emulation
10353 11:39:37.731718 <6>[ 0.813119] kvm [1]: GIC system register CPU interface enabled
10354 11:39:37.735648 <6>[ 0.819291] kvm [1]: vgic interrupt IRQ18
10355 11:39:37.740960 <6>[ 0.823651] kvm [1]: VHE mode initialized successfully
10356 11:39:37.744537 <5>[ 0.830062] Initialise system trusted keyrings
10357 11:39:37.751387 <6>[ 0.834914] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10358 11:39:37.760868 <6>[ 0.844912] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10359 11:39:37.767000 <5>[ 0.851306] NFS: Registering the id_resolver key type
10360 11:39:37.770308 <5>[ 0.856602] Key type id_resolver registered
10361 11:39:37.777043 <5>[ 0.861015] Key type id_legacy registered
10362 11:39:37.783625 <6>[ 0.865304] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10363 11:39:37.790254 <6>[ 0.872225] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10364 11:39:37.797029 <6>[ 0.879950] 9p: Installing v9fs 9p2000 file system support
10365 11:39:37.834367 <5>[ 0.918640] Key type asymmetric registered
10366 11:39:37.838421 <5>[ 0.922970] Asymmetric key parser 'x509' registered
10367 11:39:37.848026 <6>[ 0.928118] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10368 11:39:37.851192 <6>[ 0.935733] io scheduler mq-deadline registered
10369 11:39:37.853993 <6>[ 0.940495] io scheduler kyber registered
10370 11:39:37.872948 <6>[ 0.957611] EINJ: ACPI disabled.
10371 11:39:37.905751 <4>[ 0.983686] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10372 11:39:37.916733 <4>[ 0.994316] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10373 11:39:37.931477 <6>[ 1.015823] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10374 11:39:37.939523 <6>[ 1.023951] printk: console [ttyS0] disabled
10375 11:39:37.968248 <6>[ 1.048579] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10376 11:39:37.975631 <6>[ 1.058043] printk: console [ttyS0] enabled
10377 11:39:37.977948 <6>[ 1.058043] printk: console [ttyS0] enabled
10378 11:39:37.984649 <6>[ 1.066938] printk: bootconsole [mtk8250] disabled
10379 11:39:37.987576 <6>[ 1.066938] printk: bootconsole [mtk8250] disabled
10380 11:39:37.994131 <6>[ 1.078126] SuperH (H)SCI(F) driver initialized
10381 11:39:37.997343 <6>[ 1.083414] msm_serial: driver initialized
10382 11:39:38.011644 <6>[ 1.092395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10383 11:39:38.021751 <6>[ 1.100944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10384 11:39:38.028297 <6>[ 1.109491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10385 11:39:38.037795 <6>[ 1.118120] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10386 11:39:38.044717 <6>[ 1.126827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10387 11:39:38.054602 <6>[ 1.135542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10388 11:39:38.065388 <6>[ 1.144081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10389 11:39:38.071177 <6>[ 1.152887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10390 11:39:38.081151 <6>[ 1.161434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10391 11:39:38.093654 <6>[ 1.177441] loop: module loaded
10392 11:39:38.099553 <6>[ 1.183589] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10393 11:39:38.123883 <4>[ 1.206914] mtk-pmic-keys: Failed to locate of_node [id: -1]
10394 11:39:38.129724 <6>[ 1.213857] megasas: 07.719.03.00-rc1
10395 11:39:38.139350 <6>[ 1.223861] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10396 11:39:38.149051 <6>[ 1.232833] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10397 11:39:38.165186 <6>[ 1.249526] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10398 11:39:38.221631 <6>[ 1.299134] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10399 11:39:40.422458 <6>[ 3.506937] Freeing initrd memory: 59552K
10400 11:39:40.435078 <6>[ 3.518735] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10401 11:39:40.445085 <6>[ 3.529832] tun: Universal TUN/TAP device driver, 1.6
10402 11:39:40.448370 <6>[ 3.535900] thunder_xcv, ver 1.0
10403 11:39:40.451412 <6>[ 3.539406] thunder_bgx, ver 1.0
10404 11:39:40.454891 <6>[ 3.542904] nicpf, ver 1.0
10405 11:39:40.465590 <6>[ 3.546917] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10406 11:39:40.468996 <6>[ 3.554392] hns3: Copyright (c) 2017 Huawei Corporation.
10407 11:39:40.475091 <6>[ 3.559984] hclge is initializing
10408 11:39:40.478322 <6>[ 3.563563] e1000: Intel(R) PRO/1000 Network Driver
10409 11:39:40.485165 <6>[ 3.568693] e1000: Copyright (c) 1999-2006 Intel Corporation.
10410 11:39:40.488706 <6>[ 3.574707] e1000e: Intel(R) PRO/1000 Network Driver
10411 11:39:40.495936 <6>[ 3.579923] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10412 11:39:40.501902 <6>[ 3.586108] igb: Intel(R) Gigabit Ethernet Network Driver
10413 11:39:40.508900 <6>[ 3.591758] igb: Copyright (c) 2007-2014 Intel Corporation.
10414 11:39:40.515909 <6>[ 3.597598] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10415 11:39:40.521778 <6>[ 3.604117] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10416 11:39:40.524800 <6>[ 3.610578] sky2: driver version 1.30
10417 11:39:40.533868 <6>[ 3.615502] usbcore: registered new device driver r8152-cfgselector
10418 11:39:40.538915 <6>[ 3.622042] usbcore: registered new interface driver r8152
10419 11:39:40.545216 <6>[ 3.627857] VFIO - User Level meta-driver version: 0.3
10420 11:39:40.552040 <6>[ 3.636129] usbcore: registered new interface driver usb-storage
10421 11:39:40.558422 <6>[ 3.642574] usbcore: registered new device driver onboard-usb-hub
10422 11:39:40.567260 <6>[ 3.651718] mt6397-rtc mt6359-rtc: registered as rtc0
10423 11:39:40.577387 <6>[ 3.657182] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:39:40 UTC (1721216380)
10424 11:39:40.580221 <6>[ 3.666751] i2c_dev: i2c /dev entries driver
10425 11:39:40.594347 <4>[ 3.678859] cpu cpu0: supply cpu not found, using dummy regulator
10426 11:39:40.602073 <4>[ 3.685286] cpu cpu1: supply cpu not found, using dummy regulator
10427 11:39:40.607362 <4>[ 3.691692] cpu cpu2: supply cpu not found, using dummy regulator
10428 11:39:40.614174 <4>[ 3.698111] cpu cpu3: supply cpu not found, using dummy regulator
10429 11:39:40.621294 <4>[ 3.704512] cpu cpu4: supply cpu not found, using dummy regulator
10430 11:39:40.628432 <4>[ 3.710913] cpu cpu5: supply cpu not found, using dummy regulator
10431 11:39:40.634436 <4>[ 3.717309] cpu cpu6: supply cpu not found, using dummy regulator
10432 11:39:40.640734 <4>[ 3.723703] cpu cpu7: supply cpu not found, using dummy regulator
10433 11:39:40.659779 <6>[ 3.744340] cpu cpu0: EM: created perf domain
10434 11:39:40.662835 <6>[ 3.749241] cpu cpu4: EM: created perf domain
10435 11:39:40.670617 <6>[ 3.754825] sdhci: Secure Digital Host Controller Interface driver
10436 11:39:40.677395 <6>[ 3.761256] sdhci: Copyright(c) Pierre Ossman
10437 11:39:40.683987 <6>[ 3.766172] Synopsys Designware Multimedia Card Interface Driver
10438 11:39:40.690122 <6>[ 3.772760] sdhci-pltfm: SDHCI platform and OF driver helper
10439 11:39:40.692919 <6>[ 3.772843] mmc0: CQHCI version 5.10
10440 11:39:40.700053 <6>[ 3.783168] ledtrig-cpu: registered to indicate activity on CPUs
10441 11:39:40.706303 <6>[ 3.789984] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10442 11:39:40.713309 <6>[ 3.797010] usbcore: registered new interface driver usbhid
10443 11:39:40.716346 <6>[ 3.802831] usbhid: USB HID core driver
10444 11:39:40.722849 <6>[ 3.807026] spi_master spi0: will run message pump with realtime priority
10445 11:39:40.769435 <6>[ 3.847103] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10446 11:39:40.787991 <6>[ 3.862403] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10447 11:39:40.790985 <6>[ 3.871676] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10448 11:39:40.798194 <6>[ 3.882764] cros-ec-spi spi0.0: Chrome EC device registered
10449 11:39:40.806060 <6>[ 3.888808] mmc0: Command Queue Engine enabled
10450 11:39:40.811723 <6>[ 3.893576] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10451 11:39:40.814678 <6>[ 3.901283] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10452 11:39:40.825950 <6>[ 3.910424] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10453 11:39:40.833712 <6>[ 3.918286] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10454 11:39:40.843920 <6>[ 3.921556] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10455 11:39:40.846839 <6>[ 3.924176] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10456 11:39:40.854166 <6>[ 3.933880] NET: Registered PF_PACKET protocol family
10457 11:39:40.860195 <6>[ 3.938735] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10458 11:39:40.863422 <6>[ 3.943398] 9pnet: Installing 9P2000 support
10459 11:39:40.869945 <5>[ 3.954414] Key type dns_resolver registered
10460 11:39:40.873845 <6>[ 3.959391] registered taskstats version 1
10461 11:39:40.880299 <5>[ 3.963768] Loading compiled-in X.509 certificates
10462 11:39:40.908073 <4>[ 3.985659] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10463 11:39:40.917433 <4>[ 3.996421] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10464 11:39:40.934442 <6>[ 4.018470] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10465 11:39:40.940873 <6>[ 4.025300] xhci-mtk 11200000.usb: xHCI Host Controller
10466 11:39:40.949140 <6>[ 4.030827] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10467 11:39:40.957695 <6>[ 4.038681] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10468 11:39:40.964480 <6>[ 4.048115] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10469 11:39:40.971352 <6>[ 4.054284] xhci-mtk 11200000.usb: xHCI Host Controller
10470 11:39:40.977577 <6>[ 4.059775] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10471 11:39:40.984346 <6>[ 4.067430] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10472 11:39:40.992450 <6>[ 4.075127] hub 1-0:1.0: USB hub found
10473 11:39:40.994218 <6>[ 4.079141] hub 1-0:1.0: 1 port detected
10474 11:39:41.003970 <6>[ 4.083396] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10475 11:39:41.008135 <6>[ 4.092064] hub 2-0:1.0: USB hub found
10476 11:39:41.010766 <6>[ 4.096081] hub 2-0:1.0: 1 port detected
10477 11:39:41.019439 <6>[ 4.102941] mtk-msdc 11f70000.mmc: Got CD GPIO
10478 11:39:41.034255 <6>[ 4.115536] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10479 11:39:41.044478 <6>[ 4.123915] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10480 11:39:41.050840 <6>[ 4.132255] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10481 11:39:41.060824 <6>[ 4.140595] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10482 11:39:41.067014 <6>[ 4.148933] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10483 11:39:41.078324 <6>[ 4.157273] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10484 11:39:41.084621 <6>[ 4.165612] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10485 11:39:41.093914 <6>[ 4.173950] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10486 11:39:41.100797 <6>[ 4.182288] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10487 11:39:41.109895 <6>[ 4.190626] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10488 11:39:41.117572 <6>[ 4.198964] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10489 11:39:41.127262 <6>[ 4.207310] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10490 11:39:41.133036 <6>[ 4.215648] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10491 11:39:41.143445 <6>[ 4.223987] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10492 11:39:41.149907 <6>[ 4.232326] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10493 11:39:41.158114 <6>[ 4.240994] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10494 11:39:41.163599 <6>[ 4.248098] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10495 11:39:41.170442 <6>[ 4.254877] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10496 11:39:41.180818 <6>[ 4.261623] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10497 11:39:41.186724 <6>[ 4.268523] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10498 11:39:41.193665 <6>[ 4.275415] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10499 11:39:41.203760 <6>[ 4.284548] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10500 11:39:41.213893 <6>[ 4.293670] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10501 11:39:41.223536 <6>[ 4.302964] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10502 11:39:41.233305 <6>[ 4.312430] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10503 11:39:41.242814 <6>[ 4.321898] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10504 11:39:41.249664 <6>[ 4.331018] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10505 11:39:41.259540 <6>[ 4.340483] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10506 11:39:41.269575 <6>[ 4.349602] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10507 11:39:41.279290 <6>[ 4.358900] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10508 11:39:41.289191 <6>[ 4.369060] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10509 11:39:41.299899 <6>[ 4.380771] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10510 11:39:41.424576 <6>[ 4.505703] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10511 11:39:41.579760 <6>[ 4.663570] hub 1-1:1.0: USB hub found
10512 11:39:41.581998 <6>[ 4.668102] hub 1-1:1.0: 4 ports detected
10513 11:39:41.593741 <6>[ 4.678713] hub 1-1:1.0: USB hub found
10514 11:39:41.597269 <6>[ 4.683015] hub 1-1:1.0: 4 ports detected
10515 11:39:41.705095 <6>[ 4.785929] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10516 11:39:41.729978 <6>[ 4.814593] hub 2-1:1.0: USB hub found
10517 11:39:41.733050 <6>[ 4.819039] hub 2-1:1.0: 3 ports detected
10518 11:39:41.743825 <6>[ 4.828634] hub 2-1:1.0: USB hub found
10519 11:39:41.746980 <6>[ 4.832998] hub 2-1:1.0: 3 ports detected
10520 11:39:41.920386 <6>[ 5.001737] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10521 11:39:42.052459 <6>[ 5.137337] hub 1-1.4:1.0: USB hub found
10522 11:39:42.057780 <6>[ 5.142003] hub 1-1.4:1.0: 2 ports detected
10523 11:39:42.070027 <6>[ 5.154941] hub 1-1.4:1.0: USB hub found
10524 11:39:42.073610 <6>[ 5.159544] hub 1-1.4:1.0: 2 ports detected
10525 11:39:42.132098 <6>[ 5.213949] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10526 11:39:42.241010 <6>[ 5.322367] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10527 11:39:42.276306 <4>[ 5.357734] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10528 11:39:42.286073 <4>[ 5.366824] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10529 11:39:42.331055 <6>[ 5.415264] r8152 2-1.3:1.0 eth0: v1.12.13
10530 11:39:42.372553 <6>[ 5.453523] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10531 11:39:42.560410 <6>[ 5.641707] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10532 11:39:43.938824 <6>[ 7.023680] r8152 2-1.3:1.0 eth0: carrier on
10533 11:39:46.799884 <5>[ 7.045543] Sending DHCP requests .., OK
10534 11:39:46.806623 <6>[ 9.889934] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10535 11:39:46.810049 <6>[ 9.898228] IP-Config: Complete:
10536 11:39:46.825057 <6>[ 9.901723] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10537 11:39:46.830179 <6>[ 9.912431] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10538 11:39:46.836411 <6>[ 9.921048] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10539 11:39:46.843691 <6>[ 9.921057] nameserver0=192.168.201.1
10540 11:39:46.847825 <6>[ 9.933188] clk: Disabling unused clocks
10541 11:39:46.850276 <6>[ 9.938929] ALSA device list:
10542 11:39:46.856774 <6>[ 9.942170] No soundcards found.
10543 11:39:46.864181 <6>[ 9.949669] Freeing unused kernel memory: 8512K
10544 11:39:46.867510 <6>[ 9.954562] Run /init as init process
10545 11:39:46.897517 <6>[ 9.982976] NET: Registered PF_INET6 protocol family
10546 11:39:46.904108 <6>[ 9.989520] Segment Routing with IPv6
10547 11:39:46.907265 <6>[ 9.993452] In-situ OAM (IOAM) with IPv6
10548 11:39:46.948662 <30>[ 10.007597] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10549 11:39:46.955249 <30>[ 10.040663] systemd[1]: Detected architecture arm64.
10550 11:39:46.955882
10551 11:39:46.962140 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10552 11:39:46.962523
10553 11:39:46.980642 <30>[ 10.065808] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10554 11:39:47.116482 <30>[ 10.198383] systemd[1]: Queued start job for default target graphical.target.
10555 11:39:47.161671 <30>[ 10.243658] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10556 11:39:47.168359 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10557 11:39:47.187663 <30>[ 10.270024] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10558 11:39:47.197677 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10559 11:39:47.216640 <30>[ 10.298717] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10560 11:39:47.226950 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10561 11:39:47.244867 <30>[ 10.326896] systemd[1]: Created slice user.slice - User and Session Slice.
10562 11:39:47.251496 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10563 11:39:47.270660 <30>[ 10.349741] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10564 11:39:47.278293 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10565 11:39:47.299453 <30>[ 10.378223] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10566 11:39:47.306099 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10567 11:39:47.333409 <30>[ 10.405814] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10568 11:39:47.343706 <30>[ 10.425631] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10569 11:39:47.350174 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10570 11:39:47.368412 <30>[ 10.450058] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10571 11:39:47.377839 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10572 11:39:47.391512 <30>[ 10.473806] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10573 11:39:47.401935 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10574 11:39:47.416608 <30>[ 10.502239] systemd[1]: Reached target paths.target - Path Units.
10575 11:39:47.427070 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10576 11:39:47.444595 <30>[ 10.526155] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10577 11:39:47.450699 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10578 11:39:47.464745 <30>[ 10.549710] systemd[1]: Reached target slices.target - Slice Units.
10579 11:39:47.475689 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10580 11:39:47.489764 <30>[ 10.574099] systemd[1]: Reached target swap.target - Swaps.
10581 11:39:47.495212 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10582 11:39:47.515895 <30>[ 10.597838] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10583 11:39:47.526503 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10584 11:39:47.544625 <30>[ 10.626743] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10585 11:39:47.555542 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10586 11:39:47.574089 <30>[ 10.655373] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10587 11:39:47.583115 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10588 11:39:47.600703 <30>[ 10.682332] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10589 11:39:47.609814 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10590 11:39:47.628640 <30>[ 10.710337] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10591 11:39:47.634743 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10592 11:39:47.652470 <30>[ 10.734479] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10593 11:39:47.662108 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10594 11:39:47.680267 <30>[ 10.762218] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10595 11:39:47.689930 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10596 11:39:47.744817 <30>[ 10.825916] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10597 11:39:47.750900 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10598 11:39:47.763463 <30>[ 10.845371] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10599 11:39:47.770002 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10600 11:39:47.791624 <30>[ 10.873588] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10601 11:39:47.798120 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10602 11:39:47.822622 <30>[ 10.897975] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10603 11:39:47.855713 <30>[ 10.938045] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10604 11:39:47.865996 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10605 11:39:47.888970 <30>[ 10.970612] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10606 11:39:47.895495 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10607 11:39:47.920905 <30>[ 11.002785] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10608 11:39:47.934089 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 11.016726] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10609 11:39:47.937748 Module dm_mod...
10610 11:39:47.960287 <30>[ 11.042668] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10611 11:39:47.966695 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10612 11:39:48.028650 <30>[ 11.110287] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10613 11:39:48.038505 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10614 11:39:48.065001 <30>[ 11.146721] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10615 11:39:48.071547 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10616 11:39:48.120703 <30>[ 11.202035] systemd[1]: Starting systemd-journald.service - Journal Service...
10617 11:39:48.126453 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10618 11:39:48.146978 <30>[ 11.228725] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10619 11:39:48.153196 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10620 11:39:48.183907 <30>[ 11.262825] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10621 11:39:48.191070 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10622 11:39:48.209993 <30>[ 11.292546] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10623 11:39:48.220256 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10624 11:39:48.242355 <30>[ 11.324494] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10625 11:39:48.252001 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10626 11:39:48.273721 <30>[ 11.355493] systemd[1]: Started systemd-journald.service - Journal Service.
10627 11:39:48.280091 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10628 11:39:48.302764 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10629 11:39:48.320500 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10630 11:39:48.341341 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10631 11:39:48.360361 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10632 11:39:48.381156 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10633 11:39:48.403191 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10634 11:39:48.422873 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10635 11:39:48.443397 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10636 11:39:48.466966 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10637 11:39:48.489889 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10638 11:39:48.512981 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10639 11:39:48.538299 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10640 11:39:48.553019 See 'systemctl status systemd-remount-fs.service' for details.
10641 11:39:48.563773 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10642 11:39:48.582902 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10643 11:39:48.632729 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10644 11:39:48.652353 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10645 11:39:48.676077 Starting [0;1;39msyste<46>[ 11.756380] systemd-journald[190]: Received client request to flush runtime journal.
10646 11:39:48.679192 md-random-se…ice[0m - Load/Save Random Seed...
10647 11:39:48.705142 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10648 11:39:48.728524 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10649 11:39:48.753408 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10650 11:39:48.772714 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10651 11:39:48.793154 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10652 11:39:48.812717 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10653 11:39:48.832844 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10654 11:39:48.888549 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10655 11:39:48.911289 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10656 11:39:48.928511 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10657 11:39:48.947021 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10658 11:39:49.000558 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10659 11:39:49.020642 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10660 11:39:49.043617 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10661 11:39:49.062974 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10662 11:39:49.115604 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10663 11:39:49.264514 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10664 11:39:49.290359 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10665 11:39:49.335786 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10666 11:39:49.354075 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10667 11:39:49.374534 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10668 11:39:49.393397 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10669 11:39:49.418360 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<6>[ 12.501187] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10670 11:39:49.418860 t.
10671 11:39:49.434153 [[0;32m OK [0m] Started [0;<6>[ 12.515182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10672 11:39:49.444878 1;39mfstrim.time<6>[ 12.524112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10673 11:39:49.453936 r[0m - Discard <4>[ 12.533476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10674 11:39:49.464073 unused blocks on<6>[ 12.544691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10675 11:39:49.464631 ce a week.
10676 11:39:49.469999 <6>[ 12.553150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 11:39:49.481307 [[0;32m OK [<3>[ 12.564225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 11:39:49.490757 0m] Reached targ<3>[ 12.573044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:39:49.500994 et [0;1;39mtime<6>[ 12.578195] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10680 11:39:49.507009 <6>[ 12.578426] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 11:39:49.517302 <6>[ 12.579449] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10682 11:39:49.527450 rs.target[0m - <6>[ 12.579497] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10683 11:39:49.533608 <6>[ 12.579511] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10684 11:39:49.537017 Timer Units.
10685 11:39:49.543734 <3>[ 12.582576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 11:39:49.553487 <6>[ 12.591759] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10687 11:39:49.562238 <3>[ 12.609570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:39:49.567495 <6>[ 12.616680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10689 11:39:49.576979 <6>[ 12.616688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10690 11:39:49.583403 <6>[ 12.617626] remoteproc remoteproc0: scp is available
10691 11:39:49.590586 <3>[ 12.625435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 11:39:49.600318 <3>[ 12.625442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 11:39:49.606061 <3>[ 12.625456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 11:39:49.616494 <3>[ 12.625464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 11:39:49.622805 <3>[ 12.636746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 11:39:49.630156 <6>[ 12.643418] remoteproc remoteproc0: powering up scp
10697 11:39:49.636077 <3>[ 12.651512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:39:49.639523 <6>[ 12.653526] mc: Linux media interface: v0.10
10699 11:39:49.649099 <6>[ 12.658842] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10700 11:39:49.656015 <3>[ 12.667936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 11:39:49.662567 <6>[ 12.673382] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10702 11:39:49.669450 <4>[ 12.673915] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10703 11:39:49.679209 <3>[ 12.681181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 11:39:49.687106 <3>[ 12.691168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 11:39:49.692922 <4>[ 12.691225] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10706 11:39:49.699311 <6>[ 12.704195] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10707 11:39:49.710187 <3>[ 12.705458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 11:39:49.716804 <3>[ 12.705462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 11:39:49.723500 <6>[ 12.713664] pci_bus 0000:00: root bus resource [bus 00-ff]
10710 11:39:49.729849 <3>[ 12.718679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 11:39:49.739589 <3>[ 12.718682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 11:39:49.746084 <6>[ 12.750581] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 11:39:49.752975 <6>[ 12.753487] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10714 11:39:49.759374 <6>[ 12.753993] videodev: Linux video capture interface: v2.00
10715 11:39:49.766204 <3>[ 12.770101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 11:39:49.776332 <4>[ 12.775521] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10717 11:39:49.782874 <4>[ 12.775521] Fallback method does not support PEC.
10718 11:39:49.793043 <6>[ 12.778442] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10719 11:39:49.799757 <6>[ 12.799928] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10720 11:39:49.805915 <6>[ 12.808255] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10721 11:39:49.816103 <6>[ 12.810543] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10722 11:39:49.825756 <6>[ 12.810955] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10723 11:39:49.835852 <3>[ 12.813961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 11:39:49.842272 <6>[ 12.822573] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10725 11:39:49.849069 <6>[ 12.822581] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10726 11:39:49.856270 <6>[ 12.822774] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10727 11:39:49.863968 <6>[ 12.822854] pci 0000:00:00.0: supports D1 D2
10728 11:39:49.869656 <6>[ 12.822856] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 11:39:49.878104 <6>[ 12.823862] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10730 11:39:49.884023 <6>[ 12.823965] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10731 11:39:49.890579 <6>[ 12.823991] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10732 11:39:49.900959 <6>[ 12.824008] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10733 11:39:49.907577 <6>[ 12.824023] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10734 11:39:49.911805 <6>[ 12.824129] pci 0000:01:00.0: supports D1 D2
10735 11:39:49.917831 <6>[ 12.824130] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 11:39:49.924409 <6>[ 12.831619] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10737 11:39:49.931173 <6>[ 12.837040] remoteproc remoteproc0: remote processor scp is now up
10738 11:39:49.941769 <6>[ 12.837492] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10739 11:39:49.944755 <6>[ 12.872741] Bluetooth: Core ver 2.22
10740 11:39:49.951420 <6>[ 12.882143] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10741 11:39:49.958086 <6>[ 12.882150] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10742 11:39:49.965196 <6>[ 12.882158] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10743 11:39:49.975547 <6>[ 12.882169] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10744 11:39:49.981985 <6>[ 12.882182] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10745 11:39:49.989630 <6>[ 12.882195] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10746 11:39:49.995458 <6>[ 12.882206] pci 0000:00:00.0: PCI bridge to [bus 01]
10747 11:39:50.002104 <6>[ 12.882213] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10748 11:39:50.008850 <6>[ 12.882505] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10749 11:39:50.015738 <6>[ 12.884996] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10750 11:39:50.022223 <6>[ 12.885243] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10751 11:39:50.028990 <6>[ 12.885956] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10752 11:39:50.035603 <6>[ 12.891414] NET: Registered PF_BLUETOOTH protocol family
10753 11:39:50.042925 <6>[ 12.898887] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10754 11:39:50.056140 <6>[ 12.899890] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 11:39:50.059881 <6>[ 12.900004] usbcore: registered new interface driver uvcvideo
10756 11:39:50.065835 <6>[ 12.907681] Bluetooth: HCI device and connection manager initialized
10757 11:39:50.072985 <6>[ 12.907708] Bluetooth: HCI socket layer initialized
10758 11:39:50.078964 <6>[ 12.907715] Bluetooth: L2CAP socket layer initialized
10759 11:39:50.086514 <5>[ 12.918061] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 11:39:50.092623 <6>[ 12.925538] Bluetooth: SCO socket layer initialized
10761 11:39:50.099964 <5>[ 12.945861] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10762 11:39:50.106515 <3>[ 12.948421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 11:39:50.115148 <3>[ 12.949214] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10764 11:39:50.125927 <5>[ 12.953579] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10765 11:39:50.132108 <3>[ 12.968458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 11:39:50.142189 <4>[ 12.974714] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10767 11:39:50.151761 <3>[ 13.001460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10768 11:39:50.154992 <6>[ 13.001609] cfg80211: failed to load regulatory.db
10769 11:39:50.162408 <6>[ 13.002149] usbcore: registered new interface driver btusb
10770 11:39:50.171330 <4>[ 13.008999] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 11:39:50.182060 <3>[ 13.045489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10772 11:39:50.185999 <3>[ 13.049112] Bluetooth: hci0: Failed to load firmware file (-2)
10773 11:39:50.195452 <6>[ 13.067705] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 11:39:50.198699 <3>[ 13.073085] Bluetooth: hci0: Failed to set up firmware (-2)
10775 11:39:50.211830 <4>[ 13.073089] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10776 11:39:50.218482 <3>[ 13.078076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10777 11:39:50.225312 <6>[ 13.081160] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10778 11:39:50.235488 <3>[ 13.098417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 11:39:50.238261 <6>[ 13.117628] mt7921e 0000:01:00.0: ASIC revision: 79610010
10780 11:39:50.248227 <3>[ 13.142472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10781 11:39:50.257926 <6>[ 13.241547] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10782 11:39:50.258419 <6>[ 13.241547]
10783 11:39:50.267930 <3>[ 13.275032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 11:39:50.274802 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10785 11:39:50.291055 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10786 11:39:50.310061 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10787 11:39:50.363221 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10788 11:39:50.391378 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10789 11:39:50.421937 <46>[ 13.491682] systemd-journald[190]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
10790 11:39:50.439448 <46>[ 13.513008] systemd-journald[190]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
10791 11:39:50.446210 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10792 11:39:50.467031 <6>[ 13.548926] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10793 11:39:50.476192 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10794 11:39:50.497735 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10795 11:39:50.549070 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10796 11:39:50.572455 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10797 11:39:50.588633 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10798 11:39:50.608329 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10799 11:39:50.664105 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10800 11:39:50.685186 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10801 11:39:50.705008 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10802 11:39:50.719535 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10803 11:39:50.739037 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10804 11:39:50.791905 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10805 11:39:50.815885 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10806 11:39:50.841761 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10807 11:39:50.907720 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10808 11:39:50.927410 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10809 11:39:50.952288 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10810 11:39:50.992745
10811 11:39:50.996782 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10812 11:39:50.997345
10813 11:39:50.999666 debian-bookworm-arm64 login: root (automatic login)
10814 11:39:51.000173
10815 11:39:51.011027 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
10816 11:39:51.011459
10817 11:39:51.017727 The programs included with the Debian GNU/Linux system are free software;
10818 11:39:51.024666 the exact distribution terms for each program are described in the
10819 11:39:51.028011 individual files in /usr/share/doc/*/copyright.
10820 11:39:51.028539
10821 11:39:51.034224 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10822 11:39:51.037109 permitted by applicable law.
10823 11:39:51.038593 Matched prompt #10: / #
10825 11:39:51.039597 Setting prompt string to ['/ #']
10826 11:39:51.040038 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10828 11:39:51.041003 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
10829 11:39:51.041484 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10830 11:39:51.041818 Setting prompt string to ['/ #']
10831 11:39:51.042133 Forcing a shell prompt, looking for ['/ #']
10832 11:39:51.042439 Sending line: ''
10834 11:39:51.093615 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10835 11:39:51.093993 Waiting using forced prompt support (timeout 00:02:30)
10836 11:39:51.100268 / #
10837 11:39:51.101157 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10838 11:39:51.101725 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
10839 11:39:51.102223 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10840 11:39:51.102653 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
10841 11:39:51.103098 end: 2 depthcharge-action (duration 00:01:41) [common]
10842 11:39:51.103543 start: 3 lava-test-retry (timeout 00:07:55) [common]
10843 11:39:51.103994 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10844 11:39:51.104352 Using namespace: common
10845 11:39:51.104699 Sending line: '#'
10847 11:39:51.206147 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10848 11:39:51.212367 / # #
10849 11:39:51.213081 Using /lava-14864651
10850 11:39:51.213456 Sending line: 'export SHELL=/bin/sh'
10852 11:39:51.318257 / # export SHELL=/bin/sh<6>[ 14.404262] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10853 11:39:51.318689
10854 11:39:51.322531 Sending line: '. /lava-14864651/environment'
10856 11:39:51.429916 / # . /lava-14864651/environment
10857 11:39:51.430647 Sending line: '/lava-14864651/bin/lava-test-runner /lava-14864651/0'
10859 11:39:51.532074 Test shell timeout: 10s (minimum of the action and connection timeout)
10860 11:39:51.537767 / # /lava-14864651/bin/lava-test-runner /lava-14864651/0
10861 11:39:51.563620 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 14.648435] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14864651_1.5.2.3.1>
10862 11:39:51.564416 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14864651_1.5.2.3.1
10863 11:39:51.564796 Starting test lava.0_igt-gpu-panfrost (14864651_1.5.2.3.1)
10864 11:39:51.565193 Skipping test definition patterns.
10865 11:39:51.566396 rost
10866 11:39:51.570470 + cd /lava-14864651/0/tests/0_igt-gpu-panfrost
10867 11:39:51.571016 + cat uuid
10868 11:39:51.573790 + UUID=14864651_1.5.2.3.1
10869 11:39:51.574219 + set +x
10870 11:39:51.587499 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param pa<8>[ 14.672628] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10871 11:39:51.588225 Received signal: <TESTSET> START panfrost_gem_new
10872 11:39:51.588814 Starting test_set panfrost_gem_new
10873 11:39:51.590690 nfrost_prime panfrost_submit
10874 11:39:51.605011 <14>[ 14.691030] [IGT] panfrost_gem_new: executing
10875 11:39:51.611378 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.698119] [IGT] panfrost_gem_new: exiting, ret=77
10876 11:39:51.614888 h64) (Linux: 6.1.96-cip24 aarch64)
10877 11:39:51.624884 Using IGT_SRANDOM=1721216391<8>[ 14.708351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10878 11:39:51.625800 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10880 11:39:51.628199 for randomisation
10881 11:39:51.635005 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10882 11:39:51.637685 Test requirement: !(fd<0)
10883 11:39:51.644349 No known gpu fo<14>[ 14.728633] [IGT] panfrost_gem_new: executing
10884 11:39:51.650999 und for chipset flags 0x32 (panf<14>[ 14.735657] [IGT] panfrost_gem_new: exiting, ret=77
10885 11:39:51.651387 rost)
10886 11:39:51.654578 Last errno: 2, No such file or directory
10887 11:39:51.664894 [1mSubtest gem<8>[ 14.747490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10888 11:39:51.665370 -new-4096: SKIP (0.000s)[0m
10889 11:39:51.665967 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10891 11:39:51.670914 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10892 11:39:51.678097 Using IGT_SRANDOM=1721216391 for randomisation
10893 11:39:51.680695 Test requireme<14>[ 14.767271] [IGT] panfrost_gem_new: executing
10894 11:39:51.693540 nt not met in function drm_open_<14>[ 14.774813] [IGT] panfrost_gem_new: exiting, ret=77
10895 11:39:51.694580 driver, file ../lib/drmtest.c:694:
10896 11:39:51.695004 Test requirement: !(fd<0)
10897 11:39:51.704213 No known gpu foun<8>[ 14.786679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10898 11:39:51.704983 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10900 11:39:51.710968 d for chipset flags 0x32 (panfro<8>[ 14.796678] <LAVA_SIGNAL_TESTSET STOP>
10901 11:39:51.711398 st)
10902 11:39:51.711964 Received signal: <TESTSET> STOP
10903 11:39:51.712308 Closing test_set panfrost_gem_new
10904 11:39:51.713899 Last errno: 2, No such file or directory
10905 11:39:51.717717 [1mSubtest gem-new-0: SKIP (0.000s)[0m
10906 11:39:51.724517 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10907 11:39:51.731062 Using IGT_SRANDOM=1<8>[ 14.816752] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10908 11:39:51.731733 Received signal: <TESTSET> START panfrost_get_param
10909 11:39:51.732097 Starting test_set panfrost_get_param
10910 11:39:51.733828 721216391 for randomisation
10911 11:39:51.741644 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10912 11:39:51.744178 Test requirement: !(fd<0)
10913 11:39:51.747197 No known gpu found for chipset flags 0x32 (panfrost)
10914 11:39:51.754041 Last errno: 2, N<14>[ 14.840473] [IGT] panfrost_get_param: executing
10915 11:39:51.756991 o such file or directory
10916 11:39:51.764046 [1mSu<14>[ 14.848185] [IGT] panfrost_get_param: exiting, ret=77
10917 11:39:51.767367 btest gem-new-zeroed: SKIP (0.000s)[0m
10918 11:39:51.777324 IGT-Version: 1.28-ga44e<8>[ 14.858665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10919 11:39:51.778104 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10921 11:39:51.780235 bfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10922 11:39:51.784107 Using IGT_SRANDOM=1721216391 for randomisation
10923 11:39:51.795390 Test requirement not met in function drm_open_drive<14>[ 14.879263] [IGT] panfrost_get_param: executing
10924 11:39:51.796827 r, file ../lib/drmtest.c:694:
10925 11:39:51.800512 T<14>[ 14.886131] [IGT] panfrost_get_param: exiting, ret=77
10926 11:39:51.803591 est requirement: !(fd<0)
10927 11:39:51.809812 No known gpu found for chipset flags 0x32 (panfrost)
10928 11:39:51.817792 <8>[ 14.898928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10929 11:39:51.818158 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10931 11:39:51.819894 Last errno: 2, No such file or directory
10932 11:39:51.823354 [1mSubtest base-params: SKIP (0.000s)[0m
10933 11:39:51.829757 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10934 11:39:51.833161 Using <14>[ 14.919186] [IGT] panfrost_get_param: executing
10935 11:39:51.842602 IGT_SRANDOM=1721216391 for rando<14>[ 14.927029] [IGT] panfrost_get_param: exiting, ret=77
10936 11:39:51.842818 misation
10937 11:39:51.856712 Test requirement not met in function drm_open_driver, file ../lib/drmt<8>[ 14.939287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10938 11:39:51.857005 est.c:694:
10939 11:39:51.857495 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10941 11:39:51.862642 Test requirement: !(<8>[ 14.949535] <LAVA_SIGNAL_TESTSET STOP>
10942 11:39:51.862996 fd<0)
10943 11:39:51.863495 Received signal: <TESTSET> STOP
10944 11:39:51.863765 Closing test_set panfrost_get_param
10945 11:39:51.869343 No known gpu found for chipset flags 0x32 (panfrost)
10946 11:39:51.872557 Last errno: 2, No such file or directory
10947 11:39:51.875888 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10948 11:39:51.882735 IGT-Version: 1.28-ga44ebfe <8>[ 14.969297] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10949 11:39:51.883353 Received signal: <TESTSET> START panfrost_prime
10950 11:39:51.883666 Starting test_set panfrost_prime
10951 11:39:51.889495 (aarch64) (Linux: 6.1.96-cip24 aarch64)
10952 11:39:51.892755 Using IGT_SRANDOM=1721216391 for randomisation
10953 11:39:51.899976 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10954 11:39:51.903221 Test requirement: !(fd<0)
10955 11:39:51.905996 No known g<14>[ 14.992186] [IGT] panfrost_prime: executing
10956 11:39:51.916375 pu found for chipset flags 0x32 <14>[ 15.000033] [IGT] panfrost_prime: exiting, ret=77
10957 11:39:51.916764 (panfrost)
10958 11:39:51.919350 Last errno: 2, No such file or directory
10959 11:39:51.929346 [1mSubtes<8>[ 15.010221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10960 11:39:51.930138 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10962 11:39:51.936103 t get-bad-padding: SKIP (0.000s)<8>[ 15.020257] <LAVA_SIGNAL_TESTSET STOP>
10963 11:39:51.936608 [0m
10964 11:39:51.937186 Received signal: <TESTSET> STOP
10965 11:39:51.937557 Closing test_set panfrost_prime
10966 11:39:51.942526 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10967 11:39:51.946976 Using IGT_SRANDOM=1721216391 for randomisation
10968 11:39:51.955889 Test requirement not met in function drm_open_driver, <8>[ 15.040229] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10969 11:39:51.956651 Received signal: <TESTSET> START panfrost_submit
10970 11:39:51.957018 Starting test_set panfrost_submit
10971 11:39:51.959239 file ../lib/drmtest.c:694:
10972 11:39:51.959756 Test requirement: !(fd<0)
10973 11:39:51.965183 No known gpu found for chipset flags 0x32 (panfrost)
10974 11:39:51.969455 Last errno: 2, No such file or directory
10975 11:39:51.975749 [1mSubtest gem-prime-import: SKIP (0.000<14>[ 15.063082] [IGT] panfrost_submit: executing
10976 11:39:51.979142 s)[0m
10977 11:39:51.985810 IGT-Version: 1.2<14>[ 15.069845] [IGT] panfrost_submit: exiting, ret=77
10978 11:39:51.988411 8-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10979 11:39:51.995528 Using IGT_SR<8>[ 15.079505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10980 11:39:51.996363 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10982 11:39:51.999373 ANDOM=1721216391 for randomisation
10983 11:39:52.008384 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10984 11:39:52.008894 Test requirement: !(fd<0)
10985 11:39:52.014773 No known gpu fo<14>[ 15.100142] [IGT] panfrost_submit: executing
10986 11:39:52.021812 und for chipset flags 0x32 (panf<14>[ 15.108078] [IGT] panfrost_submit: exiting, ret=77
10987 11:39:52.025178 rost)
10988 11:39:52.028120 Last errno: 2, No such file or directory
10989 11:39:52.034840 [1mSubtest pan<8>[ 15.119619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10990 11:39:52.035515 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10992 11:39:52.038684 -submit: SKIP (0.000s)[0m
10993 11:39:52.045177 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
10994 11:39:52.048235 Using IGT_SRANDOM=1721216391 for randomisation
10995 11:39:52.055009 <14>[ 15.139972] [IGT] panfrost_submit: executing
10996 11:39:52.061439 Test requirement not met in func<14>[ 15.146416] [IGT] panfrost_submit: exiting, ret=77
10997 11:39:52.065682 tion drm_open_driver, file ../lib/drmtest.c:694:
10998 11:39:52.075685 Test requireme<8>[ 15.158275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10999 11:39:52.076466 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11001 11:39:52.078097 nt: !(fd<0)
11002 11:39:52.081375 No known gpu found for chipset flags 0x32 (panfrost)
11003 11:39:52.084874 Last errno: 2, No such file or directory
11004 11:39:52.094364 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[<14>[ 15.179510] [IGT] panfrost_submit: executing
11005 11:39:52.094868 0m
11006 11:39:52.101538 IGT-Version: 1.28-ga44ebfe (<14>[ 15.187097] [IGT] panfrost_submit: exiting, ret=77
11007 11:39:52.104498 aarch64) (Linux: 6.1.96-cip24 aarch64)
11008 11:39:52.117215 Using IGT_SRANDOM=172121<8>[ 15.198783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11009 11:39:52.117740 6391 for randomisation
11010 11:39:52.118341 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11012 11:39:52.127251 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11013 11:39:52.127682 Test requirement: !(fd<0)
11014 11:39:52.133846 No known gpu found for chip<14>[ 15.220219] [IGT] panfrost_submit: executing
11015 11:39:52.137630 set flags 0x32 (panfrost)
11016 11:39:52.143878 Last <14>[ 15.228104] [IGT] panfrost_submit: exiting, ret=77
11017 11:39:52.147517 errno: 2, No such file or directory
11018 11:39:52.157115 [1mSubtest pan-submit-erro<8>[ 15.239570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11019 11:39:52.157879 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11021 11:39:52.160253 r-bad-in-syncs: SKIP (0.000s)[0m
11022 11:39:52.166955 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11023 11:39:52.173283 Using IGT_SRANDOM=1721216392 for randomis<14>[ 15.260801] [IGT] panfrost_submit: executing
11024 11:39:52.173782 ation
11025 11:39:52.184092 Test requirement not met <14>[ 15.267582] [IGT] panfrost_submit: exiting, ret=77
11026 11:39:52.187157 in function drm_open_driver, file ../lib/drmtest.c:694:
11027 11:39:52.197406 Test requirement: !(fd<<8>[ 15.279338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11028 11:39:52.197898 0)
11029 11:39:52.198481 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11031 11:39:52.204001 No known gpu found for chipset flags 0x32 (panfrost)
11032 11:39:52.206811 Last errno: 2, No such file or directory
11033 11:39:52.216890 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[<14>[ 15.301688] [IGT] panfrost_submit: executing
11034 11:39:52.217420 0m
11035 11:39:52.223462 IGT-Version: 1.28-ga44ebfe (<14>[ 15.309396] [IGT] panfrost_submit: exiting, ret=77
11036 11:39:52.226688 aarch64) (Linux: 6.1.96-cip24 aarch64)
11037 11:39:52.236607 Using IGT_SRANDOM=172121<8>[ 15.321002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11038 11:39:52.237346 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11040 11:39:52.239753 6392 for randomisation
11041 11:39:52.247262 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11042 11:39:52.249291 Test requirement: !(fd<0)
11043 11:39:52.256284 No known gpu found for chip<14>[ 15.341233] [IGT] panfrost_submit: executing
11044 11:39:52.256796 set flags 0x32 (panfrost)
11045 11:39:52.263391 Last <14>[ 15.348359] [IGT] panfrost_submit: exiting, ret=77
11046 11:39:52.266369 errno: 2, No such file or directory
11047 11:39:52.276216 [1mSubtest pan-submit-erro<8>[ 15.359937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11048 11:39:52.276979 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11050 11:39:52.279456 r-bad-requirements: SKIP (0.000s)[0m
11051 11:39:52.286242 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11052 11:39:52.289123 Using IGT_SRANDOM=1721216392 for randomisation
11053 11:39:52.295994 Test <14>[ 15.380462] [IGT] panfrost_submit: executing
11054 11:39:52.303391 requirement not met in function <14>[ 15.388124] [IGT] panfrost_submit: exiting, ret=77
11055 11:39:52.306150 drm_open_driver, file ../lib/drmtest.c:694:
11056 11:39:52.315927 Test requirement: !<8>[ 15.399618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11057 11:39:52.316435 (fd<0)
11058 11:39:52.317016 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11060 11:39:52.323290 No known<8>[ 15.409026] <LAVA_SIGNAL_TESTSET STOP>
11061 11:39:52.324045 Received signal: <TESTSET> STOP
11062 11:39:52.324408 Closing test_set panfrost_submit
11063 11:39:52.329694 gpu found for c<8>[ 15.414201] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14864651_1.5.2.3.1>
11064 11:39:52.330350 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14864651_1.5.2.3.1
11065 11:39:52.330742 Ending use of test pattern.
11066 11:39:52.331055 Ending test lava.0_igt-gpu-panfrost (14864651_1.5.2.3.1), duration 0.77
11068 11:39:52.333026 hipset flags 0x32 (panfrost)
11069 11:39:52.335766 Last errno: 2, No such file or directory
11070 11:39:52.342301 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11071 11:39:52.349597 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11072 11:39:52.351974 Using IGT_SRANDOM=1721216392 for randomisation
11073 11:39:52.359556 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11074 11:39:52.361903 Test requirement: !(fd<0)
11075 11:39:52.366106 No known gpu found for chipset flags 0x32 (panfrost)
11076 11:39:52.368749 Last errno: 2, No such file or directory
11077 11:39:52.372073 [1mSubtest pan-reset: SKIP (0.000s)[0m
11078 11:39:52.379025 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11079 11:39:52.384797 Using IGT_SRANDOM=1721216392 for randomisation
11080 11:39:52.392220 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11081 11:39:52.392721 Test requirement: !(fd<0)
11082 11:39:52.398814 No known gpu found for chipset flags 0x32 (panfrost)
11083 11:39:52.402097 Last errno: 2, No such file or directory
11084 11:39:52.405293 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11085 11:39:52.412355 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.96-cip24 aarch64)
11086 11:39:52.414990 Using IGT_SRANDOM=1721216392 for randomisation
11087 11:39:52.425267 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11088 11:39:52.425811 Test requirement: !(fd<0)
11089 11:39:52.431006 No known gpu found for chipset flags 0x32 (panfrost)
11090 11:39:52.434998 Last errno: 2, No such file or directory
11091 11:39:52.438249 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11092 11:39:52.438673 + set +x
11093 11:39:52.441481 <LAVA_TEST_RUNNER EXIT>
11094 11:39:52.442162 ok: lava_test_shell seems to have completed
11095 11:39:52.443831 gem-new-4096:
set: panfrost_gem_new
result: skip
gem-new-0:
set: panfrost_gem_new
result: skip
gem-new-zeroed:
set: panfrost_gem_new
result: skip
base-params:
set: panfrost_get_param
result: skip
get-bad-param:
set: panfrost_get_param
result: skip
get-bad-padding:
set: panfrost_get_param
result: skip
gem-prime-import:
set: panfrost_prime
result: skip
pan-submit:
set: panfrost_submit
result: skip
pan-submit-error-no-jc:
set: panfrost_submit
result: skip
pan-submit-error-bad-in-syncs:
set: panfrost_submit
result: skip
pan-submit-error-bad-bo-handles:
set: panfrost_submit
result: skip
pan-submit-error-bad-requirements:
set: panfrost_submit
result: skip
pan-submit-error-bad-out-sync:
set: panfrost_submit
result: skip
pan-reset:
set: panfrost_submit
result: skip
pan-submit-and-close:
set: panfrost_submit
result: skip
pan-unhandled-pagefault:
set: panfrost_submit
result: skip
11096 11:39:52.444404 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11097 11:39:52.444831 end: 3 lava-test-retry (duration 00:00:01) [common]
11098 11:39:52.445303 start: 4 finalize (timeout 00:07:53) [common]
11099 11:39:52.445756 start: 4.1 power-off (timeout 00:00:30) [common]
11100 11:39:52.446501 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11101 11:39:54.562357 >> Command sent successfully.
11102 11:39:54.575714 Returned 0 in 2 seconds
11103 11:39:54.576273 end: 4.1 power-off (duration 00:00:02) [common]
11105 11:39:54.577196 start: 4.2 read-feedback (timeout 00:07:51) [common]
11106 11:39:54.577863 Listened to connection for namespace 'common' for up to 1s
11107 11:39:55.579008 Finalising connection for namespace 'common'
11108 11:39:55.579599 Disconnecting from shell: Finalise
11109 11:39:55.579969 / #
11110 11:39:55.680994 end: 4.2 read-feedback (duration 00:00:01) [common]
11111 11:39:55.681700 end: 4 finalize (duration 00:00:03) [common]
11112 11:39:55.682262 Cleaning after the job
11113 11:39:55.682751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/ramdisk
11114 11:39:55.713849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/kernel
11115 11:39:55.742493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/dtb
11116 11:39:55.742750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864651/tftp-deploy-lbt7ol7e/modules
11117 11:39:55.749545 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864651
11118 11:39:55.859729 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864651
11119 11:39:55.859896 Job finished correctly