Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:34:17.881235 lava-dispatcher, installed at version: 2024.05
2 11:34:17.881433 start: 0 validate
3 11:34:17.881550 Start time: 2024-07-17 11:34:17.881544+00:00 (UTC)
4 11:34:17.881676 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:34:17.881841 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:34:18.132964 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:34:18.133137 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:34:18.392796 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:34:18.393076 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:34:18.651417 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:34:18.651588 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:34:18.909256 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:34:18.909401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:34:19.168689 validate duration: 1.29
16 11:34:19.169039 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:34:19.169273 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:34:19.169388 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:34:19.169615 Not decompressing ramdisk as can be used compressed.
20 11:34:19.169715 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 11:34:19.169804 saving as /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/ramdisk/initrd.cpio.gz
22 11:34:19.169899 total size: 5628169 (5 MB)
23 11:34:19.170953 progress 0 % (0 MB)
24 11:34:19.172674 progress 5 % (0 MB)
25 11:34:19.174243 progress 10 % (0 MB)
26 11:34:19.175827 progress 15 % (0 MB)
27 11:34:19.177559 progress 20 % (1 MB)
28 11:34:19.179107 progress 25 % (1 MB)
29 11:34:19.180810 progress 30 % (1 MB)
30 11:34:19.182441 progress 35 % (1 MB)
31 11:34:19.183957 progress 40 % (2 MB)
32 11:34:19.185608 progress 45 % (2 MB)
33 11:34:19.187070 progress 50 % (2 MB)
34 11:34:19.188755 progress 55 % (2 MB)
35 11:34:19.190380 progress 60 % (3 MB)
36 11:34:19.191914 progress 65 % (3 MB)
37 11:34:19.193600 progress 70 % (3 MB)
38 11:34:19.195135 progress 75 % (4 MB)
39 11:34:19.196751 progress 80 % (4 MB)
40 11:34:19.198160 progress 85 % (4 MB)
41 11:34:19.199850 progress 90 % (4 MB)
42 11:34:19.201349 progress 95 % (5 MB)
43 11:34:19.202700 progress 100 % (5 MB)
44 11:34:19.202909 5 MB downloaded in 0.03 s (162.54 MB/s)
45 11:34:19.203054 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:34:19.203269 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:34:19.203349 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:34:19.203423 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:34:19.203598 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:34:19.203659 saving as /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/kernel/Image
52 11:34:19.203712 total size: 54813184 (52 MB)
53 11:34:19.203765 No compression specified
54 11:34:19.204767 progress 0 % (0 MB)
55 11:34:19.218371 progress 5 % (2 MB)
56 11:34:19.232176 progress 10 % (5 MB)
57 11:34:19.245692 progress 15 % (7 MB)
58 11:34:19.259533 progress 20 % (10 MB)
59 11:34:19.273320 progress 25 % (13 MB)
60 11:34:19.287877 progress 30 % (15 MB)
61 11:34:19.302948 progress 35 % (18 MB)
62 11:34:19.317799 progress 40 % (20 MB)
63 11:34:19.332514 progress 45 % (23 MB)
64 11:34:19.347572 progress 50 % (26 MB)
65 11:34:19.362276 progress 55 % (28 MB)
66 11:34:19.376987 progress 60 % (31 MB)
67 11:34:19.392246 progress 65 % (34 MB)
68 11:34:19.407236 progress 70 % (36 MB)
69 11:34:19.422019 progress 75 % (39 MB)
70 11:34:19.436687 progress 80 % (41 MB)
71 11:34:19.451679 progress 85 % (44 MB)
72 11:34:19.466698 progress 90 % (47 MB)
73 11:34:19.481774 progress 95 % (49 MB)
74 11:34:19.496420 progress 100 % (52 MB)
75 11:34:19.496700 52 MB downloaded in 0.29 s (178.42 MB/s)
76 11:34:19.496891 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:34:19.497235 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:34:19.497348 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:34:19.497455 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:34:19.497621 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:34:19.497727 saving as /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/dtb/mt8192-asurada-spherion-r0.dtb
83 11:34:19.497829 total size: 47258 (0 MB)
84 11:34:19.497911 No compression specified
85 11:34:19.499544 progress 69 % (0 MB)
86 11:34:19.499861 progress 100 % (0 MB)
87 11:34:19.500036 0 MB downloaded in 0.00 s (20.44 MB/s)
88 11:34:19.500193 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:34:19.500524 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:34:19.500634 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:34:19.500742 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:34:19.500882 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 11:34:19.500972 saving as /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/nfsrootfs/full.rootfs.tar
95 11:34:19.501052 total size: 120894716 (115 MB)
96 11:34:19.501138 Using unxz to decompress xz
97 11:34:19.502705 progress 0 % (0 MB)
98 11:34:19.851525 progress 5 % (5 MB)
99 11:34:20.217057 progress 10 % (11 MB)
100 11:34:20.571591 progress 15 % (17 MB)
101 11:34:20.897055 progress 20 % (23 MB)
102 11:34:21.206417 progress 25 % (28 MB)
103 11:34:21.546612 progress 30 % (34 MB)
104 11:34:21.863585 progress 35 % (40 MB)
105 11:34:22.032171 progress 40 % (46 MB)
106 11:34:22.213224 progress 45 % (51 MB)
107 11:34:22.513932 progress 50 % (57 MB)
108 11:34:22.864979 progress 55 % (63 MB)
109 11:34:23.196110 progress 60 % (69 MB)
110 11:34:23.546633 progress 65 % (74 MB)
111 11:34:23.905491 progress 70 % (80 MB)
112 11:34:24.257442 progress 75 % (86 MB)
113 11:34:24.586911 progress 80 % (92 MB)
114 11:34:24.919160 progress 85 % (98 MB)
115 11:34:25.251002 progress 90 % (103 MB)
116 11:34:25.570820 progress 95 % (109 MB)
117 11:34:25.927281 progress 100 % (115 MB)
118 11:34:25.932631 115 MB downloaded in 6.43 s (17.93 MB/s)
119 11:34:25.932790 end: 1.4.1 http-download (duration 00:00:06) [common]
121 11:34:25.932999 end: 1.4 download-retry (duration 00:00:06) [common]
122 11:34:25.933078 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:34:25.933153 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:34:25.933287 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:34:25.933348 saving as /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/modules/modules.tar
126 11:34:25.933402 total size: 8610184 (8 MB)
127 11:34:25.933458 Using unxz to decompress xz
128 11:34:25.934747 progress 0 % (0 MB)
129 11:34:25.955186 progress 5 % (0 MB)
130 11:34:25.979683 progress 10 % (0 MB)
131 11:34:26.003261 progress 15 % (1 MB)
132 11:34:26.027428 progress 20 % (1 MB)
133 11:34:26.050479 progress 25 % (2 MB)
134 11:34:26.073528 progress 30 % (2 MB)
135 11:34:26.095856 progress 35 % (2 MB)
136 11:34:26.121777 progress 40 % (3 MB)
137 11:34:26.145911 progress 45 % (3 MB)
138 11:34:26.169838 progress 50 % (4 MB)
139 11:34:26.194131 progress 55 % (4 MB)
140 11:34:26.217830 progress 60 % (4 MB)
141 11:34:26.241042 progress 65 % (5 MB)
142 11:34:26.266139 progress 70 % (5 MB)
143 11:34:26.292853 progress 75 % (6 MB)
144 11:34:26.320302 progress 80 % (6 MB)
145 11:34:26.343688 progress 85 % (7 MB)
146 11:34:26.366468 progress 90 % (7 MB)
147 11:34:26.389741 progress 95 % (7 MB)
148 11:34:26.412193 progress 100 % (8 MB)
149 11:34:26.417593 8 MB downloaded in 0.48 s (16.96 MB/s)
150 11:34:26.417747 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:34:26.417954 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:34:26.418032 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:34:26.418106 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:34:29.915423 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k
156 11:34:29.915627 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:34:29.915714 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:34:29.915875 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe
159 11:34:29.915992 makedir: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin
160 11:34:29.916083 makedir: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/tests
161 11:34:29.916168 makedir: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/results
162 11:34:29.916249 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-add-keys
163 11:34:29.916373 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-add-sources
164 11:34:29.916488 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-background-process-start
165 11:34:29.916603 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-background-process-stop
166 11:34:29.916723 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-common-functions
167 11:34:29.916837 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-echo-ipv4
168 11:34:29.916949 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-install-packages
169 11:34:29.917059 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-installed-packages
170 11:34:29.917169 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-os-build
171 11:34:29.917278 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-probe-channel
172 11:34:29.917390 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-probe-ip
173 11:34:29.917501 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-target-ip
174 11:34:29.917610 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-target-mac
175 11:34:29.917720 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-target-storage
176 11:34:29.917832 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-case
177 11:34:29.917942 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-event
178 11:34:29.918052 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-feedback
179 11:34:29.918162 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-raise
180 11:34:29.918272 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-reference
181 11:34:29.918383 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-runner
182 11:34:29.918492 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-set
183 11:34:29.918601 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-test-shell
184 11:34:29.918713 Updating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-add-keys (debian)
185 11:34:29.918850 Updating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-add-sources (debian)
186 11:34:29.918973 Updating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-install-packages (debian)
187 11:34:29.919094 Updating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-installed-packages (debian)
188 11:34:29.919214 Updating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/bin/lava-os-build (debian)
189 11:34:29.919320 Creating /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/environment
190 11:34:29.919404 LAVA metadata
191 11:34:29.919507 - LAVA_JOB_ID=14864600
192 11:34:29.919562 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:34:29.919652 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:34:29.919706 skipped lava-vland-overlay
195 11:34:29.919771 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:34:29.919840 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:34:29.919892 skipped lava-multinode-overlay
198 11:34:29.919953 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:34:29.920019 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:34:29.920092 Loading test definitions
201 11:34:29.920166 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:34:29.920225 Using /lava-14864600 at stage 0
203 11:34:29.920491 uuid=14864600_1.6.2.3.1 testdef=None
204 11:34:29.920568 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:34:29.920641 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:34:29.921023 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:34:29.921215 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:34:29.921710 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:34:29.921913 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:34:29.922391 runner path: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/0/tests/0_timesync-off test_uuid 14864600_1.6.2.3.1
213 11:34:29.922528 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:34:29.922724 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:34:29.922786 Using /lava-14864600 at stage 0
217 11:34:29.922869 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:34:29.922941 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/0/tests/1_kselftest-rtc'
219 11:34:33.086727 Running '/usr/bin/git checkout kernelci.org
220 11:34:33.162556 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:34:33.162916 uuid=14864600_1.6.2.3.5 testdef=None
222 11:34:33.163015 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:34:33.163206 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 11:34:33.163882 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:34:33.164080 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 11:34:33.164971 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:34:33.165191 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 11:34:33.166037 runner path: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/0/tests/1_kselftest-rtc test_uuid 14864600_1.6.2.3.5
232 11:34:33.166115 BOARD='mt8192-asurada-spherion-r0'
233 11:34:33.166173 BRANCH='cip-gitlab'
234 11:34:33.166226 SKIPFILE='/dev/null'
235 11:34:33.166276 SKIP_INSTALL='True'
236 11:34:33.166325 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz'
237 11:34:33.166375 TST_CASENAME=''
238 11:34:33.166425 TST_CMDFILES='rtc'
239 11:34:33.166555 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:34:33.166731 Creating lava-test-runner.conf files
242 11:34:33.166785 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864600/lava-overlay-scm0bwhe/lava-14864600/0 for stage 0
243 11:34:33.166863 - 0_timesync-off
244 11:34:33.166920 - 1_kselftest-rtc
245 11:34:33.167004 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:34:33.167079 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 11:34:40.232599 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:34:40.232732 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 11:34:40.232824 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:34:40.232905 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:34:40.232982 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 11:34:40.389261 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:34:40.389405 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 11:34:40.389482 extracting modules file /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k
255 11:34:40.608965 extracting modules file /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864600/extract-overlay-ramdisk-15593rc1/ramdisk
256 11:34:40.840523 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:34:40.840663 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 11:34:40.840738 [common] Applying overlay to NFS
259 11:34:40.840796 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864600/compress-overlay-8dsl_d4g/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k
260 11:34:41.662611 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:34:41.662749 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 11:34:41.662831 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:34:41.662942 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 11:34:41.663010 Building ramdisk /var/lib/lava/dispatcher/tmp/14864600/extract-overlay-ramdisk-15593rc1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864600/extract-overlay-ramdisk-15593rc1/ramdisk
265 11:34:41.993593 >> 129966 blocks
266 11:34:44.051105 rename /var/lib/lava/dispatcher/tmp/14864600/extract-overlay-ramdisk-15593rc1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/ramdisk/ramdisk.cpio.gz
267 11:34:44.051270 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:34:44.051356 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 11:34:44.051439 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 11:34:44.051554 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/kernel/Image']
271 11:34:58.103194 Returned 0 in 14 seconds
272 11:34:58.103364 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/kernel/image.itb
273 11:34:58.527528 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:34:58.527650 output: Created: Wed Jul 17 12:34:58 2024
275 11:34:58.527711 output: Image 0 (kernel-1)
276 11:34:58.527765 output: Description:
277 11:34:58.527817 output: Created: Wed Jul 17 12:34:58 2024
278 11:34:58.527868 output: Type: Kernel Image
279 11:34:58.527919 output: Compression: lzma compressed
280 11:34:58.527970 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
281 11:34:58.528019 output: Architecture: AArch64
282 11:34:58.528068 output: OS: Linux
283 11:34:58.528115 output: Load Address: 0x00000000
284 11:34:58.528163 output: Entry Point: 0x00000000
285 11:34:58.528210 output: Hash algo: crc32
286 11:34:58.528258 output: Hash value: 83448d17
287 11:34:58.528306 output: Image 1 (fdt-1)
288 11:34:58.528354 output: Description: mt8192-asurada-spherion-r0
289 11:34:58.528402 output: Created: Wed Jul 17 12:34:58 2024
290 11:34:58.528449 output: Type: Flat Device Tree
291 11:34:58.528495 output: Compression: uncompressed
292 11:34:58.528542 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 11:34:58.528591 output: Architecture: AArch64
294 11:34:58.528638 output: Hash algo: crc32
295 11:34:58.528685 output: Hash value: 0f8e4d2e
296 11:34:58.528731 output: Image 2 (ramdisk-1)
297 11:34:58.528777 output: Description: unavailable
298 11:34:58.528824 output: Created: Wed Jul 17 12:34:58 2024
299 11:34:58.528871 output: Type: RAMDisk Image
300 11:34:58.528918 output: Compression: uncompressed
301 11:34:58.528964 output: Data Size: 18721686 Bytes = 18282.90 KiB = 17.85 MiB
302 11:34:58.529012 output: Architecture: AArch64
303 11:34:58.529057 output: OS: Linux
304 11:34:58.529103 output: Load Address: unavailable
305 11:34:58.529149 output: Entry Point: unavailable
306 11:34:58.529195 output: Hash algo: crc32
307 11:34:58.529241 output: Hash value: cb96dc83
308 11:34:58.529287 output: Default Configuration: 'conf-1'
309 11:34:58.529333 output: Configuration 0 (conf-1)
310 11:34:58.529378 output: Description: mt8192-asurada-spherion-r0
311 11:34:58.529424 output: Kernel: kernel-1
312 11:34:58.529470 output: Init Ramdisk: ramdisk-1
313 11:34:58.529517 output: FDT: fdt-1
314 11:34:58.529563 output: Loadables: kernel-1
315 11:34:58.529609 output:
316 11:34:58.529705 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:34:58.529778 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:34:58.529851 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:34:58.529923 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 11:34:58.529979 No LXC device requested
321 11:34:58.530044 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:34:58.530112 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 11:34:58.530178 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:34:58.530232 Checking files for TFTP limit of 4294967296 bytes.
325 11:34:58.530645 end: 1 tftp-deploy (duration 00:00:39) [common]
326 11:34:58.530732 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:34:58.530809 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:34:58.530897 substitutions:
329 11:34:58.530955 - {DTB}: 14864600/tftp-deploy-eo48rblv/dtb/mt8192-asurada-spherion-r0.dtb
330 11:34:58.531009 - {INITRD}: 14864600/tftp-deploy-eo48rblv/ramdisk/ramdisk.cpio.gz
331 11:34:58.531059 - {KERNEL}: 14864600/tftp-deploy-eo48rblv/kernel/Image
332 11:34:58.531109 - {LAVA_MAC}: None
333 11:34:58.531159 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k
334 11:34:58.531207 - {NFS_SERVER_IP}: 192.168.201.1
335 11:34:58.531255 - {PRESEED_CONFIG}: None
336 11:34:58.531307 - {PRESEED_LOCAL}: None
337 11:34:58.531355 - {RAMDISK}: 14864600/tftp-deploy-eo48rblv/ramdisk/ramdisk.cpio.gz
338 11:34:58.531403 - {ROOT_PART}: None
339 11:34:58.531485 - {ROOT}: None
340 11:34:58.531580 - {SERVER_IP}: 192.168.201.1
341 11:34:58.531651 - {TEE}: None
342 11:34:58.531701 Parsed boot commands:
343 11:34:58.531748 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:34:58.531885 Parsed boot commands: tftpboot 192.168.201.1 14864600/tftp-deploy-eo48rblv/kernel/image.itb 14864600/tftp-deploy-eo48rblv/kernel/cmdline
345 11:34:58.531962 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:34:58.532034 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:34:58.532105 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:34:58.532174 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:34:58.532228 Not connected, no need to disconnect.
350 11:34:58.532291 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:34:58.532359 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:34:58.532412 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 11:34:58.535451 Setting prompt string to ['lava-test: # ']
354 11:34:58.535771 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:34:58.535865 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:34:58.535951 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:34:58.536029 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:34:58.536238 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=reboot']
359 11:35:07.680404 >> Command sent successfully.
360 11:35:07.684528 Returned 0 in 9 seconds
361 11:35:07.684670 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
363 11:35:07.684869 end: 2.2.2 reset-device (duration 00:00:09) [common]
364 11:35:07.684954 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
365 11:35:07.685027 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:35:07.685081 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:35:07.685141 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:35:07.685469 [Enter `^Ec?' for help]
369 11:35:09.087122
370 11:35:09.087246 F0: 102B 0000
371 11:35:09.087311
372 11:35:09.090601 F3: 1001 0000 [0200]
373 11:35:09.090679
374 11:35:09.090737 F3: 1001 0000
375 11:35:09.090795
376 11:35:09.090846 F7: 102D 0000
377 11:35:09.090899
378 11:35:09.094343 F1: 0000 0000
379 11:35:09.094420
380 11:35:09.094480 V0: 0000 0000 [0001]
381 11:35:09.094534
382 11:35:09.094587 00: 0007 8000
383 11:35:09.097805
384 11:35:09.097882 01: 0000 0000
385 11:35:09.097942
386 11:35:09.097996 BP: 0C00 0209 [0000]
387 11:35:09.098047
388 11:35:09.101360 G0: 1182 0000
389 11:35:09.101434
390 11:35:09.101492 EC: 0000 0021 [4000]
391 11:35:09.101546
392 11:35:09.105077 S7: 0000 0000 [0000]
393 11:35:09.105175
394 11:35:09.105261 CC: 0000 0000 [0001]
395 11:35:09.105340
396 11:35:09.108404 T0: 0000 0040 [010F]
397 11:35:09.108479
398 11:35:09.108536 Jump to BL
399 11:35:09.108590
400 11:35:09.134209
401 11:35:09.134285
402 11:35:09.141736 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 11:35:09.144813 ARM64: Exception handlers installed.
404 11:35:09.148744 ARM64: Testing exception
405 11:35:09.152399 ARM64: Done test exception
406 11:35:09.159170 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 11:35:09.169758 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 11:35:09.176938 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 11:35:09.187015 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 11:35:09.194879 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 11:35:09.201602 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 11:35:09.211788 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 11:35:09.217986 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 11:35:09.236983 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 11:35:09.240703 WDT: Last reset was cold boot
416 11:35:09.243408 SPI1(PAD0) initialized at 2873684 Hz
417 11:35:09.246635 SPI5(PAD0) initialized at 992727 Hz
418 11:35:09.249997 VBOOT: Loading verstage.
419 11:35:09.257003 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 11:35:09.259973 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 11:35:09.263499 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 11:35:09.266762 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 11:35:09.274675 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 11:35:09.281275 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 11:35:09.292101 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 11:35:09.292179
427 11:35:09.292242
428 11:35:09.302139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 11:35:09.305333 ARM64: Exception handlers installed.
430 11:35:09.308662 ARM64: Testing exception
431 11:35:09.308737 ARM64: Done test exception
432 11:35:09.314852 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 11:35:09.318108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 11:35:09.332631 Probing TPM: . done!
435 11:35:09.332714 TPM ready after 0 ms
436 11:35:09.339710 Connected to device vid:did:rid of 1ae0:0028:00
437 11:35:09.349980 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 11:35:09.387358 Initialized TPM device CR50 revision 0
439 11:35:09.398469 tlcl_send_startup: Startup return code is 0
440 11:35:09.398549 TPM: setup succeeded
441 11:35:09.410042 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 11:35:09.418673 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 11:35:09.426154 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 11:35:09.437739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:35:09.441677 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 11:35:09.444468 in-header: 03 07 00 00 08 00 00 00
447 11:35:09.448144 in-data: aa e4 47 04 13 02 00 00
448 11:35:09.451163 Chrome EC: UHEPI supported
449 11:35:09.457641 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 11:35:09.460912 in-header: 03 a9 00 00 08 00 00 00
451 11:35:09.464305 in-data: 84 60 60 08 00 00 00 00
452 11:35:09.464380 Phase 1
453 11:35:09.467708 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 11:35:09.474143 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 11:35:09.481235 VB2:vb2_check_recovery() Recovery was requested manually
456 11:35:09.484495 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 11:35:09.487653 Recovery requested (1009000e)
458 11:35:09.496555 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 11:35:09.501213 tlcl_extend: response is 0
460 11:35:09.509863 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 11:35:09.515256 tlcl_extend: response is 0
462 11:35:09.521742 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 11:35:09.542276 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 11:35:09.548745 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 11:35:09.548847
466 11:35:09.548936
467 11:35:09.558629 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 11:35:09.561732 ARM64: Exception handlers installed.
469 11:35:09.565731 ARM64: Testing exception
470 11:35:09.565805 ARM64: Done test exception
471 11:35:09.587521 pmic_efuse_setting: Set efuses in 11 msecs
472 11:35:09.591043 pmwrap_interface_init: Select PMIF_VLD_RDY
473 11:35:09.597234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 11:35:09.600908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 11:35:09.607324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 11:35:09.610758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 11:35:09.617531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 11:35:09.620898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 11:35:09.627487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 11:35:09.631117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 11:35:09.633700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 11:35:09.640491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 11:35:09.643816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 11:35:09.650785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 11:35:09.653913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 11:35:09.660433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 11:35:09.667039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 11:35:09.670324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 11:35:09.677114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 11:35:09.683898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 11:35:09.687305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 11:35:09.693782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 11:35:09.700189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 11:35:09.703865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 11:35:09.710260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 11:35:09.716993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 11:35:09.720223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 11:35:09.726865 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 11:35:09.733537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 11:35:09.737011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 11:35:09.743539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 11:35:09.746604 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 11:35:09.750124 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 11:35:09.757903 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 11:35:09.761767 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 11:35:09.765174 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 11:35:09.771904 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 11:35:09.775189 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 11:35:09.782515 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 11:35:09.785650 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 11:35:09.792376 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 11:35:09.795957 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 11:35:09.799053 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 11:35:09.805796 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 11:35:09.808801 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 11:35:09.812476 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 11:35:09.819051 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 11:35:09.822423 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 11:35:09.825517 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 11:35:09.828949 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 11:35:09.835127 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 11:35:09.838495 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 11:35:09.842111 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 11:35:09.852067 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 11:35:09.858537 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 11:35:09.861842 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 11:35:09.872061 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 11:35:09.878516 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 11:35:09.885142 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 11:35:09.888509 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 11:35:09.891872 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:35:09.900665 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
533 11:35:09.906896 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 11:35:09.910526 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 11:35:09.913710 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 11:35:09.924499 [RTC]rtc_get_frequency_meter,154: input=15, output=834
537 11:35:09.934338 [RTC]rtc_get_frequency_meter,154: input=7, output=708
538 11:35:09.943504 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 11:35:09.953210 [RTC]rtc_get_frequency_meter,154: input=13, output=804
540 11:35:09.962964 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 11:35:09.972378 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 11:35:09.982018 [RTC]rtc_get_frequency_meter,154: input=13, output=804
543 11:35:09.985021 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 11:35:09.992127 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 11:35:09.995580 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 11:35:09.998734 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 11:35:10.005592 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 11:35:10.008668 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 11:35:10.012233 ADC[4]: Raw value=904879 ID=7
550 11:35:10.012308 ADC[3]: Raw value=213282 ID=1
551 11:35:10.015246 RAM Code: 0x71
552 11:35:10.018652 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 11:35:10.025442 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 11:35:10.031926 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 11:35:10.038912 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 11:35:10.042350 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 11:35:10.045389 in-header: 03 07 00 00 08 00 00 00
558 11:35:10.048735 in-data: aa e4 47 04 13 02 00 00
559 11:35:10.051874 Chrome EC: UHEPI supported
560 11:35:10.058672 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 11:35:10.061703 in-header: 03 a9 00 00 08 00 00 00
562 11:35:10.064937 in-data: 84 60 60 08 00 00 00 00
563 11:35:10.068336 MRC: failed to locate region type 0.
564 11:35:10.075201 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 11:35:10.078582 DRAM-K: Running full calibration
566 11:35:10.085109 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 11:35:10.085185 header.status = 0x0
568 11:35:10.088171 header.version = 0x6 (expected: 0x6)
569 11:35:10.091356 header.size = 0xd00 (expected: 0xd00)
570 11:35:10.094888 header.flags = 0x0
571 11:35:10.101385 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 11:35:10.118742 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 11:35:10.125294 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 11:35:10.128268 dram_init: ddr_geometry: 2
575 11:35:10.131856 [EMI] MDL number = 2
576 11:35:10.131931 [EMI] Get MDL freq = 0
577 11:35:10.135229 dram_init: ddr_type: 0
578 11:35:10.135303 is_discrete_lpddr4: 1
579 11:35:10.138439 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 11:35:10.138514
581 11:35:10.138573
582 11:35:10.141859 [Bian_co] ETT version 0.0.0.1
583 11:35:10.148723 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 11:35:10.148799
585 11:35:10.151655 dramc_set_vcore_voltage set vcore to 650000
586 11:35:10.154877 Read voltage for 800, 4
587 11:35:10.154952 Vio18 = 0
588 11:35:10.155011 Vcore = 650000
589 11:35:10.155065 Vdram = 0
590 11:35:10.158250 Vddq = 0
591 11:35:10.158324 Vmddr = 0
592 11:35:10.161721 dram_init: config_dvfs: 1
593 11:35:10.165005 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 11:35:10.171654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 11:35:10.175312 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 11:35:10.178376 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 11:35:10.181769 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 11:35:10.185225 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 11:35:10.188531 MEM_TYPE=3, freq_sel=18
600 11:35:10.191875 sv_algorithm_assistance_LP4_1600
601 11:35:10.195493 ============ PULL DRAM RESETB DOWN ============
602 11:35:10.201439 ========== PULL DRAM RESETB DOWN end =========
603 11:35:10.204954 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 11:35:10.208008 ===================================
605 11:35:10.211320 LPDDR4 DRAM CONFIGURATION
606 11:35:10.214743 ===================================
607 11:35:10.214819 EX_ROW_EN[0] = 0x0
608 11:35:10.218098 EX_ROW_EN[1] = 0x0
609 11:35:10.218173 LP4Y_EN = 0x0
610 11:35:10.221631 WORK_FSP = 0x0
611 11:35:10.221707 WL = 0x2
612 11:35:10.224670 RL = 0x2
613 11:35:10.224744 BL = 0x2
614 11:35:10.228301 RPST = 0x0
615 11:35:10.228375 RD_PRE = 0x0
616 11:35:10.231253 WR_PRE = 0x1
617 11:35:10.234751 WR_PST = 0x0
618 11:35:10.234818 DBI_WR = 0x0
619 11:35:10.238130 DBI_RD = 0x0
620 11:35:10.238221 OTF = 0x1
621 11:35:10.241003 ===================================
622 11:35:10.244527 ===================================
623 11:35:10.244613 ANA top config
624 11:35:10.247677 ===================================
625 11:35:10.251169 DLL_ASYNC_EN = 0
626 11:35:10.254519 ALL_SLAVE_EN = 1
627 11:35:10.257767 NEW_RANK_MODE = 1
628 11:35:10.261286 DLL_IDLE_MODE = 1
629 11:35:10.261372 LP45_APHY_COMB_EN = 1
630 11:35:10.264256 TX_ODT_DIS = 1
631 11:35:10.267906 NEW_8X_MODE = 1
632 11:35:10.271465 ===================================
633 11:35:10.274615 ===================================
634 11:35:10.277818 data_rate = 1600
635 11:35:10.281430 CKR = 1
636 11:35:10.281497 DQ_P2S_RATIO = 8
637 11:35:10.284464 ===================================
638 11:35:10.287898 CA_P2S_RATIO = 8
639 11:35:10.291399 DQ_CA_OPEN = 0
640 11:35:10.294689 DQ_SEMI_OPEN = 0
641 11:35:10.298203 CA_SEMI_OPEN = 0
642 11:35:10.301137 CA_FULL_RATE = 0
643 11:35:10.301227 DQ_CKDIV4_EN = 1
644 11:35:10.304665 CA_CKDIV4_EN = 1
645 11:35:10.307691 CA_PREDIV_EN = 0
646 11:35:10.311022 PH8_DLY = 0
647 11:35:10.314509 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 11:35:10.314579 DQ_AAMCK_DIV = 4
649 11:35:10.317862 CA_AAMCK_DIV = 4
650 11:35:10.321178 CA_ADMCK_DIV = 4
651 11:35:10.324810 DQ_TRACK_CA_EN = 0
652 11:35:10.327640 CA_PICK = 800
653 11:35:10.331115 CA_MCKIO = 800
654 11:35:10.334332 MCKIO_SEMI = 0
655 11:35:10.334430 PLL_FREQ = 3068
656 11:35:10.337538 DQ_UI_PI_RATIO = 32
657 11:35:10.341018 CA_UI_PI_RATIO = 0
658 11:35:10.344246 ===================================
659 11:35:10.347607 ===================================
660 11:35:10.350738 memory_type:LPDDR4
661 11:35:10.354410 GP_NUM : 10
662 11:35:10.354485 SRAM_EN : 1
663 11:35:10.357596 MD32_EN : 0
664 11:35:10.361091 ===================================
665 11:35:10.361166 [ANA_INIT] >>>>>>>>>>>>>>
666 11:35:10.364575 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 11:35:10.367790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 11:35:10.370910 ===================================
669 11:35:10.374221 data_rate = 1600,PCW = 0X7600
670 11:35:10.377727 ===================================
671 11:35:10.380809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 11:35:10.387789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 11:35:10.390971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:35:10.397821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 11:35:10.401035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 11:35:10.404326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:35:10.404402 [ANA_INIT] flow start
678 11:35:10.407854 [ANA_INIT] PLL >>>>>>>>
679 11:35:10.411060 [ANA_INIT] PLL <<<<<<<<
680 11:35:10.414576 [ANA_INIT] MIDPI >>>>>>>>
681 11:35:10.414651 [ANA_INIT] MIDPI <<<<<<<<
682 11:35:10.418003 [ANA_INIT] DLL >>>>>>>>
683 11:35:10.418078 [ANA_INIT] flow end
684 11:35:10.425474 ============ LP4 DIFF to SE enter ============
685 11:35:10.428829 ============ LP4 DIFF to SE exit ============
686 11:35:10.428914 [ANA_INIT] <<<<<<<<<<<<<
687 11:35:10.432763 [Flow] Enable top DCM control >>>>>
688 11:35:10.436309 [Flow] Enable top DCM control <<<<<
689 11:35:10.439920 Enable DLL master slave shuffle
690 11:35:10.443907 ==============================================================
691 11:35:10.447973 Gating Mode config
692 11:35:10.451156 ==============================================================
693 11:35:10.454603 Config description:
694 11:35:10.464766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 11:35:10.471602 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 11:35:10.474538 SELPH_MODE 0: By rank 1: By Phase
697 11:35:10.481316 ==============================================================
698 11:35:10.484486 GAT_TRACK_EN = 1
699 11:35:10.487714 RX_GATING_MODE = 2
700 11:35:10.491007 RX_GATING_TRACK_MODE = 2
701 11:35:10.494289 SELPH_MODE = 1
702 11:35:10.494364 PICG_EARLY_EN = 1
703 11:35:10.497918 VALID_LAT_VALUE = 1
704 11:35:10.504403 ==============================================================
705 11:35:10.507720 Enter into Gating configuration >>>>
706 11:35:10.510897 Exit from Gating configuration <<<<
707 11:35:10.514334 Enter into DVFS_PRE_config >>>>>
708 11:35:10.524066 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 11:35:10.527331 Exit from DVFS_PRE_config <<<<<
710 11:35:10.531366 Enter into PICG configuration >>>>
711 11:35:10.534274 Exit from PICG configuration <<<<
712 11:35:10.538085 [RX_INPUT] configuration >>>>>
713 11:35:10.540775 [RX_INPUT] configuration <<<<<
714 11:35:10.544402 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 11:35:10.550372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 11:35:10.557155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:35:10.564063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:35:10.570565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 11:35:10.576994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 11:35:10.580353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 11:35:10.583923 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 11:35:10.587220 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 11:35:10.593443 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 11:35:10.597128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 11:35:10.600231 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 11:35:10.603521 ===================================
727 11:35:10.606687 LPDDR4 DRAM CONFIGURATION
728 11:35:10.610225 ===================================
729 11:35:10.610300 EX_ROW_EN[0] = 0x0
730 11:35:10.613358 EX_ROW_EN[1] = 0x0
731 11:35:10.613432 LP4Y_EN = 0x0
732 11:35:10.617047 WORK_FSP = 0x0
733 11:35:10.617121 WL = 0x2
734 11:35:10.619950 RL = 0x2
735 11:35:10.624010 BL = 0x2
736 11:35:10.624084 RPST = 0x0
737 11:35:10.627078 RD_PRE = 0x0
738 11:35:10.627152 WR_PRE = 0x1
739 11:35:10.630581 WR_PST = 0x0
740 11:35:10.630655 DBI_WR = 0x0
741 11:35:10.633282 DBI_RD = 0x0
742 11:35:10.633357 OTF = 0x1
743 11:35:10.636689 ===================================
744 11:35:10.640054 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 11:35:10.647250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 11:35:10.650112 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 11:35:10.653188 ===================================
748 11:35:10.656426 LPDDR4 DRAM CONFIGURATION
749 11:35:10.660034 ===================================
750 11:35:10.660110 EX_ROW_EN[0] = 0x10
751 11:35:10.663497 EX_ROW_EN[1] = 0x0
752 11:35:10.663572 LP4Y_EN = 0x0
753 11:35:10.666393 WORK_FSP = 0x0
754 11:35:10.666467 WL = 0x2
755 11:35:10.670155 RL = 0x2
756 11:35:10.670231 BL = 0x2
757 11:35:10.673171 RPST = 0x0
758 11:35:10.676205 RD_PRE = 0x0
759 11:35:10.676280 WR_PRE = 0x1
760 11:35:10.679632 WR_PST = 0x0
761 11:35:10.679707 DBI_WR = 0x0
762 11:35:10.682971 DBI_RD = 0x0
763 11:35:10.683046 OTF = 0x1
764 11:35:10.686454 ===================================
765 11:35:10.692966 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 11:35:10.697025 nWR fixed to 40
767 11:35:10.700368 [ModeRegInit_LP4] CH0 RK0
768 11:35:10.700444 [ModeRegInit_LP4] CH0 RK1
769 11:35:10.703406 [ModeRegInit_LP4] CH1 RK0
770 11:35:10.706810 [ModeRegInit_LP4] CH1 RK1
771 11:35:10.706886 match AC timing 13
772 11:35:10.713240 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 11:35:10.716441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 11:35:10.720110 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 11:35:10.726771 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 11:35:10.729998 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 11:35:10.733237 [EMI DOE] emi_dcm 0
778 11:35:10.736429 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 11:35:10.736505 ==
780 11:35:10.739822 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:35:10.743178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:35:10.743255 ==
783 11:35:10.749816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 11:35:10.756197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 11:35:10.764398 [CA 0] Center 37 (7~68) winsize 62
786 11:35:10.767405 [CA 1] Center 37 (6~68) winsize 63
787 11:35:10.770957 [CA 2] Center 34 (4~65) winsize 62
788 11:35:10.774308 [CA 3] Center 34 (4~65) winsize 62
789 11:35:10.777295 [CA 4] Center 33 (3~64) winsize 62
790 11:35:10.781158 [CA 5] Center 33 (3~64) winsize 62
791 11:35:10.781234
792 11:35:10.784188 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 11:35:10.784263
794 11:35:10.787365 [CATrainingPosCal] consider 1 rank data
795 11:35:10.791170 u2DelayCellTimex100 = 270/100 ps
796 11:35:10.794648 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 11:35:10.798041 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 11:35:10.801321 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:35:10.804997 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:35:10.811547 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 11:35:10.814526 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:35:10.814601
803 11:35:10.818457 CA PerBit enable=1, Macro0, CA PI delay=33
804 11:35:10.818532
805 11:35:10.821352 [CBTSetCACLKResult] CA Dly = 33
806 11:35:10.821428 CS Dly: 6 (0~37)
807 11:35:10.821487 ==
808 11:35:10.824481 Dram Type= 6, Freq= 0, CH_0, rank 1
809 11:35:10.831141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 11:35:10.831217 ==
811 11:35:10.834789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 11:35:10.841392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 11:35:10.850768 [CA 0] Center 37 (6~68) winsize 63
814 11:35:10.853945 [CA 1] Center 37 (7~68) winsize 62
815 11:35:10.857082 [CA 2] Center 34 (4~65) winsize 62
816 11:35:10.860511 [CA 3] Center 34 (4~65) winsize 62
817 11:35:10.863925 [CA 4] Center 33 (3~64) winsize 62
818 11:35:10.867093 [CA 5] Center 33 (3~64) winsize 62
819 11:35:10.867168
820 11:35:10.870617 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 11:35:10.870692
822 11:35:10.873989 [CATrainingPosCal] consider 2 rank data
823 11:35:10.877003 u2DelayCellTimex100 = 270/100 ps
824 11:35:10.880524 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 11:35:10.883605 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:35:10.890053 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 11:35:10.894415 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:35:10.896844 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 11:35:10.900476 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:35:10.900550
831 11:35:10.903884 CA PerBit enable=1, Macro0, CA PI delay=33
832 11:35:10.903958
833 11:35:10.907353 [CBTSetCACLKResult] CA Dly = 33
834 11:35:10.907433 CS Dly: 6 (0~38)
835 11:35:10.907493
836 11:35:10.910153 ----->DramcWriteLeveling(PI) begin...
837 11:35:10.913768 ==
838 11:35:10.913841 Dram Type= 6, Freq= 0, CH_0, rank 0
839 11:35:10.920588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 11:35:10.920663 ==
841 11:35:10.924034 Write leveling (Byte 0): 34 => 34
842 11:35:10.927098 Write leveling (Byte 1): 29 => 29
843 11:35:10.930275 DramcWriteLeveling(PI) end<-----
844 11:35:10.930349
845 11:35:10.930412 ==
846 11:35:10.933862 Dram Type= 6, Freq= 0, CH_0, rank 0
847 11:35:10.937157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 11:35:10.937231 ==
849 11:35:10.940365 [Gating] SW mode calibration
850 11:35:10.947122 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 11:35:10.950474 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 11:35:10.957136 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 11:35:10.960278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 11:35:10.963777 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 11:35:10.970367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:35:10.973734 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:35:10.976903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:35:10.983392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:35:10.986967 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:35:10.990249 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:35:10.997155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:35:11.000879 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:35:11.004524 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:35:11.010835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:35:11.013881 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:35:11.017233 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:35:11.023718 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:35:11.026928 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:35:11.030711 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 11:35:11.036987 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
871 11:35:11.040415 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:35:11.043490 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:35:11.046965 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:35:11.053918 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:35:11.056739 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:35:11.060127 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:35:11.066899 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:35:11.070228 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
879 11:35:11.073661 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
880 11:35:11.079795 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:35:11.083279 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:35:11.086610 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:35:11.093283 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:35:11.097023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:35:11.099868 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
886 11:35:11.106700 0 10 8 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
887 11:35:11.109902 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
888 11:35:11.113178 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:35:11.119654 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:35:11.122898 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:35:11.126660 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:35:11.132929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:35:11.136675 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
894 11:35:11.139382 0 11 8 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
895 11:35:11.146391 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
896 11:35:11.149842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:35:11.152841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:35:11.159384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:35:11.162724 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:35:11.165998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:35:11.172878 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 11:35:11.176221 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:35:11.179766 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:35:11.186516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:35:11.189458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:35:11.193458 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:35:11.199323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:35:11.202947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:35:11.206269 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:35:11.212568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:35:11.215988 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:35:11.219191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:35:11.225884 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:35:11.229540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:35:11.232579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:35:11.239111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:35:11.242339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 11:35:11.245662 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:35:11.249114 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:35:11.252090 Total UI for P1: 0, mck2ui 16
921 11:35:11.256017 best dqsien dly found for B0: ( 0, 14, 6)
922 11:35:11.262794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:35:11.265828 Total UI for P1: 0, mck2ui 16
924 11:35:11.268905 best dqsien dly found for B1: ( 0, 14, 12)
925 11:35:11.272574 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 11:35:11.275545 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
927 11:35:11.275620
928 11:35:11.278851 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 11:35:11.282386 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
930 11:35:11.285541 [Gating] SW calibration Done
931 11:35:11.285639 ==
932 11:35:11.289017 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:35:11.292188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:35:11.292255 ==
935 11:35:11.295402 RX Vref Scan: 0
936 11:35:11.295495
937 11:35:11.295559 RX Vref 0 -> 0, step: 1
938 11:35:11.298761
939 11:35:11.298847 RX Delay -130 -> 252, step: 16
940 11:35:11.305666 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:35:11.308941 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:35:11.312024 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:35:11.315826 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:35:11.318648 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:35:11.325521 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:35:11.329008 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 11:35:11.331753 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 11:35:11.335216 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 11:35:11.338877 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 11:35:11.345402 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 11:35:11.349131 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:35:11.351835 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 11:35:11.354958 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 11:35:11.358280 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:35:11.365286 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 11:35:11.365361 ==
957 11:35:11.368171 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:35:11.371380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:35:11.371494 ==
960 11:35:11.371554 DQS Delay:
961 11:35:11.374675 DQS0 = 0, DQS1 = 0
962 11:35:11.374749 DQM Delay:
963 11:35:11.378259 DQM0 = 85, DQM1 = 71
964 11:35:11.378333 DQ Delay:
965 11:35:11.381399 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:35:11.384898 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 11:35:11.388454 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 11:35:11.391313 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 11:35:11.391387
970 11:35:11.391484
971 11:35:11.391539 ==
972 11:35:11.394933 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:35:11.401100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:35:11.401174 ==
975 11:35:11.401232
976 11:35:11.401284
977 11:35:11.401334 TX Vref Scan disable
978 11:35:11.404918 == TX Byte 0 ==
979 11:35:11.407957 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 11:35:11.414761 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 11:35:11.414835 == TX Byte 1 ==
982 11:35:11.418000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 11:35:11.424424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 11:35:11.424498 ==
985 11:35:11.428051 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:35:11.431335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:35:11.431410 ==
988 11:35:11.444144 TX Vref=22, minBit 13, minWin=26, winSum=437
989 11:35:11.447770 TX Vref=24, minBit 0, minWin=27, winSum=445
990 11:35:11.450631 TX Vref=26, minBit 8, minWin=27, winSum=446
991 11:35:11.454120 TX Vref=28, minBit 8, minWin=27, winSum=446
992 11:35:11.457269 TX Vref=30, minBit 8, minWin=27, winSum=447
993 11:35:11.463990 TX Vref=32, minBit 8, minWin=27, winSum=446
994 11:35:11.467602 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 30
995 11:35:11.467677
996 11:35:11.470750 Final TX Range 1 Vref 30
997 11:35:11.470824
998 11:35:11.470881 ==
999 11:35:11.474347 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:35:11.477736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:35:11.480520 ==
1002 11:35:11.480593
1003 11:35:11.480651
1004 11:35:11.480705 TX Vref Scan disable
1005 11:35:11.484228 == TX Byte 0 ==
1006 11:35:11.487896 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 11:35:11.494109 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 11:35:11.494184 == TX Byte 1 ==
1009 11:35:11.497743 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 11:35:11.504305 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 11:35:11.504380
1012 11:35:11.504438 [DATLAT]
1013 11:35:11.504491 Freq=800, CH0 RK0
1014 11:35:11.504541
1015 11:35:11.507297 DATLAT Default: 0xa
1016 11:35:11.507370 0, 0xFFFF, sum = 0
1017 11:35:11.510858 1, 0xFFFF, sum = 0
1018 11:35:11.514008 2, 0xFFFF, sum = 0
1019 11:35:11.514084 3, 0xFFFF, sum = 0
1020 11:35:11.517478 4, 0xFFFF, sum = 0
1021 11:35:11.517554 5, 0xFFFF, sum = 0
1022 11:35:11.520743 6, 0xFFFF, sum = 0
1023 11:35:11.520819 7, 0xFFFF, sum = 0
1024 11:35:11.523714 8, 0xFFFF, sum = 0
1025 11:35:11.523794 9, 0x0, sum = 1
1026 11:35:11.527723 10, 0x0, sum = 2
1027 11:35:11.527798 11, 0x0, sum = 3
1028 11:35:11.527858 12, 0x0, sum = 4
1029 11:35:11.530676 best_step = 10
1030 11:35:11.530750
1031 11:35:11.530807 ==
1032 11:35:11.534162 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:35:11.537289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:35:11.537364 ==
1035 11:35:11.540935 RX Vref Scan: 1
1036 11:35:11.541010
1037 11:35:11.543717 Set Vref Range= 32 -> 127
1038 11:35:11.543792
1039 11:35:11.543850 RX Vref 32 -> 127, step: 1
1040 11:35:11.543903
1041 11:35:11.547560 RX Delay -111 -> 252, step: 8
1042 11:35:11.547634
1043 11:35:11.550516 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:35:11.553790 [Byte1]: 32
1045 11:35:11.557392
1046 11:35:11.557467 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:35:11.560581 [Byte1]: 33
1048 11:35:11.565019
1049 11:35:11.565094 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:35:11.571396 [Byte1]: 34
1051 11:35:11.571495
1052 11:35:11.574529 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:35:11.578091 [Byte1]: 35
1054 11:35:11.578165
1055 11:35:11.581035 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:35:11.584365 [Byte1]: 36
1057 11:35:11.587571
1058 11:35:11.587645 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:35:11.591075 [Byte1]: 37
1060 11:35:11.595208
1061 11:35:11.595282 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:35:11.598432 [Byte1]: 38
1063 11:35:11.602715
1064 11:35:11.602790 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:35:11.606284 [Byte1]: 39
1066 11:35:11.610373
1067 11:35:11.610448 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:35:11.614064 [Byte1]: 40
1069 11:35:11.618192
1070 11:35:11.618266 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:35:11.621711 [Byte1]: 41
1072 11:35:11.625681
1073 11:35:11.625756 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:35:11.629262 [Byte1]: 42
1075 11:35:11.633928
1076 11:35:11.634006 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:35:11.636950 [Byte1]: 43
1078 11:35:11.641397
1079 11:35:11.641470 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:35:11.644763 [Byte1]: 44
1081 11:35:11.648712
1082 11:35:11.648786 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:35:11.652401 [Byte1]: 45
1084 11:35:11.656271
1085 11:35:11.656345 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:35:11.659958 [Byte1]: 46
1087 11:35:11.664092
1088 11:35:11.664166 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:35:11.670222 [Byte1]: 47
1090 11:35:11.670297
1091 11:35:11.673898 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:35:11.676884 [Byte1]: 48
1093 11:35:11.676959
1094 11:35:11.680194 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:35:11.683989 [Byte1]: 49
1096 11:35:11.687301
1097 11:35:11.687375 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:35:11.690684 [Byte1]: 50
1099 11:35:11.694897
1100 11:35:11.694970 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:35:11.698552 [Byte1]: 51
1102 11:35:11.702228
1103 11:35:11.702302 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:35:11.705671 [Byte1]: 52
1105 11:35:11.710279
1106 11:35:11.710353 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:35:11.713279 [Byte1]: 53
1108 11:35:11.717661
1109 11:35:11.717735 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:35:11.721057 [Byte1]: 54
1111 11:35:11.725249
1112 11:35:11.725322 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:35:11.728275 [Byte1]: 55
1114 11:35:11.733088
1115 11:35:11.733161 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:35:11.736347 [Byte1]: 56
1117 11:35:11.740665
1118 11:35:11.740738 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:35:11.743846 [Byte1]: 57
1120 11:35:11.748122
1121 11:35:11.748195 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:35:11.751762 [Byte1]: 58
1123 11:35:11.755888
1124 11:35:11.755962 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:35:11.759364 [Byte1]: 59
1126 11:35:11.763640
1127 11:35:11.763714 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:35:11.769710 [Byte1]: 60
1129 11:35:11.769785
1130 11:35:11.773096 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:35:11.776347 [Byte1]: 61
1132 11:35:11.776459
1133 11:35:11.779810 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:35:11.783335 [Byte1]: 62
1135 11:35:11.786665
1136 11:35:11.786740 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:35:11.790112 [Byte1]: 63
1138 11:35:11.794048
1139 11:35:11.794123 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:35:11.798305 [Byte1]: 64
1141 11:35:11.801903
1142 11:35:11.801977 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:35:11.804751 [Byte1]: 65
1144 11:35:11.809386
1145 11:35:11.809460 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:35:11.813017 [Byte1]: 66
1147 11:35:11.816964
1148 11:35:11.817040 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:35:11.820127 [Byte1]: 67
1150 11:35:11.824669
1151 11:35:11.824743 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:35:11.827927 [Byte1]: 68
1153 11:35:11.832130
1154 11:35:11.832205 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:35:11.835602 [Byte1]: 69
1156 11:35:11.840169
1157 11:35:11.840244 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:35:11.842973 [Byte1]: 70
1159 11:35:11.847591
1160 11:35:11.847666 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:35:11.850841 [Byte1]: 71
1162 11:35:11.854978
1163 11:35:11.855102 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:35:11.858721 [Byte1]: 72
1165 11:35:11.862825
1166 11:35:11.862900 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:35:11.865927 [Byte1]: 73
1168 11:35:11.870321
1169 11:35:11.870396 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:35:11.873817 [Byte1]: 74
1171 11:35:11.878563
1172 11:35:11.878639 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:35:11.881153 [Byte1]: 75
1174 11:35:11.885758
1175 11:35:11.885835 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:35:11.889043 [Byte1]: 76
1177 11:35:11.893202
1178 11:35:11.893279 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:35:11.896813 [Byte1]: 77
1180 11:35:11.901104
1181 11:35:11.901179 Set Vref, RX VrefLevel [Byte0]: 78
1182 11:35:11.904456 [Byte1]: 78
1183 11:35:11.908479
1184 11:35:11.908554 Set Vref, RX VrefLevel [Byte0]: 79
1185 11:35:11.911846 [Byte1]: 79
1186 11:35:11.916221
1187 11:35:11.916296 Set Vref, RX VrefLevel [Byte0]: 80
1188 11:35:11.919714 [Byte1]: 80
1189 11:35:11.924044
1190 11:35:11.924119 Set Vref, RX VrefLevel [Byte0]: 81
1191 11:35:11.927496 [Byte1]: 81
1192 11:35:11.931642
1193 11:35:11.931718 Set Vref, RX VrefLevel [Byte0]: 82
1194 11:35:11.934966 [Byte1]: 82
1195 11:35:11.939530
1196 11:35:11.939605 Final RX Vref Byte 0 = 62 to rank0
1197 11:35:11.942515 Final RX Vref Byte 1 = 51 to rank0
1198 11:35:11.945727 Final RX Vref Byte 0 = 62 to rank1
1199 11:35:11.949425 Final RX Vref Byte 1 = 51 to rank1==
1200 11:35:11.952531 Dram Type= 6, Freq= 0, CH_0, rank 0
1201 11:35:11.959587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 11:35:11.959664 ==
1203 11:35:11.959724 DQS Delay:
1204 11:35:11.959777 DQS0 = 0, DQS1 = 0
1205 11:35:11.962730 DQM Delay:
1206 11:35:11.962806 DQM0 = 87, DQM1 = 76
1207 11:35:11.966016 DQ Delay:
1208 11:35:11.969352 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1209 11:35:11.969428 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =100
1210 11:35:11.972488 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1211 11:35:11.979111 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1212 11:35:11.979186
1213 11:35:11.979244
1214 11:35:11.985752 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1215 11:35:11.989750 CH0 RK0: MR19=606, MR18=4122
1216 11:35:11.995815 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1217 11:35:11.995891
1218 11:35:11.999175 ----->DramcWriteLeveling(PI) begin...
1219 11:35:11.999251 ==
1220 11:35:12.002418 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 11:35:12.046703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 11:35:12.046781 ==
1223 11:35:12.046840 Write leveling (Byte 0): 32 => 32
1224 11:35:12.047087 Write leveling (Byte 1): 31 => 31
1225 11:35:12.047646 DramcWriteLeveling(PI) end<-----
1226 11:35:12.047721
1227 11:35:12.047779 ==
1228 11:35:12.047833 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 11:35:12.048094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 11:35:12.048153 ==
1231 11:35:12.048205 [Gating] SW mode calibration
1232 11:35:12.049145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1233 11:35:12.049496 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1234 11:35:12.049571 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 11:35:12.050034 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1236 11:35:12.090722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 11:35:12.091149 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1238 11:35:12.091714 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:35:12.091783 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:35:12.092021 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:35:12.092482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:35:12.093120 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:35:12.093381 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:35:12.093477 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:35:12.093562 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:35:12.107680 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:35:12.108167 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:35:12.108444 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:35:12.108534 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:35:12.114921 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:35:12.117968 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:35:12.121123 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1253 11:35:12.127794 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1254 11:35:12.131015 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:35:12.134167 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:35:12.138018 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:35:12.144316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:35:12.147539 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:35:12.154929 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:35:12.157715 0 9 8 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
1261 11:35:12.160838 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1262 11:35:12.167304 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 11:35:12.170568 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 11:35:12.174352 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 11:35:12.177360 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 11:35:12.183682 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 11:35:12.187330 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 11:35:12.190601 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
1269 11:35:12.197198 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1270 11:35:12.200664 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 11:35:12.203958 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 11:35:12.210237 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 11:35:12.213685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 11:35:12.216861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 11:35:12.223555 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 11:35:12.226900 0 11 8 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
1277 11:35:12.230450 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1278 11:35:12.236719 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 11:35:12.240452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 11:35:12.243606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 11:35:12.250096 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 11:35:12.253800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 11:35:12.256856 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 11:35:12.263548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1285 11:35:12.266758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:35:12.270014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:35:12.276477 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:35:12.279941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:35:12.283609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:35:12.290264 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:35:12.292985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:35:12.296473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:35:12.303002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:35:12.306662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 11:35:12.309682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 11:35:12.316724 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 11:35:12.319718 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 11:35:12.322871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 11:35:12.329948 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 11:35:12.332874 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1301 11:35:12.336299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1302 11:35:12.339622 Total UI for P1: 0, mck2ui 16
1303 11:35:12.342729 best dqsien dly found for B0: ( 0, 14, 10)
1304 11:35:12.349707 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1305 11:35:12.349783 Total UI for P1: 0, mck2ui 16
1306 11:35:12.356060 best dqsien dly found for B1: ( 0, 14, 10)
1307 11:35:12.359075 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1308 11:35:12.362729 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1309 11:35:12.362804
1310 11:35:12.366030 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1311 11:35:12.369327 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1312 11:35:12.372590 [Gating] SW calibration Done
1313 11:35:12.372665 ==
1314 11:35:12.375709 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 11:35:12.379345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 11:35:12.379453 ==
1317 11:35:12.382487 RX Vref Scan: 0
1318 11:35:12.382562
1319 11:35:12.382621 RX Vref 0 -> 0, step: 1
1320 11:35:12.382675
1321 11:35:12.385839 RX Delay -130 -> 252, step: 16
1322 11:35:12.392292 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1323 11:35:12.395736 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1324 11:35:12.399170 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1325 11:35:12.402586 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1326 11:35:12.405639 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1327 11:35:12.408916 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1328 11:35:12.415888 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1329 11:35:12.418959 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1330 11:35:12.422381 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1331 11:35:12.425324 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1332 11:35:12.432413 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1333 11:35:12.435741 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1334 11:35:12.438756 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1335 11:35:12.441984 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1336 11:35:12.445544 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1337 11:35:12.452041 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1338 11:35:12.452118 ==
1339 11:35:12.455175 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:35:12.458821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:35:12.458897 ==
1342 11:35:12.458957 DQS Delay:
1343 11:35:12.461717 DQS0 = 0, DQS1 = 0
1344 11:35:12.461792 DQM Delay:
1345 11:35:12.465472 DQM0 = 84, DQM1 = 77
1346 11:35:12.465547 DQ Delay:
1347 11:35:12.468460 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1348 11:35:12.471843 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1349 11:35:12.475300 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1350 11:35:12.478698 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1351 11:35:12.478773
1352 11:35:12.478831
1353 11:35:12.478901 ==
1354 11:35:12.482053 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 11:35:12.485765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 11:35:12.485841 ==
1357 11:35:12.488263
1358 11:35:12.488337
1359 11:35:12.488396 TX Vref Scan disable
1360 11:35:12.491897 == TX Byte 0 ==
1361 11:35:12.495264 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1362 11:35:12.498256 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1363 11:35:12.501865 == TX Byte 1 ==
1364 11:35:12.504856 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1365 11:35:12.508332 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1366 11:35:12.511774 ==
1367 11:35:12.511849 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 11:35:12.518001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 11:35:12.518077 ==
1370 11:35:12.530501 TX Vref=22, minBit 3, minWin=27, winSum=445
1371 11:35:12.533741 TX Vref=24, minBit 9, minWin=27, winSum=445
1372 11:35:12.537119 TX Vref=26, minBit 9, minWin=27, winSum=448
1373 11:35:12.540295 TX Vref=28, minBit 8, minWin=27, winSum=449
1374 11:35:12.543594 TX Vref=30, minBit 9, minWin=27, winSum=448
1375 11:35:12.549848 TX Vref=32, minBit 9, minWin=27, winSum=448
1376 11:35:12.553259 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
1377 11:35:12.553335
1378 11:35:12.556369 Final TX Range 1 Vref 28
1379 11:35:12.556443
1380 11:35:12.556501 ==
1381 11:35:12.560381 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 11:35:12.563235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:35:12.566846 ==
1384 11:35:12.566910
1385 11:35:12.567000
1386 11:35:12.567087 TX Vref Scan disable
1387 11:35:12.569964 == TX Byte 0 ==
1388 11:35:12.573508 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1389 11:35:12.580405 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1390 11:35:12.580479 == TX Byte 1 ==
1391 11:35:12.583744 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1392 11:35:12.586992 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1393 11:35:12.589921
1394 11:35:12.589993 [DATLAT]
1395 11:35:12.590049 Freq=800, CH0 RK1
1396 11:35:12.590101
1397 11:35:12.593390 DATLAT Default: 0xa
1398 11:35:12.593450 0, 0xFFFF, sum = 0
1399 11:35:12.596881 1, 0xFFFF, sum = 0
1400 11:35:12.596943 2, 0xFFFF, sum = 0
1401 11:35:12.600064 3, 0xFFFF, sum = 0
1402 11:35:12.600124 4, 0xFFFF, sum = 0
1403 11:35:12.603417 5, 0xFFFF, sum = 0
1404 11:35:12.606693 6, 0xFFFF, sum = 0
1405 11:35:12.606752 7, 0xFFFF, sum = 0
1406 11:35:12.610081 8, 0xFFFF, sum = 0
1407 11:35:12.610144 9, 0x0, sum = 1
1408 11:35:12.610197 10, 0x0, sum = 2
1409 11:35:12.613561 11, 0x0, sum = 3
1410 11:35:12.613620 12, 0x0, sum = 4
1411 11:35:12.616771 best_step = 10
1412 11:35:12.616829
1413 11:35:12.616887 ==
1414 11:35:12.620205 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 11:35:12.623318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 11:35:12.623379 ==
1417 11:35:12.627015 RX Vref Scan: 0
1418 11:35:12.627074
1419 11:35:12.627130 RX Vref 0 -> 0, step: 1
1420 11:35:12.627185
1421 11:35:12.629701 RX Delay -111 -> 252, step: 8
1422 11:35:12.636882 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1423 11:35:12.640057 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1424 11:35:12.643281 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1425 11:35:12.646700 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1426 11:35:12.653323 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1427 11:35:12.657064 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1428 11:35:12.660009 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1429 11:35:12.663376 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1430 11:35:12.666678 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1431 11:35:12.670231 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1432 11:35:12.676634 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1433 11:35:12.679750 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1434 11:35:12.683250 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1435 11:35:12.686615 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1436 11:35:12.692961 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1437 11:35:12.696327 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1438 11:35:12.696392 ==
1439 11:35:12.699432 Dram Type= 6, Freq= 0, CH_0, rank 1
1440 11:35:12.702785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:35:12.702871 ==
1442 11:35:12.706149 DQS Delay:
1443 11:35:12.706219 DQS0 = 0, DQS1 = 0
1444 11:35:12.706274 DQM Delay:
1445 11:35:12.709925 DQM0 = 84, DQM1 = 76
1446 11:35:12.709991 DQ Delay:
1447 11:35:12.713129 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1448 11:35:12.716141 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1449 11:35:12.719558 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1450 11:35:12.722626 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1451 11:35:12.722713
1452 11:35:12.722768
1453 11:35:12.732648 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1454 11:35:12.732727 CH0 RK1: MR19=606, MR18=4208
1455 11:35:12.739098 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1456 11:35:12.742749 [RxdqsGatingPostProcess] freq 800
1457 11:35:12.749651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1458 11:35:12.752573 Pre-setting of DQS Precalculation
1459 11:35:12.756317 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1460 11:35:12.756386 ==
1461 11:35:12.759161 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 11:35:12.766271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 11:35:12.766357 ==
1464 11:35:12.769292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 11:35:12.775812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 11:35:12.785232 [CA 0] Center 36 (6~67) winsize 62
1467 11:35:12.788413 [CA 1] Center 37 (6~68) winsize 63
1468 11:35:12.792198 [CA 2] Center 34 (4~65) winsize 62
1469 11:35:12.795843 [CA 3] Center 34 (3~65) winsize 63
1470 11:35:12.798828 [CA 4] Center 34 (4~65) winsize 62
1471 11:35:12.802216 [CA 5] Center 34 (3~65) winsize 63
1472 11:35:12.802280
1473 11:35:12.805331 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 11:35:12.805394
1475 11:35:12.808604 [CATrainingPosCal] consider 1 rank data
1476 11:35:12.812070 u2DelayCellTimex100 = 270/100 ps
1477 11:35:12.815135 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 11:35:12.821521 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1479 11:35:12.825013 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 11:35:12.828361 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1481 11:35:12.831417 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 11:35:12.834859 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 11:35:12.834922
1484 11:35:12.838337 CA PerBit enable=1, Macro0, CA PI delay=34
1485 11:35:12.838429
1486 11:35:12.841437 [CBTSetCACLKResult] CA Dly = 34
1487 11:35:12.841504 CS Dly: 5 (0~36)
1488 11:35:12.845054 ==
1489 11:35:12.848188 Dram Type= 6, Freq= 0, CH_1, rank 1
1490 11:35:12.851339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 11:35:12.851453 ==
1492 11:35:12.857913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1493 11:35:12.861183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1494 11:35:12.871406 [CA 0] Center 36 (6~67) winsize 62
1495 11:35:12.874985 [CA 1] Center 37 (6~68) winsize 63
1496 11:35:12.878190 [CA 2] Center 34 (4~65) winsize 62
1497 11:35:12.881747 [CA 3] Center 34 (4~65) winsize 62
1498 11:35:12.884877 [CA 4] Center 34 (4~65) winsize 62
1499 11:35:12.887992 [CA 5] Center 34 (4~64) winsize 61
1500 11:35:12.888079
1501 11:35:12.891313 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1502 11:35:12.891379
1503 11:35:12.894853 [CATrainingPosCal] consider 2 rank data
1504 11:35:12.897978 u2DelayCellTimex100 = 270/100 ps
1505 11:35:12.901144 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1506 11:35:12.907655 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1507 11:35:12.911177 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1508 11:35:12.914176 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1509 11:35:12.917982 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 11:35:12.921053 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1511 11:35:12.921122
1512 11:35:12.924222 CA PerBit enable=1, Macro0, CA PI delay=34
1513 11:35:12.924292
1514 11:35:12.927922 [CBTSetCACLKResult] CA Dly = 34
1515 11:35:12.927988 CS Dly: 5 (0~37)
1516 11:35:12.931085
1517 11:35:12.934135 ----->DramcWriteLeveling(PI) begin...
1518 11:35:12.934254 ==
1519 11:35:12.937815 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 11:35:12.940631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 11:35:12.940726 ==
1522 11:35:12.944352 Write leveling (Byte 0): 26 => 26
1523 11:35:12.947670 Write leveling (Byte 1): 29 => 29
1524 11:35:12.950962 DramcWriteLeveling(PI) end<-----
1525 11:35:12.951088
1526 11:35:12.951183 ==
1527 11:35:12.954191 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 11:35:12.957313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 11:35:12.957412 ==
1530 11:35:12.960846 [Gating] SW mode calibration
1531 11:35:12.967367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1532 11:35:12.974062 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1533 11:35:12.977229 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1534 11:35:12.980995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1535 11:35:12.987073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1536 11:35:12.990629 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:35:12.993715 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:35:13.000468 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:35:13.003892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:35:13.007119 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:35:13.013997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:35:13.017248 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:35:13.021133 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:35:13.027199 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:35:13.030312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:35:13.033552 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:35:13.040614 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:35:13.043814 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:35:13.046915 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1550 11:35:13.050414 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1551 11:35:13.057299 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:35:13.060351 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:35:13.063421 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:35:13.070052 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:35:13.073794 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:35:13.077046 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:35:13.083403 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:35:13.087080 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1559 11:35:13.089853 0 9 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
1560 11:35:13.096510 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 11:35:13.099891 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 11:35:13.103137 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 11:35:13.109719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 11:35:13.113356 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 11:35:13.116865 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 11:35:13.123095 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
1567 11:35:13.126429 0 10 8 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)
1568 11:35:13.130001 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 11:35:13.136815 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 11:35:13.140057 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 11:35:13.142964 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 11:35:13.149907 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 11:35:13.152987 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 11:35:13.156037 0 11 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1575 11:35:13.163067 0 11 8 | B1->B0 | 4343 3f3f | 0 1 | (0 0) (0 0)
1576 11:35:13.166261 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 11:35:13.169611 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 11:35:13.176069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 11:35:13.179215 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 11:35:13.182683 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 11:35:13.189275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 11:35:13.192576 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1583 11:35:13.195902 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1584 11:35:13.202592 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:35:13.205931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:35:13.209369 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 11:35:13.215783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:35:13.219099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:35:13.222258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:35:13.229681 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:35:13.232560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 11:35:13.235604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 11:35:13.242390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 11:35:13.245883 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 11:35:13.249251 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 11:35:13.255342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 11:35:13.258954 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 11:35:13.262157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1599 11:35:13.268712 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1600 11:35:13.268806 Total UI for P1: 0, mck2ui 16
1601 11:35:13.272145 best dqsien dly found for B0: ( 0, 14, 4)
1602 11:35:13.278539 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1603 11:35:13.281938 Total UI for P1: 0, mck2ui 16
1604 11:35:13.285316 best dqsien dly found for B1: ( 0, 14, 8)
1605 11:35:13.288897 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1606 11:35:13.292336 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1607 11:35:13.292436
1608 11:35:13.295630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1609 11:35:13.298342 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1610 11:35:13.301619 [Gating] SW calibration Done
1611 11:35:13.301714 ==
1612 11:35:13.305381 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 11:35:13.308589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 11:35:13.308683 ==
1615 11:35:13.311692 RX Vref Scan: 0
1616 11:35:13.311790
1617 11:35:13.311854 RX Vref 0 -> 0, step: 1
1618 11:35:13.315354
1619 11:35:13.315489 RX Delay -130 -> 252, step: 16
1620 11:35:13.322116 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1621 11:35:13.325212 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1622 11:35:13.328457 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1623 11:35:13.331737 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1624 11:35:13.335246 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1625 11:35:13.341487 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1626 11:35:13.344851 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1627 11:35:13.348340 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1628 11:35:13.351642 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1629 11:35:13.354991 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1630 11:35:13.361340 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1631 11:35:13.364739 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1632 11:35:13.368348 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1633 11:35:13.371550 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1634 11:35:13.378153 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1635 11:35:13.381403 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1636 11:35:13.381478 ==
1637 11:35:13.385029 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 11:35:13.388055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 11:35:13.388131 ==
1640 11:35:13.388191 DQS Delay:
1641 11:35:13.391218 DQS0 = 0, DQS1 = 0
1642 11:35:13.391293 DQM Delay:
1643 11:35:13.394887 DQM0 = 89, DQM1 = 78
1644 11:35:13.394962 DQ Delay:
1645 11:35:13.398247 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1646 11:35:13.401451 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1647 11:35:13.404735 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1648 11:35:13.408523 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1649 11:35:13.408598
1650 11:35:13.408656
1651 11:35:13.408709 ==
1652 11:35:13.411623 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 11:35:13.418215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 11:35:13.418290 ==
1655 11:35:13.418349
1656 11:35:13.418403
1657 11:35:13.418453 TX Vref Scan disable
1658 11:35:13.421804 == TX Byte 0 ==
1659 11:35:13.424575 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1660 11:35:13.431183 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1661 11:35:13.431258 == TX Byte 1 ==
1662 11:35:13.434657 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 11:35:13.440971 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 11:35:13.441045 ==
1665 11:35:13.444348 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 11:35:13.448105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 11:35:13.448180 ==
1668 11:35:13.460541 TX Vref=22, minBit 8, minWin=26, winSum=441
1669 11:35:13.463847 TX Vref=24, minBit 0, minWin=27, winSum=443
1670 11:35:13.467419 TX Vref=26, minBit 10, minWin=27, winSum=450
1671 11:35:13.470682 TX Vref=28, minBit 13, minWin=27, winSum=452
1672 11:35:13.473827 TX Vref=30, minBit 10, minWin=27, winSum=449
1673 11:35:13.480462 TX Vref=32, minBit 8, minWin=27, winSum=448
1674 11:35:13.483815 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1675 11:35:13.483890
1676 11:35:13.486687 Final TX Range 1 Vref 28
1677 11:35:13.486762
1678 11:35:13.486820 ==
1679 11:35:13.490099 Dram Type= 6, Freq= 0, CH_1, rank 0
1680 11:35:13.496812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1681 11:35:13.496887 ==
1682 11:35:13.496945
1683 11:35:13.496998
1684 11:35:13.497048 TX Vref Scan disable
1685 11:35:13.500851 == TX Byte 0 ==
1686 11:35:13.503834 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1687 11:35:13.510910 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1688 11:35:13.510985 == TX Byte 1 ==
1689 11:35:13.514076 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1690 11:35:13.520543 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1691 11:35:13.520617
1692 11:35:13.520675 [DATLAT]
1693 11:35:13.520729 Freq=800, CH1 RK0
1694 11:35:13.520780
1695 11:35:13.523688 DATLAT Default: 0xa
1696 11:35:13.523763 0, 0xFFFF, sum = 0
1697 11:35:13.527042 1, 0xFFFF, sum = 0
1698 11:35:13.527117 2, 0xFFFF, sum = 0
1699 11:35:13.530188 3, 0xFFFF, sum = 0
1700 11:35:13.534008 4, 0xFFFF, sum = 0
1701 11:35:13.534084 5, 0xFFFF, sum = 0
1702 11:35:13.537170 6, 0xFFFF, sum = 0
1703 11:35:13.537246 7, 0xFFFF, sum = 0
1704 11:35:13.540391 8, 0xFFFF, sum = 0
1705 11:35:13.540468 9, 0x0, sum = 1
1706 11:35:13.543554 10, 0x0, sum = 2
1707 11:35:13.543630 11, 0x0, sum = 3
1708 11:35:13.543690 12, 0x0, sum = 4
1709 11:35:13.547165 best_step = 10
1710 11:35:13.547240
1711 11:35:13.547298 ==
1712 11:35:13.550255 Dram Type= 6, Freq= 0, CH_1, rank 0
1713 11:35:13.553656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1714 11:35:13.553731 ==
1715 11:35:13.556759 RX Vref Scan: 1
1716 11:35:13.556833
1717 11:35:13.560662 Set Vref Range= 32 -> 127
1718 11:35:13.560738
1719 11:35:13.560797 RX Vref 32 -> 127, step: 1
1720 11:35:13.560851
1721 11:35:13.563569 RX Delay -95 -> 252, step: 8
1722 11:35:13.563644
1723 11:35:13.566391 Set Vref, RX VrefLevel [Byte0]: 32
1724 11:35:13.570131 [Byte1]: 32
1725 11:35:13.573527
1726 11:35:13.573602 Set Vref, RX VrefLevel [Byte0]: 33
1727 11:35:13.576740 [Byte1]: 33
1728 11:35:13.581142
1729 11:35:13.581216 Set Vref, RX VrefLevel [Byte0]: 34
1730 11:35:13.584252 [Byte1]: 34
1731 11:35:13.588502
1732 11:35:13.588576 Set Vref, RX VrefLevel [Byte0]: 35
1733 11:35:13.591800 [Byte1]: 35
1734 11:35:13.596310
1735 11:35:13.599212 Set Vref, RX VrefLevel [Byte0]: 36
1736 11:35:13.602431 [Byte1]: 36
1737 11:35:13.602506
1738 11:35:13.605745 Set Vref, RX VrefLevel [Byte0]: 37
1739 11:35:13.609332 [Byte1]: 37
1740 11:35:13.609406
1741 11:35:13.612483 Set Vref, RX VrefLevel [Byte0]: 38
1742 11:35:13.615829 [Byte1]: 38
1743 11:35:13.615904
1744 11:35:13.619058 Set Vref, RX VrefLevel [Byte0]: 39
1745 11:35:13.622356 [Byte1]: 39
1746 11:35:13.626510
1747 11:35:13.626584 Set Vref, RX VrefLevel [Byte0]: 40
1748 11:35:13.633142 [Byte1]: 40
1749 11:35:13.633217
1750 11:35:13.636174 Set Vref, RX VrefLevel [Byte0]: 41
1751 11:35:13.639786 [Byte1]: 41
1752 11:35:13.639862
1753 11:35:13.642823 Set Vref, RX VrefLevel [Byte0]: 42
1754 11:35:13.646661 [Byte1]: 42
1755 11:35:13.646737
1756 11:35:13.649689 Set Vref, RX VrefLevel [Byte0]: 43
1757 11:35:13.653028 [Byte1]: 43
1758 11:35:13.656671
1759 11:35:13.656747 Set Vref, RX VrefLevel [Byte0]: 44
1760 11:35:13.660252 [Byte1]: 44
1761 11:35:13.664683
1762 11:35:13.664759 Set Vref, RX VrefLevel [Byte0]: 45
1763 11:35:13.667785 [Byte1]: 45
1764 11:35:13.672039
1765 11:35:13.672129 Set Vref, RX VrefLevel [Byte0]: 46
1766 11:35:13.675460 [Byte1]: 46
1767 11:35:13.679835
1768 11:35:13.679925 Set Vref, RX VrefLevel [Byte0]: 47
1769 11:35:13.682798 [Byte1]: 47
1770 11:35:13.687186
1771 11:35:13.687276 Set Vref, RX VrefLevel [Byte0]: 48
1772 11:35:13.690565 [Byte1]: 48
1773 11:35:13.695091
1774 11:35:13.695160 Set Vref, RX VrefLevel [Byte0]: 49
1775 11:35:13.698443 [Byte1]: 49
1776 11:35:13.702573
1777 11:35:13.702641 Set Vref, RX VrefLevel [Byte0]: 50
1778 11:35:13.706060 [Byte1]: 50
1779 11:35:13.710345
1780 11:35:13.710422 Set Vref, RX VrefLevel [Byte0]: 51
1781 11:35:13.714083 [Byte1]: 51
1782 11:35:13.717518
1783 11:35:13.717592 Set Vref, RX VrefLevel [Byte0]: 52
1784 11:35:13.720973 [Byte1]: 52
1785 11:35:13.725451
1786 11:35:13.725525 Set Vref, RX VrefLevel [Byte0]: 53
1787 11:35:13.728781 [Byte1]: 53
1788 11:35:13.732872
1789 11:35:13.732946 Set Vref, RX VrefLevel [Byte0]: 54
1790 11:35:13.736307 [Byte1]: 54
1791 11:35:13.740608
1792 11:35:13.740683 Set Vref, RX VrefLevel [Byte0]: 55
1793 11:35:13.743840 [Byte1]: 55
1794 11:35:13.748171
1795 11:35:13.748245 Set Vref, RX VrefLevel [Byte0]: 56
1796 11:35:13.751395 [Byte1]: 56
1797 11:35:13.755685
1798 11:35:13.755759 Set Vref, RX VrefLevel [Byte0]: 57
1799 11:35:13.759170 [Byte1]: 57
1800 11:35:13.763546
1801 11:35:13.763621 Set Vref, RX VrefLevel [Byte0]: 58
1802 11:35:13.766455 [Byte1]: 58
1803 11:35:13.771070
1804 11:35:13.771144 Set Vref, RX VrefLevel [Byte0]: 59
1805 11:35:13.774199 [Byte1]: 59
1806 11:35:13.778429
1807 11:35:13.778504 Set Vref, RX VrefLevel [Byte0]: 60
1808 11:35:13.781900 [Byte1]: 60
1809 11:35:13.786087
1810 11:35:13.786161 Set Vref, RX VrefLevel [Byte0]: 61
1811 11:35:13.789362 [Byte1]: 61
1812 11:35:13.793960
1813 11:35:13.794035 Set Vref, RX VrefLevel [Byte0]: 62
1814 11:35:13.797007 [Byte1]: 62
1815 11:35:13.801784
1816 11:35:13.801858 Set Vref, RX VrefLevel [Byte0]: 63
1817 11:35:13.804449 [Byte1]: 63
1818 11:35:13.809023
1819 11:35:13.809097 Set Vref, RX VrefLevel [Byte0]: 64
1820 11:35:13.812023 [Byte1]: 64
1821 11:35:13.816808
1822 11:35:13.816882 Set Vref, RX VrefLevel [Byte0]: 65
1823 11:35:13.819851 [Byte1]: 65
1824 11:35:13.823876
1825 11:35:13.823950 Set Vref, RX VrefLevel [Byte0]: 66
1826 11:35:13.831339 [Byte1]: 66
1827 11:35:13.831435
1828 11:35:13.833876 Set Vref, RX VrefLevel [Byte0]: 67
1829 11:35:13.837267 [Byte1]: 67
1830 11:35:13.837341
1831 11:35:13.840633 Set Vref, RX VrefLevel [Byte0]: 68
1832 11:35:13.844195 [Byte1]: 68
1833 11:35:13.844269
1834 11:35:13.847131 Set Vref, RX VrefLevel [Byte0]: 69
1835 11:35:13.850236 [Byte1]: 69
1836 11:35:13.854671
1837 11:35:13.854768 Set Vref, RX VrefLevel [Byte0]: 70
1838 11:35:13.857539 [Byte1]: 70
1839 11:35:13.862165
1840 11:35:13.862240 Set Vref, RX VrefLevel [Byte0]: 71
1841 11:35:13.865379 [Byte1]: 71
1842 11:35:13.870015
1843 11:35:13.870090 Set Vref, RX VrefLevel [Byte0]: 72
1844 11:35:13.873021 [Byte1]: 72
1845 11:35:13.877679
1846 11:35:13.877752 Set Vref, RX VrefLevel [Byte0]: 73
1847 11:35:13.880667 [Byte1]: 73
1848 11:35:13.885045
1849 11:35:13.885121 Set Vref, RX VrefLevel [Byte0]: 74
1850 11:35:13.887920 [Byte1]: 74
1851 11:35:13.892960
1852 11:35:13.893053 Set Vref, RX VrefLevel [Byte0]: 75
1853 11:35:13.895641 [Byte1]: 75
1854 11:35:13.899851
1855 11:35:13.899933 Set Vref, RX VrefLevel [Byte0]: 76
1856 11:35:13.903343 [Byte1]: 76
1857 11:35:13.908151
1858 11:35:13.908223 Set Vref, RX VrefLevel [Byte0]: 77
1859 11:35:13.911162 [Byte1]: 77
1860 11:35:13.915249
1861 11:35:13.915338 Final RX Vref Byte 0 = 55 to rank0
1862 11:35:13.918565 Final RX Vref Byte 1 = 63 to rank0
1863 11:35:13.922376 Final RX Vref Byte 0 = 55 to rank1
1864 11:35:13.925353 Final RX Vref Byte 1 = 63 to rank1==
1865 11:35:13.928370 Dram Type= 6, Freq= 0, CH_1, rank 0
1866 11:35:13.935291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 11:35:13.935387 ==
1868 11:35:13.935497 DQS Delay:
1869 11:35:13.935552 DQS0 = 0, DQS1 = 0
1870 11:35:13.938169 DQM Delay:
1871 11:35:13.938231 DQM0 = 86, DQM1 = 79
1872 11:35:13.941748 DQ Delay:
1873 11:35:13.944798 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1874 11:35:13.948331 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1875 11:35:13.951904 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1876 11:35:13.955251 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1877 11:35:13.955328
1878 11:35:13.955386
1879 11:35:13.961872 [DQSOSCAuto] RK0, (LSB)MR18= 0x331e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1880 11:35:13.965124 CH1 RK0: MR19=606, MR18=331E
1881 11:35:13.971357 CH1_RK0: MR19=0x606, MR18=0x331E, DQSOSC=396, MR23=63, INC=94, DEC=62
1882 11:35:13.971435
1883 11:35:13.974964 ----->DramcWriteLeveling(PI) begin...
1884 11:35:13.975059 ==
1885 11:35:13.978147 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 11:35:13.982275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 11:35:13.982364 ==
1888 11:35:13.984941 Write leveling (Byte 0): 26 => 26
1889 11:35:13.987878 Write leveling (Byte 1): 31 => 31
1890 11:35:13.991521 DramcWriteLeveling(PI) end<-----
1891 11:35:13.991610
1892 11:35:13.991690 ==
1893 11:35:13.994657 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 11:35:13.997866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 11:35:13.997935 ==
1896 11:35:14.001166 [Gating] SW mode calibration
1897 11:35:14.007936 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1898 11:35:14.014957 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1899 11:35:14.018172 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1900 11:35:14.024498 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1901 11:35:14.028292 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1902 11:35:14.031392 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:35:14.034438 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:35:14.041092 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:35:14.044521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:35:14.047815 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:35:14.054620 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:35:14.057641 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:35:14.061134 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:35:14.067885 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:35:14.070849 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:35:14.074487 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:35:14.080770 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:35:14.084309 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:35:14.087647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1916 11:35:14.094112 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:35:14.098081 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1918 11:35:14.100924 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:35:14.107277 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:35:14.110634 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:35:14.114063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:35:14.120395 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:35:14.123719 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:35:14.127194 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:35:14.133699 0 9 8 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
1926 11:35:14.137200 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 11:35:14.140419 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 11:35:14.147108 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 11:35:14.150346 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 11:35:14.153951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 11:35:14.160320 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 11:35:14.163630 0 10 4 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 1)
1933 11:35:14.166830 0 10 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 1)
1934 11:35:14.173626 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 11:35:14.176768 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 11:35:14.180184 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 11:35:14.186859 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 11:35:14.190217 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 11:35:14.193295 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 11:35:14.200139 0 11 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1941 11:35:14.204108 0 11 8 | B1->B0 | 4141 3b3b | 0 1 | (0 0) (0 0)
1942 11:35:14.206782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 11:35:14.213398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 11:35:14.216804 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 11:35:14.219805 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 11:35:14.226540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 11:35:14.229552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1948 11:35:14.233115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1949 11:35:14.239343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:35:14.243185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:35:14.246616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:35:14.253074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 11:35:14.256182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 11:35:14.259745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 11:35:14.266292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 11:35:14.269253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 11:35:14.272576 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 11:35:14.279563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 11:35:14.282943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 11:35:14.285915 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 11:35:14.292300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 11:35:14.295801 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 11:35:14.299294 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 11:35:14.305463 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 11:35:14.309237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1966 11:35:14.312397 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1967 11:35:14.315902 Total UI for P1: 0, mck2ui 16
1968 11:35:14.319235 best dqsien dly found for B0: ( 0, 14, 8)
1969 11:35:14.322241 Total UI for P1: 0, mck2ui 16
1970 11:35:14.325466 best dqsien dly found for B1: ( 0, 14, 8)
1971 11:35:14.329126 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1972 11:35:14.332720 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1973 11:35:14.332806
1974 11:35:14.335291 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1975 11:35:14.342185 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1976 11:35:14.342256 [Gating] SW calibration Done
1977 11:35:14.342314 ==
1978 11:35:14.345438 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 11:35:14.351880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 11:35:14.351969 ==
1981 11:35:14.352056 RX Vref Scan: 0
1982 11:35:14.352138
1983 11:35:14.355483 RX Vref 0 -> 0, step: 1
1984 11:35:14.355582
1985 11:35:14.358698 RX Delay -130 -> 252, step: 16
1986 11:35:14.361795 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1987 11:35:14.365277 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1988 11:35:14.368769 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1989 11:35:14.375339 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1990 11:35:14.378320 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1991 11:35:14.382124 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1992 11:35:14.385264 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1993 11:35:14.388282 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1994 11:35:14.395301 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1995 11:35:14.398339 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1996 11:35:14.401422 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1997 11:35:14.405110 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1998 11:35:14.411516 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1999 11:35:14.415322 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2000 11:35:14.418536 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2001 11:35:14.421335 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2002 11:35:14.421432 ==
2003 11:35:14.425323 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:35:14.427957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:35:14.431415 ==
2006 11:35:14.431545 DQS Delay:
2007 11:35:14.431626 DQS0 = 0, DQS1 = 0
2008 11:35:14.435216 DQM Delay:
2009 11:35:14.435276 DQM0 = 86, DQM1 = 78
2010 11:35:14.438161 DQ Delay:
2011 11:35:14.441713 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2012 11:35:14.444919 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2013 11:35:14.448527 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2014 11:35:14.451258 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2015 11:35:14.451351
2016 11:35:14.451482
2017 11:35:14.451568 ==
2018 11:35:14.454683 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 11:35:14.458121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 11:35:14.458212 ==
2021 11:35:14.458294
2022 11:35:14.458372
2023 11:35:14.461564 TX Vref Scan disable
2024 11:35:14.461654 == TX Byte 0 ==
2025 11:35:14.468196 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2026 11:35:14.471179 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2027 11:35:14.471246 == TX Byte 1 ==
2028 11:35:14.477662 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2029 11:35:14.481429 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2030 11:35:14.481516 ==
2031 11:35:14.484594 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:35:14.488131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:35:14.488196 ==
2034 11:35:14.501951 TX Vref=22, minBit 8, minWin=26, winSum=442
2035 11:35:14.505193 TX Vref=24, minBit 1, minWin=27, winSum=445
2036 11:35:14.508890 TX Vref=26, minBit 15, minWin=27, winSum=452
2037 11:35:14.512282 TX Vref=28, minBit 15, minWin=27, winSum=451
2038 11:35:14.515713 TX Vref=30, minBit 8, minWin=27, winSum=453
2039 11:35:14.521870 TX Vref=32, minBit 8, minWin=27, winSum=453
2040 11:35:14.525322 [TxChooseVref] Worse bit 8, Min win 27, Win sum 453, Final Vref 30
2041 11:35:14.525409
2042 11:35:14.528498 Final TX Range 1 Vref 30
2043 11:35:14.528562
2044 11:35:14.528615 ==
2045 11:35:14.531973 Dram Type= 6, Freq= 0, CH_1, rank 1
2046 11:35:14.535243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2047 11:35:14.539231 ==
2048 11:35:14.539319
2049 11:35:14.539399
2050 11:35:14.539502 TX Vref Scan disable
2051 11:35:14.542187 == TX Byte 0 ==
2052 11:35:14.545256 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2053 11:35:14.552373 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2054 11:35:14.552466 == TX Byte 1 ==
2055 11:35:14.555523 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2056 11:35:14.562522 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2057 11:35:14.562617
2058 11:35:14.562709 [DATLAT]
2059 11:35:14.562793 Freq=800, CH1 RK1
2060 11:35:14.562873
2061 11:35:14.565202 DATLAT Default: 0xa
2062 11:35:14.565289 0, 0xFFFF, sum = 0
2063 11:35:14.568391 1, 0xFFFF, sum = 0
2064 11:35:14.571967 2, 0xFFFF, sum = 0
2065 11:35:14.572055 3, 0xFFFF, sum = 0
2066 11:35:14.575027 4, 0xFFFF, sum = 0
2067 11:35:14.575114 5, 0xFFFF, sum = 0
2068 11:35:14.578245 6, 0xFFFF, sum = 0
2069 11:35:14.578322 7, 0xFFFF, sum = 0
2070 11:35:14.582199 8, 0xFFFF, sum = 0
2071 11:35:14.582274 9, 0x0, sum = 1
2072 11:35:14.585307 10, 0x0, sum = 2
2073 11:35:14.585383 11, 0x0, sum = 3
2074 11:35:14.588702 12, 0x0, sum = 4
2075 11:35:14.588778 best_step = 10
2076 11:35:14.588835
2077 11:35:14.588889 ==
2078 11:35:14.592186 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 11:35:14.595161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 11:35:14.595236 ==
2081 11:35:14.598905 RX Vref Scan: 0
2082 11:35:14.598979
2083 11:35:14.601723 RX Vref 0 -> 0, step: 1
2084 11:35:14.601797
2085 11:35:14.601854 RX Delay -95 -> 252, step: 8
2086 11:35:14.609052 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2087 11:35:14.612565 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2088 11:35:14.615406 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2089 11:35:14.619167 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2090 11:35:14.622707 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2091 11:35:14.628725 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2092 11:35:14.632464 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2093 11:35:14.635614 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2094 11:35:14.638680 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2095 11:35:14.642047 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2096 11:35:14.648699 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2097 11:35:14.651967 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2098 11:35:14.655304 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2099 11:35:14.658549 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2100 11:35:14.665253 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2101 11:35:14.668928 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2102 11:35:14.669003 ==
2103 11:35:14.671949 Dram Type= 6, Freq= 0, CH_1, rank 1
2104 11:35:14.675243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2105 11:35:14.675319 ==
2106 11:35:14.675377 DQS Delay:
2107 11:35:14.678618 DQS0 = 0, DQS1 = 0
2108 11:35:14.678693 DQM Delay:
2109 11:35:14.681911 DQM0 = 87, DQM1 = 78
2110 11:35:14.681986 DQ Delay:
2111 11:35:14.685830 DQ0 =88, DQ1 =80, DQ2 =80, DQ3 =84
2112 11:35:14.688567 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2113 11:35:14.692047 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2114 11:35:14.695608 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2115 11:35:14.695683
2116 11:35:14.695741
2117 11:35:14.705118 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2118 11:35:14.705194 CH1 RK1: MR19=606, MR18=1B13
2119 11:35:14.712026 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2120 11:35:14.715332 [RxdqsGatingPostProcess] freq 800
2121 11:35:14.721841 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2122 11:35:14.725583 Pre-setting of DQS Precalculation
2123 11:35:14.728647 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2124 11:35:14.735381 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2125 11:35:14.745045 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2126 11:35:14.745121
2127 11:35:14.745180
2128 11:35:14.748385 [Calibration Summary] 1600 Mbps
2129 11:35:14.748459 CH 0, Rank 0
2130 11:35:14.751889 SW Impedance : PASS
2131 11:35:14.751963 DUTY Scan : NO K
2132 11:35:14.755314 ZQ Calibration : PASS
2133 11:35:14.755412 Jitter Meter : NO K
2134 11:35:14.758365 CBT Training : PASS
2135 11:35:14.761642 Write leveling : PASS
2136 11:35:14.761784 RX DQS gating : PASS
2137 11:35:14.764969 RX DQ/DQS(RDDQC) : PASS
2138 11:35:14.768515 TX DQ/DQS : PASS
2139 11:35:14.768592 RX DATLAT : PASS
2140 11:35:14.771754 RX DQ/DQS(Engine): PASS
2141 11:35:14.774901 TX OE : NO K
2142 11:35:14.774976 All Pass.
2143 11:35:14.775035
2144 11:35:14.775098 CH 0, Rank 1
2145 11:35:14.778318 SW Impedance : PASS
2146 11:35:14.781602 DUTY Scan : NO K
2147 11:35:14.781680 ZQ Calibration : PASS
2148 11:35:14.784690 Jitter Meter : NO K
2149 11:35:14.788115 CBT Training : PASS
2150 11:35:14.788190 Write leveling : PASS
2151 11:35:14.791498 RX DQS gating : PASS
2152 11:35:14.794940 RX DQ/DQS(RDDQC) : PASS
2153 11:35:14.795014 TX DQ/DQS : PASS
2154 11:35:14.798339 RX DATLAT : PASS
2155 11:35:14.801444 RX DQ/DQS(Engine): PASS
2156 11:35:14.801519 TX OE : NO K
2157 11:35:14.804803 All Pass.
2158 11:35:14.804878
2159 11:35:14.804936 CH 1, Rank 0
2160 11:35:14.807881 SW Impedance : PASS
2161 11:35:14.807955 DUTY Scan : NO K
2162 11:35:14.811247 ZQ Calibration : PASS
2163 11:35:14.814463 Jitter Meter : NO K
2164 11:35:14.814537 CBT Training : PASS
2165 11:35:14.817771 Write leveling : PASS
2166 11:35:14.821174 RX DQS gating : PASS
2167 11:35:14.821248 RX DQ/DQS(RDDQC) : PASS
2168 11:35:14.824382 TX DQ/DQS : PASS
2169 11:35:14.824456 RX DATLAT : PASS
2170 11:35:14.828019 RX DQ/DQS(Engine): PASS
2171 11:35:14.831044 TX OE : NO K
2172 11:35:14.831119 All Pass.
2173 11:35:14.831176
2174 11:35:14.831228 CH 1, Rank 1
2175 11:35:14.834524 SW Impedance : PASS
2176 11:35:14.837710 DUTY Scan : NO K
2177 11:35:14.837784 ZQ Calibration : PASS
2178 11:35:14.841463 Jitter Meter : NO K
2179 11:35:14.844545 CBT Training : PASS
2180 11:35:14.844619 Write leveling : PASS
2181 11:35:14.847635 RX DQS gating : PASS
2182 11:35:14.850886 RX DQ/DQS(RDDQC) : PASS
2183 11:35:14.850960 TX DQ/DQS : PASS
2184 11:35:14.854008 RX DATLAT : PASS
2185 11:35:14.857485 RX DQ/DQS(Engine): PASS
2186 11:35:14.857559 TX OE : NO K
2187 11:35:14.860958 All Pass.
2188 11:35:14.861032
2189 11:35:14.861090 DramC Write-DBI off
2190 11:35:14.864554 PER_BANK_REFRESH: Hybrid Mode
2191 11:35:14.864630 TX_TRACKING: ON
2192 11:35:14.867553 [GetDramInforAfterCalByMRR] Vendor 6.
2193 11:35:14.874060 [GetDramInforAfterCalByMRR] Revision 606.
2194 11:35:14.877444 [GetDramInforAfterCalByMRR] Revision 2 0.
2195 11:35:14.877519 MR0 0x3b3b
2196 11:35:14.877577 MR8 0x5151
2197 11:35:14.880903 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2198 11:35:14.880978
2199 11:35:14.883996 MR0 0x3b3b
2200 11:35:14.884070 MR8 0x5151
2201 11:35:14.887580 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2202 11:35:14.887655
2203 11:35:14.897204 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2204 11:35:14.900320 [FAST_K] Save calibration result to emmc
2205 11:35:14.904630 [FAST_K] Save calibration result to emmc
2206 11:35:14.907174 dram_init: config_dvfs: 1
2207 11:35:14.910654 dramc_set_vcore_voltage set vcore to 662500
2208 11:35:14.913825 Read voltage for 1200, 2
2209 11:35:14.913900 Vio18 = 0
2210 11:35:14.913957 Vcore = 662500
2211 11:35:14.916991 Vdram = 0
2212 11:35:14.917065 Vddq = 0
2213 11:35:14.917123 Vmddr = 0
2214 11:35:14.923562 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2215 11:35:14.926852 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2216 11:35:14.930251 MEM_TYPE=3, freq_sel=15
2217 11:35:14.933729 sv_algorithm_assistance_LP4_1600
2218 11:35:14.936935 ============ PULL DRAM RESETB DOWN ============
2219 11:35:14.940733 ========== PULL DRAM RESETB DOWN end =========
2220 11:35:14.946809 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2221 11:35:14.950310 ===================================
2222 11:35:14.953543 LPDDR4 DRAM CONFIGURATION
2223 11:35:14.953618 ===================================
2224 11:35:14.956981 EX_ROW_EN[0] = 0x0
2225 11:35:14.960217 EX_ROW_EN[1] = 0x0
2226 11:35:14.960291 LP4Y_EN = 0x0
2227 11:35:14.963693 WORK_FSP = 0x0
2228 11:35:14.963767 WL = 0x4
2229 11:35:14.967265 RL = 0x4
2230 11:35:14.967362 BL = 0x2
2231 11:35:14.970719 RPST = 0x0
2232 11:35:14.970793 RD_PRE = 0x0
2233 11:35:14.973551 WR_PRE = 0x1
2234 11:35:14.973625 WR_PST = 0x0
2235 11:35:14.976964 DBI_WR = 0x0
2236 11:35:14.977037 DBI_RD = 0x0
2237 11:35:14.980178 OTF = 0x1
2238 11:35:14.983442 ===================================
2239 11:35:14.986766 ===================================
2240 11:35:14.986841 ANA top config
2241 11:35:14.990264 ===================================
2242 11:35:14.993427 DLL_ASYNC_EN = 0
2243 11:35:14.996835 ALL_SLAVE_EN = 0
2244 11:35:14.999773 NEW_RANK_MODE = 1
2245 11:35:14.999847 DLL_IDLE_MODE = 1
2246 11:35:15.003090 LP45_APHY_COMB_EN = 1
2247 11:35:15.006763 TX_ODT_DIS = 1
2248 11:35:15.009631 NEW_8X_MODE = 1
2249 11:35:15.013039 ===================================
2250 11:35:15.016959 ===================================
2251 11:35:15.019689 data_rate = 2400
2252 11:35:15.023638 CKR = 1
2253 11:35:15.023712 DQ_P2S_RATIO = 8
2254 11:35:15.026708 ===================================
2255 11:35:15.029903 CA_P2S_RATIO = 8
2256 11:35:15.033000 DQ_CA_OPEN = 0
2257 11:35:15.036268 DQ_SEMI_OPEN = 0
2258 11:35:15.039720 CA_SEMI_OPEN = 0
2259 11:35:15.039812 CA_FULL_RATE = 0
2260 11:35:15.043111 DQ_CKDIV4_EN = 0
2261 11:35:15.046283 CA_CKDIV4_EN = 0
2262 11:35:15.049448 CA_PREDIV_EN = 0
2263 11:35:15.052873 PH8_DLY = 17
2264 11:35:15.056229 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2265 11:35:15.056305 DQ_AAMCK_DIV = 4
2266 11:35:15.059442 CA_AAMCK_DIV = 4
2267 11:35:15.063469 CA_ADMCK_DIV = 4
2268 11:35:15.066536 DQ_TRACK_CA_EN = 0
2269 11:35:15.069535 CA_PICK = 1200
2270 11:35:15.072823 CA_MCKIO = 1200
2271 11:35:15.076490 MCKIO_SEMI = 0
2272 11:35:15.079407 PLL_FREQ = 2366
2273 11:35:15.079520 DQ_UI_PI_RATIO = 32
2274 11:35:15.082555 CA_UI_PI_RATIO = 0
2275 11:35:15.086263 ===================================
2276 11:35:15.089344 ===================================
2277 11:35:15.093304 memory_type:LPDDR4
2278 11:35:15.096125 GP_NUM : 10
2279 11:35:15.096200 SRAM_EN : 1
2280 11:35:15.099653 MD32_EN : 0
2281 11:35:15.102569 ===================================
2282 11:35:15.102644 [ANA_INIT] >>>>>>>>>>>>>>
2283 11:35:15.106431 <<<<<< [CONFIGURE PHASE]: ANA_TX
2284 11:35:15.109345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2285 11:35:15.113065 ===================================
2286 11:35:15.116409 data_rate = 2400,PCW = 0X5b00
2287 11:35:15.119054 ===================================
2288 11:35:15.122457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2289 11:35:15.128936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2290 11:35:15.135734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2291 11:35:15.139243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2292 11:35:15.142419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2293 11:35:15.145727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2294 11:35:15.149099 [ANA_INIT] flow start
2295 11:35:15.149174 [ANA_INIT] PLL >>>>>>>>
2296 11:35:15.152412 [ANA_INIT] PLL <<<<<<<<
2297 11:35:15.155836 [ANA_INIT] MIDPI >>>>>>>>
2298 11:35:15.155911 [ANA_INIT] MIDPI <<<<<<<<
2299 11:35:15.158946 [ANA_INIT] DLL >>>>>>>>
2300 11:35:15.162417 [ANA_INIT] DLL <<<<<<<<
2301 11:35:15.162492 [ANA_INIT] flow end
2302 11:35:15.169165 ============ LP4 DIFF to SE enter ============
2303 11:35:15.172504 ============ LP4 DIFF to SE exit ============
2304 11:35:15.175996 [ANA_INIT] <<<<<<<<<<<<<
2305 11:35:15.179242 [Flow] Enable top DCM control >>>>>
2306 11:35:15.182348 [Flow] Enable top DCM control <<<<<
2307 11:35:15.182423 Enable DLL master slave shuffle
2308 11:35:15.188995 ==============================================================
2309 11:35:15.192085 Gating Mode config
2310 11:35:15.195550 ==============================================================
2311 11:35:15.198962 Config description:
2312 11:35:15.208715 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2313 11:35:15.215094 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2314 11:35:15.218397 SELPH_MODE 0: By rank 1: By Phase
2315 11:35:15.224924 ==============================================================
2316 11:35:15.228679 GAT_TRACK_EN = 1
2317 11:35:15.232406 RX_GATING_MODE = 2
2318 11:35:15.234809 RX_GATING_TRACK_MODE = 2
2319 11:35:15.238474 SELPH_MODE = 1
2320 11:35:15.241637 PICG_EARLY_EN = 1
2321 11:35:15.241712 VALID_LAT_VALUE = 1
2322 11:35:15.248215 ==============================================================
2323 11:35:15.251801 Enter into Gating configuration >>>>
2324 11:35:15.254857 Exit from Gating configuration <<<<
2325 11:35:15.258238 Enter into DVFS_PRE_config >>>>>
2326 11:35:15.268131 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2327 11:35:15.271273 Exit from DVFS_PRE_config <<<<<
2328 11:35:15.275393 Enter into PICG configuration >>>>
2329 11:35:15.278105 Exit from PICG configuration <<<<
2330 11:35:15.281463 [RX_INPUT] configuration >>>>>
2331 11:35:15.284769 [RX_INPUT] configuration <<<<<
2332 11:35:15.291235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2333 11:35:15.295121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2334 11:35:15.301724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2335 11:35:15.307799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2336 11:35:15.314290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2337 11:35:15.321466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2338 11:35:15.324500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2339 11:35:15.327625 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2340 11:35:15.331196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2341 11:35:15.337507 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2342 11:35:15.341695 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2343 11:35:15.344333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 11:35:15.348136 ===================================
2345 11:35:15.351006 LPDDR4 DRAM CONFIGURATION
2346 11:35:15.354548 ===================================
2347 11:35:15.354637 EX_ROW_EN[0] = 0x0
2348 11:35:15.357798 EX_ROW_EN[1] = 0x0
2349 11:35:15.360726 LP4Y_EN = 0x0
2350 11:35:15.360803 WORK_FSP = 0x0
2351 11:35:15.364338 WL = 0x4
2352 11:35:15.364413 RL = 0x4
2353 11:35:15.367722 BL = 0x2
2354 11:35:15.367798 RPST = 0x0
2355 11:35:15.370892 RD_PRE = 0x0
2356 11:35:15.370967 WR_PRE = 0x1
2357 11:35:15.374005 WR_PST = 0x0
2358 11:35:15.374093 DBI_WR = 0x0
2359 11:35:15.377080 DBI_RD = 0x0
2360 11:35:15.377155 OTF = 0x1
2361 11:35:15.380756 ===================================
2362 11:35:15.383861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2363 11:35:15.390555 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2364 11:35:15.394026 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2365 11:35:15.397001 ===================================
2366 11:35:15.400131 LPDDR4 DRAM CONFIGURATION
2367 11:35:15.403912 ===================================
2368 11:35:15.403987 EX_ROW_EN[0] = 0x10
2369 11:35:15.406956 EX_ROW_EN[1] = 0x0
2370 11:35:15.410532 LP4Y_EN = 0x0
2371 11:35:15.410606 WORK_FSP = 0x0
2372 11:35:15.413671 WL = 0x4
2373 11:35:15.413745 RL = 0x4
2374 11:35:15.416966 BL = 0x2
2375 11:35:15.417041 RPST = 0x0
2376 11:35:15.420321 RD_PRE = 0x0
2377 11:35:15.420394 WR_PRE = 0x1
2378 11:35:15.423286 WR_PST = 0x0
2379 11:35:15.423360 DBI_WR = 0x0
2380 11:35:15.426912 DBI_RD = 0x0
2381 11:35:15.426986 OTF = 0x1
2382 11:35:15.430231 ===================================
2383 11:35:15.436657 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2384 11:35:15.436730 ==
2385 11:35:15.439909 Dram Type= 6, Freq= 0, CH_0, rank 0
2386 11:35:15.443588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 11:35:15.446752 ==
2388 11:35:15.446825 [Duty_Offset_Calibration]
2389 11:35:15.449658 B0:1 B1:-1 CA:0
2390 11:35:15.449731
2391 11:35:15.453130 [DutyScan_Calibration_Flow] k_type=0
2392 11:35:15.461657
2393 11:35:15.461731 ==CLK 0==
2394 11:35:15.465498 Final CLK duty delay cell = 0
2395 11:35:15.468338 [0] MAX Duty = 5094%(X100), DQS PI = 16
2396 11:35:15.471730 [0] MIN Duty = 4875%(X100), DQS PI = 8
2397 11:35:15.471803 [0] AVG Duty = 4984%(X100)
2398 11:35:15.475254
2399 11:35:15.478421 CH0 CLK Duty spec in!! Max-Min= 219%
2400 11:35:15.481877 [DutyScan_Calibration_Flow] ====Done====
2401 11:35:15.481951
2402 11:35:15.484840 [DutyScan_Calibration_Flow] k_type=1
2403 11:35:15.500393
2404 11:35:15.500466 ==DQS 0 ==
2405 11:35:15.503645 Final DQS duty delay cell = -4
2406 11:35:15.506858 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2407 11:35:15.510424 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2408 11:35:15.513556 [-4] AVG Duty = 4968%(X100)
2409 11:35:15.513629
2410 11:35:15.513687 ==DQS 1 ==
2411 11:35:15.517048 Final DQS duty delay cell = 0
2412 11:35:15.519939 [0] MAX Duty = 5124%(X100), DQS PI = 6
2413 11:35:15.523446 [0] MIN Duty = 5000%(X100), DQS PI = 22
2414 11:35:15.526719 [0] AVG Duty = 5062%(X100)
2415 11:35:15.526792
2416 11:35:15.530155 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2417 11:35:15.530230
2418 11:35:15.533520 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2419 11:35:15.536567 [DutyScan_Calibration_Flow] ====Done====
2420 11:35:15.536641
2421 11:35:15.540026 [DutyScan_Calibration_Flow] k_type=3
2422 11:35:15.557949
2423 11:35:15.558024 ==DQM 0 ==
2424 11:35:15.561291 Final DQM duty delay cell = 0
2425 11:35:15.564583 [0] MAX Duty = 5062%(X100), DQS PI = 20
2426 11:35:15.568128 [0] MIN Duty = 4844%(X100), DQS PI = 8
2427 11:35:15.571392 [0] AVG Duty = 4953%(X100)
2428 11:35:15.571503
2429 11:35:15.571561 ==DQM 1 ==
2430 11:35:15.575014 Final DQM duty delay cell = 4
2431 11:35:15.578053 [4] MAX Duty = 5187%(X100), DQS PI = 14
2432 11:35:15.581364 [4] MIN Duty = 5000%(X100), DQS PI = 24
2433 11:35:15.584744 [4] AVG Duty = 5093%(X100)
2434 11:35:15.584819
2435 11:35:15.587766 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2436 11:35:15.587841
2437 11:35:15.591035 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2438 11:35:15.594376 [DutyScan_Calibration_Flow] ====Done====
2439 11:35:15.594451
2440 11:35:15.597826 [DutyScan_Calibration_Flow] k_type=2
2441 11:35:15.613250
2442 11:35:15.613324 ==DQ 0 ==
2443 11:35:15.616078 Final DQ duty delay cell = -4
2444 11:35:15.619544 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2445 11:35:15.623019 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2446 11:35:15.626371 [-4] AVG Duty = 4953%(X100)
2447 11:35:15.626445
2448 11:35:15.626503 ==DQ 1 ==
2449 11:35:15.629479 Final DQ duty delay cell = -4
2450 11:35:15.633128 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2451 11:35:15.636161 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2452 11:35:15.639381 [-4] AVG Duty = 4938%(X100)
2453 11:35:15.639479
2454 11:35:15.642743 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2455 11:35:15.642842
2456 11:35:15.645856 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2457 11:35:15.649263 [DutyScan_Calibration_Flow] ====Done====
2458 11:35:15.649337 ==
2459 11:35:15.652449 Dram Type= 6, Freq= 0, CH_1, rank 0
2460 11:35:15.656212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 11:35:15.656319 ==
2462 11:35:15.659219 [Duty_Offset_Calibration]
2463 11:35:15.659293 B0:-1 B1:1 CA:2
2464 11:35:15.662716
2465 11:35:15.665806 [DutyScan_Calibration_Flow] k_type=0
2466 11:35:15.673482
2467 11:35:15.673557 ==CLK 0==
2468 11:35:15.676758 Final CLK duty delay cell = 0
2469 11:35:15.680157 [0] MAX Duty = 5156%(X100), DQS PI = 22
2470 11:35:15.683645 [0] MIN Duty = 4969%(X100), DQS PI = 60
2471 11:35:15.686990 [0] AVG Duty = 5062%(X100)
2472 11:35:15.687065
2473 11:35:15.690156 CH1 CLK Duty spec in!! Max-Min= 187%
2474 11:35:15.693698 [DutyScan_Calibration_Flow] ====Done====
2475 11:35:15.693773
2476 11:35:15.696861 [DutyScan_Calibration_Flow] k_type=1
2477 11:35:15.712962
2478 11:35:15.713036 ==DQS 0 ==
2479 11:35:15.716523 Final DQS duty delay cell = 0
2480 11:35:15.719673 [0] MAX Duty = 5125%(X100), DQS PI = 48
2481 11:35:15.722983 [0] MIN Duty = 4875%(X100), DQS PI = 6
2482 11:35:15.723057 [0] AVG Duty = 5000%(X100)
2483 11:35:15.726202
2484 11:35:15.726276 ==DQS 1 ==
2485 11:35:15.729859 Final DQS duty delay cell = 0
2486 11:35:15.732939 [0] MAX Duty = 5062%(X100), DQS PI = 10
2487 11:35:15.736253 [0] MIN Duty = 4969%(X100), DQS PI = 54
2488 11:35:15.736327 [0] AVG Duty = 5015%(X100)
2489 11:35:15.739634
2490 11:35:15.742683 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2491 11:35:15.742761
2492 11:35:15.746519 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2493 11:35:15.749807 [DutyScan_Calibration_Flow] ====Done====
2494 11:35:15.749882
2495 11:35:15.752828 [DutyScan_Calibration_Flow] k_type=3
2496 11:35:15.768503
2497 11:35:15.768582 ==DQM 0 ==
2498 11:35:15.771926 Final DQM duty delay cell = -4
2499 11:35:15.775203 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2500 11:35:15.778623 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2501 11:35:15.781566 [-4] AVG Duty = 4937%(X100)
2502 11:35:15.781639
2503 11:35:15.781698 ==DQM 1 ==
2504 11:35:15.785589 Final DQM duty delay cell = 0
2505 11:35:15.788582 [0] MAX Duty = 5187%(X100), DQS PI = 6
2506 11:35:15.791992 [0] MIN Duty = 4969%(X100), DQS PI = 28
2507 11:35:15.795096 [0] AVG Duty = 5078%(X100)
2508 11:35:15.795169
2509 11:35:15.798806 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2510 11:35:15.798879
2511 11:35:15.801540 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2512 11:35:15.805011 [DutyScan_Calibration_Flow] ====Done====
2513 11:35:15.805085
2514 11:35:15.808361 [DutyScan_Calibration_Flow] k_type=2
2515 11:35:15.825222
2516 11:35:15.825297 ==DQ 0 ==
2517 11:35:15.828674 Final DQ duty delay cell = 0
2518 11:35:15.831941 [0] MAX Duty = 5156%(X100), DQS PI = 30
2519 11:35:15.835396 [0] MIN Duty = 4907%(X100), DQS PI = 6
2520 11:35:15.835514 [0] AVG Duty = 5031%(X100)
2521 11:35:15.835574
2522 11:35:15.838482 ==DQ 1 ==
2523 11:35:15.842094 Final DQ duty delay cell = 0
2524 11:35:15.845371 [0] MAX Duty = 5124%(X100), DQS PI = 10
2525 11:35:15.848788 [0] MIN Duty = 4969%(X100), DQS PI = 0
2526 11:35:15.848867 [0] AVG Duty = 5046%(X100)
2527 11:35:15.848925
2528 11:35:15.851857 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2529 11:35:15.854866
2530 11:35:15.858773 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2531 11:35:15.861605 [DutyScan_Calibration_Flow] ====Done====
2532 11:35:15.865337 nWR fixed to 30
2533 11:35:15.865412 [ModeRegInit_LP4] CH0 RK0
2534 11:35:15.868176 [ModeRegInit_LP4] CH0 RK1
2535 11:35:15.871600 [ModeRegInit_LP4] CH1 RK0
2536 11:35:15.874936 [ModeRegInit_LP4] CH1 RK1
2537 11:35:15.875011 match AC timing 7
2538 11:35:15.877976 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2539 11:35:15.884908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2540 11:35:15.888064 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2541 11:35:15.895038 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2542 11:35:15.898082 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2543 11:35:15.898157 ==
2544 11:35:15.902002 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 11:35:15.904750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 11:35:15.904826 ==
2547 11:35:15.911347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 11:35:15.918177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2549 11:35:15.925359 [CA 0] Center 39 (9~70) winsize 62
2550 11:35:15.928306 [CA 1] Center 39 (9~70) winsize 62
2551 11:35:15.931874 [CA 2] Center 35 (5~66) winsize 62
2552 11:35:15.934934 [CA 3] Center 35 (5~65) winsize 61
2553 11:35:15.938672 [CA 4] Center 33 (3~64) winsize 62
2554 11:35:15.941736 [CA 5] Center 33 (4~63) winsize 60
2555 11:35:15.941811
2556 11:35:15.945097 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 11:35:15.945171
2558 11:35:15.948546 [CATrainingPosCal] consider 1 rank data
2559 11:35:15.951992 u2DelayCellTimex100 = 270/100 ps
2560 11:35:15.955305 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 11:35:15.961922 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 11:35:15.964665 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 11:35:15.968243 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2564 11:35:15.971399 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 11:35:15.974502 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2566 11:35:15.974577
2567 11:35:15.977987 CA PerBit enable=1, Macro0, CA PI delay=33
2568 11:35:15.978062
2569 11:35:15.981495 [CBTSetCACLKResult] CA Dly = 33
2570 11:35:15.981569 CS Dly: 8 (0~39)
2571 11:35:15.984575 ==
2572 11:35:15.987808 Dram Type= 6, Freq= 0, CH_0, rank 1
2573 11:35:15.991580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 11:35:15.991655 ==
2575 11:35:15.997959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2576 11:35:16.001016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2577 11:35:16.010888 [CA 0] Center 39 (8~70) winsize 63
2578 11:35:16.013891 [CA 1] Center 39 (9~70) winsize 62
2579 11:35:16.017354 [CA 2] Center 35 (5~66) winsize 62
2580 11:35:16.020742 [CA 3] Center 35 (5~65) winsize 61
2581 11:35:16.024085 [CA 4] Center 33 (3~64) winsize 62
2582 11:35:16.027440 [CA 5] Center 33 (3~63) winsize 61
2583 11:35:16.027515
2584 11:35:16.030696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2585 11:35:16.030770
2586 11:35:16.034311 [CATrainingPosCal] consider 2 rank data
2587 11:35:16.037245 u2DelayCellTimex100 = 270/100 ps
2588 11:35:16.040512 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2589 11:35:16.047251 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2590 11:35:16.050192 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2591 11:35:16.053755 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2592 11:35:16.057182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2593 11:35:16.060406 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2594 11:35:16.060480
2595 11:35:16.063608 CA PerBit enable=1, Macro0, CA PI delay=33
2596 11:35:16.063683
2597 11:35:16.067163 [CBTSetCACLKResult] CA Dly = 33
2598 11:35:16.070969 CS Dly: 9 (0~41)
2599 11:35:16.071044
2600 11:35:16.073971 ----->DramcWriteLeveling(PI) begin...
2601 11:35:16.074046 ==
2602 11:35:16.077208 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 11:35:16.080541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 11:35:16.080616 ==
2605 11:35:16.083657 Write leveling (Byte 0): 34 => 34
2606 11:35:16.086843 Write leveling (Byte 1): 30 => 30
2607 11:35:16.090426 DramcWriteLeveling(PI) end<-----
2608 11:35:16.090500
2609 11:35:16.090558 ==
2610 11:35:16.093472 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 11:35:16.097044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 11:35:16.097118 ==
2613 11:35:16.100710 [Gating] SW mode calibration
2614 11:35:16.106904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2615 11:35:16.113398 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2616 11:35:16.116775 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
2617 11:35:16.120222 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2618 11:35:16.126794 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2619 11:35:16.130337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 11:35:16.133116 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 11:35:16.140112 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2622 11:35:16.143031 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2623 11:35:16.146536 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2624 11:35:16.152963 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2625 11:35:16.156502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 11:35:16.159950 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 11:35:16.166293 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 11:35:16.169936 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 11:35:16.173307 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 11:35:16.179879 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2631 11:35:16.182737 1 0 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2632 11:35:16.186023 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2633 11:35:16.192748 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2634 11:35:16.196435 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 11:35:16.199369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 11:35:16.206026 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 11:35:16.209634 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 11:35:16.212599 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 11:35:16.219409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2640 11:35:16.222833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2641 11:35:16.225895 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2642 11:35:16.232420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 11:35:16.236071 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 11:35:16.239262 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 11:35:16.242428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 11:35:16.249306 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 11:35:16.252787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 11:35:16.255743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 11:35:16.263082 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 11:35:16.266095 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 11:35:16.269008 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 11:35:16.275779 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 11:35:16.278970 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 11:35:16.282190 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 11:35:16.289293 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2656 11:35:16.292302 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2657 11:35:16.295567 Total UI for P1: 0, mck2ui 16
2658 11:35:16.298872 best dqsien dly found for B0: ( 1, 3, 28)
2659 11:35:16.301943 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2660 11:35:16.308721 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2661 11:35:16.308797 Total UI for P1: 0, mck2ui 16
2662 11:35:16.315664 best dqsien dly found for B1: ( 1, 4, 0)
2663 11:35:16.318584 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2664 11:35:16.322095 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2665 11:35:16.322169
2666 11:35:16.325486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2667 11:35:16.328837 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2668 11:35:16.332232 [Gating] SW calibration Done
2669 11:35:16.332307 ==
2670 11:35:16.335198 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 11:35:16.338685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 11:35:16.338759 ==
2673 11:35:16.341922 RX Vref Scan: 0
2674 11:35:16.341996
2675 11:35:16.342055 RX Vref 0 -> 0, step: 1
2676 11:35:16.342109
2677 11:35:16.345189 RX Delay -40 -> 252, step: 8
2678 11:35:16.348689 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2679 11:35:16.355106 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2680 11:35:16.358497 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2681 11:35:16.361693 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2682 11:35:16.365126 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2683 11:35:16.368267 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2684 11:35:16.374954 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2685 11:35:16.378246 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2686 11:35:16.381404 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2687 11:35:16.384811 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2688 11:35:16.388415 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2689 11:35:16.394910 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2690 11:35:16.398297 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2691 11:35:16.401591 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2692 11:35:16.404919 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2693 11:35:16.411656 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2694 11:35:16.411785 ==
2695 11:35:16.414719 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 11:35:16.418139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 11:35:16.418214 ==
2698 11:35:16.418272 DQS Delay:
2699 11:35:16.421141 DQS0 = 0, DQS1 = 0
2700 11:35:16.421216 DQM Delay:
2701 11:35:16.424478 DQM0 = 119, DQM1 = 106
2702 11:35:16.424555 DQ Delay:
2703 11:35:16.427885 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2704 11:35:16.431156 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2705 11:35:16.434803 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2706 11:35:16.438140 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2707 11:35:16.438254
2708 11:35:16.438376
2709 11:35:16.441098 ==
2710 11:35:16.441172 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:35:16.447788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:35:16.447865 ==
2713 11:35:16.447923
2714 11:35:16.447977
2715 11:35:16.451374 TX Vref Scan disable
2716 11:35:16.451494 == TX Byte 0 ==
2717 11:35:16.454352 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2718 11:35:16.461156 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2719 11:35:16.461256 == TX Byte 1 ==
2720 11:35:16.464421 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2721 11:35:16.471152 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2722 11:35:16.471297 ==
2723 11:35:16.474224 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 11:35:16.477756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 11:35:16.477831 ==
2726 11:35:16.489661 TX Vref=22, minBit 13, minWin=25, winSum=421
2727 11:35:16.492924 TX Vref=24, minBit 7, minWin=25, winSum=426
2728 11:35:16.496415 TX Vref=26, minBit 5, minWin=26, winSum=432
2729 11:35:16.499622 TX Vref=28, minBit 13, minWin=26, winSum=436
2730 11:35:16.503243 TX Vref=30, minBit 10, minWin=26, winSum=435
2731 11:35:16.509737 TX Vref=32, minBit 10, minWin=26, winSum=432
2732 11:35:16.513160 [TxChooseVref] Worse bit 13, Min win 26, Win sum 436, Final Vref 28
2733 11:35:16.513235
2734 11:35:16.516192 Final TX Range 1 Vref 28
2735 11:35:16.516267
2736 11:35:16.516324 ==
2737 11:35:16.519388 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 11:35:16.525827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 11:35:16.525902 ==
2740 11:35:16.525960
2741 11:35:16.526013
2742 11:35:16.526064 TX Vref Scan disable
2743 11:35:16.529853 == TX Byte 0 ==
2744 11:35:16.533238 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2745 11:35:16.536557 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2746 11:35:16.539775 == TX Byte 1 ==
2747 11:35:16.542941 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2748 11:35:16.549811 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2749 11:35:16.549912
2750 11:35:16.550010 [DATLAT]
2751 11:35:16.550076 Freq=1200, CH0 RK0
2752 11:35:16.550130
2753 11:35:16.553332 DATLAT Default: 0xd
2754 11:35:16.553405 0, 0xFFFF, sum = 0
2755 11:35:16.556913 1, 0xFFFF, sum = 0
2756 11:35:16.559759 2, 0xFFFF, sum = 0
2757 11:35:16.559833 3, 0xFFFF, sum = 0
2758 11:35:16.563210 4, 0xFFFF, sum = 0
2759 11:35:16.563285 5, 0xFFFF, sum = 0
2760 11:35:16.566362 6, 0xFFFF, sum = 0
2761 11:35:16.566437 7, 0xFFFF, sum = 0
2762 11:35:16.570106 8, 0xFFFF, sum = 0
2763 11:35:16.570181 9, 0xFFFF, sum = 0
2764 11:35:16.573596 10, 0xFFFF, sum = 0
2765 11:35:16.573671 11, 0xFFFF, sum = 0
2766 11:35:16.576455 12, 0x0, sum = 1
2767 11:35:16.576531 13, 0x0, sum = 2
2768 11:35:16.579781 14, 0x0, sum = 3
2769 11:35:16.579856 15, 0x0, sum = 4
2770 11:35:16.583135 best_step = 13
2771 11:35:16.583209
2772 11:35:16.583269 ==
2773 11:35:16.586304 Dram Type= 6, Freq= 0, CH_0, rank 0
2774 11:35:16.589548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2775 11:35:16.589623 ==
2776 11:35:16.589681 RX Vref Scan: 1
2777 11:35:16.592623
2778 11:35:16.592696 Set Vref Range= 32 -> 127
2779 11:35:16.592754
2780 11:35:16.596111 RX Vref 32 -> 127, step: 1
2781 11:35:16.596185
2782 11:35:16.599603 RX Delay -21 -> 252, step: 4
2783 11:35:16.599677
2784 11:35:16.602431 Set Vref, RX VrefLevel [Byte0]: 32
2785 11:35:16.606011 [Byte1]: 32
2786 11:35:16.606085
2787 11:35:16.609301 Set Vref, RX VrefLevel [Byte0]: 33
2788 11:35:16.612384 [Byte1]: 33
2789 11:35:16.616548
2790 11:35:16.616651 Set Vref, RX VrefLevel [Byte0]: 34
2791 11:35:16.619647 [Byte1]: 34
2792 11:35:16.624454
2793 11:35:16.624527 Set Vref, RX VrefLevel [Byte0]: 35
2794 11:35:16.628092 [Byte1]: 35
2795 11:35:16.632050
2796 11:35:16.632123 Set Vref, RX VrefLevel [Byte0]: 36
2797 11:35:16.635278 [Byte1]: 36
2798 11:35:16.639956
2799 11:35:16.640030 Set Vref, RX VrefLevel [Byte0]: 37
2800 11:35:16.643159 [Byte1]: 37
2801 11:35:16.648187
2802 11:35:16.648261 Set Vref, RX VrefLevel [Byte0]: 38
2803 11:35:16.651238 [Byte1]: 38
2804 11:35:16.655875
2805 11:35:16.655949 Set Vref, RX VrefLevel [Byte0]: 39
2806 11:35:16.659198 [Byte1]: 39
2807 11:35:16.663645
2808 11:35:16.663719 Set Vref, RX VrefLevel [Byte0]: 40
2809 11:35:16.667362 [Byte1]: 40
2810 11:35:16.672204
2811 11:35:16.672279 Set Vref, RX VrefLevel [Byte0]: 41
2812 11:35:16.674915 [Byte1]: 41
2813 11:35:16.679550
2814 11:35:16.679624 Set Vref, RX VrefLevel [Byte0]: 42
2815 11:35:16.682937 [Byte1]: 42
2816 11:35:16.687660
2817 11:35:16.687734 Set Vref, RX VrefLevel [Byte0]: 43
2818 11:35:16.690883 [Byte1]: 43
2819 11:35:16.695583
2820 11:35:16.695657 Set Vref, RX VrefLevel [Byte0]: 44
2821 11:35:16.699040 [Byte1]: 44
2822 11:35:16.703566
2823 11:35:16.703642 Set Vref, RX VrefLevel [Byte0]: 45
2824 11:35:16.706813 [Byte1]: 45
2825 11:35:16.711279
2826 11:35:16.711371 Set Vref, RX VrefLevel [Byte0]: 46
2827 11:35:16.715147 [Byte1]: 46
2828 11:35:16.719184
2829 11:35:16.719273 Set Vref, RX VrefLevel [Byte0]: 47
2830 11:35:16.722824 [Byte1]: 47
2831 11:35:16.727113
2832 11:35:16.727208 Set Vref, RX VrefLevel [Byte0]: 48
2833 11:35:16.730530 [Byte1]: 48
2834 11:35:16.735570
2835 11:35:16.739090 Set Vref, RX VrefLevel [Byte0]: 49
2836 11:35:16.741891 [Byte1]: 49
2837 11:35:16.741985
2838 11:35:16.745092 Set Vref, RX VrefLevel [Byte0]: 50
2839 11:35:16.748429 [Byte1]: 50
2840 11:35:16.748518
2841 11:35:16.751762 Set Vref, RX VrefLevel [Byte0]: 51
2842 11:35:16.755076 [Byte1]: 51
2843 11:35:16.758756
2844 11:35:16.758843 Set Vref, RX VrefLevel [Byte0]: 52
2845 11:35:16.762197 [Byte1]: 52
2846 11:35:16.767392
2847 11:35:16.767480 Set Vref, RX VrefLevel [Byte0]: 53
2848 11:35:16.770317 [Byte1]: 53
2849 11:35:16.774993
2850 11:35:16.775083 Set Vref, RX VrefLevel [Byte0]: 54
2851 11:35:16.778029 [Byte1]: 54
2852 11:35:16.782806
2853 11:35:16.782880 Set Vref, RX VrefLevel [Byte0]: 55
2854 11:35:16.786240 [Byte1]: 55
2855 11:35:16.791671
2856 11:35:16.791806 Set Vref, RX VrefLevel [Byte0]: 56
2857 11:35:16.794592 [Byte1]: 56
2858 11:35:16.798646
2859 11:35:16.798782 Set Vref, RX VrefLevel [Byte0]: 57
2860 11:35:16.802141 [Byte1]: 57
2861 11:35:16.806810
2862 11:35:16.806949 Set Vref, RX VrefLevel [Byte0]: 58
2863 11:35:16.810099 [Byte1]: 58
2864 11:35:16.814698
2865 11:35:16.814854 Set Vref, RX VrefLevel [Byte0]: 59
2866 11:35:16.818752 [Byte1]: 59
2867 11:35:16.822558
2868 11:35:16.822694 Set Vref, RX VrefLevel [Byte0]: 60
2869 11:35:16.825968 [Byte1]: 60
2870 11:35:16.830882
2871 11:35:16.831066 Set Vref, RX VrefLevel [Byte0]: 61
2872 11:35:16.834291 [Byte1]: 61
2873 11:35:16.838367
2874 11:35:16.838644 Set Vref, RX VrefLevel [Byte0]: 62
2875 11:35:16.841853 [Byte1]: 62
2876 11:35:16.846763
2877 11:35:16.847009 Set Vref, RX VrefLevel [Byte0]: 63
2878 11:35:16.850176 [Byte1]: 63
2879 11:35:16.854942
2880 11:35:16.855209 Set Vref, RX VrefLevel [Byte0]: 64
2881 11:35:16.858103 [Byte1]: 64
2882 11:35:16.862556
2883 11:35:16.862996 Set Vref, RX VrefLevel [Byte0]: 65
2884 11:35:16.865719 [Byte1]: 65
2885 11:35:16.870699
2886 11:35:16.871212 Set Vref, RX VrefLevel [Byte0]: 66
2887 11:35:16.874172 [Byte1]: 66
2888 11:35:16.878514
2889 11:35:16.878931 Set Vref, RX VrefLevel [Byte0]: 67
2890 11:35:16.881492 [Byte1]: 67
2891 11:35:16.886512
2892 11:35:16.886997 Set Vref, RX VrefLevel [Byte0]: 68
2893 11:35:16.889704 [Byte1]: 68
2894 11:35:16.894307
2895 11:35:16.894792 Set Vref, RX VrefLevel [Byte0]: 69
2896 11:35:16.898168 [Byte1]: 69
2897 11:35:16.902129
2898 11:35:16.902659 Set Vref, RX VrefLevel [Byte0]: 70
2899 11:35:16.905177 [Byte1]: 70
2900 11:35:16.910420
2901 11:35:16.910960 Set Vref, RX VrefLevel [Byte0]: 71
2902 11:35:16.913145 [Byte1]: 71
2903 11:35:16.917980
2904 11:35:16.918354 Set Vref, RX VrefLevel [Byte0]: 72
2905 11:35:16.921605 [Byte1]: 72
2906 11:35:16.926290
2907 11:35:16.926739 Set Vref, RX VrefLevel [Byte0]: 73
2908 11:35:16.929050 [Byte1]: 73
2909 11:35:16.933933
2910 11:35:16.936853 Set Vref, RX VrefLevel [Byte0]: 74
2911 11:35:16.940247 [Byte1]: 74
2912 11:35:16.940625
2913 11:35:16.943502 Set Vref, RX VrefLevel [Byte0]: 75
2914 11:35:16.946868 [Byte1]: 75
2915 11:35:16.947244
2916 11:35:16.950665 Set Vref, RX VrefLevel [Byte0]: 76
2917 11:35:16.953563 [Byte1]: 76
2918 11:35:16.957644
2919 11:35:16.958019 Final RX Vref Byte 0 = 66 to rank0
2920 11:35:16.961214 Final RX Vref Byte 1 = 58 to rank0
2921 11:35:16.964135 Final RX Vref Byte 0 = 66 to rank1
2922 11:35:16.967325 Final RX Vref Byte 1 = 58 to rank1==
2923 11:35:16.970740 Dram Type= 6, Freq= 0, CH_0, rank 0
2924 11:35:16.977400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 11:35:16.977860 ==
2926 11:35:16.978215 DQS Delay:
2927 11:35:16.978502 DQS0 = 0, DQS1 = 0
2928 11:35:16.980658 DQM Delay:
2929 11:35:16.981073 DQM0 = 118, DQM1 = 108
2930 11:35:16.984301 DQ Delay:
2931 11:35:16.987372 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2932 11:35:16.990634 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =124
2933 11:35:16.994058 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2934 11:35:16.997428 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2935 11:35:16.997895
2936 11:35:16.998203
2937 11:35:17.007580 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2938 11:35:17.008046 CH0 RK0: MR19=403, MR18=10FC
2939 11:35:17.014179 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2940 11:35:17.014661
2941 11:35:17.017085 ----->DramcWriteLeveling(PI) begin...
2942 11:35:17.017473 ==
2943 11:35:17.020322 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 11:35:17.027387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 11:35:17.027809 ==
2946 11:35:17.030764 Write leveling (Byte 0): 33 => 33
2947 11:35:17.031244 Write leveling (Byte 1): 31 => 31
2948 11:35:17.033971 DramcWriteLeveling(PI) end<-----
2949 11:35:17.034419
2950 11:35:17.037494 ==
2951 11:35:17.037957 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 11:35:17.043901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 11:35:17.044368 ==
2954 11:35:17.048072 [Gating] SW mode calibration
2955 11:35:17.053458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2956 11:35:17.057131 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2957 11:35:17.063950 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2958 11:35:17.066993 0 15 4 | B1->B0 | 2f2e 3434 | 1 1 | (1 1) (1 1)
2959 11:35:17.070857 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 11:35:17.077414 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2961 11:35:17.080516 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 11:35:17.083905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 11:35:17.090204 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2964 11:35:17.093764 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2965 11:35:17.097118 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2966 11:35:17.100440 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 11:35:17.107333 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 11:35:17.110550 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 11:35:17.113414 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 11:35:17.120484 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 11:35:17.124027 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 11:35:17.127149 1 0 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2973 11:35:17.133623 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2974 11:35:17.136869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 11:35:17.140168 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 11:35:17.146788 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 11:35:17.150419 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 11:35:17.153724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 11:35:17.159961 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 11:35:17.163457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2981 11:35:17.166476 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2982 11:35:17.173272 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:35:17.176768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:35:17.180078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:35:17.186600 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:35:17.189933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:35:17.193283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:35:17.200014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 11:35:17.203223 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 11:35:17.206771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 11:35:17.212958 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 11:35:17.216562 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 11:35:17.220234 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 11:35:17.226336 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 11:35:17.230155 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 11:35:17.233523 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2997 11:35:17.239845 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 11:35:17.240271 Total UI for P1: 0, mck2ui 16
2999 11:35:17.246757 best dqsien dly found for B0: ( 1, 3, 28)
3000 11:35:17.247254 Total UI for P1: 0, mck2ui 16
3001 11:35:17.250069 best dqsien dly found for B1: ( 1, 3, 30)
3002 11:35:17.256388 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3003 11:35:17.259606 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3004 11:35:17.260119
3005 11:35:17.262812 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3006 11:35:17.265890 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3007 11:35:17.269690 [Gating] SW calibration Done
3008 11:35:17.270109 ==
3009 11:35:17.272663 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:35:17.276173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:35:17.276607 ==
3012 11:35:17.279296 RX Vref Scan: 0
3013 11:35:17.279754
3014 11:35:17.280082 RX Vref 0 -> 0, step: 1
3015 11:35:17.280385
3016 11:35:17.282951 RX Delay -40 -> 252, step: 8
3017 11:35:17.286307 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3018 11:35:17.292817 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3019 11:35:17.296398 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
3020 11:35:17.299728 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3021 11:35:17.302523 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3022 11:35:17.305727 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3023 11:35:17.312544 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3024 11:35:17.316145 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3025 11:35:17.319733 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3026 11:35:17.322903 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3027 11:35:17.325820 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3028 11:35:17.332699 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3029 11:35:17.336040 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3030 11:35:17.339413 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3031 11:35:17.342570 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3032 11:35:17.345705 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3033 11:35:17.348797 ==
3034 11:35:17.352150 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 11:35:17.356000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 11:35:17.356379 ==
3037 11:35:17.356674 DQS Delay:
3038 11:35:17.358645 DQS0 = 0, DQS1 = 0
3039 11:35:17.359020 DQM Delay:
3040 11:35:17.362060 DQM0 = 116, DQM1 = 108
3041 11:35:17.362435 DQ Delay:
3042 11:35:17.365085 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
3043 11:35:17.368470 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3044 11:35:17.371725 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3045 11:35:17.375473 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3046 11:35:17.375938
3047 11:35:17.376233
3048 11:35:17.376501 ==
3049 11:35:17.378252 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 11:35:17.385256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:35:17.385702 ==
3052 11:35:17.386000
3053 11:35:17.386271
3054 11:35:17.386531 TX Vref Scan disable
3055 11:35:17.388649 == TX Byte 0 ==
3056 11:35:17.391910 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3057 11:35:17.398620 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3058 11:35:17.398998 == TX Byte 1 ==
3059 11:35:17.402057 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3060 11:35:17.408767 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3061 11:35:17.409230 ==
3062 11:35:17.412001 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 11:35:17.414995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:35:17.415501 ==
3065 11:35:17.426978 TX Vref=22, minBit 5, minWin=25, winSum=419
3066 11:35:17.430061 TX Vref=24, minBit 4, minWin=25, winSum=423
3067 11:35:17.433430 TX Vref=26, minBit 4, minWin=26, winSum=429
3068 11:35:17.436587 TX Vref=28, minBit 1, minWin=26, winSum=434
3069 11:35:17.440339 TX Vref=30, minBit 8, minWin=26, winSum=435
3070 11:35:17.446439 TX Vref=32, minBit 8, minWin=26, winSum=431
3071 11:35:17.449664 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3072 11:35:17.450044
3073 11:35:17.453202 Final TX Range 1 Vref 30
3074 11:35:17.453581
3075 11:35:17.453874 ==
3076 11:35:17.456192 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 11:35:17.459935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 11:35:17.462772 ==
3079 11:35:17.463147
3080 11:35:17.463587
3081 11:35:17.463882 TX Vref Scan disable
3082 11:35:17.466448 == TX Byte 0 ==
3083 11:35:17.470026 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3084 11:35:17.476280 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3085 11:35:17.476670 == TX Byte 1 ==
3086 11:35:17.480165 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3087 11:35:17.487129 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3088 11:35:17.487753
3089 11:35:17.488061 [DATLAT]
3090 11:35:17.488336 Freq=1200, CH0 RK1
3091 11:35:17.488602
3092 11:35:17.489530 DATLAT Default: 0xd
3093 11:35:17.489925 0, 0xFFFF, sum = 0
3094 11:35:17.493105 1, 0xFFFF, sum = 0
3095 11:35:17.496298 2, 0xFFFF, sum = 0
3096 11:35:17.496680 3, 0xFFFF, sum = 0
3097 11:35:17.500386 4, 0xFFFF, sum = 0
3098 11:35:17.500769 5, 0xFFFF, sum = 0
3099 11:35:17.502791 6, 0xFFFF, sum = 0
3100 11:35:17.503284 7, 0xFFFF, sum = 0
3101 11:35:17.506919 8, 0xFFFF, sum = 0
3102 11:35:17.507380 9, 0xFFFF, sum = 0
3103 11:35:17.509978 10, 0xFFFF, sum = 0
3104 11:35:17.510362 11, 0xFFFF, sum = 0
3105 11:35:17.513164 12, 0x0, sum = 1
3106 11:35:17.513545 13, 0x0, sum = 2
3107 11:35:17.516393 14, 0x0, sum = 3
3108 11:35:17.516776 15, 0x0, sum = 4
3109 11:35:17.519794 best_step = 13
3110 11:35:17.520248
3111 11:35:17.520627 ==
3112 11:35:17.522676 Dram Type= 6, Freq= 0, CH_0, rank 1
3113 11:35:17.526169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 11:35:17.526552 ==
3115 11:35:17.526851 RX Vref Scan: 0
3116 11:35:17.529655
3117 11:35:17.530037 RX Vref 0 -> 0, step: 1
3118 11:35:17.530338
3119 11:35:17.532887 RX Delay -21 -> 252, step: 4
3120 11:35:17.539739 iDelay=195, Bit 0, Center 112 (43 ~ 182) 140
3121 11:35:17.542686 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3122 11:35:17.546117 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
3123 11:35:17.549388 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3124 11:35:17.552676 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3125 11:35:17.556048 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3126 11:35:17.562528 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3127 11:35:17.566006 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3128 11:35:17.569199 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3129 11:35:17.572291 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3130 11:35:17.575727 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3131 11:35:17.582829 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3132 11:35:17.586037 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3133 11:35:17.589082 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3134 11:35:17.592337 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3135 11:35:17.599202 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3136 11:35:17.599627 ==
3137 11:35:17.602322 Dram Type= 6, Freq= 0, CH_0, rank 1
3138 11:35:17.605786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 11:35:17.606402 ==
3140 11:35:17.606980 DQS Delay:
3141 11:35:17.609104 DQS0 = 0, DQS1 = 0
3142 11:35:17.609485 DQM Delay:
3143 11:35:17.612158 DQM0 = 116, DQM1 = 109
3144 11:35:17.612561 DQ Delay:
3145 11:35:17.615402 DQ0 =112, DQ1 =118, DQ2 =112, DQ3 =114
3146 11:35:17.619085 DQ4 =116, DQ5 =112, DQ6 =124, DQ7 =122
3147 11:35:17.622066 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3148 11:35:17.625539 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =118
3149 11:35:17.625922
3150 11:35:17.626283
3151 11:35:17.635139 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3152 11:35:17.639070 CH0 RK1: MR19=403, MR18=BE5
3153 11:35:17.642003 CH0_RK1: MR19=0x403, MR18=0xBE5, DQSOSC=405, MR23=63, INC=39, DEC=26
3154 11:35:17.645365 [RxdqsGatingPostProcess] freq 1200
3155 11:35:17.651724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3156 11:35:17.655729 best DQS0 dly(2T, 0.5T) = (0, 11)
3157 11:35:17.658381 best DQS1 dly(2T, 0.5T) = (0, 12)
3158 11:35:17.661875 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3159 11:35:17.665580 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3160 11:35:17.668505 best DQS0 dly(2T, 0.5T) = (0, 11)
3161 11:35:17.672056 best DQS1 dly(2T, 0.5T) = (0, 11)
3162 11:35:17.674971 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3163 11:35:17.678443 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3164 11:35:17.681662 Pre-setting of DQS Precalculation
3165 11:35:17.685024 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3166 11:35:17.685531 ==
3167 11:35:17.688105 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 11:35:17.691718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 11:35:17.694543 ==
3170 11:35:17.698151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3171 11:35:17.704570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3172 11:35:17.712849 [CA 0] Center 37 (7~68) winsize 62
3173 11:35:17.716110 [CA 1] Center 38 (8~68) winsize 61
3174 11:35:17.719419 [CA 2] Center 34 (4~64) winsize 61
3175 11:35:17.722830 [CA 3] Center 33 (3~64) winsize 62
3176 11:35:17.725723 [CA 4] Center 34 (4~64) winsize 61
3177 11:35:17.729277 [CA 5] Center 33 (3~64) winsize 62
3178 11:35:17.729738
3179 11:35:17.732279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3180 11:35:17.732661
3181 11:35:17.738658 [CATrainingPosCal] consider 1 rank data
3182 11:35:17.739202 u2DelayCellTimex100 = 270/100 ps
3183 11:35:17.741962 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3184 11:35:17.748660 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3185 11:35:17.752397 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 11:35:17.755532 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 11:35:17.758859 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3188 11:35:17.761758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3189 11:35:17.762179
3190 11:35:17.765444 CA PerBit enable=1, Macro0, CA PI delay=33
3191 11:35:17.765886
3192 11:35:17.768818 [CBTSetCACLKResult] CA Dly = 33
3193 11:35:17.771681 CS Dly: 6 (0~37)
3194 11:35:17.772101 ==
3195 11:35:17.775189 Dram Type= 6, Freq= 0, CH_1, rank 1
3196 11:35:17.778865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:35:17.779364 ==
3198 11:35:17.785264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3199 11:35:17.788160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3200 11:35:17.798802 [CA 0] Center 37 (7~67) winsize 61
3201 11:35:17.801858 [CA 1] Center 38 (8~68) winsize 61
3202 11:35:17.805114 [CA 2] Center 34 (4~65) winsize 62
3203 11:35:17.807965 [CA 3] Center 33 (3~64) winsize 62
3204 11:35:17.811723 [CA 4] Center 34 (4~65) winsize 62
3205 11:35:17.815001 [CA 5] Center 33 (3~64) winsize 62
3206 11:35:17.815548
3207 11:35:17.818106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3208 11:35:17.818576
3209 11:35:17.821686 [CATrainingPosCal] consider 2 rank data
3210 11:35:17.824589 u2DelayCellTimex100 = 270/100 ps
3211 11:35:17.828264 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3212 11:35:17.834664 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3213 11:35:17.838060 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3214 11:35:17.841408 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3215 11:35:17.844447 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3216 11:35:17.847898 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3217 11:35:17.848423
3218 11:35:17.851023 CA PerBit enable=1, Macro0, CA PI delay=33
3219 11:35:17.851473
3220 11:35:17.854501 [CBTSetCACLKResult] CA Dly = 33
3221 11:35:17.857566 CS Dly: 7 (0~40)
3222 11:35:17.858066
3223 11:35:17.861236 ----->DramcWriteLeveling(PI) begin...
3224 11:35:17.861679 ==
3225 11:35:17.864608 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 11:35:17.867778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 11:35:17.868217 ==
3228 11:35:17.870694 Write leveling (Byte 0): 23 => 23
3229 11:35:17.874304 Write leveling (Byte 1): 28 => 28
3230 11:35:17.877369 DramcWriteLeveling(PI) end<-----
3231 11:35:17.877803
3232 11:35:17.878231 ==
3233 11:35:17.880493 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 11:35:17.884349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 11:35:17.884742 ==
3236 11:35:17.887550 [Gating] SW mode calibration
3237 11:35:17.894210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3238 11:35:17.900890 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3239 11:35:17.904290 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3240 11:35:17.907281 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 11:35:17.913948 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3242 11:35:17.916971 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 11:35:17.920546 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3244 11:35:17.927348 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 11:35:17.930468 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3246 11:35:17.933923 0 15 28 | B1->B0 | 2929 2323 | 1 1 | (1 0) (1 0)
3247 11:35:17.940131 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 11:35:17.943642 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 11:35:17.947142 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 11:35:17.953619 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 11:35:17.956594 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 11:35:17.959757 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 11:35:17.966317 1 0 24 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
3254 11:35:17.969590 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3255 11:35:17.973147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 11:35:17.979740 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 11:35:17.983219 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 11:35:17.986283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 11:35:17.992957 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 11:35:17.996056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 11:35:17.999658 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3262 11:35:18.006335 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3263 11:35:18.009539 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 11:35:18.012734 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 11:35:18.019455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 11:35:18.022801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 11:35:18.026047 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 11:35:18.032639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 11:35:18.035981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 11:35:18.039068 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 11:35:18.045539 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 11:35:18.049138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 11:35:18.052435 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 11:35:18.058864 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 11:35:18.062262 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 11:35:18.065167 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 11:35:18.072309 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3278 11:35:18.075340 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3279 11:35:18.078381 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 11:35:18.081910 Total UI for P1: 0, mck2ui 16
3281 11:35:18.085319 best dqsien dly found for B0: ( 1, 3, 26)
3282 11:35:18.088700 Total UI for P1: 0, mck2ui 16
3283 11:35:18.091959 best dqsien dly found for B1: ( 1, 3, 26)
3284 11:35:18.095074 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3285 11:35:18.098656 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3286 11:35:18.101580
3287 11:35:18.105160 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3288 11:35:18.108488 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3289 11:35:18.111948 [Gating] SW calibration Done
3290 11:35:18.112471 ==
3291 11:35:18.114906 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:35:18.118017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:35:18.118408 ==
3294 11:35:18.118710 RX Vref Scan: 0
3295 11:35:18.121840
3296 11:35:18.122306 RX Vref 0 -> 0, step: 1
3297 11:35:18.122610
3298 11:35:18.125155 RX Delay -40 -> 252, step: 8
3299 11:35:18.128457 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3300 11:35:18.131351 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3301 11:35:18.138311 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3302 11:35:18.141640 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3303 11:35:18.144837 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3304 11:35:18.148254 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3305 11:35:18.151356 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3306 11:35:18.157971 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3307 11:35:18.161120 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3308 11:35:18.164583 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3309 11:35:18.168083 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3310 11:35:18.170735 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3311 11:35:18.177926 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3312 11:35:18.181244 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3313 11:35:18.184416 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3314 11:35:18.187344 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3315 11:35:18.187836 ==
3316 11:35:18.191294 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 11:35:18.197458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 11:35:18.197882 ==
3319 11:35:18.198212 DQS Delay:
3320 11:35:18.200633 DQS0 = 0, DQS1 = 0
3321 11:35:18.201107 DQM Delay:
3322 11:35:18.204409 DQM0 = 117, DQM1 = 109
3323 11:35:18.204901 DQ Delay:
3324 11:35:18.207582 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3325 11:35:18.211087 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3326 11:35:18.213901 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3327 11:35:18.216998 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3328 11:35:18.217432
3329 11:35:18.217761
3330 11:35:18.218059 ==
3331 11:35:18.220378 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 11:35:18.227459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 11:35:18.227967 ==
3334 11:35:18.228302
3335 11:35:18.228608
3336 11:35:18.228898 TX Vref Scan disable
3337 11:35:18.230313 == TX Byte 0 ==
3338 11:35:18.234352 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3339 11:35:18.240428 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3340 11:35:18.240931 == TX Byte 1 ==
3341 11:35:18.243898 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3342 11:35:18.250318 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3343 11:35:18.250891 ==
3344 11:35:18.253670 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 11:35:18.256773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 11:35:18.257200 ==
3347 11:35:18.268282 TX Vref=22, minBit 9, minWin=25, winSum=419
3348 11:35:18.271684 TX Vref=24, minBit 10, minWin=25, winSum=425
3349 11:35:18.275004 TX Vref=26, minBit 8, minWin=25, winSum=430
3350 11:35:18.278187 TX Vref=28, minBit 9, minWin=26, winSum=433
3351 11:35:18.281562 TX Vref=30, minBit 9, minWin=26, winSum=433
3352 11:35:18.288352 TX Vref=32, minBit 9, minWin=25, winSum=428
3353 11:35:18.291533 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3354 11:35:18.291922
3355 11:35:18.295164 Final TX Range 1 Vref 28
3356 11:35:18.295707
3357 11:35:18.296028 ==
3358 11:35:18.298397 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 11:35:18.301629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 11:35:18.304687 ==
3361 11:35:18.305175
3362 11:35:18.305508
3363 11:35:18.305815 TX Vref Scan disable
3364 11:35:18.308570 == TX Byte 0 ==
3365 11:35:18.311398 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3366 11:35:18.317904 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3367 11:35:18.318401 == TX Byte 1 ==
3368 11:35:18.321609 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3369 11:35:18.328083 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3370 11:35:18.328672
3371 11:35:18.329021 [DATLAT]
3372 11:35:18.329326 Freq=1200, CH1 RK0
3373 11:35:18.329619
3374 11:35:18.331320 DATLAT Default: 0xd
3375 11:35:18.334448 0, 0xFFFF, sum = 0
3376 11:35:18.334878 1, 0xFFFF, sum = 0
3377 11:35:18.337593 2, 0xFFFF, sum = 0
3378 11:35:18.338021 3, 0xFFFF, sum = 0
3379 11:35:18.340925 4, 0xFFFF, sum = 0
3380 11:35:18.341311 5, 0xFFFF, sum = 0
3381 11:35:18.344183 6, 0xFFFF, sum = 0
3382 11:35:18.344570 7, 0xFFFF, sum = 0
3383 11:35:18.347323 8, 0xFFFF, sum = 0
3384 11:35:18.347774 9, 0xFFFF, sum = 0
3385 11:35:18.350802 10, 0xFFFF, sum = 0
3386 11:35:18.351191 11, 0xFFFF, sum = 0
3387 11:35:18.353936 12, 0x0, sum = 1
3388 11:35:18.354315 13, 0x0, sum = 2
3389 11:35:18.357813 14, 0x0, sum = 3
3390 11:35:18.358195 15, 0x0, sum = 4
3391 11:35:18.360880 best_step = 13
3392 11:35:18.361303
3393 11:35:18.361600 ==
3394 11:35:18.364099 Dram Type= 6, Freq= 0, CH_1, rank 0
3395 11:35:18.367206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3396 11:35:18.367690 ==
3397 11:35:18.370657 RX Vref Scan: 1
3398 11:35:18.371029
3399 11:35:18.371319 Set Vref Range= 32 -> 127
3400 11:35:18.371645
3401 11:35:18.374187 RX Vref 32 -> 127, step: 1
3402 11:35:18.374561
3403 11:35:18.377380 RX Delay -21 -> 252, step: 4
3404 11:35:18.377757
3405 11:35:18.380442 Set Vref, RX VrefLevel [Byte0]: 32
3406 11:35:18.383719 [Byte1]: 32
3407 11:35:18.384097
3408 11:35:18.387295 Set Vref, RX VrefLevel [Byte0]: 33
3409 11:35:18.390611 [Byte1]: 33
3410 11:35:18.395238
3411 11:35:18.395653 Set Vref, RX VrefLevel [Byte0]: 34
3412 11:35:18.398034 [Byte1]: 34
3413 11:35:18.402454
3414 11:35:18.402964 Set Vref, RX VrefLevel [Byte0]: 35
3415 11:35:18.406611 [Byte1]: 35
3416 11:35:18.410824
3417 11:35:18.411279 Set Vref, RX VrefLevel [Byte0]: 36
3418 11:35:18.414764 [Byte1]: 36
3419 11:35:18.418646
3420 11:35:18.419097 Set Vref, RX VrefLevel [Byte0]: 37
3421 11:35:18.421937 [Byte1]: 37
3422 11:35:18.426351
3423 11:35:18.426741 Set Vref, RX VrefLevel [Byte0]: 38
3424 11:35:18.429838 [Byte1]: 38
3425 11:35:18.434524
3426 11:35:18.434980 Set Vref, RX VrefLevel [Byte0]: 39
3427 11:35:18.437522 [Byte1]: 39
3428 11:35:18.441977
3429 11:35:18.442355 Set Vref, RX VrefLevel [Byte0]: 40
3430 11:35:18.445470 [Byte1]: 40
3431 11:35:18.450309
3432 11:35:18.450775 Set Vref, RX VrefLevel [Byte0]: 41
3433 11:35:18.453117 [Byte1]: 41
3434 11:35:18.458238
3435 11:35:18.458825 Set Vref, RX VrefLevel [Byte0]: 42
3436 11:35:18.461316 [Byte1]: 42
3437 11:35:18.465902
3438 11:35:18.466499 Set Vref, RX VrefLevel [Byte0]: 43
3439 11:35:18.468916 [Byte1]: 43
3440 11:35:18.473879
3441 11:35:18.474381 Set Vref, RX VrefLevel [Byte0]: 44
3442 11:35:18.476887 [Byte1]: 44
3443 11:35:18.481730
3444 11:35:18.482235 Set Vref, RX VrefLevel [Byte0]: 45
3445 11:35:18.487940 [Byte1]: 45
3446 11:35:18.488377
3447 11:35:18.491533 Set Vref, RX VrefLevel [Byte0]: 46
3448 11:35:18.495014 [Byte1]: 46
3449 11:35:18.495561
3450 11:35:18.498105 Set Vref, RX VrefLevel [Byte0]: 47
3451 11:35:18.501463 [Byte1]: 47
3452 11:35:18.505414
3453 11:35:18.505911 Set Vref, RX VrefLevel [Byte0]: 48
3454 11:35:18.509162 [Byte1]: 48
3455 11:35:18.513243
3456 11:35:18.513713 Set Vref, RX VrefLevel [Byte0]: 49
3457 11:35:18.516653 [Byte1]: 49
3458 11:35:18.521563
3459 11:35:18.522060 Set Vref, RX VrefLevel [Byte0]: 50
3460 11:35:18.524742 [Byte1]: 50
3461 11:35:18.529546
3462 11:35:18.530043 Set Vref, RX VrefLevel [Byte0]: 51
3463 11:35:18.532642 [Byte1]: 51
3464 11:35:18.537148
3465 11:35:18.537566 Set Vref, RX VrefLevel [Byte0]: 52
3466 11:35:18.540846 [Byte1]: 52
3467 11:35:18.545551
3468 11:35:18.546053 Set Vref, RX VrefLevel [Byte0]: 53
3469 11:35:18.548718 [Byte1]: 53
3470 11:35:18.552943
3471 11:35:18.553426 Set Vref, RX VrefLevel [Byte0]: 54
3472 11:35:18.556250 [Byte1]: 54
3473 11:35:18.561181
3474 11:35:18.561599 Set Vref, RX VrefLevel [Byte0]: 55
3475 11:35:18.564201 [Byte1]: 55
3476 11:35:18.568951
3477 11:35:18.569440 Set Vref, RX VrefLevel [Byte0]: 56
3478 11:35:18.572914 [Byte1]: 56
3479 11:35:18.576788
3480 11:35:18.577205 Set Vref, RX VrefLevel [Byte0]: 57
3481 11:35:18.580392 [Byte1]: 57
3482 11:35:18.585173
3483 11:35:18.585675 Set Vref, RX VrefLevel [Byte0]: 58
3484 11:35:18.588261 [Byte1]: 58
3485 11:35:18.592638
3486 11:35:18.593144 Set Vref, RX VrefLevel [Byte0]: 59
3487 11:35:18.595862 [Byte1]: 59
3488 11:35:18.600649
3489 11:35:18.601151 Set Vref, RX VrefLevel [Byte0]: 60
3490 11:35:18.603969 [Byte1]: 60
3491 11:35:18.608904
3492 11:35:18.609431 Set Vref, RX VrefLevel [Byte0]: 61
3493 11:35:18.611608 [Byte1]: 61
3494 11:35:18.616529
3495 11:35:18.617027 Set Vref, RX VrefLevel [Byte0]: 62
3496 11:35:18.619798 [Byte1]: 62
3497 11:35:18.624495
3498 11:35:18.624964 Set Vref, RX VrefLevel [Byte0]: 63
3499 11:35:18.628104 [Byte1]: 63
3500 11:35:18.632448
3501 11:35:18.632950 Set Vref, RX VrefLevel [Byte0]: 64
3502 11:35:18.636000 [Byte1]: 64
3503 11:35:18.640407
3504 11:35:18.640981 Set Vref, RX VrefLevel [Byte0]: 65
3505 11:35:18.643469 [Byte1]: 65
3506 11:35:18.648192
3507 11:35:18.648694 Set Vref, RX VrefLevel [Byte0]: 66
3508 11:35:18.651578 [Byte1]: 66
3509 11:35:18.655834
3510 11:35:18.656475 Set Vref, RX VrefLevel [Byte0]: 67
3511 11:35:18.659263 [Byte1]: 67
3512 11:35:18.663861
3513 11:35:18.664268 Final RX Vref Byte 0 = 47 to rank0
3514 11:35:18.667036 Final RX Vref Byte 1 = 51 to rank0
3515 11:35:18.670320 Final RX Vref Byte 0 = 47 to rank1
3516 11:35:18.673831 Final RX Vref Byte 1 = 51 to rank1==
3517 11:35:18.676970 Dram Type= 6, Freq= 0, CH_1, rank 0
3518 11:35:18.683373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:35:18.683805 ==
3520 11:35:18.684111 DQS Delay:
3521 11:35:18.686960 DQS0 = 0, DQS1 = 0
3522 11:35:18.687342 DQM Delay:
3523 11:35:18.690294 DQM0 = 116, DQM1 = 109
3524 11:35:18.690680 DQ Delay:
3525 11:35:18.693250 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3526 11:35:18.696849 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3527 11:35:18.699860 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =98
3528 11:35:18.703190 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3529 11:35:18.703729
3530 11:35:18.704043
3531 11:35:18.713151 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3532 11:35:18.713545 CH1 RK0: MR19=403, MR18=4F7
3533 11:35:18.720000 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3534 11:35:18.720386
3535 11:35:18.723259 ----->DramcWriteLeveling(PI) begin...
3536 11:35:18.723721 ==
3537 11:35:18.726269 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 11:35:18.732869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 11:35:18.733257 ==
3540 11:35:18.736300 Write leveling (Byte 0): 24 => 24
3541 11:35:18.739311 Write leveling (Byte 1): 27 => 27
3542 11:35:18.739793 DramcWriteLeveling(PI) end<-----
3543 11:35:18.742767
3544 11:35:18.743151 ==
3545 11:35:18.745734 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 11:35:18.749100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 11:35:18.749488 ==
3548 11:35:18.752653 [Gating] SW mode calibration
3549 11:35:18.759390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3550 11:35:18.762445 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3551 11:35:18.768829 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 11:35:18.772565 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 11:35:18.775381 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 11:35:18.782504 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 11:35:18.785735 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 11:35:18.788689 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 11:35:18.795903 0 15 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3558 11:35:18.798651 0 15 28 | B1->B0 | 2424 2f2f | 0 0 | (1 0) (0 1)
3559 11:35:18.802687 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 11:35:18.808882 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 11:35:18.811905 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 11:35:18.818300 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 11:35:18.822301 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 11:35:18.825517 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3565 11:35:18.831807 1 0 24 | B1->B0 | 3a3a 2a2a | 0 0 | (0 0) (0 0)
3566 11:35:18.835381 1 0 28 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
3567 11:35:18.838132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 11:35:18.845041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 11:35:18.847907 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 11:35:18.851522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 11:35:18.858210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 11:35:18.861110 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 11:35:18.864209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3574 11:35:18.871193 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3575 11:35:18.874319 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 11:35:18.877711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 11:35:18.884305 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 11:35:18.887900 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 11:35:18.891105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 11:35:18.897684 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 11:35:18.900588 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 11:35:18.903942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 11:35:18.910566 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 11:35:18.914255 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 11:35:18.917425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 11:35:18.923894 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 11:35:18.927624 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 11:35:18.930063 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 11:35:18.937501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3590 11:35:18.940539 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3591 11:35:18.943600 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3592 11:35:18.946958 Total UI for P1: 0, mck2ui 16
3593 11:35:18.949703 best dqsien dly found for B0: ( 1, 3, 26)
3594 11:35:18.953113 Total UI for P1: 0, mck2ui 16
3595 11:35:18.956301 best dqsien dly found for B1: ( 1, 3, 26)
3596 11:35:18.960165 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3597 11:35:18.963699 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3598 11:35:18.964117
3599 11:35:18.969626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3600 11:35:18.973174 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3601 11:35:18.973591 [Gating] SW calibration Done
3602 11:35:18.976228 ==
3603 11:35:18.979890 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 11:35:18.983488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 11:35:18.984000 ==
3606 11:35:18.984330 RX Vref Scan: 0
3607 11:35:18.984635
3608 11:35:18.986186 RX Vref 0 -> 0, step: 1
3609 11:35:18.986597
3610 11:35:18.989734 RX Delay -40 -> 252, step: 8
3611 11:35:18.992651 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3612 11:35:18.996395 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3613 11:35:18.999653 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3614 11:35:19.006418 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3615 11:35:19.009805 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3616 11:35:19.012742 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3617 11:35:19.016284 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3618 11:35:19.019168 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3619 11:35:19.026265 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3620 11:35:19.029195 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3621 11:35:19.032444 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3622 11:35:19.035786 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3623 11:35:19.039193 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3624 11:35:19.046060 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3625 11:35:19.048906 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3626 11:35:19.052091 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3627 11:35:19.052375 ==
3628 11:35:19.055503 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 11:35:19.058620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 11:35:19.062245 ==
3631 11:35:19.062430 DQS Delay:
3632 11:35:19.062560 DQS0 = 0, DQS1 = 0
3633 11:35:19.065360 DQM Delay:
3634 11:35:19.065512 DQM0 = 117, DQM1 = 109
3635 11:35:19.068902 DQ Delay:
3636 11:35:19.071952 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3637 11:35:19.075169 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3638 11:35:19.078361 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3639 11:35:19.081650 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3640 11:35:19.081755
3641 11:35:19.081830
3642 11:35:19.081947 ==
3643 11:35:19.084971 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 11:35:19.088490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 11:35:19.088568 ==
3646 11:35:19.091589
3647 11:35:19.091673
3648 11:35:19.091733 TX Vref Scan disable
3649 11:35:19.094874 == TX Byte 0 ==
3650 11:35:19.098488 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3651 11:35:19.101595 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3652 11:35:19.104740 == TX Byte 1 ==
3653 11:35:19.108231 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3654 11:35:19.111219 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3655 11:35:19.111311 ==
3656 11:35:19.114599 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 11:35:19.121199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 11:35:19.121280 ==
3659 11:35:19.132323 TX Vref=22, minBit 1, minWin=26, winSum=426
3660 11:35:19.135776 TX Vref=24, minBit 8, minWin=26, winSum=429
3661 11:35:19.138872 TX Vref=26, minBit 8, minWin=26, winSum=431
3662 11:35:19.142359 TX Vref=28, minBit 10, minWin=26, winSum=436
3663 11:35:19.145631 TX Vref=30, minBit 9, minWin=26, winSum=437
3664 11:35:19.152196 TX Vref=32, minBit 7, minWin=26, winSum=432
3665 11:35:19.155209 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3666 11:35:19.155470
3667 11:35:19.158634 Final TX Range 1 Vref 30
3668 11:35:19.158932
3669 11:35:19.159212 ==
3670 11:35:19.162062 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 11:35:19.165704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 11:35:19.168720 ==
3673 11:35:19.169010
3674 11:35:19.169256
3675 11:35:19.169472 TX Vref Scan disable
3676 11:35:19.172353 == TX Byte 0 ==
3677 11:35:19.175493 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3678 11:35:19.181929 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3679 11:35:19.182333 == TX Byte 1 ==
3680 11:35:19.185490 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3681 11:35:19.191937 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3682 11:35:19.192236
3683 11:35:19.192470 [DATLAT]
3684 11:35:19.192687 Freq=1200, CH1 RK1
3685 11:35:19.192894
3686 11:35:19.195376 DATLAT Default: 0xd
3687 11:35:19.195761 0, 0xFFFF, sum = 0
3688 11:35:19.198579 1, 0xFFFF, sum = 0
3689 11:35:19.202341 2, 0xFFFF, sum = 0
3690 11:35:19.202641 3, 0xFFFF, sum = 0
3691 11:35:19.205338 4, 0xFFFF, sum = 0
3692 11:35:19.205639 5, 0xFFFF, sum = 0
3693 11:35:19.208713 6, 0xFFFF, sum = 0
3694 11:35:19.209012 7, 0xFFFF, sum = 0
3695 11:35:19.211917 8, 0xFFFF, sum = 0
3696 11:35:19.212217 9, 0xFFFF, sum = 0
3697 11:35:19.215104 10, 0xFFFF, sum = 0
3698 11:35:19.215405 11, 0xFFFF, sum = 0
3699 11:35:19.218733 12, 0x0, sum = 1
3700 11:35:19.219119 13, 0x0, sum = 2
3701 11:35:19.221706 14, 0x0, sum = 3
3702 11:35:19.222092 15, 0x0, sum = 4
3703 11:35:19.225253 best_step = 13
3704 11:35:19.225709
3705 11:35:19.226009 ==
3706 11:35:19.228895 Dram Type= 6, Freq= 0, CH_1, rank 1
3707 11:35:19.231524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3708 11:35:19.231908 ==
3709 11:35:19.234863 RX Vref Scan: 0
3710 11:35:19.235241
3711 11:35:19.235589 RX Vref 0 -> 0, step: 1
3712 11:35:19.235876
3713 11:35:19.238374 RX Delay -21 -> 252, step: 4
3714 11:35:19.245076 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3715 11:35:19.248384 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3716 11:35:19.251688 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3717 11:35:19.254888 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3718 11:35:19.258088 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3719 11:35:19.264920 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3720 11:35:19.268196 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3721 11:35:19.271641 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3722 11:35:19.274642 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3723 11:35:19.277931 iDelay=199, Bit 9, Center 98 (31 ~ 166) 136
3724 11:35:19.285047 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3725 11:35:19.287695 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3726 11:35:19.291077 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3727 11:35:19.294615 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3728 11:35:19.297854 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3729 11:35:19.304376 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3730 11:35:19.304759 ==
3731 11:35:19.307734 Dram Type= 6, Freq= 0, CH_1, rank 1
3732 11:35:19.310728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3733 11:35:19.311110 ==
3734 11:35:19.311411 DQS Delay:
3735 11:35:19.314462 DQS0 = 0, DQS1 = 0
3736 11:35:19.314840 DQM Delay:
3737 11:35:19.317761 DQM0 = 117, DQM1 = 109
3738 11:35:19.318143 DQ Delay:
3739 11:35:19.320630 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3740 11:35:19.324425 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3741 11:35:19.327664 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =98
3742 11:35:19.330863 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3743 11:35:19.331253
3744 11:35:19.334092
3745 11:35:19.340543 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3746 11:35:19.344113 CH1 RK1: MR19=303, MR18=F1EC
3747 11:35:19.350877 CH1_RK1: MR19=0x303, MR18=0xF1EC, DQSOSC=416, MR23=63, INC=37, DEC=25
3748 11:35:19.353710 [RxdqsGatingPostProcess] freq 1200
3749 11:35:19.357339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3750 11:35:19.360568 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 11:35:19.363904 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 11:35:19.366650 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 11:35:19.370422 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 11:35:19.373754 best DQS0 dly(2T, 0.5T) = (0, 11)
3755 11:35:19.377027 best DQS1 dly(2T, 0.5T) = (0, 11)
3756 11:35:19.380230 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3757 11:35:19.383409 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3758 11:35:19.386637 Pre-setting of DQS Precalculation
3759 11:35:19.389826 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3760 11:35:19.399796 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3761 11:35:19.406559 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3762 11:35:19.406767
3763 11:35:19.406926
3764 11:35:19.410203 [Calibration Summary] 2400 Mbps
3765 11:35:19.410455 CH 0, Rank 0
3766 11:35:19.413065 SW Impedance : PASS
3767 11:35:19.413388 DUTY Scan : NO K
3768 11:35:19.416704 ZQ Calibration : PASS
3769 11:35:19.420296 Jitter Meter : NO K
3770 11:35:19.420675 CBT Training : PASS
3771 11:35:19.423805 Write leveling : PASS
3772 11:35:19.426536 RX DQS gating : PASS
3773 11:35:19.426921 RX DQ/DQS(RDDQC) : PASS
3774 11:35:19.430331 TX DQ/DQS : PASS
3775 11:35:19.433359 RX DATLAT : PASS
3776 11:35:19.433825 RX DQ/DQS(Engine): PASS
3777 11:35:19.436799 TX OE : NO K
3778 11:35:19.437301 All Pass.
3779 11:35:19.437635
3780 11:35:19.440311 CH 0, Rank 1
3781 11:35:19.440813 SW Impedance : PASS
3782 11:35:19.443117 DUTY Scan : NO K
3783 11:35:19.443585 ZQ Calibration : PASS
3784 11:35:19.446689 Jitter Meter : NO K
3785 11:35:19.450013 CBT Training : PASS
3786 11:35:19.450396 Write leveling : PASS
3787 11:35:19.453014 RX DQS gating : PASS
3788 11:35:19.456183 RX DQ/DQS(RDDQC) : PASS
3789 11:35:19.456566 TX DQ/DQS : PASS
3790 11:35:19.459342 RX DATLAT : PASS
3791 11:35:19.462640 RX DQ/DQS(Engine): PASS
3792 11:35:19.463140 TX OE : NO K
3793 11:35:19.466433 All Pass.
3794 11:35:19.466813
3795 11:35:19.467115 CH 1, Rank 0
3796 11:35:19.469653 SW Impedance : PASS
3797 11:35:19.470039 DUTY Scan : NO K
3798 11:35:19.472854 ZQ Calibration : PASS
3799 11:35:19.476372 Jitter Meter : NO K
3800 11:35:19.476862 CBT Training : PASS
3801 11:35:19.479216 Write leveling : PASS
3802 11:35:19.482849 RX DQS gating : PASS
3803 11:35:19.483319 RX DQ/DQS(RDDQC) : PASS
3804 11:35:19.486458 TX DQ/DQS : PASS
3805 11:35:19.489362 RX DATLAT : PASS
3806 11:35:19.489749 RX DQ/DQS(Engine): PASS
3807 11:35:19.492689 TX OE : NO K
3808 11:35:19.493090 All Pass.
3809 11:35:19.493464
3810 11:35:19.495874 CH 1, Rank 1
3811 11:35:19.496310 SW Impedance : PASS
3812 11:35:19.498966 DUTY Scan : NO K
3813 11:35:19.502523 ZQ Calibration : PASS
3814 11:35:19.503024 Jitter Meter : NO K
3815 11:35:19.505926 CBT Training : PASS
3816 11:35:19.508889 Write leveling : PASS
3817 11:35:19.509291 RX DQS gating : PASS
3818 11:35:19.512100 RX DQ/DQS(RDDQC) : PASS
3819 11:35:19.515311 TX DQ/DQS : PASS
3820 11:35:19.515779 RX DATLAT : PASS
3821 11:35:19.518664 RX DQ/DQS(Engine): PASS
3822 11:35:19.522306 TX OE : NO K
3823 11:35:19.522721 All Pass.
3824 11:35:19.523102
3825 11:35:19.523420 DramC Write-DBI off
3826 11:35:19.525517 PER_BANK_REFRESH: Hybrid Mode
3827 11:35:19.529023 TX_TRACKING: ON
3828 11:35:19.535643 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3829 11:35:19.538901 [FAST_K] Save calibration result to emmc
3830 11:35:19.545194 dramc_set_vcore_voltage set vcore to 650000
3831 11:35:19.545575 Read voltage for 600, 5
3832 11:35:19.548592 Vio18 = 0
3833 11:35:19.548968 Vcore = 650000
3834 11:35:19.549260 Vdram = 0
3835 11:35:19.551808 Vddq = 0
3836 11:35:19.552260 Vmddr = 0
3837 11:35:19.555569 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3838 11:35:19.561835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3839 11:35:19.564891 MEM_TYPE=3, freq_sel=19
3840 11:35:19.568285 sv_algorithm_assistance_LP4_1600
3841 11:35:19.571300 ============ PULL DRAM RESETB DOWN ============
3842 11:35:19.575009 ========== PULL DRAM RESETB DOWN end =========
3843 11:35:19.578217 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3844 11:35:19.581784 ===================================
3845 11:35:19.584935 LPDDR4 DRAM CONFIGURATION
3846 11:35:19.588235 ===================================
3847 11:35:19.591482 EX_ROW_EN[0] = 0x0
3848 11:35:19.591950 EX_ROW_EN[1] = 0x0
3849 11:35:19.595100 LP4Y_EN = 0x0
3850 11:35:19.595641 WORK_FSP = 0x0
3851 11:35:19.598133 WL = 0x2
3852 11:35:19.598642 RL = 0x2
3853 11:35:19.601093 BL = 0x2
3854 11:35:19.604639 RPST = 0x0
3855 11:35:19.605118 RD_PRE = 0x0
3856 11:35:19.607775 WR_PRE = 0x1
3857 11:35:19.608145 WR_PST = 0x0
3858 11:35:19.610751 DBI_WR = 0x0
3859 11:35:19.610984 DBI_RD = 0x0
3860 11:35:19.614228 OTF = 0x1
3861 11:35:19.617612 ===================================
3862 11:35:19.621039 ===================================
3863 11:35:19.621205 ANA top config
3864 11:35:19.623838 ===================================
3865 11:35:19.627402 DLL_ASYNC_EN = 0
3866 11:35:19.630975 ALL_SLAVE_EN = 1
3867 11:35:19.631141 NEW_RANK_MODE = 1
3868 11:35:19.633687 DLL_IDLE_MODE = 1
3869 11:35:19.637795 LP45_APHY_COMB_EN = 1
3870 11:35:19.640391 TX_ODT_DIS = 1
3871 11:35:19.643870 NEW_8X_MODE = 1
3872 11:35:19.647278 ===================================
3873 11:35:19.650410 ===================================
3874 11:35:19.650576 data_rate = 1200
3875 11:35:19.654080 CKR = 1
3876 11:35:19.657427 DQ_P2S_RATIO = 8
3877 11:35:19.660407 ===================================
3878 11:35:19.663984 CA_P2S_RATIO = 8
3879 11:35:19.667184 DQ_CA_OPEN = 0
3880 11:35:19.670384 DQ_SEMI_OPEN = 0
3881 11:35:19.670552 CA_SEMI_OPEN = 0
3882 11:35:19.673625 CA_FULL_RATE = 0
3883 11:35:19.676930 DQ_CKDIV4_EN = 1
3884 11:35:19.679938 CA_CKDIV4_EN = 1
3885 11:35:19.683656 CA_PREDIV_EN = 0
3886 11:35:19.687219 PH8_DLY = 0
3887 11:35:19.687385 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3888 11:35:19.689846 DQ_AAMCK_DIV = 4
3889 11:35:19.693165 CA_AAMCK_DIV = 4
3890 11:35:19.696338 CA_ADMCK_DIV = 4
3891 11:35:19.699837 DQ_TRACK_CA_EN = 0
3892 11:35:19.703221 CA_PICK = 600
3893 11:35:19.707124 CA_MCKIO = 600
3894 11:35:19.707290 MCKIO_SEMI = 0
3895 11:35:19.709886 PLL_FREQ = 2288
3896 11:35:19.712996 DQ_UI_PI_RATIO = 32
3897 11:35:19.716271 CA_UI_PI_RATIO = 0
3898 11:35:19.720086 ===================================
3899 11:35:19.723437 ===================================
3900 11:35:19.726221 memory_type:LPDDR4
3901 11:35:19.726405 GP_NUM : 10
3902 11:35:19.729548 SRAM_EN : 1
3903 11:35:19.732748 MD32_EN : 0
3904 11:35:19.736194 ===================================
3905 11:35:19.736412 [ANA_INIT] >>>>>>>>>>>>>>
3906 11:35:19.739840 <<<<<< [CONFIGURE PHASE]: ANA_TX
3907 11:35:19.742815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3908 11:35:19.746175 ===================================
3909 11:35:19.749225 data_rate = 1200,PCW = 0X5800
3910 11:35:19.752716 ===================================
3911 11:35:19.756458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3912 11:35:19.762798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3913 11:35:19.766337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3914 11:35:19.772716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3915 11:35:19.776245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3916 11:35:19.779078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3917 11:35:19.779301 [ANA_INIT] flow start
3918 11:35:19.783179 [ANA_INIT] PLL >>>>>>>>
3919 11:35:19.785915 [ANA_INIT] PLL <<<<<<<<
3920 11:35:19.789054 [ANA_INIT] MIDPI >>>>>>>>
3921 11:35:19.789274 [ANA_INIT] MIDPI <<<<<<<<
3922 11:35:19.792281 [ANA_INIT] DLL >>>>>>>>
3923 11:35:19.795642 [ANA_INIT] flow end
3924 11:35:19.798781 ============ LP4 DIFF to SE enter ============
3925 11:35:19.802340 ============ LP4 DIFF to SE exit ============
3926 11:35:19.805675 [ANA_INIT] <<<<<<<<<<<<<
3927 11:35:19.808851 [Flow] Enable top DCM control >>>>>
3928 11:35:19.812444 [Flow] Enable top DCM control <<<<<
3929 11:35:19.815861 Enable DLL master slave shuffle
3930 11:35:19.819017 ==============================================================
3931 11:35:19.822497 Gating Mode config
3932 11:35:19.828969 ==============================================================
3933 11:35:19.829190 Config description:
3934 11:35:19.838973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3935 11:35:19.845584 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3936 11:35:19.848658 SELPH_MODE 0: By rank 1: By Phase
3937 11:35:19.855519 ==============================================================
3938 11:35:19.858515 GAT_TRACK_EN = 1
3939 11:35:19.862004 RX_GATING_MODE = 2
3940 11:35:19.865301 RX_GATING_TRACK_MODE = 2
3941 11:35:19.868387 SELPH_MODE = 1
3942 11:35:19.871661 PICG_EARLY_EN = 1
3943 11:35:19.875132 VALID_LAT_VALUE = 1
3944 11:35:19.878102 ==============================================================
3945 11:35:19.881586 Enter into Gating configuration >>>>
3946 11:35:19.884980 Exit from Gating configuration <<<<
3947 11:35:19.888163 Enter into DVFS_PRE_config >>>>>
3948 11:35:19.901161 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3949 11:35:19.904584 Exit from DVFS_PRE_config <<<<<
3950 11:35:19.907688 Enter into PICG configuration >>>>
3951 11:35:19.907765 Exit from PICG configuration <<<<
3952 11:35:19.910971 [RX_INPUT] configuration >>>>>
3953 11:35:19.914532 [RX_INPUT] configuration <<<<<
3954 11:35:19.921215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3955 11:35:19.924472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3956 11:35:19.930790 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3957 11:35:19.937457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3958 11:35:19.944285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3959 11:35:19.950478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3960 11:35:19.954165 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3961 11:35:19.957449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3962 11:35:19.963989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3963 11:35:19.967149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3964 11:35:19.971179 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3965 11:35:19.974423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3966 11:35:19.977925 ===================================
3967 11:35:19.981047 LPDDR4 DRAM CONFIGURATION
3968 11:35:19.984426 ===================================
3969 11:35:19.987287 EX_ROW_EN[0] = 0x0
3970 11:35:19.987741 EX_ROW_EN[1] = 0x0
3971 11:35:19.990815 LP4Y_EN = 0x0
3972 11:35:19.991197 WORK_FSP = 0x0
3973 11:35:19.993944 WL = 0x2
3974 11:35:19.994325 RL = 0x2
3975 11:35:19.997300 BL = 0x2
3976 11:35:19.997678 RPST = 0x0
3977 11:35:20.000564 RD_PRE = 0x0
3978 11:35:20.003572 WR_PRE = 0x1
3979 11:35:20.004106 WR_PST = 0x0
3980 11:35:20.007100 DBI_WR = 0x0
3981 11:35:20.007623 DBI_RD = 0x0
3982 11:35:20.010329 OTF = 0x1
3983 11:35:20.013754 ===================================
3984 11:35:20.017065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3985 11:35:20.020474 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3986 11:35:20.023683 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3987 11:35:20.026652 ===================================
3988 11:35:20.029984 LPDDR4 DRAM CONFIGURATION
3989 11:35:20.033548 ===================================
3990 11:35:20.037029 EX_ROW_EN[0] = 0x10
3991 11:35:20.037412 EX_ROW_EN[1] = 0x0
3992 11:35:20.039851 LP4Y_EN = 0x0
3993 11:35:20.040228 WORK_FSP = 0x0
3994 11:35:20.043500 WL = 0x2
3995 11:35:20.043881 RL = 0x2
3996 11:35:20.046496 BL = 0x2
3997 11:35:20.050154 RPST = 0x0
3998 11:35:20.050557 RD_PRE = 0x0
3999 11:35:20.053239 WR_PRE = 0x1
4000 11:35:20.053486 WR_PST = 0x0
4001 11:35:20.056641 DBI_WR = 0x0
4002 11:35:20.056910 DBI_RD = 0x0
4003 11:35:20.060360 OTF = 0x1
4004 11:35:20.062807 ===================================
4005 11:35:20.066170 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4006 11:35:20.071958 nWR fixed to 30
4007 11:35:20.074929 [ModeRegInit_LP4] CH0 RK0
4008 11:35:20.075096 [ModeRegInit_LP4] CH0 RK1
4009 11:35:20.078238 [ModeRegInit_LP4] CH1 RK0
4010 11:35:20.081467 [ModeRegInit_LP4] CH1 RK1
4011 11:35:20.081605 match AC timing 17
4012 11:35:20.087935 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4013 11:35:20.091364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4014 11:35:20.094704 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4015 11:35:20.101139 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4016 11:35:20.104513 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4017 11:35:20.104635 ==
4018 11:35:20.108272 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 11:35:20.111105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 11:35:20.111236 ==
4021 11:35:20.117393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4022 11:35:20.123989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4023 11:35:20.127289 [CA 0] Center 36 (6~66) winsize 61
4024 11:35:20.130777 [CA 1] Center 36 (6~66) winsize 61
4025 11:35:20.134362 [CA 2] Center 34 (4~65) winsize 62
4026 11:35:20.137519 [CA 3] Center 34 (4~65) winsize 62
4027 11:35:20.140535 [CA 4] Center 33 (3~64) winsize 62
4028 11:35:20.144030 [CA 5] Center 33 (3~64) winsize 62
4029 11:35:20.144104
4030 11:35:20.147287 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4031 11:35:20.147387
4032 11:35:20.150235 [CATrainingPosCal] consider 1 rank data
4033 11:35:20.153764 u2DelayCellTimex100 = 270/100 ps
4034 11:35:20.157331 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4035 11:35:20.160633 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 11:35:20.167190 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4037 11:35:20.170500 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4038 11:35:20.173290 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4039 11:35:20.176713 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4040 11:35:20.176792
4041 11:35:20.180012 CA PerBit enable=1, Macro0, CA PI delay=33
4042 11:35:20.180110
4043 11:35:20.183337 [CBTSetCACLKResult] CA Dly = 33
4044 11:35:20.183458 CS Dly: 5 (0~36)
4045 11:35:20.183554 ==
4046 11:35:20.186764 Dram Type= 6, Freq= 0, CH_0, rank 1
4047 11:35:20.193490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:35:20.193567 ==
4049 11:35:20.196964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4050 11:35:20.203264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4051 11:35:20.206803 [CA 0] Center 36 (6~66) winsize 61
4052 11:35:20.210360 [CA 1] Center 36 (6~66) winsize 61
4053 11:35:20.213641 [CA 2] Center 34 (4~64) winsize 61
4054 11:35:20.216918 [CA 3] Center 34 (4~64) winsize 61
4055 11:35:20.220585 [CA 4] Center 33 (2~64) winsize 63
4056 11:35:20.223731 [CA 5] Center 33 (3~64) winsize 62
4057 11:35:20.224113
4058 11:35:20.226993 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4059 11:35:20.227537
4060 11:35:20.230534 [CATrainingPosCal] consider 2 rank data
4061 11:35:20.233652 u2DelayCellTimex100 = 270/100 ps
4062 11:35:20.236740 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4063 11:35:20.243335 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4064 11:35:20.247003 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4065 11:35:20.250249 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4066 11:35:20.253335 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4067 11:35:20.256878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4068 11:35:20.257264
4069 11:35:20.259679 CA PerBit enable=1, Macro0, CA PI delay=33
4070 11:35:20.260013
4071 11:35:20.263257 [CBTSetCACLKResult] CA Dly = 33
4072 11:35:20.266374 CS Dly: 6 (0~38)
4073 11:35:20.266610
4074 11:35:20.269776 ----->DramcWriteLeveling(PI) begin...
4075 11:35:20.269945 ==
4076 11:35:20.272926 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 11:35:20.276414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 11:35:20.276555 ==
4079 11:35:20.280043 Write leveling (Byte 0): 34 => 34
4080 11:35:20.282700 Write leveling (Byte 1): 29 => 29
4081 11:35:20.286004 DramcWriteLeveling(PI) end<-----
4082 11:35:20.286079
4083 11:35:20.286136 ==
4084 11:35:20.289390 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 11:35:20.292734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 11:35:20.292809 ==
4087 11:35:20.295702 [Gating] SW mode calibration
4088 11:35:20.302409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4089 11:35:20.309442 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4090 11:35:20.312316 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4091 11:35:20.315938 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4092 11:35:20.322254 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4093 11:35:20.325769 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4094 11:35:20.328848 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4095 11:35:20.335512 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 11:35:20.339217 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 11:35:20.342311 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 11:35:20.348565 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 11:35:20.352474 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 11:35:20.355304 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 11:35:20.361944 0 10 12 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4102 11:35:20.365323 0 10 16 | B1->B0 | 2f2e 4545 | 1 0 | (0 0) (0 0)
4103 11:35:20.368231 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 11:35:20.375210 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 11:35:20.378295 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 11:35:20.381911 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 11:35:20.388219 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 11:35:20.391602 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 11:35:20.394656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 11:35:20.401169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4111 11:35:20.404741 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 11:35:20.407761 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 11:35:20.414418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 11:35:20.417673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 11:35:20.420940 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 11:35:20.428065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 11:35:20.431277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 11:35:20.434175 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 11:35:20.441218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 11:35:20.444409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 11:35:20.447852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 11:35:20.454246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 11:35:20.457318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 11:35:20.460907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 11:35:20.467306 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 11:35:20.470731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4127 11:35:20.474067 Total UI for P1: 0, mck2ui 16
4128 11:35:20.477284 best dqsien dly found for B0: ( 0, 13, 14)
4129 11:35:20.480340 Total UI for P1: 0, mck2ui 16
4130 11:35:20.483937 best dqsien dly found for B1: ( 0, 13, 14)
4131 11:35:20.487638 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4132 11:35:20.490400 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4133 11:35:20.490476
4134 11:35:20.494023 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4135 11:35:20.497101 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4136 11:35:20.500827 [Gating] SW calibration Done
4137 11:35:20.500903 ==
4138 11:35:20.504009 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 11:35:20.510284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 11:35:20.510362 ==
4141 11:35:20.510438 RX Vref Scan: 0
4142 11:35:20.510510
4143 11:35:20.513768 RX Vref 0 -> 0, step: 1
4144 11:35:20.513849
4145 11:35:20.517092 RX Delay -230 -> 252, step: 16
4146 11:35:20.520201 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4147 11:35:20.523658 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4148 11:35:20.527192 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4149 11:35:20.533351 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4150 11:35:20.536896 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4151 11:35:20.540581 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4152 11:35:20.543658 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4153 11:35:20.550220 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4154 11:35:20.553725 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4155 11:35:20.557042 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4156 11:35:20.560263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4157 11:35:20.566606 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4158 11:35:20.569947 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4159 11:35:20.573319 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4160 11:35:20.576395 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4161 11:35:20.583312 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4162 11:35:20.583566 ==
4163 11:35:20.586374 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 11:35:20.589716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:35:20.589791 ==
4166 11:35:20.589849 DQS Delay:
4167 11:35:20.593214 DQS0 = 0, DQS1 = 0
4168 11:35:20.593289 DQM Delay:
4169 11:35:20.596342 DQM0 = 46, DQM1 = 29
4170 11:35:20.596416 DQ Delay:
4171 11:35:20.599348 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =49
4172 11:35:20.603051 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4173 11:35:20.606865 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4174 11:35:20.609467 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4175 11:35:20.609542
4176 11:35:20.609600
4177 11:35:20.609653 ==
4178 11:35:20.612726 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 11:35:20.616122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 11:35:20.616197 ==
4181 11:35:20.616256
4182 11:35:20.619742
4183 11:35:20.619816 TX Vref Scan disable
4184 11:35:20.622870 == TX Byte 0 ==
4185 11:35:20.626173 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4186 11:35:20.629685 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4187 11:35:20.632552 == TX Byte 1 ==
4188 11:35:20.635856 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4189 11:35:20.639424 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4190 11:35:20.639521 ==
4191 11:35:20.642536 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 11:35:20.649009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 11:35:20.649084 ==
4194 11:35:20.649142
4195 11:35:20.649196
4196 11:35:20.652270 TX Vref Scan disable
4197 11:35:20.652344 == TX Byte 0 ==
4198 11:35:20.659488 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4199 11:35:20.662366 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4200 11:35:20.662441 == TX Byte 1 ==
4201 11:35:20.668930 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4202 11:35:20.672642 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4203 11:35:20.672717
4204 11:35:20.672774 [DATLAT]
4205 11:35:20.675879 Freq=600, CH0 RK0
4206 11:35:20.675954
4207 11:35:20.676011 DATLAT Default: 0x9
4208 11:35:20.678973 0, 0xFFFF, sum = 0
4209 11:35:20.679048 1, 0xFFFF, sum = 0
4210 11:35:20.681944 2, 0xFFFF, sum = 0
4211 11:35:20.685213 3, 0xFFFF, sum = 0
4212 11:35:20.685289 4, 0xFFFF, sum = 0
4213 11:35:20.688687 5, 0xFFFF, sum = 0
4214 11:35:20.688763 6, 0xFFFF, sum = 0
4215 11:35:20.692070 7, 0xFFFF, sum = 0
4216 11:35:20.692146 8, 0x0, sum = 1
4217 11:35:20.695036 9, 0x0, sum = 2
4218 11:35:20.695111 10, 0x0, sum = 3
4219 11:35:20.695170 11, 0x0, sum = 4
4220 11:35:20.698885 best_step = 9
4221 11:35:20.698959
4222 11:35:20.699016 ==
4223 11:35:20.701661 Dram Type= 6, Freq= 0, CH_0, rank 0
4224 11:35:20.705196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:35:20.705271 ==
4226 11:35:20.708392 RX Vref Scan: 1
4227 11:35:20.708496
4228 11:35:20.711745 RX Vref 0 -> 0, step: 1
4229 11:35:20.711819
4230 11:35:20.711878 RX Delay -195 -> 252, step: 8
4231 11:35:20.711931
4232 11:35:20.714941 Set Vref, RX VrefLevel [Byte0]: 66
4233 11:35:20.718146 [Byte1]: 58
4234 11:35:20.723056
4235 11:35:20.723131 Final RX Vref Byte 0 = 66 to rank0
4236 11:35:20.726297 Final RX Vref Byte 1 = 58 to rank0
4237 11:35:20.729405 Final RX Vref Byte 0 = 66 to rank1
4238 11:35:20.732477 Final RX Vref Byte 1 = 58 to rank1==
4239 11:35:20.735806 Dram Type= 6, Freq= 0, CH_0, rank 0
4240 11:35:20.742657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:35:20.742732 ==
4242 11:35:20.742791 DQS Delay:
4243 11:35:20.745894 DQS0 = 0, DQS1 = 0
4244 11:35:20.745970 DQM Delay:
4245 11:35:20.746028 DQM0 = 44, DQM1 = 32
4246 11:35:20.749107 DQ Delay:
4247 11:35:20.752328 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4248 11:35:20.756005 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =52
4249 11:35:20.759588 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4250 11:35:20.762289 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4251 11:35:20.762363
4252 11:35:20.762421
4253 11:35:20.769045 [DQSOSCAuto] RK0, (LSB)MR18= 0x653c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4254 11:35:20.772705 CH0 RK0: MR19=808, MR18=653C
4255 11:35:20.778856 CH0_RK0: MR19=0x808, MR18=0x653C, DQSOSC=390, MR23=63, INC=172, DEC=114
4256 11:35:20.778939
4257 11:35:20.782493 ----->DramcWriteLeveling(PI) begin...
4258 11:35:20.782568 ==
4259 11:35:20.785754 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 11:35:20.788767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 11:35:20.788841 ==
4262 11:35:20.792308 Write leveling (Byte 0): 32 => 32
4263 11:35:20.795532 Write leveling (Byte 1): 32 => 32
4264 11:35:20.799087 DramcWriteLeveling(PI) end<-----
4265 11:35:20.799160
4266 11:35:20.799218 ==
4267 11:35:20.801841 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:35:20.805444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:35:20.808525 ==
4270 11:35:20.808599 [Gating] SW mode calibration
4271 11:35:20.818386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4272 11:35:20.821945 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4273 11:35:20.825229 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4274 11:35:20.832369 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4275 11:35:20.835050 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4276 11:35:20.838624 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4277 11:35:20.845061 0 9 16 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
4278 11:35:20.848470 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 11:35:20.851697 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 11:35:20.858149 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 11:35:20.861706 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 11:35:20.865105 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 11:35:20.871605 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 11:35:20.874501 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4285 11:35:20.878316 0 10 16 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
4286 11:35:20.884764 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 11:35:20.888296 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 11:35:20.890983 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 11:35:20.897614 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 11:35:20.901091 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 11:35:20.904270 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 11:35:20.910874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4293 11:35:20.913959 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:35:20.917751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 11:35:20.924403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:35:20.927581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 11:35:20.930986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 11:35:20.937428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 11:35:20.940847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 11:35:20.944062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 11:35:20.951068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 11:35:20.953802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 11:35:20.957375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 11:35:20.963574 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 11:35:20.967175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 11:35:20.970233 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 11:35:20.977185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 11:35:20.980324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 11:35:20.983606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4310 11:35:20.986727 Total UI for P1: 0, mck2ui 16
4311 11:35:20.990002 best dqsien dly found for B0: ( 0, 13, 14)
4312 11:35:20.997413 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 11:35:20.997836 Total UI for P1: 0, mck2ui 16
4314 11:35:21.003474 best dqsien dly found for B1: ( 0, 13, 16)
4315 11:35:21.006682 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4316 11:35:21.009798 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4317 11:35:21.010193
4318 11:35:21.013350 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4319 11:35:21.016523 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4320 11:35:21.019678 [Gating] SW calibration Done
4321 11:35:21.020074 ==
4322 11:35:21.023085 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 11:35:21.026312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 11:35:21.026708 ==
4325 11:35:21.029838 RX Vref Scan: 0
4326 11:35:21.030221
4327 11:35:21.033198 RX Vref 0 -> 0, step: 1
4328 11:35:21.033582
4329 11:35:21.033881 RX Delay -230 -> 252, step: 16
4330 11:35:21.039951 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4331 11:35:21.043557 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4332 11:35:21.046386 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4333 11:35:21.049775 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4334 11:35:21.056524 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4335 11:35:21.059788 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4336 11:35:21.063087 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4337 11:35:21.066332 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4338 11:35:21.069547 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4339 11:35:21.075901 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4340 11:35:21.079292 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4341 11:35:21.082801 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4342 11:35:21.085932 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4343 11:35:21.092887 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4344 11:35:21.096044 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4345 11:35:21.099242 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4346 11:35:21.099774 ==
4347 11:35:21.102431 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 11:35:21.109164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 11:35:21.109551 ==
4350 11:35:21.109853 DQS Delay:
4351 11:35:21.110130 DQS0 = 0, DQS1 = 0
4352 11:35:21.112582 DQM Delay:
4353 11:35:21.112963 DQM0 = 41, DQM1 = 36
4354 11:35:21.116042 DQ Delay:
4355 11:35:21.119231 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4356 11:35:21.119785 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4357 11:35:21.122654 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4358 11:35:21.129144 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4359 11:35:21.129525
4360 11:35:21.129824
4361 11:35:21.130100 ==
4362 11:35:21.132687 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 11:35:21.135739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:35:21.136172 ==
4365 11:35:21.136476
4366 11:35:21.136752
4367 11:35:21.139064 TX Vref Scan disable
4368 11:35:21.139492 == TX Byte 0 ==
4369 11:35:21.145557 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4370 11:35:21.149285 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4371 11:35:21.149668 == TX Byte 1 ==
4372 11:35:21.155674 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4373 11:35:21.158572 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4374 11:35:21.158957 ==
4375 11:35:21.161869 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 11:35:21.165445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 11:35:21.165720 ==
4378 11:35:21.168417
4379 11:35:21.168620
4380 11:35:21.168781 TX Vref Scan disable
4381 11:35:21.172389 == TX Byte 0 ==
4382 11:35:21.175039 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4383 11:35:21.181568 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4384 11:35:21.181718 == TX Byte 1 ==
4385 11:35:21.184926 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4386 11:35:21.191773 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4387 11:35:21.191911
4388 11:35:21.192018 [DATLAT]
4389 11:35:21.192118 Freq=600, CH0 RK1
4390 11:35:21.192213
4391 11:35:21.194881 DATLAT Default: 0x9
4392 11:35:21.198299 0, 0xFFFF, sum = 0
4393 11:35:21.198438 1, 0xFFFF, sum = 0
4394 11:35:21.201510 2, 0xFFFF, sum = 0
4395 11:35:21.201650 3, 0xFFFF, sum = 0
4396 11:35:21.204755 4, 0xFFFF, sum = 0
4397 11:35:21.204899 5, 0xFFFF, sum = 0
4398 11:35:21.208312 6, 0xFFFF, sum = 0
4399 11:35:21.208471 7, 0xFFFF, sum = 0
4400 11:35:21.211311 8, 0x0, sum = 1
4401 11:35:21.211486 9, 0x0, sum = 2
4402 11:35:21.214743 10, 0x0, sum = 3
4403 11:35:21.214927 11, 0x0, sum = 4
4404 11:35:21.215072 best_step = 9
4405 11:35:21.215201
4406 11:35:21.217803 ==
4407 11:35:21.221445 Dram Type= 6, Freq= 0, CH_0, rank 1
4408 11:35:21.224917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 11:35:21.225189 ==
4410 11:35:21.225402 RX Vref Scan: 0
4411 11:35:21.225596
4412 11:35:21.227920 RX Vref 0 -> 0, step: 1
4413 11:35:21.228274
4414 11:35:21.231486 RX Delay -179 -> 252, step: 8
4415 11:35:21.238660 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4416 11:35:21.241239 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4417 11:35:21.244480 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4418 11:35:21.248055 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4419 11:35:21.254313 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4420 11:35:21.257757 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4421 11:35:21.261458 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4422 11:35:21.264709 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4423 11:35:21.267671 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4424 11:35:21.274678 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4425 11:35:21.277667 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4426 11:35:21.281097 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4427 11:35:21.284159 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4428 11:35:21.290914 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4429 11:35:21.294302 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4430 11:35:21.297502 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4431 11:35:21.297883 ==
4432 11:35:21.300864 Dram Type= 6, Freq= 0, CH_0, rank 1
4433 11:35:21.307242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 11:35:21.307659 ==
4435 11:35:21.307963 DQS Delay:
4436 11:35:21.308236 DQS0 = 0, DQS1 = 0
4437 11:35:21.310567 DQM Delay:
4438 11:35:21.310944 DQM0 = 39, DQM1 = 35
4439 11:35:21.314275 DQ Delay:
4440 11:35:21.317657 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4441 11:35:21.320278 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4442 11:35:21.320659 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4443 11:35:21.327222 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4444 11:35:21.327696
4445 11:35:21.328001
4446 11:35:21.333575 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4447 11:35:21.336943 CH0 RK1: MR19=808, MR18=5F12
4448 11:35:21.343496 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4449 11:35:21.346808 [RxdqsGatingPostProcess] freq 600
4450 11:35:21.349940 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4451 11:35:21.353567 Pre-setting of DQS Precalculation
4452 11:35:21.359808 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4453 11:35:21.360316 ==
4454 11:35:21.363217 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 11:35:21.366888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 11:35:21.367277 ==
4457 11:35:21.373602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4458 11:35:21.379793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4459 11:35:21.382960 [CA 0] Center 35 (5~66) winsize 62
4460 11:35:21.386150 [CA 1] Center 35 (5~66) winsize 62
4461 11:35:21.389495 [CA 2] Center 34 (4~65) winsize 62
4462 11:35:21.392907 [CA 3] Center 33 (3~64) winsize 62
4463 11:35:21.396527 [CA 4] Center 34 (4~64) winsize 61
4464 11:35:21.399761 [CA 5] Center 33 (3~64) winsize 62
4465 11:35:21.400165
4466 11:35:21.402764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4467 11:35:21.403152
4468 11:35:21.406048 [CATrainingPosCal] consider 1 rank data
4469 11:35:21.409070 u2DelayCellTimex100 = 270/100 ps
4470 11:35:21.412971 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4471 11:35:21.416032 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4472 11:35:21.419189 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4473 11:35:21.422372 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4474 11:35:21.425882 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4475 11:35:21.429134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 11:35:21.429519
4477 11:35:21.436153 CA PerBit enable=1, Macro0, CA PI delay=33
4478 11:35:21.436541
4479 11:35:21.439008 [CBTSetCACLKResult] CA Dly = 33
4480 11:35:21.439411 CS Dly: 5 (0~36)
4481 11:35:21.439753 ==
4482 11:35:21.442265 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 11:35:21.445665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:35:21.446056 ==
4485 11:35:21.452247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4486 11:35:21.459069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4487 11:35:21.462010 [CA 0] Center 35 (5~66) winsize 62
4488 11:35:21.465434 [CA 1] Center 36 (6~66) winsize 61
4489 11:35:21.469126 [CA 2] Center 34 (4~65) winsize 62
4490 11:35:21.472467 [CA 3] Center 33 (3~64) winsize 62
4491 11:35:21.475131 [CA 4] Center 34 (3~65) winsize 63
4492 11:35:21.478209 [CA 5] Center 34 (3~65) winsize 63
4493 11:35:21.478596
4494 11:35:21.481622 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4495 11:35:21.482010
4496 11:35:21.484996 [CATrainingPosCal] consider 2 rank data
4497 11:35:21.488626 u2DelayCellTimex100 = 270/100 ps
4498 11:35:21.492047 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4499 11:35:21.495162 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4500 11:35:21.498323 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4501 11:35:21.505327 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4502 11:35:21.508320 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4503 11:35:21.511382 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4504 11:35:21.511797
4505 11:35:21.514664 CA PerBit enable=1, Macro0, CA PI delay=33
4506 11:35:21.515092
4507 11:35:21.517976 [CBTSetCACLKResult] CA Dly = 33
4508 11:35:21.518362 CS Dly: 5 (0~37)
4509 11:35:21.518670
4510 11:35:21.521201 ----->DramcWriteLeveling(PI) begin...
4511 11:35:21.524803 ==
4512 11:35:21.525190 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 11:35:21.531054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 11:35:21.531523 ==
4515 11:35:21.534793 Write leveling (Byte 0): 30 => 30
4516 11:35:21.537809 Write leveling (Byte 1): 29 => 29
4517 11:35:21.540918 DramcWriteLeveling(PI) end<-----
4518 11:35:21.541359
4519 11:35:21.541662 ==
4520 11:35:21.544609 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 11:35:21.548182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 11:35:21.548569 ==
4523 11:35:21.551066 [Gating] SW mode calibration
4524 11:35:21.557447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4525 11:35:21.564048 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4526 11:35:21.567559 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4527 11:35:21.570614 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4528 11:35:21.577197 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
4529 11:35:21.580625 0 9 12 | B1->B0 | 3131 2929 | 1 0 | (0 0) (0 0)
4530 11:35:21.584370 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4531 11:35:21.590682 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 11:35:21.594061 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 11:35:21.597190 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 11:35:21.603644 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 11:35:21.607237 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 11:35:21.610797 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4537 11:35:21.616942 0 10 12 | B1->B0 | 3131 3838 | 0 1 | (0 0) (0 0)
4538 11:35:21.620064 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4539 11:35:21.623280 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 11:35:21.630119 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 11:35:21.633188 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 11:35:21.636796 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 11:35:21.643276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 11:35:21.646661 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 11:35:21.649777 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4546 11:35:21.656100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:35:21.659566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 11:35:21.663199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 11:35:21.669646 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 11:35:21.672875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 11:35:21.676125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 11:35:21.682732 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 11:35:21.685906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 11:35:21.689537 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 11:35:21.695682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 11:35:21.699040 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 11:35:21.702554 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 11:35:21.708881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 11:35:21.712406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 11:35:21.715363 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 11:35:21.722396 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4562 11:35:21.725562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4563 11:35:21.728812 Total UI for P1: 0, mck2ui 16
4564 11:35:21.732049 best dqsien dly found for B0: ( 0, 13, 12)
4565 11:35:21.735238 Total UI for P1: 0, mck2ui 16
4566 11:35:21.738712 best dqsien dly found for B1: ( 0, 13, 14)
4567 11:35:21.741991 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4568 11:35:21.745613 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4569 11:35:21.745789
4570 11:35:21.748730 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4571 11:35:21.752229 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4572 11:35:21.754975 [Gating] SW calibration Done
4573 11:35:21.755071 ==
4574 11:35:21.758302 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 11:35:21.761790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 11:35:21.761864 ==
4577 11:35:21.764981 RX Vref Scan: 0
4578 11:35:21.765054
4579 11:35:21.768272 RX Vref 0 -> 0, step: 1
4580 11:35:21.768347
4581 11:35:21.771644 RX Delay -230 -> 252, step: 16
4582 11:35:21.774901 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4583 11:35:21.777967 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4584 11:35:21.781868 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4585 11:35:21.787779 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4586 11:35:21.791361 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4587 11:35:21.794376 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4588 11:35:21.797749 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4589 11:35:21.801317 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4590 11:35:21.807711 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4591 11:35:21.810730 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4592 11:35:21.814098 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4593 11:35:21.820744 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4594 11:35:21.823951 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4595 11:35:21.827627 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4596 11:35:21.830737 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4597 11:35:21.837168 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4598 11:35:21.837309 ==
4599 11:35:21.840467 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 11:35:21.843575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 11:35:21.843704 ==
4602 11:35:21.843785 DQS Delay:
4603 11:35:21.847633 DQS0 = 0, DQS1 = 0
4604 11:35:21.847756 DQM Delay:
4605 11:35:21.850346 DQM0 = 44, DQM1 = 35
4606 11:35:21.850497 DQ Delay:
4607 11:35:21.853815 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4608 11:35:21.857227 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4609 11:35:21.860471 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4610 11:35:21.863656 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4611 11:35:21.863864
4612 11:35:21.863981
4613 11:35:21.864087 ==
4614 11:35:21.867073 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 11:35:21.870260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:35:21.870420 ==
4617 11:35:21.873692
4618 11:35:21.873945
4619 11:35:21.874099 TX Vref Scan disable
4620 11:35:21.876618 == TX Byte 0 ==
4621 11:35:21.879981 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4622 11:35:21.883680 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4623 11:35:21.886540 == TX Byte 1 ==
4624 11:35:21.889848 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4625 11:35:21.893823 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4626 11:35:21.896790 ==
4627 11:35:21.897178 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 11:35:21.903390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 11:35:21.903857 ==
4630 11:35:21.904233
4631 11:35:21.904553
4632 11:35:21.906422 TX Vref Scan disable
4633 11:35:21.906969 == TX Byte 0 ==
4634 11:35:21.913429 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4635 11:35:21.916372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4636 11:35:21.919699 == TX Byte 1 ==
4637 11:35:21.923492 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4638 11:35:21.926211 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4639 11:35:21.926285
4640 11:35:21.926343 [DATLAT]
4641 11:35:21.929027 Freq=600, CH1 RK0
4642 11:35:21.929102
4643 11:35:21.929160 DATLAT Default: 0x9
4644 11:35:21.932560 0, 0xFFFF, sum = 0
4645 11:35:21.936100 1, 0xFFFF, sum = 0
4646 11:35:21.936177 2, 0xFFFF, sum = 0
4647 11:35:21.939081 3, 0xFFFF, sum = 0
4648 11:35:21.939156 4, 0xFFFF, sum = 0
4649 11:35:21.942731 5, 0xFFFF, sum = 0
4650 11:35:21.942808 6, 0xFFFF, sum = 0
4651 11:35:21.945860 7, 0xFFFF, sum = 0
4652 11:35:21.945965 8, 0x0, sum = 1
4653 11:35:21.949020 9, 0x0, sum = 2
4654 11:35:21.949095 10, 0x0, sum = 3
4655 11:35:21.949154 11, 0x0, sum = 4
4656 11:35:21.952169 best_step = 9
4657 11:35:21.952243
4658 11:35:21.952300 ==
4659 11:35:21.955758 Dram Type= 6, Freq= 0, CH_1, rank 0
4660 11:35:21.958863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 11:35:21.958937 ==
4662 11:35:21.962286 RX Vref Scan: 1
4663 11:35:21.962374
4664 11:35:21.962485 RX Vref 0 -> 0, step: 1
4665 11:35:21.965702
4666 11:35:21.965777 RX Delay -195 -> 252, step: 8
4667 11:35:21.965836
4668 11:35:21.968706 Set Vref, RX VrefLevel [Byte0]: 47
4669 11:35:21.972509 [Byte1]: 51
4670 11:35:21.976736
4671 11:35:21.976810 Final RX Vref Byte 0 = 47 to rank0
4672 11:35:21.979807 Final RX Vref Byte 1 = 51 to rank0
4673 11:35:21.982982 Final RX Vref Byte 0 = 47 to rank1
4674 11:35:21.986399 Final RX Vref Byte 1 = 51 to rank1==
4675 11:35:21.989960 Dram Type= 6, Freq= 0, CH_1, rank 0
4676 11:35:21.996555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 11:35:21.996630 ==
4678 11:35:21.996689 DQS Delay:
4679 11:35:21.996742 DQS0 = 0, DQS1 = 0
4680 11:35:21.999668 DQM Delay:
4681 11:35:21.999779 DQM0 = 45, DQM1 = 33
4682 11:35:22.002921 DQ Delay:
4683 11:35:22.006405 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4684 11:35:22.009479 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4685 11:35:22.013450 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4686 11:35:22.016173 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4687 11:35:22.016261
4688 11:35:22.016318
4689 11:35:22.023276 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4690 11:35:22.026033 CH1 RK0: MR19=808, MR18=4B30
4691 11:35:22.033091 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4692 11:35:22.033164
4693 11:35:22.036202 ----->DramcWriteLeveling(PI) begin...
4694 11:35:22.036303 ==
4695 11:35:22.039282 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 11:35:22.042729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 11:35:22.042803 ==
4698 11:35:22.046056 Write leveling (Byte 0): 30 => 30
4699 11:35:22.049485 Write leveling (Byte 1): 33 => 33
4700 11:35:22.052372 DramcWriteLeveling(PI) end<-----
4701 11:35:22.052446
4702 11:35:22.052504 ==
4703 11:35:22.056096 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 11:35:22.058958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 11:35:22.062772 ==
4706 11:35:22.062847 [Gating] SW mode calibration
4707 11:35:22.069190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4708 11:35:22.075631 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4709 11:35:22.079209 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4710 11:35:22.086153 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4711 11:35:22.088830 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4712 11:35:22.092509 0 9 12 | B1->B0 | 3030 3131 | 1 1 | (1 0) (1 0)
4713 11:35:22.099260 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4714 11:35:22.102228 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 11:35:22.106313 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 11:35:22.112427 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 11:35:22.115852 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 11:35:22.119129 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 11:35:22.125493 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 11:35:22.128893 0 10 12 | B1->B0 | 3737 2b2b | 0 0 | (0 0) (1 1)
4721 11:35:22.132480 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 11:35:22.138340 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 11:35:22.142174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 11:35:22.145522 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 11:35:22.151649 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 11:35:22.155116 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 11:35:22.158568 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 11:35:22.165042 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4729 11:35:22.168369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4730 11:35:22.171540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 11:35:22.178164 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 11:35:22.181548 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 11:35:22.185141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 11:35:22.191363 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 11:35:22.194775 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 11:35:22.197803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 11:35:22.204553 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 11:35:22.207849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 11:35:22.211197 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 11:35:22.217989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 11:35:22.220968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 11:35:22.224507 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 11:35:22.230893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 11:35:22.234258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4745 11:35:22.237704 Total UI for P1: 0, mck2ui 16
4746 11:35:22.240949 best dqsien dly found for B1: ( 0, 13, 10)
4747 11:35:22.244419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4748 11:35:22.247886 Total UI for P1: 0, mck2ui 16
4749 11:35:22.250948 best dqsien dly found for B0: ( 0, 13, 12)
4750 11:35:22.254142 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4751 11:35:22.257649 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4752 11:35:22.261015
4753 11:35:22.264052 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4754 11:35:22.267576 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4755 11:35:22.270568 [Gating] SW calibration Done
4756 11:35:22.270989 ==
4757 11:35:22.274077 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 11:35:22.277317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 11:35:22.277970 ==
4760 11:35:22.278517 RX Vref Scan: 0
4761 11:35:22.278817
4762 11:35:22.280595 RX Vref 0 -> 0, step: 1
4763 11:35:22.281013
4764 11:35:22.284061 RX Delay -230 -> 252, step: 16
4765 11:35:22.287306 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4766 11:35:22.294149 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4767 11:35:22.297155 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4768 11:35:22.300860 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4769 11:35:22.303815 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4770 11:35:22.307043 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4771 11:35:22.313571 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4772 11:35:22.316707 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4773 11:35:22.320025 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4774 11:35:22.323463 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4775 11:35:22.330278 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4776 11:35:22.333487 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4777 11:35:22.336790 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4778 11:35:22.340336 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4779 11:35:22.346455 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4780 11:35:22.349632 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4781 11:35:22.350018 ==
4782 11:35:22.352955 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 11:35:22.356453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 11:35:22.356843 ==
4785 11:35:22.359647 DQS Delay:
4786 11:35:22.359926 DQS0 = 0, DQS1 = 0
4787 11:35:22.360160 DQM Delay:
4788 11:35:22.363280 DQM0 = 40, DQM1 = 32
4789 11:35:22.363512 DQ Delay:
4790 11:35:22.366101 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4791 11:35:22.369452 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4792 11:35:22.372366 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4793 11:35:22.376091 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =49
4794 11:35:22.376257
4795 11:35:22.376439
4796 11:35:22.376568 ==
4797 11:35:22.379575 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 11:35:22.385650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 11:35:22.385871 ==
4800 11:35:22.386007
4801 11:35:22.386126
4802 11:35:22.389232 TX Vref Scan disable
4803 11:35:22.389398 == TX Byte 0 ==
4804 11:35:22.395326 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4805 11:35:22.398735 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4806 11:35:22.398901 == TX Byte 1 ==
4807 11:35:22.405418 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4808 11:35:22.408704 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4809 11:35:22.408990 ==
4810 11:35:22.411820 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 11:35:22.415328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 11:35:22.415664 ==
4813 11:35:22.415900
4814 11:35:22.416116
4815 11:35:22.418584 TX Vref Scan disable
4816 11:35:22.421887 == TX Byte 0 ==
4817 11:35:22.425293 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4818 11:35:22.428313 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4819 11:35:22.431742 == TX Byte 1 ==
4820 11:35:22.434968 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4821 11:35:22.438548 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4822 11:35:22.442240
4823 11:35:22.442635 [DATLAT]
4824 11:35:22.442991 Freq=600, CH1 RK1
4825 11:35:22.443274
4826 11:35:22.444821 DATLAT Default: 0x9
4827 11:35:22.445200 0, 0xFFFF, sum = 0
4828 11:35:22.448117 1, 0xFFFF, sum = 0
4829 11:35:22.451828 2, 0xFFFF, sum = 0
4830 11:35:22.452207 3, 0xFFFF, sum = 0
4831 11:35:22.454969 4, 0xFFFF, sum = 0
4832 11:35:22.455353 5, 0xFFFF, sum = 0
4833 11:35:22.458258 6, 0xFFFF, sum = 0
4834 11:35:22.458658 7, 0xFFFF, sum = 0
4835 11:35:22.461437 8, 0x0, sum = 1
4836 11:35:22.461925 9, 0x0, sum = 2
4837 11:35:22.462240 10, 0x0, sum = 3
4838 11:35:22.464534 11, 0x0, sum = 4
4839 11:35:22.464918 best_step = 9
4840 11:35:22.465210
4841 11:35:22.468237 ==
4842 11:35:22.468637 Dram Type= 6, Freq= 0, CH_1, rank 1
4843 11:35:22.474770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4844 11:35:22.475257 ==
4845 11:35:22.475615 RX Vref Scan: 0
4846 11:35:22.475899
4847 11:35:22.477945 RX Vref 0 -> 0, step: 1
4848 11:35:22.478345
4849 11:35:22.481449 RX Delay -195 -> 252, step: 8
4850 11:35:22.487873 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4851 11:35:22.490886 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4852 11:35:22.494157 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4853 11:35:22.497756 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4854 11:35:22.500687 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4855 11:35:22.507362 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4856 11:35:22.510407 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4857 11:35:22.513745 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4858 11:35:22.517263 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4859 11:35:22.523836 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4860 11:35:22.526836 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4861 11:35:22.530262 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4862 11:35:22.533736 iDelay=205, Bit 12, Center 44 (-115 ~ 204) 320
4863 11:35:22.540461 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4864 11:35:22.543489 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4865 11:35:22.546629 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4866 11:35:22.547018 ==
4867 11:35:22.550433 Dram Type= 6, Freq= 0, CH_1, rank 1
4868 11:35:22.553489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4869 11:35:22.556739 ==
4870 11:35:22.557007 DQS Delay:
4871 11:35:22.557217 DQS0 = 0, DQS1 = 0
4872 11:35:22.560194 DQM Delay:
4873 11:35:22.560461 DQM0 = 43, DQM1 = 34
4874 11:35:22.563457 DQ Delay:
4875 11:35:22.566515 DQ0 =44, DQ1 =40, DQ2 =32, DQ3 =40
4876 11:35:22.566785 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4877 11:35:22.569678 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4878 11:35:22.573068 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4879 11:35:22.576662
4880 11:35:22.576927
4881 11:35:22.583396 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4882 11:35:22.586364 CH1 RK1: MR19=808, MR18=2A1F
4883 11:35:22.592728 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4884 11:35:22.596122 [RxdqsGatingPostProcess] freq 600
4885 11:35:22.599390 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4886 11:35:22.602849 Pre-setting of DQS Precalculation
4887 11:35:22.608933 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4888 11:35:22.615604 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4889 11:35:22.622031 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4890 11:35:22.622319
4891 11:35:22.622593
4892 11:35:22.625858 [Calibration Summary] 1200 Mbps
4893 11:35:22.626201 CH 0, Rank 0
4894 11:35:22.628653 SW Impedance : PASS
4895 11:35:22.631796 DUTY Scan : NO K
4896 11:35:22.632006 ZQ Calibration : PASS
4897 11:35:22.635222 Jitter Meter : NO K
4898 11:35:22.638490 CBT Training : PASS
4899 11:35:22.638632 Write leveling : PASS
4900 11:35:22.642074 RX DQS gating : PASS
4901 11:35:22.645335 RX DQ/DQS(RDDQC) : PASS
4902 11:35:22.645456 TX DQ/DQS : PASS
4903 11:35:22.648673 RX DATLAT : PASS
4904 11:35:22.651654 RX DQ/DQS(Engine): PASS
4905 11:35:22.651760 TX OE : NO K
4906 11:35:22.654916 All Pass.
4907 11:35:22.655010
4908 11:35:22.655084 CH 0, Rank 1
4909 11:35:22.658200 SW Impedance : PASS
4910 11:35:22.658277 DUTY Scan : NO K
4911 11:35:22.661200 ZQ Calibration : PASS
4912 11:35:22.664454 Jitter Meter : NO K
4913 11:35:22.664534 CBT Training : PASS
4914 11:35:22.667761 Write leveling : PASS
4915 11:35:22.672582 RX DQS gating : PASS
4916 11:35:22.672667 RX DQ/DQS(RDDQC) : PASS
4917 11:35:22.674807 TX DQ/DQS : PASS
4918 11:35:22.678014 RX DATLAT : PASS
4919 11:35:22.678089 RX DQ/DQS(Engine): PASS
4920 11:35:22.681156 TX OE : NO K
4921 11:35:22.681233 All Pass.
4922 11:35:22.681305
4923 11:35:22.684958 CH 1, Rank 0
4924 11:35:22.685035 SW Impedance : PASS
4925 11:35:22.687925 DUTY Scan : NO K
4926 11:35:22.691152 ZQ Calibration : PASS
4927 11:35:22.691226 Jitter Meter : NO K
4928 11:35:22.694527 CBT Training : PASS
4929 11:35:22.698235 Write leveling : PASS
4930 11:35:22.698310 RX DQS gating : PASS
4931 11:35:22.700921 RX DQ/DQS(RDDQC) : PASS
4932 11:35:22.700995 TX DQ/DQS : PASS
4933 11:35:22.704748 RX DATLAT : PASS
4934 11:35:22.707845 RX DQ/DQS(Engine): PASS
4935 11:35:22.708258 TX OE : NO K
4936 11:35:22.711483 All Pass.
4937 11:35:22.711919
4938 11:35:22.712227 CH 1, Rank 1
4939 11:35:22.714280 SW Impedance : PASS
4940 11:35:22.714655 DUTY Scan : NO K
4941 11:35:22.718540 ZQ Calibration : PASS
4942 11:35:22.721225 Jitter Meter : NO K
4943 11:35:22.721606 CBT Training : PASS
4944 11:35:22.724537 Write leveling : PASS
4945 11:35:22.727966 RX DQS gating : PASS
4946 11:35:22.728344 RX DQ/DQS(RDDQC) : PASS
4947 11:35:22.730921 TX DQ/DQS : PASS
4948 11:35:22.733895 RX DATLAT : PASS
4949 11:35:22.734164 RX DQ/DQS(Engine): PASS
4950 11:35:22.737333 TX OE : NO K
4951 11:35:22.737605 All Pass.
4952 11:35:22.737817
4953 11:35:22.740521 DramC Write-DBI off
4954 11:35:22.743826 PER_BANK_REFRESH: Hybrid Mode
4955 11:35:22.744030 TX_TRACKING: ON
4956 11:35:22.753837 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4957 11:35:22.757193 [FAST_K] Save calibration result to emmc
4958 11:35:22.760517 dramc_set_vcore_voltage set vcore to 662500
4959 11:35:22.763449 Read voltage for 933, 3
4960 11:35:22.763549 Vio18 = 0
4961 11:35:22.763652 Vcore = 662500
4962 11:35:22.766691 Vdram = 0
4963 11:35:22.766816 Vddq = 0
4964 11:35:22.766915 Vmddr = 0
4965 11:35:22.773147 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4966 11:35:22.776536 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4967 11:35:22.779790 MEM_TYPE=3, freq_sel=17
4968 11:35:22.783077 sv_algorithm_assistance_LP4_1600
4969 11:35:22.786562 ============ PULL DRAM RESETB DOWN ============
4970 11:35:22.793472 ========== PULL DRAM RESETB DOWN end =========
4971 11:35:22.796304 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 11:35:22.799960 ===================================
4973 11:35:22.802808 LPDDR4 DRAM CONFIGURATION
4974 11:35:22.805996 ===================================
4975 11:35:22.806072 EX_ROW_EN[0] = 0x0
4976 11:35:22.809836 EX_ROW_EN[1] = 0x0
4977 11:35:22.809912 LP4Y_EN = 0x0
4978 11:35:22.812642 WORK_FSP = 0x0
4979 11:35:22.812717 WL = 0x3
4980 11:35:22.816164 RL = 0x3
4981 11:35:22.819544 BL = 0x2
4982 11:35:22.819620 RPST = 0x0
4983 11:35:22.822541 RD_PRE = 0x0
4984 11:35:22.822617 WR_PRE = 0x1
4985 11:35:22.825820 WR_PST = 0x0
4986 11:35:22.825919 DBI_WR = 0x0
4987 11:35:22.829506 DBI_RD = 0x0
4988 11:35:22.829582 OTF = 0x1
4989 11:35:22.832508 ===================================
4990 11:35:22.836171 ===================================
4991 11:35:22.839252 ANA top config
4992 11:35:22.842777 ===================================
4993 11:35:22.842878 DLL_ASYNC_EN = 0
4994 11:35:22.845979 ALL_SLAVE_EN = 1
4995 11:35:22.849119 NEW_RANK_MODE = 1
4996 11:35:22.852126 DLL_IDLE_MODE = 1
4997 11:35:22.855847 LP45_APHY_COMB_EN = 1
4998 11:35:22.855980 TX_ODT_DIS = 1
4999 11:35:22.859411 NEW_8X_MODE = 1
5000 11:35:22.862381 ===================================
5001 11:35:22.865649 ===================================
5002 11:35:22.868957 data_rate = 1866
5003 11:35:22.872320 CKR = 1
5004 11:35:22.875605 DQ_P2S_RATIO = 8
5005 11:35:22.878918 ===================================
5006 11:35:22.882487 CA_P2S_RATIO = 8
5007 11:35:22.882889 DQ_CA_OPEN = 0
5008 11:35:22.885308 DQ_SEMI_OPEN = 0
5009 11:35:22.888843 CA_SEMI_OPEN = 0
5010 11:35:22.892515 CA_FULL_RATE = 0
5011 11:35:22.895472 DQ_CKDIV4_EN = 1
5012 11:35:22.898903 CA_CKDIV4_EN = 1
5013 11:35:22.899377 CA_PREDIV_EN = 0
5014 11:35:22.902557 PH8_DLY = 0
5015 11:35:22.905238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5016 11:35:22.909427 DQ_AAMCK_DIV = 4
5017 11:35:22.911888 CA_AAMCK_DIV = 4
5018 11:35:22.915268 CA_ADMCK_DIV = 4
5019 11:35:22.915827 DQ_TRACK_CA_EN = 0
5020 11:35:22.918535 CA_PICK = 933
5021 11:35:22.921722 CA_MCKIO = 933
5022 11:35:22.925097 MCKIO_SEMI = 0
5023 11:35:22.928725 PLL_FREQ = 3732
5024 11:35:22.931387 DQ_UI_PI_RATIO = 32
5025 11:35:22.934775 CA_UI_PI_RATIO = 0
5026 11:35:22.938232 ===================================
5027 11:35:22.941360 ===================================
5028 11:35:22.941748 memory_type:LPDDR4
5029 11:35:22.944842 GP_NUM : 10
5030 11:35:22.948643 SRAM_EN : 1
5031 11:35:22.949031 MD32_EN : 0
5032 11:35:22.951184 ===================================
5033 11:35:22.954918 [ANA_INIT] >>>>>>>>>>>>>>
5034 11:35:22.957874 <<<<<< [CONFIGURE PHASE]: ANA_TX
5035 11:35:22.961476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5036 11:35:22.964956 ===================================
5037 11:35:22.967774 data_rate = 1866,PCW = 0X8f00
5038 11:35:22.971124 ===================================
5039 11:35:22.974274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5040 11:35:22.977770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5041 11:35:22.984063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5042 11:35:22.987089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5043 11:35:22.990710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5044 11:35:22.997233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5045 11:35:22.997309 [ANA_INIT] flow start
5046 11:35:23.000807 [ANA_INIT] PLL >>>>>>>>
5047 11:35:23.004347 [ANA_INIT] PLL <<<<<<<<
5048 11:35:23.004422 [ANA_INIT] MIDPI >>>>>>>>
5049 11:35:23.007448 [ANA_INIT] MIDPI <<<<<<<<
5050 11:35:23.010364 [ANA_INIT] DLL >>>>>>>>
5051 11:35:23.010439 [ANA_INIT] flow end
5052 11:35:23.017182 ============ LP4 DIFF to SE enter ============
5053 11:35:23.020120 ============ LP4 DIFF to SE exit ============
5054 11:35:23.020197 [ANA_INIT] <<<<<<<<<<<<<
5055 11:35:23.024245 [Flow] Enable top DCM control >>>>>
5056 11:35:23.026814 [Flow] Enable top DCM control <<<<<
5057 11:35:23.030381 Enable DLL master slave shuffle
5058 11:35:23.036860 ==============================================================
5059 11:35:23.040264 Gating Mode config
5060 11:35:23.043055 ==============================================================
5061 11:35:23.046529 Config description:
5062 11:35:23.056373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5063 11:35:23.062868 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5064 11:35:23.066449 SELPH_MODE 0: By rank 1: By Phase
5065 11:35:23.072659 ==============================================================
5066 11:35:23.076164 GAT_TRACK_EN = 1
5067 11:35:23.079319 RX_GATING_MODE = 2
5068 11:35:23.082658 RX_GATING_TRACK_MODE = 2
5069 11:35:23.086110 SELPH_MODE = 1
5070 11:35:23.086186 PICG_EARLY_EN = 1
5071 11:35:23.089344 VALID_LAT_VALUE = 1
5072 11:35:23.096104 ==============================================================
5073 11:35:23.099333 Enter into Gating configuration >>>>
5074 11:35:23.102403 Exit from Gating configuration <<<<
5075 11:35:23.106230 Enter into DVFS_PRE_config >>>>>
5076 11:35:23.115869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5077 11:35:23.119111 Exit from DVFS_PRE_config <<<<<
5078 11:35:23.122632 Enter into PICG configuration >>>>
5079 11:35:23.125578 Exit from PICG configuration <<<<
5080 11:35:23.128974 [RX_INPUT] configuration >>>>>
5081 11:35:23.132763 [RX_INPUT] configuration <<<<<
5082 11:35:23.139140 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5083 11:35:23.142198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5084 11:35:23.148831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5085 11:35:23.155724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5086 11:35:23.162216 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5087 11:35:23.168623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5088 11:35:23.172209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5089 11:35:23.175440 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5090 11:35:23.179073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5091 11:35:23.185633 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5092 11:35:23.189157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5093 11:35:23.192204 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5094 11:35:23.195148 ===================================
5095 11:35:23.198410 LPDDR4 DRAM CONFIGURATION
5096 11:35:23.202325 ===================================
5097 11:35:23.205529 EX_ROW_EN[0] = 0x0
5098 11:35:23.205956 EX_ROW_EN[1] = 0x0
5099 11:35:23.208381 LP4Y_EN = 0x0
5100 11:35:23.208764 WORK_FSP = 0x0
5101 11:35:23.211560 WL = 0x3
5102 11:35:23.211944 RL = 0x3
5103 11:35:23.214948 BL = 0x2
5104 11:35:23.215330 RPST = 0x0
5105 11:35:23.218142 RD_PRE = 0x0
5106 11:35:23.218523 WR_PRE = 0x1
5107 11:35:23.221840 WR_PST = 0x0
5108 11:35:23.222222 DBI_WR = 0x0
5109 11:35:23.224742 DBI_RD = 0x0
5110 11:35:23.225138 OTF = 0x1
5111 11:35:23.228540 ===================================
5112 11:35:23.234974 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5113 11:35:23.238327 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5114 11:35:23.241762 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5115 11:35:23.244943 ===================================
5116 11:35:23.248022 LPDDR4 DRAM CONFIGURATION
5117 11:35:23.251745 ===================================
5118 11:35:23.254445 EX_ROW_EN[0] = 0x10
5119 11:35:23.254830 EX_ROW_EN[1] = 0x0
5120 11:35:23.257926 LP4Y_EN = 0x0
5121 11:35:23.258308 WORK_FSP = 0x0
5122 11:35:23.261204 WL = 0x3
5123 11:35:23.261599 RL = 0x3
5124 11:35:23.264554 BL = 0x2
5125 11:35:23.264938 RPST = 0x0
5126 11:35:23.267867 RD_PRE = 0x0
5127 11:35:23.268360 WR_PRE = 0x1
5128 11:35:23.271212 WR_PST = 0x0
5129 11:35:23.271678 DBI_WR = 0x0
5130 11:35:23.274711 DBI_RD = 0x0
5131 11:35:23.275099 OTF = 0x1
5132 11:35:23.277595 ===================================
5133 11:35:23.284276 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5134 11:35:23.288808 nWR fixed to 30
5135 11:35:23.292685 [ModeRegInit_LP4] CH0 RK0
5136 11:35:23.293072 [ModeRegInit_LP4] CH0 RK1
5137 11:35:23.295844 [ModeRegInit_LP4] CH1 RK0
5138 11:35:23.299220 [ModeRegInit_LP4] CH1 RK1
5139 11:35:23.299695 match AC timing 9
5140 11:35:23.305593 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5141 11:35:23.309227 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5142 11:35:23.312316 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5143 11:35:23.319171 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5144 11:35:23.321655 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5145 11:35:23.322041 ==
5146 11:35:23.325168 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 11:35:23.328532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 11:35:23.328930 ==
5149 11:35:23.335137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5150 11:35:23.342009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5151 11:35:23.345111 [CA 0] Center 37 (7~68) winsize 62
5152 11:35:23.348543 [CA 1] Center 37 (7~68) winsize 62
5153 11:35:23.351507 [CA 2] Center 34 (4~65) winsize 62
5154 11:35:23.355075 [CA 3] Center 34 (4~65) winsize 62
5155 11:35:23.358378 [CA 4] Center 34 (4~64) winsize 61
5156 11:35:23.361838 [CA 5] Center 33 (4~63) winsize 60
5157 11:35:23.362233
5158 11:35:23.365269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5159 11:35:23.365831
5160 11:35:23.368416 [CATrainingPosCal] consider 1 rank data
5161 11:35:23.371932 u2DelayCellTimex100 = 270/100 ps
5162 11:35:23.374638 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5163 11:35:23.377948 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5164 11:35:23.381457 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5165 11:35:23.387877 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5166 11:35:23.390936 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5167 11:35:23.394285 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5168 11:35:23.394670
5169 11:35:23.397904 CA PerBit enable=1, Macro0, CA PI delay=33
5170 11:35:23.398285
5171 11:35:23.401009 [CBTSetCACLKResult] CA Dly = 33
5172 11:35:23.401390 CS Dly: 7 (0~38)
5173 11:35:23.401683 ==
5174 11:35:23.404298 Dram Type= 6, Freq= 0, CH_0, rank 1
5175 11:35:23.411011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 11:35:23.411498 ==
5177 11:35:23.414682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5178 11:35:23.420970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5179 11:35:23.424140 [CA 0] Center 37 (7~68) winsize 62
5180 11:35:23.427238 [CA 1] Center 37 (7~68) winsize 62
5181 11:35:23.430688 [CA 2] Center 34 (4~65) winsize 62
5182 11:35:23.433916 [CA 3] Center 35 (5~65) winsize 61
5183 11:35:23.437243 [CA 4] Center 33 (3~64) winsize 62
5184 11:35:23.441005 [CA 5] Center 32 (2~63) winsize 62
5185 11:35:23.441462
5186 11:35:23.444092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5187 11:35:23.444478
5188 11:35:23.447256 [CATrainingPosCal] consider 2 rank data
5189 11:35:23.450498 u2DelayCellTimex100 = 270/100 ps
5190 11:35:23.453656 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5191 11:35:23.460340 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5192 11:35:23.463320 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5193 11:35:23.466800 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5194 11:35:23.469893 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5195 11:35:23.473467 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5196 11:35:23.473857
5197 11:35:23.476795 CA PerBit enable=1, Macro0, CA PI delay=33
5198 11:35:23.477180
5199 11:35:23.479975 [CBTSetCACLKResult] CA Dly = 33
5200 11:35:23.483701 CS Dly: 7 (0~39)
5201 11:35:23.484158
5202 11:35:23.487019 ----->DramcWriteLeveling(PI) begin...
5203 11:35:23.487410 ==
5204 11:35:23.489833 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 11:35:23.493302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 11:35:23.493690 ==
5207 11:35:23.497113 Write leveling (Byte 0): 35 => 35
5208 11:35:23.500307 Write leveling (Byte 1): 29 => 29
5209 11:35:23.503667 DramcWriteLeveling(PI) end<-----
5210 11:35:23.504052
5211 11:35:23.504356 ==
5212 11:35:23.506362 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:35:23.509859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:35:23.510310 ==
5215 11:35:23.513922 [Gating] SW mode calibration
5216 11:35:23.520123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5217 11:35:23.526300 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5218 11:35:23.529770 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5219 11:35:23.533071 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5220 11:35:23.539781 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 11:35:23.543183 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 11:35:23.546321 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 11:35:23.552621 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 11:35:23.555724 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 11:35:23.559258 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5226 11:35:23.566504 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5227 11:35:23.569084 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 11:35:23.572509 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 11:35:23.579168 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 11:35:23.582486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5231 11:35:23.585853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 11:35:23.592378 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 11:35:23.595732 0 15 28 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5234 11:35:23.598887 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5235 11:35:23.605640 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 11:35:23.608967 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 11:35:23.612271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 11:35:23.618730 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 11:35:23.621893 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 11:35:23.625561 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 11:35:23.631790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 11:35:23.635374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5243 11:35:23.638610 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 11:35:23.644785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 11:35:23.648117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 11:35:23.651794 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 11:35:23.658022 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 11:35:23.661746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 11:35:23.664945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 11:35:23.671286 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 11:35:23.675305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 11:35:23.677925 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 11:35:23.684513 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 11:35:23.687841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 11:35:23.690903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 11:35:23.697758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 11:35:23.701369 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 11:35:23.704200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5259 11:35:23.707689 Total UI for P1: 0, mck2ui 16
5260 11:35:23.710957 best dqsien dly found for B0: ( 1, 2, 30)
5261 11:35:23.717654 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5262 11:35:23.720898 Total UI for P1: 0, mck2ui 16
5263 11:35:23.724287 best dqsien dly found for B1: ( 1, 3, 0)
5264 11:35:23.727236 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5265 11:35:23.730922 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5266 11:35:23.731629
5267 11:35:23.733955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5268 11:35:23.737664 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5269 11:35:23.740748 [Gating] SW calibration Done
5270 11:35:23.741245 ==
5271 11:35:23.744207 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 11:35:23.747355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 11:35:23.747859 ==
5274 11:35:23.750325 RX Vref Scan: 0
5275 11:35:23.750705
5276 11:35:23.751004 RX Vref 0 -> 0, step: 1
5277 11:35:23.753879
5278 11:35:23.754429 RX Delay -80 -> 252, step: 8
5279 11:35:23.760937 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5280 11:35:23.763817 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5281 11:35:23.767113 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5282 11:35:23.770557 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5283 11:35:23.773593 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5284 11:35:23.776827 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5285 11:35:23.783623 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5286 11:35:23.786885 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5287 11:35:23.790452 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5288 11:35:23.793476 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5289 11:35:23.796926 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5290 11:35:23.803291 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5291 11:35:23.806692 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5292 11:35:23.810026 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5293 11:35:23.813210 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5294 11:35:23.816405 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5295 11:35:23.816851 ==
5296 11:35:23.819969 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:35:23.826343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:35:23.826732 ==
5299 11:35:23.827031 DQS Delay:
5300 11:35:23.829752 DQS0 = 0, DQS1 = 0
5301 11:35:23.830132 DQM Delay:
5302 11:35:23.833486 DQM0 = 96, DQM1 = 85
5303 11:35:23.833865 DQ Delay:
5304 11:35:23.836335 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5305 11:35:23.839548 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5306 11:35:23.843146 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5307 11:35:23.845994 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5308 11:35:23.846475
5309 11:35:23.846902
5310 11:35:23.847189 ==
5311 11:35:23.849541 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 11:35:23.852806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 11:35:23.853189 ==
5314 11:35:23.853488
5315 11:35:23.853758
5316 11:35:23.856107 TX Vref Scan disable
5317 11:35:23.859344 == TX Byte 0 ==
5318 11:35:23.862627 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5319 11:35:23.865785 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5320 11:35:23.868877 == TX Byte 1 ==
5321 11:35:23.872182 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5322 11:35:23.875628 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5323 11:35:23.876065 ==
5324 11:35:23.879547 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 11:35:23.885563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:35:23.885971 ==
5327 11:35:23.886270
5328 11:35:23.886540
5329 11:35:23.886798 TX Vref Scan disable
5330 11:35:23.890131 == TX Byte 0 ==
5331 11:35:23.893059 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5332 11:35:23.899815 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5333 11:35:23.900258 == TX Byte 1 ==
5334 11:35:23.902894 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5335 11:35:23.909575 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5336 11:35:23.909959
5337 11:35:23.910255 [DATLAT]
5338 11:35:23.910529 Freq=933, CH0 RK0
5339 11:35:23.910793
5340 11:35:23.913159 DATLAT Default: 0xd
5341 11:35:23.916158 0, 0xFFFF, sum = 0
5342 11:35:23.916692 1, 0xFFFF, sum = 0
5343 11:35:23.919492 2, 0xFFFF, sum = 0
5344 11:35:23.920005 3, 0xFFFF, sum = 0
5345 11:35:23.922586 4, 0xFFFF, sum = 0
5346 11:35:23.922997 5, 0xFFFF, sum = 0
5347 11:35:23.926051 6, 0xFFFF, sum = 0
5348 11:35:23.926441 7, 0xFFFF, sum = 0
5349 11:35:23.929043 8, 0xFFFF, sum = 0
5350 11:35:23.929443 9, 0xFFFF, sum = 0
5351 11:35:23.932526 10, 0x0, sum = 1
5352 11:35:23.932906 11, 0x0, sum = 2
5353 11:35:23.935933 12, 0x0, sum = 3
5354 11:35:23.936315 13, 0x0, sum = 4
5355 11:35:23.939303 best_step = 11
5356 11:35:23.939728
5357 11:35:23.940026 ==
5358 11:35:23.942663 Dram Type= 6, Freq= 0, CH_0, rank 0
5359 11:35:23.946003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 11:35:23.946456 ==
5361 11:35:23.946754 RX Vref Scan: 1
5362 11:35:23.949398
5363 11:35:23.949852 RX Vref 0 -> 0, step: 1
5364 11:35:23.950155
5365 11:35:23.952463 RX Delay -61 -> 252, step: 4
5366 11:35:23.953009
5367 11:35:23.955360 Set Vref, RX VrefLevel [Byte0]: 66
5368 11:35:23.959011 [Byte1]: 58
5369 11:35:23.962283
5370 11:35:23.965845 Final RX Vref Byte 0 = 66 to rank0
5371 11:35:23.966226 Final RX Vref Byte 1 = 58 to rank0
5372 11:35:23.968964 Final RX Vref Byte 0 = 66 to rank1
5373 11:35:23.971931 Final RX Vref Byte 1 = 58 to rank1==
5374 11:35:23.975490 Dram Type= 6, Freq= 0, CH_0, rank 0
5375 11:35:23.982120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:35:23.982501 ==
5377 11:35:23.982795 DQS Delay:
5378 11:35:23.985555 DQS0 = 0, DQS1 = 0
5379 11:35:23.985961 DQM Delay:
5380 11:35:23.986258 DQM0 = 97, DQM1 = 85
5381 11:35:23.988666 DQ Delay:
5382 11:35:23.992192 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5383 11:35:23.995159 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5384 11:35:23.998588 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =82
5385 11:35:24.002240 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5386 11:35:24.002602
5387 11:35:24.002902
5388 11:35:24.008428 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5389 11:35:24.011643 CH0 RK0: MR19=505, MR18=2A10
5390 11:35:24.018222 CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43
5391 11:35:24.018681
5392 11:35:24.021776 ----->DramcWriteLeveling(PI) begin...
5393 11:35:24.022257 ==
5394 11:35:24.025046 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 11:35:24.028224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 11:35:24.028736 ==
5397 11:35:24.031335 Write leveling (Byte 0): 31 => 31
5398 11:35:24.034496 Write leveling (Byte 1): 30 => 30
5399 11:35:24.038121 DramcWriteLeveling(PI) end<-----
5400 11:35:24.038494
5401 11:35:24.038783 ==
5402 11:35:24.041319 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:35:24.047857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:35:24.048238 ==
5405 11:35:24.048534 [Gating] SW mode calibration
5406 11:35:24.057739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 11:35:24.061190 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5408 11:35:24.067752 0 14 0 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (0 0)
5409 11:35:24.071047 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 11:35:24.074128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 11:35:24.080896 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 11:35:24.083949 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 11:35:24.087711 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 11:35:24.094138 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 11:35:24.097376 0 14 28 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
5416 11:35:24.100567 0 15 0 | B1->B0 | 3030 2727 | 0 0 | (1 1) (0 0)
5417 11:35:24.107206 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 11:35:24.110470 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 11:35:24.113919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 11:35:24.120431 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 11:35:24.123722 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 11:35:24.126941 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 11:35:24.133709 0 15 28 | B1->B0 | 2625 3838 | 1 0 | (0 0) (1 1)
5424 11:35:24.136991 1 0 0 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5425 11:35:24.140354 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 11:35:24.147070 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 11:35:24.150649 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 11:35:24.153418 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 11:35:24.157130 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 11:35:24.163151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 11:35:24.167006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5432 11:35:24.169772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5433 11:35:24.176560 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:35:24.180250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 11:35:24.183081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 11:35:24.189836 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 11:35:24.193111 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 11:35:24.196194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 11:35:24.203042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 11:35:24.206432 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 11:35:24.209406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 11:35:24.216170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 11:35:24.219251 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 11:35:24.222643 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 11:35:24.229318 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 11:35:24.232539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 11:35:24.235923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5448 11:35:24.242627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 11:35:24.246050 Total UI for P1: 0, mck2ui 16
5450 11:35:24.249613 best dqsien dly found for B0: ( 1, 2, 28)
5451 11:35:24.253173 Total UI for P1: 0, mck2ui 16
5452 11:35:24.256292 best dqsien dly found for B1: ( 1, 2, 30)
5453 11:35:24.259176 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5454 11:35:24.262432 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5455 11:35:24.262881
5456 11:35:24.265509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5457 11:35:24.268799 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5458 11:35:24.272274 [Gating] SW calibration Done
5459 11:35:24.272676 ==
5460 11:35:24.275516 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:35:24.278817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:35:24.279200 ==
5463 11:35:24.282070 RX Vref Scan: 0
5464 11:35:24.282575
5465 11:35:24.285484 RX Vref 0 -> 0, step: 1
5466 11:35:24.285865
5467 11:35:24.286161 RX Delay -80 -> 252, step: 8
5468 11:35:24.292283 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5469 11:35:24.295038 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5470 11:35:24.298378 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5471 11:35:24.301888 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5472 11:35:24.305121 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5473 11:35:24.308376 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5474 11:35:24.315194 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5475 11:35:24.318074 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5476 11:35:24.321937 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5477 11:35:24.325337 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5478 11:35:24.328567 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5479 11:35:24.334584 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5480 11:35:24.338525 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5481 11:35:24.341520 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5482 11:35:24.344739 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5483 11:35:24.348158 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5484 11:35:24.348544 ==
5485 11:35:24.351140 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 11:35:24.358140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:35:24.358626 ==
5488 11:35:24.358960 DQS Delay:
5489 11:35:24.361649 DQS0 = 0, DQS1 = 0
5490 11:35:24.362257 DQM Delay:
5491 11:35:24.364391 DQM0 = 97, DQM1 = 90
5492 11:35:24.364810 DQ Delay:
5493 11:35:24.367490 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5494 11:35:24.370852 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5495 11:35:24.374258 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5496 11:35:24.377635 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5497 11:35:24.378015
5498 11:35:24.378309
5499 11:35:24.378616 ==
5500 11:35:24.380577 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 11:35:24.383688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 11:35:24.384073 ==
5503 11:35:24.384373
5504 11:35:24.387451
5505 11:35:24.387827 TX Vref Scan disable
5506 11:35:24.390367 == TX Byte 0 ==
5507 11:35:24.393876 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5508 11:35:24.397180 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5509 11:35:24.400532 == TX Byte 1 ==
5510 11:35:24.404044 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5511 11:35:24.407216 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5512 11:35:24.407640 ==
5513 11:35:24.410266 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 11:35:24.417303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:35:24.417826 ==
5516 11:35:24.418306
5517 11:35:24.418685
5518 11:35:24.419093 TX Vref Scan disable
5519 11:35:24.421058 == TX Byte 0 ==
5520 11:35:24.424774 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5521 11:35:24.431330 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5522 11:35:24.431765 == TX Byte 1 ==
5523 11:35:24.434427 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5524 11:35:24.440824 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5525 11:35:24.441205
5526 11:35:24.441500 [DATLAT]
5527 11:35:24.441772 Freq=933, CH0 RK1
5528 11:35:24.442033
5529 11:35:24.444136 DATLAT Default: 0xb
5530 11:35:24.447694 0, 0xFFFF, sum = 0
5531 11:35:24.448084 1, 0xFFFF, sum = 0
5532 11:35:24.450488 2, 0xFFFF, sum = 0
5533 11:35:24.450874 3, 0xFFFF, sum = 0
5534 11:35:24.453996 4, 0xFFFF, sum = 0
5535 11:35:24.454383 5, 0xFFFF, sum = 0
5536 11:35:24.457465 6, 0xFFFF, sum = 0
5537 11:35:24.457849 7, 0xFFFF, sum = 0
5538 11:35:24.460505 8, 0xFFFF, sum = 0
5539 11:35:24.460893 9, 0xFFFF, sum = 0
5540 11:35:24.463538 10, 0x0, sum = 1
5541 11:35:24.464238 11, 0x0, sum = 2
5542 11:35:24.467258 12, 0x0, sum = 3
5543 11:35:24.467729 13, 0x0, sum = 4
5544 11:35:24.470551 best_step = 11
5545 11:35:24.471103
5546 11:35:24.471615 ==
5547 11:35:24.473620 Dram Type= 6, Freq= 0, CH_0, rank 1
5548 11:35:24.477150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 11:35:24.477561 ==
5550 11:35:24.477949 RX Vref Scan: 0
5551 11:35:24.480561
5552 11:35:24.480951 RX Vref 0 -> 0, step: 1
5553 11:35:24.481372
5554 11:35:24.483575 RX Delay -61 -> 252, step: 4
5555 11:35:24.490312 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5556 11:35:24.493784 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5557 11:35:24.496708 iDelay=199, Bit 2, Center 90 (-5 ~ 186) 192
5558 11:35:24.500270 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5559 11:35:24.503390 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5560 11:35:24.510086 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5561 11:35:24.513374 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5562 11:35:24.516662 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5563 11:35:24.519805 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5564 11:35:24.523099 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5565 11:35:24.529562 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5566 11:35:24.533020 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5567 11:35:24.536392 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5568 11:35:24.539392 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5569 11:35:24.543298 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5570 11:35:24.550179 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5571 11:35:24.550648 ==
5572 11:35:24.553338 Dram Type= 6, Freq= 0, CH_0, rank 1
5573 11:35:24.556457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 11:35:24.557007 ==
5575 11:35:24.557502 DQS Delay:
5576 11:35:24.559400 DQS0 = 0, DQS1 = 0
5577 11:35:24.559962 DQM Delay:
5578 11:35:24.562458 DQM0 = 94, DQM1 = 88
5579 11:35:24.562839 DQ Delay:
5580 11:35:24.566075 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =90
5581 11:35:24.569229 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5582 11:35:24.572609 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5583 11:35:24.575822 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5584 11:35:24.576202
5585 11:35:24.576494
5586 11:35:24.585519 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5587 11:35:24.586233 CH0 RK1: MR19=504, MR18=25F6
5588 11:35:24.592679 CH0_RK1: MR19=0x504, MR18=0x25F6, DQSOSC=410, MR23=63, INC=64, DEC=42
5589 11:35:24.595831 [RxdqsGatingPostProcess] freq 933
5590 11:35:24.602095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5591 11:35:24.605681 best DQS0 dly(2T, 0.5T) = (0, 10)
5592 11:35:24.609153 best DQS1 dly(2T, 0.5T) = (0, 11)
5593 11:35:24.612350 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5594 11:35:24.615190 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5595 11:35:24.615615 best DQS0 dly(2T, 0.5T) = (0, 10)
5596 11:35:24.618928 best DQS1 dly(2T, 0.5T) = (0, 10)
5597 11:35:24.622263 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5598 11:35:24.625306 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5599 11:35:24.628950 Pre-setting of DQS Precalculation
5600 11:35:24.635865 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5601 11:35:24.636438 ==
5602 11:35:24.638897 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 11:35:24.642430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 11:35:24.642812 ==
5605 11:35:24.648617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5606 11:35:24.655475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5607 11:35:24.658690 [CA 0] Center 37 (7~67) winsize 61
5608 11:35:24.662311 [CA 1] Center 37 (7~68) winsize 62
5609 11:35:24.664980 [CA 2] Center 34 (4~65) winsize 62
5610 11:35:24.668101 [CA 3] Center 33 (3~64) winsize 62
5611 11:35:24.671665 [CA 4] Center 34 (4~65) winsize 62
5612 11:35:24.674552 [CA 5] Center 33 (3~64) winsize 62
5613 11:35:24.675032
5614 11:35:24.678259 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5615 11:35:24.678641
5616 11:35:24.681903 [CATrainingPosCal] consider 1 rank data
5617 11:35:24.685000 u2DelayCellTimex100 = 270/100 ps
5618 11:35:24.687944 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5619 11:35:24.691498 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5620 11:35:24.694828 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5621 11:35:24.697726 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 11:35:24.701360 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5623 11:35:24.704882 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5624 11:35:24.705342
5625 11:35:24.711317 CA PerBit enable=1, Macro0, CA PI delay=33
5626 11:35:24.711738
5627 11:35:24.712039 [CBTSetCACLKResult] CA Dly = 33
5628 11:35:24.714817 CS Dly: 6 (0~37)
5629 11:35:24.715314 ==
5630 11:35:24.718064 Dram Type= 6, Freq= 0, CH_1, rank 1
5631 11:35:24.721317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 11:35:24.721780 ==
5633 11:35:24.727779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5634 11:35:24.734711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5635 11:35:24.737833 [CA 0] Center 37 (7~67) winsize 61
5636 11:35:24.740807 [CA 1] Center 37 (7~68) winsize 62
5637 11:35:24.743984 [CA 2] Center 34 (4~65) winsize 62
5638 11:35:24.747178 [CA 3] Center 34 (4~65) winsize 62
5639 11:35:24.750664 [CA 4] Center 34 (4~65) winsize 62
5640 11:35:24.753903 [CA 5] Center 33 (3~64) winsize 62
5641 11:35:24.754280
5642 11:35:24.757450 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5643 11:35:24.757845
5644 11:35:24.760634 [CATrainingPosCal] consider 2 rank data
5645 11:35:24.764399 u2DelayCellTimex100 = 270/100 ps
5646 11:35:24.767062 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5647 11:35:24.770502 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5648 11:35:24.773594 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5649 11:35:24.777071 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5650 11:35:24.783898 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5651 11:35:24.786938 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5652 11:35:24.787525
5653 11:35:24.790288 CA PerBit enable=1, Macro0, CA PI delay=33
5654 11:35:24.790667
5655 11:35:24.793800 [CBTSetCACLKResult] CA Dly = 33
5656 11:35:24.794182 CS Dly: 7 (0~39)
5657 11:35:24.794478
5658 11:35:24.797032 ----->DramcWriteLeveling(PI) begin...
5659 11:35:24.797416 ==
5660 11:35:24.800206 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 11:35:24.807316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 11:35:24.807829 ==
5663 11:35:24.810244 Write leveling (Byte 0): 24 => 24
5664 11:35:24.813268 Write leveling (Byte 1): 29 => 29
5665 11:35:24.813648 DramcWriteLeveling(PI) end<-----
5666 11:35:24.813944
5667 11:35:24.816914 ==
5668 11:35:24.819894 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 11:35:24.823680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 11:35:24.824058 ==
5671 11:35:24.826591 [Gating] SW mode calibration
5672 11:35:24.833203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5673 11:35:24.836252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5674 11:35:24.843077 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 11:35:24.846501 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 11:35:24.849553 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 11:35:24.856359 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 11:35:24.859484 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5679 11:35:24.863401 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5680 11:35:24.869566 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5681 11:35:24.872758 0 14 28 | B1->B0 | 3030 2b2b | 0 1 | (0 1) (1 0)
5682 11:35:24.876015 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 11:35:24.882677 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 11:35:24.886127 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 11:35:24.889284 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 11:35:24.895712 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 11:35:24.899200 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 11:35:24.902518 0 15 24 | B1->B0 | 2524 2626 | 1 0 | (0 0) (0 0)
5689 11:35:24.908940 0 15 28 | B1->B0 | 3535 3838 | 0 0 | (1 1) (1 1)
5690 11:35:24.912589 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 11:35:24.915780 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 11:35:24.922151 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 11:35:24.925932 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 11:35:24.928959 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 11:35:24.935488 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 11:35:24.938739 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5697 11:35:24.942244 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:35:24.948490 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:35:24.951702 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 11:35:24.954744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 11:35:24.961618 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 11:35:24.964960 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 11:35:24.968227 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 11:35:24.975135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 11:35:24.978417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 11:35:24.981469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 11:35:24.988220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 11:35:24.991348 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 11:35:24.995172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 11:35:25.002165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 11:35:25.004616 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 11:35:25.007674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 11:35:25.014656 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5714 11:35:25.017631 Total UI for P1: 0, mck2ui 16
5715 11:35:25.021275 best dqsien dly found for B0: ( 1, 2, 26)
5716 11:35:25.024406 Total UI for P1: 0, mck2ui 16
5717 11:35:25.027820 best dqsien dly found for B1: ( 1, 2, 26)
5718 11:35:25.031367 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5719 11:35:25.034447 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5720 11:35:25.035006
5721 11:35:25.037979 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5722 11:35:25.041266 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5723 11:35:25.044146 [Gating] SW calibration Done
5724 11:35:25.044227 ==
5725 11:35:25.047268 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 11:35:25.051102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 11:35:25.051185 ==
5728 11:35:25.053813 RX Vref Scan: 0
5729 11:35:25.053879
5730 11:35:25.053936 RX Vref 0 -> 0, step: 1
5731 11:35:25.056947
5732 11:35:25.057019 RX Delay -80 -> 252, step: 8
5733 11:35:25.064461 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5734 11:35:25.067171 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5735 11:35:25.070686 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5736 11:35:25.073988 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5737 11:35:25.077027 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5738 11:35:25.080398 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5739 11:35:25.086961 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5740 11:35:25.090350 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5741 11:35:25.093644 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5742 11:35:25.096751 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5743 11:35:25.099869 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5744 11:35:25.107196 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5745 11:35:25.110168 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5746 11:35:25.113537 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5747 11:35:25.116332 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5748 11:35:25.119916 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5749 11:35:25.119991 ==
5750 11:35:25.122866 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 11:35:25.129532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 11:35:25.129611 ==
5753 11:35:25.129667 DQS Delay:
5754 11:35:25.132818 DQS0 = 0, DQS1 = 0
5755 11:35:25.132888 DQM Delay:
5756 11:35:25.132942 DQM0 = 102, DQM1 = 92
5757 11:35:25.135946 DQ Delay:
5758 11:35:25.139407 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5759 11:35:25.142629 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5760 11:35:25.146239 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5761 11:35:25.148994 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5762 11:35:25.149068
5763 11:35:25.149125
5764 11:35:25.149179 ==
5765 11:35:25.152535 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 11:35:25.156167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 11:35:25.156241 ==
5768 11:35:25.156298
5769 11:35:25.156351
5770 11:35:25.159331 TX Vref Scan disable
5771 11:35:25.162511 == TX Byte 0 ==
5772 11:35:25.165983 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5773 11:35:25.169394 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5774 11:35:25.172850 == TX Byte 1 ==
5775 11:35:25.175757 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5776 11:35:25.178761 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5777 11:35:25.178836 ==
5778 11:35:25.182330 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 11:35:25.188987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 11:35:25.189061 ==
5781 11:35:25.189119
5782 11:35:25.189172
5783 11:35:25.189222 TX Vref Scan disable
5784 11:35:25.193269 == TX Byte 0 ==
5785 11:35:25.196340 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5786 11:35:25.202683 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5787 11:35:25.202758 == TX Byte 1 ==
5788 11:35:25.206341 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5789 11:35:25.212440 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5790 11:35:25.212513
5791 11:35:25.212571 [DATLAT]
5792 11:35:25.212634 Freq=933, CH1 RK0
5793 11:35:25.212686
5794 11:35:25.215737 DATLAT Default: 0xd
5795 11:35:25.219222 0, 0xFFFF, sum = 0
5796 11:35:25.219298 1, 0xFFFF, sum = 0
5797 11:35:25.222667 2, 0xFFFF, sum = 0
5798 11:35:25.222742 3, 0xFFFF, sum = 0
5799 11:35:25.225817 4, 0xFFFF, sum = 0
5800 11:35:25.225892 5, 0xFFFF, sum = 0
5801 11:35:25.229425 6, 0xFFFF, sum = 0
5802 11:35:25.229500 7, 0xFFFF, sum = 0
5803 11:35:25.232424 8, 0xFFFF, sum = 0
5804 11:35:25.232499 9, 0xFFFF, sum = 0
5805 11:35:25.235582 10, 0x0, sum = 1
5806 11:35:25.235657 11, 0x0, sum = 2
5807 11:35:25.238847 12, 0x0, sum = 3
5808 11:35:25.238921 13, 0x0, sum = 4
5809 11:35:25.242097 best_step = 11
5810 11:35:25.242170
5811 11:35:25.242227 ==
5812 11:35:25.245529 Dram Type= 6, Freq= 0, CH_1, rank 0
5813 11:35:25.248948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 11:35:25.249023 ==
5815 11:35:25.251917 RX Vref Scan: 1
5816 11:35:25.251991
5817 11:35:25.252048 RX Vref 0 -> 0, step: 1
5818 11:35:25.252101
5819 11:35:25.255294 RX Delay -61 -> 252, step: 4
5820 11:35:25.255392
5821 11:35:25.258748 Set Vref, RX VrefLevel [Byte0]: 47
5822 11:35:25.262283 [Byte1]: 51
5823 11:35:25.265987
5824 11:35:25.266062 Final RX Vref Byte 0 = 47 to rank0
5825 11:35:25.268727 Final RX Vref Byte 1 = 51 to rank0
5826 11:35:25.272368 Final RX Vref Byte 0 = 47 to rank1
5827 11:35:25.275288 Final RX Vref Byte 1 = 51 to rank1==
5828 11:35:25.278509 Dram Type= 6, Freq= 0, CH_1, rank 0
5829 11:35:25.285097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 11:35:25.285173 ==
5831 11:35:25.285232 DQS Delay:
5832 11:35:25.288560 DQS0 = 0, DQS1 = 0
5833 11:35:25.288629 DQM Delay:
5834 11:35:25.288683 DQM0 = 101, DQM1 = 93
5835 11:35:25.291588 DQ Delay:
5836 11:35:25.294861 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5837 11:35:25.298322 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5838 11:35:25.301804 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =84
5839 11:35:25.305217 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =104
5840 11:35:25.305305
5841 11:35:25.305393
5842 11:35:25.311759 [DQSOSCAuto] RK0, (LSB)MR18= 0x1808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5843 11:35:25.314752 CH1 RK0: MR19=505, MR18=1808
5844 11:35:25.320870 CH1_RK0: MR19=0x505, MR18=0x1808, DQSOSC=414, MR23=63, INC=63, DEC=42
5845 11:35:25.320938
5846 11:35:25.324377 ----->DramcWriteLeveling(PI) begin...
5847 11:35:25.324466 ==
5848 11:35:25.327649 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 11:35:25.334145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 11:35:25.334210 ==
5851 11:35:25.337744 Write leveling (Byte 0): 25 => 25
5852 11:35:25.337813 Write leveling (Byte 1): 27 => 27
5853 11:35:25.340945 DramcWriteLeveling(PI) end<-----
5854 11:35:25.341007
5855 11:35:25.341072 ==
5856 11:35:25.344148 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 11:35:25.351053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 11:35:25.351119 ==
5859 11:35:25.354234 [Gating] SW mode calibration
5860 11:35:25.360490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5861 11:35:25.364214 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5862 11:35:25.370652 0 14 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
5863 11:35:25.373944 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 11:35:25.377154 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 11:35:25.383980 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 11:35:25.387399 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 11:35:25.390398 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 11:35:25.396852 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
5869 11:35:25.400526 0 14 28 | B1->B0 | 2a2a 3030 | 0 0 | (1 0) (0 1)
5870 11:35:25.403410 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5871 11:35:25.409956 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 11:35:25.413956 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 11:35:25.416849 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 11:35:25.423353 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 11:35:25.426430 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 11:35:25.430075 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5877 11:35:25.436454 0 15 28 | B1->B0 | 4141 3636 | 0 0 | (0 0) (1 1)
5878 11:35:25.439830 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 11:35:25.442902 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 11:35:25.449487 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 11:35:25.452630 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 11:35:25.456236 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 11:35:25.463128 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 11:35:25.465841 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 11:35:25.469187 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5886 11:35:25.476450 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:35:25.479207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:35:25.482241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 11:35:25.489070 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 11:35:25.492223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 11:35:25.495784 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 11:35:25.502187 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 11:35:25.505767 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 11:35:25.508985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 11:35:25.515402 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 11:35:25.518917 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 11:35:25.521947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 11:35:25.528781 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 11:35:25.531931 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 11:35:25.535175 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 11:35:25.541808 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5902 11:35:25.545093 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5903 11:35:25.548229 Total UI for P1: 0, mck2ui 16
5904 11:35:25.551944 best dqsien dly found for B1: ( 1, 2, 28)
5905 11:35:25.554889 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5906 11:35:25.558242 Total UI for P1: 0, mck2ui 16
5907 11:35:25.561641 best dqsien dly found for B0: ( 1, 2, 30)
5908 11:35:25.565043 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5909 11:35:25.571214 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5910 11:35:25.571279
5911 11:35:25.575005 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5912 11:35:25.578109 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5913 11:35:25.581624 [Gating] SW calibration Done
5914 11:35:25.581694 ==
5915 11:35:25.584680 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:35:25.588027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:35:25.588093 ==
5918 11:35:25.591128 RX Vref Scan: 0
5919 11:35:25.591189
5920 11:35:25.591241 RX Vref 0 -> 0, step: 1
5921 11:35:25.591300
5922 11:35:25.594336 RX Delay -80 -> 252, step: 8
5923 11:35:25.597802 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5924 11:35:25.601062 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5925 11:35:25.607712 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5926 11:35:25.611021 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5927 11:35:25.614036 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5928 11:35:25.617460 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5929 11:35:25.620936 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5930 11:35:25.624134 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5931 11:35:25.630640 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5932 11:35:25.634238 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5933 11:35:25.637275 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5934 11:35:25.640902 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5935 11:35:25.644044 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5936 11:35:25.650458 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5937 11:35:25.654141 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5938 11:35:25.656984 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5939 11:35:25.657058 ==
5940 11:35:25.660738 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:35:25.663622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:35:25.663724 ==
5943 11:35:25.666963 DQS Delay:
5944 11:35:25.667033 DQS0 = 0, DQS1 = 0
5945 11:35:25.670402 DQM Delay:
5946 11:35:25.670516 DQM0 = 100, DQM1 = 90
5947 11:35:25.670574 DQ Delay:
5948 11:35:25.673820 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =99
5949 11:35:25.677250 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5950 11:35:25.680814 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5951 11:35:25.683773 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5952 11:35:25.686819
5953 11:35:25.686892
5954 11:35:25.686947 ==
5955 11:35:25.690207 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:35:25.693903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:35:25.693981 ==
5958 11:35:25.694037
5959 11:35:25.694090
5960 11:35:25.697022 TX Vref Scan disable
5961 11:35:25.697152 == TX Byte 0 ==
5962 11:35:25.703381 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5963 11:35:25.706730 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5964 11:35:25.706799 == TX Byte 1 ==
5965 11:35:25.713198 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5966 11:35:25.716440 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5967 11:35:25.716555 ==
5968 11:35:25.719703 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 11:35:25.722856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 11:35:25.722928 ==
5971 11:35:25.722993
5972 11:35:25.726233
5973 11:35:25.726298 TX Vref Scan disable
5974 11:35:25.729428 == TX Byte 0 ==
5975 11:35:25.732622 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5976 11:35:25.739313 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5977 11:35:25.739381 == TX Byte 1 ==
5978 11:35:25.742662 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5979 11:35:25.749337 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5980 11:35:25.749407
5981 11:35:25.749471 [DATLAT]
5982 11:35:25.749525 Freq=933, CH1 RK1
5983 11:35:25.749577
5984 11:35:25.752800 DATLAT Default: 0xb
5985 11:35:25.755765 0, 0xFFFF, sum = 0
5986 11:35:25.755833 1, 0xFFFF, sum = 0
5987 11:35:25.758939 2, 0xFFFF, sum = 0
5988 11:35:25.758998 3, 0xFFFF, sum = 0
5989 11:35:25.762544 4, 0xFFFF, sum = 0
5990 11:35:25.762603 5, 0xFFFF, sum = 0
5991 11:35:25.765878 6, 0xFFFF, sum = 0
5992 11:35:25.765937 7, 0xFFFF, sum = 0
5993 11:35:25.769287 8, 0xFFFF, sum = 0
5994 11:35:25.769345 9, 0xFFFF, sum = 0
5995 11:35:25.772281 10, 0x0, sum = 1
5996 11:35:25.772346 11, 0x0, sum = 2
5997 11:35:25.775890 12, 0x0, sum = 3
5998 11:35:25.775954 13, 0x0, sum = 4
5999 11:35:25.778792 best_step = 11
6000 11:35:25.778855
6001 11:35:25.778905 ==
6002 11:35:25.782133 Dram Type= 6, Freq= 0, CH_1, rank 1
6003 11:35:25.785355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6004 11:35:25.785416 ==
6005 11:35:25.785466 RX Vref Scan: 0
6006 11:35:25.785515
6007 11:35:25.789352 RX Vref 0 -> 0, step: 1
6008 11:35:25.789422
6009 11:35:25.792206 RX Delay -69 -> 252, step: 4
6010 11:35:25.798892 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
6011 11:35:25.801788 iDelay=203, Bit 1, Center 94 (7 ~ 182) 176
6012 11:35:25.805653 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
6013 11:35:25.808677 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
6014 11:35:25.811942 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
6015 11:35:25.818420 iDelay=203, Bit 5, Center 110 (23 ~ 198) 176
6016 11:35:25.821918 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
6017 11:35:25.825284 iDelay=203, Bit 7, Center 98 (7 ~ 190) 184
6018 11:35:25.828641 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
6019 11:35:25.831959 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
6020 11:35:25.834858 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
6021 11:35:25.841721 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
6022 11:35:25.844880 iDelay=203, Bit 12, Center 104 (15 ~ 194) 180
6023 11:35:25.848370 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
6024 11:35:25.851574 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
6025 11:35:25.858106 iDelay=203, Bit 15, Center 104 (15 ~ 194) 180
6026 11:35:25.858182 ==
6027 11:35:25.861699 Dram Type= 6, Freq= 0, CH_1, rank 1
6028 11:35:25.864723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6029 11:35:25.864788 ==
6030 11:35:25.864843 DQS Delay:
6031 11:35:25.868766 DQS0 = 0, DQS1 = 0
6032 11:35:25.868828 DQM Delay:
6033 11:35:25.871534 DQM0 = 101, DQM1 = 93
6034 11:35:25.871593 DQ Delay:
6035 11:35:25.874597 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6036 11:35:25.878082 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =98
6037 11:35:25.881328 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =84
6038 11:35:25.884871 DQ12 =104, DQ13 =100, DQ14 =102, DQ15 =104
6039 11:35:25.884931
6040 11:35:25.884982
6041 11:35:25.894725 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6042 11:35:25.894803 CH1 RK1: MR19=504, MR18=6FF
6043 11:35:25.901208 CH1_RK1: MR19=0x504, MR18=0x6FF, DQSOSC=420, MR23=63, INC=61, DEC=40
6044 11:35:25.904875 [RxdqsGatingPostProcess] freq 933
6045 11:35:25.911076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6046 11:35:25.914352 best DQS0 dly(2T, 0.5T) = (0, 10)
6047 11:35:25.918140 best DQS1 dly(2T, 0.5T) = (0, 10)
6048 11:35:25.920819 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6049 11:35:25.924288 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6050 11:35:25.927476 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 11:35:25.927550 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 11:35:25.930687 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 11:35:25.934172 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 11:35:25.937832 Pre-setting of DQS Precalculation
6055 11:35:25.944170 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6056 11:35:25.950911 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6057 11:35:25.957386 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6058 11:35:25.957460
6059 11:35:25.957517
6060 11:35:25.960705 [Calibration Summary] 1866 Mbps
6061 11:35:25.963917 CH 0, Rank 0
6062 11:35:25.963990 SW Impedance : PASS
6063 11:35:25.967142 DUTY Scan : NO K
6064 11:35:25.967216 ZQ Calibration : PASS
6065 11:35:25.970681 Jitter Meter : NO K
6066 11:35:25.973930 CBT Training : PASS
6067 11:35:25.974004 Write leveling : PASS
6068 11:35:25.977330 RX DQS gating : PASS
6069 11:35:25.980320 RX DQ/DQS(RDDQC) : PASS
6070 11:35:25.980426 TX DQ/DQS : PASS
6071 11:35:25.983334 RX DATLAT : PASS
6072 11:35:25.987098 RX DQ/DQS(Engine): PASS
6073 11:35:25.987172 TX OE : NO K
6074 11:35:25.990071 All Pass.
6075 11:35:25.990144
6076 11:35:25.990201 CH 0, Rank 1
6077 11:35:25.993368 SW Impedance : PASS
6078 11:35:25.993442 DUTY Scan : NO K
6079 11:35:25.996837 ZQ Calibration : PASS
6080 11:35:26.000356 Jitter Meter : NO K
6081 11:35:26.000431 CBT Training : PASS
6082 11:35:26.003591 Write leveling : PASS
6083 11:35:26.006845 RX DQS gating : PASS
6084 11:35:26.006919 RX DQ/DQS(RDDQC) : PASS
6085 11:35:26.009793 TX DQ/DQS : PASS
6086 11:35:26.013508 RX DATLAT : PASS
6087 11:35:26.013582 RX DQ/DQS(Engine): PASS
6088 11:35:26.016789 TX OE : NO K
6089 11:35:26.016864 All Pass.
6090 11:35:26.016938
6091 11:35:26.019717 CH 1, Rank 0
6092 11:35:26.019791 SW Impedance : PASS
6093 11:35:26.023379 DUTY Scan : NO K
6094 11:35:26.026732 ZQ Calibration : PASS
6095 11:35:26.026805 Jitter Meter : NO K
6096 11:35:26.029975 CBT Training : PASS
6097 11:35:26.033327 Write leveling : PASS
6098 11:35:26.033401 RX DQS gating : PASS
6099 11:35:26.036816 RX DQ/DQS(RDDQC) : PASS
6100 11:35:26.036890 TX DQ/DQS : PASS
6101 11:35:26.039971 RX DATLAT : PASS
6102 11:35:26.043056 RX DQ/DQS(Engine): PASS
6103 11:35:26.043129 TX OE : NO K
6104 11:35:26.046299 All Pass.
6105 11:35:26.046372
6106 11:35:26.046430 CH 1, Rank 1
6107 11:35:26.049865 SW Impedance : PASS
6108 11:35:26.049939 DUTY Scan : NO K
6109 11:35:26.052837 ZQ Calibration : PASS
6110 11:35:26.056380 Jitter Meter : NO K
6111 11:35:26.056453 CBT Training : PASS
6112 11:35:26.059878 Write leveling : PASS
6113 11:35:26.062945 RX DQS gating : PASS
6114 11:35:26.063019 RX DQ/DQS(RDDQC) : PASS
6115 11:35:26.066133 TX DQ/DQS : PASS
6116 11:35:26.069369 RX DATLAT : PASS
6117 11:35:26.069442 RX DQ/DQS(Engine): PASS
6118 11:35:26.073087 TX OE : NO K
6119 11:35:26.073161 All Pass.
6120 11:35:26.073236
6121 11:35:26.075946 DramC Write-DBI off
6122 11:35:26.079600 PER_BANK_REFRESH: Hybrid Mode
6123 11:35:26.079676 TX_TRACKING: ON
6124 11:35:26.090052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6125 11:35:26.092611 [FAST_K] Save calibration result to emmc
6126 11:35:26.096324 dramc_set_vcore_voltage set vcore to 650000
6127 11:35:26.099188 Read voltage for 400, 6
6128 11:35:26.099263 Vio18 = 0
6129 11:35:26.099321 Vcore = 650000
6130 11:35:26.102703 Vdram = 0
6131 11:35:26.102780 Vddq = 0
6132 11:35:26.102838 Vmddr = 0
6133 11:35:26.109324 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6134 11:35:26.112362 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6135 11:35:26.116043 MEM_TYPE=3, freq_sel=20
6136 11:35:26.119545 sv_algorithm_assistance_LP4_800
6137 11:35:26.122211 ============ PULL DRAM RESETB DOWN ============
6138 11:35:26.125883 ========== PULL DRAM RESETB DOWN end =========
6139 11:35:26.132698 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6140 11:35:26.135561 ===================================
6141 11:35:26.139154 LPDDR4 DRAM CONFIGURATION
6142 11:35:26.142363 ===================================
6143 11:35:26.142438 EX_ROW_EN[0] = 0x0
6144 11:35:26.145311 EX_ROW_EN[1] = 0x0
6145 11:35:26.145411 LP4Y_EN = 0x0
6146 11:35:26.148989 WORK_FSP = 0x0
6147 11:35:26.149064 WL = 0x2
6148 11:35:26.152103 RL = 0x2
6149 11:35:26.152177 BL = 0x2
6150 11:35:26.155566 RPST = 0x0
6151 11:35:26.155639 RD_PRE = 0x0
6152 11:35:26.158988 WR_PRE = 0x1
6153 11:35:26.159365 WR_PST = 0x0
6154 11:35:26.162434 DBI_WR = 0x0
6155 11:35:26.162812 DBI_RD = 0x0
6156 11:35:26.165559 OTF = 0x1
6157 11:35:26.169307 ===================================
6158 11:35:26.172424 ===================================
6159 11:35:26.172814 ANA top config
6160 11:35:26.176101 ===================================
6161 11:35:26.179190 DLL_ASYNC_EN = 0
6162 11:35:26.182556 ALL_SLAVE_EN = 1
6163 11:35:26.185762 NEW_RANK_MODE = 1
6164 11:35:26.189414 DLL_IDLE_MODE = 1
6165 11:35:26.189877 LP45_APHY_COMB_EN = 1
6166 11:35:26.192641 TX_ODT_DIS = 1
6167 11:35:26.195353 NEW_8X_MODE = 1
6168 11:35:26.199659 ===================================
6169 11:35:26.201950 ===================================
6170 11:35:26.205470 data_rate = 800
6171 11:35:26.208478 CKR = 1
6172 11:35:26.209126 DQ_P2S_RATIO = 4
6173 11:35:26.211697 ===================================
6174 11:35:26.215222 CA_P2S_RATIO = 4
6175 11:35:26.218233 DQ_CA_OPEN = 0
6176 11:35:26.221696 DQ_SEMI_OPEN = 1
6177 11:35:26.224740 CA_SEMI_OPEN = 1
6178 11:35:26.228237 CA_FULL_RATE = 0
6179 11:35:26.231862 DQ_CKDIV4_EN = 0
6180 11:35:26.232302 CA_CKDIV4_EN = 1
6181 11:35:26.234739 CA_PREDIV_EN = 0
6182 11:35:26.237763 PH8_DLY = 0
6183 11:35:26.241119 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6184 11:35:26.244458 DQ_AAMCK_DIV = 0
6185 11:35:26.247660 CA_AAMCK_DIV = 0
6186 11:35:26.247731 CA_ADMCK_DIV = 4
6187 11:35:26.251135 DQ_TRACK_CA_EN = 0
6188 11:35:26.254442 CA_PICK = 800
6189 11:35:26.257649 CA_MCKIO = 400
6190 11:35:26.260551 MCKIO_SEMI = 400
6191 11:35:26.264351 PLL_FREQ = 3016
6192 11:35:26.267491 DQ_UI_PI_RATIO = 32
6193 11:35:26.270994 CA_UI_PI_RATIO = 32
6194 11:35:26.271056 ===================================
6195 11:35:26.274096 ===================================
6196 11:35:26.277297 memory_type:LPDDR4
6197 11:35:26.280852 GP_NUM : 10
6198 11:35:26.280917 SRAM_EN : 1
6199 11:35:26.284342 MD32_EN : 0
6200 11:35:26.287217 ===================================
6201 11:35:26.290417 [ANA_INIT] >>>>>>>>>>>>>>
6202 11:35:26.293915 <<<<<< [CONFIGURE PHASE]: ANA_TX
6203 11:35:26.297083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6204 11:35:26.300901 ===================================
6205 11:35:26.300967 data_rate = 800,PCW = 0X7400
6206 11:35:26.304010 ===================================
6207 11:35:26.310542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6208 11:35:26.313763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6209 11:35:26.326906 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6210 11:35:26.330058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6211 11:35:26.333315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6212 11:35:26.336998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6213 11:35:26.340278 [ANA_INIT] flow start
6214 11:35:26.340343 [ANA_INIT] PLL >>>>>>>>
6215 11:35:26.343245 [ANA_INIT] PLL <<<<<<<<
6216 11:35:26.346762 [ANA_INIT] MIDPI >>>>>>>>
6217 11:35:26.350011 [ANA_INIT] MIDPI <<<<<<<<
6218 11:35:26.350091 [ANA_INIT] DLL >>>>>>>>
6219 11:35:26.353339 [ANA_INIT] flow end
6220 11:35:26.356491 ============ LP4 DIFF to SE enter ============
6221 11:35:26.359775 ============ LP4 DIFF to SE exit ============
6222 11:35:26.363108 [ANA_INIT] <<<<<<<<<<<<<
6223 11:35:26.366298 [Flow] Enable top DCM control >>>>>
6224 11:35:26.369571 [Flow] Enable top DCM control <<<<<
6225 11:35:26.373207 Enable DLL master slave shuffle
6226 11:35:26.379755 ==============================================================
6227 11:35:26.379832 Gating Mode config
6228 11:35:26.386103 ==============================================================
6229 11:35:26.386169 Config description:
6230 11:35:26.396086 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6231 11:35:26.402816 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6232 11:35:26.409597 SELPH_MODE 0: By rank 1: By Phase
6233 11:35:26.412429 ==============================================================
6234 11:35:26.415711 GAT_TRACK_EN = 0
6235 11:35:26.419399 RX_GATING_MODE = 2
6236 11:35:26.422475 RX_GATING_TRACK_MODE = 2
6237 11:35:26.425570 SELPH_MODE = 1
6238 11:35:26.428915 PICG_EARLY_EN = 1
6239 11:35:26.432243 VALID_LAT_VALUE = 1
6240 11:35:26.438562 ==============================================================
6241 11:35:26.441983 Enter into Gating configuration >>>>
6242 11:35:26.445166 Exit from Gating configuration <<<<
6243 11:35:26.448586 Enter into DVFS_PRE_config >>>>>
6244 11:35:26.458472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6245 11:35:26.461687 Exit from DVFS_PRE_config <<<<<
6246 11:35:26.465229 Enter into PICG configuration >>>>
6247 11:35:26.468389 Exit from PICG configuration <<<<
6248 11:35:26.471647 [RX_INPUT] configuration >>>>>
6249 11:35:26.475021 [RX_INPUT] configuration <<<<<
6250 11:35:26.478158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6251 11:35:26.484637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6252 11:35:26.491671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6253 11:35:26.498228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6254 11:35:26.501763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6255 11:35:26.508502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6256 11:35:26.512074 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6257 11:35:26.518233 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6258 11:35:26.521862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6259 11:35:26.524949 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6260 11:35:26.528713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6261 11:35:26.534694 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6262 11:35:26.537979 ===================================
6263 11:35:26.538072 LPDDR4 DRAM CONFIGURATION
6264 11:35:26.541506 ===================================
6265 11:35:26.544810 EX_ROW_EN[0] = 0x0
6266 11:35:26.547929 EX_ROW_EN[1] = 0x0
6267 11:35:26.548031 LP4Y_EN = 0x0
6268 11:35:26.551287 WORK_FSP = 0x0
6269 11:35:26.551509 WL = 0x2
6270 11:35:26.554397 RL = 0x2
6271 11:35:26.554545 BL = 0x2
6272 11:35:26.557911 RPST = 0x0
6273 11:35:26.558094 RD_PRE = 0x0
6274 11:35:26.561418 WR_PRE = 0x1
6275 11:35:26.561547 WR_PST = 0x0
6276 11:35:26.564644 DBI_WR = 0x0
6277 11:35:26.564766 DBI_RD = 0x0
6278 11:35:26.568207 OTF = 0x1
6279 11:35:26.571351 ===================================
6280 11:35:26.574324 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6281 11:35:26.577645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6282 11:35:26.584349 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6283 11:35:26.587526 ===================================
6284 11:35:26.587745 LPDDR4 DRAM CONFIGURATION
6285 11:35:26.591049 ===================================
6286 11:35:26.594699 EX_ROW_EN[0] = 0x10
6287 11:35:26.598095 EX_ROW_EN[1] = 0x0
6288 11:35:26.598475 LP4Y_EN = 0x0
6289 11:35:26.600914 WORK_FSP = 0x0
6290 11:35:26.601293 WL = 0x2
6291 11:35:26.604481 RL = 0x2
6292 11:35:26.604863 BL = 0x2
6293 11:35:26.607977 RPST = 0x0
6294 11:35:26.608354 RD_PRE = 0x0
6295 11:35:26.610877 WR_PRE = 0x1
6296 11:35:26.611256 WR_PST = 0x0
6297 11:35:26.614837 DBI_WR = 0x0
6298 11:35:26.615217 DBI_RD = 0x0
6299 11:35:26.617486 OTF = 0x1
6300 11:35:26.620718 ===================================
6301 11:35:26.627851 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6302 11:35:26.630571 nWR fixed to 30
6303 11:35:26.634073 [ModeRegInit_LP4] CH0 RK0
6304 11:35:26.634455 [ModeRegInit_LP4] CH0 RK1
6305 11:35:26.637353 [ModeRegInit_LP4] CH1 RK0
6306 11:35:26.640373 [ModeRegInit_LP4] CH1 RK1
6307 11:35:26.640756 match AC timing 19
6308 11:35:26.647309 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6309 11:35:26.650766 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6310 11:35:26.653480 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6311 11:35:26.660379 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6312 11:35:26.663826 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6313 11:35:26.664205 ==
6314 11:35:26.667108 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 11:35:26.670677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:35:26.671145 ==
6317 11:35:26.676754 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 11:35:26.683642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6319 11:35:26.686948 [CA 0] Center 36 (8~64) winsize 57
6320 11:35:26.690350 [CA 1] Center 36 (8~64) winsize 57
6321 11:35:26.693739 [CA 2] Center 36 (8~64) winsize 57
6322 11:35:26.697176 [CA 3] Center 36 (8~64) winsize 57
6323 11:35:26.699909 [CA 4] Center 36 (8~64) winsize 57
6324 11:35:26.703402 [CA 5] Center 36 (8~64) winsize 57
6325 11:35:26.703824
6326 11:35:26.706601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6327 11:35:26.707052
6328 11:35:26.709631 [CATrainingPosCal] consider 1 rank data
6329 11:35:26.713288 u2DelayCellTimex100 = 270/100 ps
6330 11:35:26.716216 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:35:26.719855 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:35:26.722814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:35:26.726490 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:35:26.729659 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:35:26.733195 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 11:35:26.733594
6337 11:35:26.736500 CA PerBit enable=1, Macro0, CA PI delay=36
6338 11:35:26.736878
6339 11:35:26.740013 [CBTSetCACLKResult] CA Dly = 36
6340 11:35:26.742921 CS Dly: 1 (0~32)
6341 11:35:26.743295 ==
6342 11:35:26.746509 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 11:35:26.749924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:35:26.750306 ==
6345 11:35:26.756432 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6346 11:35:26.762696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6347 11:35:26.766157 [CA 0] Center 36 (8~64) winsize 57
6348 11:35:26.769306 [CA 1] Center 36 (8~64) winsize 57
6349 11:35:26.769685 [CA 2] Center 36 (8~64) winsize 57
6350 11:35:26.772626 [CA 3] Center 36 (8~64) winsize 57
6351 11:35:26.775770 [CA 4] Center 36 (8~64) winsize 57
6352 11:35:26.779060 [CA 5] Center 36 (8~64) winsize 57
6353 11:35:26.779471
6354 11:35:26.785770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6355 11:35:26.786323
6356 11:35:26.788902 [CATrainingPosCal] consider 2 rank data
6357 11:35:26.792258 u2DelayCellTimex100 = 270/100 ps
6358 11:35:26.795679 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 11:35:26.799027 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 11:35:26.802955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 11:35:26.805566 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 11:35:26.808748 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 11:35:26.812410 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 11:35:26.812841
6365 11:35:26.815736 CA PerBit enable=1, Macro0, CA PI delay=36
6366 11:35:26.816113
6367 11:35:26.818968 [CBTSetCACLKResult] CA Dly = 36
6368 11:35:26.821804 CS Dly: 1 (0~32)
6369 11:35:26.822515
6370 11:35:26.825499 ----->DramcWriteLeveling(PI) begin...
6371 11:35:26.825879 ==
6372 11:35:26.828727 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 11:35:26.831987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 11:35:26.832592 ==
6375 11:35:26.835593 Write leveling (Byte 0): 40 => 8
6376 11:35:26.838601 Write leveling (Byte 1): 32 => 0
6377 11:35:26.842256 DramcWriteLeveling(PI) end<-----
6378 11:35:26.842637
6379 11:35:26.842936 ==
6380 11:35:26.845416 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:35:26.848472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:35:26.848752 ==
6383 11:35:26.852187 [Gating] SW mode calibration
6384 11:35:26.858569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6385 11:35:26.865471 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6386 11:35:26.867997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6387 11:35:26.871821 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6388 11:35:26.878671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6389 11:35:26.881462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 11:35:26.885179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 11:35:26.891862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6392 11:35:26.894782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6393 11:35:26.898098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 11:35:26.904736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6395 11:35:26.908194 Total UI for P1: 0, mck2ui 16
6396 11:35:26.911418 best dqsien dly found for B0: ( 0, 14, 24)
6397 11:35:26.914463 Total UI for P1: 0, mck2ui 16
6398 11:35:26.918000 best dqsien dly found for B1: ( 0, 14, 24)
6399 11:35:26.921711 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6400 11:35:26.924717 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6401 11:35:26.925097
6402 11:35:26.928092 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6403 11:35:26.931182 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6404 11:35:26.934246 [Gating] SW calibration Done
6405 11:35:26.934698 ==
6406 11:35:26.937423 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:35:26.940751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:35:26.941169 ==
6409 11:35:26.944101 RX Vref Scan: 0
6410 11:35:26.944552
6411 11:35:26.947407 RX Vref 0 -> 0, step: 1
6412 11:35:26.947822
6413 11:35:26.950599 RX Delay -410 -> 252, step: 16
6414 11:35:26.954171 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6415 11:35:26.957453 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6416 11:35:26.960386 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6417 11:35:26.968119 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6418 11:35:26.970596 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6419 11:35:26.973572 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6420 11:35:26.977146 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6421 11:35:26.983596 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6422 11:35:26.986699 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6423 11:35:26.989963 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6424 11:35:26.996445 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6425 11:35:26.999889 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6426 11:35:27.002762 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6427 11:35:27.006327 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6428 11:35:27.012852 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6429 11:35:27.015795 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6430 11:35:27.015870 ==
6431 11:35:27.019587 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 11:35:27.022457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 11:35:27.022532 ==
6434 11:35:27.025794 DQS Delay:
6435 11:35:27.025868 DQS0 = 43, DQS1 = 59
6436 11:35:27.029219 DQM Delay:
6437 11:35:27.029293 DQM0 = 9, DQM1 = 11
6438 11:35:27.029350 DQ Delay:
6439 11:35:27.032787 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6440 11:35:27.035830 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6441 11:35:27.039221 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6442 11:35:27.042365 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6443 11:35:27.042439
6444 11:35:27.042497
6445 11:35:27.042551 ==
6446 11:35:27.045651 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 11:35:27.052498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:35:27.052573 ==
6449 11:35:27.052631
6450 11:35:27.052684
6451 11:35:27.052734 TX Vref Scan disable
6452 11:35:27.055347 == TX Byte 0 ==
6453 11:35:27.058809 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 11:35:27.062317 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 11:35:27.065382 == TX Byte 1 ==
6456 11:35:27.068821 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 11:35:27.072164 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 11:35:27.075678 ==
6459 11:35:27.075752 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 11:35:27.081734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 11:35:27.081809 ==
6462 11:35:27.081867
6463 11:35:27.081921
6464 11:35:27.085444 TX Vref Scan disable
6465 11:35:27.085518 == TX Byte 0 ==
6466 11:35:27.088648 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 11:35:27.095286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 11:35:27.095361 == TX Byte 1 ==
6469 11:35:27.098612 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6470 11:35:27.104820 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6471 11:35:27.104895
6472 11:35:27.104955 [DATLAT]
6473 11:35:27.105009 Freq=400, CH0 RK0
6474 11:35:27.105061
6475 11:35:27.108355 DATLAT Default: 0xf
6476 11:35:27.111274 0, 0xFFFF, sum = 0
6477 11:35:27.111392 1, 0xFFFF, sum = 0
6478 11:35:27.114946 2, 0xFFFF, sum = 0
6479 11:35:27.115021 3, 0xFFFF, sum = 0
6480 11:35:27.118065 4, 0xFFFF, sum = 0
6481 11:35:27.118141 5, 0xFFFF, sum = 0
6482 11:35:27.121831 6, 0xFFFF, sum = 0
6483 11:35:27.121908 7, 0xFFFF, sum = 0
6484 11:35:27.124753 8, 0xFFFF, sum = 0
6485 11:35:27.124828 9, 0xFFFF, sum = 0
6486 11:35:27.128022 10, 0xFFFF, sum = 0
6487 11:35:27.128097 11, 0xFFFF, sum = 0
6488 11:35:27.131334 12, 0xFFFF, sum = 0
6489 11:35:27.131412 13, 0x0, sum = 1
6490 11:35:27.134907 14, 0x0, sum = 2
6491 11:35:27.134982 15, 0x0, sum = 3
6492 11:35:27.138062 16, 0x0, sum = 4
6493 11:35:27.138137 best_step = 14
6494 11:35:27.138246
6495 11:35:27.138300 ==
6496 11:35:27.141527 Dram Type= 6, Freq= 0, CH_0, rank 0
6497 11:35:27.147963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:35:27.148039 ==
6499 11:35:27.148097 RX Vref Scan: 1
6500 11:35:27.148151
6501 11:35:27.151185 RX Vref 0 -> 0, step: 1
6502 11:35:27.151259
6503 11:35:27.154850 RX Delay -359 -> 252, step: 8
6504 11:35:27.154925
6505 11:35:27.157841 Set Vref, RX VrefLevel [Byte0]: 66
6506 11:35:27.161143 [Byte1]: 58
6507 11:35:27.161225
6508 11:35:27.164240 Final RX Vref Byte 0 = 66 to rank0
6509 11:35:27.167870 Final RX Vref Byte 1 = 58 to rank0
6510 11:35:27.171315 Final RX Vref Byte 0 = 66 to rank1
6511 11:35:27.174143 Final RX Vref Byte 1 = 58 to rank1==
6512 11:35:27.177553 Dram Type= 6, Freq= 0, CH_0, rank 0
6513 11:35:27.184106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 11:35:27.184181 ==
6515 11:35:27.184240 DQS Delay:
6516 11:35:27.187878 DQS0 = 48, DQS1 = 60
6517 11:35:27.187952 DQM Delay:
6518 11:35:27.188011 DQM0 = 12, DQM1 = 11
6519 11:35:27.190523 DQ Delay:
6520 11:35:27.194369 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6521 11:35:27.194443 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6522 11:35:27.197368 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6523 11:35:27.200964 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6524 11:35:27.201038
6525 11:35:27.203787
6526 11:35:27.210469 [DQSOSCAuto] RK0, (LSB)MR18= 0xb97c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6527 11:35:27.214165 CH0 RK0: MR19=C0C, MR18=B97C
6528 11:35:27.220220 CH0_RK0: MR19=0xC0C, MR18=0xB97C, DQSOSC=386, MR23=63, INC=396, DEC=264
6529 11:35:27.220295 ==
6530 11:35:27.223865 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:35:27.227170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:35:27.227245 ==
6533 11:35:27.230471 [Gating] SW mode calibration
6534 11:35:27.236898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6535 11:35:27.243286 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6536 11:35:27.246469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6537 11:35:27.249873 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6538 11:35:27.256713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6539 11:35:27.259862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 11:35:27.263324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 11:35:27.269447 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6542 11:35:27.273553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6543 11:35:27.276484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 11:35:27.283254 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6545 11:35:27.286282 Total UI for P1: 0, mck2ui 16
6546 11:35:27.289751 best dqsien dly found for B0: ( 0, 14, 24)
6547 11:35:27.290143 Total UI for P1: 0, mck2ui 16
6548 11:35:27.296343 best dqsien dly found for B1: ( 0, 14, 24)
6549 11:35:27.300066 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6550 11:35:27.302824 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6551 11:35:27.303285
6552 11:35:27.306204 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6553 11:35:27.309612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6554 11:35:27.312800 [Gating] SW calibration Done
6555 11:35:27.313187 ==
6556 11:35:27.316148 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 11:35:27.320573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:35:27.320961 ==
6559 11:35:27.322662 RX Vref Scan: 0
6560 11:35:27.323043
6561 11:35:27.326470 RX Vref 0 -> 0, step: 1
6562 11:35:27.326857
6563 11:35:27.327160 RX Delay -410 -> 252, step: 16
6564 11:35:27.332945 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6565 11:35:27.335765 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6566 11:35:27.339054 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6567 11:35:27.345969 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6568 11:35:27.349034 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6569 11:35:27.352566 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6570 11:35:27.355492 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6571 11:35:27.363460 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6572 11:35:27.365660 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6573 11:35:27.369193 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6574 11:35:27.372240 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6575 11:35:27.378621 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6576 11:35:27.381912 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6577 11:35:27.385860 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6578 11:35:27.389635 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6579 11:35:27.395469 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6580 11:35:27.395856 ==
6581 11:35:27.398513 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 11:35:27.401945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 11:35:27.402387 ==
6584 11:35:27.402694 DQS Delay:
6585 11:35:27.405327 DQS0 = 43, DQS1 = 59
6586 11:35:27.405708 DQM Delay:
6587 11:35:27.409110 DQM0 = 10, DQM1 = 15
6588 11:35:27.409489 DQ Delay:
6589 11:35:27.412040 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6590 11:35:27.415216 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6591 11:35:27.418337 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6592 11:35:27.421644 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6593 11:35:27.422065
6594 11:35:27.422484
6595 11:35:27.422849 ==
6596 11:35:27.425110 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 11:35:27.428201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:35:27.428675 ==
6599 11:35:27.431584
6600 11:35:27.431964
6601 11:35:27.432263 TX Vref Scan disable
6602 11:35:27.435123 == TX Byte 0 ==
6603 11:35:27.438294 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6604 11:35:27.441704 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6605 11:35:27.445072 == TX Byte 1 ==
6606 11:35:27.447667 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6607 11:35:27.451420 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6608 11:35:27.451843 ==
6609 11:35:27.454678 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 11:35:27.458431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 11:35:27.461305 ==
6612 11:35:27.461685
6613 11:35:27.461982
6614 11:35:27.462260 TX Vref Scan disable
6615 11:35:27.464840 == TX Byte 0 ==
6616 11:35:27.468179 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6617 11:35:27.470981 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6618 11:35:27.474512 == TX Byte 1 ==
6619 11:35:27.477817 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6620 11:35:27.481023 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6621 11:35:27.481415
6622 11:35:27.484295 [DATLAT]
6623 11:35:27.484687 Freq=400, CH0 RK1
6624 11:35:27.485169
6625 11:35:27.487631 DATLAT Default: 0xe
6626 11:35:27.488013 0, 0xFFFF, sum = 0
6627 11:35:27.491218 1, 0xFFFF, sum = 0
6628 11:35:27.491659 2, 0xFFFF, sum = 0
6629 11:35:27.494088 3, 0xFFFF, sum = 0
6630 11:35:27.494474 4, 0xFFFF, sum = 0
6631 11:35:27.497594 5, 0xFFFF, sum = 0
6632 11:35:27.497986 6, 0xFFFF, sum = 0
6633 11:35:27.500605 7, 0xFFFF, sum = 0
6634 11:35:27.500997 8, 0xFFFF, sum = 0
6635 11:35:27.504182 9, 0xFFFF, sum = 0
6636 11:35:27.504574 10, 0xFFFF, sum = 0
6637 11:35:27.507366 11, 0xFFFF, sum = 0
6638 11:35:27.510726 12, 0xFFFF, sum = 0
6639 11:35:27.511117 13, 0x0, sum = 1
6640 11:35:27.514183 14, 0x0, sum = 2
6641 11:35:27.514579 15, 0x0, sum = 3
6642 11:35:27.514887 16, 0x0, sum = 4
6643 11:35:27.517173 best_step = 14
6644 11:35:27.517570
6645 11:35:27.517876 ==
6646 11:35:27.520613 Dram Type= 6, Freq= 0, CH_0, rank 1
6647 11:35:27.523613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 11:35:27.524002 ==
6649 11:35:27.527007 RX Vref Scan: 0
6650 11:35:27.527391
6651 11:35:27.530585 RX Vref 0 -> 0, step: 1
6652 11:35:27.531014
6653 11:35:27.531377 RX Delay -359 -> 252, step: 8
6654 11:35:27.539046 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6655 11:35:27.542942 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6656 11:35:27.545931 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6657 11:35:27.549184 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6658 11:35:27.555312 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6659 11:35:27.558846 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6660 11:35:27.562530 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6661 11:35:27.565435 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6662 11:35:27.572242 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6663 11:35:27.575642 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6664 11:35:27.578393 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6665 11:35:27.584935 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6666 11:35:27.588400 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6667 11:35:27.591668 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6668 11:35:27.594940 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6669 11:35:27.601499 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6670 11:35:27.601947 ==
6671 11:35:27.604772 Dram Type= 6, Freq= 0, CH_0, rank 1
6672 11:35:27.608065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 11:35:27.608464 ==
6674 11:35:27.608858 DQS Delay:
6675 11:35:27.611298 DQS0 = 44, DQS1 = 60
6676 11:35:27.611732 DQM Delay:
6677 11:35:27.614903 DQM0 = 7, DQM1 = 14
6678 11:35:27.615297 DQ Delay:
6679 11:35:27.617847 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =0
6680 11:35:27.621282 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6681 11:35:27.624593 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6682 11:35:27.628002 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6683 11:35:27.628397
6684 11:35:27.628788
6685 11:35:27.634417 [DQSOSCAuto] RK1, (LSB)MR18= 0xb240, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6686 11:35:27.637945 CH0 RK1: MR19=C0C, MR18=B240
6687 11:35:27.644751 CH0_RK1: MR19=0xC0C, MR18=0xB240, DQSOSC=387, MR23=63, INC=394, DEC=262
6688 11:35:27.647676 [RxdqsGatingPostProcess] freq 400
6689 11:35:27.654291 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6690 11:35:27.657341 best DQS0 dly(2T, 0.5T) = (0, 10)
6691 11:35:27.660897 best DQS1 dly(2T, 0.5T) = (0, 10)
6692 11:35:27.664145 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6693 11:35:27.667161 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6694 11:35:27.670591 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 11:35:27.670985 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 11:35:27.673815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 11:35:27.676956 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 11:35:27.680703 Pre-setting of DQS Precalculation
6699 11:35:27.687194 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6700 11:35:27.687635 ==
6701 11:35:27.690392 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 11:35:27.693401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:35:27.693810 ==
6704 11:35:27.700658 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 11:35:27.706591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6706 11:35:27.710416 [CA 0] Center 36 (8~64) winsize 57
6707 11:35:27.713543 [CA 1] Center 36 (8~64) winsize 57
6708 11:35:27.716457 [CA 2] Center 36 (8~64) winsize 57
6709 11:35:27.716893 [CA 3] Center 36 (8~64) winsize 57
6710 11:35:27.719875 [CA 4] Center 36 (8~64) winsize 57
6711 11:35:27.723826 [CA 5] Center 36 (8~64) winsize 57
6712 11:35:27.724204
6713 11:35:27.729968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6714 11:35:27.730360
6715 11:35:27.733455 [CATrainingPosCal] consider 1 rank data
6716 11:35:27.736634 u2DelayCellTimex100 = 270/100 ps
6717 11:35:27.739722 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:35:27.743351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:35:27.746184 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:35:27.749690 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:35:27.753026 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:35:27.756537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 11:35:27.756916
6724 11:35:27.759505 CA PerBit enable=1, Macro0, CA PI delay=36
6725 11:35:27.759949
6726 11:35:27.763242 [CBTSetCACLKResult] CA Dly = 36
6727 11:35:27.766163 CS Dly: 1 (0~32)
6728 11:35:27.766540 ==
6729 11:35:27.769350 Dram Type= 6, Freq= 0, CH_1, rank 1
6730 11:35:27.772709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:35:27.773089 ==
6732 11:35:27.779402 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6733 11:35:27.786044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6734 11:35:27.789064 [CA 0] Center 36 (8~64) winsize 57
6735 11:35:27.792160 [CA 1] Center 36 (8~64) winsize 57
6736 11:35:27.792563 [CA 2] Center 36 (8~64) winsize 57
6737 11:35:27.795710 [CA 3] Center 36 (8~64) winsize 57
6738 11:35:27.799045 [CA 4] Center 36 (8~64) winsize 57
6739 11:35:27.802083 [CA 5] Center 36 (8~64) winsize 57
6740 11:35:27.802511
6741 11:35:27.805582 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6742 11:35:27.808855
6743 11:35:27.811962 [CATrainingPosCal] consider 2 rank data
6744 11:35:27.815954 u2DelayCellTimex100 = 270/100 ps
6745 11:35:27.818604 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 11:35:27.821840 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 11:35:27.825103 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 11:35:27.828522 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 11:35:27.831806 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 11:35:27.835285 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 11:35:27.835763
6752 11:35:27.838268 CA PerBit enable=1, Macro0, CA PI delay=36
6753 11:35:27.838649
6754 11:35:27.841428 [CBTSetCACLKResult] CA Dly = 36
6755 11:35:27.845167 CS Dly: 1 (0~32)
6756 11:35:27.845580
6757 11:35:27.847963 ----->DramcWriteLeveling(PI) begin...
6758 11:35:27.848344 ==
6759 11:35:27.851648 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 11:35:27.854831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 11:35:27.855263 ==
6762 11:35:27.858147 Write leveling (Byte 0): 40 => 8
6763 11:35:27.861600 Write leveling (Byte 1): 32 => 0
6764 11:35:27.865170 DramcWriteLeveling(PI) end<-----
6765 11:35:27.865563
6766 11:35:27.865859 ==
6767 11:35:27.868084 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:35:27.871057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:35:27.871478 ==
6770 11:35:27.874648 [Gating] SW mode calibration
6771 11:35:27.880986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6772 11:35:27.888047 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6773 11:35:27.890841 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6774 11:35:27.897909 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6775 11:35:27.901030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6776 11:35:27.904815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 11:35:27.911249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 11:35:27.914165 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6779 11:35:27.917808 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6780 11:35:27.923880 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 11:35:27.927488 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6782 11:35:27.930759 Total UI for P1: 0, mck2ui 16
6783 11:35:27.933949 best dqsien dly found for B0: ( 0, 14, 24)
6784 11:35:27.937576 Total UI for P1: 0, mck2ui 16
6785 11:35:27.940364 best dqsien dly found for B1: ( 0, 14, 24)
6786 11:35:27.944137 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6787 11:35:27.947487 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6788 11:35:27.947877
6789 11:35:27.950617 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6790 11:35:27.953846 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6791 11:35:27.956996 [Gating] SW calibration Done
6792 11:35:27.957383 ==
6793 11:35:27.960830 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:35:27.963899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:35:27.966930 ==
6796 11:35:27.967475 RX Vref Scan: 0
6797 11:35:27.967840
6798 11:35:27.970272 RX Vref 0 -> 0, step: 1
6799 11:35:27.970772
6800 11:35:27.973484 RX Delay -410 -> 252, step: 16
6801 11:35:27.976804 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6802 11:35:27.980135 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6803 11:35:27.983404 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6804 11:35:27.989936 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6805 11:35:27.993235 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6806 11:35:27.996275 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6807 11:35:28.000726 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6808 11:35:28.006436 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6809 11:35:28.010135 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6810 11:35:28.013329 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6811 11:35:28.016171 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6812 11:35:28.023036 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6813 11:35:28.026243 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6814 11:35:28.029756 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6815 11:35:28.036209 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6816 11:35:28.039260 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6817 11:35:28.039685 ==
6818 11:35:28.042884 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 11:35:28.046331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 11:35:28.046845 ==
6821 11:35:28.049295 DQS Delay:
6822 11:35:28.049711 DQS0 = 43, DQS1 = 51
6823 11:35:28.052442 DQM Delay:
6824 11:35:28.052902 DQM0 = 12, DQM1 = 14
6825 11:35:28.053264 DQ Delay:
6826 11:35:28.056365 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6827 11:35:28.059071 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6828 11:35:28.062302 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6829 11:35:28.065836 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6830 11:35:28.066218
6831 11:35:28.066516
6832 11:35:28.066787 ==
6833 11:35:28.069186 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 11:35:28.075371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:35:28.075801 ==
6836 11:35:28.076104
6837 11:35:28.076376
6838 11:35:28.076643 TX Vref Scan disable
6839 11:35:28.078968 == TX Byte 0 ==
6840 11:35:28.082170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 11:35:28.085448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 11:35:28.089019 == TX Byte 1 ==
6843 11:35:28.092125 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6844 11:35:28.095416 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6845 11:35:28.098459 ==
6846 11:35:28.098844 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 11:35:28.105304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 11:35:28.105742 ==
6849 11:35:28.106135
6850 11:35:28.106595
6851 11:35:28.108540 TX Vref Scan disable
6852 11:35:28.109045 == TX Byte 0 ==
6853 11:35:28.111668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 11:35:28.118434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 11:35:28.118870 == TX Byte 1 ==
6856 11:35:28.121677 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6857 11:35:28.128076 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6858 11:35:28.128456
6859 11:35:28.128750 [DATLAT]
6860 11:35:28.129022 Freq=400, CH1 RK0
6861 11:35:28.129287
6862 11:35:28.131419 DATLAT Default: 0xf
6863 11:35:28.134839 0, 0xFFFF, sum = 0
6864 11:35:28.135223 1, 0xFFFF, sum = 0
6865 11:35:28.138649 2, 0xFFFF, sum = 0
6866 11:35:28.139180 3, 0xFFFF, sum = 0
6867 11:35:28.142082 4, 0xFFFF, sum = 0
6868 11:35:28.142566 5, 0xFFFF, sum = 0
6869 11:35:28.144892 6, 0xFFFF, sum = 0
6870 11:35:28.145282 7, 0xFFFF, sum = 0
6871 11:35:28.148139 8, 0xFFFF, sum = 0
6872 11:35:28.148526 9, 0xFFFF, sum = 0
6873 11:35:28.151783 10, 0xFFFF, sum = 0
6874 11:35:28.152256 11, 0xFFFF, sum = 0
6875 11:35:28.154621 12, 0xFFFF, sum = 0
6876 11:35:28.155171 13, 0x0, sum = 1
6877 11:35:28.158446 14, 0x0, sum = 2
6878 11:35:28.159020 15, 0x0, sum = 3
6879 11:35:28.161038 16, 0x0, sum = 4
6880 11:35:28.161602 best_step = 14
6881 11:35:28.162088
6882 11:35:28.162571 ==
6883 11:35:28.164278 Dram Type= 6, Freq= 0, CH_1, rank 0
6884 11:35:28.171915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:35:28.172468 ==
6886 11:35:28.173000 RX Vref Scan: 1
6887 11:35:28.173482
6888 11:35:28.174480 RX Vref 0 -> 0, step: 1
6889 11:35:28.174981
6890 11:35:28.177692 RX Delay -343 -> 252, step: 8
6891 11:35:28.178238
6892 11:35:28.181325 Set Vref, RX VrefLevel [Byte0]: 47
6893 11:35:28.184390 [Byte1]: 51
6894 11:35:28.184984
6895 11:35:28.188100 Final RX Vref Byte 0 = 47 to rank0
6896 11:35:28.190646 Final RX Vref Byte 1 = 51 to rank0
6897 11:35:28.193964 Final RX Vref Byte 0 = 47 to rank1
6898 11:35:28.197654 Final RX Vref Byte 1 = 51 to rank1==
6899 11:35:28.200732 Dram Type= 6, Freq= 0, CH_1, rank 0
6900 11:35:28.204305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 11:35:28.207183 ==
6902 11:35:28.207648 DQS Delay:
6903 11:35:28.207964 DQS0 = 44, DQS1 = 56
6904 11:35:28.210731 DQM Delay:
6905 11:35:28.211108 DQM0 = 7, DQM1 = 12
6906 11:35:28.213837 DQ Delay:
6907 11:35:28.214248 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6908 11:35:28.217216 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =0
6909 11:35:28.220489 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6910 11:35:28.223606 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6911 11:35:28.223998
6912 11:35:28.224335
6913 11:35:28.233840 [DQSOSCAuto] RK0, (LSB)MR18= 0x996e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6914 11:35:28.236718 CH1 RK0: MR19=C0C, MR18=996E
6915 11:35:28.243460 CH1_RK0: MR19=0xC0C, MR18=0x996E, DQSOSC=390, MR23=63, INC=388, DEC=258
6916 11:35:28.243644 ==
6917 11:35:28.246662 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:35:28.250257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:35:28.250436 ==
6920 11:35:28.253764 [Gating] SW mode calibration
6921 11:35:28.259950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6922 11:35:28.266437 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6923 11:35:28.269687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6924 11:35:28.272820 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6925 11:35:28.279396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 11:35:28.283053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 11:35:28.286092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 11:35:28.292774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6929 11:35:28.296226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6930 11:35:28.299702 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 11:35:28.305973 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6932 11:35:28.306050 Total UI for P1: 0, mck2ui 16
6933 11:35:28.312493 best dqsien dly found for B0: ( 0, 14, 24)
6934 11:35:28.312570 Total UI for P1: 0, mck2ui 16
6935 11:35:28.315547 best dqsien dly found for B1: ( 0, 14, 24)
6936 11:35:28.322764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6937 11:35:28.325774 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6938 11:35:28.325849
6939 11:35:28.329535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6940 11:35:28.332397 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6941 11:35:28.335643 [Gating] SW calibration Done
6942 11:35:28.335718 ==
6943 11:35:28.338644 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 11:35:28.341976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 11:35:28.342053 ==
6946 11:35:28.345490 RX Vref Scan: 0
6947 11:35:28.345564
6948 11:35:28.345622 RX Vref 0 -> 0, step: 1
6949 11:35:28.345676
6950 11:35:28.348447 RX Delay -410 -> 252, step: 16
6951 11:35:28.355194 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6952 11:35:28.358701 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6953 11:35:28.361736 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6954 11:35:28.364878 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6955 11:35:28.371638 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6956 11:35:28.375208 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6957 11:35:28.378536 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6958 11:35:28.381904 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6959 11:35:28.388146 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6960 11:35:28.391578 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6961 11:35:28.394577 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6962 11:35:28.398080 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6963 11:35:28.404914 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6964 11:35:28.407890 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6965 11:35:28.411086 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6966 11:35:28.417740 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6967 11:35:28.417817 ==
6968 11:35:28.421325 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 11:35:28.424715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 11:35:28.424792 ==
6971 11:35:28.424852 DQS Delay:
6972 11:35:28.427672 DQS0 = 51, DQS1 = 51
6973 11:35:28.427751 DQM Delay:
6974 11:35:28.431161 DQM0 = 18, DQM1 = 12
6975 11:35:28.431235 DQ Delay:
6976 11:35:28.434791 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6977 11:35:28.437998 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6978 11:35:28.440907 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6979 11:35:28.444476 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6980 11:35:28.444550
6981 11:35:28.444608
6982 11:35:28.444662 ==
6983 11:35:28.447701 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 11:35:28.451030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 11:35:28.451105 ==
6986 11:35:28.451163
6987 11:35:28.454347
6988 11:35:28.454422 TX Vref Scan disable
6989 11:35:28.457362 == TX Byte 0 ==
6990 11:35:28.460682 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6991 11:35:28.464097 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6992 11:35:28.467567 == TX Byte 1 ==
6993 11:35:28.470674 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6994 11:35:28.473810 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6995 11:35:28.473885 ==
6996 11:35:28.477431 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 11:35:28.480582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 11:35:28.484039 ==
6999 11:35:28.484112
7000 11:35:28.484169
7001 11:35:28.484222 TX Vref Scan disable
7002 11:35:28.487009 == TX Byte 0 ==
7003 11:35:28.490785 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7004 11:35:28.493490 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7005 11:35:28.496782 == TX Byte 1 ==
7006 11:35:28.500285 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7007 11:35:28.503654 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7008 11:35:28.503729
7009 11:35:28.503787 [DATLAT]
7010 11:35:28.506772 Freq=400, CH1 RK1
7011 11:35:28.506849
7012 11:35:28.510408 DATLAT Default: 0xe
7013 11:35:28.510483 0, 0xFFFF, sum = 0
7014 11:35:28.513736 1, 0xFFFF, sum = 0
7015 11:35:28.513856 2, 0xFFFF, sum = 0
7016 11:35:28.516873 3, 0xFFFF, sum = 0
7017 11:35:28.516948 4, 0xFFFF, sum = 0
7018 11:35:28.519952 5, 0xFFFF, sum = 0
7019 11:35:28.520027 6, 0xFFFF, sum = 0
7020 11:35:28.523582 7, 0xFFFF, sum = 0
7021 11:35:28.523666 8, 0xFFFF, sum = 0
7022 11:35:28.526756 9, 0xFFFF, sum = 0
7023 11:35:28.526831 10, 0xFFFF, sum = 0
7024 11:35:28.530212 11, 0xFFFF, sum = 0
7025 11:35:28.530286 12, 0xFFFF, sum = 0
7026 11:35:28.533532 13, 0x0, sum = 1
7027 11:35:28.533607 14, 0x0, sum = 2
7028 11:35:28.536531 15, 0x0, sum = 3
7029 11:35:28.536606 16, 0x0, sum = 4
7030 11:35:28.539916 best_step = 14
7031 11:35:28.539990
7032 11:35:28.540047 ==
7033 11:35:28.543114 Dram Type= 6, Freq= 0, CH_1, rank 1
7034 11:35:28.546244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7035 11:35:28.546319 ==
7036 11:35:28.549741 RX Vref Scan: 0
7037 11:35:28.549813
7038 11:35:28.549871 RX Vref 0 -> 0, step: 1
7039 11:35:28.549973
7040 11:35:28.553217 RX Delay -343 -> 252, step: 8
7041 11:35:28.561138 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
7042 11:35:28.564322 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
7043 11:35:28.568057 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
7044 11:35:28.574494 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7045 11:35:28.577532 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7046 11:35:28.581387 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7047 11:35:28.584361 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7048 11:35:28.590637 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
7049 11:35:28.594134 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7050 11:35:28.597707 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7051 11:35:28.600759 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7052 11:35:28.607317 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7053 11:35:28.610757 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
7054 11:35:28.613756 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7055 11:35:28.617070 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7056 11:35:28.623816 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7057 11:35:28.623891 ==
7058 11:35:28.626957 Dram Type= 6, Freq= 0, CH_1, rank 1
7059 11:35:28.630544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7060 11:35:28.630621 ==
7061 11:35:28.630681 DQS Delay:
7062 11:35:28.633654 DQS0 = 48, DQS1 = 56
7063 11:35:28.633743 DQM Delay:
7064 11:35:28.636689 DQM0 = 11, DQM1 = 11
7065 11:35:28.636764 DQ Delay:
7066 11:35:28.640551 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7067 11:35:28.643554 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7068 11:35:28.646614 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7069 11:35:28.650249 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7070 11:35:28.650324
7071 11:35:28.650382
7072 11:35:28.659722 [DQSOSCAuto] RK1, (LSB)MR18= 0x6757, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7073 11:35:28.659798 CH1 RK1: MR19=C0C, MR18=6757
7074 11:35:28.666569 CH1_RK1: MR19=0xC0C, MR18=0x6757, DQSOSC=396, MR23=63, INC=376, DEC=251
7075 11:35:28.669899 [RxdqsGatingPostProcess] freq 400
7076 11:35:28.676367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7077 11:35:28.679447 best DQS0 dly(2T, 0.5T) = (0, 10)
7078 11:35:28.682794 best DQS1 dly(2T, 0.5T) = (0, 10)
7079 11:35:28.686440 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7080 11:35:28.689670 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7081 11:35:28.692845 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 11:35:28.696220 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 11:35:28.699401 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 11:35:28.702631 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 11:35:28.702730 Pre-setting of DQS Precalculation
7086 11:35:28.709035 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7087 11:35:28.715785 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7088 11:35:28.722441 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7089 11:35:28.722516
7090 11:35:28.722574
7091 11:35:28.726087 [Calibration Summary] 800 Mbps
7092 11:35:28.729006 CH 0, Rank 0
7093 11:35:28.729105 SW Impedance : PASS
7094 11:35:28.732253 DUTY Scan : NO K
7095 11:35:28.735752 ZQ Calibration : PASS
7096 11:35:28.735827 Jitter Meter : NO K
7097 11:35:28.738898 CBT Training : PASS
7098 11:35:28.742408 Write leveling : PASS
7099 11:35:28.742483 RX DQS gating : PASS
7100 11:35:28.745265 RX DQ/DQS(RDDQC) : PASS
7101 11:35:28.749028 TX DQ/DQS : PASS
7102 11:35:28.749103 RX DATLAT : PASS
7103 11:35:28.752181 RX DQ/DQS(Engine): PASS
7104 11:35:28.752256 TX OE : NO K
7105 11:35:28.755241 All Pass.
7106 11:35:28.755315
7107 11:35:28.755373 CH 0, Rank 1
7108 11:35:28.758443 SW Impedance : PASS
7109 11:35:28.762031 DUTY Scan : NO K
7110 11:35:28.762105 ZQ Calibration : PASS
7111 11:35:28.765342 Jitter Meter : NO K
7112 11:35:28.765416 CBT Training : PASS
7113 11:35:28.768852 Write leveling : NO K
7114 11:35:28.772123 RX DQS gating : PASS
7115 11:35:28.772197 RX DQ/DQS(RDDQC) : PASS
7116 11:35:28.775385 TX DQ/DQS : PASS
7117 11:35:28.778304 RX DATLAT : PASS
7118 11:35:28.778382 RX DQ/DQS(Engine): PASS
7119 11:35:28.781584 TX OE : NO K
7120 11:35:28.781660 All Pass.
7121 11:35:28.781718
7122 11:35:28.785022 CH 1, Rank 0
7123 11:35:28.785105 SW Impedance : PASS
7124 11:35:28.788143 DUTY Scan : NO K
7125 11:35:28.791401 ZQ Calibration : PASS
7126 11:35:28.791484 Jitter Meter : NO K
7127 11:35:28.795025 CBT Training : PASS
7128 11:35:28.798360 Write leveling : PASS
7129 11:35:28.798434 RX DQS gating : PASS
7130 11:35:28.801698 RX DQ/DQS(RDDQC) : PASS
7131 11:35:28.805507 TX DQ/DQS : PASS
7132 11:35:28.805580 RX DATLAT : PASS
7133 11:35:28.808065 RX DQ/DQS(Engine): PASS
7134 11:35:28.811461 TX OE : NO K
7135 11:35:28.811550 All Pass.
7136 11:35:28.811609
7137 11:35:28.811663 CH 1, Rank 1
7138 11:35:28.814669 SW Impedance : PASS
7139 11:35:28.817980 DUTY Scan : NO K
7140 11:35:28.818061 ZQ Calibration : PASS
7141 11:35:28.821156 Jitter Meter : NO K
7142 11:35:28.824755 CBT Training : PASS
7143 11:35:28.824829 Write leveling : NO K
7144 11:35:28.828018 RX DQS gating : PASS
7145 11:35:28.831640 RX DQ/DQS(RDDQC) : PASS
7146 11:35:28.831714 TX DQ/DQS : PASS
7147 11:35:28.834665 RX DATLAT : PASS
7148 11:35:28.834739 RX DQ/DQS(Engine): PASS
7149 11:35:28.838006 TX OE : NO K
7150 11:35:28.838080 All Pass.
7151 11:35:28.838138
7152 11:35:28.841111 DramC Write-DBI off
7153 11:35:28.844211 PER_BANK_REFRESH: Hybrid Mode
7154 11:35:28.844285 TX_TRACKING: ON
7155 11:35:28.854118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7156 11:35:28.857433 [FAST_K] Save calibration result to emmc
7157 11:35:28.860586 dramc_set_vcore_voltage set vcore to 725000
7158 11:35:28.864396 Read voltage for 1600, 0
7159 11:35:28.864470 Vio18 = 0
7160 11:35:28.867722 Vcore = 725000
7161 11:35:28.867796 Vdram = 0
7162 11:35:28.867854 Vddq = 0
7163 11:35:28.867907 Vmddr = 0
7164 11:35:28.874180 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7165 11:35:28.880965 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7166 11:35:28.881046 MEM_TYPE=3, freq_sel=13
7167 11:35:28.883776 sv_algorithm_assistance_LP4_3733
7168 11:35:28.890595 ============ PULL DRAM RESETB DOWN ============
7169 11:35:28.894183 ========== PULL DRAM RESETB DOWN end =========
7170 11:35:28.897296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 11:35:28.900476 ===================================
7172 11:35:28.903461 LPDDR4 DRAM CONFIGURATION
7173 11:35:28.906912 ===================================
7174 11:35:28.907021 EX_ROW_EN[0] = 0x0
7175 11:35:28.910035 EX_ROW_EN[1] = 0x0
7176 11:35:28.913337 LP4Y_EN = 0x0
7177 11:35:28.913472 WORK_FSP = 0x1
7178 11:35:28.916801 WL = 0x5
7179 11:35:28.916933 RL = 0x5
7180 11:35:28.920787 BL = 0x2
7181 11:35:28.920971 RPST = 0x0
7182 11:35:28.923397 RD_PRE = 0x0
7183 11:35:28.923640 WR_PRE = 0x1
7184 11:35:28.926604 WR_PST = 0x1
7185 11:35:28.926862 DBI_WR = 0x0
7186 11:35:28.930569 DBI_RD = 0x0
7187 11:35:28.930861 OTF = 0x1
7188 11:35:28.933399 ===================================
7189 11:35:28.936662 ===================================
7190 11:35:28.940471 ANA top config
7191 11:35:28.943515 ===================================
7192 11:35:28.947087 DLL_ASYNC_EN = 0
7193 11:35:28.947492 ALL_SLAVE_EN = 0
7194 11:35:28.950018 NEW_RANK_MODE = 1
7195 11:35:28.953434 DLL_IDLE_MODE = 1
7196 11:35:28.956598 LP45_APHY_COMB_EN = 1
7197 11:35:28.956980 TX_ODT_DIS = 0
7198 11:35:28.960081 NEW_8X_MODE = 1
7199 11:35:28.963194 ===================================
7200 11:35:28.966441 ===================================
7201 11:35:28.969719 data_rate = 3200
7202 11:35:28.973120 CKR = 1
7203 11:35:28.976266 DQ_P2S_RATIO = 8
7204 11:35:28.979650 ===================================
7205 11:35:28.982899 CA_P2S_RATIO = 8
7206 11:35:28.983176 DQ_CA_OPEN = 0
7207 11:35:28.986438 DQ_SEMI_OPEN = 0
7208 11:35:28.989685 CA_SEMI_OPEN = 0
7209 11:35:28.992837 CA_FULL_RATE = 0
7210 11:35:28.996308 DQ_CKDIV4_EN = 0
7211 11:35:28.999538 CA_CKDIV4_EN = 0
7212 11:35:29.002848 CA_PREDIV_EN = 0
7213 11:35:29.003169 PH8_DLY = 12
7214 11:35:29.005736 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7215 11:35:29.009379 DQ_AAMCK_DIV = 4
7216 11:35:29.012531 CA_AAMCK_DIV = 4
7217 11:35:29.016096 CA_ADMCK_DIV = 4
7218 11:35:29.019340 DQ_TRACK_CA_EN = 0
7219 11:35:29.019644 CA_PICK = 1600
7220 11:35:29.022900 CA_MCKIO = 1600
7221 11:35:29.026123 MCKIO_SEMI = 0
7222 11:35:29.029112 PLL_FREQ = 3068
7223 11:35:29.032631 DQ_UI_PI_RATIO = 32
7224 11:35:29.035942 CA_UI_PI_RATIO = 0
7225 11:35:29.038959 ===================================
7226 11:35:29.042392 ===================================
7227 11:35:29.045479 memory_type:LPDDR4
7228 11:35:29.045555 GP_NUM : 10
7229 11:35:29.048605 SRAM_EN : 1
7230 11:35:29.048680 MD32_EN : 0
7231 11:35:29.051956 ===================================
7232 11:35:29.055718 [ANA_INIT] >>>>>>>>>>>>>>
7233 11:35:29.058621 <<<<<< [CONFIGURE PHASE]: ANA_TX
7234 11:35:29.061770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7235 11:35:29.065003 ===================================
7236 11:35:29.068483 data_rate = 3200,PCW = 0X7600
7237 11:35:29.071913 ===================================
7238 11:35:29.074923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7239 11:35:29.081880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7240 11:35:29.084950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7241 11:35:29.091617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7242 11:35:29.094797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7243 11:35:29.097865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7244 11:35:29.097940 [ANA_INIT] flow start
7245 11:35:29.101517 [ANA_INIT] PLL >>>>>>>>
7246 11:35:29.104800 [ANA_INIT] PLL <<<<<<<<
7247 11:35:29.104876 [ANA_INIT] MIDPI >>>>>>>>
7248 11:35:29.107765 [ANA_INIT] MIDPI <<<<<<<<
7249 11:35:29.111200 [ANA_INIT] DLL >>>>>>>>
7250 11:35:29.114768 [ANA_INIT] DLL <<<<<<<<
7251 11:35:29.114843 [ANA_INIT] flow end
7252 11:35:29.117769 ============ LP4 DIFF to SE enter ============
7253 11:35:29.124290 ============ LP4 DIFF to SE exit ============
7254 11:35:29.124366 [ANA_INIT] <<<<<<<<<<<<<
7255 11:35:29.127802 [Flow] Enable top DCM control >>>>>
7256 11:35:29.131243 [Flow] Enable top DCM control <<<<<
7257 11:35:29.134523 Enable DLL master slave shuffle
7258 11:35:29.140910 ==============================================================
7259 11:35:29.140986 Gating Mode config
7260 11:35:29.147235 ==============================================================
7261 11:35:29.150850 Config description:
7262 11:35:29.160576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7263 11:35:29.166970 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7264 11:35:29.170665 SELPH_MODE 0: By rank 1: By Phase
7265 11:35:29.177094 ==============================================================
7266 11:35:29.180092 GAT_TRACK_EN = 1
7267 11:35:29.183388 RX_GATING_MODE = 2
7268 11:35:29.186644 RX_GATING_TRACK_MODE = 2
7269 11:35:29.186718 SELPH_MODE = 1
7270 11:35:29.190159 PICG_EARLY_EN = 1
7271 11:35:29.193456 VALID_LAT_VALUE = 1
7272 11:35:29.200053 ==============================================================
7273 11:35:29.203099 Enter into Gating configuration >>>>
7274 11:35:29.206719 Exit from Gating configuration <<<<
7275 11:35:29.209985 Enter into DVFS_PRE_config >>>>>
7276 11:35:29.220283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7277 11:35:29.222909 Exit from DVFS_PRE_config <<<<<
7278 11:35:29.226037 Enter into PICG configuration >>>>
7279 11:35:29.229872 Exit from PICG configuration <<<<
7280 11:35:29.232794 [RX_INPUT] configuration >>>>>
7281 11:35:29.236271 [RX_INPUT] configuration <<<<<
7282 11:35:29.239500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7283 11:35:29.246212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7284 11:35:29.252689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7285 11:35:29.258873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7286 11:35:29.265644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7287 11:35:29.272351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7288 11:35:29.275693 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7289 11:35:29.278942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7290 11:35:29.281919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7291 11:35:29.288504 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7292 11:35:29.292043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7293 11:35:29.295499 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7294 11:35:29.298606 ===================================
7295 11:35:29.301661 LPDDR4 DRAM CONFIGURATION
7296 11:35:29.305261 ===================================
7297 11:35:29.308940 EX_ROW_EN[0] = 0x0
7298 11:35:29.309015 EX_ROW_EN[1] = 0x0
7299 11:35:29.311811 LP4Y_EN = 0x0
7300 11:35:29.311886 WORK_FSP = 0x1
7301 11:35:29.314760 WL = 0x5
7302 11:35:29.314835 RL = 0x5
7303 11:35:29.318165 BL = 0x2
7304 11:35:29.318240 RPST = 0x0
7305 11:35:29.321687 RD_PRE = 0x0
7306 11:35:29.321761 WR_PRE = 0x1
7307 11:35:29.324777 WR_PST = 0x1
7308 11:35:29.324852 DBI_WR = 0x0
7309 11:35:29.328089 DBI_RD = 0x0
7310 11:35:29.328164 OTF = 0x1
7311 11:35:29.331343 ===================================
7312 11:35:29.338068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7313 11:35:29.341421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7314 11:35:29.344897 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7315 11:35:29.348083 ===================================
7316 11:35:29.351115 LPDDR4 DRAM CONFIGURATION
7317 11:35:29.354589 ===================================
7318 11:35:29.357569 EX_ROW_EN[0] = 0x10
7319 11:35:29.357644 EX_ROW_EN[1] = 0x0
7320 11:35:29.361069 LP4Y_EN = 0x0
7321 11:35:29.361143 WORK_FSP = 0x1
7322 11:35:29.364498 WL = 0x5
7323 11:35:29.364573 RL = 0x5
7324 11:35:29.367646 BL = 0x2
7325 11:35:29.367721 RPST = 0x0
7326 11:35:29.371257 RD_PRE = 0x0
7327 11:35:29.371332 WR_PRE = 0x1
7328 11:35:29.374279 WR_PST = 0x1
7329 11:35:29.374353 DBI_WR = 0x0
7330 11:35:29.378084 DBI_RD = 0x0
7331 11:35:29.378159 OTF = 0x1
7332 11:35:29.380853 ===================================
7333 11:35:29.387826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7334 11:35:29.387939 ==
7335 11:35:29.390667 Dram Type= 6, Freq= 0, CH_0, rank 0
7336 11:35:29.397570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7337 11:35:29.397665 ==
7338 11:35:29.397738 [Duty_Offset_Calibration]
7339 11:35:29.400900 B0:1 B1:-1 CA:0
7340 11:35:29.400978
7341 11:35:29.404175 [DutyScan_Calibration_Flow] k_type=0
7342 11:35:29.413618
7343 11:35:29.413712 ==CLK 0==
7344 11:35:29.416981 Final CLK duty delay cell = 0
7345 11:35:29.420882 [0] MAX Duty = 5124%(X100), DQS PI = 22
7346 11:35:29.423631 [0] MIN Duty = 4907%(X100), DQS PI = 4
7347 11:35:29.426560 [0] AVG Duty = 5015%(X100)
7348 11:35:29.426667
7349 11:35:29.429691 CH0 CLK Duty spec in!! Max-Min= 217%
7350 11:35:29.433232 [DutyScan_Calibration_Flow] ====Done====
7351 11:35:29.433303
7352 11:35:29.436451 [DutyScan_Calibration_Flow] k_type=1
7353 11:35:29.452413
7354 11:35:29.452483 ==DQS 0 ==
7355 11:35:29.455855 Final DQS duty delay cell = -4
7356 11:35:29.459066 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7357 11:35:29.462228 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7358 11:35:29.465869 [-4] AVG Duty = 4906%(X100)
7359 11:35:29.465930
7360 11:35:29.465984 ==DQS 1 ==
7361 11:35:29.469030 Final DQS duty delay cell = 0
7362 11:35:29.472508 [0] MAX Duty = 5156%(X100), DQS PI = 2
7363 11:35:29.475643 [0] MIN Duty = 5000%(X100), DQS PI = 20
7364 11:35:29.479224 [0] AVG Duty = 5078%(X100)
7365 11:35:29.479296
7366 11:35:29.482434 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7367 11:35:29.482515
7368 11:35:29.485575 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7369 11:35:29.488732 [DutyScan_Calibration_Flow] ====Done====
7370 11:35:29.488795
7371 11:35:29.491832 [DutyScan_Calibration_Flow] k_type=3
7372 11:35:29.510391
7373 11:35:29.510493 ==DQM 0 ==
7374 11:35:29.513565 Final DQM duty delay cell = 0
7375 11:35:29.516670 [0] MAX Duty = 5124%(X100), DQS PI = 20
7376 11:35:29.519807 [0] MIN Duty = 4875%(X100), DQS PI = 10
7377 11:35:29.523091 [0] AVG Duty = 4999%(X100)
7378 11:35:29.523194
7379 11:35:29.523277 ==DQM 1 ==
7380 11:35:29.526442 Final DQM duty delay cell = 0
7381 11:35:29.529850 [0] MAX Duty = 5000%(X100), DQS PI = 6
7382 11:35:29.532979 [0] MIN Duty = 4782%(X100), DQS PI = 22
7383 11:35:29.536053 [0] AVG Duty = 4891%(X100)
7384 11:35:29.536123
7385 11:35:29.539688 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7386 11:35:29.539752
7387 11:35:29.543105 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7388 11:35:29.546484 [DutyScan_Calibration_Flow] ====Done====
7389 11:35:29.546577
7390 11:35:29.549366 [DutyScan_Calibration_Flow] k_type=2
7391 11:35:29.566563
7392 11:35:29.566656 ==DQ 0 ==
7393 11:35:29.569586 Final DQ duty delay cell = -4
7394 11:35:29.573150 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7395 11:35:29.576716 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7396 11:35:29.579529 [-4] AVG Duty = 4953%(X100)
7397 11:35:29.579607
7398 11:35:29.579661 ==DQ 1 ==
7399 11:35:29.582542 Final DQ duty delay cell = 0
7400 11:35:29.586344 [0] MAX Duty = 5125%(X100), DQS PI = 46
7401 11:35:29.589178 [0] MIN Duty = 5000%(X100), DQS PI = 34
7402 11:35:29.592956 [0] AVG Duty = 5062%(X100)
7403 11:35:29.593038
7404 11:35:29.596042 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7405 11:35:29.596121
7406 11:35:29.599545 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7407 11:35:29.602986 [DutyScan_Calibration_Flow] ====Done====
7408 11:35:29.603134 ==
7409 11:35:29.606164 Dram Type= 6, Freq= 0, CH_1, rank 0
7410 11:35:29.609524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7411 11:35:29.609624 ==
7412 11:35:29.612600 [Duty_Offset_Calibration]
7413 11:35:29.612698 B0:-1 B1:1 CA:2
7414 11:35:29.612777
7415 11:35:29.616144 [DutyScan_Calibration_Flow] k_type=0
7416 11:35:29.627605
7417 11:35:29.627796 ==CLK 0==
7418 11:35:29.631050 Final CLK duty delay cell = 0
7419 11:35:29.633894 [0] MAX Duty = 5187%(X100), DQS PI = 24
7420 11:35:29.637270 [0] MIN Duty = 4969%(X100), DQS PI = 0
7421 11:35:29.640957 [0] AVG Duty = 5078%(X100)
7422 11:35:29.641243
7423 11:35:29.644132 CH1 CLK Duty spec in!! Max-Min= 218%
7424 11:35:29.646982 [DutyScan_Calibration_Flow] ====Done====
7425 11:35:29.647244
7426 11:35:29.651314 [DutyScan_Calibration_Flow] k_type=1
7427 11:35:29.668063
7428 11:35:29.668593 ==DQS 0 ==
7429 11:35:29.670734 Final DQS duty delay cell = 0
7430 11:35:29.674084 [0] MAX Duty = 5124%(X100), DQS PI = 18
7431 11:35:29.677217 [0] MIN Duty = 4907%(X100), DQS PI = 8
7432 11:35:29.680574 [0] AVG Duty = 5015%(X100)
7433 11:35:29.680995
7434 11:35:29.681317 ==DQS 1 ==
7435 11:35:29.683830 Final DQS duty delay cell = 0
7436 11:35:29.686825 [0] MAX Duty = 5093%(X100), DQS PI = 24
7437 11:35:29.690459 [0] MIN Duty = 4969%(X100), DQS PI = 56
7438 11:35:29.693900 [0] AVG Duty = 5031%(X100)
7439 11:35:29.694433
7440 11:35:29.696678 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7441 11:35:29.697129
7442 11:35:29.700230 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7443 11:35:29.703634 [DutyScan_Calibration_Flow] ====Done====
7444 11:35:29.704054
7445 11:35:29.706761 [DutyScan_Calibration_Flow] k_type=3
7446 11:35:29.724250
7447 11:35:29.724777 ==DQM 0 ==
7448 11:35:29.727595 Final DQM duty delay cell = 0
7449 11:35:29.730735 [0] MAX Duty = 5218%(X100), DQS PI = 34
7450 11:35:29.734101 [0] MIN Duty = 5031%(X100), DQS PI = 6
7451 11:35:29.734522 [0] AVG Duty = 5124%(X100)
7452 11:35:29.738063
7453 11:35:29.738626 ==DQM 1 ==
7454 11:35:29.740935 Final DQM duty delay cell = 0
7455 11:35:29.744177 [0] MAX Duty = 5156%(X100), DQS PI = 6
7456 11:35:29.747761 [0] MIN Duty = 4938%(X100), DQS PI = 42
7457 11:35:29.750609 [0] AVG Duty = 5047%(X100)
7458 11:35:29.750989
7459 11:35:29.754067 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7460 11:35:29.754540
7461 11:35:29.757435 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7462 11:35:29.759958 [DutyScan_Calibration_Flow] ====Done====
7463 11:35:29.760336
7464 11:35:29.763303 [DutyScan_Calibration_Flow] k_type=2
7465 11:35:29.780939
7466 11:35:29.781429 ==DQ 0 ==
7467 11:35:29.784142 Final DQ duty delay cell = 0
7468 11:35:29.787087 [0] MAX Duty = 5187%(X100), DQS PI = 32
7469 11:35:29.790471 [0] MIN Duty = 4906%(X100), DQS PI = 8
7470 11:35:29.790987 [0] AVG Duty = 5046%(X100)
7471 11:35:29.793865
7472 11:35:29.794241 ==DQ 1 ==
7473 11:35:29.797291 Final DQ duty delay cell = 0
7474 11:35:29.800338 [0] MAX Duty = 5156%(X100), DQS PI = 8
7475 11:35:29.804136 [0] MIN Duty = 4969%(X100), DQS PI = 56
7476 11:35:29.804578 [0] AVG Duty = 5062%(X100)
7477 11:35:29.806976
7478 11:35:29.810214 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7479 11:35:29.810592
7480 11:35:29.813459 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7481 11:35:29.816720 [DutyScan_Calibration_Flow] ====Done====
7482 11:35:29.820429 nWR fixed to 30
7483 11:35:29.823779 [ModeRegInit_LP4] CH0 RK0
7484 11:35:29.824155 [ModeRegInit_LP4] CH0 RK1
7485 11:35:29.826583 [ModeRegInit_LP4] CH1 RK0
7486 11:35:29.830019 [ModeRegInit_LP4] CH1 RK1
7487 11:35:29.830458 match AC timing 5
7488 11:35:29.836521 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7489 11:35:29.839620 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7490 11:35:29.843148 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7491 11:35:29.849679 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7492 11:35:29.852897 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7493 11:35:29.853319 [MiockJmeterHQA]
7494 11:35:29.853634
7495 11:35:29.856174 [DramcMiockJmeter] u1RxGatingPI = 0
7496 11:35:29.859935 0 : 4260, 4032
7497 11:35:29.860413 4 : 4253, 4026
7498 11:35:29.863090 8 : 4363, 4137
7499 11:35:29.863636 12 : 4255, 4029
7500 11:35:29.866005 16 : 4252, 4027
7501 11:35:29.866508 20 : 4363, 4137
7502 11:35:29.869239 24 : 4252, 4027
7503 11:35:29.869731 28 : 4253, 4027
7504 11:35:29.870183 32 : 4252, 4027
7505 11:35:29.872887 36 : 4255, 4029
7506 11:35:29.873329 40 : 4253, 4026
7507 11:35:29.876192 44 : 4252, 4027
7508 11:35:29.876683 48 : 4366, 4139
7509 11:35:29.879299 52 : 4252, 4027
7510 11:35:29.879754 56 : 4255, 4029
7511 11:35:29.882508 60 : 4252, 4027
7512 11:35:29.882903 64 : 4363, 4140
7513 11:35:29.883216 68 : 4250, 4027
7514 11:35:29.885975 72 : 4360, 4138
7515 11:35:29.886591 76 : 4250, 4027
7516 11:35:29.889469 80 : 4250, 4027
7517 11:35:29.890045 84 : 4250, 4027
7518 11:35:29.892354 88 : 4252, 4029
7519 11:35:29.892788 92 : 4250, 876
7520 11:35:29.893100 96 : 4253, 0
7521 11:35:29.895949 100 : 4360, 0
7522 11:35:29.896337 104 : 4361, 0
7523 11:35:29.899256 108 : 4363, 0
7524 11:35:29.899818 112 : 4250, 0
7525 11:35:29.900132 116 : 4250, 0
7526 11:35:29.902567 120 : 4363, 0
7527 11:35:29.902954 124 : 4250, 0
7528 11:35:29.905781 128 : 4249, 0
7529 11:35:29.906126 132 : 4250, 0
7530 11:35:29.906192 136 : 4252, 0
7531 11:35:29.909235 140 : 4360, 0
7532 11:35:29.909312 144 : 4250, 0
7533 11:35:29.909372 148 : 4250, 0
7534 11:35:29.912135 152 : 4250, 0
7535 11:35:29.912212 156 : 4361, 0
7536 11:35:29.915327 160 : 4361, 0
7537 11:35:29.915404 164 : 4250, 0
7538 11:35:29.915475 168 : 4250, 0
7539 11:35:29.918580 172 : 4250, 0
7540 11:35:29.918658 176 : 4253, 0
7541 11:35:29.922144 180 : 4250, 0
7542 11:35:29.922221 184 : 4250, 0
7543 11:35:29.922281 188 : 4252, 0
7544 11:35:29.925351 192 : 4361, 0
7545 11:35:29.925455 196 : 4250, 0
7546 11:35:29.928457 200 : 4250, 0
7547 11:35:29.928534 204 : 4250, 0
7548 11:35:29.928593 208 : 4361, 0
7549 11:35:29.932095 212 : 4361, 0
7550 11:35:29.932171 216 : 4250, 0
7551 11:35:29.935280 220 : 4250, 0
7552 11:35:29.935356 224 : 4250, 250
7553 11:35:29.935416 228 : 4250, 3062
7554 11:35:29.938234 232 : 4250, 4027
7555 11:35:29.938311 236 : 4251, 4027
7556 11:35:29.941566 240 : 4250, 4027
7557 11:35:29.941643 244 : 4250, 4027
7558 11:35:29.944944 248 : 4250, 4027
7559 11:35:29.945026 252 : 4252, 4029
7560 11:35:29.948233 256 : 4250, 4027
7561 11:35:29.948323 260 : 4363, 4140
7562 11:35:29.951547 264 : 4361, 4138
7563 11:35:29.951640 268 : 4247, 4024
7564 11:35:29.954724 272 : 4363, 4139
7565 11:35:29.954801 276 : 4360, 4138
7566 11:35:29.958267 280 : 4250, 4027
7567 11:35:29.958344 284 : 4250, 4027
7568 11:35:29.958404 288 : 4252, 4029
7569 11:35:29.961355 292 : 4250, 4027
7570 11:35:29.961432 296 : 4250, 4026
7571 11:35:29.965083 300 : 4250, 4027
7572 11:35:29.965160 304 : 4250, 4027
7573 11:35:29.968165 308 : 4250, 4026
7574 11:35:29.968242 312 : 4360, 4138
7575 11:35:29.971423 316 : 4361, 4138
7576 11:35:29.971507 320 : 4250, 4027
7577 11:35:29.974703 324 : 4363, 4140
7578 11:35:29.974784 328 : 4360, 4138
7579 11:35:29.977934 332 : 4250, 4027
7580 11:35:29.978015 336 : 4250, 3673
7581 11:35:29.981470 340 : 4252, 2161
7582 11:35:29.981547 344 : 4250, 12
7583 11:35:29.981607
7584 11:35:29.984497 MIOCK jitter meter ch=0
7585 11:35:29.984572
7586 11:35:29.988250 1T = (344-92) = 252 dly cells
7587 11:35:29.991438 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7588 11:35:29.991515 ==
7589 11:35:29.994531 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 11:35:30.001109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 11:35:30.001184 ==
7592 11:35:30.004339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 11:35:30.011383 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 11:35:30.014187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 11:35:30.020668 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 11:35:30.028938 [CA 0] Center 43 (13~74) winsize 62
7597 11:35:30.032240 [CA 1] Center 43 (13~73) winsize 61
7598 11:35:30.035696 [CA 2] Center 38 (9~68) winsize 60
7599 11:35:30.038927 [CA 3] Center 38 (9~68) winsize 60
7600 11:35:30.042197 [CA 4] Center 36 (7~66) winsize 60
7601 11:35:30.045132 [CA 5] Center 36 (7~65) winsize 59
7602 11:35:30.045211
7603 11:35:30.048770 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 11:35:30.048845
7605 11:35:30.055256 [CATrainingPosCal] consider 1 rank data
7606 11:35:30.055358 u2DelayCellTimex100 = 258/100 ps
7607 11:35:30.061897 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7608 11:35:30.065249 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7609 11:35:30.068369 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7610 11:35:30.071547 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7611 11:35:30.074779 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7612 11:35:30.078574 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7613 11:35:30.078667
7614 11:35:30.081839 CA PerBit enable=1, Macro0, CA PI delay=36
7615 11:35:30.081936
7616 11:35:30.085214 [CBTSetCACLKResult] CA Dly = 36
7617 11:35:30.088090 CS Dly: 12 (0~43)
7618 11:35:30.091345 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 11:35:30.095650 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 11:35:30.095745 ==
7621 11:35:30.098565 Dram Type= 6, Freq= 0, CH_0, rank 1
7622 11:35:30.104750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:35:30.104855 ==
7624 11:35:30.108146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7625 11:35:30.114445 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7626 11:35:30.118040 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7627 11:35:30.124612 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7628 11:35:30.132053 [CA 0] Center 43 (13~74) winsize 62
7629 11:35:30.135837 [CA 1] Center 44 (14~74) winsize 61
7630 11:35:30.138800 [CA 2] Center 38 (9~68) winsize 60
7631 11:35:30.142208 [CA 3] Center 38 (9~68) winsize 60
7632 11:35:30.145353 [CA 4] Center 36 (7~66) winsize 60
7633 11:35:30.148780 [CA 5] Center 36 (6~66) winsize 61
7634 11:35:30.148882
7635 11:35:30.152054 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7636 11:35:30.152156
7637 11:35:30.159319 [CATrainingPosCal] consider 2 rank data
7638 11:35:30.159489 u2DelayCellTimex100 = 258/100 ps
7639 11:35:30.165558 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7640 11:35:30.168932 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7641 11:35:30.171446 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7642 11:35:30.174916 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7643 11:35:30.178608 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7644 11:35:30.181682 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7645 11:35:30.181856
7646 11:35:30.185209 CA PerBit enable=1, Macro0, CA PI delay=36
7647 11:35:30.185339
7648 11:35:30.188620 [CBTSetCACLKResult] CA Dly = 36
7649 11:35:30.191524 CS Dly: 12 (0~43)
7650 11:35:30.195013 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7651 11:35:30.197924 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7652 11:35:30.198219
7653 11:35:30.201254 ----->DramcWriteLeveling(PI) begin...
7654 11:35:30.201447 ==
7655 11:35:30.204493 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 11:35:30.211170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 11:35:30.211313 ==
7658 11:35:30.215306 Write leveling (Byte 0): 36 => 36
7659 11:35:30.218036 Write leveling (Byte 1): 27 => 27
7660 11:35:30.218282 DramcWriteLeveling(PI) end<-----
7661 11:35:30.221299
7662 11:35:30.221483 ==
7663 11:35:30.224739 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 11:35:30.227930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 11:35:30.228113 ==
7666 11:35:30.231495 [Gating] SW mode calibration
7667 11:35:30.238064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7668 11:35:30.240976 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7669 11:35:30.248055 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 11:35:30.251146 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 11:35:30.254611 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 11:35:30.260880 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7673 11:35:30.264475 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7674 11:35:30.267369 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7675 11:35:30.274441 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7676 11:35:30.277340 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7677 11:35:30.280785 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7678 11:35:30.287452 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 11:35:30.290976 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7680 11:35:30.294608 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7681 11:35:30.300635 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7682 11:35:30.303493 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7683 11:35:30.307125 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
7684 11:35:30.313777 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 11:35:30.316855 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 11:35:30.320916 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 11:35:30.327243 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7688 11:35:30.330551 1 6 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7689 11:35:30.333804 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7690 11:35:30.340317 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7691 11:35:30.343525 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7692 11:35:30.346986 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 11:35:30.353787 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 11:35:30.357110 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 11:35:30.359987 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7696 11:35:30.366666 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7697 11:35:30.370504 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7698 11:35:30.373270 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7699 11:35:30.380162 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7700 11:35:30.383251 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 11:35:30.386718 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 11:35:30.393235 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 11:35:30.396453 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 11:35:30.399943 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 11:35:30.407263 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 11:35:30.410339 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 11:35:30.413242 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 11:35:30.419883 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 11:35:30.423727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 11:35:30.426486 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 11:35:30.433437 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7712 11:35:30.436260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7713 11:35:30.439923 Total UI for P1: 0, mck2ui 16
7714 11:35:30.442886 best dqsien dly found for B0: ( 1, 9, 8)
7715 11:35:30.446447 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7716 11:35:30.452629 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7717 11:35:30.456048 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7718 11:35:30.459494 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7719 11:35:30.463104 Total UI for P1: 0, mck2ui 16
7720 11:35:30.466232 best dqsien dly found for B1: ( 1, 9, 20)
7721 11:35:30.468832 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7722 11:35:30.472045 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7723 11:35:30.472121
7724 11:35:30.478557 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7725 11:35:30.482220 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7726 11:35:30.485245 [Gating] SW calibration Done
7727 11:35:30.485320 ==
7728 11:35:30.488543 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 11:35:30.492074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 11:35:30.492155 ==
7731 11:35:30.492217 RX Vref Scan: 0
7732 11:35:30.492274
7733 11:35:30.495672 RX Vref 0 -> 0, step: 1
7734 11:35:30.496056
7735 11:35:30.499031 RX Delay 0 -> 252, step: 8
7736 11:35:30.502061 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7737 11:35:30.505594 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7738 11:35:30.509168 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7739 11:35:30.515533 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7740 11:35:30.518503 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7741 11:35:30.521939 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7742 11:35:30.525462 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7743 11:35:30.532430 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7744 11:35:30.535196 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7745 11:35:30.538160 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7746 11:35:30.541706 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7747 11:35:30.544801 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7748 11:35:30.551586 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7749 11:35:30.554923 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7750 11:35:30.558152 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7751 11:35:30.561421 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7752 11:35:30.561806 ==
7753 11:35:30.564565 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:35:30.571083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:35:30.571629 ==
7756 11:35:30.571946 DQS Delay:
7757 11:35:30.574906 DQS0 = 0, DQS1 = 0
7758 11:35:30.575292 DQM Delay:
7759 11:35:30.577675 DQM0 = 134, DQM1 = 126
7760 11:35:30.578079 DQ Delay:
7761 11:35:30.582049 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7762 11:35:30.584408 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7763 11:35:30.587516 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7764 11:35:30.590989 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7765 11:35:30.591383
7766 11:35:30.591721
7767 11:35:30.591995 ==
7768 11:35:30.594210 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 11:35:30.600953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 11:35:30.601338 ==
7771 11:35:30.601638
7772 11:35:30.601910
7773 11:35:30.602172 TX Vref Scan disable
7774 11:35:30.604380 == TX Byte 0 ==
7775 11:35:30.607694 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7776 11:35:30.614258 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7777 11:35:30.614641 == TX Byte 1 ==
7778 11:35:30.617683 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7779 11:35:30.624033 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7780 11:35:30.624589 ==
7781 11:35:30.627317 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 11:35:30.630827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 11:35:30.631210 ==
7784 11:35:30.644203
7785 11:35:30.647495 TX Vref early break, caculate TX vref
7786 11:35:30.650678 TX Vref=16, minBit 4, minWin=22, winSum=367
7787 11:35:30.653928 TX Vref=18, minBit 4, minWin=22, winSum=377
7788 11:35:30.656792 TX Vref=20, minBit 1, minWin=23, winSum=390
7789 11:35:30.660724 TX Vref=22, minBit 1, minWin=24, winSum=398
7790 11:35:30.663487 TX Vref=24, minBit 0, minWin=25, winSum=408
7791 11:35:30.670141 TX Vref=26, minBit 0, minWin=25, winSum=414
7792 11:35:30.673991 TX Vref=28, minBit 4, minWin=25, winSum=417
7793 11:35:30.676678 TX Vref=30, minBit 0, minWin=24, winSum=408
7794 11:35:30.679925 TX Vref=32, minBit 0, minWin=24, winSum=399
7795 11:35:30.683214 TX Vref=34, minBit 0, minWin=23, winSum=387
7796 11:35:30.690024 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7797 11:35:30.690469
7798 11:35:30.693931 Final TX Range 0 Vref 28
7799 11:35:30.694314
7800 11:35:30.694610 ==
7801 11:35:30.696866 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 11:35:30.700101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 11:35:30.700525 ==
7804 11:35:30.700894
7805 11:35:30.701198
7806 11:35:30.703254 TX Vref Scan disable
7807 11:35:30.710024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7808 11:35:30.710409 == TX Byte 0 ==
7809 11:35:30.713174 u2DelayCellOfst[0]=18 cells (5 PI)
7810 11:35:30.716186 u2DelayCellOfst[1]=18 cells (5 PI)
7811 11:35:30.719942 u2DelayCellOfst[2]=15 cells (4 PI)
7812 11:35:30.723033 u2DelayCellOfst[3]=18 cells (5 PI)
7813 11:35:30.726250 u2DelayCellOfst[4]=11 cells (3 PI)
7814 11:35:30.729635 u2DelayCellOfst[5]=0 cells (0 PI)
7815 11:35:30.733103 u2DelayCellOfst[6]=22 cells (6 PI)
7816 11:35:30.736326 u2DelayCellOfst[7]=22 cells (6 PI)
7817 11:35:30.739493 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7818 11:35:30.742898 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7819 11:35:30.746220 == TX Byte 1 ==
7820 11:35:30.749233 u2DelayCellOfst[8]=0 cells (0 PI)
7821 11:35:30.752569 u2DelayCellOfst[9]=0 cells (0 PI)
7822 11:35:30.756319 u2DelayCellOfst[10]=7 cells (2 PI)
7823 11:35:30.759524 u2DelayCellOfst[11]=0 cells (0 PI)
7824 11:35:30.760094 u2DelayCellOfst[12]=11 cells (3 PI)
7825 11:35:30.762458 u2DelayCellOfst[13]=11 cells (3 PI)
7826 11:35:30.765925 u2DelayCellOfst[14]=15 cells (4 PI)
7827 11:35:30.769237 u2DelayCellOfst[15]=11 cells (3 PI)
7828 11:35:30.775933 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7829 11:35:30.779024 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7830 11:35:30.779404 DramC Write-DBI on
7831 11:35:30.782339 ==
7832 11:35:30.785718 Dram Type= 6, Freq= 0, CH_0, rank 0
7833 11:35:30.788856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7834 11:35:30.789269 ==
7835 11:35:30.789757
7836 11:35:30.790216
7837 11:35:30.792037 TX Vref Scan disable
7838 11:35:30.792431 == TX Byte 0 ==
7839 11:35:30.798885 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7840 11:35:30.799368 == TX Byte 1 ==
7841 11:35:30.801995 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7842 11:35:30.805993 DramC Write-DBI off
7843 11:35:30.806477
7844 11:35:30.806892 [DATLAT]
7845 11:35:30.808553 Freq=1600, CH0 RK0
7846 11:35:30.808937
7847 11:35:30.809234 DATLAT Default: 0xf
7848 11:35:30.812416 0, 0xFFFF, sum = 0
7849 11:35:30.812867 1, 0xFFFF, sum = 0
7850 11:35:30.815005 2, 0xFFFF, sum = 0
7851 11:35:30.818930 3, 0xFFFF, sum = 0
7852 11:35:30.819317 4, 0xFFFF, sum = 0
7853 11:35:30.821861 5, 0xFFFF, sum = 0
7854 11:35:30.822397 6, 0xFFFF, sum = 0
7855 11:35:30.825440 7, 0xFFFF, sum = 0
7856 11:35:30.825908 8, 0xFFFF, sum = 0
7857 11:35:30.828905 9, 0xFFFF, sum = 0
7858 11:35:30.829292 10, 0xFFFF, sum = 0
7859 11:35:30.832187 11, 0xFFFF, sum = 0
7860 11:35:30.832579 12, 0xFFFF, sum = 0
7861 11:35:30.835234 13, 0xFFFF, sum = 0
7862 11:35:30.835687 14, 0x0, sum = 1
7863 11:35:30.838539 15, 0x0, sum = 2
7864 11:35:30.839070 16, 0x0, sum = 3
7865 11:35:30.841914 17, 0x0, sum = 4
7866 11:35:30.842404 best_step = 15
7867 11:35:30.842832
7868 11:35:30.843253 ==
7869 11:35:30.844720 Dram Type= 6, Freq= 0, CH_0, rank 0
7870 11:35:30.851349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7871 11:35:30.851900 ==
7872 11:35:30.852388 RX Vref Scan: 1
7873 11:35:30.852806
7874 11:35:30.854635 Set Vref Range= 24 -> 127
7875 11:35:30.855105
7876 11:35:30.857925 RX Vref 24 -> 127, step: 1
7877 11:35:30.858226
7878 11:35:30.858438 RX Delay 19 -> 252, step: 4
7879 11:35:30.858634
7880 11:35:30.861173 Set Vref, RX VrefLevel [Byte0]: 24
7881 11:35:30.864579 [Byte1]: 24
7882 11:35:30.868786
7883 11:35:30.869057 Set Vref, RX VrefLevel [Byte0]: 25
7884 11:35:30.872014 [Byte1]: 25
7885 11:35:30.876473
7886 11:35:30.876743 Set Vref, RX VrefLevel [Byte0]: 26
7887 11:35:30.879567 [Byte1]: 26
7888 11:35:30.883971
7889 11:35:30.884241 Set Vref, RX VrefLevel [Byte0]: 27
7890 11:35:30.887250 [Byte1]: 27
7891 11:35:30.891422
7892 11:35:30.891720 Set Vref, RX VrefLevel [Byte0]: 28
7893 11:35:30.894699 [Byte1]: 28
7894 11:35:30.898913
7895 11:35:30.899184 Set Vref, RX VrefLevel [Byte0]: 29
7896 11:35:30.902496 [Byte1]: 29
7897 11:35:30.906772
7898 11:35:30.907146 Set Vref, RX VrefLevel [Byte0]: 30
7899 11:35:30.909959 [Byte1]: 30
7900 11:35:30.913883
7901 11:35:30.914155 Set Vref, RX VrefLevel [Byte0]: 31
7902 11:35:30.917560 [Byte1]: 31
7903 11:35:30.921303
7904 11:35:30.924768 Set Vref, RX VrefLevel [Byte0]: 32
7905 11:35:30.928460 [Byte1]: 32
7906 11:35:30.928732
7907 11:35:30.931854 Set Vref, RX VrefLevel [Byte0]: 33
7908 11:35:30.934940 [Byte1]: 33
7909 11:35:30.935210
7910 11:35:30.938287 Set Vref, RX VrefLevel [Byte0]: 34
7911 11:35:30.941547 [Byte1]: 34
7912 11:35:30.941831
7913 11:35:30.944927 Set Vref, RX VrefLevel [Byte0]: 35
7914 11:35:30.947708 [Byte1]: 35
7915 11:35:30.951864
7916 11:35:30.952226 Set Vref, RX VrefLevel [Byte0]: 36
7917 11:35:30.958196 [Byte1]: 36
7918 11:35:30.958467
7919 11:35:30.961961 Set Vref, RX VrefLevel [Byte0]: 37
7920 11:35:30.964702 [Byte1]: 37
7921 11:35:30.965080
7922 11:35:30.968354 Set Vref, RX VrefLevel [Byte0]: 38
7923 11:35:30.971312 [Byte1]: 38
7924 11:35:30.971678
7925 11:35:30.974879 Set Vref, RX VrefLevel [Byte0]: 39
7926 11:35:30.978235 [Byte1]: 39
7927 11:35:30.982268
7928 11:35:30.982555 Set Vref, RX VrefLevel [Byte0]: 40
7929 11:35:30.985882 [Byte1]: 40
7930 11:35:30.989629
7931 11:35:30.989902 Set Vref, RX VrefLevel [Byte0]: 41
7932 11:35:30.993022 [Byte1]: 41
7933 11:35:30.997176
7934 11:35:30.997542 Set Vref, RX VrefLevel [Byte0]: 42
7935 11:35:31.000818 [Byte1]: 42
7936 11:35:31.004989
7937 11:35:31.005260 Set Vref, RX VrefLevel [Byte0]: 43
7938 11:35:31.008462 [Byte1]: 43
7939 11:35:31.012351
7940 11:35:31.012622 Set Vref, RX VrefLevel [Byte0]: 44
7941 11:35:31.015883 [Byte1]: 44
7942 11:35:31.020080
7943 11:35:31.020353 Set Vref, RX VrefLevel [Byte0]: 45
7944 11:35:31.023390 [Byte1]: 45
7945 11:35:31.027801
7946 11:35:31.028069 Set Vref, RX VrefLevel [Byte0]: 46
7947 11:35:31.031123 [Byte1]: 46
7948 11:35:31.035169
7949 11:35:31.035541 Set Vref, RX VrefLevel [Byte0]: 47
7950 11:35:31.038572 [Byte1]: 47
7951 11:35:31.042761
7952 11:35:31.043066 Set Vref, RX VrefLevel [Byte0]: 48
7953 11:35:31.046007 [Byte1]: 48
7954 11:35:31.050739
7955 11:35:31.051146 Set Vref, RX VrefLevel [Byte0]: 49
7956 11:35:31.053475 [Byte1]: 49
7957 11:35:31.058072
7958 11:35:31.058571 Set Vref, RX VrefLevel [Byte0]: 50
7959 11:35:31.061357 [Byte1]: 50
7960 11:35:31.065652
7961 11:35:31.066030 Set Vref, RX VrefLevel [Byte0]: 51
7962 11:35:31.068762 [Byte1]: 51
7963 11:35:31.073125
7964 11:35:31.073503 Set Vref, RX VrefLevel [Byte0]: 52
7965 11:35:31.076447 [Byte1]: 52
7966 11:35:31.080714
7967 11:35:31.081094 Set Vref, RX VrefLevel [Byte0]: 53
7968 11:35:31.084086 [Byte1]: 53
7969 11:35:31.088400
7970 11:35:31.088920 Set Vref, RX VrefLevel [Byte0]: 54
7971 11:35:31.091496 [Byte1]: 54
7972 11:35:31.095860
7973 11:35:31.096238 Set Vref, RX VrefLevel [Byte0]: 55
7974 11:35:31.098990 [Byte1]: 55
7975 11:35:31.103723
7976 11:35:31.104163 Set Vref, RX VrefLevel [Byte0]: 56
7977 11:35:31.106563 [Byte1]: 56
7978 11:35:31.111017
7979 11:35:31.111398 Set Vref, RX VrefLevel [Byte0]: 57
7980 11:35:31.114029 [Byte1]: 57
7981 11:35:31.118821
7982 11:35:31.119201 Set Vref, RX VrefLevel [Byte0]: 58
7983 11:35:31.121872 [Byte1]: 58
7984 11:35:31.126299
7985 11:35:31.126800 Set Vref, RX VrefLevel [Byte0]: 59
7986 11:35:31.129490 [Byte1]: 59
7987 11:35:31.133932
7988 11:35:31.134340 Set Vref, RX VrefLevel [Byte0]: 60
7989 11:35:31.136700 [Byte1]: 60
7990 11:35:31.141385
7991 11:35:31.141798 Set Vref, RX VrefLevel [Byte0]: 61
7992 11:35:31.144480 [Byte1]: 61
7993 11:35:31.148808
7994 11:35:31.149213 Set Vref, RX VrefLevel [Byte0]: 62
7995 11:35:31.152293 [Byte1]: 62
7996 11:35:31.156684
7997 11:35:31.157149 Set Vref, RX VrefLevel [Byte0]: 63
7998 11:35:31.159833 [Byte1]: 63
7999 11:35:31.164441
8000 11:35:31.164855 Set Vref, RX VrefLevel [Byte0]: 64
8001 11:35:31.167225 [Byte1]: 64
8002 11:35:31.171367
8003 11:35:31.171909 Set Vref, RX VrefLevel [Byte0]: 65
8004 11:35:31.175196 [Byte1]: 65
8005 11:35:31.179207
8006 11:35:31.179777 Set Vref, RX VrefLevel [Byte0]: 66
8007 11:35:31.182398 [Byte1]: 66
8008 11:35:31.186621
8009 11:35:31.187022 Set Vref, RX VrefLevel [Byte0]: 67
8010 11:35:31.189833 [Byte1]: 67
8011 11:35:31.194522
8012 11:35:31.194903 Set Vref, RX VrefLevel [Byte0]: 68
8013 11:35:31.198042 [Byte1]: 68
8014 11:35:31.201980
8015 11:35:31.202362 Set Vref, RX VrefLevel [Byte0]: 69
8016 11:35:31.205171 [Byte1]: 69
8017 11:35:31.209574
8018 11:35:31.210111 Set Vref, RX VrefLevel [Byte0]: 70
8019 11:35:31.212961 [Byte1]: 70
8020 11:35:31.217183
8021 11:35:31.217699 Set Vref, RX VrefLevel [Byte0]: 71
8022 11:35:31.220275 [Byte1]: 71
8023 11:35:31.224163
8024 11:35:31.224238 Set Vref, RX VrefLevel [Byte0]: 72
8025 11:35:31.228124 [Byte1]: 72
8026 11:35:31.231882
8027 11:35:31.231981 Set Vref, RX VrefLevel [Byte0]: 73
8028 11:35:31.235348 [Byte1]: 73
8029 11:35:31.239380
8030 11:35:31.239491 Set Vref, RX VrefLevel [Byte0]: 74
8031 11:35:31.242601 [Byte1]: 74
8032 11:35:31.247286
8033 11:35:31.247360 Set Vref, RX VrefLevel [Byte0]: 75
8034 11:35:31.250516 [Byte1]: 75
8035 11:35:31.254534
8036 11:35:31.254635 Set Vref, RX VrefLevel [Byte0]: 76
8037 11:35:31.257905 [Byte1]: 76
8038 11:35:31.262129
8039 11:35:31.262211 Set Vref, RX VrefLevel [Byte0]: 77
8040 11:35:31.265627 [Byte1]: 77
8041 11:35:31.269535
8042 11:35:31.269657 Set Vref, RX VrefLevel [Byte0]: 78
8043 11:35:31.273064 [Byte1]: 78
8044 11:35:31.277293
8045 11:35:31.277423 Set Vref, RX VrefLevel [Byte0]: 79
8046 11:35:31.280670 [Byte1]: 79
8047 11:35:31.284808
8048 11:35:31.284975 Set Vref, RX VrefLevel [Byte0]: 80
8049 11:35:31.288179 [Byte1]: 80
8050 11:35:31.292590
8051 11:35:31.292728 Final RX Vref Byte 0 = 61 to rank0
8052 11:35:31.296036 Final RX Vref Byte 1 = 58 to rank0
8053 11:35:31.298913 Final RX Vref Byte 0 = 61 to rank1
8054 11:35:31.302507 Final RX Vref Byte 1 = 58 to rank1==
8055 11:35:31.305532 Dram Type= 6, Freq= 0, CH_0, rank 0
8056 11:35:31.312228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 11:35:31.312305 ==
8058 11:35:31.312364 DQS Delay:
8059 11:35:31.315378 DQS0 = 0, DQS1 = 0
8060 11:35:31.315492 DQM Delay:
8061 11:35:31.315551 DQM0 = 132, DQM1 = 123
8062 11:35:31.318672 DQ Delay:
8063 11:35:31.322280 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
8064 11:35:31.325431 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8065 11:35:31.328803 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =116
8066 11:35:31.332155 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8067 11:35:31.332234
8068 11:35:31.332349
8069 11:35:31.332404
8070 11:35:31.335177 [DramC_TX_OE_Calibration] TA2
8071 11:35:31.338687 Original DQ_B0 (3 6) =30, OEN = 27
8072 11:35:31.341769 Original DQ_B1 (3 6) =30, OEN = 27
8073 11:35:31.345454 24, 0x0, End_B0=24 End_B1=24
8074 11:35:31.348537 25, 0x0, End_B0=25 End_B1=25
8075 11:35:31.348667 26, 0x0, End_B0=26 End_B1=26
8076 11:35:31.352144 27, 0x0, End_B0=27 End_B1=27
8077 11:35:31.354993 28, 0x0, End_B0=28 End_B1=28
8078 11:35:31.358965 29, 0x0, End_B0=29 End_B1=29
8079 11:35:31.359359 30, 0x0, End_B0=30 End_B1=30
8080 11:35:31.362192 31, 0x4141, End_B0=30 End_B1=30
8081 11:35:31.365462 Byte0 end_step=30 best_step=27
8082 11:35:31.368955 Byte1 end_step=30 best_step=27
8083 11:35:31.371838 Byte0 TX OE(2T, 0.5T) = (3, 3)
8084 11:35:31.375182 Byte1 TX OE(2T, 0.5T) = (3, 3)
8085 11:35:31.375687
8086 11:35:31.376083
8087 11:35:31.382119 [DQSOSCAuto] RK0, (LSB)MR18= 0x2214, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8088 11:35:31.385272 CH0 RK0: MR19=303, MR18=2214
8089 11:35:31.392119 CH0_RK0: MR19=0x303, MR18=0x2214, DQSOSC=392, MR23=63, INC=24, DEC=16
8090 11:35:31.392502
8091 11:35:31.394748 ----->DramcWriteLeveling(PI) begin...
8092 11:35:31.394824 ==
8093 11:35:31.398030 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 11:35:31.401452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 11:35:31.401526 ==
8096 11:35:31.404798 Write leveling (Byte 0): 35 => 35
8097 11:35:31.408167 Write leveling (Byte 1): 26 => 26
8098 11:35:31.410749 DramcWriteLeveling(PI) end<-----
8099 11:35:31.410844
8100 11:35:31.410937 ==
8101 11:35:31.414120 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 11:35:31.420920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 11:35:31.420995 ==
8104 11:35:31.421076 [Gating] SW mode calibration
8105 11:35:31.430657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8106 11:35:31.434021 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8107 11:35:31.437672 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 11:35:31.443991 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 11:35:31.447718 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 11:35:31.450843 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8111 11:35:31.457506 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8112 11:35:31.460871 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
8113 11:35:31.464203 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 11:35:31.470526 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 11:35:31.473943 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 11:35:31.476975 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 11:35:31.483705 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8118 11:35:31.487372 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8119 11:35:31.490406 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8120 11:35:31.497436 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8121 11:35:31.501005 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 11:35:31.504077 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 11:35:31.510881 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 11:35:31.513855 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 11:35:31.517106 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 11:35:31.523840 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8127 11:35:31.527044 1 6 16 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
8128 11:35:31.530498 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8129 11:35:31.537188 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 11:35:31.540238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 11:35:31.543314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 11:35:31.550610 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 11:35:31.553222 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8134 11:35:31.556977 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8135 11:35:31.563599 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8136 11:35:31.566995 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8137 11:35:31.569923 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 11:35:31.576107 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 11:35:31.579627 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 11:35:31.582832 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 11:35:31.590158 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 11:35:31.592742 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 11:35:31.595912 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 11:35:31.602674 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 11:35:31.605768 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 11:35:31.608966 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 11:35:31.615592 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 11:35:31.619177 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 11:35:31.622556 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 11:35:31.629210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8151 11:35:31.632220 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8152 11:35:31.635558 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 11:35:31.638744 Total UI for P1: 0, mck2ui 16
8154 11:35:31.642014 best dqsien dly found for B0: ( 1, 9, 14)
8155 11:35:31.645488 Total UI for P1: 0, mck2ui 16
8156 11:35:31.648649 best dqsien dly found for B1: ( 1, 9, 18)
8157 11:35:31.652153 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8158 11:35:31.658617 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8159 11:35:31.659007
8160 11:35:31.661770 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8161 11:35:31.665352 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8162 11:35:31.668595 [Gating] SW calibration Done
8163 11:35:31.668981 ==
8164 11:35:31.671898 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:35:31.675485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:35:31.675903 ==
8167 11:35:31.678531 RX Vref Scan: 0
8168 11:35:31.679034
8169 11:35:31.679384 RX Vref 0 -> 0, step: 1
8170 11:35:31.679740
8171 11:35:31.681696 RX Delay 0 -> 252, step: 8
8172 11:35:31.685092 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8173 11:35:31.688545 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8174 11:35:31.695051 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8175 11:35:31.698364 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8176 11:35:31.701491 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8177 11:35:31.705865 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8178 11:35:31.711850 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8179 11:35:31.715162 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8180 11:35:31.718343 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8181 11:35:31.720996 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8182 11:35:31.724773 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8183 11:35:31.731324 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8184 11:35:31.734527 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8185 11:35:31.737877 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8186 11:35:31.740686 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8187 11:35:31.747503 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8188 11:35:31.747996 ==
8189 11:35:31.750958 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:35:31.754056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:35:31.754487 ==
8192 11:35:31.754825 DQS Delay:
8193 11:35:31.757307 DQS0 = 0, DQS1 = 0
8194 11:35:31.757731 DQM Delay:
8195 11:35:31.760941 DQM0 = 133, DQM1 = 129
8196 11:35:31.761497 DQ Delay:
8197 11:35:31.764156 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8198 11:35:31.767613 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8199 11:35:31.770673 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8200 11:35:31.773653 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8201 11:35:31.774080
8202 11:35:31.774412
8203 11:35:31.777513 ==
8204 11:35:31.780934 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 11:35:31.783916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 11:35:31.784344 ==
8207 11:35:31.784714
8208 11:35:31.785067
8209 11:35:31.786948 TX Vref Scan disable
8210 11:35:31.787372 == TX Byte 0 ==
8211 11:35:31.794001 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8212 11:35:31.797119 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8213 11:35:31.797541 == TX Byte 1 ==
8214 11:35:31.803456 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8215 11:35:31.807130 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8216 11:35:31.807703 ==
8217 11:35:31.810120 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 11:35:31.813609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 11:35:31.814089 ==
8220 11:35:31.827745
8221 11:35:31.831174 TX Vref early break, caculate TX vref
8222 11:35:31.834576 TX Vref=16, minBit 3, minWin=22, winSum=375
8223 11:35:31.837652 TX Vref=18, minBit 1, minWin=23, winSum=386
8224 11:35:31.841151 TX Vref=20, minBit 1, minWin=23, winSum=392
8225 11:35:31.844512 TX Vref=22, minBit 3, minWin=24, winSum=402
8226 11:35:31.847282 TX Vref=24, minBit 3, minWin=24, winSum=404
8227 11:35:31.854220 TX Vref=26, minBit 1, minWin=24, winSum=410
8228 11:35:31.857188 TX Vref=28, minBit 0, minWin=24, winSum=409
8229 11:35:31.860581 TX Vref=30, minBit 0, minWin=24, winSum=401
8230 11:35:31.863793 TX Vref=32, minBit 1, minWin=23, winSum=389
8231 11:35:31.867029 TX Vref=34, minBit 1, minWin=23, winSum=383
8232 11:35:31.874593 [TxChooseVref] Worse bit 1, Min win 24, Win sum 410, Final Vref 26
8233 11:35:31.875103
8234 11:35:31.877027 Final TX Range 0 Vref 26
8235 11:35:31.877453
8236 11:35:31.877785 ==
8237 11:35:31.880090 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 11:35:31.883642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 11:35:31.884088 ==
8240 11:35:31.884421
8241 11:35:31.884724
8242 11:35:31.887135 TX Vref Scan disable
8243 11:35:31.893773 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8244 11:35:31.894190 == TX Byte 0 ==
8245 11:35:31.896587 u2DelayCellOfst[0]=15 cells (4 PI)
8246 11:35:31.900183 u2DelayCellOfst[1]=18 cells (5 PI)
8247 11:35:31.903587 u2DelayCellOfst[2]=15 cells (4 PI)
8248 11:35:31.907289 u2DelayCellOfst[3]=15 cells (4 PI)
8249 11:35:31.909950 u2DelayCellOfst[4]=11 cells (3 PI)
8250 11:35:31.913000 u2DelayCellOfst[5]=0 cells (0 PI)
8251 11:35:31.916791 u2DelayCellOfst[6]=22 cells (6 PI)
8252 11:35:31.919722 u2DelayCellOfst[7]=18 cells (5 PI)
8253 11:35:31.922893 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8254 11:35:31.926279 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8255 11:35:31.930098 == TX Byte 1 ==
8256 11:35:31.932798 u2DelayCellOfst[8]=0 cells (0 PI)
8257 11:35:31.936466 u2DelayCellOfst[9]=0 cells (0 PI)
8258 11:35:31.939386 u2DelayCellOfst[10]=7 cells (2 PI)
8259 11:35:31.942933 u2DelayCellOfst[11]=0 cells (0 PI)
8260 11:35:31.946880 u2DelayCellOfst[12]=11 cells (3 PI)
8261 11:35:31.947271 u2DelayCellOfst[13]=11 cells (3 PI)
8262 11:35:31.949528 u2DelayCellOfst[14]=15 cells (4 PI)
8263 11:35:31.952941 u2DelayCellOfst[15]=11 cells (3 PI)
8264 11:35:31.959711 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8265 11:35:31.962910 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8266 11:35:31.963419 DramC Write-DBI on
8267 11:35:31.966133 ==
8268 11:35:31.969428 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 11:35:31.972637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 11:35:31.973148 ==
8271 11:35:31.973489
8272 11:35:31.973792
8273 11:35:31.976007 TX Vref Scan disable
8274 11:35:31.976434 == TX Byte 0 ==
8275 11:35:31.982255 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8276 11:35:31.982729 == TX Byte 1 ==
8277 11:35:31.985802 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8278 11:35:31.988900 DramC Write-DBI off
8279 11:35:31.989323
8280 11:35:31.989738 [DATLAT]
8281 11:35:31.992637 Freq=1600, CH0 RK1
8282 11:35:31.993064
8283 11:35:31.993396 DATLAT Default: 0xf
8284 11:35:31.995862 0, 0xFFFF, sum = 0
8285 11:35:31.996256 1, 0xFFFF, sum = 0
8286 11:35:31.998832 2, 0xFFFF, sum = 0
8287 11:35:32.002271 3, 0xFFFF, sum = 0
8288 11:35:32.002661 4, 0xFFFF, sum = 0
8289 11:35:32.005810 5, 0xFFFF, sum = 0
8290 11:35:32.006198 6, 0xFFFF, sum = 0
8291 11:35:32.008944 7, 0xFFFF, sum = 0
8292 11:35:32.009332 8, 0xFFFF, sum = 0
8293 11:35:32.012094 9, 0xFFFF, sum = 0
8294 11:35:32.012661 10, 0xFFFF, sum = 0
8295 11:35:32.015505 11, 0xFFFF, sum = 0
8296 11:35:32.016026 12, 0xFFFF, sum = 0
8297 11:35:32.019507 13, 0xFFFF, sum = 0
8298 11:35:32.019913 14, 0x0, sum = 1
8299 11:35:32.022534 15, 0x0, sum = 2
8300 11:35:32.022989 16, 0x0, sum = 3
8301 11:35:32.026004 17, 0x0, sum = 4
8302 11:35:32.026463 best_step = 15
8303 11:35:32.026762
8304 11:35:32.027040 ==
8305 11:35:32.028448 Dram Type= 6, Freq= 0, CH_0, rank 1
8306 11:35:32.035148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:35:32.035706 ==
8308 11:35:32.036123 RX Vref Scan: 0
8309 11:35:32.036434
8310 11:35:32.038573 RX Vref 0 -> 0, step: 1
8311 11:35:32.039105
8312 11:35:32.041823 RX Delay 11 -> 252, step: 4
8313 11:35:32.045156 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8314 11:35:32.048346 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8315 11:35:32.054800 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8316 11:35:32.058293 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8317 11:35:32.061483 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8318 11:35:32.064832 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8319 11:35:32.067938 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8320 11:35:32.071530 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8321 11:35:32.078212 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8322 11:35:32.081411 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8323 11:35:32.084492 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8324 11:35:32.087827 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8325 11:35:32.094335 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8326 11:35:32.097861 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8327 11:35:32.101190 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8328 11:35:32.104367 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8329 11:35:32.104752 ==
8330 11:35:32.107157 Dram Type= 6, Freq= 0, CH_0, rank 1
8331 11:35:32.113803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:35:32.113881 ==
8333 11:35:32.113940 DQS Delay:
8334 11:35:32.116858 DQS0 = 0, DQS1 = 0
8335 11:35:32.116932 DQM Delay:
8336 11:35:32.120322 DQM0 = 130, DQM1 = 125
8337 11:35:32.120398 DQ Delay:
8338 11:35:32.123794 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8339 11:35:32.126935 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8340 11:35:32.130042 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8341 11:35:32.133548 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8342 11:35:32.133623
8343 11:35:32.133681
8344 11:35:32.133734
8345 11:35:32.136564 [DramC_TX_OE_Calibration] TA2
8346 11:35:32.140162 Original DQ_B0 (3 6) =30, OEN = 27
8347 11:35:32.143554 Original DQ_B1 (3 6) =30, OEN = 27
8348 11:35:32.146639 24, 0x0, End_B0=24 End_B1=24
8349 11:35:32.150189 25, 0x0, End_B0=25 End_B1=25
8350 11:35:32.150345 26, 0x0, End_B0=26 End_B1=26
8351 11:35:32.153441 27, 0x0, End_B0=27 End_B1=27
8352 11:35:32.156635 28, 0x0, End_B0=28 End_B1=28
8353 11:35:32.160235 29, 0x0, End_B0=29 End_B1=29
8354 11:35:32.160385 30, 0x0, End_B0=30 End_B1=30
8355 11:35:32.163288 31, 0x4545, End_B0=30 End_B1=30
8356 11:35:32.166366 Byte0 end_step=30 best_step=27
8357 11:35:32.169618 Byte1 end_step=30 best_step=27
8358 11:35:32.172890 Byte0 TX OE(2T, 0.5T) = (3, 3)
8359 11:35:32.176455 Byte1 TX OE(2T, 0.5T) = (3, 3)
8360 11:35:32.176547
8361 11:35:32.176607
8362 11:35:32.183234 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8363 11:35:32.186149 CH0 RK1: MR19=303, MR18=1F03
8364 11:35:32.192944 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8365 11:35:32.196017 [RxdqsGatingPostProcess] freq 1600
8366 11:35:32.202613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8367 11:35:32.202690 best DQS0 dly(2T, 0.5T) = (1, 1)
8368 11:35:32.206004 best DQS1 dly(2T, 0.5T) = (1, 1)
8369 11:35:32.209854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8370 11:35:32.212612 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8371 11:35:32.216086 best DQS0 dly(2T, 0.5T) = (1, 1)
8372 11:35:32.219402 best DQS1 dly(2T, 0.5T) = (1, 1)
8373 11:35:32.222742 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8374 11:35:32.225870 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8375 11:35:32.229484 Pre-setting of DQS Precalculation
8376 11:35:32.233042 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8377 11:35:32.233193 ==
8378 11:35:32.235908 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 11:35:32.242451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 11:35:32.242582 ==
8381 11:35:32.246038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8382 11:35:32.252566 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8383 11:35:32.255969 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8384 11:35:32.262481 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8385 11:35:32.270374 [CA 0] Center 41 (12~71) winsize 60
8386 11:35:32.273866 [CA 1] Center 42 (13~72) winsize 60
8387 11:35:32.277090 [CA 2] Center 37 (8~66) winsize 59
8388 11:35:32.280778 [CA 3] Center 36 (7~65) winsize 59
8389 11:35:32.284108 [CA 4] Center 36 (7~66) winsize 60
8390 11:35:32.286784 [CA 5] Center 36 (6~66) winsize 61
8391 11:35:32.287225
8392 11:35:32.290190 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8393 11:35:32.290577
8394 11:35:32.293372 [CATrainingPosCal] consider 1 rank data
8395 11:35:32.296559 u2DelayCellTimex100 = 258/100 ps
8396 11:35:32.303627 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8397 11:35:32.306641 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8398 11:35:32.309992 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8399 11:35:32.313461 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8400 11:35:32.317063 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8401 11:35:32.319836 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8402 11:35:32.320230
8403 11:35:32.323412 CA PerBit enable=1, Macro0, CA PI delay=36
8404 11:35:32.323819
8405 11:35:32.326589 [CBTSetCACLKResult] CA Dly = 36
8406 11:35:32.330008 CS Dly: 9 (0~40)
8407 11:35:32.333482 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8408 11:35:32.336464 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8409 11:35:32.336852 ==
8410 11:35:32.339959 Dram Type= 6, Freq= 0, CH_1, rank 1
8411 11:35:32.346475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 11:35:32.346954 ==
8413 11:35:32.349679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8414 11:35:32.356269 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8415 11:35:32.359526 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8416 11:35:32.366450 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8417 11:35:32.373772 [CA 0] Center 42 (12~72) winsize 61
8418 11:35:32.376943 [CA 1] Center 42 (13~72) winsize 60
8419 11:35:32.380549 [CA 2] Center 37 (8~67) winsize 60
8420 11:35:32.383666 [CA 3] Center 37 (8~66) winsize 59
8421 11:35:32.387032 [CA 4] Center 37 (8~67) winsize 60
8422 11:35:32.390357 [CA 5] Center 36 (7~66) winsize 60
8423 11:35:32.390828
8424 11:35:32.393559 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8425 11:35:32.393956
8426 11:35:32.396738 [CATrainingPosCal] consider 2 rank data
8427 11:35:32.400256 u2DelayCellTimex100 = 258/100 ps
8428 11:35:32.406715 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8429 11:35:32.409711 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8430 11:35:32.413336 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8431 11:35:32.416396 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8432 11:35:32.420022 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8433 11:35:32.423301 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8434 11:35:32.423752
8435 11:35:32.426506 CA PerBit enable=1, Macro0, CA PI delay=36
8436 11:35:32.426887
8437 11:35:32.429651 [CBTSetCACLKResult] CA Dly = 36
8438 11:35:32.432838 CS Dly: 10 (0~43)
8439 11:35:32.436521 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8440 11:35:32.439347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8441 11:35:32.439921
8442 11:35:32.442809 ----->DramcWriteLeveling(PI) begin...
8443 11:35:32.445486 ==
8444 11:35:32.449443 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:35:32.452628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:35:32.453020 ==
8447 11:35:32.456032 Write leveling (Byte 0): 23 => 23
8448 11:35:32.458884 Write leveling (Byte 1): 25 => 25
8449 11:35:32.461924 DramcWriteLeveling(PI) end<-----
8450 11:35:32.462305
8451 11:35:32.462603 ==
8452 11:35:32.465382 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:35:32.468612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:35:32.469024 ==
8455 11:35:32.471982 [Gating] SW mode calibration
8456 11:35:32.478888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8457 11:35:32.485312 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8458 11:35:32.488406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 11:35:32.491679 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 11:35:32.498648 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8461 11:35:32.501974 1 4 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
8462 11:35:32.505008 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 11:35:32.511400 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 11:35:32.514811 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 11:35:32.518137 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 11:35:32.525077 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 11:35:32.528091 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 11:35:32.531412 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8469 11:35:32.537895 1 5 12 | B1->B0 | 2a2a 2424 | 1 0 | (0 1) (1 0)
8470 11:35:32.541183 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8471 11:35:32.544396 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 11:35:32.551082 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 11:35:32.554213 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 11:35:32.558132 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 11:35:32.564558 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 11:35:32.567695 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8477 11:35:32.570915 1 6 12 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
8478 11:35:32.577984 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 11:35:32.581144 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 11:35:32.583963 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 11:35:32.590622 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 11:35:32.593930 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 11:35:32.597633 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 11:35:32.603957 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8485 11:35:32.607233 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8486 11:35:32.610315 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8487 11:35:32.616943 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:35:32.620444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:35:32.623810 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:35:32.630059 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:35:32.633134 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:35:32.636790 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:35:32.643397 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:35:32.646574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 11:35:32.649559 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 11:35:32.656762 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 11:35:32.659641 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 11:35:32.662777 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 11:35:32.669518 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 11:35:32.672545 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8501 11:35:32.675866 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8502 11:35:32.683013 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8503 11:35:32.683088 Total UI for P1: 0, mck2ui 16
8504 11:35:32.689225 best dqsien dly found for B0: ( 1, 9, 10)
8505 11:35:32.689299 Total UI for P1: 0, mck2ui 16
8506 11:35:32.696636 best dqsien dly found for B1: ( 1, 9, 10)
8507 11:35:32.699064 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8508 11:35:32.702299 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8509 11:35:32.702377
8510 11:35:32.705598 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8511 11:35:32.708934 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8512 11:35:32.712561 [Gating] SW calibration Done
8513 11:35:32.712716 ==
8514 11:35:32.715737 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 11:35:32.719150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 11:35:32.719322 ==
8517 11:35:32.722452 RX Vref Scan: 0
8518 11:35:32.722612
8519 11:35:32.722706 RX Vref 0 -> 0, step: 1
8520 11:35:32.726068
8521 11:35:32.726246 RX Delay 0 -> 252, step: 8
8522 11:35:32.728614 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8523 11:35:32.735442 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8524 11:35:32.739116 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8525 11:35:32.742559 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8526 11:35:32.746304 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8527 11:35:32.748846 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8528 11:35:32.755871 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8529 11:35:32.758700 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8530 11:35:32.761976 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8531 11:35:32.765977 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8532 11:35:32.771864 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8533 11:35:32.775350 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8534 11:35:32.778945 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8535 11:35:32.781762 iDelay=208, Bit 13, Center 135 (72 ~ 199) 128
8536 11:35:32.785149 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8537 11:35:32.791762 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8538 11:35:32.792184 ==
8539 11:35:32.795047 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 11:35:32.798531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 11:35:32.798915 ==
8542 11:35:32.799211 DQS Delay:
8543 11:35:32.801717 DQS0 = 0, DQS1 = 0
8544 11:35:32.802097 DQM Delay:
8545 11:35:32.804944 DQM0 = 137, DQM1 = 128
8546 11:35:32.805322 DQ Delay:
8547 11:35:32.807906 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8548 11:35:32.811309 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8549 11:35:32.814841 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8550 11:35:32.822108 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8551 11:35:32.822518
8552 11:35:32.822820
8553 11:35:32.823094 ==
8554 11:35:32.824678 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 11:35:32.827931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 11:35:32.828317 ==
8557 11:35:32.828613
8558 11:35:32.828883
8559 11:35:32.831484 TX Vref Scan disable
8560 11:35:32.831869 == TX Byte 0 ==
8561 11:35:32.837616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8562 11:35:32.841345 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8563 11:35:32.841756 == TX Byte 1 ==
8564 11:35:32.847576 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8565 11:35:32.851041 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8566 11:35:32.851598 ==
8567 11:35:32.854330 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 11:35:32.857515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 11:35:32.857900 ==
8570 11:35:32.871131
8571 11:35:32.874392 TX Vref early break, caculate TX vref
8572 11:35:32.878180 TX Vref=16, minBit 0, minWin=21, winSum=371
8573 11:35:32.881210 TX Vref=18, minBit 0, minWin=23, winSum=386
8574 11:35:32.884263 TX Vref=20, minBit 0, minWin=23, winSum=395
8575 11:35:32.887714 TX Vref=22, minBit 5, minWin=22, winSum=400
8576 11:35:32.890870 TX Vref=24, minBit 0, minWin=24, winSum=417
8577 11:35:32.897267 TX Vref=26, minBit 0, minWin=24, winSum=417
8578 11:35:32.901238 TX Vref=28, minBit 0, minWin=24, winSum=417
8579 11:35:32.904288 TX Vref=30, minBit 5, minWin=24, winSum=413
8580 11:35:32.907198 TX Vref=32, minBit 0, minWin=23, winSum=402
8581 11:35:32.910417 TX Vref=34, minBit 0, minWin=23, winSum=394
8582 11:35:32.917237 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 24
8583 11:35:32.917625
8584 11:35:32.920398 Final TX Range 0 Vref 24
8585 11:35:32.920783
8586 11:35:32.921139 ==
8587 11:35:32.924244 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 11:35:32.927399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 11:35:32.927837 ==
8590 11:35:32.928210
8591 11:35:32.928493
8592 11:35:32.930179 TX Vref Scan disable
8593 11:35:32.937078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8594 11:35:32.937486 == TX Byte 0 ==
8595 11:35:32.940868 u2DelayCellOfst[0]=18 cells (5 PI)
8596 11:35:32.943619 u2DelayCellOfst[1]=15 cells (4 PI)
8597 11:35:32.947001 u2DelayCellOfst[2]=0 cells (0 PI)
8598 11:35:32.950143 u2DelayCellOfst[3]=7 cells (2 PI)
8599 11:35:32.953538 u2DelayCellOfst[4]=11 cells (3 PI)
8600 11:35:32.956834 u2DelayCellOfst[5]=22 cells (6 PI)
8601 11:35:32.960306 u2DelayCellOfst[6]=22 cells (6 PI)
8602 11:35:32.963303 u2DelayCellOfst[7]=7 cells (2 PI)
8603 11:35:32.967161 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8604 11:35:32.970030 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8605 11:35:32.973495 == TX Byte 1 ==
8606 11:35:32.976643 u2DelayCellOfst[8]=0 cells (0 PI)
8607 11:35:32.980173 u2DelayCellOfst[9]=3 cells (1 PI)
8608 11:35:32.980555 u2DelayCellOfst[10]=11 cells (3 PI)
8609 11:35:32.983341 u2DelayCellOfst[11]=3 cells (1 PI)
8610 11:35:32.987032 u2DelayCellOfst[12]=15 cells (4 PI)
8611 11:35:32.990474 u2DelayCellOfst[13]=15 cells (4 PI)
8612 11:35:32.993449 u2DelayCellOfst[14]=18 cells (5 PI)
8613 11:35:32.997039 u2DelayCellOfst[15]=18 cells (5 PI)
8614 11:35:33.003385 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8615 11:35:33.007200 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8616 11:35:33.007716 DramC Write-DBI on
8617 11:35:33.009806 ==
8618 11:35:33.010188 Dram Type= 6, Freq= 0, CH_1, rank 0
8619 11:35:33.016347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8620 11:35:33.016851 ==
8621 11:35:33.017349
8622 11:35:33.017697
8623 11:35:33.019687 TX Vref Scan disable
8624 11:35:33.020066 == TX Byte 0 ==
8625 11:35:33.026373 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8626 11:35:33.026757 == TX Byte 1 ==
8627 11:35:33.029685 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8628 11:35:33.033333 DramC Write-DBI off
8629 11:35:33.033792
8630 11:35:33.034093 [DATLAT]
8631 11:35:33.036348 Freq=1600, CH1 RK0
8632 11:35:33.036728
8633 11:35:33.037024 DATLAT Default: 0xf
8634 11:35:33.039356 0, 0xFFFF, sum = 0
8635 11:35:33.039788 1, 0xFFFF, sum = 0
8636 11:35:33.043503 2, 0xFFFF, sum = 0
8637 11:35:33.043891 3, 0xFFFF, sum = 0
8638 11:35:33.046151 4, 0xFFFF, sum = 0
8639 11:35:33.046537 5, 0xFFFF, sum = 0
8640 11:35:33.049181 6, 0xFFFF, sum = 0
8641 11:35:33.049565 7, 0xFFFF, sum = 0
8642 11:35:33.052938 8, 0xFFFF, sum = 0
8643 11:35:33.053320 9, 0xFFFF, sum = 0
8644 11:35:33.055826 10, 0xFFFF, sum = 0
8645 11:35:33.059292 11, 0xFFFF, sum = 0
8646 11:35:33.059722 12, 0xFFFF, sum = 0
8647 11:35:33.062349 13, 0xFFFF, sum = 0
8648 11:35:33.062748 14, 0x0, sum = 1
8649 11:35:33.065481 15, 0x0, sum = 2
8650 11:35:33.065865 16, 0x0, sum = 3
8651 11:35:33.069338 17, 0x0, sum = 4
8652 11:35:33.069769 best_step = 15
8653 11:35:33.070208
8654 11:35:33.070574 ==
8655 11:35:33.072272 Dram Type= 6, Freq= 0, CH_1, rank 0
8656 11:35:33.076078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8657 11:35:33.076496 ==
8658 11:35:33.078588 RX Vref Scan: 1
8659 11:35:33.078964
8660 11:35:33.082322 Set Vref Range= 24 -> 127
8661 11:35:33.082832
8662 11:35:33.083277 RX Vref 24 -> 127, step: 1
8663 11:35:33.085523
8664 11:35:33.085868 RX Delay 11 -> 252, step: 4
8665 11:35:33.086154
8666 11:35:33.088615 Set Vref, RX VrefLevel [Byte0]: 24
8667 11:35:33.092135 [Byte1]: 24
8668 11:35:33.095639
8669 11:35:33.096036 Set Vref, RX VrefLevel [Byte0]: 25
8670 11:35:33.099000 [Byte1]: 25
8671 11:35:33.103862
8672 11:35:33.104240 Set Vref, RX VrefLevel [Byte0]: 26
8673 11:35:33.106665 [Byte1]: 26
8674 11:35:33.111192
8675 11:35:33.111859 Set Vref, RX VrefLevel [Byte0]: 27
8676 11:35:33.114406 [Byte1]: 27
8677 11:35:33.118899
8678 11:35:33.119276 Set Vref, RX VrefLevel [Byte0]: 28
8679 11:35:33.121792 [Byte1]: 28
8680 11:35:33.126284
8681 11:35:33.126830 Set Vref, RX VrefLevel [Byte0]: 29
8682 11:35:33.129648 [Byte1]: 29
8683 11:35:33.134301
8684 11:35:33.134710 Set Vref, RX VrefLevel [Byte0]: 30
8685 11:35:33.137222 [Byte1]: 30
8686 11:35:33.141288
8687 11:35:33.141667 Set Vref, RX VrefLevel [Byte0]: 31
8688 11:35:33.145118 [Byte1]: 31
8689 11:35:33.148832
8690 11:35:33.149216 Set Vref, RX VrefLevel [Byte0]: 32
8691 11:35:33.152061 [Byte1]: 32
8692 11:35:33.156502
8693 11:35:33.157040 Set Vref, RX VrefLevel [Byte0]: 33
8694 11:35:33.160329 [Byte1]: 33
8695 11:35:33.164125
8696 11:35:33.164521 Set Vref, RX VrefLevel [Byte0]: 34
8697 11:35:33.167708 [Byte1]: 34
8698 11:35:33.171577
8699 11:35:33.171992 Set Vref, RX VrefLevel [Byte0]: 35
8700 11:35:33.175120 [Byte1]: 35
8701 11:35:33.179489
8702 11:35:33.180036 Set Vref, RX VrefLevel [Byte0]: 36
8703 11:35:33.182672 [Byte1]: 36
8704 11:35:33.187036
8705 11:35:33.187420 Set Vref, RX VrefLevel [Byte0]: 37
8706 11:35:33.190733 [Byte1]: 37
8707 11:35:33.194571
8708 11:35:33.195110 Set Vref, RX VrefLevel [Byte0]: 38
8709 11:35:33.197856 [Byte1]: 38
8710 11:35:33.201988
8711 11:35:33.202489 Set Vref, RX VrefLevel [Byte0]: 39
8712 11:35:33.205672 [Byte1]: 39
8713 11:35:33.210138
8714 11:35:33.210520 Set Vref, RX VrefLevel [Byte0]: 40
8715 11:35:33.213436 [Byte1]: 40
8716 11:35:33.217831
8717 11:35:33.218216 Set Vref, RX VrefLevel [Byte0]: 41
8718 11:35:33.220698 [Byte1]: 41
8719 11:35:33.225238
8720 11:35:33.225620 Set Vref, RX VrefLevel [Byte0]: 42
8721 11:35:33.228407 [Byte1]: 42
8722 11:35:33.232653
8723 11:35:33.233165 Set Vref, RX VrefLevel [Byte0]: 43
8724 11:35:33.236247 [Byte1]: 43
8725 11:35:33.240467
8726 11:35:33.240847 Set Vref, RX VrefLevel [Byte0]: 44
8727 11:35:33.243534 [Byte1]: 44
8728 11:35:33.248164
8729 11:35:33.248447 Set Vref, RX VrefLevel [Byte0]: 45
8730 11:35:33.251128 [Byte1]: 45
8731 11:35:33.255272
8732 11:35:33.255551 Set Vref, RX VrefLevel [Byte0]: 46
8733 11:35:33.258947 [Byte1]: 46
8734 11:35:33.262677
8735 11:35:33.262883 Set Vref, RX VrefLevel [Byte0]: 47
8736 11:35:33.266358 [Byte1]: 47
8737 11:35:33.270627
8738 11:35:33.270869 Set Vref, RX VrefLevel [Byte0]: 48
8739 11:35:33.273752 [Byte1]: 48
8740 11:35:33.277836
8741 11:35:33.277910 Set Vref, RX VrefLevel [Byte0]: 49
8742 11:35:33.281304 [Byte1]: 49
8743 11:35:33.285669
8744 11:35:33.285744 Set Vref, RX VrefLevel [Byte0]: 50
8745 11:35:33.288842 [Byte1]: 50
8746 11:35:33.293268
8747 11:35:33.293354 Set Vref, RX VrefLevel [Byte0]: 51
8748 11:35:33.296811 [Byte1]: 51
8749 11:35:33.301269
8750 11:35:33.301361 Set Vref, RX VrefLevel [Byte0]: 52
8751 11:35:33.304749 [Byte1]: 52
8752 11:35:33.308674
8753 11:35:33.308795 Set Vref, RX VrefLevel [Byte0]: 53
8754 11:35:33.311875 [Byte1]: 53
8755 11:35:33.315993
8756 11:35:33.316108 Set Vref, RX VrefLevel [Byte0]: 54
8757 11:35:33.319227 [Byte1]: 54
8758 11:35:33.324185
8759 11:35:33.324582 Set Vref, RX VrefLevel [Byte0]: 55
8760 11:35:33.327291 [Byte1]: 55
8761 11:35:33.331849
8762 11:35:33.332236 Set Vref, RX VrefLevel [Byte0]: 56
8763 11:35:33.334778 [Byte1]: 56
8764 11:35:33.339547
8765 11:35:33.339933 Set Vref, RX VrefLevel [Byte0]: 57
8766 11:35:33.342526 [Byte1]: 57
8767 11:35:33.347113
8768 11:35:33.347538 Set Vref, RX VrefLevel [Byte0]: 58
8769 11:35:33.349971 [Byte1]: 58
8770 11:35:33.354317
8771 11:35:33.354699 Set Vref, RX VrefLevel [Byte0]: 59
8772 11:35:33.358300 [Byte1]: 59
8773 11:35:33.362100
8774 11:35:33.362485 Set Vref, RX VrefLevel [Byte0]: 60
8775 11:35:33.365548 [Byte1]: 60
8776 11:35:33.370121
8777 11:35:33.370520 Set Vref, RX VrefLevel [Byte0]: 61
8778 11:35:33.372877 [Byte1]: 61
8779 11:35:33.377452
8780 11:35:33.377834 Set Vref, RX VrefLevel [Byte0]: 62
8781 11:35:33.380816 [Byte1]: 62
8782 11:35:33.385002
8783 11:35:33.385386 Set Vref, RX VrefLevel [Byte0]: 63
8784 11:35:33.388521 [Byte1]: 63
8785 11:35:33.392538
8786 11:35:33.392920 Set Vref, RX VrefLevel [Byte0]: 64
8787 11:35:33.395795 [Byte1]: 64
8788 11:35:33.400374
8789 11:35:33.400752 Set Vref, RX VrefLevel [Byte0]: 65
8790 11:35:33.403317 [Byte1]: 65
8791 11:35:33.407936
8792 11:35:33.408318 Set Vref, RX VrefLevel [Byte0]: 66
8793 11:35:33.410936 [Byte1]: 66
8794 11:35:33.415379
8795 11:35:33.415809 Set Vref, RX VrefLevel [Byte0]: 67
8796 11:35:33.418480 [Byte1]: 67
8797 11:35:33.423138
8798 11:35:33.423553 Set Vref, RX VrefLevel [Byte0]: 68
8799 11:35:33.426439 [Byte1]: 68
8800 11:35:33.430328
8801 11:35:33.430885 Set Vref, RX VrefLevel [Byte0]: 69
8802 11:35:33.433739 [Byte1]: 69
8803 11:35:33.438083
8804 11:35:33.438454 Set Vref, RX VrefLevel [Byte0]: 70
8805 11:35:33.441427 [Byte1]: 70
8806 11:35:33.445680
8807 11:35:33.446058 Set Vref, RX VrefLevel [Byte0]: 71
8808 11:35:33.449252 [Byte1]: 71
8809 11:35:33.453436
8810 11:35:33.453811 Set Vref, RX VrefLevel [Byte0]: 72
8811 11:35:33.456907 [Byte1]: 72
8812 11:35:33.461024
8813 11:35:33.461401 Set Vref, RX VrefLevel [Byte0]: 73
8814 11:35:33.464463 [Byte1]: 73
8815 11:35:33.468355
8816 11:35:33.468733 Set Vref, RX VrefLevel [Byte0]: 74
8817 11:35:33.472018 [Byte1]: 74
8818 11:35:33.476039
8819 11:35:33.476454 Final RX Vref Byte 0 = 53 to rank0
8820 11:35:33.479481 Final RX Vref Byte 1 = 59 to rank0
8821 11:35:33.482944 Final RX Vref Byte 0 = 53 to rank1
8822 11:35:33.486674 Final RX Vref Byte 1 = 59 to rank1==
8823 11:35:33.489966 Dram Type= 6, Freq= 0, CH_1, rank 0
8824 11:35:33.496000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 11:35:33.496412 ==
8826 11:35:33.496798 DQS Delay:
8827 11:35:33.499495 DQS0 = 0, DQS1 = 0
8828 11:35:33.499890 DQM Delay:
8829 11:35:33.500194 DQM0 = 133, DQM1 = 127
8830 11:35:33.502537 DQ Delay:
8831 11:35:33.505976 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =128
8832 11:35:33.509386 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8833 11:35:33.512500 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8834 11:35:33.515560 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8835 11:35:33.515767
8836 11:35:33.515999
8837 11:35:33.516197
8838 11:35:33.518842 [DramC_TX_OE_Calibration] TA2
8839 11:35:33.522615 Original DQ_B0 (3 6) =30, OEN = 27
8840 11:35:33.525761 Original DQ_B1 (3 6) =30, OEN = 27
8841 11:35:33.528665 24, 0x0, End_B0=24 End_B1=24
8842 11:35:33.531907 25, 0x0, End_B0=25 End_B1=25
8843 11:35:33.532112 26, 0x0, End_B0=26 End_B1=26
8844 11:35:33.535631 27, 0x0, End_B0=27 End_B1=27
8845 11:35:33.538542 28, 0x0, End_B0=28 End_B1=28
8846 11:35:33.542002 29, 0x0, End_B0=29 End_B1=29
8847 11:35:33.542170 30, 0x0, End_B0=30 End_B1=30
8848 11:35:33.545048 31, 0x4141, End_B0=30 End_B1=30
8849 11:35:33.548422 Byte0 end_step=30 best_step=27
8850 11:35:33.551588 Byte1 end_step=30 best_step=27
8851 11:35:33.555300 Byte0 TX OE(2T, 0.5T) = (3, 3)
8852 11:35:33.558411 Byte1 TX OE(2T, 0.5T) = (3, 3)
8853 11:35:33.558626
8854 11:35:33.558813
8855 11:35:33.565260 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8856 11:35:33.568670 CH1 RK0: MR19=303, MR18=1B10
8857 11:35:33.574878 CH1_RK0: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8858 11:35:33.575052
8859 11:35:33.578447 ----->DramcWriteLeveling(PI) begin...
8860 11:35:33.578650 ==
8861 11:35:33.581694 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 11:35:33.584916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 11:35:33.585093 ==
8864 11:35:33.588240 Write leveling (Byte 0): 24 => 24
8865 11:35:33.591412 Write leveling (Byte 1): 27 => 27
8866 11:35:33.594853 DramcWriteLeveling(PI) end<-----
8867 11:35:33.595017
8868 11:35:33.595203 ==
8869 11:35:33.598514 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 11:35:33.601239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 11:35:33.604416 ==
8872 11:35:33.604524 [Gating] SW mode calibration
8873 11:35:33.614377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8874 11:35:33.617853 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8875 11:35:33.621207 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 11:35:33.627902 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 11:35:33.631334 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 11:35:33.634358 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8879 11:35:33.640854 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8880 11:35:33.644250 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 11:35:33.647391 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 11:35:33.653887 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 11:35:33.657020 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 11:35:33.660814 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 11:35:33.667102 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8886 11:35:33.670769 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8887 11:35:33.674166 1 5 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 0)
8888 11:35:33.680458 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 11:35:33.684013 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 11:35:33.686901 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 11:35:33.693666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 11:35:33.697111 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 11:35:33.700247 1 6 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8894 11:35:33.706607 1 6 12 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8895 11:35:33.710515 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 11:35:33.713525 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 11:35:33.719840 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 11:35:33.723241 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 11:35:33.726374 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 11:35:33.732984 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 11:35:33.736813 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8902 11:35:33.740248 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8903 11:35:33.746687 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8904 11:35:33.749672 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 11:35:33.756464 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 11:35:33.759456 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 11:35:33.762542 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 11:35:33.769530 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 11:35:33.773271 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 11:35:33.776321 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 11:35:33.782388 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 11:35:33.785696 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 11:35:33.789008 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 11:35:33.795742 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 11:35:33.798882 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 11:35:33.802143 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 11:35:33.808649 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8918 11:35:33.812140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8919 11:35:33.815458 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8920 11:35:33.818579 Total UI for P1: 0, mck2ui 16
8921 11:35:33.821942 best dqsien dly found for B1: ( 1, 9, 10)
8922 11:35:33.828205 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8923 11:35:33.828585 Total UI for P1: 0, mck2ui 16
8924 11:35:33.834830 best dqsien dly found for B0: ( 1, 9, 12)
8925 11:35:33.838087 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8926 11:35:33.841644 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8927 11:35:33.842085
8928 11:35:33.845130 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8929 11:35:33.848386 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8930 11:35:33.851818 [Gating] SW calibration Done
8931 11:35:33.852199 ==
8932 11:35:33.854852 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 11:35:33.858113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 11:35:33.858496 ==
8935 11:35:33.861413 RX Vref Scan: 0
8936 11:35:33.861791
8937 11:35:33.862088 RX Vref 0 -> 0, step: 1
8938 11:35:33.862361
8939 11:35:33.865031 RX Delay 0 -> 252, step: 8
8940 11:35:33.867919 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8941 11:35:33.874419 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8942 11:35:33.878168 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8943 11:35:33.881181 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8944 11:35:33.884477 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8945 11:35:33.887968 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8946 11:35:33.894038 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8947 11:35:33.898014 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8948 11:35:33.900814 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8949 11:35:33.904019 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8950 11:35:33.911073 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8951 11:35:33.914272 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8952 11:35:33.917148 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8953 11:35:33.920148 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8954 11:35:33.926683 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8955 11:35:33.929768 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8956 11:35:33.929844 ==
8957 11:35:33.933417 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 11:35:33.936409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 11:35:33.936486 ==
8960 11:35:33.936544 DQS Delay:
8961 11:35:33.939881 DQS0 = 0, DQS1 = 0
8962 11:35:33.939956 DQM Delay:
8963 11:35:33.943092 DQM0 = 136, DQM1 = 129
8964 11:35:33.943166 DQ Delay:
8965 11:35:33.946494 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8966 11:35:33.949934 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8967 11:35:33.953052 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8968 11:35:33.959238 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8969 11:35:33.959313
8970 11:35:33.959372
8971 11:35:33.959432 ==
8972 11:35:33.962899 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 11:35:33.965852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 11:35:33.965928 ==
8975 11:35:33.965986
8976 11:35:33.966040
8977 11:35:33.969521 TX Vref Scan disable
8978 11:35:33.969598 == TX Byte 0 ==
8979 11:35:33.975924 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 11:35:33.979361 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 11:35:33.982625 == TX Byte 1 ==
8982 11:35:33.985799 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8983 11:35:33.989070 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8984 11:35:33.989144 ==
8985 11:35:33.992225 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 11:35:33.995877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 11:35:33.998573 ==
8988 11:35:34.010982
8989 11:35:34.014600 TX Vref early break, caculate TX vref
8990 11:35:34.017805 TX Vref=16, minBit 0, minWin=23, winSum=386
8991 11:35:34.021154 TX Vref=18, minBit 0, minWin=23, winSum=396
8992 11:35:34.024464 TX Vref=20, minBit 0, minWin=24, winSum=403
8993 11:35:34.028054 TX Vref=22, minBit 1, minWin=24, winSum=411
8994 11:35:34.030872 TX Vref=24, minBit 5, minWin=25, winSum=422
8995 11:35:34.037432 TX Vref=26, minBit 8, minWin=25, winSum=423
8996 11:35:34.040558 TX Vref=28, minBit 0, minWin=25, winSum=421
8997 11:35:34.044084 TX Vref=30, minBit 0, minWin=25, winSum=420
8998 11:35:34.047309 TX Vref=32, minBit 3, minWin=24, winSum=408
8999 11:35:34.050724 TX Vref=34, minBit 0, minWin=24, winSum=402
9000 11:35:34.057311 TX Vref=36, minBit 5, minWin=23, winSum=388
9001 11:35:34.060796 [TxChooseVref] Worse bit 8, Min win 25, Win sum 423, Final Vref 26
9002 11:35:34.061228
9003 11:35:34.064050 Final TX Range 0 Vref 26
9004 11:35:34.064498
9005 11:35:34.064908 ==
9006 11:35:34.067088 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:35:34.070653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:35:34.074279 ==
9009 11:35:34.074672
9010 11:35:34.074971
9011 11:35:34.075245 TX Vref Scan disable
9012 11:35:34.080840 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9013 11:35:34.081223 == TX Byte 0 ==
9014 11:35:34.084227 u2DelayCellOfst[0]=18 cells (5 PI)
9015 11:35:34.086951 u2DelayCellOfst[1]=11 cells (3 PI)
9016 11:35:34.090562 u2DelayCellOfst[2]=0 cells (0 PI)
9017 11:35:34.093830 u2DelayCellOfst[3]=3 cells (1 PI)
9018 11:35:34.096792 u2DelayCellOfst[4]=7 cells (2 PI)
9019 11:35:34.100310 u2DelayCellOfst[5]=22 cells (6 PI)
9020 11:35:34.103497 u2DelayCellOfst[6]=22 cells (6 PI)
9021 11:35:34.106682 u2DelayCellOfst[7]=3 cells (1 PI)
9022 11:35:34.110255 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9023 11:35:34.113298 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9024 11:35:34.116689 == TX Byte 1 ==
9025 11:35:34.119867 u2DelayCellOfst[8]=0 cells (0 PI)
9026 11:35:34.123399 u2DelayCellOfst[9]=7 cells (2 PI)
9027 11:35:34.126452 u2DelayCellOfst[10]=15 cells (4 PI)
9028 11:35:34.130098 u2DelayCellOfst[11]=7 cells (2 PI)
9029 11:35:34.132855 u2DelayCellOfst[12]=18 cells (5 PI)
9030 11:35:34.136523 u2DelayCellOfst[13]=18 cells (5 PI)
9031 11:35:34.139500 u2DelayCellOfst[14]=18 cells (5 PI)
9032 11:35:34.142726 u2DelayCellOfst[15]=18 cells (5 PI)
9033 11:35:34.146251 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9034 11:35:34.149377 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9035 11:35:34.153008 DramC Write-DBI on
9036 11:35:34.153467 ==
9037 11:35:34.156048 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 11:35:34.159903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 11:35:34.160363 ==
9040 11:35:34.160682
9041 11:35:34.161036
9042 11:35:34.162508 TX Vref Scan disable
9043 11:35:34.165639 == TX Byte 0 ==
9044 11:35:34.169361 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9045 11:35:34.169749 == TX Byte 1 ==
9046 11:35:34.176261 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9047 11:35:34.176797 DramC Write-DBI off
9048 11:35:34.177121
9049 11:35:34.177445 [DATLAT]
9050 11:35:34.179039 Freq=1600, CH1 RK1
9051 11:35:34.179418
9052 11:35:34.182833 DATLAT Default: 0xf
9053 11:35:34.183211 0, 0xFFFF, sum = 0
9054 11:35:34.185861 1, 0xFFFF, sum = 0
9055 11:35:34.186242 2, 0xFFFF, sum = 0
9056 11:35:34.189144 3, 0xFFFF, sum = 0
9057 11:35:34.189626 4, 0xFFFF, sum = 0
9058 11:35:34.192372 5, 0xFFFF, sum = 0
9059 11:35:34.192858 6, 0xFFFF, sum = 0
9060 11:35:34.195533 7, 0xFFFF, sum = 0
9061 11:35:34.196035 8, 0xFFFF, sum = 0
9062 11:35:34.199104 9, 0xFFFF, sum = 0
9063 11:35:34.199542 10, 0xFFFF, sum = 0
9064 11:35:34.202033 11, 0xFFFF, sum = 0
9065 11:35:34.202421 12, 0xFFFF, sum = 0
9066 11:35:34.205848 13, 0xFFFF, sum = 0
9067 11:35:34.206236 14, 0x0, sum = 1
9068 11:35:34.208843 15, 0x0, sum = 2
9069 11:35:34.209229 16, 0x0, sum = 3
9070 11:35:34.212777 17, 0x0, sum = 4
9071 11:35:34.213190 best_step = 15
9072 11:35:34.213499
9073 11:35:34.213776 ==
9074 11:35:34.215585 Dram Type= 6, Freq= 0, CH_1, rank 1
9075 11:35:34.222450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9076 11:35:34.222838 ==
9077 11:35:34.223139 RX Vref Scan: 0
9078 11:35:34.223414
9079 11:35:34.225500 RX Vref 0 -> 0, step: 1
9080 11:35:34.225878
9081 11:35:34.229298 RX Delay 11 -> 252, step: 4
9082 11:35:34.231956 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9083 11:35:34.235517 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9084 11:35:34.242408 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9085 11:35:34.245268 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9086 11:35:34.248599 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9087 11:35:34.251872 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9088 11:35:34.255761 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9089 11:35:34.261550 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9090 11:35:34.264851 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9091 11:35:34.268695 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9092 11:35:34.271883 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9093 11:35:34.274843 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9094 11:35:34.281519 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9095 11:35:34.285030 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9096 11:35:34.288442 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9097 11:35:34.291818 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9098 11:35:34.292198 ==
9099 11:35:34.294565 Dram Type= 6, Freq= 0, CH_1, rank 1
9100 11:35:34.301213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9101 11:35:34.301600 ==
9102 11:35:34.301901 DQS Delay:
9103 11:35:34.304878 DQS0 = 0, DQS1 = 0
9104 11:35:34.305257 DQM Delay:
9105 11:35:34.308140 DQM0 = 134, DQM1 = 126
9106 11:35:34.308520 DQ Delay:
9107 11:35:34.311407 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9108 11:35:34.314364 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9109 11:35:34.317766 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9110 11:35:34.320947 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9111 11:35:34.321348
9112 11:35:34.321649
9113 11:35:34.321923
9114 11:35:34.324365 [DramC_TX_OE_Calibration] TA2
9115 11:35:34.327945 Original DQ_B0 (3 6) =30, OEN = 27
9116 11:35:34.330911 Original DQ_B1 (3 6) =30, OEN = 27
9117 11:35:34.334536 24, 0x0, End_B0=24 End_B1=24
9118 11:35:34.337676 25, 0x0, End_B0=25 End_B1=25
9119 11:35:34.338065 26, 0x0, End_B0=26 End_B1=26
9120 11:35:34.340628 27, 0x0, End_B0=27 End_B1=27
9121 11:35:34.344079 28, 0x0, End_B0=28 End_B1=28
9122 11:35:34.347561 29, 0x0, End_B0=29 End_B1=29
9123 11:35:34.347952 30, 0x0, End_B0=30 End_B1=30
9124 11:35:34.351099 31, 0x4545, End_B0=30 End_B1=30
9125 11:35:34.354042 Byte0 end_step=30 best_step=27
9126 11:35:34.357884 Byte1 end_step=30 best_step=27
9127 11:35:34.360853 Byte0 TX OE(2T, 0.5T) = (3, 3)
9128 11:35:34.364138 Byte1 TX OE(2T, 0.5T) = (3, 3)
9129 11:35:34.364519
9130 11:35:34.364817
9131 11:35:34.370824 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9132 11:35:34.373846 CH1 RK1: MR19=303, MR18=B07
9133 11:35:34.380660 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9134 11:35:34.383883 [RxdqsGatingPostProcess] freq 1600
9135 11:35:34.387117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9136 11:35:34.391316 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 11:35:34.393513 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 11:35:34.397270 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 11:35:34.400049 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 11:35:34.403545 best DQS0 dly(2T, 0.5T) = (1, 1)
9141 11:35:34.407197 best DQS1 dly(2T, 0.5T) = (1, 1)
9142 11:35:34.409921 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9143 11:35:34.413471 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9144 11:35:34.417295 Pre-setting of DQS Precalculation
9145 11:35:34.419997 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9146 11:35:34.430116 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9147 11:35:34.436594 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9148 11:35:34.437008
9149 11:35:34.437305
9150 11:35:34.439663 [Calibration Summary] 3200 Mbps
9151 11:35:34.440101 CH 0, Rank 0
9152 11:35:34.442950 SW Impedance : PASS
9153 11:35:34.443330 DUTY Scan : NO K
9154 11:35:34.446965 ZQ Calibration : PASS
9155 11:35:34.450038 Jitter Meter : NO K
9156 11:35:34.450437 CBT Training : PASS
9157 11:35:34.453454 Write leveling : PASS
9158 11:35:34.456636 RX DQS gating : PASS
9159 11:35:34.457056 RX DQ/DQS(RDDQC) : PASS
9160 11:35:34.459745 TX DQ/DQS : PASS
9161 11:35:34.462881 RX DATLAT : PASS
9162 11:35:34.463259 RX DQ/DQS(Engine): PASS
9163 11:35:34.466713 TX OE : PASS
9164 11:35:34.467200 All Pass.
9165 11:35:34.467552
9166 11:35:34.470093 CH 0, Rank 1
9167 11:35:34.470565 SW Impedance : PASS
9168 11:35:34.472878 DUTY Scan : NO K
9169 11:35:34.475904 ZQ Calibration : PASS
9170 11:35:34.476287 Jitter Meter : NO K
9171 11:35:34.479904 CBT Training : PASS
9172 11:35:34.482666 Write leveling : PASS
9173 11:35:34.483048 RX DQS gating : PASS
9174 11:35:34.486273 RX DQ/DQS(RDDQC) : PASS
9175 11:35:34.486653 TX DQ/DQS : PASS
9176 11:35:34.489382 RX DATLAT : PASS
9177 11:35:34.492455 RX DQ/DQS(Engine): PASS
9178 11:35:34.492847 TX OE : PASS
9179 11:35:34.496135 All Pass.
9180 11:35:34.496566
9181 11:35:34.496871 CH 1, Rank 0
9182 11:35:34.499044 SW Impedance : PASS
9183 11:35:34.499473 DUTY Scan : NO K
9184 11:35:34.502937 ZQ Calibration : PASS
9185 11:35:34.505747 Jitter Meter : NO K
9186 11:35:34.506336 CBT Training : PASS
9187 11:35:34.508986 Write leveling : PASS
9188 11:35:34.511935 RX DQS gating : PASS
9189 11:35:34.512454 RX DQ/DQS(RDDQC) : PASS
9190 11:35:34.515305 TX DQ/DQS : PASS
9191 11:35:34.519071 RX DATLAT : PASS
9192 11:35:34.519653 RX DQ/DQS(Engine): PASS
9193 11:35:34.522158 TX OE : PASS
9194 11:35:34.522754 All Pass.
9195 11:35:34.523256
9196 11:35:34.525496 CH 1, Rank 1
9197 11:35:34.525897 SW Impedance : PASS
9198 11:35:34.528819 DUTY Scan : NO K
9199 11:35:34.532054 ZQ Calibration : PASS
9200 11:35:34.532628 Jitter Meter : NO K
9201 11:35:34.535103 CBT Training : PASS
9202 11:35:34.538523 Write leveling : PASS
9203 11:35:34.538901 RX DQS gating : PASS
9204 11:35:34.541957 RX DQ/DQS(RDDQC) : PASS
9205 11:35:34.545158 TX DQ/DQS : PASS
9206 11:35:34.545539 RX DATLAT : PASS
9207 11:35:34.548464 RX DQ/DQS(Engine): PASS
9208 11:35:34.551705 TX OE : PASS
9209 11:35:34.552086 All Pass.
9210 11:35:34.552386
9211 11:35:34.552658 DramC Write-DBI on
9212 11:35:34.554948 PER_BANK_REFRESH: Hybrid Mode
9213 11:35:34.558784 TX_TRACKING: ON
9214 11:35:34.564967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9215 11:35:34.575111 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9216 11:35:34.581691 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9217 11:35:34.584923 [FAST_K] Save calibration result to emmc
9218 11:35:34.587916 sync common calibartion params.
9219 11:35:34.591452 sync cbt_mode0:1, 1:1
9220 11:35:34.591879 dram_init: ddr_geometry: 2
9221 11:35:34.594811 dram_init: ddr_geometry: 2
9222 11:35:34.597850 dram_init: ddr_geometry: 2
9223 11:35:34.602191 0:dram_rank_size:100000000
9224 11:35:34.602693 1:dram_rank_size:100000000
9225 11:35:34.608098 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9226 11:35:34.611352 DFS_SHUFFLE_HW_MODE: ON
9227 11:35:34.614483 dramc_set_vcore_voltage set vcore to 725000
9228 11:35:34.617807 Read voltage for 1600, 0
9229 11:35:34.618298 Vio18 = 0
9230 11:35:34.618637 Vcore = 725000
9231 11:35:34.621028 Vdram = 0
9232 11:35:34.621448 Vddq = 0
9233 11:35:34.621773 Vmddr = 0
9234 11:35:34.624386 switch to 3200 Mbps bootup
9235 11:35:34.624841 [DramcRunTimeConfig]
9236 11:35:34.627814 PHYPLL
9237 11:35:34.628310 DPM_CONTROL_AFTERK: ON
9238 11:35:34.630778 PER_BANK_REFRESH: ON
9239 11:35:34.634143 REFRESH_OVERHEAD_REDUCTION: ON
9240 11:35:34.634566 CMD_PICG_NEW_MODE: OFF
9241 11:35:34.637677 XRTWTW_NEW_MODE: ON
9242 11:35:34.638179 XRTRTR_NEW_MODE: ON
9243 11:35:34.640795 TX_TRACKING: ON
9244 11:35:34.641253 RDSEL_TRACKING: OFF
9245 11:35:34.644432 DQS Precalculation for DVFS: ON
9246 11:35:34.647383 RX_TRACKING: OFF
9247 11:35:34.647873 HW_GATING DBG: ON
9248 11:35:34.650907 ZQCS_ENABLE_LP4: ON
9249 11:35:34.651372 RX_PICG_NEW_MODE: ON
9250 11:35:34.654120 TX_PICG_NEW_MODE: ON
9251 11:35:34.654541 ENABLE_RX_DCM_DPHY: ON
9252 11:35:34.657674 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9253 11:35:34.660437 DUMMY_READ_FOR_TRACKING: OFF
9254 11:35:34.663721 !!! SPM_CONTROL_AFTERK: OFF
9255 11:35:34.667106 !!! SPM could not control APHY
9256 11:35:34.667618 IMPEDANCE_TRACKING: ON
9257 11:35:34.670428 TEMP_SENSOR: ON
9258 11:35:34.670915 HW_SAVE_FOR_SR: OFF
9259 11:35:34.674228 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9260 11:35:34.677218 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9261 11:35:34.680319 Read ODT Tracking: ON
9262 11:35:34.683841 Refresh Rate DeBounce: ON
9263 11:35:34.684497 DFS_NO_QUEUE_FLUSH: ON
9264 11:35:34.686679 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9265 11:35:34.690447 ENABLE_DFS_RUNTIME_MRW: OFF
9266 11:35:34.693329 DDR_RESERVE_NEW_MODE: ON
9267 11:35:34.693713 MR_CBT_SWITCH_FREQ: ON
9268 11:35:34.697009 =========================
9269 11:35:34.715809 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9270 11:35:34.719205 dram_init: ddr_geometry: 2
9271 11:35:34.737556 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9272 11:35:34.740764 dram_init: dram init end (result: 0)
9273 11:35:34.747908 DRAM-K: Full calibration passed in 24656 msecs
9274 11:35:34.750719 MRC: failed to locate region type 0.
9275 11:35:34.751099 DRAM rank0 size:0x100000000,
9276 11:35:34.753977 DRAM rank1 size=0x100000000
9277 11:35:34.763572 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9278 11:35:34.770323 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9279 11:35:34.776938 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9280 11:35:34.787220 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9281 11:35:34.787886 DRAM rank0 size:0x100000000,
9282 11:35:34.790364 DRAM rank1 size=0x100000000
9283 11:35:34.790757 CBMEM:
9284 11:35:34.793164 IMD: root @ 0xfffff000 254 entries.
9285 11:35:34.796635 IMD: root @ 0xffffec00 62 entries.
9286 11:35:34.800033 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9287 11:35:34.806926 WARNING: RO_VPD is uninitialized or empty.
9288 11:35:34.810155 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9289 11:35:34.818024 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9290 11:35:34.830408 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9291 11:35:34.841660 BS: romstage times (exec / console): total (unknown) / 24144 ms
9292 11:35:34.842181
9293 11:35:34.842527
9294 11:35:34.851577 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9295 11:35:34.855131 ARM64: Exception handlers installed.
9296 11:35:34.858280 ARM64: Testing exception
9297 11:35:34.861619 ARM64: Done test exception
9298 11:35:34.862135 Enumerating buses...
9299 11:35:34.865126 Show all devs... Before device enumeration.
9300 11:35:34.868140 Root Device: enabled 1
9301 11:35:34.871771 CPU_CLUSTER: 0: enabled 1
9302 11:35:34.872290 CPU: 00: enabled 1
9303 11:35:34.875115 Compare with tree...
9304 11:35:34.875579 Root Device: enabled 1
9305 11:35:34.877978 CPU_CLUSTER: 0: enabled 1
9306 11:35:34.881434 CPU: 00: enabled 1
9307 11:35:34.881854 Root Device scanning...
9308 11:35:34.884904 scan_static_bus for Root Device
9309 11:35:34.887781 CPU_CLUSTER: 0 enabled
9310 11:35:34.891105 scan_static_bus for Root Device done
9311 11:35:34.894482 scan_bus: bus Root Device finished in 8 msecs
9312 11:35:34.894895 done
9313 11:35:34.901158 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9314 11:35:34.904335 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9315 11:35:34.910665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9316 11:35:34.917277 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9317 11:35:34.917723 Allocating resources...
9318 11:35:34.920314 Reading resources...
9319 11:35:34.924023 Root Device read_resources bus 0 link: 0
9320 11:35:34.927152 DRAM rank0 size:0x100000000,
9321 11:35:34.927602 DRAM rank1 size=0x100000000
9322 11:35:34.933618 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9323 11:35:34.934039 CPU: 00 missing read_resources
9324 11:35:34.940314 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9325 11:35:34.943715 Root Device read_resources bus 0 link: 0 done
9326 11:35:34.946551 Done reading resources.
9327 11:35:34.950001 Show resources in subtree (Root Device)...After reading.
9328 11:35:34.953751 Root Device child on link 0 CPU_CLUSTER: 0
9329 11:35:34.957095 CPU_CLUSTER: 0 child on link 0 CPU: 00
9330 11:35:34.966648 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9331 11:35:34.967114 CPU: 00
9332 11:35:34.973306 Root Device assign_resources, bus 0 link: 0
9333 11:35:34.976563 CPU_CLUSTER: 0 missing set_resources
9334 11:35:34.979808 Root Device assign_resources, bus 0 link: 0 done
9335 11:35:34.983278 Done setting resources.
9336 11:35:34.986141 Show resources in subtree (Root Device)...After assigning values.
9337 11:35:34.992829 Root Device child on link 0 CPU_CLUSTER: 0
9338 11:35:34.996110 CPU_CLUSTER: 0 child on link 0 CPU: 00
9339 11:35:35.003021 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9340 11:35:35.006108 CPU: 00
9341 11:35:35.006487 Done allocating resources.
9342 11:35:35.012699 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9343 11:35:35.015738 Enabling resources...
9344 11:35:35.016112 done.
9345 11:35:35.019554 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9346 11:35:35.022639 Initializing devices...
9347 11:35:35.023015 Root Device init
9348 11:35:35.025822 init hardware done!
9349 11:35:35.029677 0x00000018: ctrlr->caps
9350 11:35:35.030138 52.000 MHz: ctrlr->f_max
9351 11:35:35.032156 0.400 MHz: ctrlr->f_min
9352 11:35:35.035800 0x40ff8080: ctrlr->voltages
9353 11:35:35.036187 sclk: 390625
9354 11:35:35.036486 Bus Width = 1
9355 11:35:35.039509 sclk: 390625
9356 11:35:35.039964 Bus Width = 1
9357 11:35:35.042550 Early init status = 3
9358 11:35:35.045501 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9359 11:35:35.049110 in-header: 03 fc 00 00 01 00 00 00
9360 11:35:35.052260 in-data: 00
9361 11:35:35.055356 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9362 11:35:35.060188 in-header: 03 fd 00 00 00 00 00 00
9363 11:35:35.063672 in-data:
9364 11:35:35.067230 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9365 11:35:35.070597 in-header: 03 fc 00 00 01 00 00 00
9366 11:35:35.074045 in-data: 00
9367 11:35:35.077030 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9368 11:35:35.083161 in-header: 03 fd 00 00 00 00 00 00
9369 11:35:35.086404 in-data:
9370 11:35:35.089454 [SSUSB] Setting up USB HOST controller...
9371 11:35:35.092483 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9372 11:35:35.096144 [SSUSB] phy power-on done.
9373 11:35:35.099046 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9374 11:35:35.105903 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9375 11:35:35.109260 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9376 11:35:35.115608 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9377 11:35:35.122473 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9378 11:35:35.129111 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9379 11:35:35.135774 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9380 11:35:35.142240 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9381 11:35:35.145631 SPM: binary array size = 0x9dc
9382 11:35:35.148835 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9383 11:35:35.155021 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9384 11:35:35.162105 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9385 11:35:35.168702 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9386 11:35:35.171610 configure_display: Starting display init
9387 11:35:35.205853 anx7625_power_on_init: Init interface.
9388 11:35:35.209310 anx7625_disable_pd_protocol: Disabled PD feature.
9389 11:35:35.212660 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9390 11:35:35.240233 anx7625_start_dp_work: Secure OCM version=00
9391 11:35:35.243745 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9392 11:35:35.258508 sp_tx_get_edid_block: EDID Block = 1
9393 11:35:35.361115 Extracted contents:
9394 11:35:35.364468 header: 00 ff ff ff ff ff ff 00
9395 11:35:35.368094 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9396 11:35:35.370982 version: 01 04
9397 11:35:35.374401 basic params: 95 1f 11 78 0a
9398 11:35:35.377389 chroma info: 76 90 94 55 54 90 27 21 50 54
9399 11:35:35.380824 established: 00 00 00
9400 11:35:35.387273 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9401 11:35:35.390670 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9402 11:35:35.397294 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 11:35:35.403855 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9404 11:35:35.410979 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9405 11:35:35.413799 extensions: 00
9406 11:35:35.414175 checksum: fb
9407 11:35:35.414470
9408 11:35:35.419932 Manufacturer: IVO Model 57d Serial Number 0
9409 11:35:35.420309 Made week 0 of 2020
9410 11:35:35.423779 EDID version: 1.4
9411 11:35:35.424234 Digital display
9412 11:35:35.427196 6 bits per primary color channel
9413 11:35:35.427695 DisplayPort interface
9414 11:35:35.430485 Maximum image size: 31 cm x 17 cm
9415 11:35:35.433734 Gamma: 220%
9416 11:35:35.434149 Check DPMS levels
9417 11:35:35.440037 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9418 11:35:35.443207 First detailed timing is preferred timing
9419 11:35:35.443710 Established timings supported:
9420 11:35:35.446520 Standard timings supported:
9421 11:35:35.449627 Detailed timings
9422 11:35:35.453459 Hex of detail: 383680a07038204018303c0035ae10000019
9423 11:35:35.459830 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9424 11:35:35.463349 0780 0798 07c8 0820 hborder 0
9425 11:35:35.466371 0438 043b 0447 0458 vborder 0
9426 11:35:35.469599 -hsync -vsync
9427 11:35:35.469980 Did detailed timing
9428 11:35:35.476129 Hex of detail: 000000000000000000000000000000000000
9429 11:35:35.479717 Manufacturer-specified data, tag 0
9430 11:35:35.482991 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9431 11:35:35.486058 ASCII string: InfoVision
9432 11:35:35.489354 Hex of detail: 000000fe00523134304e574635205248200a
9433 11:35:35.492961 ASCII string: R140NWF5 RH
9434 11:35:35.493368 Checksum
9435 11:35:35.496275 Checksum: 0xfb (valid)
9436 11:35:35.499478 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9437 11:35:35.503042 DSI data_rate: 832800000 bps
9438 11:35:35.509860 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9439 11:35:35.512889 anx7625_parse_edid: pixelclock(138800).
9440 11:35:35.516070 hactive(1920), hsync(48), hfp(24), hbp(88)
9441 11:35:35.519503 vactive(1080), vsync(12), vfp(3), vbp(17)
9442 11:35:35.522713 anx7625_dsi_config: config dsi.
9443 11:35:35.529005 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9444 11:35:35.542837 anx7625_dsi_config: success to config DSI
9445 11:35:35.546061 anx7625_dp_start: MIPI phy setup OK.
9446 11:35:35.549854 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9447 11:35:35.553104 mtk_ddp_mode_set invalid vrefresh 60
9448 11:35:35.556149 main_disp_path_setup
9449 11:35:35.556526 ovl_layer_smi_id_en
9450 11:35:35.559108 ovl_layer_smi_id_en
9451 11:35:35.559542 ccorr_config
9452 11:35:35.559853 aal_config
9453 11:35:35.562704 gamma_config
9454 11:35:35.563165 postmask_config
9455 11:35:35.565815 dither_config
9456 11:35:35.569397 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9457 11:35:35.575975 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9458 11:35:35.579405 Root Device init finished in 552 msecs
9459 11:35:35.582410 CPU_CLUSTER: 0 init
9460 11:35:35.588784 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9461 11:35:35.595269 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9462 11:35:35.595681 APU_MBOX 0x190000b0 = 0x10001
9463 11:35:35.598792 APU_MBOX 0x190001b0 = 0x10001
9464 11:35:35.601836 APU_MBOX 0x190005b0 = 0x10001
9465 11:35:35.605660 APU_MBOX 0x190006b0 = 0x10001
9466 11:35:35.611897 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9467 11:35:35.621876 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9468 11:35:35.634370 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9469 11:35:35.641011 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9470 11:35:35.652975 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9471 11:35:35.661737 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9472 11:35:35.665041 CPU_CLUSTER: 0 init finished in 81 msecs
9473 11:35:35.667932 Devices initialized
9474 11:35:35.671340 Show all devs... After init.
9475 11:35:35.671898 Root Device: enabled 1
9476 11:35:35.674953 CPU_CLUSTER: 0: enabled 1
9477 11:35:35.678266 CPU: 00: enabled 1
9478 11:35:35.681458 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9479 11:35:35.684976 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9480 11:35:35.688228 ELOG: NV offset 0x57f000 size 0x1000
9481 11:35:35.694894 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9482 11:35:35.701652 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9483 11:35:35.704928 ELOG: Event(17) added with size 13 at 2024-07-17 11:35:35 UTC
9484 11:35:35.711407 out: cmd=0x121: 03 db 21 01 00 00 00 00
9485 11:35:35.714650 in-header: 03 ee 00 00 2c 00 00 00
9486 11:35:35.727527 in-data: 4f 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9487 11:35:35.730946 ELOG: Event(A1) added with size 10 at 2024-07-17 11:35:35 UTC
9488 11:35:35.737782 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9489 11:35:35.744394 ELOG: Event(A0) added with size 9 at 2024-07-17 11:35:35 UTC
9490 11:35:35.747592 elog_add_boot_reason: Logged dev mode boot
9491 11:35:35.754114 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9492 11:35:35.754498 Finalize devices...
9493 11:35:35.757546 Devices finalized
9494 11:35:35.760589 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9495 11:35:35.763724 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9496 11:35:35.767374 in-header: 03 07 00 00 08 00 00 00
9497 11:35:35.770788 in-data: aa e4 47 04 13 02 00 00
9498 11:35:35.773859 Chrome EC: UHEPI supported
9499 11:35:35.780451 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9500 11:35:35.783777 in-header: 03 a9 00 00 08 00 00 00
9501 11:35:35.787031 in-data: 84 60 60 08 00 00 00 00
9502 11:35:35.793493 ELOG: Event(91) added with size 10 at 2024-07-17 11:35:35 UTC
9503 11:35:35.796742 Chrome EC: clear events_b mask to 0x0000000020004000
9504 11:35:35.803528 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9505 11:35:35.806983 in-header: 03 fd 00 00 00 00 00 00
9506 11:35:35.810015 in-data:
9507 11:35:35.813406 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9508 11:35:35.816616 Writing coreboot table at 0xffe64000
9509 11:35:35.823881 0. 000000000010a000-0000000000113fff: RAMSTAGE
9510 11:35:35.827013 1. 0000000040000000-00000000400fffff: RAM
9511 11:35:35.830107 2. 0000000040100000-000000004032afff: RAMSTAGE
9512 11:35:35.833348 3. 000000004032b000-00000000545fffff: RAM
9513 11:35:35.836973 4. 0000000054600000-000000005465ffff: BL31
9514 11:35:35.839876 5. 0000000054660000-00000000ffe63fff: RAM
9515 11:35:35.846288 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9516 11:35:35.849829 7. 0000000100000000-000000023fffffff: RAM
9517 11:35:35.853157 Passing 5 GPIOs to payload:
9518 11:35:35.856424 NAME | PORT | POLARITY | VALUE
9519 11:35:35.863463 EC in RW | 0x000000aa | low | undefined
9520 11:35:35.866711 EC interrupt | 0x00000005 | low | undefined
9521 11:35:35.873275 TPM interrupt | 0x000000ab | high | undefined
9522 11:35:35.876495 SD card detect | 0x00000011 | high | undefined
9523 11:35:35.879707 speaker enable | 0x00000093 | high | undefined
9524 11:35:35.882928 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9525 11:35:35.887790 in-header: 03 f9 00 00 02 00 00 00
9526 11:35:35.891240 in-data: 02 00
9527 11:35:35.894272 ADC[4]: Raw value=904139 ID=7
9528 11:35:35.897565 ADC[3]: Raw value=213282 ID=1
9529 11:35:35.897961 RAM Code: 0x71
9530 11:35:35.900813 ADC[6]: Raw value=75036 ID=0
9531 11:35:35.904356 ADC[5]: Raw value=213282 ID=1
9532 11:35:35.904738 SKU Code: 0x1
9533 11:35:35.910662 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bbe7
9534 11:35:35.911051 coreboot table: 964 bytes.
9535 11:35:35.914265 IMD ROOT 0. 0xfffff000 0x00001000
9536 11:35:35.917317 IMD SMALL 1. 0xffffe000 0x00001000
9537 11:35:35.920698 RO MCACHE 2. 0xffffc000 0x00001104
9538 11:35:35.924033 CONSOLE 3. 0xfff7c000 0x00080000
9539 11:35:35.927693 FMAP 4. 0xfff7b000 0x00000452
9540 11:35:35.930625 TIME STAMP 5. 0xfff7a000 0x00000910
9541 11:35:35.934622 VBOOT WORK 6. 0xfff66000 0x00014000
9542 11:35:35.937279 RAMOOPS 7. 0xffe66000 0x00100000
9543 11:35:35.940464 COREBOOT 8. 0xffe64000 0x00002000
9544 11:35:35.944438 IMD small region:
9545 11:35:35.947531 IMD ROOT 0. 0xffffec00 0x00000400
9546 11:35:35.951090 VPD 1. 0xffffeb80 0x0000006c
9547 11:35:35.953959 MMC STATUS 2. 0xffffeb60 0x00000004
9548 11:35:35.957174 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9549 11:35:35.963705 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9550 11:35:36.005391 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9551 11:35:36.008720 Checking segment from ROM address 0x40100000
9552 11:35:36.014929 Checking segment from ROM address 0x4010001c
9553 11:35:36.019027 Loading segment from ROM address 0x40100000
9554 11:35:36.019412 code (compression=0)
9555 11:35:36.028321 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9556 11:35:36.035261 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9557 11:35:36.035727 it's not compressed!
9558 11:35:36.041761 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9559 11:35:36.048025 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9560 11:35:36.065496 Loading segment from ROM address 0x4010001c
9561 11:35:36.065886 Entry Point 0x80000000
9562 11:35:36.068547 Loaded segments
9563 11:35:36.072343 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9564 11:35:36.078342 Jumping to boot code at 0x80000000(0xffe64000)
9565 11:35:36.085055 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9566 11:35:36.091494 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9567 11:35:36.099941 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9568 11:35:36.103539 Checking segment from ROM address 0x40100000
9569 11:35:36.107016 Checking segment from ROM address 0x4010001c
9570 11:35:36.113522 Loading segment from ROM address 0x40100000
9571 11:35:36.113909 code (compression=1)
9572 11:35:36.120148 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9573 11:35:36.129708 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9574 11:35:36.130186 using LZMA
9575 11:35:36.138109 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9576 11:35:36.144876 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9577 11:35:36.148221 Loading segment from ROM address 0x4010001c
9578 11:35:36.151271 Entry Point 0x54601000
9579 11:35:36.151847 Loaded segments
9580 11:35:36.154808 NOTICE: MT8192 bl31_setup
9581 11:35:36.162023 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9582 11:35:36.165247 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9583 11:35:36.168550 WARNING: region 0:
9584 11:35:36.171947 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 11:35:36.172333 WARNING: region 1:
9586 11:35:36.178636 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9587 11:35:36.181793 WARNING: region 2:
9588 11:35:36.185398 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9589 11:35:36.188883 WARNING: region 3:
9590 11:35:36.191774 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9591 11:35:36.194928 WARNING: region 4:
9592 11:35:36.201943 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9593 11:35:36.202336 WARNING: region 5:
9594 11:35:36.205183 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9595 11:35:36.209001 WARNING: region 6:
9596 11:35:36.211837 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9597 11:35:36.215161 WARNING: region 7:
9598 11:35:36.217980 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 11:35:36.224840 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9600 11:35:36.228419 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9601 11:35:36.234670 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9602 11:35:36.237890 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9603 11:35:36.241541 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9604 11:35:36.248098 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9605 11:35:36.251171 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9606 11:35:36.254317 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9607 11:35:36.261165 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9608 11:35:36.265008 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9609 11:35:36.271192 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9610 11:35:36.274209 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9611 11:35:36.278003 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9612 11:35:36.284552 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9613 11:35:36.287963 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9614 11:35:36.291097 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9615 11:35:36.297516 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9616 11:35:36.300914 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9617 11:35:36.308420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9618 11:35:36.311130 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9619 11:35:36.314512 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9620 11:35:36.320701 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9621 11:35:36.324047 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9622 11:35:36.330642 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9623 11:35:36.334157 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9624 11:35:36.337321 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9625 11:35:36.343825 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9626 11:35:36.347266 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9627 11:35:36.353886 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9628 11:35:36.357024 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9629 11:35:36.360123 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9630 11:35:36.366823 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9631 11:35:36.370175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9632 11:35:36.373920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9633 11:35:36.380150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9634 11:35:36.383472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9635 11:35:36.386632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9636 11:35:36.390001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9637 11:35:36.396635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9638 11:35:36.399955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9639 11:35:36.403165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9640 11:35:36.406844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9641 11:35:36.413454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9642 11:35:36.416683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9643 11:35:36.419919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9644 11:35:36.423301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9645 11:35:36.430141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9646 11:35:36.433395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9647 11:35:36.436297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9648 11:35:36.443534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9649 11:35:36.446693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9650 11:35:36.453433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9651 11:35:36.456534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9652 11:35:36.462902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9653 11:35:36.466529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9654 11:35:36.469424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9655 11:35:36.476345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9656 11:35:36.479607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9657 11:35:36.485678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9658 11:35:36.488990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9659 11:35:36.496125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9660 11:35:36.499622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9661 11:35:36.505615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9662 11:35:36.509048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9663 11:35:36.516144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9664 11:35:36.519284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9665 11:35:36.522324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9666 11:35:36.528830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9667 11:35:36.532494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9668 11:35:36.539032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9669 11:35:36.542007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9670 11:35:36.548534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9671 11:35:36.552053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9672 11:35:36.555492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9673 11:35:36.561896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9674 11:35:36.565326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9675 11:35:36.571823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9676 11:35:36.575338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9677 11:35:36.581882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9678 11:35:36.585191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9679 11:35:36.591608 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9680 11:35:36.594919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9681 11:35:36.598442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9682 11:35:36.605048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9683 11:35:36.608286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9684 11:35:36.615012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9685 11:35:36.617994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9686 11:35:36.624737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9687 11:35:36.628158 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9688 11:35:36.634791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9689 11:35:36.637869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9690 11:35:36.641443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9691 11:35:36.647753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9692 11:35:36.650936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9693 11:35:36.657690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9694 11:35:36.661005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9695 11:35:36.667578 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9696 11:35:36.671385 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9697 11:35:36.674419 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9698 11:35:36.677466 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9699 11:35:36.684202 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9700 11:35:36.687732 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9701 11:35:36.690581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9702 11:35:36.697365 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9703 11:35:36.700979 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9704 11:35:36.707556 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9705 11:35:36.710552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9706 11:35:36.713830 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9707 11:35:36.720445 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9708 11:35:36.723974 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9709 11:35:36.730419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9710 11:35:36.734187 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9711 11:35:36.737300 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9712 11:35:36.743916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9713 11:35:36.747139 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9714 11:35:36.754120 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9715 11:35:36.757187 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9716 11:35:36.760496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9717 11:35:36.767411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9718 11:35:36.770363 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9719 11:35:36.773687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9720 11:35:36.776972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9721 11:35:36.780592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9722 11:35:36.787369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9723 11:35:36.790336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9724 11:35:36.796877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9725 11:35:36.800187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9726 11:35:36.803881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9727 11:35:36.809905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9728 11:35:36.813395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9729 11:35:36.819916 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9730 11:35:36.823485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9731 11:35:36.826368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9732 11:35:36.833402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9733 11:35:36.836394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9734 11:35:36.842916 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9735 11:35:36.846489 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9736 11:35:36.849814 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9737 11:35:36.856603 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9738 11:35:36.859309 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9739 11:35:36.866350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9740 11:35:36.869535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9741 11:35:36.872555 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9742 11:35:36.879170 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9743 11:35:36.882754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9744 11:35:36.889525 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9745 11:35:36.892857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9746 11:35:36.895902 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9747 11:35:36.902505 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9748 11:35:36.905986 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9749 11:35:36.912771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9750 11:35:36.915531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9751 11:35:36.919287 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9752 11:35:36.925413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9753 11:35:36.928771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9754 11:35:36.935810 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9755 11:35:36.938863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9756 11:35:36.942025 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9757 11:35:36.948677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9758 11:35:36.952472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9759 11:35:36.955483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9760 11:35:36.962266 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9761 11:35:36.965395 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9762 11:35:36.972481 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9763 11:35:36.975250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9764 11:35:36.978651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9765 11:35:36.985311 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9766 11:35:36.988463 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9767 11:35:36.995389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9768 11:35:36.998573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9769 11:35:37.001609 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9770 11:35:37.008645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9771 11:35:37.011923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9772 11:35:37.018619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9773 11:35:37.022798 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9774 11:35:37.025106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9775 11:35:37.031949 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9776 11:35:37.034982 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9777 11:35:37.041708 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9778 11:35:37.045215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9779 11:35:37.048742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9780 11:35:37.055090 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9781 11:35:37.058203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9782 11:35:37.064724 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9783 11:35:37.068200 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9784 11:35:37.071471 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9785 11:35:37.078253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9786 11:35:37.081275 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9787 11:35:37.087679 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9788 11:35:37.091396 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9789 11:35:37.094624 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9790 11:35:37.101013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9791 11:35:37.104358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9792 11:35:37.111068 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9793 11:35:37.114409 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9794 11:35:37.120991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9795 11:35:37.124761 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9796 11:35:37.127498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9797 11:35:37.134078 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9798 11:35:37.137494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9799 11:35:37.144654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9800 11:35:37.147549 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9801 11:35:37.151009 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9802 11:35:37.157643 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9803 11:35:37.160759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9804 11:35:37.166843 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9805 11:35:37.170215 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9806 11:35:37.176879 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9807 11:35:37.180193 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9808 11:35:37.183787 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9809 11:35:37.190346 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9810 11:35:37.193753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9811 11:35:37.200091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9812 11:35:37.203675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9813 11:35:37.207186 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9814 11:35:37.213797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9815 11:35:37.217082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9816 11:35:37.223240 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9817 11:35:37.226692 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9818 11:35:37.233299 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9819 11:35:37.236404 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9820 11:35:37.240211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9821 11:35:37.246533 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9822 11:35:37.250391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9823 11:35:37.256969 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9824 11:35:37.260468 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9825 11:35:37.266790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9826 11:35:37.270066 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9827 11:35:37.273246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9828 11:35:37.279819 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9829 11:35:37.283156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9830 11:35:37.286251 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9831 11:35:37.289543 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9832 11:35:37.296631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9833 11:35:37.299757 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9834 11:35:37.303136 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9835 11:35:37.309715 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9836 11:35:37.312950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9837 11:35:37.316059 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9838 11:35:37.322173 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9839 11:35:37.325950 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9840 11:35:37.332740 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9841 11:35:37.335852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9842 11:35:37.339121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9843 11:35:37.345684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9844 11:35:37.349152 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9845 11:35:37.355990 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9846 11:35:37.359089 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9847 11:35:37.362342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9848 11:35:37.368690 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9849 11:35:37.372352 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9850 11:35:37.375285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9851 11:35:37.382440 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9852 11:35:37.385298 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9853 11:35:37.388687 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9854 11:35:37.395126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9855 11:35:37.398854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9856 11:35:37.405275 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9857 11:35:37.408521 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9858 11:35:37.411938 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9859 11:35:37.418494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9860 11:35:37.421785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9861 11:35:37.425345 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9862 11:35:37.431601 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9863 11:35:37.435341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9864 11:35:37.441882 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9865 11:35:37.444882 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9866 11:35:37.448302 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9867 11:35:37.455165 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9868 11:35:37.458285 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9869 11:35:37.461389 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9870 11:35:37.464685 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9871 11:35:37.468116 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9872 11:35:37.474584 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9873 11:35:37.478049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9874 11:35:37.481315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9875 11:35:37.484849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9876 11:35:37.491148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9877 11:35:37.494726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9878 11:35:37.498250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9879 11:35:37.504649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9880 11:35:37.507854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9881 11:35:37.511214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9882 11:35:37.517589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9883 11:35:37.521040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9884 11:35:37.527675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9885 11:35:37.531277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9886 11:35:37.534497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9887 11:35:37.541168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9888 11:35:37.544139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9889 11:35:37.547682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9890 11:35:37.554149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9891 11:35:37.558086 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9892 11:35:37.563935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9893 11:35:37.567563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9894 11:35:37.573912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9895 11:35:37.577184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9896 11:35:37.580747 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9897 11:35:37.587111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9898 11:35:37.590166 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9899 11:35:37.596825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9900 11:35:37.600268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9901 11:35:37.606958 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9902 11:35:37.609950 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9903 11:35:37.613429 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9904 11:35:37.620097 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9905 11:35:37.623357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9906 11:35:37.630069 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9907 11:35:37.633378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9908 11:35:37.636483 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9909 11:35:37.643172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9910 11:35:37.646772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9911 11:35:37.653438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9912 11:35:37.656965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9913 11:35:37.659798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9914 11:35:37.666191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9915 11:35:37.669204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9916 11:35:37.676288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9917 11:35:37.679689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9918 11:35:37.686012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9919 11:35:37.689598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9920 11:35:37.693344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9921 11:35:37.699480 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9922 11:35:37.702911 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9923 11:35:37.709702 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9924 11:35:37.712758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9925 11:35:37.719110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9926 11:35:37.722395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9927 11:35:37.725878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9928 11:35:37.732757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9929 11:35:37.736049 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9930 11:35:37.743150 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9931 11:35:37.746312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9932 11:35:37.749300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9933 11:35:37.755486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9934 11:35:37.759620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9935 11:35:37.766240 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9936 11:35:37.768915 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9937 11:35:37.772062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9938 11:35:37.779048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9939 11:35:37.782068 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9940 11:35:37.788497 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9941 11:35:37.791711 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9942 11:35:37.798297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9943 11:35:37.801496 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9944 11:35:37.805011 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9945 11:35:37.811746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9946 11:35:37.814851 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9947 11:35:37.821390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9948 11:35:37.825159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9949 11:35:37.831182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9950 11:35:37.834383 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9951 11:35:37.837912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9952 11:35:37.844302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9953 11:35:37.848277 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9954 11:35:37.854028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9955 11:35:37.857559 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9956 11:35:37.864468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9957 11:35:37.867248 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9958 11:35:37.874129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9959 11:35:37.877420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9960 11:35:37.880947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9961 11:35:37.887570 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9962 11:35:37.890267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9963 11:35:37.897156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9964 11:35:37.900547 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9965 11:35:37.906963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9966 11:35:37.910470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9967 11:35:37.916960 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9968 11:35:37.920093 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9969 11:35:37.924030 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9970 11:35:37.930004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9971 11:35:37.933590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9972 11:35:37.940014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9973 11:35:37.943364 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9974 11:35:37.949994 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9975 11:35:37.953436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9976 11:35:37.956536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9977 11:35:37.963348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9978 11:35:37.966780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9979 11:35:37.973103 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9980 11:35:37.976249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9981 11:35:37.982890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9982 11:35:37.986378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9983 11:35:37.992965 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9984 11:35:37.996500 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9985 11:35:37.999830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9986 11:35:38.006679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9987 11:35:38.009506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9988 11:35:38.015997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9989 11:35:38.019331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9990 11:35:38.025584 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9991 11:35:38.029270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9992 11:35:38.036185 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9993 11:35:38.038983 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9994 11:35:38.042632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9995 11:35:38.048992 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9996 11:35:38.052465 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9997 11:35:38.058999 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9998 11:35:38.061825 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9999 11:35:38.068615 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10000 11:35:38.072156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10001 11:35:38.075538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10002 11:35:38.081993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10003 11:35:38.085304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10004 11:35:38.091721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10005 11:35:38.095313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10006 11:35:38.101902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10007 11:35:38.105290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10008 11:35:38.112204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10009 11:35:38.115076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10010 11:35:38.121595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10011 11:35:38.124877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10012 11:35:38.131930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10013 11:35:38.134938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10014 11:35:38.141777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10015 11:35:38.145389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10016 11:35:38.151215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10017 11:35:38.154723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10018 11:35:38.161848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10019 11:35:38.164365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10020 11:35:38.170747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10021 11:35:38.174033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10022 11:35:38.180827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10023 11:35:38.184432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10024 11:35:38.190717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10025 11:35:38.194165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10026 11:35:38.200816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10027 11:35:38.204190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10028 11:35:38.210915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10029 11:35:38.214408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10030 11:35:38.220865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10031 11:35:38.224080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10032 11:35:38.230451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10033 11:35:38.234328 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10034 11:35:38.237075 INFO: [APUAPC] vio 0
10035 11:35:38.240436 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10036 11:35:38.247154 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10037 11:35:38.250143 INFO: [APUAPC] D0_APC_0: 0x400510
10038 11:35:38.250523 INFO: [APUAPC] D0_APC_1: 0x0
10039 11:35:38.253637 INFO: [APUAPC] D0_APC_2: 0x1540
10040 11:35:38.257211 INFO: [APUAPC] D0_APC_3: 0x0
10041 11:35:38.259813 INFO: [APUAPC] D1_APC_0: 0xffffffff
10042 11:35:38.263312 INFO: [APUAPC] D1_APC_1: 0xffffffff
10043 11:35:38.267202 INFO: [APUAPC] D1_APC_2: 0x3fffff
10044 11:35:38.270339 INFO: [APUAPC] D1_APC_3: 0x0
10045 11:35:38.273513 INFO: [APUAPC] D2_APC_0: 0xffffffff
10046 11:35:38.276796 INFO: [APUAPC] D2_APC_1: 0xffffffff
10047 11:35:38.279964 INFO: [APUAPC] D2_APC_2: 0x3fffff
10048 11:35:38.283624 INFO: [APUAPC] D2_APC_3: 0x0
10049 11:35:38.286847 INFO: [APUAPC] D3_APC_0: 0xffffffff
10050 11:35:38.289705 INFO: [APUAPC] D3_APC_1: 0xffffffff
10051 11:35:38.293167 INFO: [APUAPC] D3_APC_2: 0x3fffff
10052 11:35:38.296516 INFO: [APUAPC] D3_APC_3: 0x0
10053 11:35:38.300057 INFO: [APUAPC] D4_APC_0: 0xffffffff
10054 11:35:38.303332 INFO: [APUAPC] D4_APC_1: 0xffffffff
10055 11:35:38.306201 INFO: [APUAPC] D4_APC_2: 0x3fffff
10056 11:35:38.309504 INFO: [APUAPC] D4_APC_3: 0x0
10057 11:35:38.312897 INFO: [APUAPC] D5_APC_0: 0xffffffff
10058 11:35:38.316390 INFO: [APUAPC] D5_APC_1: 0xffffffff
10059 11:35:38.320088 INFO: [APUAPC] D5_APC_2: 0x3fffff
10060 11:35:38.322965 INFO: [APUAPC] D5_APC_3: 0x0
10061 11:35:38.326122 INFO: [APUAPC] D6_APC_0: 0xffffffff
10062 11:35:38.329788 INFO: [APUAPC] D6_APC_1: 0xffffffff
10063 11:35:38.332882 INFO: [APUAPC] D6_APC_2: 0x3fffff
10064 11:35:38.336046 INFO: [APUAPC] D6_APC_3: 0x0
10065 11:35:38.339683 INFO: [APUAPC] D7_APC_0: 0xffffffff
10066 11:35:38.343093 INFO: [APUAPC] D7_APC_1: 0xffffffff
10067 11:35:38.345931 INFO: [APUAPC] D7_APC_2: 0x3fffff
10068 11:35:38.349527 INFO: [APUAPC] D7_APC_3: 0x0
10069 11:35:38.352716 INFO: [APUAPC] D8_APC_0: 0xffffffff
10070 11:35:38.355961 INFO: [APUAPC] D8_APC_1: 0xffffffff
10071 11:35:38.359465 INFO: [APUAPC] D8_APC_2: 0x3fffff
10072 11:35:38.362730 INFO: [APUAPC] D8_APC_3: 0x0
10073 11:35:38.365825 INFO: [APUAPC] D9_APC_0: 0xffffffff
10074 11:35:38.369155 INFO: [APUAPC] D9_APC_1: 0xffffffff
10075 11:35:38.372469 INFO: [APUAPC] D9_APC_2: 0x3fffff
10076 11:35:38.375784 INFO: [APUAPC] D9_APC_3: 0x0
10077 11:35:38.378818 INFO: [APUAPC] D10_APC_0: 0xffffffff
10078 11:35:38.382152 INFO: [APUAPC] D10_APC_1: 0xffffffff
10079 11:35:38.385653 INFO: [APUAPC] D10_APC_2: 0x3fffff
10080 11:35:38.388978 INFO: [APUAPC] D10_APC_3: 0x0
10081 11:35:38.392454 INFO: [APUAPC] D11_APC_0: 0xffffffff
10082 11:35:38.395589 INFO: [APUAPC] D11_APC_1: 0xffffffff
10083 11:35:38.399002 INFO: [APUAPC] D11_APC_2: 0x3fffff
10084 11:35:38.401998 INFO: [APUAPC] D11_APC_3: 0x0
10085 11:35:38.405189 INFO: [APUAPC] D12_APC_0: 0xffffffff
10086 11:35:38.408896 INFO: [APUAPC] D12_APC_1: 0xffffffff
10087 11:35:38.411929 INFO: [APUAPC] D12_APC_2: 0x3fffff
10088 11:35:38.415311 INFO: [APUAPC] D12_APC_3: 0x0
10089 11:35:38.418663 INFO: [APUAPC] D13_APC_0: 0xffffffff
10090 11:35:38.422256 INFO: [APUAPC] D13_APC_1: 0xffffffff
10091 11:35:38.425057 INFO: [APUAPC] D13_APC_2: 0x3fffff
10092 11:35:38.428558 INFO: [APUAPC] D13_APC_3: 0x0
10093 11:35:38.432012 INFO: [APUAPC] D14_APC_0: 0xffffffff
10094 11:35:38.435258 INFO: [APUAPC] D14_APC_1: 0xffffffff
10095 11:35:38.438376 INFO: [APUAPC] D14_APC_2: 0x3fffff
10096 11:35:38.442227 INFO: [APUAPC] D14_APC_3: 0x0
10097 11:35:38.445082 INFO: [APUAPC] D15_APC_0: 0xffffffff
10098 11:35:38.448346 INFO: [APUAPC] D15_APC_1: 0xffffffff
10099 11:35:38.451710 INFO: [APUAPC] D15_APC_2: 0x3fffff
10100 11:35:38.454962 INFO: [APUAPC] D15_APC_3: 0x0
10101 11:35:38.458317 INFO: [APUAPC] APC_CON: 0x4
10102 11:35:38.461818 INFO: [NOCDAPC] D0_APC_0: 0x0
10103 11:35:38.461893 INFO: [NOCDAPC] D0_APC_1: 0x0
10104 11:35:38.465302 INFO: [NOCDAPC] D1_APC_0: 0x0
10105 11:35:38.468317 INFO: [NOCDAPC] D1_APC_1: 0xfff
10106 11:35:38.471975 INFO: [NOCDAPC] D2_APC_0: 0x0
10107 11:35:38.475611 INFO: [NOCDAPC] D2_APC_1: 0xfff
10108 11:35:38.478456 INFO: [NOCDAPC] D3_APC_0: 0x0
10109 11:35:38.482051 INFO: [NOCDAPC] D3_APC_1: 0xfff
10110 11:35:38.484874 INFO: [NOCDAPC] D4_APC_0: 0x0
10111 11:35:38.488577 INFO: [NOCDAPC] D4_APC_1: 0xfff
10112 11:35:38.491585 INFO: [NOCDAPC] D5_APC_0: 0x0
10113 11:35:38.491665 INFO: [NOCDAPC] D5_APC_1: 0xfff
10114 11:35:38.495029 INFO: [NOCDAPC] D6_APC_0: 0x0
10115 11:35:38.498407 INFO: [NOCDAPC] D6_APC_1: 0xfff
10116 11:35:38.501629 INFO: [NOCDAPC] D7_APC_0: 0x0
10117 11:35:38.504798 INFO: [NOCDAPC] D7_APC_1: 0xfff
10118 11:35:38.508841 INFO: [NOCDAPC] D8_APC_0: 0x0
10119 11:35:38.511299 INFO: [NOCDAPC] D8_APC_1: 0xfff
10120 11:35:38.515048 INFO: [NOCDAPC] D9_APC_0: 0x0
10121 11:35:38.518130 INFO: [NOCDAPC] D9_APC_1: 0xfff
10122 11:35:38.521655 INFO: [NOCDAPC] D10_APC_0: 0x0
10123 11:35:38.524471 INFO: [NOCDAPC] D10_APC_1: 0xfff
10124 11:35:38.528204 INFO: [NOCDAPC] D11_APC_0: 0x0
10125 11:35:38.531316 INFO: [NOCDAPC] D11_APC_1: 0xfff
10126 11:35:38.531415 INFO: [NOCDAPC] D12_APC_0: 0x0
10127 11:35:38.534486 INFO: [NOCDAPC] D12_APC_1: 0xfff
10128 11:35:38.538070 INFO: [NOCDAPC] D13_APC_0: 0x0
10129 11:35:38.541410 INFO: [NOCDAPC] D13_APC_1: 0xfff
10130 11:35:38.544855 INFO: [NOCDAPC] D14_APC_0: 0x0
10131 11:35:38.548023 INFO: [NOCDAPC] D14_APC_1: 0xfff
10132 11:35:38.551033 INFO: [NOCDAPC] D15_APC_0: 0x0
10133 11:35:38.554773 INFO: [NOCDAPC] D15_APC_1: 0xfff
10134 11:35:38.557659 INFO: [NOCDAPC] APC_CON: 0x4
10135 11:35:38.561330 INFO: [APUAPC] set_apusys_apc done
10136 11:35:38.564781 INFO: [DEVAPC] devapc_init done
10137 11:35:38.568059 INFO: GICv3 without legacy support detected.
10138 11:35:38.571082 INFO: ARM GICv3 driver initialized in EL3
10139 11:35:38.574583 INFO: Maximum SPI INTID supported: 639
10140 11:35:38.581119 INFO: BL31: Initializing runtime services
10141 11:35:38.584442 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10142 11:35:38.587575 INFO: SPM: enable CPC mode
10143 11:35:38.594162 INFO: mcdi ready for mcusys-off-idle and system suspend
10144 11:35:38.597818 INFO: BL31: Preparing for EL3 exit to normal world
10145 11:35:38.600999 INFO: Entry point address = 0x80000000
10146 11:35:38.604272 INFO: SPSR = 0x8
10147 11:35:38.609750
10148 11:35:38.609825
10149 11:35:38.609883
10150 11:35:38.612794 Starting depthcharge on Spherion...
10151 11:35:38.612869
10152 11:35:38.612926 Wipe memory regions:
10153 11:35:38.612980
10154 11:35:38.613613 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10155 11:35:38.613702 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10156 11:35:38.613777 Setting prompt string to ['asurada:']
10157 11:35:38.613840 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10158 11:35:38.615853 [0x00000040000000, 0x00000054600000)
10159 11:35:38.738899
10160 11:35:38.739030 [0x00000054660000, 0x00000080000000)
10161 11:35:38.998851
10162 11:35:38.998982 [0x000000821a7280, 0x000000ffe64000)
10163 11:35:39.744009
10164 11:35:39.744504 [0x00000100000000, 0x00000240000000)
10165 11:35:41.633563
10166 11:35:41.636303 Initializing XHCI USB controller at 0x11200000.
10167 11:35:42.675241
10168 11:35:42.678426 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10169 11:35:42.678826
10170 11:35:42.679124
10171 11:35:42.679776 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10172 11:35:42.680154 Sending line: 'tftpboot 192.168.201.1 14864600/tftp-deploy-eo48rblv/kernel/image.itb 14864600/tftp-deploy-eo48rblv/kernel/cmdline '
10174 11:35:42.781449 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 11:35:42.781937 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10176 11:35:42.786080 asurada: tftpboot 192.168.201.1 14864600/tftp-deploy-eo48rblv/kernel/image.itp-deploy-eo48rblv/kernel/cmdline
10177 11:35:42.786468
10178 11:35:42.786767 Waiting for link
10179 11:35:42.944303
10180 11:35:42.944725 R8152: Initializing
10181 11:35:42.945024
10182 11:35:42.948022 Version 6 (ocp_data = 5c30)
10183 11:35:42.948429
10184 11:35:42.950798 R8152: Done initializing
10185 11:35:42.951180
10186 11:35:42.951522 Adding net device
10187 11:35:44.854201
10188 11:35:44.854694 done.
10189 11:35:44.855023
10190 11:35:44.855330 MAC: 00:e0:4c:68:02:81
10191 11:35:44.855690
10192 11:35:44.857653 Sending DHCP discover... done.
10193 11:35:44.858087
10194 11:35:44.860789 Waiting for reply... done.
10195 11:35:44.861470
10196 11:35:44.863943 Sending DHCP request... done.
10197 11:35:44.864473
10198 11:35:44.868800 Waiting for reply... done.
10199 11:35:44.869226
10200 11:35:44.869554 My ip is 192.168.201.14
10201 11:35:44.869859
10202 11:35:44.871971 The DHCP server ip is 192.168.201.1
10203 11:35:44.872402
10204 11:35:44.878640 TFTP server IP predefined by user: 192.168.201.1
10205 11:35:44.879025
10206 11:35:44.885091 Bootfile predefined by user: 14864600/tftp-deploy-eo48rblv/kernel/image.itb
10207 11:35:44.885483
10208 11:35:44.888390 Sending tftp read request... done.
10209 11:35:44.888778
10210 11:35:44.895312 Waiting for the transfer...
10211 11:35:44.895769
10212 11:35:45.496391 00000000 ################################################################
10213 11:35:45.496564
10214 11:35:46.133473 00080000 ################################################################
10215 11:35:46.134050
10216 11:35:46.775536 00100000 ################################################################
10217 11:35:46.776178
10218 11:35:47.443743 00180000 ################################################################
10219 11:35:47.444297
10220 11:35:48.106913 00200000 ################################################################
10221 11:35:48.107041
10222 11:35:48.703468 00280000 ################################################################
10223 11:35:48.703604
10224 11:35:49.285569 00300000 ################################################################
10225 11:35:49.286056
10226 11:35:49.966324 00380000 ################################################################
10227 11:35:49.966801
10228 11:35:50.661476 00400000 ################################################################
10229 11:35:50.661949
10230 11:35:51.343495 00480000 ################################################################
10231 11:35:51.344030
10232 11:35:52.009613 00500000 ################################################################
10233 11:35:52.010064
10234 11:35:52.667688 00580000 ################################################################
10235 11:35:52.668152
10236 11:35:53.343080 00600000 ################################################################
10237 11:35:53.343573
10238 11:35:54.034471 00680000 ################################################################
10239 11:35:54.035003
10240 11:35:54.721965 00700000 ################################################################
10241 11:35:54.722425
10242 11:35:55.416636 00780000 ################################################################
10243 11:35:55.417154
10244 11:35:56.069688 00800000 ################################################################
10245 11:35:56.069833
10246 11:35:56.700243 00880000 ################################################################
10247 11:35:56.700371
10248 11:35:57.384000 00900000 ################################################################
10249 11:35:57.384450
10250 11:35:58.060314 00980000 ################################################################
10251 11:35:58.060787
10252 11:35:58.746098 00a00000 ################################################################
10253 11:35:58.746570
10254 11:35:59.414607 00a80000 ################################################################
10255 11:35:59.415118
10256 11:36:00.074831 00b00000 ################################################################
10257 11:36:00.075304
10258 11:36:00.729000 00b80000 ################################################################
10259 11:36:00.729473
10260 11:36:01.401112 00c00000 ################################################################
10261 11:36:01.401581
10262 11:36:02.042776 00c80000 ################################################################
10263 11:36:02.043242
10264 11:36:02.699125 00d00000 ################################################################
10265 11:36:02.699625
10266 11:36:03.356013 00d80000 ################################################################
10267 11:36:03.356466
10268 11:36:04.019849 00e00000 ################################################################
10269 11:36:04.020306
10270 11:36:04.685874 00e80000 ################################################################
10271 11:36:04.686397
10272 11:36:05.369619 00f00000 ################################################################
10273 11:36:05.370074
10274 11:36:06.048653 00f80000 ################################################################
10275 11:36:06.049177
10276 11:36:06.730247 01000000 ################################################################
10277 11:36:06.730700
10278 11:36:07.410971 01080000 ################################################################
10279 11:36:07.411453
10280 11:36:08.074433 01100000 ################################################################
10281 11:36:08.074955
10282 11:36:08.753317 01180000 ################################################################
10283 11:36:08.753786
10284 11:36:09.430548 01200000 ################################################################
10285 11:36:09.431003
10286 11:36:10.103197 01280000 ################################################################
10287 11:36:10.103754
10288 11:36:10.776264 01300000 ################################################################
10289 11:36:10.776746
10290 11:36:11.451495 01380000 ################################################################
10291 11:36:11.451950
10292 11:36:12.110196 01400000 ################################################################
10293 11:36:12.110656
10294 11:36:12.781457 01480000 ################################################################
10295 11:36:12.782054
10296 11:36:13.445690 01500000 ################################################################
10297 11:36:13.446178
10298 11:36:14.110374 01580000 ################################################################
10299 11:36:14.110819
10300 11:36:14.769935 01600000 ################################################################
10301 11:36:14.770437
10302 11:36:15.440049 01680000 ################################################################
10303 11:36:15.440526
10304 11:36:16.121695 01700000 ################################################################
10305 11:36:16.122152
10306 11:36:16.792767 01780000 ################################################################
10307 11:36:16.793302
10308 11:36:17.461001 01800000 ################################################################
10309 11:36:17.461458
10310 11:36:18.075019 01880000 ################################################################
10311 11:36:18.075132
10312 11:36:18.720871 01900000 ################################################################
10313 11:36:18.721332
10314 11:36:19.345928 01980000 ################################################################
10315 11:36:19.346042
10316 11:36:19.885665 01a00000 ################################################################
10317 11:36:19.885793
10318 11:36:20.449078 01a80000 ################################################################
10319 11:36:20.449224
10320 11:36:21.001792 01b00000 ################################################################
10321 11:36:21.001945
10322 11:36:21.568339 01b80000 ################################################################
10323 11:36:21.568468
10324 11:36:22.112413 01c00000 ################################################################
10325 11:36:22.112538
10326 11:36:22.654358 01c80000 ################################################################
10327 11:36:22.654492
10328 11:36:23.201068 01d00000 ################################################################
10329 11:36:23.201198
10330 11:36:23.749729 01d80000 ################################################################
10331 11:36:23.749886
10332 11:36:24.218889 01e00000 ##################################################### done.
10333 11:36:24.219017
10334 11:36:24.222403 The bootfile was 31889266 bytes long.
10335 11:36:24.222490
10336 11:36:24.225687 Sending tftp read request... done.
10337 11:36:24.225768
10338 11:36:24.225828 Waiting for the transfer...
10339 11:36:24.225883
10340 11:36:24.229100 00000000 # done.
10341 11:36:24.229178
10342 11:36:24.235183 Command line loaded dynamically from TFTP file: 14864600/tftp-deploy-eo48rblv/kernel/cmdline
10343 11:36:24.235261
10344 11:36:24.258538 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10345 11:36:24.258632
10346 11:36:24.258691 Loading FIT.
10347 11:36:24.261487
10348 11:36:24.261583 Image ramdisk-1 has 18721686 bytes.
10349 11:36:24.261667
10350 11:36:24.264954 Image fdt-1 has 47258 bytes.
10351 11:36:24.265029
10352 11:36:24.268136 Image kernel-1 has 13118294 bytes.
10353 11:36:24.268211
10354 11:36:24.279005 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10355 11:36:24.279085
10356 11:36:24.295210 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10357 11:36:24.295302
10358 11:36:24.301394 Choosing best match conf-1 for compat google,spherion-rev2.
10359 11:36:24.304585
10360 11:36:24.308657 Connected to device vid:did:rid of 1ae0:0028:00
10361 11:36:24.316271
10362 11:36:24.319577 tpm_get_response: command 0x17b, return code 0x0
10363 11:36:24.319656
10364 11:36:24.322767 ec_init: CrosEC protocol v3 supported (256, 248)
10365 11:36:24.327387
10366 11:36:24.329936 tpm_cleanup: add release locality here.
10367 11:36:24.330012
10368 11:36:24.330070 Shutting down all USB controllers.
10369 11:36:24.333809
10370 11:36:24.333941 Removing current net device
10371 11:36:24.334027
10372 11:36:24.339903 Exiting depthcharge with code 4 at timestamp: 75202040
10373 11:36:24.339979
10374 11:36:24.343216 LZMA decompressing kernel-1 to 0x821a6718
10375 11:36:24.343292
10376 11:36:24.346790 LZMA decompressing kernel-1 to 0x40000000
10377 11:36:25.962747
10378 11:36:25.962867 jumping to kernel
10379 11:36:25.963325 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10380 11:36:25.963420 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10381 11:36:25.963531 Setting prompt string to ['Linux version [0-9]']
10382 11:36:25.963596 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10383 11:36:25.963665 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10384 11:36:26.042937
10385 11:36:26.046018 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10386 11:36:26.050103 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10387 11:36:26.050199 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10388 11:36:26.050267 Setting prompt string to []
10389 11:36:26.050337 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10390 11:36:26.050406 Using line separator: #'\n'#
10391 11:36:26.050459 No login prompt set.
10392 11:36:26.050514 Parsing kernel messages
10393 11:36:26.050563 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10394 11:36:26.050692 [login-action] Waiting for messages, (timeout 00:03:32)
10395 11:36:26.050786 Waiting using forced prompt support (timeout 00:01:46)
10396 11:36:26.069684 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10397 11:36:26.072602 [ 0.000000] random: crng init done
10398 11:36:26.075853 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10399 11:36:26.078881 [ 0.000000] efi: UEFI not found.
10400 11:36:26.089011 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10401 11:36:26.095758 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10402 11:36:26.105285 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10403 11:36:26.115308 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10404 11:36:26.121945 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10405 11:36:26.125488 [ 0.000000] printk: bootconsole [mtk8250] enabled
10406 11:36:26.134122 [ 0.000000] NUMA: No NUMA configuration found
10407 11:36:26.140791 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10408 11:36:26.147244 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10409 11:36:26.147323 [ 0.000000] Zone ranges:
10410 11:36:26.153529 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10411 11:36:26.157048 [ 0.000000] DMA32 empty
10412 11:36:26.163612 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10413 11:36:26.167362 [ 0.000000] Movable zone start for each node
10414 11:36:26.170598 [ 0.000000] Early memory node ranges
10415 11:36:26.176535 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10416 11:36:26.183672 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10417 11:36:26.190382 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10418 11:36:26.196439 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10419 11:36:26.202977 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10420 11:36:26.209811 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10421 11:36:26.267340 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10422 11:36:26.274064 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10423 11:36:26.280433 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10424 11:36:26.283589 [ 0.000000] psci: probing for conduit method from DT.
10425 11:36:26.290639 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10426 11:36:26.293720 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10427 11:36:26.300521 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10428 11:36:26.303555 [ 0.000000] psci: SMC Calling Convention v1.2
10429 11:36:26.310383 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10430 11:36:26.313638 [ 0.000000] Detected VIPT I-cache on CPU0
10431 11:36:26.320376 [ 0.000000] CPU features: detected: GIC system register CPU interface
10432 11:36:26.326545 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10433 11:36:26.333078 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10434 11:36:26.340288 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10435 11:36:26.350472 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10436 11:36:26.355990 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10437 11:36:26.359702 [ 0.000000] alternatives: applying boot alternatives
10438 11:36:26.366414 [ 0.000000] Fallback order for Node 0: 0
10439 11:36:26.373336 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10440 11:36:26.376193 [ 0.000000] Policy zone: Normal
10441 11:36:26.399176 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10442 11:36:26.409426 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10443 11:36:26.419376 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10444 11:36:26.429607 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10445 11:36:26.436016 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10446 11:36:26.439322 <6>[ 0.000000] software IO TLB: area num 8.
10447 11:36:26.496643 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10448 11:36:26.645324 <6>[ 0.000000] Memory: 7945776K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406992K reserved, 32768K cma-reserved)
10449 11:36:26.651919 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10450 11:36:26.658843 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10451 11:36:26.661887 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10452 11:36:26.669185 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10453 11:36:26.675294 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10454 11:36:26.681649 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10455 11:36:26.688375 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10456 11:36:26.694765 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10457 11:36:26.701426 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10458 11:36:26.707950 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10459 11:36:26.711014 <6>[ 0.000000] GICv3: 608 SPIs implemented
10460 11:36:26.714165 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10461 11:36:26.721043 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10462 11:36:26.725283 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10463 11:36:26.731062 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10464 11:36:26.743944 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10465 11:36:26.757174 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10466 11:36:26.764121 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10467 11:36:26.772574 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10468 11:36:26.785688 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10469 11:36:26.791692 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10470 11:36:26.798862 <6>[ 0.009177] Console: colour dummy device 80x25
10471 11:36:26.808607 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10472 11:36:26.815371 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10473 11:36:26.818723 <6>[ 0.029288] LSM: Security Framework initializing
10474 11:36:26.824919 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10475 11:36:26.835763 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10476 11:36:26.844618 <6>[ 0.051549] cblist_init_generic: Setting adjustable number of callback queues.
10477 11:36:26.851366 <6>[ 0.059035] cblist_init_generic: Setting shift to 3 and lim to 1.
10478 11:36:26.857823 <6>[ 0.065375] cblist_init_generic: Setting adjustable number of callback queues.
10479 11:36:26.864477 <6>[ 0.072802] cblist_init_generic: Setting shift to 3 and lim to 1.
10480 11:36:26.867834 <6>[ 0.079205] rcu: Hierarchical SRCU implementation.
10481 11:36:26.874612 <6>[ 0.084220] rcu: Max phase no-delay instances is 1000.
10482 11:36:26.880864 <6>[ 0.091248] EFI services will not be available.
10483 11:36:26.884194 <6>[ 0.096233] smp: Bringing up secondary CPUs ...
10484 11:36:26.893429 <6>[ 0.101285] Detected VIPT I-cache on CPU1
10485 11:36:26.899760 <6>[ 0.101356] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10486 11:36:26.906929 <6>[ 0.101386] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10487 11:36:26.909714 <6>[ 0.101732] Detected VIPT I-cache on CPU2
10488 11:36:26.919674 <6>[ 0.101785] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10489 11:36:26.926198 <6>[ 0.101803] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10490 11:36:26.929554 <6>[ 0.102068] Detected VIPT I-cache on CPU3
10491 11:36:26.935826 <6>[ 0.102116] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10492 11:36:26.942346 <6>[ 0.102131] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10493 11:36:26.948686 <6>[ 0.102440] CPU features: detected: Spectre-v4
10494 11:36:26.952726 <6>[ 0.102446] CPU features: detected: Spectre-BHB
10495 11:36:26.955967 <6>[ 0.102452] Detected PIPT I-cache on CPU4
10496 11:36:26.965559 <6>[ 0.102515] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10497 11:36:26.972003 <6>[ 0.102532] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10498 11:36:26.975154 <6>[ 0.102828] Detected PIPT I-cache on CPU5
10499 11:36:26.981851 <6>[ 0.102891] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10500 11:36:26.988526 <6>[ 0.102908] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10501 11:36:26.991365 <6>[ 0.103192] Detected PIPT I-cache on CPU6
10502 11:36:27.001480 <6>[ 0.103258] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10503 11:36:27.007785 <6>[ 0.103274] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10504 11:36:27.011414 <6>[ 0.103573] Detected PIPT I-cache on CPU7
10505 11:36:27.017642 <6>[ 0.103638] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10506 11:36:27.024410 <6>[ 0.103654] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10507 11:36:27.030907 <6>[ 0.103701] smp: Brought up 1 node, 8 CPUs
10508 11:36:27.034757 <6>[ 0.245050] SMP: Total of 8 processors activated.
10509 11:36:27.041255 <6>[ 0.249971] CPU features: detected: 32-bit EL0 Support
10510 11:36:27.047248 <6>[ 0.255367] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10511 11:36:27.053847 <6>[ 0.264222] CPU features: detected: Common not Private translations
10512 11:36:27.060841 <6>[ 0.270738] CPU features: detected: CRC32 instructions
10513 11:36:27.067434 <6>[ 0.276090] CPU features: detected: RCpc load-acquire (LDAPR)
10514 11:36:27.073826 <6>[ 0.282087] CPU features: detected: LSE atomic instructions
10515 11:36:27.077009 <6>[ 0.287904] CPU features: detected: Privileged Access Never
10516 11:36:27.083694 <6>[ 0.293720] CPU features: detected: RAS Extension Support
10517 11:36:27.089997 <6>[ 0.299363] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10518 11:36:27.096650 <6>[ 0.306581] CPU: All CPU(s) started at EL2
10519 11:36:27.100226 <6>[ 0.310897] alternatives: applying system-wide alternatives
10520 11:36:27.111375 <6>[ 0.321817] devtmpfs: initialized
10521 11:36:27.126865 <6>[ 0.330688] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10522 11:36:27.133129 <6>[ 0.340650] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10523 11:36:27.139738 <6>[ 0.348900] pinctrl core: initialized pinctrl subsystem
10524 11:36:27.143042 <6>[ 0.355581] DMI not present or invalid.
10525 11:36:27.149558 <6>[ 0.359992] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10526 11:36:27.159704 <6>[ 0.366893] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10527 11:36:27.165974 <6>[ 0.374480] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10528 11:36:27.176131 <6>[ 0.382710] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10529 11:36:27.179768 <6>[ 0.390953] audit: initializing netlink subsys (disabled)
10530 11:36:27.189732 <5>[ 0.396644] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10531 11:36:27.196402 <6>[ 0.397323] thermal_sys: Registered thermal governor 'step_wise'
10532 11:36:27.202402 <6>[ 0.404605] thermal_sys: Registered thermal governor 'power_allocator'
10533 11:36:27.206273 <6>[ 0.410859] cpuidle: using governor menu
10534 11:36:27.212105 <6>[ 0.421821] NET: Registered PF_QIPCRTR protocol family
10535 11:36:27.218806 <6>[ 0.427325] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10536 11:36:27.225303 <6>[ 0.434427] ASID allocator initialised with 32768 entries
10537 11:36:27.228758 <6>[ 0.441002] Serial: AMBA PL011 UART driver
10538 11:36:27.239996 <4>[ 0.450355] Trying to register duplicate clock ID: 134
10539 11:36:27.299463 <6>[ 0.513411] KASLR enabled
10540 11:36:27.313813 <6>[ 0.521026] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10541 11:36:27.320185 <6>[ 0.528042] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10542 11:36:27.327354 <6>[ 0.534529] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10543 11:36:27.333495 <6>[ 0.541535] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10544 11:36:27.340874 <6>[ 0.548020] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10545 11:36:27.346770 <6>[ 0.555021] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10546 11:36:27.353510 <6>[ 0.561508] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10547 11:36:27.360280 <6>[ 0.568513] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10548 11:36:27.363327 <6>[ 0.575988] ACPI: Interpreter disabled.
10549 11:36:27.371857 <6>[ 0.582425] iommu: Default domain type: Translated
10550 11:36:27.378790 <6>[ 0.587577] iommu: DMA domain TLB invalidation policy: strict mode
10551 11:36:27.381867 <5>[ 0.594229] SCSI subsystem initialized
10552 11:36:27.388376 <6>[ 0.598484] usbcore: registered new interface driver usbfs
10553 11:36:27.395396 <6>[ 0.604214] usbcore: registered new interface driver hub
10554 11:36:27.398493 <6>[ 0.609765] usbcore: registered new device driver usb
10555 11:36:27.405246 <6>[ 0.615892] pps_core: LinuxPPS API ver. 1 registered
10556 11:36:27.415209 <6>[ 0.621084] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10557 11:36:27.418626 <6>[ 0.630422] PTP clock support registered
10558 11:36:27.422129 <6>[ 0.634668] EDAC MC: Ver: 3.0.0
10559 11:36:27.429361 <6>[ 0.639862] FPGA manager framework
10560 11:36:27.435899 <6>[ 0.643541] Advanced Linux Sound Architecture Driver Initialized.
10561 11:36:27.439091 <6>[ 0.650343] vgaarb: loaded
10562 11:36:27.446302 <6>[ 0.653505] clocksource: Switched to clocksource arch_sys_counter
10563 11:36:27.448950 <5>[ 0.659954] VFS: Disk quotas dquot_6.6.0
10564 11:36:27.455866 <6>[ 0.664142] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10565 11:36:27.459668 <6>[ 0.671337] pnp: PnP ACPI: disabled
10566 11:36:27.467848 <6>[ 0.678062] NET: Registered PF_INET protocol family
10567 11:36:27.477588 <6>[ 0.683653] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10568 11:36:27.489041 <6>[ 0.695988] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10569 11:36:27.498474 <6>[ 0.704794] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10570 11:36:27.505224 <6>[ 0.712762] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10571 11:36:27.514988 <6>[ 0.721463] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10572 11:36:27.521902 <6>[ 0.731207] TCP: Hash tables configured (established 65536 bind 65536)
10573 11:36:27.527946 <6>[ 0.738080] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10574 11:36:27.538333 <6>[ 0.745277] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10575 11:36:27.544529 <6>[ 0.752979] NET: Registered PF_UNIX/PF_LOCAL protocol family
10576 11:36:27.551388 <6>[ 0.759129] RPC: Registered named UNIX socket transport module.
10577 11:36:27.555255 <6>[ 0.765284] RPC: Registered udp transport module.
10578 11:36:27.561498 <6>[ 0.770215] RPC: Registered tcp transport module.
10579 11:36:27.567604 <6>[ 0.775146] RPC: Registered tcp NFSv4.1 backchannel transport module.
10580 11:36:27.571300 <6>[ 0.781811] PCI: CLS 0 bytes, default 64
10581 11:36:27.574294 <6>[ 0.786178] Unpacking initramfs...
10582 11:36:27.584051 <6>[ 0.789895] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10583 11:36:27.590633 <6>[ 0.798534] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10584 11:36:27.597524 <6>[ 0.807334] kvm [1]: IPA Size Limit: 40 bits
10585 11:36:27.600379 <6>[ 0.811867] kvm [1]: GICv3: no GICV resource entry
10586 11:36:27.607451 <6>[ 0.816889] kvm [1]: disabling GICv2 emulation
10587 11:36:27.613693 <6>[ 0.821572] kvm [1]: GIC system register CPU interface enabled
10588 11:36:27.616713 <6>[ 0.827725] kvm [1]: vgic interrupt IRQ18
10589 11:36:27.623464 <6>[ 0.833571] kvm [1]: VHE mode initialized successfully
10590 11:36:27.630128 <5>[ 0.840009] Initialise system trusted keyrings
10591 11:36:27.636312 <6>[ 0.844776] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10592 11:36:27.644266 <6>[ 0.854740] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10593 11:36:27.650584 <5>[ 0.861096] NFS: Registering the id_resolver key type
10594 11:36:27.654401 <5>[ 0.866391] Key type id_resolver registered
10595 11:36:27.660529 <5>[ 0.870809] Key type id_legacy registered
10596 11:36:27.668008 <6>[ 0.875087] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10597 11:36:27.673997 <6>[ 0.882008] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10598 11:36:27.680919 <6>[ 0.889734] 9p: Installing v9fs 9p2000 file system support
10599 11:36:27.716612 <5>[ 0.927192] Key type asymmetric registered
10600 11:36:27.719637 <5>[ 0.931522] Asymmetric key parser 'x509' registered
10601 11:36:27.729925 <6>[ 0.936665] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10602 11:36:27.733154 <6>[ 0.944284] io scheduler mq-deadline registered
10603 11:36:27.736379 <6>[ 0.949044] io scheduler kyber registered
10604 11:36:27.755368 <6>[ 0.966127] EINJ: ACPI disabled.
10605 11:36:27.788494 <4>[ 0.992561] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 11:36:27.798219 <4>[ 1.003209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 11:36:27.813699 <6>[ 1.024184] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10608 11:36:27.821793 <6>[ 1.032073] printk: console [ttyS0] disabled
10609 11:36:27.849483 <6>[ 1.056703] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10610 11:36:27.856087 <6>[ 1.066204] printk: console [ttyS0] enabled
10611 11:36:27.859269 <6>[ 1.066204] printk: console [ttyS0] enabled
10612 11:36:27.866076 <6>[ 1.075101] printk: bootconsole [mtk8250] disabled
10613 11:36:27.869416 <6>[ 1.075101] printk: bootconsole [mtk8250] disabled
10614 11:36:27.876176 <6>[ 1.086148] SuperH (H)SCI(F) driver initialized
10615 11:36:27.878859 <6>[ 1.091422] msm_serial: driver initialized
10616 11:36:27.893182 <6>[ 1.100398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10617 11:36:27.903036 <6>[ 1.108947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10618 11:36:27.909287 <6>[ 1.117489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10619 11:36:27.919664 <6>[ 1.126116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10620 11:36:27.929135 <6>[ 1.134823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10621 11:36:27.936251 <6>[ 1.143543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10622 11:36:27.945472 <6>[ 1.152084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10623 11:36:27.952218 <6>[ 1.160880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10624 11:36:27.962522 <6>[ 1.169422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10625 11:36:27.974342 <6>[ 1.185006] loop: module loaded
10626 11:36:27.980849 <6>[ 1.190912] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10627 11:36:28.003503 <4>[ 1.214248] mtk-pmic-keys: Failed to locate of_node [id: -1]
10628 11:36:28.010301 <6>[ 1.221057] megasas: 07.719.03.00-rc1
10629 11:36:28.020162 <6>[ 1.230754] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10630 11:36:28.030201 <6>[ 1.240894] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10631 11:36:28.047223 <6>[ 1.257582] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10632 11:36:28.107706 <6>[ 1.311727] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10633 11:36:28.375493 <6>[ 1.585926] Freeing initrd memory: 18280K
10634 11:36:28.386924 <6>[ 1.597632] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10635 11:36:28.397924 <6>[ 1.608625] tun: Universal TUN/TAP device driver, 1.6
10636 11:36:28.401258 <6>[ 1.614697] thunder_xcv, ver 1.0
10637 11:36:28.404477 <6>[ 1.618200] thunder_bgx, ver 1.0
10638 11:36:28.407872 <6>[ 1.621695] nicpf, ver 1.0
10639 11:36:28.419256 <6>[ 1.625755] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10640 11:36:28.421569 <6>[ 1.633231] hns3: Copyright (c) 2017 Huawei Corporation.
10641 11:36:28.428537 <6>[ 1.638822] hclge is initializing
10642 11:36:28.431768 <6>[ 1.642397] e1000: Intel(R) PRO/1000 Network Driver
10643 11:36:28.438850 <6>[ 1.647527] e1000: Copyright (c) 1999-2006 Intel Corporation.
10644 11:36:28.441580 <6>[ 1.653546] e1000e: Intel(R) PRO/1000 Network Driver
10645 11:36:28.448116 <6>[ 1.658762] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10646 11:36:28.455493 <6>[ 1.664947] igb: Intel(R) Gigabit Ethernet Network Driver
10647 11:36:28.461637 <6>[ 1.670597] igb: Copyright (c) 2007-2014 Intel Corporation.
10648 11:36:28.468151 <6>[ 1.676434] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10649 11:36:28.474845 <6>[ 1.682953] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10650 11:36:28.478303 <6>[ 1.689421] sky2: driver version 1.30
10651 11:36:28.485026 <6>[ 1.694368] usbcore: registered new device driver r8152-cfgselector
10652 11:36:28.491400 <6>[ 1.700904] usbcore: registered new interface driver r8152
10653 11:36:28.497674 <6>[ 1.706730] VFIO - User Level meta-driver version: 0.3
10654 11:36:28.504560 <6>[ 1.714974] usbcore: registered new interface driver usb-storage
10655 11:36:28.511310 <6>[ 1.721422] usbcore: registered new device driver onboard-usb-hub
10656 11:36:28.519863 <6>[ 1.730659] mt6397-rtc mt6359-rtc: registered as rtc0
10657 11:36:28.529661 <6>[ 1.736128] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:36:28 UTC (1721216188)
10658 11:36:28.533153 <6>[ 1.745737] i2c_dev: i2c /dev entries driver
10659 11:36:28.547288 <4>[ 1.757917] cpu cpu0: supply cpu not found, using dummy regulator
10660 11:36:28.553856 <4>[ 1.764344] cpu cpu1: supply cpu not found, using dummy regulator
10661 11:36:28.560359 <4>[ 1.770750] cpu cpu2: supply cpu not found, using dummy regulator
10662 11:36:28.567027 <4>[ 1.777153] cpu cpu3: supply cpu not found, using dummy regulator
10663 11:36:28.573526 <4>[ 1.783550] cpu cpu4: supply cpu not found, using dummy regulator
10664 11:36:28.580517 <4>[ 1.789968] cpu cpu5: supply cpu not found, using dummy regulator
10665 11:36:28.586860 <4>[ 1.796366] cpu cpu6: supply cpu not found, using dummy regulator
10666 11:36:28.593397 <4>[ 1.802764] cpu cpu7: supply cpu not found, using dummy regulator
10667 11:36:28.612721 <6>[ 1.823403] cpu cpu0: EM: created perf domain
10668 11:36:28.615797 <6>[ 1.828357] cpu cpu4: EM: created perf domain
10669 11:36:28.623568 <6>[ 1.834028] sdhci: Secure Digital Host Controller Interface driver
10670 11:36:28.630057 <6>[ 1.840457] sdhci: Copyright(c) Pierre Ossman
10671 11:36:28.637498 <6>[ 1.845414] Synopsys Designware Multimedia Card Interface Driver
10672 11:36:28.643004 <6>[ 1.852060] sdhci-pltfm: SDHCI platform and OF driver helper
10673 11:36:28.646557 <6>[ 1.852081] mmc0: CQHCI version 5.10
10674 11:36:28.653488 <6>[ 1.862428] ledtrig-cpu: registered to indicate activity on CPUs
10675 11:36:28.659866 <6>[ 1.869486] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10676 11:36:28.666650 <6>[ 1.876536] usbcore: registered new interface driver usbhid
10677 11:36:28.669859 <6>[ 1.882358] usbhid: USB HID core driver
10678 11:36:28.679418 <6>[ 1.886570] spi_master spi0: will run message pump with realtime priority
10679 11:36:28.722607 <6>[ 1.926519] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10680 11:36:28.741923 <6>[ 1.942594] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10681 11:36:28.745068 <6>[ 1.955033] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10682 11:36:28.753983 <6>[ 1.964427] cros-ec-spi spi0.0: Chrome EC device registered
10683 11:36:28.760898 <6>[ 1.970413] mmc0: Command Queue Engine enabled
10684 11:36:28.767116 <6>[ 1.975138] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10685 11:36:28.770107 <6>[ 1.982744] mmcblk0: mmc0:0001 DA4128 116 GiB
10686 11:36:28.780593 <6>[ 1.991294] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10687 11:36:28.787892 <6>[ 1.998543] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10688 11:36:28.794589 <6>[ 2.004543] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10689 11:36:28.804438 <6>[ 2.010444] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10690 11:36:28.810726 <6>[ 2.010508] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10691 11:36:28.814319 <6>[ 2.021277] NET: Registered PF_PACKET protocol family
10692 11:36:28.821247 <6>[ 2.031695] 9pnet: Installing 9P2000 support
10693 11:36:28.824032 <5>[ 2.036275] Key type dns_resolver registered
10694 11:36:28.830856 <6>[ 2.041276] registered taskstats version 1
10695 11:36:28.834132 <5>[ 2.045658] Loading compiled-in X.509 certificates
10696 11:36:28.865542 <4>[ 2.069766] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10697 11:36:28.875450 <4>[ 2.080496] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10698 11:36:28.890819 <6>[ 2.101525] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10699 11:36:28.897718 <6>[ 2.108515] xhci-mtk 11200000.usb: xHCI Host Controller
10700 11:36:28.904229 <6>[ 2.114016] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10701 11:36:28.914548 <6>[ 2.121868] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10702 11:36:28.921098 <6>[ 2.131300] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10703 11:36:28.927877 <6>[ 2.137476] xhci-mtk 11200000.usb: xHCI Host Controller
10704 11:36:28.934135 <6>[ 2.142968] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10705 11:36:28.940625 <6>[ 2.150625] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10706 11:36:28.947517 <6>[ 2.158440] hub 1-0:1.0: USB hub found
10707 11:36:28.951164 <6>[ 2.162464] hub 1-0:1.0: 1 port detected
10708 11:36:28.960725 <6>[ 2.166761] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10709 11:36:28.964241 <6>[ 2.175463] hub 2-0:1.0: USB hub found
10710 11:36:28.967605 <6>[ 2.179503] hub 2-0:1.0: 1 port detected
10711 11:36:28.976045 <6>[ 2.186620] mtk-msdc 11f70000.mmc: Got CD GPIO
10712 11:36:28.989382 <6>[ 2.196499] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10713 11:36:28.999138 <6>[ 2.204897] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10714 11:36:29.005207 <6>[ 2.213238] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10715 11:36:29.015597 <6>[ 2.221579] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10716 11:36:29.022107 <6>[ 2.229919] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10717 11:36:29.032104 <6>[ 2.238258] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10718 11:36:29.038717 <6>[ 2.246599] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10719 11:36:29.048435 <6>[ 2.254937] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10720 11:36:29.054896 <6>[ 2.263279] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10721 11:36:29.065085 <6>[ 2.271618] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10722 11:36:29.071393 <6>[ 2.279957] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10723 11:36:29.081426 <6>[ 2.288300] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10724 11:36:29.088182 <6>[ 2.296639] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10725 11:36:29.098208 <6>[ 2.304977] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10726 11:36:29.104535 <6>[ 2.313316] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10727 11:36:29.111235 <6>[ 2.322062] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10728 11:36:29.118277 <6>[ 2.329223] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10729 11:36:29.125046 <6>[ 2.335992] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10730 11:36:29.136302 <6>[ 2.342800] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10731 11:36:29.141930 <6>[ 2.349733] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10732 11:36:29.148715 <6>[ 2.356598] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10733 11:36:29.158374 <6>[ 2.365747] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10734 11:36:29.168359 <6>[ 2.374870] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10735 11:36:29.177832 <6>[ 2.384165] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10736 11:36:29.188169 <6>[ 2.393632] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10737 11:36:29.197832 <6>[ 2.403099] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10738 11:36:29.204642 <6>[ 2.412219] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10739 11:36:29.214180 <6>[ 2.421687] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10740 11:36:29.224126 <6>[ 2.430807] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10741 11:36:29.234245 <6>[ 2.440103] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10742 11:36:29.244132 <6>[ 2.450264] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10743 11:36:29.254191 <6>[ 2.461915] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10744 11:36:29.262097 <6>[ 2.473075] Trying to probe devices needed for running init ...
10745 11:36:29.272732 <3>[ 2.480201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10746 11:36:29.382105 <6>[ 2.589792] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10747 11:36:29.536836 <6>[ 2.747464] hub 1-1:1.0: USB hub found
10748 11:36:29.539839 <6>[ 2.751968] hub 1-1:1.0: 4 ports detected
10749 11:36:29.549993 <6>[ 2.760762] hub 1-1:1.0: USB hub found
10750 11:36:29.553021 <6>[ 2.765131] hub 1-1:1.0: 4 ports detected
10751 11:36:29.662418 <6>[ 2.870071] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10752 11:36:29.688863 <6>[ 2.899652] hub 2-1:1.0: USB hub found
10753 11:36:29.691979 <6>[ 2.904150] hub 2-1:1.0: 3 ports detected
10754 11:36:29.704124 <6>[ 2.914814] hub 2-1:1.0: USB hub found
10755 11:36:29.707636 <6>[ 2.919260] hub 2-1:1.0: 3 ports detected
10756 11:36:29.874403 <6>[ 3.081821] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10757 11:36:30.006762 <6>[ 3.217698] hub 1-1.4:1.0: USB hub found
10758 11:36:30.010390 <6>[ 3.222381] hub 1-1.4:1.0: 2 ports detected
10759 11:36:30.022851 <6>[ 3.233892] hub 1-1.4:1.0: USB hub found
10760 11:36:30.026196 <6>[ 3.238484] hub 1-1.4:1.0: 2 ports detected
10761 11:36:30.090499 <6>[ 3.298035] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10762 11:36:30.198661 <6>[ 3.406447] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10763 11:36:30.234929 <4>[ 3.442638] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10764 11:36:30.245248 <4>[ 3.451724] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10765 11:36:30.280443 <6>[ 3.491241] r8152 2-1.3:1.0 eth0: v1.12.13
10766 11:36:30.321934 <6>[ 3.529586] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10767 11:36:30.514144 <6>[ 3.721843] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10768 11:36:32.053458 <6>[ 5.264731] r8152 2-1.3:1.0 eth0: carrier on
10769 11:36:34.870770 <5>[ 5.289620] Sending DHCP requests .., OK
10770 11:36:34.876796 <6>[ 8.085981] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10771 11:36:34.880178 <6>[ 8.094293] IP-Config: Complete:
10772 11:36:34.893969 <6>[ 8.097787] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10773 11:36:34.899911 <6>[ 8.108492] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10774 11:36:34.909650 <6>[ 8.117106] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10775 11:36:34.913489 <6>[ 8.117115] nameserver0=192.168.201.1
10776 11:36:34.916404 <6>[ 8.129274] clk: Disabling unused clocks
10777 11:36:34.920144 <6>[ 8.134787] ALSA device list:
10778 11:36:34.926454 <6>[ 8.138067] No soundcards found.
10779 11:36:34.934483 <6>[ 8.145636] Freeing unused kernel memory: 8512K
10780 11:36:34.937388 <6>[ 8.150534] Run /init as init process
10781 11:36:34.947109 Loading, please wait...
10782 11:36:34.979669 Starting systemd-udevd version 252.22-1~deb12u1
10783 11:36:35.227254 <6>[ 8.435386] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10784 11:36:35.247123 <6>[ 8.454870] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10785 11:36:35.256948 <6>[ 8.463846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10786 11:36:35.263317 <6>[ 8.472472] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10787 11:36:35.269776 <6>[ 8.477358] remoteproc remoteproc0: scp is available
10788 11:36:35.276421 <6>[ 8.477643] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10789 11:36:35.283524 <6>[ 8.478353] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10790 11:36:35.292911 <6>[ 8.478931] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10791 11:36:35.302568 <6>[ 8.478941] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10792 11:36:35.309078 <3>[ 8.479657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 11:36:35.316215 <3>[ 8.479670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 11:36:35.326416 <3>[ 8.479674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 11:36:35.332689 <3>[ 8.479864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 11:36:35.343211 <3>[ 8.479880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 11:36:35.349823 <3>[ 8.479889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 11:36:35.359804 <3>[ 8.479902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 11:36:35.365761 <3>[ 8.479911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 11:36:35.376402 <3>[ 8.479963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 11:36:35.382863 <3>[ 8.480028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 11:36:35.392160 <3>[ 8.480038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 11:36:35.398936 <3>[ 8.480048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 11:36:35.405366 <3>[ 8.480111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 11:36:35.415360 <3>[ 8.480121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 11:36:35.421801 <3>[ 8.480129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 11:36:35.431859 <3>[ 8.480139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 11:36:35.438448 <3>[ 8.480146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 11:36:35.448660 <3>[ 8.480187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 11:36:35.454988 <4>[ 8.480574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10811 11:36:35.461568 <6>[ 8.485639] remoteproc remoteproc0: powering up scp
10812 11:36:35.468444 <6>[ 8.493753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10813 11:36:35.478350 <6>[ 8.500790] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10814 11:36:35.484510 <6>[ 8.510085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10815 11:36:35.494555 <4>[ 8.513736] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10816 11:36:35.501782 <4>[ 8.513736] Fallback method does not support PEC.
10817 11:36:35.504773 <6>[ 8.515755] mc: Linux media interface: v0.10
10818 11:36:35.510987 <6>[ 8.518303] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10819 11:36:35.518004 <6>[ 8.527933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10820 11:36:35.527741 <3>[ 8.529345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 11:36:35.534420 <4>[ 8.545550] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10822 11:36:35.540588 <6>[ 8.550778] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10823 11:36:35.547316 <4>[ 8.562699] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10824 11:36:35.557112 <6>[ 8.567355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10825 11:36:35.564518 <6>[ 8.572693] videodev: Linux video capture interface: v2.00
10826 11:36:35.570672 <6>[ 8.595218] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10827 11:36:35.576909 <6>[ 8.599233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10828 11:36:35.583722 <6>[ 8.607485] pci_bus 0000:00: root bus resource [bus 00-ff]
10829 11:36:35.593707 <3>[ 8.615431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 11:36:35.603473 <6>[ 8.654885] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10831 11:36:35.610392 <6>[ 8.655967] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10832 11:36:35.616555 <6>[ 8.660162] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10833 11:36:35.626622 <6>[ 8.664005] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10834 11:36:35.636718 <6>[ 8.670187] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10835 11:36:35.647556 <6>[ 8.673007] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10836 11:36:35.649700 <6>[ 8.673065] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10837 11:36:35.659338 <6>[ 8.674395] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10838 11:36:35.666486 <6>[ 8.676117] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10839 11:36:35.672844 <6>[ 8.678168] remoteproc remoteproc0: remote processor scp is now up
10840 11:36:35.683195 <6>[ 8.680651] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10841 11:36:35.689357 <6>[ 8.686228] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10842 11:36:35.695866 <6>[ 8.721719] Bluetooth: Core ver 2.22
10843 11:36:35.699173 <6>[ 8.726432] pci 0000:00:00.0: supports D1 D2
10844 11:36:35.706131 <6>[ 8.734366] NET: Registered PF_BLUETOOTH protocol family
10845 11:36:35.712349 <6>[ 8.743043] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10846 11:36:35.718962 <6>[ 8.744288] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10847 11:36:35.725903 <6>[ 8.744613] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10848 11:36:35.738431 <6>[ 8.745715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10849 11:36:35.745201 <6>[ 8.745852] usbcore: registered new interface driver uvcvideo
10850 11:36:35.752508 <6>[ 8.750478] Bluetooth: HCI device and connection manager initialized
10851 11:36:35.758551 <6>[ 8.758321] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10852 11:36:35.761662 <6>[ 8.765510] Bluetooth: HCI socket layer initialized
10853 11:36:35.768864 <6>[ 8.766145] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10854 11:36:35.778305 <6>[ 8.773352] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10855 11:36:35.785064 <6>[ 8.773371] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10856 11:36:35.788614 <6>[ 8.779243] Bluetooth: L2CAP socket layer initialized
10857 11:36:35.798292 <6>[ 8.785970] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10858 11:36:35.801634 <6>[ 8.795086] Bluetooth: SCO socket layer initialized
10859 11:36:35.808091 <6>[ 8.800910] pci 0000:01:00.0: supports D1 D2
10860 11:36:35.811401 <6>[ 8.861764] usbcore: registered new interface driver btusb
10861 11:36:35.824587 <4>[ 8.862934] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10862 11:36:35.827825 <3>[ 8.862946] Bluetooth: hci0: Failed to load firmware file (-2)
10863 11:36:35.834271 <3>[ 8.862951] Bluetooth: hci0: Failed to set up firmware (-2)
10864 11:36:35.844192 <4>[ 8.862956] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10865 11:36:35.851500 <6>[ 8.867507] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10866 11:36:35.858365 <6>[ 8.877697] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10867 11:36:35.867780 <6>[ 9.075819] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10868 11:36:35.874272 <6>[ 9.083900] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10869 11:36:35.884706 <6>[ 9.091897] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10870 11:36:35.890925 <6>[ 9.099898] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10871 11:36:35.900795 <6>[ 9.107898] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10872 11:36:35.903909 <6>[ 9.115898] pci 0000:00:00.0: PCI bridge to [bus 01]
10873 11:36:35.914018 <6>[ 9.121115] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10874 11:36:35.920416 <6>[ 9.129239] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10875 11:36:35.926840 <6>[ 9.136038] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10876 11:36:35.933442 <6>[ 9.142981] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10877 11:36:35.949467 <5>[ 9.158063] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10878 11:36:35.971526 <5>[ 9.179757] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10879 11:36:35.978260 <5>[ 9.186856] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10880 11:36:35.987976 <4>[ 9.195277] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10881 11:36:35.991721 <6>[ 9.204149] cfg80211: failed to load regulatory.db
10882 11:36:36.041283 <6>[ 9.249293] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10883 11:36:36.047524 <6>[ 9.256871] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10884 11:36:36.070306 <6>[ 9.281719] mt7921e 0000:01:00.0: ASIC revision: 79610010
10885 11:36:36.173439 <6>[ 9.381315] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10886 11:36:36.176268 <6>[ 9.381315]
10887 11:36:36.185503 Begin: Loading essential drivers ... done.
10888 11:36:36.189027 Begin: Running /scripts/init-premount ... done.
10889 11:36:36.195594 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10890 11:36:36.205171 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10891 11:36:36.208978 Device /sys/class/net/eth0 found
10892 11:36:36.209074 done.
10893 11:36:36.215190 Begin: Waiting up to 180 secs for any network device to become available ... done.
10894 11:36:36.262394 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10895 11:36:36.269440 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10896 11:36:36.276259 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10897 11:36:36.282894 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10898 11:36:36.289701 host : mt8192-asurada-spherion-r0-cbg-9
10899 11:36:36.295961 domain : lava-rack
10900 11:36:36.299268 rootserver: 192.168.201.1 rootpath:
10901 11:36:36.302972 filename :
10902 11:36:36.327820 done.
10903 11:36:36.334736 Begin: Running /scripts/nfs-bottom ... done.
10904 11:36:36.351992 Begin: Running /scripts/init-bottom ... done.
10905 11:36:36.440200 <6>[ 9.647933] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10906 11:36:37.715103 <6>[ 10.926704] NET: Registered PF_INET6 protocol family
10907 11:36:37.722455 <6>[ 10.934237] Segment Routing with IPv6
10908 11:36:37.725497 <6>[ 10.938241] In-situ OAM (IOAM) with IPv6
10909 11:36:37.904390 <30>[ 11.086351] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10910 11:36:37.907260 <30>[ 11.119481] systemd[1]: Detected architecture arm64.
10911 11:36:37.918103
10912 11:36:37.920562 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10913 11:36:37.920657
10914 11:36:37.943921 <30>[ 11.155575] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10915 11:36:39.050429 <30>[ 12.259167] systemd[1]: Queued start job for default target graphical.target.
10916 11:36:39.090388 <30>[ 12.298788] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10917 11:36:39.096809 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10918 11:36:39.119035 <30>[ 12.327669] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10919 11:36:39.129049 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10920 11:36:39.147335 <30>[ 12.355549] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10921 11:36:39.156313 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10922 11:36:39.174873 <30>[ 12.383302] systemd[1]: Created slice user.slice - User and Session Slice.
10923 11:36:39.181306 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10924 11:36:39.205324 <30>[ 12.410669] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10925 11:36:39.215084 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10926 11:36:39.232787 <30>[ 12.438088] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10927 11:36:39.239351 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10928 11:36:39.268247 <30>[ 12.466388] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10929 11:36:39.277792 <30>[ 12.486318] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10930 11:36:39.284117 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10931 11:36:39.301271 <30>[ 12.510192] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10932 11:36:39.312055 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10933 11:36:39.329809 <30>[ 12.538333] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10934 11:36:39.339951 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10935 11:36:39.354353 <30>[ 12.566335] systemd[1]: Reached target paths.target - Path Units.
10936 11:36:39.364769 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10937 11:36:39.381675 <30>[ 12.590276] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10938 11:36:39.388295 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10939 11:36:39.401770 <30>[ 12.613801] systemd[1]: Reached target slices.target - Slice Units.
10940 11:36:39.411834 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10941 11:36:39.426404 <30>[ 12.638300] systemd[1]: Reached target swap.target - Swaps.
10942 11:36:39.432927 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10943 11:36:39.454199 <30>[ 12.662316] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10944 11:36:39.463744 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10945 11:36:39.482113 <30>[ 12.690709] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10946 11:36:39.491848 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10947 11:36:39.513058 <30>[ 12.721761] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10948 11:36:39.523638 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10949 11:36:39.543214 <30>[ 12.751453] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10950 11:36:39.552641 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10951 11:36:39.570004 <30>[ 12.778497] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10952 11:36:39.576451 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10953 11:36:39.594826 <30>[ 12.803432] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10954 11:36:39.604607 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10955 11:36:39.624389 <30>[ 12.833008] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10956 11:36:39.634091 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10957 11:36:39.649464 <30>[ 12.858303] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10958 11:36:39.659648 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10959 11:36:39.709383 <30>[ 12.918221] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10960 11:36:39.715909 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10961 11:36:39.735389 <30>[ 12.944260] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10962 11:36:39.742090 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10963 11:36:39.765165 <30>[ 12.973584] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10964 11:36:39.771641 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10965 11:36:39.796645 <30>[ 12.998398] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10966 11:36:39.811996 <30>[ 13.020483] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10967 11:36:39.821959 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10968 11:36:39.842683 <30>[ 13.051390] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10969 11:36:39.852380 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10970 11:36:39.874495 <30>[ 13.083290] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10971 11:36:39.881127 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10972 11:36:39.906811 <30>[ 13.115368] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10973 11:36:39.920217 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 13.128534] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10974 11:36:39.923290 l Module drm...
10975 11:36:39.946804 <30>[ 13.155485] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10976 11:36:39.956700 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10977 11:36:39.978850 <30>[ 13.187425] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10978 11:36:39.985268 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10979 11:36:40.010809 <30>[ 13.219449] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10980 11:36:40.021027 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 13.233681] fuse: init (API version 7.37)
10981 11:36:40.024221 .
10982 11:36:40.050844 <30>[ 13.259507] systemd[1]: Starting systemd-journald.service - Journal Service...
10983 11:36:40.057246 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10984 11:36:40.090361 <30>[ 13.299254] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10985 11:36:40.097112 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10986 11:36:40.126489 <30>[ 13.331769] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10987 11:36:40.132755 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10988 11:36:40.159829 <30>[ 13.368081] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10989 11:36:40.169415 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10990 11:36:40.192699 <30>[ 13.401083] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10991 11:36:40.206375 Starting [0;1;39msystemd-udev-trig…[<3>[ 13.412981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 11:36:40.209907 0m - Coldplug All udev Devices...
10993 11:36:40.234023 <30>[ 13.442307] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10994 11:36:40.240314 <3>[ 13.445866] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 11:36:40.250339 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10996 11:36:40.269471 <30>[ 13.478333] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10997 11:36:40.276727 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10998 11:36:40.286819 <3>[ 13.494870] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 11:36:40.293225 <30>[ 13.504104] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11000 11:36:40.303853 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11001 11:36:40.314745 <3>[ 13.523709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 11:36:40.324991 <30>[ 13.533426] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11003 11:36:40.335809 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11004 11:36:40.345421 <3>[ 13.552940] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 11:36:40.355279 <30>[ 13.563668] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11006 11:36:40.361979 <30>[ 13.571759] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11007 11:36:40.375773 [[0;32m OK [0m] Finished [0<3>[ 13.583053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 11:36:40.381933 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11009 11:36:40.399420 <30>[ 13.607673] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11010 11:36:40.405730 <3>[ 13.613033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 11:36:40.415612 <30>[ 13.615811] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11012 11:36:40.423099 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11013 11:36:40.437134 <3>[ 13.645875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 11:36:40.448046 <30>[ 13.656866] systemd[1]: modprobe@drm.service: Deactivated successfully.
11015 11:36:40.454680 <30>[ 13.664688] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11016 11:36:40.468212 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.675975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 11:36:40.471401 rm.service[0m - Load Kernel Module drm.
11018 11:36:40.491147 <30>[ 13.699564] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11019 11:36:40.497691 <3>[ 13.706982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 11:36:40.507523 <30>[ 13.708186] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11021 11:36:40.517589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11022 11:36:40.533361 <3>[ 13.741673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 11:36:40.539253 <30>[ 13.742808] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11024 11:36:40.549726 <30>[ 13.758440] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11025 11:36:40.563755 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m <3>[ 13.771816] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 11:36:40.566771 - Load Kernel Module fuse.
11027 11:36:40.590752 <30>[ 13.798854] systemd[1]: modprobe@loop.service: Deactivated successfully.
11028 11:36:40.597049 <30>[ 13.806713] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11029 11:36:40.607309 <3>[ 13.813155] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 11:36:40.614178 <3>[ 13.814100] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11031 11:36:40.629872 <4>[ 13.814116] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11032 11:36:40.636502 <3>[ 13.814118] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
11033 11:36:40.646394 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11034 11:36:40.666532 <30>[ 13.875079] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11035 11:36:40.673195 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11036 11:36:40.697083 <30>[ 13.902406] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11037 11:36:40.704115 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11038 11:36:40.721929 <30>[ 13.930280] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11039 11:36:40.731703 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11040 11:36:40.749583 <30>[ 13.958372] systemd[1]: Started systemd-journald.service - Journal Service.
11041 11:36:40.756113 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11042 11:36:40.777730 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11043 11:36:40.796046 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11044 11:36:40.850317 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11045 11:36:40.873106 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11046 11:36:40.895413 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11047 11:36:40.919046 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11048 11:36:40.952226 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11049 11:36:40.961994 <46>[ 14.170961] systemd-journald[309]: Received client request to flush runtime journal.
11050 11:36:40.975531 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11051 11:36:41.005989 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11052 11:36:41.025785 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11053 11:36:41.046796 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11054 11:36:41.385885 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11055 11:36:42.077254 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11056 11:36:42.113268 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11057 11:36:42.381191 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11058 11:36:42.488203 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11059 11:36:42.505217 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11060 11:36:42.520856 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11061 11:36:42.582132 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11062 11:36:42.609930 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11063 11:36:42.862556 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11064 11:36:42.928440 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11065 11:36:42.952533 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11066 11:36:43.287342 [[0;32m OK [<6>[ 16.496309] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11067 11:36:43.294036 0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11068 11:36:43.349247 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11069 11:36:43.369928 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11070 11:36:43.413915 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11071 11:36:43.498089 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11072 11:36:43.520214 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11073 11:36:43.543363 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11074 11:36:43.563843 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11075 11:36:43.598282 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11076 11:36:43.617184 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11077 11:36:43.690125 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11078 11:36:43.720452 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11079 11:36:43.761994 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11080 11:36:43.781096 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11081 11:36:43.797057 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11082 11:36:43.813177 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11083 11:36:43.828862 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11084 11:36:43.854209 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11085 11:36:43.880071 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11086 11:36:43.896734 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11087 11:36:43.915822 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11088 11:36:43.936436 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11089 11:36:43.952778 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11090 11:36:43.971003 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11091 11:36:43.989194 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11092 11:36:44.005311 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11093 11:36:44.049414 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11094 11:36:44.093230 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11095 11:36:44.183576 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11096 11:36:44.210164 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11097 11:36:44.254513 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11098 11:36:44.297877 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11099 11:36:44.339027 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11100 11:36:44.358113 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11101 11:36:44.464148 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11102 11:36:44.526992 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11103 11:36:44.551768 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11104 11:36:44.574393 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11105 11:36:44.595185 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11106 11:36:44.656870 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11107 11:36:44.700649 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11108 11:36:44.774087
11109 11:36:44.777322 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11110 11:36:44.777410
11111 11:36:44.780685 debian-bookworm-arm64 login: root (automatic login)
11112 11:36:44.780765
11113 11:36:45.106889 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11114 11:36:45.107015
11115 11:36:45.114244 The programs included with the Debian GNU/Linux system are free software;
11116 11:36:45.120299 the exact distribution terms for each program are described in the
11117 11:36:45.123221 individual files in /usr/share/doc/*/copyright.
11118 11:36:45.123357
11119 11:36:45.129841 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11120 11:36:45.133686 permitted by applicable law.
11121 11:36:46.281077 Matched prompt #10: / #
11123 11:36:46.281425 Setting prompt string to ['/ #']
11124 11:36:46.281544 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11126 11:36:46.281831 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11127 11:36:46.281951 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11128 11:36:46.282039 Setting prompt string to ['/ #']
11129 11:36:46.282170 Forcing a shell prompt, looking for ['/ #']
11130 11:36:46.282278 Sending line: ''
11132 11:36:46.332757 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11133 11:36:46.332845 Waiting using forced prompt support (timeout 00:02:30)
11134 11:36:46.337131 / #
11135 11:36:46.337442 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11136 11:36:46.337566 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11137 11:36:46.337670 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k'"
11139 11:36:46.443338 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864600/extract-nfsrootfs-d96773_k'
11140 11:36:46.443625 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11142 11:36:46.548897 / # export NFS_SERVER_IP='192.168.201.1'
11143 11:36:46.549199 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11144 11:36:46.549313 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11145 11:36:46.549427 end: 2 depthcharge-action (duration 00:01:48) [common]
11146 11:36:46.549544 start: 3 lava-test-retry (timeout 00:07:33) [common]
11147 11:36:46.549652 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11148 11:36:46.549751 Using namespace: common
11149 11:36:46.549848 Sending line: '#'
11151 11:36:46.650301 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11152 11:36:46.654977 / # #
11153 11:36:46.655239 Using /lava-14864600
11154 11:36:46.655302 Sending line: 'export SHELL=/bin/bash'
11156 11:36:46.760523 / # export SHELL=/bin/bash
11157 11:36:46.760796 Sending line: '. /lava-14864600/environment'
11159 11:36:46.866125 / # . /lava-14864600/environment
11160 11:36:46.872223 Sending line: '/lava-14864600/bin/lava-test-runner /lava-14864600/0'
11162 11:36:46.972771 Test shell timeout: 10s (minimum of the action and connection timeout)
11163 11:36:46.977675 / # /lava-14864600/bin/lava-test-runner /lava-14864600/0
11164 11:36:47.251469 + export TESTRUN_ID=0_timesync-off
11165 11:36:47.254413 + TESTRUN_ID=0_timesync-off
11166 11:36:47.258214 + cd /lava-14864600/0/tests/0_timesync-off
11167 11:36:47.260989 ++ cat uuid
11168 11:36:47.266895 + UUID=14864600_1.6.2.3.1
11169 11:36:47.266991 + set +x
11170 11:36:47.273531 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14864600_1.6.2.3.1>
11171 11:36:47.273812 Received signal: <STARTRUN> 0_timesync-off 14864600_1.6.2.3.1
11172 11:36:47.273903 Starting test lava.0_timesync-off (14864600_1.6.2.3.1)
11173 11:36:47.273986 Skipping test definition patterns.
11174 11:36:47.277111 + systemctl stop systemd-timesyncd
11175 11:36:47.341080 + set +x
11176 11:36:47.344187 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14864600_1.6.2.3.1>
11177 11:36:47.344464 Received signal: <ENDRUN> 0_timesync-off 14864600_1.6.2.3.1
11178 11:36:47.344588 Ending use of test pattern.
11179 11:36:47.344646 Ending test lava.0_timesync-off (14864600_1.6.2.3.1), duration 0.07
11181 11:36:47.425532 + export TESTRUN_ID=1_kselftest-rtc
11182 11:36:47.429032 + TESTRUN_ID=1_kselftest-rtc
11183 11:36:47.432410 + cd /lava-14864600/0/tests/1_kselftest-rtc
11184 11:36:47.435311 ++ cat uuid
11185 11:36:47.439820 + UUID=14864600_1.6.2.3.5
11186 11:36:47.439912 + set +x
11187 11:36:47.446392 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14864600_1.6.2.3.5>
11188 11:36:47.446670 Received signal: <STARTRUN> 1_kselftest-rtc 14864600_1.6.2.3.5
11189 11:36:47.446737 Starting test lava.1_kselftest-rtc (14864600_1.6.2.3.5)
11190 11:36:47.446811 Skipping test definition patterns.
11191 11:36:47.449530 + cd ./automated/linux/kselftest/
11192 11:36:47.479504 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
11193 11:36:47.517535 INFO: install_deps skipped
11194 11:36:48.022598 --2024-07-17 11:36:47-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kselftest.tar.xz
11195 11:36:48.029412 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11196 11:36:48.158422 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11197 11:36:48.287947 HTTP request sent, awaiting response... 200 OK
11198 11:36:48.291595 Length: 1920476 (1.8M) [application/octet-stream]
11199 11:36:48.294575 Saving to: 'kselftest_armhf.tar.gz'
11200 11:36:48.294675
11201 11:36:48.294762
11202 11:36:48.547147 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11203 11:36:48.805634 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11204 11:36:49.193114 kselftest_armhf.tar 11%[=> ] 217.50K 421KB/s
11205 11:36:49.327158 kselftest_armhf.tar 45%[========> ] 851.00K 941KB/s
11206 11:36:49.333337 kselftest_armhf.tar 100%[===================>] 1.83M 1.76MB/s in 1.0s
11207 11:36:49.333448
11208 11:36:49.502442 2024-07-17 11:36:49 (1.76 MB/s) - 'kselftest_armhf.tar.gz' saved [1920476/1920476]
11209 11:36:49.502599
11210 11:36:56.466704 skiplist:
11211 11:36:56.469923 ========================================
11212 11:36:56.473444 ========================================
11213 11:36:56.521383 rtc:rtctest
11214 11:36:56.542864 ============== Tests to run ===============
11215 11:36:56.543027 rtc:rtctest
11216 11:36:56.545911 ===========End Tests to run ===============
11217 11:36:56.550378 shardfile-rtc pass
11218 11:36:56.660056 <12>[ 29.873538] kselftest: Running tests in rtc
11219 11:36:56.670095 TAP version 13
11220 11:36:56.685503 1..1
11221 11:36:56.719356 # selftests: rtc: rtctest
11222 11:36:57.165950 # TAP version 13
11223 11:36:57.166079 # 1..8
11224 11:36:57.169697 # # Starting 8 tests from 2 test cases.
11225 11:36:57.172526 # # RUN rtc.date_read ...
11226 11:36:57.179436 # # rtctest.c:49:date_read:Current RTC date/time is 17/07/2024 11:36:56.
11227 11:36:57.182415 # # OK rtc.date_read
11228 11:36:57.185740 # ok 1 rtc.date_read
11229 11:36:57.188967 # # RUN rtc.date_read_loop ...
11230 11:36:57.198643 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11231 11:37:06.796019 <6>[ 40.013664] vpu: disabling
11232 11:37:06.798894 <6>[ 40.016769] vproc2: disabling
11233 11:37:06.802539 <6>[ 40.020594] vproc1: disabling
11234 11:37:06.806567 <6>[ 40.024638] vaud18: disabling
11235 11:37:06.814156 <6>[ 40.028756] vsram_others: disabling
11236 11:37:06.817037 <6>[ 40.032956] va09: disabling
11237 11:37:06.820438 <6>[ 40.036337] vsram_md: disabling
11238 11:37:06.824129 <6>[ 40.040464] Vgpu: disabling
11239 11:37:26.942211 # # rtctest.c:115:date_read_loop:Performed 2610 RTC time reads.
11240 11:37:26.945746 # # OK rtc.date_read_loop
11241 11:37:26.948941 # ok 2 rtc.date_read_loop
11242 11:37:26.952158 # # RUN rtc.uie_read ...
11243 11:37:29.923730 # # OK rtc.uie_read
11244 11:37:29.927146 # ok 3 rtc.uie_read
11245 11:37:29.930113 # # RUN rtc.uie_select ...
11246 11:37:32.923378 # # OK rtc.uie_select
11247 11:37:32.926434 # ok 4 rtc.uie_select
11248 11:37:32.930133 # # RUN rtc.alarm_alm_set ...
11249 11:37:32.936392 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:37:36.
11250 11:37:32.939523 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11251 11:37:32.946315 # # alarm_alm_set: Test terminated by assertion
11252 11:37:32.949529 # # FAIL rtc.alarm_alm_set
11253 11:37:32.952756 # not ok 5 rtc.alarm_alm_set
11254 11:37:32.956290 # # RUN rtc.alarm_wkalm_set ...
11255 11:37:32.962820 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 17/07/2024 11:37:36.
11256 11:37:35.925447 # # OK rtc.alarm_wkalm_set
11257 11:37:35.925562 # ok 6 rtc.alarm_wkalm_set
11258 11:37:35.932111 # # RUN rtc.alarm_alm_set_minute ...
11259 11:37:35.935532 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:38:00.
11260 11:37:35.942112 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11261 11:37:35.948656 # # alarm_alm_set_minute: Test terminated by assertion
11262 11:37:35.951862 # # FAIL rtc.alarm_alm_set_minute
11263 11:37:35.955091 # not ok 7 rtc.alarm_alm_set_minute
11264 11:37:35.958382 # # RUN rtc.alarm_wkalm_set_minute ...
11265 11:37:35.965043 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 17/07/2024 11:38:00.
11266 11:37:59.923490 # # OK rtc.alarm_wkalm_set_minute
11267 11:37:59.926538 # ok 8 rtc.alarm_wkalm_set_minute
11268 11:37:59.930212 # # FAILED: 6 / 8 tests passed.
11269 11:37:59.933308 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11270 11:37:59.936918 not ok 1 selftests: rtc: rtctest # exit=1
11271 11:38:01.457669 rtc_rtctest_rtc_date_read pass
11272 11:38:01.460823 rtc_rtctest_rtc_date_read_loop pass
11273 11:38:01.464244 rtc_rtctest_rtc_uie_read pass
11274 11:38:01.467040 rtc_rtctest_rtc_uie_select pass
11275 11:38:01.469973 rtc_rtctest_rtc_alarm_alm_set fail
11276 11:38:01.473573 rtc_rtctest_rtc_alarm_wkalm_set pass
11277 11:38:01.476670 rtc_rtctest_rtc_alarm_alm_set_minute fail
11278 11:38:01.480075 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11279 11:38:01.483518 rtc_rtctest fail
11280 11:38:01.534465 + ../../utils/send-to-lava.sh ./output/result.txt
11281 11:38:01.624603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11282 11:38:01.625351 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11284 11:38:01.683629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11285 11:38:01.683914 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11287 11:38:01.746005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11288 11:38:01.746324 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11290 11:38:01.809583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11291 11:38:01.810371 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11293 11:38:01.872870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11294 11:38:01.873785 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11296 11:38:01.936689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11297 11:38:01.937384 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11299 11:38:02.002364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11300 11:38:02.003194 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11302 11:38:02.059981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11303 11:38:02.060371 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11305 11:38:02.121390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11306 11:38:02.122045 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11308 11:38:02.181013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11309 11:38:02.181422 + set +x
11310 11:38:02.181964 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11312 11:38:02.187814 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14864600_1.6.2.3.5>
11313 11:38:02.188434 Received signal: <ENDRUN> 1_kselftest-rtc 14864600_1.6.2.3.5
11314 11:38:02.188771 Ending use of test pattern.
11315 11:38:02.189056 Ending test lava.1_kselftest-rtc (14864600_1.6.2.3.5), duration 74.74
11317 11:38:02.190033 ok: lava_test_shell seems to have completed
11318 11:38:02.190639 shardfile-rtc: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest: fail
11319 11:38:02.191037 end: 3.1 lava-test-shell (duration 00:01:16) [common]
11320 11:38:02.191416 end: 3 lava-test-retry (duration 00:01:16) [common]
11321 11:38:02.191873 start: 4 finalize (timeout 00:06:17) [common]
11322 11:38:02.192293 start: 4.1 power-off (timeout 00:00:30) [common]
11323 11:38:02.192896 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11324 11:38:04.299369 >> Command sent successfully.
11325 11:38:04.317041 Returned 0 in 2 seconds
11326 11:38:04.317636 end: 4.1 power-off (duration 00:00:02) [common]
11328 11:38:04.318562 start: 4.2 read-feedback (timeout 00:06:15) [common]
11330 11:38:04.320226 Listened to connection for namespace 'common' for up to 1s
11331 11:38:05.319508 Finalising connection for namespace 'common'
11332 11:38:05.319636 Disconnecting from shell: Finalise
11333 11:38:05.319701 / #
11334 11:38:05.419948 end: 4.2 read-feedback (duration 00:00:01) [common]
11335 11:38:05.420079 end: 4 finalize (duration 00:00:03) [common]
11336 11:38:05.420177 Cleaning after the job
11337 11:38:05.420273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/ramdisk
11338 11:38:05.422364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/kernel
11339 11:38:05.433241 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/dtb
11340 11:38:05.433486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/nfsrootfs
11341 11:38:05.498099 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864600/tftp-deploy-eo48rblv/modules
11342 11:38:05.503922 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864600
11343 11:38:06.065350 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864600
11344 11:38:06.065511 Job finished correctly