Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:35:03.529523 lava-dispatcher, installed at version: 2024.05
2 11:35:03.529721 start: 0 validate
3 11:35:03.529833 Start time: 2024-07-17 11:35:03.529824+00:00 (UTC)
4 11:35:03.529960 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:35:03.530103 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:35:03.791036 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:35:03.791326 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fkernel%2FImage exists
8 11:35:04.050215 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:35:04.050453 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:35:04.299960 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:35:04.300144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:35:04.560581 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:35:04.561070 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.96-cip24-23-gd25f4b93e0db9%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-12%2Fmodules.tar.xz exists
14 11:35:04.826596 validate duration: 1.30
16 11:35:04.827512 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:35:04.827895 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:35:04.828281 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:35:04.828866 Not decompressing ramdisk as can be used compressed.
20 11:35:04.829250 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 11:35:04.829521 saving as /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/ramdisk/initrd.cpio.gz
22 11:35:04.829809 total size: 5628151 (5 MB)
23 11:35:04.833514 progress 0 % (0 MB)
24 11:35:04.840364 progress 5 % (0 MB)
25 11:35:04.846716 progress 10 % (0 MB)
26 11:35:04.852255 progress 15 % (0 MB)
27 11:35:04.856879 progress 20 % (1 MB)
28 11:35:04.860148 progress 25 % (1 MB)
29 11:35:04.863440 progress 30 % (1 MB)
30 11:35:04.866499 progress 35 % (1 MB)
31 11:35:04.868826 progress 40 % (2 MB)
32 11:35:04.871363 progress 45 % (2 MB)
33 11:35:04.873434 progress 50 % (2 MB)
34 11:35:04.875634 progress 55 % (2 MB)
35 11:35:04.877768 progress 60 % (3 MB)
36 11:35:04.879481 progress 65 % (3 MB)
37 11:35:04.881449 progress 70 % (3 MB)
38 11:35:04.883127 progress 75 % (4 MB)
39 11:35:04.884827 progress 80 % (4 MB)
40 11:35:04.886367 progress 85 % (4 MB)
41 11:35:04.888006 progress 90 % (4 MB)
42 11:35:04.889554 progress 95 % (5 MB)
43 11:35:04.891031 progress 100 % (5 MB)
44 11:35:04.891278 5 MB downloaded in 0.06 s (87.31 MB/s)
45 11:35:04.891442 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:35:04.891670 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:35:04.891753 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:35:04.891831 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:35:04.891975 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/kernel/Image
51 11:35:04.892038 saving as /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/kernel/Image
52 11:35:04.892090 total size: 54813184 (52 MB)
53 11:35:04.892142 No compression specified
54 11:35:04.893156 progress 0 % (0 MB)
55 11:35:04.906620 progress 5 % (2 MB)
56 11:35:04.920803 progress 10 % (5 MB)
57 11:35:04.934444 progress 15 % (7 MB)
58 11:35:04.947894 progress 20 % (10 MB)
59 11:35:04.961772 progress 25 % (13 MB)
60 11:35:04.975431 progress 30 % (15 MB)
61 11:35:04.988668 progress 35 % (18 MB)
62 11:35:05.002116 progress 40 % (20 MB)
63 11:35:05.015221 progress 45 % (23 MB)
64 11:35:05.028625 progress 50 % (26 MB)
65 11:35:05.042006 progress 55 % (28 MB)
66 11:35:05.054950 progress 60 % (31 MB)
67 11:35:05.068056 progress 65 % (34 MB)
68 11:35:05.081228 progress 70 % (36 MB)
69 11:35:05.094360 progress 75 % (39 MB)
70 11:35:05.107577 progress 80 % (41 MB)
71 11:35:05.120706 progress 85 % (44 MB)
72 11:35:05.133930 progress 90 % (47 MB)
73 11:35:05.147166 progress 95 % (49 MB)
74 11:35:05.160318 progress 100 % (52 MB)
75 11:35:05.160538 52 MB downloaded in 0.27 s (194.73 MB/s)
76 11:35:05.160687 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:35:05.160910 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:35:05.160988 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:35:05.161061 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:35:05.161250 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:35:05.161317 saving as /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/dtb/mt8192-asurada-spherion-r0.dtb
83 11:35:05.161370 total size: 47258 (0 MB)
84 11:35:05.161423 No compression specified
85 11:35:05.162562 progress 69 % (0 MB)
86 11:35:05.162812 progress 100 % (0 MB)
87 11:35:05.162952 0 MB downloaded in 0.00 s (28.54 MB/s)
88 11:35:05.163060 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:35:05.163283 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:35:05.163357 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:35:05.163435 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:35:05.163540 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 11:35:05.163598 saving as /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/nfsrootfs/full.rootfs.tar
95 11:35:05.163648 total size: 69067788 (65 MB)
96 11:35:05.163723 Using unxz to decompress xz
97 11:35:05.164904 progress 0 % (0 MB)
98 11:35:05.346318 progress 5 % (3 MB)
99 11:35:05.533814 progress 10 % (6 MB)
100 11:35:05.722336 progress 15 % (9 MB)
101 11:35:05.880868 progress 20 % (13 MB)
102 11:35:06.060680 progress 25 % (16 MB)
103 11:35:06.252185 progress 30 % (19 MB)
104 11:35:06.373857 progress 35 % (23 MB)
105 11:35:06.473710 progress 40 % (26 MB)
106 11:35:06.668430 progress 45 % (29 MB)
107 11:35:06.860207 progress 50 % (32 MB)
108 11:35:07.050276 progress 55 % (36 MB)
109 11:35:07.252530 progress 60 % (39 MB)
110 11:35:07.437587 progress 65 % (42 MB)
111 11:35:07.629130 progress 70 % (46 MB)
112 11:35:07.814012 progress 75 % (49 MB)
113 11:35:08.008074 progress 80 % (52 MB)
114 11:35:08.174225 progress 85 % (56 MB)
115 11:35:08.358104 progress 90 % (59 MB)
116 11:35:08.557427 progress 95 % (62 MB)
117 11:35:08.757773 progress 100 % (65 MB)
118 11:35:08.763903 65 MB downloaded in 3.60 s (18.30 MB/s)
119 11:35:08.764057 end: 1.4.1 http-download (duration 00:00:04) [common]
121 11:35:08.764262 end: 1.4 download-retry (duration 00:00:04) [common]
122 11:35:08.764339 start: 1.5 download-retry (timeout 00:09:56) [common]
123 11:35:08.764411 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 11:35:08.764543 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.96-cip24-23-gd25f4b93e0db9/arm64/defconfig+arm64-chromebook/gcc-12/modules.tar.xz
125 11:35:08.764603 saving as /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/modules/modules.tar
126 11:35:08.764654 total size: 8610184 (8 MB)
127 11:35:08.764707 Using unxz to decompress xz
128 11:35:08.765949 progress 0 % (0 MB)
129 11:35:08.785694 progress 5 % (0 MB)
130 11:35:08.809343 progress 10 % (0 MB)
131 11:35:08.832861 progress 15 % (1 MB)
132 11:35:08.857700 progress 20 % (1 MB)
133 11:35:08.880468 progress 25 % (2 MB)
134 11:35:08.903349 progress 30 % (2 MB)
135 11:35:08.925540 progress 35 % (2 MB)
136 11:35:08.951637 progress 40 % (3 MB)
137 11:35:08.975871 progress 45 % (3 MB)
138 11:35:08.999623 progress 50 % (4 MB)
139 11:35:09.023602 progress 55 % (4 MB)
140 11:35:09.047271 progress 60 % (4 MB)
141 11:35:09.070132 progress 65 % (5 MB)
142 11:35:09.094702 progress 70 % (5 MB)
143 11:35:09.120625 progress 75 % (6 MB)
144 11:35:09.147312 progress 80 % (6 MB)
145 11:35:09.170985 progress 85 % (7 MB)
146 11:35:09.193330 progress 90 % (7 MB)
147 11:35:09.216048 progress 95 % (7 MB)
148 11:35:09.237906 progress 100 % (8 MB)
149 11:35:09.243223 8 MB downloaded in 0.48 s (17.16 MB/s)
150 11:35:09.243371 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:35:09.243573 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:35:09.243649 start: 1.6 prepare-tftp-overlay (timeout 00:09:56) [common]
154 11:35:09.243724 start: 1.6.1 extract-nfsrootfs (timeout 00:09:56) [common]
155 11:35:10.787629 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_
156 11:35:10.787812 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:35:10.787940 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 11:35:10.788142 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j
159 11:35:10.788261 makedir: /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin
160 11:35:10.788352 makedir: /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/tests
161 11:35:10.788440 makedir: /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/results
162 11:35:10.788521 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-add-keys
163 11:35:10.788642 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-add-sources
164 11:35:10.788755 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-background-process-start
165 11:35:10.788868 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-background-process-stop
166 11:35:10.788989 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-common-functions
167 11:35:10.789101 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-echo-ipv4
168 11:35:10.789257 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-install-packages
169 11:35:10.789366 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-installed-packages
170 11:35:10.789481 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-os-build
171 11:35:10.789591 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-probe-channel
172 11:35:10.789699 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-probe-ip
173 11:35:10.789810 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-target-ip
174 11:35:10.789919 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-target-mac
175 11:35:10.790027 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-target-storage
176 11:35:10.790140 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-case
177 11:35:10.790251 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-event
178 11:35:10.790358 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-feedback
179 11:35:10.790466 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-raise
180 11:35:10.790574 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-reference
181 11:35:10.790681 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-runner
182 11:35:10.790791 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-set
183 11:35:10.790898 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-test-shell
184 11:35:10.791008 Updating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-install-packages (oe)
185 11:35:10.791143 Updating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/bin/lava-installed-packages (oe)
186 11:35:10.791251 Creating /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/environment
187 11:35:10.791334 LAVA metadata
188 11:35:10.791397 - LAVA_JOB_ID=14864627
189 11:35:10.791452 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:35:10.791540 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 11:35:10.791595 skipped lava-vland-overlay
192 11:35:10.791659 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:35:10.791729 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 11:35:10.791782 skipped lava-multinode-overlay
195 11:35:10.791845 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:35:10.791913 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 11:35:10.791976 Loading test definitions
198 11:35:10.792047 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 11:35:10.792104 Using /lava-14864627 at stage 0
200 11:35:10.792395 uuid=14864627_1.6.2.3.1 testdef=None
201 11:35:10.792475 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:35:10.792549 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 11:35:10.793050 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:35:10.793379 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 11:35:10.793925 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:35:10.794129 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 11:35:10.794649 runner path: /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/0/tests/0_lc-compliance test_uuid 14864627_1.6.2.3.1
210 11:35:10.794789 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:35:10.794966 Creating lava-test-runner.conf files
213 11:35:10.795021 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14864627/lava-overlay-o3bnb79j/lava-14864627/0 for stage 0
214 11:35:10.795100 - 0_lc-compliance
215 11:35:10.795185 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:35:10.795258 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 11:35:10.800803 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:35:10.800893 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 11:35:10.800969 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:35:10.801048 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:35:10.801153 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 11:35:10.943520 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:35:10.943659 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 11:35:10.943732 extracting modules file /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_
225 11:35:11.160795 extracting modules file /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14864627/extract-overlay-ramdisk-8eadxgyv/ramdisk
226 11:35:11.386460 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:35:11.386599 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 11:35:11.386674 [common] Applying overlay to NFS
229 11:35:11.386729 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14864627/compress-overlay-h7woehz6/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_
230 11:35:11.392807 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:35:11.392899 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 11:35:11.392978 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:35:11.393052 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 11:35:11.393143 Building ramdisk /var/lib/lava/dispatcher/tmp/14864627/extract-overlay-ramdisk-8eadxgyv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14864627/extract-overlay-ramdisk-8eadxgyv/ramdisk
235 11:35:11.650567 >> 129966 blocks
236 11:35:13.705871 rename /var/lib/lava/dispatcher/tmp/14864627/extract-overlay-ramdisk-8eadxgyv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/ramdisk/ramdisk.cpio.gz
237 11:35:13.706036 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:35:13.706121 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 11:35:13.706196 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 11:35:13.706273 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/kernel/Image']
241 11:35:27.077069 Returned 0 in 13 seconds
242 11:35:27.077232 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/kernel/image.itb
243 11:35:27.425237 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:35:27.425357 output: Created: Wed Jul 17 12:35:27 2024
245 11:35:27.425417 output: Image 0 (kernel-1)
246 11:35:27.425471 output: Description:
247 11:35:27.425523 output: Created: Wed Jul 17 12:35:27 2024
248 11:35:27.425574 output: Type: Kernel Image
249 11:35:27.425623 output: Compression: lzma compressed
250 11:35:27.425674 output: Data Size: 13118294 Bytes = 12810.83 KiB = 12.51 MiB
251 11:35:27.425723 output: Architecture: AArch64
252 11:35:27.425770 output: OS: Linux
253 11:35:27.425818 output: Load Address: 0x00000000
254 11:35:27.425866 output: Entry Point: 0x00000000
255 11:35:27.425915 output: Hash algo: crc32
256 11:35:27.425966 output: Hash value: 83448d17
257 11:35:27.426014 output: Image 1 (fdt-1)
258 11:35:27.426062 output: Description: mt8192-asurada-spherion-r0
259 11:35:27.426109 output: Created: Wed Jul 17 12:35:27 2024
260 11:35:27.426157 output: Type: Flat Device Tree
261 11:35:27.426204 output: Compression: uncompressed
262 11:35:27.426252 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 11:35:27.426300 output: Architecture: AArch64
264 11:35:27.426347 output: Hash algo: crc32
265 11:35:27.426394 output: Hash value: 0f8e4d2e
266 11:35:27.426441 output: Image 2 (ramdisk-1)
267 11:35:27.426489 output: Description: unavailable
268 11:35:27.426536 output: Created: Wed Jul 17 12:35:27 2024
269 11:35:27.426584 output: Type: RAMDisk Image
270 11:35:27.426632 output: Compression: uncompressed
271 11:35:27.426679 output: Data Size: 18725982 Bytes = 18287.09 KiB = 17.86 MiB
272 11:35:27.426727 output: Architecture: AArch64
273 11:35:27.426774 output: OS: Linux
274 11:35:27.426821 output: Load Address: unavailable
275 11:35:27.426868 output: Entry Point: unavailable
276 11:35:27.426915 output: Hash algo: crc32
277 11:35:27.426961 output: Hash value: 08fd0a90
278 11:35:27.427008 output: Default Configuration: 'conf-1'
279 11:35:27.427055 output: Configuration 0 (conf-1)
280 11:35:27.427102 output: Description: mt8192-asurada-spherion-r0
281 11:35:27.427149 output: Kernel: kernel-1
282 11:35:27.427197 output: Init Ramdisk: ramdisk-1
283 11:35:27.427244 output: FDT: fdt-1
284 11:35:27.427291 output: Loadables: kernel-1
285 11:35:27.427338 output:
286 11:35:27.427441 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 11:35:27.427514 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 11:35:27.427587 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 11:35:27.427659 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 11:35:27.427715 No LXC device requested
291 11:35:27.427781 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:35:27.427850 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 11:35:27.427916 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:35:27.427971 Checking files for TFTP limit of 4294967296 bytes.
295 11:35:27.428333 end: 1 tftp-deploy (duration 00:00:23) [common]
296 11:35:27.428424 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:35:27.428500 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:35:27.428613 substitutions:
299 11:35:27.428673 - {DTB}: 14864627/tftp-deploy-ijd5ck1a/dtb/mt8192-asurada-spherion-r0.dtb
300 11:35:27.428727 - {INITRD}: 14864627/tftp-deploy-ijd5ck1a/ramdisk/ramdisk.cpio.gz
301 11:35:27.428779 - {KERNEL}: 14864627/tftp-deploy-ijd5ck1a/kernel/Image
302 11:35:27.428829 - {LAVA_MAC}: None
303 11:35:27.428878 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_
304 11:35:27.428927 - {NFS_SERVER_IP}: 192.168.201.1
305 11:35:27.428977 - {PRESEED_CONFIG}: None
306 11:35:27.429030 - {PRESEED_LOCAL}: None
307 11:35:27.429079 - {RAMDISK}: 14864627/tftp-deploy-ijd5ck1a/ramdisk/ramdisk.cpio.gz
308 11:35:27.429141 - {ROOT_PART}: None
309 11:35:27.429193 - {ROOT}: None
310 11:35:27.429243 - {SERVER_IP}: 192.168.201.1
311 11:35:27.429291 - {TEE}: None
312 11:35:27.429339 Parsed boot commands:
313 11:35:27.429387 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:35:27.429521 Parsed boot commands: tftpboot 192.168.201.1 14864627/tftp-deploy-ijd5ck1a/kernel/image.itb 14864627/tftp-deploy-ijd5ck1a/kernel/cmdline
315 11:35:27.429599 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:35:27.429671 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:35:27.429742 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:35:27.429812 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:35:27.429867 Not connected, no need to disconnect.
320 11:35:27.429931 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:35:27.429999 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:35:27.430053 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
323 11:35:27.433031 Setting prompt string to ['lava-test: # ']
324 11:35:27.433354 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:35:27.433469 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:35:27.433558 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:35:27.433636 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:35:27.433804 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
329 11:35:36.630288 >> Command sent successfully.
330 11:35:36.643802 Returned 0 in 9 seconds
331 11:35:36.644365 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
333 11:35:36.645477 end: 2.2.2 reset-device (duration 00:00:09) [common]
334 11:35:36.645910 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
335 11:35:36.646246 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:35:36.646525 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:35:36.646821 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:35:36.648573 [Enter `^Ec?' for help]
339 11:35:38.282111
340 11:35:38.282283
341 11:35:38.282345 F0: 102B 0000
342 11:35:38.282403
343 11:35:38.282456 F3: 1001 0000 [0200]
344 11:35:38.284998
345 11:35:38.285069 F3: 1001 0000
346 11:35:38.285150
347 11:35:38.285219 F7: 102D 0000
348 11:35:38.285270
349 11:35:38.289263 F1: 0000 0000
350 11:35:38.289343
351 11:35:38.289401 V0: 0000 0000 [0001]
352 11:35:38.289453
353 11:35:38.289503 00: 0007 8000
354 11:35:38.289553
355 11:35:38.292585 01: 0000 0000
356 11:35:38.292660
357 11:35:38.292716 BP: 0C00 0209 [0000]
358 11:35:38.292768
359 11:35:38.296156 G0: 1182 0000
360 11:35:38.296229
361 11:35:38.296285 EC: 0000 0021 [4000]
362 11:35:38.296337
363 11:35:38.300412 S7: 0000 0000 [0000]
364 11:35:38.300485
365 11:35:38.300541 CC: 0000 0000 [0001]
366 11:35:38.300593
367 11:35:38.303768 T0: 0000 0040 [010F]
368 11:35:38.303843
369 11:35:38.303900 Jump to BL
370 11:35:38.303952
371 11:35:38.329282
372 11:35:38.329361
373 11:35:38.336396 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 11:35:38.339596 ARM64: Exception handlers installed.
375 11:35:38.343007 ARM64: Testing exception
376 11:35:38.346290 ARM64: Done test exception
377 11:35:38.353109 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 11:35:38.362559 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 11:35:38.369537 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 11:35:38.379695 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 11:35:38.386200 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 11:35:38.396998 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 11:35:38.406692 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 11:35:38.413393 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 11:35:38.431624 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 11:35:38.434836 WDT: Last reset was cold boot
387 11:35:38.438668 SPI1(PAD0) initialized at 2873684 Hz
388 11:35:38.441524 SPI5(PAD0) initialized at 992727 Hz
389 11:35:38.445183 VBOOT: Loading verstage.
390 11:35:38.451335 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 11:35:38.455318 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 11:35:38.458172 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 11:35:38.461365 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 11:35:38.469269 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 11:35:38.475504 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 11:35:38.486615 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 11:35:38.486689
398 11:35:38.486746
399 11:35:38.496566 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 11:35:38.499858 ARM64: Exception handlers installed.
401 11:35:38.503498 ARM64: Testing exception
402 11:35:38.503617 ARM64: Done test exception
403 11:35:38.510256 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 11:35:38.513255 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 11:35:38.528166 Probing TPM: . done!
406 11:35:38.528242 TPM ready after 0 ms
407 11:35:38.534492 Connected to device vid:did:rid of 1ae0:0028:00
408 11:35:38.540997 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 11:35:38.544443 Initialized TPM device CR50 revision 0
410 11:35:38.592840 tlcl_send_startup: Startup return code is 0
411 11:35:38.592918 TPM: setup succeeded
412 11:35:38.604451 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 11:35:38.613624 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 11:35:38.623491 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 11:35:38.632369 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 11:35:38.635751 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 11:35:38.639085 in-header: 03 07 00 00 08 00 00 00
418 11:35:38.642246 in-data: aa e4 47 04 13 02 00 00
419 11:35:38.645719 Chrome EC: UHEPI supported
420 11:35:38.652393 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 11:35:38.655790 in-header: 03 a9 00 00 08 00 00 00
422 11:35:38.659156 in-data: 84 60 60 08 00 00 00 00
423 11:35:38.659231 Phase 1
424 11:35:38.662536 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 11:35:38.669268 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 11:35:38.676412 VB2:vb2_check_recovery() Recovery was requested manually
427 11:35:38.679499 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 11:35:38.682742 Recovery requested (1009000e)
429 11:35:38.686670 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:35:38.696035 tlcl_extend: response is 0
431 11:35:38.704041 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:35:38.709676 tlcl_extend: response is 0
433 11:35:38.716031 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:35:38.736811 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 11:35:38.743387 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:35:38.743462
437 11:35:38.743519
438 11:35:38.753387 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:35:38.756601 ARM64: Exception handlers installed.
440 11:35:38.760183 ARM64: Testing exception
441 11:35:38.760261 ARM64: Done test exception
442 11:35:38.779479 pmic_efuse_setting: Set efuses in 11 msecs
443 11:35:38.788175 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:35:38.791993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:35:38.795438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:35:38.802042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:35:38.805716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:35:38.809391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:35:38.816173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:35:38.819261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:35:38.825782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:35:38.829059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:35:38.832601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:35:38.839617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:35:38.842807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:35:38.849304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:35:38.855885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:35:38.859131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:35:38.865848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:35:38.872685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:35:38.875855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:35:38.882793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:35:38.889388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:35:38.892970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:35:38.899763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:35:38.906500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:35:38.909622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:35:38.916746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:35:38.923349 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:35:38.926444 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:35:38.929856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:35:38.936273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:35:38.939906 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:35:38.946437 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:35:38.949977 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:35:38.957014 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:35:38.959886 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:35:38.966826 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:35:38.970092 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:35:38.976669 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:35:38.979738 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:35:38.986687 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:35:38.990483 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:35:38.994292 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:35:38.997857 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:35:39.004213 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:35:39.007924 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:35:39.011064 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:35:39.018105 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:35:39.020817 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:35:39.024208 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:35:39.027458 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:35:39.034337 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:35:39.037931 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:35:39.044713 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 11:35:39.054404 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:35:39.058053 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:35:39.064337 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:35:39.074916 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:35:39.077849 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:35:39.084650 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:35:39.087885 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:35:39.094813 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
504 11:35:39.101225 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:35:39.104763 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 11:35:39.108000 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:35:39.119848 [RTC]rtc_get_frequency_meter,154: input=15, output=789
508 11:35:39.128911 [RTC]rtc_get_frequency_meter,154: input=23, output=978
509 11:35:39.138711 [RTC]rtc_get_frequency_meter,154: input=19, output=884
510 11:35:39.147730 [RTC]rtc_get_frequency_meter,154: input=17, output=838
511 11:35:39.157318 [RTC]rtc_get_frequency_meter,154: input=16, output=813
512 11:35:39.167088 [RTC]rtc_get_frequency_meter,154: input=15, output=789
513 11:35:39.176226 [RTC]rtc_get_frequency_meter,154: input=16, output=814
514 11:35:39.179859 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
515 11:35:39.187234 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
516 11:35:39.190179 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:35:39.193562 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 11:35:39.201129 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:35:39.204098 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 11:35:39.206841 ADC[4]: Raw value=900959 ID=7
521 11:35:39.206917 ADC[3]: Raw value=213336 ID=1
522 11:35:39.210268 RAM Code: 0x71
523 11:35:39.213673 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:35:39.220576 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:35:39.227256 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:35:39.234538 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:35:39.237332 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:35:39.240461 in-header: 03 07 00 00 08 00 00 00
529 11:35:39.243894 in-data: aa e4 47 04 13 02 00 00
530 11:35:39.247403 Chrome EC: UHEPI supported
531 11:35:39.253930 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:35:39.257492 in-header: 03 a9 00 00 08 00 00 00
533 11:35:39.260768 in-data: 84 60 60 08 00 00 00 00
534 11:35:39.264414 MRC: failed to locate region type 0.
535 11:35:39.271196 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:35:39.274196 DRAM-K: Running full calibration
537 11:35:39.277904 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:35:39.280922 header.status = 0x0
539 11:35:39.284322 header.version = 0x6 (expected: 0x6)
540 11:35:39.287414 header.size = 0xd00 (expected: 0xd00)
541 11:35:39.290849 header.flags = 0x0
542 11:35:39.294344 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:35:39.313336 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 11:35:39.320179 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:35:39.323386 dram_init: ddr_geometry: 2
546 11:35:39.326824 [EMI] MDL number = 2
547 11:35:39.326916 [EMI] Get MDL freq = 0
548 11:35:39.330289 dram_init: ddr_type: 0
549 11:35:39.330380 is_discrete_lpddr4: 1
550 11:35:39.333705 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:35:39.333798
552 11:35:39.333881
553 11:35:39.336737 [Bian_co] ETT version 0.0.0.1
554 11:35:39.343288 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:35:39.343386
556 11:35:39.346908 dramc_set_vcore_voltage set vcore to 650000
557 11:35:39.346998 Read voltage for 800, 4
558 11:35:39.350263 Vio18 = 0
559 11:35:39.350354 Vcore = 650000
560 11:35:39.350438 Vdram = 0
561 11:35:39.353675 Vddq = 0
562 11:35:39.353741 Vmddr = 0
563 11:35:39.357019 dram_init: config_dvfs: 1
564 11:35:39.360372 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:35:39.366902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:35:39.370670 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
567 11:35:39.373671 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
568 11:35:39.376993 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
569 11:35:39.380671 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
570 11:35:39.383720 MEM_TYPE=3, freq_sel=18
571 11:35:39.387344 sv_algorithm_assistance_LP4_1600
572 11:35:39.390642 ============ PULL DRAM RESETB DOWN ============
573 11:35:39.393599 ========== PULL DRAM RESETB DOWN end =========
574 11:35:39.400279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:35:39.403511 ===================================
576 11:35:39.403608 LPDDR4 DRAM CONFIGURATION
577 11:35:39.407118 ===================================
578 11:35:39.410375 EX_ROW_EN[0] = 0x0
579 11:35:39.414081 EX_ROW_EN[1] = 0x0
580 11:35:39.414176 LP4Y_EN = 0x0
581 11:35:39.417243 WORK_FSP = 0x0
582 11:35:39.417310 WL = 0x2
583 11:35:39.420770 RL = 0x2
584 11:35:39.420894 BL = 0x2
585 11:35:39.424070 RPST = 0x0
586 11:35:39.424160 RD_PRE = 0x0
587 11:35:39.427587 WR_PRE = 0x1
588 11:35:39.427676 WR_PST = 0x0
589 11:35:39.431209 DBI_WR = 0x0
590 11:35:39.431338 DBI_RD = 0x0
591 11:35:39.433945 OTF = 0x1
592 11:35:39.437343 ===================================
593 11:35:39.440588 ===================================
594 11:35:39.440655 ANA top config
595 11:35:39.444451 ===================================
596 11:35:39.448257 DLL_ASYNC_EN = 0
597 11:35:39.448329 ALL_SLAVE_EN = 1
598 11:35:39.451739 NEW_RANK_MODE = 1
599 11:35:39.455464 DLL_IDLE_MODE = 1
600 11:35:39.455561 LP45_APHY_COMB_EN = 1
601 11:35:39.459257 TX_ODT_DIS = 1
602 11:35:39.463003 NEW_8X_MODE = 1
603 11:35:39.467406 ===================================
604 11:35:39.467499 ===================================
605 11:35:39.471339 data_rate = 1600
606 11:35:39.474505 CKR = 1
607 11:35:39.478387 DQ_P2S_RATIO = 8
608 11:35:39.482481 ===================================
609 11:35:39.482549 CA_P2S_RATIO = 8
610 11:35:39.485124 DQ_CA_OPEN = 0
611 11:35:39.488316 DQ_SEMI_OPEN = 0
612 11:35:39.491951 CA_SEMI_OPEN = 0
613 11:35:39.495001 CA_FULL_RATE = 0
614 11:35:39.498795 DQ_CKDIV4_EN = 1
615 11:35:39.498860 CA_CKDIV4_EN = 1
616 11:35:39.502355 CA_PREDIV_EN = 0
617 11:35:39.505310 PH8_DLY = 0
618 11:35:39.508443 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:35:39.511912 DQ_AAMCK_DIV = 4
620 11:35:39.515577 CA_AAMCK_DIV = 4
621 11:35:39.515651 CA_ADMCK_DIV = 4
622 11:35:39.518840 DQ_TRACK_CA_EN = 0
623 11:35:39.522581 CA_PICK = 800
624 11:35:39.525809 CA_MCKIO = 800
625 11:35:39.528698 MCKIO_SEMI = 0
626 11:35:39.532027 PLL_FREQ = 3068
627 11:35:39.532095 DQ_UI_PI_RATIO = 32
628 11:35:39.535577 CA_UI_PI_RATIO = 0
629 11:35:39.538905 ===================================
630 11:35:39.542198 ===================================
631 11:35:39.545703 memory_type:LPDDR4
632 11:35:39.549108 GP_NUM : 10
633 11:35:39.549218 SRAM_EN : 1
634 11:35:39.552297 MD32_EN : 0
635 11:35:39.555421 ===================================
636 11:35:39.555486 [ANA_INIT] >>>>>>>>>>>>>>
637 11:35:39.558850 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:35:39.562445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:35:39.565781 ===================================
640 11:35:39.568869 data_rate = 1600,PCW = 0X7600
641 11:35:39.572281 ===================================
642 11:35:39.575984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:35:39.582751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:35:39.585968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:35:39.592521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:35:39.595725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:35:39.599283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:35:39.602499 [ANA_INIT] flow start
649 11:35:39.602563 [ANA_INIT] PLL >>>>>>>>
650 11:35:39.606160 [ANA_INIT] PLL <<<<<<<<
651 11:35:39.609642 [ANA_INIT] MIDPI >>>>>>>>
652 11:35:39.609712 [ANA_INIT] MIDPI <<<<<<<<
653 11:35:39.612601 [ANA_INIT] DLL >>>>>>>>
654 11:35:39.612665 [ANA_INIT] flow end
655 11:35:39.619520 ============ LP4 DIFF to SE enter ============
656 11:35:39.623023 ============ LP4 DIFF to SE exit ============
657 11:35:39.626780 [ANA_INIT] <<<<<<<<<<<<<
658 11:35:39.629306 [Flow] Enable top DCM control >>>>>
659 11:35:39.632828 [Flow] Enable top DCM control <<<<<
660 11:35:39.632917 Enable DLL master slave shuffle
661 11:35:39.639861 ==============================================================
662 11:35:39.642821 Gating Mode config
663 11:35:39.646334 ==============================================================
664 11:35:39.649779 Config description:
665 11:35:39.659998 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:35:39.666277 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:35:39.669802 SELPH_MODE 0: By rank 1: By Phase
668 11:35:39.676142 ==============================================================
669 11:35:39.679684 GAT_TRACK_EN = 1
670 11:35:39.683072 RX_GATING_MODE = 2
671 11:35:39.686498 RX_GATING_TRACK_MODE = 2
672 11:35:39.686562 SELPH_MODE = 1
673 11:35:39.689611 PICG_EARLY_EN = 1
674 11:35:39.693540 VALID_LAT_VALUE = 1
675 11:35:39.699660 ==============================================================
676 11:35:39.703380 Enter into Gating configuration >>>>
677 11:35:39.706638 Exit from Gating configuration <<<<
678 11:35:39.709809 Enter into DVFS_PRE_config >>>>>
679 11:35:39.719832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:35:39.723306 Exit from DVFS_PRE_config <<<<<
681 11:35:39.726792 Enter into PICG configuration >>>>
682 11:35:39.729771 Exit from PICG configuration <<<<
683 11:35:39.733400 [RX_INPUT] configuration >>>>>
684 11:35:39.736899 [RX_INPUT] configuration <<<<<
685 11:35:39.739993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:35:39.746528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:35:39.753355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:35:39.757167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:35:39.763304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:35:39.770139 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:35:39.773618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:35:39.777449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:35:39.783653 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:35:39.787568 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:35:39.790441 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:35:39.793789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:35:39.797315 ===================================
698 11:35:39.800427 LPDDR4 DRAM CONFIGURATION
699 11:35:39.803648 ===================================
700 11:35:39.807167 EX_ROW_EN[0] = 0x0
701 11:35:39.807242 EX_ROW_EN[1] = 0x0
702 11:35:39.810549 LP4Y_EN = 0x0
703 11:35:39.810623 WORK_FSP = 0x0
704 11:35:39.814629 WL = 0x2
705 11:35:39.814703 RL = 0x2
706 11:35:39.818013 BL = 0x2
707 11:35:39.818087 RPST = 0x0
708 11:35:39.820624 RD_PRE = 0x0
709 11:35:39.820698 WR_PRE = 0x1
710 11:35:39.823998 WR_PST = 0x0
711 11:35:39.824072 DBI_WR = 0x0
712 11:35:39.827704 DBI_RD = 0x0
713 11:35:39.827778 OTF = 0x1
714 11:35:39.830509 ===================================
715 11:35:39.837160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:35:39.840700 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:35:39.844024 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:35:39.847569 ===================================
719 11:35:39.850921 LPDDR4 DRAM CONFIGURATION
720 11:35:39.854394 ===================================
721 11:35:39.854468 EX_ROW_EN[0] = 0x10
722 11:35:39.857642 EX_ROW_EN[1] = 0x0
723 11:35:39.860963 LP4Y_EN = 0x0
724 11:35:39.861038 WORK_FSP = 0x0
725 11:35:39.864191 WL = 0x2
726 11:35:39.864265 RL = 0x2
727 11:35:39.867691 BL = 0x2
728 11:35:39.867766 RPST = 0x0
729 11:35:39.870959 RD_PRE = 0x0
730 11:35:39.871033 WR_PRE = 0x1
731 11:35:39.874601 WR_PST = 0x0
732 11:35:39.874675 DBI_WR = 0x0
733 11:35:39.877559 DBI_RD = 0x0
734 11:35:39.877632 OTF = 0x1
735 11:35:39.881307 ===================================
736 11:35:39.887507 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:35:39.891582 nWR fixed to 40
738 11:35:39.895062 [ModeRegInit_LP4] CH0 RK0
739 11:35:39.895135 [ModeRegInit_LP4] CH0 RK1
740 11:35:39.898343 [ModeRegInit_LP4] CH1 RK0
741 11:35:39.902141 [ModeRegInit_LP4] CH1 RK1
742 11:35:39.902215 match AC timing 13
743 11:35:39.908868 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:35:39.911955 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:35:39.915492 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:35:39.922667 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:35:39.925615 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:35:39.925690 [EMI DOE] emi_dcm 0
749 11:35:39.931929 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:35:39.932003 ==
751 11:35:39.935293 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:35:39.939099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:35:39.939173 ==
754 11:35:39.946168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:35:39.948529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:35:39.959484 [CA 0] Center 37 (7~68) winsize 62
757 11:35:39.963174 [CA 1] Center 37 (6~68) winsize 63
758 11:35:39.965917 [CA 2] Center 35 (4~66) winsize 63
759 11:35:39.969246 [CA 3] Center 34 (4~65) winsize 62
760 11:35:39.972301 [CA 4] Center 34 (3~65) winsize 63
761 11:35:39.975949 [CA 5] Center 34 (4~64) winsize 61
762 11:35:39.976024
763 11:35:39.978962 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 11:35:39.979037
765 11:35:39.982698 [CATrainingPosCal] consider 1 rank data
766 11:35:39.985679 u2DelayCellTimex100 = 270/100 ps
767 11:35:39.989173 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
768 11:35:39.992853 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
769 11:35:39.996750 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
770 11:35:40.000119 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
771 11:35:40.003458 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
772 11:35:40.010533 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
773 11:35:40.010608
774 11:35:40.013192 CA PerBit enable=1, Macro0, CA PI delay=34
775 11:35:40.013266
776 11:35:40.016648 [CBTSetCACLKResult] CA Dly = 34
777 11:35:40.016722 CS Dly: 5 (0~36)
778 11:35:40.016779 ==
779 11:35:40.019966 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:35:40.023147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:35:40.027092 ==
782 11:35:40.031145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:35:40.037731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:35:40.045366 [CA 0] Center 37 (6~68) winsize 63
785 11:35:40.048520 [CA 1] Center 37 (7~68) winsize 62
786 11:35:40.051952 [CA 2] Center 35 (4~66) winsize 63
787 11:35:40.055282 [CA 3] Center 34 (4~65) winsize 62
788 11:35:40.058771 [CA 4] Center 34 (3~65) winsize 63
789 11:35:40.061886 [CA 5] Center 33 (3~64) winsize 62
790 11:35:40.061959
791 11:35:40.065229 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 11:35:40.065304
793 11:35:40.069035 [CATrainingPosCal] consider 2 rank data
794 11:35:40.072295 u2DelayCellTimex100 = 270/100 ps
795 11:35:40.075348 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
796 11:35:40.078649 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
797 11:35:40.082121 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
798 11:35:40.088879 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
799 11:35:40.092160 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
800 11:35:40.095789 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
801 11:35:40.095863
802 11:35:40.099222 CA PerBit enable=1, Macro0, CA PI delay=34
803 11:35:40.099301
804 11:35:40.102477 [CBTSetCACLKResult] CA Dly = 34
805 11:35:40.102551 CS Dly: 6 (0~38)
806 11:35:40.102609
807 11:35:40.105774 ----->DramcWriteLeveling(PI) begin...
808 11:35:40.105850 ==
809 11:35:40.109026 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:35:40.115865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:35:40.115938 ==
812 11:35:40.119240 Write leveling (Byte 0): 28 => 28
813 11:35:40.119314 Write leveling (Byte 1): 29 => 29
814 11:35:40.122365 DramcWriteLeveling(PI) end<-----
815 11:35:40.122447
816 11:35:40.122511 ==
817 11:35:40.125885 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:35:40.132977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:35:40.133052 ==
820 11:35:40.136324 [Gating] SW mode calibration
821 11:35:40.142669 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:35:40.146269 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:35:40.149574 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:35:40.156148 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 11:35:40.159292 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
826 11:35:40.163324 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:35:40.169955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:35:40.173288 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:35:40.176521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:35:40.183237 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:35:40.186460 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:35:40.190043 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:35:40.196688 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:35:40.200116 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:35:40.203094 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:35:40.206538 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:35:40.213235 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:35:40.216710 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:35:40.219742 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:35:40.226508 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 11:35:40.230532 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
842 11:35:40.233455 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
843 11:35:40.239995 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:35:40.243527 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:35:40.247037 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:35:40.253530 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:35:40.256998 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:35:40.260155 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:35:40.266900 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
850 11:35:40.270506 0 9 12 | B1->B0 | 2b2b 3333 | 1 0 | (0 0) (0 0)
851 11:35:40.273618 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:35:40.276941 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:35:40.283848 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:35:40.287064 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:35:40.290375 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:35:40.297216 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
857 11:35:40.300517 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
858 11:35:40.304240 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
859 11:35:40.310629 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:35:40.314196 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:35:40.317792 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:35:40.323902 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:35:40.327711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:35:40.330884 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:35:40.334045 0 11 8 | B1->B0 | 2625 3030 | 1 0 | (0 0) (0 0)
866 11:35:40.341031 0 11 12 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (1 1)
867 11:35:40.344653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:35:40.347912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:35:40.354473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:35:40.358407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:35:40.361317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:35:40.367739 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 11:35:40.371106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 11:35:40.374449 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 11:35:40.381267 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:35:40.384437 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:35:40.388016 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:35:40.391550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:35:40.397899 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:35:40.401738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:35:40.405227 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:35:40.411789 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:35:40.415093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:35:40.418286 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:35:40.424884 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:35:40.428179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:35:40.431342 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:35:40.438215 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 11:35:40.441505 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 11:35:40.445150 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
891 11:35:40.449095 Total UI for P1: 0, mck2ui 16
892 11:35:40.452270 best dqsien dly found for B0: ( 0, 14, 8)
893 11:35:40.454976 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:35:40.458606 Total UI for P1: 0, mck2ui 16
895 11:35:40.461687 best dqsien dly found for B1: ( 0, 14, 10)
896 11:35:40.464917 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
897 11:35:40.468466 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 11:35:40.472057
899 11:35:40.475208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 11:35:40.478789 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 11:35:40.478864 [Gating] SW calibration Done
902 11:35:40.482334 ==
903 11:35:40.485257 Dram Type= 6, Freq= 0, CH_0, rank 0
904 11:35:40.488564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 11:35:40.488639 ==
906 11:35:40.488696 RX Vref Scan: 0
907 11:35:40.488749
908 11:35:40.492530 RX Vref 0 -> 0, step: 1
909 11:35:40.492626
910 11:35:40.495439 RX Delay -130 -> 252, step: 16
911 11:35:40.498476 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
912 11:35:40.502304 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
913 11:35:40.505368 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 11:35:40.511988 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
915 11:35:40.515286 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
916 11:35:40.518811 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
917 11:35:40.522438 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
918 11:35:40.525640 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
919 11:35:40.532317 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
920 11:35:40.536028 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
921 11:35:40.539053 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
922 11:35:40.542901 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
923 11:35:40.545758 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
924 11:35:40.552558 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
925 11:35:40.556006 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
926 11:35:40.559029 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
927 11:35:40.559126 ==
928 11:35:40.562716 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:35:40.566024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:35:40.566121 ==
931 11:35:40.569222 DQS Delay:
932 11:35:40.569298 DQS0 = 0, DQS1 = 0
933 11:35:40.569356 DQM Delay:
934 11:35:40.573017 DQM0 = 87, DQM1 = 82
935 11:35:40.573139 DQ Delay:
936 11:35:40.576264 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
937 11:35:40.579279 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
938 11:35:40.582586 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
939 11:35:40.586000 DQ12 =93, DQ13 =85, DQ14 =93, DQ15 =93
940 11:35:40.586074
941 11:35:40.586130
942 11:35:40.586193 ==
943 11:35:40.589450 Dram Type= 6, Freq= 0, CH_0, rank 0
944 11:35:40.596300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 11:35:40.596374 ==
946 11:35:40.596432
947 11:35:40.596485
948 11:35:40.596535 TX Vref Scan disable
949 11:35:40.599767 == TX Byte 0 ==
950 11:35:40.603388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
951 11:35:40.606374 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
952 11:35:40.609965 == TX Byte 1 ==
953 11:35:40.613094 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
954 11:35:40.616402 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
955 11:35:40.619949 ==
956 11:35:40.623138 Dram Type= 6, Freq= 0, CH_0, rank 0
957 11:35:40.626244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 11:35:40.626318 ==
959 11:35:40.638754 TX Vref=22, minBit 0, minWin=27, winSum=439
960 11:35:40.642380 TX Vref=24, minBit 3, minWin=27, winSum=443
961 11:35:40.645554 TX Vref=26, minBit 3, minWin=27, winSum=444
962 11:35:40.648725 TX Vref=28, minBit 5, minWin=27, winSum=448
963 11:35:40.652567 TX Vref=30, minBit 2, minWin=28, winSum=456
964 11:35:40.655599 TX Vref=32, minBit 12, minWin=27, winSum=452
965 11:35:40.662316 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
966 11:35:40.662391
967 11:35:40.665471 Final TX Range 1 Vref 30
968 11:35:40.665546
969 11:35:40.665602 ==
970 11:35:40.668862 Dram Type= 6, Freq= 0, CH_0, rank 0
971 11:35:40.672332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 11:35:40.672406 ==
973 11:35:40.672464
974 11:35:40.672517
975 11:35:40.675988 TX Vref Scan disable
976 11:35:40.679154 == TX Byte 0 ==
977 11:35:40.682546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
978 11:35:40.685935 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
979 11:35:40.689675 == TX Byte 1 ==
980 11:35:40.692747 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
981 11:35:40.695884 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
982 11:35:40.695959
983 11:35:40.699483 [DATLAT]
984 11:35:40.699556 Freq=800, CH0 RK0
985 11:35:40.699614
986 11:35:40.703161 DATLAT Default: 0xa
987 11:35:40.703234 0, 0xFFFF, sum = 0
988 11:35:40.705881 1, 0xFFFF, sum = 0
989 11:35:40.705956 2, 0xFFFF, sum = 0
990 11:35:40.709313 3, 0xFFFF, sum = 0
991 11:35:40.709388 4, 0xFFFF, sum = 0
992 11:35:40.712776 5, 0xFFFF, sum = 0
993 11:35:40.712850 6, 0xFFFF, sum = 0
994 11:35:40.715783 7, 0xFFFF, sum = 0
995 11:35:40.715883 8, 0xFFFF, sum = 0
996 11:35:40.719489 9, 0x0, sum = 1
997 11:35:40.719564 10, 0x0, sum = 2
998 11:35:40.722842 11, 0x0, sum = 3
999 11:35:40.722917 12, 0x0, sum = 4
1000 11:35:40.725929 best_step = 10
1001 11:35:40.726003
1002 11:35:40.726059 ==
1003 11:35:40.729503 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 11:35:40.732705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 11:35:40.732779 ==
1006 11:35:40.736070 RX Vref Scan: 1
1007 11:35:40.736144
1008 11:35:40.736202 Set Vref Range= 32 -> 127
1009 11:35:40.736257
1010 11:35:40.739719 RX Vref 32 -> 127, step: 1
1011 11:35:40.739793
1012 11:35:40.742934 RX Delay -95 -> 252, step: 8
1013 11:35:40.743008
1014 11:35:40.746153 Set Vref, RX VrefLevel [Byte0]: 32
1015 11:35:40.749913 [Byte1]: 32
1016 11:35:40.749987
1017 11:35:40.752687 Set Vref, RX VrefLevel [Byte0]: 33
1018 11:35:40.755973 [Byte1]: 33
1019 11:35:40.756047
1020 11:35:40.759508 Set Vref, RX VrefLevel [Byte0]: 34
1021 11:35:40.762818 [Byte1]: 34
1022 11:35:40.766872
1023 11:35:40.766946 Set Vref, RX VrefLevel [Byte0]: 35
1024 11:35:40.770362 [Byte1]: 35
1025 11:35:40.774443
1026 11:35:40.774518 Set Vref, RX VrefLevel [Byte0]: 36
1027 11:35:40.777560 [Byte1]: 36
1028 11:35:40.782350
1029 11:35:40.782423 Set Vref, RX VrefLevel [Byte0]: 37
1030 11:35:40.785281 [Byte1]: 37
1031 11:35:40.789462
1032 11:35:40.789536 Set Vref, RX VrefLevel [Byte0]: 38
1033 11:35:40.792665 [Byte1]: 38
1034 11:35:40.797460
1035 11:35:40.797533 Set Vref, RX VrefLevel [Byte0]: 39
1036 11:35:40.800202 [Byte1]: 39
1037 11:35:40.804838
1038 11:35:40.804911 Set Vref, RX VrefLevel [Byte0]: 40
1039 11:35:40.808150 [Byte1]: 40
1040 11:35:40.812533
1041 11:35:40.812607 Set Vref, RX VrefLevel [Byte0]: 41
1042 11:35:40.815429 [Byte1]: 41
1043 11:35:40.819918
1044 11:35:40.819992 Set Vref, RX VrefLevel [Byte0]: 42
1045 11:35:40.823077 [Byte1]: 42
1046 11:35:40.827469
1047 11:35:40.827574 Set Vref, RX VrefLevel [Byte0]: 43
1048 11:35:40.830495 [Byte1]: 43
1049 11:35:40.835088
1050 11:35:40.835162 Set Vref, RX VrefLevel [Byte0]: 44
1051 11:35:40.838921 [Byte1]: 44
1052 11:35:40.842766
1053 11:35:40.842840 Set Vref, RX VrefLevel [Byte0]: 45
1054 11:35:40.846069 [Byte1]: 45
1055 11:35:40.849995
1056 11:35:40.850068 Set Vref, RX VrefLevel [Byte0]: 46
1057 11:35:40.853575 [Byte1]: 46
1058 11:35:40.857876
1059 11:35:40.857950 Set Vref, RX VrefLevel [Byte0]: 47
1060 11:35:40.861379 [Byte1]: 47
1061 11:35:40.865386
1062 11:35:40.865460 Set Vref, RX VrefLevel [Byte0]: 48
1063 11:35:40.868602 [Byte1]: 48
1064 11:35:40.873186
1065 11:35:40.873260 Set Vref, RX VrefLevel [Byte0]: 49
1066 11:35:40.876375 [Byte1]: 49
1067 11:35:40.880388
1068 11:35:40.880491 Set Vref, RX VrefLevel [Byte0]: 50
1069 11:35:40.884070 [Byte1]: 50
1070 11:35:40.888051
1071 11:35:40.888124 Set Vref, RX VrefLevel [Byte0]: 51
1072 11:35:40.891682 [Byte1]: 51
1073 11:35:40.895690
1074 11:35:40.895766 Set Vref, RX VrefLevel [Byte0]: 52
1075 11:35:40.899069 [Byte1]: 52
1076 11:35:40.903284
1077 11:35:40.903358 Set Vref, RX VrefLevel [Byte0]: 53
1078 11:35:40.906519 [Byte1]: 53
1079 11:35:40.911004
1080 11:35:40.911078 Set Vref, RX VrefLevel [Byte0]: 54
1081 11:35:40.914525 [Byte1]: 54
1082 11:35:40.918814
1083 11:35:40.918888 Set Vref, RX VrefLevel [Byte0]: 55
1084 11:35:40.922007 [Byte1]: 55
1085 11:35:40.926226
1086 11:35:40.926300 Set Vref, RX VrefLevel [Byte0]: 56
1087 11:35:40.929677 [Byte1]: 56
1088 11:35:40.933511
1089 11:35:40.933585 Set Vref, RX VrefLevel [Byte0]: 57
1090 11:35:40.936795 [Byte1]: 57
1091 11:35:40.941416
1092 11:35:40.941490 Set Vref, RX VrefLevel [Byte0]: 58
1093 11:35:40.945023 [Byte1]: 58
1094 11:35:40.948680
1095 11:35:40.948753 Set Vref, RX VrefLevel [Byte0]: 59
1096 11:35:40.952726 [Byte1]: 59
1097 11:35:40.956468
1098 11:35:40.956543 Set Vref, RX VrefLevel [Byte0]: 60
1099 11:35:40.960293 [Byte1]: 60
1100 11:35:40.964126
1101 11:35:40.964200 Set Vref, RX VrefLevel [Byte0]: 61
1102 11:35:40.967179 [Byte1]: 61
1103 11:35:40.972005
1104 11:35:40.972079 Set Vref, RX VrefLevel [Byte0]: 62
1105 11:35:40.975187 [Byte1]: 62
1106 11:35:40.979515
1107 11:35:40.979590 Set Vref, RX VrefLevel [Byte0]: 63
1108 11:35:40.982312 [Byte1]: 63
1109 11:35:40.987514
1110 11:35:40.987588 Set Vref, RX VrefLevel [Byte0]: 64
1111 11:35:40.990399 [Byte1]: 64
1112 11:35:40.994559
1113 11:35:40.994632 Set Vref, RX VrefLevel [Byte0]: 65
1114 11:35:40.997689 [Byte1]: 65
1115 11:35:41.002066
1116 11:35:41.002140 Set Vref, RX VrefLevel [Byte0]: 66
1117 11:35:41.005639 [Byte1]: 66
1118 11:35:41.010186
1119 11:35:41.010260 Set Vref, RX VrefLevel [Byte0]: 67
1120 11:35:41.012877 [Byte1]: 67
1121 11:35:41.017529
1122 11:35:41.017603 Set Vref, RX VrefLevel [Byte0]: 68
1123 11:35:41.020582 [Byte1]: 68
1124 11:35:41.024598
1125 11:35:41.024672 Set Vref, RX VrefLevel [Byte0]: 69
1126 11:35:41.028080 [Byte1]: 69
1127 11:35:41.032350
1128 11:35:41.032424 Set Vref, RX VrefLevel [Byte0]: 70
1129 11:35:41.035844 [Byte1]: 70
1130 11:35:41.040010
1131 11:35:41.040084 Set Vref, RX VrefLevel [Byte0]: 71
1132 11:35:41.043503 [Byte1]: 71
1133 11:35:41.047837
1134 11:35:41.047911 Set Vref, RX VrefLevel [Byte0]: 72
1135 11:35:41.050913 [Byte1]: 72
1136 11:35:41.055324
1137 11:35:41.055398 Set Vref, RX VrefLevel [Byte0]: 73
1138 11:35:41.058283 [Byte1]: 73
1139 11:35:41.062655
1140 11:35:41.062729 Set Vref, RX VrefLevel [Byte0]: 74
1141 11:35:41.066660 [Byte1]: 74
1142 11:35:41.070514
1143 11:35:41.070588 Set Vref, RX VrefLevel [Byte0]: 75
1144 11:35:41.073795 [Byte1]: 75
1145 11:35:41.078105
1146 11:35:41.078179 Set Vref, RX VrefLevel [Byte0]: 76
1147 11:35:41.081771 [Byte1]: 76
1148 11:35:41.085585
1149 11:35:41.085658 Set Vref, RX VrefLevel [Byte0]: 77
1150 11:35:41.088603 [Byte1]: 77
1151 11:35:41.093574
1152 11:35:41.093646 Final RX Vref Byte 0 = 60 to rank0
1153 11:35:41.096677 Final RX Vref Byte 1 = 59 to rank0
1154 11:35:41.099680 Final RX Vref Byte 0 = 60 to rank1
1155 11:35:41.103713 Final RX Vref Byte 1 = 59 to rank1==
1156 11:35:41.107057 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 11:35:41.109862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 11:35:41.113098 ==
1159 11:35:41.113211 DQS Delay:
1160 11:35:41.113268 DQS0 = 0, DQS1 = 0
1161 11:35:41.116763 DQM Delay:
1162 11:35:41.116835 DQM0 = 87, DQM1 = 78
1163 11:35:41.120110 DQ Delay:
1164 11:35:41.120183 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1165 11:35:41.123198 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1166 11:35:41.126437 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1167 11:35:41.129870 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1168 11:35:41.129943
1169 11:35:41.133488
1170 11:35:41.140113 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1171 11:35:41.143604 CH0 RK0: MR19=606, MR18=2C13
1172 11:35:41.150299 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1173 11:35:41.150373
1174 11:35:41.153591 ----->DramcWriteLeveling(PI) begin...
1175 11:35:41.153666 ==
1176 11:35:41.157085 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 11:35:41.160488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 11:35:41.160562 ==
1179 11:35:41.163433 Write leveling (Byte 0): 32 => 32
1180 11:35:41.166951 Write leveling (Byte 1): 28 => 28
1181 11:35:41.170367 DramcWriteLeveling(PI) end<-----
1182 11:35:41.170442
1183 11:35:41.170501 ==
1184 11:35:41.173549 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 11:35:41.177319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 11:35:41.177395 ==
1187 11:35:41.180316 [Gating] SW mode calibration
1188 11:35:41.187351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 11:35:41.190381 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 11:35:41.196966 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 11:35:41.200663 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 11:35:41.203976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 11:35:41.210813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:35:41.214112 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:35:41.258011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:35:41.258499 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:35:41.259160 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:35:41.259235 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:35:41.259803 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:35:41.260066 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:35:41.260132 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:35:41.260600 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:35:41.260674 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:35:41.261105 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:35:41.301944 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:35:41.302235 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:35:41.302513 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1208 11:35:41.302577 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 11:35:41.302819 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 11:35:41.303398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:35:41.303653 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:35:41.303895 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:35:41.303954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:35:41.304016 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:35:41.307986 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:35:41.311170 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1217 11:35:41.314453 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1218 11:35:41.318003 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 11:35:41.324650 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 11:35:41.327746 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 11:35:41.331334 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 11:35:41.338290 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 11:35:41.341452 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1224 11:35:41.345269 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
1225 11:35:41.351593 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1226 11:35:41.354643 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:35:41.358136 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:35:41.364713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:35:41.368297 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:35:41.371545 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:35:41.378510 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1232 11:35:41.381289 0 11 8 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
1233 11:35:41.384756 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1234 11:35:41.388372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 11:35:41.395074 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 11:35:41.398614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 11:35:41.401579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 11:35:41.408438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1239 11:35:41.411903 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1240 11:35:41.415190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 11:35:41.421966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 11:35:41.425061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 11:35:41.428413 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 11:35:41.435277 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 11:35:41.438758 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 11:35:41.441830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:35:41.448735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:35:41.452172 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:35:41.455190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:35:41.458760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:35:41.465265 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:35:41.468562 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:35:41.471816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:35:41.478483 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:35:41.481991 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1256 11:35:41.485349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1257 11:35:41.488609 Total UI for P1: 0, mck2ui 16
1258 11:35:41.492012 best dqsien dly found for B0: ( 0, 14, 4)
1259 11:35:41.498652 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:35:41.498726 Total UI for P1: 0, mck2ui 16
1261 11:35:41.502716 best dqsien dly found for B1: ( 0, 14, 8)
1262 11:35:41.508761 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1263 11:35:41.512307 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1264 11:35:41.512380
1265 11:35:41.515809 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1266 11:35:41.519137 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1267 11:35:41.522215 [Gating] SW calibration Done
1268 11:35:41.522288 ==
1269 11:35:41.525600 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 11:35:41.529057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 11:35:41.529200 ==
1272 11:35:41.529291 RX Vref Scan: 0
1273 11:35:41.532923
1274 11:35:41.532996 RX Vref 0 -> 0, step: 1
1275 11:35:41.533053
1276 11:35:41.536050 RX Delay -130 -> 252, step: 16
1277 11:35:41.539163 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1278 11:35:41.542578 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1279 11:35:41.548998 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1280 11:35:41.552490 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1281 11:35:41.555933 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1282 11:35:41.559475 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1283 11:35:41.562594 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1284 11:35:41.569340 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1285 11:35:41.572545 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1286 11:35:41.575948 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1287 11:35:41.579219 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1288 11:35:41.582778 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1289 11:35:41.586344 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1290 11:35:41.593008 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1291 11:35:41.596553 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1292 11:35:41.599649 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1293 11:35:41.599721 ==
1294 11:35:41.603254 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 11:35:41.606138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 11:35:41.609803 ==
1297 11:35:41.609899 DQS Delay:
1298 11:35:41.609992 DQS0 = 0, DQS1 = 0
1299 11:35:41.612656 DQM Delay:
1300 11:35:41.612757 DQM0 = 85, DQM1 = 78
1301 11:35:41.612840 DQ Delay:
1302 11:35:41.616068 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1303 11:35:41.619701 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1304 11:35:41.622841 DQ8 =61, DQ9 =77, DQ10 =77, DQ11 =77
1305 11:35:41.626313 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1306 11:35:41.626386
1307 11:35:41.626442
1308 11:35:41.629952 ==
1309 11:35:41.632881 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 11:35:41.636825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 11:35:41.636956 ==
1312 11:35:41.637049
1313 11:35:41.637153
1314 11:35:41.639777 TX Vref Scan disable
1315 11:35:41.639850 == TX Byte 0 ==
1316 11:35:41.643152 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1317 11:35:41.649773 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1318 11:35:41.649847 == TX Byte 1 ==
1319 11:35:41.653333 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1320 11:35:41.659691 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1321 11:35:41.659763 ==
1322 11:35:41.663248 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 11:35:41.666939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 11:35:41.667013 ==
1325 11:35:41.679760 TX Vref=22, minBit 8, minWin=27, winSum=446
1326 11:35:41.683115 TX Vref=24, minBit 9, minWin=27, winSum=448
1327 11:35:41.686576 TX Vref=26, minBit 13, minWin=27, winSum=452
1328 11:35:41.690252 TX Vref=28, minBit 13, minWin=27, winSum=454
1329 11:35:41.693447 TX Vref=30, minBit 4, minWin=28, winSum=457
1330 11:35:41.699984 TX Vref=32, minBit 4, minWin=28, winSum=459
1331 11:35:41.704026 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 32
1332 11:35:41.704100
1333 11:35:41.706591 Final TX Range 1 Vref 32
1334 11:35:41.706665
1335 11:35:41.706722 ==
1336 11:35:41.709987 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 11:35:41.713243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 11:35:41.713318 ==
1339 11:35:41.713375
1340 11:35:41.716592
1341 11:35:41.716688 TX Vref Scan disable
1342 11:35:41.720227 == TX Byte 0 ==
1343 11:35:41.723372 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1344 11:35:41.726526 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1345 11:35:41.730345 == TX Byte 1 ==
1346 11:35:41.733439 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1347 11:35:41.737047 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1348 11:35:41.740259
1349 11:35:41.740331 [DATLAT]
1350 11:35:41.740388 Freq=800, CH0 RK1
1351 11:35:41.740441
1352 11:35:41.743437 DATLAT Default: 0xa
1353 11:35:41.743510 0, 0xFFFF, sum = 0
1354 11:35:41.746866 1, 0xFFFF, sum = 0
1355 11:35:41.746939 2, 0xFFFF, sum = 0
1356 11:35:41.750353 3, 0xFFFF, sum = 0
1357 11:35:41.750427 4, 0xFFFF, sum = 0
1358 11:35:41.753659 5, 0xFFFF, sum = 0
1359 11:35:41.753733 6, 0xFFFF, sum = 0
1360 11:35:41.756712 7, 0xFFFF, sum = 0
1361 11:35:41.760112 8, 0xFFFF, sum = 0
1362 11:35:41.760186 9, 0x0, sum = 1
1363 11:35:41.760244 10, 0x0, sum = 2
1364 11:35:41.763861 11, 0x0, sum = 3
1365 11:35:41.763935 12, 0x0, sum = 4
1366 11:35:41.766966 best_step = 10
1367 11:35:41.767039
1368 11:35:41.767095 ==
1369 11:35:41.770590 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 11:35:41.774101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:35:41.774175 ==
1372 11:35:41.777240 RX Vref Scan: 0
1373 11:35:41.777313
1374 11:35:41.777369 RX Vref 0 -> 0, step: 1
1375 11:35:41.777422
1376 11:35:41.780080 RX Delay -95 -> 252, step: 8
1377 11:35:41.786811 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1378 11:35:41.790555 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1379 11:35:41.793742 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1380 11:35:41.797366 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1381 11:35:41.801080 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1382 11:35:41.807457 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1383 11:35:41.810450 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1384 11:35:41.814197 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1385 11:35:41.817435 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1386 11:35:41.820401 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1387 11:35:41.823913 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1388 11:35:41.830603 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1389 11:35:41.834071 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1390 11:35:41.837581 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1391 11:35:41.841080 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1392 11:35:41.844670 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1393 11:35:41.847419 ==
1394 11:35:41.847492 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 11:35:41.854525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 11:35:41.854597 ==
1397 11:35:41.854654 DQS Delay:
1398 11:35:41.857848 DQS0 = 0, DQS1 = 0
1399 11:35:41.857925 DQM Delay:
1400 11:35:41.861259 DQM0 = 86, DQM1 = 78
1401 11:35:41.861337 DQ Delay:
1402 11:35:41.864135 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1403 11:35:41.867389 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1404 11:35:41.870718 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1405 11:35:41.874183 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1406 11:35:41.874291
1407 11:35:41.874393
1408 11:35:41.881141 [DQSOSCAuto] RK1, (LSB)MR18= 0x3620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1409 11:35:41.883965 CH0 RK1: MR19=606, MR18=3620
1410 11:35:41.891308 CH0_RK1: MR19=0x606, MR18=0x3620, DQSOSC=396, MR23=63, INC=94, DEC=62
1411 11:35:41.894201 [RxdqsGatingPostProcess] freq 800
1412 11:35:41.897835 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1413 11:35:41.901205 Pre-setting of DQS Precalculation
1414 11:35:41.908323 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1415 11:35:41.908601 ==
1416 11:35:41.911354 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 11:35:41.915107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 11:35:41.915464 ==
1419 11:35:41.921554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 11:35:41.927994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 11:35:41.935554 [CA 0] Center 36 (6~66) winsize 61
1422 11:35:41.938528 [CA 1] Center 36 (6~67) winsize 62
1423 11:35:41.942277 [CA 2] Center 34 (4~65) winsize 62
1424 11:35:41.945090 [CA 3] Center 33 (3~64) winsize 62
1425 11:35:41.948620 [CA 4] Center 34 (4~65) winsize 62
1426 11:35:41.951967 [CA 5] Center 33 (3~64) winsize 62
1427 11:35:41.952353
1428 11:35:41.955404 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 11:35:41.955797
1430 11:35:41.958760 [CATrainingPosCal] consider 1 rank data
1431 11:35:41.962132 u2DelayCellTimex100 = 270/100 ps
1432 11:35:41.965661 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1433 11:35:41.968763 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 11:35:41.972833 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 11:35:41.979091 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 11:35:41.982129 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 11:35:41.986050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1438 11:35:41.986448
1439 11:35:41.989016 CA PerBit enable=1, Macro0, CA PI delay=33
1440 11:35:41.989420
1441 11:35:41.992385 [CBTSetCACLKResult] CA Dly = 33
1442 11:35:41.992768 CS Dly: 5 (0~36)
1443 11:35:41.993068 ==
1444 11:35:41.995745 Dram Type= 6, Freq= 0, CH_1, rank 1
1445 11:35:41.999102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 11:35:42.002500 ==
1447 11:35:42.005926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 11:35:42.013092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 11:35:42.021448 [CA 0] Center 36 (6~66) winsize 61
1450 11:35:42.024782 [CA 1] Center 36 (6~66) winsize 61
1451 11:35:42.028518 [CA 2] Center 34 (4~65) winsize 62
1452 11:35:42.031277 [CA 3] Center 33 (3~64) winsize 62
1453 11:35:42.034420 [CA 4] Center 34 (4~65) winsize 62
1454 11:35:42.038044 [CA 5] Center 33 (3~64) winsize 62
1455 11:35:42.038431
1456 11:35:42.041460 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 11:35:42.041853
1458 11:35:42.044906 [CATrainingPosCal] consider 2 rank data
1459 11:35:42.048659 u2DelayCellTimex100 = 270/100 ps
1460 11:35:42.051567 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1461 11:35:42.054781 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 11:35:42.058048 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 11:35:42.064911 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 11:35:42.068091 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 11:35:42.071484 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1466 11:35:42.071874
1467 11:35:42.074785 CA PerBit enable=1, Macro0, CA PI delay=33
1468 11:35:42.075173
1469 11:35:42.078088 [CBTSetCACLKResult] CA Dly = 33
1470 11:35:42.078480 CS Dly: 5 (0~37)
1471 11:35:42.078866
1472 11:35:42.081763 ----->DramcWriteLeveling(PI) begin...
1473 11:35:42.082157 ==
1474 11:35:42.084901 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 11:35:42.091293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 11:35:42.091727 ==
1477 11:35:42.094972 Write leveling (Byte 0): 27 => 27
1478 11:35:42.098268 Write leveling (Byte 1): 29 => 29
1479 11:35:42.098644 DramcWriteLeveling(PI) end<-----
1480 11:35:42.098960
1481 11:35:42.101655 ==
1482 11:35:42.104887 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 11:35:42.108125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 11:35:42.108473 ==
1485 11:35:42.111566 [Gating] SW mode calibration
1486 11:35:42.118435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1487 11:35:42.121700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1488 11:35:42.128549 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 11:35:42.131580 0 6 4 | B1->B0 | 2423 2323 | 1 0 | (1 0) (1 1)
1490 11:35:42.135213 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1491 11:35:42.141609 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:35:42.145052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:35:42.148622 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:35:42.152052 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:35:42.158835 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:35:42.161925 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:35:42.165636 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:35:42.172105 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:35:42.175394 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1500 11:35:42.178692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:35:42.185562 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:35:42.189006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:35:42.192203 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1504 11:35:42.199228 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:35:42.202319 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:35:42.206195 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1507 11:35:42.208857 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:35:42.215625 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:35:42.218827 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:35:42.222283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:35:42.229446 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:35:42.232381 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:35:42.235904 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:35:42.242742 0 9 8 | B1->B0 | 2525 2828 | 1 0 | (1 1) (0 0)
1515 11:35:42.245907 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 11:35:42.249223 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 11:35:42.255947 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 11:35:42.259466 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 11:35:42.262873 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 11:35:42.269693 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 11:35:42.272757 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1522 11:35:42.275817 0 10 8 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
1523 11:35:42.279581 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:35:42.286291 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:35:42.289345 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:35:42.292667 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:35:42.299629 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:35:42.302754 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:35:42.306127 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:35:42.313158 0 11 8 | B1->B0 | 3737 3535 | 0 1 | (0 0) (0 0)
1531 11:35:42.316367 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 11:35:42.319986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 11:35:42.326076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 11:35:42.329992 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 11:35:42.333442 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 11:35:42.336619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 11:35:42.343378 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 11:35:42.346737 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1539 11:35:42.350204 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 11:35:42.356874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 11:35:42.360076 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 11:35:42.363391 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 11:35:42.369877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 11:35:42.373439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:35:42.376923 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:35:42.383617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:35:42.387006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:35:42.390236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:35:42.393373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:35:42.400445 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:35:42.404068 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:35:42.407505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:35:42.413617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1554 11:35:42.417031 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1555 11:35:42.420480 Total UI for P1: 0, mck2ui 16
1556 11:35:42.423803 best dqsien dly found for B0: ( 0, 14, 4)
1557 11:35:42.427117 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:35:42.430624 Total UI for P1: 0, mck2ui 16
1559 11:35:42.433922 best dqsien dly found for B1: ( 0, 14, 8)
1560 11:35:42.437060 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1561 11:35:42.440359 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1562 11:35:42.440717
1563 11:35:42.444202 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1564 11:35:42.450398 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1565 11:35:42.450761 [Gating] SW calibration Done
1566 11:35:42.451071 ==
1567 11:35:42.454020 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 11:35:42.460486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 11:35:42.460883 ==
1570 11:35:42.461311 RX Vref Scan: 0
1571 11:35:42.461613
1572 11:35:42.464288 RX Vref 0 -> 0, step: 1
1573 11:35:42.464716
1574 11:35:42.467090 RX Delay -130 -> 252, step: 16
1575 11:35:42.470499 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1576 11:35:42.473731 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1577 11:35:42.477057 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1578 11:35:42.483967 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1579 11:35:42.487478 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1580 11:35:42.490834 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1581 11:35:42.494203 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1582 11:35:42.497308 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1583 11:35:42.503747 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1584 11:35:42.507396 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1585 11:35:42.510739 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1586 11:35:42.513997 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1587 11:35:42.517104 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1588 11:35:42.524073 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1589 11:35:42.527647 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1590 11:35:42.531392 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1591 11:35:42.531852 ==
1592 11:35:42.533998 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 11:35:42.537556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 11:35:42.537961 ==
1595 11:35:42.540788 DQS Delay:
1596 11:35:42.541207 DQS0 = 0, DQS1 = 0
1597 11:35:42.541510 DQM Delay:
1598 11:35:42.544328 DQM0 = 83, DQM1 = 75
1599 11:35:42.544706 DQ Delay:
1600 11:35:42.547351 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1601 11:35:42.550617 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1602 11:35:42.554487 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1603 11:35:42.557541 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1604 11:35:42.557918
1605 11:35:42.558211
1606 11:35:42.558479 ==
1607 11:35:42.560920 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 11:35:42.567753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 11:35:42.568134 ==
1610 11:35:42.568426
1611 11:35:42.568696
1612 11:35:42.568955 TX Vref Scan disable
1613 11:35:42.571179 == TX Byte 0 ==
1614 11:35:42.574535 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1615 11:35:42.577644 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1616 11:35:42.581366 == TX Byte 1 ==
1617 11:35:42.584009 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1618 11:35:42.587620 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1619 11:35:42.590930 ==
1620 11:35:42.594137 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 11:35:42.597299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 11:35:42.597707 ==
1623 11:35:42.609710 TX Vref=22, minBit 10, minWin=26, winSum=438
1624 11:35:42.613558 TX Vref=24, minBit 0, minWin=27, winSum=441
1625 11:35:42.616480 TX Vref=26, minBit 0, minWin=27, winSum=445
1626 11:35:42.620024 TX Vref=28, minBit 8, minWin=27, winSum=451
1627 11:35:42.623645 TX Vref=30, minBit 0, minWin=28, winSum=455
1628 11:35:42.626964 TX Vref=32, minBit 9, minWin=27, winSum=453
1629 11:35:42.633613 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1630 11:35:42.633991
1631 11:35:42.636739 Final TX Range 1 Vref 30
1632 11:35:42.637155
1633 11:35:42.637491 ==
1634 11:35:42.640068 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 11:35:42.643406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 11:35:42.643787 ==
1637 11:35:42.644080
1638 11:35:42.644346
1639 11:35:42.646954 TX Vref Scan disable
1640 11:35:42.650634 == TX Byte 0 ==
1641 11:35:42.653733 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1642 11:35:42.657221 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1643 11:35:42.659999 == TX Byte 1 ==
1644 11:35:42.663754 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1645 11:35:42.666686 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1646 11:35:42.667074
1647 11:35:42.670094 [DATLAT]
1648 11:35:42.670513 Freq=800, CH1 RK0
1649 11:35:42.670811
1650 11:35:42.673560 DATLAT Default: 0xa
1651 11:35:42.674065 0, 0xFFFF, sum = 0
1652 11:35:42.677088 1, 0xFFFF, sum = 0
1653 11:35:42.677512 2, 0xFFFF, sum = 0
1654 11:35:42.680383 3, 0xFFFF, sum = 0
1655 11:35:42.680766 4, 0xFFFF, sum = 0
1656 11:35:42.683814 5, 0xFFFF, sum = 0
1657 11:35:42.684240 6, 0xFFFF, sum = 0
1658 11:35:42.687183 7, 0xFFFF, sum = 0
1659 11:35:42.687607 8, 0xFFFF, sum = 0
1660 11:35:42.690214 9, 0x0, sum = 1
1661 11:35:42.690580 10, 0x0, sum = 2
1662 11:35:42.693837 11, 0x0, sum = 3
1663 11:35:42.694191 12, 0x0, sum = 4
1664 11:35:42.697030 best_step = 10
1665 11:35:42.697529
1666 11:35:42.697952 ==
1667 11:35:42.700194 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 11:35:42.703773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 11:35:42.704263 ==
1670 11:35:42.707390 RX Vref Scan: 1
1671 11:35:42.707903
1672 11:35:42.708322 Set Vref Range= 32 -> 127
1673 11:35:42.708622
1674 11:35:42.710335 RX Vref 32 -> 127, step: 1
1675 11:35:42.710795
1676 11:35:42.714062 RX Delay -111 -> 252, step: 8
1677 11:35:42.714451
1678 11:35:42.717154 Set Vref, RX VrefLevel [Byte0]: 32
1679 11:35:42.720570 [Byte1]: 32
1680 11:35:42.720969
1681 11:35:42.723690 Set Vref, RX VrefLevel [Byte0]: 33
1682 11:35:42.727377 [Byte1]: 33
1683 11:35:42.730752
1684 11:35:42.731141 Set Vref, RX VrefLevel [Byte0]: 34
1685 11:35:42.733660 [Byte1]: 34
1686 11:35:42.738319
1687 11:35:42.738729 Set Vref, RX VrefLevel [Byte0]: 35
1688 11:35:42.741284 [Byte1]: 35
1689 11:35:42.745686
1690 11:35:42.746073 Set Vref, RX VrefLevel [Byte0]: 36
1691 11:35:42.748776 [Byte1]: 36
1692 11:35:42.753499
1693 11:35:42.753915 Set Vref, RX VrefLevel [Byte0]: 37
1694 11:35:42.756570 [Byte1]: 37
1695 11:35:42.760880
1696 11:35:42.761372 Set Vref, RX VrefLevel [Byte0]: 38
1697 11:35:42.764738 [Byte1]: 38
1698 11:35:42.768365
1699 11:35:42.768762 Set Vref, RX VrefLevel [Byte0]: 39
1700 11:35:42.773895 [Byte1]: 39
1701 11:35:42.776171
1702 11:35:42.776694 Set Vref, RX VrefLevel [Byte0]: 40
1703 11:35:42.779745 [Byte1]: 40
1704 11:35:42.784172
1705 11:35:42.784575 Set Vref, RX VrefLevel [Byte0]: 41
1706 11:35:42.787114 [Byte1]: 41
1707 11:35:42.792058
1708 11:35:42.792648 Set Vref, RX VrefLevel [Byte0]: 42
1709 11:35:42.795094 [Byte1]: 42
1710 11:35:42.799124
1711 11:35:42.799500 Set Vref, RX VrefLevel [Byte0]: 43
1712 11:35:42.802586 [Byte1]: 43
1713 11:35:42.806685
1714 11:35:42.807104 Set Vref, RX VrefLevel [Byte0]: 44
1715 11:35:42.810207 [Byte1]: 44
1716 11:35:42.814420
1717 11:35:42.815040 Set Vref, RX VrefLevel [Byte0]: 45
1718 11:35:42.817679 [Byte1]: 45
1719 11:35:42.822661
1720 11:35:42.823035 Set Vref, RX VrefLevel [Byte0]: 46
1721 11:35:42.825576 [Byte1]: 46
1722 11:35:42.829922
1723 11:35:42.830325 Set Vref, RX VrefLevel [Byte0]: 47
1724 11:35:42.832981 [Byte1]: 47
1725 11:35:42.837610
1726 11:35:42.838036 Set Vref, RX VrefLevel [Byte0]: 48
1727 11:35:42.840586 [Byte1]: 48
1728 11:35:42.845081
1729 11:35:42.845500 Set Vref, RX VrefLevel [Byte0]: 49
1730 11:35:42.848428 [Byte1]: 49
1731 11:35:42.852574
1732 11:35:42.852960 Set Vref, RX VrefLevel [Byte0]: 50
1733 11:35:42.855986 [Byte1]: 50
1734 11:35:42.860603
1735 11:35:42.860977 Set Vref, RX VrefLevel [Byte0]: 51
1736 11:35:42.863952 [Byte1]: 51
1737 11:35:42.868329
1738 11:35:42.868703 Set Vref, RX VrefLevel [Byte0]: 52
1739 11:35:42.871487 [Byte1]: 52
1740 11:35:42.875549
1741 11:35:42.875924 Set Vref, RX VrefLevel [Byte0]: 53
1742 11:35:42.879111 [Byte1]: 53
1743 11:35:42.882885
1744 11:35:42.882993 Set Vref, RX VrefLevel [Byte0]: 54
1745 11:35:42.886123 [Byte1]: 54
1746 11:35:42.890399
1747 11:35:42.890472 Set Vref, RX VrefLevel [Byte0]: 55
1748 11:35:42.894433 [Byte1]: 55
1749 11:35:42.898424
1750 11:35:42.898497 Set Vref, RX VrefLevel [Byte0]: 56
1751 11:35:42.901493 [Byte1]: 56
1752 11:35:42.905783
1753 11:35:42.905856 Set Vref, RX VrefLevel [Byte0]: 57
1754 11:35:42.909376 [Byte1]: 57
1755 11:35:42.913641
1756 11:35:42.913714 Set Vref, RX VrefLevel [Byte0]: 58
1757 11:35:42.916963 [Byte1]: 58
1758 11:35:42.921048
1759 11:35:42.921126 Set Vref, RX VrefLevel [Byte0]: 59
1760 11:35:42.924821 [Byte1]: 59
1761 11:35:42.928623
1762 11:35:42.928696 Set Vref, RX VrefLevel [Byte0]: 60
1763 11:35:42.932310 [Byte1]: 60
1764 11:35:42.936631
1765 11:35:42.936704 Set Vref, RX VrefLevel [Byte0]: 61
1766 11:35:42.939980 [Byte1]: 61
1767 11:35:42.944309
1768 11:35:42.944382 Set Vref, RX VrefLevel [Byte0]: 62
1769 11:35:42.947568 [Byte1]: 62
1770 11:35:42.952518
1771 11:35:42.952591 Set Vref, RX VrefLevel [Byte0]: 63
1772 11:35:42.954945 [Byte1]: 63
1773 11:35:42.959239
1774 11:35:42.959312 Set Vref, RX VrefLevel [Byte0]: 64
1775 11:35:42.962820 [Byte1]: 64
1776 11:35:42.967047
1777 11:35:42.967120 Set Vref, RX VrefLevel [Byte0]: 65
1778 11:35:42.970330 [Byte1]: 65
1779 11:35:42.974609
1780 11:35:42.974682 Set Vref, RX VrefLevel [Byte0]: 66
1781 11:35:42.977797 [Byte1]: 66
1782 11:35:42.982310
1783 11:35:42.982383 Set Vref, RX VrefLevel [Byte0]: 67
1784 11:35:42.985772 [Byte1]: 67
1785 11:35:42.989798
1786 11:35:42.989872 Set Vref, RX VrefLevel [Byte0]: 68
1787 11:35:42.993148 [Byte1]: 68
1788 11:35:42.997635
1789 11:35:42.997708 Set Vref, RX VrefLevel [Byte0]: 69
1790 11:35:43.000925 [Byte1]: 69
1791 11:35:43.005163
1792 11:35:43.005239 Set Vref, RX VrefLevel [Byte0]: 70
1793 11:35:43.008634 [Byte1]: 70
1794 11:35:43.012864
1795 11:35:43.012937 Set Vref, RX VrefLevel [Byte0]: 71
1796 11:35:43.016209 [Byte1]: 71
1797 11:35:43.020788
1798 11:35:43.020861 Set Vref, RX VrefLevel [Byte0]: 72
1799 11:35:43.024090 [Byte1]: 72
1800 11:35:43.028492
1801 11:35:43.028565 Set Vref, RX VrefLevel [Byte0]: 73
1802 11:35:43.031785 [Byte1]: 73
1803 11:35:43.035725
1804 11:35:43.035798 Set Vref, RX VrefLevel [Byte0]: 74
1805 11:35:43.039040 [Byte1]: 74
1806 11:35:43.044300
1807 11:35:43.044375 Set Vref, RX VrefLevel [Byte0]: 75
1808 11:35:43.046923 [Byte1]: 75
1809 11:35:43.051093
1810 11:35:43.051166 Set Vref, RX VrefLevel [Byte0]: 76
1811 11:35:43.054582 [Byte1]: 76
1812 11:35:43.059117
1813 11:35:43.059190 Set Vref, RX VrefLevel [Byte0]: 77
1814 11:35:43.062289 [Byte1]: 77
1815 11:35:43.066372
1816 11:35:43.066445 Set Vref, RX VrefLevel [Byte0]: 78
1817 11:35:43.069787 [Byte1]: 78
1818 11:35:43.074072
1819 11:35:43.074144 Set Vref, RX VrefLevel [Byte0]: 79
1820 11:35:43.077400 [Byte1]: 79
1821 11:35:43.081770
1822 11:35:43.081846 Set Vref, RX VrefLevel [Byte0]: 80
1823 11:35:43.085357 [Byte1]: 80
1824 11:35:43.089240
1825 11:35:43.089317 Set Vref, RX VrefLevel [Byte0]: 81
1826 11:35:43.092648 [Byte1]: 81
1827 11:35:43.097328
1828 11:35:43.097400 Final RX Vref Byte 0 = 59 to rank0
1829 11:35:43.100593 Final RX Vref Byte 1 = 58 to rank0
1830 11:35:43.104279 Final RX Vref Byte 0 = 59 to rank1
1831 11:35:43.107158 Final RX Vref Byte 1 = 58 to rank1==
1832 11:35:43.110709 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 11:35:43.113865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:35:43.117288 ==
1835 11:35:43.117363 DQS Delay:
1836 11:35:43.117421 DQS0 = 0, DQS1 = 0
1837 11:35:43.120331 DQM Delay:
1838 11:35:43.120404 DQM0 = 83, DQM1 = 73
1839 11:35:43.123777 DQ Delay:
1840 11:35:43.123851 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1841 11:35:43.127295 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1842 11:35:43.130813 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1843 11:35:43.134622 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1844 11:35:43.134696
1845 11:35:43.134753
1846 11:35:43.144420 [DQSOSCAuto] RK0, (LSB)MR18= 0x3105, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
1847 11:35:43.148111 CH1 RK0: MR19=606, MR18=3105
1848 11:35:43.150787 CH1_RK0: MR19=0x606, MR18=0x3105, DQSOSC=397, MR23=63, INC=93, DEC=62
1849 11:35:43.154359
1850 11:35:43.157676 ----->DramcWriteLeveling(PI) begin...
1851 11:35:43.157751 ==
1852 11:35:43.160727 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 11:35:43.164470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 11:35:43.164548 ==
1855 11:35:43.167640 Write leveling (Byte 0): 27 => 27
1856 11:35:43.170954 Write leveling (Byte 1): 27 => 27
1857 11:35:43.174348 DramcWriteLeveling(PI) end<-----
1858 11:35:43.174451
1859 11:35:43.174510 ==
1860 11:35:43.177858 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 11:35:43.181005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 11:35:43.181080 ==
1863 11:35:43.184412 [Gating] SW mode calibration
1864 11:35:43.191172 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 11:35:43.194771 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 11:35:43.201951 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 11:35:43.204684 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1868 11:35:43.208478 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:35:43.214941 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:35:43.218505 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:35:43.221545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:35:43.227985 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:35:43.231483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:35:43.235463 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:35:43.238428 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:35:43.244994 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:35:43.248140 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1878 11:35:43.251509 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:35:43.258869 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:35:43.261463 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1881 11:35:43.265281 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:35:43.272322 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1883 11:35:43.275290 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1884 11:35:43.278703 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:35:43.285156 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1886 11:35:43.288429 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:35:43.291957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:35:43.298585 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:35:43.302051 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:35:43.305137 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:35:43.308579 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1892 11:35:43.315745 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1893 11:35:43.318711 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 11:35:43.322089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 11:35:43.328961 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:35:43.331835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:35:43.335382 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:35:43.341956 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:35:43.345601 0 10 4 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (1 0)
1900 11:35:43.349211 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
1901 11:35:43.355400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:35:43.358975 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:35:43.361898 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:35:43.368667 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:35:43.372348 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:35:43.375492 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:35:43.379070 0 11 4 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
1908 11:35:43.385774 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1909 11:35:43.389231 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 11:35:43.392454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 11:35:43.398796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:35:43.402163 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:35:43.405705 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:35:43.412246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:35:43.416182 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 11:35:43.419164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1917 11:35:43.426172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:35:43.429000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:35:43.432510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:35:43.435789 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:35:43.442963 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:35:43.445751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:35:43.449257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:35:43.455907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:35:43.459678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:35:43.462742 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:35:43.469836 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:35:43.472943 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:35:43.476341 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:35:43.482991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:35:43.486505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1932 11:35:43.489501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:35:43.492781 Total UI for P1: 0, mck2ui 16
1934 11:35:43.496486 best dqsien dly found for B0: ( 0, 14, 4)
1935 11:35:43.499343 Total UI for P1: 0, mck2ui 16
1936 11:35:43.502730 best dqsien dly found for B1: ( 0, 14, 6)
1937 11:35:43.506127 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 11:35:43.509775 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1939 11:35:43.509848
1940 11:35:43.512882 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 11:35:43.516351 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1942 11:35:43.519478 [Gating] SW calibration Done
1943 11:35:43.519552 ==
1944 11:35:43.523268 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 11:35:43.529759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 11:35:43.529833 ==
1947 11:35:43.529891 RX Vref Scan: 0
1948 11:35:43.529945
1949 11:35:43.533052 RX Vref 0 -> 0, step: 1
1950 11:35:43.533146
1951 11:35:43.537001 RX Delay -130 -> 252, step: 16
1952 11:35:43.539519 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1953 11:35:43.543188 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1954 11:35:43.546258 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1955 11:35:43.549952 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1956 11:35:43.556252 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1957 11:35:43.559679 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1958 11:35:43.563235 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1959 11:35:43.566731 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1960 11:35:43.570756 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1961 11:35:43.576547 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1962 11:35:43.580178 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1963 11:35:43.583941 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1964 11:35:43.587416 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1965 11:35:43.590103 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1966 11:35:43.596499 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1967 11:35:43.600085 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1968 11:35:43.600174 ==
1969 11:35:43.603799 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 11:35:43.606939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 11:35:43.607012 ==
1972 11:35:43.607069 DQS Delay:
1973 11:35:43.610407 DQS0 = 0, DQS1 = 0
1974 11:35:43.610482 DQM Delay:
1975 11:35:43.613760 DQM0 = 82, DQM1 = 77
1976 11:35:43.613833 DQ Delay:
1977 11:35:43.617333 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1978 11:35:43.620750 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1979 11:35:43.623899 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1980 11:35:43.626851 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1981 11:35:43.626924
1982 11:35:43.626980
1983 11:35:43.627046 ==
1984 11:35:43.630461 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:35:43.633719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:35:43.633793 ==
1987 11:35:43.636836
1988 11:35:43.636909
1989 11:35:43.636965 TX Vref Scan disable
1990 11:35:43.640136 == TX Byte 0 ==
1991 11:35:43.643988 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1992 11:35:43.647245 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1993 11:35:43.650702 == TX Byte 1 ==
1994 11:35:43.653799 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1995 11:35:43.657331 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1996 11:35:43.657404 ==
1997 11:35:43.660932 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 11:35:43.667611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 11:35:43.667685 ==
2000 11:35:43.678784 TX Vref=22, minBit 11, minWin=27, winSum=445
2001 11:35:43.682304 TX Vref=24, minBit 9, minWin=27, winSum=441
2002 11:35:43.685617 TX Vref=26, minBit 12, minWin=27, winSum=447
2003 11:35:43.689027 TX Vref=28, minBit 10, minWin=27, winSum=449
2004 11:35:43.692215 TX Vref=30, minBit 11, minWin=27, winSum=447
2005 11:35:43.699692 TX Vref=32, minBit 0, minWin=28, winSum=453
2006 11:35:43.702517 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
2007 11:35:43.702591
2008 11:35:43.705511 Final TX Range 1 Vref 32
2009 11:35:43.705585
2010 11:35:43.705641 ==
2011 11:35:43.709142 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 11:35:43.712322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 11:35:43.712396 ==
2014 11:35:43.712453
2015 11:35:43.716138
2016 11:35:43.716211 TX Vref Scan disable
2017 11:35:43.719140 == TX Byte 0 ==
2018 11:35:43.722531 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 11:35:43.725673 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 11:35:43.729101 == TX Byte 1 ==
2021 11:35:43.732293 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2022 11:35:43.735737 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2023 11:35:43.735811
2024 11:35:43.739503 [DATLAT]
2025 11:35:43.739576 Freq=800, CH1 RK1
2026 11:35:43.739633
2027 11:35:43.742290 DATLAT Default: 0xa
2028 11:35:43.742364 0, 0xFFFF, sum = 0
2029 11:35:43.746021 1, 0xFFFF, sum = 0
2030 11:35:43.746120 2, 0xFFFF, sum = 0
2031 11:35:43.749261 3, 0xFFFF, sum = 0
2032 11:35:43.749335 4, 0xFFFF, sum = 0
2033 11:35:43.752687 5, 0xFFFF, sum = 0
2034 11:35:43.752762 6, 0xFFFF, sum = 0
2035 11:35:43.756157 7, 0xFFFF, sum = 0
2036 11:35:43.756232 8, 0xFFFF, sum = 0
2037 11:35:43.759311 9, 0x0, sum = 1
2038 11:35:43.759386 10, 0x0, sum = 2
2039 11:35:43.762475 11, 0x0, sum = 3
2040 11:35:43.762550 12, 0x0, sum = 4
2041 11:35:43.766252 best_step = 10
2042 11:35:43.766324
2043 11:35:43.766381 ==
2044 11:35:43.769466 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 11:35:43.772834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 11:35:43.772908 ==
2047 11:35:43.775920 RX Vref Scan: 0
2048 11:35:43.775993
2049 11:35:43.776050 RX Vref 0 -> 0, step: 1
2050 11:35:43.776103
2051 11:35:43.779883 RX Delay -95 -> 252, step: 8
2052 11:35:43.786351 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2053 11:35:43.789410 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2054 11:35:43.793106 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2055 11:35:43.796132 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2056 11:35:43.799741 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2057 11:35:43.803125 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2058 11:35:43.809702 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2059 11:35:43.813476 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2060 11:35:43.816688 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2061 11:35:43.819638 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2062 11:35:43.823235 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
2063 11:35:43.830373 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2064 11:35:43.833077 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2065 11:35:43.836636 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2066 11:35:43.840100 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2067 11:35:43.843421 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2068 11:35:43.843510 ==
2069 11:35:43.846503 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 11:35:43.853459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 11:35:43.853530 ==
2072 11:35:43.853606 DQS Delay:
2073 11:35:43.856712 DQS0 = 0, DQS1 = 0
2074 11:35:43.856776 DQM Delay:
2075 11:35:43.856848 DQM0 = 80, DQM1 = 75
2076 11:35:43.859956 DQ Delay:
2077 11:35:43.863838 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2078 11:35:43.866860 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2079 11:35:43.870585 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =68
2080 11:35:43.873469 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2081 11:35:43.873543
2082 11:35:43.873600
2083 11:35:43.880585 [DQSOSCAuto] RK1, (LSB)MR18= 0x202a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
2084 11:35:43.883697 CH1 RK1: MR19=606, MR18=202A
2085 11:35:43.890633 CH1_RK1: MR19=0x606, MR18=0x202A, DQSOSC=399, MR23=63, INC=92, DEC=61
2086 11:35:43.893956 [RxdqsGatingPostProcess] freq 800
2087 11:35:43.897013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 11:35:43.900528 Pre-setting of DQS Precalculation
2089 11:35:43.906878 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 11:35:43.913924 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 11:35:43.920676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 11:35:43.920787
2093 11:35:43.920871
2094 11:35:43.923731 [Calibration Summary] 1600 Mbps
2095 11:35:43.923806 CH 0, Rank 0
2096 11:35:43.927008 SW Impedance : PASS
2097 11:35:43.930297 DUTY Scan : NO K
2098 11:35:43.930370 ZQ Calibration : PASS
2099 11:35:43.933997 Jitter Meter : NO K
2100 11:35:43.934071 CBT Training : PASS
2101 11:35:43.937236 Write leveling : PASS
2102 11:35:43.940206 RX DQS gating : PASS
2103 11:35:43.940304 RX DQ/DQS(RDDQC) : PASS
2104 11:35:43.943655 TX DQ/DQS : PASS
2105 11:35:43.946968 RX DATLAT : PASS
2106 11:35:43.947059 RX DQ/DQS(Engine): PASS
2107 11:35:43.950682 TX OE : NO K
2108 11:35:43.950756 All Pass.
2109 11:35:43.950813
2110 11:35:43.954408 CH 0, Rank 1
2111 11:35:43.954481 SW Impedance : PASS
2112 11:35:43.957337 DUTY Scan : NO K
2113 11:35:43.960377 ZQ Calibration : PASS
2114 11:35:43.960450 Jitter Meter : NO K
2115 11:35:43.963978 CBT Training : PASS
2116 11:35:43.967392 Write leveling : PASS
2117 11:35:43.967466 RX DQS gating : PASS
2118 11:35:43.970600 RX DQ/DQS(RDDQC) : PASS
2119 11:35:43.970674 TX DQ/DQS : PASS
2120 11:35:43.974161 RX DATLAT : PASS
2121 11:35:43.977302 RX DQ/DQS(Engine): PASS
2122 11:35:43.977376 TX OE : NO K
2123 11:35:43.980986 All Pass.
2124 11:35:43.981059
2125 11:35:43.981140 CH 1, Rank 0
2126 11:35:43.984089 SW Impedance : PASS
2127 11:35:43.984163 DUTY Scan : NO K
2128 11:35:43.987312 ZQ Calibration : PASS
2129 11:35:43.990838 Jitter Meter : NO K
2130 11:35:43.990985 CBT Training : PASS
2131 11:35:43.994138 Write leveling : PASS
2132 11:35:43.998711 RX DQS gating : PASS
2133 11:35:43.998785 RX DQ/DQS(RDDQC) : PASS
2134 11:35:44.000930 TX DQ/DQS : PASS
2135 11:35:44.001004 RX DATLAT : PASS
2136 11:35:44.004425 RX DQ/DQS(Engine): PASS
2137 11:35:44.007538 TX OE : NO K
2138 11:35:44.007612 All Pass.
2139 11:35:44.007719
2140 11:35:44.007778 CH 1, Rank 1
2141 11:35:44.010715 SW Impedance : PASS
2142 11:35:44.014671 DUTY Scan : NO K
2143 11:35:44.014747 ZQ Calibration : PASS
2144 11:35:44.017267 Jitter Meter : NO K
2145 11:35:44.021010 CBT Training : PASS
2146 11:35:44.021083 Write leveling : PASS
2147 11:35:44.024198 RX DQS gating : PASS
2148 11:35:44.027744 RX DQ/DQS(RDDQC) : PASS
2149 11:35:44.027832 TX DQ/DQS : PASS
2150 11:35:44.030908 RX DATLAT : PASS
2151 11:35:44.034482 RX DQ/DQS(Engine): PASS
2152 11:35:44.034556 TX OE : NO K
2153 11:35:44.034613 All Pass.
2154 11:35:44.037474
2155 11:35:44.037546 DramC Write-DBI off
2156 11:35:44.041350 PER_BANK_REFRESH: Hybrid Mode
2157 11:35:44.041530 TX_TRACKING: ON
2158 11:35:44.044268 [GetDramInforAfterCalByMRR] Vendor 6.
2159 11:35:44.047681 [GetDramInforAfterCalByMRR] Revision 606.
2160 11:35:44.054999 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 11:35:44.055097 MR0 0x3b3b
2162 11:35:44.055189 MR8 0x5151
2163 11:35:44.057869 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 11:35:44.057996
2165 11:35:44.060891 MR0 0x3b3b
2166 11:35:44.060964 MR8 0x5151
2167 11:35:44.064865 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 11:35:44.064962
2169 11:35:44.074631 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 11:35:44.078051 [FAST_K] Save calibration result to emmc
2171 11:35:44.081270 [FAST_K] Save calibration result to emmc
2172 11:35:44.085043 dram_init: config_dvfs: 1
2173 11:35:44.087825 dramc_set_vcore_voltage set vcore to 662500
2174 11:35:44.087895 Read voltage for 1200, 2
2175 11:35:44.090997 Vio18 = 0
2176 11:35:44.091094 Vcore = 662500
2177 11:35:44.091186 Vdram = 0
2178 11:35:44.094390 Vddq = 0
2179 11:35:44.094493 Vmddr = 0
2180 11:35:44.097996 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 11:35:44.104548 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 11:35:44.107858 MEM_TYPE=3, freq_sel=15
2183 11:35:44.111946 sv_algorithm_assistance_LP4_1600
2184 11:35:44.114561 ============ PULL DRAM RESETB DOWN ============
2185 11:35:44.118287 ========== PULL DRAM RESETB DOWN end =========
2186 11:35:44.121476 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 11:35:44.124973 ===================================
2188 11:35:44.127935 LPDDR4 DRAM CONFIGURATION
2189 11:35:44.131676 ===================================
2190 11:35:44.134809 EX_ROW_EN[0] = 0x0
2191 11:35:44.134907 EX_ROW_EN[1] = 0x0
2192 11:35:44.138354 LP4Y_EN = 0x0
2193 11:35:44.138451 WORK_FSP = 0x0
2194 11:35:44.142173 WL = 0x4
2195 11:35:44.142247 RL = 0x4
2196 11:35:44.144876 BL = 0x2
2197 11:35:44.144966 RPST = 0x0
2198 11:35:44.148424 RD_PRE = 0x0
2199 11:35:44.148498 WR_PRE = 0x1
2200 11:35:44.151624 WR_PST = 0x0
2201 11:35:44.151698 DBI_WR = 0x0
2202 11:35:44.155300 DBI_RD = 0x0
2203 11:35:44.155373 OTF = 0x1
2204 11:35:44.158346 ===================================
2205 11:35:44.161924 ===================================
2206 11:35:44.165339 ANA top config
2207 11:35:44.168450 ===================================
2208 11:35:44.168524 DLL_ASYNC_EN = 0
2209 11:35:44.171869 ALL_SLAVE_EN = 0
2210 11:35:44.175202 NEW_RANK_MODE = 1
2211 11:35:44.178685 DLL_IDLE_MODE = 1
2212 11:35:44.182038 LP45_APHY_COMB_EN = 1
2213 11:35:44.182112 TX_ODT_DIS = 1
2214 11:35:44.185254 NEW_8X_MODE = 1
2215 11:35:44.188541 ===================================
2216 11:35:44.191574 ===================================
2217 11:35:44.194902 data_rate = 2400
2218 11:35:44.198741 CKR = 1
2219 11:35:44.201922 DQ_P2S_RATIO = 8
2220 11:35:44.205340 ===================================
2221 11:35:44.205415 CA_P2S_RATIO = 8
2222 11:35:44.208529 DQ_CA_OPEN = 0
2223 11:35:44.211745 DQ_SEMI_OPEN = 0
2224 11:35:44.215111 CA_SEMI_OPEN = 0
2225 11:35:44.218558 CA_FULL_RATE = 0
2226 11:35:44.221847 DQ_CKDIV4_EN = 0
2227 11:35:44.221921 CA_CKDIV4_EN = 0
2228 11:35:44.225403 CA_PREDIV_EN = 0
2229 11:35:44.228651 PH8_DLY = 17
2230 11:35:44.232467 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 11:35:44.235447 DQ_AAMCK_DIV = 4
2232 11:35:44.239001 CA_AAMCK_DIV = 4
2233 11:35:44.239075 CA_ADMCK_DIV = 4
2234 11:35:44.242414 DQ_TRACK_CA_EN = 0
2235 11:35:44.245595 CA_PICK = 1200
2236 11:35:44.249663 CA_MCKIO = 1200
2237 11:35:44.252512 MCKIO_SEMI = 0
2238 11:35:44.255722 PLL_FREQ = 2366
2239 11:35:44.259226 DQ_UI_PI_RATIO = 32
2240 11:35:44.259300 CA_UI_PI_RATIO = 0
2241 11:35:44.261937 ===================================
2242 11:35:44.265433 ===================================
2243 11:35:44.268834 memory_type:LPDDR4
2244 11:35:44.272266 GP_NUM : 10
2245 11:35:44.272339 SRAM_EN : 1
2246 11:35:44.275531 MD32_EN : 0
2247 11:35:44.278863 ===================================
2248 11:35:44.282038 [ANA_INIT] >>>>>>>>>>>>>>
2249 11:35:44.282112 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 11:35:44.285759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 11:35:44.288835 ===================================
2252 11:35:44.292391 data_rate = 2400,PCW = 0X5b00
2253 11:35:44.295706 ===================================
2254 11:35:44.298852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 11:35:44.305918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 11:35:44.312531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 11:35:44.315864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 11:35:44.319046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 11:35:44.322888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 11:35:44.325955 [ANA_INIT] flow start
2261 11:35:44.326029 [ANA_INIT] PLL >>>>>>>>
2262 11:35:44.329481 [ANA_INIT] PLL <<<<<<<<
2263 11:35:44.332806 [ANA_INIT] MIDPI >>>>>>>>
2264 11:35:44.332880 [ANA_INIT] MIDPI <<<<<<<<
2265 11:35:44.335897 [ANA_INIT] DLL >>>>>>>>
2266 11:35:44.339556 [ANA_INIT] DLL <<<<<<<<
2267 11:35:44.339630 [ANA_INIT] flow end
2268 11:35:44.342773 ============ LP4 DIFF to SE enter ============
2269 11:35:44.349381 ============ LP4 DIFF to SE exit ============
2270 11:35:44.349455 [ANA_INIT] <<<<<<<<<<<<<
2271 11:35:44.352718 [Flow] Enable top DCM control >>>>>
2272 11:35:44.356057 [Flow] Enable top DCM control <<<<<
2273 11:35:44.359206 Enable DLL master slave shuffle
2274 11:35:44.366398 ==============================================================
2275 11:35:44.366472 Gating Mode config
2276 11:35:44.372976 ==============================================================
2277 11:35:44.376233 Config description:
2278 11:35:44.386725 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 11:35:44.389827 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 11:35:44.396237 SELPH_MODE 0: By rank 1: By Phase
2281 11:35:44.403074 ==============================================================
2282 11:35:44.403149 GAT_TRACK_EN = 1
2283 11:35:44.406344 RX_GATING_MODE = 2
2284 11:35:44.409730 RX_GATING_TRACK_MODE = 2
2285 11:35:44.413312 SELPH_MODE = 1
2286 11:35:44.416888 PICG_EARLY_EN = 1
2287 11:35:44.420235 VALID_LAT_VALUE = 1
2288 11:35:44.426766 ==============================================================
2289 11:35:44.429904 Enter into Gating configuration >>>>
2290 11:35:44.433350 Exit from Gating configuration <<<<
2291 11:35:44.433424 Enter into DVFS_PRE_config >>>>>
2292 11:35:44.446759 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 11:35:44.450226 Exit from DVFS_PRE_config <<<<<
2294 11:35:44.453569 Enter into PICG configuration >>>>
2295 11:35:44.457687 Exit from PICG configuration <<<<
2296 11:35:44.457760 [RX_INPUT] configuration >>>>>
2297 11:35:44.460157 [RX_INPUT] configuration <<<<<
2298 11:35:44.466910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 11:35:44.470079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 11:35:44.477011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 11:35:44.483738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 11:35:44.490548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 11:35:44.497223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 11:35:44.500282 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 11:35:44.503779 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 11:35:44.506863 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 11:35:44.513770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 11:35:44.517426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 11:35:44.520528 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 11:35:44.523680 ===================================
2311 11:35:44.527127 LPDDR4 DRAM CONFIGURATION
2312 11:35:44.530438 ===================================
2313 11:35:44.530512 EX_ROW_EN[0] = 0x0
2314 11:35:44.533829 EX_ROW_EN[1] = 0x0
2315 11:35:44.537241 LP4Y_EN = 0x0
2316 11:35:44.537315 WORK_FSP = 0x0
2317 11:35:44.540974 WL = 0x4
2318 11:35:44.541052 RL = 0x4
2319 11:35:44.544360 BL = 0x2
2320 11:35:44.544432 RPST = 0x0
2321 11:35:44.547294 RD_PRE = 0x0
2322 11:35:44.547367 WR_PRE = 0x1
2323 11:35:44.551349 WR_PST = 0x0
2324 11:35:44.551422 DBI_WR = 0x0
2325 11:35:44.554054 DBI_RD = 0x0
2326 11:35:44.554151 OTF = 0x1
2327 11:35:44.557098 ===================================
2328 11:35:44.560666 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 11:35:44.567151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 11:35:44.570836 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 11:35:44.573900 ===================================
2332 11:35:44.577630 LPDDR4 DRAM CONFIGURATION
2333 11:35:44.580495 ===================================
2334 11:35:44.580569 EX_ROW_EN[0] = 0x10
2335 11:35:44.584765 EX_ROW_EN[1] = 0x0
2336 11:35:44.584839 LP4Y_EN = 0x0
2337 11:35:44.587337 WORK_FSP = 0x0
2338 11:35:44.587411 WL = 0x4
2339 11:35:44.590836 RL = 0x4
2340 11:35:44.590910 BL = 0x2
2341 11:35:44.594004 RPST = 0x0
2342 11:35:44.594077 RD_PRE = 0x0
2343 11:35:44.597594 WR_PRE = 0x1
2344 11:35:44.597693 WR_PST = 0x0
2345 11:35:44.600665 DBI_WR = 0x0
2346 11:35:44.604649 DBI_RD = 0x0
2347 11:35:44.604722 OTF = 0x1
2348 11:35:44.607610 ===================================
2349 11:35:44.614289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 11:35:44.614363 ==
2351 11:35:44.617771 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 11:35:44.621020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 11:35:44.621128 ==
2354 11:35:44.624809 [Duty_Offset_Calibration]
2355 11:35:44.624881 B0:2 B1:-1 CA:1
2356 11:35:44.624937
2357 11:35:44.627689 [DutyScan_Calibration_Flow] k_type=0
2358 11:35:44.637425
2359 11:35:44.637498 ==CLK 0==
2360 11:35:44.640877 Final CLK duty delay cell = -4
2361 11:35:44.644191 [-4] MAX Duty = 5031%(X100), DQS PI = 6
2362 11:35:44.647699 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2363 11:35:44.651156 [-4] AVG Duty = 4953%(X100)
2364 11:35:44.651228
2365 11:35:44.654195 CH0 CLK Duty spec in!! Max-Min= 156%
2366 11:35:44.657867 [DutyScan_Calibration_Flow] ====Done====
2367 11:35:44.657941
2368 11:35:44.660898 [DutyScan_Calibration_Flow] k_type=1
2369 11:35:44.676416
2370 11:35:44.676507 ==DQS 0 ==
2371 11:35:44.679718 Final DQS duty delay cell = 0
2372 11:35:44.683449 [0] MAX Duty = 5156%(X100), DQS PI = 46
2373 11:35:44.686778 [0] MIN Duty = 5000%(X100), DQS PI = 12
2374 11:35:44.686851 [0] AVG Duty = 5078%(X100)
2375 11:35:44.689683
2376 11:35:44.689754 ==DQS 1 ==
2377 11:35:44.693512 Final DQS duty delay cell = -4
2378 11:35:44.696341 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2379 11:35:44.699843 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2380 11:35:44.703389 [-4] AVG Duty = 5062%(X100)
2381 11:35:44.703461
2382 11:35:44.706466 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2383 11:35:44.706539
2384 11:35:44.710332 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2385 11:35:44.713510 [DutyScan_Calibration_Flow] ====Done====
2386 11:35:44.713583
2387 11:35:44.716710 [DutyScan_Calibration_Flow] k_type=3
2388 11:35:44.733444
2389 11:35:44.733517 ==DQM 0 ==
2390 11:35:44.736963 Final DQM duty delay cell = 0
2391 11:35:44.740089 [0] MAX Duty = 5000%(X100), DQS PI = 46
2392 11:35:44.743549 [0] MIN Duty = 4907%(X100), DQS PI = 2
2393 11:35:44.743621 [0] AVG Duty = 4953%(X100)
2394 11:35:44.746750
2395 11:35:44.746822 ==DQM 1 ==
2396 11:35:44.750581 Final DQM duty delay cell = 0
2397 11:35:44.753571 [0] MAX Duty = 5156%(X100), DQS PI = 62
2398 11:35:44.756743 [0] MIN Duty = 5000%(X100), DQS PI = 10
2399 11:35:44.756842 [0] AVG Duty = 5078%(X100)
2400 11:35:44.760079
2401 11:35:44.763743 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2402 11:35:44.763816
2403 11:35:44.767044 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2404 11:35:44.770276 [DutyScan_Calibration_Flow] ====Done====
2405 11:35:44.770349
2406 11:35:44.773187 [DutyScan_Calibration_Flow] k_type=2
2407 11:35:44.789076
2408 11:35:44.789172 ==DQ 0 ==
2409 11:35:44.792405 Final DQ duty delay cell = -4
2410 11:35:44.796190 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2411 11:35:44.799051 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2412 11:35:44.802359 [-4] AVG Duty = 4953%(X100)
2413 11:35:44.802431
2414 11:35:44.802487 ==DQ 1 ==
2415 11:35:44.805942 Final DQ duty delay cell = 0
2416 11:35:44.809434 [0] MAX Duty = 5031%(X100), DQS PI = 18
2417 11:35:44.812578 [0] MIN Duty = 4907%(X100), DQS PI = 46
2418 11:35:44.812650 [0] AVG Duty = 4969%(X100)
2419 11:35:44.816364
2420 11:35:44.818986 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2421 11:35:44.819058
2422 11:35:44.822344 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 11:35:44.825964 [DutyScan_Calibration_Flow] ====Done====
2424 11:35:44.826037 ==
2425 11:35:44.828849 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 11:35:44.832390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 11:35:44.832489 ==
2428 11:35:44.835575 [Duty_Offset_Calibration]
2429 11:35:44.835648 B0:1 B1:1 CA:2
2430 11:35:44.835704
2431 11:35:44.839038 [DutyScan_Calibration_Flow] k_type=0
2432 11:35:44.849398
2433 11:35:44.849470 ==CLK 0==
2434 11:35:44.852798 Final CLK duty delay cell = 0
2435 11:35:44.855987 [0] MAX Duty = 5156%(X100), DQS PI = 24
2436 11:35:44.859979 [0] MIN Duty = 4938%(X100), DQS PI = 42
2437 11:35:44.860052 [0] AVG Duty = 5047%(X100)
2438 11:35:44.862650
2439 11:35:44.862722 CH1 CLK Duty spec in!! Max-Min= 218%
2440 11:35:44.869809 [DutyScan_Calibration_Flow] ====Done====
2441 11:35:44.869881
2442 11:35:44.872527 [DutyScan_Calibration_Flow] k_type=1
2443 11:35:44.888513
2444 11:35:44.888611 ==DQS 0 ==
2445 11:35:44.892032 Final DQS duty delay cell = 0
2446 11:35:44.895347 [0] MAX Duty = 5031%(X100), DQS PI = 18
2447 11:35:44.899287 [0] MIN Duty = 4813%(X100), DQS PI = 50
2448 11:35:44.899378 [0] AVG Duty = 4922%(X100)
2449 11:35:44.901853
2450 11:35:44.901941 ==DQS 1 ==
2451 11:35:44.905174 Final DQS duty delay cell = 0
2452 11:35:44.908536 [0] MAX Duty = 5062%(X100), DQS PI = 36
2453 11:35:44.912042 [0] MIN Duty = 4907%(X100), DQS PI = 16
2454 11:35:44.912140 [0] AVG Duty = 4984%(X100)
2455 11:35:44.915383
2456 11:35:44.918869 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2457 11:35:44.918942
2458 11:35:44.922023 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2459 11:35:44.925159 [DutyScan_Calibration_Flow] ====Done====
2460 11:35:44.925232
2461 11:35:44.928638 [DutyScan_Calibration_Flow] k_type=3
2462 11:35:44.945033
2463 11:35:44.945106 ==DQM 0 ==
2464 11:35:44.948445 Final DQM duty delay cell = 0
2465 11:35:44.952007 [0] MAX Duty = 5093%(X100), DQS PI = 18
2466 11:35:44.955201 [0] MIN Duty = 4876%(X100), DQS PI = 48
2467 11:35:44.955274 [0] AVG Duty = 4984%(X100)
2468 11:35:44.959236
2469 11:35:44.959309 ==DQM 1 ==
2470 11:35:44.962227 Final DQM duty delay cell = 0
2471 11:35:44.965511 [0] MAX Duty = 5125%(X100), DQS PI = 0
2472 11:35:44.969059 [0] MIN Duty = 4938%(X100), DQS PI = 24
2473 11:35:44.969141 [0] AVG Duty = 5031%(X100)
2474 11:35:44.971865
2475 11:35:44.975148 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2476 11:35:44.975222
2477 11:35:44.978531 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2478 11:35:44.982014 [DutyScan_Calibration_Flow] ====Done====
2479 11:35:44.982087
2480 11:35:44.985214 [DutyScan_Calibration_Flow] k_type=2
2481 11:35:45.001753
2482 11:35:45.001826 ==DQ 0 ==
2483 11:35:45.004987 Final DQ duty delay cell = 0
2484 11:35:45.008359 [0] MAX Duty = 5093%(X100), DQS PI = 18
2485 11:35:45.011813 [0] MIN Duty = 4907%(X100), DQS PI = 50
2486 11:35:45.011886 [0] AVG Duty = 5000%(X100)
2487 11:35:45.011944
2488 11:35:45.015564 ==DQ 1 ==
2489 11:35:45.018376 Final DQ duty delay cell = 0
2490 11:35:45.022113 [0] MAX Duty = 5093%(X100), DQS PI = 10
2491 11:35:45.025657 [0] MIN Duty = 5000%(X100), DQS PI = 2
2492 11:35:45.025731 [0] AVG Duty = 5046%(X100)
2493 11:35:45.025788
2494 11:35:45.028743 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2495 11:35:45.028816
2496 11:35:45.032594 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2497 11:35:45.035170 [DutyScan_Calibration_Flow] ====Done====
2498 11:35:45.040615 nWR fixed to 30
2499 11:35:45.043777 [ModeRegInit_LP4] CH0 RK0
2500 11:35:45.043851 [ModeRegInit_LP4] CH0 RK1
2501 11:35:45.047287 [ModeRegInit_LP4] CH1 RK0
2502 11:35:45.050723 [ModeRegInit_LP4] CH1 RK1
2503 11:35:45.050796 match AC timing 7
2504 11:35:45.057257 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 11:35:45.061021 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 11:35:45.064092 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 11:35:45.070741 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 11:35:45.074564 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 11:35:45.074664 ==
2510 11:35:45.077618 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 11:35:45.080981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 11:35:45.081055 ==
2513 11:35:45.087483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 11:35:45.094321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 11:35:45.101645 [CA 0] Center 40 (10~71) winsize 62
2516 11:35:45.104817 [CA 1] Center 39 (9~70) winsize 62
2517 11:35:45.108369 [CA 2] Center 36 (6~67) winsize 62
2518 11:35:45.111812 [CA 3] Center 35 (5~66) winsize 62
2519 11:35:45.114857 [CA 4] Center 35 (5~65) winsize 61
2520 11:35:45.118085 [CA 5] Center 34 (4~65) winsize 62
2521 11:35:45.118159
2522 11:35:45.121789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 11:35:45.121863
2524 11:35:45.125049 [CATrainingPosCal] consider 1 rank data
2525 11:35:45.128255 u2DelayCellTimex100 = 270/100 ps
2526 11:35:45.131616 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2527 11:35:45.135202 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2528 11:35:45.141959 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2529 11:35:45.145533 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2530 11:35:45.148763 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2531 11:35:45.151867 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2532 11:35:45.151949
2533 11:35:45.155401 CA PerBit enable=1, Macro0, CA PI delay=34
2534 11:35:45.155474
2535 11:35:45.159299 [CBTSetCACLKResult] CA Dly = 34
2536 11:35:45.159388 CS Dly: 7 (0~38)
2537 11:35:45.159507 ==
2538 11:35:45.162024 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 11:35:45.168522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 11:35:45.168602 ==
2541 11:35:45.172274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 11:35:45.178899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 11:35:45.187667 [CA 0] Center 39 (9~70) winsize 62
2544 11:35:45.191000 [CA 1] Center 39 (9~70) winsize 62
2545 11:35:45.194317 [CA 2] Center 36 (6~67) winsize 62
2546 11:35:45.197573 [CA 3] Center 35 (5~66) winsize 62
2547 11:35:45.201293 [CA 4] Center 34 (4~65) winsize 62
2548 11:35:45.204247 [CA 5] Center 34 (4~64) winsize 61
2549 11:35:45.204343
2550 11:35:45.207385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 11:35:45.207476
2552 11:35:45.211094 [CATrainingPosCal] consider 2 rank data
2553 11:35:45.214610 u2DelayCellTimex100 = 270/100 ps
2554 11:35:45.217658 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2555 11:35:45.220981 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2556 11:35:45.227798 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2557 11:35:45.231205 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2558 11:35:45.234653 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2559 11:35:45.237754 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2560 11:35:45.237827
2561 11:35:45.241004 CA PerBit enable=1, Macro0, CA PI delay=34
2562 11:35:45.241101
2563 11:35:45.244357 [CBTSetCACLKResult] CA Dly = 34
2564 11:35:45.244431 CS Dly: 8 (0~41)
2565 11:35:45.244488
2566 11:35:45.247916 ----->DramcWriteLeveling(PI) begin...
2567 11:35:45.248015 ==
2568 11:35:45.251641 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 11:35:45.257797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 11:35:45.257871 ==
2571 11:35:45.261832 Write leveling (Byte 0): 30 => 30
2572 11:35:45.264553 Write leveling (Byte 1): 29 => 29
2573 11:35:45.264627 DramcWriteLeveling(PI) end<-----
2574 11:35:45.264684
2575 11:35:45.268027 ==
2576 11:35:45.271581 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 11:35:45.274516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 11:35:45.274590 ==
2579 11:35:45.277958 [Gating] SW mode calibration
2580 11:35:45.284785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 11:35:45.288290 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 11:35:45.294979 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 11:35:45.298169 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2584 11:35:45.301565 0 15 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2585 11:35:45.308009 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 11:35:45.311454 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:35:45.314546 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:35:45.321268 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:35:45.324848 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:35:45.328354 1 0 0 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
2591 11:35:45.331692 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2592 11:35:45.338442 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 11:35:45.341492 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:35:45.344888 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:35:45.351852 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:35:45.354812 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:35:45.358096 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:35:45.364899 1 1 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2599 11:35:45.368664 1 1 4 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
2600 11:35:45.371768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 11:35:45.378223 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 11:35:45.381783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:35:45.385129 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:35:45.391667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:35:45.395159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:35:45.398399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2607 11:35:45.402268 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 11:35:45.408222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 11:35:45.411742 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:35:45.414896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:35:45.421628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:35:45.424991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:35:45.428759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:35:45.435122 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:35:45.439181 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:35:45.441942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:35:45.448709 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:35:45.452091 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:35:45.455549 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:35:45.462198 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:35:45.465337 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:35:45.469151 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2623 11:35:45.472295 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 11:35:45.475450 Total UI for P1: 0, mck2ui 16
2625 11:35:45.478908 best dqsien dly found for B0: ( 1, 4, 0)
2626 11:35:45.485396 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:35:45.485470 Total UI for P1: 0, mck2ui 16
2628 11:35:45.492671 best dqsien dly found for B1: ( 1, 4, 2)
2629 11:35:45.495428 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2630 11:35:45.498721 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 11:35:45.498795
2632 11:35:45.502267 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 11:35:45.505735 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 11:35:45.508999 [Gating] SW calibration Done
2635 11:35:45.509088 ==
2636 11:35:45.512369 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:35:45.515807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:35:45.515881 ==
2639 11:35:45.519229 RX Vref Scan: 0
2640 11:35:45.519303
2641 11:35:45.519360 RX Vref 0 -> 0, step: 1
2642 11:35:45.519415
2643 11:35:45.522697 RX Delay -40 -> 252, step: 8
2644 11:35:45.525917 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2645 11:35:45.528989 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2646 11:35:45.535679 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 11:35:45.539315 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2648 11:35:45.542524 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2649 11:35:45.545730 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2650 11:35:45.549379 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2651 11:35:45.555957 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2652 11:35:45.559182 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 11:35:45.562475 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 11:35:45.566373 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2655 11:35:45.569460 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2656 11:35:45.572839 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 11:35:45.579331 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2658 11:35:45.582743 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 11:35:45.585783 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2660 11:35:45.585858 ==
2661 11:35:45.589204 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:35:45.592976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:35:45.595985 ==
2664 11:35:45.596058 DQS Delay:
2665 11:35:45.596116 DQS0 = 0, DQS1 = 0
2666 11:35:45.599536 DQM Delay:
2667 11:35:45.599610 DQM0 = 115, DQM1 = 107
2668 11:35:45.602642 DQ Delay:
2669 11:35:45.606057 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2670 11:35:45.609452 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2671 11:35:45.613315 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2672 11:35:45.616673 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2673 11:35:45.616747
2674 11:35:45.616805
2675 11:35:45.616858 ==
2676 11:35:45.619790 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:35:45.623084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:35:45.623159 ==
2679 11:35:45.623217
2680 11:35:45.623270
2681 11:35:45.626501 TX Vref Scan disable
2682 11:35:45.629370 == TX Byte 0 ==
2683 11:35:45.632806 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2684 11:35:45.636165 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2685 11:35:45.636239 == TX Byte 1 ==
2686 11:35:45.643175 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2687 11:35:45.646471 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2688 11:35:45.646544 ==
2689 11:35:45.649741 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 11:35:45.652932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 11:35:45.653007 ==
2692 11:35:45.665934 TX Vref=22, minBit 1, minWin=24, winSum=417
2693 11:35:45.669263 TX Vref=24, minBit 5, minWin=25, winSum=425
2694 11:35:45.672761 TX Vref=26, minBit 1, minWin=25, winSum=428
2695 11:35:45.676183 TX Vref=28, minBit 1, minWin=26, winSum=433
2696 11:35:45.679661 TX Vref=30, minBit 1, minWin=26, winSum=435
2697 11:35:45.683301 TX Vref=32, minBit 0, minWin=26, winSum=435
2698 11:35:45.689854 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
2699 11:35:45.689928
2700 11:35:45.693082 Final TX Range 1 Vref 30
2701 11:35:45.693205
2702 11:35:45.693264 ==
2703 11:35:45.696422 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 11:35:45.699640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 11:35:45.699714 ==
2706 11:35:45.699771
2707 11:35:45.699824
2708 11:35:45.703332 TX Vref Scan disable
2709 11:35:45.706593 == TX Byte 0 ==
2710 11:35:45.709473 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2711 11:35:45.713038 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2712 11:35:45.716480 == TX Byte 1 ==
2713 11:35:45.720026 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2714 11:35:45.722873 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2715 11:35:45.722947
2716 11:35:45.726873 [DATLAT]
2717 11:35:45.726947 Freq=1200, CH0 RK0
2718 11:35:45.727005
2719 11:35:45.729702 DATLAT Default: 0xd
2720 11:35:45.729775 0, 0xFFFF, sum = 0
2721 11:35:45.733426 1, 0xFFFF, sum = 0
2722 11:35:45.733501 2, 0xFFFF, sum = 0
2723 11:35:45.736404 3, 0xFFFF, sum = 0
2724 11:35:45.736478 4, 0xFFFF, sum = 0
2725 11:35:45.740164 5, 0xFFFF, sum = 0
2726 11:35:45.740239 6, 0xFFFF, sum = 0
2727 11:35:45.743443 7, 0xFFFF, sum = 0
2728 11:35:45.743518 8, 0xFFFF, sum = 0
2729 11:35:45.746916 9, 0xFFFF, sum = 0
2730 11:35:45.746991 10, 0xFFFF, sum = 0
2731 11:35:45.749915 11, 0xFFFF, sum = 0
2732 11:35:45.749990 12, 0x0, sum = 1
2733 11:35:45.753418 13, 0x0, sum = 2
2734 11:35:45.753493 14, 0x0, sum = 3
2735 11:35:45.757106 15, 0x0, sum = 4
2736 11:35:45.757189 best_step = 13
2737 11:35:45.757246
2738 11:35:45.757298 ==
2739 11:35:45.760386 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 11:35:45.763252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 11:35:45.766639 ==
2742 11:35:45.766712 RX Vref Scan: 1
2743 11:35:45.766769
2744 11:35:45.770002 Set Vref Range= 32 -> 127
2745 11:35:45.770076
2746 11:35:45.773683 RX Vref 32 -> 127, step: 1
2747 11:35:45.773757
2748 11:35:45.773813 RX Delay -21 -> 252, step: 4
2749 11:35:45.773866
2750 11:35:45.776871 Set Vref, RX VrefLevel [Byte0]: 32
2751 11:35:45.780012 [Byte1]: 32
2752 11:35:45.784815
2753 11:35:45.784888 Set Vref, RX VrefLevel [Byte0]: 33
2754 11:35:45.787655 [Byte1]: 33
2755 11:35:45.792291
2756 11:35:45.792364 Set Vref, RX VrefLevel [Byte0]: 34
2757 11:35:45.795662 [Byte1]: 34
2758 11:35:45.800566
2759 11:35:45.800639 Set Vref, RX VrefLevel [Byte0]: 35
2760 11:35:45.803497 [Byte1]: 35
2761 11:35:45.808396
2762 11:35:45.808469 Set Vref, RX VrefLevel [Byte0]: 36
2763 11:35:45.811710 [Byte1]: 36
2764 11:35:45.816260
2765 11:35:45.816334 Set Vref, RX VrefLevel [Byte0]: 37
2766 11:35:45.819288 [Byte1]: 37
2767 11:35:45.823855
2768 11:35:45.823928 Set Vref, RX VrefLevel [Byte0]: 38
2769 11:35:45.827046 [Byte1]: 38
2770 11:35:45.831645
2771 11:35:45.831718 Set Vref, RX VrefLevel [Byte0]: 39
2772 11:35:45.835307 [Byte1]: 39
2773 11:35:45.840079
2774 11:35:45.840153 Set Vref, RX VrefLevel [Byte0]: 40
2775 11:35:45.842970 [Byte1]: 40
2776 11:35:45.847616
2777 11:35:45.847689 Set Vref, RX VrefLevel [Byte0]: 41
2778 11:35:45.851102 [Byte1]: 41
2779 11:35:45.855416
2780 11:35:45.855489 Set Vref, RX VrefLevel [Byte0]: 42
2781 11:35:45.858616 [Byte1]: 42
2782 11:35:45.863531
2783 11:35:45.863613 Set Vref, RX VrefLevel [Byte0]: 43
2784 11:35:45.866783 [Byte1]: 43
2785 11:35:45.871537
2786 11:35:45.871610 Set Vref, RX VrefLevel [Byte0]: 44
2787 11:35:45.874938 [Byte1]: 44
2788 11:35:45.879383
2789 11:35:45.879456 Set Vref, RX VrefLevel [Byte0]: 45
2790 11:35:45.882605 [Byte1]: 45
2791 11:35:45.887438
2792 11:35:45.887511 Set Vref, RX VrefLevel [Byte0]: 46
2793 11:35:45.890528 [Byte1]: 46
2794 11:35:45.895168
2795 11:35:45.895245 Set Vref, RX VrefLevel [Byte0]: 47
2796 11:35:45.898909 [Byte1]: 47
2797 11:35:45.903030
2798 11:35:45.903103 Set Vref, RX VrefLevel [Byte0]: 48
2799 11:35:45.906487 [Byte1]: 48
2800 11:35:45.911231
2801 11:35:45.911304 Set Vref, RX VrefLevel [Byte0]: 49
2802 11:35:45.914686 [Byte1]: 49
2803 11:35:45.919003
2804 11:35:45.919077 Set Vref, RX VrefLevel [Byte0]: 50
2805 11:35:45.922590 [Byte1]: 50
2806 11:35:45.926785
2807 11:35:45.926858 Set Vref, RX VrefLevel [Byte0]: 51
2808 11:35:45.930274 [Byte1]: 51
2809 11:35:45.934788
2810 11:35:45.934861 Set Vref, RX VrefLevel [Byte0]: 52
2811 11:35:45.938719 [Byte1]: 52
2812 11:35:45.942983
2813 11:35:45.943084 Set Vref, RX VrefLevel [Byte0]: 53
2814 11:35:45.946286 [Byte1]: 53
2815 11:35:45.951214
2816 11:35:45.951287 Set Vref, RX VrefLevel [Byte0]: 54
2817 11:35:45.953973 [Byte1]: 54
2818 11:35:45.958495
2819 11:35:45.958568 Set Vref, RX VrefLevel [Byte0]: 55
2820 11:35:45.961991 [Byte1]: 55
2821 11:35:45.966561
2822 11:35:45.966634 Set Vref, RX VrefLevel [Byte0]: 56
2823 11:35:45.969983 [Byte1]: 56
2824 11:35:45.974820
2825 11:35:45.974893 Set Vref, RX VrefLevel [Byte0]: 57
2826 11:35:45.977899 [Byte1]: 57
2827 11:35:45.982632
2828 11:35:45.982705 Set Vref, RX VrefLevel [Byte0]: 58
2829 11:35:45.986189 [Byte1]: 58
2830 11:35:45.990233
2831 11:35:45.990306 Set Vref, RX VrefLevel [Byte0]: 59
2832 11:35:45.994136 [Byte1]: 59
2833 11:35:45.998107
2834 11:35:45.998180 Set Vref, RX VrefLevel [Byte0]: 60
2835 11:35:46.001339 [Byte1]: 60
2836 11:35:46.006158
2837 11:35:46.006231 Set Vref, RX VrefLevel [Byte0]: 61
2838 11:35:46.009286 [Byte1]: 61
2839 11:35:46.014133
2840 11:35:46.014206 Set Vref, RX VrefLevel [Byte0]: 62
2841 11:35:46.017396 [Byte1]: 62
2842 11:35:46.022105
2843 11:35:46.022178 Set Vref, RX VrefLevel [Byte0]: 63
2844 11:35:46.025310 [Byte1]: 63
2845 11:35:46.030224
2846 11:35:46.030297 Set Vref, RX VrefLevel [Byte0]: 64
2847 11:35:46.033637 [Byte1]: 64
2848 11:35:46.038004
2849 11:35:46.038078 Set Vref, RX VrefLevel [Byte0]: 65
2850 11:35:46.041287 [Byte1]: 65
2851 11:35:46.045891
2852 11:35:46.045963 Set Vref, RX VrefLevel [Byte0]: 66
2853 11:35:46.049041 [Byte1]: 66
2854 11:35:46.053671
2855 11:35:46.053744 Set Vref, RX VrefLevel [Byte0]: 67
2856 11:35:46.057699 [Byte1]: 67
2857 11:35:46.061835
2858 11:35:46.061908 Set Vref, RX VrefLevel [Byte0]: 68
2859 11:35:46.065063 [Byte1]: 68
2860 11:35:46.069761
2861 11:35:46.069838 Set Vref, RX VrefLevel [Byte0]: 69
2862 11:35:46.072644 [Byte1]: 69
2863 11:35:46.077594
2864 11:35:46.077668 Final RX Vref Byte 0 = 54 to rank0
2865 11:35:46.081055 Final RX Vref Byte 1 = 51 to rank0
2866 11:35:46.084187 Final RX Vref Byte 0 = 54 to rank1
2867 11:35:46.087672 Final RX Vref Byte 1 = 51 to rank1==
2868 11:35:46.090779 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 11:35:46.094396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 11:35:46.097673 ==
2871 11:35:46.097746 DQS Delay:
2872 11:35:46.097803 DQS0 = 0, DQS1 = 0
2873 11:35:46.101063 DQM Delay:
2874 11:35:46.101158 DQM0 = 114, DQM1 = 104
2875 11:35:46.104413 DQ Delay:
2876 11:35:46.107615 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2877 11:35:46.111629 DQ4 =114, DQ5 =110, DQ6 =120, DQ7 =122
2878 11:35:46.114646 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2879 11:35:46.118240 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2880 11:35:46.118313
2881 11:35:46.118370
2882 11:35:46.125037 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2883 11:35:46.127596 CH0 RK0: MR19=303, MR18=FCEC
2884 11:35:46.134477 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2885 11:35:46.134551
2886 11:35:46.137698 ----->DramcWriteLeveling(PI) begin...
2887 11:35:46.137772 ==
2888 11:35:46.141587 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:35:46.144662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:35:46.144736 ==
2891 11:35:46.148343 Write leveling (Byte 0): 32 => 32
2892 11:35:46.151607 Write leveling (Byte 1): 29 => 29
2893 11:35:46.154671 DramcWriteLeveling(PI) end<-----
2894 11:35:46.154744
2895 11:35:46.154801 ==
2896 11:35:46.157951 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 11:35:46.161572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 11:35:46.161646 ==
2899 11:35:46.164896 [Gating] SW mode calibration
2900 11:35:46.171441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 11:35:46.178147 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 11:35:46.181741 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2903 11:35:46.185026 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2904 11:35:46.191740 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:35:46.195071 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:35:46.198300 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:35:46.205111 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:35:46.208876 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2909 11:35:46.212007 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2910 11:35:46.218560 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
2911 11:35:46.222316 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2912 11:35:46.225081 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:35:46.232229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:35:46.235363 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:35:46.238498 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:35:46.242004 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2917 11:35:46.248876 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2918 11:35:46.253059 1 1 0 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
2919 11:35:46.255575 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2920 11:35:46.262155 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:35:46.265882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:35:46.268805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:35:46.275749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:35:46.279091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2925 11:35:46.282457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 11:35:46.289051 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2927 11:35:46.292113 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:35:46.295540 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:35:46.302219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:35:46.305549 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:35:46.309136 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:35:46.312640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:35:46.319281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:35:46.322880 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:35:46.325779 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:35:46.332303 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:35:46.335689 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:35:46.339042 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:35:46.345830 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:35:46.349251 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:35:46.352801 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 11:35:46.359363 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2943 11:35:46.359433 Total UI for P1: 0, mck2ui 16
2944 11:35:46.362581 best dqsien dly found for B0: ( 1, 3, 28)
2945 11:35:46.369494 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:35:46.372416 Total UI for P1: 0, mck2ui 16
2947 11:35:46.375847 best dqsien dly found for B1: ( 1, 4, 0)
2948 11:35:46.379341 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2949 11:35:46.382970 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2950 11:35:46.383047
2951 11:35:46.386116 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 11:35:46.389708 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2953 11:35:46.392565 [Gating] SW calibration Done
2954 11:35:46.392642 ==
2955 11:35:46.396161 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:35:46.399270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:35:46.399347 ==
2958 11:35:46.402898 RX Vref Scan: 0
2959 11:35:46.402974
2960 11:35:46.403051 RX Vref 0 -> 0, step: 1
2961 11:35:46.403123
2962 11:35:46.406157 RX Delay -40 -> 252, step: 8
2963 11:35:46.409545 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2964 11:35:46.416418 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2965 11:35:46.420264 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2966 11:35:46.422856 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2967 11:35:46.426437 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2968 11:35:46.429664 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2969 11:35:46.436350 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2970 11:35:46.439352 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2971 11:35:46.442661 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2972 11:35:46.446514 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2973 11:35:46.449338 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2974 11:35:46.455898 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2975 11:35:46.459433 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2976 11:35:46.463012 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2977 11:35:46.465918 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 11:35:46.469710 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2979 11:35:46.472574 ==
2980 11:35:46.475796 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 11:35:46.479336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 11:35:46.479413 ==
2983 11:35:46.479490 DQS Delay:
2984 11:35:46.482856 DQS0 = 0, DQS1 = 0
2985 11:35:46.482930 DQM Delay:
2986 11:35:46.485817 DQM0 = 115, DQM1 = 106
2987 11:35:46.485891 DQ Delay:
2988 11:35:46.489999 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2989 11:35:46.492674 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2990 11:35:46.495942 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2991 11:35:46.499489 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2992 11:35:46.499562
2993 11:35:46.499619
2994 11:35:46.499672 ==
2995 11:35:46.502510 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 11:35:46.509273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 11:35:46.509347 ==
2998 11:35:46.509404
2999 11:35:46.509457
3000 11:35:46.509506 TX Vref Scan disable
3001 11:35:46.512755 == TX Byte 0 ==
3002 11:35:46.515775 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 11:35:46.519341 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 11:35:46.523002 == TX Byte 1 ==
3005 11:35:46.525861 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3006 11:35:46.529265 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3007 11:35:46.532564 ==
3008 11:35:46.535765 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:35:46.539298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:35:46.539386 ==
3011 11:35:46.550464 TX Vref=22, minBit 4, minWin=25, winSum=425
3012 11:35:46.554326 TX Vref=24, minBit 5, minWin=25, winSum=425
3013 11:35:46.557423 TX Vref=26, minBit 3, minWin=26, winSum=433
3014 11:35:46.560872 TX Vref=28, minBit 3, minWin=26, winSum=434
3015 11:35:46.563948 TX Vref=30, minBit 12, minWin=26, winSum=436
3016 11:35:46.570552 TX Vref=32, minBit 12, minWin=26, winSum=437
3017 11:35:46.573968 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 32
3018 11:35:46.574042
3019 11:35:46.577230 Final TX Range 1 Vref 32
3020 11:35:46.577321
3021 11:35:46.577401 ==
3022 11:35:46.580454 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:35:46.583958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:35:46.584035 ==
3025 11:35:46.587351
3026 11:35:46.587427
3027 11:35:46.587504 TX Vref Scan disable
3028 11:35:46.590635 == TX Byte 0 ==
3029 11:35:46.593754 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3030 11:35:46.597512 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3031 11:35:46.600767 == TX Byte 1 ==
3032 11:35:46.603751 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3033 11:35:46.607093 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3034 11:35:46.610934
3035 11:35:46.611009 [DATLAT]
3036 11:35:46.611085 Freq=1200, CH0 RK1
3037 11:35:46.611156
3038 11:35:46.614232 DATLAT Default: 0xd
3039 11:35:46.614309 0, 0xFFFF, sum = 0
3040 11:35:46.617374 1, 0xFFFF, sum = 0
3041 11:35:46.617451 2, 0xFFFF, sum = 0
3042 11:35:46.620931 3, 0xFFFF, sum = 0
3043 11:35:46.621008 4, 0xFFFF, sum = 0
3044 11:35:46.623921 5, 0xFFFF, sum = 0
3045 11:35:46.627332 6, 0xFFFF, sum = 0
3046 11:35:46.627410 7, 0xFFFF, sum = 0
3047 11:35:46.630747 8, 0xFFFF, sum = 0
3048 11:35:46.630825 9, 0xFFFF, sum = 0
3049 11:35:46.633897 10, 0xFFFF, sum = 0
3050 11:35:46.633974 11, 0xFFFF, sum = 0
3051 11:35:46.637682 12, 0x0, sum = 1
3052 11:35:46.637759 13, 0x0, sum = 2
3053 11:35:46.641047 14, 0x0, sum = 3
3054 11:35:46.641156 15, 0x0, sum = 4
3055 11:35:46.641249 best_step = 13
3056 11:35:46.641320
3057 11:35:46.643890 ==
3058 11:35:46.647540 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 11:35:46.651094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 11:35:46.651168 ==
3061 11:35:46.651225 RX Vref Scan: 0
3062 11:35:46.651278
3063 11:35:46.654214 RX Vref 0 -> 0, step: 1
3064 11:35:46.654288
3065 11:35:46.657385 RX Delay -21 -> 252, step: 4
3066 11:35:46.660684 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3067 11:35:46.667381 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3068 11:35:46.670922 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3069 11:35:46.674180 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3070 11:35:46.677401 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3071 11:35:46.680743 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3072 11:35:46.684168 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3073 11:35:46.690843 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3074 11:35:46.694184 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3075 11:35:46.697654 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3076 11:35:46.700997 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3077 11:35:46.704384 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3078 11:35:46.710894 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3079 11:35:46.713923 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3080 11:35:46.717705 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3081 11:35:46.720697 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3082 11:35:46.720764 ==
3083 11:35:46.724364 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 11:35:46.730798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 11:35:46.730869 ==
3086 11:35:46.730931 DQS Delay:
3087 11:35:46.730985 DQS0 = 0, DQS1 = 0
3088 11:35:46.734375 DQM Delay:
3089 11:35:46.734437 DQM0 = 114, DQM1 = 104
3090 11:35:46.737338 DQ Delay:
3091 11:35:46.741223 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3092 11:35:46.744124 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3093 11:35:46.747353 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3094 11:35:46.750733 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3095 11:35:46.750800
3096 11:35:46.750857
3097 11:35:46.757653 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3098 11:35:46.760929 CH0 RK1: MR19=403, MR18=5F6
3099 11:35:46.767312 CH0_RK1: MR19=0x403, MR18=0x5F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3100 11:35:46.770549 [RxdqsGatingPostProcess] freq 1200
3101 11:35:46.777308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 11:35:46.777381 best DQS0 dly(2T, 0.5T) = (0, 12)
3103 11:35:46.781078 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 11:35:46.784537 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3105 11:35:46.787411 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 11:35:46.790681 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 11:35:46.794616 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 11:35:46.797358 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 11:35:46.800840 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 11:35:46.803826 Pre-setting of DQS Precalculation
3111 11:35:46.807357 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 11:35:46.810615 ==
3113 11:35:46.810689 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:35:46.817662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:35:46.817736 ==
3116 11:35:46.821056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 11:35:46.827691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 11:35:46.836298 [CA 0] Center 38 (9~68) winsize 60
3119 11:35:46.839835 [CA 1] Center 38 (8~68) winsize 61
3120 11:35:46.843238 [CA 2] Center 35 (5~65) winsize 61
3121 11:35:46.846735 [CA 3] Center 34 (4~65) winsize 62
3122 11:35:46.849967 [CA 4] Center 34 (4~65) winsize 62
3123 11:35:46.853022 [CA 5] Center 34 (4~64) winsize 61
3124 11:35:46.853108
3125 11:35:46.856574 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3126 11:35:46.856637
3127 11:35:46.859892 [CATrainingPosCal] consider 1 rank data
3128 11:35:46.863440 u2DelayCellTimex100 = 270/100 ps
3129 11:35:46.866408 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3130 11:35:46.869674 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3131 11:35:46.876400 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3132 11:35:46.879957 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3133 11:35:46.883320 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3134 11:35:46.886470 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3135 11:35:46.886544
3136 11:35:46.889951 CA PerBit enable=1, Macro0, CA PI delay=34
3137 11:35:46.890025
3138 11:35:46.892985 [CBTSetCACLKResult] CA Dly = 34
3139 11:35:46.893058 CS Dly: 6 (0~37)
3140 11:35:46.893121 ==
3141 11:35:46.896531 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 11:35:46.903171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 11:35:46.903244 ==
3144 11:35:46.906398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 11:35:46.913093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 11:35:46.921930 [CA 0] Center 38 (8~68) winsize 61
3147 11:35:46.925021 [CA 1] Center 38 (8~68) winsize 61
3148 11:35:46.929200 [CA 2] Center 35 (5~65) winsize 61
3149 11:35:46.932166 [CA 3] Center 34 (3~65) winsize 63
3150 11:35:46.935216 [CA 4] Center 34 (4~65) winsize 62
3151 11:35:46.938956 [CA 5] Center 33 (3~63) winsize 61
3152 11:35:46.939033
3153 11:35:46.942231 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3154 11:35:46.942318
3155 11:35:46.945557 [CATrainingPosCal] consider 2 rank data
3156 11:35:46.948599 u2DelayCellTimex100 = 270/100 ps
3157 11:35:46.952221 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3158 11:35:46.955782 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 11:35:46.961627 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3160 11:35:46.965349 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3161 11:35:46.968854 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3162 11:35:46.972311 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3163 11:35:46.972398
3164 11:35:46.975665 CA PerBit enable=1, Macro0, CA PI delay=33
3165 11:35:46.975750
3166 11:35:46.978774 [CBTSetCACLKResult] CA Dly = 33
3167 11:35:46.978850 CS Dly: 7 (0~40)
3168 11:35:46.978903
3169 11:35:46.981979 ----->DramcWriteLeveling(PI) begin...
3170 11:35:46.982067 ==
3171 11:35:46.985818 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:35:46.992334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:35:46.992425 ==
3174 11:35:46.995581 Write leveling (Byte 0): 25 => 25
3175 11:35:46.998956 Write leveling (Byte 1): 30 => 30
3176 11:35:46.999019 DramcWriteLeveling(PI) end<-----
3177 11:35:47.001829
3178 11:35:47.001893 ==
3179 11:35:47.005403 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 11:35:47.008664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 11:35:47.008729 ==
3182 11:35:47.011878 [Gating] SW mode calibration
3183 11:35:47.018637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 11:35:47.022282 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 11:35:47.028622 0 15 0 | B1->B0 | 2b2b 2626 | 1 0 | (0 0) (0 0)
3186 11:35:47.032017 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:35:47.035410 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:35:47.042398 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:35:47.045466 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:35:47.049248 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:35:47.055093 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:35:47.058933 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3193 11:35:47.062179 1 0 0 | B1->B0 | 2424 2929 | 0 0 | (1 0) (1 0)
3194 11:35:47.068541 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:35:47.071810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:35:47.075920 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:35:47.082492 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:35:47.084997 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:35:47.088450 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:35:47.095723 1 0 28 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
3201 11:35:47.098583 1 1 0 | B1->B0 | 4545 3838 | 0 0 | (0 0) (1 1)
3202 11:35:47.102117 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:35:47.105521 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:35:47.111808 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:35:47.115353 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:35:47.118766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:35:47.125297 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:35:47.128880 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 11:35:47.131876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 11:35:47.138680 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:35:47.141747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:35:47.145106 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:35:47.151999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:35:47.155356 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:35:47.158700 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:35:47.165542 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:35:47.168762 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:35:47.171938 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:35:47.178660 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:35:47.181844 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:35:47.185466 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:35:47.192099 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:35:47.195109 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:35:47.198772 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3225 11:35:47.201778 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:35:47.205464 Total UI for P1: 0, mck2ui 16
3227 11:35:47.208922 best dqsien dly found for B0: ( 1, 3, 28)
3228 11:35:47.212232 Total UI for P1: 0, mck2ui 16
3229 11:35:47.215956 best dqsien dly found for B1: ( 1, 3, 30)
3230 11:35:47.218504 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3231 11:35:47.221833 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3232 11:35:47.225112
3233 11:35:47.228512 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3234 11:35:47.232260 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3235 11:35:47.235172 [Gating] SW calibration Done
3236 11:35:47.235268 ==
3237 11:35:47.238492 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 11:35:47.242211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 11:35:47.242275 ==
3240 11:35:47.242328 RX Vref Scan: 0
3241 11:35:47.242388
3242 11:35:47.245427 RX Vref 0 -> 0, step: 1
3243 11:35:47.245489
3244 11:35:47.248504 RX Delay -40 -> 252, step: 8
3245 11:35:47.252193 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3246 11:35:47.255371 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3247 11:35:47.262333 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3248 11:35:47.265760 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3249 11:35:47.268924 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3250 11:35:47.271970 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3251 11:35:47.275460 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3252 11:35:47.279228 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3253 11:35:47.285920 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3254 11:35:47.288716 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3255 11:35:47.292088 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3256 11:35:47.295898 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3257 11:35:47.298864 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3258 11:35:47.305789 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3259 11:35:47.308767 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3260 11:35:47.312045 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3261 11:35:47.312114 ==
3262 11:35:47.315377 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 11:35:47.318718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 11:35:47.318782 ==
3265 11:35:47.322080 DQS Delay:
3266 11:35:47.322144 DQS0 = 0, DQS1 = 0
3267 11:35:47.325459 DQM Delay:
3268 11:35:47.325525 DQM0 = 116, DQM1 = 109
3269 11:35:47.325585 DQ Delay:
3270 11:35:47.332436 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3271 11:35:47.335728 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3272 11:35:47.339050 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3273 11:35:47.342234 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3274 11:35:47.342301
3275 11:35:47.342356
3276 11:35:47.342409 ==
3277 11:35:47.345682 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 11:35:47.349213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 11:35:47.349277 ==
3280 11:35:47.349329
3281 11:35:47.349383
3282 11:35:47.352196 TX Vref Scan disable
3283 11:35:47.355881 == TX Byte 0 ==
3284 11:35:47.359107 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3285 11:35:47.362939 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3286 11:35:47.365554 == TX Byte 1 ==
3287 11:35:47.369109 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3288 11:35:47.372372 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3289 11:35:47.372447 ==
3290 11:35:47.375997 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 11:35:47.378919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 11:35:47.378989 ==
3293 11:35:47.392144 TX Vref=22, minBit 1, minWin=24, winSum=408
3294 11:35:47.395547 TX Vref=24, minBit 0, minWin=26, winSum=418
3295 11:35:47.398872 TX Vref=26, minBit 1, minWin=25, winSum=420
3296 11:35:47.402245 TX Vref=28, minBit 0, minWin=26, winSum=423
3297 11:35:47.406055 TX Vref=30, minBit 15, minWin=25, winSum=425
3298 11:35:47.412821 TX Vref=32, minBit 15, minWin=25, winSum=427
3299 11:35:47.415767 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
3300 11:35:47.415836
3301 11:35:47.419022 Final TX Range 1 Vref 28
3302 11:35:47.419087
3303 11:35:47.419141 ==
3304 11:35:47.422344 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:35:47.425752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:35:47.425820 ==
3307 11:35:47.425876
3308 11:35:47.429056
3309 11:35:47.429132 TX Vref Scan disable
3310 11:35:47.432795 == TX Byte 0 ==
3311 11:35:47.435794 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3312 11:35:47.438895 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3313 11:35:47.442163 == TX Byte 1 ==
3314 11:35:47.445720 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3315 11:35:47.448874 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3316 11:35:47.452104
3317 11:35:47.452194 [DATLAT]
3318 11:35:47.452250 Freq=1200, CH1 RK0
3319 11:35:47.452302
3320 11:35:47.455530 DATLAT Default: 0xd
3321 11:35:47.455600 0, 0xFFFF, sum = 0
3322 11:35:47.458990 1, 0xFFFF, sum = 0
3323 11:35:47.459053 2, 0xFFFF, sum = 0
3324 11:35:47.462430 3, 0xFFFF, sum = 0
3325 11:35:47.462493 4, 0xFFFF, sum = 0
3326 11:35:47.465924 5, 0xFFFF, sum = 0
3327 11:35:47.465986 6, 0xFFFF, sum = 0
3328 11:35:47.469648 7, 0xFFFF, sum = 0
3329 11:35:47.472434 8, 0xFFFF, sum = 0
3330 11:35:47.472535 9, 0xFFFF, sum = 0
3331 11:35:47.475710 10, 0xFFFF, sum = 0
3332 11:35:47.475773 11, 0xFFFF, sum = 0
3333 11:35:47.479193 12, 0x0, sum = 1
3334 11:35:47.479257 13, 0x0, sum = 2
3335 11:35:47.482269 14, 0x0, sum = 3
3336 11:35:47.482358 15, 0x0, sum = 4
3337 11:35:47.482447 best_step = 13
3338 11:35:47.482525
3339 11:35:47.485505 ==
3340 11:35:47.485574 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 11:35:47.492339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 11:35:47.492411 ==
3343 11:35:47.492477 RX Vref Scan: 1
3344 11:35:47.492556
3345 11:35:47.495721 Set Vref Range= 32 -> 127
3346 11:35:47.495805
3347 11:35:47.499091 RX Vref 32 -> 127, step: 1
3348 11:35:47.499176
3349 11:35:47.502314 RX Delay -21 -> 252, step: 4
3350 11:35:47.502377
3351 11:35:47.505751 Set Vref, RX VrefLevel [Byte0]: 32
3352 11:35:47.508904 [Byte1]: 32
3353 11:35:47.508969
3354 11:35:47.512379 Set Vref, RX VrefLevel [Byte0]: 33
3355 11:35:47.515761 [Byte1]: 33
3356 11:35:47.515833
3357 11:35:47.519467 Set Vref, RX VrefLevel [Byte0]: 34
3358 11:35:47.522147 [Byte1]: 34
3359 11:35:47.526742
3360 11:35:47.526815 Set Vref, RX VrefLevel [Byte0]: 35
3361 11:35:47.530032 [Byte1]: 35
3362 11:35:47.534396
3363 11:35:47.534463 Set Vref, RX VrefLevel [Byte0]: 36
3364 11:35:47.537680 [Byte1]: 36
3365 11:35:47.542532
3366 11:35:47.542595 Set Vref, RX VrefLevel [Byte0]: 37
3367 11:35:47.545644 [Byte1]: 37
3368 11:35:47.550425
3369 11:35:47.550498 Set Vref, RX VrefLevel [Byte0]: 38
3370 11:35:47.553737 [Byte1]: 38
3371 11:35:47.558060
3372 11:35:47.558132 Set Vref, RX VrefLevel [Byte0]: 39
3373 11:35:47.561385 [Byte1]: 39
3374 11:35:47.566193
3375 11:35:47.566275 Set Vref, RX VrefLevel [Byte0]: 40
3376 11:35:47.569272 [Byte1]: 40
3377 11:35:47.574681
3378 11:35:47.574768 Set Vref, RX VrefLevel [Byte0]: 41
3379 11:35:47.577562 [Byte1]: 41
3380 11:35:47.581744
3381 11:35:47.581831 Set Vref, RX VrefLevel [Byte0]: 42
3382 11:35:47.585350 [Byte1]: 42
3383 11:35:47.589761
3384 11:35:47.589838 Set Vref, RX VrefLevel [Byte0]: 43
3385 11:35:47.593055 [Byte1]: 43
3386 11:35:47.598073
3387 11:35:47.598138 Set Vref, RX VrefLevel [Byte0]: 44
3388 11:35:47.601344 [Byte1]: 44
3389 11:35:47.605760
3390 11:35:47.605849 Set Vref, RX VrefLevel [Byte0]: 45
3391 11:35:47.608878 [Byte1]: 45
3392 11:35:47.613807
3393 11:35:47.613892 Set Vref, RX VrefLevel [Byte0]: 46
3394 11:35:47.617024 [Byte1]: 46
3395 11:35:47.622137
3396 11:35:47.622210 Set Vref, RX VrefLevel [Byte0]: 47
3397 11:35:47.625125 [Byte1]: 47
3398 11:35:47.629790
3399 11:35:47.629863 Set Vref, RX VrefLevel [Byte0]: 48
3400 11:35:47.632809 [Byte1]: 48
3401 11:35:47.637758
3402 11:35:47.637831 Set Vref, RX VrefLevel [Byte0]: 49
3403 11:35:47.640563 [Byte1]: 49
3404 11:35:47.645505
3405 11:35:47.645582 Set Vref, RX VrefLevel [Byte0]: 50
3406 11:35:47.648598 [Byte1]: 50
3407 11:35:47.653255
3408 11:35:47.653352 Set Vref, RX VrefLevel [Byte0]: 51
3409 11:35:47.656565 [Byte1]: 51
3410 11:35:47.661056
3411 11:35:47.661153 Set Vref, RX VrefLevel [Byte0]: 52
3412 11:35:47.664852 [Byte1]: 52
3413 11:35:47.669291
3414 11:35:47.669382 Set Vref, RX VrefLevel [Byte0]: 53
3415 11:35:47.672340 [Byte1]: 53
3416 11:35:47.676957
3417 11:35:47.677049 Set Vref, RX VrefLevel [Byte0]: 54
3418 11:35:47.680520 [Byte1]: 54
3419 11:35:47.684805
3420 11:35:47.684867 Set Vref, RX VrefLevel [Byte0]: 55
3421 11:35:47.689003 [Byte1]: 55
3422 11:35:47.693270
3423 11:35:47.693333 Set Vref, RX VrefLevel [Byte0]: 56
3424 11:35:47.695970 [Byte1]: 56
3425 11:35:47.700967
3426 11:35:47.701034 Set Vref, RX VrefLevel [Byte0]: 57
3427 11:35:47.704208 [Byte1]: 57
3428 11:35:47.708790
3429 11:35:47.708859 Set Vref, RX VrefLevel [Byte0]: 58
3430 11:35:47.712107 [Byte1]: 58
3431 11:35:47.716769
3432 11:35:47.716842 Set Vref, RX VrefLevel [Byte0]: 59
3433 11:35:47.720165 [Byte1]: 59
3434 11:35:47.724374
3435 11:35:47.724447 Set Vref, RX VrefLevel [Byte0]: 60
3436 11:35:47.727694 [Byte1]: 60
3437 11:35:47.733225
3438 11:35:47.733298 Set Vref, RX VrefLevel [Byte0]: 61
3439 11:35:47.736200 [Byte1]: 61
3440 11:35:47.740382
3441 11:35:47.740481 Set Vref, RX VrefLevel [Byte0]: 62
3442 11:35:47.743629 [Byte1]: 62
3443 11:35:47.748741
3444 11:35:47.748830 Set Vref, RX VrefLevel [Byte0]: 63
3445 11:35:47.751599 [Byte1]: 63
3446 11:35:47.755979
3447 11:35:47.756041 Set Vref, RX VrefLevel [Byte0]: 64
3448 11:35:47.759546 [Byte1]: 64
3449 11:35:47.764158
3450 11:35:47.764218 Set Vref, RX VrefLevel [Byte0]: 65
3451 11:35:47.767675 [Byte1]: 65
3452 11:35:47.773161
3453 11:35:47.773248 Set Vref, RX VrefLevel [Byte0]: 66
3454 11:35:47.775957 [Byte1]: 66
3455 11:35:47.780103
3456 11:35:47.780169 Set Vref, RX VrefLevel [Byte0]: 67
3457 11:35:47.783147 [Byte1]: 67
3458 11:35:47.788184
3459 11:35:47.788249 Set Vref, RX VrefLevel [Byte0]: 68
3460 11:35:47.791324 [Byte1]: 68
3461 11:35:47.796092
3462 11:35:47.796151 Set Vref, RX VrefLevel [Byte0]: 69
3463 11:35:47.799078 [Byte1]: 69
3464 11:35:47.804318
3465 11:35:47.804378 Set Vref, RX VrefLevel [Byte0]: 70
3466 11:35:47.807014 [Byte1]: 70
3467 11:35:47.811508
3468 11:35:47.811568 Set Vref, RX VrefLevel [Byte0]: 71
3469 11:35:47.815269 [Byte1]: 71
3470 11:35:47.819552
3471 11:35:47.819615 Final RX Vref Byte 0 = 57 to rank0
3472 11:35:47.823249 Final RX Vref Byte 1 = 47 to rank0
3473 11:35:47.826267 Final RX Vref Byte 0 = 57 to rank1
3474 11:35:47.829625 Final RX Vref Byte 1 = 47 to rank1==
3475 11:35:47.833039 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 11:35:47.839869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 11:35:47.839950 ==
3478 11:35:47.840007 DQS Delay:
3479 11:35:47.840060 DQS0 = 0, DQS1 = 0
3480 11:35:47.842813 DQM Delay:
3481 11:35:47.842874 DQM0 = 116, DQM1 = 107
3482 11:35:47.846021 DQ Delay:
3483 11:35:47.849363 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3484 11:35:47.853208 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3485 11:35:47.856137 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =102
3486 11:35:47.859726 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =114
3487 11:35:47.859814
3488 11:35:47.859899
3489 11:35:47.866511 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3490 11:35:47.869337 CH1 RK0: MR19=403, MR18=2E6
3491 11:35:47.876120 CH1_RK0: MR19=0x403, MR18=0x2E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3492 11:35:47.876186
3493 11:35:47.879984 ----->DramcWriteLeveling(PI) begin...
3494 11:35:47.880049 ==
3495 11:35:47.882889 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 11:35:47.885999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 11:35:47.886090 ==
3498 11:35:47.889338 Write leveling (Byte 0): 25 => 25
3499 11:35:47.893288 Write leveling (Byte 1): 27 => 27
3500 11:35:47.896056 DramcWriteLeveling(PI) end<-----
3501 11:35:47.896118
3502 11:35:47.896170 ==
3503 11:35:47.899676 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 11:35:47.902762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 11:35:47.906423 ==
3506 11:35:47.906510 [Gating] SW mode calibration
3507 11:35:47.916109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 11:35:47.919893 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 11:35:47.922684 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3510 11:35:47.929685 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:35:47.933035 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:35:47.936331 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 11:35:47.943115 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 11:35:47.946646 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3515 11:35:47.949778 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
3516 11:35:47.956354 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3517 11:35:47.960151 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:35:47.963307 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:35:47.969738 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:35:47.973099 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 11:35:47.976113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 11:35:47.983056 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 11:35:47.986275 1 0 24 | B1->B0 | 2727 4343 | 0 0 | (0 0) (1 1)
3524 11:35:47.989739 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:35:47.992887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 11:35:47.999520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:35:48.002738 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:35:48.006016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:35:48.012815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 11:35:48.016355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3531 11:35:48.020137 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3532 11:35:48.026210 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3533 11:35:48.029659 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:35:48.032998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:35:48.039712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:35:48.042973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:35:48.046278 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:35:48.052711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:35:48.055917 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:35:48.059798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:35:48.066179 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:35:48.070248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:35:48.073101 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:35:48.079408 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:35:48.082836 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:35:48.086350 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:35:48.089658 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3548 11:35:48.096191 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3549 11:35:48.099326 Total UI for P1: 0, mck2ui 16
3550 11:35:48.102807 best dqsien dly found for B0: ( 1, 3, 24)
3551 11:35:48.106061 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 11:35:48.109813 Total UI for P1: 0, mck2ui 16
3553 11:35:48.112561 best dqsien dly found for B1: ( 1, 3, 28)
3554 11:35:48.116413 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3555 11:35:48.119703 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3556 11:35:48.119776
3557 11:35:48.123057 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3558 11:35:48.125945 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3559 11:35:48.129728 [Gating] SW calibration Done
3560 11:35:48.129802 ==
3561 11:35:48.132895 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 11:35:48.139312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 11:35:48.139382 ==
3564 11:35:48.139438 RX Vref Scan: 0
3565 11:35:48.139505
3566 11:35:48.142691 RX Vref 0 -> 0, step: 1
3567 11:35:48.142754
3568 11:35:48.146072 RX Delay -40 -> 252, step: 8
3569 11:35:48.149375 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3570 11:35:48.152567 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3571 11:35:48.156210 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3572 11:35:48.159264 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3573 11:35:48.166222 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3574 11:35:48.169347 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3575 11:35:48.172736 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3576 11:35:48.176395 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3577 11:35:48.179422 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3578 11:35:48.182962 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3579 11:35:48.189812 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3580 11:35:48.193173 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3581 11:35:48.196191 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3582 11:35:48.199787 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3583 11:35:48.202861 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3584 11:35:48.210073 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3585 11:35:48.210147 ==
3586 11:35:48.213901 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:35:48.216829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:35:48.216908 ==
3589 11:35:48.216966 DQS Delay:
3590 11:35:48.220569 DQS0 = 0, DQS1 = 0
3591 11:35:48.220713 DQM Delay:
3592 11:35:48.223524 DQM0 = 114, DQM1 = 108
3593 11:35:48.223645 DQ Delay:
3594 11:35:48.227015 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3595 11:35:48.230318 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3596 11:35:48.233375 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3597 11:35:48.236903 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3598 11:35:48.237028
3599 11:35:48.237150
3600 11:35:48.237244 ==
3601 11:35:48.240199 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:35:48.246726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:35:48.246804 ==
3604 11:35:48.246862
3605 11:35:48.246915
3606 11:35:48.246965 TX Vref Scan disable
3607 11:35:48.250516 == TX Byte 0 ==
3608 11:35:48.253497 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3609 11:35:48.257106 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3610 11:35:48.260166 == TX Byte 1 ==
3611 11:35:48.263757 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3612 11:35:48.270184 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3613 11:35:48.270259 ==
3614 11:35:48.273518 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:35:48.277050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:35:48.277173 ==
3617 11:35:48.288295 TX Vref=22, minBit 1, minWin=25, winSum=417
3618 11:35:48.291559 TX Vref=24, minBit 0, minWin=25, winSum=420
3619 11:35:48.294806 TX Vref=26, minBit 3, minWin=25, winSum=427
3620 11:35:48.298578 TX Vref=28, minBit 2, minWin=26, winSum=429
3621 11:35:48.301824 TX Vref=30, minBit 9, minWin=26, winSum=434
3622 11:35:48.304958 TX Vref=32, minBit 9, minWin=26, winSum=432
3623 11:35:48.311497 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3624 11:35:48.311572
3625 11:35:48.315222 Final TX Range 1 Vref 30
3626 11:35:48.315309
3627 11:35:48.315368 ==
3628 11:35:48.318176 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 11:35:48.321974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 11:35:48.322071 ==
3631 11:35:48.322154
3632 11:35:48.322234
3633 11:35:48.324992 TX Vref Scan disable
3634 11:35:48.328318 == TX Byte 0 ==
3635 11:35:48.332138 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3636 11:35:48.335053 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3637 11:35:48.338564 == TX Byte 1 ==
3638 11:35:48.341775 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3639 11:35:48.345358 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3640 11:35:48.345431
3641 11:35:48.348450 [DATLAT]
3642 11:35:48.348545 Freq=1200, CH1 RK1
3643 11:35:48.348626
3644 11:35:48.351842 DATLAT Default: 0xd
3645 11:35:48.351904 0, 0xFFFF, sum = 0
3646 11:35:48.355629 1, 0xFFFF, sum = 0
3647 11:35:48.355692 2, 0xFFFF, sum = 0
3648 11:35:48.358802 3, 0xFFFF, sum = 0
3649 11:35:48.358894 4, 0xFFFF, sum = 0
3650 11:35:48.361909 5, 0xFFFF, sum = 0
3651 11:35:48.361971 6, 0xFFFF, sum = 0
3652 11:35:48.365126 7, 0xFFFF, sum = 0
3653 11:35:48.365200 8, 0xFFFF, sum = 0
3654 11:35:48.368590 9, 0xFFFF, sum = 0
3655 11:35:48.368677 10, 0xFFFF, sum = 0
3656 11:35:48.371910 11, 0xFFFF, sum = 0
3657 11:35:48.371971 12, 0x0, sum = 1
3658 11:35:48.375458 13, 0x0, sum = 2
3659 11:35:48.375552 14, 0x0, sum = 3
3660 11:35:48.378757 15, 0x0, sum = 4
3661 11:35:48.378827 best_step = 13
3662 11:35:48.378880
3663 11:35:48.378930 ==
3664 11:35:48.381708 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 11:35:48.388624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 11:35:48.388691 ==
3667 11:35:48.388744 RX Vref Scan: 0
3668 11:35:48.388810
3669 11:35:48.391949 RX Vref 0 -> 0, step: 1
3670 11:35:48.392038
3671 11:35:48.395492 RX Delay -21 -> 252, step: 4
3672 11:35:48.398700 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3673 11:35:48.402027 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3674 11:35:48.408813 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3675 11:35:48.412080 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3676 11:35:48.415382 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3677 11:35:48.418540 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3678 11:35:48.422123 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3679 11:35:48.425318 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3680 11:35:48.432396 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3681 11:35:48.435463 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3682 11:35:48.439093 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3683 11:35:48.442174 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3684 11:35:48.445449 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3685 11:35:48.452221 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3686 11:35:48.455254 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3687 11:35:48.458980 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3688 11:35:48.459044 ==
3689 11:35:48.461830 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 11:35:48.465714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 11:35:48.465777 ==
3692 11:35:48.468539 DQS Delay:
3693 11:35:48.468623 DQS0 = 0, DQS1 = 0
3694 11:35:48.471799 DQM Delay:
3695 11:35:48.471859 DQM0 = 113, DQM1 = 108
3696 11:35:48.475172 DQ Delay:
3697 11:35:48.478750 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3698 11:35:48.482117 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3699 11:35:48.485298 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3700 11:35:48.488345 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =116
3701 11:35:48.488431
3702 11:35:48.488516
3703 11:35:48.495077 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3704 11:35:48.498710 CH1 RK1: MR19=303, MR18=F7FE
3705 11:35:48.505019 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3706 11:35:48.508597 [RxdqsGatingPostProcess] freq 1200
3707 11:35:48.515105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3708 11:35:48.515202 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 11:35:48.518538 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 11:35:48.521768 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 11:35:48.525403 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 11:35:48.528423 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 11:35:48.531846 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 11:35:48.535048 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 11:35:48.538833 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 11:35:48.541776 Pre-setting of DQS Precalculation
3717 11:35:48.544955 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3718 11:35:48.555437 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3719 11:35:48.561685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3720 11:35:48.561754
3721 11:35:48.561810
3722 11:35:48.565043 [Calibration Summary] 2400 Mbps
3723 11:35:48.565132 CH 0, Rank 0
3724 11:35:48.568457 SW Impedance : PASS
3725 11:35:48.568520 DUTY Scan : NO K
3726 11:35:48.571833 ZQ Calibration : PASS
3727 11:35:48.575693 Jitter Meter : NO K
3728 11:35:48.575759 CBT Training : PASS
3729 11:35:48.578450 Write leveling : PASS
3730 11:35:48.581705 RX DQS gating : PASS
3731 11:35:48.581779 RX DQ/DQS(RDDQC) : PASS
3732 11:35:48.585030 TX DQ/DQS : PASS
3733 11:35:48.588490 RX DATLAT : PASS
3734 11:35:48.588563 RX DQ/DQS(Engine): PASS
3735 11:35:48.591725 TX OE : NO K
3736 11:35:48.591798 All Pass.
3737 11:35:48.591855
3738 11:35:48.595467 CH 0, Rank 1
3739 11:35:48.595540 SW Impedance : PASS
3740 11:35:48.598504 DUTY Scan : NO K
3741 11:35:48.602153 ZQ Calibration : PASS
3742 11:35:48.602227 Jitter Meter : NO K
3743 11:35:48.604964 CBT Training : PASS
3744 11:35:48.605037 Write leveling : PASS
3745 11:35:48.608511 RX DQS gating : PASS
3746 11:35:48.611751 RX DQ/DQS(RDDQC) : PASS
3747 11:35:48.611824 TX DQ/DQS : PASS
3748 11:35:48.615271 RX DATLAT : PASS
3749 11:35:48.618728 RX DQ/DQS(Engine): PASS
3750 11:35:48.618801 TX OE : NO K
3751 11:35:48.621584 All Pass.
3752 11:35:48.621657
3753 11:35:48.621714 CH 1, Rank 0
3754 11:35:48.625575 SW Impedance : PASS
3755 11:35:48.625663 DUTY Scan : NO K
3756 11:35:48.628213 ZQ Calibration : PASS
3757 11:35:48.632023 Jitter Meter : NO K
3758 11:35:48.632096 CBT Training : PASS
3759 11:35:48.635242 Write leveling : PASS
3760 11:35:48.638523 RX DQS gating : PASS
3761 11:35:48.638597 RX DQ/DQS(RDDQC) : PASS
3762 11:35:48.641865 TX DQ/DQS : PASS
3763 11:35:48.641938 RX DATLAT : PASS
3764 11:35:48.645173 RX DQ/DQS(Engine): PASS
3765 11:35:48.648387 TX OE : NO K
3766 11:35:48.648460 All Pass.
3767 11:35:48.648518
3768 11:35:48.648571 CH 1, Rank 1
3769 11:35:48.651792 SW Impedance : PASS
3770 11:35:48.655121 DUTY Scan : NO K
3771 11:35:48.655194 ZQ Calibration : PASS
3772 11:35:48.658878 Jitter Meter : NO K
3773 11:35:48.661899 CBT Training : PASS
3774 11:35:48.661971 Write leveling : PASS
3775 11:35:48.665309 RX DQS gating : PASS
3776 11:35:48.668626 RX DQ/DQS(RDDQC) : PASS
3777 11:35:48.668700 TX DQ/DQS : PASS
3778 11:35:48.671884 RX DATLAT : PASS
3779 11:35:48.675772 RX DQ/DQS(Engine): PASS
3780 11:35:48.675852 TX OE : NO K
3781 11:35:48.679165 All Pass.
3782 11:35:48.679238
3783 11:35:48.679295 DramC Write-DBI off
3784 11:35:48.681693 PER_BANK_REFRESH: Hybrid Mode
3785 11:35:48.681767 TX_TRACKING: ON
3786 11:35:48.692145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3787 11:35:48.695357 [FAST_K] Save calibration result to emmc
3788 11:35:48.698610 dramc_set_vcore_voltage set vcore to 650000
3789 11:35:48.702006 Read voltage for 600, 5
3790 11:35:48.702079 Vio18 = 0
3791 11:35:48.705099 Vcore = 650000
3792 11:35:48.705210 Vdram = 0
3793 11:35:48.705283 Vddq = 0
3794 11:35:48.705380 Vmddr = 0
3795 11:35:48.711486 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3796 11:35:48.718469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3797 11:35:48.718544 MEM_TYPE=3, freq_sel=19
3798 11:35:48.721868 sv_algorithm_assistance_LP4_1600
3799 11:35:48.725300 ============ PULL DRAM RESETB DOWN ============
3800 11:35:48.732018 ========== PULL DRAM RESETB DOWN end =========
3801 11:35:48.735023 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3802 11:35:48.738546 ===================================
3803 11:35:48.742051 LPDDR4 DRAM CONFIGURATION
3804 11:35:48.745113 ===================================
3805 11:35:48.745191 EX_ROW_EN[0] = 0x0
3806 11:35:48.748453 EX_ROW_EN[1] = 0x0
3807 11:35:48.748527 LP4Y_EN = 0x0
3808 11:35:48.752226 WORK_FSP = 0x0
3809 11:35:48.752300 WL = 0x2
3810 11:35:48.755376 RL = 0x2
3811 11:35:48.755449 BL = 0x2
3812 11:35:48.758466 RPST = 0x0
3813 11:35:48.761909 RD_PRE = 0x0
3814 11:35:48.761983 WR_PRE = 0x1
3815 11:35:48.766009 WR_PST = 0x0
3816 11:35:48.766082 DBI_WR = 0x0
3817 11:35:48.768651 DBI_RD = 0x0
3818 11:35:48.768725 OTF = 0x1
3819 11:35:48.771659 ===================================
3820 11:35:48.774933 ===================================
3821 11:35:48.775007 ANA top config
3822 11:35:48.778889 ===================================
3823 11:35:48.781702 DLL_ASYNC_EN = 0
3824 11:35:48.785563 ALL_SLAVE_EN = 1
3825 11:35:48.788412 NEW_RANK_MODE = 1
3826 11:35:48.792148 DLL_IDLE_MODE = 1
3827 11:35:48.792222 LP45_APHY_COMB_EN = 1
3828 11:35:48.795157 TX_ODT_DIS = 1
3829 11:35:48.798553 NEW_8X_MODE = 1
3830 11:35:48.802443 ===================================
3831 11:35:48.805668 ===================================
3832 11:35:48.808527 data_rate = 1200
3833 11:35:48.812101 CKR = 1
3834 11:35:48.812176 DQ_P2S_RATIO = 8
3835 11:35:48.815436 ===================================
3836 11:35:48.818772 CA_P2S_RATIO = 8
3837 11:35:48.821832 DQ_CA_OPEN = 0
3838 11:35:48.825458 DQ_SEMI_OPEN = 0
3839 11:35:48.828838 CA_SEMI_OPEN = 0
3840 11:35:48.828911 CA_FULL_RATE = 0
3841 11:35:48.832174 DQ_CKDIV4_EN = 1
3842 11:35:48.835201 CA_CKDIV4_EN = 1
3843 11:35:48.838930 CA_PREDIV_EN = 0
3844 11:35:48.841960 PH8_DLY = 0
3845 11:35:48.845432 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3846 11:35:48.845505 DQ_AAMCK_DIV = 4
3847 11:35:48.848698 CA_AAMCK_DIV = 4
3848 11:35:48.852466 CA_ADMCK_DIV = 4
3849 11:35:48.855414 DQ_TRACK_CA_EN = 0
3850 11:35:48.859038 CA_PICK = 600
3851 11:35:48.862230 CA_MCKIO = 600
3852 11:35:48.862303 MCKIO_SEMI = 0
3853 11:35:48.865958 PLL_FREQ = 2288
3854 11:35:48.869059 DQ_UI_PI_RATIO = 32
3855 11:35:48.872165 CA_UI_PI_RATIO = 0
3856 11:35:48.875808 ===================================
3857 11:35:48.878821 ===================================
3858 11:35:48.882097 memory_type:LPDDR4
3859 11:35:48.882170 GP_NUM : 10
3860 11:35:48.885907 SRAM_EN : 1
3861 11:35:48.888995 MD32_EN : 0
3862 11:35:48.891977 ===================================
3863 11:35:48.892050 [ANA_INIT] >>>>>>>>>>>>>>
3864 11:35:48.895408 <<<<<< [CONFIGURE PHASE]: ANA_TX
3865 11:35:48.899345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3866 11:35:48.902375 ===================================
3867 11:35:48.905892 data_rate = 1200,PCW = 0X5800
3868 11:35:48.908841 ===================================
3869 11:35:48.912059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3870 11:35:48.918801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 11:35:48.922463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 11:35:48.928847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3873 11:35:48.932429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3874 11:35:48.935801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3875 11:35:48.935875 [ANA_INIT] flow start
3876 11:35:48.938939 [ANA_INIT] PLL >>>>>>>>
3877 11:35:48.942385 [ANA_INIT] PLL <<<<<<<<
3878 11:35:48.942459 [ANA_INIT] MIDPI >>>>>>>>
3879 11:35:48.945427 [ANA_INIT] MIDPI <<<<<<<<
3880 11:35:48.949097 [ANA_INIT] DLL >>>>>>>>
3881 11:35:48.949180 [ANA_INIT] flow end
3882 11:35:48.955729 ============ LP4 DIFF to SE enter ============
3883 11:35:48.959329 ============ LP4 DIFF to SE exit ============
3884 11:35:48.959404 [ANA_INIT] <<<<<<<<<<<<<
3885 11:35:48.962337 [Flow] Enable top DCM control >>>>>
3886 11:35:48.965435 [Flow] Enable top DCM control <<<<<
3887 11:35:48.969083 Enable DLL master slave shuffle
3888 11:35:48.975972 ==============================================================
3889 11:35:48.979018 Gating Mode config
3890 11:35:48.982394 ==============================================================
3891 11:35:48.986042 Config description:
3892 11:35:48.995565 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3893 11:35:49.002238 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3894 11:35:49.005806 SELPH_MODE 0: By rank 1: By Phase
3895 11:35:49.012490 ==============================================================
3896 11:35:49.015539 GAT_TRACK_EN = 1
3897 11:35:49.019308 RX_GATING_MODE = 2
3898 11:35:49.019406 RX_GATING_TRACK_MODE = 2
3899 11:35:49.022524 SELPH_MODE = 1
3900 11:35:49.025773 PICG_EARLY_EN = 1
3901 11:35:49.029068 VALID_LAT_VALUE = 1
3902 11:35:49.035737 ==============================================================
3903 11:35:49.039154 Enter into Gating configuration >>>>
3904 11:35:49.042750 Exit from Gating configuration <<<<
3905 11:35:49.045812 Enter into DVFS_PRE_config >>>>>
3906 11:35:49.055964 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3907 11:35:49.059518 Exit from DVFS_PRE_config <<<<<
3908 11:35:49.063205 Enter into PICG configuration >>>>
3909 11:35:49.066209 Exit from PICG configuration <<<<
3910 11:35:49.069350 [RX_INPUT] configuration >>>>>
3911 11:35:49.069423 [RX_INPUT] configuration <<<<<
3912 11:35:49.076079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3913 11:35:49.082604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3914 11:35:49.085982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 11:35:49.092936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 11:35:49.099402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 11:35:49.105813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 11:35:49.109053 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3919 11:35:49.112645 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3920 11:35:49.119503 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3921 11:35:49.122572 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3922 11:35:49.126008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3923 11:35:49.132784 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 11:35:49.136292 ===================================
3925 11:35:49.136366 LPDDR4 DRAM CONFIGURATION
3926 11:35:49.139600 ===================================
3927 11:35:49.142656 EX_ROW_EN[0] = 0x0
3928 11:35:49.142729 EX_ROW_EN[1] = 0x0
3929 11:35:49.145885 LP4Y_EN = 0x0
3930 11:35:49.145959 WORK_FSP = 0x0
3931 11:35:49.149485 WL = 0x2
3932 11:35:49.149558 RL = 0x2
3933 11:35:49.152514 BL = 0x2
3934 11:35:49.152587 RPST = 0x0
3935 11:35:49.155914 RD_PRE = 0x0
3936 11:35:49.159181 WR_PRE = 0x1
3937 11:35:49.159255 WR_PST = 0x0
3938 11:35:49.163083 DBI_WR = 0x0
3939 11:35:49.163156 DBI_RD = 0x0
3940 11:35:49.165954 OTF = 0x1
3941 11:35:49.169096 ===================================
3942 11:35:49.172791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3943 11:35:49.176319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3944 11:35:49.179198 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3945 11:35:49.182584 ===================================
3946 11:35:49.185810 LPDDR4 DRAM CONFIGURATION
3947 11:35:49.189080 ===================================
3948 11:35:49.193044 EX_ROW_EN[0] = 0x10
3949 11:35:49.193164 EX_ROW_EN[1] = 0x0
3950 11:35:49.196226 LP4Y_EN = 0x0
3951 11:35:49.196299 WORK_FSP = 0x0
3952 11:35:49.199581 WL = 0x2
3953 11:35:49.199655 RL = 0x2
3954 11:35:49.202599 BL = 0x2
3955 11:35:49.202673 RPST = 0x0
3956 11:35:49.206294 RD_PRE = 0x0
3957 11:35:49.206367 WR_PRE = 0x1
3958 11:35:49.209222 WR_PST = 0x0
3959 11:35:49.209298 DBI_WR = 0x0
3960 11:35:49.212532 DBI_RD = 0x0
3961 11:35:49.212607 OTF = 0x1
3962 11:35:49.215817 ===================================
3963 11:35:49.222292 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3964 11:35:49.227629 nWR fixed to 30
3965 11:35:49.230700 [ModeRegInit_LP4] CH0 RK0
3966 11:35:49.230777 [ModeRegInit_LP4] CH0 RK1
3967 11:35:49.234100 [ModeRegInit_LP4] CH1 RK0
3968 11:35:49.237634 [ModeRegInit_LP4] CH1 RK1
3969 11:35:49.237711 match AC timing 17
3970 11:35:49.244363 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3971 11:35:49.247539 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3972 11:35:49.250635 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3973 11:35:49.257293 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3974 11:35:49.260590 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3975 11:35:49.260681 ==
3976 11:35:49.264044 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 11:35:49.267362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 11:35:49.267431 ==
3979 11:35:49.274485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 11:35:49.281043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 11:35:49.284435 [CA 0] Center 36 (6~66) winsize 61
3982 11:35:49.287487 [CA 1] Center 36 (6~66) winsize 61
3983 11:35:49.290955 [CA 2] Center 34 (4~65) winsize 62
3984 11:35:49.294057 [CA 3] Center 34 (4~65) winsize 62
3985 11:35:49.297480 [CA 4] Center 34 (4~64) winsize 61
3986 11:35:49.300660 [CA 5] Center 33 (3~64) winsize 62
3987 11:35:49.300746
3988 11:35:49.304025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 11:35:49.304109
3990 11:35:49.307544 [CATrainingPosCal] consider 1 rank data
3991 11:35:49.310661 u2DelayCellTimex100 = 270/100 ps
3992 11:35:49.313955 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3993 11:35:49.317565 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 11:35:49.320673 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 11:35:49.324445 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 11:35:49.327582 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3997 11:35:49.330760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 11:35:49.330836
3999 11:35:49.337568 CA PerBit enable=1, Macro0, CA PI delay=33
4000 11:35:49.337644
4001 11:35:49.337721 [CBTSetCACLKResult] CA Dly = 33
4002 11:35:49.340660 CS Dly: 4 (0~35)
4003 11:35:49.340736 ==
4004 11:35:49.344002 Dram Type= 6, Freq= 0, CH_0, rank 1
4005 11:35:49.347610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 11:35:49.347687 ==
4007 11:35:49.354418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 11:35:49.361248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4009 11:35:49.364599 [CA 0] Center 36 (6~66) winsize 61
4010 11:35:49.367579 [CA 1] Center 36 (6~66) winsize 61
4011 11:35:49.370834 [CA 2] Center 34 (4~65) winsize 62
4012 11:35:49.374266 [CA 3] Center 34 (4~64) winsize 61
4013 11:35:49.377395 [CA 4] Center 33 (3~64) winsize 62
4014 11:35:49.380796 [CA 5] Center 33 (3~64) winsize 62
4015 11:35:49.380872
4016 11:35:49.384068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4017 11:35:49.384145
4018 11:35:49.387820 [CATrainingPosCal] consider 2 rank data
4019 11:35:49.390885 u2DelayCellTimex100 = 270/100 ps
4020 11:35:49.394364 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4021 11:35:49.397336 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 11:35:49.400741 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4023 11:35:49.404360 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4024 11:35:49.407480 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4025 11:35:49.410631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 11:35:49.410707
4027 11:35:49.417934 CA PerBit enable=1, Macro0, CA PI delay=33
4028 11:35:49.418034
4029 11:35:49.421043 [CBTSetCACLKResult] CA Dly = 33
4030 11:35:49.421124 CS Dly: 4 (0~36)
4031 11:35:49.421231
4032 11:35:49.424418 ----->DramcWriteLeveling(PI) begin...
4033 11:35:49.424496 ==
4034 11:35:49.427546 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 11:35:49.430588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 11:35:49.430665 ==
4037 11:35:49.434261 Write leveling (Byte 0): 31 => 31
4038 11:35:49.437706 Write leveling (Byte 1): 28 => 28
4039 11:35:49.440804 DramcWriteLeveling(PI) end<-----
4040 11:35:49.440880
4041 11:35:49.440957 ==
4042 11:35:49.444267 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 11:35:49.447611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 11:35:49.450896 ==
4045 11:35:49.450973 [Gating] SW mode calibration
4046 11:35:49.460992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 11:35:49.464678 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4048 11:35:49.467527 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 11:35:49.474076 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 11:35:49.477409 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 11:35:49.480834 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 11:35:49.488073 0 9 16 | B1->B0 | 3333 2828 | 1 0 | (0 1) (1 0)
4053 11:35:49.491228 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:35:49.494632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:35:49.497934 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:35:49.504351 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:35:49.508343 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:35:49.511563 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:35:49.517585 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4060 11:35:49.521729 0 10 16 | B1->B0 | 3030 3939 | 1 0 | (0 0) (0 0)
4061 11:35:49.524482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:35:49.531314 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:35:49.534566 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:35:49.537810 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:35:49.545289 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 11:35:49.548127 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:35:49.550859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:35:49.558322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4069 11:35:49.560985 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:35:49.564804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:35:49.571565 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:35:49.574495 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:35:49.577600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:35:49.581265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:35:49.587939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:35:49.590985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:35:49.594385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:35:49.601062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:35:49.604289 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:35:49.607816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:35:49.615029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:35:49.617844 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:35:49.621360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:35:49.627929 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4085 11:35:49.631337 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 11:35:49.634607 Total UI for P1: 0, mck2ui 16
4087 11:35:49.637510 best dqsien dly found for B0: ( 0, 13, 16)
4088 11:35:49.641017 Total UI for P1: 0, mck2ui 16
4089 11:35:49.644652 best dqsien dly found for B1: ( 0, 13, 16)
4090 11:35:49.648439 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4091 11:35:49.651010 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4092 11:35:49.651088
4093 11:35:49.654823 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4094 11:35:49.657624 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4095 11:35:49.661056 [Gating] SW calibration Done
4096 11:35:49.661171 ==
4097 11:35:49.664936 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 11:35:49.668795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 11:35:49.671328 ==
4100 11:35:49.671404 RX Vref Scan: 0
4101 11:35:49.671479
4102 11:35:49.675003 RX Vref 0 -> 0, step: 1
4103 11:35:49.675079
4104 11:35:49.677896 RX Delay -230 -> 252, step: 16
4105 11:35:49.681372 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4106 11:35:49.684801 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4107 11:35:49.687920 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4108 11:35:49.691499 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4109 11:35:49.698492 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4110 11:35:49.701179 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4111 11:35:49.705113 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4112 11:35:49.707782 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4113 11:35:49.714698 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4114 11:35:49.718020 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4115 11:35:49.721416 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4116 11:35:49.724560 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4117 11:35:49.728253 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4118 11:35:49.734931 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4119 11:35:49.738043 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4120 11:35:49.741780 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4121 11:35:49.741856 ==
4122 11:35:49.744544 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:35:49.748087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:35:49.751474 ==
4125 11:35:49.751551 DQS Delay:
4126 11:35:49.751628 DQS0 = 0, DQS1 = 0
4127 11:35:49.754592 DQM Delay:
4128 11:35:49.754669 DQM0 = 40, DQM1 = 32
4129 11:35:49.758111 DQ Delay:
4130 11:35:49.758188 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4131 11:35:49.761288 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4132 11:35:49.764905 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4133 11:35:49.768083 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4134 11:35:49.768159
4135 11:35:49.771640
4136 11:35:49.771716 ==
4137 11:35:49.775026 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 11:35:49.777912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 11:35:49.777988 ==
4140 11:35:49.778065
4141 11:35:49.778136
4142 11:35:49.781390 TX Vref Scan disable
4143 11:35:49.781466 == TX Byte 0 ==
4144 11:35:49.787918 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4145 11:35:49.791531 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4146 11:35:49.791607 == TX Byte 1 ==
4147 11:35:49.797861 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4148 11:35:49.801355 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4149 11:35:49.801432 ==
4150 11:35:49.804659 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 11:35:49.808006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:35:49.808083 ==
4153 11:35:49.808159
4154 11:35:49.808229
4155 11:35:49.811306 TX Vref Scan disable
4156 11:35:49.814686 == TX Byte 0 ==
4157 11:35:49.817911 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4158 11:35:49.821798 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4159 11:35:49.824898 == TX Byte 1 ==
4160 11:35:49.828244 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4161 11:35:49.831241 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4162 11:35:49.831331
4163 11:35:49.834614 [DATLAT]
4164 11:35:49.834700 Freq=600, CH0 RK0
4165 11:35:49.834782
4166 11:35:49.837704 DATLAT Default: 0x9
4167 11:35:49.837763 0, 0xFFFF, sum = 0
4168 11:35:49.841251 1, 0xFFFF, sum = 0
4169 11:35:49.841311 2, 0xFFFF, sum = 0
4170 11:35:49.844430 3, 0xFFFF, sum = 0
4171 11:35:49.844487 4, 0xFFFF, sum = 0
4172 11:35:49.847925 5, 0xFFFF, sum = 0
4173 11:35:49.848011 6, 0xFFFF, sum = 0
4174 11:35:49.851312 7, 0xFFFF, sum = 0
4175 11:35:49.851397 8, 0x0, sum = 1
4176 11:35:49.855152 9, 0x0, sum = 2
4177 11:35:49.855238 10, 0x0, sum = 3
4178 11:35:49.858026 11, 0x0, sum = 4
4179 11:35:49.858114 best_step = 9
4180 11:35:49.858190
4181 11:35:49.858267 ==
4182 11:35:49.861268 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 11:35:49.864645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 11:35:49.867809 ==
4185 11:35:49.867895 RX Vref Scan: 1
4186 11:35:49.867972
4187 11:35:49.871655 RX Vref 0 -> 0, step: 1
4188 11:35:49.871739
4189 11:35:49.874807 RX Delay -195 -> 252, step: 8
4190 11:35:49.874869
4191 11:35:49.877914 Set Vref, RX VrefLevel [Byte0]: 54
4192 11:35:49.877977 [Byte1]: 51
4193 11:35:49.883269
4194 11:35:49.883357 Final RX Vref Byte 0 = 54 to rank0
4195 11:35:49.886364 Final RX Vref Byte 1 = 51 to rank0
4196 11:35:49.889951 Final RX Vref Byte 0 = 54 to rank1
4197 11:35:49.893288 Final RX Vref Byte 1 = 51 to rank1==
4198 11:35:49.896370 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 11:35:49.903048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 11:35:49.903139 ==
4201 11:35:49.903222 DQS Delay:
4202 11:35:49.903300 DQS0 = 0, DQS1 = 0
4203 11:35:49.906350 DQM Delay:
4204 11:35:49.906413 DQM0 = 43, DQM1 = 33
4205 11:35:49.909711 DQ Delay:
4206 11:35:49.912914 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4207 11:35:49.913002 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4208 11:35:49.916484 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4209 11:35:49.919648 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4210 11:35:49.923125
4211 11:35:49.923215
4212 11:35:49.930047 [DQSOSCAuto] RK0, (LSB)MR18= 0x4827, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4213 11:35:49.933026 CH0 RK0: MR19=808, MR18=4827
4214 11:35:49.939920 CH0_RK0: MR19=0x808, MR18=0x4827, DQSOSC=396, MR23=63, INC=167, DEC=111
4215 11:35:49.939990
4216 11:35:49.943334 ----->DramcWriteLeveling(PI) begin...
4217 11:35:49.943399 ==
4218 11:35:49.946280 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 11:35:49.949451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:35:49.949547 ==
4221 11:35:49.952970 Write leveling (Byte 0): 33 => 33
4222 11:35:49.956174 Write leveling (Byte 1): 30 => 30
4223 11:35:49.959865 DramcWriteLeveling(PI) end<-----
4224 11:35:49.959953
4225 11:35:49.960031 ==
4226 11:35:49.963111 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 11:35:49.966140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 11:35:49.966232 ==
4229 11:35:49.969474 [Gating] SW mode calibration
4230 11:35:49.976489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 11:35:49.982916 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4232 11:35:49.986309 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 11:35:49.989890 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 11:35:49.996253 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 11:35:49.999590 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
4236 11:35:50.002977 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4237 11:35:50.009914 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:35:50.012806 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:35:50.016412 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:35:50.022940 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 11:35:50.026559 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:35:50.029756 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:35:50.036555 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4244 11:35:50.039579 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4245 11:35:50.043441 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:35:50.046413 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:35:50.053047 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:35:50.056643 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:35:50.059862 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:35:50.066351 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:35:50.070503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4252 11:35:50.073363 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 11:35:50.080037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:35:50.083984 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:35:50.086875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:35:50.093727 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:35:50.097279 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:35:50.100379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:35:50.107201 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:35:50.110554 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:35:50.113527 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:35:50.116864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:35:50.123613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:35:50.127144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:35:50.130266 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:35:50.136769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:35:50.141047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:35:50.143842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4269 11:35:50.146978 Total UI for P1: 0, mck2ui 16
4270 11:35:50.150217 best dqsien dly found for B0: ( 0, 13, 14)
4271 11:35:50.157468 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4272 11:35:50.160318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:35:50.163713 Total UI for P1: 0, mck2ui 16
4274 11:35:50.167325 best dqsien dly found for B1: ( 0, 13, 18)
4275 11:35:50.170778 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4276 11:35:50.173499 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4277 11:35:50.173565
4278 11:35:50.176804 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 11:35:50.180651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4280 11:35:50.183713 [Gating] SW calibration Done
4281 11:35:50.183802 ==
4282 11:35:50.187134 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:35:50.190300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:35:50.193488 ==
4285 11:35:50.193555 RX Vref Scan: 0
4286 11:35:50.193612
4287 11:35:50.197298 RX Vref 0 -> 0, step: 1
4288 11:35:50.197360
4289 11:35:50.200646 RX Delay -230 -> 252, step: 16
4290 11:35:50.203528 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 11:35:50.207213 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4292 11:35:50.210207 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 11:35:50.213851 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 11:35:50.220368 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 11:35:50.223539 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4296 11:35:50.227024 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 11:35:50.230498 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 11:35:50.237208 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 11:35:50.240547 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 11:35:50.243819 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 11:35:50.247078 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 11:35:50.250340 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 11:35:50.257021 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 11:35:50.260358 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4305 11:35:50.263405 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4306 11:35:50.263491 ==
4307 11:35:50.267226 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 11:35:50.270125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 11:35:50.273614 ==
4310 11:35:50.273684 DQS Delay:
4311 11:35:50.273742 DQS0 = 0, DQS1 = 0
4312 11:35:50.277097 DQM Delay:
4313 11:35:50.277167 DQM0 = 39, DQM1 = 33
4314 11:35:50.280343 DQ Delay:
4315 11:35:50.280428 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4316 11:35:50.283841 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4317 11:35:50.287082 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4318 11:35:50.290952 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4319 11:35:50.291039
4320 11:35:50.294240
4321 11:35:50.294303 ==
4322 11:35:50.297202 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 11:35:50.300642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 11:35:50.300720 ==
4325 11:35:50.300801
4326 11:35:50.300878
4327 11:35:50.303835 TX Vref Scan disable
4328 11:35:50.303897 == TX Byte 0 ==
4329 11:35:50.310383 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 11:35:50.314149 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 11:35:50.314212 == TX Byte 1 ==
4332 11:35:50.320919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 11:35:50.323594 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 11:35:50.323680 ==
4335 11:35:50.327185 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 11:35:50.330468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 11:35:50.330536 ==
4338 11:35:50.330607
4339 11:35:50.330684
4340 11:35:50.333957 TX Vref Scan disable
4341 11:35:50.337385 == TX Byte 0 ==
4342 11:35:50.340734 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4343 11:35:50.343876 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4344 11:35:50.347246 == TX Byte 1 ==
4345 11:35:50.350883 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 11:35:50.353604 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 11:35:50.353666
4348 11:35:50.357040 [DATLAT]
4349 11:35:50.357128 Freq=600, CH0 RK1
4350 11:35:50.357183
4351 11:35:50.360796 DATLAT Default: 0x9
4352 11:35:50.360852 0, 0xFFFF, sum = 0
4353 11:35:50.363914 1, 0xFFFF, sum = 0
4354 11:35:50.363999 2, 0xFFFF, sum = 0
4355 11:35:50.367204 3, 0xFFFF, sum = 0
4356 11:35:50.367289 4, 0xFFFF, sum = 0
4357 11:35:50.370570 5, 0xFFFF, sum = 0
4358 11:35:50.370652 6, 0xFFFF, sum = 0
4359 11:35:50.373729 7, 0xFFFF, sum = 0
4360 11:35:50.373790 8, 0x0, sum = 1
4361 11:35:50.377272 9, 0x0, sum = 2
4362 11:35:50.377330 10, 0x0, sum = 3
4363 11:35:50.380852 11, 0x0, sum = 4
4364 11:35:50.380937 best_step = 9
4365 11:35:50.381017
4366 11:35:50.381094 ==
4367 11:35:50.383670 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 11:35:50.387677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 11:35:50.387745 ==
4370 11:35:50.390392 RX Vref Scan: 0
4371 11:35:50.390457
4372 11:35:50.394013 RX Vref 0 -> 0, step: 1
4373 11:35:50.394075
4374 11:35:50.394128 RX Delay -179 -> 252, step: 8
4375 11:35:50.401882 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4376 11:35:50.405485 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4377 11:35:50.408860 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4378 11:35:50.411969 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4379 11:35:50.418298 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4380 11:35:50.421795 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4381 11:35:50.425306 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4382 11:35:50.428521 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4383 11:35:50.432239 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4384 11:35:50.438615 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4385 11:35:50.442129 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4386 11:35:50.445241 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4387 11:35:50.448739 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 11:35:50.455180 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4389 11:35:50.458807 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4390 11:35:50.461917 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4391 11:35:50.461982 ==
4392 11:35:50.465403 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 11:35:50.469522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:35:50.469587 ==
4395 11:35:50.472093 DQS Delay:
4396 11:35:50.472177 DQS0 = 0, DQS1 = 0
4397 11:35:50.475328 DQM Delay:
4398 11:35:50.475414 DQM0 = 39, DQM1 = 33
4399 11:35:50.475491 DQ Delay:
4400 11:35:50.478812 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4401 11:35:50.482028 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4402 11:35:50.485378 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4403 11:35:50.488811 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4404 11:35:50.488900
4405 11:35:50.488983
4406 11:35:50.498508 [DQSOSCAuto] RK1, (LSB)MR18= 0x5235, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4407 11:35:50.502257 CH0 RK1: MR19=808, MR18=5235
4408 11:35:50.508730 CH0_RK1: MR19=0x808, MR18=0x5235, DQSOSC=394, MR23=63, INC=168, DEC=112
4409 11:35:50.508822 [RxdqsGatingPostProcess] freq 600
4410 11:35:50.515381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 11:35:50.518713 Pre-setting of DQS Precalculation
4412 11:35:50.522381 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 11:35:50.525266 ==
4414 11:35:50.528773 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 11:35:50.531832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 11:35:50.531922 ==
4417 11:35:50.535243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 11:35:50.541566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 11:35:50.545363 [CA 0] Center 35 (5~66) winsize 62
4420 11:35:50.549105 [CA 1] Center 35 (5~66) winsize 62
4421 11:35:50.552554 [CA 2] Center 33 (3~64) winsize 62
4422 11:35:50.555635 [CA 3] Center 33 (3~64) winsize 62
4423 11:35:50.558771 [CA 4] Center 33 (3~64) winsize 62
4424 11:35:50.562452 [CA 5] Center 33 (2~64) winsize 63
4425 11:35:50.562546
4426 11:35:50.565370 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 11:35:50.565436
4428 11:35:50.568647 [CATrainingPosCal] consider 1 rank data
4429 11:35:50.572487 u2DelayCellTimex100 = 270/100 ps
4430 11:35:50.575476 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 11:35:50.579450 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 11:35:50.585772 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 11:35:50.588993 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 11:35:50.592138 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 11:35:50.595465 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4436 11:35:50.595553
4437 11:35:50.599162 CA PerBit enable=1, Macro0, CA PI delay=33
4438 11:35:50.599233
4439 11:35:50.602360 [CBTSetCACLKResult] CA Dly = 33
4440 11:35:50.602426 CS Dly: 4 (0~35)
4441 11:35:50.602500 ==
4442 11:35:50.605383 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 11:35:50.612270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 11:35:50.612362 ==
4445 11:35:50.615381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 11:35:50.622495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 11:35:50.625724 [CA 0] Center 35 (5~66) winsize 62
4448 11:35:50.628795 [CA 1] Center 35 (5~66) winsize 62
4449 11:35:50.632297 [CA 2] Center 34 (3~65) winsize 63
4450 11:35:50.636111 [CA 3] Center 33 (3~64) winsize 62
4451 11:35:50.638963 [CA 4] Center 34 (3~65) winsize 63
4452 11:35:50.642815 [CA 5] Center 33 (3~64) winsize 62
4453 11:35:50.642890
4454 11:35:50.645721 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 11:35:50.645801
4456 11:35:50.649114 [CATrainingPosCal] consider 2 rank data
4457 11:35:50.652769 u2DelayCellTimex100 = 270/100 ps
4458 11:35:50.655822 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 11:35:50.658892 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 11:35:50.665945 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 11:35:50.668917 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 11:35:50.672727 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 11:35:50.675800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 11:35:50.675877
4465 11:35:50.678825 CA PerBit enable=1, Macro0, CA PI delay=33
4466 11:35:50.678899
4467 11:35:50.682282 [CBTSetCACLKResult] CA Dly = 33
4468 11:35:50.682356 CS Dly: 5 (0~37)
4469 11:35:50.682413
4470 11:35:50.685532 ----->DramcWriteLeveling(PI) begin...
4471 11:35:50.689504 ==
4472 11:35:50.692373 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 11:35:50.695616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 11:35:50.695710 ==
4475 11:35:50.699032 Write leveling (Byte 0): 30 => 30
4476 11:35:50.702382 Write leveling (Byte 1): 30 => 30
4477 11:35:50.705343 DramcWriteLeveling(PI) end<-----
4478 11:35:50.705434
4479 11:35:50.705526 ==
4480 11:35:50.708765 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:35:50.711839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:35:50.711908 ==
4483 11:35:50.715334 [Gating] SW mode calibration
4484 11:35:50.722285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 11:35:50.728989 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 11:35:50.732225 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 11:35:50.735339 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 11:35:50.738750 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 11:35:50.745677 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4490 11:35:50.748531 0 9 16 | B1->B0 | 2828 2525 | 1 0 | (1 0) (0 0)
4491 11:35:50.752745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:35:50.758407 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4493 11:35:50.762310 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:35:50.765655 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:35:50.772116 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:35:50.775034 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:35:50.778647 0 10 12 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
4498 11:35:50.785291 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4499 11:35:50.788333 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:35:50.791673 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:35:50.798722 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:35:50.801956 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:35:50.805309 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:35:50.811626 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:35:50.815624 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:35:50.818408 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:35:50.824963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:35:50.828134 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:35:50.831961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:35:50.838769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:35:50.841971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:35:50.845202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:35:50.851723 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:35:50.854948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:35:50.858132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:35:50.862032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:35:50.868327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:35:50.871804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:35:50.875024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:35:50.881855 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:35:50.885717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4522 11:35:50.888278 Total UI for P1: 0, mck2ui 16
4523 11:35:50.892032 best dqsien dly found for B0: ( 0, 13, 10)
4524 11:35:50.894899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4525 11:35:50.898385 Total UI for P1: 0, mck2ui 16
4526 11:35:50.902132 best dqsien dly found for B1: ( 0, 13, 12)
4527 11:35:50.905066 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4528 11:35:50.908539 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4529 11:35:50.908608
4530 11:35:50.915300 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4531 11:35:50.918401 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4532 11:35:50.922188 [Gating] SW calibration Done
4533 11:35:50.922278 ==
4534 11:35:50.924767 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:35:50.928506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:35:50.928597 ==
4537 11:35:50.928696 RX Vref Scan: 0
4538 11:35:50.928785
4539 11:35:50.931762 RX Vref 0 -> 0, step: 1
4540 11:35:50.931856
4541 11:35:50.934840 RX Delay -230 -> 252, step: 16
4542 11:35:50.938138 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4543 11:35:50.941982 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4544 11:35:50.948341 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4545 11:35:50.951757 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4546 11:35:50.954929 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4547 11:35:50.958116 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4548 11:35:50.964658 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4549 11:35:50.968388 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4550 11:35:50.971455 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 11:35:50.974848 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4552 11:35:50.978312 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4553 11:35:50.985039 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4554 11:35:50.988458 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4555 11:35:50.991289 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4556 11:35:50.994996 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4557 11:35:51.001609 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4558 11:35:51.001681 ==
4559 11:35:51.004798 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 11:35:51.008007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:35:51.008073 ==
4562 11:35:51.008144 DQS Delay:
4563 11:35:51.011757 DQS0 = 0, DQS1 = 0
4564 11:35:51.011845 DQM Delay:
4565 11:35:51.014836 DQM0 = 43, DQM1 = 35
4566 11:35:51.014899 DQ Delay:
4567 11:35:51.018372 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4568 11:35:51.021768 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4569 11:35:51.024967 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4570 11:35:51.028301 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4571 11:35:51.028377
4572 11:35:51.028452
4573 11:35:51.028523 ==
4574 11:35:51.031500 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 11:35:51.034655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 11:35:51.034731 ==
4577 11:35:51.034808
4578 11:35:51.037971
4579 11:35:51.038048 TX Vref Scan disable
4580 11:35:51.041707 == TX Byte 0 ==
4581 11:35:51.044724 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 11:35:51.048380 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 11:35:51.051503 == TX Byte 1 ==
4584 11:35:51.054960 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 11:35:51.058084 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 11:35:51.058160 ==
4587 11:35:51.061451 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:35:51.068175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:35:51.068252 ==
4590 11:35:51.068328
4591 11:35:51.068399
4592 11:35:51.068469 TX Vref Scan disable
4593 11:35:51.073037 == TX Byte 0 ==
4594 11:35:51.076448 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 11:35:51.079779 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 11:35:51.082364 == TX Byte 1 ==
4597 11:35:51.086363 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4598 11:35:51.089085 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4599 11:35:51.092870
4600 11:35:51.092945 [DATLAT]
4601 11:35:51.093036 Freq=600, CH1 RK0
4602 11:35:51.093133
4603 11:35:51.096016 DATLAT Default: 0x9
4604 11:35:51.096114 0, 0xFFFF, sum = 0
4605 11:35:51.099491 1, 0xFFFF, sum = 0
4606 11:35:51.099569 2, 0xFFFF, sum = 0
4607 11:35:51.102726 3, 0xFFFF, sum = 0
4608 11:35:51.102804 4, 0xFFFF, sum = 0
4609 11:35:51.105921 5, 0xFFFF, sum = 0
4610 11:35:51.105998 6, 0xFFFF, sum = 0
4611 11:35:51.109071 7, 0xFFFF, sum = 0
4612 11:35:51.109180 8, 0x0, sum = 1
4613 11:35:51.112697 9, 0x0, sum = 2
4614 11:35:51.112798 10, 0x0, sum = 3
4615 11:35:51.115911 11, 0x0, sum = 4
4616 11:35:51.115992 best_step = 9
4617 11:35:51.116067
4618 11:35:51.116138 ==
4619 11:35:51.120295 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 11:35:51.126008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 11:35:51.126085 ==
4622 11:35:51.126197 RX Vref Scan: 1
4623 11:35:51.126269
4624 11:35:51.129515 RX Vref 0 -> 0, step: 1
4625 11:35:51.129602
4626 11:35:51.132941 RX Delay -195 -> 252, step: 8
4627 11:35:51.133039
4628 11:35:51.136127 Set Vref, RX VrefLevel [Byte0]: 57
4629 11:35:51.139384 [Byte1]: 47
4630 11:35:51.139460
4631 11:35:51.142878 Final RX Vref Byte 0 = 57 to rank0
4632 11:35:51.146285 Final RX Vref Byte 1 = 47 to rank0
4633 11:35:51.149479 Final RX Vref Byte 0 = 57 to rank1
4634 11:35:51.152543 Final RX Vref Byte 1 = 47 to rank1==
4635 11:35:51.156148 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 11:35:51.159342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 11:35:51.159419 ==
4638 11:35:51.162967 DQS Delay:
4639 11:35:51.163043 DQS0 = 0, DQS1 = 0
4640 11:35:51.163119 DQM Delay:
4641 11:35:51.166024 DQM0 = 40, DQM1 = 31
4642 11:35:51.166101 DQ Delay:
4643 11:35:51.169418 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4644 11:35:51.172595 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4645 11:35:51.175769 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4646 11:35:51.179126 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =36
4647 11:35:51.179202
4648 11:35:51.179278
4649 11:35:51.189127 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4650 11:35:51.189205 CH1 RK0: MR19=808, MR18=4C12
4651 11:35:51.196149 CH1_RK0: MR19=0x808, MR18=0x4C12, DQSOSC=395, MR23=63, INC=168, DEC=112
4652 11:35:51.196227
4653 11:35:51.199296 ----->DramcWriteLeveling(PI) begin...
4654 11:35:51.199374 ==
4655 11:35:51.202769 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 11:35:51.208894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 11:35:51.208971 ==
4658 11:35:51.212648 Write leveling (Byte 0): 30 => 30
4659 11:35:51.215761 Write leveling (Byte 1): 30 => 30
4660 11:35:51.215837 DramcWriteLeveling(PI) end<-----
4661 11:35:51.219483
4662 11:35:51.219560 ==
4663 11:35:51.222610 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 11:35:51.225962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 11:35:51.226039 ==
4666 11:35:51.229074 [Gating] SW mode calibration
4667 11:35:51.235825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 11:35:51.239867 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 11:35:51.245926 0 9 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4670 11:35:51.248976 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 11:35:51.252441 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 11:35:51.259190 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
4673 11:35:51.262688 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:35:51.265838 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:35:51.272810 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:35:51.275725 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 11:35:51.279481 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:35:51.285715 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:35:51.289035 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4680 11:35:51.292882 0 10 12 | B1->B0 | 3030 4141 | 0 0 | (0 0) (0 0)
4681 11:35:51.300029 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4682 11:35:51.302303 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:35:51.305698 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:35:51.309024 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:35:51.316279 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:35:51.319177 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:35:51.322551 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 11:35:51.329236 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4689 11:35:51.332772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4690 11:35:51.335736 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:35:51.342308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:35:51.346041 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:35:51.349282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:35:51.356437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:35:51.359071 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:35:51.362909 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:35:51.369352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:35:51.373153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:35:51.376007 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:35:51.382421 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:35:51.386120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:35:51.389469 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:35:51.395624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:35:51.399151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 11:35:51.402460 Total UI for P1: 0, mck2ui 16
4706 11:35:51.406361 best dqsien dly found for B0: ( 0, 13, 10)
4707 11:35:51.409830 Total UI for P1: 0, mck2ui 16
4708 11:35:51.412909 best dqsien dly found for B1: ( 0, 13, 10)
4709 11:35:51.416202 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4710 11:35:51.419264 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4711 11:35:51.419340
4712 11:35:51.422671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4713 11:35:51.425989 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4714 11:35:51.429329 [Gating] SW calibration Done
4715 11:35:51.429405 ==
4716 11:35:51.432537 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 11:35:51.436240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 11:35:51.436317 ==
4719 11:35:51.439521 RX Vref Scan: 0
4720 11:35:51.439598
4721 11:35:51.439674 RX Vref 0 -> 0, step: 1
4722 11:35:51.442711
4723 11:35:51.442788 RX Delay -230 -> 252, step: 16
4724 11:35:51.449743 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4725 11:35:51.452667 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4726 11:35:51.456345 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4727 11:35:51.459274 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4728 11:35:51.462711 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4729 11:35:51.469248 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4730 11:35:51.472444 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4731 11:35:51.475986 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4732 11:35:51.479800 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4733 11:35:51.487097 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4734 11:35:51.489750 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4735 11:35:51.492729 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4736 11:35:51.496624 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4737 11:35:51.499298 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4738 11:35:51.506303 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4739 11:35:51.509808 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4740 11:35:51.509882 ==
4741 11:35:51.512824 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:35:51.516445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:35:51.516519 ==
4744 11:35:51.519857 DQS Delay:
4745 11:35:51.519931 DQS0 = 0, DQS1 = 0
4746 11:35:51.519988 DQM Delay:
4747 11:35:51.523315 DQM0 = 39, DQM1 = 34
4748 11:35:51.523389 DQ Delay:
4749 11:35:51.526289 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4750 11:35:51.530193 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4751 11:35:51.533254 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4752 11:35:51.536377 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4753 11:35:51.536451
4754 11:35:51.536509
4755 11:35:51.536562 ==
4756 11:35:51.539845 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:35:51.546482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:35:51.546557 ==
4759 11:35:51.546614
4760 11:35:51.546686
4761 11:35:51.546742 TX Vref Scan disable
4762 11:35:51.550190 == TX Byte 0 ==
4763 11:35:51.553088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4764 11:35:51.556740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4765 11:35:51.560137 == TX Byte 1 ==
4766 11:35:51.563266 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 11:35:51.566784 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 11:35:51.570362 ==
4769 11:35:51.573504 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 11:35:51.576592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 11:35:51.576666 ==
4772 11:35:51.576724
4773 11:35:51.576776
4774 11:35:51.580135 TX Vref Scan disable
4775 11:35:51.580210 == TX Byte 0 ==
4776 11:35:51.586607 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4777 11:35:51.590149 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4778 11:35:51.590223 == TX Byte 1 ==
4779 11:35:51.596695 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4780 11:35:51.600201 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4781 11:35:51.600275
4782 11:35:51.600333 [DATLAT]
4783 11:35:51.603291 Freq=600, CH1 RK1
4784 11:35:51.603365
4785 11:35:51.603422 DATLAT Default: 0x9
4786 11:35:51.606582 0, 0xFFFF, sum = 0
4787 11:35:51.606657 1, 0xFFFF, sum = 0
4788 11:35:51.610244 2, 0xFFFF, sum = 0
4789 11:35:51.610320 3, 0xFFFF, sum = 0
4790 11:35:51.613342 4, 0xFFFF, sum = 0
4791 11:35:51.613417 5, 0xFFFF, sum = 0
4792 11:35:51.616500 6, 0xFFFF, sum = 0
4793 11:35:51.616576 7, 0xFFFF, sum = 0
4794 11:35:51.620062 8, 0x0, sum = 1
4795 11:35:51.620137 9, 0x0, sum = 2
4796 11:35:51.623567 10, 0x0, sum = 3
4797 11:35:51.623643 11, 0x0, sum = 4
4798 11:35:51.627057 best_step = 9
4799 11:35:51.627129
4800 11:35:51.627187 ==
4801 11:35:51.630256 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 11:35:51.633236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 11:35:51.633311 ==
4804 11:35:51.637004 RX Vref Scan: 0
4805 11:35:51.637078
4806 11:35:51.637172 RX Vref 0 -> 0, step: 1
4807 11:35:51.637227
4808 11:35:51.640211 RX Delay -195 -> 252, step: 8
4809 11:35:51.646856 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4810 11:35:51.650176 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4811 11:35:51.653873 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4812 11:35:51.657150 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4813 11:35:51.663778 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4814 11:35:51.666994 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4815 11:35:51.670368 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4816 11:35:51.673650 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4817 11:35:51.677040 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4818 11:35:51.683631 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4819 11:35:51.687205 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4820 11:35:51.690264 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4821 11:35:51.693881 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4822 11:35:51.700468 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4823 11:35:51.703609 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4824 11:35:51.707521 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4825 11:35:51.707595 ==
4826 11:35:51.710571 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 11:35:51.713671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 11:35:51.713776 ==
4829 11:35:51.717123 DQS Delay:
4830 11:35:51.717215 DQS0 = 0, DQS1 = 0
4831 11:35:51.720501 DQM Delay:
4832 11:35:51.720577 DQM0 = 37, DQM1 = 33
4833 11:35:51.720636 DQ Delay:
4834 11:35:51.723687 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4835 11:35:51.727508 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4836 11:35:51.730797 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4837 11:35:51.733781 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4838 11:35:51.733855
4839 11:35:51.733913
4840 11:35:51.743607 [DQSOSCAuto] RK1, (LSB)MR18= 0x3745, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4841 11:35:51.747226 CH1 RK1: MR19=808, MR18=3745
4842 11:35:51.754067 CH1_RK1: MR19=0x808, MR18=0x3745, DQSOSC=396, MR23=63, INC=167, DEC=111
4843 11:35:51.754141 [RxdqsGatingPostProcess] freq 600
4844 11:35:51.760479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4845 11:35:51.763540 Pre-setting of DQS Precalculation
4846 11:35:51.767091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4847 11:35:51.777220 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4848 11:35:51.783599 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4849 11:35:51.783674
4850 11:35:51.783731
4851 11:35:51.787356 [Calibration Summary] 1200 Mbps
4852 11:35:51.787430 CH 0, Rank 0
4853 11:35:51.790599 SW Impedance : PASS
4854 11:35:51.790673 DUTY Scan : NO K
4855 11:35:51.793885 ZQ Calibration : PASS
4856 11:35:51.797207 Jitter Meter : NO K
4857 11:35:51.797280 CBT Training : PASS
4858 11:35:51.800739 Write leveling : PASS
4859 11:35:51.803993 RX DQS gating : PASS
4860 11:35:51.804067 RX DQ/DQS(RDDQC) : PASS
4861 11:35:51.807726 TX DQ/DQS : PASS
4862 11:35:51.807801 RX DATLAT : PASS
4863 11:35:51.810617 RX DQ/DQS(Engine): PASS
4864 11:35:51.814030 TX OE : NO K
4865 11:35:51.814105 All Pass.
4866 11:35:51.814162
4867 11:35:51.814215 CH 0, Rank 1
4868 11:35:51.817220 SW Impedance : PASS
4869 11:35:51.821176 DUTY Scan : NO K
4870 11:35:51.821251 ZQ Calibration : PASS
4871 11:35:51.824117 Jitter Meter : NO K
4872 11:35:51.827568 CBT Training : PASS
4873 11:35:51.827643 Write leveling : PASS
4874 11:35:51.831009 RX DQS gating : PASS
4875 11:35:51.834585 RX DQ/DQS(RDDQC) : PASS
4876 11:35:51.834659 TX DQ/DQS : PASS
4877 11:35:51.837179 RX DATLAT : PASS
4878 11:35:51.841127 RX DQ/DQS(Engine): PASS
4879 11:35:51.841216 TX OE : NO K
4880 11:35:51.841274 All Pass.
4881 11:35:51.844048
4882 11:35:51.844121 CH 1, Rank 0
4883 11:35:51.847187 SW Impedance : PASS
4884 11:35:51.847261 DUTY Scan : NO K
4885 11:35:51.850996 ZQ Calibration : PASS
4886 11:35:51.851070 Jitter Meter : NO K
4887 11:35:51.854066 CBT Training : PASS
4888 11:35:51.857400 Write leveling : PASS
4889 11:35:51.857474 RX DQS gating : PASS
4890 11:35:51.860747 RX DQ/DQS(RDDQC) : PASS
4891 11:35:51.863967 TX DQ/DQS : PASS
4892 11:35:51.864041 RX DATLAT : PASS
4893 11:35:51.867097 RX DQ/DQS(Engine): PASS
4894 11:35:51.870642 TX OE : NO K
4895 11:35:51.870716 All Pass.
4896 11:35:51.870773
4897 11:35:51.870826 CH 1, Rank 1
4898 11:35:51.874132 SW Impedance : PASS
4899 11:35:51.877401 DUTY Scan : NO K
4900 11:35:51.877475 ZQ Calibration : PASS
4901 11:35:51.880413 Jitter Meter : NO K
4902 11:35:51.883779 CBT Training : PASS
4903 11:35:51.883854 Write leveling : PASS
4904 11:35:51.887313 RX DQS gating : PASS
4905 11:35:51.890515 RX DQ/DQS(RDDQC) : PASS
4906 11:35:51.890590 TX DQ/DQS : PASS
4907 11:35:51.894375 RX DATLAT : PASS
4908 11:35:51.894449 RX DQ/DQS(Engine): PASS
4909 11:35:51.897236 TX OE : NO K
4910 11:35:51.897310 All Pass.
4911 11:35:51.897368
4912 11:35:51.900700 DramC Write-DBI off
4913 11:35:51.904355 PER_BANK_REFRESH: Hybrid Mode
4914 11:35:51.904430 TX_TRACKING: ON
4915 11:35:51.914119 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4916 11:35:51.917531 [FAST_K] Save calibration result to emmc
4917 11:35:51.920986 dramc_set_vcore_voltage set vcore to 662500
4918 11:35:51.924149 Read voltage for 933, 3
4919 11:35:51.924223 Vio18 = 0
4920 11:35:51.924281 Vcore = 662500
4921 11:35:51.927434 Vdram = 0
4922 11:35:51.927508 Vddq = 0
4923 11:35:51.927566 Vmddr = 0
4924 11:35:51.933791 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4925 11:35:51.937265 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4926 11:35:51.940716 MEM_TYPE=3, freq_sel=17
4927 11:35:51.943977 sv_algorithm_assistance_LP4_1600
4928 11:35:51.947642 ============ PULL DRAM RESETB DOWN ============
4929 11:35:51.950543 ========== PULL DRAM RESETB DOWN end =========
4930 11:35:51.957313 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4931 11:35:51.960500 ===================================
4932 11:35:51.960575 LPDDR4 DRAM CONFIGURATION
4933 11:35:51.963912 ===================================
4934 11:35:51.967376 EX_ROW_EN[0] = 0x0
4935 11:35:51.970776 EX_ROW_EN[1] = 0x0
4936 11:35:51.970850 LP4Y_EN = 0x0
4937 11:35:51.973957 WORK_FSP = 0x0
4938 11:35:51.974031 WL = 0x3
4939 11:35:51.977266 RL = 0x3
4940 11:35:51.977340 BL = 0x2
4941 11:35:51.980560 RPST = 0x0
4942 11:35:51.980635 RD_PRE = 0x0
4943 11:35:51.984345 WR_PRE = 0x1
4944 11:35:51.984419 WR_PST = 0x0
4945 11:35:51.987317 DBI_WR = 0x0
4946 11:35:51.987391 DBI_RD = 0x0
4947 11:35:51.990606 OTF = 0x1
4948 11:35:51.993809 ===================================
4949 11:35:51.997380 ===================================
4950 11:35:51.997454 ANA top config
4951 11:35:52.000862 ===================================
4952 11:35:52.003985 DLL_ASYNC_EN = 0
4953 11:35:52.007269 ALL_SLAVE_EN = 1
4954 11:35:52.011109 NEW_RANK_MODE = 1
4955 11:35:52.011184 DLL_IDLE_MODE = 1
4956 11:35:52.013893 LP45_APHY_COMB_EN = 1
4957 11:35:52.017282 TX_ODT_DIS = 1
4958 11:35:52.020786 NEW_8X_MODE = 1
4959 11:35:52.024099 ===================================
4960 11:35:52.027493 ===================================
4961 11:35:52.030914 data_rate = 1866
4962 11:35:52.030989 CKR = 1
4963 11:35:52.034163 DQ_P2S_RATIO = 8
4964 11:35:52.037268 ===================================
4965 11:35:52.040606 CA_P2S_RATIO = 8
4966 11:35:52.043903 DQ_CA_OPEN = 0
4967 11:35:52.047834 DQ_SEMI_OPEN = 0
4968 11:35:52.047908 CA_SEMI_OPEN = 0
4969 11:35:52.050626 CA_FULL_RATE = 0
4970 11:35:52.054491 DQ_CKDIV4_EN = 1
4971 11:35:52.057860 CA_CKDIV4_EN = 1
4972 11:35:52.060721 CA_PREDIV_EN = 0
4973 11:35:52.064331 PH8_DLY = 0
4974 11:35:52.064406 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4975 11:35:52.067725 DQ_AAMCK_DIV = 4
4976 11:35:52.070777 CA_AAMCK_DIV = 4
4977 11:35:52.074468 CA_ADMCK_DIV = 4
4978 11:35:52.077641 DQ_TRACK_CA_EN = 0
4979 11:35:52.081090 CA_PICK = 933
4980 11:35:52.081234 CA_MCKIO = 933
4981 11:35:52.084284 MCKIO_SEMI = 0
4982 11:35:52.087794 PLL_FREQ = 3732
4983 11:35:52.090768 DQ_UI_PI_RATIO = 32
4984 11:35:52.094284 CA_UI_PI_RATIO = 0
4985 11:35:52.097321 ===================================
4986 11:35:52.101093 ===================================
4987 11:35:52.103937 memory_type:LPDDR4
4988 11:35:52.104030 GP_NUM : 10
4989 11:35:52.107542 SRAM_EN : 1
4990 11:35:52.107635 MD32_EN : 0
4991 11:35:52.111058 ===================================
4992 11:35:52.114505 [ANA_INIT] >>>>>>>>>>>>>>
4993 11:35:52.117694 <<<<<< [CONFIGURE PHASE]: ANA_TX
4994 11:35:52.121023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4995 11:35:52.124753 ===================================
4996 11:35:52.127629 data_rate = 1866,PCW = 0X8f00
4997 11:35:52.131066 ===================================
4998 11:35:52.134129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4999 11:35:52.137632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 11:35:52.144184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 11:35:52.147719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5002 11:35:52.154406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5003 11:35:52.157848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5004 11:35:52.157926 [ANA_INIT] flow start
5005 11:35:52.161403 [ANA_INIT] PLL >>>>>>>>
5006 11:35:52.164134 [ANA_INIT] PLL <<<<<<<<
5007 11:35:52.164210 [ANA_INIT] MIDPI >>>>>>>>
5008 11:35:52.167782 [ANA_INIT] MIDPI <<<<<<<<
5009 11:35:52.170969 [ANA_INIT] DLL >>>>>>>>
5010 11:35:52.171046 [ANA_INIT] flow end
5011 11:35:52.174000 ============ LP4 DIFF to SE enter ============
5012 11:35:52.181142 ============ LP4 DIFF to SE exit ============
5013 11:35:52.181234 [ANA_INIT] <<<<<<<<<<<<<
5014 11:35:52.184477 [Flow] Enable top DCM control >>>>>
5015 11:35:52.187463 [Flow] Enable top DCM control <<<<<
5016 11:35:52.191453 Enable DLL master slave shuffle
5017 11:35:52.197915 ==============================================================
5018 11:35:52.197992 Gating Mode config
5019 11:35:52.204293 ==============================================================
5020 11:35:52.207703 Config description:
5021 11:35:52.217656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5022 11:35:52.224129 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5023 11:35:52.227595 SELPH_MODE 0: By rank 1: By Phase
5024 11:35:52.234391 ==============================================================
5025 11:35:52.237438 GAT_TRACK_EN = 1
5026 11:35:52.237519 RX_GATING_MODE = 2
5027 11:35:52.241103 RX_GATING_TRACK_MODE = 2
5028 11:35:52.244042 SELPH_MODE = 1
5029 11:35:52.247563 PICG_EARLY_EN = 1
5030 11:35:52.251264 VALID_LAT_VALUE = 1
5031 11:35:52.257559 ==============================================================
5032 11:35:52.260768 Enter into Gating configuration >>>>
5033 11:35:52.264201 Exit from Gating configuration <<<<
5034 11:35:52.267074 Enter into DVFS_PRE_config >>>>>
5035 11:35:52.277157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5036 11:35:52.280984 Exit from DVFS_PRE_config <<<<<
5037 11:35:52.284259 Enter into PICG configuration >>>>
5038 11:35:52.287106 Exit from PICG configuration <<<<
5039 11:35:52.290409 [RX_INPUT] configuration >>>>>
5040 11:35:52.293782 [RX_INPUT] configuration <<<<<
5041 11:35:52.297144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5042 11:35:52.304033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5043 11:35:52.310418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 11:35:52.317379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 11:35:52.320251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 11:35:52.326911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 11:35:52.330592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5048 11:35:52.337386 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5049 11:35:52.340200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5050 11:35:52.344426 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5051 11:35:52.347116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5052 11:35:52.353963 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 11:35:52.357439 ===================================
5054 11:35:52.357507 LPDDR4 DRAM CONFIGURATION
5055 11:35:52.360470 ===================================
5056 11:35:52.363523 EX_ROW_EN[0] = 0x0
5057 11:35:52.367221 EX_ROW_EN[1] = 0x0
5058 11:35:52.367307 LP4Y_EN = 0x0
5059 11:35:52.370426 WORK_FSP = 0x0
5060 11:35:52.370489 WL = 0x3
5061 11:35:52.373943 RL = 0x3
5062 11:35:52.374006 BL = 0x2
5063 11:35:52.377472 RPST = 0x0
5064 11:35:52.377537 RD_PRE = 0x0
5065 11:35:52.380747 WR_PRE = 0x1
5066 11:35:52.380829 WR_PST = 0x0
5067 11:35:52.383615 DBI_WR = 0x0
5068 11:35:52.383700 DBI_RD = 0x0
5069 11:35:52.387211 OTF = 0x1
5070 11:35:52.390445 ===================================
5071 11:35:52.394105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5072 11:35:52.397451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5073 11:35:52.400670 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 11:35:52.403834 ===================================
5075 11:35:52.407146 LPDDR4 DRAM CONFIGURATION
5076 11:35:52.410359 ===================================
5077 11:35:52.414085 EX_ROW_EN[0] = 0x10
5078 11:35:52.414174 EX_ROW_EN[1] = 0x0
5079 11:35:52.417391 LP4Y_EN = 0x0
5080 11:35:52.417457 WORK_FSP = 0x0
5081 11:35:52.420455 WL = 0x3
5082 11:35:52.420541 RL = 0x3
5083 11:35:52.423629 BL = 0x2
5084 11:35:52.423713 RPST = 0x0
5085 11:35:52.427175 RD_PRE = 0x0
5086 11:35:52.430263 WR_PRE = 0x1
5087 11:35:52.430326 WR_PST = 0x0
5088 11:35:52.433673 DBI_WR = 0x0
5089 11:35:52.433738 DBI_RD = 0x0
5090 11:35:52.437072 OTF = 0x1
5091 11:35:52.440201 ===================================
5092 11:35:52.443917 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5093 11:35:52.448981 nWR fixed to 30
5094 11:35:52.452179 [ModeRegInit_LP4] CH0 RK0
5095 11:35:52.452256 [ModeRegInit_LP4] CH0 RK1
5096 11:35:52.455578 [ModeRegInit_LP4] CH1 RK0
5097 11:35:52.459107 [ModeRegInit_LP4] CH1 RK1
5098 11:35:52.459172 match AC timing 9
5099 11:35:52.466244 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5100 11:35:52.468936 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5101 11:35:52.472451 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5102 11:35:52.479308 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5103 11:35:52.482634 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5104 11:35:52.482703 ==
5105 11:35:52.486387 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 11:35:52.489395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 11:35:52.489475 ==
5108 11:35:52.495883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 11:35:52.502206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5110 11:35:52.505861 [CA 0] Center 38 (8~69) winsize 62
5111 11:35:52.509084 [CA 1] Center 38 (8~69) winsize 62
5112 11:35:52.512590 [CA 2] Center 35 (5~66) winsize 62
5113 11:35:52.515644 [CA 3] Center 35 (4~66) winsize 63
5114 11:35:52.518974 [CA 4] Center 34 (4~64) winsize 61
5115 11:35:52.522420 [CA 5] Center 34 (4~64) winsize 61
5116 11:35:52.522508
5117 11:35:52.525864 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5118 11:35:52.525950
5119 11:35:52.529067 [CATrainingPosCal] consider 1 rank data
5120 11:35:52.532953 u2DelayCellTimex100 = 270/100 ps
5121 11:35:52.535761 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5122 11:35:52.539395 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 11:35:52.542450 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5124 11:35:52.546234 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5125 11:35:52.549100 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5126 11:35:52.552433 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5127 11:35:52.552499
5128 11:35:52.555802 CA PerBit enable=1, Macro0, CA PI delay=34
5129 11:35:52.559245
5130 11:35:52.559308 [CBTSetCACLKResult] CA Dly = 34
5131 11:35:52.562373 CS Dly: 6 (0~37)
5132 11:35:52.562454 ==
5133 11:35:52.566127 Dram Type= 6, Freq= 0, CH_0, rank 1
5134 11:35:52.569358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 11:35:52.569435 ==
5136 11:35:52.575980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 11:35:52.582627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5138 11:35:52.585716 [CA 0] Center 38 (7~69) winsize 63
5139 11:35:52.589084 [CA 1] Center 38 (7~69) winsize 63
5140 11:35:52.592473 [CA 2] Center 35 (5~66) winsize 62
5141 11:35:52.595998 [CA 3] Center 35 (5~66) winsize 62
5142 11:35:52.599069 [CA 4] Center 34 (3~65) winsize 63
5143 11:35:52.602736 [CA 5] Center 33 (3~64) winsize 62
5144 11:35:52.602813
5145 11:35:52.605972 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5146 11:35:52.606049
5147 11:35:52.609304 [CATrainingPosCal] consider 2 rank data
5148 11:35:52.612378 u2DelayCellTimex100 = 270/100 ps
5149 11:35:52.615847 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5150 11:35:52.618928 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 11:35:52.622486 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5152 11:35:52.625663 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5153 11:35:52.629245 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5154 11:35:52.632355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5155 11:35:52.632432
5156 11:35:52.635954 CA PerBit enable=1, Macro0, CA PI delay=34
5157 11:35:52.639327
5158 11:35:52.639403 [CBTSetCACLKResult] CA Dly = 34
5159 11:35:52.642575 CS Dly: 7 (0~39)
5160 11:35:52.642651
5161 11:35:52.646393 ----->DramcWriteLeveling(PI) begin...
5162 11:35:52.646471 ==
5163 11:35:52.649120 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 11:35:52.652454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 11:35:52.652531 ==
5166 11:35:52.655635 Write leveling (Byte 0): 33 => 33
5167 11:35:52.659280 Write leveling (Byte 1): 28 => 28
5168 11:35:52.662706 DramcWriteLeveling(PI) end<-----
5169 11:35:52.662782
5170 11:35:52.662858 ==
5171 11:35:52.665766 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:35:52.668971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:35:52.669048 ==
5174 11:35:52.672112 [Gating] SW mode calibration
5175 11:35:52.679399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5176 11:35:52.685844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5177 11:35:52.689383 0 14 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5178 11:35:52.695759 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5179 11:35:52.698846 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 11:35:52.702490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:35:52.709174 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:35:52.712446 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:35:52.715546 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:35:52.722340 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5185 11:35:52.725656 0 15 0 | B1->B0 | 3030 2a2a | 1 1 | (1 0) (1 0)
5186 11:35:52.729001 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5187 11:35:52.732809 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 11:35:52.738997 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:35:52.742135 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:35:52.745349 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:35:52.752109 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:35:52.755755 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:35:52.758962 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
5194 11:35:52.765546 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:35:52.769053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:35:52.772240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:35:52.779227 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:35:52.782411 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:35:52.785542 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:35:52.792030 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5201 11:35:52.795818 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5202 11:35:52.799009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5203 11:35:52.805339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:35:52.808914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:35:52.812110 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:35:52.818796 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:35:52.822213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:35:52.825857 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:35:52.828806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:35:52.835406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:35:52.838864 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:35:52.842229 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:35:52.849236 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:35:52.852472 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:35:52.855676 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:35:52.862565 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:35:52.865760 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5218 11:35:52.868837 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 11:35:52.872074 Total UI for P1: 0, mck2ui 16
5220 11:35:52.875340 best dqsien dly found for B0: ( 1, 3, 0)
5221 11:35:52.879093 Total UI for P1: 0, mck2ui 16
5222 11:35:52.882427 best dqsien dly found for B1: ( 1, 3, 0)
5223 11:35:52.885745 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5224 11:35:52.889307 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5225 11:35:52.889381
5226 11:35:52.892328 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5227 11:35:52.899318 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5228 11:35:52.899393 [Gating] SW calibration Done
5229 11:35:52.899451 ==
5230 11:35:52.902250 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 11:35:52.909105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 11:35:52.909220 ==
5233 11:35:52.909279 RX Vref Scan: 0
5234 11:35:52.909333
5235 11:35:52.912555 RX Vref 0 -> 0, step: 1
5236 11:35:52.912629
5237 11:35:52.916061 RX Delay -80 -> 252, step: 8
5238 11:35:52.919445 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5239 11:35:52.922768 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5240 11:35:52.926053 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5241 11:35:52.929708 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5242 11:35:52.932570 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5243 11:35:52.939042 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5244 11:35:52.942941 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5245 11:35:52.946061 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5246 11:35:52.949168 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5247 11:35:52.952614 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5248 11:35:52.955739 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5249 11:35:52.962296 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5250 11:35:52.965623 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5251 11:35:52.969320 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5252 11:35:52.972691 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5253 11:35:52.975656 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5254 11:35:52.979524 ==
5255 11:35:52.979599 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 11:35:52.986050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 11:35:52.986125 ==
5258 11:35:52.986182 DQS Delay:
5259 11:35:52.988871 DQS0 = 0, DQS1 = 0
5260 11:35:52.988945 DQM Delay:
5261 11:35:52.992221 DQM0 = 98, DQM1 = 86
5262 11:35:52.992294 DQ Delay:
5263 11:35:52.995833 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5264 11:35:52.998865 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5265 11:35:53.002128 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5266 11:35:53.005559 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5267 11:35:53.005633
5268 11:35:53.005690
5269 11:35:53.005743 ==
5270 11:35:53.009067 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:35:53.012052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:35:53.012126 ==
5273 11:35:53.012184
5274 11:35:53.012236
5275 11:35:53.015736 TX Vref Scan disable
5276 11:35:53.019331 == TX Byte 0 ==
5277 11:35:53.022347 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5278 11:35:53.026004 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5279 11:35:53.028920 == TX Byte 1 ==
5280 11:35:53.032287 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5281 11:35:53.035853 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5282 11:35:53.035927 ==
5283 11:35:53.039095 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:35:53.045323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:35:53.045402 ==
5286 11:35:53.045460
5287 11:35:53.045513
5288 11:35:53.045564 TX Vref Scan disable
5289 11:35:53.049596 == TX Byte 0 ==
5290 11:35:53.053288 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5291 11:35:53.056482 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5292 11:35:53.059392 == TX Byte 1 ==
5293 11:35:53.062547 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5294 11:35:53.066627 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5295 11:35:53.069446
5296 11:35:53.069548 [DATLAT]
5297 11:35:53.069635 Freq=933, CH0 RK0
5298 11:35:53.069717
5299 11:35:53.072725 DATLAT Default: 0xd
5300 11:35:53.072798 0, 0xFFFF, sum = 0
5301 11:35:53.076058 1, 0xFFFF, sum = 0
5302 11:35:53.076133 2, 0xFFFF, sum = 0
5303 11:35:53.079392 3, 0xFFFF, sum = 0
5304 11:35:53.079497 4, 0xFFFF, sum = 0
5305 11:35:53.083159 5, 0xFFFF, sum = 0
5306 11:35:53.083234 6, 0xFFFF, sum = 0
5307 11:35:53.086148 7, 0xFFFF, sum = 0
5308 11:35:53.089858 8, 0xFFFF, sum = 0
5309 11:35:53.089933 9, 0xFFFF, sum = 0
5310 11:35:53.089992 10, 0x0, sum = 1
5311 11:35:53.092725 11, 0x0, sum = 2
5312 11:35:53.092800 12, 0x0, sum = 3
5313 11:35:53.096077 13, 0x0, sum = 4
5314 11:35:53.096152 best_step = 11
5315 11:35:53.096210
5316 11:35:53.096263 ==
5317 11:35:53.099869 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 11:35:53.106739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 11:35:53.106813 ==
5320 11:35:53.106872 RX Vref Scan: 1
5321 11:35:53.106926
5322 11:35:53.109413 RX Vref 0 -> 0, step: 1
5323 11:35:53.109487
5324 11:35:53.112684 RX Delay -69 -> 252, step: 4
5325 11:35:53.112757
5326 11:35:53.117052 Set Vref, RX VrefLevel [Byte0]: 54
5327 11:35:53.119619 [Byte1]: 51
5328 11:35:53.119693
5329 11:35:53.122758 Final RX Vref Byte 0 = 54 to rank0
5330 11:35:53.126488 Final RX Vref Byte 1 = 51 to rank0
5331 11:35:53.129656 Final RX Vref Byte 0 = 54 to rank1
5332 11:35:53.133149 Final RX Vref Byte 1 = 51 to rank1==
5333 11:35:53.136169 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 11:35:53.139758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 11:35:53.139833 ==
5336 11:35:53.143241 DQS Delay:
5337 11:35:53.143315 DQS0 = 0, DQS1 = 0
5338 11:35:53.146403 DQM Delay:
5339 11:35:53.146476 DQM0 = 97, DQM1 = 88
5340 11:35:53.146534 DQ Delay:
5341 11:35:53.149954 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5342 11:35:53.152945 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5343 11:35:53.156180 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5344 11:35:53.159540 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5345 11:35:53.159644
5346 11:35:53.159749
5347 11:35:53.169918 [DQSOSCAuto] RK0, (LSB)MR18= 0x1804, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5348 11:35:53.173359 CH0 RK0: MR19=505, MR18=1804
5349 11:35:53.176374 CH0_RK0: MR19=0x505, MR18=0x1804, DQSOSC=414, MR23=63, INC=63, DEC=42
5350 11:35:53.176474
5351 11:35:53.179727 ----->DramcWriteLeveling(PI) begin...
5352 11:35:53.183065 ==
5353 11:35:53.186282 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 11:35:53.190389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 11:35:53.190525 ==
5356 11:35:53.192753 Write leveling (Byte 0): 31 => 31
5357 11:35:53.196151 Write leveling (Byte 1): 30 => 30
5358 11:35:53.199540 DramcWriteLeveling(PI) end<-----
5359 11:35:53.199718
5360 11:35:53.199859 ==
5361 11:35:53.203017 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 11:35:53.206866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 11:35:53.207136 ==
5364 11:35:53.209679 [Gating] SW mode calibration
5365 11:35:53.216558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5366 11:35:53.220156 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5367 11:35:53.226444 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
5368 11:35:53.229993 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5369 11:35:53.233629 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:35:53.240212 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:35:53.243356 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:35:53.246872 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 11:35:53.253176 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 11:35:53.257153 0 14 28 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 0)
5375 11:35:53.259724 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5376 11:35:53.267119 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:35:53.269930 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:35:53.273541 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:35:53.280193 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:35:53.283328 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 11:35:53.287442 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 11:35:53.293548 0 15 28 | B1->B0 | 2525 2f2f | 1 0 | (0 0) (0 0)
5383 11:35:53.296568 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5384 11:35:53.299864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:35:53.306833 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:35:53.310250 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:35:53.313110 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:35:53.317046 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:35:53.323245 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5390 11:35:53.327079 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5391 11:35:53.330407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 11:35:53.336526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 11:35:53.340411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:35:53.344085 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:35:53.350172 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:35:53.353964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:35:53.357047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:35:53.363139 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:35:53.366517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:35:53.370105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:35:53.376350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:35:53.379763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:35:53.383043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:35:53.386777 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:35:53.393528 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5406 11:35:53.396969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5407 11:35:53.399888 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5408 11:35:53.403387 Total UI for P1: 0, mck2ui 16
5409 11:35:53.406307 best dqsien dly found for B0: ( 1, 2, 26)
5410 11:35:53.413081 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5411 11:35:53.416985 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 11:35:53.419735 Total UI for P1: 0, mck2ui 16
5413 11:35:53.422989 best dqsien dly found for B1: ( 1, 3, 2)
5414 11:35:53.426635 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5415 11:35:53.429700 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5416 11:35:53.429773
5417 11:35:53.433455 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 11:35:53.436633 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5419 11:35:53.439994 [Gating] SW calibration Done
5420 11:35:53.440067 ==
5421 11:35:53.443259 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:35:53.446793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:35:53.450196 ==
5424 11:35:53.450270 RX Vref Scan: 0
5425 11:35:53.450334
5426 11:35:53.453129 RX Vref 0 -> 0, step: 1
5427 11:35:53.453203
5428 11:35:53.456418 RX Delay -80 -> 252, step: 8
5429 11:35:53.460481 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5430 11:35:53.462983 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5431 11:35:53.466711 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5432 11:35:53.470312 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5433 11:35:53.473766 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5434 11:35:53.480220 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5435 11:35:53.483344 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5436 11:35:53.486514 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5437 11:35:53.489845 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5438 11:35:53.493693 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5439 11:35:53.496523 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5440 11:35:53.503343 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5441 11:35:53.506594 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5442 11:35:53.509773 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5443 11:35:53.513172 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5444 11:35:53.516772 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5445 11:35:53.516846 ==
5446 11:35:53.519801 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:35:53.526413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:35:53.526487 ==
5449 11:35:53.526545 DQS Delay:
5450 11:35:53.526598 DQS0 = 0, DQS1 = 0
5451 11:35:53.529866 DQM Delay:
5452 11:35:53.529939 DQM0 = 98, DQM1 = 87
5453 11:35:53.532879 DQ Delay:
5454 11:35:53.536356 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5455 11:35:53.539913 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5456 11:35:53.543546 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5457 11:35:53.546206 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5458 11:35:53.546280
5459 11:35:53.546336
5460 11:35:53.546389 ==
5461 11:35:53.549972 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:35:53.553346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:35:53.553420 ==
5464 11:35:53.553477
5465 11:35:53.553529
5466 11:35:53.556614 TX Vref Scan disable
5467 11:35:53.556705 == TX Byte 0 ==
5468 11:35:53.563148 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5469 11:35:53.566428 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5470 11:35:53.566501 == TX Byte 1 ==
5471 11:35:53.573337 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5472 11:35:53.576840 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5473 11:35:53.576913 ==
5474 11:35:53.579767 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:35:53.583305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:35:53.583379 ==
5477 11:35:53.583436
5478 11:35:53.583488
5479 11:35:53.586599 TX Vref Scan disable
5480 11:35:53.590254 == TX Byte 0 ==
5481 11:35:53.593422 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5482 11:35:53.596581 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5483 11:35:53.600230 == TX Byte 1 ==
5484 11:35:53.603353 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5485 11:35:53.606501 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5486 11:35:53.606574
5487 11:35:53.610459 [DATLAT]
5488 11:35:53.610532 Freq=933, CH0 RK1
5489 11:35:53.610590
5490 11:35:53.613631 DATLAT Default: 0xb
5491 11:35:53.613704 0, 0xFFFF, sum = 0
5492 11:35:53.617078 1, 0xFFFF, sum = 0
5493 11:35:53.617189 2, 0xFFFF, sum = 0
5494 11:35:53.619976 3, 0xFFFF, sum = 0
5495 11:35:53.620051 4, 0xFFFF, sum = 0
5496 11:35:53.623573 5, 0xFFFF, sum = 0
5497 11:35:53.623648 6, 0xFFFF, sum = 0
5498 11:35:53.626692 7, 0xFFFF, sum = 0
5499 11:35:53.626767 8, 0xFFFF, sum = 0
5500 11:35:53.630362 9, 0xFFFF, sum = 0
5501 11:35:53.630436 10, 0x0, sum = 1
5502 11:35:53.633228 11, 0x0, sum = 2
5503 11:35:53.633303 12, 0x0, sum = 3
5504 11:35:53.636721 13, 0x0, sum = 4
5505 11:35:53.636820 best_step = 11
5506 11:35:53.636902
5507 11:35:53.636982 ==
5508 11:35:53.640206 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 11:35:53.643147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 11:35:53.646747 ==
5511 11:35:53.646821 RX Vref Scan: 0
5512 11:35:53.646878
5513 11:35:53.649922 RX Vref 0 -> 0, step: 1
5514 11:35:53.649995
5515 11:35:53.653042 RX Delay -61 -> 252, step: 4
5516 11:35:53.656820 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5517 11:35:53.659854 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5518 11:35:53.663515 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5519 11:35:53.670392 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5520 11:35:53.673696 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5521 11:35:53.676593 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5522 11:35:53.680286 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5523 11:35:53.683749 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5524 11:35:53.686874 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5525 11:35:53.693548 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5526 11:35:53.696947 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5527 11:35:53.699793 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5528 11:35:53.703357 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5529 11:35:53.706454 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5530 11:35:53.710048 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5531 11:35:53.716771 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5532 11:35:53.716844 ==
5533 11:35:53.719949 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 11:35:53.723551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 11:35:53.723625 ==
5536 11:35:53.723682 DQS Delay:
5537 11:35:53.726856 DQS0 = 0, DQS1 = 0
5538 11:35:53.726928 DQM Delay:
5539 11:35:53.730367 DQM0 = 95, DQM1 = 87
5540 11:35:53.730440 DQ Delay:
5541 11:35:53.733730 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5542 11:35:53.737020 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5543 11:35:53.740219 DQ8 =80, DQ9 =80, DQ10 =86, DQ11 =78
5544 11:35:53.743533 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5545 11:35:53.743606
5546 11:35:53.743664
5547 11:35:53.750280 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5548 11:35:53.753398 CH0 RK1: MR19=505, MR18=1906
5549 11:35:53.760329 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5550 11:35:53.763405 [RxdqsGatingPostProcess] freq 933
5551 11:35:53.770457 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 11:35:53.773354 best DQS0 dly(2T, 0.5T) = (0, 11)
5553 11:35:53.773429 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 11:35:53.777016 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5555 11:35:53.780387 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 11:35:53.783697 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 11:35:53.787009 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 11:35:53.790102 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 11:35:53.793659 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 11:35:53.796627 Pre-setting of DQS Precalculation
5561 11:35:53.803428 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 11:35:53.803502 ==
5563 11:35:53.806819 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 11:35:53.810444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 11:35:53.810518 ==
5566 11:35:53.817050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 11:35:53.820226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 11:35:53.824474 [CA 0] Center 36 (6~67) winsize 62
5569 11:35:53.827494 [CA 1] Center 36 (6~67) winsize 62
5570 11:35:53.830618 [CA 2] Center 34 (4~64) winsize 61
5571 11:35:53.833885 [CA 3] Center 33 (3~64) winsize 62
5572 11:35:53.837342 [CA 4] Center 34 (4~64) winsize 61
5573 11:35:53.840757 [CA 5] Center 33 (3~63) winsize 61
5574 11:35:53.840830
5575 11:35:53.844345 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 11:35:53.844419
5577 11:35:53.847893 [CATrainingPosCal] consider 1 rank data
5578 11:35:53.851129 u2DelayCellTimex100 = 270/100 ps
5579 11:35:53.853971 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 11:35:53.857261 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 11:35:53.864163 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5582 11:35:53.867356 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 11:35:53.870699 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 11:35:53.874083 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5585 11:35:53.874156
5586 11:35:53.877248 CA PerBit enable=1, Macro0, CA PI delay=33
5587 11:35:53.877322
5588 11:35:53.880632 [CBTSetCACLKResult] CA Dly = 33
5589 11:35:53.880706 CS Dly: 4 (0~35)
5590 11:35:53.880763 ==
5591 11:35:53.883909 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 11:35:53.890869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:35:53.890943 ==
5594 11:35:53.893978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 11:35:53.901258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 11:35:53.904450 [CA 0] Center 36 (6~67) winsize 62
5597 11:35:53.907487 [CA 1] Center 36 (6~67) winsize 62
5598 11:35:53.910818 [CA 2] Center 33 (3~64) winsize 62
5599 11:35:53.914170 [CA 3] Center 33 (3~64) winsize 62
5600 11:35:53.917536 [CA 4] Center 33 (3~64) winsize 62
5601 11:35:53.920925 [CA 5] Center 33 (3~63) winsize 61
5602 11:35:53.920999
5603 11:35:53.924219 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 11:35:53.924292
5605 11:35:53.927564 [CATrainingPosCal] consider 2 rank data
5606 11:35:53.931215 u2DelayCellTimex100 = 270/100 ps
5607 11:35:53.934385 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 11:35:53.937689 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 11:35:53.941054 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5610 11:35:53.947575 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 11:35:53.951161 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 11:35:53.954046 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5613 11:35:53.954120
5614 11:35:53.957459 CA PerBit enable=1, Macro0, CA PI delay=33
5615 11:35:53.957533
5616 11:35:53.960661 [CBTSetCACLKResult] CA Dly = 33
5617 11:35:53.960734 CS Dly: 5 (0~37)
5618 11:35:53.960791
5619 11:35:53.964234 ----->DramcWriteLeveling(PI) begin...
5620 11:35:53.964308 ==
5621 11:35:53.967376 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:35:53.974197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:35:53.974271 ==
5624 11:35:53.977552 Write leveling (Byte 0): 26 => 26
5625 11:35:53.980747 Write leveling (Byte 1): 27 => 27
5626 11:35:53.980820 DramcWriteLeveling(PI) end<-----
5627 11:35:53.984330
5628 11:35:53.984403 ==
5629 11:35:53.987368 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:35:53.991170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:35:53.991244 ==
5632 11:35:53.994288 [Gating] SW mode calibration
5633 11:35:54.000732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 11:35:54.004217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 11:35:54.011021 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5636 11:35:54.014796 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:35:54.017423 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:35:54.024197 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 11:35:54.027178 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 11:35:54.030630 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 11:35:54.037315 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 11:35:54.040908 0 14 28 | B1->B0 | 3131 3030 | 0 0 | (1 1) (0 1)
5643 11:35:54.044155 0 15 0 | B1->B0 | 2828 2828 | 0 0 | (1 1) (0 0)
5644 11:35:54.050765 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:35:54.054104 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:35:54.057618 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 11:35:54.063990 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:35:54.067392 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 11:35:54.070632 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 11:35:54.078062 0 15 28 | B1->B0 | 2928 2727 | 1 0 | (0 0) (0 0)
5651 11:35:54.080875 1 0 0 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
5652 11:35:54.083887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:35:54.087382 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:35:54.094435 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:35:54.097682 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 11:35:54.101027 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 11:35:54.107205 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:35:54.111005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 11:35:54.114360 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5660 11:35:54.120438 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:35:54.123864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:35:54.127118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:35:54.133905 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:35:54.137420 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:35:54.140698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:35:54.147991 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:35:54.150583 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:35:54.153767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:35:54.160820 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:35:54.164729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:35:54.167809 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:35:54.174046 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:35:54.177169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5674 11:35:54.180362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 11:35:54.184239 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 11:35:54.187360 Total UI for P1: 0, mck2ui 16
5677 11:35:54.190671 best dqsien dly found for B0: ( 1, 2, 26)
5678 11:35:54.194249 Total UI for P1: 0, mck2ui 16
5679 11:35:54.197654 best dqsien dly found for B1: ( 1, 2, 26)
5680 11:35:54.200846 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5681 11:35:54.204279 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5682 11:35:54.207429
5683 11:35:54.210658 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 11:35:54.214314 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5685 11:35:54.217631 [Gating] SW calibration Done
5686 11:35:54.217705 ==
5687 11:35:54.220900 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 11:35:54.223935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 11:35:54.224009 ==
5690 11:35:54.224066 RX Vref Scan: 0
5691 11:35:54.224119
5692 11:35:54.227329 RX Vref 0 -> 0, step: 1
5693 11:35:54.227402
5694 11:35:54.231318 RX Delay -80 -> 252, step: 8
5695 11:35:54.234463 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5696 11:35:54.237167 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5697 11:35:54.241067 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5698 11:35:54.247389 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5699 11:35:54.250947 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5700 11:35:54.253852 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5701 11:35:54.257484 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5702 11:35:54.260866 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5703 11:35:54.264581 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5704 11:35:54.270531 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5705 11:35:54.274367 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5706 11:35:54.277354 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5707 11:35:54.280862 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5708 11:35:54.284027 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5709 11:35:54.290795 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5710 11:35:54.294131 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5711 11:35:54.294222 ==
5712 11:35:54.297746 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:35:54.300735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:35:54.300834 ==
5715 11:35:54.300918 DQS Delay:
5716 11:35:54.304043 DQS0 = 0, DQS1 = 0
5717 11:35:54.304116 DQM Delay:
5718 11:35:54.307911 DQM0 = 96, DQM1 = 88
5719 11:35:54.307984 DQ Delay:
5720 11:35:54.310857 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5721 11:35:54.314227 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5722 11:35:54.317469 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5723 11:35:54.321331 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5724 11:35:54.321405
5725 11:35:54.321461
5726 11:35:54.321515 ==
5727 11:35:54.324308 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 11:35:54.327970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 11:35:54.328046 ==
5730 11:35:54.330635
5731 11:35:54.330708
5732 11:35:54.330765 TX Vref Scan disable
5733 11:35:54.334081 == TX Byte 0 ==
5734 11:35:54.338019 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5735 11:35:54.341003 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5736 11:35:54.344164 == TX Byte 1 ==
5737 11:35:54.347597 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5738 11:35:54.350639 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5739 11:35:54.350713 ==
5740 11:35:54.354476 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 11:35:54.360894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:35:54.360968 ==
5743 11:35:54.361026
5744 11:35:54.361079
5745 11:35:54.361156 TX Vref Scan disable
5746 11:35:54.365174 == TX Byte 0 ==
5747 11:35:54.368394 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5748 11:35:54.375559 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5749 11:35:54.375633 == TX Byte 1 ==
5750 11:35:54.378463 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5751 11:35:54.385054 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5752 11:35:54.385155
5753 11:35:54.385252 [DATLAT]
5754 11:35:54.385322 Freq=933, CH1 RK0
5755 11:35:54.385376
5756 11:35:54.388470 DATLAT Default: 0xd
5757 11:35:54.388543 0, 0xFFFF, sum = 0
5758 11:35:54.392307 1, 0xFFFF, sum = 0
5759 11:35:54.392382 2, 0xFFFF, sum = 0
5760 11:35:54.395754 3, 0xFFFF, sum = 0
5761 11:35:54.395828 4, 0xFFFF, sum = 0
5762 11:35:54.398305 5, 0xFFFF, sum = 0
5763 11:35:54.401788 6, 0xFFFF, sum = 0
5764 11:35:54.401864 7, 0xFFFF, sum = 0
5765 11:35:54.405279 8, 0xFFFF, sum = 0
5766 11:35:54.405353 9, 0xFFFF, sum = 0
5767 11:35:54.405411 10, 0x0, sum = 1
5768 11:35:54.409385 11, 0x0, sum = 2
5769 11:35:54.409460 12, 0x0, sum = 3
5770 11:35:54.411748 13, 0x0, sum = 4
5771 11:35:54.411822 best_step = 11
5772 11:35:54.411879
5773 11:35:54.411932 ==
5774 11:35:54.415650 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 11:35:54.422005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 11:35:54.422137 ==
5777 11:35:54.422213 RX Vref Scan: 1
5778 11:35:54.422267
5779 11:35:54.425120 RX Vref 0 -> 0, step: 1
5780 11:35:54.425233
5781 11:35:54.428337 RX Delay -69 -> 252, step: 4
5782 11:35:54.428411
5783 11:35:54.431982 Set Vref, RX VrefLevel [Byte0]: 57
5784 11:35:54.435065 [Byte1]: 47
5785 11:35:54.435139
5786 11:35:54.438411 Final RX Vref Byte 0 = 57 to rank0
5787 11:35:54.441698 Final RX Vref Byte 1 = 47 to rank0
5788 11:35:54.445390 Final RX Vref Byte 0 = 57 to rank1
5789 11:35:54.448691 Final RX Vref Byte 1 = 47 to rank1==
5790 11:35:54.451574 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 11:35:54.455166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 11:35:54.455239 ==
5793 11:35:54.458679 DQS Delay:
5794 11:35:54.458751 DQS0 = 0, DQS1 = 0
5795 11:35:54.461497 DQM Delay:
5796 11:35:54.461570 DQM0 = 97, DQM1 = 89
5797 11:35:54.461628 DQ Delay:
5798 11:35:54.464932 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5799 11:35:54.468316 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5800 11:35:54.471681 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =84
5801 11:35:54.475523 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =94
5802 11:35:54.475596
5803 11:35:54.475653
5804 11:35:54.485093 [DQSOSCAuto] RK0, (LSB)MR18= 0x18f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5805 11:35:54.488486 CH1 RK0: MR19=504, MR18=18F4
5806 11:35:54.494874 CH1_RK0: MR19=0x504, MR18=0x18F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5807 11:35:54.494948
5808 11:35:54.497991 ----->DramcWriteLeveling(PI) begin...
5809 11:35:54.498065 ==
5810 11:35:54.501414 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 11:35:54.505037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 11:35:54.505168 ==
5813 11:35:54.508527 Write leveling (Byte 0): 29 => 29
5814 11:35:54.511296 Write leveling (Byte 1): 29 => 29
5815 11:35:54.514842 DramcWriteLeveling(PI) end<-----
5816 11:35:54.514915
5817 11:35:54.514972 ==
5818 11:35:54.518413 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 11:35:54.521362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 11:35:54.521436 ==
5821 11:35:54.524793 [Gating] SW mode calibration
5822 11:35:54.531290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 11:35:54.537892 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 11:35:54.541536 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:35:54.544878 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5826 11:35:54.551522 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:35:54.554649 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 11:35:54.557715 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 11:35:54.564641 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 11:35:54.568496 0 14 24 | B1->B0 | 3232 3030 | 1 1 | (0 0) (0 1)
5831 11:35:54.571291 0 14 28 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
5832 11:35:54.578352 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:35:54.581446 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:35:54.584730 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:35:54.590975 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 11:35:54.594526 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 11:35:54.597873 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 11:35:54.604578 0 15 24 | B1->B0 | 2727 3232 | 1 1 | (0 0) (0 0)
5839 11:35:54.607739 0 15 28 | B1->B0 | 4141 4545 | 1 0 | (0 0) (0 0)
5840 11:35:54.611145 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:35:54.618124 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:35:54.621227 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:35:54.624227 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:35:54.627956 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 11:35:54.634454 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 11:35:54.637965 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5847 11:35:54.641331 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5848 11:35:54.648141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:35:54.651095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:35:54.654489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:35:54.661364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:35:54.664768 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:35:54.667901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:35:54.674473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:35:54.677744 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:35:54.681010 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:35:54.687713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:35:54.691186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:35:54.694808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:35:54.698313 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:35:54.704628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:35:54.707981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 11:35:54.711513 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5864 11:35:54.714785 Total UI for P1: 0, mck2ui 16
5865 11:35:54.717789 best dqsien dly found for B0: ( 1, 2, 24)
5866 11:35:54.724984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5867 11:35:54.727839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 11:35:54.731491 Total UI for P1: 0, mck2ui 16
5869 11:35:54.734914 best dqsien dly found for B1: ( 1, 2, 30)
5870 11:35:54.738068 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 11:35:54.741315 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5872 11:35:54.741388
5873 11:35:54.744827 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 11:35:54.748333 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5875 11:35:54.752098 [Gating] SW calibration Done
5876 11:35:54.752171 ==
5877 11:35:54.754522 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 11:35:54.758418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 11:35:54.761305 ==
5880 11:35:54.761379 RX Vref Scan: 0
5881 11:35:54.761438
5882 11:35:54.764689 RX Vref 0 -> 0, step: 1
5883 11:35:54.764762
5884 11:35:54.764820 RX Delay -80 -> 252, step: 8
5885 11:35:54.771572 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5886 11:35:54.775249 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5887 11:35:54.778456 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5888 11:35:54.781939 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5889 11:35:54.785192 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5890 11:35:54.788178 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5891 11:35:54.794759 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5892 11:35:54.798234 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5893 11:35:54.801523 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5894 11:35:54.805333 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5895 11:35:54.808018 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5896 11:35:54.811615 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5897 11:35:54.818090 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5898 11:35:54.821824 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5899 11:35:54.825295 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5900 11:35:54.828320 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5901 11:35:54.828394 ==
5902 11:35:54.831484 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 11:35:54.835195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 11:35:54.838473 ==
5905 11:35:54.838546 DQS Delay:
5906 11:35:54.838605 DQS0 = 0, DQS1 = 0
5907 11:35:54.841573 DQM Delay:
5908 11:35:54.841646 DQM0 = 94, DQM1 = 88
5909 11:35:54.844707 DQ Delay:
5910 11:35:54.844780 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5911 11:35:54.848501 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5912 11:35:54.851561 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5913 11:35:54.855188 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5914 11:35:54.858385
5915 11:35:54.858457
5916 11:35:54.858514 ==
5917 11:35:54.861656 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 11:35:54.864994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 11:35:54.865068 ==
5920 11:35:54.865148
5921 11:35:54.865214
5922 11:35:54.868057 TX Vref Scan disable
5923 11:35:54.868130 == TX Byte 0 ==
5924 11:35:54.875168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5925 11:35:54.878502 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5926 11:35:54.878576 == TX Byte 1 ==
5927 11:35:54.884864 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5928 11:35:54.888614 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5929 11:35:54.888687 ==
5930 11:35:54.891611 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 11:35:54.894986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 11:35:54.895059 ==
5933 11:35:54.895117
5934 11:35:54.895170
5935 11:35:54.898615 TX Vref Scan disable
5936 11:35:54.901968 == TX Byte 0 ==
5937 11:35:54.905398 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5938 11:35:54.908415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5939 11:35:54.912020 == TX Byte 1 ==
5940 11:35:54.915025 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5941 11:35:54.918669 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5942 11:35:54.918743
5943 11:35:54.918833 [DATLAT]
5944 11:35:54.921655 Freq=933, CH1 RK1
5945 11:35:54.921729
5946 11:35:54.925347 DATLAT Default: 0xb
5947 11:35:54.925419 0, 0xFFFF, sum = 0
5948 11:35:54.928540 1, 0xFFFF, sum = 0
5949 11:35:54.928615 2, 0xFFFF, sum = 0
5950 11:35:54.931829 3, 0xFFFF, sum = 0
5951 11:35:54.931904 4, 0xFFFF, sum = 0
5952 11:35:54.934864 5, 0xFFFF, sum = 0
5953 11:35:54.934939 6, 0xFFFF, sum = 0
5954 11:35:54.938557 7, 0xFFFF, sum = 0
5955 11:35:54.938631 8, 0xFFFF, sum = 0
5956 11:35:54.942257 9, 0xFFFF, sum = 0
5957 11:35:54.942331 10, 0x0, sum = 1
5958 11:35:54.945264 11, 0x0, sum = 2
5959 11:35:54.945340 12, 0x0, sum = 3
5960 11:35:54.948272 13, 0x0, sum = 4
5961 11:35:54.948346 best_step = 11
5962 11:35:54.948403
5963 11:35:54.948455 ==
5964 11:35:54.952180 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 11:35:54.955080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 11:35:54.955155 ==
5967 11:35:54.958698 RX Vref Scan: 0
5968 11:35:54.958796
5969 11:35:54.961682 RX Vref 0 -> 0, step: 1
5970 11:35:54.961755
5971 11:35:54.961812 RX Delay -69 -> 252, step: 4
5972 11:35:54.969597 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5973 11:35:54.973657 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5974 11:35:54.976657 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5975 11:35:54.979624 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5976 11:35:54.982987 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5977 11:35:54.986621 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5978 11:35:54.992888 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5979 11:35:54.996927 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5980 11:35:54.999631 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5981 11:35:55.003096 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5982 11:35:55.006368 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5983 11:35:55.009630 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5984 11:35:55.017053 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5985 11:35:55.019837 iDelay=199, Bit 13, Center 98 (11 ~ 186) 176
5986 11:35:55.023094 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5987 11:35:55.026455 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5988 11:35:55.026529 ==
5989 11:35:55.030051 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 11:35:55.036484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 11:35:55.036558 ==
5992 11:35:55.036616 DQS Delay:
5993 11:35:55.036669 DQS0 = 0, DQS1 = 0
5994 11:35:55.039742 DQM Delay:
5995 11:35:55.039815 DQM0 = 95, DQM1 = 90
5996 11:35:55.043341 DQ Delay:
5997 11:35:55.046531 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5998 11:35:55.049730 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5999 11:35:55.053387 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =82
6000 11:35:55.056633 DQ12 =96, DQ13 =98, DQ14 =100, DQ15 =98
6001 11:35:55.056707
6002 11:35:55.056763
6003 11:35:55.063711 [DQSOSCAuto] RK1, (LSB)MR18= 0x121b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6004 11:35:55.066900 CH1 RK1: MR19=505, MR18=121B
6005 11:35:55.073764 CH1_RK1: MR19=0x505, MR18=0x121B, DQSOSC=413, MR23=63, INC=63, DEC=42
6006 11:35:55.077146 [RxdqsGatingPostProcess] freq 933
6007 11:35:55.080608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 11:35:55.083736 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 11:35:55.086946 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 11:35:55.090745 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 11:35:55.093781 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 11:35:55.097054 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 11:35:55.100140 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 11:35:55.103686 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 11:35:55.107046 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 11:35:55.110592 Pre-setting of DQS Precalculation
6017 11:35:55.114300 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 11:35:55.120636 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 11:35:55.127514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 11:35:55.127923
6021 11:35:55.130536
6022 11:35:55.131007 [Calibration Summary] 1866 Mbps
6023 11:35:55.133910 CH 0, Rank 0
6024 11:35:55.134388 SW Impedance : PASS
6025 11:35:55.137560 DUTY Scan : NO K
6026 11:35:55.140571 ZQ Calibration : PASS
6027 11:35:55.140948 Jitter Meter : NO K
6028 11:35:55.143998 CBT Training : PASS
6029 11:35:55.147295 Write leveling : PASS
6030 11:35:55.147674 RX DQS gating : PASS
6031 11:35:55.150770 RX DQ/DQS(RDDQC) : PASS
6032 11:35:55.154159 TX DQ/DQS : PASS
6033 11:35:55.154703 RX DATLAT : PASS
6034 11:35:55.157409 RX DQ/DQS(Engine): PASS
6035 11:35:55.160430 TX OE : NO K
6036 11:35:55.161007 All Pass.
6037 11:35:55.161496
6038 11:35:55.161942 CH 0, Rank 1
6039 11:35:55.163909 SW Impedance : PASS
6040 11:35:55.167271 DUTY Scan : NO K
6041 11:35:55.167767 ZQ Calibration : PASS
6042 11:35:55.170713 Jitter Meter : NO K
6043 11:35:55.171195 CBT Training : PASS
6044 11:35:55.174203 Write leveling : PASS
6045 11:35:55.177508 RX DQS gating : PASS
6046 11:35:55.178022 RX DQ/DQS(RDDQC) : PASS
6047 11:35:55.180793 TX DQ/DQS : PASS
6048 11:35:55.184203 RX DATLAT : PASS
6049 11:35:55.184660 RX DQ/DQS(Engine): PASS
6050 11:35:55.187473 TX OE : NO K
6051 11:35:55.187852 All Pass.
6052 11:35:55.188146
6053 11:35:55.191066 CH 1, Rank 0
6054 11:35:55.191443 SW Impedance : PASS
6055 11:35:55.194206 DUTY Scan : NO K
6056 11:35:55.197696 ZQ Calibration : PASS
6057 11:35:55.198153 Jitter Meter : NO K
6058 11:35:55.200569 CBT Training : PASS
6059 11:35:55.204248 Write leveling : PASS
6060 11:35:55.204704 RX DQS gating : PASS
6061 11:35:55.207471 RX DQ/DQS(RDDQC) : PASS
6062 11:35:55.207851 TX DQ/DQS : PASS
6063 11:35:55.210902 RX DATLAT : PASS
6064 11:35:55.214817 RX DQ/DQS(Engine): PASS
6065 11:35:55.215273 TX OE : NO K
6066 11:35:55.217452 All Pass.
6067 11:35:55.217915
6068 11:35:55.218215 CH 1, Rank 1
6069 11:35:55.220753 SW Impedance : PASS
6070 11:35:55.221170 DUTY Scan : NO K
6071 11:35:55.223977 ZQ Calibration : PASS
6072 11:35:55.227847 Jitter Meter : NO K
6073 11:35:55.228305 CBT Training : PASS
6074 11:35:55.231367 Write leveling : PASS
6075 11:35:55.235081 RX DQS gating : PASS
6076 11:35:55.235460 RX DQ/DQS(RDDQC) : PASS
6077 11:35:55.237370 TX DQ/DQS : PASS
6078 11:35:55.241205 RX DATLAT : PASS
6079 11:35:55.241658 RX DQ/DQS(Engine): PASS
6080 11:35:55.244683 TX OE : NO K
6081 11:35:55.245177 All Pass.
6082 11:35:55.245487
6083 11:35:55.247522 DramC Write-DBI off
6084 11:35:55.251043 PER_BANK_REFRESH: Hybrid Mode
6085 11:35:55.251503 TX_TRACKING: ON
6086 11:35:55.261215 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 11:35:55.264127 [FAST_K] Save calibration result to emmc
6088 11:35:55.267380 dramc_set_vcore_voltage set vcore to 650000
6089 11:35:55.270666 Read voltage for 400, 6
6090 11:35:55.271159 Vio18 = 0
6091 11:35:55.271489 Vcore = 650000
6092 11:35:55.274340 Vdram = 0
6093 11:35:55.274762 Vddq = 0
6094 11:35:55.275093 Vmddr = 0
6095 11:35:55.280605 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 11:35:55.284505 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 11:35:55.287350 MEM_TYPE=3, freq_sel=20
6098 11:35:55.291331 sv_algorithm_assistance_LP4_800
6099 11:35:55.294155 ============ PULL DRAM RESETB DOWN ============
6100 11:35:55.297958 ========== PULL DRAM RESETB DOWN end =========
6101 11:35:55.304633 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 11:35:55.308030 ===================================
6103 11:35:55.308529 LPDDR4 DRAM CONFIGURATION
6104 11:35:55.311324 ===================================
6105 11:35:55.314366 EX_ROW_EN[0] = 0x0
6106 11:35:55.314859 EX_ROW_EN[1] = 0x0
6107 11:35:55.317705 LP4Y_EN = 0x0
6108 11:35:55.321082 WORK_FSP = 0x0
6109 11:35:55.321612 WL = 0x2
6110 11:35:55.324690 RL = 0x2
6111 11:35:55.325106 BL = 0x2
6112 11:35:55.327582 RPST = 0x0
6113 11:35:55.328001 RD_PRE = 0x0
6114 11:35:55.331090 WR_PRE = 0x1
6115 11:35:55.331587 WR_PST = 0x0
6116 11:35:55.334812 DBI_WR = 0x0
6117 11:35:55.335229 DBI_RD = 0x0
6118 11:35:55.337476 OTF = 0x1
6119 11:35:55.340981 ===================================
6120 11:35:55.344915 ===================================
6121 11:35:55.345454 ANA top config
6122 11:35:55.347390 ===================================
6123 11:35:55.351467 DLL_ASYNC_EN = 0
6124 11:35:55.354540 ALL_SLAVE_EN = 1
6125 11:35:55.355032 NEW_RANK_MODE = 1
6126 11:35:55.357923 DLL_IDLE_MODE = 1
6127 11:35:55.360959 LP45_APHY_COMB_EN = 1
6128 11:35:55.364550 TX_ODT_DIS = 1
6129 11:35:55.365187 NEW_8X_MODE = 1
6130 11:35:55.367746 ===================================
6131 11:35:55.371354 ===================================
6132 11:35:55.374294 data_rate = 800
6133 11:35:55.377768 CKR = 1
6134 11:35:55.380754 DQ_P2S_RATIO = 4
6135 11:35:55.384274 ===================================
6136 11:35:55.388160 CA_P2S_RATIO = 4
6137 11:35:55.390984 DQ_CA_OPEN = 0
6138 11:35:55.391473 DQ_SEMI_OPEN = 1
6139 11:35:55.394373 CA_SEMI_OPEN = 1
6140 11:35:55.397662 CA_FULL_RATE = 0
6141 11:35:55.401240 DQ_CKDIV4_EN = 0
6142 11:35:55.404458 CA_CKDIV4_EN = 1
6143 11:35:55.407993 CA_PREDIV_EN = 0
6144 11:35:55.408487 PH8_DLY = 0
6145 11:35:55.411388 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 11:35:55.414476 DQ_AAMCK_DIV = 0
6147 11:35:55.417847 CA_AAMCK_DIV = 0
6148 11:35:55.421014 CA_ADMCK_DIV = 4
6149 11:35:55.424190 DQ_TRACK_CA_EN = 0
6150 11:35:55.424611 CA_PICK = 800
6151 11:35:55.427723 CA_MCKIO = 400
6152 11:35:55.430880 MCKIO_SEMI = 400
6153 11:35:55.434252 PLL_FREQ = 3016
6154 11:35:55.437612 DQ_UI_PI_RATIO = 32
6155 11:35:55.441358 CA_UI_PI_RATIO = 32
6156 11:35:55.444297 ===================================
6157 11:35:55.447600 ===================================
6158 11:35:55.448278 memory_type:LPDDR4
6159 11:35:55.451237 GP_NUM : 10
6160 11:35:55.454093 SRAM_EN : 1
6161 11:35:55.454515 MD32_EN : 0
6162 11:35:55.457350 ===================================
6163 11:35:55.461334 [ANA_INIT] >>>>>>>>>>>>>>
6164 11:35:55.464596 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 11:35:55.467673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 11:35:55.471071 ===================================
6167 11:35:55.474688 data_rate = 800,PCW = 0X7400
6168 11:35:55.477948 ===================================
6169 11:35:55.480962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 11:35:55.484691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 11:35:55.497418 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 11:35:55.500779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 11:35:55.504851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 11:35:55.507889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 11:35:55.511308 [ANA_INIT] flow start
6176 11:35:55.511799 [ANA_INIT] PLL >>>>>>>>
6177 11:35:55.514386 [ANA_INIT] PLL <<<<<<<<
6178 11:35:55.518039 [ANA_INIT] MIDPI >>>>>>>>
6179 11:35:55.521429 [ANA_INIT] MIDPI <<<<<<<<
6180 11:35:55.522084 [ANA_INIT] DLL >>>>>>>>
6181 11:35:55.524641 [ANA_INIT] flow end
6182 11:35:55.527637 ============ LP4 DIFF to SE enter ============
6183 11:35:55.531160 ============ LP4 DIFF to SE exit ============
6184 11:35:55.535196 [ANA_INIT] <<<<<<<<<<<<<
6185 11:35:55.538023 [Flow] Enable top DCM control >>>>>
6186 11:35:55.541071 [Flow] Enable top DCM control <<<<<
6187 11:35:55.544306 Enable DLL master slave shuffle
6188 11:35:55.547982 ==============================================================
6189 11:35:55.551767 Gating Mode config
6190 11:35:55.558043 ==============================================================
6191 11:35:55.558424 Config description:
6192 11:35:55.568245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 11:35:55.574428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 11:35:55.581302 SELPH_MODE 0: By rank 1: By Phase
6195 11:35:55.584706 ==============================================================
6196 11:35:55.587843 GAT_TRACK_EN = 0
6197 11:35:55.591817 RX_GATING_MODE = 2
6198 11:35:55.594477 RX_GATING_TRACK_MODE = 2
6199 11:35:55.597288 SELPH_MODE = 1
6200 11:35:55.601337 PICG_EARLY_EN = 1
6201 11:35:55.604272 VALID_LAT_VALUE = 1
6202 11:35:55.607942 ==============================================================
6203 11:35:55.611491 Enter into Gating configuration >>>>
6204 11:35:55.614851 Exit from Gating configuration <<<<
6205 11:35:55.617534 Enter into DVFS_PRE_config >>>>>
6206 11:35:55.631109 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 11:35:55.634686 Exit from DVFS_PRE_config <<<<<
6208 11:35:55.635191 Enter into PICG configuration >>>>
6209 11:35:55.637426 Exit from PICG configuration <<<<
6210 11:35:55.641627 [RX_INPUT] configuration >>>>>
6211 11:35:55.644665 [RX_INPUT] configuration <<<<<
6212 11:35:55.651255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 11:35:55.655338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 11:35:55.661550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 11:35:55.668054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 11:35:55.674531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 11:35:55.681186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 11:35:55.684358 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 11:35:55.687716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 11:35:55.691471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 11:35:55.697484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 11:35:55.701543 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 11:35:55.704404 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 11:35:55.707986 ===================================
6225 11:35:55.710857 LPDDR4 DRAM CONFIGURATION
6226 11:35:55.714764 ===================================
6227 11:35:55.715265 EX_ROW_EN[0] = 0x0
6228 11:35:55.717616 EX_ROW_EN[1] = 0x0
6229 11:35:55.721303 LP4Y_EN = 0x0
6230 11:35:55.721803 WORK_FSP = 0x0
6231 11:35:55.724590 WL = 0x2
6232 11:35:55.725009 RL = 0x2
6233 11:35:55.727700 BL = 0x2
6234 11:35:55.728117 RPST = 0x0
6235 11:35:55.731174 RD_PRE = 0x0
6236 11:35:55.731593 WR_PRE = 0x1
6237 11:35:55.734964 WR_PST = 0x0
6238 11:35:55.735344 DBI_WR = 0x0
6239 11:35:55.738379 DBI_RD = 0x0
6240 11:35:55.738757 OTF = 0x1
6241 11:35:55.741090 ===================================
6242 11:35:55.744795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 11:35:55.751607 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 11:35:55.754515 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 11:35:55.758068 ===================================
6246 11:35:55.761824 LPDDR4 DRAM CONFIGURATION
6247 11:35:55.764603 ===================================
6248 11:35:55.765104 EX_ROW_EN[0] = 0x10
6249 11:35:55.768236 EX_ROW_EN[1] = 0x0
6250 11:35:55.768735 LP4Y_EN = 0x0
6251 11:35:55.771308 WORK_FSP = 0x0
6252 11:35:55.771810 WL = 0x2
6253 11:35:55.774711 RL = 0x2
6254 11:35:55.775129 BL = 0x2
6255 11:35:55.778021 RPST = 0x0
6256 11:35:55.778517 RD_PRE = 0x0
6257 11:35:55.780941 WR_PRE = 0x1
6258 11:35:55.784680 WR_PST = 0x0
6259 11:35:55.785098 DBI_WR = 0x0
6260 11:35:55.788066 DBI_RD = 0x0
6261 11:35:55.788498 OTF = 0x1
6262 11:35:55.791327 ===================================
6263 11:35:55.797423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 11:35:55.801280 nWR fixed to 30
6265 11:35:55.804717 [ModeRegInit_LP4] CH0 RK0
6266 11:35:55.805260 [ModeRegInit_LP4] CH0 RK1
6267 11:35:55.808369 [ModeRegInit_LP4] CH1 RK0
6268 11:35:55.811084 [ModeRegInit_LP4] CH1 RK1
6269 11:35:55.811502 match AC timing 19
6270 11:35:55.818425 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 11:35:55.821525 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 11:35:55.824818 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 11:35:55.831600 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 11:35:55.834553 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 11:35:55.834973 ==
6276 11:35:55.838041 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 11:35:55.841647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 11:35:55.842145 ==
6279 11:35:55.848644 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 11:35:55.855176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 11:35:55.858143 [CA 0] Center 36 (8~64) winsize 57
6282 11:35:55.861715 [CA 1] Center 36 (8~64) winsize 57
6283 11:35:55.862131 [CA 2] Center 36 (8~64) winsize 57
6284 11:35:55.865240 [CA 3] Center 36 (8~64) winsize 57
6285 11:35:55.868361 [CA 4] Center 36 (8~64) winsize 57
6286 11:35:55.872204 [CA 5] Center 36 (8~64) winsize 57
6287 11:35:55.872696
6288 11:35:55.875089 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 11:35:55.875580
6290 11:35:55.878830 [CATrainingPosCal] consider 1 rank data
6291 11:35:55.881957 u2DelayCellTimex100 = 270/100 ps
6292 11:35:55.885244 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:35:55.888333 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:35:55.894715 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 11:35:55.898092 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:35:55.901863 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:35:55.904693 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:35:55.905227
6299 11:35:55.908721 CA PerBit enable=1, Macro0, CA PI delay=36
6300 11:35:55.909259
6301 11:35:55.911690 [CBTSetCACLKResult] CA Dly = 36
6302 11:35:55.912106 CS Dly: 1 (0~32)
6303 11:35:55.915112 ==
6304 11:35:55.915601 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 11:35:55.921413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 11:35:55.921949 ==
6307 11:35:55.925054 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 11:35:55.931134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6309 11:35:55.935179 [CA 0] Center 36 (8~64) winsize 57
6310 11:35:55.937895 [CA 1] Center 36 (8~64) winsize 57
6311 11:35:55.941757 [CA 2] Center 36 (8~64) winsize 57
6312 11:35:55.944861 [CA 3] Center 36 (8~64) winsize 57
6313 11:35:55.948181 [CA 4] Center 36 (8~64) winsize 57
6314 11:35:55.951297 [CA 5] Center 36 (8~64) winsize 57
6315 11:35:55.951720
6316 11:35:55.954794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6317 11:35:55.955252
6318 11:35:55.958801 [CATrainingPosCal] consider 2 rank data
6319 11:35:55.961563 u2DelayCellTimex100 = 270/100 ps
6320 11:35:55.964883 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:35:55.968477 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:35:55.971333 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:35:55.974333 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:35:55.978182 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 11:35:55.984505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:35:55.984959
6327 11:35:55.988041 CA PerBit enable=1, Macro0, CA PI delay=36
6328 11:35:55.988505
6329 11:35:55.991782 [CBTSetCACLKResult] CA Dly = 36
6330 11:35:55.992235 CS Dly: 1 (0~32)
6331 11:35:55.992529
6332 11:35:55.994990 ----->DramcWriteLeveling(PI) begin...
6333 11:35:55.995458 ==
6334 11:35:55.997705 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 11:35:56.004900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 11:35:56.005417 ==
6337 11:35:56.005721 Write leveling (Byte 0): 40 => 8
6338 11:35:56.007721 Write leveling (Byte 1): 32 => 0
6339 11:35:56.010991 DramcWriteLeveling(PI) end<-----
6340 11:35:56.011437
6341 11:35:56.011731 ==
6342 11:35:56.014694 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 11:35:56.021548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:35:56.021961 ==
6345 11:35:56.022267 [Gating] SW mode calibration
6346 11:35:56.031223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 11:35:56.034508 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 11:35:56.037769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 11:35:56.044601 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 11:35:56.047787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 11:35:56.051601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 11:35:56.057707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 11:35:56.061114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 11:35:56.065292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 11:35:56.071517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 11:35:56.074484 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 11:35:56.078065 Total UI for P1: 0, mck2ui 16
6358 11:35:56.081020 best dqsien dly found for B0: ( 0, 14, 24)
6359 11:35:56.084948 Total UI for P1: 0, mck2ui 16
6360 11:35:56.088451 best dqsien dly found for B1: ( 0, 14, 24)
6361 11:35:56.091580 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 11:35:56.094940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 11:35:56.095431
6364 11:35:56.098214 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 11:35:56.101050 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 11:35:56.104871 [Gating] SW calibration Done
6367 11:35:56.105320 ==
6368 11:35:56.108420 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 11:35:56.111303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 11:35:56.114976 ==
6371 11:35:56.115464 RX Vref Scan: 0
6372 11:35:56.115785
6373 11:35:56.118250 RX Vref 0 -> 0, step: 1
6374 11:35:56.118659
6375 11:35:56.121321 RX Delay -410 -> 252, step: 16
6376 11:35:56.125191 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6377 11:35:56.127732 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6378 11:35:56.131262 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6379 11:35:56.138251 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6380 11:35:56.141109 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6381 11:35:56.145112 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6382 11:35:56.148140 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6383 11:35:56.154645 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6384 11:35:56.159008 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6385 11:35:56.161367 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6386 11:35:56.164987 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6387 11:35:56.171468 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6388 11:35:56.174855 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6389 11:35:56.178070 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6390 11:35:56.181772 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6391 11:35:56.188210 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6392 11:35:56.188705 ==
6393 11:35:56.191654 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 11:35:56.194877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 11:35:56.195370 ==
6396 11:35:56.195698 DQS Delay:
6397 11:35:56.198048 DQS0 = 43, DQS1 = 51
6398 11:35:56.198649 DQM Delay:
6399 11:35:56.201862 DQM0 = 13, DQM1 = 10
6400 11:35:56.202275 DQ Delay:
6401 11:35:56.205236 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6402 11:35:56.208709 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6403 11:35:56.212011 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6404 11:35:56.214947 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6405 11:35:56.215445
6406 11:35:56.215769
6407 11:35:56.216073 ==
6408 11:35:56.218880 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 11:35:56.221949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 11:35:56.222448 ==
6411 11:35:56.222774
6412 11:35:56.223073
6413 11:35:56.225024 TX Vref Scan disable
6414 11:35:56.225470 == TX Byte 0 ==
6415 11:35:56.231641 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 11:35:56.235075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 11:35:56.235491 == TX Byte 1 ==
6418 11:35:56.241535 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 11:35:56.244992 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 11:35:56.245513 ==
6421 11:35:56.248699 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 11:35:56.252475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 11:35:56.252893 ==
6424 11:35:56.253261
6425 11:35:56.253566
6426 11:35:56.254749 TX Vref Scan disable
6427 11:35:56.258143 == TX Byte 0 ==
6428 11:35:56.261785 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 11:35:56.264829 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 11:35:56.265282 == TX Byte 1 ==
6431 11:35:56.271422 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6432 11:35:56.274868 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6433 11:35:56.275369
6434 11:35:56.275696 [DATLAT]
6435 11:35:56.278230 Freq=400, CH0 RK0
6436 11:35:56.278651
6437 11:35:56.278974 DATLAT Default: 0xf
6438 11:35:56.281821 0, 0xFFFF, sum = 0
6439 11:35:56.282316 1, 0xFFFF, sum = 0
6440 11:35:56.284952 2, 0xFFFF, sum = 0
6441 11:35:56.285512 3, 0xFFFF, sum = 0
6442 11:35:56.288641 4, 0xFFFF, sum = 0
6443 11:35:56.291234 5, 0xFFFF, sum = 0
6444 11:35:56.291658 6, 0xFFFF, sum = 0
6445 11:35:56.294801 7, 0xFFFF, sum = 0
6446 11:35:56.295321 8, 0xFFFF, sum = 0
6447 11:35:56.298492 9, 0xFFFF, sum = 0
6448 11:35:56.299120 10, 0xFFFF, sum = 0
6449 11:35:56.301563 11, 0xFFFF, sum = 0
6450 11:35:56.301989 12, 0xFFFF, sum = 0
6451 11:35:56.305113 13, 0x0, sum = 1
6452 11:35:56.305561 14, 0x0, sum = 2
6453 11:35:56.308700 15, 0x0, sum = 3
6454 11:35:56.309250 16, 0x0, sum = 4
6455 11:35:56.309590 best_step = 14
6456 11:35:56.311718
6457 11:35:56.312130 ==
6458 11:35:56.315275 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 11:35:56.318701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 11:35:56.319201 ==
6461 11:35:56.319536 RX Vref Scan: 1
6462 11:35:56.319841
6463 11:35:56.321354 RX Vref 0 -> 0, step: 1
6464 11:35:56.321772
6465 11:35:56.324789 RX Delay -343 -> 252, step: 8
6466 11:35:56.325335
6467 11:35:56.327881 Set Vref, RX VrefLevel [Byte0]: 54
6468 11:35:56.331382 [Byte1]: 51
6469 11:35:56.335754
6470 11:35:56.336250 Final RX Vref Byte 0 = 54 to rank0
6471 11:35:56.338939 Final RX Vref Byte 1 = 51 to rank0
6472 11:35:56.342122 Final RX Vref Byte 0 = 54 to rank1
6473 11:35:56.345151 Final RX Vref Byte 1 = 51 to rank1==
6474 11:35:56.348477 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 11:35:56.355536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 11:35:56.356052 ==
6477 11:35:56.356386 DQS Delay:
6478 11:35:56.356692 DQS0 = 44, DQS1 = 60
6479 11:35:56.359381 DQM Delay:
6480 11:35:56.359878 DQM0 = 11, DQM1 = 14
6481 11:35:56.361764 DQ Delay:
6482 11:35:56.365599 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6483 11:35:56.366099 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6484 11:35:56.368780 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6485 11:35:56.372131 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =28
6486 11:35:56.372627
6487 11:35:56.375347
6488 11:35:56.381849 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6489 11:35:56.385416 CH0 RK0: MR19=C0C, MR18=8A59
6490 11:35:56.391922 CH0_RK0: MR19=0xC0C, MR18=0x8A59, DQSOSC=392, MR23=63, INC=384, DEC=256
6491 11:35:56.392498 ==
6492 11:35:56.395643 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 11:35:56.398344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 11:35:56.398769 ==
6495 11:35:56.401724 [Gating] SW mode calibration
6496 11:35:56.408384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 11:35:56.415422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 11:35:56.418851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 11:35:56.422401 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 11:35:56.425213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 11:35:56.432021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 11:35:56.435221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 11:35:56.438057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 11:35:56.445253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 11:35:56.448109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 11:35:56.451690 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 11:35:56.455462 Total UI for P1: 0, mck2ui 16
6508 11:35:56.458478 best dqsien dly found for B0: ( 0, 14, 24)
6509 11:35:56.461679 Total UI for P1: 0, mck2ui 16
6510 11:35:56.465523 best dqsien dly found for B1: ( 0, 14, 24)
6511 11:35:56.468851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 11:35:56.471926 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 11:35:56.472421
6514 11:35:56.478599 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 11:35:56.482461 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 11:35:56.485196 [Gating] SW calibration Done
6517 11:35:56.485613 ==
6518 11:35:56.488686 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 11:35:56.492283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 11:35:56.492783 ==
6521 11:35:56.493112 RX Vref Scan: 0
6522 11:35:56.493472
6523 11:35:56.495067 RX Vref 0 -> 0, step: 1
6524 11:35:56.495552
6525 11:35:56.498668 RX Delay -410 -> 252, step: 16
6526 11:35:56.501640 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6527 11:35:56.508541 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6528 11:35:56.512058 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6529 11:35:56.515217 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6530 11:35:56.518516 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6531 11:35:56.524921 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6532 11:35:56.528230 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6533 11:35:56.531493 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6534 11:35:56.534925 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6535 11:35:56.541589 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6536 11:35:56.545242 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6537 11:35:56.548263 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6538 11:35:56.551488 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6539 11:35:56.558038 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6540 11:35:56.561846 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6541 11:35:56.565095 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6542 11:35:56.565621 ==
6543 11:35:56.568190 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 11:35:56.572228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 11:35:56.574511 ==
6546 11:35:56.574931 DQS Delay:
6547 11:35:56.575258 DQS0 = 43, DQS1 = 51
6548 11:35:56.578169 DQM Delay:
6549 11:35:56.578677 DQM0 = 11, DQM1 = 10
6550 11:35:56.581992 DQ Delay:
6551 11:35:56.582497 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6552 11:35:56.584702 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6553 11:35:56.588007 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 11:35:56.591296 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 11:35:56.591720
6556 11:35:56.592046
6557 11:35:56.592348 ==
6558 11:35:56.595223 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 11:35:56.601526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 11:35:56.602210 ==
6561 11:35:56.602651
6562 11:35:56.602965
6563 11:35:56.603259 TX Vref Scan disable
6564 11:35:56.604961 == TX Byte 0 ==
6565 11:35:56.608520 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6566 11:35:56.611570 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6567 11:35:56.614817 == TX Byte 1 ==
6568 11:35:56.618211 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6569 11:35:56.621708 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6570 11:35:56.622143 ==
6571 11:35:56.624693 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 11:35:56.631456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 11:35:56.631835 ==
6574 11:35:56.632129
6575 11:35:56.632397
6576 11:35:56.632655 TX Vref Scan disable
6577 11:35:56.635156 == TX Byte 0 ==
6578 11:35:56.638265 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6579 11:35:56.641427 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6580 11:35:56.645085 == TX Byte 1 ==
6581 11:35:56.648566 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6582 11:35:56.652186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6583 11:35:56.652562
6584 11:35:56.655198 [DATLAT]
6585 11:35:56.655576 Freq=400, CH0 RK1
6586 11:35:56.655884
6587 11:35:56.659051 DATLAT Default: 0xe
6588 11:35:56.659770 0, 0xFFFF, sum = 0
6589 11:35:56.661510 1, 0xFFFF, sum = 0
6590 11:35:56.662108 2, 0xFFFF, sum = 0
6591 11:35:56.664954 3, 0xFFFF, sum = 0
6592 11:35:56.665388 4, 0xFFFF, sum = 0
6593 11:35:56.668395 5, 0xFFFF, sum = 0
6594 11:35:56.668776 6, 0xFFFF, sum = 0
6595 11:35:56.671814 7, 0xFFFF, sum = 0
6596 11:35:56.672277 8, 0xFFFF, sum = 0
6597 11:35:56.674712 9, 0xFFFF, sum = 0
6598 11:35:56.675094 10, 0xFFFF, sum = 0
6599 11:35:56.678639 11, 0xFFFF, sum = 0
6600 11:35:56.679246 12, 0xFFFF, sum = 0
6601 11:35:56.682119 13, 0x0, sum = 1
6602 11:35:56.682497 14, 0x0, sum = 2
6603 11:35:56.685230 15, 0x0, sum = 3
6604 11:35:56.685612 16, 0x0, sum = 4
6605 11:35:56.688336 best_step = 14
6606 11:35:56.688713
6607 11:35:56.689000 ==
6608 11:35:56.691416 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 11:35:56.695408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 11:35:56.695870 ==
6611 11:35:56.698395 RX Vref Scan: 0
6612 11:35:56.698836
6613 11:35:56.699220 RX Vref 0 -> 0, step: 1
6614 11:35:56.699583
6615 11:35:56.701638 RX Delay -343 -> 252, step: 8
6616 11:35:56.709726 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6617 11:35:56.712837 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6618 11:35:56.716138 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6619 11:35:56.719629 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6620 11:35:56.726495 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6621 11:35:56.729632 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6622 11:35:56.732634 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6623 11:35:56.735935 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6624 11:35:56.742682 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6625 11:35:56.746090 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6626 11:35:56.748979 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6627 11:35:56.755870 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6628 11:35:56.759579 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6629 11:35:56.762585 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6630 11:35:56.766024 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6631 11:35:56.772439 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6632 11:35:56.772936 ==
6633 11:35:56.775640 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 11:35:56.779461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 11:35:56.779953 ==
6636 11:35:56.780282 DQS Delay:
6637 11:35:56.782430 DQS0 = 48, DQS1 = 60
6638 11:35:56.782845 DQM Delay:
6639 11:35:56.785975 DQM0 = 11, DQM1 = 13
6640 11:35:56.786391 DQ Delay:
6641 11:35:56.789328 DQ0 =16, DQ1 =12, DQ2 =8, DQ3 =12
6642 11:35:56.793099 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6643 11:35:56.796464 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6644 11:35:56.799116 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6645 11:35:56.799534
6646 11:35:56.799855
6647 11:35:56.806178 [DQSOSCAuto] RK1, (LSB)MR18= 0x9569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6648 11:35:56.809030 CH0 RK1: MR19=C0C, MR18=9569
6649 11:35:56.815826 CH0_RK1: MR19=0xC0C, MR18=0x9569, DQSOSC=391, MR23=63, INC=386, DEC=257
6650 11:35:56.819049 [RxdqsGatingPostProcess] freq 400
6651 11:35:56.826130 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 11:35:56.826649 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 11:35:56.829167 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 11:35:56.832368 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 11:35:56.835727 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 11:35:56.839838 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 11:35:56.842703 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 11:35:56.846032 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 11:35:56.849026 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 11:35:56.852499 Pre-setting of DQS Precalculation
6661 11:35:56.856388 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 11:35:56.859176 ==
6663 11:35:56.862340 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 11:35:56.866319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 11:35:56.866830 ==
6666 11:35:56.869269 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 11:35:56.875701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 11:35:56.879704 [CA 0] Center 36 (8~64) winsize 57
6669 11:35:56.882499 [CA 1] Center 36 (8~64) winsize 57
6670 11:35:56.885660 [CA 2] Center 36 (8~64) winsize 57
6671 11:35:56.889636 [CA 3] Center 36 (8~64) winsize 57
6672 11:35:56.892847 [CA 4] Center 36 (8~64) winsize 57
6673 11:35:56.896184 [CA 5] Center 36 (8~64) winsize 57
6674 11:35:56.896693
6675 11:35:56.899571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 11:35:56.900005
6677 11:35:56.902609 [CATrainingPosCal] consider 1 rank data
6678 11:35:56.905918 u2DelayCellTimex100 = 270/100 ps
6679 11:35:56.909375 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:35:56.913196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:35:56.916076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 11:35:56.919523 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:35:56.922902 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:35:56.926333 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:35:56.929540
6686 11:35:56.932776 CA PerBit enable=1, Macro0, CA PI delay=36
6687 11:35:56.933362
6688 11:35:56.936131 [CBTSetCACLKResult] CA Dly = 36
6689 11:35:56.936643 CS Dly: 1 (0~32)
6690 11:35:56.937074 ==
6691 11:35:56.939348 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 11:35:56.943111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 11:35:56.943627 ==
6694 11:35:56.949608 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 11:35:56.956319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6696 11:35:56.959560 [CA 0] Center 36 (8~64) winsize 57
6697 11:35:56.963038 [CA 1] Center 36 (8~64) winsize 57
6698 11:35:56.965916 [CA 2] Center 36 (8~64) winsize 57
6699 11:35:56.969602 [CA 3] Center 36 (8~64) winsize 57
6700 11:35:56.970120 [CA 4] Center 36 (8~64) winsize 57
6701 11:35:56.972848 [CA 5] Center 36 (8~64) winsize 57
6702 11:35:56.973417
6703 11:35:56.979718 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6704 11:35:56.980241
6705 11:35:56.982903 [CATrainingPosCal] consider 2 rank data
6706 11:35:56.986169 u2DelayCellTimex100 = 270/100 ps
6707 11:35:56.989653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:35:56.993743 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:35:56.996100 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:35:56.999492 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:35:57.002976 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 11:35:57.006304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:35:57.006737
6714 11:35:57.009503 CA PerBit enable=1, Macro0, CA PI delay=36
6715 11:35:57.010021
6716 11:35:57.013020 [CBTSetCACLKResult] CA Dly = 36
6717 11:35:57.016050 CS Dly: 1 (0~32)
6718 11:35:57.016559
6719 11:35:57.020119 ----->DramcWriteLeveling(PI) begin...
6720 11:35:57.020640 ==
6721 11:35:57.023125 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 11:35:57.026190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 11:35:57.026674 ==
6724 11:35:57.029416 Write leveling (Byte 0): 40 => 8
6725 11:35:57.032757 Write leveling (Byte 1): 40 => 8
6726 11:35:57.036322 DramcWriteLeveling(PI) end<-----
6727 11:35:57.036751
6728 11:35:57.037212 ==
6729 11:35:57.039627 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 11:35:57.042882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:35:57.043316 ==
6732 11:35:57.046153 [Gating] SW mode calibration
6733 11:35:57.052665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 11:35:57.060279 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 11:35:57.062750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 11:35:57.066217 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 11:35:57.072984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 11:35:57.076506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 11:35:57.079732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 11:35:57.083131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 11:35:57.090225 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 11:35:57.093193 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 11:35:57.096631 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 11:35:57.099920 Total UI for P1: 0, mck2ui 16
6745 11:35:57.103162 best dqsien dly found for B0: ( 0, 14, 24)
6746 11:35:57.106554 Total UI for P1: 0, mck2ui 16
6747 11:35:57.110078 best dqsien dly found for B1: ( 0, 14, 24)
6748 11:35:57.113292 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 11:35:57.116715 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 11:35:57.119711
6751 11:35:57.123160 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 11:35:57.126156 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 11:35:57.129594 [Gating] SW calibration Done
6754 11:35:57.130136 ==
6755 11:35:57.133136 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 11:35:57.136296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 11:35:57.136672 ==
6758 11:35:57.136966 RX Vref Scan: 0
6759 11:35:57.137291
6760 11:35:57.140047 RX Vref 0 -> 0, step: 1
6761 11:35:57.140504
6762 11:35:57.143142 RX Delay -410 -> 252, step: 16
6763 11:35:57.146858 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6764 11:35:57.153575 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6765 11:35:57.156484 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6766 11:35:57.159835 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6767 11:35:57.162730 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6768 11:35:57.169862 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6769 11:35:57.173157 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6770 11:35:57.176048 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6771 11:35:57.180007 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6772 11:35:57.186324 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6773 11:35:57.189532 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6774 11:35:57.192970 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6775 11:35:57.195932 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6776 11:35:57.202828 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6777 11:35:57.206196 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6778 11:35:57.209323 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6779 11:35:57.209745 ==
6780 11:35:57.213157 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 11:35:57.217053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 11:35:57.219366 ==
6783 11:35:57.219779 DQS Delay:
6784 11:35:57.220099 DQS0 = 51, DQS1 = 59
6785 11:35:57.223140 DQM Delay:
6786 11:35:57.223554 DQM0 = 19, DQM1 = 16
6787 11:35:57.226530 DQ Delay:
6788 11:35:57.226904 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6789 11:35:57.229793 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6790 11:35:57.232542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6791 11:35:57.235976 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6792 11:35:57.236348
6793 11:35:57.236637
6794 11:35:57.239386 ==
6795 11:35:57.242565 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 11:35:57.245973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 11:35:57.246396 ==
6798 11:35:57.246692
6799 11:35:57.246961
6800 11:35:57.250075 TX Vref Scan disable
6801 11:35:57.250451 == TX Byte 0 ==
6802 11:35:57.252801 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 11:35:57.259419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 11:35:57.259796 == TX Byte 1 ==
6805 11:35:57.263044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 11:35:57.269868 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 11:35:57.270324 ==
6808 11:35:57.272895 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 11:35:57.276362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 11:35:57.276857 ==
6811 11:35:57.277237
6812 11:35:57.277545
6813 11:35:57.279454 TX Vref Scan disable
6814 11:35:57.279857 == TX Byte 0 ==
6815 11:35:57.283709 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 11:35:57.289608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 11:35:57.290047 == TX Byte 1 ==
6818 11:35:57.292821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 11:35:57.299556 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 11:35:57.299979
6821 11:35:57.300274 [DATLAT]
6822 11:35:57.300546 Freq=400, CH1 RK0
6823 11:35:57.300808
6824 11:35:57.303090 DATLAT Default: 0xf
6825 11:35:57.303466 0, 0xFFFF, sum = 0
6826 11:35:57.306097 1, 0xFFFF, sum = 0
6827 11:35:57.306509 2, 0xFFFF, sum = 0
6828 11:35:57.309842 3, 0xFFFF, sum = 0
6829 11:35:57.310341 4, 0xFFFF, sum = 0
6830 11:35:57.313003 5, 0xFFFF, sum = 0
6831 11:35:57.316035 6, 0xFFFF, sum = 0
6832 11:35:57.316459 7, 0xFFFF, sum = 0
6833 11:35:57.319711 8, 0xFFFF, sum = 0
6834 11:35:57.320098 9, 0xFFFF, sum = 0
6835 11:35:57.323345 10, 0xFFFF, sum = 0
6836 11:35:57.323731 11, 0xFFFF, sum = 0
6837 11:35:57.326208 12, 0xFFFF, sum = 0
6838 11:35:57.326594 13, 0x0, sum = 1
6839 11:35:57.329492 14, 0x0, sum = 2
6840 11:35:57.329876 15, 0x0, sum = 3
6841 11:35:57.333432 16, 0x0, sum = 4
6842 11:35:57.333817 best_step = 14
6843 11:35:57.334111
6844 11:35:57.334383 ==
6845 11:35:57.336045 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 11:35:57.339969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 11:35:57.340350 ==
6848 11:35:57.343309 RX Vref Scan: 1
6849 11:35:57.343761
6850 11:35:57.346241 RX Vref 0 -> 0, step: 1
6851 11:35:57.346615
6852 11:35:57.346907 RX Delay -359 -> 252, step: 8
6853 11:35:57.347178
6854 11:35:57.349927 Set Vref, RX VrefLevel [Byte0]: 57
6855 11:35:57.352979 [Byte1]: 47
6856 11:35:57.358626
6857 11:35:57.359051 Final RX Vref Byte 0 = 57 to rank0
6858 11:35:57.361609 Final RX Vref Byte 1 = 47 to rank0
6859 11:35:57.364852 Final RX Vref Byte 0 = 57 to rank1
6860 11:35:57.368376 Final RX Vref Byte 1 = 47 to rank1==
6861 11:35:57.371642 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 11:35:57.378185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 11:35:57.378676 ==
6864 11:35:57.378990 DQS Delay:
6865 11:35:57.381482 DQS0 = 48, DQS1 = 60
6866 11:35:57.381929 DQM Delay:
6867 11:35:57.382221 DQM0 = 11, DQM1 = 12
6868 11:35:57.385340 DQ Delay:
6869 11:35:57.388276 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6870 11:35:57.388770 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6871 11:35:57.391827 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6872 11:35:57.394746 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =16
6873 11:35:57.395159
6874 11:35:57.397988
6875 11:35:57.404917 [DQSOSCAuto] RK0, (LSB)MR18= 0x9037, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6876 11:35:57.407930 CH1 RK0: MR19=C0C, MR18=9037
6877 11:35:57.414478 CH1_RK0: MR19=0xC0C, MR18=0x9037, DQSOSC=391, MR23=63, INC=386, DEC=257
6878 11:35:57.414903 ==
6879 11:35:57.418110 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 11:35:57.421886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 11:35:57.422266 ==
6882 11:35:57.425364 [Gating] SW mode calibration
6883 11:35:57.431305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 11:35:57.438012 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 11:35:57.441463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 11:35:57.444706 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 11:35:57.448652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 11:35:57.455212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 11:35:57.458497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 11:35:57.461809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 11:35:57.468431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 11:35:57.471123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 11:35:57.475613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 11:35:57.478076 Total UI for P1: 0, mck2ui 16
6895 11:35:57.481256 best dqsien dly found for B0: ( 0, 14, 24)
6896 11:35:57.484826 Total UI for P1: 0, mck2ui 16
6897 11:35:57.487900 best dqsien dly found for B1: ( 0, 14, 24)
6898 11:35:57.491553 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 11:35:57.498271 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 11:35:57.498759
6901 11:35:57.502034 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 11:35:57.504855 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 11:35:57.507624 [Gating] SW calibration Done
6904 11:35:57.508163 ==
6905 11:35:57.511027 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 11:35:57.514333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 11:35:57.514830 ==
6908 11:35:57.515162 RX Vref Scan: 0
6909 11:35:57.517672
6910 11:35:57.518087 RX Vref 0 -> 0, step: 1
6911 11:35:57.518414
6912 11:35:57.521195 RX Delay -410 -> 252, step: 16
6913 11:35:57.524466 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6914 11:35:57.530978 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6915 11:35:57.534023 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6916 11:35:57.537753 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6917 11:35:57.540730 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6918 11:35:57.548293 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6919 11:35:57.550985 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6920 11:35:57.554012 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6921 11:35:57.557826 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6922 11:35:57.564423 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6923 11:35:57.567669 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6924 11:35:57.570740 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6925 11:35:57.574178 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6926 11:35:57.580721 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6927 11:35:57.584790 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6928 11:35:57.588054 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6929 11:35:57.588473 ==
6930 11:35:57.590608 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 11:35:57.593996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 11:35:57.597592 ==
6933 11:35:57.598053 DQS Delay:
6934 11:35:57.598383 DQS0 = 43, DQS1 = 51
6935 11:35:57.600776 DQM Delay:
6936 11:35:57.601238 DQM0 = 9, DQM1 = 9
6937 11:35:57.604601 DQ Delay:
6938 11:35:57.605017 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6939 11:35:57.607950 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6940 11:35:57.610803 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6941 11:35:57.614292 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6942 11:35:57.614776
6943 11:35:57.615101
6944 11:35:57.615467 ==
6945 11:35:57.618035 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 11:35:57.624207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 11:35:57.624668 ==
6948 11:35:57.624992
6949 11:35:57.625352
6950 11:35:57.625646 TX Vref Scan disable
6951 11:35:57.627266 == TX Byte 0 ==
6952 11:35:57.631026 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6953 11:35:57.634411 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6954 11:35:57.637779 == TX Byte 1 ==
6955 11:35:57.641204 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6956 11:35:57.644027 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6957 11:35:57.644404 ==
6958 11:35:57.647599 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 11:35:57.653878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 11:35:57.654257 ==
6961 11:35:57.654553
6962 11:35:57.654823
6963 11:35:57.655080 TX Vref Scan disable
6964 11:35:57.657796 == TX Byte 0 ==
6965 11:35:57.660926 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6966 11:35:57.664352 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6967 11:35:57.667419 == TX Byte 1 ==
6968 11:35:57.671158 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6969 11:35:57.674373 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6970 11:35:57.674751
6971 11:35:57.677578 [DATLAT]
6972 11:35:57.678004 Freq=400, CH1 RK1
6973 11:35:57.678307
6974 11:35:57.681179 DATLAT Default: 0xe
6975 11:35:57.681639 0, 0xFFFF, sum = 0
6976 11:35:57.684577 1, 0xFFFF, sum = 0
6977 11:35:57.685008 2, 0xFFFF, sum = 0
6978 11:35:57.687601 3, 0xFFFF, sum = 0
6979 11:35:57.687984 4, 0xFFFF, sum = 0
6980 11:35:57.691109 5, 0xFFFF, sum = 0
6981 11:35:57.691496 6, 0xFFFF, sum = 0
6982 11:35:57.695174 7, 0xFFFF, sum = 0
6983 11:35:57.695557 8, 0xFFFF, sum = 0
6984 11:35:57.697502 9, 0xFFFF, sum = 0
6985 11:35:57.697885 10, 0xFFFF, sum = 0
6986 11:35:57.701053 11, 0xFFFF, sum = 0
6987 11:35:57.701476 12, 0xFFFF, sum = 0
6988 11:35:57.704168 13, 0x0, sum = 1
6989 11:35:57.704551 14, 0x0, sum = 2
6990 11:35:57.707628 15, 0x0, sum = 3
6991 11:35:57.708015 16, 0x0, sum = 4
6992 11:35:57.710661 best_step = 14
6993 11:35:57.711040
6994 11:35:57.711463 ==
6995 11:35:57.714444 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 11:35:57.717387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 11:35:57.717766 ==
6998 11:35:57.721010 RX Vref Scan: 0
6999 11:35:57.721413
7000 11:35:57.721712 RX Vref 0 -> 0, step: 1
7001 11:35:57.721986
7002 11:35:57.724076 RX Delay -343 -> 252, step: 8
7003 11:35:57.732026 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7004 11:35:57.735663 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7005 11:35:57.738778 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7006 11:35:57.742022 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7007 11:35:57.748684 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7008 11:35:57.752418 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7009 11:35:57.755599 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7010 11:35:57.759071 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7011 11:35:57.765667 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7012 11:35:57.769382 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7013 11:35:57.772291 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7014 11:35:57.775418 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7015 11:35:57.782230 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7016 11:35:57.785440 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7017 11:35:57.788463 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7018 11:35:57.795114 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7019 11:35:57.795279 ==
7020 11:35:57.798557 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 11:35:57.801537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 11:35:57.801704 ==
7023 11:35:57.801833 DQS Delay:
7024 11:35:57.804977 DQS0 = 52, DQS1 = 60
7025 11:35:57.805160 DQM Delay:
7026 11:35:57.808593 DQM0 = 12, DQM1 = 13
7027 11:35:57.808754 DQ Delay:
7028 11:35:57.811856 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7029 11:35:57.815324 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7030 11:35:57.818190 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
7031 11:35:57.821867 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7032 11:35:57.822030
7033 11:35:57.822157
7034 11:35:57.828828 [DQSOSCAuto] RK1, (LSB)MR18= 0x7c92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
7035 11:35:57.831905 CH1 RK1: MR19=C0C, MR18=7C92
7036 11:35:57.838647 CH1_RK1: MR19=0xC0C, MR18=0x7C92, DQSOSC=391, MR23=63, INC=386, DEC=257
7037 11:35:57.841748 [RxdqsGatingPostProcess] freq 400
7038 11:35:57.845308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 11:35:57.848502 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 11:35:57.852082 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 11:35:57.855329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 11:35:57.858600 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 11:35:57.861911 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 11:35:57.865363 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 11:35:57.868772 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 11:35:57.872109 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 11:35:57.875522 Pre-setting of DQS Precalculation
7048 11:35:57.878659 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 11:35:57.888722 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 11:35:57.895433 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 11:35:57.895920
7052 11:35:57.896319
7053 11:35:57.898328 [Calibration Summary] 800 Mbps
7054 11:35:57.898724 CH 0, Rank 0
7055 11:35:57.901805 SW Impedance : PASS
7056 11:35:57.902200 DUTY Scan : NO K
7057 11:35:57.905643 ZQ Calibration : PASS
7058 11:35:57.909562 Jitter Meter : NO K
7059 11:35:57.910054 CBT Training : PASS
7060 11:35:57.911702 Write leveling : PASS
7061 11:35:57.915683 RX DQS gating : PASS
7062 11:35:57.916078 RX DQ/DQS(RDDQC) : PASS
7063 11:35:57.919046 TX DQ/DQS : PASS
7064 11:35:57.922694 RX DATLAT : PASS
7065 11:35:57.923211 RX DQ/DQS(Engine): PASS
7066 11:35:57.925219 TX OE : NO K
7067 11:35:57.925601 All Pass.
7068 11:35:57.925899
7069 11:35:57.928682 CH 0, Rank 1
7070 11:35:57.929077 SW Impedance : PASS
7071 11:35:57.931882 DUTY Scan : NO K
7072 11:35:57.932276 ZQ Calibration : PASS
7073 11:35:57.935038 Jitter Meter : NO K
7074 11:35:57.938280 CBT Training : PASS
7075 11:35:57.938676 Write leveling : NO K
7076 11:35:57.942345 RX DQS gating : PASS
7077 11:35:57.945444 RX DQ/DQS(RDDQC) : PASS
7078 11:35:57.945840 TX DQ/DQS : PASS
7079 11:35:57.948502 RX DATLAT : PASS
7080 11:35:57.951897 RX DQ/DQS(Engine): PASS
7081 11:35:57.952294 TX OE : NO K
7082 11:35:57.955151 All Pass.
7083 11:35:57.955541
7084 11:35:57.955935 CH 1, Rank 0
7085 11:35:57.958583 SW Impedance : PASS
7086 11:35:57.958975 DUTY Scan : NO K
7087 11:35:57.961816 ZQ Calibration : PASS
7088 11:35:57.965343 Jitter Meter : NO K
7089 11:35:57.965755 CBT Training : PASS
7090 11:35:57.968558 Write leveling : PASS
7091 11:35:57.972085 RX DQS gating : PASS
7092 11:35:57.972480 RX DQ/DQS(RDDQC) : PASS
7093 11:35:57.975616 TX DQ/DQS : PASS
7094 11:35:57.976279 RX DATLAT : PASS
7095 11:35:57.978661 RX DQ/DQS(Engine): PASS
7096 11:35:57.981630 TX OE : NO K
7097 11:35:57.982026 All Pass.
7098 11:35:57.982414
7099 11:35:57.982786 CH 1, Rank 1
7100 11:35:57.985035 SW Impedance : PASS
7101 11:35:57.988435 DUTY Scan : NO K
7102 11:35:57.988830 ZQ Calibration : PASS
7103 11:35:57.991744 Jitter Meter : NO K
7104 11:35:57.995562 CBT Training : PASS
7105 11:35:57.996045 Write leveling : NO K
7106 11:35:57.998703 RX DQS gating : PASS
7107 11:35:58.001939 RX DQ/DQS(RDDQC) : PASS
7108 11:35:58.002331 TX DQ/DQS : PASS
7109 11:35:58.004936 RX DATLAT : PASS
7110 11:35:58.008542 RX DQ/DQS(Engine): PASS
7111 11:35:58.008936 TX OE : NO K
7112 11:35:58.009365 All Pass.
7113 11:35:58.011701
7114 11:35:58.012093 DramC Write-DBI off
7115 11:35:58.016117 PER_BANK_REFRESH: Hybrid Mode
7116 11:35:58.016592 TX_TRACKING: ON
7117 11:35:58.025666 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 11:35:58.028725 [FAST_K] Save calibration result to emmc
7119 11:35:58.031995 dramc_set_vcore_voltage set vcore to 725000
7120 11:35:58.035545 Read voltage for 1600, 0
7121 11:35:58.035941 Vio18 = 0
7122 11:35:58.038425 Vcore = 725000
7123 11:35:58.038814 Vdram = 0
7124 11:35:58.039207 Vddq = 0
7125 11:35:58.039573 Vmddr = 0
7126 11:35:58.045438 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 11:35:58.051883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 11:35:58.052280 MEM_TYPE=3, freq_sel=13
7129 11:35:58.055509 sv_algorithm_assistance_LP4_3733
7130 11:35:58.058473 ============ PULL DRAM RESETB DOWN ============
7131 11:35:58.065114 ========== PULL DRAM RESETB DOWN end =========
7132 11:35:58.068644 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 11:35:58.072009 ===================================
7134 11:35:58.075576 LPDDR4 DRAM CONFIGURATION
7135 11:35:58.078403 ===================================
7136 11:35:58.078803 EX_ROW_EN[0] = 0x0
7137 11:35:58.081805 EX_ROW_EN[1] = 0x0
7138 11:35:58.082198 LP4Y_EN = 0x0
7139 11:35:58.085306 WORK_FSP = 0x1
7140 11:35:58.085786 WL = 0x5
7141 11:35:58.088337 RL = 0x5
7142 11:35:58.088735 BL = 0x2
7143 11:35:58.092000 RPST = 0x0
7144 11:35:58.092395 RD_PRE = 0x0
7145 11:35:58.094980 WR_PRE = 0x1
7146 11:35:58.098792 WR_PST = 0x1
7147 11:35:58.099266 DBI_WR = 0x0
7148 11:35:58.102067 DBI_RD = 0x0
7149 11:35:58.102461 OTF = 0x1
7150 11:35:58.104888 ===================================
7151 11:35:58.108260 ===================================
7152 11:35:58.108831 ANA top config
7153 11:35:58.111417 ===================================
7154 11:35:58.115568 DLL_ASYNC_EN = 0
7155 11:35:58.118279 ALL_SLAVE_EN = 0
7156 11:35:58.121719 NEW_RANK_MODE = 1
7157 11:35:58.125341 DLL_IDLE_MODE = 1
7158 11:35:58.125806 LP45_APHY_COMB_EN = 1
7159 11:35:58.128509 TX_ODT_DIS = 0
7160 11:35:58.131753 NEW_8X_MODE = 1
7161 11:35:58.135207 ===================================
7162 11:35:58.138496 ===================================
7163 11:35:58.141627 data_rate = 3200
7164 11:35:58.145495 CKR = 1
7165 11:35:58.145891 DQ_P2S_RATIO = 8
7166 11:35:58.148470 ===================================
7167 11:35:58.151671 CA_P2S_RATIO = 8
7168 11:35:58.155160 DQ_CA_OPEN = 0
7169 11:35:58.158700 DQ_SEMI_OPEN = 0
7170 11:35:58.161570 CA_SEMI_OPEN = 0
7171 11:35:58.165210 CA_FULL_RATE = 0
7172 11:35:58.165716 DQ_CKDIV4_EN = 0
7173 11:35:58.168381 CA_CKDIV4_EN = 0
7174 11:35:58.173205 CA_PREDIV_EN = 0
7175 11:35:58.175618 PH8_DLY = 12
7176 11:35:58.178697 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 11:35:58.181759 DQ_AAMCK_DIV = 4
7178 11:35:58.182151 CA_AAMCK_DIV = 4
7179 11:35:58.185337 CA_ADMCK_DIV = 4
7180 11:35:58.188230 DQ_TRACK_CA_EN = 0
7181 11:35:58.191970 CA_PICK = 1600
7182 11:35:58.195057 CA_MCKIO = 1600
7183 11:35:58.198231 MCKIO_SEMI = 0
7184 11:35:58.201531 PLL_FREQ = 3068
7185 11:35:58.202013 DQ_UI_PI_RATIO = 32
7186 11:35:58.204995 CA_UI_PI_RATIO = 0
7187 11:35:58.208887 ===================================
7188 11:35:58.211947 ===================================
7189 11:35:58.215376 memory_type:LPDDR4
7190 11:35:58.219059 GP_NUM : 10
7191 11:35:58.219536 SRAM_EN : 1
7192 11:35:58.222156 MD32_EN : 0
7193 11:35:58.225037 ===================================
7194 11:35:58.225549 [ANA_INIT] >>>>>>>>>>>>>>
7195 11:35:58.228474 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 11:35:58.231872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 11:35:58.235351 ===================================
7198 11:35:58.238664 data_rate = 3200,PCW = 0X7600
7199 11:35:58.241777 ===================================
7200 11:35:58.245551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 11:35:58.251782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 11:35:58.255330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 11:35:58.262188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 11:35:58.264953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 11:35:58.268446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 11:35:58.268985 [ANA_INIT] flow start
7207 11:35:58.271885 [ANA_INIT] PLL >>>>>>>>
7208 11:35:58.275492 [ANA_INIT] PLL <<<<<<<<
7209 11:35:58.278739 [ANA_INIT] MIDPI >>>>>>>>
7210 11:35:58.279209 [ANA_INIT] MIDPI <<<<<<<<
7211 11:35:58.282461 [ANA_INIT] DLL >>>>>>>>
7212 11:35:58.285145 [ANA_INIT] DLL <<<<<<<<
7213 11:35:58.285530 [ANA_INIT] flow end
7214 11:35:58.288970 ============ LP4 DIFF to SE enter ============
7215 11:35:58.295241 ============ LP4 DIFF to SE exit ============
7216 11:35:58.295670 [ANA_INIT] <<<<<<<<<<<<<
7217 11:35:58.299160 [Flow] Enable top DCM control >>>>>
7218 11:35:58.301913 [Flow] Enable top DCM control <<<<<
7219 11:35:58.305140 Enable DLL master slave shuffle
7220 11:35:58.312336 ==============================================================
7221 11:35:58.312735 Gating Mode config
7222 11:35:58.318738 ==============================================================
7223 11:35:58.321745 Config description:
7224 11:35:58.331973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 11:35:58.338648 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 11:35:58.341675 SELPH_MODE 0: By rank 1: By Phase
7227 11:35:58.348728 ==============================================================
7228 11:35:58.351983 GAT_TRACK_EN = 1
7229 11:35:58.352477 RX_GATING_MODE = 2
7230 11:35:58.354803 RX_GATING_TRACK_MODE = 2
7231 11:35:58.358229 SELPH_MODE = 1
7232 11:35:58.362009 PICG_EARLY_EN = 1
7233 11:35:58.365208 VALID_LAT_VALUE = 1
7234 11:35:58.371845 ==============================================================
7235 11:35:58.375063 Enter into Gating configuration >>>>
7236 11:35:58.378272 Exit from Gating configuration <<<<
7237 11:35:58.381918 Enter into DVFS_PRE_config >>>>>
7238 11:35:58.392673 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 11:35:58.395439 Exit from DVFS_PRE_config <<<<<
7240 11:35:58.398645 Enter into PICG configuration >>>>
7241 11:35:58.401646 Exit from PICG configuration <<<<
7242 11:35:58.405071 [RX_INPUT] configuration >>>>>
7243 11:35:58.405538 [RX_INPUT] configuration <<<<<
7244 11:35:58.412049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 11:35:58.418734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 11:35:58.421897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 11:35:58.428438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 11:35:58.435280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 11:35:58.441668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 11:35:58.444924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 11:35:58.448849 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 11:35:58.455052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 11:35:58.459039 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 11:35:58.461812 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 11:35:58.468462 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 11:35:58.471914 ===================================
7257 11:35:58.472382 LPDDR4 DRAM CONFIGURATION
7258 11:35:58.475295 ===================================
7259 11:35:58.478477 EX_ROW_EN[0] = 0x0
7260 11:35:58.478859 EX_ROW_EN[1] = 0x0
7261 11:35:58.481911 LP4Y_EN = 0x0
7262 11:35:58.482287 WORK_FSP = 0x1
7263 11:35:58.485420 WL = 0x5
7264 11:35:58.485798 RL = 0x5
7265 11:35:58.488968 BL = 0x2
7266 11:35:58.489461 RPST = 0x0
7267 11:35:58.491901 RD_PRE = 0x0
7268 11:35:58.492277 WR_PRE = 0x1
7269 11:35:58.495025 WR_PST = 0x1
7270 11:35:58.498782 DBI_WR = 0x0
7271 11:35:58.499243 DBI_RD = 0x0
7272 11:35:58.501934 OTF = 0x1
7273 11:35:58.505289 ===================================
7274 11:35:58.508620 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 11:35:58.512020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 11:35:58.515186 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 11:35:58.519188 ===================================
7278 11:35:58.522797 LPDDR4 DRAM CONFIGURATION
7279 11:35:58.525057 ===================================
7280 11:35:58.528638 EX_ROW_EN[0] = 0x10
7281 11:35:58.529015 EX_ROW_EN[1] = 0x0
7282 11:35:58.531818 LP4Y_EN = 0x0
7283 11:35:58.532194 WORK_FSP = 0x1
7284 11:35:58.535330 WL = 0x5
7285 11:35:58.535797 RL = 0x5
7286 11:35:58.538291 BL = 0x2
7287 11:35:58.538667 RPST = 0x0
7288 11:35:58.541667 RD_PRE = 0x0
7289 11:35:58.542056 WR_PRE = 0x1
7290 11:35:58.545229 WR_PST = 0x1
7291 11:35:58.545639 DBI_WR = 0x0
7292 11:35:58.548471 DBI_RD = 0x0
7293 11:35:58.548864 OTF = 0x1
7294 11:35:58.551517 ===================================
7295 11:35:58.558860 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 11:35:58.559377 ==
7297 11:35:58.561743 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 11:35:58.568843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 11:35:58.569363 ==
7300 11:35:58.569769 [Duty_Offset_Calibration]
7301 11:35:58.572598 B0:2 B1:-1 CA:1
7302 11:35:58.573070
7303 11:35:58.575198 [DutyScan_Calibration_Flow] k_type=0
7304 11:35:58.583472
7305 11:35:58.583868 ==CLK 0==
7306 11:35:58.586895 Final CLK duty delay cell = -4
7307 11:35:58.590365 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7308 11:35:58.593888 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7309 11:35:58.596992 [-4] AVG Duty = 4922%(X100)
7310 11:35:58.597431
7311 11:35:58.600659 CH0 CLK Duty spec in!! Max-Min= 156%
7312 11:35:58.604104 [DutyScan_Calibration_Flow] ====Done====
7313 11:35:58.604496
7314 11:35:58.606974 [DutyScan_Calibration_Flow] k_type=1
7315 11:35:58.623320
7316 11:35:58.623792 ==DQS 0 ==
7317 11:35:58.626221 Final DQS duty delay cell = 0
7318 11:35:58.629997 [0] MAX Duty = 5125%(X100), DQS PI = 20
7319 11:35:58.633391 [0] MIN Duty = 5000%(X100), DQS PI = 16
7320 11:35:58.636649 [0] AVG Duty = 5062%(X100)
7321 11:35:58.637157
7322 11:35:58.637566 ==DQS 1 ==
7323 11:35:58.640154 Final DQS duty delay cell = -4
7324 11:35:58.642998 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7325 11:35:58.646818 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7326 11:35:58.649638 [-4] AVG Duty = 5062%(X100)
7327 11:35:58.650030
7328 11:35:58.653167 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7329 11:35:58.653569
7330 11:35:58.656659 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7331 11:35:58.660230 [DutyScan_Calibration_Flow] ====Done====
7332 11:35:58.660702
7333 11:35:58.663597 [DutyScan_Calibration_Flow] k_type=3
7334 11:35:58.681175
7335 11:35:58.681679 ==DQM 0 ==
7336 11:35:58.684277 Final DQM duty delay cell = 0
7337 11:35:58.687770 [0] MAX Duty = 5000%(X100), DQS PI = 18
7338 11:35:58.690643 [0] MIN Duty = 4875%(X100), DQS PI = 4
7339 11:35:58.691064 [0] AVG Duty = 4937%(X100)
7340 11:35:58.694152
7341 11:35:58.694564 ==DQM 1 ==
7342 11:35:58.697227 Final DQM duty delay cell = 0
7343 11:35:58.700593 [0] MAX Duty = 5218%(X100), DQS PI = 58
7344 11:35:58.703998 [0] MIN Duty = 4969%(X100), DQS PI = 20
7345 11:35:58.704377 [0] AVG Duty = 5093%(X100)
7346 11:35:58.707477
7347 11:35:58.710241 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7348 11:35:58.710618
7349 11:35:58.713611 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7350 11:35:58.717376 [DutyScan_Calibration_Flow] ====Done====
7351 11:35:58.717753
7352 11:35:58.721108 [DutyScan_Calibration_Flow] k_type=2
7353 11:35:58.737494
7354 11:35:58.737963 ==DQ 0 ==
7355 11:35:58.741074 Final DQ duty delay cell = 0
7356 11:35:58.744127 [0] MAX Duty = 5156%(X100), DQS PI = 0
7357 11:35:58.747833 [0] MIN Duty = 5031%(X100), DQS PI = 4
7358 11:35:58.748214 [0] AVG Duty = 5093%(X100)
7359 11:35:58.748509
7360 11:35:58.750714 ==DQ 1 ==
7361 11:35:58.754526 Final DQ duty delay cell = 0
7362 11:35:58.757917 [0] MAX Duty = 5031%(X100), DQS PI = 14
7363 11:35:58.761108 [0] MIN Duty = 4907%(X100), DQS PI = 18
7364 11:35:58.761524 [0] AVG Duty = 4969%(X100)
7365 11:35:58.761822
7366 11:35:58.764124 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7367 11:35:58.764501
7368 11:35:58.767981 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7369 11:35:58.774546 [DutyScan_Calibration_Flow] ====Done====
7370 11:35:58.774892 ==
7371 11:35:58.777847 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 11:35:58.781035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 11:35:58.781428 ==
7374 11:35:58.784258 [Duty_Offset_Calibration]
7375 11:35:58.784528 B0:1 B1:1 CA:2
7376 11:35:58.784740
7377 11:35:58.787537 [DutyScan_Calibration_Flow] k_type=0
7378 11:35:58.797615
7379 11:35:58.797881 ==CLK 0==
7380 11:35:58.801476 Final CLK duty delay cell = 0
7381 11:35:58.804089 [0] MAX Duty = 5156%(X100), DQS PI = 24
7382 11:35:58.808079 [0] MIN Duty = 4938%(X100), DQS PI = 50
7383 11:35:58.808542 [0] AVG Duty = 5047%(X100)
7384 11:35:58.810932
7385 11:35:58.814198 CH1 CLK Duty spec in!! Max-Min= 218%
7386 11:35:58.817568 [DutyScan_Calibration_Flow] ====Done====
7387 11:35:58.817952
7388 11:35:58.820936 [DutyScan_Calibration_Flow] k_type=1
7389 11:35:58.837741
7390 11:35:58.838183 ==DQS 0 ==
7391 11:35:58.841247 Final DQS duty delay cell = 0
7392 11:35:58.844056 [0] MAX Duty = 5031%(X100), DQS PI = 20
7393 11:35:58.847802 [0] MIN Duty = 4813%(X100), DQS PI = 50
7394 11:35:58.848189 [0] AVG Duty = 4922%(X100)
7395 11:35:58.850795
7396 11:35:58.851187 ==DQS 1 ==
7397 11:35:58.854424 Final DQS duty delay cell = 0
7398 11:35:58.857857 [0] MAX Duty = 5031%(X100), DQS PI = 34
7399 11:35:58.861353 [0] MIN Duty = 4938%(X100), DQS PI = 14
7400 11:35:58.861814 [0] AVG Duty = 4984%(X100)
7401 11:35:58.864331
7402 11:35:58.867329 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7403 11:35:58.867827
7404 11:35:58.871149 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7405 11:35:58.874145 [DutyScan_Calibration_Flow] ====Done====
7406 11:35:58.874573
7407 11:35:58.877236 [DutyScan_Calibration_Flow] k_type=3
7408 11:35:58.894726
7409 11:35:58.895131 ==DQM 0 ==
7410 11:35:58.897680 Final DQM duty delay cell = 0
7411 11:35:58.901209 [0] MAX Duty = 5156%(X100), DQS PI = 20
7412 11:35:58.904370 [0] MIN Duty = 4844%(X100), DQS PI = 50
7413 11:35:58.905060 [0] AVG Duty = 5000%(X100)
7414 11:35:58.907477
7415 11:35:58.907850 ==DQM 1 ==
7416 11:35:58.911435 Final DQM duty delay cell = 0
7417 11:35:58.914334 [0] MAX Duty = 5125%(X100), DQS PI = 10
7418 11:35:58.917767 [0] MIN Duty = 4907%(X100), DQS PI = 18
7419 11:35:58.918143 [0] AVG Duty = 5016%(X100)
7420 11:35:58.920763
7421 11:35:58.924274 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7422 11:35:58.924716
7423 11:35:58.928084 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7424 11:35:58.931202 [DutyScan_Calibration_Flow] ====Done====
7425 11:35:58.931587
7426 11:35:58.934091 [DutyScan_Calibration_Flow] k_type=2
7427 11:35:58.951461
7428 11:35:58.952115 ==DQ 0 ==
7429 11:35:58.954504 Final DQ duty delay cell = 0
7430 11:35:58.957836 [0] MAX Duty = 5125%(X100), DQS PI = 20
7431 11:35:58.961211 [0] MIN Duty = 4907%(X100), DQS PI = 52
7432 11:35:58.961592 [0] AVG Duty = 5016%(X100)
7433 11:35:58.964821
7434 11:35:58.965246 ==DQ 1 ==
7435 11:35:58.968062 Final DQ duty delay cell = 0
7436 11:35:58.971722 [0] MAX Duty = 5093%(X100), DQS PI = 8
7437 11:35:58.974596 [0] MIN Duty = 5031%(X100), DQS PI = 0
7438 11:35:58.975006 [0] AVG Duty = 5062%(X100)
7439 11:35:58.975313
7440 11:35:58.977950 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7441 11:35:58.978328
7442 11:35:58.981364 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7443 11:35:58.988296 [DutyScan_Calibration_Flow] ====Done====
7444 11:35:58.991385 nWR fixed to 30
7445 11:35:58.991771 [ModeRegInit_LP4] CH0 RK0
7446 11:35:58.994396 [ModeRegInit_LP4] CH0 RK1
7447 11:35:58.998111 [ModeRegInit_LP4] CH1 RK0
7448 11:35:58.998494 [ModeRegInit_LP4] CH1 RK1
7449 11:35:59.001303 match AC timing 5
7450 11:35:59.004591 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 11:35:59.007694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 11:35:59.014970 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 11:35:59.017968 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 11:35:59.024824 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 11:35:59.025309 [MiockJmeterHQA]
7456 11:35:59.025609
7457 11:35:59.028243 [DramcMiockJmeter] u1RxGatingPI = 0
7458 11:35:59.030999 0 : 4253, 4026
7459 11:35:59.031395 4 : 4363, 4138
7460 11:35:59.031698 8 : 4252, 4027
7461 11:35:59.034766 12 : 4363, 4137
7462 11:35:59.035224 16 : 4253, 4026
7463 11:35:59.037961 20 : 4252, 4027
7464 11:35:59.038344 24 : 4252, 4027
7465 11:35:59.038644 28 : 4252, 4029
7466 11:35:59.041027 32 : 4361, 4137
7467 11:35:59.041515 36 : 4253, 4027
7468 11:35:59.044946 40 : 4250, 4026
7469 11:35:59.045542 44 : 4252, 4027
7470 11:35:59.048264 48 : 4252, 4029
7471 11:35:59.048644 52 : 4250, 4026
7472 11:35:59.051557 56 : 4363, 4140
7473 11:35:59.051942 60 : 4360, 4137
7474 11:35:59.052243 64 : 4250, 4027
7475 11:35:59.054551 68 : 4250, 4027
7476 11:35:59.054935 72 : 4250, 4026
7477 11:35:59.057825 76 : 4250, 4027
7478 11:35:59.058211 80 : 4252, 4029
7479 11:35:59.061189 84 : 4360, 4138
7480 11:35:59.061574 88 : 4250, 4027
7481 11:35:59.065041 92 : 4250, 4027
7482 11:35:59.065545 96 : 4250, 3437
7483 11:35:59.065849 100 : 4252, 0
7484 11:35:59.067915 104 : 4250, 0
7485 11:35:59.068300 108 : 4253, 0
7486 11:35:59.068626 112 : 4252, 0
7487 11:35:59.071711 116 : 4360, 0
7488 11:35:59.072169 120 : 4360, 0
7489 11:35:59.075404 124 : 4363, 0
7490 11:35:59.075878 128 : 4250, 0
7491 11:35:59.076189 132 : 4250, 0
7492 11:35:59.078385 136 : 4250, 0
7493 11:35:59.078783 140 : 4250, 0
7494 11:35:59.081575 144 : 4250, 0
7495 11:35:59.081990 148 : 4250, 0
7496 11:35:59.082303 152 : 4252, 0
7497 11:35:59.085214 156 : 4250, 0
7498 11:35:59.085596 160 : 4250, 0
7499 11:35:59.089328 164 : 4253, 0
7500 11:35:59.089713 168 : 4360, 0
7501 11:35:59.090012 172 : 4361, 0
7502 11:35:59.091580 176 : 4363, 0
7503 11:35:59.091976 180 : 4250, 0
7504 11:35:59.092279 184 : 4250, 0
7505 11:35:59.094675 188 : 4250, 0
7506 11:35:59.095059 192 : 4250, 0
7507 11:35:59.098499 196 : 4250, 0
7508 11:35:59.098882 200 : 4250, 0
7509 11:35:59.099180 204 : 4250, 0
7510 11:35:59.101671 208 : 4250, 0
7511 11:35:59.102055 212 : 4250, 60
7512 11:35:59.104925 216 : 4250, 3618
7513 11:35:59.105415 220 : 4363, 4140
7514 11:35:59.108183 224 : 4252, 4029
7515 11:35:59.108593 228 : 4250, 4027
7516 11:35:59.111377 232 : 4250, 4027
7517 11:35:59.111898 236 : 4253, 4030
7518 11:35:59.112263 240 : 4250, 4027
7519 11:35:59.114700 244 : 4250, 4027
7520 11:35:59.115084 248 : 4360, 4138
7521 11:35:59.118421 252 : 4250, 4026
7522 11:35:59.118806 256 : 4250, 4027
7523 11:35:59.121687 260 : 4360, 4137
7524 11:35:59.122072 264 : 4250, 4027
7525 11:35:59.125144 268 : 4250, 4027
7526 11:35:59.125543 272 : 4363, 4140
7527 11:35:59.128013 276 : 4250, 4027
7528 11:35:59.128396 280 : 4250, 4027
7529 11:35:59.131452 284 : 4252, 4030
7530 11:35:59.131914 288 : 4252, 4030
7531 11:35:59.132229 292 : 4250, 4027
7532 11:35:59.134959 296 : 4250, 4027
7533 11:35:59.135344 300 : 4360, 4138
7534 11:35:59.138470 304 : 4249, 4027
7535 11:35:59.138854 308 : 4250, 4027
7536 11:35:59.141381 312 : 4360, 4138
7537 11:35:59.141765 316 : 4250, 4027
7538 11:35:59.144831 320 : 4250, 4027
7539 11:35:59.145259 324 : 4363, 4139
7540 11:35:59.148050 328 : 4250, 4027
7541 11:35:59.148444 332 : 4250, 2825
7542 11:35:59.152256 336 : 4250, 28
7543 11:35:59.152709
7544 11:35:59.153007 MIOCK jitter meter ch=0
7545 11:35:59.153341
7546 11:35:59.155012 1T = (336-100) = 236 dly cells
7547 11:35:59.161811 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7548 11:35:59.162249 ==
7549 11:35:59.165047 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 11:35:59.168903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 11:35:59.169451 ==
7552 11:35:59.175180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 11:35:59.178693 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 11:35:59.181623 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 11:35:59.188611 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 11:35:59.197455 [CA 0] Center 44 (14~75) winsize 62
7557 11:35:59.201036 [CA 1] Center 44 (13~75) winsize 63
7558 11:35:59.204632 [CA 2] Center 40 (11~69) winsize 59
7559 11:35:59.207994 [CA 3] Center 39 (10~69) winsize 60
7560 11:35:59.211214 [CA 4] Center 37 (8~67) winsize 60
7561 11:35:59.214282 [CA 5] Center 37 (7~67) winsize 61
7562 11:35:59.214700
7563 11:35:59.217647 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 11:35:59.218101
7565 11:35:59.221235 [CATrainingPosCal] consider 1 rank data
7566 11:35:59.224354 u2DelayCellTimex100 = 275/100 ps
7567 11:35:59.227839 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7568 11:35:59.234247 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7569 11:35:59.238063 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7570 11:35:59.240887 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7571 11:35:59.245253 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7572 11:35:59.247613 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7573 11:35:59.248069
7574 11:35:59.251354 CA PerBit enable=1, Macro0, CA PI delay=37
7575 11:35:59.251824
7576 11:35:59.255019 [CBTSetCACLKResult] CA Dly = 37
7577 11:35:59.257615 CS Dly: 10 (0~41)
7578 11:35:59.261261 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 11:35:59.264582 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 11:35:59.265179 ==
7581 11:35:59.267540 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 11:35:59.271455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 11:35:59.274452 ==
7584 11:35:59.277865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 11:35:59.281514 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 11:35:59.288014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 11:35:59.291512 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 11:35:59.301676 [CA 0] Center 44 (14~75) winsize 62
7589 11:35:59.304864 [CA 1] Center 44 (14~75) winsize 62
7590 11:35:59.307864 [CA 2] Center 40 (11~69) winsize 59
7591 11:35:59.311525 [CA 3] Center 39 (10~69) winsize 60
7592 11:35:59.314715 [CA 4] Center 37 (8~67) winsize 60
7593 11:35:59.317980 [CA 5] Center 37 (7~67) winsize 61
7594 11:35:59.318489
7595 11:35:59.321622 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 11:35:59.322004
7597 11:35:59.324554 [CATrainingPosCal] consider 2 rank data
7598 11:35:59.327756 u2DelayCellTimex100 = 275/100 ps
7599 11:35:59.334421 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7600 11:35:59.338202 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7601 11:35:59.341208 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7602 11:35:59.344482 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7603 11:35:59.347796 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7604 11:35:59.351148 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7605 11:35:59.351526
7606 11:35:59.354799 CA PerBit enable=1, Macro0, CA PI delay=37
7607 11:35:59.355175
7608 11:35:59.357987 [CBTSetCACLKResult] CA Dly = 37
7609 11:35:59.361268 CS Dly: 11 (0~44)
7610 11:35:59.364738 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 11:35:59.368069 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 11:35:59.368568
7613 11:35:59.371205 ----->DramcWriteLeveling(PI) begin...
7614 11:35:59.371587 ==
7615 11:35:59.374736 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 11:35:59.381407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:35:59.381791 ==
7618 11:35:59.384677 Write leveling (Byte 0): 33 => 33
7619 11:35:59.387613 Write leveling (Byte 1): 29 => 29
7620 11:35:59.387994 DramcWriteLeveling(PI) end<-----
7621 11:35:59.388290
7622 11:35:59.391152 ==
7623 11:35:59.391596 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 11:35:59.398329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 11:35:59.398712 ==
7626 11:35:59.401053 [Gating] SW mode calibration
7627 11:35:59.407857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 11:35:59.411430 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 11:35:59.417820 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:35:59.421707 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:35:59.424741 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 11:35:59.431369 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:35:59.434715 1 4 16 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7634 11:35:59.437763 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7635 11:35:59.444365 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7636 11:35:59.447637 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:35:59.451625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 11:35:59.454345 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:35:59.461755 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 11:35:59.464320 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7641 11:35:59.468150 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7642 11:35:59.474782 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7643 11:35:59.478053 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7644 11:35:59.481054 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 11:35:59.487708 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:35:59.491404 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:35:59.495102 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:35:59.501763 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 11:35:59.504732 1 6 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7650 11:35:59.507967 1 6 20 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
7651 11:35:59.514651 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7652 11:35:59.518064 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:35:59.521558 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:35:59.528182 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:35:59.531727 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 11:35:59.534492 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 11:35:59.538034 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7658 11:35:59.544921 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 11:35:59.548015 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7660 11:35:59.551575 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:35:59.558820 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:35:59.561520 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:35:59.564853 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:35:59.571511 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:35:59.574741 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:35:59.578345 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:35:59.585047 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:35:59.588028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:35:59.591413 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:35:59.598315 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:35:59.601225 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:35:59.605228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:35:59.611768 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 11:35:59.614969 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7675 11:35:59.618596 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 11:35:59.621602 Total UI for P1: 0, mck2ui 16
7677 11:35:59.625111 best dqsien dly found for B0: ( 1, 9, 18)
7678 11:35:59.628371 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 11:35:59.631399 Total UI for P1: 0, mck2ui 16
7680 11:35:59.635149 best dqsien dly found for B1: ( 1, 9, 22)
7681 11:35:59.639023 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7682 11:35:59.641387 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7683 11:35:59.641767
7684 11:35:59.648817 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7685 11:35:59.651602 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7686 11:35:59.655116 [Gating] SW calibration Done
7687 11:35:59.655495 ==
7688 11:35:59.658245 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 11:35:59.662056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 11:35:59.662554 ==
7691 11:35:59.662883 RX Vref Scan: 0
7692 11:35:59.663184
7693 11:35:59.665488 RX Vref 0 -> 0, step: 1
7694 11:35:59.665979
7695 11:35:59.668159 RX Delay 0 -> 252, step: 8
7696 11:35:59.671636 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7697 11:35:59.674808 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7698 11:35:59.678906 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7699 11:35:59.684928 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7700 11:35:59.688701 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7701 11:35:59.691929 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7702 11:35:59.694793 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7703 11:35:59.698729 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7704 11:35:59.704765 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7705 11:35:59.708308 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7706 11:35:59.711641 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7707 11:35:59.714832 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7708 11:35:59.718167 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7709 11:35:59.725436 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7710 11:35:59.728240 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7711 11:35:59.731953 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7712 11:35:59.732410 ==
7713 11:35:59.735278 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:35:59.738841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:35:59.739235 ==
7716 11:35:59.741888 DQS Delay:
7717 11:35:59.742284 DQS0 = 0, DQS1 = 0
7718 11:35:59.745007 DQM Delay:
7719 11:35:59.745442 DQM0 = 132, DQM1 = 125
7720 11:35:59.748445 DQ Delay:
7721 11:35:59.751774 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7722 11:35:59.755010 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7723 11:35:59.758375 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7724 11:35:59.761808 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7725 11:35:59.762262
7726 11:35:59.762557
7727 11:35:59.762824 ==
7728 11:35:59.765513 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 11:35:59.768680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 11:35:59.769410 ==
7731 11:35:59.769777
7732 11:35:59.770313
7733 11:35:59.771770 TX Vref Scan disable
7734 11:35:59.774754 == TX Byte 0 ==
7735 11:35:59.778583 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7736 11:35:59.781810 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7737 11:35:59.784963 == TX Byte 1 ==
7738 11:35:59.789330 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7739 11:35:59.791867 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7740 11:35:59.792284 ==
7741 11:35:59.795280 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 11:35:59.798510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 11:35:59.801443 ==
7744 11:35:59.814733
7745 11:35:59.818001 TX Vref early break, caculate TX vref
7746 11:35:59.821040 TX Vref=16, minBit 4, minWin=21, winSum=367
7747 11:35:59.824220 TX Vref=18, minBit 0, minWin=22, winSum=378
7748 11:35:59.828181 TX Vref=20, minBit 0, minWin=23, winSum=387
7749 11:35:59.831037 TX Vref=22, minBit 0, minWin=24, winSum=401
7750 11:35:59.834520 TX Vref=24, minBit 0, minWin=24, winSum=404
7751 11:35:59.841034 TX Vref=26, minBit 0, minWin=25, winSum=418
7752 11:35:59.844930 TX Vref=28, minBit 4, minWin=25, winSum=426
7753 11:35:59.847869 TX Vref=30, minBit 4, minWin=25, winSum=424
7754 11:35:59.851515 TX Vref=32, minBit 4, minWin=24, winSum=413
7755 11:35:59.854324 TX Vref=34, minBit 0, minWin=24, winSum=409
7756 11:35:59.857756 TX Vref=36, minBit 3, minWin=23, winSum=393
7757 11:35:59.864263 [TxChooseVref] Worse bit 4, Min win 25, Win sum 426, Final Vref 28
7758 11:35:59.864708
7759 11:35:59.867908 Final TX Range 0 Vref 28
7760 11:35:59.868446
7761 11:35:59.868773 ==
7762 11:35:59.871380 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 11:35:59.874378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 11:35:59.874794 ==
7765 11:35:59.875179
7766 11:35:59.875624
7767 11:35:59.878070 TX Vref Scan disable
7768 11:35:59.884530 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7769 11:35:59.884910 == TX Byte 0 ==
7770 11:35:59.888478 u2DelayCellOfst[0]=14 cells (4 PI)
7771 11:35:59.891216 u2DelayCellOfst[1]=17 cells (5 PI)
7772 11:35:59.894864 u2DelayCellOfst[2]=14 cells (4 PI)
7773 11:35:59.897969 u2DelayCellOfst[3]=14 cells (4 PI)
7774 11:35:59.901244 u2DelayCellOfst[4]=10 cells (3 PI)
7775 11:35:59.904451 u2DelayCellOfst[5]=0 cells (0 PI)
7776 11:35:59.908394 u2DelayCellOfst[6]=21 cells (6 PI)
7777 11:35:59.911009 u2DelayCellOfst[7]=17 cells (5 PI)
7778 11:35:59.914619 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7779 11:35:59.917860 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7780 11:35:59.921571 == TX Byte 1 ==
7781 11:35:59.922030 u2DelayCellOfst[8]=0 cells (0 PI)
7782 11:35:59.924475 u2DelayCellOfst[9]=0 cells (0 PI)
7783 11:35:59.927953 u2DelayCellOfst[10]=7 cells (2 PI)
7784 11:35:59.931361 u2DelayCellOfst[11]=0 cells (0 PI)
7785 11:35:59.934873 u2DelayCellOfst[12]=10 cells (3 PI)
7786 11:35:59.938023 u2DelayCellOfst[13]=10 cells (3 PI)
7787 11:35:59.941499 u2DelayCellOfst[14]=10 cells (3 PI)
7788 11:35:59.945001 u2DelayCellOfst[15]=10 cells (3 PI)
7789 11:35:59.948155 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7790 11:35:59.954487 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7791 11:35:59.954965 DramC Write-DBI on
7792 11:35:59.955289 ==
7793 11:35:59.958175 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 11:35:59.961387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 11:35:59.961833 ==
7796 11:35:59.964683
7797 11:35:59.965054
7798 11:35:59.965381 TX Vref Scan disable
7799 11:35:59.967693 == TX Byte 0 ==
7800 11:35:59.971089 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7801 11:35:59.975069 == TX Byte 1 ==
7802 11:35:59.977771 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7803 11:35:59.978151 DramC Write-DBI off
7804 11:35:59.981229
7805 11:35:59.981660 [DATLAT]
7806 11:35:59.981952 Freq=1600, CH0 RK0
7807 11:35:59.982229
7808 11:35:59.985020 DATLAT Default: 0xf
7809 11:35:59.985424 0, 0xFFFF, sum = 0
7810 11:35:59.988504 1, 0xFFFF, sum = 0
7811 11:35:59.988973 2, 0xFFFF, sum = 0
7812 11:35:59.991423 3, 0xFFFF, sum = 0
7813 11:35:59.991813 4, 0xFFFF, sum = 0
7814 11:35:59.994976 5, 0xFFFF, sum = 0
7815 11:35:59.998528 6, 0xFFFF, sum = 0
7816 11:35:59.998959 7, 0xFFFF, sum = 0
7817 11:36:00.001675 8, 0xFFFF, sum = 0
7818 11:36:00.002182 9, 0xFFFF, sum = 0
7819 11:36:00.005086 10, 0xFFFF, sum = 0
7820 11:36:00.005546 11, 0xFFFF, sum = 0
7821 11:36:00.007885 12, 0xFFFF, sum = 0
7822 11:36:00.008309 13, 0xFFFF, sum = 0
7823 11:36:00.011542 14, 0x0, sum = 1
7824 11:36:00.012004 15, 0x0, sum = 2
7825 11:36:00.014759 16, 0x0, sum = 3
7826 11:36:00.015309 17, 0x0, sum = 4
7827 11:36:00.018009 best_step = 15
7828 11:36:00.018414
7829 11:36:00.018805 ==
7830 11:36:00.021186 Dram Type= 6, Freq= 0, CH_0, rank 0
7831 11:36:00.024922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7832 11:36:00.025447 ==
7833 11:36:00.025751 RX Vref Scan: 1
7834 11:36:00.026028
7835 11:36:00.027976 Set Vref Range= 24 -> 127
7836 11:36:00.028421
7837 11:36:00.031473 RX Vref 24 -> 127, step: 1
7838 11:36:00.031853
7839 11:36:00.034429 RX Delay 11 -> 252, step: 4
7840 11:36:00.034807
7841 11:36:00.038355 Set Vref, RX VrefLevel [Byte0]: 24
7842 11:36:00.041265 [Byte1]: 24
7843 11:36:00.041652
7844 11:36:00.044324 Set Vref, RX VrefLevel [Byte0]: 25
7845 11:36:00.047810 [Byte1]: 25
7846 11:36:00.048222
7847 11:36:00.051423 Set Vref, RX VrefLevel [Byte0]: 26
7848 11:36:00.054760 [Byte1]: 26
7849 11:36:00.058137
7850 11:36:00.058512 Set Vref, RX VrefLevel [Byte0]: 27
7851 11:36:00.061792 [Byte1]: 27
7852 11:36:00.066209
7853 11:36:00.066699 Set Vref, RX VrefLevel [Byte0]: 28
7854 11:36:00.069826 [Byte1]: 28
7855 11:36:00.073302
7856 11:36:00.073726 Set Vref, RX VrefLevel [Byte0]: 29
7857 11:36:00.076693 [Byte1]: 29
7858 11:36:00.081222
7859 11:36:00.081644 Set Vref, RX VrefLevel [Byte0]: 30
7860 11:36:00.084551 [Byte1]: 30
7861 11:36:00.089093
7862 11:36:00.089592 Set Vref, RX VrefLevel [Byte0]: 31
7863 11:36:00.092423 [Byte1]: 31
7864 11:36:00.096669
7865 11:36:00.097183 Set Vref, RX VrefLevel [Byte0]: 32
7866 11:36:00.099615 [Byte1]: 32
7867 11:36:00.104183
7868 11:36:00.104674 Set Vref, RX VrefLevel [Byte0]: 33
7869 11:36:00.107528 [Byte1]: 33
7870 11:36:00.112642
7871 11:36:00.113158 Set Vref, RX VrefLevel [Byte0]: 34
7872 11:36:00.115360 [Byte1]: 34
7873 11:36:00.119082
7874 11:36:00.119500 Set Vref, RX VrefLevel [Byte0]: 35
7875 11:36:00.122790 [Byte1]: 35
7876 11:36:00.127075
7877 11:36:00.127566 Set Vref, RX VrefLevel [Byte0]: 36
7878 11:36:00.130010 [Byte1]: 36
7879 11:36:00.134653
7880 11:36:00.135153 Set Vref, RX VrefLevel [Byte0]: 37
7881 11:36:00.137571 [Byte1]: 37
7882 11:36:00.142187
7883 11:36:00.142649 Set Vref, RX VrefLevel [Byte0]: 38
7884 11:36:00.145189 [Byte1]: 38
7885 11:36:00.149935
7886 11:36:00.150469 Set Vref, RX VrefLevel [Byte0]: 39
7887 11:36:00.153274 [Byte1]: 39
7888 11:36:00.157656
7889 11:36:00.158074 Set Vref, RX VrefLevel [Byte0]: 40
7890 11:36:00.160878 [Byte1]: 40
7891 11:36:00.164710
7892 11:36:00.165082 Set Vref, RX VrefLevel [Byte0]: 41
7893 11:36:00.168420 [Byte1]: 41
7894 11:36:00.172428
7895 11:36:00.172848 Set Vref, RX VrefLevel [Byte0]: 42
7896 11:36:00.176202 [Byte1]: 42
7897 11:36:00.180309
7898 11:36:00.180893 Set Vref, RX VrefLevel [Byte0]: 43
7899 11:36:00.183532 [Byte1]: 43
7900 11:36:00.188100
7901 11:36:00.188564 Set Vref, RX VrefLevel [Byte0]: 44
7902 11:36:00.191052 [Byte1]: 44
7903 11:36:00.195460
7904 11:36:00.195873 Set Vref, RX VrefLevel [Byte0]: 45
7905 11:36:00.198448 [Byte1]: 45
7906 11:36:00.203022
7907 11:36:00.203472 Set Vref, RX VrefLevel [Byte0]: 46
7908 11:36:00.206368 [Byte1]: 46
7909 11:36:00.211167
7910 11:36:00.211656 Set Vref, RX VrefLevel [Byte0]: 47
7911 11:36:00.213714 [Byte1]: 47
7912 11:36:00.218136
7913 11:36:00.218601 Set Vref, RX VrefLevel [Byte0]: 48
7914 11:36:00.221157 [Byte1]: 48
7915 11:36:00.226186
7916 11:36:00.226644 Set Vref, RX VrefLevel [Byte0]: 49
7917 11:36:00.229302 [Byte1]: 49
7918 11:36:00.233814
7919 11:36:00.234230 Set Vref, RX VrefLevel [Byte0]: 50
7920 11:36:00.236633 [Byte1]: 50
7921 11:36:00.241378
7922 11:36:00.244859 Set Vref, RX VrefLevel [Byte0]: 51
7923 11:36:00.245392 [Byte1]: 51
7924 11:36:00.248741
7925 11:36:00.249279 Set Vref, RX VrefLevel [Byte0]: 52
7926 11:36:00.252031 [Byte1]: 52
7927 11:36:00.256782
7928 11:36:00.257224 Set Vref, RX VrefLevel [Byte0]: 53
7929 11:36:00.259637 [Byte1]: 53
7930 11:36:00.264485
7931 11:36:00.264977 Set Vref, RX VrefLevel [Byte0]: 54
7932 11:36:00.267199 [Byte1]: 54
7933 11:36:00.271833
7934 11:36:00.272248 Set Vref, RX VrefLevel [Byte0]: 55
7935 11:36:00.274683 [Byte1]: 55
7936 11:36:00.279372
7937 11:36:00.279744 Set Vref, RX VrefLevel [Byte0]: 56
7938 11:36:00.282215 [Byte1]: 56
7939 11:36:00.286620
7940 11:36:00.287072 Set Vref, RX VrefLevel [Byte0]: 57
7941 11:36:00.289773 [Byte1]: 57
7942 11:36:00.294262
7943 11:36:00.294680 Set Vref, RX VrefLevel [Byte0]: 58
7944 11:36:00.297882 [Byte1]: 58
7945 11:36:00.301939
7946 11:36:00.302320 Set Vref, RX VrefLevel [Byte0]: 59
7947 11:36:00.305185 [Byte1]: 59
7948 11:36:00.309887
7949 11:36:00.310323 Set Vref, RX VrefLevel [Byte0]: 60
7950 11:36:00.312904 [Byte1]: 60
7951 11:36:00.317082
7952 11:36:00.317547 Set Vref, RX VrefLevel [Byte0]: 61
7953 11:36:00.320411 [Byte1]: 61
7954 11:36:00.324797
7955 11:36:00.325327 Set Vref, RX VrefLevel [Byte0]: 62
7956 11:36:00.328282 [Byte1]: 62
7957 11:36:00.332424
7958 11:36:00.332800 Set Vref, RX VrefLevel [Byte0]: 63
7959 11:36:00.335636 [Byte1]: 63
7960 11:36:00.340199
7961 11:36:00.340571 Set Vref, RX VrefLevel [Byte0]: 64
7962 11:36:00.343257 [Byte1]: 64
7963 11:36:00.347790
7964 11:36:00.348163 Set Vref, RX VrefLevel [Byte0]: 65
7965 11:36:00.350649 [Byte1]: 65
7966 11:36:00.355568
7967 11:36:00.356050 Set Vref, RX VrefLevel [Byte0]: 66
7968 11:36:00.358305 [Byte1]: 66
7969 11:36:00.362867
7970 11:36:00.363459 Set Vref, RX VrefLevel [Byte0]: 67
7971 11:36:00.365964 [Byte1]: 67
7972 11:36:00.370420
7973 11:36:00.370864 Set Vref, RX VrefLevel [Byte0]: 68
7974 11:36:00.373595 [Byte1]: 68
7975 11:36:00.378829
7976 11:36:00.379321 Set Vref, RX VrefLevel [Byte0]: 69
7977 11:36:00.381223 [Byte1]: 69
7978 11:36:00.385965
7979 11:36:00.386548 Set Vref, RX VrefLevel [Byte0]: 70
7980 11:36:00.389424 [Byte1]: 70
7981 11:36:00.393390
7982 11:36:00.393806 Set Vref, RX VrefLevel [Byte0]: 71
7983 11:36:00.396802 [Byte1]: 71
7984 11:36:00.400833
7985 11:36:00.401366 Set Vref, RX VrefLevel [Byte0]: 72
7986 11:36:00.404329 [Byte1]: 72
7987 11:36:00.408476
7988 11:36:00.408893 Set Vref, RX VrefLevel [Byte0]: 73
7989 11:36:00.412094 [Byte1]: 73
7990 11:36:00.416373
7991 11:36:00.416863 Set Vref, RX VrefLevel [Byte0]: 74
7992 11:36:00.419376 [Byte1]: 74
7993 11:36:00.424337
7994 11:36:00.424830 Set Vref, RX VrefLevel [Byte0]: 75
7995 11:36:00.427603 [Byte1]: 75
7996 11:36:00.431613
7997 11:36:00.432106 Final RX Vref Byte 0 = 57 to rank0
7998 11:36:00.435390 Final RX Vref Byte 1 = 63 to rank0
7999 11:36:00.437944 Final RX Vref Byte 0 = 57 to rank1
8000 11:36:00.441327 Final RX Vref Byte 1 = 63 to rank1==
8001 11:36:00.444582 Dram Type= 6, Freq= 0, CH_0, rank 0
8002 11:36:00.451383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 11:36:00.451806 ==
8004 11:36:00.452131 DQS Delay:
8005 11:36:00.452430 DQS0 = 0, DQS1 = 0
8006 11:36:00.454722 DQM Delay:
8007 11:36:00.455199 DQM0 = 128, DQM1 = 122
8008 11:36:00.457889 DQ Delay:
8009 11:36:00.461535 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =124
8010 11:36:00.465056 DQ4 =132, DQ5 =116, DQ6 =136, DQ7 =136
8011 11:36:00.468289 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8012 11:36:00.471849 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
8013 11:36:00.472410
8014 11:36:00.472745
8015 11:36:00.473045
8016 11:36:00.474640 [DramC_TX_OE_Calibration] TA2
8017 11:36:00.477765 Original DQ_B0 (3 6) =30, OEN = 27
8018 11:36:00.481258 Original DQ_B1 (3 6) =30, OEN = 27
8019 11:36:00.484891 24, 0x0, End_B0=24 End_B1=24
8020 11:36:00.485447 25, 0x0, End_B0=25 End_B1=25
8021 11:36:00.488502 26, 0x0, End_B0=26 End_B1=26
8022 11:36:00.491122 27, 0x0, End_B0=27 End_B1=27
8023 11:36:00.495124 28, 0x0, End_B0=28 End_B1=28
8024 11:36:00.495550 29, 0x0, End_B0=29 End_B1=29
8025 11:36:00.497824 30, 0x0, End_B0=30 End_B1=30
8026 11:36:00.501511 31, 0x4141, End_B0=30 End_B1=30
8027 11:36:00.504836 Byte0 end_step=30 best_step=27
8028 11:36:00.507787 Byte1 end_step=30 best_step=27
8029 11:36:00.511222 Byte0 TX OE(2T, 0.5T) = (3, 3)
8030 11:36:00.511640 Byte1 TX OE(2T, 0.5T) = (3, 3)
8031 11:36:00.512017
8032 11:36:00.514794
8033 11:36:00.522192 [DQSOSCAuto] RK0, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8034 11:36:00.525080 CH0 RK0: MR19=303, MR18=160B
8035 11:36:00.531506 CH0_RK0: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8036 11:36:00.532001
8037 11:36:00.534772 ----->DramcWriteLeveling(PI) begin...
8038 11:36:00.535213 ==
8039 11:36:00.538049 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 11:36:00.541845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 11:36:00.542342 ==
8042 11:36:00.545400 Write leveling (Byte 0): 33 => 33
8043 11:36:00.548489 Write leveling (Byte 1): 27 => 27
8044 11:36:00.551802 DramcWriteLeveling(PI) end<-----
8045 11:36:00.552291
8046 11:36:00.552616 ==
8047 11:36:00.555129 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:36:00.558523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:36:00.558944 ==
8050 11:36:00.562309 [Gating] SW mode calibration
8051 11:36:00.568488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 11:36:00.574917 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8053 11:36:00.578387 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 11:36:00.581965 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:36:00.585390 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8056 11:36:00.591947 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8057 11:36:00.595027 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8058 11:36:00.598453 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8059 11:36:00.604968 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:36:00.608586 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:36:00.612150 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:36:00.618366 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:36:00.621890 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8064 11:36:00.625093 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8065 11:36:00.631976 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8066 11:36:00.634955 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8067 11:36:00.638150 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8068 11:36:00.644823 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:36:00.647951 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:36:00.652391 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:36:00.658431 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8072 11:36:00.662043 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8073 11:36:00.665201 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8074 11:36:00.671716 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8075 11:36:00.674948 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:36:00.678092 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:36:00.684994 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:36:00.688541 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:36:00.691716 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:36:00.694907 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8081 11:36:00.701610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8082 11:36:00.705273 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 11:36:00.708339 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 11:36:00.715550 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:36:00.718229 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:36:00.721388 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:36:00.728713 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:36:00.732115 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:36:00.734886 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:36:00.741888 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:36:00.745171 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:36:00.748177 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:36:00.755038 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:36:00.758283 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:36:00.761732 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 11:36:00.768489 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8097 11:36:00.771712 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 11:36:00.774791 Total UI for P1: 0, mck2ui 16
8099 11:36:00.778674 best dqsien dly found for B0: ( 1, 9, 10)
8100 11:36:00.781746 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8101 11:36:00.784941 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:36:00.788740 Total UI for P1: 0, mck2ui 16
8103 11:36:00.792003 best dqsien dly found for B1: ( 1, 9, 18)
8104 11:36:00.794979 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8105 11:36:00.798672 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8106 11:36:00.801682
8107 11:36:00.805333 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8108 11:36:00.808745 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8109 11:36:00.812144 [Gating] SW calibration Done
8110 11:36:00.812640 ==
8111 11:36:00.815130 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 11:36:00.818919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 11:36:00.819423 ==
8114 11:36:00.821491 RX Vref Scan: 0
8115 11:36:00.822093
8116 11:36:00.822436 RX Vref 0 -> 0, step: 1
8117 11:36:00.822738
8118 11:36:00.824902 RX Delay 0 -> 252, step: 8
8119 11:36:00.828317 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8120 11:36:00.832069 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8121 11:36:00.838157 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8122 11:36:00.841511 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8123 11:36:00.845037 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8124 11:36:00.848377 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8125 11:36:00.851772 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8126 11:36:00.858346 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8127 11:36:00.861774 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8128 11:36:00.865357 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8129 11:36:00.868352 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8130 11:36:00.871524 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8131 11:36:00.878100 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8132 11:36:00.881535 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8133 11:36:00.885223 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 11:36:00.888402 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8135 11:36:00.888898 ==
8136 11:36:00.891758 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 11:36:00.898433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 11:36:00.898936 ==
8139 11:36:00.899268 DQS Delay:
8140 11:36:00.899570 DQS0 = 0, DQS1 = 0
8141 11:36:00.901488 DQM Delay:
8142 11:36:00.901899 DQM0 = 131, DQM1 = 124
8143 11:36:00.905347 DQ Delay:
8144 11:36:00.908741 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8145 11:36:00.911615 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8146 11:36:00.914987 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
8147 11:36:00.918279 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8148 11:36:00.918699
8149 11:36:00.919026
8150 11:36:00.919327 ==
8151 11:36:00.921448 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 11:36:00.925022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 11:36:00.925494 ==
8154 11:36:00.928458
8155 11:36:00.928971
8156 11:36:00.929521 TX Vref Scan disable
8157 11:36:00.931734 == TX Byte 0 ==
8158 11:36:00.934911 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8159 11:36:00.938103 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8160 11:36:00.941676 == TX Byte 1 ==
8161 11:36:00.944878 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8162 11:36:00.948451 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 11:36:00.948977 ==
8164 11:36:00.951780 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:36:00.958202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:36:00.958699 ==
8167 11:36:00.971670
8168 11:36:00.975276 TX Vref early break, caculate TX vref
8169 11:36:00.978100 TX Vref=16, minBit 9, minWin=22, winSum=375
8170 11:36:00.981441 TX Vref=18, minBit 9, minWin=22, winSum=383
8171 11:36:00.985282 TX Vref=20, minBit 3, minWin=23, winSum=396
8172 11:36:00.988344 TX Vref=22, minBit 9, minWin=23, winSum=401
8173 11:36:00.991501 TX Vref=24, minBit 11, minWin=24, winSum=409
8174 11:36:00.998822 TX Vref=26, minBit 3, minWin=25, winSum=416
8175 11:36:01.001566 TX Vref=28, minBit 1, minWin=25, winSum=420
8176 11:36:01.004821 TX Vref=30, minBit 10, minWin=25, winSum=420
8177 11:36:01.008643 TX Vref=32, minBit 1, minWin=25, winSum=416
8178 11:36:01.011655 TX Vref=34, minBit 8, minWin=24, winSum=401
8179 11:36:01.015288 TX Vref=36, minBit 0, minWin=24, winSum=396
8180 11:36:01.021346 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
8181 11:36:01.021907
8182 11:36:01.025650 Final TX Range 0 Vref 28
8183 11:36:01.026075
8184 11:36:01.026431 ==
8185 11:36:01.028725 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 11:36:01.031734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 11:36:01.032155 ==
8188 11:36:01.032455
8189 11:36:01.032733
8190 11:36:01.034805 TX Vref Scan disable
8191 11:36:01.041460 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8192 11:36:01.041866 == TX Byte 0 ==
8193 11:36:01.045385 u2DelayCellOfst[0]=14 cells (4 PI)
8194 11:36:01.048535 u2DelayCellOfst[1]=21 cells (6 PI)
8195 11:36:01.051664 u2DelayCellOfst[2]=10 cells (3 PI)
8196 11:36:01.055780 u2DelayCellOfst[3]=14 cells (4 PI)
8197 11:36:01.058498 u2DelayCellOfst[4]=10 cells (3 PI)
8198 11:36:01.061737 u2DelayCellOfst[5]=0 cells (0 PI)
8199 11:36:01.065370 u2DelayCellOfst[6]=21 cells (6 PI)
8200 11:36:01.068438 u2DelayCellOfst[7]=21 cells (6 PI)
8201 11:36:01.071985 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8202 11:36:01.075256 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8203 11:36:01.078367 == TX Byte 1 ==
8204 11:36:01.082228 u2DelayCellOfst[8]=0 cells (0 PI)
8205 11:36:01.082610 u2DelayCellOfst[9]=0 cells (0 PI)
8206 11:36:01.084938 u2DelayCellOfst[10]=3 cells (1 PI)
8207 11:36:01.088583 u2DelayCellOfst[11]=0 cells (0 PI)
8208 11:36:01.091748 u2DelayCellOfst[12]=10 cells (3 PI)
8209 11:36:01.095109 u2DelayCellOfst[13]=10 cells (3 PI)
8210 11:36:01.098170 u2DelayCellOfst[14]=14 cells (4 PI)
8211 11:36:01.101421 u2DelayCellOfst[15]=10 cells (3 PI)
8212 11:36:01.105298 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8213 11:36:01.111143 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8214 11:36:01.111638 DramC Write-DBI on
8215 11:36:01.112025 ==
8216 11:36:01.115388 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 11:36:01.121654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 11:36:01.122039 ==
8219 11:36:01.122330
8220 11:36:01.122600
8221 11:36:01.122857 TX Vref Scan disable
8222 11:36:01.125615 == TX Byte 0 ==
8223 11:36:01.128509 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8224 11:36:01.131652 == TX Byte 1 ==
8225 11:36:01.135437 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8226 11:36:01.138519 DramC Write-DBI off
8227 11:36:01.138927
8228 11:36:01.139222 [DATLAT]
8229 11:36:01.139497 Freq=1600, CH0 RK1
8230 11:36:01.139811
8231 11:36:01.141819 DATLAT Default: 0xf
8232 11:36:01.142210 0, 0xFFFF, sum = 0
8233 11:36:01.145321 1, 0xFFFF, sum = 0
8234 11:36:01.145703 2, 0xFFFF, sum = 0
8235 11:36:01.148897 3, 0xFFFF, sum = 0
8236 11:36:01.151950 4, 0xFFFF, sum = 0
8237 11:36:01.152410 5, 0xFFFF, sum = 0
8238 11:36:01.155280 6, 0xFFFF, sum = 0
8239 11:36:01.155750 7, 0xFFFF, sum = 0
8240 11:36:01.158767 8, 0xFFFF, sum = 0
8241 11:36:01.159162 9, 0xFFFF, sum = 0
8242 11:36:01.161907 10, 0xFFFF, sum = 0
8243 11:36:01.162294 11, 0xFFFF, sum = 0
8244 11:36:01.165091 12, 0xFFFF, sum = 0
8245 11:36:01.165505 13, 0xFFFF, sum = 0
8246 11:36:01.168634 14, 0x0, sum = 1
8247 11:36:01.169022 15, 0x0, sum = 2
8248 11:36:01.171716 16, 0x0, sum = 3
8249 11:36:01.172256 17, 0x0, sum = 4
8250 11:36:01.175111 best_step = 15
8251 11:36:01.175487
8252 11:36:01.175780 ==
8253 11:36:01.178639 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 11:36:01.182235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:36:01.182618 ==
8256 11:36:01.182914 RX Vref Scan: 0
8257 11:36:01.183185
8258 11:36:01.185203 RX Vref 0 -> 0, step: 1
8259 11:36:01.185584
8260 11:36:01.188666 RX Delay 11 -> 252, step: 4
8261 11:36:01.191730 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8262 11:36:01.198762 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8263 11:36:01.201810 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8264 11:36:01.205149 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8265 11:36:01.208455 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8266 11:36:01.211660 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8267 11:36:01.215449 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8268 11:36:01.222005 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8269 11:36:01.225210 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8270 11:36:01.228683 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8271 11:36:01.231629 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8272 11:36:01.238520 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8273 11:36:01.242039 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8274 11:36:01.245029 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8275 11:36:01.248718 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8276 11:36:01.252131 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8277 11:36:01.252510 ==
8278 11:36:01.255215 Dram Type= 6, Freq= 0, CH_0, rank 1
8279 11:36:01.262138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 11:36:01.262563 ==
8281 11:36:01.262859 DQS Delay:
8282 11:36:01.265276 DQS0 = 0, DQS1 = 0
8283 11:36:01.265652 DQM Delay:
8284 11:36:01.265941 DQM0 = 126, DQM1 = 122
8285 11:36:01.269003 DQ Delay:
8286 11:36:01.271742 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8287 11:36:01.275302 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8288 11:36:01.278368 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8289 11:36:01.281741 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8290 11:36:01.282118
8291 11:36:01.282409
8292 11:36:01.282681
8293 11:36:01.285566 [DramC_TX_OE_Calibration] TA2
8294 11:36:01.288781 Original DQ_B0 (3 6) =30, OEN = 27
8295 11:36:01.292316 Original DQ_B1 (3 6) =30, OEN = 27
8296 11:36:01.295200 24, 0x0, End_B0=24 End_B1=24
8297 11:36:01.295625 25, 0x0, End_B0=25 End_B1=25
8298 11:36:01.299265 26, 0x0, End_B0=26 End_B1=26
8299 11:36:01.301701 27, 0x0, End_B0=27 End_B1=27
8300 11:36:01.305571 28, 0x0, End_B0=28 End_B1=28
8301 11:36:01.309239 29, 0x0, End_B0=29 End_B1=29
8302 11:36:01.309744 30, 0x0, End_B0=30 End_B1=30
8303 11:36:01.311981 31, 0x4141, End_B0=30 End_B1=30
8304 11:36:01.315718 Byte0 end_step=30 best_step=27
8305 11:36:01.319489 Byte1 end_step=30 best_step=27
8306 11:36:01.322492 Byte0 TX OE(2T, 0.5T) = (3, 3)
8307 11:36:01.325306 Byte1 TX OE(2T, 0.5T) = (3, 3)
8308 11:36:01.325724
8309 11:36:01.326047
8310 11:36:01.332299 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8311 11:36:01.335460 CH0 RK1: MR19=303, MR18=1A0F
8312 11:36:01.341966 CH0_RK1: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8313 11:36:01.345639 [RxdqsGatingPostProcess] freq 1600
8314 11:36:01.349010 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8315 11:36:01.352197 best DQS0 dly(2T, 0.5T) = (1, 1)
8316 11:36:01.355509 best DQS1 dly(2T, 0.5T) = (1, 1)
8317 11:36:01.358717 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8318 11:36:01.362235 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8319 11:36:01.366116 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 11:36:01.369113 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 11:36:01.372055 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 11:36:01.375362 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 11:36:01.379001 Pre-setting of DQS Precalculation
8324 11:36:01.382305 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8325 11:36:01.382760 ==
8326 11:36:01.385519 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 11:36:01.388914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 11:36:01.389330 ==
8329 11:36:01.395899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8330 11:36:01.399320 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8331 11:36:01.402370 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8332 11:36:01.408928 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8333 11:36:01.419092 [CA 0] Center 42 (14~71) winsize 58
8334 11:36:01.421905 [CA 1] Center 42 (13~71) winsize 59
8335 11:36:01.425241 [CA 2] Center 37 (8~66) winsize 59
8336 11:36:01.428302 [CA 3] Center 36 (7~66) winsize 60
8337 11:36:01.431680 [CA 4] Center 37 (8~66) winsize 59
8338 11:36:01.435049 [CA 5] Center 36 (7~66) winsize 60
8339 11:36:01.435468
8340 11:36:01.438123 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8341 11:36:01.438567
8342 11:36:01.441785 [CATrainingPosCal] consider 1 rank data
8343 11:36:01.445155 u2DelayCellTimex100 = 275/100 ps
8344 11:36:01.448420 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8345 11:36:01.455422 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8346 11:36:01.458199 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8347 11:36:01.462027 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 11:36:01.465288 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8349 11:36:01.468461 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8350 11:36:01.468914
8351 11:36:01.471714 CA PerBit enable=1, Macro0, CA PI delay=36
8352 11:36:01.472167
8353 11:36:01.475262 [CBTSetCACLKResult] CA Dly = 36
8354 11:36:01.475732 CS Dly: 9 (0~40)
8355 11:36:01.481547 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8356 11:36:01.484939 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8357 11:36:01.485389 ==
8358 11:36:01.488410 Dram Type= 6, Freq= 0, CH_1, rank 1
8359 11:36:01.492137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 11:36:01.492589 ==
8361 11:36:01.498794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 11:36:01.501785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 11:36:01.508703 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 11:36:01.511747 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 11:36:01.521923 [CA 0] Center 43 (14~72) winsize 59
8366 11:36:01.525466 [CA 1] Center 43 (14~72) winsize 59
8367 11:36:01.528621 [CA 2] Center 38 (9~67) winsize 59
8368 11:36:01.531902 [CA 3] Center 37 (9~66) winsize 58
8369 11:36:01.534941 [CA 4] Center 38 (9~68) winsize 60
8370 11:36:01.538143 [CA 5] Center 36 (7~66) winsize 60
8371 11:36:01.538608
8372 11:36:01.541832 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8373 11:36:01.542322
8374 11:36:01.545359 [CATrainingPosCal] consider 2 rank data
8375 11:36:01.548499 u2DelayCellTimex100 = 275/100 ps
8376 11:36:01.551306 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8377 11:36:01.558410 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8378 11:36:01.561375 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8379 11:36:01.565060 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8380 11:36:01.568163 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8381 11:36:01.571784 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8382 11:36:01.572284
8383 11:36:01.574594 CA PerBit enable=1, Macro0, CA PI delay=36
8384 11:36:01.575036
8385 11:36:01.578869 [CBTSetCACLKResult] CA Dly = 36
8386 11:36:01.581742 CS Dly: 11 (0~45)
8387 11:36:01.584631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 11:36:01.588926 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 11:36:01.589460
8390 11:36:01.591274 ----->DramcWriteLeveling(PI) begin...
8391 11:36:01.591693 ==
8392 11:36:01.594926 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 11:36:01.598134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 11:36:01.601186 ==
8395 11:36:01.601605 Write leveling (Byte 0): 23 => 23
8396 11:36:01.605168 Write leveling (Byte 1): 28 => 28
8397 11:36:01.608361 DramcWriteLeveling(PI) end<-----
8398 11:36:01.608844
8399 11:36:01.609207 ==
8400 11:36:01.611232 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:36:01.618087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:36:01.618588 ==
8403 11:36:01.618919 [Gating] SW mode calibration
8404 11:36:01.628050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8405 11:36:01.632302 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8406 11:36:01.635420 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:36:01.641361 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 11:36:01.645164 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 11:36:01.648275 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 11:36:01.655204 1 4 16 | B1->B0 | 3030 2626 | 1 1 | (1 1) (1 1)
8411 11:36:01.658321 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:36:01.661419 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:36:01.668291 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:36:01.671930 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:36:01.675415 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:36:01.681546 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:36:01.684978 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8418 11:36:01.688174 1 5 16 | B1->B0 | 2c2c 3232 | 0 0 | (1 0) (1 0)
8419 11:36:01.694721 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:36:01.698284 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:36:01.701601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:36:01.707826 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:36:01.711389 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:36:01.714721 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:36:01.721865 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8426 11:36:01.724851 1 6 16 | B1->B0 | 3e3e 3030 | 0 0 | (0 0) (0 0)
8427 11:36:01.728292 1 6 20 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
8428 11:36:01.731641 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:36:01.738523 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:36:01.741767 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:36:01.744899 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:36:01.752053 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:36:01.755417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:36:01.758283 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8435 11:36:01.766001 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:36:01.768600 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:36:01.772042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:36:01.778864 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:36:01.782182 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:36:01.786280 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:36:01.788477 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:36:01.795166 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:36:01.798098 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:36:01.801777 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:36:01.808730 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:36:01.812442 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:36:01.815089 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:36:01.821944 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:36:01.825369 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8450 11:36:01.828618 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8451 11:36:01.835108 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:36:01.838448 Total UI for P1: 0, mck2ui 16
8453 11:36:01.841576 best dqsien dly found for B0: ( 1, 9, 14)
8454 11:36:01.842001 Total UI for P1: 0, mck2ui 16
8455 11:36:01.848819 best dqsien dly found for B1: ( 1, 9, 14)
8456 11:36:01.851994 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8457 11:36:01.855425 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8458 11:36:01.855916
8459 11:36:01.858591 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8460 11:36:01.861438 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8461 11:36:01.865156 [Gating] SW calibration Done
8462 11:36:01.865661 ==
8463 11:36:01.868857 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 11:36:01.871820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 11:36:01.872242 ==
8466 11:36:01.874791 RX Vref Scan: 0
8467 11:36:01.875205
8468 11:36:01.875543 RX Vref 0 -> 0, step: 1
8469 11:36:01.875848
8470 11:36:01.878592 RX Delay 0 -> 252, step: 8
8471 11:36:01.881814 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8472 11:36:01.888397 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8473 11:36:01.892083 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8474 11:36:01.895307 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8475 11:36:01.899224 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8476 11:36:01.901528 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8477 11:36:01.905787 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8478 11:36:01.911817 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8479 11:36:01.915525 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8480 11:36:01.918896 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8481 11:36:01.922492 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8482 11:36:01.925334 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8483 11:36:01.932131 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8484 11:36:01.935440 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8485 11:36:01.938889 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8486 11:36:01.942343 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8487 11:36:01.942845 ==
8488 11:36:01.945592 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 11:36:01.952470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 11:36:01.952997 ==
8491 11:36:01.953384 DQS Delay:
8492 11:36:01.953695 DQS0 = 0, DQS1 = 0
8493 11:36:01.955320 DQM Delay:
8494 11:36:01.955819 DQM0 = 134, DQM1 = 127
8495 11:36:01.959053 DQ Delay:
8496 11:36:01.962365 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8497 11:36:01.966128 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8498 11:36:01.968661 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8499 11:36:01.972031 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8500 11:36:01.972534
8501 11:36:01.972863
8502 11:36:01.973204 ==
8503 11:36:01.975131 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:36:01.979024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:36:01.981960 ==
8506 11:36:01.982454
8507 11:36:01.982847
8508 11:36:01.983147 TX Vref Scan disable
8509 11:36:01.985347 == TX Byte 0 ==
8510 11:36:01.988904 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 11:36:01.992161 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8512 11:36:01.995548 == TX Byte 1 ==
8513 11:36:01.998554 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8514 11:36:02.001609 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8515 11:36:02.002028 ==
8516 11:36:02.005619 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 11:36:02.012180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 11:36:02.012684 ==
8519 11:36:02.024207
8520 11:36:02.027350 TX Vref early break, caculate TX vref
8521 11:36:02.031427 TX Vref=16, minBit 8, minWin=21, winSum=365
8522 11:36:02.033831 TX Vref=18, minBit 8, minWin=21, winSum=373
8523 11:36:02.037243 TX Vref=20, minBit 8, minWin=22, winSum=384
8524 11:36:02.040522 TX Vref=22, minBit 8, minWin=23, winSum=398
8525 11:36:02.044115 TX Vref=24, minBit 8, minWin=23, winSum=407
8526 11:36:02.050720 TX Vref=26, minBit 8, minWin=24, winSum=412
8527 11:36:02.054442 TX Vref=28, minBit 9, minWin=25, winSum=421
8528 11:36:02.057051 TX Vref=30, minBit 8, minWin=25, winSum=420
8529 11:36:02.060587 TX Vref=32, minBit 9, minWin=24, winSum=412
8530 11:36:02.064867 TX Vref=34, minBit 9, minWin=23, winSum=396
8531 11:36:02.070932 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8532 11:36:02.071442
8533 11:36:02.073878 Final TX Range 0 Vref 28
8534 11:36:02.074294
8535 11:36:02.074617 ==
8536 11:36:02.077512 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 11:36:02.080867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 11:36:02.081440 ==
8539 11:36:02.081770
8540 11:36:02.082071
8541 11:36:02.084240 TX Vref Scan disable
8542 11:36:02.090541 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8543 11:36:02.091024 == TX Byte 0 ==
8544 11:36:02.093882 u2DelayCellOfst[0]=17 cells (5 PI)
8545 11:36:02.097382 u2DelayCellOfst[1]=14 cells (4 PI)
8546 11:36:02.100663 u2DelayCellOfst[2]=0 cells (0 PI)
8547 11:36:02.104080 u2DelayCellOfst[3]=7 cells (2 PI)
8548 11:36:02.107444 u2DelayCellOfst[4]=7 cells (2 PI)
8549 11:36:02.111069 u2DelayCellOfst[5]=17 cells (5 PI)
8550 11:36:02.111488 u2DelayCellOfst[6]=17 cells (5 PI)
8551 11:36:02.113831 u2DelayCellOfst[7]=3 cells (1 PI)
8552 11:36:02.121288 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8553 11:36:02.124195 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8554 11:36:02.124638 == TX Byte 1 ==
8555 11:36:02.127490 u2DelayCellOfst[8]=0 cells (0 PI)
8556 11:36:02.131110 u2DelayCellOfst[9]=3 cells (1 PI)
8557 11:36:02.133916 u2DelayCellOfst[10]=7 cells (2 PI)
8558 11:36:02.137574 u2DelayCellOfst[11]=3 cells (1 PI)
8559 11:36:02.141280 u2DelayCellOfst[12]=10 cells (3 PI)
8560 11:36:02.144537 u2DelayCellOfst[13]=14 cells (4 PI)
8561 11:36:02.147381 u2DelayCellOfst[14]=14 cells (4 PI)
8562 11:36:02.150880 u2DelayCellOfst[15]=14 cells (4 PI)
8563 11:36:02.154003 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8564 11:36:02.158022 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8565 11:36:02.160619 DramC Write-DBI on
8566 11:36:02.161152 ==
8567 11:36:02.164484 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 11:36:02.167382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 11:36:02.167879 ==
8570 11:36:02.168208
8571 11:36:02.168510
8572 11:36:02.170784 TX Vref Scan disable
8573 11:36:02.174286 == TX Byte 0 ==
8574 11:36:02.177501 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8575 11:36:02.178000 == TX Byte 1 ==
8576 11:36:02.184364 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8577 11:36:02.184847 DramC Write-DBI off
8578 11:36:02.185224
8579 11:36:02.187233 [DATLAT]
8580 11:36:02.187659 Freq=1600, CH1 RK0
8581 11:36:02.187983
8582 11:36:02.190586 DATLAT Default: 0xf
8583 11:36:02.191005 0, 0xFFFF, sum = 0
8584 11:36:02.193753 1, 0xFFFF, sum = 0
8585 11:36:02.194136 2, 0xFFFF, sum = 0
8586 11:36:02.197757 3, 0xFFFF, sum = 0
8587 11:36:02.198141 4, 0xFFFF, sum = 0
8588 11:36:02.200793 5, 0xFFFF, sum = 0
8589 11:36:02.201304 6, 0xFFFF, sum = 0
8590 11:36:02.203991 7, 0xFFFF, sum = 0
8591 11:36:02.204381 8, 0xFFFF, sum = 0
8592 11:36:02.207524 9, 0xFFFF, sum = 0
8593 11:36:02.207989 10, 0xFFFF, sum = 0
8594 11:36:02.211018 11, 0xFFFF, sum = 0
8595 11:36:02.211479 12, 0xFFFF, sum = 0
8596 11:36:02.214063 13, 0xFFFF, sum = 0
8597 11:36:02.214521 14, 0x0, sum = 1
8598 11:36:02.217530 15, 0x0, sum = 2
8599 11:36:02.218030 16, 0x0, sum = 3
8600 11:36:02.220777 17, 0x0, sum = 4
8601 11:36:02.221328 best_step = 15
8602 11:36:02.221670
8603 11:36:02.221972 ==
8604 11:36:02.224057 Dram Type= 6, Freq= 0, CH_1, rank 0
8605 11:36:02.231083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8606 11:36:02.231581 ==
8607 11:36:02.231908 RX Vref Scan: 1
8608 11:36:02.232210
8609 11:36:02.234114 Set Vref Range= 24 -> 127
8610 11:36:02.234561
8611 11:36:02.237288 RX Vref 24 -> 127, step: 1
8612 11:36:02.237758
8613 11:36:02.238108 RX Delay 19 -> 252, step: 4
8614 11:36:02.240593
8615 11:36:02.241012 Set Vref, RX VrefLevel [Byte0]: 24
8616 11:36:02.244208 [Byte1]: 24
8617 11:36:02.248457
8618 11:36:02.248911 Set Vref, RX VrefLevel [Byte0]: 25
8619 11:36:02.252087 [Byte1]: 25
8620 11:36:02.255524
8621 11:36:02.255903 Set Vref, RX VrefLevel [Byte0]: 26
8622 11:36:02.258973 [Byte1]: 26
8623 11:36:02.263274
8624 11:36:02.263659 Set Vref, RX VrefLevel [Byte0]: 27
8625 11:36:02.266749 [Byte1]: 27
8626 11:36:02.271031
8627 11:36:02.271405 Set Vref, RX VrefLevel [Byte0]: 28
8628 11:36:02.274191 [Byte1]: 28
8629 11:36:02.278884
8630 11:36:02.279262 Set Vref, RX VrefLevel [Byte0]: 29
8631 11:36:02.281786 [Byte1]: 29
8632 11:36:02.285780
8633 11:36:02.286164 Set Vref, RX VrefLevel [Byte0]: 30
8634 11:36:02.289310 [Byte1]: 30
8635 11:36:02.294028
8636 11:36:02.294473 Set Vref, RX VrefLevel [Byte0]: 31
8637 11:36:02.296748 [Byte1]: 31
8638 11:36:02.301428
8639 11:36:02.301875 Set Vref, RX VrefLevel [Byte0]: 32
8640 11:36:02.304611 [Byte1]: 32
8641 11:36:02.308886
8642 11:36:02.309488 Set Vref, RX VrefLevel [Byte0]: 33
8643 11:36:02.311950 [Byte1]: 33
8644 11:36:02.316553
8645 11:36:02.316932 Set Vref, RX VrefLevel [Byte0]: 34
8646 11:36:02.319399 [Byte1]: 34
8647 11:36:02.323688
8648 11:36:02.324064 Set Vref, RX VrefLevel [Byte0]: 35
8649 11:36:02.327058 [Byte1]: 35
8650 11:36:02.331594
8651 11:36:02.331968 Set Vref, RX VrefLevel [Byte0]: 36
8652 11:36:02.335081 [Byte1]: 36
8653 11:36:02.338865
8654 11:36:02.339367 Set Vref, RX VrefLevel [Byte0]: 37
8655 11:36:02.342483 [Byte1]: 37
8656 11:36:02.346600
8657 11:36:02.346977 Set Vref, RX VrefLevel [Byte0]: 38
8658 11:36:02.349929 [Byte1]: 38
8659 11:36:02.353957
8660 11:36:02.354340 Set Vref, RX VrefLevel [Byte0]: 39
8661 11:36:02.357475 [Byte1]: 39
8662 11:36:02.361555
8663 11:36:02.361939 Set Vref, RX VrefLevel [Byte0]: 40
8664 11:36:02.365197 [Byte1]: 40
8665 11:36:02.369061
8666 11:36:02.369476 Set Vref, RX VrefLevel [Byte0]: 41
8667 11:36:02.372601 [Byte1]: 41
8668 11:36:02.377149
8669 11:36:02.377883 Set Vref, RX VrefLevel [Byte0]: 42
8670 11:36:02.380402 [Byte1]: 42
8671 11:36:02.384571
8672 11:36:02.385009 Set Vref, RX VrefLevel [Byte0]: 43
8673 11:36:02.387737 [Byte1]: 43
8674 11:36:02.392454
8675 11:36:02.392908 Set Vref, RX VrefLevel [Byte0]: 44
8676 11:36:02.395626 [Byte1]: 44
8677 11:36:02.399366
8678 11:36:02.399742 Set Vref, RX VrefLevel [Byte0]: 45
8679 11:36:02.403459 [Byte1]: 45
8680 11:36:02.407007
8681 11:36:02.407406 Set Vref, RX VrefLevel [Byte0]: 46
8682 11:36:02.410366 [Byte1]: 46
8683 11:36:02.415212
8684 11:36:02.415682 Set Vref, RX VrefLevel [Byte0]: 47
8685 11:36:02.418342 [Byte1]: 47
8686 11:36:02.422291
8687 11:36:02.422671 Set Vref, RX VrefLevel [Byte0]: 48
8688 11:36:02.425745 [Byte1]: 48
8689 11:36:02.430093
8690 11:36:02.430470 Set Vref, RX VrefLevel [Byte0]: 49
8691 11:36:02.433234 [Byte1]: 49
8692 11:36:02.437892
8693 11:36:02.438267 Set Vref, RX VrefLevel [Byte0]: 50
8694 11:36:02.441189 [Byte1]: 50
8695 11:36:02.445465
8696 11:36:02.445842 Set Vref, RX VrefLevel [Byte0]: 51
8697 11:36:02.448278 [Byte1]: 51
8698 11:36:02.452882
8699 11:36:02.453320 Set Vref, RX VrefLevel [Byte0]: 52
8700 11:36:02.455645 [Byte1]: 52
8701 11:36:02.460714
8702 11:36:02.461207 Set Vref, RX VrefLevel [Byte0]: 53
8703 11:36:02.463856 [Byte1]: 53
8704 11:36:02.468422
8705 11:36:02.468873 Set Vref, RX VrefLevel [Byte0]: 54
8706 11:36:02.471355 [Byte1]: 54
8707 11:36:02.475588
8708 11:36:02.476039 Set Vref, RX VrefLevel [Byte0]: 55
8709 11:36:02.478634 [Byte1]: 55
8710 11:36:02.482996
8711 11:36:02.483447 Set Vref, RX VrefLevel [Byte0]: 56
8712 11:36:02.486135 [Byte1]: 56
8713 11:36:02.490564
8714 11:36:02.491052 Set Vref, RX VrefLevel [Byte0]: 57
8715 11:36:02.494262 [Byte1]: 57
8716 11:36:02.498440
8717 11:36:02.498933 Set Vref, RX VrefLevel [Byte0]: 58
8718 11:36:02.502051 [Byte1]: 58
8719 11:36:02.505585
8720 11:36:02.506004 Set Vref, RX VrefLevel [Byte0]: 59
8721 11:36:02.509742 [Byte1]: 59
8722 11:36:02.513295
8723 11:36:02.513840 Set Vref, RX VrefLevel [Byte0]: 60
8724 11:36:02.516940 [Byte1]: 60
8725 11:36:02.520913
8726 11:36:02.521380 Set Vref, RX VrefLevel [Byte0]: 61
8727 11:36:02.524469 [Byte1]: 61
8728 11:36:02.528659
8729 11:36:02.529215 Set Vref, RX VrefLevel [Byte0]: 62
8730 11:36:02.531708 [Byte1]: 62
8731 11:36:02.536421
8732 11:36:02.536911 Set Vref, RX VrefLevel [Byte0]: 63
8733 11:36:02.539402 [Byte1]: 63
8734 11:36:02.543982
8735 11:36:02.544476 Set Vref, RX VrefLevel [Byte0]: 64
8736 11:36:02.547245 [Byte1]: 64
8737 11:36:02.551459
8738 11:36:02.551949 Set Vref, RX VrefLevel [Byte0]: 65
8739 11:36:02.554320 [Byte1]: 65
8740 11:36:02.559023
8741 11:36:02.559517 Set Vref, RX VrefLevel [Byte0]: 66
8742 11:36:02.562057 [Byte1]: 66
8743 11:36:02.566972
8744 11:36:02.567461 Set Vref, RX VrefLevel [Byte0]: 67
8745 11:36:02.569669 [Byte1]: 67
8746 11:36:02.573903
8747 11:36:02.574402 Set Vref, RX VrefLevel [Byte0]: 68
8748 11:36:02.578099 [Byte1]: 68
8749 11:36:02.582016
8750 11:36:02.582507 Set Vref, RX VrefLevel [Byte0]: 69
8751 11:36:02.584868 [Byte1]: 69
8752 11:36:02.589092
8753 11:36:02.589642 Set Vref, RX VrefLevel [Byte0]: 70
8754 11:36:02.592674 [Byte1]: 70
8755 11:36:02.596885
8756 11:36:02.597426 Set Vref, RX VrefLevel [Byte0]: 71
8757 11:36:02.600125 [Byte1]: 71
8758 11:36:02.603868
8759 11:36:02.604283 Set Vref, RX VrefLevel [Byte0]: 72
8760 11:36:02.607360 [Byte1]: 72
8761 11:36:02.611530
8762 11:36:02.612019 Set Vref, RX VrefLevel [Byte0]: 73
8763 11:36:02.615101 [Byte1]: 73
8764 11:36:02.619314
8765 11:36:02.619811 Set Vref, RX VrefLevel [Byte0]: 74
8766 11:36:02.622486 [Byte1]: 74
8767 11:36:02.627103
8768 11:36:02.627592 Set Vref, RX VrefLevel [Byte0]: 75
8769 11:36:02.630177 [Byte1]: 75
8770 11:36:02.634531
8771 11:36:02.635020 Final RX Vref Byte 0 = 55 to rank0
8772 11:36:02.637770 Final RX Vref Byte 1 = 57 to rank0
8773 11:36:02.641199 Final RX Vref Byte 0 = 55 to rank1
8774 11:36:02.644683 Final RX Vref Byte 1 = 57 to rank1==
8775 11:36:02.647779 Dram Type= 6, Freq= 0, CH_1, rank 0
8776 11:36:02.654458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 11:36:02.654991 ==
8778 11:36:02.655393 DQS Delay:
8779 11:36:02.655735 DQS0 = 0, DQS1 = 0
8780 11:36:02.657634 DQM Delay:
8781 11:36:02.658052 DQM0 = 131, DQM1 = 124
8782 11:36:02.661472 DQ Delay:
8783 11:36:02.664479 DQ0 =136, DQ1 =124, DQ2 =118, DQ3 =130
8784 11:36:02.668105 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8785 11:36:02.671235 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
8786 11:36:02.675099 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8787 11:36:02.675605
8788 11:36:02.675932
8789 11:36:02.676227
8790 11:36:02.677707 [DramC_TX_OE_Calibration] TA2
8791 11:36:02.682093 Original DQ_B0 (3 6) =30, OEN = 27
8792 11:36:02.684766 Original DQ_B1 (3 6) =30, OEN = 27
8793 11:36:02.688292 24, 0x0, End_B0=24 End_B1=24
8794 11:36:02.688796 25, 0x0, End_B0=25 End_B1=25
8795 11:36:02.691181 26, 0x0, End_B0=26 End_B1=26
8796 11:36:02.694664 27, 0x0, End_B0=27 End_B1=27
8797 11:36:02.697975 28, 0x0, End_B0=28 End_B1=28
8798 11:36:02.698473 29, 0x0, End_B0=29 End_B1=29
8799 11:36:02.701048 30, 0x0, End_B0=30 End_B1=30
8800 11:36:02.704821 31, 0x4545, End_B0=30 End_B1=30
8801 11:36:02.708221 Byte0 end_step=30 best_step=27
8802 11:36:02.711438 Byte1 end_step=30 best_step=27
8803 11:36:02.714299 Byte0 TX OE(2T, 0.5T) = (3, 3)
8804 11:36:02.714735 Byte1 TX OE(2T, 0.5T) = (3, 3)
8805 11:36:02.715060
8806 11:36:02.717803
8807 11:36:02.724820 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8808 11:36:02.727909 CH1 RK0: MR19=302, MR18=14FF
8809 11:36:02.734170 CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8810 11:36:02.734588
8811 11:36:02.737991 ----->DramcWriteLeveling(PI) begin...
8812 11:36:02.738413 ==
8813 11:36:02.740931 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 11:36:02.744722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 11:36:02.745277 ==
8816 11:36:02.748160 Write leveling (Byte 0): 25 => 25
8817 11:36:02.751518 Write leveling (Byte 1): 26 => 26
8818 11:36:02.754290 DramcWriteLeveling(PI) end<-----
8819 11:36:02.754708
8820 11:36:02.755031 ==
8821 11:36:02.757944 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 11:36:02.760800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 11:36:02.761240 ==
8824 11:36:02.765151 [Gating] SW mode calibration
8825 11:36:02.771304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8826 11:36:02.777156 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8827 11:36:02.781074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 11:36:02.784255 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 11:36:02.791688 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 0)
8830 11:36:02.794174 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8831 11:36:02.797835 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 11:36:02.804802 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 11:36:02.808014 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 11:36:02.811332 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 11:36:02.818284 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 11:36:02.821420 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8837 11:36:02.824576 1 5 8 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
8838 11:36:02.828107 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
8839 11:36:02.835145 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8840 11:36:02.837853 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 11:36:02.841218 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 11:36:02.848122 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 11:36:02.851219 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 11:36:02.855136 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 11:36:02.861337 1 6 8 | B1->B0 | 2727 3e3e | 0 0 | (0 0) (0 0)
8846 11:36:02.864562 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8847 11:36:02.868162 1 6 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8848 11:36:02.874966 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 11:36:02.877917 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 11:36:02.881188 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 11:36:02.888090 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 11:36:02.891721 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 11:36:02.895338 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8854 11:36:02.898166 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8855 11:36:02.904701 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8856 11:36:02.908296 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:36:02.911683 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:36:02.918565 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:36:02.921685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:36:02.925094 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:36:02.931501 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:36:02.934571 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:36:02.938841 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:36:02.944993 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:36:02.948232 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:36:02.951642 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:36:02.958262 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:36:02.961153 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:36:02.964762 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8870 11:36:02.971901 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8871 11:36:02.972397 Total UI for P1: 0, mck2ui 16
8872 11:36:02.977823 best dqsien dly found for B0: ( 1, 9, 8)
8873 11:36:02.981735 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 11:36:02.984923 Total UI for P1: 0, mck2ui 16
8875 11:36:02.987658 best dqsien dly found for B1: ( 1, 9, 10)
8876 11:36:02.991472 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8877 11:36:02.995249 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8878 11:36:02.995745
8879 11:36:02.997831 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8880 11:36:03.001308 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8881 11:36:03.004462 [Gating] SW calibration Done
8882 11:36:03.004903 ==
8883 11:36:03.007649 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 11:36:03.011289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 11:36:03.011712 ==
8886 11:36:03.014614 RX Vref Scan: 0
8887 11:36:03.014990
8888 11:36:03.018124 RX Vref 0 -> 0, step: 1
8889 11:36:03.018499
8890 11:36:03.018792 RX Delay 0 -> 252, step: 8
8891 11:36:03.024528 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8892 11:36:03.028065 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8893 11:36:03.031338 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8894 11:36:03.034637 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8895 11:36:03.037875 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8896 11:36:03.041384 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8897 11:36:03.047561 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8898 11:36:03.051444 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8899 11:36:03.054415 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8900 11:36:03.057962 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8901 11:36:03.064270 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8902 11:36:03.068020 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8903 11:36:03.071503 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8904 11:36:03.075041 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8905 11:36:03.077874 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8906 11:36:03.084504 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8907 11:36:03.085010 ==
8908 11:36:03.087917 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 11:36:03.091105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 11:36:03.091545 ==
8911 11:36:03.091982 DQS Delay:
8912 11:36:03.094606 DQS0 = 0, DQS1 = 0
8913 11:36:03.095045 DQM Delay:
8914 11:36:03.097861 DQM0 = 131, DQM1 = 127
8915 11:36:03.098297 DQ Delay:
8916 11:36:03.101442 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8917 11:36:03.104881 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8918 11:36:03.108189 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8919 11:36:03.111668 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8920 11:36:03.112142
8921 11:36:03.112539
8922 11:36:03.112906 ==
8923 11:36:03.115097 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 11:36:03.121363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 11:36:03.121853 ==
8926 11:36:03.122255
8927 11:36:03.122625
8928 11:36:03.122987 TX Vref Scan disable
8929 11:36:03.125565 == TX Byte 0 ==
8930 11:36:03.128508 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 11:36:03.131853 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8932 11:36:03.134720 == TX Byte 1 ==
8933 11:36:03.138108 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8934 11:36:03.141730 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8935 11:36:03.145280 ==
8936 11:36:03.148239 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 11:36:03.151913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 11:36:03.152312 ==
8939 11:36:03.164650
8940 11:36:03.168225 TX Vref early break, caculate TX vref
8941 11:36:03.171466 TX Vref=16, minBit 11, minWin=22, winSum=379
8942 11:36:03.174685 TX Vref=18, minBit 0, minWin=24, winSum=395
8943 11:36:03.178306 TX Vref=20, minBit 6, minWin=24, winSum=401
8944 11:36:03.181750 TX Vref=22, minBit 0, minWin=25, winSum=406
8945 11:36:03.184832 TX Vref=24, minBit 0, minWin=25, winSum=413
8946 11:36:03.191732 TX Vref=26, minBit 0, minWin=26, winSum=422
8947 11:36:03.194925 TX Vref=28, minBit 0, minWin=26, winSum=424
8948 11:36:03.198120 TX Vref=30, minBit 0, minWin=26, winSum=428
8949 11:36:03.201516 TX Vref=32, minBit 0, minWin=25, winSum=417
8950 11:36:03.205304 TX Vref=34, minBit 0, minWin=25, winSum=412
8951 11:36:03.208687 TX Vref=36, minBit 0, minWin=23, winSum=397
8952 11:36:03.215060 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
8953 11:36:03.215537
8954 11:36:03.218442 Final TX Range 0 Vref 30
8955 11:36:03.218922
8956 11:36:03.219322 ==
8957 11:36:03.221321 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 11:36:03.225239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 11:36:03.225714 ==
8960 11:36:03.226111
8961 11:36:03.226478
8962 11:36:03.228592 TX Vref Scan disable
8963 11:36:03.234964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8964 11:36:03.235426 == TX Byte 0 ==
8965 11:36:03.238171 u2DelayCellOfst[0]=17 cells (5 PI)
8966 11:36:03.241739 u2DelayCellOfst[1]=10 cells (3 PI)
8967 11:36:03.245244 u2DelayCellOfst[2]=0 cells (0 PI)
8968 11:36:03.248119 u2DelayCellOfst[3]=7 cells (2 PI)
8969 11:36:03.251814 u2DelayCellOfst[4]=7 cells (2 PI)
8970 11:36:03.254709 u2DelayCellOfst[5]=17 cells (5 PI)
8971 11:36:03.258375 u2DelayCellOfst[6]=17 cells (5 PI)
8972 11:36:03.258849 u2DelayCellOfst[7]=7 cells (2 PI)
8973 11:36:03.264767 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8974 11:36:03.268854 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8975 11:36:03.269359 == TX Byte 1 ==
8976 11:36:03.271585 u2DelayCellOfst[8]=0 cells (0 PI)
8977 11:36:03.275308 u2DelayCellOfst[9]=3 cells (1 PI)
8978 11:36:03.279325 u2DelayCellOfst[10]=7 cells (2 PI)
8979 11:36:03.281725 u2DelayCellOfst[11]=3 cells (1 PI)
8980 11:36:03.285147 u2DelayCellOfst[12]=14 cells (4 PI)
8981 11:36:03.288415 u2DelayCellOfst[13]=14 cells (4 PI)
8982 11:36:03.291889 u2DelayCellOfst[14]=17 cells (5 PI)
8983 11:36:03.295645 u2DelayCellOfst[15]=14 cells (4 PI)
8984 11:36:03.298701 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8985 11:36:03.302286 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8986 11:36:03.304932 DramC Write-DBI on
8987 11:36:03.305467 ==
8988 11:36:03.308730 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 11:36:03.311938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 11:36:03.312487 ==
8991 11:36:03.312818
8992 11:36:03.315107
8993 11:36:03.315600 TX Vref Scan disable
8994 11:36:03.317994 == TX Byte 0 ==
8995 11:36:03.321537 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8996 11:36:03.325052 == TX Byte 1 ==
8997 11:36:03.328638 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8998 11:36:03.329179 DramC Write-DBI off
8999 11:36:03.329518
9000 11:36:03.331732 [DATLAT]
9001 11:36:03.332226 Freq=1600, CH1 RK1
9002 11:36:03.332556
9003 11:36:03.334946 DATLAT Default: 0xf
9004 11:36:03.335411 0, 0xFFFF, sum = 0
9005 11:36:03.338113 1, 0xFFFF, sum = 0
9006 11:36:03.338604 2, 0xFFFF, sum = 0
9007 11:36:03.341273 3, 0xFFFF, sum = 0
9008 11:36:03.341701 4, 0xFFFF, sum = 0
9009 11:36:03.344610 5, 0xFFFF, sum = 0
9010 11:36:03.345039 6, 0xFFFF, sum = 0
9011 11:36:03.348350 7, 0xFFFF, sum = 0
9012 11:36:03.348887 8, 0xFFFF, sum = 0
9013 11:36:03.351607 9, 0xFFFF, sum = 0
9014 11:36:03.355343 10, 0xFFFF, sum = 0
9015 11:36:03.355848 11, 0xFFFF, sum = 0
9016 11:36:03.358354 12, 0xFFFF, sum = 0
9017 11:36:03.358781 13, 0xFFFF, sum = 0
9018 11:36:03.361663 14, 0x0, sum = 1
9019 11:36:03.362163 15, 0x0, sum = 2
9020 11:36:03.364949 16, 0x0, sum = 3
9021 11:36:03.365413 17, 0x0, sum = 4
9022 11:36:03.365747 best_step = 15
9023 11:36:03.368520
9024 11:36:03.369008 ==
9025 11:36:03.371316 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 11:36:03.374993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 11:36:03.375491 ==
9028 11:36:03.375821 RX Vref Scan: 0
9029 11:36:03.376124
9030 11:36:03.378315 RX Vref 0 -> 0, step: 1
9031 11:36:03.378805
9032 11:36:03.381420 RX Delay 11 -> 252, step: 4
9033 11:36:03.384879 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9034 11:36:03.388136 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9035 11:36:03.394692 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9036 11:36:03.398114 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9037 11:36:03.401269 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9038 11:36:03.404980 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9039 11:36:03.408027 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9040 11:36:03.414835 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9041 11:36:03.418085 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9042 11:36:03.421208 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9043 11:36:03.424735 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9044 11:36:03.428254 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9045 11:36:03.434701 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9046 11:36:03.438147 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9047 11:36:03.441656 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9048 11:36:03.444911 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9049 11:36:03.445331 ==
9050 11:36:03.448055 Dram Type= 6, Freq= 0, CH_1, rank 1
9051 11:36:03.451456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9052 11:36:03.454871 ==
9053 11:36:03.455247 DQS Delay:
9054 11:36:03.455543 DQS0 = 0, DQS1 = 0
9055 11:36:03.457995 DQM Delay:
9056 11:36:03.458373 DQM0 = 129, DQM1 = 126
9057 11:36:03.461524 DQ Delay:
9058 11:36:03.465002 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9059 11:36:03.468175 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9060 11:36:03.471684 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9061 11:36:03.475173 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9062 11:36:03.475554
9063 11:36:03.475849
9064 11:36:03.476120
9065 11:36:03.478421 [DramC_TX_OE_Calibration] TA2
9066 11:36:03.481644 Original DQ_B0 (3 6) =30, OEN = 27
9067 11:36:03.485049 Original DQ_B1 (3 6) =30, OEN = 27
9068 11:36:03.488201 24, 0x0, End_B0=24 End_B1=24
9069 11:36:03.488587 25, 0x0, End_B0=25 End_B1=25
9070 11:36:03.491297 26, 0x0, End_B0=26 End_B1=26
9071 11:36:03.494918 27, 0x0, End_B0=27 End_B1=27
9072 11:36:03.498293 28, 0x0, End_B0=28 End_B1=28
9073 11:36:03.498886 29, 0x0, End_B0=29 End_B1=29
9074 11:36:03.501452 30, 0x0, End_B0=30 End_B1=30
9075 11:36:03.505217 31, 0x4141, End_B0=30 End_B1=30
9076 11:36:03.508121 Byte0 end_step=30 best_step=27
9077 11:36:03.512181 Byte1 end_step=30 best_step=27
9078 11:36:03.515143 Byte0 TX OE(2T, 0.5T) = (3, 3)
9079 11:36:03.515546 Byte1 TX OE(2T, 0.5T) = (3, 3)
9080 11:36:03.515935
9081 11:36:03.516298
9082 11:36:03.525100 [DQSOSCAuto] RK1, (LSB)MR18= 0x1116, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9083 11:36:03.528145 CH1 RK1: MR19=303, MR18=1116
9084 11:36:03.535161 CH1_RK1: MR19=0x303, MR18=0x1116, DQSOSC=398, MR23=63, INC=23, DEC=15
9085 11:36:03.535555 [RxdqsGatingPostProcess] freq 1600
9086 11:36:03.541829 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9087 11:36:03.545809 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 11:36:03.548319 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 11:36:03.551828 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 11:36:03.555157 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 11:36:03.558136 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 11:36:03.561668 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 11:36:03.564941 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 11:36:03.565512 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 11:36:03.568126 Pre-setting of DQS Precalculation
9096 11:36:03.575266 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9097 11:36:03.582102 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9098 11:36:03.588770 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 11:36:03.589322
9100 11:36:03.589652
9101 11:36:03.592224 [Calibration Summary] 3200 Mbps
9102 11:36:03.592720 CH 0, Rank 0
9103 11:36:03.595488 SW Impedance : PASS
9104 11:36:03.598897 DUTY Scan : NO K
9105 11:36:03.599314 ZQ Calibration : PASS
9106 11:36:03.602546 Jitter Meter : NO K
9107 11:36:03.605341 CBT Training : PASS
9108 11:36:03.605756 Write leveling : PASS
9109 11:36:03.609017 RX DQS gating : PASS
9110 11:36:03.611651 RX DQ/DQS(RDDQC) : PASS
9111 11:36:03.612066 TX DQ/DQS : PASS
9112 11:36:03.615433 RX DATLAT : PASS
9113 11:36:03.619356 RX DQ/DQS(Engine): PASS
9114 11:36:03.619773 TX OE : PASS
9115 11:36:03.621860 All Pass.
9116 11:36:03.622291
9117 11:36:03.622614 CH 0, Rank 1
9118 11:36:03.625588 SW Impedance : PASS
9119 11:36:03.626090 DUTY Scan : NO K
9120 11:36:03.628675 ZQ Calibration : PASS
9121 11:36:03.632354 Jitter Meter : NO K
9122 11:36:03.632854 CBT Training : PASS
9123 11:36:03.635141 Write leveling : PASS
9124 11:36:03.635573 RX DQS gating : PASS
9125 11:36:03.638873 RX DQ/DQS(RDDQC) : PASS
9126 11:36:03.641940 TX DQ/DQS : PASS
9127 11:36:03.642362 RX DATLAT : PASS
9128 11:36:03.645598 RX DQ/DQS(Engine): PASS
9129 11:36:03.648573 TX OE : PASS
9130 11:36:03.648991 All Pass.
9131 11:36:03.649355
9132 11:36:03.649658 CH 1, Rank 0
9133 11:36:03.651957 SW Impedance : PASS
9134 11:36:03.655793 DUTY Scan : NO K
9135 11:36:03.656298 ZQ Calibration : PASS
9136 11:36:03.658532 Jitter Meter : NO K
9137 11:36:03.661703 CBT Training : PASS
9138 11:36:03.662168 Write leveling : PASS
9139 11:36:03.665015 RX DQS gating : PASS
9140 11:36:03.669250 RX DQ/DQS(RDDQC) : PASS
9141 11:36:03.669749 TX DQ/DQS : PASS
9142 11:36:03.672022 RX DATLAT : PASS
9143 11:36:03.675376 RX DQ/DQS(Engine): PASS
9144 11:36:03.675874 TX OE : PASS
9145 11:36:03.676205 All Pass.
9146 11:36:03.676508
9147 11:36:03.678574 CH 1, Rank 1
9148 11:36:03.678992 SW Impedance : PASS
9149 11:36:03.681811 DUTY Scan : NO K
9150 11:36:03.685219 ZQ Calibration : PASS
9151 11:36:03.685639 Jitter Meter : NO K
9152 11:36:03.688442 CBT Training : PASS
9153 11:36:03.692005 Write leveling : PASS
9154 11:36:03.692423 RX DQS gating : PASS
9155 11:36:03.695165 RX DQ/DQS(RDDQC) : PASS
9156 11:36:03.698786 TX DQ/DQS : PASS
9157 11:36:03.699301 RX DATLAT : PASS
9158 11:36:03.701728 RX DQ/DQS(Engine): PASS
9159 11:36:03.705394 TX OE : PASS
9160 11:36:03.705813 All Pass.
9161 11:36:03.706135
9162 11:36:03.706433 DramC Write-DBI on
9163 11:36:03.708862 PER_BANK_REFRESH: Hybrid Mode
9164 11:36:03.712060 TX_TRACKING: ON
9165 11:36:03.718567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9166 11:36:03.728698 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9167 11:36:03.736001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9168 11:36:03.738636 [FAST_K] Save calibration result to emmc
9169 11:36:03.742110 sync common calibartion params.
9170 11:36:03.742544 sync cbt_mode0:1, 1:1
9171 11:36:03.745283 dram_init: ddr_geometry: 2
9172 11:36:03.748604 dram_init: ddr_geometry: 2
9173 11:36:03.752537 dram_init: ddr_geometry: 2
9174 11:36:03.753031 0:dram_rank_size:100000000
9175 11:36:03.755607 1:dram_rank_size:100000000
9176 11:36:03.762412 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9177 11:36:03.762927 DFS_SHUFFLE_HW_MODE: ON
9178 11:36:03.768941 dramc_set_vcore_voltage set vcore to 725000
9179 11:36:03.769511 Read voltage for 1600, 0
9180 11:36:03.772625 Vio18 = 0
9181 11:36:03.773158 Vcore = 725000
9182 11:36:03.773509 Vdram = 0
9183 11:36:03.773813 Vddq = 0
9184 11:36:03.775556 Vmddr = 0
9185 11:36:03.775973 switch to 3200 Mbps bootup
9186 11:36:03.778346 [DramcRunTimeConfig]
9187 11:36:03.778758 PHYPLL
9188 11:36:03.781831 DPM_CONTROL_AFTERK: ON
9189 11:36:03.782245 PER_BANK_REFRESH: ON
9190 11:36:03.785726 REFRESH_OVERHEAD_REDUCTION: ON
9191 11:36:03.789149 CMD_PICG_NEW_MODE: OFF
9192 11:36:03.789662 XRTWTW_NEW_MODE: ON
9193 11:36:03.792084 XRTRTR_NEW_MODE: ON
9194 11:36:03.792499 TX_TRACKING: ON
9195 11:36:03.795553 RDSEL_TRACKING: OFF
9196 11:36:03.798769 DQS Precalculation for DVFS: ON
9197 11:36:03.799186 RX_TRACKING: OFF
9198 11:36:03.801757 HW_GATING DBG: ON
9199 11:36:03.802172 ZQCS_ENABLE_LP4: ON
9200 11:36:03.805592 RX_PICG_NEW_MODE: ON
9201 11:36:03.806081 TX_PICG_NEW_MODE: ON
9202 11:36:03.809430 ENABLE_RX_DCM_DPHY: ON
9203 11:36:03.812184 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9204 11:36:03.815144 DUMMY_READ_FOR_TRACKING: OFF
9205 11:36:03.818955 !!! SPM_CONTROL_AFTERK: OFF
9206 11:36:03.819519 !!! SPM could not control APHY
9207 11:36:03.821954 IMPEDANCE_TRACKING: ON
9208 11:36:03.822369 TEMP_SENSOR: ON
9209 11:36:03.825518 HW_SAVE_FOR_SR: OFF
9210 11:36:03.828548 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9211 11:36:03.832083 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9212 11:36:03.835818 Read ODT Tracking: ON
9213 11:36:03.836286 Refresh Rate DeBounce: ON
9214 11:36:03.838943 DFS_NO_QUEUE_FLUSH: ON
9215 11:36:03.842070 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9216 11:36:03.845596 ENABLE_DFS_RUNTIME_MRW: OFF
9217 11:36:03.846090 DDR_RESERVE_NEW_MODE: ON
9218 11:36:03.848863 MR_CBT_SWITCH_FREQ: ON
9219 11:36:03.852745 =========================
9220 11:36:03.869380 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9221 11:36:03.872421 dram_init: ddr_geometry: 2
9222 11:36:03.891029 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9223 11:36:03.893920 dram_init: dram init end (result: 0)
9224 11:36:03.900612 DRAM-K: Full calibration passed in 24615 msecs
9225 11:36:03.903988 MRC: failed to locate region type 0.
9226 11:36:03.904168 DRAM rank0 size:0x100000000,
9227 11:36:03.907376 DRAM rank1 size=0x100000000
9228 11:36:03.917744 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9229 11:36:03.924003 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9230 11:36:03.931478 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9231 11:36:03.937307 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9232 11:36:03.940763 DRAM rank0 size:0x100000000,
9233 11:36:03.944469 DRAM rank1 size=0x100000000
9234 11:36:03.944888 CBMEM:
9235 11:36:03.947588 IMD: root @ 0xfffff000 254 entries.
9236 11:36:03.951209 IMD: root @ 0xffffec00 62 entries.
9237 11:36:03.953972 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9238 11:36:03.957502 WARNING: RO_VPD is uninitialized or empty.
9239 11:36:03.964200 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9240 11:36:03.970954 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9241 11:36:03.983751 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9242 11:36:03.995444 BS: romstage times (exec / console): total (unknown) / 24113 ms
9243 11:36:03.995946
9244 11:36:03.996274
9245 11:36:04.005324 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9246 11:36:04.009157 ARM64: Exception handlers installed.
9247 11:36:04.011922 ARM64: Testing exception
9248 11:36:04.015527 ARM64: Done test exception
9249 11:36:04.016021 Enumerating buses...
9250 11:36:04.018490 Show all devs... Before device enumeration.
9251 11:36:04.021890 Root Device: enabled 1
9252 11:36:04.025835 CPU_CLUSTER: 0: enabled 1
9253 11:36:04.026329 CPU: 00: enabled 1
9254 11:36:04.028978 Compare with tree...
9255 11:36:04.029555 Root Device: enabled 1
9256 11:36:04.031971 CPU_CLUSTER: 0: enabled 1
9257 11:36:04.035222 CPU: 00: enabled 1
9258 11:36:04.035646 Root Device scanning...
9259 11:36:04.038696 scan_static_bus for Root Device
9260 11:36:04.041868 CPU_CLUSTER: 0 enabled
9261 11:36:04.045194 scan_static_bus for Root Device done
9262 11:36:04.048436 scan_bus: bus Root Device finished in 8 msecs
9263 11:36:04.048856 done
9264 11:36:04.055159 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9265 11:36:04.058630 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9266 11:36:04.065485 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9267 11:36:04.068637 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9268 11:36:04.072135 Allocating resources...
9269 11:36:04.072628 Reading resources...
9270 11:36:04.078313 Root Device read_resources bus 0 link: 0
9271 11:36:04.078793 DRAM rank0 size:0x100000000,
9272 11:36:04.082110 DRAM rank1 size=0x100000000
9273 11:36:04.085208 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9274 11:36:04.089029 CPU: 00 missing read_resources
9275 11:36:04.092190 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9276 11:36:04.098720 Root Device read_resources bus 0 link: 0 done
9277 11:36:04.099222 Done reading resources.
9278 11:36:04.105645 Show resources in subtree (Root Device)...After reading.
9279 11:36:04.108732 Root Device child on link 0 CPU_CLUSTER: 0
9280 11:36:04.112206 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 11:36:04.121939 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 11:36:04.122439 CPU: 00
9283 11:36:04.125507 Root Device assign_resources, bus 0 link: 0
9284 11:36:04.129068 CPU_CLUSTER: 0 missing set_resources
9285 11:36:04.132016 Root Device assign_resources, bus 0 link: 0 done
9286 11:36:04.135650 Done setting resources.
9287 11:36:04.142085 Show resources in subtree (Root Device)...After assigning values.
9288 11:36:04.145282 Root Device child on link 0 CPU_CLUSTER: 0
9289 11:36:04.148874 CPU_CLUSTER: 0 child on link 0 CPU: 00
9290 11:36:04.159129 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9291 11:36:04.159675 CPU: 00
9292 11:36:04.162591 Done allocating resources.
9293 11:36:04.165481 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9294 11:36:04.168773 Enabling resources...
9295 11:36:04.169480 done.
9296 11:36:04.172287 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9297 11:36:04.175700 Initializing devices...
9298 11:36:04.176190 Root Device init
9299 11:36:04.178591 init hardware done!
9300 11:36:04.182271 0x00000018: ctrlr->caps
9301 11:36:04.182693 52.000 MHz: ctrlr->f_max
9302 11:36:04.185645 0.400 MHz: ctrlr->f_min
9303 11:36:04.188884 0x40ff8080: ctrlr->voltages
9304 11:36:04.189436 sclk: 390625
9305 11:36:04.189770 Bus Width = 1
9306 11:36:04.192201 sclk: 390625
9307 11:36:04.192678 Bus Width = 1
9308 11:36:04.195827 Early init status = 3
9309 11:36:04.198947 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9310 11:36:04.203946 in-header: 03 fc 00 00 01 00 00 00
9311 11:36:04.207257 in-data: 00
9312 11:36:04.210499 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9313 11:36:04.216114 in-header: 03 fd 00 00 00 00 00 00
9314 11:36:04.219651 in-data:
9315 11:36:04.222444 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9316 11:36:04.227226 in-header: 03 fc 00 00 01 00 00 00
9317 11:36:04.230512 in-data: 00
9318 11:36:04.233827 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9319 11:36:04.239599 in-header: 03 fd 00 00 00 00 00 00
9320 11:36:04.242302 in-data:
9321 11:36:04.245735 [SSUSB] Setting up USB HOST controller...
9322 11:36:04.249328 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9323 11:36:04.253304 [SSUSB] phy power-on done.
9324 11:36:04.256233 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9325 11:36:04.263470 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9326 11:36:04.266415 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9327 11:36:04.272649 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9328 11:36:04.278923 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9329 11:36:04.286127 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9330 11:36:04.292757 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9331 11:36:04.299644 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9332 11:36:04.300151 SPM: binary array size = 0x9dc
9333 11:36:04.306100 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9334 11:36:04.312558 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9335 11:36:04.319298 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9336 11:36:04.322942 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9337 11:36:04.326216 configure_display: Starting display init
9338 11:36:04.362274 anx7625_power_on_init: Init interface.
9339 11:36:04.365535 anx7625_disable_pd_protocol: Disabled PD feature.
9340 11:36:04.368978 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9341 11:36:04.396795 anx7625_start_dp_work: Secure OCM version=00
9342 11:36:04.400321 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9343 11:36:04.415131 sp_tx_get_edid_block: EDID Block = 1
9344 11:36:04.517670 Extracted contents:
9345 11:36:04.520842 header: 00 ff ff ff ff ff ff 00
9346 11:36:04.524157 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9347 11:36:04.527635 version: 01 04
9348 11:36:04.531054 basic params: 95 1f 11 78 0a
9349 11:36:04.534287 chroma info: 76 90 94 55 54 90 27 21 50 54
9350 11:36:04.537728 established: 00 00 00
9351 11:36:04.544113 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9352 11:36:04.547381 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9353 11:36:04.553842 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 11:36:04.560590 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9355 11:36:04.567072 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9356 11:36:04.570466 extensions: 00
9357 11:36:04.570914 checksum: fb
9358 11:36:04.571209
9359 11:36:04.573819 Manufacturer: IVO Model 57d Serial Number 0
9360 11:36:04.576960 Made week 0 of 2020
9361 11:36:04.577362 EDID version: 1.4
9362 11:36:04.580401 Digital display
9363 11:36:04.583912 6 bits per primary color channel
9364 11:36:04.584362 DisplayPort interface
9365 11:36:04.587359 Maximum image size: 31 cm x 17 cm
9366 11:36:04.590454 Gamma: 220%
9367 11:36:04.590828 Check DPMS levels
9368 11:36:04.593500 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9369 11:36:04.597140 First detailed timing is preferred timing
9370 11:36:04.600288 Established timings supported:
9371 11:36:04.603809 Standard timings supported:
9372 11:36:04.606817 Detailed timings
9373 11:36:04.610082 Hex of detail: 383680a07038204018303c0035ae10000019
9374 11:36:04.614373 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9375 11:36:04.620397 0780 0798 07c8 0820 hborder 0
9376 11:36:04.624421 0438 043b 0447 0458 vborder 0
9377 11:36:04.627368 -hsync -vsync
9378 11:36:04.627865 Did detailed timing
9379 11:36:04.633621 Hex of detail: 000000000000000000000000000000000000
9380 11:36:04.634017 Manufacturer-specified data, tag 0
9381 11:36:04.640540 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9382 11:36:04.640932 ASCII string: InfoVision
9383 11:36:04.647205 Hex of detail: 000000fe00523134304e574635205248200a
9384 11:36:04.650115 ASCII string: R140NWF5 RH
9385 11:36:04.650499 Checksum
9386 11:36:04.650917 Checksum: 0xfb (valid)
9387 11:36:04.657059 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9388 11:36:04.660691 DSI data_rate: 832800000 bps
9389 11:36:04.663971 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9390 11:36:04.670728 anx7625_parse_edid: pixelclock(138800).
9391 11:36:04.674374 hactive(1920), hsync(48), hfp(24), hbp(88)
9392 11:36:04.677299 vactive(1080), vsync(12), vfp(3), vbp(17)
9393 11:36:04.680368 anx7625_dsi_config: config dsi.
9394 11:36:04.687574 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9395 11:36:04.699841 anx7625_dsi_config: success to config DSI
9396 11:36:04.703337 anx7625_dp_start: MIPI phy setup OK.
9397 11:36:04.706551 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9398 11:36:04.709804 mtk_ddp_mode_set invalid vrefresh 60
9399 11:36:04.713112 main_disp_path_setup
9400 11:36:04.713665 ovl_layer_smi_id_en
9401 11:36:04.716258 ovl_layer_smi_id_en
9402 11:36:04.716762 ccorr_config
9403 11:36:04.717094 aal_config
9404 11:36:04.719965 gamma_config
9405 11:36:04.720458 postmask_config
9406 11:36:04.723203 dither_config
9407 11:36:04.726532 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9408 11:36:04.733158 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9409 11:36:04.736494 Root Device init finished in 555 msecs
9410 11:36:04.736992 CPU_CLUSTER: 0 init
9411 11:36:04.746475 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9412 11:36:04.750052 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9413 11:36:04.752760 APU_MBOX 0x190000b0 = 0x10001
9414 11:36:04.756554 APU_MBOX 0x190001b0 = 0x10001
9415 11:36:04.759628 APU_MBOX 0x190005b0 = 0x10001
9416 11:36:04.762842 APU_MBOX 0x190006b0 = 0x10001
9417 11:36:04.766273 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9418 11:36:04.778871 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9419 11:36:04.791276 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9420 11:36:04.797610 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9421 11:36:04.809248 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9422 11:36:04.818349 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9423 11:36:04.821863 CPU_CLUSTER: 0 init finished in 81 msecs
9424 11:36:04.825270 Devices initialized
9425 11:36:04.828645 Show all devs... After init.
9426 11:36:04.829208 Root Device: enabled 1
9427 11:36:04.832042 CPU_CLUSTER: 0: enabled 1
9428 11:36:04.834855 CPU: 00: enabled 1
9429 11:36:04.838605 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9430 11:36:04.841804 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9431 11:36:04.845188 ELOG: NV offset 0x57f000 size 0x1000
9432 11:36:04.851390 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9433 11:36:04.858183 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9434 11:36:04.861703 ELOG: Event(17) added with size 13 at 2024-07-17 11:36:05 UTC
9435 11:36:04.864710 out: cmd=0x121: 03 db 21 01 00 00 00 00
9436 11:36:04.869984 in-header: 03 76 00 00 2c 00 00 00
9437 11:36:04.883497 in-data: c7 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9438 11:36:04.889748 ELOG: Event(A1) added with size 10 at 2024-07-17 11:36:05 UTC
9439 11:36:04.896164 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9440 11:36:04.903010 ELOG: Event(A0) added with size 9 at 2024-07-17 11:36:05 UTC
9441 11:36:04.906371 elog_add_boot_reason: Logged dev mode boot
9442 11:36:04.909961 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9443 11:36:04.913253 Finalize devices...
9444 11:36:04.913743 Devices finalized
9445 11:36:04.919772 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9446 11:36:04.923341 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9447 11:36:04.926498 in-header: 03 07 00 00 08 00 00 00
9448 11:36:04.930167 in-data: aa e4 47 04 13 02 00 00
9449 11:36:04.933113 Chrome EC: UHEPI supported
9450 11:36:04.939894 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9451 11:36:04.943136 in-header: 03 a9 00 00 08 00 00 00
9452 11:36:04.946187 in-data: 84 60 60 08 00 00 00 00
9453 11:36:04.949413 ELOG: Event(91) added with size 10 at 2024-07-17 11:36:05 UTC
9454 11:36:04.956910 Chrome EC: clear events_b mask to 0x0000000020004000
9455 11:36:04.963275 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9456 11:36:04.966517 in-header: 03 fd 00 00 00 00 00 00
9457 11:36:04.966940 in-data:
9458 11:36:04.973481 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9459 11:36:04.976613 Writing coreboot table at 0xffe64000
9460 11:36:04.980123 0. 000000000010a000-0000000000113fff: RAMSTAGE
9461 11:36:04.983667 1. 0000000040000000-00000000400fffff: RAM
9462 11:36:04.990150 2. 0000000040100000-000000004032afff: RAMSTAGE
9463 11:36:04.993049 3. 000000004032b000-00000000545fffff: RAM
9464 11:36:04.997165 4. 0000000054600000-000000005465ffff: BL31
9465 11:36:05.000239 5. 0000000054660000-00000000ffe63fff: RAM
9466 11:36:05.007299 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9467 11:36:05.009731 7. 0000000100000000-000000023fffffff: RAM
9468 11:36:05.013669 Passing 5 GPIOs to payload:
9469 11:36:05.016874 NAME | PORT | POLARITY | VALUE
9470 11:36:05.020830 EC in RW | 0x000000aa | low | undefined
9471 11:36:05.026358 EC interrupt | 0x00000005 | low | undefined
9472 11:36:05.029573 TPM interrupt | 0x000000ab | high | undefined
9473 11:36:05.036640 SD card detect | 0x00000011 | high | undefined
9474 11:36:05.039955 speaker enable | 0x00000093 | high | undefined
9475 11:36:05.043358 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9476 11:36:05.046594 in-header: 03 f9 00 00 02 00 00 00
9477 11:36:05.050179 in-data: 02 00
9478 11:36:05.050675 ADC[4]: Raw value=899483 ID=7
9479 11:36:05.053563 ADC[3]: Raw value=213336 ID=1
9480 11:36:05.056825 RAM Code: 0x71
9481 11:36:05.057365 ADC[6]: Raw value=74557 ID=0
9482 11:36:05.059671 ADC[5]: Raw value=212229 ID=1
9483 11:36:05.063133 SKU Code: 0x1
9484 11:36:05.066614 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7051
9485 11:36:05.069923 coreboot table: 964 bytes.
9486 11:36:05.073157 IMD ROOT 0. 0xfffff000 0x00001000
9487 11:36:05.076892 IMD SMALL 1. 0xffffe000 0x00001000
9488 11:36:05.080286 RO MCACHE 2. 0xffffc000 0x00001104
9489 11:36:05.083471 CONSOLE 3. 0xfff7c000 0x00080000
9490 11:36:05.086543 FMAP 4. 0xfff7b000 0x00000452
9491 11:36:05.090110 TIME STAMP 5. 0xfff7a000 0x00000910
9492 11:36:05.093368 VBOOT WORK 6. 0xfff66000 0x00014000
9493 11:36:05.096600 RAMOOPS 7. 0xffe66000 0x00100000
9494 11:36:05.099577 COREBOOT 8. 0xffe64000 0x00002000
9495 11:36:05.100116 IMD small region:
9496 11:36:05.103747 IMD ROOT 0. 0xffffec00 0x00000400
9497 11:36:05.106512 VPD 1. 0xffffeb80 0x0000006c
9498 11:36:05.109480 MMC STATUS 2. 0xffffeb60 0x00000004
9499 11:36:05.116386 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9500 11:36:05.123100 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9501 11:36:05.163127 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9502 11:36:05.166162 Checking segment from ROM address 0x40100000
9503 11:36:05.170035 Checking segment from ROM address 0x4010001c
9504 11:36:05.176857 Loading segment from ROM address 0x40100000
9505 11:36:05.177419 code (compression=0)
9506 11:36:05.183645 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9507 11:36:05.193587 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9508 11:36:05.194106 it's not compressed!
9509 11:36:05.199879 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9510 11:36:05.203196 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9511 11:36:05.223619 Loading segment from ROM address 0x4010001c
9512 11:36:05.224120 Entry Point 0x80000000
9513 11:36:05.226796 Loaded segments
9514 11:36:05.230599 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9515 11:36:05.236947 Jumping to boot code at 0x80000000(0xffe64000)
9516 11:36:05.243168 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9517 11:36:05.250553 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9518 11:36:05.258255 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9519 11:36:05.260779 Checking segment from ROM address 0x40100000
9520 11:36:05.264404 Checking segment from ROM address 0x4010001c
9521 11:36:05.271176 Loading segment from ROM address 0x40100000
9522 11:36:05.271641 code (compression=1)
9523 11:36:05.277836 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9524 11:36:05.287595 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9525 11:36:05.287984 using LZMA
9526 11:36:05.296526 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9527 11:36:05.302702 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9528 11:36:05.306503 Loading segment from ROM address 0x4010001c
9529 11:36:05.306971 Entry Point 0x54601000
9530 11:36:05.309334 Loaded segments
9531 11:36:05.313274 NOTICE: MT8192 bl31_setup
9532 11:36:05.319577 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9533 11:36:05.323131 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9534 11:36:05.326530 WARNING: region 0:
9535 11:36:05.329676 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 11:36:05.330141 WARNING: region 1:
9537 11:36:05.336366 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9538 11:36:05.339555 WARNING: region 2:
9539 11:36:05.342817 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9540 11:36:05.346422 WARNING: region 3:
9541 11:36:05.349877 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 11:36:05.353318 WARNING: region 4:
9543 11:36:05.359701 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 11:36:05.360152 WARNING: region 5:
9545 11:36:05.363081 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 11:36:05.366154 WARNING: region 6:
9547 11:36:05.369646 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:36:05.372806 WARNING: region 7:
9549 11:36:05.376505 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 11:36:05.382734 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9551 11:36:05.386401 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9552 11:36:05.389679 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9553 11:36:05.396182 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9554 11:36:05.399456 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9555 11:36:05.402941 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9556 11:36:05.409236 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9557 11:36:05.412985 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9558 11:36:05.419287 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9559 11:36:05.422797 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9560 11:36:05.426015 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9561 11:36:05.432950 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9562 11:36:05.436470 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9563 11:36:05.439513 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9564 11:36:05.446062 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9565 11:36:05.449555 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9566 11:36:05.456385 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9567 11:36:05.459668 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9568 11:36:05.462800 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9569 11:36:05.469776 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9570 11:36:05.472716 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9571 11:36:05.476220 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9572 11:36:05.483149 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9573 11:36:05.486042 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9574 11:36:05.492954 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9575 11:36:05.495895 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9576 11:36:05.499354 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9577 11:36:05.505883 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9578 11:36:05.509420 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9579 11:36:05.516022 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9580 11:36:05.519608 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9581 11:36:05.522660 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9582 11:36:05.529660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9583 11:36:05.532750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9584 11:36:05.536109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9585 11:36:05.539545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9586 11:36:05.546078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9587 11:36:05.549413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9588 11:36:05.552854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9589 11:36:05.556451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9590 11:36:05.562567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9591 11:36:05.566137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9592 11:36:05.569486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9593 11:36:05.572663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9594 11:36:05.579458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9595 11:36:05.583576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9596 11:36:05.586106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9597 11:36:05.589761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9598 11:36:05.596370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9599 11:36:05.599374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9600 11:36:05.606222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9601 11:36:05.609325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9602 11:36:05.616297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9603 11:36:05.619569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9604 11:36:05.622838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9605 11:36:05.629366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9606 11:36:05.632732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9607 11:36:05.640015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9608 11:36:05.642688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9609 11:36:05.645953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9610 11:36:05.652649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9611 11:36:05.656853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9612 11:36:05.662523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9613 11:36:05.665824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9614 11:36:05.672634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9615 11:36:05.676399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9616 11:36:05.682677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9617 11:36:05.685985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9618 11:36:05.689494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9619 11:36:05.695786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9620 11:36:05.698960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9621 11:36:05.705761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9622 11:36:05.709045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9623 11:36:05.715768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9624 11:36:05.719489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9625 11:36:05.722435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9626 11:36:05.729153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9627 11:36:05.732511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9628 11:36:05.739384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9629 11:36:05.742521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9630 11:36:05.749032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9631 11:36:05.752628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9632 11:36:05.759562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9633 11:36:05.762743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9634 11:36:05.765503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9635 11:36:05.772534 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9636 11:36:05.775443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9637 11:36:05.782296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9638 11:36:05.785642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9639 11:36:05.792483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9640 11:36:05.795772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9641 11:36:05.799384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9642 11:36:05.805513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9643 11:36:05.808694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9644 11:36:05.815876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9645 11:36:05.818770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9646 11:36:05.822159 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9647 11:36:05.829189 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9648 11:36:05.832611 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9649 11:36:05.835662 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9650 11:36:05.839012 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9651 11:36:05.845954 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9652 11:36:05.849225 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9653 11:36:05.855276 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9654 11:36:05.858663 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9655 11:36:05.862230 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9656 11:36:05.868726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9657 11:36:05.871762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9658 11:36:05.878666 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9659 11:36:05.882333 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9660 11:36:05.885459 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9661 11:36:05.892492 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9662 11:36:05.895854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9663 11:36:05.901923 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9664 11:36:05.905373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9665 11:36:05.908551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9666 11:36:05.915240 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9667 11:36:05.919009 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9668 11:36:05.922542 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9669 11:36:05.928756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9670 11:36:05.931962 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9671 11:36:05.935211 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9672 11:36:05.939510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9673 11:36:05.945702 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9674 11:36:05.949046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9675 11:36:05.952404 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9676 11:36:05.958712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9677 11:36:05.962210 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9678 11:36:05.966252 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9679 11:36:05.971848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9680 11:36:05.975331 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9681 11:36:05.982165 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9682 11:36:05.985657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9683 11:36:05.988956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9684 11:36:05.995275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9685 11:36:05.998697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9686 11:36:06.005215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9687 11:36:06.008628 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9688 11:36:06.011989 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9689 11:36:06.018630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9690 11:36:06.022328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9691 11:36:06.025628 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9692 11:36:06.032724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9693 11:36:06.035567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9694 11:36:06.042047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9695 11:36:06.045877 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9696 11:36:06.049046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9697 11:36:06.055392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9698 11:36:06.058495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9699 11:36:06.065710 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9700 11:36:06.068874 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9701 11:36:06.072143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9702 11:36:06.079019 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9703 11:36:06.082038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9704 11:36:06.085575 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9705 11:36:06.091696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9706 11:36:06.094929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9707 11:36:06.101315 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9708 11:36:06.104716 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9709 11:36:06.108518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9710 11:36:06.114928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9711 11:36:06.118676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9712 11:36:06.124851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9713 11:36:06.128509 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9714 11:36:06.131823 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9715 11:36:06.138697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9716 11:36:06.141634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9717 11:36:06.148265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9718 11:36:06.151948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9719 11:36:06.154990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9720 11:36:06.161678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9721 11:36:06.165025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9722 11:36:06.168424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9723 11:36:06.175079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9724 11:36:06.178607 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9725 11:36:06.185394 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9726 11:36:06.188398 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9727 11:36:06.192330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9728 11:36:06.198636 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9729 11:36:06.202434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9730 11:36:06.208643 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9731 11:36:06.212534 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9732 11:36:06.215265 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9733 11:36:06.221773 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9734 11:36:06.225347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9735 11:36:06.228471 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9736 11:36:06.235174 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9737 11:36:06.238635 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9738 11:36:06.245631 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9739 11:36:06.248797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9740 11:36:06.255433 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9741 11:36:06.258572 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9742 11:36:06.261924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9743 11:36:06.268616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9744 11:36:06.271934 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9745 11:36:06.278468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9746 11:36:06.282112 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9747 11:36:06.285699 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9748 11:36:06.292009 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9749 11:36:06.294863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9750 11:36:06.301688 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9751 11:36:06.305446 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9752 11:36:06.308672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9753 11:36:06.315002 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9754 11:36:06.318427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9755 11:36:06.325371 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9756 11:36:06.328365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9757 11:36:06.335040 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9758 11:36:06.338134 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9759 11:36:06.341657 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9760 11:36:06.347936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9761 11:36:06.351523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9762 11:36:06.358387 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9763 11:36:06.361540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9764 11:36:06.364632 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9765 11:36:06.371710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9766 11:36:06.375104 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9767 11:36:06.381621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9768 11:36:06.384859 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9769 11:36:06.388286 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9770 11:36:06.394717 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9771 11:36:06.398358 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9772 11:36:06.404748 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9773 11:36:06.408374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9774 11:36:06.414640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9775 11:36:06.418796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9776 11:36:06.421522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9777 11:36:06.428176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9778 11:36:06.431719 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9779 11:36:06.435362 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9780 11:36:06.441616 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9781 11:36:06.444878 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9782 11:36:06.448261 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9783 11:36:06.451474 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9784 11:36:06.458265 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9785 11:36:06.461218 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9786 11:36:06.464741 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9787 11:36:06.471690 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9788 11:36:06.474476 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9789 11:36:06.478456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9790 11:36:06.484771 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9791 11:36:06.487980 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9792 11:36:06.494631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9793 11:36:06.498090 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9794 11:36:06.501825 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9795 11:36:06.508097 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9796 11:36:06.511570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9797 11:36:06.514712 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9798 11:36:06.521939 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9799 11:36:06.524798 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9800 11:36:06.528224 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9801 11:36:06.535259 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9802 11:36:06.538223 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9803 11:36:06.541601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9804 11:36:06.548252 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9805 11:36:06.551428 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9806 11:36:06.557779 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9807 11:36:06.561478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9808 11:36:06.564587 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9809 11:36:06.571126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9810 11:36:06.574723 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9811 11:36:06.581411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9812 11:36:06.584597 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9813 11:36:06.588283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9814 11:36:06.594509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9815 11:36:06.597545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9816 11:36:06.600761 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9817 11:36:06.607501 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9818 11:36:06.610765 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9819 11:36:06.614076 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9820 11:36:06.617643 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9821 11:36:06.623976 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9822 11:36:06.627288 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9823 11:36:06.630786 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9824 11:36:06.634092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9825 11:36:06.640691 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9826 11:36:06.644145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9827 11:36:06.647309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9828 11:36:06.650951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9829 11:36:06.657383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9830 11:36:06.660483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9831 11:36:06.664154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9832 11:36:06.670496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9833 11:36:06.673956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9834 11:36:06.680625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9835 11:36:06.683751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9836 11:36:06.687455 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9837 11:36:06.694048 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9838 11:36:06.697372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9839 11:36:06.703936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9840 11:36:06.707011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9841 11:36:06.710395 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9842 11:36:06.716779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9843 11:36:06.720853 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9844 11:36:06.726767 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9845 11:36:06.730240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9846 11:36:06.737226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9847 11:36:06.740553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9848 11:36:06.743627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9849 11:36:06.750136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9850 11:36:06.753947 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9851 11:36:06.757027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9852 11:36:06.763370 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9853 11:36:06.766768 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9854 11:36:06.773728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9855 11:36:06.777057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9856 11:36:06.780092 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9857 11:36:06.787040 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9858 11:36:06.790114 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9859 11:36:06.796620 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9860 11:36:06.800274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9861 11:36:06.806563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9862 11:36:06.810420 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9863 11:36:06.813510 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9864 11:36:06.819822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9865 11:36:06.823334 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9866 11:36:06.829632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9867 11:36:06.832975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9868 11:36:06.836474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9869 11:36:06.843880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9870 11:36:06.847026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9871 11:36:06.853576 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9872 11:36:06.856989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9873 11:36:06.860325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9874 11:36:06.867003 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9875 11:36:06.870216 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9876 11:36:06.876816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9877 11:36:06.880299 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9878 11:36:06.883354 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9879 11:36:06.890218 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9880 11:36:06.893058 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9881 11:36:06.899999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9882 11:36:06.903342 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9883 11:36:06.906803 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9884 11:36:06.913470 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9885 11:36:06.916490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9886 11:36:06.923485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9887 11:36:06.926558 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9888 11:36:06.929898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9889 11:36:06.936451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9890 11:36:06.940072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9891 11:36:06.946493 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9892 11:36:06.949645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9893 11:36:06.956364 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9894 11:36:06.959651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9895 11:36:06.963035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9896 11:36:06.970387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9897 11:36:06.972896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9898 11:36:06.979876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9899 11:36:06.983435 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9900 11:36:06.986728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9901 11:36:06.993484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9902 11:36:06.996618 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9903 11:36:06.999930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9904 11:36:07.006310 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9905 11:36:07.009955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9906 11:36:07.016195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9907 11:36:07.019347 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9908 11:36:07.026341 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9909 11:36:07.029283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9910 11:36:07.036188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9911 11:36:07.039099 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9912 11:36:07.042695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9913 11:36:07.049125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9914 11:36:07.052701 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9915 11:36:07.059420 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9916 11:36:07.062558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9917 11:36:07.069372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9918 11:36:07.073022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9919 11:36:07.075947 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9920 11:36:07.083024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9921 11:36:07.086435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9922 11:36:07.092600 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9923 11:36:07.096229 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9924 11:36:07.099555 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9925 11:36:07.106384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9926 11:36:07.109690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9927 11:36:07.116680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9928 11:36:07.119404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9929 11:36:07.126054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9930 11:36:07.129448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9931 11:36:07.132621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9932 11:36:07.139432 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9933 11:36:07.142697 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9934 11:36:07.149780 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9935 11:36:07.152596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9936 11:36:07.159627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9937 11:36:07.162853 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9938 11:36:07.169264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9939 11:36:07.172926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9940 11:36:07.175973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9941 11:36:07.182978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9942 11:36:07.185711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9943 11:36:07.192497 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9944 11:36:07.195664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9945 11:36:07.202529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9946 11:36:07.205967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9947 11:36:07.209298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9948 11:36:07.216252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9949 11:36:07.219224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9950 11:36:07.226258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9951 11:36:07.229101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9952 11:36:07.232806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9953 11:36:07.239346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9954 11:36:07.242744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9955 11:36:07.249178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9956 11:36:07.252494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9957 11:36:07.259403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9958 11:36:07.262721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9959 11:36:07.269747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9960 11:36:07.272584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9961 11:36:07.279338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9962 11:36:07.282556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9963 11:36:07.289085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9964 11:36:07.292844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9965 11:36:07.295661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9966 11:36:07.302242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9967 11:36:07.305691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9968 11:36:07.312450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9969 11:36:07.315728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9970 11:36:07.322601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9971 11:36:07.325718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9972 11:36:07.332535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9973 11:36:07.335973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9974 11:36:07.342772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9975 11:36:07.345628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9976 11:36:07.352323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9977 11:36:07.355530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9978 11:36:07.362211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9979 11:36:07.365881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9980 11:36:07.372264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9981 11:36:07.376054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9982 11:36:07.382524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9983 11:36:07.385946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9984 11:36:07.392080 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9985 11:36:07.392152 INFO: [APUAPC] vio 0
9986 11:36:07.399237 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9987 11:36:07.402602 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9988 11:36:07.405675 INFO: [APUAPC] D0_APC_0: 0x400510
9989 11:36:07.409148 INFO: [APUAPC] D0_APC_1: 0x0
9990 11:36:07.412660 INFO: [APUAPC] D0_APC_2: 0x1540
9991 11:36:07.415833 INFO: [APUAPC] D0_APC_3: 0x0
9992 11:36:07.419213 INFO: [APUAPC] D1_APC_0: 0xffffffff
9993 11:36:07.422248 INFO: [APUAPC] D1_APC_1: 0xffffffff
9994 11:36:07.426234 INFO: [APUAPC] D1_APC_2: 0x3fffff
9995 11:36:07.428862 INFO: [APUAPC] D1_APC_3: 0x0
9996 11:36:07.432316 INFO: [APUAPC] D2_APC_0: 0xffffffff
9997 11:36:07.435696 INFO: [APUAPC] D2_APC_1: 0xffffffff
9998 11:36:07.438980 INFO: [APUAPC] D2_APC_2: 0x3fffff
9999 11:36:07.442576 INFO: [APUAPC] D2_APC_3: 0x0
10000 11:36:07.445596 INFO: [APUAPC] D3_APC_0: 0xffffffff
10001 11:36:07.449200 INFO: [APUAPC] D3_APC_1: 0xffffffff
10002 11:36:07.452464 INFO: [APUAPC] D3_APC_2: 0x3fffff
10003 11:36:07.455899 INFO: [APUAPC] D3_APC_3: 0x0
10004 11:36:07.459219 INFO: [APUAPC] D4_APC_0: 0xffffffff
10005 11:36:07.462403 INFO: [APUAPC] D4_APC_1: 0xffffffff
10006 11:36:07.465386 INFO: [APUAPC] D4_APC_2: 0x3fffff
10007 11:36:07.465458 INFO: [APUAPC] D4_APC_3: 0x0
10008 11:36:07.468815 INFO: [APUAPC] D5_APC_0: 0xffffffff
10009 11:36:07.471966 INFO: [APUAPC] D5_APC_1: 0xffffffff
10010 11:36:07.475473 INFO: [APUAPC] D5_APC_2: 0x3fffff
10011 11:36:07.478586 INFO: [APUAPC] D5_APC_3: 0x0
10012 11:36:07.482038 INFO: [APUAPC] D6_APC_0: 0xffffffff
10013 11:36:07.485190 INFO: [APUAPC] D6_APC_1: 0xffffffff
10014 11:36:07.488596 INFO: [APUAPC] D6_APC_2: 0x3fffff
10015 11:36:07.492488 INFO: [APUAPC] D6_APC_3: 0x0
10016 11:36:07.495461 INFO: [APUAPC] D7_APC_0: 0xffffffff
10017 11:36:07.498917 INFO: [APUAPC] D7_APC_1: 0xffffffff
10018 11:36:07.501945 INFO: [APUAPC] D7_APC_2: 0x3fffff
10019 11:36:07.505332 INFO: [APUAPC] D7_APC_3: 0x0
10020 11:36:07.508591 INFO: [APUAPC] D8_APC_0: 0xffffffff
10021 11:36:07.512005 INFO: [APUAPC] D8_APC_1: 0xffffffff
10022 11:36:07.515614 INFO: [APUAPC] D8_APC_2: 0x3fffff
10023 11:36:07.518979 INFO: [APUAPC] D8_APC_3: 0x0
10024 11:36:07.522353 INFO: [APUAPC] D9_APC_0: 0xffffffff
10025 11:36:07.525596 INFO: [APUAPC] D9_APC_1: 0xffffffff
10026 11:36:07.528692 INFO: [APUAPC] D9_APC_2: 0x3fffff
10027 11:36:07.532514 INFO: [APUAPC] D9_APC_3: 0x0
10028 11:36:07.535957 INFO: [APUAPC] D10_APC_0: 0xffffffff
10029 11:36:07.538953 INFO: [APUAPC] D10_APC_1: 0xffffffff
10030 11:36:07.542760 INFO: [APUAPC] D10_APC_2: 0x3fffff
10031 11:36:07.545386 INFO: [APUAPC] D10_APC_3: 0x0
10032 11:36:07.549125 INFO: [APUAPC] D11_APC_0: 0xffffffff
10033 11:36:07.552472 INFO: [APUAPC] D11_APC_1: 0xffffffff
10034 11:36:07.555327 INFO: [APUAPC] D11_APC_2: 0x3fffff
10035 11:36:07.558754 INFO: [APUAPC] D11_APC_3: 0x0
10036 11:36:07.562583 INFO: [APUAPC] D12_APC_0: 0xffffffff
10037 11:36:07.565541 INFO: [APUAPC] D12_APC_1: 0xffffffff
10038 11:36:07.569157 INFO: [APUAPC] D12_APC_2: 0x3fffff
10039 11:36:07.572632 INFO: [APUAPC] D12_APC_3: 0x0
10040 11:36:07.575524 INFO: [APUAPC] D13_APC_0: 0xffffffff
10041 11:36:07.579141 INFO: [APUAPC] D13_APC_1: 0xffffffff
10042 11:36:07.582448 INFO: [APUAPC] D13_APC_2: 0x3fffff
10043 11:36:07.585508 INFO: [APUAPC] D13_APC_3: 0x0
10044 11:36:07.589034 INFO: [APUAPC] D14_APC_0: 0xffffffff
10045 11:36:07.592610 INFO: [APUAPC] D14_APC_1: 0xffffffff
10046 11:36:07.595560 INFO: [APUAPC] D14_APC_2: 0x3fffff
10047 11:36:07.599164 INFO: [APUAPC] D14_APC_3: 0x0
10048 11:36:07.602281 INFO: [APUAPC] D15_APC_0: 0xffffffff
10049 11:36:07.605700 INFO: [APUAPC] D15_APC_1: 0xffffffff
10050 11:36:07.608910 INFO: [APUAPC] D15_APC_2: 0x3fffff
10051 11:36:07.612505 INFO: [APUAPC] D15_APC_3: 0x0
10052 11:36:07.615948 INFO: [APUAPC] APC_CON: 0x4
10053 11:36:07.619204 INFO: [NOCDAPC] D0_APC_0: 0x0
10054 11:36:07.622639 INFO: [NOCDAPC] D0_APC_1: 0x0
10055 11:36:07.623019 INFO: [NOCDAPC] D1_APC_0: 0x0
10056 11:36:07.626020 INFO: [NOCDAPC] D1_APC_1: 0xfff
10057 11:36:07.628975 INFO: [NOCDAPC] D2_APC_0: 0x0
10058 11:36:07.632603 INFO: [NOCDAPC] D2_APC_1: 0xfff
10059 11:36:07.636379 INFO: [NOCDAPC] D3_APC_0: 0x0
10060 11:36:07.639198 INFO: [NOCDAPC] D3_APC_1: 0xfff
10061 11:36:07.642392 INFO: [NOCDAPC] D4_APC_0: 0x0
10062 11:36:07.645808 INFO: [NOCDAPC] D4_APC_1: 0xfff
10063 11:36:07.649341 INFO: [NOCDAPC] D5_APC_0: 0x0
10064 11:36:07.652268 INFO: [NOCDAPC] D5_APC_1: 0xfff
10065 11:36:07.655491 INFO: [NOCDAPC] D6_APC_0: 0x0
10066 11:36:07.655888 INFO: [NOCDAPC] D6_APC_1: 0xfff
10067 11:36:07.659215 INFO: [NOCDAPC] D7_APC_0: 0x0
10068 11:36:07.662813 INFO: [NOCDAPC] D7_APC_1: 0xfff
10069 11:36:07.665698 INFO: [NOCDAPC] D8_APC_0: 0x0
10070 11:36:07.669056 INFO: [NOCDAPC] D8_APC_1: 0xfff
10071 11:36:07.672404 INFO: [NOCDAPC] D9_APC_0: 0x0
10072 11:36:07.675646 INFO: [NOCDAPC] D9_APC_1: 0xfff
10073 11:36:07.679468 INFO: [NOCDAPC] D10_APC_0: 0x0
10074 11:36:07.682396 INFO: [NOCDAPC] D10_APC_1: 0xfff
10075 11:36:07.685583 INFO: [NOCDAPC] D11_APC_0: 0x0
10076 11:36:07.688920 INFO: [NOCDAPC] D11_APC_1: 0xfff
10077 11:36:07.692004 INFO: [NOCDAPC] D12_APC_0: 0x0
10078 11:36:07.695468 INFO: [NOCDAPC] D12_APC_1: 0xfff
10079 11:36:07.695934 INFO: [NOCDAPC] D13_APC_0: 0x0
10080 11:36:07.698826 INFO: [NOCDAPC] D13_APC_1: 0xfff
10081 11:36:07.701982 INFO: [NOCDAPC] D14_APC_0: 0x0
10082 11:36:07.705947 INFO: [NOCDAPC] D14_APC_1: 0xfff
10083 11:36:07.708967 INFO: [NOCDAPC] D15_APC_0: 0x0
10084 11:36:07.712432 INFO: [NOCDAPC] D15_APC_1: 0xfff
10085 11:36:07.715461 INFO: [NOCDAPC] APC_CON: 0x4
10086 11:36:07.718590 INFO: [APUAPC] set_apusys_apc done
10087 11:36:07.722015 INFO: [DEVAPC] devapc_init done
10088 11:36:07.725428 INFO: GICv3 without legacy support detected.
10089 11:36:07.728837 INFO: ARM GICv3 driver initialized in EL3
10090 11:36:07.732205 INFO: Maximum SPI INTID supported: 639
10091 11:36:07.739353 INFO: BL31: Initializing runtime services
10092 11:36:07.741997 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10093 11:36:07.745348 INFO: SPM: enable CPC mode
10094 11:36:07.752781 INFO: mcdi ready for mcusys-off-idle and system suspend
10095 11:36:07.755975 INFO: BL31: Preparing for EL3 exit to normal world
10096 11:36:07.758956 INFO: Entry point address = 0x80000000
10097 11:36:07.762371 INFO: SPSR = 0x8
10098 11:36:07.767668
10099 11:36:07.768043
10100 11:36:07.768338
10101 11:36:07.771081 Starting depthcharge on Spherion...
10102 11:36:07.771462
10103 11:36:07.771757 Wipe memory regions:
10104 11:36:07.772031
10105 11:36:07.774392 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10106 11:36:07.774846 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10107 11:36:07.775192 Setting prompt string to ['asurada:']
10108 11:36:07.775506 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10109 11:36:07.776088 [0x00000040000000, 0x00000054600000)
10110 11:36:07.896086
10111 11:36:07.896538 [0x00000054660000, 0x00000080000000)
10112 11:36:08.157168
10113 11:36:08.157709 [0x000000821a7280, 0x000000ffe64000)
10114 11:36:08.901108
10115 11:36:08.901728 [0x00000100000000, 0x00000240000000)
10116 11:36:10.790757
10117 11:36:10.793816 Initializing XHCI USB controller at 0x11200000.
10118 11:36:11.832206
10119 11:36:11.835181 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10120 11:36:11.835251
10121 11:36:11.835329
10122 11:36:11.835613 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 11:36:11.835706 Sending line: 'tftpboot 192.168.201.1 14864627/tftp-deploy-ijd5ck1a/kernel/image.itb 14864627/tftp-deploy-ijd5ck1a/kernel/cmdline '
10125 11:36:11.936724 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 11:36:11.937179 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:15)
10127 11:36:11.941614 asurada: tftpboot 192.168.201.1 14864627/tftp-deploy-ijd5ck1a/kernel/image.ittp-deploy-ijd5ck1a/kernel/cmdline
10128 11:36:11.942025
10129 11:36:11.942351 Waiting for link
10130 11:36:12.099279
10131 11:36:12.099405 R8152: Initializing
10132 11:36:12.099467
10133 11:36:12.102458 Version 6 (ocp_data = 5c30)
10134 11:36:12.102544
10135 11:36:12.105666 R8152: Done initializing
10136 11:36:12.105732
10137 11:36:12.105785 Adding net device
10138 11:36:13.979310
10139 11:36:13.979800 done.
10140 11:36:13.980257
10141 11:36:13.980587 MAC: 00:24:32:30:78:52
10142 11:36:13.981019
10143 11:36:13.983001 Sending DHCP discover... done.
10144 11:36:13.983457
10145 11:36:13.986022 Waiting for reply... done.
10146 11:36:13.986465
10147 11:36:13.989644 Sending DHCP request... done.
10148 11:36:13.990030
10149 11:36:13.994797 Waiting for reply... done.
10150 11:36:13.994963
10151 11:36:13.995093 My ip is 192.168.201.14
10152 11:36:13.995214
10153 11:36:13.998068 The DHCP server ip is 192.168.201.1
10154 11:36:13.998262
10155 11:36:14.004373 TFTP server IP predefined by user: 192.168.201.1
10156 11:36:14.004731
10157 11:36:14.011620 Bootfile predefined by user: 14864627/tftp-deploy-ijd5ck1a/kernel/image.itb
10158 11:36:14.012010
10159 11:36:14.012307 Sending tftp read request... done.
10160 11:36:14.014429
10161 11:36:14.021812 Waiting for the transfer...
10162 11:36:14.022195
10163 11:36:14.609616 00000000 ################################################################
10164 11:36:14.609730
10165 11:36:15.187122 00080000 ################################################################
10166 11:36:15.187234
10167 11:36:15.760960 00100000 ################################################################
10168 11:36:15.761087
10169 11:36:16.379386 00180000 ################################################################
10170 11:36:16.379526
10171 11:36:17.013097 00200000 ################################################################
10172 11:36:17.013575
10173 11:36:17.677050 00280000 ################################################################
10174 11:36:17.677212
10175 11:36:18.262263 00300000 ################################################################
10176 11:36:18.262382
10177 11:36:18.920994 00380000 ################################################################
10178 11:36:18.921464
10179 11:36:19.584574 00400000 ################################################################
10180 11:36:19.584683
10181 11:36:20.219417 00480000 ################################################################
10182 11:36:20.219547
10183 11:36:20.858214 00500000 ################################################################
10184 11:36:20.858401
10185 11:36:21.530952 00580000 ################################################################
10186 11:36:21.531419
10187 11:36:22.238243 00600000 ################################################################
10188 11:36:22.238373
10189 11:36:22.946572 00680000 ################################################################
10190 11:36:22.946701
10191 11:36:23.549364 00700000 ################################################################
10192 11:36:23.549489
10193 11:36:24.171496 00780000 ################################################################
10194 11:36:24.171625
10195 11:36:24.778159 00800000 ################################################################
10196 11:36:24.778284
10197 11:36:25.369889 00880000 ################################################################
10198 11:36:25.370017
10199 11:36:26.017266 00900000 ################################################################
10200 11:36:26.017395
10201 11:36:26.622147 00980000 ################################################################
10202 11:36:26.622266
10203 11:36:27.175351 00a00000 ################################################################
10204 11:36:27.175465
10205 11:36:27.779556 00a80000 ################################################################
10206 11:36:27.779671
10207 11:36:28.394080 00b00000 ################################################################
10208 11:36:28.394190
10209 11:36:29.012633 00b80000 ################################################################
10210 11:36:29.012750
10211 11:36:29.607309 00c00000 ################################################################
10212 11:36:29.607433
10213 11:36:30.199199 00c80000 ################################################################
10214 11:36:30.199335
10215 11:36:30.805058 00d00000 ################################################################
10216 11:36:30.805233
10217 11:36:31.400587 00d80000 ################################################################
10218 11:36:31.400721
10219 11:36:31.996715 00e00000 ################################################################
10220 11:36:31.996824
10221 11:36:32.606116 00e80000 ################################################################
10222 11:36:32.606228
10223 11:36:33.204690 00f00000 ################################################################
10224 11:36:33.204803
10225 11:36:33.767795 00f80000 ################################################################
10226 11:36:33.767926
10227 11:36:34.316710 01000000 ################################################################
10228 11:36:34.316824
10229 11:36:34.881033 01080000 ################################################################
10230 11:36:34.881185
10231 11:36:35.442931 01100000 ################################################################
10232 11:36:35.443044
10233 11:36:36.008984 01180000 ################################################################
10234 11:36:36.009101
10235 11:36:36.600453 01200000 ################################################################
10236 11:36:36.600569
10237 11:36:37.185226 01280000 ################################################################
10238 11:36:37.185762
10239 11:36:37.860760 01300000 ################################################################
10240 11:36:37.861379
10241 11:36:38.509141 01380000 ################################################################
10242 11:36:38.509252
10243 11:36:39.095117 01400000 ################################################################
10244 11:36:39.095252
10245 11:36:39.714318 01480000 ################################################################
10246 11:36:39.714470
10247 11:36:40.306333 01500000 ################################################################
10248 11:36:40.306448
10249 11:36:40.892787 01580000 ################################################################
10250 11:36:40.892902
10251 11:36:41.481875 01600000 ################################################################
10252 11:36:41.481989
10253 11:36:42.068857 01680000 ################################################################
10254 11:36:42.068970
10255 11:36:42.661252 01700000 ################################################################
10256 11:36:42.661367
10257 11:36:43.231592 01780000 ################################################################
10258 11:36:43.231705
10259 11:36:43.812453 01800000 ################################################################
10260 11:36:43.812569
10261 11:36:44.376183 01880000 ################################################################
10262 11:36:44.376298
10263 11:36:44.948285 01900000 ################################################################
10264 11:36:44.948399
10265 11:36:45.502113 01980000 ################################################################
10266 11:36:45.502228
10267 11:36:46.058341 01a00000 ################################################################
10268 11:36:46.058453
10269 11:36:46.622331 01a80000 ################################################################
10270 11:36:46.622452
10271 11:36:47.201327 01b00000 ################################################################
10272 11:36:47.201436
10273 11:36:47.780351 01b80000 ################################################################
10274 11:36:47.780466
10275 11:36:48.341369 01c00000 ################################################################
10276 11:36:48.341480
10277 11:36:48.912011 01c80000 ################################################################
10278 11:36:48.912130
10279 11:36:49.494132 01d00000 ################################################################
10280 11:36:49.494244
10281 11:36:50.123822 01d80000 ################################################################
10282 11:36:50.124261
10283 11:36:50.628587 01e00000 ###################################################### done.
10284 11:36:50.628700
10285 11:36:50.632078 The bootfile was 31893562 bytes long.
10286 11:36:50.632153
10287 11:36:50.635398 Sending tftp read request... done.
10288 11:36:50.635474
10289 11:36:50.639199 Waiting for the transfer...
10290 11:36:50.639275
10291 11:36:50.642013 00000000 # done.
10292 11:36:50.642094
10293 11:36:50.649135 Command line loaded dynamically from TFTP file: 14864627/tftp-deploy-ijd5ck1a/kernel/cmdline
10294 11:36:50.649224
10295 11:36:50.672563 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10296 11:36:50.672687
10297 11:36:50.672774 Loading FIT.
10298 11:36:50.672855
10299 11:36:50.675754 Image ramdisk-1 has 18725982 bytes.
10300 11:36:50.675877
10301 11:36:50.678716 Image fdt-1 has 47258 bytes.
10302 11:36:50.678838
10303 11:36:50.682265 Image kernel-1 has 13118294 bytes.
10304 11:36:50.682404
10305 11:36:50.689451 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10306 11:36:50.689648
10307 11:36:50.705971 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10308 11:36:50.709590
10309 11:36:50.712667 Choosing best match conf-1 for compat google,spherion-rev2.
10310 11:36:50.717579
10311 11:36:50.722059 Connected to device vid:did:rid of 1ae0:0028:00
10312 11:36:50.730149
10313 11:36:50.733268 tpm_get_response: command 0x17b, return code 0x0
10314 11:36:50.733691
10315 11:36:50.740037 ec_init: CrosEC protocol v3 supported (256, 248)
10316 11:36:50.740423
10317 11:36:50.743528 tpm_cleanup: add release locality here.
10318 11:36:50.743910
10319 11:36:50.746704 Shutting down all USB controllers.
10320 11:36:50.747082
10321 11:36:50.750443 Removing current net device
10322 11:36:50.750822
10323 11:36:50.753712 Exiting depthcharge with code 4 at timestamp: 72423156
10324 11:36:50.754092
10325 11:36:50.756758 LZMA decompressing kernel-1 to 0x821a6718
10326 11:36:50.757278
10327 11:36:50.763527 LZMA decompressing kernel-1 to 0x40000000
10328 11:36:52.377994
10329 11:36:52.378434 jumping to kernel
10330 11:36:52.380021 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10331 11:36:52.380475 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10332 11:36:52.380821 Setting prompt string to ['Linux version [0-9]']
10333 11:36:52.381167 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10334 11:36:52.381493 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10335 11:36:52.458858
10336 11:36:52.462303 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10337 11:36:52.466018 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10338 11:36:52.466447 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10339 11:36:52.466780 Setting prompt string to []
10340 11:36:52.467134 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 11:36:52.467455 Using line separator: #'\n'#
10342 11:36:52.467722 No login prompt set.
10343 11:36:52.467996 Parsing kernel messages
10344 11:36:52.468246 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 11:36:52.468729 [login-action] Waiting for messages, (timeout 00:03:35)
10346 11:36:52.469013 Waiting using forced prompt support (timeout 00:01:47)
10347 11:36:52.485703 [ 0.000000] Linux version 6.1.96-cip24 (KernelCI@build-j270465-arm64-gcc-12-defconfig-arm64-chromebook-hjsv4) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024
10348 11:36:52.488584 [ 0.000000] random: crng init done
10349 11:36:52.492122 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10350 11:36:52.495089 [ 0.000000] efi: UEFI not found.
10351 11:36:52.504992 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10352 11:36:52.512557 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10353 11:36:52.522045 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10354 11:36:52.531457 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10355 11:36:52.538258 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10356 11:36:52.541461 [ 0.000000] printk: bootconsole [mtk8250] enabled
10357 11:36:52.550110 [ 0.000000] NUMA: No NUMA configuration found
10358 11:36:52.556833 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10359 11:36:52.563277 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10360 11:36:52.563656 [ 0.000000] Zone ranges:
10361 11:36:52.570032 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10362 11:36:52.573290 [ 0.000000] DMA32 empty
10363 11:36:52.579591 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10364 11:36:52.583306 [ 0.000000] Movable zone start for each node
10365 11:36:52.586340 [ 0.000000] Early memory node ranges
10366 11:36:52.593476 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10367 11:36:52.599584 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10368 11:36:52.606203 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10369 11:36:52.612983 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10370 11:36:52.619743 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10371 11:36:52.626666 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10372 11:36:52.682890 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10373 11:36:52.689411 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10374 11:36:52.696249 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10375 11:36:52.700346 [ 0.000000] psci: probing for conduit method from DT.
10376 11:36:52.706423 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10377 11:36:52.709551 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10378 11:36:52.716230 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10379 11:36:52.719919 [ 0.000000] psci: SMC Calling Convention v1.2
10380 11:36:52.726198 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10381 11:36:52.729525 [ 0.000000] Detected VIPT I-cache on CPU0
10382 11:36:52.736331 [ 0.000000] CPU features: detected: GIC system register CPU interface
10383 11:36:52.743234 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10384 11:36:52.750140 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10385 11:36:52.756960 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10386 11:36:52.763574 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10387 11:36:52.770002 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10388 11:36:52.776413 [ 0.000000] alternatives: applying boot alternatives
10389 11:36:52.780171 [ 0.000000] Fallback order for Node 0: 0
10390 11:36:52.787002 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10391 11:36:52.790200 [ 0.000000] Policy zone: Normal
10392 11:36:52.813475 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10393 11:36:52.826282 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10394 11:36:52.836883 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10395 11:36:52.846010 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10396 11:36:52.852741 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
10397 11:36:52.856031 <6>[ 0.000000] software IO TLB: area num 8.
10398 11:36:52.912835 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10399 11:36:53.062697 <6>[ 0.000000] Memory: 7945772K/8385536K available (18112K kernel code, 4120K rwdata, 22640K rodata, 8512K init, 615K bss, 406996K reserved, 32768K cma-reserved)
10400 11:36:53.069027 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10401 11:36:53.075738 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10402 11:36:53.079071 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10403 11:36:53.085345 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10404 11:36:53.092128 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10405 11:36:53.095904 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10406 11:36:53.105731 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10407 11:36:53.112556 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10408 11:36:53.115496 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10409 11:36:53.123617 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10410 11:36:53.126915 <6>[ 0.000000] GICv3: 608 SPIs implemented
10411 11:36:53.133897 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10412 11:36:53.136987 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10413 11:36:53.140559 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10414 11:36:53.150382 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10415 11:36:53.160335 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10416 11:36:53.173463 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10417 11:36:53.179769 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10418 11:36:53.189097 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10419 11:36:53.202550 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10420 11:36:53.209107 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10421 11:36:53.215495 <6>[ 0.009174] Console: colour dummy device 80x25
10422 11:36:53.225978 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10423 11:36:53.229685 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10424 11:36:53.236138 <6>[ 0.029219] LSM: Security Framework initializing
10425 11:36:53.242413 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 11:36:53.252442 <6>[ 0.041970] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 11:36:53.259222 <6>[ 0.051389] cblist_init_generic: Setting adjustable number of callback queues.
10428 11:36:53.265654 <6>[ 0.058830] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 11:36:53.272431 <6>[ 0.065168] cblist_init_generic: Setting adjustable number of callback queues.
10430 11:36:53.279048 <6>[ 0.072595] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 11:36:53.285324 <6>[ 0.078997] rcu: Hierarchical SRCU implementation.
10432 11:36:53.291951 <6>[ 0.084012] rcu: Max phase no-delay instances is 1000.
10433 11:36:53.295508 <6>[ 0.091046] EFI services will not be available.
10434 11:36:53.302421 <6>[ 0.096002] smp: Bringing up secondary CPUs ...
10435 11:36:53.309495 <6>[ 0.101053] Detected VIPT I-cache on CPU1
10436 11:36:53.316189 <6>[ 0.101123] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10437 11:36:53.322908 <6>[ 0.101153] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10438 11:36:53.326294 <6>[ 0.101501] Detected VIPT I-cache on CPU2
10439 11:36:53.333026 <6>[ 0.101555] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10440 11:36:53.343209 <6>[ 0.101572] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10441 11:36:53.346512 <6>[ 0.101833] Detected VIPT I-cache on CPU3
10442 11:36:53.352972 <6>[ 0.101882] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10443 11:36:53.359815 <6>[ 0.101896] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10444 11:36:53.362946 <6>[ 0.102205] CPU features: detected: Spectre-v4
10445 11:36:53.369678 <6>[ 0.102211] CPU features: detected: Spectre-BHB
10446 11:36:53.372938 <6>[ 0.102217] Detected PIPT I-cache on CPU4
10447 11:36:53.379825 <6>[ 0.102278] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10448 11:36:53.386205 <6>[ 0.102296] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10449 11:36:53.393393 <6>[ 0.102589] Detected PIPT I-cache on CPU5
10450 11:36:53.399698 <6>[ 0.102651] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10451 11:36:53.406567 <6>[ 0.102667] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10452 11:36:53.409901 <6>[ 0.102951] Detected PIPT I-cache on CPU6
10453 11:36:53.416354 <6>[ 0.103016] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10454 11:36:53.423220 <6>[ 0.103032] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10455 11:36:53.426411 <6>[ 0.103329] Detected PIPT I-cache on CPU7
10456 11:36:53.436268 <6>[ 0.103387] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10457 11:36:53.442903 <6>[ 0.103402] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10458 11:36:53.446116 <6>[ 0.103449] smp: Brought up 1 node, 8 CPUs
10459 11:36:53.449804 <6>[ 0.244811] SMP: Total of 8 processors activated.
10460 11:36:53.456157 <6>[ 0.249732] CPU features: detected: 32-bit EL0 Support
10461 11:36:53.466156 <6>[ 0.255096] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10462 11:36:53.472792 <6>[ 0.263896] CPU features: detected: Common not Private translations
10463 11:36:53.476367 <6>[ 0.270372] CPU features: detected: CRC32 instructions
10464 11:36:53.483299 <6>[ 0.275757] CPU features: detected: RCpc load-acquire (LDAPR)
10465 11:36:53.489549 <6>[ 0.281717] CPU features: detected: LSE atomic instructions
10466 11:36:53.496098 <6>[ 0.287534] CPU features: detected: Privileged Access Never
10467 11:36:53.499466 <6>[ 0.293314] CPU features: detected: RAS Extension Support
10468 11:36:53.506332 <6>[ 0.298922] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10469 11:36:53.512752 <6>[ 0.306186] CPU: All CPU(s) started at EL2
10470 11:36:53.519142 <6>[ 0.310502] alternatives: applying system-wide alternatives
10471 11:36:53.527741 <6>[ 0.321371] devtmpfs: initialized
10472 11:36:53.539950 <6>[ 0.330191] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10473 11:36:53.550089 <6>[ 0.340153] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10474 11:36:53.556650 <6>[ 0.348411] pinctrl core: initialized pinctrl subsystem
10475 11:36:53.560531 <6>[ 0.355045] DMI not present or invalid.
10476 11:36:53.566642 <6>[ 0.359458] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10477 11:36:53.576727 <6>[ 0.366366] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10478 11:36:53.583280 <6>[ 0.373952] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10479 11:36:53.593728 <6>[ 0.382184] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10480 11:36:53.596488 <6>[ 0.390425] audit: initializing netlink subsys (disabled)
10481 11:36:53.606451 <5>[ 0.396124] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10482 11:36:53.613043 <6>[ 0.396846] thermal_sys: Registered thermal governor 'step_wise'
10483 11:36:53.620105 <6>[ 0.404088] thermal_sys: Registered thermal governor 'power_allocator'
10484 11:36:53.623772 <6>[ 0.410344] cpuidle: using governor menu
10485 11:36:53.629784 <6>[ 0.421307] NET: Registered PF_QIPCRTR protocol family
10486 11:36:53.636205 <6>[ 0.426843] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10487 11:36:53.639709 <6>[ 0.433948] ASID allocator initialised with 32768 entries
10488 11:36:53.647348 <6>[ 0.440533] Serial: AMBA PL011 UART driver
10489 11:36:53.656436 <4>[ 0.449897] Trying to register duplicate clock ID: 134
10490 11:36:53.714330 <6>[ 0.511349] KASLR enabled
10491 11:36:53.729005 <6>[ 0.519014] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10492 11:36:53.735279 <6>[ 0.526025] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10493 11:36:53.741723 <6>[ 0.532512] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10494 11:36:53.748849 <6>[ 0.539516] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10495 11:36:53.756231 <6>[ 0.546000] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10496 11:36:53.762085 <6>[ 0.553003] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10497 11:36:53.769088 <6>[ 0.559491] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10498 11:36:53.774900 <6>[ 0.566493] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10499 11:36:53.778844 <6>[ 0.574003] ACPI: Interpreter disabled.
10500 11:36:53.787099 <6>[ 0.580430] iommu: Default domain type: Translated
10501 11:36:53.794105 <6>[ 0.585540] iommu: DMA domain TLB invalidation policy: strict mode
10502 11:36:53.796847 <5>[ 0.592190] SCSI subsystem initialized
10503 11:36:53.803421 <6>[ 0.596352] usbcore: registered new interface driver usbfs
10504 11:36:53.810286 <6>[ 0.602082] usbcore: registered new interface driver hub
10505 11:36:53.813385 <6>[ 0.607635] usbcore: registered new device driver usb
10506 11:36:53.820135 <6>[ 0.613738] pps_core: LinuxPPS API ver. 1 registered
10507 11:36:53.830357 <6>[ 0.618927] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10508 11:36:53.833694 <6>[ 0.628272] PTP clock support registered
10509 11:36:53.837014 <6>[ 0.632517] EDAC MC: Ver: 3.0.0
10510 11:36:53.844211 <6>[ 0.637678] FPGA manager framework
10511 11:36:53.850810 <6>[ 0.641363] Advanced Linux Sound Architecture Driver Initialized.
10512 11:36:53.854479 <6>[ 0.648153] vgaarb: loaded
10513 11:36:53.860450 <6>[ 0.651338] clocksource: Switched to clocksource arch_sys_counter
10514 11:36:53.864048 <5>[ 0.657783] VFS: Disk quotas dquot_6.6.0
10515 11:36:53.870568 <6>[ 0.661972] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10516 11:36:53.873880 <6>[ 0.669154] pnp: PnP ACPI: disabled
10517 11:36:53.882869 <6>[ 0.675840] NET: Registered PF_INET protocol family
10518 11:36:53.889187 <6>[ 0.681425] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10519 11:36:53.903884 <6>[ 0.693728] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10520 11:36:53.913434 <6>[ 0.702541] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10521 11:36:53.920248 <6>[ 0.710512] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10522 11:36:53.926947 <6>[ 0.719213] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10523 11:36:53.938989 <6>[ 0.728965] TCP: Hash tables configured (established 65536 bind 65536)
10524 11:36:53.945660 <6>[ 0.735836] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 11:36:53.951913 <6>[ 0.743035] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 11:36:53.959006 <6>[ 0.750739] NET: Registered PF_UNIX/PF_LOCAL protocol family
10527 11:36:53.965413 <6>[ 0.756885] RPC: Registered named UNIX socket transport module.
10528 11:36:53.968832 <6>[ 0.763037] RPC: Registered udp transport module.
10529 11:36:53.975038 <6>[ 0.767972] RPC: Registered tcp transport module.
10530 11:36:53.981775 <6>[ 0.772906] RPC: Registered tcp NFSv4.1 backchannel transport module.
10531 11:36:53.985436 <6>[ 0.779573] PCI: CLS 0 bytes, default 64
10532 11:36:53.988752 <6>[ 0.783976] Unpacking initramfs...
10533 11:36:53.998774 <6>[ 0.787680] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10534 11:36:54.005972 <6>[ 0.796314] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10535 11:36:54.012848 <6>[ 0.805124] kvm [1]: IPA Size Limit: 40 bits
10536 11:36:54.015138 <6>[ 0.809647] kvm [1]: GICv3: no GICV resource entry
10537 11:36:54.022030 <6>[ 0.814665] kvm [1]: disabling GICv2 emulation
10538 11:36:54.025314 <6>[ 0.819349] kvm [1]: GIC system register CPU interface enabled
10539 11:36:54.032555 <6>[ 0.825509] kvm [1]: vgic interrupt IRQ18
10540 11:36:54.038815 <6>[ 0.831387] kvm [1]: VHE mode initialized successfully
10541 11:36:54.042647 <5>[ 0.837772] Initialise system trusted keyrings
10542 11:36:54.048907 <6>[ 0.842572] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10543 11:36:54.058921 <6>[ 0.852554] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10544 11:36:54.066072 <5>[ 0.858947] NFS: Registering the id_resolver key type
10545 11:36:54.069055 <5>[ 0.864248] Key type id_resolver registered
10546 11:36:54.075705 <5>[ 0.868664] Key type id_legacy registered
10547 11:36:54.082425 <6>[ 0.872944] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10548 11:36:54.089402 <6>[ 0.879868] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10549 11:36:54.095799 <6>[ 0.887580] 9p: Installing v9fs 9p2000 file system support
10550 11:36:54.131632 <5>[ 0.925156] Key type asymmetric registered
10551 11:36:54.134777 <5>[ 0.929487] Asymmetric key parser 'x509' registered
10552 11:36:54.145136 <6>[ 0.934622] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10553 11:36:54.148037 <6>[ 0.942236] io scheduler mq-deadline registered
10554 11:36:54.151389 <6>[ 0.946998] io scheduler kyber registered
10555 11:36:54.170217 <6>[ 0.964047] EINJ: ACPI disabled.
10556 11:36:54.203324 <4>[ 0.990012] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 11:36:54.212953 <4>[ 1.000646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 11:36:54.228295 <6>[ 1.021749] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10559 11:36:54.236067 <6>[ 1.029836] printk: console [ttyS0] disabled
10560 11:36:54.264271 <6>[ 1.054492] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10561 11:36:54.270663 <6>[ 1.063965] printk: console [ttyS0] enabled
10562 11:36:54.274244 <6>[ 1.063965] printk: console [ttyS0] enabled
10563 11:36:54.280866 <6>[ 1.072862] printk: bootconsole [mtk8250] disabled
10564 11:36:54.284273 <6>[ 1.072862] printk: bootconsole [mtk8250] disabled
10565 11:36:54.290931 <6>[ 1.084228] SuperH (H)SCI(F) driver initialized
10566 11:36:54.294324 <6>[ 1.089523] msm_serial: driver initialized
10567 11:36:54.308461 <6>[ 1.098541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10568 11:36:54.318365 <6>[ 1.107092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10569 11:36:54.324923 <6>[ 1.115634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10570 11:36:54.334767 <6>[ 1.124261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10571 11:36:54.341903 <6>[ 1.132969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10572 11:36:54.351790 <6>[ 1.141684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10573 11:36:54.361945 <6>[ 1.150225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10574 11:36:54.368181 <6>[ 1.159038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10575 11:36:54.377882 <6>[ 1.167583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10576 11:36:54.389586 <6>[ 1.183279] loop: module loaded
10577 11:36:54.396158 <6>[ 1.189219] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10578 11:36:54.419230 <4>[ 1.212792] mtk-pmic-keys: Failed to locate of_node [id: -1]
10579 11:36:54.426129 <6>[ 1.219686] megasas: 07.719.03.00-rc1
10580 11:36:54.435617 <6>[ 1.229375] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10581 11:36:54.445424 <6>[ 1.238733] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10582 11:36:54.462033 <6>[ 1.255535] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10583 11:36:54.518881 <6>[ 1.305783] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10584 11:36:54.788856 <6>[ 1.582148] Freeing initrd memory: 18284K
10585 11:36:54.800188 <6>[ 1.593965] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10586 11:36:54.811583 <6>[ 1.604884] tun: Universal TUN/TAP device driver, 1.6
10587 11:36:54.814684 <6>[ 1.610952] thunder_xcv, ver 1.0
10588 11:36:54.818802 <6>[ 1.614460] thunder_bgx, ver 1.0
10589 11:36:54.821142 <6>[ 1.617959] nicpf, ver 1.0
10590 11:36:54.832105 <6>[ 1.621987] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10591 11:36:54.834886 <6>[ 1.629464] hns3: Copyright (c) 2017 Huawei Corporation.
10592 11:36:54.838761 <6>[ 1.635053] hclge is initializing
10593 11:36:54.845072 <6>[ 1.638628] e1000: Intel(R) PRO/1000 Network Driver
10594 11:36:54.851682 <6>[ 1.643756] e1000: Copyright (c) 1999-2006 Intel Corporation.
10595 11:36:54.855704 <6>[ 1.649772] e1000e: Intel(R) PRO/1000 Network Driver
10596 11:36:54.861950 <6>[ 1.654988] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10597 11:36:54.868588 <6>[ 1.661172] igb: Intel(R) Gigabit Ethernet Network Driver
10598 11:36:54.875255 <6>[ 1.666822] igb: Copyright (c) 2007-2014 Intel Corporation.
10599 11:36:54.881747 <6>[ 1.672658] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10600 11:36:54.885064 <6>[ 1.679176] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10601 11:36:54.892133 <6>[ 1.685639] sky2: driver version 1.30
10602 11:36:54.898562 <6>[ 1.690570] usbcore: registered new device driver r8152-cfgselector
10603 11:36:54.905691 <6>[ 1.697108] usbcore: registered new interface driver r8152
10604 11:36:54.908864 <6>[ 1.702927] VFIO - User Level meta-driver version: 0.3
10605 11:36:54.917709 <6>[ 1.711172] usbcore: registered new interface driver usb-storage
10606 11:36:54.924183 <6>[ 1.717622] usbcore: registered new device driver onboard-usb-hub
10607 11:36:54.933417 <6>[ 1.726777] mt6397-rtc mt6359-rtc: registered as rtc0
10608 11:36:54.943246 <6>[ 1.732244] mt6397-rtc mt6359-rtc: setting system clock to 2024-07-17T11:36:55 UTC (1721216215)
10609 11:36:54.946750 <6>[ 1.741826] i2c_dev: i2c /dev entries driver
10610 11:36:54.960506 <4>[ 1.753958] cpu cpu0: supply cpu not found, using dummy regulator
10611 11:36:54.967169 <4>[ 1.760382] cpu cpu1: supply cpu not found, using dummy regulator
10612 11:36:54.973534 <4>[ 1.766804] cpu cpu2: supply cpu not found, using dummy regulator
10613 11:36:54.980174 <4>[ 1.773217] cpu cpu3: supply cpu not found, using dummy regulator
10614 11:36:54.987024 <4>[ 1.779615] cpu cpu4: supply cpu not found, using dummy regulator
10615 11:36:54.994186 <4>[ 1.786013] cpu cpu5: supply cpu not found, using dummy regulator
10616 11:36:55.000744 <4>[ 1.792410] cpu cpu6: supply cpu not found, using dummy regulator
10617 11:36:55.007050 <4>[ 1.798808] cpu cpu7: supply cpu not found, using dummy regulator
10618 11:36:55.027226 <6>[ 1.820463] cpu cpu0: EM: created perf domain
10619 11:36:55.030330 <6>[ 1.825398] cpu cpu4: EM: created perf domain
10620 11:36:55.037347 <6>[ 1.831030] sdhci: Secure Digital Host Controller Interface driver
10621 11:36:55.044647 <6>[ 1.837461] sdhci: Copyright(c) Pierre Ossman
10622 11:36:55.050843 <6>[ 1.842423] Synopsys Designware Multimedia Card Interface Driver
10623 11:36:55.057730 <6>[ 1.849069] sdhci-pltfm: SDHCI platform and OF driver helper
10624 11:36:55.060966 <6>[ 1.849126] mmc0: CQHCI version 5.10
10625 11:36:55.067474 <6>[ 1.859026] ledtrig-cpu: registered to indicate activity on CPUs
10626 11:36:55.074756 <6>[ 1.866027] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10627 11:36:55.080777 <6>[ 1.873077] usbcore: registered new interface driver usbhid
10628 11:36:55.084385 <6>[ 1.878900] usbhid: USB HID core driver
10629 11:36:55.091051 <6>[ 1.883094] spi_master spi0: will run message pump with realtime priority
10630 11:36:55.140539 <6>[ 1.927232] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10631 11:36:55.157248 <6>[ 1.943772] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10632 11:36:55.164291 <6>[ 1.952998] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10633 11:36:55.171263 <6>[ 1.959855] cros-ec-spi spi0.0: Chrome EC device registered
10634 11:36:55.174242 <6>[ 1.969235] mmc0: Command Queue Engine enabled
10635 11:36:55.180858 <6>[ 1.973965] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10636 11:36:55.188133 <6>[ 1.981588] mmcblk0: mmc0:0001 DA4128 116 GiB
10637 11:36:55.197972 <6>[ 1.983087] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10638 11:36:55.201269 <6>[ 1.989935] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10639 11:36:55.208095 <6>[ 1.996691] NET: Registered PF_PACKET protocol family
10640 11:36:55.214649 <6>[ 2.002801] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 11:36:55.218044 <6>[ 2.006932] 9pnet: Installing 9P2000 support
10642 11:36:55.224816 <6>[ 2.012792] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 11:36:55.228153 <5>[ 2.016631] Key type dns_resolver registered
10644 11:36:55.234746 <6>[ 2.022539] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 11:36:55.238071 <6>[ 2.026883] registered taskstats version 1
10646 11:36:55.244797 <5>[ 2.037292] Loading compiled-in X.509 certificates
10647 11:36:55.271640 <4>[ 2.058363] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10648 11:36:55.281383 <4>[ 2.069091] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10649 11:36:55.296542 <6>[ 2.089575] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10650 11:36:55.302850 <6>[ 2.096475] xhci-mtk 11200000.usb: xHCI Host Controller
10651 11:36:55.309554 <6>[ 2.102006] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10652 11:36:55.319535 <6>[ 2.109864] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10653 11:36:55.326217 <6>[ 2.119295] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10654 11:36:55.333055 <6>[ 2.125472] xhci-mtk 11200000.usb: xHCI Host Controller
10655 11:36:55.339850 <6>[ 2.130975] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10656 11:36:55.346446 <6>[ 2.138640] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10657 11:36:55.352675 <6>[ 2.146472] hub 1-0:1.0: USB hub found
10658 11:36:55.356007 <6>[ 2.150500] hub 1-0:1.0: 1 port detected
10659 11:36:55.363424 <6>[ 2.154805] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10660 11:36:55.370639 <6>[ 2.163560] hub 2-0:1.0: USB hub found
10661 11:36:55.373367 <6>[ 2.167584] hub 2-0:1.0: 1 port detected
10662 11:36:55.380994 <6>[ 2.174583] mtk-msdc 11f70000.mmc: Got CD GPIO
10663 11:36:55.397072 <6>[ 2.187155] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 11:36:55.403669 <6>[ 2.195540] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 11:36:55.413876 <6>[ 2.203882] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 11:36:55.420553 <6>[ 2.212223] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 11:36:55.430194 <6>[ 2.220564] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 11:36:55.437219 <6>[ 2.228903] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 11:36:55.446835 <6>[ 2.237244] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 11:36:55.453578 <6>[ 2.245583] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 11:36:55.463991 <6>[ 2.253925] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 11:36:55.471005 <6>[ 2.262263] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 11:36:55.480478 <6>[ 2.270602] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 11:36:55.487753 <6>[ 2.278946] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 11:36:55.496995 <6>[ 2.287284] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 11:36:55.503820 <6>[ 2.295624] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 11:36:55.513425 <6>[ 2.303963] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 11:36:55.519957 <6>[ 2.312633] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 11:36:55.526714 <6>[ 2.319810] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 11:36:55.533556 <6>[ 2.326647] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 11:36:55.540520 <6>[ 2.333421] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 11:36:55.550228 <6>[ 2.340398] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 11:36:55.556661 <6>[ 2.347248] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 11:36:55.567147 <6>[ 2.356381] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 11:36:55.576562 <6>[ 2.365504] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 11:36:55.586913 <6>[ 2.374799] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 11:36:55.596562 <6>[ 2.384267] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 11:36:55.603421 <6>[ 2.393734] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 11:36:55.613186 <6>[ 2.402855] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 11:36:55.622875 <6>[ 2.412322] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 11:36:55.633065 <6>[ 2.421444] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 11:36:55.642814 <6>[ 2.430743] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 11:36:55.652710 <6>[ 2.440903] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 11:36:55.662562 <6>[ 2.452552] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 11:36:55.669885 <6>[ 2.463761] Trying to probe devices needed for running init ...
10696 11:36:55.680666 <3>[ 2.470997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10697 11:36:55.785293 <6>[ 2.575658] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 11:36:55.939468 <6>[ 2.733613] hub 1-1:1.0: USB hub found
10699 11:36:55.942652 <6>[ 2.738136] hub 1-1:1.0: 4 ports detected
10700 11:36:55.955469 <6>[ 2.749296] hub 1-1:1.0: USB hub found
10701 11:36:55.958717 <6>[ 2.753725] hub 1-1:1.0: 4 ports detected
10702 11:36:56.065473 <6>[ 2.855832] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 11:36:56.091978 <6>[ 2.885817] hub 2-1:1.0: USB hub found
10704 11:36:56.095413 <6>[ 2.890353] hub 2-1:1.0: 3 ports detected
10705 11:36:56.108030 <6>[ 2.901598] hub 2-1:1.0: USB hub found
10706 11:36:56.111096 <6>[ 2.906076] hub 2-1:1.0: 3 ports detected
10707 11:36:56.280996 <6>[ 3.071654] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 11:36:56.413380 <6>[ 3.206857] hub 1-1.4:1.0: USB hub found
10709 11:36:56.416414 <6>[ 3.211418] hub 1-1.4:1.0: 2 ports detected
10710 11:36:56.430658 <6>[ 3.224474] hub 1-1.4:1.0: USB hub found
10711 11:36:56.433644 <6>[ 3.229060] hub 1-1.4:1.0: 2 ports detected
10712 11:36:56.497105 <6>[ 3.287815] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10713 11:36:56.606372 <6>[ 3.396289] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10714 11:36:56.642114 <4>[ 3.432501] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10715 11:36:56.652015 <4>[ 3.441597] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10716 11:36:56.687539 <6>[ 3.480938] r8152 2-1.3:1.0 eth0: v1.12.13
10717 11:36:56.736951 <6>[ 3.527631] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 11:36:56.933266 <6>[ 3.723695] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 11:36:58.314067 <6>[ 5.108550] r8152 2-1.3:1.0 eth0: carrier on
10720 11:37:00.557604 <5>[ 5.135429] Sending DHCP requests .., OK
10721 11:37:00.563894 <6>[ 7.355887] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10722 11:37:00.567344 <6>[ 7.364187] IP-Config: Complete:
10723 11:37:00.580785 <6>[ 7.367681] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10724 11:37:00.587539 <6>[ 7.378394] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10725 11:37:00.594190 <6>[ 7.387010] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10726 11:37:00.600623 <6>[ 7.387019] nameserver0=192.168.201.1
10727 11:37:00.604561 <6>[ 7.399177] clk: Disabling unused clocks
10728 11:37:00.606979 <6>[ 7.404752] ALSA device list:
10729 11:37:00.614073 <6>[ 7.408006] No soundcards found.
10730 11:37:00.621540 <6>[ 7.415483] Freeing unused kernel memory: 8512K
10731 11:37:00.624536 <6>[ 7.420370] Run /init as init process
10732 11:37:00.634326 Loading, please wait...
10733 11:37:00.662802 Starting systemd-udevd version 252.22-1~deb12u1
10734 11:37:00.879931 <6>[ 7.670941] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10735 11:37:00.893962 <6>[ 7.684589] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10736 11:37:00.900490 <6>[ 7.686447] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10737 11:37:00.910345 <6>[ 7.700581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10738 11:37:00.913480 <6>[ 7.704272] remoteproc remoteproc0: scp is available
10739 11:37:00.923381 <4>[ 7.708884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10740 11:37:00.930051 <6>[ 7.714133] remoteproc remoteproc0: powering up scp
10741 11:37:00.936795 <6>[ 7.723555] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10742 11:37:00.946845 <6>[ 7.727973] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10743 11:37:00.953422 <6>[ 7.736089] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10744 11:37:00.959941 <6>[ 7.738327] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10745 11:37:00.967177 <6>[ 7.744463] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10746 11:37:00.973325 <4>[ 7.749813] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10747 11:37:00.979838 <6>[ 7.749906] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10748 11:37:00.989770 <6>[ 7.749944] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10749 11:37:00.999729 <6>[ 7.749950] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10750 11:37:01.006934 <6>[ 7.752584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10751 11:37:01.012952 <4>[ 7.760419] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10752 11:37:01.022794 <6>[ 7.765976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10753 11:37:01.029578 <3>[ 7.789921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 11:37:01.032917 <6>[ 7.791389] mc: Linux media interface: v0.10
10755 11:37:01.043520 <6>[ 7.798146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10756 11:37:01.050430 <3>[ 7.806632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:37:01.060439 <6>[ 7.813537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10758 11:37:01.067114 <3>[ 7.821258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 11:37:01.074042 <6>[ 7.822445] videodev: Linux video capture interface: v2.00
10760 11:37:01.080521 <3>[ 7.824922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 11:37:01.090478 <3>[ 7.825084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 11:37:01.097826 <3>[ 7.825123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 11:37:01.104592 <3>[ 7.825141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 11:37:01.114703 <3>[ 7.825148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 11:37:01.120986 <3>[ 7.825303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 11:37:01.131324 <3>[ 7.825412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 11:37:01.137547 <3>[ 7.825420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:37:01.148122 <3>[ 7.825424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 11:37:01.154595 <3>[ 7.825510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 11:37:01.164815 <3>[ 7.825518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 11:37:01.171705 <3>[ 7.825521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:37:01.177655 <3>[ 7.825526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 11:37:01.187542 <3>[ 7.825529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:37:01.194225 <3>[ 7.825554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 11:37:01.204459 <4>[ 7.827951] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10776 11:37:01.207569 <4>[ 7.827951] Fallback method does not support PEC.
10777 11:37:01.217510 <3>[ 7.857404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 11:37:01.224104 <6>[ 7.865270] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10779 11:37:01.234397 <6>[ 7.865320] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10780 11:37:01.240832 <6>[ 7.865329] remoteproc remoteproc0: remote processor scp is now up
10781 11:37:01.246993 <6>[ 7.872926] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10782 11:37:01.253590 <6>[ 7.890401] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10783 11:37:01.263786 <6>[ 7.891836] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10784 11:37:01.273334 <6>[ 7.892291] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10785 11:37:01.280272 <6>[ 7.897273] pci_bus 0000:00: root bus resource [bus 00-ff]
10786 11:37:01.287071 <6>[ 7.901706] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10787 11:37:01.296706 <3>[ 7.902748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 11:37:01.306853 <6>[ 7.916936] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10789 11:37:01.313567 <6>[ 7.921872] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10790 11:37:01.316916 <6>[ 7.930590] Bluetooth: Core ver 2.22
10791 11:37:01.326583 <6>[ 7.938053] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10792 11:37:01.333154 <6>[ 7.946079] NET: Registered PF_BLUETOOTH protocol family
10793 11:37:01.336461 <6>[ 7.954149] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10794 11:37:01.343212 <6>[ 7.962193] Bluetooth: HCI device and connection manager initialized
10795 11:37:01.352810 <6>[ 7.963033] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10796 11:37:01.362902 <6>[ 7.964159] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10797 11:37:01.369460 <6>[ 7.964304] usbcore: registered new interface driver uvcvideo
10798 11:37:01.375953 <6>[ 7.970269] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10799 11:37:01.382809 <6>[ 7.978348] Bluetooth: HCI socket layer initialized
10800 11:37:01.386378 <6>[ 7.986476] pci 0000:00:00.0: supports D1 D2
10801 11:37:01.392492 <6>[ 7.994492] Bluetooth: L2CAP socket layer initialized
10802 11:37:01.399225 <6>[ 7.995000] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10803 11:37:01.405813 <6>[ 8.008118] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 11:37:01.412300 <6>[ 8.016896] Bluetooth: SCO socket layer initialized
10805 11:37:01.419242 <6>[ 8.024856] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10806 11:37:01.425996 <6>[ 8.079274] usbcore: registered new interface driver btusb
10807 11:37:01.435926 <4>[ 8.080427] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10808 11:37:01.442299 <3>[ 8.080437] Bluetooth: hci0: Failed to load firmware file (-2)
10809 11:37:01.449137 <3>[ 8.080441] Bluetooth: hci0: Failed to set up firmware (-2)
10810 11:37:01.458642 <4>[ 8.080445] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10811 11:37:01.465349 <6>[ 8.088224] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10812 11:37:01.472155 <6>[ 8.263818] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10813 11:37:01.478419 <6>[ 8.271304] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10814 11:37:01.485530 <6>[ 8.278786] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10815 11:37:01.491671 <6>[ 8.286360] pci 0000:01:00.0: supports D1 D2
10816 11:37:01.498360 <6>[ 8.290879] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10817 11:37:01.516090 <6>[ 8.307570] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10818 11:37:01.522741 <6>[ 8.314470] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10819 11:37:01.529381 <6>[ 8.322556] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10820 11:37:01.539504 <6>[ 8.330554] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10821 11:37:01.546088 <6>[ 8.338555] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10822 11:37:01.556414 <6>[ 8.346555] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10823 11:37:01.560014 <6>[ 8.354556] pci 0000:00:00.0: PCI bridge to [bus 01]
10824 11:37:01.569476 <6>[ 8.359773] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10825 11:37:01.576185 <6>[ 8.367898] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10826 11:37:01.582385 <6>[ 8.374696] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10827 11:37:01.588952 <6>[ 8.381471] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10828 11:37:01.603416 <5>[ 8.394982] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10829 11:37:01.625420 <5>[ 8.416685] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10830 11:37:01.632398 <5>[ 8.424231] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10831 11:37:01.642599 <4>[ 8.432730] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10832 11:37:01.645980 <6>[ 8.441620] cfg80211: failed to load regulatory.db
10833 11:37:01.693367 <6>[ 8.484644] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10834 11:37:01.700295 <6>[ 8.492157] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10835 11:37:01.720995 <6>[ 8.515624] mt7921e 0000:01:00.0: ASIC revision: 79610010
10836 11:37:01.824265 <6>[ 8.615659] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10837 11:37:01.827625 <6>[ 8.615659]
10838 11:37:01.858058 Begin: Loading essential drivers ... done.
10839 11:37:01.860945 Begin: Running /scripts/init-premount ... done.
10840 11:37:01.867936 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10841 11:37:01.878090 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10842 11:37:01.880785 Device /sys/class/net/eth0 found
10843 11:37:01.880859 done.
10844 11:37:01.912614 Begin: Waiting up to 180 secs for any network device to become available ... done.
10845 11:37:01.968807 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10846 11:37:01.976065 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10847 11:37:01.982516 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10848 11:37:01.989457 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10849 11:37:01.996005 host : mt8192-asurada-spherion-r0-cbg-3
10850 11:37:02.002529 domain : lava-rack
10851 11:37:02.005555 rootserver: 192.168.201.1 rootpath:
10852 11:37:02.008884 filename :
10853 11:37:02.021345 done.
10854 11:37:02.029089 Begin: Running /scripts/nfs-bottom ... done.
10855 11:37:02.046744 Begin: Running /scripts/init-bottom ... done.
10856 11:37:02.093603 <6>[ 8.884818] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10857 11:37:03.423492 <6>[ 10.218202] NET: Registered PF_INET6 protocol family
10858 11:37:03.430906 <6>[ 10.225956] Segment Routing with IPv6
10859 11:37:03.434094 <6>[ 10.229961] In-situ OAM (IOAM) with IPv6
10860 11:37:03.618542 <30>[ 10.386395] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10861 11:37:03.624756 <30>[ 10.419532] systemd[1]: Detected architecture arm64.
10862 11:37:03.635482
10863 11:37:03.638756 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10864 11:37:03.639139
10865 11:37:03.663073 <30>[ 10.457867] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10866 11:37:04.791086 <30>[ 11.582660] systemd[1]: Queued start job for default target graphical.target.
10867 11:37:04.837623 <30>[ 11.628792] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10868 11:37:04.843816 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10869 11:37:04.865863 <30>[ 11.657514] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10870 11:37:04.875649 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10871 11:37:04.894780 <30>[ 11.685419] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10872 11:37:04.903787 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10873 11:37:04.921625 <30>[ 11.713041] systemd[1]: Created slice user.slice - User and Session Slice.
10874 11:37:04.928163 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10875 11:37:04.951682 <30>[ 11.739951] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10876 11:37:04.958428 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10877 11:37:04.979686 <30>[ 11.767886] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10878 11:37:04.986804 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10879 11:37:05.014274 <30>[ 11.795792] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10880 11:37:05.024180 <30>[ 11.815595] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10881 11:37:05.030775 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10882 11:37:05.048875 <30>[ 11.840035] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10883 11:37:05.055324 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10884 11:37:05.076764 <30>[ 11.868108] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10885 11:37:05.086972 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10886 11:37:05.101208 <30>[ 11.895729] systemd[1]: Reached target paths.target - Path Units.
10887 11:37:05.111121 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10888 11:37:05.128913 <30>[ 11.920103] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10889 11:37:05.135943 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10890 11:37:05.149065 <30>[ 11.943623] systemd[1]: Reached target slices.target - Slice Units.
10891 11:37:05.159507 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10892 11:37:05.173257 <30>[ 11.968116] systemd[1]: Reached target swap.target - Swaps.
10893 11:37:05.180352 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10894 11:37:05.200959 <30>[ 11.991720] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10895 11:37:05.210485 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10896 11:37:05.229407 <30>[ 12.020576] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10897 11:37:05.239152 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10898 11:37:05.260909 <30>[ 12.051555] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10899 11:37:05.269854 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10900 11:37:05.290362 <30>[ 12.081369] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10901 11:37:05.300428 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10902 11:37:05.318008 <30>[ 12.109054] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10903 11:37:05.324393 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10904 11:37:05.346302 <30>[ 12.137319] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10905 11:37:05.356195 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10906 11:37:05.375658 <30>[ 12.167115] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10907 11:37:05.385605 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10908 11:37:05.401000 <30>[ 12.192029] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10909 11:37:05.410754 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10910 11:37:05.452057 <30>[ 12.243676] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10911 11:37:05.459253 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10912 11:37:05.480253 <30>[ 12.271740] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10913 11:37:05.486807 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10914 11:37:05.508069 <30>[ 12.299613] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10915 11:37:05.514691 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10916 11:37:05.539660 <30>[ 12.324386] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10917 11:37:05.555355 <30>[ 12.346605] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10918 11:37:05.565374 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10919 11:37:05.585501 <30>[ 12.376317] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10920 11:37:05.594612 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10921 11:37:05.618552 <30>[ 12.409732] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10922 11:37:05.625001 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10923 11:37:05.650158 <30>[ 12.441457] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10924 11:37:05.656608 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10925 11:37:05.666470 <6>[ 12.455764] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10926 11:37:05.666900
10927 11:37:05.724941 <30>[ 12.516477] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10928 11:37:05.734620 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10929 11:37:05.757926 <30>[ 12.549323] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10930 11:37:05.764371 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10931 11:37:05.789484 <30>[ 12.581203] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10932 11:37:05.799573 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.596085] fuse: init (API version 7.37)
10933 11:37:05.799969 .
10934 11:37:05.860983 <30>[ 12.652542] systemd[1]: Starting systemd-journald.service - Journal Service...
10935 11:37:05.868150 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10936 11:37:05.903333 <30>[ 12.694327] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10937 11:37:05.909180 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10938 11:37:05.937614 <30>[ 12.725793] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10939 11:37:05.944229 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10940 11:37:06.001027 <30>[ 12.792584] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10941 11:37:06.010937 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10942 11:37:06.032855 <30>[ 12.823649] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10943 11:37:06.046162 Starting [0;1;39msystemd-udev-trig…[<3>[ 12.836017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 11:37:06.049819 0m - Coldplug All udev Devices...
10945 11:37:06.070641 <30>[ 12.865041] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10946 11:37:06.081207 <3>[ 12.871714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:37:06.093679 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10948 11:37:06.108694 <30>[ 12.900050] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10949 11:37:06.115044 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10950 11:37:06.132448 <3>[ 12.923917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 11:37:06.139050 <30>[ 12.924176] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10952 11:37:06.149014 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10953 11:37:06.163249 <3>[ 12.955162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:37:06.174450 <30>[ 12.965742] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10955 11:37:06.184217 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10956 11:37:06.195240 <3>[ 12.986476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 11:37:06.205683 <30>[ 12.997363] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10958 11:37:06.212883 <30>[ 13.005727] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10959 11:37:06.229711 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 13.018589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:37:06.229871 Load Kernel Module configfs.
10961 11:37:06.249721 <30>[ 13.040862] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10962 11:37:06.256486 <30>[ 13.048749] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10963 11:37:06.266337 <3>[ 13.050837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:37:06.272980 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10965 11:37:06.294621 <30>[ 13.086486] systemd[1]: modprobe@drm.service: Deactivated successfully.
10966 11:37:06.301268 <3>[ 13.091630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:37:06.311146 <30>[ 13.094424] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10968 11:37:06.318060 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10969 11:37:06.334538 <3>[ 13.126611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:37:06.346157 <30>[ 13.138204] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10971 11:37:06.356700 <30>[ 13.146919] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10972 11:37:06.369841 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Lo<3>[ 13.160609] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 11:37:06.373636 ad Kernel Module efi_pstore.
10974 11:37:06.392547 <30>[ 13.186696] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10975 11:37:06.403215 <30>[ 13.194847] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10976 11:37:06.409549 <3>[ 13.197283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 11:37:06.419803 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10978 11:37:06.435475 <30>[ 13.229878] systemd[1]: modprobe@loop.service: Deactivated successfully.
10979 11:37:06.446035 <30>[ 13.238022] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10980 11:37:06.452379 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10981 11:37:06.474615 <30>[ 13.265422] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10982 11:37:06.487836 <4>[ 13.272902] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10983 11:37:06.498026 <3>[ 13.289156] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10984 11:37:06.504304 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10985 11:37:06.525541 <30>[ 13.317140] systemd[1]: Started systemd-journald.service - Journal Service.
10986 11:37:06.531692 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10987 11:37:06.556479 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10988 11:37:06.577418 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10989 11:37:06.597621 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10990 11:37:06.618975 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10991 11:37:06.660536 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10992 11:37:06.681377 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10993 11:37:06.705547 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10994 11:37:06.729718 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10995 11:37:06.769970 <46>[ 13.562051] systemd-journald[308]: Received client request to flush runtime journal.
10996 11:37:06.780265 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10997 11:37:06.806188 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10998 11:37:07.093657 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10999 11:37:07.112558 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11000 11:37:07.133964 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11001 11:37:07.540623 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11002 11:37:08.181289 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11003 11:37:08.201301 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11004 11:37:08.260683 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11005 11:37:08.390808 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11006 11:37:08.408514 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11007 11:37:08.428236 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11008 11:37:08.492980 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11009 11:37:08.516133 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11010 11:37:08.749632 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11011 11:37:08.803271 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11012 11:37:08.877687 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11013 11:37:09.174034 <6>[ 15.968998] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11014 11:37:09.183694 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11015 11:37:09.247600 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11016 11:37:09.362934 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11017 11:37:09.387307 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11018 11:37:09.404361 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11019 11:37:09.452362 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11020 11:37:09.473205 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11021 11:37:09.495054 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11022 11:37:09.514910 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11023 11:37:09.544157 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11024 11:37:09.604245 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11025 11:37:09.639282 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11026 11:37:09.664561 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11027 11:37:09.749194 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11028 11:37:09.767807 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11029 11:37:09.784624 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11030 11:37:09.800199 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11031 11:37:09.828086 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11032 11:37:09.847906 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11033 11:37:09.864705 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11034 11:37:09.884997 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11035 11:37:09.908445 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11036 11:37:09.924852 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11037 11:37:09.942838 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11038 11:37:09.960046 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11039 11:37:09.966677 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11040 11:37:10.033388 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11041 11:37:10.116701 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11042 11:37:10.167172 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11043 11:37:10.189306 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11044 11:37:10.367258 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11045 11:37:10.429567 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11046 11:37:10.451384 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11047 11:37:10.468173 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11048 11:37:10.509760 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11049 11:37:10.528872 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11050 11:37:10.569346 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11051 11:37:10.590124 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11052 11:37:10.612560 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11053 11:37:10.657826 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11054 11:37:10.715364 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11055 11:37:10.830899
11056 11:37:10.834378 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11057 11:37:10.834761
11058 11:37:10.837925 debian-bookworm-arm64 login: root (automatic login)
11059 11:37:10.838304
11060 11:37:11.120206 Linux debian-bookworm-arm64 6.1.96-cip24 #1 SMP PREEMPT Wed Jul 17 11:18:13 UTC 2024 aarch64
11061 11:37:11.120640
11062 11:37:11.126923 The programs included with the Debian GNU/Linux system are free software;
11063 11:37:11.133267 the exact distribution terms for each program are described in the
11064 11:37:11.136655 individual files in /usr/share/doc/*/copyright.
11065 11:37:11.137032
11066 11:37:11.143305 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11067 11:37:11.146600 permitted by applicable law.
11068 11:37:11.270834 Matched prompt #10: / #
11070 11:37:11.271827 Setting prompt string to ['/ #']
11071 11:37:11.272243 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11073 11:37:11.273159 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11074 11:37:11.273563 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11075 11:37:11.273869 Setting prompt string to ['/ #']
11076 11:37:11.274141 Forcing a shell prompt, looking for ['/ #']
11077 11:37:11.274417 Sending line: ''
11079 11:37:11.325604 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11080 11:37:11.326094 Waiting using forced prompt support (timeout 00:02:30)
11081 11:37:11.331155 / #
11082 11:37:11.332001 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11083 11:37:11.332467 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11084 11:37:11.332897 Sending line: "export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_'"
11086 11:37:11.440415 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14864627/extract-nfsrootfs-e3ust7p_'
11087 11:37:11.441282 Sending line: "export NFS_SERVER_IP='192.168.201.1'"
11089 11:37:11.548396 / # export NFS_SERVER_IP='192.168.201.1'
11090 11:37:11.549187 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11091 11:37:11.549667 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11092 11:37:11.550144 end: 2 depthcharge-action (duration 00:01:44) [common]
11093 11:37:11.550618 start: 3 lava-test-retry (timeout 00:30:00) [common]
11094 11:37:11.551019 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11095 11:37:11.551401 Using namespace: common
11096 11:37:11.551731 Sending line: '#'
11098 11:37:11.652956 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11099 11:37:11.658208 / # #
11100 11:37:11.658848 Using /lava-14864627
11101 11:37:11.659156 Sending line: 'export SHELL=/bin/sh'
11103 11:37:11.766460 / # export SHELL=/bin/sh
11104 11:37:11.767189 Sending line: '. /lava-14864627/environment'
11106 11:37:11.874147 / # . /lava-14864627/environment
11107 11:37:11.880888 Sending line: '/lava-14864627/bin/lava-test-runner /lava-14864627/0'
11109 11:37:11.982616 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 11:37:11.988406 / # /lava-14864627/bin/lava-test-runner /lava-14864627/0
11111 11:37:12.274468 + export TESTRUN_ID=0_lc-compliance
11112 11:37:12.280843 + cd /lava-14864627/0/tests/0_lc-compliance
11113 11:37:12.281355 + cat uuid
11114 11:37:12.291549 + UUID=14864627_1.6.2.3.1
11115 11:37:12.292011 + set +x
11116 11:37:12.298593 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14864627_1.6.2.3.1>
11117 11:37:12.299322 Received signal: <STARTRUN> 0_lc-compliance 14864627_1.6.2.3.1
11118 11:37:12.299704 Starting test lava.0_lc-compliance (14864627_1.6.2.3.1)
11119 11:37:12.300188 Skipping test definition patterns.
11120 11:37:12.301855 + /usr/bin/lc-compliance-parser.sh
11121 11:37:13.985573 [0:00:20.659449770] [414] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11122 11:37:13.988998 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11123 11:37:14.004735 [0:00:20.679184231] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11124 11:37:14.060168 [0:00:20.734071770] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11125 11:37:14.079523 [==========] Running 120 tests from 1 test suite.
11126 11:37:14.112453 [0:00:20.786442000] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 11:37:14.165574 [0:00:20.839455385] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 11:37:14.174731 [----------] Global test environment set-up.
11129 11:37:14.267847 [----------] 120 tests from CaptureTests/SingleStream
11130 11:37:14.362343 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11131 11:37:14.439261 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11132 11:37:14.440036 Received signal: <TESTSET> START CaptureTests/SingleStream
11133 11:37:14.440440 Starting test_set CaptureTests/SingleStream
11134 11:37:14.442759 Camera needs 4 requests, can't test only 1
11135 11:37:14.545616 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11136 11:37:14.595976 [0:00:21.269817847] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 11:37:14.646540
11138 11:37:14.750013 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11139 11:37:14.884391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11140 11:37:14.885074 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11142 11:37:14.904080 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11143 11:37:14.966359 Camera needs 4 requests, can't test only 2
11144 11:37:15.065594 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11145 11:37:15.158425
11146 11:37:15.263561 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (52 ms)
11147 11:37:15.291925 [0:00:21.965899462] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11148 11:37:15.374643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11149 11:37:15.375331 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11151 11:37:15.393865 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11152 11:37:15.455768 Camera needs 4 requests, can't test only 3
11153 11:37:15.551729 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11154 11:37:15.641162
11155 11:37:15.741227 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11156 11:37:15.848788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11157 11:37:15.849554 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11159 11:37:15.868034 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11160 11:37:15.930547 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (428 ms)
11161 11:37:16.042357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11162 11:37:16.043022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11164 11:37:16.060352 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11165 11:37:16.126700 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (696 ms)
11166 11:37:16.241415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11167 11:37:16.242072 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11169 11:37:16.260012 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11170 11:37:16.538220 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1255 ms)
11171 11:37:16.548000 [0:00:23.222077770] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 11:37:16.648843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11173 11:37:16.649598 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11175 11:37:16.666945 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11176 11:37:18.354604 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1817 ms)
11177 11:37:18.365093 [0:00:25.039151078] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 11:37:18.472520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11179 11:37:18.473217 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11181 11:37:18.491378 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11182 11:37:21.082972 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2728 ms)
11183 11:37:21.092774 [0:00:27.767335001] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 11:37:21.202863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11185 11:37:21.203522 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11187 11:37:21.221593 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11188 11:37:25.280948 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11189 11:37:25.290620 [0:00:31.964485770] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 11:37:25.390871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11191 11:37:25.391515 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11193 11:37:25.409546 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11194 11:37:31.166445 <6>[ 37.967576] vpu: disabling
11195 11:37:31.169874 <6>[ 37.970780] vproc2: disabling
11196 11:37:31.173358 <6>[ 37.974659] vproc1: disabling
11197 11:37:31.177779 <6>[ 37.978788] vaud18: disabling
11198 11:37:31.185277 <6>[ 37.982538] vsram_others: disabling
11199 11:37:31.187959 <6>[ 37.986713] va09: disabling
11200 11:37:31.191439 <6>[ 37.990109] vsram_md: disabling
11201 11:37:31.194581 <6>[ 37.993881] Vgpu: disabling
11202 11:37:31.856155 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6576 ms)
11203 11:37:31.866381 [0:00:38.540716694] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11204 11:37:31.920507 [0:00:38.595981078] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11205 11:37:31.973864 [0:00:38.649505694] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 11:37:31.977285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11207 11:37:31.977908 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11209 11:37:31.990679 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11210 11:37:32.028267 [0:00:38.703579309] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 11:37:32.055936 Camera needs 4 requests, can't test only 1
11212 11:37:32.143931 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11213 11:37:32.230190
11214 11:37:32.322723 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11215 11:37:32.426632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11216 11:37:32.427491 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11218 11:37:32.446111 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11219 11:37:32.506489 Camera needs 4 requests, can't test only 2
11220 11:37:32.595897 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11221 11:37:32.683212
11222 11:37:32.721190 [0:00:39.396693232] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 11:37:32.775750 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11224 11:37:32.877384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11225 11:37:32.878044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11227 11:37:32.897853 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11228 11:37:32.957751 Camera needs 4 requests, can't test only 3
11229 11:37:33.045295 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11230 11:37:33.131625
11231 11:37:33.222415 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (53 ms)
11232 11:37:33.324180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11233 11:37:33.324494 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11235 11:37:33.342091 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11236 11:37:33.403131 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (693 ms)
11237 11:37:33.507502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11238 11:37:33.508155 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11240 11:37:33.525452 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11241 11:37:33.619417 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (906 ms)
11242 11:37:33.632383 [0:00:40.304149463] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 11:37:33.725527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11244 11:37:33.726214 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11246 11:37:33.743652 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11247 11:37:34.875844 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
11248 11:37:34.887519 [0:00:41.559570540] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 11:37:34.983949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11250 11:37:34.984720 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11252 11:37:35.004166 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11253 11:37:36.691544 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
11254 11:37:36.704184 [0:00:43.375645848] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 11:37:36.798631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11256 11:37:36.799436 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11258 11:37:36.818322 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11259 11:37:39.417519 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2726 ms)
11260 11:37:39.430763 [0:00:46.102816617] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 11:37:39.524818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11262 11:37:39.525573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11264 11:37:39.543786 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11265 11:37:43.612727 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4195 ms)
11266 11:37:43.625733 [0:00:50.298322771] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 11:37:43.727642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11268 11:37:43.728378 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11270 11:37:43.745653 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11271 11:37:50.187613 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6575 ms)
11272 11:37:50.200406 [0:00:56.873995310] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 11:37:50.249575 [0:00:56.926485002] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 11:37:50.301479 [0:00:56.979459387] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 11:37:50.308301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11276 11:37:50.308944 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11278 11:37:50.320546 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11279 11:37:50.356616 [0:00:57.034810772] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 11:37:50.381247 Camera needs 4 requests, can't test only 1
11281 11:37:50.469452 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11282 11:37:50.553977
11283 11:37:50.643447 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (52 ms)
11284 11:37:50.748492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11285 11:37:50.749304 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11287 11:37:50.767747 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11288 11:37:50.826616 Camera needs 4 requests, can't test only 2
11289 11:37:50.915653 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11290 11:37:50.999551
11291 11:37:51.050599 [0:00:57.729025772] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 11:37:51.091030 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (52 ms)
11293 11:37:51.193928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11294 11:37:51.194650 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11296 11:37:51.214214 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11297 11:37:51.274747 Camera needs 4 requests, can't test only 3
11298 11:37:51.364436 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11299 11:37:51.450245
11300 11:37:51.539616 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11301 11:37:51.643814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11302 11:37:51.644476 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11304 11:37:51.662323 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11305 11:37:51.724110 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11306 11:37:51.830214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11307 11:37:51.830923 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11309 11:37:51.848937 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11310 11:37:51.948550 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (906 ms)
11311 11:37:51.961562 [0:00:58.636206772] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 11:37:52.047439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11313 11:37:52.047791 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11315 11:37:52.065562 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11316 11:37:53.205335 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1256 ms)
11317 11:37:53.218675 [0:00:59.892611233] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 11:37:53.313857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11319 11:37:53.314532 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11321 11:37:53.333096 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11322 11:37:55.020798 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
11323 11:37:55.033869 [0:01:01.707922080] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 11:37:55.127541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11325 11:37:55.128187 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11327 11:37:55.144928 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11328 11:37:57.747999 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2727 ms)
11329 11:37:57.761259 [0:01:04.435344003] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 11:37:57.856881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11331 11:37:57.857596 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11333 11:37:57.875649 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11334 11:38:01.943405 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4195 ms)
11335 11:38:01.956121 [0:01:08.630550388] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 11:38:02.051991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11337 11:38:02.052633 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11339 11:38:02.070483 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11340 11:38:08.516958 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6575 ms)
11341 11:38:08.530117 [0:01:15.205993157] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 11:38:08.579021 [0:01:15.259325311] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 11:38:08.611423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11344 11:38:08.611695 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11346 11:38:08.632312 [0:01:15.312552004] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11347 11:38:08.635601 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11348 11:38:08.686263 [0:01:15.366750234] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 11:38:08.689148 Camera needs 4 requests, can't test only 1
11350 11:38:08.752873 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11351 11:38:08.822330
11352 11:38:08.903764 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (53 ms)
11353 11:38:08.990476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11354 11:38:08.990754 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11356 11:38:09.007837 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11357 11:38:09.062664 Camera needs 4 requests, can't test only 2
11358 11:38:09.139942 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11359 11:38:09.211125
11360 11:38:09.292060 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)
11361 11:38:09.380517 [0:01:16.061355004] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 11:38:09.384158 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11364 11:38:09.387276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11365 11:38:09.398089 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11366 11:38:09.450519 Camera needs 4 requests, can't test only 3
11367 11:38:09.525759 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11368 11:38:09.599672
11369 11:38:09.678612 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11370 11:38:09.767892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11371 11:38:09.768172 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11373 11:38:09.782881 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11374 11:38:09.836163 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11375 11:38:09.927349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11376 11:38:09.927627 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11378 11:38:09.944338 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11379 11:38:10.277895 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11380 11:38:10.287595 [0:01:16.967264004] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 11:38:10.367913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11382 11:38:10.368186 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11384 11:38:10.383523 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11385 11:38:11.532404 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11386 11:38:11.545599 [0:01:18.222193773] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 11:38:11.621348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11388 11:38:11.621647 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11390 11:38:11.636990 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11391 11:38:13.347237 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1814 ms)
11392 11:38:13.361076 [0:01:20.036460850] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 11:38:13.436726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11394 11:38:13.437017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11396 11:38:13.452009 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11397 11:38:16.071484 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2724 ms)
11398 11:38:16.084679 [0:01:22.761582235] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 11:38:16.167458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11400 11:38:16.167750 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11402 11:38:16.183752 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11403 11:38:20.266967 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4195 ms)
11404 11:38:20.279971 [0:01:26.956808389] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 11:38:20.354265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11406 11:38:20.354561 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11408 11:38:20.370948 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11409 11:38:26.841963 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6575 ms)
11410 11:38:26.854798 [0:01:33.532682851] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 11:38:26.903364 [0:01:33.586123005] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 11:38:26.934849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11413 11:38:26.935143 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11415 11:38:26.949985 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11416 11:38:26.959844 [0:01:33.639517620] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 11:38:27.004314 Camera needs 4 requests, can't test only 1
11418 11:38:27.014450 [0:01:33.694483620] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 11:38:27.080029 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11420 11:38:27.148576
11421 11:38:27.229716 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (53 ms)
11422 11:38:27.316088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11423 11:38:27.316377 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11425 11:38:27.330595 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11426 11:38:27.381256 Camera needs 4 requests, can't test only 2
11427 11:38:27.460040 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11428 11:38:27.531425
11429 11:38:27.605541 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (53 ms)
11430 11:38:27.691108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11431 11:38:27.691404 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11433 11:38:27.709647 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11434 11:38:27.762278 Camera needs 4 requests, can't test only 3
11435 11:38:27.838477 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11436 11:38:27.908674
11437 11:38:27.988912 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)
11438 11:38:28.078058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11439 11:38:28.078348 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11441 11:38:28.094463 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11442 11:38:29.080655 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2078 ms)
11443 11:38:29.094083 [0:01:35.772048005] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 11:38:29.184821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11445 11:38:29.185454 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11447 11:38:29.202246 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11448 11:38:31.795776 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2715 ms)
11449 11:38:31.809366 [0:01:38.487432851] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 11:38:31.899011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11451 11:38:31.899673 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11453 11:38:31.918579 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11454 11:38:35.554897 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3759 ms)
11455 11:38:35.568215 [0:01:42.247020236] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 11:38:35.651219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11457 11:38:35.651514 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11459 11:38:35.667209 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11460 11:38:40.993844 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5439 ms)
11461 11:38:41.006733 [0:01:47.686415159] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 11:38:41.102439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11463 11:38:41.103124 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11465 11:38:41.120312 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11466 11:38:49.165735 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8173 ms)
11467 11:38:49.178215 [0:01:55.859328775] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 11:38:49.263200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11469 11:38:49.263505 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11471 11:38:49.279430 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11472 11:39:01.744664 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12580 ms)
11473 11:39:01.758176 [0:02:08.440036853] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 11:39:01.836819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11475 11:39:01.837096 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11477 11:39:01.851239 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11478 11:39:21.463740 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19721 ms)
11479 11:39:21.476914 [0:02:28.161149008] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 11:39:21.525713 [0:02:28.214780239] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 11:39:21.552173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11482 11:39:21.552519 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11484 11:39:21.567636 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11485 11:39:21.580753 [0:02:28.269398162] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 11:39:21.616686 Camera needs 4 requests, can't test only 1
11487 11:39:21.633600 [0:02:28.322556316] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 11:39:21.689902 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11489 11:39:21.756358
11490 11:39:21.831446 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11491 11:39:21.917657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11492 11:39:21.918008 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11494 11:39:21.930855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11495 11:39:21.981593 Camera needs 4 requests, can't test only 2
11496 11:39:22.058352 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11497 11:39:22.133615
11498 11:39:22.214389 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11499 11:39:22.317280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11500 11:39:22.317943 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11502 11:39:22.336773 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11503 11:39:22.395188 Camera needs 4 requests, can't test only 3
11504 11:39:22.482148 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11505 11:39:22.567134
11506 11:39:22.661783 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11507 11:39:22.747476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11508 11:39:22.747822 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11510 11:39:22.760855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11511 11:39:23.706210 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2076 ms)
11512 11:39:23.715578 [0:02:30.400057085] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 11:39:23.809522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11514 11:39:23.810519 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11516 11:39:23.825420 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11517 11:39:26.415447 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2709 ms)
11518 11:39:26.425173 [0:02:33.109888162] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 11:39:26.520263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11520 11:39:26.520962 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11522 11:39:26.534491 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11523 11:39:30.172935 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3757 ms)
11524 11:39:30.182900 [0:02:36.867930778] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 11:39:30.274779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11526 11:39:30.275430 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11528 11:39:30.290025 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11529 11:39:35.611086 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5438 ms)
11530 11:39:35.620913 [0:02:42.307047778] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 11:39:35.696465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11532 11:39:35.696802 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11534 11:39:35.708197 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11535 11:39:43.782406 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8172 ms)
11536 11:39:43.792507 [0:02:50.479428394] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 11:39:43.869658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11538 11:39:43.869950 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11540 11:39:43.880560 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11541 11:39:56.362475 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12581 ms)
11542 11:39:56.372329 [0:03:03.060705472] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 11:39:56.452971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11544 11:39:56.453254 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11546 11:39:56.464843 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11547 11:40:16.082640 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19721 ms)
11548 11:40:16.092265 [0:03:22.782888780] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 11:40:16.141041 [0:03:22.836342627] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 11:40:16.184195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11551 11:40:16.184486 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11553 11:40:16.193756 [0:03:22.890257780] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11554 11:40:16.199947 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11555 11:40:16.247953 [0:03:22.943612088] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 11:40:16.251263 Camera needs 4 requests, can't test only 1
11557 11:40:16.319699 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11558 11:40:16.384600
11559 11:40:16.466335 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11560 11:40:16.551457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11561 11:40:16.551745 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11563 11:40:16.563963 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11564 11:40:16.616901 Camera needs 4 requests, can't test only 2
11565 11:40:16.688159 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11566 11:40:16.754248
11567 11:40:16.833352 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11568 11:40:16.915103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11569 11:40:16.915384 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11571 11:40:16.926639 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11572 11:40:16.977506 Camera needs 4 requests, can't test only 3
11573 11:40:17.049280 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11574 11:40:17.117850
11575 11:40:17.192877 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11576 11:40:17.277627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11577 11:40:17.277917 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11579 11:40:17.289026 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11580 11:40:18.320221 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2077 ms)
11581 11:40:18.330547 [0:03:25.021395242] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 11:40:18.409560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11583 11:40:18.409846 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11585 11:40:18.421808 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11586 11:40:21.029616 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2709 ms)
11587 11:40:21.039513 [0:03:27.731120242] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 11:40:21.119709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11589 11:40:21.120004 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11591 11:40:21.131690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11592 11:40:24.788640 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3758 ms)
11593 11:40:24.798708 [0:03:31.490303242] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 11:40:24.878533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11595 11:40:24.878840 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11597 11:40:24.893127 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11598 11:40:30.226940 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5438 ms)
11599 11:40:30.236531 [0:03:36.928634550] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 11:40:30.328812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11601 11:40:30.329715 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11603 11:40:30.343484 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11604 11:40:38.399062 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8172 ms)
11605 11:40:38.408999 [0:03:45.101874013] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 11:40:38.507449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11607 11:40:38.508129 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11609 11:40:38.521670 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11610 11:40:50.977386 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12579 ms)
11611 11:40:50.987154 [0:03:57.681600859] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 11:40:51.070594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11613 11:40:51.070871 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11615 11:40:51.083950 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11616 11:41:10.696515 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19721 ms)
11617 11:41:10.706569 [0:04:17.403755091] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 11:41:10.755487 [0:04:17.457651630] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 11:41:10.800442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11620 11:41:10.800730 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11622 11:41:10.810446 [0:04:17.511612014] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 11:41:10.817064 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11624 11:41:10.865594 [0:04:17.566913322] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 11:41:10.868689 Camera needs 4 requests, can't test only 1
11626 11:41:10.941371 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11627 11:41:11.010004
11628 11:41:11.092872 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11629 11:41:11.182116 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11631 11:41:11.184947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11632 11:41:11.198857 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11633 11:41:11.257162 Camera needs 4 requests, can't test only 2
11634 11:41:11.344092 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11635 11:41:11.429066
11636 11:41:11.525085 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11637 11:41:11.619705 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11639 11:41:11.623148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11640 11:41:11.634290 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11641 11:41:11.685675 Camera needs 4 requests, can't test only 3
11642 11:41:11.760258 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11643 11:41:11.829865
11644 11:41:11.908493 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11645 11:41:11.998362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11646 11:41:11.999011 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11648 11:41:12.011770 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11649 11:41:12.937559 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2077 ms)
11650 11:41:12.947005 [0:04:19.644268861] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 11:41:13.041056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11652 11:41:13.041752 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11654 11:41:13.055745 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11655 11:41:15.645140 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2708 ms)
11656 11:41:15.655238 [0:04:22.352448246] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11657 11:41:15.733582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11658 11:41:15.733852 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11660 11:41:15.746868 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11661 11:41:19.403303 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3758 ms)
11662 11:41:19.413049 [0:04:26.111167246] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11663 11:41:19.513107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11664 11:41:19.513794 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11666 11:41:19.528772 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11667 11:41:24.840747 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5437 ms)
11668 11:41:24.850381 [0:04:31.548976785] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 11:41:24.947881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11670 11:41:24.948535 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11672 11:41:24.962594 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11673 11:41:33.009961 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8170 ms)
11674 11:41:33.019832 [0:04:39.719491939] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 11:41:33.115730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11676 11:41:33.116477 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11678 11:41:33.129007 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11679 11:41:45.587399 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12578 ms)
11680 11:41:45.597212 [0:04:52.298365786] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 11:41:45.690036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11682 11:41:45.690694 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11684 11:41:45.703609 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11685 11:42:05.306012 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19720 ms)
11686 11:42:05.315988 [0:05:12.019261941] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 11:42:05.415933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11688 11:42:05.416585 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11690 11:42:05.432208 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11691 11:42:05.717572 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (414 ms)
11692 11:42:05.730333 [0:05:12.434108710] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 11:42:05.825589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11694 11:42:05.826227 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11696 11:42:05.843706 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11697 11:42:06.204701 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (486 ms)
11698 11:42:06.217259 [0:05:12.920433095] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 11:42:06.308128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11700 11:42:06.308399 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11702 11:42:06.322972 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11703 11:42:06.758528 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (554 ms)
11704 11:42:06.771523 [0:05:13.475470633] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 11:42:06.845441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11706 11:42:06.845718 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11708 11:42:06.860980 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11709 11:42:07.453952 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11710 11:42:07.464257 [0:05:14.170741864] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 11:42:07.563151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11712 11:42:07.563872 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11714 11:42:07.580991 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11715 11:42:08.359014 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (905 ms)
11716 11:42:08.372041 [0:05:15.075800172] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 11:42:08.466539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11718 11:42:08.467208 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11720 11:42:08.485733 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11721 11:42:09.613953 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1254 ms)
11722 11:42:09.626714 [0:05:16.330761326] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 11:42:09.720572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11724 11:42:09.721251 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11726 11:42:09.738497 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11727 11:42:11.427997 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1814 ms)
11728 11:42:11.440912 [0:05:18.144898941] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11729 11:42:11.540884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11730 11:42:11.541678 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11732 11:42:11.558009 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11733 11:42:14.152623 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2725 ms)
11734 11:42:14.165894 [0:05:20.870516864] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11735 11:42:14.240757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11736 11:42:14.241034 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11738 11:42:14.254765 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11739 11:42:18.348240 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4195 ms)
11740 11:42:18.361199 [0:05:25.066238711] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 11:42:18.457955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11742 11:42:18.458662 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11744 11:42:18.476188 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11745 11:42:24.923097 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6575 ms)
11746 11:42:24.936120 [0:05:31.641765250] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 11:42:25.030582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11748 11:42:25.031271 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11750 11:42:25.047965 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11751 11:42:25.341261 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (414 ms)
11752 11:42:25.351457 [0:05:32.056511711] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 11:42:25.442842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11754 11:42:25.443113 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11756 11:42:25.455571 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11757 11:42:25.825559 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (484 ms)
11758 11:42:25.835614 [0:05:32.541238173] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 11:42:25.912529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11760 11:42:25.912818 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11762 11:42:25.922895 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11763 11:42:26.380545 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (554 ms)
11764 11:42:26.391160 [0:05:33.096356942] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11765 11:42:26.481639 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11767 11:42:26.484275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11768 11:42:26.499577 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11769 11:42:27.075406 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (694 ms)
11770 11:42:27.085018 [0:05:33.790895865] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 11:42:27.177630 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11773 11:42:27.180441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11774 11:42:27.194379 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11775 11:42:27.981973 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (906 ms)
11776 11:42:27.991894 [0:05:34.697872634] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11777 11:42:28.086952 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11779 11:42:28.089857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11780 11:42:28.105774 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11781 11:42:29.236991 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1254 ms)
11782 11:42:29.246842 [0:05:35.952664788] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11783 11:42:29.337308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11784 11:42:29.337976 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11786 11:42:29.350802 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11787 11:42:31.051897 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1814 ms)
11788 11:42:31.061669 [0:05:37.767456250] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11789 11:42:31.155388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11790 11:42:31.155666 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11792 11:42:31.168740 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11793 11:42:33.777575 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2726 ms)
11794 11:42:33.787387 [0:05:40.493487173] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11795 11:42:33.883077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11796 11:42:33.883750 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11798 11:42:33.897197 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11799 11:42:37.972256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4194 ms)
11800 11:42:37.981621 [0:05:44.688618327] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11801 11:42:38.076226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11802 11:42:38.076901 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11804 11:42:38.091498 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11805 11:42:44.546638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6575 ms)
11806 11:42:44.556407 [0:05:51.264388712] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11807 11:42:44.658393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11808 11:42:44.659036 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11810 11:42:44.672183 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11811 11:42:44.961257 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (414 ms)
11812 11:42:44.971511 [0:05:51.679120789] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11813 11:42:45.066312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11814 11:42:45.066975 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11816 11:42:45.081224 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11817 11:42:45.446257 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (484 ms)
11818 11:42:45.456115 [0:05:52.163964405] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11819 11:42:45.538691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11820 11:42:45.538988 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11822 11:42:45.550817 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11823 11:42:46.001592 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (555 ms)
11824 11:42:46.011339 [0:05:52.719235097] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11825 11:42:46.111215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11826 11:42:46.111854 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11828 11:42:46.125228 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11829 11:42:46.695457 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (694 ms)
11830 11:42:46.705837 [0:05:53.413507251] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11831 11:42:46.805169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11832 11:42:46.805812 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11834 11:42:46.819873 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11835 11:42:47.601992 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (906 ms)
11836 11:42:47.611492 [0:05:54.319835482] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11837 11:42:47.708080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11838 11:42:47.708765 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11840 11:42:47.721653 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11841 11:42:48.856405 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11842 11:42:48.866940 [0:05:55.575054559] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11843 11:42:48.968891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11844 11:42:48.969593 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11846 11:42:48.985050 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11847 11:42:50.671574 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1815 ms)
11848 11:42:50.681302 [0:05:57.390237251] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11849 11:42:50.778003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11850 11:42:50.778643 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11852 11:42:50.793294 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11853 11:42:53.396889 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2725 ms)
11854 11:42:53.406526 [0:06:00.115742174] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11855 11:42:53.505041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11856 11:42:53.505808 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11858 11:42:53.520151 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11859 11:42:57.591919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4195 ms)
11860 11:42:57.601796 [0:06:04.311371021] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11861 11:42:57.694882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11862 11:42:57.695536 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11864 11:42:57.709287 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11865 11:43:04.167156 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6575 ms)
11866 11:43:04.176760 [0:06:10.886557021] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11867 11:43:04.273498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11868 11:43:04.274136 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11870 11:43:04.286996 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11871 11:43:04.581197 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (414 ms)
11872 11:43:04.590996 [0:06:11.300884329] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11873 11:43:04.685494 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11875 11:43:04.688033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11876 11:43:04.703090 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11877 11:43:05.065793 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (484 ms)
11878 11:43:05.075316 [0:06:11.785819483] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11879 11:43:05.169305 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11881 11:43:05.172462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11882 11:43:05.188115 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11883 11:43:05.620504 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (554 ms)
11884 11:43:05.629900 [0:06:12.340597637] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11885 11:43:05.723252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11887 11:43:05.726745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11888 11:43:05.741825 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11889 11:43:06.315744 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (694 ms)
11890 11:43:06.325758 [0:06:13.035760406] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11891 11:43:06.420578 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11893 11:43:06.423693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11894 11:43:06.438991 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11895 11:43:07.220919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (905 ms)
11896 11:43:07.230364 [0:06:13.940820483] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11897 11:43:07.323033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11898 11:43:07.323725 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11900 11:43:07.340714 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11901 11:43:08.475528 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1254 ms)
11902 11:43:08.485525 [0:06:15.195769791] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11903 11:43:08.579294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11905 11:43:08.581771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11906 11:43:08.597029 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11907 11:43:10.289646 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1814 ms)
11908 11:43:10.299687 [0:06:17.010657483] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11909 11:43:10.389780 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11911 11:43:10.392764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11912 11:43:10.404809 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11913 11:43:13.015276 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2725 ms)
11914 11:43:13.024570 [0:06:19.736093099] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11915 11:43:13.120874 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11917 11:43:13.123725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11918 11:43:13.138794 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11919 11:43:17.209897 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
11920 11:43:17.219895 [0:06:23.931639253] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11921 11:43:17.313553 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11923 11:43:17.316304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11924 11:43:17.331492 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11925 11:43:23.785413 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
11926 11:43:23.884220 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11928 11:43:23.887473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11929 11:43:23.901852 [----------] 120 tests from CaptureTests/SingleStream (369829 ms total)
11930 11:43:23.991726
11931 11:43:24.079584 [----------] Global test environment tear-down
11932 11:43:24.166148 [==========] 120 tests from 1 test suite ran. (369829 ms total)
11933 11:43:24.256935 <LAVA_SIGNAL_TESTSET STOP>
11934 11:43:24.257613 Received signal: <TESTSET> STOP
11935 11:43:24.257922 Closing test_set CaptureTests/SingleStream
11936 11:43:24.260150 + set +x
11937 11:43:24.263488 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14864627_1.6.2.3.1>
11938 11:43:24.264089 Received signal: <ENDRUN> 0_lc-compliance 14864627_1.6.2.3.1
11939 11:43:24.264440 Ending use of test pattern.
11940 11:43:24.264723 Ending test lava.0_lc-compliance (14864627_1.6.2.3.1), duration 371.97
11942 11:43:24.266730 <LAVA_TEST_RUNNER EXIT>
11943 11:43:24.267327 ok: lava_test_shell seems to have completed
11944 11:43:24.275648 Capture/Raw_1:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_2:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_3:
set: CaptureTests/SingleStream
result: skip
Capture/Raw_5:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_8:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_13:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_21:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_34:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_55:
set: CaptureTests/SingleStream
result: pass
Capture/Raw_89:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
Capture/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
Capture/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
Capture/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
Capture/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
Capture/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
Capture/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: skip
CaptureStartStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
CaptureStartStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Raw_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/StillCapture_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/VideoRecording_89:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_1:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_2:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_3:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_5:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_8:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_13:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_21:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_34:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_55:
set: CaptureTests/SingleStream
result: pass
UnbalancedStop/Viewfinder_89:
set: CaptureTests/SingleStream
result: pass
11945 11:43:24.276581 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11946 11:43:24.276979 end: 3 lava-test-retry (duration 00:06:13) [common]
11947 11:43:24.277429 start: 4 finalize (timeout 00:10:00) [common]
11948 11:43:24.277828 start: 4.1 power-off (timeout 00:00:30) [common]
11949 11:43:24.278430 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11950 11:43:26.352552 >> Command sent successfully.
11951 11:43:26.366487 Returned 0 in 2 seconds
11952 11:43:26.367050 end: 4.1 power-off (duration 00:00:02) [common]
11954 11:43:26.367994 start: 4.2 read-feedback (timeout 00:09:58) [common]
11955 11:43:26.368757 Listened to connection for namespace 'common' for up to 1s
11956 11:43:27.369414 Finalising connection for namespace 'common'
11957 11:43:27.369986 Disconnecting from shell: Finalise
11958 11:43:27.370370 / #
11959 11:43:27.471374 end: 4.2 read-feedback (duration 00:00:01) [common]
11960 11:43:27.471944 end: 4 finalize (duration 00:00:03) [common]
11961 11:43:27.472550 Cleaning after the job
11962 11:43:27.473198 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/ramdisk
11963 11:43:27.483650 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/kernel
11964 11:43:27.518250 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/dtb
11965 11:43:27.518576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/nfsrootfs
11966 11:43:27.564443 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14864627/tftp-deploy-ijd5ck1a/modules
11967 11:43:27.569938 Removing override tmp directory at /var/lib/lava/dispatcher/tmp/14864627
11968 11:43:27.830786 Removing root tmp directory at /var/lib/lava/dispatcher/tmp/14864627
11969 11:43:27.830952 Job finished correctly