[Enter `^Ec?' for help] coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)... CPU: 12th Gen Intel(R) Core(TM) i3-1215U CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423 CPU: AES supported, TXT NOT supported, VT supported Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384 Cache size = 10 MiB MCH: device id 4609 (rev 04) is Alderlake-P PCH: device id 5182 (rev 01) is Raptorlake-P SKU IGD: device id 46b3 (rev 0c) is Alderlake P GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 37 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)... Probing TPM I2C: I2C bus 1 version 0x3230302a DW I2C bus 1 at 0xfe022000 (400 KHz) done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Reading cr50 boot mode Cr50 says boot_mode is VERIFIED_RW(0x00). Phase 1 FMAP: area GBB found @ 1805000 (458752 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 1805000 (458752 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_data() HW crypto for hash_alg 3 not supported, using SW VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW FMAP: area VBLOCK_A found @ 500000 (65536 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_data() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Phase 4 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Saving vboot hash. TPM: Extending digest for `VBOOT: boot mode` into PCR 0 tlcl_extend: response is 0 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1 tlcl_extend: response is 0 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 0 Slot A is selected FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) CBFS: mcache @0xfef87600 built for 22 files, used 0x43c of 0x2000 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x1d810 in mcache @0xfef87600 BS: verstage times (exec / console): total (unknown) / 256 ms coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)... Google Chrome EC: version: ro: volmar_v2.0.14126-e605144e9c rw: volmar_v0.0.55-22d1557 running image: 2 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'ecrw.hash' @0x7de00 size 0x20 in mcache @0xfef8785c VB2:check_ec_hash() Hexp RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa VB2:check_ec_hash() Hmir: 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa EC took 941us to calculate image hash VB2:check_ec_hash() Heff RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa VB2:sync_ec() select_rw=RW(active) Waited 270us to clear limit power flag. pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000 TCO_STS: 0000 0000 GEN_PMCON: d0015038 00002200 GBLRST_CAUSE: 00000000 00000000 HPR_CAUSE0: 00000000 prev_sleep_state 5 Abort disabling TXT, as CPU is not TXT capable. cse_lite: Number of partitions = 3 cse_lite: Current partition = RO cse_lite: Next partition = RO cse_lite: Flags = 0x7 cse_lite: RO version = 16.1.25.2049 (Status=0x0, Start=0x2000, End=0x14ffff) cse_lite: RW version = 16.1.25.2049 (Status=0x0, Start=0x1b9000, End=0x3a1fff) FMAP: area SI_ME found @ 1000 (5238784 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 cse_lite: CSE RW partition: offset = 0x1b9000, size = 0x1e9000 CBFS: Found 'me_rw.version' @0x7dd00 size 0xd in mcache @0xfef877e8 cse_lite: CSE CBFS RW version : 16.1.25.2049 cse_lite: Set Boot Partition Info Command (RW) HECI: Global Reset(Type:1) Command coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)... CPU: 12th Gen Intel(R) Core(TM) i3-1215U CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423 CPU: AES supported, TXT NOT supported, VT supported Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384 Cache size = 10 MiB MCH: device id 4609 (rev 04) is Alderlake-P PCH: device id 5182 (rev 01) is Raptorlake-P SKU IGD: device id 46b3 (rev 0c) is Alderlake P GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 37 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)... Probing TPM I2C: I2C bus 1 version 0x3230302a DW I2C bus 1 at 0xfe022000 (400 KHz) done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Reading cr50 boot mode Cr50 says boot_mode is VERIFIED_RW(0x00). Phase 1 FMAP: area GBB found @ 1805000 (458752 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 1805000 (458752 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_data() HW crypto for hash_alg 3 not supported, using SW VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW FMAP: area VBLOCK_A found @ 500000 (65536 bytes) FMAP: area VBLOCK_A found @ 500000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_data() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Phase 4 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Saving vboot hash. TPM: Extending digest for `VBOOT: boot mode` into PCR 0 tlcl_extend: response is 0 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1 tlcl_extend: response is 0 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 0 Slot A is selected FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) CBFS: mcache @0xfef87600 built for 22 files, used 0x43c of 0x2000 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x1d810 in mcache @0xfef87600 BS: verstage times (exec / console): total (unknown) / 257 ms coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)... Google Chrome EC: version: ro: volmar_v2.0.14126-e605144e9c rw: volmar_v0.0.55-22d1557 running image: 2 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'ecrw.hash' @0x7de00 size 0x20 in mcache @0xfef8785c VB2:check_ec_hash() Hexp RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa VB2:check_ec_hash() Hmir: 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa EC took 941us to calculate image hash VB2:check_ec_hash() Heff RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa VB2:sync_ec() select_rw=RW(active) Waited 270us to clear limit power flag. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000 TCO_STS: 0000 0000 GEN_PMCON: d1001038 00002200 GBLRST_CAUSE: 00000040 00000000 HPR_CAUSE0: 00000000 prev_sleep_state 5 Abort disabling TXT, as CPU is not TXT capable. cse_lite: Number of partitions = 3 cse_lite: Current partition = RW cse_lite: Next partition = RW cse_lite: Flags = 0x7 cse_lite: RO version = 16.1.25.2049 (Status=0x0, Start=0x2000, End=0x14ffff) cse_lite: RW version = 16.1.25.2049 (Status=0x0, Start=0x1b9000, End=0x3a1fff) FMAP: area SI_ME found @ 1000 (5238784 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 cse_lite: CSE RW partition: offset = 0x1b9000, size = 0x1e9000 CBFS: Found 'me_rw.version' @0x7dd00 size 0xd in mcache @0xfef877e8 cse_lite: CSE CBFS RW version : 16.1.25.2049 Boot Count incremented to 2865 CBFS: Found 'fspm.bin' @0x7dfc0 size 0xc0000 in mcache @0xfef878d4 FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes) Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100d return code 0 MRC: Hash idx 0x100d comparison successful. MRC cache found, size f6c8 bootmode is set to: 2 EC returned error result code 3 FW_CONFIG value from CBI is 0x131 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED SPD index = 0 CBFS: Found 'spd.bin' @0x78380 size 0x400 in mcache @0xfef8776c SPD: module type is LPDDR4X SPD: module part number is K4U6E3S4AB-MGCL SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 16 bits SPD: module size is 1024 MB (per channel) CBMEM: IMD: root @ 0x76fff000 254 entries. IMD: root @ 0x76ffec00 62 entries. FMAP: area RO_VPD found @ 1800000 (16384 bytes) RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ f29000 (8192 bytes) FMAP: area COREBOOT found @ 1875000 (7909376 bytes) External stage cache: IMD: root @ 0x7bbff000 254 entries. IMD: root @ 0x7bbfec00 62 entries. FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. MRC: 'RW_MRC_CACHE' does not need update. 8 DIMMs found SMM Memory Map SMRAM : 0x7b800000 0x800000 Subregion 0: 0x7b800000 0x200000 Subregion 1: 0x7ba00000 0x200000 Subregion 2: 0x7bc00000 0x400000 top_of_ram = 0x77000000 MTRR Range: Start=76000000 End=77000000 (Size 1000000) MTRR Range: Start=7b800000 End=7c000000 (Size 800000) MTRR Range: Start=f9000000 End=fa000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) Normal boot CBFS: Found 'fallback/postcar' @0x185000 size 0x54dc in mcache @0xfef87948 Loading module at 0x76ab9000 with entry 0x76ab9031. filesize: 0x50e8 memsize: 0xa4a0 Processing 237 relocs. Offset value of 0x74ab9000 BS: romstage times (exec / console): total (unknown) / 377 ms coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 postcar starting (log level: 8)... Normal boot FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'fallback/ramstage' @0x52d00 size 0x24b33 in mcache @0x76add0b0 Loading module at 0x76a2f000 with entry 0x76a2f000. filesize: 0x51f70 memsize: 0x880d0 Processing 5931 relocs. Offset value of 0x72a2f000 BS: postcar times (exec / console): total (unknown) / 51 ms coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 ramstage starting (log level: 8)... Reserving BERT start 76a1e000, size 10000 Normal boot FMAP: area RO_VPD found @ 1800000 (16384 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 FMAP: area RW_VPD found @ f29000 (8192 bytes) Google Chrome EC: version: ro: volmar_v2.0.14126-e605144e9c rw: volmar_v0.0.55-22d1557 running image: 2 ACPI _SWS is PM1 Index 8 GPE Index -1 BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms EC returned error result code 3 FW_CONFIG value from CBI is 0x131 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED PCI: 00:1c.2 disabled by fw_config fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: FPMCU_MASK=FPMCU_ENABLED FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes) CBFS: Found 'cpu_microcode_blob.bin' @0x1d8c0 size 0x35400 in mcache @0x76add080 microcode: sig=0x906a4 pf=0x80 revision=0x423 microcode: Update skipped, already up-to-date CBFS: Found 'fsps.bin' @0x13e000 size 0x46fb3 in mcache @0x76add314 Detected 6 core, 8 thread CPU. Setting up SMI for CPU IED base = 0x7bc00000 IED size = 0x00400000 Will perform SMM setup. CPU: 12th Gen Intel(R) Core(TM) i3-1215U. LAPIC 0x0 in XAPIC mode. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 Processing 18 relocs. Offset value of 0x00030000 Attempting to start 7 APs Waiting for 10ms after sending INIT. Waiting for SIPI to complete... done. LAPIC 0x16 in XAPIC mode. LAPIC 0x14 in XAPIC mode. LAPIC 0x1 in XAPIC mode. AP: slot 1 apic_id 16, MCU rev: 0x00000423 AP: slot 4 apic_id 14, MCU rev: 0x00000423 LAPIC 0x9 in XAPIC mode. LAPIC 0x8 in XAPIC mode. LAPIC 0x10 in XAPIC mode. Waiting for SIPI to complete... done. AP: slot 6 apic_id 1, MCU rev: 0x00000423 LAPIC 0x12 in XAPIC mode. AP: slot 2 apic_id 10, MCU rev: 0x00000423 AP: slot 3 apic_id 12, MCU rev: 0x00000423 AP: slot 7 apic_id 8, MCU rev: 0x00000423 AP: slot 5 apic_id 9, MCU rev: 0x00000423 smm_setup_relocation_handler: enter smm_setup_relocation_handler: exit Loading module at 0x00038000 with entry 0x00038000. filesize: 0x208 memsize: 0x208 Processing 11 relocs. Offset value of 0x00038000 smm_module_setup_stub: stack_top = 0x7b804000 smm_module_setup_stub: per cpu stack_size = 0x800 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0x10000 SMM Module: stub loaded at 38000. Will call 0x76a52094 Installing permanent SMM handler to 0x7b800000 smm_load_module: total_smm_space_needed e468, available -> 200000 Loading module at 0x7b9f6000 with entry 0x7b9f6d5f. filesize: 0x4348 memsize: 0x9468 Processing 255 relocs. Offset value of 0x7b9f6000 smm_load_module: smram_start: 0x7b800000 smm_load_module: smram_end: 7ba00000 smm_load_module: handler start 0x7b9f6d5f smm_load_module: handler_size 98d0 smm_load_module: fxsave_area 0x7b9ff000 smm_load_module: fxsave_size 1000 smm_load_module: CONFIG_MSEG_SIZE 0x0 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0 smm_load_module: handler_mod_params.smbase = 0x7b800000 smm_load_module: per_cpu_save_state_size = 0x400 smm_load_module: num_cpus = 0x8 smm_load_module: cbmemc = 0x76ade000, cbmemc_size = 0x20000 smm_load_module: total_save_state_size = 0x2000 smm_load_module: cpu0 entry: 7b9e6000 smm_create_map: cpus allowed in one segment 30 smm_create_map: min # of segments needed 1 CPU 0x0 smbase 7b9e6000 entry 7b9ee000 ss_start 7b9f5c00 code_end 7b9ee208 CPU 0x1 smbase 7b9e5c00 entry 7b9edc00 ss_start 7b9f5800 code_end 7b9ede08 CPU 0x2 smbase 7b9e5800 entry 7b9ed800 ss_start 7b9f5400 code_end 7b9eda08 CPU 0x3 smbase 7b9e5400 entry 7b9ed400 ss_start 7b9f5000 code_end 7b9ed608 CPU 0x4 smbase 7b9e5000 entry 7b9ed000 ss_start 7b9f4c00 code_end 7b9ed208 CPU 0x5 smbase 7b9e4c00 entry 7b9ecc00 ss_start 7b9f4800 code_end 7b9ece08 CPU 0x6 smbase 7b9e4800 entry 7b9ec800 ss_start 7b9f4400 code_end 7b9eca08 CPU 0x7 smbase 7b9e4400 entry 7b9ec400 ss_start 7b9f4000 code_end 7b9ec608 Loading module at 0x7b9ee000 with entry 0x7b9ee000. filesize: 0x208 memsize: 0x208 Processing 11 relocs. Offset value of 0x7b9ee000 smm_place_entry_code: smbase 7b9e4400, stack_top 7b804000 SMM Module: placing smm entry code at 7b9edc00, cpu # 0x1 smm_place_entry_code: copying from 7b9ee000 to 7b9edc00 0x208 bytes SMM Module: placing smm entry code at 7b9ed800, cpu # 0x2 smm_place_entry_code: copying from 7b9ee000 to 7b9ed800 0x208 bytes SMM Module: placing smm entry code at 7b9ed400, cpu # 0x3 smm_place_entry_code: copying from 7b9ee000 to 7b9ed400 0x208 bytes SMM Module: placing smm entry code at 7b9ed000, cpu # 0x4 smm_place_entry_code: copying from 7b9ee000 to 7b9ed000 0x208 bytes SMM Module: placing smm entry code at 7b9ecc00, cpu # 0x5 smm_place_entry_code: copying from 7b9ee000 to 7b9ecc00 0x208 bytes SMM Module: placing smm entry code at 7b9ec800, cpu # 0x6 smm_place_entry_code: copying from 7b9ee000 to 7b9ec800 0x208 bytes SMM Module: placing smm entry code at 7b9ec400, cpu # 0x7 smm_place_entry_code: copying from 7b9ee000 to 7b9ec400 0x208 bytes smm_module_setup_stub: stack_top = 0x7b804000 smm_module_setup_stub: per cpu stack_size = 0x800 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0x200000 SMM Module: stub loaded at 7b9ee000. Will call 0x7b9f6d5f Clearing SMI status registers SMI_STS: PM1 PM1_STS: WAK PWRBTN smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e6000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x7b9e6000 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4800, cpu = 6 In relocation handler: CPU 6 New SMBASE=0x7b9e4800 IEDBASE=0x7bc00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5000, cpu = 4 In relocation handler: CPU 4 New SMBASE=0x7b9e5000 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5c00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x7b9e5c00 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5800, cpu = 2 In relocation handler: CPU 2 New SMBASE=0x7b9e5800 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5400, cpu = 3 In relocation handler: CPU 3 New SMBASE=0x7b9e5400 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4c00, cpu = 5 In relocation handler: CPU 5 New SMBASE=0x7b9e4c00 IEDBASE=0x7bc00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4400, cpu = 7 In relocation handler: CPU 7 New SMBASE=0x7b9e4400 IEDBASE=0x7bc00000 Writing SMRR. base = 0x7b800006, mask=0xff800c00 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 Clearing out pending MCEs cpu: energy policy set to 7 Turbo is available but hidden Turbo is available and visible microcode: Update skipped, already up-to-date CPU #0 initialized Initializing CPU #6 Initializing CPU #3 Initializing CPU #4 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 Initializing CPU #1 Initializing CPU #7 Initializing CPU #2 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 Clearing out pending MCEs Clearing out pending MCEs Clearing out pending MCEs CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 cpu: energy policy set to 7 Clearing out pending MCEs cpu: energy policy set to 7 microcode: Update skipped, already up-to-date CPU #2 initialized microcode: Update skipped, already up-to-date CPU #3 initialized cpu: energy policy set to 7 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 microcode: Update skipped, already up-to-date CPU #4 initialized Clearing out pending MCEs Clearing out pending MCEs cpu: energy policy set to 7 Initializing CPU #5 microcode: Update skipped, already up-to-date CPU #1 initialized cpu: energy policy set to 7 cpu: energy policy set to 7 CPU: vendor Intel device 906a4 CPU: family 06, model 9a, stepping 04 microcode: Update skipped, already up-to-date CPU #7 initialized Clearing out pending MCEs microcode: Update skipped, already up-to-date CPU #6 initialized cpu: energy policy set to 7 microcode: Update skipped, already up-to-date CPU #5 initialized bsp_do_flight_plan done after 712 msecs. CPU: frequency set to 4400 MHz Enabling SMIs. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 380 / 521 ms Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9 Enabling GPIO PM b/c CR50 has long IRQ pulse support fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S CBFS: Found 'vbt.bin' @0x7d7c0 size 0x4e9 in mcache @0x76add1b8 Found a VBT of 9216 bytes after decompression PCI 1.0, PIN A, using IRQ #16 PCI 2.0, PIN A, using IRQ #17 PCI 4.0, PIN A, using IRQ #18 PCI 5.0, PIN A, using IRQ #16 PCI 6.0, PIN A, using IRQ #16 PCI 6.2, PIN C, using IRQ #18 PCI 7.0, PIN A, using IRQ #19 PCI 7.1, PIN B, using IRQ #20 PCI 7.2, PIN C, using IRQ #21 PCI 7.3, PIN D, using IRQ #22 PCI 8.0, PIN A, using IRQ #23 PCI D.0, PIN A, using IRQ #17 PCI D.1, PIN B, using IRQ #19 PCI 10.0, PIN A, using IRQ #24 PCI 10.1, PIN B, using IRQ #25 PCI 10.6, PIN C, using IRQ #20 PCI 10.7, PIN D, using IRQ #21 PCI 11.0, PIN A, using IRQ #26 PCI 11.1, PIN B, using IRQ #27 PCI 11.2, PIN C, using IRQ #28 PCI 11.3, PIN D, using IRQ #29 PCI 12.0, PIN A, using IRQ #30 PCI 12.6, PIN B, using IRQ #31 PCI 12.7, PIN C, using IRQ #22 PCI 13.0, PIN A, using IRQ #32 PCI 13.1, PIN B, using IRQ #33 PCI 13.2, PIN C, using IRQ #34 PCI 13.3, PIN D, using IRQ #35 PCI 14.0, PIN B, using IRQ #23 PCI 14.1, PIN A, using IRQ #36 PCI 14.3, PIN C, using IRQ #17 PCI 15.0, PIN A, using IRQ #37 PCI 15.1, PIN B, using IRQ #38 PCI 15.2, PIN C, using IRQ #39 PCI 15.3, PIN D, using IRQ #40 PCI 16.0, PIN A, using IRQ #18 PCI 16.1, PIN B, using IRQ #19 PCI 16.2, PIN C, using IRQ #20 PCI 16.3, PIN D, using IRQ #21 PCI 16.4, PIN A, using IRQ #18 PCI 16.5, PIN B, using IRQ #19 PCI 17.0, PIN A, using IRQ #22 PCI 19.0, PIN A, using IRQ #41 PCI 19.1, PIN B, using IRQ #42 PCI 19.2, PIN C, using IRQ #43 PCI 1C.0, PIN A, using IRQ #16 PCI 1C.1, PIN B, using IRQ #17 PCI 1C.2, PIN C, using IRQ #18 PCI 1C.3, PIN D, using IRQ #19 PCI 1C.4, PIN A, using IRQ #16 PCI 1C.5, PIN B, using IRQ #17 PCI 1C.6, PIN C, using IRQ #18 PCI 1C.7, PIN D, using IRQ #19 PCI 1D.0, PIN A, using IRQ #16 PCI 1D.1, PIN B, using IRQ #17 PCI 1D.2, PIN C, using IRQ #18 PCI 1D.3, PIN D, using IRQ #19 PCI 1E.0, PIN A, using IRQ #23 PCI 1E.1, PIN B, using IRQ #20 PCI 1E.2, PIN C, using IRQ #44 PCI 1E.3, PIN D, using IRQ #45 PCI 1F.3, PIN B, using IRQ #22 PCI 1F.4, PIN C, using IRQ #23 PCI 1F.6, PIN D, using IRQ #20 PCI 1F.7, PIN A, using IRQ #21 IRQ: Using dynamically assigned PCI IO-APIC IRQs WEAK: src/soc/intel/alderlake/fsp_params.c/mainboard_silicon_init_params called FSPS returned 0 Executing Phase 1 of FspMultiPhaseSiInit FSP MultiPhaseSiInit src/soc/intel/alderlake/fsp_params.c/platform_fsp_multi_phase_init_cb called port C0 DISC req: usage 1 usb3 1 usb2 1 Raw Buffer output 0 00000111 Raw Buffer output 1 00000000 pmc_send_ipc_cmd succeeded port C1 DISC req: usage 1 usb3 3 usb2 3 Raw Buffer output 0 00000331 Raw Buffer output 1 00000000 pmc_send_ipc_cmd succeeded Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Detected 6 core, 8 thread CPU. Display FSP Version Info HOB Reference Code - CPU = c.0.65.70 uCode Version = 0.0.4.23 TXT ACM version = ff.ff.ff.ffff Reference Code - ME = c.0.65.70 MEBx version = 0.0.0.0 ME Firmware Version = Lite SKU Reference Code - PCH = c.0.65.70 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff PCH Hsio Version = 4.0.0.0 Reference Code - SA - System Agent = c.0.65.70 Reference Code - MRC = 0.0.3.80 SA - PCIe Version = c.0.65.70 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.4 SA-CRID New Value = 0.0.0.4 OPROM - VBIOS = ff.ff.ff.ffff IO Manageability Engine FW Version = 24.0.4.0 PHY Build Version = 0.0.0.2016 Thunderbolt(TM) FW Version = 0.0.0.0 System Agent Manageability Engine FW Version = ff.ff.ff.ffff BS: BS_DEV_INIT_CHIPS run times (exec / console): 496 / 507 ms Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 GPIO: 0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 0 PCI: 00:01.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:06.2: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:07.1: enabled 0 PCI: 00:07.2: enabled 0 PCI: 00:07.3: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0d.1: enabled 0 PCI: 00:0d.2: enabled 0 PCI: 00:0d.3: enabled 0 PCI: 00:0e.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:10.1: enabled 0 PCI: 00:10.6: enabled 0 PCI: 00:10.7: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:12.7: enabled 0 PCI: 00:13.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 0 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1d.1: enabled 0 PCI: 00:1d.2: enabled 0 PCI: 00:1d.3: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 00:1f.7: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 USB0 port 0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:31: enabled 1 I2C: 00:32: enabled 1 I2C: 00:50: enabled 1 I2C: 00:10: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 GENERIC: 0.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 1 USB3 port 3: enabled 0 USB2 port 0: enabled 1 USB2 port 1: enabled 0 USB2 port 2: enabled 1 USB2 port 3: enabled 0 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 0 USB2 port 8: enabled 1 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 0 USB3 port 3: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 APIC: 00: enabled 1 APIC: 16: enabled 1 APIC: 10: enabled 1 APIC: 12: enabled 1 APIC: 14: enabled 1 APIC: 09: enabled 1 APIC: 01: enabled 1 APIC: 08: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: 16: enabled 1 APIC: 10: enabled 1 APIC: 12: enabled 1 APIC: 14: enabled 1 APIC: 09: enabled 1 APIC: 01: enabled 1 APIC: 08: enabled 1 DOMAIN: 0000: enabled 1 GPIO: 0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 0 PCI: 00:01.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:06.2: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0d.0: enabled 1 USB0 port 0: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 1 USB3 port 3: enabled 0 PCI: 00:0d.1: enabled 0 PCI: 00:0d.2: enabled 0 PCI: 00:0d.3: enabled 0 PCI: 00:0e.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:10.1: enabled 0 PCI: 00:10.6: enabled 0 PCI: 00:10.7: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:12.7: enabled 0 PCI: 00:13.0: enabled 0 PCI: 00:14.0: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 0 USB2 port 2: enabled 1 USB2 port 3: enabled 0 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 0 USB2 port 8: enabled 1 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 0 USB3 port 3: enabled 0 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:15.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:31: enabled 1 I2C: 00:32: enabled 1 PCI: 00:15.1: enabled 1 I2C: 00:50: enabled 1 PCI: 00:15.2: enabled 0 PCI: 00:15.3: enabled 1 I2C: 00:10: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:19.1: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 SPI: 00: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 00:1f.7: enabled 0 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/4609] enabled PCI: 00:02.0 [8086/0000] bus ops PCI: 00:02.0 [8086/46b3] enabled PCI: 00:04.0 [8086/0000] bus ops PCI: 00:04.0 [8086/461d] enabled PCI: 00:06.0 [8086/0000] bus ops PCI: 00:06.0 [8086/464d] enabled PCI: 00:08.0 [8086/464f] disabled PCI: 00:0a.0 [8086/467d] enabled PCI: 00:0d.0 [8086/0000] bus ops PCI: 00:0d.0 [8086/461e] enabled PCI: 00:14.0 [8086/0000] bus ops PCI: 00:14.0 [8086/51ed] enabled PCI: 00:14.2 [8086/51ef] enabled PCI: 00:14.3 [8086/0000] bus ops PCI: 00:14.3 [8086/51f0] enabled PCI: 00:15.0 [8086/0000] bus ops PCI: 00:15.0 [8086/51e8] enabled PCI: 00:15.1 [8086/0000] bus ops PCI: 00:15.1 [8086/51e9] enabled PCI: 00:15.2 [8086/0000] bus ops PCI: 00:15.2 [8086/51ea] disabled PCI: 00:15.3 [8086/0000] bus ops PCI: 00:15.3 [8086/51eb] enabled PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/51e0] enabled PCI: Static device PCI: 00:17.0 not found, disabling it. PCI: 00:19.0 [8086/0000] bus ops PCI: 00:19.0 [8086/51c5] disabled PCI: 00:19.1 [8086/0000] bus ops PCI: 00:19.1 [8086/51c6] enabled PCI: 00:1e.0 [8086/0000] ops PCI: 00:1e.0 [8086/51a8] enabled PCI: 00:1e.3 [8086/0000] bus ops PCI: 00:1e.3 [8086/51ab] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/5182] enabled RTC Init Set power on after power failure. Disabling Deep S3 Disabling Deep S3 Disabling Deep S4 Disabling Deep S4 Disabling Deep S5 Disabling Deep S5 PCI: 00:1f.2 [0000/0000] hidden PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/51c8] enabled PCI: 00:1f.5 [8086/0000] bus ops PCI: 00:1f.5 [8086/51a4] enabled GPIO: 0 enabled PCI: Leftover static devices: PCI: 00:01.0 PCI: 00:01.1 PCI: 00:05.0 PCI: 00:06.2 PCI: 00:09.0 PCI: 00:0d.1 PCI: 00:0d.2 PCI: 00:0d.3 PCI: 00:0e.0 PCI: 00:10.0 PCI: 00:10.1 PCI: 00:10.6 PCI: 00:10.7 PCI: 00:12.0 PCI: 00:12.6 PCI: 00:12.7 PCI: 00:13.0 PCI: 00:14.1 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:16.4 PCI: 00:16.5 PCI: 00:17.0 PCI: 00:19.2 PCI: 00:1a.0 PCI: 00:1e.1 PCI: 00:1e.2 PCI: 00:1f.1 PCI: 00:1f.4 PCI: 00:1f.6 PCI: 00:1f.7 PCI: Check your devicetree.cb. PCI: 00:02.0 scanning... scan_generic_bus for PCI: 00:02.0 scan_generic_bus for PCI: 00:02.0 done scan_bus: bus PCI: 00:02.0 finished in 7 msecs PCI: 00:04.0 scanning... scan_generic_bus for PCI: 00:04.0 GENERIC: 0.0 enabled bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done scan_bus: bus PCI: 00:04.0 finished in 11 msecs PCI: 00:06.0 scanning... do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [15b7/5009] enabled Enabling Common Clock Configuration L1 Sub-State supported from root port 6 L1 Sub-State Support = 0x5 CommonModeRestoreTime = 0x6e Power On Value = 0x5, Power On Scale = 0x2 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 256 PCI: 01:00.0: Enabled LTR PCI: 01:00.0: Programmed LTR max latencies scan_bus: bus PCI: 00:06.0 finished in 40 msecs PCI: 00:0d.0 scanning... scan_static_bus for PCI: 00:0d.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB3 port 0 enabled USB3 port 1 disabled USB3 port 2 enabled USB3 port 3 disabled USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs USB3 port 2 scanning... scan_static_bus for USB3 port 2 scan_static_bus for USB3 port 2 done scan_bus: bus USB3 port 2 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 43 msecs scan_static_bus for PCI: 00:0d.0 done scan_bus: bus PCI: 00:0d.0 finished in 59 msecs PCI: 00:14.0 scanning... scan_static_bus for PCI: 00:14.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB2 port 0 enabled USB2 port 1 disabled USB2 port 2 enabled USB2 port 3 disabled USB2 port 4 disabled USB2 port 5 enabled USB2 port 6 disabled USB2 port 7 disabled USB2 port 8 enabled USB2 port 9 enabled USB3 port 0 enabled USB3 port 1 disabled USB3 port 2 disabled USB3 port 3 disabled USB2 port 0 scanning... scan_static_bus for USB2 port 0 scan_static_bus for USB2 port 0 done scan_bus: bus USB2 port 0 finished in 6 msecs USB2 port 2 scanning... scan_static_bus for USB2 port 2 scan_static_bus for USB2 port 2 done scan_bus: bus USB2 port 2 finished in 6 msecs USB2 port 5 scanning... scan_static_bus for USB2 port 5 scan_static_bus for USB2 port 5 done scan_bus: bus USB2 port 5 finished in 6 msecs USB2 port 8 scanning... scan_static_bus for USB2 port 8 scan_static_bus for USB2 port 8 done scan_bus: bus USB2 port 8 finished in 6 msecs USB2 port 9 scanning... scan_static_bus for USB2 port 9 scan_static_bus for USB2 port 9 done scan_bus: bus USB2 port 9 finished in 6 msecs USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 120 msecs scan_static_bus for PCI: 00:14.0 done scan_bus: bus PCI: 00:14.0 finished in 136 msecs PCI: 00:14.3 scanning... scan_static_bus for PCI: 00:14.3 GENERIC: 0.0 enabled scan_static_bus for PCI: 00:14.3 done scan_bus: bus PCI: 00:14.3 finished in 9 msecs PCI: 00:15.0 scanning... scan_static_bus for PCI: 00:15.0 I2C: 00:1a enabled I2C: 00:31 enabled I2C: 00:32 enabled scan_static_bus for PCI: 00:15.0 done scan_bus: bus PCI: 00:15.0 finished in 13 msecs PCI: 00:15.1 scanning... scan_static_bus for PCI: 00:15.1 I2C: 00:50 enabled scan_static_bus for PCI: 00:15.1 done scan_bus: bus PCI: 00:15.1 finished in 9 msecs PCI: 00:15.3 scanning... scan_static_bus for PCI: 00:15.3 I2C: 00:10 enabled scan_static_bus for PCI: 00:15.3 done scan_bus: bus PCI: 00:15.3 finished in 9 msecs PCI: 00:19.1 scanning... scan_static_bus for PCI: 00:19.1 I2C: 00:15 enabled I2C: 00:2c enabled scan_static_bus for PCI: 00:19.1 done scan_bus: bus PCI: 00:19.1 finished in 11 msecs PCI: 00:1e.3 scanning... scan_generic_bus for PCI: 00:1e.3 SPI: 00 enabled bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done scan_bus: bus PCI: 00:1e.3 finished in 11 msecs PCI: 00:1f.0 scanning... scan_static_bus for PCI: 00:1f.0 PNP: 0c09.0 enabled PNP: 0c09.0 scanning... scan_static_bus for PNP: 0c09.0 scan_static_bus for PNP: 0c09.0 done scan_bus: bus PNP: 0c09.0 finished in 6 msecs scan_static_bus for PCI: 00:1f.0 done scan_bus: bus PCI: 00:1f.0 finished in 23 msecs PCI: 00:1f.2 scanning... scan_static_bus for PCI: 00:1f.2 GENERIC: 0.0 enabled GENERIC: 0.0 scanning... scan_static_bus for GENERIC: 0.0 GENERIC: 0.0 enabled GENERIC: 1.0 enabled scan_static_bus for GENERIC: 0.0 done scan_bus: bus GENERIC: 0.0 finished in 11 msecs scan_static_bus for PCI: 00:1f.2 done scan_bus: bus PCI: 00:1f.2 finished in 28 msecs PCI: 00:1f.3 scanning... scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done scan_bus: bus PCI: 00:1f.3 finished in 7 msecs PCI: 00:1f.5 scanning... scan_generic_bus for PCI: 00:1f.5 scan_generic_bus for PCI: 00:1f.5 done scan_bus: bus PCI: 00:1f.5 finished in 7 msecs scan_bus: bus DOMAIN: 0000 finished in 710 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 729 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 1297 ms FMAP: area UNIFIED_MRC_CACHE found @ f00000 (131072 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 SPI flash protection: WPSW=0 SRP0=0 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 20 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x20000 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x1000 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x1000 SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x1000 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x4000 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x80000 SA MMIO resource: TPM -> base = 0xfed40000, size = 0x10000 SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x20000 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x100000 SA MMIO resource: PCH_RESERVED -> base = 0xfc800000, size = 0x2000000 SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x1000 SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x1000 SA MMIO resource: TBT0BAR -> base = 0xfed84000, size = 0x1000 SA MMIO resource: TBT1BAR -> base = 0xfed85000, size = 0x1000 SA MMIO resource: TBT2BAR -> base = 0xfed86000, size = 0x1000 SA MMIO resource: TBT3BAR -> base = 0xfed87000, size = 0x1000 SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x1000 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 SA MMIO resource: DSM -> base = 0x7c800000, size = 0x3c00000 SA MMIO resource: TSEG -> base = 0x7b800000, size = 0x800000 SA MMIO resource: GSM -> base = 0x7c000000, size = 0x800000 PCI: 00:04.0 read_resources bus 1 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 done PCI: 00:06.0 read_resources bus 1 link: 0 PCI: 00:06.0 read_resources bus 1 link: 0 done PCI: 00:0d.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:0d.0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:15.0 read_resources bus 0 link: 0 PCI: 00:15.0 read_resources bus 0 link: 0 done PCI: 00:15.1 read_resources bus 0 link: 0 PCI: 00:15.1 read_resources bus 0 link: 0 done PCI: 00:15.3 read_resources bus 0 link: 0 PCI: 00:15.3 read_resources bus 0 link: 0 done PCI: 00:19.1 read_resources bus 0 link: 0 PCI: 00:19.1 read_resources bus 0 link: 0 done PCI: 00:1e.3 read_resources bus 2 link: 0 PCI: 00:1e.3 read_resources bus 2 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI: 00:1f.2 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 done PCI: 00:1f.2 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 16 APIC: 10 APIC: 12 APIC: 14 APIC: 09 APIC: 01 APIC: 08 DOMAIN: 0000 child on link 0 GPIO: 0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 GPIO: 0 PCI: 00:00.0 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:06.0 child on link 0 PCI: 01:00.0 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20 PCI: 00:08.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 PCI: 00:0d.0 child on link 0 USB0 port 0 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB3 port 0 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 4 USB2 port 5 USB2 port 6 USB2 port 7 USB2 port 8 USB2 port 9 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 00:14.3 child on link 0 GENERIC: 0.0 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:15.0 child on link 0 I2C: 00:1a PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:1a I2C: 00:31 I2C: 00:32 PCI: 00:15.1 child on link 0 I2C: 00:50 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:50 PCI: 00:15.2 PCI: 00:15.3 child on link 0 I2C: 00:10 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:19.0 PCI: 00:19.1 child on link 0 I2C: 00:15 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:15 I2C: 00:2c PCI: 00:1e.0 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:1e.3 child on link 0 SPI: 00 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.2 child on link 0 GENERIC: 0.0 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1 GENERIC: 0.0 child on link 0 GENERIC: 0.0 GENERIC: 0.0 GENERIC: 1.0 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20 PCI: 00:1f.5 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x3fff] mem PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed) update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 800, Tag: 100 * Base: 1900, Size: e700, Tag: 100 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 00 base fedc0000 limit feddffff mem (fixed) update_constraints: PCI: 00:00.0 01 base feda0000 limit feda0fff mem (fixed) update_constraints: PCI: 00:00.0 02 base feda1000 limit feda1fff mem (fixed) update_constraints: PCI: 00:00.0 03 base fb000000 limit fb000fff mem (fixed) update_constraints: PCI: 00:00.0 04 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 05 base feb00000 limit feb7ffff mem (fixed) update_constraints: PCI: 00:00.0 06 base fed40000 limit fed4ffff mem (fixed) update_constraints: PCI: 00:00.0 07 base fed50000 limit fed6ffff mem (fixed) update_constraints: PCI: 00:00.0 08 base fec00000 limit fecfffff mem (fixed) update_constraints: PCI: 00:00.0 09 base fc800000 limit fe7fffff mem (fixed) update_constraints: PCI: 00:00.0 0a base fed90000 limit fed90fff mem (fixed) update_constraints: PCI: 00:00.0 0b base fed92000 limit fed92fff mem (fixed) update_constraints: PCI: 00:00.0 0c base fed84000 limit fed84fff mem (fixed) update_constraints: PCI: 00:00.0 0d base fed85000 limit fed85fff mem (fixed) update_constraints: PCI: 00:00.0 0e base fed86000 limit fed86fff mem (fixed) update_constraints: PCI: 00:00.0 0f base fed87000 limit fed87fff mem (fixed) update_constraints: PCI: 00:00.0 10 base fed91000 limit fed91fff mem (fixed) update_constraints: PCI: 00:00.0 11 base c0000000 limit cfffffff mem (fixed) update_constraints: PCI: 00:00.0 12 base 7c800000 limit 803fffff mem (fixed) update_constraints: PCI: 00:00.0 13 base 7b800000 limit 7bffffff mem (fixed) update_constraints: PCI: 00:00.0 14 base 7c000000 limit 7c7fffff mem (fixed) update_constraints: PCI: 00:00.0 15 base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 16 base 000c0000 limit 76ffffff mem (fixed) update_constraints: PCI: 00:00.0 17 base 77000000 limit 803fffff mem (fixed) update_constraints: PCI: 00:00.0 18 base 100000000 limit 27fbfffff mem (fixed) update_constraints: PCI: 00:00.0 19 base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 1a base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:00.0 1b base f8000000 limit f9ffffff mem (fixed) update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed) update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 80400000, Size: 3fc00000, Tag: 200 * Base: d0000000, Size: 28000000, Tag: 200 * Base: fa000000, Size: 1000000, Tag: 200 * Base: fb001000, Size: 17ff000, Tag: 200 * Base: fe800000, Size: 300000, Tag: 200 * Base: feb80000, Size: 80000, Tag: 200 * Base: fed00000, Size: 40000, Tag: 200 * Base: fed70000, Size: 10000, Tag: 200 * Base: fed88000, Size: 8000, Tag: 200 * Base: fed93000, Size: d000, Tag: 200 * Base: feda2000, Size: 1e000, Tag: 200 * Base: fede0000, Size: 1220000, Tag: 200 * Base: 27fc00000, Size: 7d80400000, Tag: 100200 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem PCI: 00:02.0 10 * [0x81000000 - 0x81ffffff] limit: 81ffffff mem PCI: 00:06.0 20 * [0x80400000 - 0x804fffff] limit: 804fffff mem PCI: 00:1f.3 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem PCI: 00:04.0 10 * [0x80600000 - 0x8061ffff] limit: 8061ffff mem PCI: 00:0d.0 10 * [0x80620000 - 0x8062ffff] limit: 8062ffff mem PCI: 00:14.0 10 * [0x80630000 - 0x8063ffff] limit: 8063ffff mem PCI: 00:0a.0 10 * [0x80640000 - 0x80647fff] limit: 80647fff mem PCI: 00:14.2 10 * [0x80648000 - 0x8064bfff] limit: 8064bfff mem PCI: 00:14.3 10 * [0x8064c000 - 0x8064ffff] limit: 8064ffff mem PCI: 00:1f.3 10 * [0x80650000 - 0x80653fff] limit: 80653fff mem PCI: 00:14.2 18 * [0x80654000 - 0x80654fff] limit: 80654fff mem PCI: 00:15.0 10 * [0x80655000 - 0x80655fff] limit: 80655fff mem PCI: 00:15.1 10 * [0x80656000 - 0x80656fff] limit: 80656fff mem PCI: 00:15.3 10 * [0x80657000 - 0x80657fff] limit: 80657fff mem PCI: 00:16.0 10 * [0x80658000 - 0x80658fff] limit: 80658fff mem PCI: 00:19.1 10 * [0x80659000 - 0x80659fff] limit: 80659fff mem PCI: 00:1e.3 10 * [0x8065a000 - 0x8065afff] limit: 8065afff mem PCI: 00:1f.5 10 * [0x8065b000 - 0x8065bfff] limit: 8065bfff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff PCI: 00:06.0: Resource ranges: * Base: 80400000, Size: 100000, Tag: 200 PCI: 01:00.0 10 * [0x80400000 - 0x80403fff] limit: 80403fff mem PCI: 01:00.0 20 * [0x80404000 - 0x804040ff] limit: 804040ff mem PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x0081000000 - 0x0081ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x0080600000 - 0x008061ffff] size 0x00020000 gran 0x11 mem64 PCI: 00:04.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 assign_resources, bus 1 link: 0 done PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:06.0 20 <- [0x0080400000 - 0x00804fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:06.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e mem64 PCI: 01:00.0 20 <- [0x0080404000 - 0x00804040ff] size 0x00000100 gran 0x08 mem64 PCI: 00:06.0 assign_resources, bus 1 link: 0 done PCI: 00:0a.0 10 <- [0x0080640000 - 0x0080647fff] size 0x00008000 gran 0x0f mem64 PCI: 00:0d.0 10 <- [0x0080620000 - 0x008062ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:0d.0 assign_resources, bus 0 link: 0 PCI: 00:0d.0 assign_resources, bus 0 link: 0 done PCI: 00:14.0 10 <- [0x0080630000 - 0x008063ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:14.0 assign_resources, bus 0 link: 0 PCI: 00:14.0 assign_resources, bus 0 link: 0 done PCI: 00:14.2 10 <- [0x0080648000 - 0x008064bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.2 18 <- [0x0080654000 - 0x0080654fff] size 0x00001000 gran 0x0c mem64 PCI: 00:14.3 10 <- [0x008064c000 - 0x008064ffff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 done PCI: 00:15.0 10 <- [0x0080655000 - 0x0080655fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.0 assign_resources, bus 0 link: 0 PCI: 00:15.0 assign_resources, bus 0 link: 0 done PCI: 00:15.1 10 <- [0x0080656000 - 0x0080656fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.1 assign_resources, bus 0 link: 0 PCI: 00:15.1 assign_resources, bus 0 link: 0 done PCI: 00:15.3 10 <- [0x0080657000 - 0x0080657fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.3 assign_resources, bus 0 link: 0 PCI: 00:15.3 assign_resources, bus 0 link: 0 done PCI: 00:16.0 10 <- [0x0080658000 - 0x0080658fff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.1 10 <- [0x0080659000 - 0x0080659fff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.1 assign_resources, bus 0 link: 0 PCI: 00:19.1 assign_resources, bus 0 link: 0 done PCI: 00:1e.3 10 <- [0x008065a000 - 0x008065afff] size 0x00001000 gran 0x0c mem64 PCI: 00:1e.3 assign_resources, bus 2 link: 0 PCI: 00:1e.3 assign_resources, bus 2 link: 0 done PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 done LPC: Trying to open IO window from 800 size 1ff PCI: 00:1f.3 10 <- [0x0080650000 - 0x0080653fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1f.3 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 mem64 PCI: 00:1f.5 10 <- [0x008065b000 - 0x008065bfff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 done Root Device assign_resources, bus 0 link: 0 done Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 16 APIC: 10 APIC: 12 APIC: 14 APIC: 09 APIC: 01 APIC: 08 DOMAIN: 0000 child on link 0 GPIO: 0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 GPIO: 0 PCI: 00:00.0 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b PCI: 00:02.0 PCI: 00:02.0 resource base 81000000 size 1000000 align 24 gran 24 limit 81ffffff flags 60000201 index 10 PCI: 00:02.0 resource base 90000000 size 10000000 align 28 gran 28 limit 9fffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 80600000 size 20000 align 17 gran 17 limit 8061ffff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:06.0 child on link 0 PCI: 01:00.0 PCI: 00:06.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c PCI: 00:06.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 PCI: 00:06.0 resource base 80400000 size 100000 align 20 gran 20 limit 804fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 80400000 size 4000 align 14 gran 14 limit 80403fff flags 60000201 index 10 PCI: 01:00.0 resource base 80404000 size 100 align 12 gran 8 limit 804040ff flags 60000201 index 20 PCI: 00:08.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 80640000 size 8000 align 15 gran 15 limit 80647fff flags 60000201 index 10 PCI: 00:0d.0 child on link 0 USB0 port 0 PCI: 00:0d.0 resource base 80620000 size 10000 align 16 gran 16 limit 8062ffff flags 60000201 index 10 USB0 port 0 child on link 0 USB3 port 0 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 80630000 size 10000 align 16 gran 16 limit 8063ffff flags 60000201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 4 USB2 port 5 USB2 port 6 USB2 port 7 USB2 port 8 USB2 port 9 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.2 PCI: 00:14.2 resource base 80648000 size 4000 align 14 gran 14 limit 8064bfff flags 60000201 index 10 PCI: 00:14.2 resource base 80654000 size 1000 align 12 gran 12 limit 80654fff flags 60000201 index 18 PCI: 00:14.3 child on link 0 GENERIC: 0.0 PCI: 00:14.3 resource base 8064c000 size 4000 align 14 gran 14 limit 8064ffff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:15.0 child on link 0 I2C: 00:1a PCI: 00:15.0 resource base 80655000 size 1000 align 12 gran 12 limit 80655fff flags 60000201 index 10 I2C: 00:1a I2C: 00:31 I2C: 00:32 PCI: 00:15.1 child on link 0 I2C: 00:50 PCI: 00:15.1 resource base 80656000 size 1000 align 12 gran 12 limit 80656fff flags 60000201 index 10 I2C: 00:50 PCI: 00:15.2 PCI: 00:15.3 child on link 0 I2C: 00:10 PCI: 00:15.3 resource base 80657000 size 1000 align 12 gran 12 limit 80657fff flags 60000201 index 10 I2C: 00:10 PCI: 00:16.0 PCI: 00:16.0 resource base 80658000 size 1000 align 12 gran 12 limit 80658fff flags 60000201 index 10 PCI: 00:19.0 PCI: 00:19.1 child on link 0 I2C: 00:15 PCI: 00:19.1 resource base 80659000 size 1000 align 12 gran 12 limit 80659fff flags 60000201 index 10 I2C: 00:15 I2C: 00:2c PCI: 00:1e.0 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:1e.3 child on link 0 SPI: 00 PCI: 00:1e.3 resource base 8065a000 size 1000 align 12 gran 12 limit 8065afff flags 60000201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.2 child on link 0 GENERIC: 0.0 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1 GENERIC: 0.0 child on link 0 GENERIC: 0.0 GENERIC: 0.0 GENERIC: 1.0 PCI: 00:1f.3 PCI: 00:1f.3 resource base 80650000 size 4000 align 14 gran 14 limit 80653fff flags 60000201 index 10 PCI: 00:1f.3 resource base 80500000 size 100000 align 20 gran 20 limit 805fffff flags 60000201 index 20 PCI: 00:1f.5 PCI: 00:1f.5 resource base 8065b000 size 1000 align 12 gran 12 limit 8065bfff flags 60000200 index 10 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 3 / 2716 ms fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S Configure audio over I2S with MAX98373 NAU88L25B. Enabling BT offload BS: BS_DEV_ENABLE entry times (exec / console): 5 / 12 ms Enabling resources... PCI: 00:00.0 subsystem <- 8086/4609 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/46b3 PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 subsystem <- 8086/461d PCI: 00:04.0 cmd <- 02 PCI: 00:06.0 bridge ctrl <- 0013 PCI: 00:06.0 subsystem <- 8086/464d PCI: 00:06.0 cmd <- 106 PCI: 00:0a.0 subsystem <- 8086/467d PCI: 00:0a.0 cmd <- 02 PCI: 00:0d.0 subsystem <- 8086/461e PCI: 00:0d.0 cmd <- 02 PCI: 00:14.0 subsystem <- 8086/51ed PCI: 00:14.0 cmd <- 02 PCI: 00:14.2 subsystem <- 8086/51ef PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 8086/51f0 PCI: 00:14.3 cmd <- 02 PCI: 00:15.0 subsystem <- 8086/51e8 PCI: 00:15.0 cmd <- 02 PCI: 00:15.1 subsystem <- 8086/51e9 PCI: 00:15.1 cmd <- 06 PCI: 00:15.3 subsystem <- 8086/51eb PCI: 00:15.3 cmd <- 02 PCI: 00:16.0 subsystem <- 8086/51e0 PCI: 00:16.0 cmd <- 02 PCI: 00:19.1 subsystem <- 8086/51c6 PCI: 00:19.1 cmd <- 02 PCI: 00:1e.0 subsystem <- 8086/51a8 PCI: 00:1e.0 cmd <- 06 PCI: 00:1e.3 subsystem <- 8086/51ab PCI: 00:1e.3 cmd <- 02 PCI: 00:1f.0 subsystem <- 8086/5182 PCI: 00:1f.0 cmd <- 407 PCI: 00:1f.3 subsystem <- 8086/51c8 PCI: 00:1f.3 cmd <- 02 PCI: 00:1f.5 subsystem <- 8086/51a4 PCI: 00:1f.5 cmd <- 406 PCI: 01:00.0 cmd <- 02 done. BS: BS_DEV_ENABLE run times (exec / console): 1 / 122 ms ME: Version: Unavailable BS: BS_DEV_ENABLE exit times (exec / console): 0 / 3 ms Initializing devices... Root Device init mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: clear events_b mask to 0x0000000000000000 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001808101e Chrome EC: Set WAKE mask to 0x0000000000000000 Root Device init finished in 41 msecs PCI: 00:00.0 init CPU TDP = 15 Watts CPU PL1 = 15 Watts CPU PL2 = 55 Watts CPU PL4 = 123 Watts PCI: 00:00.0 init finished in 8 msecs PCI: 00:02.0 init GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000 PCI: 00:02.0 init finished in 18 msecs PCI: 00:06.0 init Initializing PCH PCIe bridge. PCI: 00:06.0 init finished in 3 msecs PCI: 00:0a.0 init PCI: 00:0a.0 init finished in 0 msecs PCI: 00:14.0 init PCI: 00:14.0 init finished in 0 msecs PCI: 00:14.2 init PCI: 00:14.2 init finished in 0 msecs PCI: 00:15.0 init I2C bus 0 version 0x3230302a DW I2C bus 0 at 0x80655000 (400 KHz) PCI: 00:15.0 init finished in 6 msecs PCI: 00:15.1 init I2C bus 1 version 0x3230302a DW I2C bus 1 at 0x80656000 (400 KHz) PCI: 00:15.1 init finished in 6 msecs PCI: 00:15.3 init I2C bus 3 version 0x3230302a DW I2C bus 3 at 0x80657000 (400 KHz) PCI: 00:15.3 init finished in 6 msecs PCI: 00:16.0 init PCI: 00:16.0 init finished in 0 msecs PCI: 00:19.1 init I2C bus 5 version 0x3230302a DW I2C bus 5 at 0x80659000 (400 KHz) PCI: 00:19.1 init finished in 6 msecs PCI: 00:1f.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x0000: 0x02000000 reg 0x0001: 0x00770020 reg 0x0002: 0x00000000 IOAPIC: 120 interrupts IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: vector 0x00 value 0x00000000 0x00010000 IOAPIC: vector 0x01 value 0x00000000 0x00010000 IOAPIC: vector 0x02 value 0x00000000 0x00010000 IOAPIC: vector 0x03 value 0x00000000 0x00010000 IOAPIC: vector 0x04 value 0x00000000 0x00010000 IOAPIC: vector 0x05 value 0x00000000 0x00010000 IOAPIC: vector 0x06 value 0x00000000 0x00010000 IOAPIC: vector 0x07 value 0x00000000 0x00010000 IOAPIC: vector 0x08 value 0x00000000 0x00010000 IOAPIC: vector 0x09 value 0x00000000 0x00010000 IOAPIC: vector 0x0a value 0x00000000 0x00010000 IOAPIC: vector 0x0b value 0x00000000 0x00010000 IOAPIC: vector 0x0c value 0x00000000 0x00010000 IOAPIC: vector 0x0d value 0x00000000 0x00010000 IOAPIC: vector 0x0e value 0x00000000 0x00010000 IOAPIC: vector 0x0f value 0x00000000 0x00010000 IOAPIC: vector 0x10 value 0x00000000 0x00010000 IOAPIC: vector 0x11 value 0x00000000 0x00010000 IOAPIC: vector 0x12 value 0x00000000 0x00010000 IOAPIC: vector 0x13 value 0x00000000 0x00010000 IOAPIC: vector 0x14 value 0x00000000 0x00010000 IOAPIC: vector 0x15 value 0x00000000 0x00010000 IOAPIC: vector 0x16 value 0x00000000 0x00010000 IOAPIC: vector 0x17 value 0x00000000 0x00010000 IOAPIC: vector 0x18 value 0x00000000 0x00010000 IOAPIC: vector 0x19 value 0x00000000 0x00010000 IOAPIC: vector 0x1a value 0x00000000 0x00010000 IOAPIC: vector 0x1b value 0x00000000 0x00010000 IOAPIC: vector 0x1c value 0x00000000 0x00010000 IOAPIC: vector 0x1d value 0x00000000 0x00010000 IOAPIC: vector 0x1e value 0x00000000 0x00010000 IOAPIC: vector 0x1f value 0x00000000 0x00010000 IOAPIC: vector 0x20 value 0x00000000 0x00010000 IOAPIC: vector 0x21 value 0x00000000 0x00010000 IOAPIC: vector 0x22 value 0x00000000 0x00010000 IOAPIC: vector 0x23 value 0x00000000 0x00010000 IOAPIC: vector 0x24 value 0x00000000 0x00010000 IOAPIC: vector 0x25 value 0x00000000 0x00010000 IOAPIC: vector 0x26 value 0x00000000 0x00010000 IOAPIC: vector 0x27 value 0x00000000 0x00010000 IOAPIC: vector 0x28 value 0x00000000 0x00010000 IOAPIC: vector 0x29 value 0x00000000 0x00010000 IOAPIC: vector 0x2a value 0x00000000 0x00010000 IOAPIC: vector 0x2b value 0x00000000 0x00010000 IOAPIC: vector 0x2c value 0x00000000 0x00010000 IOAPIC: vector 0x2d value 0x00000000 0x00010000 IOAPIC: vector 0x2e value 0x00000000 0x00010000 IOAPIC: vector 0x2f value 0x00000000 0x00010000 IOAPIC: vector 0x30 value 0x00000000 0x00010000 IOAPIC: vector 0x31 value 0x00000000 0x00010000 IOAPIC: vector 0x32 value 0x00000000 0x00010000 IOAPIC: vector 0x33 value 0x00000000 0x00010000 IOAPIC: vector 0x34 value 0x00000000 0x00010000 IOAPIC: vector 0x35 value 0x00000000 0x00010000 IOAPIC: vector 0x36 value 0x00000000 0x00010000 IOAPIC: vector 0x37 value 0x00000000 0x00010000 IOAPIC: vector 0x38 value 0x00000000 0x00010000 IOAPIC: vector 0x39 value 0x00000000 0x00010000 IOAPIC: vector 0x3a value 0x00000000 0x00010000 IOAPIC: vector 0x3b value 0x00000000 0x00010000 IOAPIC: vector 0x3c value 0x00000000 0x00010000 IOAPIC: vector 0x3d value 0x00000000 0x00010000 IOAPIC: vector 0x3e value 0x00000000 0x00010000 IOAPIC: vector 0x3f value 0x00000000 0x00010000 IOAPIC: vector 0x40 value 0x00000000 0x00010000 IOAPIC: vector 0x41 value 0x00000000 0x00010000 IOAPIC: vector 0x42 value 0x00000000 0x00010000 IOAPIC: vector 0x43 value 0x00000000 0x00010000 IOAPIC: vector 0x44 value 0x00000000 0x00010000 IOAPIC: vector 0x45 value 0x00000000 0x00010000 IOAPIC: vector 0x46 value 0x00000000 0x00010000 IOAPIC: vector 0x47 value 0x00000000 0x00010000 IOAPIC: vector 0x48 value 0x00000000 0x00010000 IOAPIC: vector 0x49 value 0x00000000 0x00010000 IOAPIC: vector 0x4a value 0x00000000 0x00010000 IOAPIC: vector 0x4b value 0x00000000 0x00010000 IOAPIC: vector 0x4c value 0x00000000 0x00010000 IOAPIC: vector 0x4d value 0x00000000 0x00010000 IOAPIC: vector 0x4e value 0x00000000 0x00010000 IOAPIC: vector 0x4f value 0x00000000 0x00010000 IOAPIC: vector 0x50 value 0x00000000 0x00010000 IOAPIC: vector 0x51 value 0x00000000 0x00010000 IOAPIC: vector 0x52 value 0x00000000 0x00010000 IOAPIC: vector 0x53 value 0x00000000 0x00010000 IOAPIC: vector 0x54 value 0x00000000 0x00010000 IOAPIC: vector 0x55 value 0x00000000 0x00010000 IOAPIC: vector 0x56 value 0x00000000 0x00010000 IOAPIC: vector 0x57 value 0x00000000 0x00010000 IOAPIC: vector 0x58 value 0x00000000 0x00010000 IOAPIC: vector 0x59 value 0x00000000 0x00010000 IOAPIC: vector 0x5a value 0x00000000 0x00010000 IOAPIC: vector 0x5b value 0x00000000 0x00010000 IOAPIC: vector 0x5c value 0x00000000 0x00010000 IOAPIC: vector 0x5d value 0x00000000 0x00010000 IOAPIC: vector 0x5e value 0x00000000 0x00010000 IOAPIC: vector 0x5f value 0x00000000 0x00010000 IOAPIC: vector 0x60 value 0x00000000 0x00010000 IOAPIC: vector 0x61 value 0x00000000 0x00010000 IOAPIC: vector 0x62 value 0x00000000 0x00010000 IOAPIC: vector 0x63 value 0x00000000 0x00010000 IOAPIC: vector 0x64 value 0x00000000 0x00010000 IOAPIC: vector 0x65 value 0x00000000 0x00010000 IOAPIC: vector 0x66 value 0x00000000 0x00010000 IOAPIC: vector 0x67 value 0x00000000 0x00010000 IOAPIC: vector 0x68 value 0x00000000 0x00010000 IOAPIC: vector 0x69 value 0x00000000 0x00010000 IOAPIC: vector 0x6a value 0x00000000 0x00010000 IOAPIC: vector 0x6b value 0x00000000 0x00010000 IOAPIC: vector 0x6c value 0x00000000 0x00010000 IOAPIC: vector 0x6d value 0x00000000 0x00010000 IOAPIC: vector 0x6e value 0x00000000 0x00010000 IOAPIC: vector 0x6f value 0x00000000 0x00010000 IOAPIC: vector 0x70 value 0x00000000 0x00010000 IOAPIC: vector 0x71 value 0x00000000 0x00010000 IOAPIC: vector 0x72 value 0x00000000 0x00010000 IOAPIC: vector 0x73 value 0x00000000 0x00010000 IOAPIC: vector 0x74 value 0x00000000 0x00010000 IOAPIC: vector 0x75 value 0x00000000 0x00010000 IOAPIC: vector 0x76 value 0x00000000 0x00010000 IOAPIC: vector 0x77 value 0x00000000 0x00010000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: vector 0x00 value 0x00000000 0x00000700 PCI: 00:1f.0 init finished in 607 msecs PCI: 00:1f.2 init apm_control: Disabling ACPI. APMC done. PCI: 00:1f.2 init finished in 6 msecs PCI: 00:1f.3 init PCI: 00:1f.3 init finished in 0 msecs PCI: 01:00.0 init PCI: 01:00.0 init finished in 0 msecs PNP: 0c09.0 init Google Chrome EC uptime: 12.138 seconds Google Chrome AP resets since EC boot: 1 Google Chrome most recent AP reset causes: 0.342: 32775 shutdown: entering G3 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump PNP: 0c09.0 init finished in 23 msecs GENERIC: 0.0 init GENERIC: 0.0 init finished in 0 msecs GENERIC: 1.0 init GENERIC: 1.0 init finished in 0 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 GPIO: 0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 0 PCI: 00:01.1: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:06.2: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:07.1: enabled 0 PCI: 00:07.2: enabled 0 PCI: 00:07.3: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0d.1: enabled 0 PCI: 00:0d.2: enabled 0 PCI: 00:0d.3: enabled 0 PCI: 00:0e.0: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:10.1: enabled 0 PCI: 00:10.6: enabled 0 PCI: 00:10.7: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:12.7: enabled 0 PCI: 00:13.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 0 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 0 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 0 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 0 PCI: 00:1d.1: enabled 0 PCI: 00:1d.2: enabled 0 PCI: 00:1d.3: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 0 PCI: 00:1e.3: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 00:1f.7: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 USB0 port 0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:31: enabled 1 I2C: 00:32: enabled 1 I2C: 00:50: enabled 1 I2C: 00:10: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 GENERIC: 0.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 1 USB3 port 3: enabled 0 USB2 port 0: enabled 1 USB2 port 1: enabled 0 USB2 port 2: enabled 1 USB2 port 3: enabled 0 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 0 USB2 port 8: enabled 1 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 0 USB3 port 2: enabled 0 USB3 port 3: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 APIC: 00: enabled 1 APIC: 16: enabled 1 APIC: 10: enabled 1 APIC: 12: enabled 1 APIC: 14: enabled 1 APIC: 09: enabled 1 APIC: 01: enabled 1 APIC: 08: enabled 1 PCI: 01:00.0: enabled 1 BS: BS_DEV_INIT run times (exec / console): 11 / 1133 ms FMAP: area RW_ELOG found @ f20000 (16384 bytes) ELOG: NV offset 0xf20000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-03-02 02:18:50 UTC ELOG: Event(9E) added with size 10 at 2024-03-02 02:18:50 UTC ELOG: Event(9F) added with size 14 at 2024-03-02 02:18:50 UTC BS: BS_DEV_INIT exit times (exec / console): 3 / 33 ms ELOG: Event(A0) added with size 9 at 2024-03-02 02:18:50 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 1 / 10 ms Finalize devices... PCI: 00:16.0 final PCI: 00:1f.2 final GENERIC: 0.0 final added type-c port0 info to cbmem: usb2:1 usb3:1 sbu:0 data:0 GENERIC: 1.0 final added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 24 ms FMAP: area RW_NVRAM found @ f2b000 (24576 bytes) BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms ME: HFSTS1 : 0x90000245 ME: HFSTS2 : 0x82100116 ME: HFSTS3 : 0x00000050 ME: HFSTS4 : 0x00004000 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x40600006 ME: Manufacturing Mode : NO ME: SPI Protection Mode Enabled : YES ME: FPFs Committed : YES ME: Manufacturing Vars Locked : YES ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : YES ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 0 ME: Error Code : 0 ME: Enhanced Debug Mode : NO ME: CPU Debug Disabled : YES ME: TXT Support : NO ME: WP for RO is enabled : YES ME: RO write protection scope - Start=0x1000, End=0x15AFFF BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 111 ms Ramoops buffer: 0x100000@0x76899000. BS: BS_WRITE_TABLES entry times (exec / console): 0 / 4 ms CBFS: Found 'fallback/dsdt.aml' @0x787c0 size 0x4fd1 in mcache @0x76add18c CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7686d000. ACPI: * FACS ACPI: * DSDT PCI space above 4GB MMIO is at 0x27fc00000, len = 0x7d80400000 ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 6/8 physical/logical core(s) each. \_SB.PCI0.PEPD: Intel Power Engine Plug-in \_SB.PCI0.PMC: Intel Alderlake at PCI: 00:1f.2 \_SB.DPTF: Intel DPTF at GENERIC: 0.0 CBFS: Found 'wifi_sar_0.hex' @0x1bbd00 size 0xe6 in mcache @0x76add3e4 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0 \_SB.PCI0.I2C0.NAU8: Nuvoton NAU8825 Codec address 01ah irq 0 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h \_SB.PCI0.I2C1.TPMI: I2C TPM at I2C: 00:50 \_SB.PCI0.I2C3.H010: ELAN Touchscreen at I2C: 00:10 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15 \_SB.PCI0.I2C5.H02C: Synaptics Touchpad at I2C: 00:2c \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ] PS2K: Passing 80 keymaps to kernel \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0 \_SB.PCI0.TXHC.RHUB.SS03: USB3 Type-C Port C1 (DB) at USB3 port 2 \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-C Port C0 (MLB) at USB2 port 0 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2 \_SB.PCI0.XHCI.RHUB.HS06: USB2 Camera at USB2 port 5 \_SB.PCI0.XHCI.RHUB.HS09: USB2 Type-A Port A0 (DB) at USB2 port 8 \_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9 \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Port A0 (DB) at USB3 port 0 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0x7685d000 ACPI: added table 4/32, length now 52 ACPI: * LPIT ACPI: added table 5/32, length now 56 ACPI: * MADT SCI is IRQ9 ACPI: added table 6/32, length now 60 cmd_reg from pmc_make_ipc_cmd 1052838 CL PMC desc table: numb of regions is 0x2 at addr 0xfe0121bc CL PMC desc table: region 0x0 has size 0x280 at offset 0x2200 CL PMC desc table: region 0x1 has size 0x80 at offset 0x3e00 PMC CrashLog size in discovery mode: 0xC00 cpu crashlog bar addr: 0x80640000 cpu discovery table offset: 0x6030 cpu_crashlog_discovery_table buffer count: 0x3 cpu_crashlog_discovery_table buffer: 0x0 size: 0x700 offset: 0x0 cpu_crashlog_discovery_table buffer: 0x1 size: 0x2b0 offset: 0x4000 cpu_crashlog_discovery_table buffer: 0x2 size: 0x370 offset: 0x5000 PMC crashLog size in discovery mode : 0xC00 Invalid data 0x0 at offset 0x2200 from addr 0xfe010000 of PMC SRAM. discover mode PMC crashlog size adjusted to: 0x200 Invalid data 0x0 at offset 0x3e00 from addr 0xfe010000 of PMC SRAM. discover mode PMC crashlog size adjusted to: 0x0 m_cpu_crashLog_size : 0x3480 bytes CPU crashLog present. CPU crash data size: 0x3480 bytes in 0x3 region(s). Invalid data 0x0 at offset 0x0 from addr 0x80640000 of telemetry SRAM. current = 76876550 ACPI: * DMAR ACPI: added table 7/32, length now 64 ACPI: added table 8/32, length now 68 ACPI: * HPET ACPI: added table 9/32, length now 72 ACPI: done. ACPI tables: 38528 bytes. smbios_write_tables: 76857000 EC returned error result code 3 Couldn't obtain OEM name from CBI Create SMBIOS type 16 Create SMBIOS type 17 Create SMBIOS type 20 GENERIC: 0.0 (WIFI Device) SMBIOS tables: 2156 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7955 Writing coreboot table at 0x76891000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000076856fff: RAM 4. 0000000076857000-0000000076a2efff: CONFIGURATION TABLES 5. 0000000076a2f000-0000000076ab7fff: RAMSTAGE 6. 0000000076ab8000-0000000076ffffff: CONFIGURATION TABLES 7. 0000000077000000-00000000803fffff: RESERVED 8. 00000000c0000000-00000000cfffffff: RESERVED 9. 00000000f8000000-00000000f9ffffff: RESERVED 10. 00000000fb000000-00000000fb000fff: RESERVED 11. 00000000fc800000-00000000fe7fffff: RESERVED 12. 00000000feb00000-00000000feb7ffff: RESERVED 13. 00000000fec00000-00000000fecfffff: RESERVED 14. 00000000fed40000-00000000fed6ffff: RESERVED 15. 00000000fed80000-00000000fed87fff: RESERVED 16. 00000000fed90000-00000000fed92fff: RESERVED 17. 00000000feda0000-00000000feda1fff: RESERVED 18. 00000000fedc0000-00000000feddffff: RESERVED 19. 0000000100000000-000000027fbfffff: RAM Passing 4 GPIOs to payload: NAME | PORT | POLARITY | VALUE lid | undefined | high | high power | undefined | high | low oprom | undefined | high | low EC in RW | 0x00000151 | high | high Board ID: 3 FW config: 0x131 Wrote coreboot table at: 0x76891000, 0x6e4 bytes, checksum 73b7 coreboot table: 1788 bytes. IMD ROOT 0. 0x76fff000 0x00001000 IMD SMALL 1. 0x76ffe000 0x00001000 FSP MEMORY 2. 0x76afe000 0x00500000 CONSOLE 3. 0x76ade000 0x00020000 RW MCACHE 4. 0x76add000 0x0000043c RO MCACHE 5. 0x76adc000 0x00000fd8 FMAP 6. 0x76adb000 0x0000064a TIME STAMP 7. 0x76ada000 0x00000910 VBOOT WORK 8. 0x76ac6000 0x00014000 MEM INFO 9. 0x76ac5000 0x000003b8 ROMSTG STCK10. 0x76ac4000 0x00001000 AFTER CAR 11. 0x76ab8000 0x0000c000 RAMSTAGE 12. 0x76a2e000 0x0008a000 ACPI BERT 13. 0x76a1e000 0x00010000 CHROMEOS NVS14. 0x76a1d000 0x00000f00 REFCODE 15. 0x769ae000 0x0006f000 SMM BACKUP 16. 0x7699e000 0x00010000 IGD OPREGION17. 0x76999000 0x00004203 RAMOOPS 18. 0x76899000 0x00100000 COREBOOT 19. 0x76891000 0x00008000 ACPI 20. 0x7686d000 0x00024000 TPM2 TCGLOG21. 0x7685d000 0x00010000 PMC CRASHLOG22. 0x7685c000 0x00000c00 CPU CRASHLOG23. 0x76858000 0x00003480 SMBIOS 24. 0x76857000 0x00001000 IMD small region: IMD ROOT 0. 0x76ffec00 0x00000400 FSP RUNTIME 1. 0x76ffebe0 0x00000004 VPD 2. 0x76ffeb80 0x0000004c POWER STATE 3. 0x76ffeb20 0x00000044 ROMSTAGE 4. 0x76ffeb00 0x00000004 ACPI GNVS 5. 0x76ffeaa0 0x00000048 TYPE_C INFO 6. 0x76ffea80 0x0000000c BS: BS_WRITE_TABLES run times (exec / console): 8 / 628 ms MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6 0x0000000077000000 - 0x0000000090000000 size 0x19000000 type 0 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0 0x0000000100000000 - 0x000000027fc00000 size 0x17fc00000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 CPU physical address size: 39 bits MTRR: Fixed MSR 0x258 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 CPU physical address size: 39 bits MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x250 0x0606060606060606 CPU physical address size: 39 bits MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 call enable_fixed_mtrr() MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled BS: BS_WRITE_TABLES exit times (exec / console): 252 / 150 ms Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 18 / 6 ms CBFS: Found 'fallback/payload' @0x1bbe40 size 0x25902 in mcache @0x76add40c Checking segment from ROM address 0xf96cbe6c Checking segment from ROM address 0xf96cbe88 Loading segment from ROM address 0xf96cbe6c code (compression=1) New segment dstaddr 0x30000000 memsize 0x2668e60 srcaddr 0xf96cbea4 filesize 0x258ca Loading Segment: addr: 0x30000000 memsz: 0x0000000002668e60 filesz: 0x00000000000258ca using LZMA [ 0x30000000, 30051214, 0x32668e60) <- f96cbea4 Clearing Segment: addr: 0x0000000030051214 memsz: 0x0000000002617c4c Loading segment from ROM address 0xf96cbe88 Entry Point 0x30000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 21 / 62 ms BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: CSE device 16.1 is disabled HECI: CSE device 16.2 is disabled HECI: CSE device 16.3 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot BS: BS_PAYLOAD_BOOT entry times (exec / console): 4 / 34 ms mp_park_aps done after 0 msecs. Jumping to boot code at 0x30000000(0x76891000) CPU0: stack: 0x76a99000 - 0x76a9a000, lowest used address 0x76a993dc, stack used: 3108 bytes Starting depthcharge on Volmar... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! Looking for NVMe Controller 0x300653d8 @ 00:06:00 configure_storage: Failed to remap 1C:2 Wipe memory regions: [0x00000000001000, 0x000000000a0000) [0x00000000100000, 0x00000030000000) [0x00000032668e60, 0x00000076857000) [0x00000100000000, 0x0000027fc00000) ec_init: CrosEC protocol v3 supported (256, 256) R8152: Initializing Version 6 (ocp_data = 5c30) R8152: Done initializing Adding net device [firmware-brya-14505.B-collabora] Feb 7 2023 16:06:26 brya: tftpboot 192.168.201.1 12912104/tftp-deploy-r0i7qzms/kernel/bzImage 12912104/tftp-deploy-r0i7qzms/kernel/cmdline 12912104/tftp-deploy-r0i7qzms/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 12912104/tftp-deploy-r0i7qzms/kernel/bzIploy-r0i7qzms/kernel/cmdline 12912104/tftp-deploy-r0i7qzms/ramdisk/ramdisk.cpio.gz Waiting for link done. MAC: 00:13:3b:00:0f:d5 Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.23 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 12912104/tftp-deploy-r0i7qzms/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ##################################### done. The bootfile was 12357632 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################ done. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 12912104/tftp-deploy-r0i7qzms/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12912104/extract-nfsrootfs-vgshw2tc,tcp,hard ip=dhcp tftpserverip=192.168.201.1 Shutting down all USB controllers. Removing current net device Finalizing coreboot Exiting depthcharge with code 4 at timestamp: 36284567 Starting kernel ...