Boot log: hip07-d05
- Kernel Warnings: 0
- Warnings: 4
- Kernel Errors: 0
- Boot result: PASS
- Errors: 1
1 01:18:23.962010 Action timeout for pdu-reboot exceeds Job timeout
2 01:18:24.101748 lava-dispatcher, installed at version: 2022.11
3 01:18:24.102073 start: 0 validate
4 01:18:24.102548 Start time: 2022-12-10 01:18:24.102522+00:00 (UTC)
5 01:18:24.102971 Using caching service: 'http://localhost/cache/?uri=%s'
6 01:18:24.103395 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20221202.0%2Farm64%2Finitrd.cpio.gz exists
7 01:18:24.398498 Using caching service: 'http://localhost/cache/?uri=%s'
8 01:18:24.398959 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.268-cip87%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
9 01:18:24.689742 Using caching service: 'http://localhost/cache/?uri=%s'
10 01:18:24.690169 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.268-cip87%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fhisilicon%2Fhip07-d05.dtb exists
11 01:18:24.979230 Using caching service: 'http://localhost/cache/?uri=%s'
12 01:18:24.979594 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20221202.0%2Farm64%2Ffull.rootfs.tar.xz exists
13 01:18:25.274983 Using caching service: 'http://localhost/cache/?uri=%s'
14 01:18:25.275373 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.268-cip87%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
15 01:18:25.559796 validate duration: 1.46
17 01:18:25.560678 start: 1 tftp-deploy (timeout 00:10:00) [common]
18 01:18:25.561035 start: 1.1 download-retry (timeout 00:10:00) [common]
19 01:18:25.561351 start: 1.1.1 http-download (timeout 00:10:00) [common]
20 01:18:25.561698 Not decompressing ramdisk as can be used compressed.
21 01:18:25.561989 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20221202.0/arm64/initrd.cpio.gz
22 01:18:25.562221 saving as /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/ramdisk/initrd.cpio.gz
23 01:18:25.562486 total size: 4662407 (4MB)
24 01:18:25.566166 progress 0% (0MB)
25 01:18:25.570652 progress 5% (0MB)
26 01:18:25.574277 progress 10% (0MB)
27 01:18:25.577973 progress 15% (0MB)
28 01:18:25.581597 progress 20% (0MB)
29 01:18:25.585278 progress 25% (1MB)
30 01:18:25.588902 progress 30% (1MB)
31 01:18:25.592664 progress 35% (1MB)
32 01:18:25.596138 progress 40% (1MB)
33 01:18:25.600149 progress 45% (2MB)
34 01:18:25.603673 progress 50% (2MB)
35 01:18:25.607267 progress 55% (2MB)
36 01:18:25.610841 progress 60% (2MB)
37 01:18:25.614328 progress 65% (2MB)
38 01:18:25.617866 progress 70% (3MB)
39 01:18:25.621375 progress 75% (3MB)
40 01:18:25.625015 progress 80% (3MB)
41 01:18:25.628449 progress 85% (3MB)
42 01:18:25.632424 progress 90% (4MB)
43 01:18:25.635876 progress 95% (4MB)
44 01:18:25.639485 progress 100% (4MB)
45 01:18:25.640044 4MB downloaded in 0.08s (57.34MB/s)
46 01:18:25.640557 end: 1.1.1 http-download (duration 00:00:00) [common]
48 01:18:25.641257 end: 1.1 download-retry (duration 00:00:00) [common]
49 01:18:25.641523 start: 1.2 download-retry (timeout 00:10:00) [common]
50 01:18:25.641860 start: 1.2.1 http-download (timeout 00:10:00) [common]
51 01:18:25.642223 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.268-cip87/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
52 01:18:25.642424 saving as /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/kernel/Image
53 01:18:25.642619 total size: 19241472 (18MB)
54 01:18:25.642811 No compression specified
55 01:18:25.646013 progress 0% (0MB)
56 01:18:25.660365 progress 5% (0MB)
57 01:18:25.674446 progress 10% (1MB)
58 01:18:25.688763 progress 15% (2MB)
59 01:18:25.702569 progress 20% (3MB)
60 01:18:25.716618 progress 25% (4MB)
61 01:18:25.731124 progress 30% (5MB)
62 01:18:25.745198 progress 35% (6MB)
63 01:18:25.759220 progress 40% (7MB)
64 01:18:25.773677 progress 45% (8MB)
65 01:18:25.787877 progress 50% (9MB)
66 01:18:25.801777 progress 55% (10MB)
67 01:18:25.816077 progress 60% (11MB)
68 01:18:25.829986 progress 65% (11MB)
69 01:18:25.844404 progress 70% (12MB)
70 01:18:25.858359 progress 75% (13MB)
71 01:18:25.872000 progress 80% (14MB)
72 01:18:25.886102 progress 85% (15MB)
73 01:18:25.899863 progress 90% (16MB)
74 01:18:25.913398 progress 95% (17MB)
75 01:18:25.927419 progress 100% (18MB)
76 01:18:25.927971 18MB downloaded in 0.29s (64.31MB/s)
77 01:18:25.928443 end: 1.2.1 http-download (duration 00:00:00) [common]
79 01:18:25.929183 end: 1.2 download-retry (duration 00:00:00) [common]
80 01:18:25.929452 start: 1.3 download-retry (timeout 00:10:00) [common]
81 01:18:25.929795 start: 1.3.1 http-download (timeout 00:10:00) [common]
82 01:18:25.930168 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.268-cip87/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/hisilicon/hip07-d05.dtb
83 01:18:25.930372 saving as /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/dtb/hip07-d05.dtb
84 01:18:25.930568 total size: 34901 (0MB)
85 01:18:25.930762 No compression specified
86 01:18:25.933961 progress 93% (0MB)
87 01:18:25.934667 progress 100% (0MB)
88 01:18:25.935074 0MB downloaded in 0.00s (7.40MB/s)
89 01:18:25.935500 end: 1.3.1 http-download (duration 00:00:00) [common]
91 01:18:25.936166 end: 1.3 download-retry (duration 00:00:00) [common]
92 01:18:25.936427 start: 1.4 download-retry (timeout 00:10:00) [common]
93 01:18:25.936851 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 01:18:25.937191 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20221202.0/arm64/full.rootfs.tar.xz
95 01:18:25.937391 saving as /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/nfsrootfs/full.rootfs.tar
96 01:18:25.937588 total size: 125150616 (119MB)
97 01:18:25.937782 Using unxz to decompress xz
98 01:18:25.946164 progress 0% (0MB)
99 01:18:26.618205 progress 5% (5MB)
100 01:18:27.228373 progress 10% (11MB)
101 01:18:27.902987 progress 15% (17MB)
102 01:18:28.286627 progress 20% (23MB)
103 01:18:28.625045 progress 25% (29MB)
104 01:18:29.319059 progress 30% (35MB)
105 01:18:30.025851 progress 35% (41MB)
106 01:18:30.812542 progress 40% (47MB)
107 01:18:31.581466 progress 45% (53MB)
108 01:18:32.413662 progress 50% (59MB)
109 01:18:33.121612 progress 55% (65MB)
110 01:18:33.862259 progress 60% (71MB)
111 01:18:34.541867 progress 65% (77MB)
112 01:18:35.277253 progress 70% (83MB)
113 01:18:36.051688 progress 75% (89MB)
114 01:18:36.884971 progress 80% (95MB)
115 01:18:37.735849 progress 85% (101MB)
116 01:18:38.250166 progress 90% (107MB)
117 01:18:38.978235 progress 95% (113MB)
118 01:18:39.749904 progress 100% (119MB)
119 01:18:39.760288 119MB downloaded in 13.82s (8.63MB/s)
120 01:18:39.761224 end: 1.4.1 http-download (duration 00:00:14) [common]
122 01:18:39.762281 end: 1.4 download-retry (duration 00:00:14) [common]
123 01:18:39.762706 start: 1.5 download-retry (timeout 00:09:46) [common]
124 01:18:39.763037 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 01:18:39.763660 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.268-cip87/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
126 01:18:39.763916 saving as /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/modules/modules.tar
127 01:18:39.764166 total size: 4659496 (4MB)
128 01:18:39.764463 Using unxz to decompress xz
129 01:18:40.067012 progress 0% (0MB)
130 01:18:40.093651 progress 5% (0MB)
131 01:18:40.116770 progress 10% (0MB)
132 01:18:40.146000 progress 15% (0MB)
133 01:18:40.173573 progress 20% (0MB)
134 01:18:40.202722 progress 25% (1MB)
135 01:18:40.233987 progress 30% (1MB)
136 01:18:40.264290 progress 35% (1MB)
137 01:18:40.292569 progress 40% (1MB)
138 01:18:40.319053 progress 45% (2MB)
139 01:18:40.350571 progress 50% (2MB)
140 01:18:40.377855 progress 55% (2MB)
141 01:18:40.405641 progress 60% (2MB)
142 01:18:40.430709 progress 65% (2MB)
143 01:18:40.457585 progress 70% (3MB)
144 01:18:40.489648 progress 75% (3MB)
145 01:18:40.516609 progress 80% (3MB)
146 01:18:40.543643 progress 85% (3MB)
147 01:18:40.569526 progress 90% (4MB)
148 01:18:40.599774 progress 95% (4MB)
149 01:18:40.625825 progress 100% (4MB)
150 01:18:40.636178 4MB downloaded in 0.87s (5.10MB/s)
151 01:18:40.637125 end: 1.5.1 http-download (duration 00:00:01) [common]
153 01:18:40.638147 end: 1.5 download-retry (duration 00:00:01) [common]
154 01:18:40.638567 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 01:18:40.638954 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 01:18:50.665712 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n
157 01:18:50.666258 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
158 01:18:50.666544 start: 1.6.2 lava-overlay (timeout 00:09:35) [common]
159 01:18:50.667045 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw
160 01:18:50.667411 makedir: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin
161 01:18:50.667700 makedir: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/tests
162 01:18:50.667988 makedir: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/results
163 01:18:50.668301 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-add-keys
164 01:18:50.668787 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-add-sources
165 01:18:50.669216 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-background-process-start
166 01:18:50.669620 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-background-process-stop
167 01:18:50.670019 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-common-functions
168 01:18:50.670417 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-echo-ipv4
169 01:18:50.670815 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-install-packages
170 01:18:50.671212 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-installed-packages
171 01:18:50.671606 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-os-build
172 01:18:50.672020 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-probe-channel
173 01:18:50.672427 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-probe-ip
174 01:18:50.672943 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-target-ip
175 01:18:50.673341 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-target-mac
176 01:18:50.673737 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-target-storage
177 01:18:50.674143 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-case
178 01:18:50.674541 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-event
179 01:18:50.674936 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-feedback
180 01:18:50.675347 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-raise
181 01:18:50.675741 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-reference
182 01:18:50.676136 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-runner
183 01:18:50.676557 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-set
184 01:18:50.676971 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-test-shell
185 01:18:50.677372 Updating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-install-packages (oe)
186 01:18:50.677789 Updating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/bin/lava-installed-packages (oe)
187 01:18:50.678137 Creating /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/environment
188 01:18:50.678424 LAVA metadata
189 01:18:50.678632 - LAVA_JOB_ID=8315107
190 01:18:50.678826 - LAVA_DISPATCHER_IP=192.168.101.1
191 01:18:50.679168 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:35) [common]
192 01:18:50.679358 skipped lava-vland-overlay
193 01:18:50.679601 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
194 01:18:50.679860 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:35) [common]
195 01:18:50.680053 skipped lava-multinode-overlay
196 01:18:50.680289 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
197 01:18:50.680668 start: 1.6.2.3 test-definition (timeout 00:09:35) [common]
198 01:18:50.680913 Loading test definitions
199 01:18:50.681206 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:35) [common]
200 01:18:50.681420 Using /lava-8315107 at stage 0
201 01:18:50.682388 uuid=8315107_1.6.2.3.1 testdef=None
202 01:18:50.682641 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
203 01:18:50.682892 start: 1.6.2.3.2 test-overlay (timeout 00:09:35) [common]
204 01:18:50.684424 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
206 01:18:50.685119 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:35) [common]
207 01:18:50.686932 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
209 01:18:50.687585 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:35) [common]
210 01:18:50.689336 runner path: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/0/tests/0_dmesg test_uuid 8315107_1.6.2.3.1
211 01:18:50.689820 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
213 01:18:50.690459 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:35) [common]
214 01:18:50.690660 Using /lava-8315107 at stage 1
215 01:18:50.691547 uuid=8315107_1.6.2.3.5 testdef=None
216 01:18:50.691801 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
217 01:18:50.692052 start: 1.6.2.3.6 test-overlay (timeout 00:09:35) [common]
218 01:18:50.693494 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
220 01:18:50.694113 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:35) [common]
221 01:18:50.695932 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
223 01:18:50.696606 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:35) [common]
224 01:18:50.698365 runner path: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/1/tests/1_bootrr test_uuid 8315107_1.6.2.3.5
225 01:18:50.698818 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
227 01:18:50.699393 Creating lava-test-runner.conf files
228 01:18:50.699575 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/0 for stage 0
229 01:18:50.699840 - 0_dmesg
230 01:18:50.700078 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8315107/lava-overlay-263fqdlw/lava-8315107/1 for stage 1
231 01:18:50.700344 - 1_bootrr
232 01:18:50.700658 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
233 01:18:50.700926 start: 1.6.2.4 compress-overlay (timeout 00:09:35) [common]
234 01:18:50.728019 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
235 01:18:50.728316 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
236 01:18:50.728685 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
237 01:18:50.728972 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
238 01:18:50.729253 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
239 01:18:51.036280 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
240 01:18:51.037645 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
241 01:18:51.037982 extracting modules file /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n
242 01:18:51.574523 extracting modules file /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8315107/extract-overlay-ramdisk-p9azt7cg/ramdisk
243 01:18:52.208969 end: 1.6.4 extract-modules (duration 00:00:01) [common]
244 01:18:52.209400 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
245 01:18:52.209654 [common] Applying overlay to NFS
246 01:18:52.209885 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8315107/compress-overlay-v46f5ejj/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n
247 01:18:52.237406 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
248 01:18:52.237758 start: 1.6.6 prepare-kernel (timeout 00:09:33) [common]
249 01:18:52.238054 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
250 01:18:52.238339 start: 1.6.7 configure-preseed-file (timeout 00:09:33) [common]
251 01:18:52.238607 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
252 01:18:52.238890 start: 1.6.8 compress-ramdisk (timeout 00:09:33) [common]
253 01:18:52.239125 Building ramdisk /var/lib/lava/dispatcher/tmp/8315107/extract-overlay-ramdisk-p9azt7cg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8315107/extract-overlay-ramdisk-p9azt7cg/ramdisk
254 01:18:52.724846 >> 67832 blocks
255 01:18:54.875724 rename /var/lib/lava/dispatcher/tmp/8315107/extract-overlay-ramdisk-p9azt7cg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8315107/tftp-deploy-6iwhbpo5/ramdisk/ramdisk.cpio.gz
256 01:18:54.877193 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
257 01:18:54.877644 end: 1.6 prepare-tftp-overlay (duration 00:00:14) [common]
258 01:18:54.878081 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
259 01:18:54.878421 No LXC device requested
260 01:18:54.878815 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
261 01:18:54.879205 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
262 01:18:54.879590 end: 1.8 deploy-device-env (duration 00:00:00) [common]
263 01:18:54.879954 Checking files for TFTP limit of 4294967296 bytes.
264 01:18:54.882185 end: 1 tftp-deploy (duration 00:00:29) [common]
265 01:18:54.882629 start: 2 grub-main-action (timeout 00:05:00) [common]
266 01:18:54.883111 start: 2.1 bootloader-from-media (timeout 00:05:00) [common]
267 01:18:54.883504 end: 2.1 bootloader-from-media (duration 00:00:00) [common]
268 01:18:54.883941 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
269 01:18:54.884497 substitutions:
270 01:18:54.884757 - {DTB}: 8315107/tftp-deploy-6iwhbpo5/dtb/hip07-d05.dtb
271 01:18:54.884984 - {INITRD}: 8315107/tftp-deploy-6iwhbpo5/ramdisk/ramdisk.cpio.gz
272 01:18:54.885180 - {KERNEL}: 8315107/tftp-deploy-6iwhbpo5/kernel/Image
273 01:18:54.885487 - {LAVA_MAC}: None
274 01:18:54.885786 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n
275 01:18:54.886063 - {NFS_SERVER_IP}: 192.168.101.1
276 01:18:54.886354 - {PRESEED_CONFIG}: None
277 01:18:54.886576 - {PRESEED_LOCAL}: None
278 01:18:54.886827 - {RAMDISK}: 8315107/tftp-deploy-6iwhbpo5/ramdisk/ramdisk.cpio.gz
279 01:18:54.887026 - {ROOT_PART}: None
280 01:18:54.887211 - {ROOT}: None
281 01:18:54.887394 - {SERVER_IP}: 192.168.101.1
282 01:18:54.887591 - {TEE}: None
283 01:18:54.887787 Parsed boot commands:
284 01:18:54.887965 - linux (tftp,192.168.101.1)/8315107/tftp-deploy-6iwhbpo5/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n,tcp,hard,vers=3 ip=:::::eth0:dhcp
285 01:18:54.888199 - devicetree (tftp,192.168.101.1)/8315107/tftp-deploy-6iwhbpo5/dtb/hip07-d05.dtb
286 01:18:54.888472 - boot
287 01:18:54.888775 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
288 01:18:54.889127 start: 2.3 connect-device (timeout 00:05:00) [common]
289 01:18:54.889357 [common] connect-device Connecting to device using '/usr/local/bin/d05-console.sh hip07-d05-cbg-0-bmc'
290 01:18:54.897359 Setting prompt string to ['lava-test: # ']
291 01:18:54.898212 end: 2.3 connect-device (duration 00:00:00) [common]
292 01:18:54.898548 start: 2.4 reset-device (timeout 00:05:00) [common]
293 01:18:54.898867 start: 2.4.1 pdu-reboot (timeout 00:05:00) [common]
294 01:18:54.899349 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'reset'
295 01:18:55.191925 >> Chassis Power Control: Down/Off
296 01:19:05.421989 >> Chassis Power Control: Up/On
297 01:19:15.426160 Returned 0 in 20 seconds
298 01:19:15.528214 end: 2.4.1 pdu-reboot (duration 00:00:21) [common]
300 01:19:15.529495 end: 2.4 reset-device (duration 00:00:21) [common]
301 01:19:15.530009 start: 2.5 bootloader-interrupt (timeout 00:04:39) [common]
302 01:19:15.530379 Setting prompt string to ['PCIE MEM CONFIG']
303 01:19:15.530721 bootloader-interrupt: Wait for prompt ['PCIE MEM CONFIG'] (timeout 00:05:00)
304 01:19:15.531780 Info: SOL payload already de-activated
305 01:19:15.532073 Never mind
306 01:19:15.532386 [SOL Session operational. Use ~? for help]
307 01:19:15.532729 [serdes_init]:SerDes0 init success!
308 01:19:15.533014 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G
309 01:19:17.310374 [serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
310 01:19:17.329100 [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms)
311 01:19:19.649431 [serdes_init]:SerDes1 init success!
312 01:19:19.721258 Continue to dreset PCS
313 01:19:19.721714 Continue to dreset HLLC
314 01:19:20.729159 Continue to open PCS RX
315 01:19:20.759089 Wait for HLLC Training........OK
316 01:19:20.759361 Wait for HLLC1 Training........OK
317 01:19:20.759620 Wait for S1 HLLC Training........OK
318 01:19:20.759849 Wait for S1 HLLC1 Training........OK
319 01:19:20.760070 Open Secondary socket Window
320 01:19:20.760287 Djtag secondary 0x4004001d818 and 0x400d000d818 init
321 01:19:21.739212 Macro 0 Download Firmware Success!!
322 01:19:22.719907 Macro 1 Download Firmware Success!!
323 01:19:23.690001 Macro 0 Download Firmware Success!!
324 01:19:28.489472 Release Macro 1 MCU!!
325 01:19:29.839538 Temperature: 27 (0x1B)
326 01:19:33.940504 GetVariable Not Found!
327 01:19:33.944799 Get Default Setup Configration
328 01:19:33.945198 &&&Now config iBMC BIOS WDT [action:0 countdown:3928 timeruse 2!
329 01:19:33.945555 Memory Init PEIM Loaded
330 01:19:33.959109 B I2C1 init ok.
331 01:19:33.959474
332 01:19:33.959772 socket[0] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54
333 01:19:33.960044 ---------------------------------------------------------------------
334 01:19:33.960299 SPD_KEY_BYTE : DDR4
335 01:19:33.971613 SPD_KEY_BYTE2 : RDIMM
336 01:19:33.972115 SPD_MODULE_ORG_DDR4 : 0x8
337 01:19:33.972644 SPD_MIN_TCK_DDR4 : 0x7
338 01:19:33.973051 SPD_MAX_TCK_DDR4 : 0xD
339 01:19:33.973380 SPD_FTB_MIN_TCK_DDR4 : 0xD6
340 01:19:33.989331 DimmMaxFreq : 2401Mbps
341 01:19:33.989753 pGblData->Channel[0][0].Dimm[0].DramWidth : X4
342 01:19:33.990084 pGblData->Channel[0][0].Dimm[0].RankNum : 2
343 01:19:33.990426 pGblData->Channel[0][0].Dimm[0].ddrFreq : 2400Mbps
344 01:19:33.990702 pGblData->Channel[0][0].Dimm[0].minTck : 8330
345 01:19:34.000222 ---------------------------------------------------------------------
346 01:19:34.000653
347 01:19:34.000959 socket[0] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
348 01:19:34.001313 ---------------------------------------------------------------------
349 01:19:34.019364 SPD_KEY_BYTE : Empty
350 01:19:34.019730 Socket[0] Channel[0] Dimm[1] is empty.
351 01:19:34.020108 ---------------------------------------------------------------------
352 01:19:34.020467 pGblData->Channel[0][0].RankPresent : 0x3
353 01:19:34.020977
354 01:19:34.021463
355 01:19:34.072033 socket[0] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
356 01:19:34.072446 ---------------------------------------------------------------------
357 01:19:34.072806 SPD_KEY_BYTE : DDR4
358 01:19:34.073085 SPD_KEY_BYTE2 : RDIMM
359 01:19:34.091472 SPD_MODULE_ORG_DDR4 : 0x8
360 01:19:34.091905 SPD_MIN_TCK_DDR4 : 0x7
361 01:19:34.092283 SPD_MAX_TCK_DDR4 : 0xD
362 01:19:34.092589 SPD_FTB_MIN_TCK_DDR4 : 0xD6
363 01:19:34.092955 DimmMaxFreq : 2401Mbps
364 01:19:34.109532 pGblData->Channel[0][1].Dimm[0].DramWidth : X4
365 01:19:34.109947 pGblData->Channel[0][1].Dimm[0].RankNum : 2
366 01:19:34.110327 pGblData->Channel[0][1].Dimm[0].ddrFreq : 2400Mbps
367 01:19:34.110653 pGblData->Channel[0][1].Dimm[0].minTck : 8330
368 01:19:34.121118 ---------------------------------------------------------------------
369 01:19:34.121702
370 01:19:34.122005 socket[0] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
371 01:19:34.122315 ---------------------------------------------------------------------
372 01:19:34.140365 SPD_KEY_BYTE : Empty
373 01:19:34.140738 Socket[0] Channel[1] Dimm[1] is empty.
374 01:19:34.141029 ---------------------------------------------------------------------
375 01:19:34.141363 pGblData->Channel[0][1].RankPresent : 0x3
376 01:19:34.141643
377 01:19:34.141994
378 01:19:34.159274 socket[0] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
379 01:19:34.159625 ---------------------------------------------------------------------
380 01:19:34.159919 SPD_KEY_BYTE : DDR4
381 01:19:34.160191 SPD_KEY_BYTE2 : RDIMM
382 01:19:34.169641 SPD_MODULE_ORG_DDR4 : 0x8
383 01:19:34.169933 SPD_MIN_TCK_DDR4 : 0x7
384 01:19:34.170260 SPD_MAX_TCK_DDR4 : 0xD
385 01:19:34.170554 SPD_FTB_MIN_TCK_DDR4 : 0xD6
386 01:19:34.170861 DimmMaxFreq : 2401Mbps
387 01:19:34.180126 pGblData->Channel[0][2].Dimm[0].DramWidth : X4
388 01:19:34.180409 pGblData->Channel[0][2].Dimm[0].RankNum : 2
389 01:19:34.180746 pGblData->Channel[0][2].Dimm[0].ddrFreq : 2400Mbps
390 01:19:34.181015 pGblData->Channel[0][2].Dimm[0].minTck : 8330
391 01:19:34.199354 ---------------------------------------------------------------------
392 01:19:34.199884
393 01:19:34.200176 socket[0] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
394 01:19:34.200530 ---------------------------------------------------------------------
395 01:19:34.211811 SPD_KEY_BYTE : Empty
396 01:19:34.212151 Socket[0] Channel[2] Dimm[1] is empty.
397 01:19:34.212417 ---------------------------------------------------------------------
398 01:19:34.212772 pGblData->Channel[0][2].RankPresent : 0x3
399 01:19:34.213093
400 01:19:34.213362
401 01:19:34.229220 socket[0] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
402 01:19:34.229565 ---------------------------------------------------------------------
403 01:19:34.229824 SPD_KEY_BYTE : DDR4
404 01:19:34.230092 SPD_KEY_BYTE2 : RDIMM
405 01:19:34.280708 SPD_MODULE_ORG_DDR4 : 0x8
406 01:19:34.281113 SPD_MIN_TCK_DDR4 : 0x7
407 01:19:34.281445 SPD_MAX_TCK_DDR4 : 0xD
408 01:19:34.281731 SPD_FTB_MIN_TCK_DDR4 : 0xD6
409 01:19:34.282038 DimmMaxFreq : 2401Mbps
410 01:19:34.299471 pGblData->Channel[0][3].Dimm[0].DramWidth : X4
411 01:19:34.300203 pGblData->Channel[0][3].Dimm[0].RankNum : 2
412 01:19:34.300496 pGblData->Channel[0][3].Dimm[0].ddrFreq : 2400Mbps
413 01:19:34.300843 pGblData->Channel[0][3].Dimm[0].minTck : 8330
414 01:19:34.311864 ---------------------------------------------------------------------
415 01:19:34.312229
416 01:19:34.312710 socket[0] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
417 01:19:34.313053 ---------------------------------------------------------------------
418 01:19:34.330829 SPD_KEY_BYTE : Empty
419 01:19:34.331134 Socket[0] Channel[3] Dimm[1] is empty.
420 01:19:34.331437 ---------------------------------------------------------------------
421 01:19:34.331744 pGblData->Channel[0][3].RankPresent : 0x3
422 01:19:34.332057
423 01:19:34.332340
424 01:19:34.349249 socket[1] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54
425 01:19:34.349568 ---------------------------------------------------------------------
426 01:19:34.350084 SPD_KEY_BYTE : DDR4
427 01:19:34.350373 SPD_KEY_BYTE2 : RDIMM
428 01:19:34.360181 SPD_MODULE_ORG_DDR4 : 0x8
429 01:19:34.360614 SPD_MIN_TCK_DDR4 : 0x7
430 01:19:34.360914 SPD_MAX_TCK_DDR4 : 0xD
431 01:19:34.361226 SPD_FTB_MIN_TCK_DDR4 : 0xD6
432 01:19:34.361500 DimmMaxFreq : 2401Mbps
433 01:19:34.379333 pGblData->Channel[1][0].Dimm[0].DramWidth : X4
434 01:19:34.379698 pGblData->Channel[1][0].Dimm[0].RankNum : 2
435 01:19:34.380024 pGblData->Channel[1][0].Dimm[0].ddrFreq : 2400Mbps
436 01:19:34.380351 pGblData->Channel[1][0].Dimm[0].minTck : 8330
437 01:19:34.389623 ---------------------------------------------------------------------
438 01:19:34.389922
439 01:19:34.390245 socket[1] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
440 01:19:34.390520 ---------------------------------------------------------------------
441 01:19:34.400714 SPD_KEY_BYTE : Empty
442 01:19:34.401074 Socket[1] Channel[0] Dimm[1] is empty.
443 01:19:34.401406 ---------------------------------------------------------------------
444 01:19:34.401690 pGblData->Channel[1][0].RankPresent : 0x3
445 01:19:34.402017
446 01:19:34.402786
447 01:19:34.419629 socket[1] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
448 01:19:34.419990 ---------------------------------------------------------------------
449 01:19:34.420326 SPD_KEY_BYTE : DDR4
450 01:19:34.420892 SPD_KEY_BYTE2 : RDIMM
451 01:19:34.431886 SPD_MODULE_ORG_DDR4 : 0x8
452 01:19:34.432184 SPD_MIN_TCK_DDR4 : 0x7
453 01:19:34.432505 SPD_MAX_TCK_DDR4 : 0xD
454 01:19:34.432803 SPD_FTB_MIN_TCK_DDR4 : 0xD6
455 01:19:34.433146 DimmMaxFreq : 2401Mbps
456 01:19:34.461045 pGblData->Channel[1][1].Dimm[0].DramWidth : X4
457 01:19:34.461346 pGblData->Channel[1][1].Dimm[0].RankNum : 2
458 01:19:34.461611 pGblData->Channel[1][1].Dimm[0].ddrFreq : 2400Mbps
459 01:19:34.462168 pGblData->Channel[1][1].Dimm[0].minTck : 8330
460 01:19:34.479422 ---------------------------------------------------------------------
461 01:19:34.479792
462 01:19:34.480122 socket[1] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
463 01:19:34.480466 ---------------------------------------------------------------------
464 01:19:34.489227 SPD_KEY_BYTE : Empty
465 01:19:34.489506 Socket[1] Channel[1] Dimm[1] is empty.
466 01:19:34.489783 ---------------------------------------------------------------------
467 01:19:34.490044 pGblData->Channel[1][1].RankPresent : 0x3
468 01:19:34.490359
469 01:19:34.490609
470 01:19:34.499309 socket[1] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
471 01:19:34.499648 ---------------------------------------------------------------------
472 01:19:34.499964 SPD_KEY_BYTE : DDR4
473 01:19:34.500249 SPD_KEY_BYTE2 : RDIMM
474 01:19:34.509614 SPD_MODULE_ORG_DDR4 : 0x8
475 01:19:34.509966 SPD_MIN_TCK_DDR4 : 0x7
476 01:19:34.510278 SPD_MAX_TCK_DDR4 : 0xD
477 01:19:34.510982 SPD_FTB_MIN_TCK_DDR4 : 0xD6
478 01:19:34.511272 DimmMaxFreq : 2401Mbps
479 01:19:34.521518 pGblData->Channel[1][2].Dimm[0].DramWidth : X4
480 01:19:34.521857 pGblData->Channel[1][2].Dimm[0].RankNum : 2
481 01:19:34.522172 pGblData->Channel[1][2].Dimm[0].ddrFreq : 2400Mbps
482 01:19:34.522449 pGblData->Channel[1][2].Dimm[0].minTck : 8330
483 01:19:34.539610 ---------------------------------------------------------------------
484 01:19:34.539959
485 01:19:34.540281 socket[1] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
486 01:19:34.540575 ---------------------------------------------------------------------
487 01:19:34.552233 SPD_KEY_BYTE : Empty
488 01:19:34.552659 Socket[1] Channel[2] Dimm[1] is empty.
489 01:19:34.553113 ---------------------------------------------------------------------
490 01:19:34.553517 pGblData->Channel[1][2].RankPresent : 0x3
491 01:19:34.554010
492 01:19:34.554435
493 01:19:34.569425 socket[1] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
494 01:19:34.569731 ---------------------------------------------------------------------
495 01:19:34.570065 SPD_KEY_BYTE : DDR4
496 01:19:34.570430 SPD_KEY_BYTE2 : RDIMM
497 01:19:34.580085 SPD_MODULE_ORG_DDR4 : 0x8
498 01:19:34.580641 SPD_MIN_TCK_DDR4 : 0x7
499 01:19:34.580969 SPD_MAX_TCK_DDR4 : 0xD
500 01:19:34.581337 SPD_FTB_MIN_TCK_DDR4 : 0xD6
501 01:19:34.581646 DimmMaxFreq : 2401Mbps
502 01:19:34.599514 pGblData->Channel[1][3].Dimm[0].DramWidth : X4
503 01:19:34.599869 pGblData->Channel[1][3].Dimm[0].RankNum : 2
504 01:19:34.600177 pGblData->Channel[1][3].Dimm[0].ddrFreq : 2400Mbps
505 01:19:34.600462 pGblData->Channel[1][3].Dimm[0].minTck : 8330
506 01:19:34.609641 ---------------------------------------------------------------------
507 01:19:34.609992
508 01:19:34.610290 socket[1] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
509 01:19:34.610579 ---------------------------------------------------------------------
510 01:19:34.619438 SPD_KEY_BYTE : Empty
511 01:19:34.619739 Socket[1] Channel[3] Dimm[1] is empty.
512 01:19:34.620014 ---------------------------------------------------------------------
513 01:19:34.620324 pGblData->Channel[1][3].RankPresent : 0x3
514 01:19:34.620965
515 01:19:34.630281 DimmMaxFreq : 2401Mbps
516 01:19:34.630648 GblData->Freq : 2400
517 01:19:34.630967 GblData->Tck : 8333
518 01:19:34.631303 GblData->DdrFreqIdx : 13
519 01:19:34.631592 Check dimm status ok!
520 01:19:34.631916 pGblData->MaxSPCNum = 2
521 01:19:34.632200 skt[0] ch[0] maxPORFreqIdx = 13
522 01:19:34.632539 skt[0] ch[1] maxPORFreqIdx = 13
523 01:19:34.649311 skt[0] ch[2] maxPORFreqIdx = 13
524 01:19:34.649597 skt[0] ch[3] maxPORFreqIdx = 13
525 01:19:34.649935 skt[1] ch[0] maxPORFreqIdx = 13
526 01:19:34.650214 skt[1] ch[1] maxPORFreqIdx = 13
527 01:19:34.650534 skt[1] ch[2] maxPORFreqIdx = 13
528 01:19:34.650804 skt[1] ch[3] maxPORFreqIdx = 13
529 01:19:34.651067 ---------------------------------------------------------------------
530 01:19:34.660459 ---------------------------------------------------------------------
531 01:19:34.660866 PORFreqTable result(max system ddr frequency):
532 01:19:34.661217 pGblData->DdrFreqIdx = 13
533 01:19:34.661503 pGblData->DevParaFreqIdx = 13
534 01:19:34.661831 pGblData->Tck = 8333
535 01:19:34.662072 pGblData->Freq = 2400
536 01:19:34.679751 ---------------------------------------------------------------------
537 01:19:34.680095 ---------------------------------------------------------------------
538 01:19:34.680378 Set ddr frequency ok!
539 01:19:34.680734 Get dimm spd information
540 01:19:34.681092
541 01:19:34.741146 socket[0] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
542 01:19:35.309264 SPD_MIN_TRCD_DDR4: 0x6E
543 01:19:35.309775 SPD_FTB_TRCD_DDR4: 0x0
544 01:19:35.310042 SPD_MIN_TRRDL_DDR4: 0x28
545 01:19:35.310343 SPD_FTB_TRRDL_DDR4: 0x9C
546 01:19:35.310656 SPD_MIN_TRRDS_DDR4: 0x1B
547 01:19:35.310947 SPD_FTB_TRRDS_DDR4: 0xB5
548 01:19:35.311270 SPD_EXT_TRC_TRAS_DDR4: 0x11
549 01:19:35.311513 SPD_MIN_TRAS_DDR4: 0x0
550 01:19:35.311842 SPD_MIN_TRC_DDR4: 0x6E
551 01:19:35.312248 SPD_FTB_TRC_DDR4: 0x0
552 01:19:35.333912 SPD_MIN_TRFC1_MSB_DDR4: 0xA
553 01:19:35.334304 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
554 01:19:35.334497 tRFC: 0xAF0
555 01:19:35.334682 tempCkNum: 0x55730
556 01:19:35.334865 SPD_MIN_TAA_DDR4: 0x6E
557 01:19:35.335043 SPD_FTB_TAA: 0x0
558 01:19:35.335219 SPD_TFAW_UPPER_DDR4: 0x0
559 01:19:35.335394 SPD_MIN_TFAW_DDR4: 0x68
560 01:19:35.335567 SPD_MIN_TRP_DDR4: 0x6E
561 01:19:35.335741 SPD_FTB_TRP_DDR4: 0x0
562 01:19:35.339150 SPD_MIN_TCCDL_DDR4: 0x28
563 01:19:35.339377 SPD_FTB_TCCDL_DDR4: 0x0
564 01:19:35.339569 ---------------------------------------------------------------------
565 01:19:35.339759 pGblData item skt ch dimm value
566 01:19:35.339942 ---------------------------------------------------------------------
567 01:19:35.352937 SDRAMCapacity 0 0 0 0x5
568 01:19:35.353313 BGNum 0 0 0 4
569 01:19:35.353511 BankNum 0 0 0 16
570 01:19:35.353701 ColBits 0 0 0 10
571 01:19:35.353888 RowBits 0 0 0 17
572 01:19:35.374482 SpdMirror 0 0 0 1
573 01:19:35.374806 SpdVdd 0 0 0 3
574 01:19:35.375002 PrimaryBusWidth 0 0 0 64
575 01:19:35.375191 ExtensionBusWidth 0 0 0 8
576 01:19:35.396396 RankSize 0 0 0 16384
577 01:19:35.396711 SpdRMId 0 0 0 0x3206
578 01:19:35.396929 SpdMMfgId 0 0 0 0xCE00
579 01:19:35.397116 SpdMMDate 0 0 0 0x2817
580 01:19:35.397297 SpdSerialNum 0 0 0 0x4F82936
581 01:19:35.418191 SpdMinTRCD 0 0 0 0x6E
582 01:19:35.418481 SpdMinTRCDFtb 0 0 0 0x0
583 01:19:35.418675 nRCD 0 0 0 0x35B6
584 01:19:35.418862 SpdMinTRRDL 0 0 0 0x28
585 01:19:35.443629 SpdMinTRRD 0 0 0 0x1B
586 01:19:35.443857 SpdMinTRAS 0 0 0 0x100
587 01:19:35.444049 SpdMinTRC 0 0 0 0x16E
588 01:19:35.444234 SpdMinTRCFtb 0 0 0 0x0
589 01:19:35.444433 SpdMinTRFC 0 0 0 0xAF0
590 01:19:35.461981 SpdMinTAA 0 0 0 0x6E
591 01:19:35.462208 SpdMinTAAFtb 0 0 0 0x0
592 01:19:35.462402 SpdMinTFAW 0 0 0 0x68
593 01:19:35.462588 SpdMinTRP 0 0 0 0x6E
594 01:19:35.462769 SpdMinTRPFtb 0 0 0 0x0
595 01:19:35.542089 nRP 0 0 0 0x35B6
596 01:19:35.542410 SpdMinTCCDL 0 0 0 0x28
597 01:19:35.542603 SpdMinTCCDLFtb 0 0 0 0x0
598 01:19:35.542788 SpdModuleAttr 0 0 0 0x0
599 01:19:35.559387 SpdAddrMap 0 0 0 0x1
600 01:19:35.559614 ---------------------------------------------------------------------
601 01:19:35.559811
602 01:19:35.559996 socket[0] channel[0] SPD information:
603 01:19:35.560177 ---------------------------------------------------------------------
604 01:19:35.560360 item skt ch value
605 01:19:35.572268 ---------------------------------------------------------------------
606 01:19:35.572545 nWR 0 0 0ps
607 01:19:35.572741 nRCD 0 0 13750ps
608 01:19:35.572948 nRRDL 0 0 4900ps
609 01:19:35.573133 nRRD 0 0 3300ps
610 01:19:35.573314 nRAS 0 0 32000ps
611 01:19:35.579192 nRC 0 0 45750ps
612 01:19:35.579422 nRFC 0 0 350000ps
613 01:19:35.579614 nWTR 0 0 0ps
614 01:19:35.579818 nRTP 0 0 0ps
615 01:19:35.580002 nAA 0 0 13750ps
616 01:19:35.580183 nFAW 0 0 13000ps
617 01:19:35.599267 nRP 0 0 13750ps
618 01:19:35.599494 nCCDL 0 0 5000ps
619 01:19:35.599686 ---------------------------------------------------------------------
620 01:19:35.599875
621 01:19:35.600058 socket[0] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
622 01:19:36.277952 SPD_MIN_TRCD_DDR4: 0x6E
623 01:19:36.278306 SPD_FTB_TRCD_DDR4: 0x0
624 01:19:36.278498 SPD_MIN_TRRDL_DDR4: 0x28
625 01:19:36.278682 SPD_FTB_TRRDL_DDR4: 0x9C
626 01:19:36.278863 SPD_MIN_TRRDS_DDR4: 0x1B
627 01:19:36.279041 SPD_FTB_TRRDS_DDR4: 0xB5
628 01:19:36.279217 SPD_EXT_TRC_TRAS_DDR4: 0x11
629 01:19:36.279393 SPD_MIN_TRAS_DDR4: 0x0
630 01:19:36.279568 SPD_MIN_TRC_DDR4: 0x6E
631 01:19:36.279743 SPD_FTB_TRC_DDR4: 0x0
632 01:19:36.300903
633 01:19:36.301136 SPD_MIN_TRFC1_MSB_DDR4: 0xA
634 01:19:36.301328 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
635 01:19:36.301514 tRFC: 0xAF0
636 01:19:36.301697 tempCkNum: 0x55730
637 01:19:36.301877 SPD_MIN_TAA_DDR4: 0x6E
638 01:19:36.302054 SPD_FTB_TAA: 0x0
639 01:19:36.302231 SPD_TFAW_UPPER_DDR4: 0x0
640 01:19:36.302406 SPD_MIN_TFAW_DDR4: 0x68
641 01:19:36.302581 SPD_MIN_TRP_DDR4: 0x6E
642 01:19:36.302755 SPD_FTB_TRP_DDR4: 0x0
643 01:19:36.321749 SPD_MIN_TCCDL_DDR4: 0x28
644 01:19:36.321978 SPD_FTB_TCCDL_DDR4: 0x0
645 01:19:36.322171 ---------------------------------------------------------------------
646 01:19:36.322363 pGblData item skt ch dimm value
647 01:19:36.323320 ---------------------------------------------------------------------
648 01:19:36.388112 SDRAMCapacity 0 1 0 0x5
649 01:19:36.388374 BGNum 0 1 0 4
650 01:19:36.399259 BankNum 0 1 0 16
651 01:19:36.399487 ColBits 0 1 0 10
652 01:19:36.399679 RowBits 0 1 0 17
653 01:19:36.399864 SpdMirror 0 1 0 1
654 01:19:36.400044 SpdVdd 0 1 0 3
655 01:19:36.422850 PrimaryBusWidth 0 1 0 64
656 01:19:36.423087 ExtensionBusWidth 0 1 0 8
657 01:19:36.423279 RankSize 0 1 0 16384
658 01:19:36.423464 SpdRMId 0 1 0 0x3206
659 01:19:36.423645 SpdMMfgId 0 1 0 0xCE00
660 01:19:36.439564 SpdMMDate 0 1 0 0x2817
661 01:19:36.439793 SpdSerialNum 0 1 0 0xE3F82936
662 01:19:36.439986 SpdMinTRCD 0 1 0 0x6E
663 01:19:36.440170 SpdMinTRCDFtb 0 1 0 0x0
664 01:19:36.451901 nRCD 0 1 0 0x35B6
665 01:19:36.452130 SpdMinTRRDL 0 1 0 0x28
666 01:19:36.452323 SpdMinTRRD 0 1 0 0x1B
667 01:19:36.452508 SpdMinTRAS 0 1 0 0x100
668 01:19:36.452717 SpdMinTRC 0 1 0 0x16E
669 01:19:36.469273 SpdMinTRCFtb 0 1 0 0x0
670 01:19:36.469502 SpdMinTRFC 0 1 0 0xAF0
671 01:19:36.469694 SpdMinTAA 0 1 0 0x6E
672 01:19:36.469878 SpdMinTAAFtb 0 1 0 0x0
673 01:19:36.479523 SpdMinTFAW 0 1 0 0x68
674 01:19:36.479750 SpdMinTRP 0 1 0 0x6E
675 01:19:36.479941 SpdMinTRPFtb 0 1 0 0x0
676 01:19:36.480124 nRP 0 1 0 0x35B6
677 01:19:36.480306 SpdMinTCCDL 0 1 0 0x28
678 01:19:36.489337 SpdMinTCCDLFtb 0 1 0 0x0
679 01:19:36.489565 SpdModuleAttr 0 1 0 0x0
680 01:19:36.489756 SpdAddrMap 0 1 0 0x1
681 01:19:36.489940 ---------------------------------------------------------------------
682 01:19:36.490127
683 01:19:36.507489 socket[0] channel[1] SPD information:
684 01:19:36.507794 ---------------------------------------------------------------------
685 01:19:36.508080 item skt ch value
686 01:19:36.508383 ---------------------------------------------------------------------
687 01:19:36.508717 nWR 0 1 0ps
688 01:19:36.530409 nRCD 0 1 13750ps
689 01:19:36.530731 nRRDL 0 1 4900ps
690 01:19:36.531027 nRRD 0 1 3300ps
691 01:19:36.531302 nRAS 0 1 32000ps
692 01:19:36.531572 nRC 0 1 45750ps
693 01:19:36.531843 nRFC 0 1 350000ps
694 01:19:36.532122 nWTR 0 1 0ps
695 01:19:36.549341 nRTP 0 1 0ps
696 01:19:36.549624 nAA 0 1 13750ps
697 01:19:36.549902 nFAW 0 1 13000ps
698 01:19:36.550182 nRP 0 1 13750ps
699 01:19:36.550459 nCCDL 0 1 5000ps
700 01:19:36.550732 ---------------------------------------------------------------------
701 01:19:36.551010
702 01:19:36.569181 socket[0] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
703 01:19:37.269727 SPD_MIN_TRCD_DDR4: 0x6E
704 01:19:37.270098 SPD_FTB_TRCD_DDR4: 0x0
705 01:19:37.270310 SPD_MIN_TRRDL_DDR4: 0x28
706 01:19:37.270509 SPD_FTB_TRRDL_DDR4: 0x9C
707 01:19:37.270713 SPD_MIN_TRRDS_DDR4: 0x1B
708 01:19:37.270904 SPD_FTB_TRRDS_DDR4: 0xB5
709 01:19:37.271103 SPD_EXT_TRC_TRAS_DDR4: 0x11
710 01:19:37.271293 SPD_MIN_TRAS_DDR4: 0x0
711 01:19:37.271489 SPD_MIN_TRC_DDR4: 0x6E
712 01:19:37.271677 SPD_FTB_TRC_DDR4: 0x0
713 01:19:37.292044
714 01:19:37.292286 SPD_MIN_TRFC1_MSB_DDR4: 0xA
715 01:19:37.292489 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
716 01:19:37.292727 tRFC: 0xAF0
717 01:19:37.292948 tempCkNum: 0x55730
718 01:19:37.293145 SPD_MIN_TAA_DDR4: 0x6E
719 01:19:37.293346 SPD_FTB_TAA: 0x0
720 01:19:37.293543 SPD_TFAW_UPPER_DDR4: 0x0
721 01:19:37.294401 SPD_MIN_TFAW_DDR4: 0x68
722 01:19:37.294604 SPD_MIN_TRP_DDR4: 0x6E
723 01:19:37.294806 SPD_FTB_TRP_DDR4: 0x0
724 01:19:37.312445 SPD_MIN_TCCDL_DDR4: 0x28
725 01:19:37.312749 SPD_FTB_TCCDL_DDR4: 0x0
726 01:19:37.312971 ---------------------------------------------------------------------
727 01:19:37.313174 pGblData item skt ch dimm value
728 01:19:37.313380 ---------------------------------------------------------------------
729 01:19:37.334498 SDRAMCapacity 0 2 0 0x5
730 01:19:37.334755 BGNum 0 2 0 4
731 01:19:37.334969 BankNum 0 2 0 16
732 01:19:37.335167 ColBits 0 2 0 10
733 01:19:37.335384 RowBits 0 2 0 17
734 01:19:37.356199 SpdMirror 0 2 0 1
735 01:19:37.356450 SpdVdd 0 2 0 3
736 01:19:37.356692 PrimaryBusWidth 0 2 0 64
737 01:19:37.356910 ExtensionBusWidth 0 2 0 8
738 01:19:37.378400 RankSize 0 2 0 16384
739 01:19:37.378656 SpdRMId 0 2 0 0x3206
740 01:19:37.378878 SpdMMfgId 0 2 0 0xCE00
741 01:19:37.379086 SpdMMDate 0 2 0 0x2817
742 01:19:37.379283 SpdSerialNum 0 2 0 0xDFF32936
743 01:19:37.401925 SpdMinTRCD 0 2 0 0x6E
744 01:19:37.402163 SpdMinTRCDFtb 0 2 0 0x0
745 01:19:37.402385 nRCD 0 2 0 0x35B6
746 01:19:37.402593 SpdMinTRRDL 0 2 0 0x28
747 01:19:37.421782 SpdMinTRRD 0 2 0 0x1B
748 01:19:37.422024 SpdMinTRAS 0 2 0 0x100
749 01:19:37.422228 SpdMinTRC 0 2 0 0x16E
750 01:19:37.422436 SpdMinTRCFtb 0 2 0 0x0
751 01:19:37.422631 SpdMinTRFC 0 2 0 0xAF0
752 01:19:37.443741 SpdMinTAA 0 2 0 0x6E
753 01:19:37.443994 SpdMinTAAFtb 0 2 0 0x0
754 01:19:37.444207 SpdMinTFAW 0 2 0 0x68
755 01:19:37.444405 SpdMinTRP 0 2 0 0x6E
756 01:19:37.444641 SpdMinTRPFtb 0 2 0 0x0
757 01:19:37.465933 nRP 0 2 0 0x35B6
758 01:19:37.466181 SpdMinTCCDL 0 2 0 0x28
759 01:19:37.466394 SpdMinTCCDLFtb 0 2 0 0x0
760 01:19:37.466603 SpdModuleAttr 0 2 0 0x0
761 01:19:37.487367 SpdAddrMap 0 2 0 0x1
762 01:19:37.487606 ---------------------------------------------------------------------
763 01:19:37.487822
764 01:19:37.488028 socket[0] channel[2] SPD information:
765 01:19:37.488222 ---------------------------------------------------------------------
766 01:19:37.488428 item skt ch value
767 01:19:37.556560 ---------------------------------------------------------------------
768 01:19:37.556868 nWR 0 2 0ps
769 01:19:37.557085 nRCD 0 2 13750ps
770 01:19:37.557293 nRRDL 0 2 4900ps
771 01:19:37.557500 nRRD 0 2 3300ps
772 01:19:37.557695 nRAS 0 2 32000ps
773 01:19:37.569732 nRC 0 2 45750ps
774 01:19:37.570108 nRFC 0 2 350000ps
775 01:19:37.570410 nWTR 0 2 0ps
776 01:19:37.570731 nRTP 0 2 0ps
777 01:19:37.571034 nAA 0 2 13750ps
778 01:19:37.571324 nFAW 0 2 13000ps
779 01:19:37.591843 nRP 0 2 13750ps
780 01:19:37.592551 nCCDL 0 2 5000ps
781 01:19:37.592898 ---------------------------------------------------------------------
782 01:19:37.593212
783 01:19:37.593511 socket[0] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
784 01:19:38.260699 SPD_MIN_TRCD_DDR4: 0x6E
785 01:19:38.261137 SPD_FTB_TRCD_DDR4: 0x0
786 01:19:38.261353 SPD_MIN_TRRDL_DDR4: 0x28
787 01:19:38.261606 SPD_FTB_TRRDL_DDR4: 0x9C
788 01:19:38.261861 SPD_MIN_TRRDS_DDR4: 0x1B
789 01:19:38.262111 SPD_FTB_TRRDS_DDR4: 0xB5
790 01:19:38.262359 SPD_EXT_TRC_TRAS_DDR4: 0x11
791 01:19:38.262603 SPD_MIN_TRAS_DDR4: 0x0
792 01:19:38.262849 SPD_MIN_TRC_DDR4: 0x6E
793 01:19:38.263094 SPD_FTB_TRC_DDR4: 0x0
794 01:19:38.281686
795 01:19:38.281990 SPD_MIN_TRFC1_MSB_DDR4: 0xA
796 01:19:38.282251 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
797 01:19:38.282507 tRFC: 0xAF0
798 01:19:38.283081 tempCkNum: 0x55730
799 01:19:38.283355 SPD_MIN_TAA_DDR4: 0x6E
800 01:19:38.283610 SPD_FTB_TAA: 0x0
801 01:19:38.283856 SPD_TFAW_UPPER_DDR4: 0x0
802 01:19:38.284053 SPD_MIN_TFAW_DDR4: 0x68
803 01:19:38.284266 SPD_MIN_TRP_DDR4: 0x6E
804 01:19:38.284474 SPD_FTB_TRP_DDR4: 0x0
805 01:19:38.303532 SPD_MIN_TCCDL_DDR4: 0x28
806 01:19:38.303806 SPD_FTB_TCCDL_DDR4: 0x0
807 01:19:38.304010 ---------------------------------------------------------------------
808 01:19:38.304201 pGblData item skt ch dimm value
809 01:19:38.304399 ---------------------------------------------------------------------
810 01:19:38.325625 SDRAMCapacity 0 3 0 0x5
811 01:19:38.326341 BGNum 0 3 0 4
812 01:19:38.326545 BankNum 0 3 0 16
813 01:19:38.326733 ColBits 0 3 0 10
814 01:19:38.326919 RowBits 0 3 0 17
815 01:19:38.351108 SpdMirror 0 3 0 1
816 01:19:38.351344 SpdVdd 0 3 0 3
817 01:19:38.351611 PrimaryBusWidth 0 3 0 64
818 01:19:38.351910 ExtensionBusWidth 0 3 0 8
819 01:19:38.369202 RankSize 0 3 0 16384
820 01:19:38.369480 SpdRMId 0 3 0 0x3206
821 01:19:38.369686 SpdMMfgId 0 3 0 0xCE00
822 01:19:38.369871 SpdMMDate 0 3 0 0x2817
823 01:19:38.370052 SpdSerialNum 0 3 0 0xF5F02936
824 01:19:38.392460 SpdMinTRCD 0 3 0 0x6E
825 01:19:38.392775 SpdMinTRCDFtb 0 3 0 0x0
826 01:19:38.393014 nRCD 0 3 0 0x35B6
827 01:19:38.393271 SpdMinTRRDL 0 3 0 0x28
828 01:19:38.413016 SpdMinTRRD 0 3 0 0x1B
829 01:19:38.413289 SpdMinTRAS 0 3 0 0x100
830 01:19:38.413480 SpdMinTRC 0 3 0 0x16E
831 01:19:38.413664 SpdMinTRCFtb 0 3 0 0x0
832 01:19:38.413845 SpdMinTRFC 0 3 0 0xAF0
833 01:19:38.434723 SpdMinTAA 0 3 0 0x6E
834 01:19:38.434937 SpdMinTAAFtb 0 3 0 0x0
835 01:19:38.435127 SpdMinTFAW 0 3 0 0x68
836 01:19:38.435312 SpdMinTRP 0 3 0 0x6E
837 01:19:38.435492 SpdMinTRPFtb 0 3 0 0x0
838 01:19:38.456570 nRP 0 3 0 0x35B6
839 01:19:38.456939 SpdMinTCCDL 0 3 0 0x28
840 01:19:38.457220 SpdMinTCCDLFtb 0 3 0 0x0
841 01:19:38.457489 SpdModuleAttr 0 3 0 0x0
842 01:19:38.478410 SpdAddrMap 0 3 0 0x1
843 01:19:38.478683 ---------------------------------------------------------------------
844 01:19:38.478966
845 01:19:38.479236 socket[0] channel[3] SPD information:
846 01:19:38.479504 ---------------------------------------------------------------------
847 01:19:38.479784 item skt ch value
848 01:19:38.501039 ---------------------------------------------------------------------
849 01:19:38.501285 nWR 0 3 0ps
850 01:19:38.501556 nRCD 0 3 13750ps
851 01:19:38.501826 nRRDL 0 3 4900ps
852 01:19:38.502092 nRRD 0 3 3300ps
853 01:19:38.502365 nRAS 0 3 32000ps
854 01:19:38.526726 nRC 0 3 45750ps
855 01:19:38.526968 nRFC 0 3 350000ps
856 01:19:38.527238 nWTR 0 3 0ps
857 01:19:38.539884 nRTP 0 3 0ps
858 01:19:38.540125 nAA 0 3 13750ps
859 01:19:38.540405 nFAW 0 3 13000ps
860 01:19:38.540696 nRP 0 3 13750ps
861 01:19:38.540982 nCCDL 0 3 5000ps
862 01:19:38.541268 ---------------------------------------------------------------------
863 01:19:38.541573
864 01:19:38.569281 socket[1] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
865 01:19:39.249158 SPD_MIN_TRCD_DDR4: 0x6E
866 01:19:39.249510 SPD_FTB_TRCD_DDR4: 0x0
867 01:19:39.249703 SPD_MIN_TRRDL_DDR4: 0x28
868 01:19:39.249889 SPD_FTB_TRRDL_DDR4: 0x9C
869 01:19:39.250071 SPD_MIN_TRRDS_DDR4: 0x1B
870 01:19:39.250251 SPD_FTB_TRRDS_DDR4: 0xB5
871 01:19:39.250428 SPD_EXT_TRC_TRAS_DDR4: 0x11
872 01:19:39.250605 SPD_MIN_TRAS_DDR4: 0x0
873 01:19:39.250781 SPD_MIN_TRC_DDR4: 0x6E
874 01:19:39.250956 SPD_FTB_TRC_DDR4: 0x0
875 01:19:39.270291
876 01:19:39.270518 SPD_MIN_TRFC1_MSB_DDR4: 0xA
877 01:19:39.270708 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
878 01:19:39.270890 tRFC: 0xAF0
879 01:19:39.271070 tempCkNum: 0x55730
880 01:19:39.271248 SPD_MIN_TAA_DDR4: 0x6E
881 01:19:39.271424 SPD_FTB_TAA: 0x0
882 01:19:39.271599 SPD_TFAW_UPPER_DDR4: 0x0
883 01:19:39.271773 SPD_MIN_TFAW_DDR4: 0x68
884 01:19:39.271947 SPD_MIN_TRP_DDR4: 0x6E
885 01:19:39.272120 SPD_FTB_TRP_DDR4: 0x0
886 01:19:39.290231 SPD_MIN_TCCDL_DDR4: 0x28
887 01:19:39.290471 SPD_FTB_TCCDL_DDR4: 0x0
888 01:19:39.290661 ---------------------------------------------------------------------
889 01:19:39.290850 pGblData item skt ch dimm value
890 01:19:39.291035 ---------------------------------------------------------------------
891 01:19:39.310768 SDRAMCapacity 1 0 0 0x5
892 01:19:39.310990 BGNum 1 0 0 4
893 01:19:39.311180 BankNum 1 0 0 16
894 01:19:39.311365 ColBits 1 0 0 10
895 01:19:39.311546 RowBits 1 0 0 17
896 01:19:39.340238 SpdMirror 1 0 0 1
897 01:19:39.340467 SpdVdd 1 0 0 3
898 01:19:39.340692 PrimaryBusWidth 1 0 0 64
899 01:19:39.340891 ExtensionBusWidth 1 0 0 8
900 01:19:39.360640 RankSize 1 0 0 16384
901 01:19:39.360861 SpdRMId 1 0 0 0x3206
902 01:19:39.361070 SpdMMfgId 1 0 0 0xCE00
903 01:19:39.361254 SpdMMDate 1 0 0 0x2817
904 01:19:39.361435 SpdSerialNum 1 0 0 0xE2F32936
905 01:19:39.425234 SpdMinTRCD 1 0 0 0x6E
906 01:19:39.425529 SpdMinTRCDFtb 1 0 0 0x0
907 01:19:39.431672 nRCD 1 0 0 0x35B6
908 01:19:39.431919 SpdMinTRRDL 1 0 0 0x28
909 01:19:39.432120 SpdMinTRRD 1 0 0 0x1B
910 01:19:39.432357 SpdMinTRAS 1 0 0 0x100
911 01:19:39.432573 SpdMinTRC 1 0 0 0x16E
912 01:19:39.439672 SpdMinTRCFtb 1 0 0 0x0
913 01:19:39.439896 SpdMinTRFC 1 0 0 0xAF0
914 01:19:39.440137 SpdMinTAA 1 0 0 0x6E
915 01:19:39.440325 SpdMinTAAFtb 1 0 0 0x0
916 01:19:39.449390 SpdMinTFAW 1 0 0 0x68
917 01:19:39.449671 SpdMinTRP 1 0 0 0x6E
918 01:19:39.449868 SpdMinTRPFtb 1 0 0 0x0
919 01:19:39.450095 nRP 1 0 0 0x35B6
920 01:19:39.450282 SpdMinTCCDL 1 0 0 0x28
921 01:19:39.459658 SpdMinTCCDLFtb 1 0 0 0x0
922 01:19:39.459922 SpdModuleAttr 1 0 0 0x0
923 01:19:39.460170 SpdAddrMap 1 0 0 0x1
924 01:19:39.460362 ---------------------------------------------------------------------
925 01:19:39.460575
926 01:19:39.479460 socket[1] channel[0] SPD information:
927 01:19:39.479710 ---------------------------------------------------------------------
928 01:19:39.479927 item skt ch value
929 01:19:39.480138 ---------------------------------------------------------------------
930 01:19:39.480349 nWR 1 0 0ps
931 01:19:39.499996 nRCD 1 0 13750ps
932 01:19:39.500209 nRRDL 1 0 4900ps
933 01:19:39.500412 nRRD 1 0 3300ps
934 01:19:39.500641 nRAS 1 0 32000ps
935 01:19:39.500837 nRC 1 0 45750ps
936 01:19:39.501052 nRFC 1 0 350000ps
937 01:19:39.501244 nWTR 1 0 0ps
938 01:19:39.519459 nRTP 1 0 0ps
939 01:19:39.519692 nAA 1 0 13750ps
940 01:19:39.519905 nFAW 1 0 13000ps
941 01:19:39.520114 nRP 1 0 13750ps
942 01:19:39.520320 nCCDL 1 0 5000ps
943 01:19:39.520539 ---------------------------------------------------------------------
944 01:19:39.520747
945 01:19:39.540939 socket[1] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
946 01:19:40.261138 SPD_MIN_TRCD_DDR4: 0x6E
947 01:19:40.261507 SPD_FTB_TRCD_DDR4: 0x0
948 01:19:40.261700 SPD_MIN_TRRDL_DDR4: 0x28
949 01:19:40.261893 SPD_FTB_TRRDL_DDR4: 0x9C
950 01:19:40.262084 SPD_MIN_TRRDS_DDR4: 0x1B
951 01:19:40.262270 SPD_FTB_TRRDS_DDR4: 0xB5
952 01:19:40.262458 SPD_EXT_TRC_TRAS_DDR4: 0x11
953 01:19:40.262641 SPD_MIN_TRAS_DDR4: 0x0
954 01:19:40.262824 SPD_MIN_TRC_DDR4: 0x6E
955 01:19:40.263009 SPD_FTB_TRC_DDR4: 0x0
956 01:19:40.270327 SPD_MIN_TRFC1_MSB_DDR4: 0xA
957 01:19:40.270558 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
958 01:19:40.270760 tRFC: 0xAF0
959 01:19:40.270955 tempCkNum: 0x55730
960 01:19:40.271148 SPD_MIN_TAA_DDR4: 0x6E
961 01:19:40.271336 SPD_FTB_TAA: 0x0
962 01:19:40.271521 SPD_TFAW_UPPER_DDR4: 0x0
963 01:19:40.271704 SPD_MIN_TFAW_DDR4: 0x68
964 01:19:40.271885 SPD_MIN_TRP_DDR4: 0x6E
965 01:19:40.272069 SPD_FTB_TRP_DDR4: 0x0
966 01:19:40.286594 SPD_MIN_TCCDL_DDR4: 0x28
967 01:19:40.286827 SPD_FTB_TCCDL_DDR4: 0x0
968 01:19:40.287027 ---------------------------------------------------------------------
969 01:19:40.287228 pGblData item skt ch dimm value
970 01:19:40.287419 ---------------------------------------------------------------------
971 01:19:40.308038 SDRAMCapacity 1 1 0 0x5
972 01:19:40.308288 BGNum 1 1 0 4
973 01:19:40.308489 BankNum 1 1 0 16
974 01:19:40.308714 ColBits 1 1 0 10
975 01:19:40.308921 RowBits 1 1 0 17
976 01:19:40.329411 SpdMirror 1 1 0 1
977 01:19:40.329751 SpdVdd 1 1 0 3
978 01:19:40.330662 PrimaryBusWidth 1 1 0 64
979 01:19:40.330859 ExtensionBusWidth 1 1 0 8
980 01:19:40.349440 RankSize 1 1 0 16384
981 01:19:40.349699 SpdRMId 1 1 0 0x3206
982 01:19:40.349901 SpdMMfgId 1 1 0 0xCE00
983 01:19:40.350098 SpdMMDate 1 1 0 0x2817
984 01:19:40.350292 SpdSerialNum 1 1 0 0x9AF22936
985 01:19:40.373981 SpdMinTRCD 1 1 0 0x6E
986 01:19:40.374308 SpdMinTRCDFtb 1 1 0 0x0
987 01:19:40.374509 nRCD 1 1 0 0x35B6
988 01:19:40.374702 SpdMinTRRDL 1 1 0 0x28
989 01:19:40.425622 SpdMinTRRD 1 1 0 0x1B
990 01:19:40.425859 SpdMinTRAS 1 1 0 0x100
991 01:19:40.426059 SpdMinTRC 1 1 0 0x16E
992 01:19:40.433622 SpdMinTRCFtb 1 1 0 0x0
993 01:19:40.433846 SpdMinTRFC 1 1 0 0xAF0
994 01:19:40.434046 SpdMinTAA 1 1 0 0x6E
995 01:19:40.434243 SpdMinTAAFtb 1 1 0 0x0
996 01:19:40.441350 SpdMinTFAW 1 1 0 0x68
997 01:19:40.441583 SpdMinTRP 1 1 0 0x6E
998 01:19:40.441783 SpdMinTRPFtb 1 1 0 0x0
999 01:19:40.441975 nRP 1 1 0 0x35B6
1000 01:19:40.442165 SpdMinTCCDL 1 1 0 0x28
1001 01:19:40.455868 SpdMinTCCDLFtb 1 1 0 0x0
1002 01:19:40.456114 SpdModuleAttr 1 1 0 0x0
1003 01:19:40.456314 SpdAddrMap 1 1 0 0x1
1004 01:19:40.456507 ---------------------------------------------------------------------
1005 01:19:40.456725
1006 01:19:40.473858 socket[1] channel[1] SPD information:
1007 01:19:40.474102 ---------------------------------------------------------------------
1008 01:19:40.474306 item skt ch value
1009 01:19:40.474497 ---------------------------------------------------------------------
1010 01:19:40.474689 nWR 1 1 0ps
1011 01:19:40.490033 nRCD 1 1 13750ps
1012 01:19:40.490265 nRRDL 1 1 4900ps
1013 01:19:40.490464 nRRD 1 1 3300ps
1014 01:19:40.490659 nRAS 1 1 32000ps
1015 01:19:40.490847 nRC 1 1 45750ps
1016 01:19:40.491033 nRFC 1 1 350000ps
1017 01:19:40.491217 nWTR 1 1 0ps
1018 01:19:40.509277 nRTP 1 1 0ps
1019 01:19:40.509510 nAA 1 1 13750ps
1020 01:19:40.509709 nFAW 1 1 13000ps
1021 01:19:40.509901 nRP 1 1 13750ps
1022 01:19:40.510093 nCCDL 1 1 5000ps
1023 01:19:40.510280 ---------------------------------------------------------------------
1024 01:19:40.510469
1025 01:19:40.529081 socket[1] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
1026 01:19:41.233846 SPD_MIN_TRCD_DDR4: 0x6E
1027 01:19:41.234196 SPD_FTB_TRCD_DDR4: 0x0
1028 01:19:41.234400 SPD_MIN_TRRDL_DDR4: 0x28
1029 01:19:41.234604 SPD_FTB_TRRDL_DDR4: 0x9C
1030 01:19:41.234803 SPD_MIN_TRRDS_DDR4: 0x1B
1031 01:19:41.235005 SPD_FTB_TRRDS_DDR4: 0xB5
1032 01:19:41.235197 SPD_EXT_TRC_TRAS_DDR4: 0x11
1033 01:19:41.235392 SPD_MIN_TRAS_DDR4: 0x0
1034 01:19:41.235584 SPD_MIN_TRC_DDR4: 0x6E
1035 01:19:41.235777 SPD_FTB_TRC_DDR4: 0x0
1036 01:19:41.249817
1037 01:19:41.250057 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1038 01:19:41.250267 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1039 01:19:41.250473 tRFC: 0xAF0
1040 01:19:41.250677 tempCkNum: 0x55730
1041 01:19:41.250869 SPD_MIN_TAA_DDR4: 0x6E
1042 01:19:41.251065 SPD_FTB_TAA: 0x0
1043 01:19:41.251258 SPD_TFAW_UPPER_DDR4: 0x0
1044 01:19:41.251452 SPD_MIN_TFAW_DDR4: 0x68
1045 01:19:41.251929 SPD_MIN_TRP_DDR4: 0x6E
1046 01:19:41.252153 SPD_FTB_TRP_DDR4: 0x0
1047 01:19:41.277470 SPD_MIN_TCCDL_DDR4: 0x28
1048 01:19:41.277706 SPD_FTB_TCCDL_DDR4: 0x0
1049 01:19:41.277912 ---------------------------------------------------------------------
1050 01:19:41.278112 pGblData item skt ch dimm value
1051 01:19:41.278310 ---------------------------------------------------------------------
1052 01:19:41.299409 SDRAMCapacity 1 2 0 0x5
1053 01:19:41.299645 BGNum 1 2 0 4
1054 01:19:41.299852 BankNum 1 2 0 16
1055 01:19:41.300049 ColBits 1 2 0 10
1056 01:19:41.300248 RowBits 1 2 0 17
1057 01:19:41.320435 SpdMirror 1 2 0 1
1058 01:19:41.320706 SpdVdd 1 2 0 3
1059 01:19:41.320928 PrimaryBusWidth 1 2 0 64
1060 01:19:41.321130 ExtensionBusWidth 1 2 0 8
1061 01:19:41.340134 RankSize 1 2 0 16384
1062 01:19:41.340394 SpdRMId 1 2 0 0x3206
1063 01:19:41.340638 SpdMMfgId 1 2 0 0xCE00
1064 01:19:41.340845 SpdMMDate 1 2 0 0x2817
1065 01:19:41.341068 SpdSerialNum 1 2 0 0x9BF22936
1066 01:19:41.360681 SpdMinTRCD 1 2 0 0x6E
1067 01:19:41.360939 SpdMinTRCDFtb 1 2 0 0x0
1068 01:19:41.361148 nRCD 1 2 0 0x35B6
1069 01:19:41.361355 SpdMinTRRDL 1 2 0 0x28
1070 01:19:41.417556 SpdMinTRRD 1 2 0 0x1B
1071 01:19:41.417852 SpdMinTRAS 1 2 0 0x100
1072 01:19:41.418066 SpdMinTRC 1 2 0 0x16E
1073 01:19:41.418273 SpdMinTRCFtb 1 2 0 0x0
1074 01:19:41.418474 SpdMinTRFC 1 2 0 0xAF0
1075 01:19:41.432446 SpdMinTAA 1 2 0 0x6E
1076 01:19:41.432717 SpdMinTAAFtb 1 2 0 0x0
1077 01:19:41.432942 SpdMinTFAW 1 2 0 0x68
1078 01:19:41.433148 SpdMinTRP 1 2 0 0x6E
1079 01:19:41.433353 SpdMinTRPFtb 1 2 0 0x0
1080 01:19:41.439199 nRP 1 2 0 0x35B6
1081 01:19:41.439439 SpdMinTCCDL 1 2 0 0x28
1082 01:19:41.439647 SpdMinTCCDLFtb 1 2 0 0x0
1083 01:19:41.439846 SpdModuleAttr 1 2 0 0x0
1084 01:19:41.452609 SpdAddrMap 1 2 0 0x1
1085 01:19:41.452860 ---------------------------------------------------------------------
1086 01:19:41.453083
1087 01:19:41.453311 socket[1] channel[2] SPD information:
1088 01:19:41.453505 ---------------------------------------------------------------------
1089 01:19:41.453701 item skt ch value
1090 01:19:41.470964 ---------------------------------------------------------------------
1091 01:19:41.471191 nWR 1 2 0ps
1092 01:19:41.471393 nRCD 1 2 13750ps
1093 01:19:41.471621 nRRDL 1 2 4900ps
1094 01:19:41.471815 nRRD 1 2 3300ps
1095 01:19:41.472003 nRAS 1 2 32000ps
1096 01:19:41.490319 nRC 1 2 45750ps
1097 01:19:41.490553 nRFC 1 2 350000ps
1098 01:19:41.490769 nWTR 1 2 0ps
1099 01:19:41.490966 nRTP 1 2 0ps
1100 01:19:41.491157 nAA 1 2 13750ps
1101 01:19:41.491347 nFAW 1 2 13000ps
1102 01:19:41.510327 nRP 1 2 13750ps
1103 01:19:41.510558 nCCDL 1 2 5000ps
1104 01:19:41.510761 ---------------------------------------------------------------------
1105 01:19:41.510961
1106 01:19:41.511155 socket[1] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
1107 01:19:42.210228 SPD_MIN_TRCD_DDR4: 0x6E
1108 01:19:42.210568 SPD_FTB_TRCD_DDR4: 0x0
1109 01:19:42.210760 SPD_MIN_TRRDL_DDR4: 0x28
1110 01:19:42.210956 SPD_FTB_TRRDL_DDR4: 0x9C
1111 01:19:42.211184 SPD_MIN_TRRDS_DDR4: 0x1B
1112 01:19:42.231616
1113 01:19:42.231864 SPD_FTB_TRRDS_DDR4: 0xB5
1114 01:19:42.232056 SPD_EXT_TRC_TRAS_DDR4: 0x11
1115 01:19:42.232301 SPD_MIN_TRAS_DDR4: 0x0
1116 01:19:42.232495 SPD_MIN_TRC_DDR4: 0x6E
1117 01:19:42.232725 SPD_FTB_TRC_DDR4: 0x0
1118 01:19:42.232935 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1119 01:19:42.233125 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1120 01:19:42.233308 tRFC: 0xAF0
1121 01:19:42.233493 tempCkNum: 0x55730
1122 01:19:42.233677 SPD_MIN_TAA_DDR4: 0x6E
1123 01:19:42.258040 SPD_FTB_TAA: 0x0
1124 01:19:42.258313 SPD_TFAW_UPPER_DDR4: 0x0
1125 01:19:42.258515 SPD_MIN_TFAW_DDR4: 0x68
1126 01:19:42.258709 SPD_MIN_TRP_DDR4: 0x6E
1127 01:19:42.258921 SPD_FTB_TRP_DDR4: 0x0
1128 01:19:42.259109 SPD_MIN_TCCDL_DDR4: 0x28
1129 01:19:42.259297 SPD_FTB_TCCDL_DDR4: 0x0
1130 01:19:42.259481 ---------------------------------------------------------------------
1131 01:19:42.279360 pGblData item skt ch dimm value
1132 01:19:42.279593 ---------------------------------------------------------------------
1133 01:19:42.279800 SDRAMCapacity 1 3 0 0x5
1134 01:19:42.279997 BGNum 1 3 0 4
1135 01:19:42.299756 BankNum 1 3 0 16
1136 01:19:42.299989 ColBits 1 3 0 10
1137 01:19:42.300192 RowBits 1 3 0 17
1138 01:19:42.300388 SpdMirror 1 3 0 1
1139 01:19:42.300606 SpdVdd 1 3 0 3
1140 01:19:42.319756 PrimaryBusWidth 1 3 0 64
1141 01:19:42.319987 ExtensionBusWidth 1 3 0 8
1142 01:19:42.320190 RankSize 1 3 0 16384
1143 01:19:42.320387 SpdRMId 1 3 0 0x3206
1144 01:19:42.320605 SpdMMfgId 1 3 0 0xCE00
1145 01:19:42.340107 SpdMMDate 1 3 0 0x2817
1146 01:19:42.340355 SpdSerialNum 1 3 0 0x84E82936
1147 01:19:42.340580 SpdMinTRCD 1 3 0 0x6E
1148 01:19:42.340776 SpdMinTRCDFtb 1 3 0 0x0
1149 01:19:42.367285 nRCD 1 3 0 0x35B6
1150 01:19:42.367517 SpdMinTRRDL 1 3 0 0x28
1151 01:19:42.367719 SpdMinTRRD 1 3 0 0x1B
1152 01:19:42.367906 SpdMinTRAS 1 3 0 0x100
1153 01:19:42.368097 SpdMinTRC 1 3 0 0x16E
1154 01:19:42.389371 SpdMinTRCFtb 1 3 0 0x0
1155 01:19:42.389684 SpdMinTRFC 1 3 0 0xAF0
1156 01:19:42.389890 SpdMinTAA 1 3 0 0x6E
1157 01:19:42.390089 SpdMinTAAFtb 1 3 0 0x0
1158 01:19:42.409239 SpdMinTFAW 1 3 0 0x68
1159 01:19:42.409472 SpdMinTRP 1 3 0 0x6E
1160 01:19:42.409676 SpdMinTRPFtb 1 3 0 0x0
1161 01:19:42.409864 nRP 1 3 0 0x35B6
1162 01:19:42.410057 SpdMinTCCDL 1 3 0 0x28
1163 01:19:42.429397 SpdMinTCCDLFtb 1 3 0 0x0
1164 01:19:42.429630 SpdModuleAttr 1 3 0 0x0
1165 01:19:42.429833 SpdAddrMap 1 3 0 0x1
1166 01:19:42.430030 ---------------------------------------------------------------------
1167 01:19:42.430227
1168 01:19:42.450067 socket[1] channel[3] SPD information:
1169 01:19:42.450331 ---------------------------------------------------------------------
1170 01:19:42.450538 item skt ch value
1171 01:19:42.450762 ---------------------------------------------------------------------
1172 01:19:42.450957 nWR 1 3 0ps
1173 01:19:42.477977 nRCD 1 3 13750ps
1174 01:19:42.478209 nRRDL 1 3 4900ps
1175 01:19:42.478403 nRRD 1 3 3300ps
1176 01:19:42.478598 nRAS 1 3 32000ps
1177 01:19:42.478789 nRC 1 3 45750ps
1178 01:19:42.478979 nRFC 1 3 350000ps
1179 01:19:42.479168 nWTR 1 3 0ps
1180 01:19:42.498799 nRTP 1 3 0ps
1181 01:19:42.499051 nAA 1 3 13750ps
1182 01:19:42.499252 nFAW 1 3 13000ps
1183 01:19:42.499439 nRP 1 3 13750ps
1184 01:19:42.499628 nCCDL 1 3 5000ps
1185 01:19:42.499815 ---------------------------------------------------------------------
1186 01:19:42.519334 ---------------------------------------------------------------------
1187 01:19:42.519570 Socket Channel Dimm Present Rank0 Rank1 Rank2 Rank3
1188 01:19:42.519772 0 0 0 YES YES YES NOT NOT
1189 01:19:42.540278 0 0 1 NOT NOT NOT NOT NOT
1190 01:19:42.540543 0 0 2 NOT NOT NOT NOT NOT
1191 01:19:42.540757 0 1 0 YES YES YES NOT NOT
1192 01:19:42.559564 0 1 1 NOT NOT NOT NOT NOT
1193 01:19:42.559796 0 1 2 NOT NOT NOT NOT NOT
1194 01:19:42.559999 0 2 0 YES YES YES NOT NOT
1195 01:19:42.560196 0 2 1 NOT NOT NOT NOT NOT
1196 01:19:42.581605 0 2 2 NOT NOT NOT NOT NOT
1197 01:19:42.581838 0 3 0 YES YES YES NOT NOT
1198 01:19:42.582043 0 3 1 NOT NOT NOT NOT NOT
1199 01:19:42.607894 0 3 2 NOT NOT NOT NOT NOT
1200 01:19:42.608129 1 0 0 YES YES YES NOT NOT
1201 01:19:42.608332 1 0 1 NOT NOT NOT NOT NOT
1202 01:19:42.608544 1 0 2 NOT NOT NOT NOT NOT
1203 01:19:42.631468 1 1 0 YES YES YES NOT NOT
1204 01:19:42.631702 1 1 1 NOT NOT NOT NOT NOT
1205 01:19:42.631897 1 1 2 NOT NOT NOT NOT NOT
1206 01:19:42.701520 1 2 0 YES YES YES NOT NOT
1207 01:19:42.701765 1 2 1 NOT NOT NOT NOT NOT
1208 01:19:42.709865 1 2 2 NOT NOT NOT NOT NOT
1209 01:19:42.710109 1 3 0 YES YES YES NOT NOT
1210 01:19:42.710312 1 3 1 NOT NOT NOT NOT NOT
1211 01:19:42.720560 1 3 2 NOT NOT NOT NOT NOT
1212 01:19:42.720792 ---------------------------------------------------------------------
1213 01:19:42.721017 **********************************************************************
1214 01:19:42.721215 Socket[0] Channel[0] Base:[0x60340000] Speed:[2400]
1215 01:19:42.729780 **********************************************************************
1216 01:19:42.730015 ==========================
1217 01:19:42.730219 config parameters from SPD
1218 01:19:42.730414 ==========================
1219 01:19:42.730605 DDR PHY PLL config.....................................OK!
1220 01:19:42.730795 Top module cfg.........................................OK
1221 01:19:42.739242 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1222 01:19:42.739476 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1223 01:19:42.739670 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1224 01:19:42.739864 Dmc init static........................................OK
1225 01:19:42.750326 Phy init dynamic.......................................OK
1226 01:19:42.750558
1227 01:19:42.750761 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1228 01:19:42.750959 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1229 01:19:42.766098 dimm[0] rcd init finished!
1230 01:19:42.766331 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1231 01:19:42.766560 rank[0] sdram init finished!
1232 01:19:42.766750 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1233 01:19:42.766933 rank[1] sdram init finished!
1234 01:19:42.767114 -----------------------------------------------------
1235 01:19:42.803660 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1236 01:19:42.803936 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1237 01:19:42.804138 -----------------------------------------------------
1238 01:19:42.804354 Dram init..............................................OK
1239 01:19:42.820759 socket[0] channel[0] rank[0] Phy gate leveling.....OK
1240 01:19:42.821106 socket[0] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1241 01:19:42.880653 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1242 01:19:42.880906 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1243 01:19:42.881136 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1244 01:19:42.890538 OK
1245 01:19:42.890771 socket[0] channel[0] rank[0] Phy write leveling.....OK
1246 01:19:42.890973 socket[0] channel[0] rank[1] Phy write leveling.....OK
1247 01:19:42.891171 socket[0] channel[0] rank[0] Phy write leveling 2...OK
1248 01:19:42.891363 socket[0] channel[0] rank[1] Phy write leveling 2...OK
1249 01:19:42.909279 socket[0] channel[0] rank[0] Read data eye training start:
1250 01:19:42.941447 socket[0] channel[0] rank[0] Read data eye training end
1251 01:19:42.941719
1252 01:19:42.941924 socket[0] channel[0] rank[1] Read data eye training start:
1253 01:19:43.009238 socket[0] channel[0] rank[1] Read data eye training end
1254 01:19:43.009483
1255 01:19:43.009686 socket[0] channel[0] rank[0] Write data eye training start:
1256 01:19:43.089138 socket[0] channel[0] rank[0] Write data eye training end
1257 01:19:43.089375
1258 01:19:43.089575 socket[0] channel[0] rank[1] Write data eye training start:
1259 01:19:43.119281 socket[0] channel[0] rank[1] Write data eye training end
1260 01:19:43.119514
1261 01:19:43.119716 socket[0] channel[0] Rx vref training start
1262 01:19:43.490194 socket[0] channel[0] Rx vref training end
1263 01:19:43.490529
1264 01:19:43.490835 socket[0] channel[0] rank[0] Read data eye training start:
1265 01:19:43.529128 socket[0] channel[0] rank[0] Read data eye training end
1266 01:19:43.529361
1267 01:19:43.529564 socket[0] channel[0] rank[1] Read data eye training start:
1268 01:19:43.592660 socket[0] channel[0] rank[1] Read data eye training end
1269 01:19:43.592925
1270 01:19:43.593129 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1271 01:19:43.610579 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1272 01:19:43.610812
1273 01:19:43.611014 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1274 01:19:43.611201 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1275 01:19:43.611394
1276 01:19:43.611585 socket[0] channel[0] Tx vref training start
1277 01:19:45.099340 socket[0] channel[0] Tx vref training end
1278 01:19:45.099701
1279 01:19:45.099909 socket[0] channel[0] rank[0] Write data eye training start:
1280 01:19:45.169146 socket[0] channel[0] rank[0] Write data eye training end
1281 01:19:45.169593
1282 01:19:45.169795 socket[0] channel[0] rank[1] Write data eye training start:
1283 01:19:45.236056 socket[0] channel[0] rank[1] Write data eye training end
1284 01:19:45.236564
1285 01:19:45.236780 //----------------------------------
1286 01:19:45.236994 sfc test rank0
1287 01:19:45.237188 [0]wdata: 0x11111111 - 0x11111111 rdata
1288 01:19:45.237376 [1]wdata: 0x11111111 - 0x11111111 rdata
1289 01:19:45.237564 [2]wdata: 0x22222222 - 0x22222222 rdata
1290 01:19:45.249878 [3]wdata: 0x22222222 - 0x22222222 rdata
1291 01:19:45.250116 [4]wdata: 0x33333333 - 0x33333333 rdata
1292 01:19:45.250318 [5]wdata: 0x33333333 - 0x33333333 rdata
1293 01:19:45.250513 [6]wdata: 0x44444444 - 0x44444444 rdata
1294 01:19:45.250707 [7]wdata: 0x44444444 - 0x44444444 rdata
1295 01:19:45.250911 [8]wdata: 0x55555555 - 0x55555555 rdata
1296 01:19:45.269701 [9]wdata: 0x55555555 - 0x55555555 rdata
1297 01:19:45.270022 [10]wdata: 0x66666666 - 0x66666666 rdata
1298 01:19:45.270249 [11]wdata: 0x66666666 - 0x66666666 rdata
1299 01:19:45.270518 [12]wdata: 0x77777777 - 0x77777777 rdata
1300 01:19:45.270736 [13]wdata: 0x77777777 - 0x77777777 rdata
1301 01:19:45.270973 [14]wdata: 0x88888888 - 0x88888888 rdata
1302 01:19:45.289479 [15]wdata: 0x88888888 - 0x88888888 rdata
1303 01:19:45.289896 [16]wdata: 0x44332211 - 0x44332211 rdata
1304 01:19:45.290220 [17]wdata: 0x88776655 - 0x88776655 rdata
1305 01:19:45.290534 sfc test rank1
1306 01:19:45.290853 [0]wdata: 0x11111111 - 0x11111111 rdata
1307 01:19:45.291167 [1]wdata: 0x11111111 - 0x11111111 rdata
1308 01:19:45.291483 [2]wdata: 0x22222222 - 0x22222222 rdata
1309 01:19:45.309304 [3]wdata: 0x22222222 - 0x22222222 rdata
1310 01:19:45.309756 [4]wdata: 0x33333333 - 0x33333333 rdata
1311 01:19:45.310083 [5]wdata: 0x33333333 - 0x33333333 rdata
1312 01:19:45.310447 [6]wdata: 0x44444444 - 0x44444444 rdata
1313 01:19:45.310760 [7]wdata: 0x44444444 - 0x44444444 rdata
1314 01:19:45.311067 [8]wdata: 0x55555555 - 0x55555555 rdata
1315 01:19:45.329664 [9]wdata: 0x55555555 - 0x55555555 rdata
1316 01:19:45.330141 [10]wdata: 0x66666666 - 0x66666666 rdata
1317 01:19:45.330454 [11]wdata: 0x66666666 - 0x66666666 rdata
1318 01:19:45.330760 [12]wdata: 0x77777777 - 0x77777777 rdata
1319 01:19:45.331066 [13]wdata: 0x77777777 - 0x77777777 rdata
1320 01:19:45.331373 [14]wdata: 0x88888888 - 0x88888888 rdata
1321 01:19:45.359382 [15]wdata: 0x88888888 - 0x88888888 rdata
1322 01:19:45.359678 [16]wdata: 0x44332211 - 0x44332211 rdata
1323 01:19:45.359878 [17]wdata: 0x88776655 - 0x88776655 rdata
1324 01:19:45.360074 //----------------------------------
1325 01:19:45.360265 **********************************************************************
1326 01:19:45.379876 Socket[0] Channel[0] DDR Init Finished!
1327 01:19:45.380110 **********************************************************************
1328 01:19:45.380311 **********************************************************************
1329 01:19:45.380508 Socket[0] Channel[1] Base:[0x60350000] Speed:[2400]
1330 01:19:45.436379 **********************************************************************
1331 01:19:45.436728 ==========================
1332 01:19:45.436946 config parameters from SPD
1333 01:19:45.437141 ==========================
1334 01:19:45.439296 DDR PHY PLL config.....................................OK!
1335 01:19:45.439528 Top module cfg.........................................OK
1336 01:19:45.439731 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1337 01:19:45.439927 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1338 01:19:45.450503 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1339 01:19:45.450739 Dmc init static........................................OK
1340 01:19:45.450966 Phy init dynamic.......................................OK
1341 01:19:45.451199
1342 01:19:45.451412 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1343 01:19:45.460663 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1344 01:19:45.460928 dimm[0] rcd init finished!
1345 01:19:45.461130 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1346 01:19:45.461326 rank[0] sdram init finished!
1347 01:19:45.461517 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1348 01:19:45.461706 rank[1] sdram init finished!
1349 01:19:45.461892 -----------------------------------------------------
1350 01:19:45.481980 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1351 01:19:45.482223 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1352 01:19:45.482424 -----------------------------------------------------
1353 01:19:45.482621 Dram init..............................................OK
1354 01:19:45.529989 socket[0] channel[1] rank[0] Phy gate leveling.....OK
1355 01:19:45.530296 socket[0] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1356 01:19:45.552094 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1357 01:19:45.552329 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1358 01:19:45.552548 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1359 01:19:45.552737 OK
1360 01:19:45.571976 socket[0] channel[1] rank[0] Phy write leveling.....OK
1361 01:19:45.572223 socket[0] channel[1] rank[1] Phy write leveling.....OK
1362 01:19:45.572422 socket[0] channel[1] rank[0] Phy write leveling 2...OK
1363 01:19:45.572649 socket[0] channel[1] rank[1] Phy write leveling 2...OK
1364 01:19:45.639867 socket[0] channel[1] rank[0] Read data eye training start:
1365 01:19:45.640165 socket[0] channel[1] rank[0] Read data eye training end
1366 01:19:45.640365
1367 01:19:45.640581 socket[0] channel[1] rank[1] Read data eye training start:
1368 01:19:45.709162 socket[0] channel[1] rank[1] Read data eye training end
1369 01:19:45.709407
1370 01:19:45.709609 socket[0] channel[1] rank[0] Write data eye training start:
1371 01:19:45.750289 socket[0] channel[1] rank[0] Write data eye training end
1372 01:19:45.750532
1373 01:19:45.750805 socket[0] channel[1] rank[1] Write data eye training start:
1374 01:19:45.819311 socket[0] channel[1] rank[1] Write data eye training end
1375 01:19:45.819681
1376 01:19:45.819874 socket[0] channel[1] Rx vref training start
1377 01:19:46.169411 socket[0] channel[1] Rx vref training end
1378 01:19:46.169842
1379 01:19:46.170144 socket[0] channel[1] rank[0] Read data eye training start:
1380 01:19:46.245605 socket[0] channel[1] rank[0] Read data eye training end
1381 01:19:46.246014
1382 01:19:46.246338 socket[0] channel[1] rank[1] Read data eye training start:
1383 01:19:46.280128 socket[0] channel[1] rank[1] Read data eye training end
1384 01:19:46.280483
1385 01:19:46.280830 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1386 01:19:46.299669 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1387 01:19:46.300028
1388 01:19:46.300372 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1389 01:19:46.300779 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1390 01:19:46.301166
1391 01:19:46.301524 socket[0] channel[1] Tx vref training start
1392 01:19:47.839474 socket[0] channel[1] Tx vref training end
1393 01:19:47.839843
1394 01:19:47.840227 socket[0] channel[1] rank[0] Write data eye training start:
1395 01:19:47.869220 socket[0] channel[1] rank[0] Write data eye training end
1396 01:19:47.869474
1397 01:19:47.869795 socket[0] channel[1] rank[1] Write data eye training start:
1398 01:19:47.909611 socket[0] channel[1] rank[1] Write data eye training end
1399 01:19:47.909874
1400 01:19:47.910201 //----------------------------------
1401 01:19:47.910490 sfc test rank0
1402 01:19:47.929383 [0]wdata: 0x11111111 - 0x11111111 rdata
1403 01:19:47.929616 [1]wdata: 0x11111111 - 0x11111111 rdata
1404 01:19:47.929809 [2]wdata: 0x22222222 - 0x22222222 rdata
1405 01:19:47.929995 [3]wdata: 0x22222222 - 0x22222222 rdata
1406 01:19:47.930176 [4]wdata: 0x33333333 - 0x33333333 rdata
1407 01:19:47.930354 [5]wdata: 0x33333333 - 0x33333333 rdata
1408 01:19:47.954341 [6]wdata: 0x44444444 - 0x44444444 rdata
1409 01:19:47.954734 [7]wdata: 0x44444444 - 0x44444444 rdata
1410 01:19:47.955006 [8]wdata: 0x55555555 - 0x55555555 rdata
1411 01:19:47.955242 [9]wdata: 0x55555555 - 0x55555555 rdata
1412 01:19:47.955452 [10]wdata: 0x66666666 - 0x66666666 rdata
1413 01:19:47.955659 [11]wdata: 0x66666666 - 0x66666666 rdata
1414 01:19:47.972208 [12]wdata: 0x77777777 - 0x77777777 rdata
1415 01:19:47.972564 [13]wdata: 0x77777777 - 0x77777777 rdata
1416 01:19:47.972838 [14]wdata: 0x88888888 - 0x88888888 rdata
1417 01:19:47.973247 [15]wdata: 0x88888888 - 0x88888888 rdata
1418 01:19:47.973480 [16]wdata: 0x44332211 - 0x44332211 rdata
1419 01:19:47.973712 [17]wdata: 0x88776655 - 0x88776655 rdata
1420 01:19:47.973931 sfc test rank1
1421 01:19:47.989557 [0]wdata: 0x11111111 - 0x11111111 rdata
1422 01:19:47.989879 [1]wdata: 0x11111111 - 0x11111111 rdata
1423 01:19:47.990123 [2]wdata: 0x22222222 - 0x22222222 rdata
1424 01:19:47.990402 [3]wdata: 0x22222222 - 0x22222222 rdata
1425 01:19:47.990621 [4]wdata: 0x33333333 - 0x33333333 rdata
1426 01:19:47.990869 [5]wdata: 0x33333333 - 0x33333333 rdata
1427 01:19:48.019248 [6]wdata: 0x44444444 - 0x44444444 rdata
1428 01:19:48.019546 [7]wdata: 0x44444444 - 0x44444444 rdata
1429 01:19:48.019814 [8]wdata: 0x55555555 - 0x55555555 rdata
1430 01:19:48.020071 [9]wdata: 0x55555555 - 0x55555555 rdata
1431 01:19:48.020292 [10]wdata: 0x66666666 - 0x66666666 rdata
1432 01:19:48.020610 [11]wdata: 0x66666666 - 0x66666666 rdata
1433 01:19:48.109269 [12]wdata: 0x77777777 - 0x77777777 rdata
1434 01:19:48.109722 [13]wdata: 0x77777777 - 0x77777777 rdata
1435 01:19:48.110103 [14]wdata: 0x88888888 - 0x88888888 rdata
1436 01:19:48.110423 [15]wdata: 0x88888888 - 0x88888888 rdata
1437 01:19:48.110721 [16]wdata: 0x44332211 - 0x44332211 rdata
1438 01:19:48.111144 [17]wdata: 0x88776655 - 0x88776655 rdata
1439 01:19:48.119767 //----------------------------------
1440 01:19:48.120155 **********************************************************************
1441 01:19:48.120499 Socket[0] Channel[1] DDR Init Finished!
1442 01:19:48.120832 **********************************************************************
1443 01:19:48.129436 **********************************************************************
1444 01:19:48.129817 Socket[0] Channel[2] Base:[0x40340000] Speed:[2400]
1445 01:19:48.130145 **********************************************************************
1446 01:19:48.130448 ==========================
1447 01:19:48.130922 config parameters from SPD
1448 01:19:48.131277 ==========================
1449 01:19:48.139588 DDR PHY PLL config.....................................OK!
1450 01:19:48.140013 Top module cfg.........................................OK
1451 01:19:48.140412 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1452 01:19:48.140920 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1453 01:19:48.149484 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1454 01:19:48.149959 Dmc init static........................................OK
1455 01:19:48.150323 Phy init dynamic.......................................OK
1456 01:19:48.150621
1457 01:19:48.151005 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1458 01:19:48.159487 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1459 01:19:48.159819 dimm[0] rcd init finished!
1460 01:19:48.160183 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1461 01:19:48.160624 rank[0] sdram init finished!
1462 01:19:48.169472 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1463 01:19:48.169815 rank[1] sdram init finished!
1464 01:19:48.170269 -----------------------------------------------------
1465 01:19:48.170712 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1466 01:19:48.171356 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1467 01:19:48.203194 -----------------------------------------------------
1468 01:19:48.203595 Dram init..............................................OK
1469 01:19:48.204141 socket[0] channel[2] rank[0] Phy gate leveling.....OK
1470 01:19:48.220696 socket[0] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1471 01:19:48.221118 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1472 01:19:48.221434 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1473 01:19:48.239232 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1474 01:19:48.239662 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1475 01:19:48.240081 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1476 01:19:48.240425 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1477 01:19:48.240790 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1478 01:19:48.269300 OK
1479 01:19:48.269905 socket[0] channel[2] rank[0] Phy write leveling.....OK
1480 01:19:48.270281 socket[0] channel[2] rank[1] Phy write leveling.....OK
1481 01:19:48.289254 socket[0] channel[2] rank[0] Phy write leveling 2...OK
1482 01:19:48.289713 socket[0] channel[2] rank[1] Phy write leveling 2...OK
1483 01:19:48.290061 socket[0] channel[2] rank[0] Read data eye training start:
1484 01:19:48.360087 socket[0] channel[2] rank[0] Read data eye training end
1485 01:19:48.360836
1486 01:19:48.361270 socket[0] channel[2] rank[1] Read data eye training start:
1487 01:19:48.389341 socket[0] channel[2] rank[1] Read data eye training end
1488 01:19:48.389785
1489 01:19:48.390207 socket[0] channel[2] rank[0] Write data eye training start:
1490 01:19:48.459406 socket[0] channel[2] rank[0] Write data eye training end
1491 01:19:48.459967
1492 01:19:48.460325 socket[0] channel[2] rank[1] Write data eye training start:
1493 01:19:48.550497 socket[0] channel[2] rank[1] Write data eye training end
1494 01:19:48.550915
1495 01:19:48.551311 socket[0] channel[2] Rx vref training start
1496 01:19:48.860585 socket[0] channel[2] Rx vref training end
1497 01:19:48.861084
1498 01:19:48.861565 socket[0] channel[2] rank[0] Read data eye training start:
1499 01:19:48.959572 socket[0] channel[2] rank[0] Read data eye training end
1500 01:19:48.959994
1501 01:19:48.960316 socket[0] channel[2] rank[1] Read data eye training start:
1502 01:19:48.975648 socket[0] channel[2] rank[1] Read data eye training end
1503 01:19:48.975898
1504 01:19:48.976205 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
1505 01:19:48.976558 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
1506 01:19:48.976865
1507 01:19:48.999502 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
1508 01:19:48.999797 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
1509 01:19:49.000124
1510 01:19:49.000484 socket[0] channel[2] Tx vref training start
1511 01:19:50.550464 socket[0] channel[2] Tx vref training end
1512 01:19:50.550974
1513 01:19:50.551259 socket[0] channel[2] rank[0] Write data eye training start:
1514 01:19:50.590985 socket[0] channel[2] rank[0] Write data eye training end
1515 01:19:50.591346
1516 01:19:50.591541 socket[0] channel[2] rank[1] Write data eye training start:
1517 01:19:50.661580 socket[0] channel[2] rank[1] Write data eye training end
1518 01:19:50.661890
1519 01:19:50.662093 //----------------------------------
1520 01:19:50.662289 sfc test rank0
1521 01:19:50.662481 [0]wdata: 0x11111111 - 0x11111111 rdata
1522 01:19:50.662795 [1]wdata: 0x11111111 - 0x11111111 rdata
1523 01:19:50.662989 [2]wdata: 0x22222222 - 0x22222222 rdata
1524 01:19:50.683911 [3]wdata: 0x22222222 - 0x22222222 rdata
1525 01:19:50.684175 [4]wdata: 0x33333333 - 0x33333333 rdata
1526 01:19:50.684376 [5]wdata: 0x33333333 - 0x33333333 rdata
1527 01:19:50.684619 [6]wdata: 0x44444444 - 0x44444444 rdata
1528 01:19:50.684817 [7]wdata: 0x44444444 - 0x44444444 rdata
1529 01:19:50.685024 [8]wdata: 0x55555555 - 0x55555555 rdata
1530 01:19:50.700121 [9]wdata: 0x55555555 - 0x55555555 rdata
1531 01:19:50.700668 [10]wdata: 0x66666666 - 0x66666666 rdata
1532 01:19:50.700874 [11]wdata: 0x66666666 - 0x66666666 rdata
1533 01:19:50.701165 [12]wdata: 0x77777777 - 0x77777777 rdata
1534 01:19:50.701387 [13]wdata: 0x77777777 - 0x77777777 rdata
1535 01:19:50.701580 [14]wdata: 0x88888888 - 0x88888888 rdata
1536 01:19:50.724130 [15]wdata: 0x88888888 - 0x88888888 rdata
1537 01:19:50.724409 [16]wdata: 0x44332211 - 0x44332211 rdata
1538 01:19:50.724650 [17]wdata: 0x88776655 - 0x88776655 rdata
1539 01:19:50.724924 sfc test rank1
1540 01:19:50.725189 [0]wdata: 0x11111111 - 0x11111111 rdata
1541 01:19:50.725384 [1]wdata: 0x11111111 - 0x11111111 rdata
1542 01:19:50.725576 [2]wdata: 0x22222222 - 0x22222222 rdata
1543 01:19:50.749448 [3]wdata: 0x22222222 - 0x22222222 rdata
1544 01:19:50.749782 [4]wdata: 0x33333333 - 0x33333333 rdata
1545 01:19:50.750021 [5]wdata: 0x33333333 - 0x33333333 rdata
1546 01:19:50.750579 [6]wdata: 0x44444444 - 0x44444444 rdata
1547 01:19:50.750803 [7]wdata: 0x44444444 - 0x44444444 rdata
1548 01:19:50.751024 [8]wdata: 0x55555555 - 0x55555555 rdata
1549 01:19:50.769536 [9]wdata: 0x55555555 - 0x55555555 rdata
1550 01:19:50.769794 [10]wdata: 0x66666666 - 0x66666666 rdata
1551 01:19:50.770042 [11]wdata: 0x66666666 - 0x66666666 rdata
1552 01:19:50.770241 [12]wdata: 0x77777777 - 0x77777777 rdata
1553 01:19:50.770481 [13]wdata: 0x77777777 - 0x77777777 rdata
1554 01:19:50.770745 [14]wdata: 0x88888888 - 0x88888888 rdata
1555 01:19:50.793063 [15]wdata: 0x88888888 - 0x88888888 rdata
1556 01:19:50.793500 [16]wdata: 0x44332211 - 0x44332211 rdata
1557 01:19:50.793789 [17]wdata: 0x88776655 - 0x88776655 rdata
1558 01:19:50.794014 //----------------------------------
1559 01:19:50.794235 **********************************************************************
1560 01:19:50.809317 Socket[0] Channel[2] DDR Init Finished!
1561 01:19:50.809584 **********************************************************************
1562 01:19:50.809868 **********************************************************************
1563 01:19:50.810105 Socket[0] Channel[3] Base:[0x40350000] Speed:[2400]
1564 01:19:50.830670 **********************************************************************
1565 01:19:50.831001 ==========================
1566 01:19:50.831225 config parameters from SPD
1567 01:19:50.831443 ==========================
1568 01:19:50.831659 DDR PHY PLL config.....................................OK!
1569 01:19:50.831937 Top module cfg.........................................OK
1570 01:19:50.859222 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1571 01:19:50.859519 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
1572 01:19:50.859789 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
1573 01:19:50.860024 Dmc init static........................................OK
1574 01:19:50.872952 Phy init dynamic.......................................OK
1575 01:19:50.873191
1576 01:19:50.873482 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1577 01:19:50.873705 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1578 01:19:50.891314 dimm[0] rcd init finished!
1579 01:19:50.891616 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1580 01:19:50.891836 rank[0] sdram init finished!
1581 01:19:50.892055 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1582 01:19:50.892270 rank[1] sdram init finished!
1583 01:19:50.892531 -----------------------------------------------------
1584 01:19:50.909679 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1585 01:19:50.909943 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1586 01:19:50.910226 -----------------------------------------------------
1587 01:19:50.910466 Dram init..............................................OK
1588 01:19:50.960026 socket[0] channel[3] rank[0] Phy gate leveling.....OK
1589 01:19:50.960468 socket[0] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1590 01:19:50.972213 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1591 01:19:50.972571 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1592 01:19:50.972850 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1593 01:19:50.973089 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1594 01:19:50.973310 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1595 01:19:50.989658 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1596 01:19:50.989910 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1597 01:19:51.011210 OK
1598 01:19:51.011474 socket[0] channel[3] rank[0] Phy write leveling.....OK
1599 01:19:51.011757 socket[0] channel[3] rank[1] Phy write leveling.....OK
1600 01:19:51.029247 socket[0] channel[3] rank[0] Phy write leveling 2...OK
1601 01:19:51.029497 socket[0] channel[3] rank[1] Phy write leveling 2...OK
1602 01:19:51.029780 socket[0] channel[3] rank[0] Read data eye training start:
1603 01:19:51.099260 socket[0] channel[3] rank[0] Read data eye training end
1604 01:19:51.099689
1605 01:19:51.099985 socket[0] channel[3] rank[1] Read data eye training start:
1606 01:19:51.161023 socket[0] channel[3] rank[1] Read data eye training end
1607 01:19:51.161413
1608 01:19:51.161648 socket[0] channel[3] rank[0] Write data eye training start:
1609 01:19:51.192254 socket[0] channel[3] rank[0] Write data eye training end
1610 01:19:51.192643
1611 01:19:51.192900 socket[0] channel[3] rank[1] Write data eye training start:
1612 01:19:51.262821 socket[0] channel[3] rank[1] Write data eye training end
1613 01:19:51.263200
1614 01:19:51.263570 socket[0] channel[3] Rx vref training start
1615 01:19:51.609420 socket[0] channel[3] Rx vref training end
1616 01:19:51.609845
1617 01:19:51.610085 socket[0] channel[3] rank[0] Read data eye training start:
1618 01:19:51.659420 socket[0] channel[3] rank[0] Read data eye training end
1619 01:19:51.659732
1620 01:19:51.659955 socket[0] channel[3] rank[1] Read data eye training start:
1621 01:19:51.727051 socket[0] channel[3] rank[1] Read data eye training end
1622 01:19:51.727321
1623 01:19:51.727540 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
1624 01:19:51.727755 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
1625 01:19:51.727970
1626 01:19:51.753080 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
1627 01:19:51.753331 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
1628 01:19:51.753566
1629 01:19:51.753796 socket[0] channel[3] Tx vref training start
1630 01:19:53.139997 socket[0] channel[3] Tx vref training end
1631 01:19:53.140421
1632 01:19:53.140687 socket[0] channel[3] rank[0] Write data eye training start:
1633 01:19:53.189214 socket[0] channel[3] rank[0] Write data eye training end
1634 01:19:53.189473
1635 01:19:53.189711 socket[0] channel[3] rank[1] Write data eye training start:
1636 01:19:53.255069 socket[0] channel[3] rank[1] Write data eye training end
1637 01:19:53.255322
1638 01:19:53.255556 //----------------------------------
1639 01:19:53.255782 sfc test rank0
1640 01:19:53.256005 [0]wdata: 0x11111111 - 0x11111111 rdata
1641 01:19:53.256243 [1]wdata: 0x11111111 - 0x11111111 rdata
1642 01:19:53.256440 [2]wdata: 0x22222222 - 0x22222222 rdata
1643 01:19:53.276868 [3]wdata: 0x22222222 - 0x22222222 rdata
1644 01:19:53.277146 [4]wdata: 0x33333333 - 0x33333333 rdata
1645 01:19:53.277386 [5]wdata: 0x33333333 - 0x33333333 rdata
1646 01:19:53.277615 [6]wdata: 0x44444444 - 0x44444444 rdata
1647 01:19:53.277837 [7]wdata: 0x44444444 - 0x44444444 rdata
1648 01:19:53.278054 [8]wdata: 0x55555555 - 0x55555555 rdata
1649 01:19:53.300002 [9]wdata: 0x55555555 - 0x55555555 rdata
1650 01:19:53.300254 [10]wdata: 0x66666666 - 0x66666666 rdata
1651 01:19:53.300482 [11]wdata: 0x66666666 - 0x66666666 rdata
1652 01:19:53.300762 [12]wdata: 0x77777777 - 0x77777777 rdata
1653 01:19:53.301044 [13]wdata: 0x77777777 - 0x77777777 rdata
1654 01:19:53.301274 [14]wdata: 0x88888888 - 0x88888888 rdata
1655 01:19:53.320016 [15]wdata: 0x88888888 - 0x88888888 rdata
1656 01:19:53.320255 [16]wdata: 0x44332211 - 0x44332211 rdata
1657 01:19:53.320482 [17]wdata: 0x88776655 - 0x88776655 rdata
1658 01:19:53.320758 sfc test rank1
1659 01:19:53.320993 [0]wdata: 0x11111111 - 0x11111111 rdata
1660 01:19:53.321246 [1]wdata: 0x11111111 - 0x11111111 rdata
1661 01:19:53.321467 [2]wdata: 0x22222222 - 0x22222222 rdata
1662 01:19:53.340855 [3]wdata: 0x22222222 - 0x22222222 rdata
1663 01:19:53.341130 [4]wdata: 0x33333333 - 0x33333333 rdata
1664 01:19:53.341370 [5]wdata: 0x33333333 - 0x33333333 rdata
1665 01:19:53.341653 [6]wdata: 0x44444444 - 0x44444444 rdata
1666 01:19:53.341883 [7]wdata: 0x44444444 - 0x44444444 rdata
1667 01:19:53.342108 [8]wdata: 0x55555555 - 0x55555555 rdata
1668 01:19:53.364442 [9]wdata: 0x55555555 - 0x55555555 rdata
1669 01:19:53.364777 [10]wdata: 0x66666666 - 0x66666666 rdata
1670 01:19:53.365030 [11]wdata: 0x66666666 - 0x66666666 rdata
1671 01:19:53.365262 [12]wdata: 0x77777777 - 0x77777777 rdata
1672 01:19:53.365486 [13]wdata: 0x77777777 - 0x77777777 rdata
1673 01:19:53.365705 [14]wdata: 0x88888888 - 0x88888888 rdata
1674 01:19:53.386156 [15]wdata: 0x88888888 - 0x88888888 rdata
1675 01:19:53.386715 [16]wdata: 0x44332211 - 0x44332211 rdata
1676 01:19:53.386951 [17]wdata: 0x88776655 - 0x88776655 rdata
1677 01:19:53.387213 //----------------------------------
1678 01:19:53.387439 **********************************************************************
1679 01:19:53.407244 Socket[0] Channel[3] DDR Init Finished!
1680 01:19:53.407525 **********************************************************************
1681 01:19:53.407763 **********************************************************************
1682 01:19:53.407991 Socket[1] Channel[0] Base:[0x40060340000] Speed:[2400]
1683 01:19:53.429245 **********************************************************************
1684 01:19:53.429582 ==========================
1685 01:19:53.429842 config parameters from SPD
1686 01:19:53.430085 ==========================
1687 01:19:53.430656 DDR PHY PLL config.....................................OK!
1688 01:19:53.430931 Top module cfg.........................................OK
1689 01:19:53.451131 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1690 01:19:53.451370 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1691 01:19:53.451597 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1692 01:19:53.451815 Dmc init static........................................OK
1693 01:19:53.466285 Phy init dynamic.......................................OK
1694 01:19:53.466534
1695 01:19:53.466793 [software pad_cal_0]: pvtr=0x1F; pvtn=0x19; pvtp=0xB
1696 01:19:53.467023 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1697 01:19:53.488191 dimm[0] rcd init finished!
1698 01:19:53.488440 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1699 01:19:53.488750 rank[0] sdram init finished!
1700 01:19:53.488988 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1701 01:19:53.489271 rank[1] sdram init finished!
1702 01:19:53.489462 -----------------------------------------------------
1703 01:19:53.511310 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1704 01:19:53.511593 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1705 01:19:53.511820 -----------------------------------------------------
1706 01:19:53.512079 Dram init..............................................OK
1707 01:19:53.571218 socket[1] channel[0] rank[0] Phy gate leveling.....OK
1708 01:19:53.571632 socket[1] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1709 01:19:53.589788 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1710 01:19:53.590171 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1711 01:19:53.590396 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1712 01:19:53.665588 OK
1713 01:19:53.665982 socket[1] channel[0] rank[0] Phy write leveling.....OK
1714 01:19:53.666214 socket[1] channel[0] rank[1] Phy write leveling.....OK
1715 01:19:53.666436 socket[1] channel[0] rank[0] Phy write leveling 2...OK
1716 01:19:53.666653 socket[1] channel[0] rank[1] Phy write leveling 2...OK
1717 01:19:53.691801 socket[1] channel[0] rank[0] Read data eye training start:
1718 01:19:53.719903 socket[1] channel[0] rank[0] Read data eye training end
1719 01:19:53.720319
1720 01:19:53.720622 socket[1] channel[0] rank[1] Read data eye training start:
1721 01:19:53.849863 socket[1] channel[0] rank[1] Read data eye training end
1722 01:19:53.850238
1723 01:19:53.850503 socket[1] channel[0] rank[0] Write data eye training start:
1724 01:19:53.850720 socket[1] channel[0] rank[0] Write data eye training end
1725 01:19:53.850939
1726 01:19:53.851166 socket[1] channel[0] rank[1] Write data eye training start:
1727 01:19:53.914107 socket[1] channel[0] rank[1] Write data eye training end
1728 01:19:53.914457
1729 01:19:53.914686 socket[1] channel[0] Rx vref training start
1730 01:19:54.269359 socket[1] channel[0] Rx vref training end
1731 01:19:54.269817
1732 01:19:54.270091 socket[1] channel[0] rank[0] Read data eye training start:
1733 01:19:54.339465 socket[1] channel[0] rank[0] Read data eye training end
1734 01:19:54.339725
1735 01:19:54.339992 socket[1] channel[0] rank[1] Read data eye training start:
1736 01:19:54.400636 socket[1] channel[0] rank[1] Read data eye training end
1737 01:19:54.400908
1738 01:19:54.401173 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1739 01:19:54.401390 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1740 01:19:54.401667
1741 01:19:54.420126 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1742 01:19:54.420464 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1743 01:19:54.421135
1744 01:19:54.421438 socket[1] channel[0] Tx vref training start
1745 01:19:56.209298 socket[1] channel[0] Tx vref training end
1746 01:19:56.209631
1747 01:19:56.209826 socket[1] channel[0] rank[0] Write data eye training start:
1748 01:19:56.358231 socket[1] channel[0] rank[0] Write data eye training end
1749 01:19:56.358587
1750 01:19:56.358860 socket[1] channel[0] rank[1] Write data eye training start:
1751 01:19:56.369186 socket[1] channel[0] rank[1] Write data eye training end
1752 01:19:56.369419
1753 01:19:56.369666 //----------------------------------
1754 01:19:56.369884 sfc test rank0
1755 01:19:56.370070 [0]wdata: 0x11111111 - 0x11111111 rdata
1756 01:19:56.370282 [1]wdata: 0x11111111 - 0x11111111 rdata
1757 01:19:56.370497 [2]wdata: 0x22222222 - 0x22222222 rdata
1758 01:19:56.381450 [3]wdata: 0x22222222 - 0x22222222 rdata
1759 01:19:56.381715 [4]wdata: 0x33333333 - 0x33333333 rdata
1760 01:19:56.381934 [5]wdata: 0x33333333 - 0x33333333 rdata
1761 01:19:56.382195 [6]wdata: 0x44444444 - 0x44444444 rdata
1762 01:19:56.382458 [7]wdata: 0x44444444 - 0x44444444 rdata
1763 01:19:56.382727 [8]wdata: 0x55555555 - 0x55555555 rdata
1764 01:19:56.393114 [9]wdata: 0x55555555 - 0x55555555 rdata
1765 01:19:56.393404 [10]wdata: 0x66666666 - 0x66666666 rdata
1766 01:19:56.393713 [11]wdata: 0x66666666 - 0x66666666 rdata
1767 01:19:56.393984 [12]wdata: 0x77777777 - 0x77777777 rdata
1768 01:19:56.394273 [13]wdata: 0x77777777 - 0x77777777 rdata
1769 01:19:56.394535 [14]wdata: 0x88888888 - 0x88888888 rdata
1770 01:19:56.414868 [15]wdata: 0x88888888 - 0x88888888 rdata
1771 01:19:56.415223 [16]wdata: 0x44332211 - 0x44332211 rdata
1772 01:19:56.415527 [17]wdata: 0x88776655 - 0x88776655 rdata
1773 01:19:56.415850 sfc test rank1
1774 01:19:56.416126 [0]wdata: 0x11111111 - 0x11111111 rdata
1775 01:19:56.416400 [1]wdata: 0x11111111 - 0x11111111 rdata
1776 01:19:56.416730 [2]wdata: 0x22222222 - 0x22222222 rdata
1777 01:19:56.436654 [3]wdata: 0x22222222 - 0x22222222 rdata
1778 01:19:56.436997 [4]wdata: 0x33333333 - 0x33333333 rdata
1779 01:19:56.437276 [5]wdata: 0x33333333 - 0x33333333 rdata
1780 01:19:56.437546 [6]wdata: 0x44444444 - 0x44444444 rdata
1781 01:19:56.437823 [7]wdata: 0x44444444 - 0x44444444 rdata
1782 01:19:56.438067 [8]wdata: 0x55555555 - 0x55555555 rdata
1783 01:19:56.458482 [9]wdata: 0x55555555 - 0x55555555 rdata
1784 01:19:56.458764 [10]wdata: 0x66666666 - 0x66666666 rdata
1785 01:19:56.459002 [11]wdata: 0x66666666 - 0x66666666 rdata
1786 01:19:56.459235 [12]wdata: 0x77777777 - 0x77777777 rdata
1787 01:19:56.459463 [13]wdata: 0x77777777 - 0x77777777 rdata
1788 01:19:56.459722 [14]wdata: 0x88888888 - 0x88888888 rdata
1789 01:19:56.482195 [15]wdata: 0x88888888 - 0x88888888 rdata
1790 01:19:56.482587 [16]wdata: 0x44332211 - 0x44332211 rdata
1791 01:19:56.482875 [17]wdata: 0x88776655 - 0x88776655 rdata
1792 01:19:56.483165 //----------------------------------
1793 01:19:56.483526 **********************************************************************
1794 01:19:56.541398 Socket[1] Channel[0] DDR Init Finished!
1795 01:19:56.541631 **********************************************************************
1796 01:19:56.550055 **********************************************************************
1797 01:19:56.550296 Socket[1] Channel[1] Base:[0x40060350000] Speed:[2400]
1798 01:19:56.550564 **********************************************************************
1799 01:19:56.550784 ==========================
1800 01:19:56.550998 config parameters from SPD
1801 01:19:56.551211 ==========================
1802 01:19:56.559786 DDR PHY PLL config.....................................OK!
1803 01:19:56.560037 Top module cfg.........................................OK
1804 01:19:56.560279 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1805 01:19:56.560496 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1806 01:19:56.573577 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1807 01:19:56.573824 Dmc init static........................................OK
1808 01:19:56.574056 Phy init dynamic.......................................OK
1809 01:19:56.574283
1810 01:19:56.574540 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1811 01:19:56.575075 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1812 01:19:56.590683 dimm[0] rcd init finished!
1813 01:19:56.590953 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1814 01:19:56.591190 rank[0] sdram init finished!
1815 01:19:56.591411 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1816 01:19:56.591663 rank[1] sdram init finished!
1817 01:19:56.591912 -----------------------------------------------------
1818 01:19:56.620069 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1819 01:19:56.620305 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1820 01:19:56.620542 -----------------------------------------------------
1821 01:19:56.620756 Dram init..............................................OK
1822 01:19:56.665669 socket[1] channel[1] rank[0] Phy gate leveling.....OK
1823 01:19:56.665970 socket[1] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1824 01:19:56.689483 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1825 01:19:56.689868 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1826 01:19:56.690194 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1827 01:19:56.750749 OK
1828 01:19:56.751201 socket[1] channel[1] rank[0] Phy write leveling.....OK
1829 01:19:56.751525 socket[1] channel[1] rank[1] Phy write leveling.....OK
1830 01:19:56.751792 socket[1] channel[1] rank[0] Phy write leveling 2...OK
1831 01:19:56.752055 socket[1] channel[1] rank[1] Phy write leveling 2...OK
1832 01:19:56.769872 socket[1] channel[1] rank[0] Read data eye training start:
1833 01:19:56.810518 socket[1] channel[1] rank[0] Read data eye training end
1834 01:19:56.811011
1835 01:19:56.811429 socket[1] channel[1] rank[1] Read data eye training start:
1836 01:19:56.880604 socket[1] channel[1] rank[1] Read data eye training end
1837 01:19:56.881008
1838 01:19:56.881323 socket[1] channel[1] rank[0] Write data eye training start:
1839 01:19:56.939925 socket[1] channel[1] rank[0] Write data eye training end
1840 01:19:56.940300
1841 01:19:56.940642 socket[1] channel[1] rank[1] Write data eye training start:
1842 01:19:57.009861 socket[1] channel[1] rank[1] Write data eye training end
1843 01:19:57.010387
1844 01:19:57.010699 socket[1] channel[1] Rx vref training start
1845 01:19:57.409567 socket[1] channel[1] Rx vref training end
1846 01:19:57.410051
1847 01:19:57.410404 socket[1] channel[1] rank[0] Read data eye training start:
1848 01:19:57.431937 socket[1] channel[1] rank[0] Read data eye training end
1849 01:19:57.432411
1850 01:19:57.432821 socket[1] channel[1] rank[1] Read data eye training start:
1851 01:19:57.489662 socket[1] channel[1] rank[1] Read data eye training end
1852 01:19:57.490138
1853 01:19:57.490607 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1854 01:19:57.520195 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1855 01:19:57.520767
1856 01:19:57.521262 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1857 01:19:57.521689 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1858 01:19:57.522106
1859 01:19:57.522521 socket[1] channel[1] Tx vref training start
1860 01:19:59.069787 socket[1] channel[1] Tx vref training end
1861 01:19:59.070411
1862 01:19:59.070852 socket[1] channel[1] rank[0] Write data eye training start:
1863 01:19:59.099583 socket[1] channel[1] rank[0] Write data eye training end
1864 01:19:59.100085
1865 01:19:59.100568 socket[1] channel[1] rank[1] Write data eye training start:
1866 01:19:59.194530 socket[1] channel[1] rank[1] Write data eye training end
1867 01:19:59.194797
1868 01:19:59.195016 //----------------------------------
1869 01:19:59.195228 sfc test rank0
1870 01:19:59.195435 [0]wdata: 0x11111111 - 0x11111111 rdata
1871 01:19:59.195643 [1]wdata: 0x11111111 - 0x11111111 rdata
1872 01:19:59.195846 [2]wdata: 0x22222222 - 0x22222222 rdata
1873 01:19:59.209547 [3]wdata: 0x22222222 - 0x22222222 rdata
1874 01:19:59.209905 [4]wdata: 0x33333333 - 0x33333333 rdata
1875 01:19:59.210215 [5]wdata: 0x33333333 - 0x33333333 rdata
1876 01:19:59.210514 [6]wdata: 0x44444444 - 0x44444444 rdata
1877 01:19:59.210808 [7]wdata: 0x44444444 - 0x44444444 rdata
1878 01:19:59.211098 [8]wdata: 0x55555555 - 0x55555555 rdata
1879 01:19:59.219737 [9]wdata: 0x55555555 - 0x55555555 rdata
1880 01:19:59.220174 [10]wdata: 0x66666666 - 0x66666666 rdata
1881 01:19:59.220583 [11]wdata: 0x66666666 - 0x66666666 rdata
1882 01:19:59.220961 [12]wdata: 0x77777777 - 0x77777777 rdata
1883 01:19:59.221314 [13]wdata: 0x77777777 - 0x77777777 rdata
1884 01:19:59.221667 [14]wdata: 0x88888888 - 0x88888888 rdata
1885 01:19:59.231214 [15]wdata: 0x88888888 - 0x88888888 rdata
1886 01:19:59.231690 [16]wdata: 0x44332211 - 0x44332211 rdata
1887 01:19:59.232252 [17]wdata: 0x88776655 - 0x88776655 rdata
1888 01:19:59.232760 sfc test rank1
1889 01:19:59.233280 [0]wdata: 0x11111111 - 0x11111111 rdata
1890 01:19:59.233667 [1]wdata: 0x11111111 - 0x11111111 rdata
1891 01:19:59.234048 [2]wdata: 0x22222222 - 0x22222222 rdata
1892 01:19:59.249745 [3]wdata: 0x22222222 - 0x22222222 rdata
1893 01:19:59.250231 [4]wdata: 0x33333333 - 0x33333333 rdata
1894 01:19:59.250636 [5]wdata: 0x33333333 - 0x33333333 rdata
1895 01:19:59.251186 [6]wdata: 0x44444444 - 0x44444444 rdata
1896 01:19:59.251575 [7]wdata: 0x44444444 - 0x44444444 rdata
1897 01:19:59.251956 [8]wdata: 0x55555555 - 0x55555555 rdata
1898 01:19:59.268224 [9]wdata: 0x55555555 - 0x55555555 rdata
1899 01:19:59.268925 [10]wdata: 0x66666666 - 0x66666666 rdata
1900 01:19:59.269470 [11]wdata: 0x66666666 - 0x66666666 rdata
1901 01:19:59.269931 [12]wdata: 0x77777777 - 0x77777777 rdata
1902 01:19:59.270575 [13]wdata: 0x77777777 - 0x77777777 rdata
1903 01:19:59.270969 [14]wdata: 0x88888888 - 0x88888888 rdata
1904 01:19:59.290671 [15]wdata: 0x88888888 - 0x88888888 rdata
1905 01:19:59.291176 [16]wdata: 0x44332211 - 0x44332211 rdata
1906 01:19:59.291613 [17]wdata: 0x88776655 - 0x88776655 rdata
1907 01:19:59.292036 //----------------------------------
1908 01:19:59.292449 **********************************************************************
1909 01:19:59.315116 Socket[1] Channel[1] DDR Init Finished!
1910 01:19:59.315802 **********************************************************************
1911 01:19:59.316267 **********************************************************************
1912 01:19:59.316782 Socket[1] Channel[2] Base:[0x40040340000] Speed:[2400]
1913 01:19:59.334929 **********************************************************************
1914 01:19:59.335454 ==========================
1915 01:19:59.335890 config parameters from SPD
1916 01:19:59.336310 ==========================
1917 01:19:59.336839 DDR PHY PLL config.....................................OK!
1918 01:19:59.337314 Top module cfg.........................................OK
1919 01:19:59.356489 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1920 01:19:59.357407 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1921 01:19:59.357893 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1922 01:19:59.358548 Dmc init static........................................OK
1923 01:19:59.370551 Phy init dynamic.......................................OK
1924 01:19:59.370953
1925 01:19:59.371364 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1C; pvtp=0xC
1926 01:19:59.371780 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1927 01:19:59.390689 dimm[0] rcd init finished!
1928 01:19:59.391218 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1929 01:19:59.391695 rank[0] sdram init finished!
1930 01:19:59.392088 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1931 01:19:59.392836 rank[1] sdram init finished!
1932 01:19:59.393340 -----------------------------------------------------
1933 01:19:59.464069 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1934 01:19:59.464676 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1935 01:19:59.465226 -----------------------------------------------------
1936 01:19:59.465670 Dram init..............................................OK
1937 01:19:59.466183 socket[1] channel[2] rank[0] Phy gate leveling.....OK
1938 01:19:59.486188 socket[1] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1939 01:19:59.486693 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1940 01:19:59.487132 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1941 01:19:59.509793 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1942 01:19:59.510234 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1943 01:19:59.510586 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1944 01:19:59.510924 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1945 01:19:59.511309 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1946 01:19:59.555953 OK
1947 01:19:59.556585 socket[1] channel[2] rank[0] Phy write leveling.....OK
1948 01:19:59.557060 socket[1] channel[2] rank[1] Phy write leveling.....OK
1949 01:19:59.580601 socket[1] channel[2] rank[0] Phy write leveling 2...OK
1950 01:19:59.581137 socket[1] channel[2] rank[1] Phy write leveling 2...OK
1951 01:19:59.581727 socket[1] channel[2] rank[0] Read data eye training start:
1952 01:19:59.650043 socket[1] channel[2] rank[0] Read data eye training end
1953 01:19:59.650566
1954 01:19:59.651070 socket[1] channel[2] rank[1] Read data eye training start:
1955 01:19:59.699756 socket[1] channel[2] rank[1] Read data eye training end
1956 01:19:59.700311
1957 01:19:59.700836 socket[1] channel[2] rank[0] Write data eye training start:
1958 01:19:59.759553 socket[1] channel[2] rank[0] Write data eye training end
1959 01:19:59.760047
1960 01:19:59.760461 socket[1] channel[2] rank[1] Write data eye training start:
1961 01:19:59.860017 socket[1] channel[2] rank[1] Write data eye training end
1962 01:19:59.860510
1963 01:19:59.861040 socket[1] channel[2] Rx vref training start
1964 01:20:00.180741 socket[1] channel[2] Rx vref training end
1965 01:20:00.181342
1966 01:20:00.181777 socket[1] channel[2] rank[0] Read data eye training start:
1967 01:20:00.279577 socket[1] channel[2] rank[0] Read data eye training end
1968 01:20:00.280089
1969 01:20:00.280568 socket[1] channel[2] rank[1] Read data eye training start:
1970 01:20:00.305349 socket[1] channel[2] rank[1] Read data eye training end
1971 01:20:00.305747
1972 01:20:00.306128 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
1973 01:20:00.306506 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
1974 01:20:00.306873
1975 01:20:00.329562 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
1976 01:20:00.329980 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
1977 01:20:00.330330
1978 01:20:00.330677 socket[1] channel[2] Tx vref training start
1979 01:20:01.970114 socket[1] channel[2] Tx vref training end
1980 01:20:01.970498
1981 01:20:01.970694 socket[1] channel[2] rank[0] Write data eye training start:
1982 01:20:02.029355 socket[1] channel[2] rank[0] Write data eye training end
1983 01:20:02.029650
1984 01:20:02.029843 socket[1] channel[2] rank[1] Write data eye training start:
1985 01:20:02.102623 socket[1] channel[2] rank[1] Write data eye training end
1986 01:20:02.102872
1987 01:20:02.103064 //----------------------------------
1988 01:20:02.103247 sfc test rank0
1989 01:20:02.103427 [0]wdata: 0x11111111 - 0x11111111 rdata
1990 01:20:02.103606 [1]wdata: 0x11111111 - 0x11111111 rdata
1991 01:20:02.103784 [2]wdata: 0x22222222 - 0x22222222 rdata
1992 01:20:02.122809 [3]wdata: 0x22222222 - 0x22222222 rdata
1993 01:20:02.123033 [4]wdata: 0x33333333 - 0x33333333 rdata
1994 01:20:02.123247 [5]wdata: 0x33333333 - 0x33333333 rdata
1995 01:20:02.123456 [6]wdata: 0x44444444 - 0x44444444 rdata
1996 01:20:02.123668 [7]wdata: 0x44444444 - 0x44444444 rdata
1997 01:20:02.123873 [8]wdata: 0x55555555 - 0x55555555 rdata
1998 01:20:02.144701 [9]wdata: 0x55555555 - 0x55555555 rdata
1999 01:20:02.144939 [10]wdata: 0x66666666 - 0x66666666 rdata
2000 01:20:02.145131 [11]wdata: 0x66666666 - 0x66666666 rdata
2001 01:20:02.145316 [12]wdata: 0x77777777 - 0x77777777 rdata
2002 01:20:02.145496 [13]wdata: 0x77777777 - 0x77777777 rdata
2003 01:20:02.145676 [14]wdata: 0x88888888 - 0x88888888 rdata
2004 01:20:02.166693 [15]wdata: 0x88888888 - 0x88888888 rdata
2005 01:20:02.166954 [16]wdata: 0x44332211 - 0x44332211 rdata
2006 01:20:02.167308 [17]wdata: 0x88776655 - 0x88776655 rdata
2007 01:20:02.167606 sfc test rank1
2008 01:20:02.167805 [0]wdata: 0x11111111 - 0x11111111 rdata
2009 01:20:02.168027 [1]wdata: 0x11111111 - 0x11111111 rdata
2010 01:20:02.168229 [2]wdata: 0x22222222 - 0x22222222 rdata
2011 01:20:02.188492 [3]wdata: 0x22222222 - 0x22222222 rdata
2012 01:20:02.188748 [4]wdata: 0x33333333 - 0x33333333 rdata
2013 01:20:02.188962 [5]wdata: 0x33333333 - 0x33333333 rdata
2014 01:20:02.189437 [6]wdata: 0x44444444 - 0x44444444 rdata
2015 01:20:02.189633 [7]wdata: 0x44444444 - 0x44444444 rdata
2016 01:20:02.189823 [8]wdata: 0x55555555 - 0x55555555 rdata
2017 01:20:02.210213 [9]wdata: 0x55555555 - 0x55555555 rdata
2018 01:20:02.210435 [10]wdata: 0x66666666 - 0x66666666 rdata
2019 01:20:02.210627 [11]wdata: 0x66666666 - 0x66666666 rdata
2020 01:20:02.210816 [12]wdata: 0x77777777 - 0x77777777 rdata
2021 01:20:02.210999 [13]wdata: 0x77777777 - 0x77777777 rdata
2022 01:20:02.211179 [14]wdata: 0x88888888 - 0x88888888 rdata
2023 01:20:02.232079 [15]wdata: 0x88888888 - 0x88888888 rdata
2024 01:20:02.232342 [16]wdata: 0x44332211 - 0x44332211 rdata
2025 01:20:02.232570 [17]wdata: 0x88776655 - 0x88776655 rdata
2026 01:20:02.232757 //----------------------------------
2027 01:20:02.233390 **********************************************************************
2028 01:20:02.253201 Socket[1] Channel[2] DDR Init Finished!
2029 01:20:02.253472 **********************************************************************
2030 01:20:02.253683 **********************************************************************
2031 01:20:02.253872 Socket[1] Channel[3] Base:[0x40040350000] Speed:[2400]
2032 01:20:02.276840 **********************************************************************
2033 01:20:02.277084 ==========================
2034 01:20:02.277304 config parameters from SPD
2035 01:20:02.277492 ==========================
2036 01:20:02.277685 DDR PHY PLL config.....................................OK!
2037 01:20:02.277875 Top module cfg.........................................OK
2038 01:20:02.298798 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
2039 01:20:02.299015 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
2040 01:20:02.299218 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
2041 01:20:02.299415 Dmc init static........................................OK
2042 01:20:02.312338 Phy init dynamic.......................................OK
2043 01:20:02.312592
2044 01:20:02.312796 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
2045 01:20:02.313010 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
2046 01:20:02.334232 dimm[0] rcd init finished!
2047 01:20:02.334467 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2048 01:20:02.334668 rank[0] sdram init finished!
2049 01:20:02.334861 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2050 01:20:02.335052 rank[1] sdram init finished!
2051 01:20:02.335242 -----------------------------------------------------
2052 01:20:02.359266 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
2053 01:20:02.359501 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
2054 01:20:02.359695 -----------------------------------------------------
2055 01:20:02.359892 Dram init..............................................OK
2056 01:20:02.416464 socket[1] channel[3] rank[0] Phy gate leveling.....OK
2057 01:20:02.416738 socket[1] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
2058 01:20:02.436219 lat_adj_start of rank 1 byte 1 is set to 0x00000001
2059 01:20:02.436480 lat_adj_start of rank 1 byte 2 is set to 0x00000001
2060 01:20:02.436737 lat_adj_start of rank 1 byte 3 is set to 0x00000001
2061 01:20:02.436971 lat_adj_start of rank 1 byte 4 is set to 0x00000001
2062 01:20:02.437164 lat_adj_start of rank 1 byte 5 is set to 0x00000001
2063 01:20:02.460092 lat_adj_start of rank 1 byte 6 is set to 0x00000001
2064 01:20:02.460353 lat_adj_start of rank 1 byte 7 is set to 0x00000001
2065 01:20:02.496615 OK
2066 01:20:02.496848 socket[1] channel[3] rank[0] Phy write leveling.....OK
2067 01:20:02.497071 socket[1] channel[3] rank[1] Phy write leveling.....OK
2068 01:20:02.519361 socket[1] channel[3] rank[0] Phy write leveling 2...OK
2069 01:20:02.519592 socket[1] channel[3] rank[1] Phy write leveling 2...OK
2070 01:20:02.519792 socket[1] channel[3] rank[0] Read data eye training start:
2071 01:20:02.589395 socket[1] channel[3] rank[0] Read data eye training end
2072 01:20:02.589699
2073 01:20:02.589963 socket[1] channel[3] rank[1] Read data eye training start:
2074 01:20:02.639417 socket[1] channel[3] rank[1] Read data eye training end
2075 01:20:02.639664
2076 01:20:02.639914 socket[1] channel[3] rank[0] Write data eye training start:
2077 01:20:02.769279 socket[1] channel[3] rank[0] Write data eye training end
2078 01:20:02.769574
2079 01:20:02.769767 socket[1] channel[3] rank[1] Write data eye training start:
2080 01:20:02.769960 socket[1] channel[3] rank[1] Write data eye training end
2081 01:20:02.770150
2082 01:20:02.770338 socket[1] channel[3] Rx vref training start
2083 01:20:03.141489 socket[1] channel[3] Rx vref training end
2084 01:20:03.141847
2085 01:20:03.142052 socket[1] channel[3] rank[0] Read data eye training start:
2086 01:20:03.245012 socket[1] channel[3] rank[0] Read data eye training end
2087 01:20:03.245398
2088 01:20:03.245680 socket[1] channel[3] rank[1] Read data eye training start:
2089 01:20:03.245949 socket[1] channel[3] rank[1] Read data eye training end
2090 01:20:03.246230
2091 01:20:03.246517 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
2092 01:20:03.270271 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
2093 01:20:03.270536
2094 01:20:03.270739 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
2095 01:20:03.270936 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
2096 01:20:03.271128
2097 01:20:03.271335 socket[1] channel[3] Tx vref training start
2098 01:20:04.849380 socket[1] channel[3] Tx vref training end
2099 01:20:04.849800
2100 01:20:04.850081 socket[1] channel[3] rank[0] Write data eye training start:
2101 01:20:04.929457 socket[1] channel[3] rank[0] Write data eye training end
2102 01:20:04.929882
2103 01:20:04.930179 socket[1] channel[3] rank[1] Write data eye training start:
2104 01:20:04.986379 socket[1] channel[3] rank[1] Write data eye training end
2105 01:20:04.986726
2106 01:20:04.987018 //----------------------------------
2107 01:20:04.987302 sfc test rank0
2108 01:20:04.987579 [0]wdata: 0x11111111 - 0x11111111 rdata
2109 01:20:04.987854 [1]wdata: 0x11111111 - 0x11111111 rdata
2110 01:20:04.988129 [2]wdata: 0x22222222 - 0x22222222 rdata
2111 01:20:05.008566 [3]wdata: 0x22222222 - 0x22222222 rdata
2112 01:20:05.009038 [4]wdata: 0x33333333 - 0x33333333 rdata
2113 01:20:05.009414 [5]wdata: 0x33333333 - 0x33333333 rdata
2114 01:20:05.009792 [6]wdata: 0x44444444 - 0x44444444 rdata
2115 01:20:05.010072 [7]wdata: 0x44444444 - 0x44444444 rdata
2116 01:20:05.010347 [8]wdata: 0x55555555 - 0x55555555 rdata
2117 01:20:05.031484 [9]wdata: 0x55555555 - 0x55555555 rdata
2118 01:20:05.031953 [10]wdata: 0x66666666 - 0x66666666 rdata
2119 01:20:05.032263 [11]wdata: 0x66666666 - 0x66666666 rdata
2120 01:20:05.032583 [12]wdata: 0x77777777 - 0x77777777 rdata
2121 01:20:05.032862 [13]wdata: 0x77777777 - 0x77777777 rdata
2122 01:20:05.033168 [14]wdata: 0x88888888 - 0x88888888 rdata
2123 01:20:05.054106 [15]wdata: 0x88888888 - 0x88888888 rdata
2124 01:20:05.054542 [16]wdata: 0x44332211 - 0x44332211 rdata
2125 01:20:05.054916 [17]wdata: 0x88776655 - 0x88776655 rdata
2126 01:20:05.055242 sfc test rank1
2127 01:20:05.055517 [0]wdata: 0x11111111 - 0x11111111 rdata
2128 01:20:05.055790 [1]wdata: 0x11111111 - 0x11111111 rdata
2129 01:20:05.056071 [2]wdata: 0x22222222 - 0x22222222 rdata
2130 01:20:05.073496 [3]wdata: 0x22222222 - 0x22222222 rdata
2131 01:20:05.073942 [4]wdata: 0x33333333 - 0x33333333 rdata
2132 01:20:05.074178 [5]wdata: 0x33333333 - 0x33333333 rdata
2133 01:20:05.074392 [6]wdata: 0x44444444 - 0x44444444 rdata
2134 01:20:05.074600 [7]wdata: 0x44444444 - 0x44444444 rdata
2135 01:20:05.074807 [8]wdata: 0x55555555 - 0x55555555 rdata
2136 01:20:05.095498 [9]wdata: 0x55555555 - 0x55555555 rdata
2137 01:20:05.095880 [10]wdata: 0x66666666 - 0x66666666 rdata
2138 01:20:05.096209 [11]wdata: 0x66666666 - 0x66666666 rdata
2139 01:20:05.096572 [12]wdata: 0x77777777 - 0x77777777 rdata
2140 01:20:05.096854 [13]wdata: 0x77777777 - 0x77777777 rdata
2141 01:20:05.097153 [14]wdata: 0x88888888 - 0x88888888 rdata
2142 01:20:05.117285 [15]wdata: 0x88888888 - 0x88888888 rdata
2143 01:20:05.117625 [16]wdata: 0x44332211 - 0x44332211 rdata
2144 01:20:05.117918 [17]wdata: 0x88776655 - 0x88776655 rdata
2145 01:20:05.118198 //----------------------------------
2146 01:20:05.118475 **********************************************************************
2147 01:20:05.177438 Socket[1] Channel[3] DDR Init Finished!
2148 01:20:05.177782 **********************************************************************
2149 01:20:05.189613 ========================================================================================
2150 01:20:05.190062 | socekt 0 |
2151 01:20:05.190361 ========================================================================================
2152 01:20:05.216062 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2153 01:20:05.216499 ========================================================================================
2154 01:20:05.216945 | 0 | Samsung | Samsung | Samsung | Samsung |
2155 01:20:05.230044 | | Montage | Montage | Montage | Montage |
2156 01:20:05.230389 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2157 01:20:05.240626 | | 2400 | 2400 | 2400 | 2400 |
2158 01:20:05.240977 | | ww282017 | ww282017 | ww282017 | ww282017 |
2159 01:20:05.241272 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2160 01:20:05.249590 | | | | | |
2161 01:20:05.249942 ----------------------------------------------------------------------------------------
2162 01:20:05.250239 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2163 01:20:05.260088 | | | | | |
2164 01:20:05.260416 | | | | | |
2165 01:20:05.260752 | | | | | |
2166 01:20:05.279899 | | | | | |
2167 01:20:05.280329 | | | | | |
2168 01:20:05.280698 | | | | | |
2169 01:20:05.302824 ----------------------------------------------------------------------------------------
2170 01:20:05.303168 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2171 01:20:05.324914 | | | | | |
2172 01:20:05.325151 | | | | | |
2173 01:20:05.325352 | | | | | |
2174 01:20:05.347073 | | | | | |
2175 01:20:05.347513 | | | | | |
2176 01:20:05.347894 | | | | | |
2177 01:20:05.369190 ----------------------------------------------------------------------------------------
2178 01:20:05.369601 ========================================================================================
2179 01:20:05.369892 | socekt 1 |
2180 01:20:05.390267 ========================================================================================
2181 01:20:05.390609 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2182 01:20:05.390904 ========================================================================================
2183 01:20:05.453669 | 0 | Samsung | Samsung | Samsung | Samsung |
2184 01:20:05.469631 | | Montage | Montage | Montage | Montage |
2185 01:20:05.470039 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2186 01:20:05.470393 | | 2400 | 2400 | 2400 | 2400 |
2187 01:20:05.481039 | | ww282017 | ww282017 | ww282017 | ww282017 |
2188 01:20:05.481393 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2189 01:20:05.481697 | | | | | |
2190 01:20:05.489669
2191 01:20:05.489982 ----------------------------------------------------------------------------------------
2192 01:20:05.490252 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2193 01:20:05.500488 | | | | | |
2194 01:20:05.500754 | | | | | |
2195 01:20:05.500980 | | | | | |
2196 01:20:05.511038 | | | | | |
2197 01:20:05.511270 | | | | | |
2198 01:20:05.511552 | | | | | |
2199 01:20:05.529638 ----------------------------------------------------------------------------------------
2200 01:20:05.529880 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2201 01:20:05.530093 | | | | | |
2202 01:20:05.555093 | | | | | |
2203 01:20:05.555356 | | | | | |
2204 01:20:05.629294 | | | | | |
2205 01:20:05.629536 | | | | | |
2206 01:20:05.629744 | | | | | |
2207 01:20:05.640130 ----------------------------------------------------------------------------------------
2208 01:20:05.640398 socket[0] channel[0] rank[0] memory clean start.
2209 01:20:05.640663 socket[0] channel[1] rank[0] memory clean start.
2210 01:20:05.640891 socket[0] channel[2] rank[0] memory clean start.
2211 01:20:05.641110 socket[0] channel[3] rank[0] memory clean start.
2212 01:20:05.660003 socket[1] channel[0] rank[0] memory clean start.
2213 01:20:05.660237 socket[1] channel[1] rank[0] memory clean start.
2214 01:20:05.660448 socket[1] channel[2] rank[0] memory clean start.
2215 01:20:05.660699 socket[1] channel[3] rank[0] memory clean start.
2216 01:20:06.653116 all rank[0] memory clean ok!
2217 01:20:06.653497
2218 01:20:06.653714 socket[0] channel[0] rank[0] memory clean read start.
2219 01:20:06.653938 socket[0] channel[1] rank[0] memory clean read start.
2220 01:20:06.654155 socket[0] channel[2] rank[0] memory clean read start.
2221 01:20:06.654372 socket[0] channel[3] rank[0] memory clean read start.
2222 01:20:06.679427 socket[1] channel[0] rank[0] memory clean read start.
2223 01:20:06.679789 socket[1] channel[1] rank[0] memory clean read start.
2224 01:20:06.680107 socket[1] channel[2] rank[0] memory clean read start.
2225 01:20:06.680408 socket[1] channel[3] rank[0] memory clean read start.
2226 01:20:07.705512 all rank[0] memory clean read ok!
2227 01:20:07.706067
2228 01:20:07.706423 socket[0] channel[0] rank[1] memory clean start.
2229 01:20:07.706766 socket[0] channel[1] rank[1] memory clean start.
2230 01:20:07.707101 socket[0] channel[2] rank[1] memory clean start.
2231 01:20:07.707432 socket[0] channel[3] rank[1] memory clean start.
2232 01:20:07.776416 socket[1] channel[0] rank[1] memory clean start.
2233 01:20:07.776860 socket[1] channel[1] rank[1] memory clean start.
2234 01:20:07.777220 socket[1] channel[2] rank[1] memory clean start.
2235 01:20:07.777537 socket[1] channel[3] rank[1] memory clean start.
2236 01:20:08.758397 all rank[1] memory clean ok!
2237 01:20:08.758805
2238 01:20:08.759172 socket[0] channel[0] rank[1] memory clean read start.
2239 01:20:08.759369 socket[0] channel[1] rank[1] memory clean read start.
2240 01:20:08.759561 socket[0] channel[2] rank[1] memory clean read start.
2241 01:20:08.759749 socket[0] channel[3] rank[1] memory clean read start.
2242 01:20:08.780941 socket[1] channel[0] rank[1] memory clean read start.
2243 01:20:08.781297 socket[1] channel[1] rank[1] memory clean read start.
2244 01:20:08.781624 socket[1] channel[2] rank[1] memory clean read start.
2245 01:20:08.781932 socket[1] channel[3] rank[1] memory clean read start.
2246 01:20:09.790765 all rank[1] memory clean read ok!
2247 01:20:09.791306
2248 01:20:09.819598 RAM Diagnose or not ?
2249 01:20:09.819997 (Press 'Ctrl+t' or 'Ctrl+T' to Begin Memory Diagnose)
2250 01:20:12.847811 Now wait for 3 seconds...
2251 01:20:12.848233 Not Press 'Ctrl+t' or 'Ctrl+T', The RAM Diagnose Exit
2252 01:20:12.848532 Start config DAW.
2253 01:20:12.848837 Record Interrupts
2254 01:20:12.849141 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC0] = 0xB0111168
2255 01:20:12.849430 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC1] = 0xA0311168
2256 01:20:12.864096 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC0] = 0x10201001
2257 01:20:12.864379 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC1] = 0x80301164
2258 01:20:12.864683 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC0] = 0x16223
2259 01:20:12.864958 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC1] = 0x403101
2260 01:20:12.886294 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC0] = 0x613010
2261 01:20:12.886725 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC1] = 0xB07132
2262 01:20:12.887006 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT0] = 0x8A
2263 01:20:12.887261 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT0] = 0x10
2264 01:20:12.910104 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT0] = 0x220
2265 01:20:12.910365 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT0] = 0x609
2266 01:20:12.922274 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT0] = 0x40
2267 01:20:12.922593 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT0] = 0x28
2268 01:20:12.922895 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT0] = 0x4
2269 01:20:12.923198 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT1] = 0x8089
2270 01:20:12.939337 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT1] = 0x180
2271 01:20:12.939643 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT1] = 0x4A00C0
2272 01:20:12.957020 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT1] = 0x42AC0C
2273 01:20:12.957299 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT1] = 0x4404
2274 01:20:12.957601 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT1] = 0x5940
2275 01:20:12.957892 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT0] = 0x6
2276 01:20:12.979622 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT0] = 0x16
2277 01:20:12.979939 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT0] = 0x30
2278 01:20:13.032353 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT0] = 0x10
2279 01:20:13.032711 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT0] = 0x2
2280 01:20:13.033042 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT0] = 0x40
2281 01:20:13.033350 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT1] = 0x1400
2282 01:20:13.040255 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT1] = 0x22C4
2283 01:20:13.040567 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT1] = 0xC044
2284 01:20:13.040864 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT1] = 0x80820
2285 01:20:13.041175 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT1] = 0x9048
2286 01:20:13.050006 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT1] = 0xF06
2287 01:20:13.050300 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS6_INT1] = 0x181
2288 01:20:13.050601 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT0] = 0x68
2289 01:20:13.050890 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT0] = 0xF4
2290 01:20:13.063636 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT0] = 0x74
2291 01:20:13.063940 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT1] = 0x3CAC
2292 01:20:13.080652 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT1] = 0x2410
2293 01:20:13.080950 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT1] = 0x41
2294 01:20:13.081277 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT0] = 0xEC
2295 01:20:13.081593 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT0] = 0x3B
2296 01:20:13.098020 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT0] = 0xFC
2297 01:20:13.098392 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT1] = 0xB144
2298 01:20:13.098817 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT1] = 0x306D
2299 01:20:13.099257 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT1] = 0xA8B1
2300 01:20:13.119538 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA0] = 0x88030
2301 01:20:13.119829 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA1] = 0x400
2302 01:20:13.131540 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA0] = 0x9121
2303 01:20:13.131825 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA1] = 0x80200
2304 01:20:13.132124 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC0] = 0x280
2305 01:20:13.132421 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC1] = 0xA80
2306 01:20:13.159545 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC3] = 0x20000
2307 01:20:13.159922 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC0] = 0x400
2308 01:20:13.170945 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC1] = 0x4020
2309 01:20:13.171268 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC2] = 0x10001
2310 01:20:13.171619 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC3] = 0x1280
2311 01:20:13.171973 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER0] = 0x3
2312 01:20:13.189597 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER1] = 0x4
2313 01:20:13.189911 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER2] = 0x3
2314 01:20:13.190216 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER3] = 0x2
2315 01:20:13.190519 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_POE] = 0x7
2316 01:20:13.266679 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER3] = 0x2
2317 01:20:13.267010 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_POE] = 0x7
2318 01:20:13.267316 Interrupt Status:[SocketId: 0] [DieId: 0] [AA_SAS] = 0x1
2319 01:20:13.267613 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_ALG] = 0x3
2320 01:20:13.279433 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_PCIE] = 0x2
2321 01:20:13.279651 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_SAS] = 0x1
2322 01:20:13.279854 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_SRAM] = 0x8
2323 01:20:13.280053 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_SRAM] = 0xEB
2324 01:20:13.289312 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC0] = 0x9111115C
2325 01:20:13.289633 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC1] = 0xE1501000
2326 01:20:13.289963 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC0] = 0xC1001178
2327 01:20:13.290294 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC1] = 0xA0111040
2328 01:20:13.300332 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC0] = 0xA10321
2329 01:20:13.300602 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC1] = 0x207222
2330 01:20:13.300808 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC0] = 0x31A022
2331 01:20:13.301030 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC1] = 0x6110
2332 01:20:13.309540 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT0] = 0x60
2333 01:20:13.309854 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT0] = 0x20
2334 01:20:13.310142 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT0] = 0xA
2335 01:20:13.310443 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT0] = 0x413
2336 01:20:13.339311 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT0] = 0x10
2337 01:20:13.339581 23061
2338 01:20:13.339900 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT1] = 0x201
2339 01:20:13.340243 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS5_INT1] = 0xB5E
2340 01:20:13.340580 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS6_INT1] = 0x1D55
2341 01:20:13.361900 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT0] = 0x800
2342 01:20:13.362210 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS3_INT0] = 0x200
2343 01:20:13.362509 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT0] = 0x84
2344 01:20:13.382266 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT0] = 0x20
2345 01:20:13.382551 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT0] = 0x8C
2346 01:20:13.382867 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT1] = 0x100
2347 01:20:13.383226 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS1_INT1] = 0x5CCD
2348 01:20:13.400313 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT1] = 0x3CACC
2349 01:20:13.400766 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS3_INT1] = 0x58388
2350 01:20:13.401227 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT1] = 0x4180
2351 01:20:13.401664 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT1] = 0x8882
2352 01:20:13.425239 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT1] = 0xB104
2353 01:20:13.426059 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT0] = 0x60
2354 01:20:13.426912 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT0] = 0x3C
2355 01:20:13.427421 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT0] = 0xC9
2356 01:20:13.446792 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT1] = 0x810
2357 01:20:13.447099 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT1] = 0x3063
2358 01:20:13.447395 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT1] = 0x400D
2359 01:20:13.447688 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT0] = 0x8
2360 01:20:13.508619 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT0] = 0xE
2361 01:20:13.509160 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT1] = 0xA07C
2362 01:20:13.520497 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS1_INT1] = 0x4940
2363 01:20:13.520829 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT1] = 0x2D0C
2364 01:20:13.521147 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA0] = 0xC019
2365 01:20:13.521441 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA1] = 0x8A041
2366 01:20:13.529284 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA0] = 0x30
2367 01:20:13.529557 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA1] = 0x48002
2368 01:20:13.529891 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC0] = 0x8200
2369 01:20:13.530223 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC3] = 0x20
2370 01:20:13.530556 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC0] = 0x5000
2371 01:20:13.540665 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC2] = 0x20
2372 01:20:13.541088 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_CLUSTER3] = 0x2
2373 01:20:13.541525 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_POE] = 0x6
2374 01:20:13.560546 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER1] = 0x2
2375 01:20:13.561038 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER3] = 0x1
2376 01:20:13.561499 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_POE] = 0x2
2377 01:20:13.561955 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_ALG] = 0x1
2378 01:20:13.580284 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_PCIE] = 0x2
2379 01:20:13.580719 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_ALG] = 0x1
2380 01:20:13.581195 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_SAS] = 0x1
2381 01:20:13.581649 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_SRAM] = 0xFD
2382 01:20:13.613100 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_SRAM] = 0x7B
2383 01:20:13.613635 Clear Interrupts
2384 01:20:13.614205 Clear DDRC
2385 01:20:13.614752 Clear RASC
2386 01:20:13.615299 Clear CS
2387 01:20:13.615869 Clear SLLC
2388 01:20:13.616383 Clear HHA
2389 01:20:13.616986 Clear LLC
2390 01:20:13.645266 Clear AA
2391 01:20:13.645737 Clear SRAM
2392 01:20:13.646309 Clear DDRC
2393 01:20:13.646896 Clear RASC
2394 01:20:13.647454 Clear CS
2395 01:20:13.647912 Clear SLLC
2396 01:20:13.648458 Clear HHA
2397 01:20:13.649096 Clear LLC
2398 01:20:13.649628 Clear AA
2399 01:20:13.650174 Clear SRAM
2400 01:20:13.650698 Clear Interrupt End
2401 01:20:13.651206 Enable Channel Interleave for socket[0]
2402 01:20:13.651642 Enable Channel Interleave for socket[0]
2403 01:20:13.659465 Daw Cinfig :Skt 0 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2404 01:20:13.659868 ColBits = 0xA
2405 01:20:13.660255 RowBits = 0x11
2406 01:20:13.660670 Banknum = 0x10
2407 01:20:13.661073 RankSize = 0x400000000
2408 01:20:13.661446 Ranknum = 0x2
2409 01:20:13.661819 DramWidth = 0x4
2410 01:20:13.662189 Size = 0x1000000000
2411 01:20:13.662560 Daw Config: Skt 0 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2412 01:20:13.669549 LowMemory(<4G):Base=0x0, Size=0x40000000
2413 01:20:13.669958 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2414 01:20:13.670401 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2415 01:20:13.679414 HighMemory(>4G):Base=0x1800000000, Size=0x7FC000000
2416 01:20:13.679860 ColBits = 0xA
2417 01:20:13.680354 RowBits = 0x11
2418 01:20:13.680971 Banknum = 0x10
2419 01:20:13.681449 RankSize = 0x400000000
2420 01:20:13.681917 Ranknum = 0x2
2421 01:20:13.682437 DramWidth = 0x4
2422 01:20:13.682928 Size = 0x1000000000
2423 01:20:13.689693 Daw Config: Skt 0 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2424 01:20:13.690161 HighMemory(>4G):Base=0x2000000000, Size=0xFFC000000
2425 01:20:13.690674 Enable Channel Interleave for socket[1]
2426 01:20:13.691202 Enable Channel Interleave for socket[1]
2427 01:20:13.703731 Daw Cinfig :Skt 1 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2428 01:20:13.704234 ColBits = 0xA
2429 01:20:13.704741 RowBits = 0x11
2430 01:20:13.705265 Banknum = 0x10
2431 01:20:13.705743 RankSize = 0x400000000
2432 01:20:13.706216 Ranknum = 0x2
2433 01:20:13.706686 DramWidth = 0x4
2434 01:20:13.707157 Size = 0x1000000000
2435 01:20:13.719642 Daw Config: Skt 1 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2436 01:20:13.719930 HighMemory(>4G):Base=0x41000000000, Size=0xFFC000000
2437 01:20:13.720212 ColBits = 0xA
2438 01:20:13.720502 RowBits = 0x11
2439 01:20:13.720816 Banknum = 0x10
2440 01:20:13.721125 RankSize = 0x400000000
2441 01:20:13.721420 Ranknum = 0x2
2442 01:20:13.721707 DramWidth = 0x4
2443 01:20:13.745000 Size = 0x1000000000
2444 01:20:13.745312 Daw Config: Skt 1 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2445 01:20:13.745614 HighMemory(>4G):Base=0x42000000000, Size=0xFFC000000
2446 01:20:13.762879 Finish Config DAW.
2447 01:20:13.763174
2448 01:20:13.763471 Start config RAS or ECC.
2449 01:20:13.763763 pGblData->mem.rascBypass = 1
2450 01:20:13.764057 pGblData->mem.demandScrubMode = 0
2451 01:20:13.764347 pGblData->mem.patrolScrubMode = 0
2452 01:20:13.764723 skt[0] ch[0] ecc enable.
2453 01:20:13.765034 skt[0] ch[1] ecc enable.
2454 01:20:13.779498 skt[0] ch[2] ecc enable.
2455 01:20:13.779782 skt[0] ch[3] ecc enable.
2456 01:20:13.780073 skt[1] ch[0] ecc enable.
2457 01:20:13.780361 skt[1] ch[1] ecc enable.
2458 01:20:13.780677 skt[1] ch[2] ecc enable.
2459 01:20:13.780982 skt[1] ch[3] ecc enable.
2460 01:20:13.781265 Finish config RAS or ECC.
2461 01:20:13.781545
2462 01:20:13.781824 Clean ddrc or rasc interrupt OK
2463 01:20:13.809552 NOTICE: PL011_UART_BASE: 0x602b0000
2464 01:20:13.809866
2465 01:20:13.810167 NOTICE: BL1: 0x3fc8a000 - 0x3fc8b000 [size = 4096]
2466 01:20:13.810465 NOTICE: Booting Trusted Firmware
2467 01:20:13.810761 NOTICE: BL1: v1.1(release):50e18f8
2468 01:20:13.811060 NOTICE: BL1: Built : 08:50:23, Feb 25 2017
2469 01:20:13.851119 NOTICE: BL1: Booting BL2
2470 01:20:13.851470 NOTICE: BL2: v1.1(release):50e18f8
2471 01:20:13.851812 NOTICE: BL2: Built : 08:50:24, Feb 25 2017
2472 01:20:13.941655 NOTICE: BL1: Booting BL3-1
2473 01:20:14.380423 NOTICE: Before BL31 EL3 MMU
2474 01:20:14.380937
2475 01:20:14.381219 NOTICE: After BL31 EL3 MMU
2476 01:20:14.381500
2477 01:20:14.381791 NOTICE: BL3-1: v1.1(release):50e18f8
2478 01:20:14.400982 NOTICE: BL3-1: Built : 08:50:27, Feb 25 2017
2479 01:20:14.401243 NOTICE: [runtime_svc_init]:[94L] rt_svc_descs_num=0x1
2480 01:20:14.401469 NOTICE: [runtime_svc_init]:[109L] start_oen=4 end_oen=4 call_type=1 std_svc
2481 01:20:14.401716 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2482 01:20:14.419684 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2483 01:20:14.420020 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 0
2484 01:20:14.420334 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2485 01:20:14.420675 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2486 01:20:14.421000 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 1
2487 01:20:14.445289 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2488 01:20:14.445506 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2489 01:20:14.445708 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 2
2490 01:20:14.445909 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2491 01:20:14.446108 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2492 01:20:14.466851 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 3
2493 01:20:14.467092 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2494 01:20:14.467295 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2495 01:20:14.467495 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 4
2496 01:20:14.467693 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2497 01:20:14.525318 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2498 01:20:14.525610 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 5
2499 01:20:14.525821 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2500 01:20:14.539993 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2501 01:20:14.540212 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 6
2502 01:20:14.540460 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2503 01:20:14.540715 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2504 01:20:14.551618 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 7
2505 01:20:14.551833 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2506 01:20:14.552071 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2507 01:20:14.552270 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 8
2508 01:20:14.552481 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2509 01:20:14.552716 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2510 01:20:14.560252 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 9
2511 01:20:14.560462 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2512 01:20:14.560756 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2513 01:20:14.560973 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 10
2514 01:20:14.569939 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2515 01:20:14.570159 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2516 01:20:14.570362 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 11
2517 01:20:14.570579 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2518 01:20:14.570777 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2519 01:20:14.587109 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 12
2520 01:20:14.587335 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2521 01:20:14.587539 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2522 01:20:14.587738 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 13
2523 01:20:14.587935 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2524 01:20:14.609178 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2525 01:20:14.609382 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 14
2526 01:20:14.609575 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2527 01:20:14.609769 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2528 01:20:14.609961 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 15
2529 01:20:14.629543 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2530 01:20:14.629778 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2531 01:20:14.629986 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 16
2532 01:20:14.630188 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2533 01:20:14.630388 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2534 01:20:14.652755 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 17
2535 01:20:14.653046 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2536 01:20:14.653252 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2537 01:20:14.653471 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 18
2538 01:20:14.653673 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2539 01:20:14.674903 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2540 01:20:14.675173 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 19
2541 01:20:14.675383 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2542 01:20:14.675587 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2543 01:20:14.726220 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 20
2544 01:20:14.726468 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2545 01:20:14.726674 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2546 01:20:14.739710 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 21
2547 01:20:14.739942 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2548 01:20:14.740157 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2549 01:20:14.740379 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 22
2550 01:20:14.740606 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2551 01:20:14.750796 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2552 01:20:14.751027 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 23
2553 01:20:14.751233 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2554 01:20:14.751436 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2555 01:20:14.751636 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 24
2556 01:20:14.760257 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2557 01:20:14.760510 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2558 01:20:14.760735 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 25
2559 01:20:14.760946 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2560 01:20:14.773243 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2561 01:20:14.773476 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 26
2562 01:20:14.773678 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2563 01:20:14.773934 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2564 01:20:14.774208 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 27
2565 01:20:14.795247 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2566 01:20:14.795486 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2567 01:20:14.795688 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 28
2568 01:20:14.795884 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2569 01:20:14.796078 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2570 01:20:14.817119 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 29
2571 01:20:14.817407 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2572 01:20:14.817632 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2573 01:20:14.817830 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 30
2574 01:20:14.818023 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2575 01:20:14.839182 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2576 01:20:14.839423 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 31
2577 01:20:14.839624 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2578 01:20:14.839818 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2579 01:20:14.840009 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 32
2580 01:20:14.863753 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2581 01:20:14.864058 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2582 01:20:14.864264 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 33
2583 01:20:14.864462 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2584 01:20:14.864687 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2585 01:20:14.882508 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 34
2586 01:20:14.882740 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2587 01:20:14.882939 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2588 01:20:14.883134 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 35
2589 01:20:14.899625 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2590 01:20:14.899860 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2591 01:20:14.900062 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 36
2592 01:20:14.900257 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
2593 01:20:14.900448 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2594 01:20:14.926142 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 37
2595 01:20:14.926375 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
2596 01:20:14.926576 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2597 01:20:14.926770 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 38
2598 01:20:14.926961 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
2599 01:20:14.948157 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2600 01:20:14.948390 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 39
2601 01:20:14.948635 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2602 01:20:14.948833 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2603 01:20:14.949048 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 40
2604 01:20:14.976084 NOTICE: [psci_init_aff_map]:[296L] mpidr = 1
2605 01:20:14.976323 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2606 01:20:14.976543 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 41
2607 01:20:14.976743 NOTICE: [psci_init_aff_map]:[296L] mpidr = 2
2608 01:20:14.976950 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2609 01:20:14.991822 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 42
2610 01:20:14.992051 NOTICE: [psci_init_aff_map]:[296L] mpidr = 3
2611 01:20:14.992244 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2612 01:20:14.992431 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 43
2613 01:20:14.992657 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2614 01:20:15.009426 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2615 01:20:15.009689 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 44
2616 01:20:15.009936 NOTICE: [psci_init_aff_map]:[296L] mpidr = 101
2617 01:20:15.010177 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2618 01:20:15.010373 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 45
2619 01:20:15.035490 NOTICE: [psci_init_aff_map]:[296L] mpidr = 102
2620 01:20:15.035727 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2621 01:20:15.035929 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 46
2622 01:20:15.036123 NOTICE: [psci_init_aff_map]:[296L] mpidr = 103
2623 01:20:15.036315 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2624 01:20:15.057348 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 47
2625 01:20:15.057581 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2626 01:20:15.057781 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2627 01:20:15.057976 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 48
2628 01:20:15.058166 NOTICE: [psci_init_aff_map]:[296L] mpidr = 201
2629 01:20:15.079710 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2630 01:20:15.079942 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 49
2631 01:20:15.080147 NOTICE: [psci_init_aff_map]:[296L] mpidr = 202
2632 01:20:15.080347 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2633 01:20:15.080606 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 50
2634 01:20:15.102144 NOTICE: [psci_init_aff_map]:[296L] mpidr = 203
2635 01:20:15.102376 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2636 01:20:15.102586 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 51
2637 01:20:15.102782 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2638 01:20:15.102972 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2639 01:20:15.120037 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 52
2640 01:20:15.120291 NOTICE: [psci_init_aff_map]:[296L] mpidr = 301
2641 01:20:15.120494 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2642 01:20:15.120778 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 53
2643 01:20:15.121048 NOTICE: [psci_init_aff_map]:[296L] mpidr = 302
2644 01:20:15.145049
2645 01:20:15.145288 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2646 01:20:15.145497 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 54
2647 01:20:15.145709 NOTICE: [psci_init_aff_map]:[296L] mpidr = 303
2648 01:20:15.145901 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2649 01:20:15.167004 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 55
2650 01:20:15.167354 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2651 01:20:15.167674 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2652 01:20:15.167950 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 56
2653 01:20:15.168146 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10001
2654 01:20:15.193809 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2655 01:20:15.194042 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 57
2656 01:20:15.194243 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10002
2657 01:20:15.194437 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2658 01:20:15.194628 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 58
2659 01:20:15.211148 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10003
2660 01:20:15.211379 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2661 01:20:15.211581 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 59
2662 01:20:15.211776 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2663 01:20:15.211966 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2664 01:20:15.229673 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 60
2665 01:20:15.229955 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10101
2666 01:20:15.230157 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2667 01:20:15.230351 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 61
2668 01:20:15.230543 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10102
2669 01:20:15.255265 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2670 01:20:15.255531 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 62
2671 01:20:15.255788 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10103
2672 01:20:15.256017 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2673 01:20:15.256225 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 63
2674 01:20:15.277506 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2675 01:20:15.277779 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2676 01:20:15.277988 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 64
2677 01:20:15.278207 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10201
2678 01:20:15.303583 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2679 01:20:15.303886 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 65
2680 01:20:15.304096 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10202
2681 01:20:15.304307 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2682 01:20:15.304604 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 66
2683 01:20:15.363651 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10203
2684 01:20:15.364116 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2685 01:20:15.364548 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 67
2686 01:20:15.379357 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2687 01:20:15.379699 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2688 01:20:15.380029 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 68
2689 01:20:15.380357 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10301
2690 01:20:15.380726 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2691 01:20:15.390157 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 69
2692 01:20:15.390531 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10302
2693 01:20:15.390870 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2694 01:20:15.391191 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 70
2695 01:20:15.391521 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10303
2696 01:20:15.400987 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2697 01:20:15.401361 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 71
2698 01:20:15.401693 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2699 01:20:15.402011 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2700 01:20:15.414470 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 72
2701 01:20:15.414816 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20001
2702 01:20:15.415159 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2703 01:20:15.415484 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 73
2704 01:20:15.415802 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20002
2705 01:20:15.429993 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2706 01:20:15.430353 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 74
2707 01:20:15.430682 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20003
2708 01:20:15.431004 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2709 01:20:15.431327 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 75
2710 01:20:15.440313 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2711 01:20:15.440709 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2712 01:20:15.441060 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 76
2713 01:20:15.441378 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20101
2714 01:20:15.441700 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2715 01:20:15.462264 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 77
2716 01:20:15.462640 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20102
2717 01:20:15.462970 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2718 01:20:15.463336 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 78
2719 01:20:15.463791 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20103
2720 01:20:15.486396 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2721 01:20:15.486742 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 79
2722 01:20:15.487080 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2723 01:20:15.487405 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2724 01:20:15.487758 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 80
2725 01:20:15.553570 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20201
2726 01:20:15.553914 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2727 01:20:15.554109 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 81
2728 01:20:15.554319 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20202
2729 01:20:15.569235 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2730 01:20:15.569467 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 82
2731 01:20:15.569668 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20203
2732 01:20:15.569860 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2733 01:20:15.570051 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 83
2734 01:20:15.580290 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2735 01:20:15.580539 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2736 01:20:15.580745 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 84
2737 01:20:15.580958 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20301
2738 01:20:15.581143 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2739 01:20:15.589461 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 85
2740 01:20:15.589692 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20302
2741 01:20:15.589894 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2742 01:20:15.590089 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 86
2743 01:20:15.590280 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20303
2744 01:20:15.605925 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2745 01:20:15.606225 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 87
2746 01:20:15.606452 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2747 01:20:15.606647 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2748 01:20:15.606839 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 88
2749 01:20:15.620167 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30001
2750 01:20:15.620397 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2751 01:20:15.620625 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 89
2752 01:20:15.620821 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30002
2753 01:20:15.621031 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2754 01:20:15.637347 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 90
2755 01:20:15.637605 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30003
2756 01:20:15.637806 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2757 01:20:15.638001 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 91
2758 01:20:15.662163 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2759 01:20:15.662397 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2760 01:20:15.662598 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 92
2761 01:20:15.662791 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30101
2762 01:20:15.662981 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2763 01:20:15.733743 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 93
2764 01:20:15.734054 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30102
2765 01:20:15.734255 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2766 01:20:15.734448 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 94
2767 01:20:15.734638 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30103
2768 01:20:15.750669 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2769 01:20:15.750901 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 95
2770 01:20:15.751100 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2771 01:20:15.769617 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2772 01:20:15.769850 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 96
2773 01:20:15.770051 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30201
2774 01:20:15.770245 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2775 01:20:15.781500 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 97
2776 01:20:15.781762 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30202
2777 01:20:15.781966 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2778 01:20:15.782162 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 98
2779 01:20:15.782356 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30203
2780 01:20:15.800144 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2781 01:20:15.800378 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 99
2782 01:20:15.800603 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2783 01:20:15.800799 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2784 01:20:15.801012 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 100
2785 01:20:15.809435 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30301
2786 01:20:15.809676 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2787 01:20:15.809914 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 101
2788 01:20:15.810111 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30302
2789 01:20:15.810303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2790 01:20:15.820481 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 102
2791 01:20:15.820741 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30303
2792 01:20:15.829340 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2793 01:20:15.829566 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 103
2794 01:20:15.829768 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2795 01:20:15.829964 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2796 01:20:15.830157 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 104
2797 01:20:15.841895 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40001
2798 01:20:15.842153 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2799 01:20:15.842356 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 105
2800 01:20:15.842659 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40002
2801 01:20:15.842856 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2802 01:20:15.859575 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 106
2803 01:20:15.859802 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40003
2804 01:20:15.860003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2805 01:20:15.860197 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 107
2806 01:20:15.860390 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2807 01:20:15.878559 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2808 01:20:15.878802 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 108
2809 01:20:15.879005 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40101
2810 01:20:15.879199 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2811 01:20:15.879390 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 109
2812 01:20:15.938201 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40102
2813 01:20:15.938434 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2814 01:20:15.949468 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 110
2815 01:20:15.949701 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40103
2816 01:20:15.949902 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2817 01:20:15.950096 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 111
2818 01:20:15.950281 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2819 01:20:15.959600 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2820 01:20:15.959831 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 112
2821 01:20:15.960063 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40201
2822 01:20:15.960258 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2823 01:20:15.960477 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 113
2824 01:20:15.971266 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40202
2825 01:20:15.971517 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2826 01:20:15.971719 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 114
2827 01:20:15.971914 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40203
2828 01:20:15.989358 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2829 01:20:15.989591 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 115
2830 01:20:15.989793 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2831 01:20:15.989987 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2832 01:20:15.990178 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 116
2833 01:20:16.000222 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40301
2834 01:20:16.000472 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2835 01:20:16.000720 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 117
2836 01:20:16.000929 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40302
2837 01:20:16.001122 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2838 01:20:16.019595 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 118
2839 01:20:16.019829 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40303
2840 01:20:16.020031 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2841 01:20:16.020226 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 119
2842 01:20:16.020418 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2843 01:20:16.042685 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2844 01:20:16.042919 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 120
2845 01:20:16.043156 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50001
2846 01:20:16.043351 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2847 01:20:16.043542 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 121
2848 01:20:16.065392 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50002
2849 01:20:16.065626 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2850 01:20:16.065827 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 122
2851 01:20:16.066015 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50003
2852 01:20:16.066205 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2853 01:20:16.085740 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 123
2854 01:20:16.085971 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2855 01:20:16.086181 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2856 01:20:16.086378 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 124
2857 01:20:16.107710 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50101
2858 01:20:16.107942 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2859 01:20:16.108144 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 125
2860 01:20:16.108339 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50102
2861 01:20:16.108547 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2862 01:20:16.129536 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 126
2863 01:20:16.129766 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50103
2864 01:20:16.129969 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2865 01:20:16.130164 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 127
2866 01:20:16.130355 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2867 01:20:16.150490 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2868 01:20:16.150756 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 128
2869 01:20:16.150959 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50201
2870 01:20:16.151154 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2871 01:20:16.151345 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 129
2872 01:20:16.173221 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50202
2873 01:20:16.173451 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2874 01:20:16.173651 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 130
2875 01:20:16.173845 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50203
2876 01:20:16.174048 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2877 01:20:16.195118 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 131
2878 01:20:16.195349 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2879 01:20:16.195551 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2880 01:20:16.195746 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 132
2881 01:20:16.217052 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50301
2882 01:20:16.217282 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2883 01:20:16.217484 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 133
2884 01:20:16.217678 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50302
2885 01:20:16.217870 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2886 01:20:16.239437 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 134
2887 01:20:16.239668 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50303
2888 01:20:16.239868 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2889 01:20:16.240061 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 135
2890 01:20:16.240252 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2891 01:20:16.261565 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2892 01:20:16.261799 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 136
2893 01:20:16.262003 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60001
2894 01:20:16.262199 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2895 01:20:16.262390 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 137
2896 01:20:16.282832 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60002
2897 01:20:16.283066 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2898 01:20:16.283266 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 138
2899 01:20:16.283461 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60003
2900 01:20:16.283669 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2901 01:20:16.304486 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 139
2902 01:20:16.304746 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2903 01:20:16.304961 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2904 01:20:16.305156 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 140
2905 01:20:16.305348 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60101
2906 01:20:16.327558
2907 01:20:16.327788 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2908 01:20:16.327989 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 141
2909 01:20:16.328183 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60102
2910 01:20:16.328375 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2911 01:20:16.348237 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 142
2912 01:20:16.348467 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60103
2913 01:20:16.348698 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2914 01:20:16.348905 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 143
2915 01:20:16.349097 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2916 01:20:16.372974 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2917 01:20:16.373205 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 144
2918 01:20:16.373405 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60201
2919 01:20:16.373599 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2920 01:20:16.373790 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 145
2921 01:20:16.391924 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60202
2922 01:20:16.392162 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2923 01:20:16.392363 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 146
2924 01:20:16.392578 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60203
2925 01:20:16.392770 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2926 01:20:16.413890 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 147
2927 01:20:16.414119 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2928 01:20:16.414320 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2929 01:20:16.414513 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 148
2930 01:20:16.414701 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60301
2931 01:20:16.435738 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2932 01:20:16.435969 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 149
2933 01:20:16.436168 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60302
2934 01:20:16.436384 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2935 01:20:16.457623 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 150
2936 01:20:16.457855 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60303
2937 01:20:16.458057 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2938 01:20:16.458278 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 151
2939 01:20:16.458470 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2940 01:20:16.479785 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2941 01:20:16.480016 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 152
2942 01:20:16.480217 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70001
2943 01:20:16.480411 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2944 01:20:16.480632 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 153
2945 01:20:16.501691 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70002
2946 01:20:16.501921 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2947 01:20:16.502122 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 154
2948 01:20:16.502315 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70003
2949 01:20:16.502507 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2950 01:20:16.525939 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 155
2951 01:20:16.526170 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
2952 01:20:16.526370 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2953 01:20:16.526565 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 156
2954 01:20:16.526754 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70101
2955 01:20:16.584592 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2956 01:20:16.584836 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 157
2957 01:20:16.599595 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70102
2958 01:20:16.599825 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2959 01:20:16.600025 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 158
2960 01:20:16.600219 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70103
2961 01:20:16.600411 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2962 01:20:16.609581 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 159
2963 01:20:16.609812 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
2964 01:20:16.610013 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2965 01:20:16.610207 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 160
2966 01:20:16.610398 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70201
2967 01:20:16.622992 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2968 01:20:16.623226 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 161
2969 01:20:16.623427 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70202
2970 01:20:16.623636 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2971 01:20:16.639381 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 162
2972 01:20:16.639612 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70203
2973 01:20:16.639812 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2974 01:20:16.640005 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 163
2975 01:20:16.640196 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
2976 01:20:16.649586 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2977 01:20:16.649816 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 164
2978 01:20:16.650018 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70301
2979 01:20:16.650212 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2980 01:20:16.650402 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 165
2981 01:20:16.665458 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70302
2982 01:20:16.665689 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2983 01:20:16.665889 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 166
2984 01:20:16.666083 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70303
2985 01:20:16.666273 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2986 01:20:16.691036 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 167
2987 01:20:16.691324 NOTICE: [cm_prepare_el3_exit]:[262L] read_tpidr_el3 = 3fc5e800
2988 01:20:16.691529 NOTICE: [cm_prepare_el3_exit]:[319L] ctx add = 3fc7ef80
2989 01:20:16.691725
2990 01:20:16.691940 :486=170
2991 01:20:19.519985 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
2992 01:20:19.520591 Halt Macro 2 MCU!!
2993 01:20:19.589703 Macro 2 Download Firmware Success!!
2994 01:20:19.590083 Release Macro 2 MCU!!
2995 01:20:19.639724 Temperature: 29 (0x1D)
2996 01:20:19.730611 Temperature: 29 (0x1D)
2997 01:20:19.769349 [serdes_init]:SerDes2 init success!
2998 01:20:19.769715 Halt Macro 3 MCU!!
2999 01:20:19.789332 Macro 3 Download Firmware Success!!
3000 01:20:19.789698 Release Macro 3 MCU!!
3001 01:20:19.869667 Temperature: 30 (0x1E)
3002 01:20:19.869907 Temperature: 30 (0x1E)
3003 01:20:19.899293 [serdes_init]:SerDes3 init success!
3004 01:20:19.899551 Halt Macro 4 MCU!!
3005 01:20:19.920599 Macro 4 Download Firmware Success!!
3006 01:20:19.920993 Release Macro 4 MCU!!
3007 01:20:19.999680 Temperature: 31 (0x1F)
3008 01:20:20.000042 Temperature: 31 (0x1F)
3009 01:20:20.031236 [serdes_init]:SerDes4 init success!
3010 01:20:20.031512 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3011 01:20:20.031756 Halt Macro 5 MCU!!
3012 01:20:20.119920 Macro 5 Download Firmware Success!!
3013 01:20:20.120252 Release Macro 5 MCU!!
3014 01:20:20.170387 Temperature: 31 (0x1F)
3015 01:20:20.250886 Temperature: 31 (0x1F)
3016 01:20:20.251198 [serdes_init]:SerDes5 init success!
3017 01:20:20.251512 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3018 01:20:20.251795 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3019 01:20:20.272953 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3020 01:20:20.273258 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3021 01:20:20.273526 Halt Macro 6 MCU!!
3022 01:20:20.410088 Macro 6 Download Firmware Success!!
3023 01:20:20.410366 Release Macro 6 MCU!!
3024 01:20:20.410608 Temperature: 31 (0x1F)
3025 01:20:20.459649 Temperature: 31 (0x1F)
3026 01:20:20.479555 [serdes_init]:SerDes6 init success!
3027 01:20:20.479851 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3028 01:20:20.480112 Halt Macro 0 MCU!!
3029 01:20:20.570578 Macro 0 Download Firmware Success!!
3030 01:20:20.570846 Release Macro 0 MCU!!
3031 01:20:20.659472 Temperature: 28 (0x1C)
3032 01:20:20.659763 Temperature: 28 (0x1C)
3033 01:20:20.769803 [serdes_init]:SerDes0 init success!
3034 01:20:20.770033 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3035 01:20:20.770259 Halt Macro 1 MCU!!
3036 01:20:20.849965 Macro 1 Download Firmware Success!!
3037 01:20:20.850382 Release Macro 1 MCU!!
3038 01:20:20.929265 Temperature: 28 (0x1C)
3039 01:20:20.929496 Temperature: 28 (0x1C)
3040 01:20:21.009315 [serdes_init]:SerDes1 init success!
3041 01:20:21.009560 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3042 01:20:21.009768 Halt Macro 5 MCU!!
3043 01:20:21.099266 Macro 5 Download Firmware Success!!
3044 01:20:21.099506 Release Macro 5 MCU!!
3045 01:20:21.150785 Temperature: 28 (0x1C)
3046 01:20:21.210664 Temperature: 28 (0x1C)
3047 01:20:21.239863 [serdes_init]:SerDes5 init success!
3048 01:20:21.240294 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3049 01:20:21.240728 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3050 01:20:21.241087 Halt Macro 6 MCU!!
3051 01:20:21.334753 Macro 6 Download Firmware Success!!
3052 01:20:21.335264 Release Macro 6 MCU!!
3053 01:20:21.389993 Temperature: 28 (0x1C)
3054 01:20:21.453183 Temperature: 28 (0x1C)
3055 01:20:21.453445 [serdes_init]:SerDes6 init success!
3056 01:20:21.453653 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
3057 01:20:21.453858 Halt Macro 2 MCU!!
3058 01:20:21.559584 Macro 2 Download Firmware Success!!
3059 01:20:21.559855 Release Macro 2 MCU!!
3060 01:20:21.662934 Temperature: 29 (0x1D)
3061 01:20:21.730406 Temperature: 29 (0x1D)
3062 01:20:21.730784 [serdes_init]:SerDes2 init success!
3063 01:20:21.731124 Halt Macro 3 MCU!!
3064 01:20:21.759547 Macro 3 Download Firmware Success!!
3065 01:20:21.759939 Release Macro 3 MCU!!
3066 01:20:21.879381 Temperature: 30 (0x1E)
3067 01:20:21.879649 Temperature: 30 (0x1E)
3068 01:20:21.879892 [serdes_init]:SerDes3 init success!
3069 01:20:21.880086 Halt Macro 4 MCU!!
3070 01:20:21.880303 Macro 4 Download Firmware Success!!
3071 01:20:21.880536 Release Macro 4 MCU!!
3072 01:20:21.969972 Temperature: 30 (0x1E)
3073 01:20:21.970226 Temperature: 30 (0x1E)
3074 01:20:22.009291 [serdes_init]:SerDes4 init success!
3075 01:20:22.009568 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3076 01:20:22.009788 Halt Macro 5 MCU!!
3077 01:20:22.143170 Macro 5 Download Firmware Success!!
3078 01:20:22.143451 Release Macro 5 MCU!!
3079 01:20:22.143687 Temperature: 31 (0x1F)
3080 01:20:22.209469 Temperature: 31 (0x1F)
3081 01:20:22.239805 [serdes_init]:SerDes5 init success!
3082 01:20:22.240278 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3083 01:20:22.240732 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3084 01:20:22.241195 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3085 01:20:22.241579 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3086 01:20:22.241957 Halt Macro 6 MCU!!
3087 01:20:22.409464 Macro 6 Download Firmware Success!!
3088 01:20:22.409925 Release Macro 6 MCU!!
3089 01:20:22.410299 Temperature: 31 (0x1F)
3090 01:20:22.479670 Temperature: 31 (0x1F)
3091 01:20:22.480191 [serdes_init]:SerDes6 init success!
3092 01:20:22.480409 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3093 01:20:22.480656 Halt Macro 0 MCU!!
3094 01:20:22.629319 Macro 0 Download Firmware Success!!
3095 01:20:22.629665 Release Macro 0 MCU!!
3096 01:20:22.700629 Temperature: 27 (0x1B)
3097 01:20:22.779701 Temperature: 27 (0x1B)
3098 01:20:22.810264 [serdes_init]:SerDes0 init success!
3099 01:20:22.810630 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3100 01:20:22.810920 Halt Macro 1 MCU!!
3101 01:20:22.950441 Macro 1 Download Firmware Success!!
3102 01:20:22.950824 Release Macro 1 MCU!!
3103 01:20:22.999853 Temperature: 27 (0x1B)
3104 01:20:23.075212 Temperature: 27 (0x1B)
3105 01:20:23.139928 [serdes_init]:SerDes1 init success!
3106 01:20:23.140399 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3107 01:20:23.140868 Halt Macro 5 MCU!!
3108 01:20:23.290162 Macro 5 Download Firmware Success!!
3109 01:20:23.290475 Release Macro 5 MCU!!
3110 01:20:23.369894 Temperature: 27 (0x1B)
3111 01:20:23.370377 Temperature: 27 (0x1B)
3112 01:20:23.410280 [serdes_init]:SerDes5 init success!
3113 01:20:23.410643 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3114 01:20:23.410921 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3115 01:20:23.411150 Halt Macro 6 MCU!!
3116 01:20:23.579601 Macro 6 Download Firmware Success!!
3117 01:20:23.579845 Release Macro 6 MCU!!
3118 01:20:23.689978 Temperature: 27 (0x1B)
3119 01:20:23.690651 Temperature: 27 (0x1B)
3120 01:20:23.691268 [serdes_init]:SerDes6 init success!
3121 01:20:23.940299 InfoFromBmc.ProductName TaiShan 2280
3122 01:20:23.940714 InfoFromBmc.SerialNum 2102311TBJ10H8000087
3123 01:20:23.940955 InfoFromBmc.ManufactureType02 Huawei
3124 01:20:23.941269 InfoFromBmc.AssetTag
3125 01:20:23.941581 InfoFromBmc.SrNumType02 024APL10H8000090
3126 01:20:23.941764 InfoFromBmc.AssetTagType03
3127 01:20:23.980124 InfoFromBmc.SrNumType03 To be filled by O.E.M.
3128 01:20:23.980354 InfoFromBmc.VersionType03
3129 01:20:23.980575 InfoFromBmc.ChassisType03
3130 01:20:23.980763 InfoFromBmc.ManufacturerType03 Huawei
3131 01:20:23.980962 Create event for smbios table transfer success.
3132 01:20:23.981144 VerStr:1.12
3133 01:20:24.009460 Create event for miscellaneous ipmi operation success.
3134 01:20:32.900687 Locate gEfiPciIoProtocol Failed.
3135 01:20:33.013410 DawNum[0] = 2,DawNum[1] = 1,DawNum[2] =2,DawNum[3] =1
3136 01:20:33.013853 0 Base = 0x0, Size = 0x40000000
3137 01:20:33.014245 0 Base = 0x1000000000, Size = 0x1000000000
3138 01:20:33.014617 1 Base = 0x2000000000, Size = 0x1000000000
3139 01:20:33.014960 2 Base = 0x40000000000, Size = 0x40000000
3140 01:20:33.049608 2 Base = 0x41000000000, Size = 0x1000000000
3141 01:20:33.049960 3 Base = 0x42000000000, Size = 0x1000000000
3142 01:20:33.050325 [gmac_initialize]:[3650L] GpriData=0x3E8DE018
3143 01:20:33.081030 pPriv->ulMacSpeed:9
3144 01:20:33.081460 pPriv->ulMacDuplex:1
3145 01:20:33.081815 pPriv->ulPort:0
3146 01:20:33.082153 pPriv->ulGEBase:0xC7040000
3147 01:20:33.082487 pPriv->ulPpeCommonBase:0xC5070000
3148 01:20:33.101406 pPriv->ulPpeTNLBase:0xC5000000
3149 01:20:33.101677 pPriv->ulRCBCommonBase:0xC5080000
3150 01:20:33.101902 pPriv->ulRCBCommonEntryBase:0xC5080000
3151 01:20:33.102118 pPriv->ulRCBSramEntryBase:0xC5090000
3152 01:20:33.102331 pPriv->ulRingNum:0
3153 01:20:33.102541 pPriv->ulRingAddr:0
3154 01:20:33.103373 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE8
3155 01:20:33.216481 DSAF_init
3156 01:20:33.216752 tbl_tcam_data
3157 01:20:33.216971 0x3F196CA0:0xA0A33BC1 0x40E80000 0x00000000 0x00000001
3158 01:20:33.217168 0x3F196CB0:0x00000000
3159 01:20:33.217366 tbl_tcam_ucast
3160 01:20:33.217553 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3161 01:20:33.217829 0x3F196CB8:0x0000007F 0x00000000 0x0000007F 0x80000800
3162 01:20:33.240132 0x3F196CC8:0x00800000
3163 01:20:33.240398 ----ok
3164 01:20:33.240658 LocateProtocol mOemXgeStatusProtocol success.
3165 01:20:33.240894 RXRING = 0x3E8D9000
3166 01:20:33.241102 TXRING = 0x3E8D4000
3167 01:20:33.241306 pPriv->ulTxMask = 512
3168 01:20:33.241507 RXBUFF = 0x3E6D3000
3169 01:20:33.241706 TXBUFF = 0x3E4D2000
3170 01:20:33.241903 [gmac_initialize]:[3650L] GpriData=0x3E44C018
3171 01:20:33.269445 pPriv->ulMacSpeed:9
3172 01:20:33.269805 pPriv->ulMacDuplex:1
3173 01:20:33.270096 pPriv->ulPort:1
3174 01:20:33.270376 pPriv->ulGEBase:0xC7044000
3175 01:20:33.270661 pPriv->ulPpeCommonBase:0xC5070000
3176 01:20:33.291210 pPriv->ulPpeTNLBase:0xC5010000
3177 01:20:33.291608 pPriv->ulRCBCommonBase:0xC5080000
3178 01:20:33.291987 pPriv->ulRCBCommonEntryBase:0xC5080000
3179 01:20:33.292359 pPriv->ulRCBSramEntryBase:0xC5090000
3180 01:20:33.292715 pPriv->ulRingNum:16
3181 01:20:33.293008 pPriv->ulRingAddr:1048576
3182 01:20:33.293281 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE9
3183 01:20:33.293593 DSAF_init
3184 01:20:33.313185 tbl_tcam_data
3185 01:20:33.313792 0x3F196CA0:0xA0A33BC1 0x40E90001 0x00000000 0x00000001
3186 01:20:33.314425 0x3F196CB0:0x00000000
3187 01:20:33.314913 tbl_tcam_ucast
3188 01:20:33.315382 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3189 01:20:33.315740 0x3F196CB8:0x0000008F 0x00000000 0x0000008F 0xC13BA3A0
3190 01:20:33.316024 0x3F196CC8:0x0000E940
3191 01:20:33.339724 ----ok
3192 01:20:33.340044 LocateProtocol mOemXgeStatusProtocol success.
3193 01:20:33.340324 RXRING = 0x3E447000
3194 01:20:33.340625 TXRING = 0x3E442000
3195 01:20:33.340904 pPriv->ulTxMask = 512
3196 01:20:33.341148 RXBUFF = 0x3E241000
3197 01:20:33.341370 TXBUFF = 0x3E040000
3198 01:20:33.341600 [gmac_initialize]:[3650L] GpriData=0x3DFB8018
3199 01:20:33.374527 pPriv->ulMacSpeed:8
3200 01:20:33.374922 pPriv->ulMacDuplex:1
3201 01:20:33.375323 pPriv->ulPort:4
3202 01:20:33.375693 pPriv->ulGEBase:0xC7050000
3203 01:20:33.376071 pPriv->ulPpeCommonBase:0xC5070000
3204 01:20:33.376391 pPriv->ulPpeTNLBase:0xC5040000
3205 01:20:33.376825 pPriv->ulRCBCommonBase:0xC5080000
3206 01:20:33.377253 pPriv->ulRCBCommonEntryBase:0xC5080000
3207 01:20:33.452726 pPriv->ulRCBSramEntryBase:0xC5090000
3208 01:20:33.453166 pPriv->ulRingNum:64
3209 01:20:33.453504 pPriv->ulRingAddr:4194304
3210 01:20:33.453832 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE6
3211 01:20:33.454181 PhyID : 0x1410DD0
3212 01:20:33.454535 PhyAddr: 0x0
3213 01:20:33.454873 ETH_PhyInit 1928; Marvell 88E1512 detect!
3214 01:20:33.809539 MII_CTRL_REG = 0x3100
3215 01:20:33.809843 MII_STAT_REG = 0x7949
3216 01:20:33.902760 page 18, reg20:0x1
3217 01:20:33.912623 page 0, reg17:0x4000
3218 01:20:33.913149 Phy Init OK
3219 01:20:33.913598 DSAF_init
3220 01:20:33.914063 tbl_tcam_data
3221 01:20:33.914526 0x3F196CA0:0xA0A33BC1 0x40E60004 0x00000000 0x00000001
3222 01:20:33.914954 0x3F196CB0:0x00000000
3223 01:20:33.915243 tbl_tcam_ucast
3224 01:20:33.915532 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3225 01:20:33.930593 0x3F196CB8:0x000000BF 0x00000000 0x000000BF 0xAFAFAFAF
3226 01:20:33.931027 0x3F196CC8:0xAFAFAFAF
3227 01:20:33.931388 ----ok
3228 01:20:34.000422 RXRING = 0x3DFB3000
3229 01:20:34.000967 TXRING = 0x3DFAD000
3230 01:20:34.001356 pPriv->ulTxMask = 512
3231 01:20:34.001724 RXBUFF = 0x3DDAB000
3232 01:20:34.002085 TXBUFF = 0x3DBA9000
3233 01:20:34.030034 [gmac_initialize]:[3650L] GpriData=0x3DB21018
3234 01:20:34.104821 pPriv->ulMacSpeed:8
3235 01:20:34.105239 pPriv->ulMacDuplex:1
3236 01:20:34.105559 pPriv->ulPort:5
3237 01:20:34.105855 pPriv->ulGEBase:0xC7054000
3238 01:20:34.106134 pPriv->ulPpeCommonBase:0xC5070000
3239 01:20:34.106411 pPriv->ulPpeTNLBase:0xC5050000
3240 01:20:34.106684 pPriv->ulRCBCommonBase:0xC5080000
3241 01:20:34.106957 pPriv->ulRCBCommonEntryBase:0xC5080000
3242 01:20:34.132250 pPriv->ulRCBSramEntryBase:0xC5090000
3243 01:20:34.132682 pPriv->ulRingNum:80
3244 01:20:34.133037 pPriv->ulRingAddr:5242880
3245 01:20:34.133359 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE7
3246 01:20:34.133671 PhyID : 0x1410DD0
3247 01:20:34.133980 PhyAddr: 0x1
3248 01:20:34.134287 ETH_PhyInit 1928; Marvell 88E1512 detect!
3249 01:20:34.519476 MII_CTRL_REG = 0x3100
3250 01:20:34.519799 MII_STAT_REG = 0x7949
3251 01:20:34.586523 page 18, reg20:0x1
3252 01:20:34.586759 page 0, reg17:0x4000
3253 01:20:34.618933 Phy Init OK
3254 01:20:34.619161 DSAF_init
3255 01:20:34.619353 tbl_tcam_data
3256 01:20:34.619538 0x3F196CA0:0xA0A33BC1 0x40E70005 0x00000000 0x00000001
3257 01:20:34.619723 0x3F196CB0:0x00000000
3258 01:20:34.619905 tbl_tcam_ucast
3259 01:20:34.620083 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3260 01:20:34.620262 0x3F196CB8:0x000000CF 0x00000000 0x000000CF 0xAFAFAFAF
3261 01:20:34.669346 0x3F196CC8:0xAFAFAFAF
3262 01:20:34.669576 ----ok
3263 01:20:34.751967 RXRING = 0x3DB1C000
3264 01:20:34.752203 TXRING = 0x3DB17000
3265 01:20:34.752401 pPriv->ulTxMask = 512
3266 01:20:34.752753 RXBUFF = 0x3D916000
3267 01:20:34.752958 TXBUFF = 0x3D714000
3268 01:20:34.899616 SasDriverInitialize Ok!!!
3269 01:20:34.899863 [sas_init,2173]Card:1 init ok
3270 01:20:34.900054 [Higgs_StartPhy,185]Card:1 no cable on phy:0, default as electric cable
3271 01:20:35.509572 [Higgs_IntrInquiryOperation,219]Identify info:0x20010202,DevType:2--2,uiPhyContext:0x0
3272 01:20:35.509896 [Higgs_PhyCtrlUpDown,332]Higgs_PhyCtrlUpDown at uiPhyId = 0x0
3273 01:20:35.510089 [Higgs_PhyCtrlUpDown,346]uiPhyId:0x0, uiIrqVal:0x26
3274 01:20:35.510276 [Higgs_PhyUp,503]phyid:0,Rate is 11
3275 01:20:35.559504 [SAINI_ClearPortRsc,449]Card:1 port:0 clr port rsc,remove all device from device list of Disc
3276 01:20:35.576582 [SAINI_ExpanderBufferSwitch,1306]EXPANDER Buffer function is 2 !
3277 01:20:35.576809 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CC9F0(uni id:0x0) to dev addr:0x500E004AAAAAAA00(sal dev:3D5D42D8) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3278 01:20:35.594865 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CCFD8(uni id:0x0) to dev addr:0x500E004AAAAAAA01(sal dev:3D5D4598) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3279 01:20:35.616068 [SAL_AbortTaskSet,646]Now let's start abort SAS dev Io Card:1 msg:3D5CD5C0 to dev addr:0x500E004AAAAAAA1E(sal dev:3D5D4858),v_pstMsg->stStatus.enDrvResp803,pstMsg->pfnDone:31B85BF8
3280 01:20:35.616384 [SasScanDisk,838]Open Card:1 Phy:0 success!
3281 01:20:35.616702
3282 01:20:35.644382 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA00, status = Success
3283 01:20:35.644759 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA01, status = Success
3284 01:20:35.645074 SasDriverStart Ok!!!
3285 01:20:38.704137 SmiControllerDriverSupported - Status:Success
3286 01:20:38.704954 Install GopDevicePath Handle 0
3287 01:20:38.705461 Install GopDevicePath Handle 3D54D898
3288 01:20:38.705895 Install GopDevicePath Status Success
3289 01:20:38.706473 SmiGraphicsOutputSetMode +
3290 01:20:38.706943 Resetting Memory
3291 01:20:38.707356 setModeEx +
3292 01:20:38.707826 programModeRegisters +
3293 01:20:38.729121 [LPC] CRT_PLL1_750HS = 0x1D40A02
3294 01:20:38.729554 [LPC] CRT_PLL2_750HS = 0x206B851E
3295 01:20:38.730155 [LPC] SECONDARY_DISPLAY_CTRL = 0x2087106
3296 01:20:38.730595 setModeEx -
3297 01:20:38.731115 SmiGraphicsOutputSetMode x=640 y=480
3298 01:20:38.731553 SmiGraphicsOutputSetMode -
3299 01:20:38.731992 SmiGraphicsOutputConstructor -
3300 01:20:38.771151 [2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiGraphicsOutputQueryMode +
3301 01:20:38.771560 SmiGraphicsOutputQueryMode -
3302 01:20:38.771871 SmiGraphicsOutputQueryMode +
3303 01:20:38.772170 SmiGraphicsOutputQueryMode -
3304 01:20:38.900430 SmiGraphicsOutputQueryMode +
3305 01:20:38.901111 SmiGraphicsOutputQueryMode -
3306 01:20:38.901529 SmiGraphicsOutputQueryMode +
3307 01:20:38.901929 SmiGraphicsOutputQueryMode -
3308 01:20:38.902334 [2J[01;01H[=3h[2J[01;01H[0m[37m[40mSmiGraphicsOutputQueryMode +
3309 01:20:38.902731 SmiGraphicsOutputQueryMode -
3310 01:20:40.611659 [2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiControllerDriverSupported - Status:Unsupported
3311 01:20:40.612090 SmiControllerDriverSupported - Status:Unsupported
3312 01:20:40.629741 SmiControllerDriverSupported - Status:Unsupported
3313 01:20:40.630165 SmiControllerDriverSupported - Status:Unsupported
3314 01:20:40.630550 SmiControllerDriverSupported - Status:Unsupported
3315 01:20:40.630920 SmiControllerDriverSupported - Status:Unsupported
3316 01:20:40.631268 SmiControllerDriverSupported - Status:Unsupported
3317 01:20:40.689942 SmiControllerDriverSupported - Status:Unsupported
3318 01:20:41.370179 SmiControllerDriverSupported - Status:Unsupported
3319 01:20:41.370813 SmiControllerDriverSupported - Status:Unsupported
3320 01:20:41.371248 SmiControllerDriverSupported - Status:Unsupported
3321 01:20:41.371725 SmiControllerDriverSupported - Status:Unsupported
3322 01:20:41.389792 SmiControllerDriverSupported - Status:Unsupported
3323 01:20:41.390296 SmiControllerDriverSupported - Status:Unsupported
3324 01:20:41.390710 SmiControllerDriverSupported - Status:Unsupported
3325 01:20:41.391109 SmiControllerDriverSupported - Status:Unsupported
3326 01:20:42.070195 [0m[37m[40mPress Enter to boot OS immediately.
3327 01:20:42.070764 Press any other key in 10 seconds to stop automatical booting...
3328 01:20:52.126414 [2J[01;01HSmiGraphicsOutputQueryMode +
3329 01:20:52.127045 SmiGraphicsOutputQueryMode -
3330 01:20:59.480049 ..[0m[30m[47mWelcome to GRUB!
3331 01:20:59.481158
3332 01:20:59.481837
3333 01:20:59.615036 [0m[37m[40m[0m[30m[40m[2J[01;01H[0m[37m[40m[02;27HGNU GRUB version 2.02~beta3
3334 01:20:59.615643
3335 01:20:59.616243
3336 01:20:59.616967 Minimal BASH-like line editing is supported. For the first word, TAB
3337 01:20:59.617545
3338 01:20:59.618118 lists possible command completions. Anywhere else TAB lists possible
3339 01:20:59.618748
3340 01:20:59.639945 device or file completions.
3341 01:20:59.640393
3342 01:20:59.641023
3343 01:20:59.641524
3345 01:23:54.530668 end: 2.5 bootloader-interrupt (duration 00:04:39) [common]
3347 01:23:54.531449 grub-main-action failed: 1 of 3 attempts. 'bootloader-interrupt timed out after 279 seconds'
3348 01:23:55.536975 Retrying: 2 grub-main-action (timeout 00:05:00)
3349 01:23:55.537743 start: 2.1 bootloader-from-media (timeout 00:05:00) [common]
3350 01:23:55.538341 end: 2.1 bootloader-from-media (duration 00:00:00) [common]
3351 01:23:55.538917 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
3352 01:23:55.539898 substitutions:
3353 01:23:55.540337 - {DTB}: 8315107/tftp-deploy-6iwhbpo5/dtb/hip07-d05.dtb
3354 01:23:55.540841 - {INITRD}: 8315107/tftp-deploy-6iwhbpo5/ramdisk/ramdisk.cpio.gz
3355 01:23:55.541299 - {KERNEL}: 8315107/tftp-deploy-6iwhbpo5/kernel/Image
3356 01:23:55.541720 - {LAVA_MAC}: None
3357 01:23:55.542136 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n
3358 01:23:55.542551 - {NFS_SERVER_IP}: 192.168.101.1
3359 01:23:55.542959 - {PRESEED_CONFIG}: None
3360 01:23:55.543367 - {PRESEED_LOCAL}: None
3361 01:23:55.543770 - {RAMDISK}: 8315107/tftp-deploy-6iwhbpo5/ramdisk/ramdisk.cpio.gz
3362 01:23:55.544172 - {ROOT_PART}: None
3363 01:23:55.544607 - {ROOT}: None
3364 01:23:55.544991 - {SERVER_IP}: 192.168.101.1
3365 01:23:55.545184 - {TEE}: None
3366 01:23:55.545385 Parsed boot commands:
3367 01:23:55.545575 - linux (tftp,192.168.101.1)/8315107/tftp-deploy-6iwhbpo5/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava/dispatcher/tmp/8315107/extract-nfsrootfs-ovtopn8n,tcp,hard,vers=3 ip=:::::eth0:dhcp
3368 01:23:55.545804 - devicetree (tftp,192.168.101.1)/8315107/tftp-deploy-6iwhbpo5/dtb/hip07-d05.dtb
3369 01:23:55.545997 - boot
3370 01:23:55.546251 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
3371 01:23:55.546526 start: 2.3 connect-device (timeout 00:05:00) [common]
3372 01:23:55.546750 Already connected
3373 01:23:55.547016 end: 2.3 connect-device (duration 00:00:00) [common]
3374 01:23:55.547290 start: 2.4 reset-device (timeout 00:05:00) [common]
3375 01:23:55.547565 start: 2.4.1 pdu-reboot (timeout 00:05:00) [common]
3376 01:23:55.547964 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'reset'
3377 01:23:55.927582 >> Chassis Power Control: Down/Off
3378 01:24:06.292775 >> Chassis Power Control: Up/On
3379 01:24:16.304769 Returned 0 in 20 seconds
3380 01:24:16.406774 end: 2.4.1 pdu-reboot (duration 00:00:21) [common]
3382 01:24:16.408679 end: 2.4 reset-device (duration 00:00:21) [common]
3383 01:24:16.409401 start: 2.5 bootloader-interrupt (timeout 00:04:39) [common]
3384 01:24:16.409946 Setting prompt string to ['PCIE MEM CONFIG']
3385 01:24:16.410414 bootloader-interrupt: Wait for prompt ['PCIE MEM CONFIG'] (timeout 00:05:00)
3386 01:24:16.411894 grub> �����+�� �� � � ` �Need Reset
3387 01:24:16.412338 Reset Now...
3388 01:24:16.412819 Needn't Reset, Go on
3389 01:24:16.413288 [LPC] Config TA/TB AA
3390 01:24:16.413729 [LPC] Config TA/TB LLC
3391 01:24:16.414134 Djtag primary 8d000D818 init
3392 01:24:16.414534 [LPC] Config NA AA
3393 01:24:16.414932 [LPC] Config NB AA
3394 01:24:16.415285 PCIE MEM CONFIG.........Done
3395 01:24:16.415567 [LPC] DReset GIC ITS MBIGEN
3396 01:24:16.415844 [LPC] Platform Event Broadcast Config between TA/TB
3397 01:24:16.416124 [LPC] GICR CONFIG Done
3398 01:24:16.416402 [LPC] MBIGEN CONFIG
3399 01:24:16.416723 [LPC] GICD Broadcast CONFIG
3400 01:24:16.417031
3401 01:24:16.417307 1:Continue 2: HLLC Config
3402 01:24:16.417604 I2C Init
3403 01:24:16.417878 S1_PLL Init
3404 01:24:16.418150 TA PLL init....OK
3405 01:24:16.418422 NA PLL init....OK
3406 01:24:16.418694 I2C ReInit
3407 01:24:16.418964 S0 HLLC0 Interrupt status(0x4) = 0xABF
3408 01:24:16.419234 S0 HLLC1 Interrupt status(0x4) = 0x23C
3409 01:24:16.419504 S1 HLLC0 Interrupt status(0x4) = 0x4A0
3410 01:24:16.419775 S1 HLLC1 Interrupt status(0x4) = 0x82A
3411 01:24:16.420047
3412 01:24:16.420318 1:X8_32 2: X16_32 3:X8_16 4:X16_16
3413 01:24:16.420616 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 5G
3414 01:24:16.420923 [serdes_cs_hw_calibration_optionV2_exec]:Macro0 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
3415 01:24:16.421106 [SerdesCsCalib]:Macro0 CS1 PLL lock success!(0 ms)
3416 01:24:16.421283 [serdes_init]:SerDes0 init success!
3417 01:24:16.421459 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G
3418 01:24:16.421636 [serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
3419 01:24:16.421815 [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms)
3420 01:24:16.421992 [serdes_init]:SerDes1 init success!
3421 01:24:16.422167 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 5G
3422 01:24:16.422343 [serdes_cs_hw_calibration_optionV2_exec]:Macro0 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
3423 01:24:16.422520 [SerdesCsCalib]:Macro0 CS1 PLL lock success!(0 ms)
3424 01:24:16.422697 [serdes_init]:SerDes0 init success!
3425 01:24:16.422872 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G
3426 01:24:16.474030 end: 2.5 bootloader-interrupt (duration 00:00:00) [common]
3428 01:24:16.475525 start: 2.6 bootloader-commands (timeout 00:04:39) [common]
3429 01:24:16.476007 Setting prompt string to ['grub>']
3430 01:24:16.476466 bootloader-commands: Wait for prompt ['grub>'] (timeout 00:04:39)
3431 01:24:17.861389 c[serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
3432 01:24:17.861974 [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms)
3433 01:24:20.180786 [serdes_init]:SerDes1 init success!
3434 01:24:20.261132 Continue to dreset PCS
3435 01:24:20.261648 Continue to dreset HLLC
3436 01:24:21.260988 Continue to open PCS RX
3437 01:24:21.294605 Wait for HLLC Training........OK
3438 01:24:21.295097 Wait for HLLC1 Training........OK
3439 01:24:21.295531 Wait for S1 HLLC Training........OK
3440 01:24:21.295929 Wait for S1 HLLC1 Training........OK
3441 01:24:21.296355 Open Secondary socket Window
3442 01:24:21.296856 Djtag secondary 0x4004001d818 and 0x400d000d818 init
3443 01:24:22.280940 Macro 0 Download Firmware Success!!
3444 01:24:23.250688 Macro 1 Download Firmware Success!!
3445 01:24:24.229343 Macro 0 Download Firmware Success!!
3446 01:24:25.131746 Macro 1 Download Firmware Success!!
3447 01:24:25.132376 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
3448 01:24:25.132913 Halt Macro 0 MCU!!
3449 01:24:25.133357 Release Macro 0 MCU!!
3450 01:24:25.200755 Temperature: 29 (0x1D)
3451 01:24:25.300977 [serdes_init]:SerDes0 init success!
3452 01:24:25.301503 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
3453 01:24:25.301923 Halt Macro 1 MCU!!
3454 01:24:25.302320 Release Macro 1 MCU!!
3455 01:24:25.352447 Temperature: 29 (0x1D)
3456 01:24:25.470845 [serdes_init]:SerDes1 init success!
3457 01:24:25.471349 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
3458 01:24:25.681344 Halt Macro 0 MCU!!
3459 01:24:25.940796 Release Macro 0 MCU!!
3460 01:24:27.570553 Temperature: 28 (0x1C)
3461 01:24:28.271128 [serdes_init]:SerDes0 init success!
3462 01:24:28.271520 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
3463 01:24:28.450815 Halt Macro 1 MCU!!
3464 01:24:28.710828 Release Macro 1 MCU!!
3465 01:24:30.373314 Temperature: 28 (0x1C)
3466 01:24:31.070690 [serdes_init]:SerDes1 init success!
3467 01:24:31.160635 Continue to dreset PCS
3468 01:24:31.160863 Continue to dreset HLLC
3469 01:24:31.161075 Continue to Enable CTLE
3470 01:24:32.382165 Continue to open PCS RX
3471 01:24:32.436352 Wait for HLLC Training........OK
3472 01:24:32.437015 Wait for HLLC1 Training........OK
3473 01:24:32.437433 Wait for S1 HLLC Training........OK
3474 01:24:32.437832 Wait for S1 HLLC1 Training........OK
3475 01:24:32.438235 S0 HLLC0 Interrupt status(0x4) = 0x0
3476 01:24:32.438625 S0 HLLC1 Interrupt status(0x4) = 0x0
3477 01:24:32.453097 S1 HLLC0 Interrupt status(0x4) = 0x0
3478 01:24:32.453590 S1 HLLC1 Interrupt status(0x4) = 0x0
3479 01:24:32.454003
3480 01:24:32.454404 Config Secondary socket
3481 01:24:32.454784 Open Secondary socket Window
3482 01:24:32.455181 close NB CS2 to PA
3483 01:24:32.455573 Config socket0 NA PA
3484 01:24:32.455955 Enable socket0 PA 2+2 Mode
3485 01:24:32.456579 Config Secondary socket PA
3486 01:24:32.476760 clean S0 remap for PA....Done
3487 01:24:32.477250 clean remap for PA....Done
3488 01:24:32.477634 Enable socket1 PA 2+2 Mode
3489 01:24:32.478015 Djtag Secondary 0x4006001d818 Init
3490 01:24:32.478378 S1 Preinit
3491 01:24:32.478735 S1 Preinit End
3492 01:24:32.479090 Config Secondary socket AA&LLC
3493 01:24:32.479440 close S1 NB CS2 to PA
3494 01:24:32.499038 OK1OK2OK3Djtag Secondary 0x408d000d818 Init
3495 01:24:32.499535 Visit S1 NB
3496 01:24:32.499946 Visit S1 NB DONE
3497 01:24:32.500344 S1 NA PCIE clean remap.........Done
3498 01:24:32.500825 S1 NA PCIE MEM CONFIG.........Done
3499 01:24:32.501253 S1 NB PCIE clean remap.........Done
3500 01:24:32.521156 S1 NB PCIE MEM CONFIG.........Done
3501 01:24:32.521646 NB/TB PLL Init
3502 01:24:32.522062 TB PLL init....OK
3503 01:24:32.522461 NB PLL init....OK
3504 01:24:32.522865 [LPC] S1 MBIGEN CONFIG Done
3505 01:24:32.551171 add-symbol-file /home/s00296804/Edk2/Build/D05Source/RELEASE_GCC49/AARCH64/HwPkg/Override/ArmPlatformPkg/Sec/Sec/DEBUG/ArmPlatformSec.dll 0xA4801800
3506 01:24:32.551717 Trust Zone Configuration is disabled
3507 01:24:32.552151
3508 01:24:33.930833