Boot log: asus-C436FA-Flip-hatch
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
1 15:07:30.136394 lava-dispatcher, installed at version: 2023.05.1
2 15:07:30.136627 start: 0 validate
3 15:07:30.136777 Start time: 2023-06-09 15:07:30.136768+00:00 (UTC)
4 15:07:30.136919 Using caching service: 'http://localhost/cache/?uri=%s'
5 15:07:30.137062 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Fx86%2Frootfs.cpio.gz exists
6 15:07:30.395572 Using caching service: 'http://localhost/cache/?uri=%s'
7 15:07:30.395774 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.284-cip99%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 15:07:30.656866 Using caching service: 'http://localhost/cache/?uri=%s'
9 15:07:30.657068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.284-cip99%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 15:07:34.110643 validate duration: 3.97
12 15:07:34.111047 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 15:07:34.111191 start: 1.1 download-retry (timeout 00:10:00) [common]
14 15:07:34.111329 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 15:07:34.111507 Not decompressing ramdisk as can be used compressed.
16 15:07:34.111639 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/x86/rootfs.cpio.gz
17 15:07:34.111745 saving as /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/ramdisk/rootfs.cpio.gz
18 15:07:34.111857 total size: 8430069 (8MB)
19 15:07:34.729796 progress 0% (0MB)
20 15:07:34.732456 progress 5% (0MB)
21 15:07:34.734993 progress 10% (0MB)
22 15:07:34.737633 progress 15% (1MB)
23 15:07:34.740276 progress 20% (1MB)
24 15:07:34.742914 progress 25% (2MB)
25 15:07:34.745455 progress 30% (2MB)
26 15:07:34.748041 progress 35% (2MB)
27 15:07:34.750496 progress 40% (3MB)
28 15:07:34.753103 progress 45% (3MB)
29 15:07:34.755684 progress 50% (4MB)
30 15:07:34.758332 progress 55% (4MB)
31 15:07:34.761016 progress 60% (4MB)
32 15:07:34.763714 progress 65% (5MB)
33 15:07:34.766372 progress 70% (5MB)
34 15:07:34.768841 progress 75% (6MB)
35 15:07:34.771524 progress 80% (6MB)
36 15:07:34.774167 progress 85% (6MB)
37 15:07:34.776837 progress 90% (7MB)
38 15:07:34.779430 progress 95% (7MB)
39 15:07:34.782134 progress 100% (8MB)
40 15:07:34.782329 8MB downloaded in 0.67s (11.99MB/s)
41 15:07:34.782561 end: 1.1.1 http-download (duration 00:00:01) [common]
43 15:07:34.783021 end: 1.1 download-retry (duration 00:00:01) [common]
44 15:07:34.783158 start: 1.2 download-retry (timeout 00:09:59) [common]
45 15:07:34.783296 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 15:07:34.783494 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.284-cip99/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 15:07:34.783606 saving as /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/kernel/bzImage
48 15:07:34.783720 total size: 10858496 (10MB)
49 15:07:34.783830 No compression specified
50 15:07:34.785681 progress 0% (0MB)
51 15:07:34.789067 progress 5% (0MB)
52 15:07:34.792619 progress 10% (1MB)
53 15:07:34.795950 progress 15% (1MB)
54 15:07:34.799365 progress 20% (2MB)
55 15:07:34.802585 progress 25% (2MB)
56 15:07:34.806001 progress 30% (3MB)
57 15:07:34.809122 progress 35% (3MB)
58 15:07:34.812511 progress 40% (4MB)
59 15:07:34.815999 progress 45% (4MB)
60 15:07:34.819257 progress 50% (5MB)
61 15:07:34.822681 progress 55% (5MB)
62 15:07:34.825819 progress 60% (6MB)
63 15:07:34.829147 progress 65% (6MB)
64 15:07:34.832329 progress 70% (7MB)
65 15:07:34.835585 progress 75% (7MB)
66 15:07:34.838856 progress 80% (8MB)
67 15:07:34.842076 progress 85% (8MB)
68 15:07:34.845479 progress 90% (9MB)
69 15:07:34.848694 progress 95% (9MB)
70 15:07:34.852136 progress 100% (10MB)
71 15:07:34.852331 10MB downloaded in 0.07s (150.94MB/s)
72 15:07:34.852549 end: 1.2.1 http-download (duration 00:00:00) [common]
74 15:07:34.852976 end: 1.2 download-retry (duration 00:00:00) [common]
75 15:07:34.853122 start: 1.3 download-retry (timeout 00:09:59) [common]
76 15:07:34.853252 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 15:07:34.853435 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.284-cip99/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 15:07:34.853551 saving as /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/modules/modules.tar
79 15:07:34.853655 total size: 483884 (0MB)
80 15:07:34.853755 Using unxz to decompress xz
81 15:07:34.857711 progress 6% (0MB)
82 15:07:34.858187 progress 13% (0MB)
83 15:07:34.858458 progress 20% (0MB)
84 15:07:34.860038 progress 27% (0MB)
85 15:07:34.862470 progress 33% (0MB)
86 15:07:34.864656 progress 40% (0MB)
87 15:07:34.867127 progress 47% (0MB)
88 15:07:34.869252 progress 54% (0MB)
89 15:07:34.871584 progress 60% (0MB)
90 15:07:34.873665 progress 67% (0MB)
91 15:07:34.875944 progress 74% (0MB)
92 15:07:34.878679 progress 81% (0MB)
93 15:07:34.880840 progress 88% (0MB)
94 15:07:34.882908 progress 94% (0MB)
95 15:07:34.885777 progress 100% (0MB)
96 15:07:34.892920 0MB downloaded in 0.04s (11.76MB/s)
97 15:07:34.893254 end: 1.3.1 http-download (duration 00:00:00) [common]
99 15:07:34.893581 end: 1.3 download-retry (duration 00:00:00) [common]
100 15:07:34.893721 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
101 15:07:34.893874 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
102 15:07:34.894000 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 15:07:34.894142 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
104 15:07:34.894429 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox
105 15:07:34.894620 makedir: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin
106 15:07:34.894772 makedir: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/tests
107 15:07:34.894924 makedir: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/results
108 15:07:34.895108 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-add-keys
109 15:07:34.895313 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-add-sources
110 15:07:34.895506 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-background-process-start
111 15:07:34.895672 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-background-process-stop
112 15:07:34.895822 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-common-functions
113 15:07:34.895960 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-echo-ipv4
114 15:07:34.896111 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-install-packages
115 15:07:34.896247 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-installed-packages
116 15:07:34.896401 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-os-build
117 15:07:34.896549 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-probe-channel
118 15:07:34.896685 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-probe-ip
119 15:07:34.896833 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-target-ip
120 15:07:34.896997 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-target-mac
121 15:07:34.897155 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-target-storage
122 15:07:34.897307 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-case
123 15:07:34.897444 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-event
124 15:07:34.897600 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-feedback
125 15:07:34.897735 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-raise
126 15:07:34.897896 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-reference
127 15:07:34.898045 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-runner
128 15:07:34.898181 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-set
129 15:07:34.898330 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-test-shell
130 15:07:34.898469 Updating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-install-packages (oe)
131 15:07:34.898648 Updating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/bin/lava-installed-packages (oe)
132 15:07:34.898803 Creating /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/environment
133 15:07:34.898917 LAVA metadata
134 15:07:34.899055 - LAVA_JOB_ID=10660955
135 15:07:34.899176 - LAVA_DISPATCHER_IP=192.168.201.1
136 15:07:34.899329 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
137 15:07:34.899438 skipped lava-vland-overlay
138 15:07:34.899539 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 15:07:34.899631 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
140 15:07:34.899702 skipped lava-multinode-overlay
141 15:07:34.899786 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 15:07:34.899879 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
143 15:07:34.899966 Loading test definitions
144 15:07:34.900075 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
145 15:07:34.900161 Using /lava-10660955 at stage 0
146 15:07:34.900499 uuid=10660955_1.4.2.3.1 testdef=None
147 15:07:34.900603 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 15:07:34.900696 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
149 15:07:34.901299 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 15:07:34.901553 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
152 15:07:34.902595 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 15:07:34.903009 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
155 15:07:34.904039 runner path: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/0/tests/0_dmesg test_uuid 10660955_1.4.2.3.1
156 15:07:34.904250 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 15:07:34.904666 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
159 15:07:34.904781 Using /lava-10660955 at stage 1
160 15:07:34.905264 uuid=10660955_1.4.2.3.5 testdef=None
161 15:07:34.905399 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 15:07:34.905543 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
163 15:07:34.906248 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 15:07:34.906528 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
166 15:07:34.907500 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 15:07:34.907787 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
169 15:07:34.908505 runner path: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/1/tests/1_bootrr test_uuid 10660955_1.4.2.3.5
170 15:07:34.908686 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 15:07:34.908951 Creating lava-test-runner.conf files
173 15:07:34.909031 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/0 for stage 0
174 15:07:34.909138 - 0_dmesg
175 15:07:34.909231 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10660955/lava-overlay-l771wiox/lava-10660955/1 for stage 1
176 15:07:34.909354 - 1_bootrr
177 15:07:34.909463 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 15:07:34.909583 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
179 15:07:34.921046 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 15:07:34.921248 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
181 15:07:34.921385 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 15:07:34.921554 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 15:07:34.921696 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
184 15:07:35.210147 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 15:07:35.210633 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
186 15:07:35.210818 extracting modules file /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10660955/extract-overlay-ramdisk-wfjf6xvq/ramdisk
187 15:07:35.246544 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 15:07:35.246778 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
189 15:07:35.246930 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10660955/compress-overlay-byi0ilxr/overlay-1.4.2.4.tar.gz to ramdisk
190 15:07:35.247051 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10660955/compress-overlay-byi0ilxr/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10660955/extract-overlay-ramdisk-wfjf6xvq/ramdisk
191 15:07:35.261991 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 15:07:35.262211 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
193 15:07:35.262364 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 15:07:35.262513 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
195 15:07:35.262658 Building ramdisk /var/lib/lava/dispatcher/tmp/10660955/extract-overlay-ramdisk-wfjf6xvq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10660955/extract-overlay-ramdisk-wfjf6xvq/ramdisk
196 15:07:35.416517 >> 53979 blocks
197 15:07:36.523131 rename /var/lib/lava/dispatcher/tmp/10660955/extract-overlay-ramdisk-wfjf6xvq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
198 15:07:36.523740 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 15:07:36.523938 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 15:07:36.524105 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 15:07:36.524267 No mkimage arch provided, not using FIT.
202 15:07:36.524408 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 15:07:36.524551 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 15:07:36.524719 end: 1.4 prepare-tftp-overlay (duration 00:00:02) [common]
205 15:07:36.524878 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 15:07:36.525016 No LXC device requested
207 15:07:36.525165 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 15:07:36.525327 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 15:07:36.525455 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 15:07:36.525586 Checking files for TFTP limit of 4294967296 bytes.
211 15:07:36.526185 end: 1 tftp-deploy (duration 00:00:02) [common]
212 15:07:36.526358 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 15:07:36.526512 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 15:07:36.526710 substitutions:
215 15:07:36.526832 - {DTB}: None
216 15:07:36.526944 - {INITRD}: 10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
217 15:07:36.527055 - {KERNEL}: 10660955/tftp-deploy-khoypiv0/kernel/bzImage
218 15:07:36.527153 - {LAVA_MAC}: None
219 15:07:36.527262 - {PRESEED_CONFIG}: None
220 15:07:36.527365 - {PRESEED_LOCAL}: None
221 15:07:36.527473 - {RAMDISK}: 10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
222 15:07:36.527589 - {ROOT_PART}: None
223 15:07:36.527690 - {ROOT}: None
224 15:07:36.527800 - {SERVER_IP}: 192.168.201.1
225 15:07:36.527901 - {TEE}: None
226 15:07:36.528003 Parsed boot commands:
227 15:07:36.528108 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 15:07:36.528376 Parsed boot commands: tftpboot 192.168.201.1 10660955/tftp-deploy-khoypiv0/kernel/bzImage 10660955/tftp-deploy-khoypiv0/kernel/cmdline 10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
229 15:07:36.528533 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 15:07:36.528680 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 15:07:36.528837 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 15:07:36.528976 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 15:07:36.529109 Not connected, no need to disconnect.
234 15:07:36.529240 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 15:07:36.529389 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 15:07:36.529514 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-4'
237 15:07:36.533881 Setting prompt string to ['lava-test: # ']
238 15:07:36.534405 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 15:07:36.534583 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 15:07:36.534750 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 15:07:36.534904 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 15:07:36.535240 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=reboot'
243 15:07:41.678949 >> Command sent successfully.
244 15:07:41.682411 Returned 0 in 5 seconds
245 15:07:41.782834 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 15:07:41.783321 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 15:07:41.783488 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 15:07:41.783634 Setting prompt string to 'Starting depthcharge on Helios...'
250 15:07:41.783753 Changing prompt to 'Starting depthcharge on Helios...'
251 15:07:41.783878 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
252 15:07:41.784213 [Enter `^Ec?' for help]
253 15:07:42.405280
254 15:07:42.405435
255 15:07:42.414643 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
256 15:07:42.418198 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
257 15:07:42.424680 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
258 15:07:42.428254 CPU: AES supported, TXT NOT supported, VT supported
259 15:07:42.435067 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
260 15:07:42.438584 PCH: device id 0284 (rev 00) is Cometlake-U Premium
261 15:07:42.445318 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
262 15:07:42.448265 VBOOT: Loading verstage.
263 15:07:42.451545 FMAP: Found "FLASH" version 1.1 at 0xc04000.
264 15:07:42.458472 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
265 15:07:42.462066 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
266 15:07:42.465118 CBFS @ c08000 size 3f8000
267 15:07:42.471731 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
268 15:07:42.474789 CBFS: Locating 'fallback/verstage'
269 15:07:42.478293 CBFS: Found @ offset 10fb80 size 1072c
270 15:07:42.478413
271 15:07:42.478525
272 15:07:42.491617 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
273 15:07:42.505683 Probing TPM: . done!
274 15:07:42.508755 TPM ready after 0 ms
275 15:07:42.512383 Connected to device vid:did:rid of 1ae0:0028:00
276 15:07:42.522376 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.153/cr50_v2.94_mp.151-b967c9caf7
277 15:07:42.526050 Initialized TPM device CR50 revision 0
278 15:07:42.567275 tlcl_send_startup: Startup return code is 0
279 15:07:42.567466 TPM: setup succeeded
280 15:07:42.579972 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
281 15:07:42.583574 Chrome EC: UHEPI supported
282 15:07:42.587222 Phase 1
283 15:07:42.590169 FMAP: area GBB found @ c05000 (12288 bytes)
284 15:07:42.596897 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
285 15:07:42.597060 Phase 2
286 15:07:42.599981 Phase 3
287 15:07:42.603750 FMAP: area GBB found @ c05000 (12288 bytes)
288 15:07:42.610500 VB2:vb2_report_dev_firmware() This is developer signed firmware
289 15:07:42.616669 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
290 15:07:42.620567 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
291 15:07:42.626718 VB2:vb2_verify_keyblock() Checking keyblock signature...
292 15:07:42.642117 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
293 15:07:42.645750 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
294 15:07:42.652296 VB2:vb2_verify_fw_preamble() Verifying preamble.
295 15:07:42.656285 Phase 4
296 15:07:42.660079 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
297 15:07:42.666140 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
298 15:07:42.845878 VB2:vb2_rsa_verify_digest() Digest check failed!
299 15:07:42.852222 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
300 15:07:42.852377 Saving nvdata
301 15:07:42.855748 Reboot requested (10020007)
302 15:07:42.859246 board_reset() called!
303 15:07:42.859400 full_reset() called!
304 15:07:47.372221
305 15:07:47.372640
306 15:07:47.382315 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
307 15:07:47.385360 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
308 15:07:47.392668 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
309 15:07:47.395850 CPU: AES supported, TXT NOT supported, VT supported
310 15:07:47.401983 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
311 15:07:47.405350 PCH: device id 0284 (rev 00) is Cometlake-U Premium
312 15:07:47.412518 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
313 15:07:47.415919 VBOOT: Loading verstage.
314 15:07:47.418644 FMAP: Found "FLASH" version 1.1 at 0xc04000.
315 15:07:47.425427 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
316 15:07:47.428662 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
317 15:07:47.432412 CBFS @ c08000 size 3f8000
318 15:07:47.438598 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
319 15:07:47.442331 CBFS: Locating 'fallback/verstage'
320 15:07:47.445381 CBFS: Found @ offset 10fb80 size 1072c
321 15:07:47.449122
322 15:07:47.449459
323 15:07:47.458684 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
324 15:07:47.472752 Probing TPM: . done!
325 15:07:47.476271 TPM ready after 0 ms
326 15:07:47.479786 Connected to device vid:did:rid of 1ae0:0028:00
327 15:07:47.489818 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.153/cr50_v2.94_mp.151-b967c9caf7
328 15:07:47.493931 Initialized TPM device CR50 revision 0
329 15:07:47.534289 tlcl_send_startup: Startup return code is 0
330 15:07:47.534643 TPM: setup succeeded
331 15:07:47.547199 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
332 15:07:47.550935 Chrome EC: UHEPI supported
333 15:07:47.554175 Phase 1
334 15:07:47.557884 FMAP: area GBB found @ c05000 (12288 bytes)
335 15:07:47.564236 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
336 15:07:47.570802 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
337 15:07:47.574069 Recovery requested (1009000e)
338 15:07:47.579661 Saving nvdata
339 15:07:47.585981 tlcl_extend: response is 0
340 15:07:47.594615 tlcl_extend: response is 0
341 15:07:47.601874 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
342 15:07:47.605382 CBFS @ c08000 size 3f8000
343 15:07:47.611842 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
344 15:07:47.614856 CBFS: Locating 'fallback/romstage'
345 15:07:47.617964 CBFS: Found @ offset 80 size 145fc
346 15:07:47.621787 Accumulated console time in verstage 98 ms
347 15:07:47.621885
348 15:07:47.621961
349 15:07:47.634764 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
350 15:07:47.641450 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
351 15:07:47.644722 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
352 15:07:47.648033 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
353 15:07:47.654839 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
354 15:07:47.657874 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
355 15:07:47.660948 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
356 15:07:47.664286 TCO_STS: 0000 0000
357 15:07:47.667605 GEN_PMCON: e0015238 00000200
358 15:07:47.670787 GBLRST_CAUSE: 00000000 00000000
359 15:07:47.670924 prev_sleep_state 5
360 15:07:47.674340 Boot Count incremented to 58780
361 15:07:47.681355 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
362 15:07:47.684657 CBFS @ c08000 size 3f8000
363 15:07:47.690882 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
364 15:07:47.691004 CBFS: Locating 'fspm.bin'
365 15:07:47.697902 CBFS: Found @ offset 5ffc0 size 71000
366 15:07:47.701337 Chrome EC: UHEPI supported
367 15:07:47.708008 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
368 15:07:47.711925 Probing TPM: done!
369 15:07:47.718536 Connected to device vid:did:rid of 1ae0:0028:00
370 15:07:47.728424 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.153/cr50_v2.94_mp.151-b967c9caf7
371 15:07:47.734531 Initialized TPM device CR50 revision 0
372 15:07:47.743130 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
373 15:07:47.749706 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
374 15:07:47.753002 MRC cache found, size 1948
375 15:07:47.756469 bootmode is set to: 2
376 15:07:47.759755 PRMRR disabled by config.
377 15:07:47.760042 SPD INDEX = 1
378 15:07:47.766683 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
379 15:07:47.770129 CBFS @ c08000 size 3f8000
380 15:07:47.776607 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
381 15:07:47.776900 CBFS: Locating 'spd.bin'
382 15:07:47.779646 CBFS: Found @ offset 5fb80 size 400
383 15:07:47.783212 SPD: module type is LPDDR3
384 15:07:47.786460 SPD: module part is
385 15:07:47.793364 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
386 15:07:47.796823 SPD: device width 4 bits, bus width 8 bits
387 15:07:47.799614 SPD: module size is 4096 MB (per channel)
388 15:07:47.802901 memory slot: 0 configuration done.
389 15:07:47.806347 memory slot: 2 configuration done.
390 15:07:47.858020 CBMEM:
391 15:07:47.861386 IMD: root @ 99fff000 254 entries.
392 15:07:47.864551 IMD: root @ 99ffec00 62 entries.
393 15:07:47.867826 External stage cache:
394 15:07:47.871436 IMD: root @ 9abff000 254 entries.
395 15:07:47.874688 IMD: root @ 9abfec00 62 entries.
396 15:07:47.878024 Chrome EC: clear events_b mask to 0x0000000020004000
397 15:07:47.893935 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
398 15:07:47.907511 tlcl_write: response is 0
399 15:07:47.916250 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
400 15:07:47.923407 MRC: TPM MRC hash updated successfully.
401 15:07:47.923944 2 DIMMs found
402 15:07:47.926634 SMM Memory Map
403 15:07:47.930031 SMRAM : 0x9a000000 0x1000000
404 15:07:47.933336 Subregion 0: 0x9a000000 0xa00000
405 15:07:47.936578 Subregion 1: 0x9aa00000 0x200000
406 15:07:47.939913 Subregion 2: 0x9ac00000 0x400000
407 15:07:47.943062 top_of_ram = 0x9a000000
408 15:07:47.946145 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
409 15:07:47.952953 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
410 15:07:47.956319 MTRR Range: Start=ff000000 End=0 (Size 1000000)
411 15:07:47.962693 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
412 15:07:47.966210 CBFS @ c08000 size 3f8000
413 15:07:47.969534 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
414 15:07:47.973014 CBFS: Locating 'fallback/postcar'
415 15:07:47.976414 CBFS: Found @ offset 107000 size 4b44
416 15:07:47.983007 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
417 15:07:47.994956 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
418 15:07:47.997726 Processing 180 relocs. Offset value of 0x97c0c000
419 15:07:48.006776 Accumulated console time in romstage 286 ms
420 15:07:48.007116
421 15:07:48.007412
422 15:07:48.016999 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
423 15:07:48.023015 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
424 15:07:48.026971 CBFS @ c08000 size 3f8000
425 15:07:48.030298 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
426 15:07:48.036558 CBFS: Locating 'fallback/ramstage'
427 15:07:48.039936 CBFS: Found @ offset 43380 size 1b9e8
428 15:07:48.046667 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
429 15:07:48.078883 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
430 15:07:48.082364 Processing 3976 relocs. Offset value of 0x98db0000
431 15:07:48.089010 Accumulated console time in postcar 52 ms
432 15:07:48.089432
433 15:07:48.089745
434 15:07:48.098377 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
435 15:07:48.105560 FMAP: area RO_VPD found @ c00000 (16384 bytes)
436 15:07:48.108834 WARNING: RO_VPD is uninitialized or empty.
437 15:07:48.111684 FMAP: area RW_VPD found @ af8000 (8192 bytes)
438 15:07:48.118385 FMAP: area RW_VPD found @ af8000 (8192 bytes)
439 15:07:48.118958 Normal boot.
440 15:07:48.125436 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
441 15:07:48.128773 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
442 15:07:48.131866 CBFS @ c08000 size 3f8000
443 15:07:48.138398 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
444 15:07:48.141692 CBFS: Locating 'cpu_microcode_blob.bin'
445 15:07:48.145228 CBFS: Found @ offset 14700 size 2ec00
446 15:07:48.148598 microcode: sig=0x806ec pf=0x4 revision=0xc9
447 15:07:48.152007 Skip microcode update
448 15:07:48.154860 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
449 15:07:48.158160 CBFS @ c08000 size 3f8000
450 15:07:48.164758 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
451 15:07:48.168027 CBFS: Locating 'fsps.bin'
452 15:07:48.171319 CBFS: Found @ offset d1fc0 size 35000
453 15:07:48.196893 Detected 4 core, 8 thread CPU.
454 15:07:48.200390 Setting up SMI for CPU
455 15:07:48.203614 IED base = 0x9ac00000
456 15:07:48.203895 IED size = 0x00400000
457 15:07:48.206967 Will perform SMM setup.
458 15:07:48.213802 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
459 15:07:48.219836 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
460 15:07:48.223097 Processing 16 relocs. Offset value of 0x00030000
461 15:07:48.227161 Attempting to start 7 APs
462 15:07:48.230558 Waiting for 10ms after sending INIT.
463 15:07:48.246739 Waiting for 1st SIPI to complete...done.
464 15:07:48.247142 AP: slot 3 apic_id 1.
465 15:07:48.253059 Waiting for 2nd SIPI to complete...done.
466 15:07:48.253450 AP: slot 1 apic_id 2.
467 15:07:48.256365 AP: slot 4 apic_id 3.
468 15:07:48.259590 AP: slot 5 apic_id 6.
469 15:07:48.259994 AP: slot 2 apic_id 7.
470 15:07:48.263555 AP: slot 6 apic_id 4.
471 15:07:48.266697 AP: slot 7 apic_id 5.
472 15:07:48.273158 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
473 15:07:48.276425 Processing 13 relocs. Offset value of 0x00038000
474 15:07:48.283035 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
475 15:07:48.290187 Installing SMM handler to 0x9a000000
476 15:07:48.296757 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
477 15:07:48.300029 Processing 658 relocs. Offset value of 0x9a010000
478 15:07:48.309596 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
479 15:07:48.312798 Processing 13 relocs. Offset value of 0x9a008000
480 15:07:48.319969 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
481 15:07:48.326207 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
482 15:07:48.329597 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
483 15:07:48.336476 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
484 15:07:48.343022 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
485 15:07:48.349180 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
486 15:07:48.352968 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
487 15:07:48.359497 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
488 15:07:48.362753 Clearing SMI status registers
489 15:07:48.366057 SMI_STS: PM1
490 15:07:48.366449 PM1_STS: PWRBTN
491 15:07:48.369369 TCO_STS: SECOND_TO
492 15:07:48.372663 New SMBASE 0x9a000000
493 15:07:48.376005 In relocation handler: CPU 0
494 15:07:48.379200 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
495 15:07:48.382471 Writing SMRR. base = 0x9a000006, mask=0xff000800
496 15:07:48.385694 Relocation complete.
497 15:07:48.389017 New SMBASE 0x99fff400
498 15:07:48.389235 In relocation handler: CPU 3
499 15:07:48.395673 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
500 15:07:48.399154 Writing SMRR. base = 0x9a000006, mask=0xff000800
501 15:07:48.402686 Relocation complete.
502 15:07:48.402862 New SMBASE 0x99ffe800
503 15:07:48.406365 In relocation handler: CPU 6
504 15:07:48.412762 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
505 15:07:48.416038 Writing SMRR. base = 0x9a000006, mask=0xff000800
506 15:07:48.419375 Relocation complete.
507 15:07:48.419639 New SMBASE 0x99ffe400
508 15:07:48.422716 In relocation handler: CPU 7
509 15:07:48.429549 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
510 15:07:48.432261 Writing SMRR. base = 0x9a000006, mask=0xff000800
511 15:07:48.435795 Relocation complete.
512 15:07:48.436036 New SMBASE 0x99ffec00
513 15:07:48.439055 In relocation handler: CPU 5
514 15:07:48.442585 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
515 15:07:48.448839 Writing SMRR. base = 0x9a000006, mask=0xff000800
516 15:07:48.452311 Relocation complete.
517 15:07:48.452516 New SMBASE 0x99fff800
518 15:07:48.455622 In relocation handler: CPU 2
519 15:07:48.458839 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
520 15:07:48.466016 Writing SMRR. base = 0x9a000006, mask=0xff000800
521 15:07:48.466263 Relocation complete.
522 15:07:48.469203 New SMBASE 0x99fff000
523 15:07:48.472306 In relocation handler: CPU 4
524 15:07:48.475739 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
525 15:07:48.482496 Writing SMRR. base = 0x9a000006, mask=0xff000800
526 15:07:48.482750 Relocation complete.
527 15:07:48.485944 New SMBASE 0x99fffc00
528 15:07:48.489177 In relocation handler: CPU 1
529 15:07:48.492342 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
530 15:07:48.498839 Writing SMRR. base = 0x9a000006, mask=0xff000800
531 15:07:48.499009 Relocation complete.
532 15:07:48.502278 Initializing CPU #0
533 15:07:48.505777 CPU: vendor Intel device 806ec
534 15:07:48.509058 CPU: family 06, model 8e, stepping 0c
535 15:07:48.512308 Clearing out pending MCEs
536 15:07:48.515470 Setting up local APIC...
537 15:07:48.515567 apic_id: 0x00 done.
538 15:07:48.518826 Turbo is available but hidden
539 15:07:48.522161 Turbo is available and visible
540 15:07:48.525455 VMX status: enabled
541 15:07:48.528660 IA32_FEATURE_CONTROL status: locked
542 15:07:48.532018 Skip microcode update
543 15:07:48.532111 CPU #0 initialized
544 15:07:48.535397 Initializing CPU #3
545 15:07:48.535510 Initializing CPU #6
546 15:07:48.538819 Initializing CPU #7
547 15:07:48.542054 CPU: vendor Intel device 806ec
548 15:07:48.545351 CPU: family 06, model 8e, stepping 0c
549 15:07:48.548976 CPU: vendor Intel device 806ec
550 15:07:48.552222 CPU: family 06, model 8e, stepping 0c
551 15:07:48.555703 Clearing out pending MCEs
552 15:07:48.558510 Clearing out pending MCEs
553 15:07:48.558604 Initializing CPU #5
554 15:07:48.561783 Initializing CPU #2
555 15:07:48.565032 CPU: vendor Intel device 806ec
556 15:07:48.568944 CPU: family 06, model 8e, stepping 0c
557 15:07:48.572018 CPU: vendor Intel device 806ec
558 15:07:48.575016 CPU: family 06, model 8e, stepping 0c
559 15:07:48.578871 Clearing out pending MCEs
560 15:07:48.582024 Clearing out pending MCEs
561 15:07:48.582128 Setting up local APIC...
562 15:07:48.585221 Initializing CPU #4
563 15:07:48.588558 Initializing CPU #1
564 15:07:48.591886 CPU: vendor Intel device 806ec
565 15:07:48.595124 CPU: family 06, model 8e, stepping 0c
566 15:07:48.598547 CPU: vendor Intel device 806ec
567 15:07:48.601629 CPU: family 06, model 8e, stepping 0c
568 15:07:48.605464 Clearing out pending MCEs
569 15:07:48.605588 Clearing out pending MCEs
570 15:07:48.608300 Setting up local APIC...
571 15:07:48.611571 CPU: vendor Intel device 806ec
572 15:07:48.615348 CPU: family 06, model 8e, stepping 0c
573 15:07:48.618489 Clearing out pending MCEs
574 15:07:48.621820 Setting up local APIC...
575 15:07:48.621986 apic_id: 0x07 done.
576 15:07:48.625192 Setting up local APIC...
577 15:07:48.628572 apic_id: 0x03 done.
578 15:07:48.631824 apic_id: 0x02 done.
579 15:07:48.631958 VMX status: enabled
580 15:07:48.635109 VMX status: enabled
581 15:07:48.638614 IA32_FEATURE_CONTROL status: locked
582 15:07:48.641892 IA32_FEATURE_CONTROL status: locked
583 15:07:48.645180 Skip microcode update
584 15:07:48.645492 Skip microcode update
585 15:07:48.648430 CPU #4 initialized
586 15:07:48.648735 CPU #1 initialized
587 15:07:48.651897 VMX status: enabled
588 15:07:48.655380 apic_id: 0x06 done.
589 15:07:48.658880 IA32_FEATURE_CONTROL status: locked
590 15:07:48.659166 VMX status: enabled
591 15:07:48.662262 Skip microcode update
592 15:07:48.665121 IA32_FEATURE_CONTROL status: locked
593 15:07:48.668269 CPU #2 initialized
594 15:07:48.668611 Skip microcode update
595 15:07:48.672088 Setting up local APIC...
596 15:07:48.675198 CPU #5 initialized
597 15:07:48.678581 Setting up local APIC...
598 15:07:48.678934 apic_id: 0x04 done.
599 15:07:48.681782 Setting up local APIC...
600 15:07:48.684969 apic_id: 0x01 done.
601 15:07:48.685362 apic_id: 0x05 done.
602 15:07:48.688522 VMX status: enabled
603 15:07:48.688917 VMX status: enabled
604 15:07:48.694754 IA32_FEATURE_CONTROL status: locked
605 15:07:48.698271 IA32_FEATURE_CONTROL status: locked
606 15:07:48.698658 Skip microcode update
607 15:07:48.701608 Skip microcode update
608 15:07:48.705088 CPU #6 initialized
609 15:07:48.705484 CPU #7 initialized
610 15:07:48.708397 VMX status: enabled
611 15:07:48.711359 IA32_FEATURE_CONTROL status: locked
612 15:07:48.714572 Skip microcode update
613 15:07:48.714938 CPU #3 initialized
614 15:07:48.718122 bsp_do_flight_plan done after 466 msecs.
615 15:07:48.721434 CPU: frequency set to 4200 MHz
616 15:07:48.724852 Enabling SMIs.
617 15:07:48.725134 Locking SMM.
618 15:07:48.740412 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
619 15:07:48.743774 CBFS @ c08000 size 3f8000
620 15:07:48.750404 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
621 15:07:48.750680 CBFS: Locating 'vbt.bin'
622 15:07:48.753963 CBFS: Found @ offset 5f5c0 size 499
623 15:07:48.760757 Found a VBT of 4608 bytes after decompression
624 15:07:48.942291 Display FSP Version Info HOB
625 15:07:48.945608 Reference Code - CPU = 9.0.1e.30
626 15:07:48.948884 uCode Version = 0.0.0.ca
627 15:07:48.952662 TXT ACM version = ff.ff.ff.ffff
628 15:07:48.955841 Display FSP Version Info HOB
629 15:07:48.959177 Reference Code - ME = 9.0.1e.30
630 15:07:48.962619 MEBx version = 0.0.0.0
631 15:07:48.966326 ME Firmware Version = Consumer SKU
632 15:07:48.969604 Display FSP Version Info HOB
633 15:07:48.972053 Reference Code - CML PCH = 9.0.1e.30
634 15:07:48.975412 PCH-CRID Status = Disabled
635 15:07:48.978741 PCH-CRID Original Value = ff.ff.ff.ffff
636 15:07:48.982114 PCH-CRID New Value = ff.ff.ff.ffff
637 15:07:48.985255 OPROM - RST - RAID = ff.ff.ff.ffff
638 15:07:48.988992 ChipsetInit Base Version = ff.ff.ff.ffff
639 15:07:48.992123 ChipsetInit Oem Version = ff.ff.ff.ffff
640 15:07:48.995416 Display FSP Version Info HOB
641 15:07:49.002400 Reference Code - SA - System Agent = 9.0.1e.30
642 15:07:49.005293 Reference Code - MRC = 0.7.1.6c
643 15:07:49.005746 SA - PCIe Version = 9.0.1e.30
644 15:07:49.009025 SA-CRID Status = Disabled
645 15:07:49.012054 SA-CRID Original Value = 0.0.0.c
646 15:07:49.015344 SA-CRID New Value = 0.0.0.c
647 15:07:49.018755 OPROM - VBIOS = ff.ff.ff.ffff
648 15:07:49.022417 RTC Init
649 15:07:49.025123 Set power on after power failure.
650 15:07:49.025561 Disabling Deep S3
651 15:07:49.028582 Disabling Deep S3
652 15:07:49.029120 Disabling Deep S4
653 15:07:49.031724 Disabling Deep S4
654 15:07:49.032156 Disabling Deep S5
655 15:07:49.035076 Disabling Deep S5
656 15:07:49.041921 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 192 exit 1
657 15:07:49.042359 Enumerating buses...
658 15:07:49.048439 Show all devs... Before device enumeration.
659 15:07:49.048888 Root Device: enabled 1
660 15:07:49.051575 CPU_CLUSTER: 0: enabled 1
661 15:07:49.055232 DOMAIN: 0000: enabled 1
662 15:07:49.058410 APIC: 00: enabled 1
663 15:07:49.058845 PCI: 00:00.0: enabled 1
664 15:07:49.061578 PCI: 00:02.0: enabled 1
665 15:07:49.065519 PCI: 00:04.0: enabled 0
666 15:07:49.065950 PCI: 00:05.0: enabled 0
667 15:07:49.069148 PCI: 00:12.0: enabled 1
668 15:07:49.071596 PCI: 00:12.5: enabled 0
669 15:07:49.074976 PCI: 00:12.6: enabled 0
670 15:07:49.075411 PCI: 00:14.0: enabled 1
671 15:07:49.079015 PCI: 00:14.1: enabled 0
672 15:07:49.081954 PCI: 00:14.3: enabled 1
673 15:07:49.085196 PCI: 00:14.5: enabled 0
674 15:07:49.085632 PCI: 00:15.0: enabled 1
675 15:07:49.088507 PCI: 00:15.1: enabled 1
676 15:07:49.091876 PCI: 00:15.2: enabled 0
677 15:07:49.095001 PCI: 00:15.3: enabled 0
678 15:07:49.095506 PCI: 00:16.0: enabled 1
679 15:07:49.098534 PCI: 00:16.1: enabled 0
680 15:07:49.101569 PCI: 00:16.2: enabled 0
681 15:07:49.102005 PCI: 00:16.3: enabled 0
682 15:07:49.104798 PCI: 00:16.4: enabled 0
683 15:07:49.108782 PCI: 00:16.5: enabled 0
684 15:07:49.111954 PCI: 00:17.0: enabled 1
685 15:07:49.112393 PCI: 00:19.0: enabled 1
686 15:07:49.115566 PCI: 00:19.1: enabled 0
687 15:07:49.118515 PCI: 00:19.2: enabled 0
688 15:07:49.121572 PCI: 00:1a.0: enabled 0
689 15:07:49.122008 PCI: 00:1c.0: enabled 0
690 15:07:49.124930 PCI: 00:1c.1: enabled 0
691 15:07:49.128114 PCI: 00:1c.2: enabled 0
692 15:07:49.132034 PCI: 00:1c.3: enabled 0
693 15:07:49.132593 PCI: 00:1c.4: enabled 0
694 15:07:49.135111 PCI: 00:1c.5: enabled 0
695 15:07:49.138531 PCI: 00:1c.6: enabled 0
696 15:07:49.139087 PCI: 00:1c.7: enabled 0
697 15:07:49.141651 PCI: 00:1d.0: enabled 1
698 15:07:49.145005 PCI: 00:1d.1: enabled 0
699 15:07:49.148197 PCI: 00:1d.2: enabled 0
700 15:07:49.148626 PCI: 00:1d.3: enabled 0
701 15:07:49.151356 PCI: 00:1d.4: enabled 0
702 15:07:49.154445 PCI: 00:1d.5: enabled 1
703 15:07:49.158214 PCI: 00:1e.0: enabled 1
704 15:07:49.158645 PCI: 00:1e.1: enabled 0
705 15:07:49.161418 PCI: 00:1e.2: enabled 1
706 15:07:49.164779 PCI: 00:1e.3: enabled 1
707 15:07:49.165210 PCI: 00:1f.0: enabled 1
708 15:07:49.167769 PCI: 00:1f.1: enabled 1
709 15:07:49.171503 PCI: 00:1f.2: enabled 1
710 15:07:49.174944 PCI: 00:1f.3: enabled 1
711 15:07:49.175375 PCI: 00:1f.4: enabled 1
712 15:07:49.178067 PCI: 00:1f.5: enabled 1
713 15:07:49.181466 PCI: 00:1f.6: enabled 0
714 15:07:49.184709 USB0 port 0: enabled 1
715 15:07:49.185138 I2C: 00:15: enabled 1
716 15:07:49.188018 I2C: 00:5d: enabled 1
717 15:07:49.191398 GENERIC: 0.0: enabled 1
718 15:07:49.191861 I2C: 00:1a: enabled 1
719 15:07:49.194728 I2C: 00:38: enabled 1
720 15:07:49.198013 I2C: 00:39: enabled 1
721 15:07:49.198441 I2C: 00:3a: enabled 1
722 15:07:49.201091 I2C: 00:3b: enabled 1
723 15:07:49.205018 PCI: 00:00.0: enabled 1
724 15:07:49.205451 SPI: 00: enabled 1
725 15:07:49.208391 SPI: 01: enabled 1
726 15:07:49.211717 PNP: 0c09.0: enabled 1
727 15:07:49.212147 USB2 port 0: enabled 1
728 15:07:49.215054 USB2 port 1: enabled 1
729 15:07:49.218383 USB2 port 2: enabled 0
730 15:07:49.218810 USB2 port 3: enabled 0
731 15:07:49.221492 USB2 port 5: enabled 0
732 15:07:49.224661 USB2 port 6: enabled 1
733 15:07:49.227659 USB2 port 9: enabled 1
734 15:07:49.228090 USB3 port 0: enabled 1
735 15:07:49.231534 USB3 port 1: enabled 1
736 15:07:49.234736 USB3 port 2: enabled 1
737 15:07:49.235167 USB3 port 3: enabled 1
738 15:07:49.237938 USB3 port 4: enabled 0
739 15:07:49.241080 APIC: 02: enabled 1
740 15:07:49.241498 APIC: 07: enabled 1
741 15:07:49.244380 APIC: 01: enabled 1
742 15:07:49.244774 APIC: 03: enabled 1
743 15:07:49.247670 APIC: 06: enabled 1
744 15:07:49.251519 APIC: 04: enabled 1
745 15:07:49.251909 APIC: 05: enabled 1
746 15:07:49.254690 Compare with tree...
747 15:07:49.257966 Root Device: enabled 1
748 15:07:49.260981 CPU_CLUSTER: 0: enabled 1
749 15:07:49.261378 APIC: 00: enabled 1
750 15:07:49.264114 APIC: 02: enabled 1
751 15:07:49.267935 APIC: 07: enabled 1
752 15:07:49.268328 APIC: 01: enabled 1
753 15:07:49.270942 APIC: 03: enabled 1
754 15:07:49.274388 APIC: 06: enabled 1
755 15:07:49.274780 APIC: 04: enabled 1
756 15:07:49.277599 APIC: 05: enabled 1
757 15:07:49.281506 DOMAIN: 0000: enabled 1
758 15:07:49.281898 PCI: 00:00.0: enabled 1
759 15:07:49.284168 PCI: 00:02.0: enabled 1
760 15:07:49.287841 PCI: 00:04.0: enabled 0
761 15:07:49.291154 PCI: 00:05.0: enabled 0
762 15:07:49.294478 PCI: 00:12.0: enabled 1
763 15:07:49.294888 PCI: 00:12.5: enabled 0
764 15:07:49.297524 PCI: 00:12.6: enabled 0
765 15:07:49.300689 PCI: 00:14.0: enabled 1
766 15:07:49.304365 USB0 port 0: enabled 1
767 15:07:49.307513 USB2 port 0: enabled 1
768 15:07:49.307902 USB2 port 1: enabled 1
769 15:07:49.310419 USB2 port 2: enabled 0
770 15:07:49.313712 USB2 port 3: enabled 0
771 15:07:49.317526 USB2 port 5: enabled 0
772 15:07:49.320869 USB2 port 6: enabled 1
773 15:07:49.324028 USB2 port 9: enabled 1
774 15:07:49.324121 USB3 port 0: enabled 1
775 15:07:49.327339 USB3 port 1: enabled 1
776 15:07:49.330297 USB3 port 2: enabled 1
777 15:07:49.334211 USB3 port 3: enabled 1
778 15:07:49.337380 USB3 port 4: enabled 0
779 15:07:49.337489 PCI: 00:14.1: enabled 0
780 15:07:49.340221 PCI: 00:14.3: enabled 1
781 15:07:49.343818 PCI: 00:14.5: enabled 0
782 15:07:49.347073 PCI: 00:15.0: enabled 1
783 15:07:49.350363 I2C: 00:15: enabled 1
784 15:07:49.350465 PCI: 00:15.1: enabled 1
785 15:07:49.353696 I2C: 00:5d: enabled 1
786 15:07:49.357012 GENERIC: 0.0: enabled 1
787 15:07:49.360320 PCI: 00:15.2: enabled 0
788 15:07:49.364024 PCI: 00:15.3: enabled 0
789 15:07:49.364117 PCI: 00:16.0: enabled 1
790 15:07:49.367280 PCI: 00:16.1: enabled 0
791 15:07:49.370575 PCI: 00:16.2: enabled 0
792 15:07:49.373786 PCI: 00:16.3: enabled 0
793 15:07:49.373879 PCI: 00:16.4: enabled 0
794 15:07:49.376932 PCI: 00:16.5: enabled 0
795 15:07:49.380083 PCI: 00:17.0: enabled 1
796 15:07:49.383689 PCI: 00:19.0: enabled 1
797 15:07:49.386962 I2C: 00:1a: enabled 1
798 15:07:49.387056 I2C: 00:38: enabled 1
799 15:07:49.390234 I2C: 00:39: enabled 1
800 15:07:49.393451 I2C: 00:3a: enabled 1
801 15:07:49.396674 I2C: 00:3b: enabled 1
802 15:07:49.396768 PCI: 00:19.1: enabled 0
803 15:07:49.400385 PCI: 00:19.2: enabled 0
804 15:07:49.403762 PCI: 00:1a.0: enabled 0
805 15:07:49.407012 PCI: 00:1c.0: enabled 0
806 15:07:49.410088 PCI: 00:1c.1: enabled 0
807 15:07:49.410182 PCI: 00:1c.2: enabled 0
808 15:07:49.413222 PCI: 00:1c.3: enabled 0
809 15:07:49.416428 PCI: 00:1c.4: enabled 0
810 15:07:49.419737 PCI: 00:1c.5: enabled 0
811 15:07:49.423609 PCI: 00:1c.6: enabled 0
812 15:07:49.423693 PCI: 00:1c.7: enabled 0
813 15:07:49.426877 PCI: 00:1d.0: enabled 1
814 15:07:49.430161 PCI: 00:1d.1: enabled 0
815 15:07:49.433363 PCI: 00:1d.2: enabled 0
816 15:07:49.436792 PCI: 00:1d.3: enabled 0
817 15:07:49.436877 PCI: 00:1d.4: enabled 0
818 15:07:49.439789 PCI: 00:1d.5: enabled 1
819 15:07:49.443006 PCI: 00:00.0: enabled 1
820 15:07:49.446378 PCI: 00:1e.0: enabled 1
821 15:07:49.449662 PCI: 00:1e.1: enabled 0
822 15:07:49.449755 PCI: 00:1e.2: enabled 1
823 15:07:49.453243 SPI: 00: enabled 1
824 15:07:49.456624 PCI: 00:1e.3: enabled 1
825 15:07:49.456716 SPI: 01: enabled 1
826 15:07:49.459722 PCI: 00:1f.0: enabled 1
827 15:07:49.463041 PNP: 0c09.0: enabled 1
828 15:07:49.466455 PCI: 00:1f.1: enabled 1
829 15:07:49.470122 PCI: 00:1f.2: enabled 1
830 15:07:49.470215 PCI: 00:1f.3: enabled 1
831 15:07:49.473446 PCI: 00:1f.4: enabled 1
832 15:07:49.476374 PCI: 00:1f.5: enabled 1
833 15:07:49.479973 PCI: 00:1f.6: enabled 0
834 15:07:49.483073 Root Device scanning...
835 15:07:49.486239 scan_static_bus for Root Device
836 15:07:49.486331 CPU_CLUSTER: 0 enabled
837 15:07:49.489966 DOMAIN: 0000 enabled
838 15:07:49.493025 DOMAIN: 0000 scanning...
839 15:07:49.496575 PCI: pci_scan_bus for bus 00
840 15:07:49.499484 PCI: 00:00.0 [8086/0000] ops
841 15:07:49.503350 PCI: 00:00.0 [8086/9b61] enabled
842 15:07:49.506688 PCI: 00:02.0 [8086/0000] bus ops
843 15:07:49.510070 PCI: 00:02.0 [8086/9b41] enabled
844 15:07:49.513246 PCI: 00:04.0 [8086/1903] disabled
845 15:07:49.516307 PCI: 00:08.0 [8086/1911] enabled
846 15:07:49.520001 PCI: 00:12.0 [8086/02f9] enabled
847 15:07:49.523329 PCI: 00:14.0 [8086/0000] bus ops
848 15:07:49.526757 PCI: 00:14.0 [8086/02ed] enabled
849 15:07:49.530025 PCI: 00:14.2 [8086/02ef] enabled
850 15:07:49.533289 PCI: 00:14.3 [8086/02f0] enabled
851 15:07:49.535990 PCI: 00:15.0 [8086/0000] bus ops
852 15:07:49.539344 PCI: 00:15.0 [8086/02e8] enabled
853 15:07:49.543134 PCI: 00:15.1 [8086/0000] bus ops
854 15:07:49.546199 PCI: 00:15.1 [8086/02e9] enabled
855 15:07:49.546293 PCI: 00:16.0 [8086/0000] ops
856 15:07:49.549500 PCI: 00:16.0 [8086/02e0] enabled
857 15:07:49.552795 PCI: 00:17.0 [8086/0000] ops
858 15:07:49.556065 PCI: 00:17.0 [8086/02d3] enabled
859 15:07:49.559706 PCI: 00:19.0 [8086/0000] bus ops
860 15:07:49.562725 PCI: 00:19.0 [8086/02c5] enabled
861 15:07:49.566525 PCI: 00:1d.0 [8086/0000] bus ops
862 15:07:49.569658 PCI: 00:1d.0 [8086/02b0] enabled
863 15:07:49.576715 PCI: Static device PCI: 00:1d.5 not found, disabling it.
864 15:07:49.579918 PCI: 00:1e.0 [8086/0000] ops
865 15:07:49.583070 PCI: 00:1e.0 [8086/02a8] enabled
866 15:07:49.586324 PCI: 00:1e.2 [8086/0000] bus ops
867 15:07:49.589661 PCI: 00:1e.2 [8086/02aa] enabled
868 15:07:49.592891 PCI: 00:1e.3 [8086/0000] bus ops
869 15:07:49.596455 PCI: 00:1e.3 [8086/02ab] enabled
870 15:07:49.599693 PCI: 00:1f.0 [8086/0000] bus ops
871 15:07:49.602872 PCI: 00:1f.0 [8086/0284] enabled
872 15:07:49.609719 PCI: Static device PCI: 00:1f.1 not found, disabling it.
873 15:07:49.612975 PCI: Static device PCI: 00:1f.2 not found, disabling it.
874 15:07:49.616231 PCI: 00:1f.3 [8086/0000] bus ops
875 15:07:49.620005 PCI: 00:1f.3 [8086/02c8] enabled
876 15:07:49.622930 PCI: 00:1f.4 [8086/0000] bus ops
877 15:07:49.626237 PCI: 00:1f.4 [8086/02a3] enabled
878 15:07:49.629705 PCI: 00:1f.5 [8086/0000] bus ops
879 15:07:49.633180 PCI: 00:1f.5 [8086/02a4] enabled
880 15:07:49.636386 PCI: Leftover static devices:
881 15:07:49.639849 PCI: 00:05.0
882 15:07:49.639978 PCI: 00:12.5
883 15:07:49.640089 PCI: 00:12.6
884 15:07:49.643312 PCI: 00:14.1
885 15:07:49.643435 PCI: 00:14.5
886 15:07:49.646716 PCI: 00:15.2
887 15:07:49.646843 PCI: 00:15.3
888 15:07:49.646954 PCI: 00:16.1
889 15:07:49.649985 PCI: 00:16.2
890 15:07:49.650107 PCI: 00:16.3
891 15:07:49.652863 PCI: 00:16.4
892 15:07:49.652983 PCI: 00:16.5
893 15:07:49.653090 PCI: 00:19.1
894 15:07:49.656144 PCI: 00:19.2
895 15:07:49.656257 PCI: 00:1a.0
896 15:07:49.659534 PCI: 00:1c.0
897 15:07:49.659624 PCI: 00:1c.1
898 15:07:49.663211 PCI: 00:1c.2
899 15:07:49.663325 PCI: 00:1c.3
900 15:07:49.663428 PCI: 00:1c.4
901 15:07:49.666232 PCI: 00:1c.5
902 15:07:49.666349 PCI: 00:1c.6
903 15:07:49.669939 PCI: 00:1c.7
904 15:07:49.670055 PCI: 00:1d.1
905 15:07:49.670158 PCI: 00:1d.2
906 15:07:49.673040 PCI: 00:1d.3
907 15:07:49.673159 PCI: 00:1d.4
908 15:07:49.676358 PCI: 00:1d.5
909 15:07:49.676475 PCI: 00:1e.1
910 15:07:49.676582 PCI: 00:1f.1
911 15:07:49.679516 PCI: 00:1f.2
912 15:07:49.679602 PCI: 00:1f.6
913 15:07:49.683136 PCI: Check your devicetree.cb.
914 15:07:49.686672 PCI: 00:02.0 scanning...
915 15:07:49.689866 scan_generic_bus for PCI: 00:02.0
916 15:07:49.693122 scan_generic_bus for PCI: 00:02.0 done
917 15:07:49.699450 scan_bus: scanning of bus PCI: 00:02.0 took 10183 usecs
918 15:07:49.702755 PCI: 00:14.0 scanning...
919 15:07:49.706206 scan_static_bus for PCI: 00:14.0
920 15:07:49.706337 USB0 port 0 enabled
921 15:07:49.709476 USB0 port 0 scanning...
922 15:07:49.712803 scan_static_bus for USB0 port 0
923 15:07:49.716070 USB2 port 0 enabled
924 15:07:49.716194 USB2 port 1 enabled
925 15:07:49.719350 USB2 port 2 disabled
926 15:07:49.722467 USB2 port 3 disabled
927 15:07:49.722590 USB2 port 5 disabled
928 15:07:49.726132 USB2 port 6 enabled
929 15:07:49.729340 USB2 port 9 enabled
930 15:07:49.729455 USB3 port 0 enabled
931 15:07:49.732705 USB3 port 1 enabled
932 15:07:49.732828 USB3 port 2 enabled
933 15:07:49.735937 USB3 port 3 enabled
934 15:07:49.739355 USB3 port 4 disabled
935 15:07:49.742674 USB2 port 0 scanning...
936 15:07:49.746172 scan_static_bus for USB2 port 0
937 15:07:49.748781 scan_static_bus for USB2 port 0 done
938 15:07:49.752233 scan_bus: scanning of bus USB2 port 0 took 9704 usecs
939 15:07:49.755466 USB2 port 1 scanning...
940 15:07:49.758947 scan_static_bus for USB2 port 1
941 15:07:49.762376 scan_static_bus for USB2 port 1 done
942 15:07:49.769040 scan_bus: scanning of bus USB2 port 1 took 9698 usecs
943 15:07:49.772369 USB2 port 6 scanning...
944 15:07:49.775723 scan_static_bus for USB2 port 6
945 15:07:49.779122 scan_static_bus for USB2 port 6 done
946 15:07:49.782131 scan_bus: scanning of bus USB2 port 6 took 9704 usecs
947 15:07:49.785471 USB2 port 9 scanning...
948 15:07:49.789046 scan_static_bus for USB2 port 9
949 15:07:49.792332 scan_static_bus for USB2 port 9 done
950 15:07:49.798448 scan_bus: scanning of bus USB2 port 9 took 9686 usecs
951 15:07:49.801724 USB3 port 0 scanning...
952 15:07:49.805384 scan_static_bus for USB3 port 0
953 15:07:49.808631 scan_static_bus for USB3 port 0 done
954 15:07:49.811910 scan_bus: scanning of bus USB3 port 0 took 9701 usecs
955 15:07:49.815315 USB3 port 1 scanning...
956 15:07:49.818550 scan_static_bus for USB3 port 1
957 15:07:49.821728 scan_static_bus for USB3 port 1 done
958 15:07:49.828527 scan_bus: scanning of bus USB3 port 1 took 9694 usecs
959 15:07:49.831599 USB3 port 2 scanning...
960 15:07:49.835140 scan_static_bus for USB3 port 2
961 15:07:49.838303 scan_static_bus for USB3 port 2 done
962 15:07:49.844880 scan_bus: scanning of bus USB3 port 2 took 9700 usecs
963 15:07:49.844995 USB3 port 3 scanning...
964 15:07:49.848260 scan_static_bus for USB3 port 3
965 15:07:49.852059 scan_static_bus for USB3 port 3 done
966 15:07:49.858424 scan_bus: scanning of bus USB3 port 3 took 9704 usecs
967 15:07:49.861683 scan_static_bus for USB0 port 0 done
968 15:07:49.868337 scan_bus: scanning of bus USB0 port 0 took 155331 usecs
969 15:07:49.871500 scan_static_bus for PCI: 00:14.0 done
970 15:07:49.877801 scan_bus: scanning of bus PCI: 00:14.0 took 172945 usecs
971 15:07:49.877900 PCI: 00:15.0 scanning...
972 15:07:49.884924 scan_generic_bus for PCI: 00:15.0
973 15:07:49.888358 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
974 15:07:49.891562 scan_generic_bus for PCI: 00:15.0 done
975 15:07:49.898549 scan_bus: scanning of bus PCI: 00:15.0 took 14295 usecs
976 15:07:49.898656 PCI: 00:15.1 scanning...
977 15:07:49.901618 scan_generic_bus for PCI: 00:15.1
978 15:07:49.908095 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
979 15:07:49.911348 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
980 15:07:49.914617 scan_generic_bus for PCI: 00:15.1 done
981 15:07:49.921229 scan_bus: scanning of bus PCI: 00:15.1 took 18612 usecs
982 15:07:49.924561 PCI: 00:19.0 scanning...
983 15:07:49.927974 scan_generic_bus for PCI: 00:19.0
984 15:07:49.931269 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
985 15:07:49.934434 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
986 15:07:49.938105 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
987 15:07:49.944396 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
988 15:07:49.948237 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
989 15:07:49.951356 scan_generic_bus for PCI: 00:19.0 done
990 15:07:49.957957 scan_bus: scanning of bus PCI: 00:19.0 took 30731 usecs
991 15:07:49.958099 PCI: 00:1d.0 scanning...
992 15:07:49.964462 do_pci_scan_bridge for PCI: 00:1d.0
993 15:07:49.964577 PCI: pci_scan_bus for bus 01
994 15:07:49.968392 PCI: 01:00.0 [1c5c/1327] enabled
995 15:07:49.974926 Enabling Common Clock Configuration
996 15:07:49.978030 L1 Sub-State supported from root port 29
997 15:07:49.981986 L1 Sub-State Support = 0xf
998 15:07:49.984644 CommonModeRestoreTime = 0x28
999 15:07:49.988619 Power On Value = 0x16, Power On Scale = 0x0
1000 15:07:49.988717 ASPM: Enabled L1
1001 15:07:49.995217 scan_bus: scanning of bus PCI: 00:1d.0 took 32779 usecs
1002 15:07:49.998531 PCI: 00:1e.2 scanning...
1003 15:07:50.001833 scan_generic_bus for PCI: 00:1e.2
1004 15:07:50.005181 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1005 15:07:50.008262 scan_generic_bus for PCI: 00:1e.2 done
1006 15:07:50.015055 scan_bus: scanning of bus PCI: 00:1e.2 took 14002 usecs
1007 15:07:50.018273 PCI: 00:1e.3 scanning...
1008 15:07:50.021661 scan_generic_bus for PCI: 00:1e.3
1009 15:07:50.025168 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1010 15:07:50.027912 scan_generic_bus for PCI: 00:1e.3 done
1011 15:07:50.034783 scan_bus: scanning of bus PCI: 00:1e.3 took 14000 usecs
1012 15:07:50.037930 PCI: 00:1f.0 scanning...
1013 15:07:50.041003 scan_static_bus for PCI: 00:1f.0
1014 15:07:50.041131 PNP: 0c09.0 enabled
1015 15:07:50.044583 scan_static_bus for PCI: 00:1f.0 done
1016 15:07:50.051335 scan_bus: scanning of bus PCI: 00:1f.0 took 12035 usecs
1017 15:07:50.054538 PCI: 00:1f.3 scanning...
1018 15:07:50.061389 scan_bus: scanning of bus PCI: 00:1f.3 took 2859 usecs
1019 15:07:50.061515 PCI: 00:1f.4 scanning...
1020 15:07:50.064541 scan_generic_bus for PCI: 00:1f.4
1021 15:07:50.071523 scan_generic_bus for PCI: 00:1f.4 done
1022 15:07:50.074703 scan_bus: scanning of bus PCI: 00:1f.4 took 10192 usecs
1023 15:07:50.077964 PCI: 00:1f.5 scanning...
1024 15:07:50.081235 scan_generic_bus for PCI: 00:1f.5
1025 15:07:50.084306 scan_generic_bus for PCI: 00:1f.5 done
1026 15:07:50.091393 scan_bus: scanning of bus PCI: 00:1f.5 took 10184 usecs
1027 15:07:50.097935 scan_bus: scanning of bus DOMAIN: 0000 took 604869 usecs
1028 15:07:50.101172 scan_static_bus for Root Device done
1029 15:07:50.104443 scan_bus: scanning of bus Root Device took 624738 usecs
1030 15:07:50.108365 done
1031 15:07:50.111536 Chrome EC: UHEPI supported
1032 15:07:50.114657 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1033 15:07:50.121657 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1034 15:07:50.128339 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1035 15:07:50.134694 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1036 15:07:50.137961 SPI flash protection: WPSW=0 SRP0=0
1037 15:07:50.144938 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1038 15:07:50.148097 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1039 15:07:50.151392 found VGA at PCI: 00:02.0
1040 15:07:50.154728 Setting up VGA for PCI: 00:02.0
1041 15:07:50.161811 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1042 15:07:50.164789 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1043 15:07:50.168522 Allocating resources...
1044 15:07:50.168637 Reading resources...
1045 15:07:50.174891 Root Device read_resources bus 0 link: 0
1046 15:07:50.178123 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1047 15:07:50.184638 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1048 15:07:50.188214 DOMAIN: 0000 read_resources bus 0 link: 0
1049 15:07:50.194634 PCI: 00:14.0 read_resources bus 0 link: 0
1050 15:07:50.197977 USB0 port 0 read_resources bus 0 link: 0
1051 15:07:50.206419 USB0 port 0 read_resources bus 0 link: 0 done
1052 15:07:50.209650 PCI: 00:14.0 read_resources bus 0 link: 0 done
1053 15:07:50.216899 PCI: 00:15.0 read_resources bus 1 link: 0
1054 15:07:50.220054 PCI: 00:15.0 read_resources bus 1 link: 0 done
1055 15:07:50.226914 PCI: 00:15.1 read_resources bus 2 link: 0
1056 15:07:50.230039 PCI: 00:15.1 read_resources bus 2 link: 0 done
1057 15:07:50.237493 PCI: 00:19.0 read_resources bus 3 link: 0
1058 15:07:50.243944 PCI: 00:19.0 read_resources bus 3 link: 0 done
1059 15:07:50.247193 PCI: 00:1d.0 read_resources bus 1 link: 0
1060 15:07:50.254308 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1061 15:07:50.257657 PCI: 00:1e.2 read_resources bus 4 link: 0
1062 15:07:50.264341 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1063 15:07:50.267537 PCI: 00:1e.3 read_resources bus 5 link: 0
1064 15:07:50.274295 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1065 15:07:50.277352 PCI: 00:1f.0 read_resources bus 0 link: 0
1066 15:07:50.284274 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1067 15:07:50.290644 DOMAIN: 0000 read_resources bus 0 link: 0 done
1068 15:07:50.293980 Root Device read_resources bus 0 link: 0 done
1069 15:07:50.297256 Done reading resources.
1070 15:07:50.300501 Show resources in subtree (Root Device)...After reading.
1071 15:07:50.307204 Root Device child on link 0 CPU_CLUSTER: 0
1072 15:07:50.310549 CPU_CLUSTER: 0 child on link 0 APIC: 00
1073 15:07:50.310664 APIC: 00
1074 15:07:50.313706 APIC: 02
1075 15:07:50.313818 APIC: 07
1076 15:07:50.317609 APIC: 01
1077 15:07:50.317702 APIC: 03
1078 15:07:50.317776 APIC: 06
1079 15:07:50.320949 APIC: 04
1080 15:07:50.321041 APIC: 05
1081 15:07:50.324223 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1082 15:07:50.334013 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1083 15:07:50.386402 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1084 15:07:50.386511 PCI: 00:00.0
1085 15:07:50.386775 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1086 15:07:50.386863 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1087 15:07:50.387557 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1088 15:07:50.387840 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1089 15:07:50.393880 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1090 15:07:50.400846 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1091 15:07:50.410763 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1092 15:07:50.420673 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1093 15:07:50.430303 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1094 15:07:50.440430 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1095 15:07:50.446918 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1096 15:07:50.456614 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1097 15:07:50.466323 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1098 15:07:50.476825 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1099 15:07:50.486400 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1100 15:07:50.496792 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1101 15:07:50.496887 PCI: 00:02.0
1102 15:07:50.506129 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1103 15:07:50.516169 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1104 15:07:50.526127 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1105 15:07:50.529349 PCI: 00:04.0
1106 15:07:50.529447 PCI: 00:08.0
1107 15:07:50.539454 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1108 15:07:50.539551 PCI: 00:12.0
1109 15:07:50.549929 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1110 15:07:50.556031 PCI: 00:14.0 child on link 0 USB0 port 0
1111 15:07:50.566326 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1112 15:07:50.569577 USB0 port 0 child on link 0 USB2 port 0
1113 15:07:50.572777 USB2 port 0
1114 15:07:50.572899 USB2 port 1
1115 15:07:50.576110 USB2 port 2
1116 15:07:50.576198 USB2 port 3
1117 15:07:50.579415 USB2 port 5
1118 15:07:50.579522 USB2 port 6
1119 15:07:50.582716 USB2 port 9
1120 15:07:50.582795 USB3 port 0
1121 15:07:50.586050 USB3 port 1
1122 15:07:50.586164 USB3 port 2
1123 15:07:50.589358 USB3 port 3
1124 15:07:50.589449 USB3 port 4
1125 15:07:50.592897 PCI: 00:14.2
1126 15:07:50.602780 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1127 15:07:50.613081 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1128 15:07:50.613174 PCI: 00:14.3
1129 15:07:50.622574 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1130 15:07:50.629235 PCI: 00:15.0 child on link 0 I2C: 01:15
1131 15:07:50.639032 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1132 15:07:50.639159 I2C: 01:15
1133 15:07:50.642314 PCI: 00:15.1 child on link 0 I2C: 02:5d
1134 15:07:50.652565 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1135 15:07:50.655723 I2C: 02:5d
1136 15:07:50.655818 GENERIC: 0.0
1137 15:07:50.659137 PCI: 00:16.0
1138 15:07:50.669050 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1139 15:07:50.669143 PCI: 00:17.0
1140 15:07:50.679255 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1141 15:07:50.688917 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1142 15:07:50.695384 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1143 15:07:50.705509 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1144 15:07:50.712311 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1145 15:07:50.722432 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1146 15:07:50.725620 PCI: 00:19.0 child on link 0 I2C: 03:1a
1147 15:07:50.735361 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1148 15:07:50.738615 I2C: 03:1a
1149 15:07:50.738707 I2C: 03:38
1150 15:07:50.741828 I2C: 03:39
1151 15:07:50.741919 I2C: 03:3a
1152 15:07:50.745474 I2C: 03:3b
1153 15:07:50.748583 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1154 15:07:50.758993 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1155 15:07:50.768760 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1156 15:07:50.775218 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1157 15:07:50.778516 PCI: 01:00.0
1158 15:07:50.788703 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1159 15:07:50.788796 PCI: 00:1e.0
1160 15:07:50.801788 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1161 15:07:50.811910 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1162 15:07:50.815295 PCI: 00:1e.2 child on link 0 SPI: 00
1163 15:07:50.825128 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1164 15:07:50.825218 SPI: 00
1165 15:07:50.831621 PCI: 00:1e.3 child on link 0 SPI: 01
1166 15:07:50.838049 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1167 15:07:50.841323 SPI: 01
1168 15:07:50.845562 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1169 15:07:50.855192 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1170 15:07:50.861850 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1171 15:07:50.865102 PNP: 0c09.0
1172 15:07:50.875226 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1173 15:07:50.875321 PCI: 00:1f.3
1174 15:07:50.885166 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1175 15:07:50.894981 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1176 15:07:50.898111 PCI: 00:1f.4
1177 15:07:50.905012 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1178 15:07:50.914612 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1179 15:07:50.917871 PCI: 00:1f.5
1180 15:07:50.927705 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1181 15:07:50.934361 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1182 15:07:50.937683 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1183 15:07:50.944537 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1184 15:07:50.951394 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1185 15:07:50.954574 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1186 15:07:50.957580 PCI: 00:17.0 18 * [0x60 - 0x67] io
1187 15:07:50.961355 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1188 15:07:50.967357 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1189 15:07:50.974069 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1190 15:07:50.981005 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1191 15:07:50.990675 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1192 15:07:50.997166 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1193 15:07:51.001020 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1194 15:07:51.007315 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1195 15:07:51.013925 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1196 15:07:51.017095 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1197 15:07:51.024117 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1198 15:07:51.027358 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1199 15:07:51.033810 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1200 15:07:51.037082 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1201 15:07:51.043641 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1202 15:07:51.047021 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1203 15:07:51.053852 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1204 15:07:51.056986 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1205 15:07:51.060635 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1206 15:07:51.066698 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1207 15:07:51.070175 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1208 15:07:51.076723 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1209 15:07:51.080101 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1210 15:07:51.087114 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1211 15:07:51.090359 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1212 15:07:51.096976 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1213 15:07:51.100314 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1214 15:07:51.106739 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1215 15:07:51.110148 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1216 15:07:51.116288 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1217 15:07:51.119891 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1218 15:07:51.129710 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1219 15:07:51.132955 avoid_fixed_resources: DOMAIN: 0000
1220 15:07:51.140177 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1221 15:07:51.143464 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1222 15:07:51.152683 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1223 15:07:51.159713 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1224 15:07:51.166051 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1225 15:07:51.175957 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1226 15:07:51.182516 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1227 15:07:51.189089 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1228 15:07:51.199259 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1229 15:07:51.206084 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1230 15:07:51.212784 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1231 15:07:51.219254 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1232 15:07:51.222624 Setting resources...
1233 15:07:51.229230 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1234 15:07:51.232478 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1235 15:07:51.236082 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1236 15:07:51.239223 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1237 15:07:51.245769 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1238 15:07:51.252366 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1239 15:07:51.255745 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1240 15:07:51.262245 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1241 15:07:51.272423 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1242 15:07:51.275530 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1243 15:07:51.281777 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1244 15:07:51.285306 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1245 15:07:51.291882 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1246 15:07:51.295687 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1247 15:07:51.298669 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1248 15:07:51.305390 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1249 15:07:51.308613 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1250 15:07:51.315058 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1251 15:07:51.318320 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1252 15:07:51.324899 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1253 15:07:51.328151 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1254 15:07:51.335215 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1255 15:07:51.338260 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1256 15:07:51.344801 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1257 15:07:51.348513 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1258 15:07:51.355058 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1259 15:07:51.358436 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1260 15:07:51.365022 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1261 15:07:51.368329 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1262 15:07:51.374694 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1263 15:07:51.377912 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1264 15:07:51.381178 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1265 15:07:51.391376 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1266 15:07:51.397749 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1267 15:07:51.404120 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1268 15:07:51.411357 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1269 15:07:51.417979 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1270 15:07:51.424167 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1271 15:07:51.428040 Root Device assign_resources, bus 0 link: 0
1272 15:07:51.434440 DOMAIN: 0000 assign_resources, bus 0 link: 0
1273 15:07:51.440968 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1274 15:07:51.450850 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1275 15:07:51.457479 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1276 15:07:51.467307 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1277 15:07:51.474233 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1278 15:07:51.484047 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1279 15:07:51.487319 PCI: 00:14.0 assign_resources, bus 0 link: 0
1280 15:07:51.494355 PCI: 00:14.0 assign_resources, bus 0 link: 0
1281 15:07:51.500391 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1282 15:07:51.507106 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1283 15:07:51.517507 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1284 15:07:51.524143 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1285 15:07:51.530701 PCI: 00:15.0 assign_resources, bus 1 link: 0
1286 15:07:51.534030 PCI: 00:15.0 assign_resources, bus 1 link: 0
1287 15:07:51.544391 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1288 15:07:51.547665 PCI: 00:15.1 assign_resources, bus 2 link: 0
1289 15:07:51.550828 PCI: 00:15.1 assign_resources, bus 2 link: 0
1290 15:07:51.560685 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1291 15:07:51.567676 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1292 15:07:51.577560 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1293 15:07:51.584190 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1294 15:07:51.591161 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1295 15:07:51.600827 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1296 15:07:51.607307 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1297 15:07:51.614204 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1298 15:07:51.621018 PCI: 00:19.0 assign_resources, bus 3 link: 0
1299 15:07:51.624202 PCI: 00:19.0 assign_resources, bus 3 link: 0
1300 15:07:51.634008 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1301 15:07:51.640952 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1302 15:07:51.651046 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1303 15:07:51.653813 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1304 15:07:51.663663 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1305 15:07:51.667524 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1306 15:07:51.677008 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1307 15:07:51.684015 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1308 15:07:51.690539 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1309 15:07:51.693838 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1310 15:07:51.703791 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1311 15:07:51.707094 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1312 15:07:51.710352 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1313 15:07:51.717308 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1314 15:07:51.720259 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1315 15:07:51.726858 LPC: Trying to open IO window from 800 size 1ff
1316 15:07:51.733422 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1317 15:07:51.743188 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1318 15:07:51.749946 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1319 15:07:51.759747 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1320 15:07:51.763513 DOMAIN: 0000 assign_resources, bus 0 link: 0
1321 15:07:51.769973 Root Device assign_resources, bus 0 link: 0
1322 15:07:51.770088 Done setting resources.
1323 15:07:51.776960 Show resources in subtree (Root Device)...After assigning values.
1324 15:07:51.783422 Root Device child on link 0 CPU_CLUSTER: 0
1325 15:07:51.786491 CPU_CLUSTER: 0 child on link 0 APIC: 00
1326 15:07:51.786581 APIC: 00
1327 15:07:51.789877 APIC: 02
1328 15:07:51.789967 APIC: 07
1329 15:07:51.790037 APIC: 01
1330 15:07:51.793144 APIC: 03
1331 15:07:51.793234 APIC: 06
1332 15:07:51.793304 APIC: 04
1333 15:07:51.796392 APIC: 05
1334 15:07:51.799690 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1335 15:07:51.810030 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1336 15:07:51.819889 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1337 15:07:51.822992 PCI: 00:00.0
1338 15:07:51.833256 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1339 15:07:51.842852 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1340 15:07:51.852746 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1341 15:07:51.859398 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1342 15:07:51.869047 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1343 15:07:51.879214 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1344 15:07:51.888966 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1345 15:07:51.899323 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1346 15:07:51.905432 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1347 15:07:51.915817 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1348 15:07:51.925918 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1349 15:07:51.935352 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1350 15:07:51.945435 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1351 15:07:51.955290 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1352 15:07:51.965362 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1353 15:07:51.971959 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1354 15:07:51.975207 PCI: 00:02.0
1355 15:07:51.984893 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1356 15:07:51.994993 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1357 15:07:52.004631 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1358 15:07:52.008007 PCI: 00:04.0
1359 15:07:52.008104 PCI: 00:08.0
1360 15:07:52.018036 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1361 15:07:52.021094 PCI: 00:12.0
1362 15:07:52.031020 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1363 15:07:52.034196 PCI: 00:14.0 child on link 0 USB0 port 0
1364 15:07:52.044585 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1365 15:07:52.050800 USB0 port 0 child on link 0 USB2 port 0
1366 15:07:52.050915 USB2 port 0
1367 15:07:52.054729 USB2 port 1
1368 15:07:52.054825 USB2 port 2
1369 15:07:52.057951 USB2 port 3
1370 15:07:52.058046 USB2 port 5
1371 15:07:52.061342 USB2 port 6
1372 15:07:52.061441 USB2 port 9
1373 15:07:52.064057 USB3 port 0
1374 15:07:52.064148 USB3 port 1
1375 15:07:52.067970 USB3 port 2
1376 15:07:52.068067 USB3 port 3
1377 15:07:52.071182 USB3 port 4
1378 15:07:52.071326 PCI: 00:14.2
1379 15:07:52.084075 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1380 15:07:52.094326 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1381 15:07:52.094440 PCI: 00:14.3
1382 15:07:52.103691 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1383 15:07:52.110996 PCI: 00:15.0 child on link 0 I2C: 01:15
1384 15:07:52.120712 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1385 15:07:52.120840 I2C: 01:15
1386 15:07:52.124066 PCI: 00:15.1 child on link 0 I2C: 02:5d
1387 15:07:52.137069 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1388 15:07:52.137171 I2C: 02:5d
1389 15:07:52.140229 GENERIC: 0.0
1390 15:07:52.140310 PCI: 00:16.0
1391 15:07:52.150400 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1392 15:07:52.153561 PCI: 00:17.0
1393 15:07:52.163806 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1394 15:07:52.173365 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1395 15:07:52.183241 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1396 15:07:52.189722 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1397 15:07:52.199573 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1398 15:07:52.209430 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1399 15:07:52.213415 PCI: 00:19.0 child on link 0 I2C: 03:1a
1400 15:07:52.226037 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1401 15:07:52.226158 I2C: 03:1a
1402 15:07:52.229413 I2C: 03:38
1403 15:07:52.229506 I2C: 03:39
1404 15:07:52.229578 I2C: 03:3a
1405 15:07:52.233266 I2C: 03:3b
1406 15:07:52.236749 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1407 15:07:52.246200 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1408 15:07:52.256076 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1409 15:07:52.265990 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1410 15:07:52.269282 PCI: 01:00.0
1411 15:07:52.279094 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1412 15:07:52.279252 PCI: 00:1e.0
1413 15:07:52.292299 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1414 15:07:52.302098 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1415 15:07:52.305365 PCI: 00:1e.2 child on link 0 SPI: 00
1416 15:07:52.315547 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1417 15:07:52.318961 SPI: 00
1418 15:07:52.322343 PCI: 00:1e.3 child on link 0 SPI: 01
1419 15:07:52.332477 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1420 15:07:52.332590 SPI: 01
1421 15:07:52.338855 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1422 15:07:52.345253 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1423 15:07:52.355438 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1424 15:07:52.355567 PNP: 0c09.0
1425 15:07:52.365388 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1426 15:07:52.368139 PCI: 00:1f.3
1427 15:07:52.378660 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1428 15:07:52.388395 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1429 15:07:52.388527 PCI: 00:1f.4
1430 15:07:52.398443 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1431 15:07:52.408644 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1432 15:07:52.411200 PCI: 00:1f.5
1433 15:07:52.421031 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1434 15:07:52.424966 Done allocating resources.
1435 15:07:52.427667 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1436 15:07:52.430900 Enabling resources...
1437 15:07:52.437648 PCI: 00:00.0 subsystem <- 8086/9b61
1438 15:07:52.437748 PCI: 00:00.0 cmd <- 06
1439 15:07:52.441012 PCI: 00:02.0 subsystem <- 8086/9b41
1440 15:07:52.444337 PCI: 00:02.0 cmd <- 03
1441 15:07:52.448071 PCI: 00:08.0 cmd <- 06
1442 15:07:52.451199 PCI: 00:12.0 subsystem <- 8086/02f9
1443 15:07:52.454314 PCI: 00:12.0 cmd <- 02
1444 15:07:52.457516 PCI: 00:14.0 subsystem <- 8086/02ed
1445 15:07:52.461325 PCI: 00:14.0 cmd <- 02
1446 15:07:52.461419 PCI: 00:14.2 cmd <- 02
1447 15:07:52.467847 PCI: 00:14.3 subsystem <- 8086/02f0
1448 15:07:52.467941 PCI: 00:14.3 cmd <- 02
1449 15:07:52.471063 PCI: 00:15.0 subsystem <- 8086/02e8
1450 15:07:52.475004 PCI: 00:15.0 cmd <- 02
1451 15:07:52.478145 PCI: 00:15.1 subsystem <- 8086/02e9
1452 15:07:52.481314 PCI: 00:15.1 cmd <- 02
1453 15:07:52.484522 PCI: 00:16.0 subsystem <- 8086/02e0
1454 15:07:52.487699 PCI: 00:16.0 cmd <- 02
1455 15:07:52.491115 PCI: 00:17.0 subsystem <- 8086/02d3
1456 15:07:52.494847 PCI: 00:17.0 cmd <- 03
1457 15:07:52.497991 PCI: 00:19.0 subsystem <- 8086/02c5
1458 15:07:52.501422 PCI: 00:19.0 cmd <- 02
1459 15:07:52.504714 PCI: 00:1d.0 bridge ctrl <- 0013
1460 15:07:52.507884 PCI: 00:1d.0 subsystem <- 8086/02b0
1461 15:07:52.511085 PCI: 00:1d.0 cmd <- 06
1462 15:07:52.514370 PCI: 00:1e.0 subsystem <- 8086/02a8
1463 15:07:52.517557 PCI: 00:1e.0 cmd <- 06
1464 15:07:52.521265 PCI: 00:1e.2 subsystem <- 8086/02aa
1465 15:07:52.521389 PCI: 00:1e.2 cmd <- 06
1466 15:07:52.527429 PCI: 00:1e.3 subsystem <- 8086/02ab
1467 15:07:52.527534 PCI: 00:1e.3 cmd <- 02
1468 15:07:52.531338 PCI: 00:1f.0 subsystem <- 8086/0284
1469 15:07:52.534541 PCI: 00:1f.0 cmd <- 407
1470 15:07:52.537777 PCI: 00:1f.3 subsystem <- 8086/02c8
1471 15:07:52.541127 PCI: 00:1f.3 cmd <- 02
1472 15:07:52.544346 PCI: 00:1f.4 subsystem <- 8086/02a3
1473 15:07:52.547778 PCI: 00:1f.4 cmd <- 03
1474 15:07:52.551058 PCI: 00:1f.5 subsystem <- 8086/02a4
1475 15:07:52.554378 PCI: 00:1f.5 cmd <- 406
1476 15:07:52.562985 PCI: 01:00.0 cmd <- 02
1477 15:07:52.567819 done.
1478 15:07:52.582087 ME: Version: 14.0.39.1367
1479 15:07:52.588486 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 13
1480 15:07:52.591644 Initializing devices...
1481 15:07:52.591735 Root Device init ...
1482 15:07:52.598203 Chrome EC: Set SMI mask to 0x0000000000000000
1483 15:07:52.601350 Chrome EC: clear events_b mask to 0x0000000000000000
1484 15:07:52.608665 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1485 15:07:52.615108 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1486 15:07:52.621751 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1487 15:07:52.624933 Chrome EC: Set WAKE mask to 0x0000000000000000
1488 15:07:52.628053 Root Device init finished in 35206 usecs
1489 15:07:52.632029 CPU_CLUSTER: 0 init ...
1490 15:07:52.638400 CPU_CLUSTER: 0 init finished in 2449 usecs
1491 15:07:52.642362 PCI: 00:00.0 init ...
1492 15:07:52.645575 CPU TDP: 15 Watts
1493 15:07:52.649364 CPU PL2 = 64 Watts
1494 15:07:52.652694 PCI: 00:00.0 init finished in 7076 usecs
1495 15:07:52.655892 PCI: 00:02.0 init ...
1496 15:07:52.659010 PCI: 00:02.0 init finished in 2254 usecs
1497 15:07:52.662587 PCI: 00:08.0 init ...
1498 15:07:52.665729 PCI: 00:08.0 init finished in 2253 usecs
1499 15:07:52.668903 PCI: 00:12.0 init ...
1500 15:07:52.672595 PCI: 00:12.0 init finished in 2253 usecs
1501 15:07:52.675673 PCI: 00:14.0 init ...
1502 15:07:52.678982 PCI: 00:14.0 init finished in 2252 usecs
1503 15:07:52.682382 PCI: 00:14.2 init ...
1504 15:07:52.685706 PCI: 00:14.2 init finished in 2252 usecs
1505 15:07:52.689084 PCI: 00:14.3 init ...
1506 15:07:52.692248 PCI: 00:14.3 init finished in 2271 usecs
1507 15:07:52.696065 PCI: 00:15.0 init ...
1508 15:07:52.698756 DW I2C bus 0 at 0xd121f000 (400 KHz)
1509 15:07:52.702575 PCI: 00:15.0 init finished in 5978 usecs
1510 15:07:52.705559 PCI: 00:15.1 init ...
1511 15:07:52.709018 DW I2C bus 1 at 0xd1220000 (400 KHz)
1512 15:07:52.712351 PCI: 00:15.1 init finished in 5979 usecs
1513 15:07:52.715666 PCI: 00:16.0 init ...
1514 15:07:52.719079 PCI: 00:16.0 init finished in 2251 usecs
1515 15:07:52.723008 PCI: 00:19.0 init ...
1516 15:07:52.726237 DW I2C bus 4 at 0xd1222000 (400 KHz)
1517 15:07:52.732607 PCI: 00:19.0 init finished in 5977 usecs
1518 15:07:52.732719 PCI: 00:1d.0 init ...
1519 15:07:52.736075 Initializing PCH PCIe bridge.
1520 15:07:52.739308 PCI: 00:1d.0 init finished in 5287 usecs
1521 15:07:52.744324 PCI: 00:1f.0 init ...
1522 15:07:52.747462 IOAPIC: Initializing IOAPIC at 0xfec00000
1523 15:07:52.754054 IOAPIC: Bootstrap Processor Local APIC = 0x00
1524 15:07:52.754185 IOAPIC: ID = 0x02
1525 15:07:52.757344 IOAPIC: Dumping registers
1526 15:07:52.760706 reg 0x0000: 0x02000000
1527 15:07:52.764471 reg 0x0001: 0x00770020
1528 15:07:52.764596 reg 0x0002: 0x00000000
1529 15:07:52.771090 PCI: 00:1f.0 init finished in 23548 usecs
1530 15:07:52.774532 PCI: 00:1f.4 init ...
1531 15:07:52.777703 PCI: 00:1f.4 init finished in 2262 usecs
1532 15:07:52.788586 PCI: 01:00.0 init ...
1533 15:07:52.791875 PCI: 01:00.0 init finished in 2254 usecs
1534 15:07:52.796342 PNP: 0c09.0 init ...
1535 15:07:52.799584 Google Chrome EC uptime: 11.047 seconds
1536 15:07:52.805845 Google Chrome AP resets since EC boot: 0
1537 15:07:52.809693 Google Chrome most recent AP reset causes:
1538 15:07:52.816248 Google Chrome EC reset flags at last EC boot: reset-pin
1539 15:07:52.819458 PNP: 0c09.0 init finished in 20577 usecs
1540 15:07:52.822811 Devices initialized
1541 15:07:52.822921 Show all devs... After init.
1542 15:07:52.825946 Root Device: enabled 1
1543 15:07:52.829244 CPU_CLUSTER: 0: enabled 1
1544 15:07:52.832592 DOMAIN: 0000: enabled 1
1545 15:07:52.832704 APIC: 00: enabled 1
1546 15:07:52.835670 PCI: 00:00.0: enabled 1
1547 15:07:52.839104 PCI: 00:02.0: enabled 1
1548 15:07:52.842466 PCI: 00:04.0: enabled 0
1549 15:07:52.842590 PCI: 00:05.0: enabled 0
1550 15:07:52.845650 PCI: 00:12.0: enabled 1
1551 15:07:52.848919 PCI: 00:12.5: enabled 0
1552 15:07:52.852092 PCI: 00:12.6: enabled 0
1553 15:07:52.852179 PCI: 00:14.0: enabled 1
1554 15:07:52.855765 PCI: 00:14.1: enabled 0
1555 15:07:52.859007 PCI: 00:14.3: enabled 1
1556 15:07:52.859115 PCI: 00:14.5: enabled 0
1557 15:07:52.862161 PCI: 00:15.0: enabled 1
1558 15:07:52.865371 PCI: 00:15.1: enabled 1
1559 15:07:52.869264 PCI: 00:15.2: enabled 0
1560 15:07:52.869384 PCI: 00:15.3: enabled 0
1561 15:07:52.872444 PCI: 00:16.0: enabled 1
1562 15:07:52.875816 PCI: 00:16.1: enabled 0
1563 15:07:52.879092 PCI: 00:16.2: enabled 0
1564 15:07:52.879211 PCI: 00:16.3: enabled 0
1565 15:07:52.882339 PCI: 00:16.4: enabled 0
1566 15:07:52.885553 PCI: 00:16.5: enabled 0
1567 15:07:52.888609 PCI: 00:17.0: enabled 1
1568 15:07:52.888693 PCI: 00:19.0: enabled 1
1569 15:07:52.892384 PCI: 00:19.1: enabled 0
1570 15:07:52.895688 PCI: 00:19.2: enabled 0
1571 15:07:52.895800 PCI: 00:1a.0: enabled 0
1572 15:07:52.898934 PCI: 00:1c.0: enabled 0
1573 15:07:52.902217 PCI: 00:1c.1: enabled 0
1574 15:07:52.905375 PCI: 00:1c.2: enabled 0
1575 15:07:52.905484 PCI: 00:1c.3: enabled 0
1576 15:07:52.908616 PCI: 00:1c.4: enabled 0
1577 15:07:52.911666 PCI: 00:1c.5: enabled 0
1578 15:07:52.914993 PCI: 00:1c.6: enabled 0
1579 15:07:52.915101 PCI: 00:1c.7: enabled 0
1580 15:07:52.918784 PCI: 00:1d.0: enabled 1
1581 15:07:52.922092 PCI: 00:1d.1: enabled 0
1582 15:07:52.925272 PCI: 00:1d.2: enabled 0
1583 15:07:52.925385 PCI: 00:1d.3: enabled 0
1584 15:07:52.928598 PCI: 00:1d.4: enabled 0
1585 15:07:52.931934 PCI: 00:1d.5: enabled 0
1586 15:07:52.935170 PCI: 00:1e.0: enabled 1
1587 15:07:52.935276 PCI: 00:1e.1: enabled 0
1588 15:07:52.938308 PCI: 00:1e.2: enabled 1
1589 15:07:52.941454 PCI: 00:1e.3: enabled 1
1590 15:07:52.941562 PCI: 00:1f.0: enabled 1
1591 15:07:52.944835 PCI: 00:1f.1: enabled 0
1592 15:07:52.948138 PCI: 00:1f.2: enabled 0
1593 15:07:52.951512 PCI: 00:1f.3: enabled 1
1594 15:07:52.951639 PCI: 00:1f.4: enabled 1
1595 15:07:52.954827 PCI: 00:1f.5: enabled 1
1596 15:07:52.958577 PCI: 00:1f.6: enabled 0
1597 15:07:52.961776 USB0 port 0: enabled 1
1598 15:07:52.961870 I2C: 01:15: enabled 1
1599 15:07:52.965114 I2C: 02:5d: enabled 1
1600 15:07:52.968411 GENERIC: 0.0: enabled 1
1601 15:07:52.968506 I2C: 03:1a: enabled 1
1602 15:07:52.971723 I2C: 03:38: enabled 1
1603 15:07:52.974993 I2C: 03:39: enabled 1
1604 15:07:52.975084 I2C: 03:3a: enabled 1
1605 15:07:52.978181 I2C: 03:3b: enabled 1
1606 15:07:52.981538 PCI: 00:00.0: enabled 1
1607 15:07:52.981630 SPI: 00: enabled 1
1608 15:07:52.984989 SPI: 01: enabled 1
1609 15:07:52.988293 PNP: 0c09.0: enabled 1
1610 15:07:52.988386 USB2 port 0: enabled 1
1611 15:07:52.991713 USB2 port 1: enabled 1
1612 15:07:52.994884 USB2 port 2: enabled 0
1613 15:07:52.994976 USB2 port 3: enabled 0
1614 15:07:52.997994 USB2 port 5: enabled 0
1615 15:07:53.001253 USB2 port 6: enabled 1
1616 15:07:53.004643 USB2 port 9: enabled 1
1617 15:07:53.004734 USB3 port 0: enabled 1
1618 15:07:53.007979 USB3 port 1: enabled 1
1619 15:07:53.011178 USB3 port 2: enabled 1
1620 15:07:53.011270 USB3 port 3: enabled 1
1621 15:07:53.015010 USB3 port 4: enabled 0
1622 15:07:53.018093 APIC: 02: enabled 1
1623 15:07:53.018186 APIC: 07: enabled 1
1624 15:07:53.021411 APIC: 01: enabled 1
1625 15:07:53.024753 APIC: 03: enabled 1
1626 15:07:53.024845 APIC: 06: enabled 1
1627 15:07:53.027953 APIC: 04: enabled 1
1628 15:07:53.028045 APIC: 05: enabled 1
1629 15:07:53.031393 PCI: 00:08.0: enabled 1
1630 15:07:53.034669 PCI: 00:14.2: enabled 1
1631 15:07:53.037955 PCI: 01:00.0: enabled 1
1632 15:07:53.041107 Disabling ACPI via APMC:
1633 15:07:53.041198 done.
1634 15:07:53.048206 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1635 15:07:53.051409 ELOG: NV offset 0xaf0000 size 0x4000
1636 15:07:53.058015 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1637 15:07:53.064670 ELOG: Event(17) added with size 13 at 2023-06-09 15:07:49 UTC
1638 15:07:53.071382 ELOG: Event(92) added with size 9 at 2023-06-09 15:07:49 UTC
1639 15:07:53.078474 ELOG: Event(93) added with size 9 at 2023-06-09 15:07:49 UTC
1640 15:07:53.084720 ELOG: Event(9A) added with size 9 at 2023-06-09 15:07:49 UTC
1641 15:07:53.091341 ELOG: Event(9E) added with size 10 at 2023-06-09 15:07:49 UTC
1642 15:07:53.097996 ELOG: Event(9F) added with size 14 at 2023-06-09 15:07:49 UTC
1643 15:07:53.101205 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1644 15:07:53.108211 ELOG: Event(A1) added with size 10 at 2023-06-09 15:07:49 UTC
1645 15:07:53.117920 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1646 15:07:53.124926 ELOG: Event(A0) added with size 9 at 2023-06-09 15:07:49 UTC
1647 15:07:53.128141 elog_add_boot_reason: Logged dev mode boot
1648 15:07:53.128239 Finalize devices...
1649 15:07:53.131344 PCI: 00:17.0 final
1650 15:07:53.134707 Devices finalized
1651 15:07:53.138053 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1652 15:07:53.144800 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1653 15:07:53.147948 ME: HFSTS1 : 0x90000245
1654 15:07:53.151212 ME: HFSTS2 : 0x3B850126
1655 15:07:53.158234 ME: HFSTS3 : 0x00000020
1656 15:07:53.161480 ME: HFSTS4 : 0x00004800
1657 15:07:53.164795 ME: HFSTS5 : 0x00000000
1658 15:07:53.167603 ME: HFSTS6 : 0x40400006
1659 15:07:53.170927 ME: Manufacturing Mode : NO
1660 15:07:53.174679 ME: FW Partition Table : OK
1661 15:07:53.177884 ME: Bringup Loader Failure : NO
1662 15:07:53.181304 ME: Firmware Init Complete : YES
1663 15:07:53.184625 ME: Boot Options Present : NO
1664 15:07:53.187770 ME: Update In Progress : NO
1665 15:07:53.191056 ME: D0i3 Support : YES
1666 15:07:53.194367 ME: Low Power State Enabled : NO
1667 15:07:53.197760 ME: CPU Replaced : NO
1668 15:07:53.200967 ME: CPU Replacement Valid : YES
1669 15:07:53.204024 ME: Current Working State : 5
1670 15:07:53.207303 ME: Current Operation State : 1
1671 15:07:53.210717 ME: Current Operation Mode : 0
1672 15:07:53.214071 ME: Error Code : 0
1673 15:07:53.217282 ME: CPU Debug Disabled : YES
1674 15:07:53.220613 ME: TXT Support : NO
1675 15:07:53.227529 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1676 15:07:53.233907 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1677 15:07:53.234008 CBFS @ c08000 size 3f8000
1678 15:07:53.240588 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1679 15:07:53.243964 CBFS: Locating 'fallback/dsdt.aml'
1680 15:07:53.247161 CBFS: Found @ offset 10bb80 size 3fa5
1681 15:07:53.253801 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1682 15:07:53.257428 CBFS @ c08000 size 3f8000
1683 15:07:53.260673 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1684 15:07:53.263978 CBFS: Locating 'fallback/slic'
1685 15:07:53.268592 CBFS: 'fallback/slic' not found.
1686 15:07:53.275246 ACPI: Writing ACPI tables at 99b3e000.
1687 15:07:53.275372 ACPI: * FACS
1688 15:07:53.279061 ACPI: * DSDT
1689 15:07:53.282269 Ramoops buffer: 0x100000@0x99a3d000.
1690 15:07:53.285618 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1691 15:07:53.292060 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1692 15:07:53.295286 Google Chrome EC: version:
1693 15:07:53.298577 ro: helios_v2.0.2659-56403530b
1694 15:07:53.302025 rw: helios_v2.0.2849-c41de27e7d
1695 15:07:53.302119 running image: 1
1696 15:07:53.305961 ACPI: * FADT
1697 15:07:53.306054 SCI is IRQ9
1698 15:07:53.312910 ACPI: added table 1/32, length now 40
1699 15:07:53.313007 ACPI: * SSDT
1700 15:07:53.316006 Found 1 CPU(s) with 8 core(s) each.
1701 15:07:53.319206 Error: Could not locate 'wifi_sar' in VPD.
1702 15:07:53.325776 Checking CBFS for default SAR values
1703 15:07:53.329583 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1704 15:07:53.332670 CBFS @ c08000 size 3f8000
1705 15:07:53.338997 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1706 15:07:53.342931 CBFS: Locating 'wifi_sar_defaults.hex'
1707 15:07:53.346205 CBFS: Found @ offset 5fac0 size 77
1708 15:07:53.349372 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1709 15:07:53.356123 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1710 15:07:53.359211 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1711 15:07:53.365652 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1712 15:07:53.369089 failed to find key in VPD: dsm_calib_r0_0
1713 15:07:53.378642 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1714 15:07:53.382654 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1715 15:07:53.385803 failed to find key in VPD: dsm_calib_r0_1
1716 15:07:53.395359 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1717 15:07:53.402441 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1718 15:07:53.405676 failed to find key in VPD: dsm_calib_r0_2
1719 15:07:53.415282 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1720 15:07:53.418582 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1721 15:07:53.425151 failed to find key in VPD: dsm_calib_r0_3
1722 15:07:53.431576 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1723 15:07:53.438307 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1724 15:07:53.441685 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1725 15:07:53.444959 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1726 15:07:53.448938 EC returned error result code 1
1727 15:07:53.452931 EC returned error result code 1
1728 15:07:53.456878 EC returned error result code 1
1729 15:07:53.463370 PS2K: Bad resp from EC. Vivaldi disabled!
1730 15:07:53.466619 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1731 15:07:53.473123 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1732 15:07:53.480155 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1733 15:07:53.483418 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1734 15:07:53.489535 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1735 15:07:53.496539 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1736 15:07:53.502964 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1737 15:07:53.506222 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1738 15:07:53.512874 ACPI: added table 2/32, length now 44
1739 15:07:53.512970 ACPI: * MCFG
1740 15:07:53.515993 ACPI: added table 3/32, length now 48
1741 15:07:53.519801 ACPI: * TPM2
1742 15:07:53.523079 TPM2 log created at 99a2d000
1743 15:07:53.526242 ACPI: added table 4/32, length now 52
1744 15:07:53.526361 ACPI: * MADT
1745 15:07:53.529563 SCI is IRQ9
1746 15:07:53.532611 ACPI: added table 5/32, length now 56
1747 15:07:53.532705 current = 99b43ac0
1748 15:07:53.536330 ACPI: * DMAR
1749 15:07:53.539581 ACPI: added table 6/32, length now 60
1750 15:07:53.542811 ACPI: * IGD OpRegion
1751 15:07:53.542928 GMA: Found VBT in CBFS
1752 15:07:53.546024 GMA: Found valid VBT in CBFS
1753 15:07:53.549148 ACPI: added table 7/32, length now 64
1754 15:07:53.552804 ACPI: * HPET
1755 15:07:53.555938 ACPI: added table 8/32, length now 68
1756 15:07:53.556027 ACPI: done.
1757 15:07:53.559887 ACPI tables: 31744 bytes.
1758 15:07:53.562960 smbios_write_tables: 99a2c000
1759 15:07:53.566332 EC returned error result code 3
1760 15:07:53.569613 Couldn't obtain OEM name from CBI
1761 15:07:53.572747 Create SMBIOS type 17
1762 15:07:53.576026 PCI: 00:00.0 (Intel Cannonlake)
1763 15:07:53.579459 PCI: 00:14.3 (Intel WiFi)
1764 15:07:53.582752 SMBIOS tables: 939 bytes.
1765 15:07:53.585961 Writing table forward entry at 0x00000500
1766 15:07:53.592462 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1767 15:07:53.596002 Writing coreboot table at 0x99b62000
1768 15:07:53.602671 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1769 15:07:53.605838 1. 0000000000001000-000000000009ffff: RAM
1770 15:07:53.609056 2. 00000000000a0000-00000000000fffff: RESERVED
1771 15:07:53.615749 3. 0000000000100000-0000000099a2bfff: RAM
1772 15:07:53.622212 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1773 15:07:53.625562 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1774 15:07:53.632134 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1775 15:07:53.635329 7. 000000009a000000-000000009f7fffff: RESERVED
1776 15:07:53.642073 8. 00000000e0000000-00000000efffffff: RESERVED
1777 15:07:53.645358 9. 00000000fc000000-00000000fc000fff: RESERVED
1778 15:07:53.652017 10. 00000000fe000000-00000000fe00ffff: RESERVED
1779 15:07:53.655207 11. 00000000fed10000-00000000fed17fff: RESERVED
1780 15:07:53.658969 12. 00000000fed80000-00000000fed83fff: RESERVED
1781 15:07:53.664976 13. 00000000fed90000-00000000fed91fff: RESERVED
1782 15:07:53.668509 14. 00000000feda0000-00000000feda1fff: RESERVED
1783 15:07:53.674897 15. 0000000100000000-000000045e7fffff: RAM
1784 15:07:53.678689 Graphics framebuffer located at 0xc0000000
1785 15:07:53.682026 Passing 5 GPIOs to payload:
1786 15:07:53.685315 NAME | PORT | POLARITY | VALUE
1787 15:07:53.691950 write protect | undefined | high | low
1788 15:07:53.698306 lid | undefined | high | high
1789 15:07:53.701439 power | undefined | high | low
1790 15:07:53.708583 oprom | undefined | high | low
1791 15:07:53.711227 EC in RW | 0x000000cb | high | low
1792 15:07:53.714519 Board ID: 4
1793 15:07:53.717860 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1794 15:07:53.721753 CBFS @ c08000 size 3f8000
1795 15:07:53.728032 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1796 15:07:53.734675 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6264
1797 15:07:53.734778 coreboot table: 1492 bytes.
1798 15:07:53.738014 IMD ROOT 0. 99fff000 00001000
1799 15:07:53.741237 IMD SMALL 1. 99ffe000 00001000
1800 15:07:53.744502 FSP MEMORY 2. 99c4e000 003b0000
1801 15:07:53.747675 CONSOLE 3. 99c2e000 00020000
1802 15:07:53.751423 FMAP 4. 99c2d000 0000054e
1803 15:07:53.754784 TIME STAMP 5. 99c2c000 00000910
1804 15:07:53.758011 VBOOT WORK 6. 99c18000 00014000
1805 15:07:53.761250 MRC DATA 7. 99c16000 00001958
1806 15:07:53.764438 ROMSTG STCK 8. 99c15000 00001000
1807 15:07:53.767641 AFTER CAR 9. 99c0b000 0000a000
1808 15:07:53.771167 RAMSTAGE 10. 99baf000 0005c000
1809 15:07:53.774222 REFCODE 11. 99b7a000 00035000
1810 15:07:53.777672 SMM BACKUP 12. 99b6a000 00010000
1811 15:07:53.780890 COREBOOT 13. 99b62000 00008000
1812 15:07:53.784607 ACPI 14. 99b3e000 00024000
1813 15:07:53.787886 ACPI GNVS 15. 99b3d000 00001000
1814 15:07:53.794337 RAMOOPS 16. 99a3d000 00100000
1815 15:07:53.797617 TPM2 TCGLOG17. 99a2d000 00010000
1816 15:07:53.800898 SMBIOS 18. 99a2c000 00000800
1817 15:07:53.800986 IMD small region:
1818 15:07:53.804557 IMD ROOT 0. 99ffec00 00000400
1819 15:07:53.807851 FSP RUNTIME 1. 99ffebe0 00000004
1820 15:07:53.811197 EC HOSTEVENT 2. 99ffebc0 00000008
1821 15:07:53.814348 POWER STATE 3. 99ffeb80 00000040
1822 15:07:53.817677 ROMSTAGE 4. 99ffeb60 00000004
1823 15:07:53.820912 MEM INFO 5. 99ffe9a0 000001b9
1824 15:07:53.827489 VPD 6. 99ffe920 0000006c
1825 15:07:53.827579 MTRR: Physical address space:
1826 15:07:53.834466 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1827 15:07:53.841032 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1828 15:07:53.847639 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1829 15:07:53.854220 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1830 15:07:53.860686 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1831 15:07:53.867305 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1832 15:07:53.873665 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1833 15:07:53.876921 MTRR: Fixed MSR 0x250 0x0606060606060606
1834 15:07:53.880762 MTRR: Fixed MSR 0x258 0x0606060606060606
1835 15:07:53.883909 MTRR: Fixed MSR 0x259 0x0000000000000000
1836 15:07:53.890670 MTRR: Fixed MSR 0x268 0x0606060606060606
1837 15:07:53.893725 MTRR: Fixed MSR 0x269 0x0606060606060606
1838 15:07:53.896941 MTRR: Fixed MSR 0x26a 0x0606060606060606
1839 15:07:53.900302 MTRR: Fixed MSR 0x26b 0x0606060606060606
1840 15:07:53.907174 MTRR: Fixed MSR 0x26c 0x0606060606060606
1841 15:07:53.910290 MTRR: Fixed MSR 0x26d 0x0606060606060606
1842 15:07:53.913652 MTRR: Fixed MSR 0x26e 0x0606060606060606
1843 15:07:53.916811 MTRR: Fixed MSR 0x26f 0x0606060606060606
1844 15:07:53.920000 call enable_fixed_mtrr()
1845 15:07:53.923342 CPU physical address size: 39 bits
1846 15:07:53.929914 MTRR: default type WB/UC MTRR counts: 6/8.
1847 15:07:53.933180 MTRR: WB selected as default type.
1848 15:07:53.939627 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1849 15:07:53.943017 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1850 15:07:53.949500 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1851 15:07:53.956184 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1852 15:07:53.962905 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1853 15:07:53.969462 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1854 15:07:53.976534 MTRR: Fixed MSR 0x250 0x0606060606060606
1855 15:07:53.979708 MTRR: Fixed MSR 0x258 0x0606060606060606
1856 15:07:53.982962 MTRR: Fixed MSR 0x259 0x0000000000000000
1857 15:07:53.986221 MTRR: Fixed MSR 0x268 0x0606060606060606
1858 15:07:53.992536 MTRR: Fixed MSR 0x269 0x0606060606060606
1859 15:07:53.995885 MTRR: Fixed MSR 0x26a 0x0606060606060606
1860 15:07:53.998829 MTRR: Fixed MSR 0x26b 0x0606060606060606
1861 15:07:54.002494 MTRR: Fixed MSR 0x26c 0x0606060606060606
1862 15:07:54.005600 MTRR: Fixed MSR 0x26d 0x0606060606060606
1863 15:07:54.012684 MTRR: Fixed MSR 0x26e 0x0606060606060606
1864 15:07:54.015773 MTRR: Fixed MSR 0x26f 0x0606060606060606
1865 15:07:54.015874
1866 15:07:54.015947 MTRR check
1867 15:07:54.018840 call enable_fixed_mtrr()
1868 15:07:54.022176 Fixed MTRRs : Enabled
1869 15:07:54.025405 Variable MTRRs: Enabled
1870 15:07:54.025504
1871 15:07:54.028697 CPU physical address size: 39 bits
1872 15:07:54.035268 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1873 15:07:54.038848 MTRR: Fixed MSR 0x250 0x0606060606060606
1874 15:07:54.042085 MTRR: Fixed MSR 0x258 0x0606060606060606
1875 15:07:54.045240 MTRR: Fixed MSR 0x259 0x0000000000000000
1876 15:07:54.048565 MTRR: Fixed MSR 0x268 0x0606060606060606
1877 15:07:54.054987 MTRR: Fixed MSR 0x269 0x0606060606060606
1878 15:07:54.058878 MTRR: Fixed MSR 0x26a 0x0606060606060606
1879 15:07:54.062252 MTRR: Fixed MSR 0x26b 0x0606060606060606
1880 15:07:54.065636 MTRR: Fixed MSR 0x26c 0x0606060606060606
1881 15:07:54.071917 MTRR: Fixed MSR 0x26d 0x0606060606060606
1882 15:07:54.075230 MTRR: Fixed MSR 0x26e 0x0606060606060606
1883 15:07:54.078524 MTRR: Fixed MSR 0x26f 0x0606060606060606
1884 15:07:54.081588 MTRR: Fixed MSR 0x250 0x0606060606060606
1885 15:07:54.085308 call enable_fixed_mtrr()
1886 15:07:54.088603 MTRR: Fixed MSR 0x258 0x0606060606060606
1887 15:07:54.095166 MTRR: Fixed MSR 0x259 0x0000000000000000
1888 15:07:54.098331 MTRR: Fixed MSR 0x268 0x0606060606060606
1889 15:07:54.101596 MTRR: Fixed MSR 0x269 0x0606060606060606
1890 15:07:54.104689 MTRR: Fixed MSR 0x26a 0x0606060606060606
1891 15:07:54.111435 MTRR: Fixed MSR 0x26b 0x0606060606060606
1892 15:07:54.114565 MTRR: Fixed MSR 0x26c 0x0606060606060606
1893 15:07:54.118299 MTRR: Fixed MSR 0x26d 0x0606060606060606
1894 15:07:54.121338 MTRR: Fixed MSR 0x26e 0x0606060606060606
1895 15:07:54.127958 MTRR: Fixed MSR 0x26f 0x0606060606060606
1896 15:07:54.131278 CPU physical address size: 39 bits
1897 15:07:54.134548 call enable_fixed_mtrr()
1898 15:07:54.137824 MTRR: Fixed MSR 0x250 0x0606060606060606
1899 15:07:54.141515 MTRR: Fixed MSR 0x250 0x0606060606060606
1900 15:07:54.144689 MTRR: Fixed MSR 0x258 0x0606060606060606
1901 15:07:54.151190 MTRR: Fixed MSR 0x259 0x0000000000000000
1902 15:07:54.154383 MTRR: Fixed MSR 0x268 0x0606060606060606
1903 15:07:54.157696 MTRR: Fixed MSR 0x269 0x0606060606060606
1904 15:07:54.160945 MTRR: Fixed MSR 0x26a 0x0606060606060606
1905 15:07:54.167707 MTRR: Fixed MSR 0x26b 0x0606060606060606
1906 15:07:54.170844 MTRR: Fixed MSR 0x26c 0x0606060606060606
1907 15:07:54.174184 MTRR: Fixed MSR 0x26d 0x0606060606060606
1908 15:07:54.177332 MTRR: Fixed MSR 0x26e 0x0606060606060606
1909 15:07:54.180681 MTRR: Fixed MSR 0x26f 0x0606060606060606
1910 15:07:54.187658 MTRR: Fixed MSR 0x258 0x0606060606060606
1911 15:07:54.190964 call enable_fixed_mtrr()
1912 15:07:54.194254 MTRR: Fixed MSR 0x259 0x0000000000000000
1913 15:07:54.197515 MTRR: Fixed MSR 0x268 0x0606060606060606
1914 15:07:54.200656 MTRR: Fixed MSR 0x269 0x0606060606060606
1915 15:07:54.207626 MTRR: Fixed MSR 0x26a 0x0606060606060606
1916 15:07:54.210716 MTRR: Fixed MSR 0x26b 0x0606060606060606
1917 15:07:54.213912 MTRR: Fixed MSR 0x26c 0x0606060606060606
1918 15:07:54.216937 MTRR: Fixed MSR 0x26d 0x0606060606060606
1919 15:07:54.220886 MTRR: Fixed MSR 0x26e 0x0606060606060606
1920 15:07:54.226917 MTRR: Fixed MSR 0x26f 0x0606060606060606
1921 15:07:54.230540 CPU physical address size: 39 bits
1922 15:07:54.233607 call enable_fixed_mtrr()
1923 15:07:54.237341 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1924 15:07:54.240658 CPU physical address size: 39 bits
1925 15:07:54.243709 CPU physical address size: 39 bits
1926 15:07:54.250259 MTRR: Fixed MSR 0x250 0x0606060606060606
1927 15:07:54.253681 MTRR: Fixed MSR 0x250 0x0606060606060606
1928 15:07:54.256854 MTRR: Fixed MSR 0x258 0x0606060606060606
1929 15:07:54.260176 MTRR: Fixed MSR 0x259 0x0000000000000000
1930 15:07:54.266769 MTRR: Fixed MSR 0x268 0x0606060606060606
1931 15:07:54.270004 MTRR: Fixed MSR 0x269 0x0606060606060606
1932 15:07:54.273320 MTRR: Fixed MSR 0x26a 0x0606060606060606
1933 15:07:54.276663 MTRR: Fixed MSR 0x26b 0x0606060606060606
1934 15:07:54.279895 MTRR: Fixed MSR 0x26c 0x0606060606060606
1935 15:07:54.286297 MTRR: Fixed MSR 0x26d 0x0606060606060606
1936 15:07:54.289648 MTRR: Fixed MSR 0x26e 0x0606060606060606
1937 15:07:54.293411 MTRR: Fixed MSR 0x26f 0x0606060606060606
1938 15:07:54.299773 MTRR: Fixed MSR 0x258 0x0606060606060606
1939 15:07:54.299870 CBFS @ c08000 size 3f8000
1940 15:07:54.306338 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1941 15:07:54.309983 CBFS: Locating 'fallback/payload'
1942 15:07:54.313129 MTRR: Fixed MSR 0x259 0x0000000000000000
1943 15:07:54.319393 MTRR: Fixed MSR 0x268 0x0606060606060606
1944 15:07:54.322958 MTRR: Fixed MSR 0x269 0x0606060606060606
1945 15:07:54.326145 MTRR: Fixed MSR 0x26a 0x0606060606060606
1946 15:07:54.329448 MTRR: Fixed MSR 0x26b 0x0606060606060606
1947 15:07:54.335877 MTRR: Fixed MSR 0x26c 0x0606060606060606
1948 15:07:54.339517 MTRR: Fixed MSR 0x26d 0x0606060606060606
1949 15:07:54.342624 MTRR: Fixed MSR 0x26e 0x0606060606060606
1950 15:07:54.345818 MTRR: Fixed MSR 0x26f 0x0606060606060606
1951 15:07:54.349665 call enable_fixed_mtrr()
1952 15:07:54.352621 call enable_fixed_mtrr()
1953 15:07:54.355807 CPU physical address size: 39 bits
1954 15:07:54.359125 CPU physical address size: 39 bits
1955 15:07:54.362342 CBFS: Found @ offset 1c96c0 size 3f798
1956 15:07:54.369012 Checking segment from ROM address 0xffdd16f8
1957 15:07:54.372907 Checking segment from ROM address 0xffdd1714
1958 15:07:54.376080 Loading segment from ROM address 0xffdd16f8
1959 15:07:54.379354 code (compression=0)
1960 15:07:54.389246 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1961 15:07:54.395725 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1962 15:07:54.398967 it's not compressed!
1963 15:07:54.490948 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1964 15:07:54.497421 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1965 15:07:54.500529 Loading segment from ROM address 0xffdd1714
1966 15:07:54.503953 Entry Point 0x30000000
1967 15:07:54.507133 Loaded segments
1968 15:07:54.513003 Finalizing chipset.
1969 15:07:54.516228 Finalizing SMM.
1970 15:07:54.519573 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1971 15:07:54.522692 mp_park_aps done after 0 msecs.
1972 15:07:54.529788 Jumping to boot code at 30000000(99b62000)
1973 15:07:54.535984 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1974 15:07:54.536098
1975 15:07:54.536172
1976 15:07:54.536240
1977 15:07:54.539177 Starting depthcharge on Helios...
1978 15:07:54.539269
1979 15:07:54.539585 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
1980 15:07:54.539701 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
1981 15:07:54.539823 Setting prompt string to ['hatch:']
1982 15:07:54.539917 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
1983 15:07:54.549001 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1984 15:07:54.549103
1985 15:07:54.556046 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1986 15:07:54.556149
1987 15:07:54.562211 board_setup: Info: eMMC controller not present; skipping
1988 15:07:54.562314
1989 15:07:54.566046 New NVMe Controller 0x30053ac0 @ 00:1d:00
1990 15:07:54.566145
1991 15:07:54.572045 board_setup: Info: SDHCI controller not present; skipping
1992 15:07:54.572143
1993 15:07:54.576010 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
1994 15:07:54.579311
1995 15:07:54.579403 Wipe memory regions:
1996 15:07:54.579492
1997 15:07:54.582034 [0x00000000001000, 0x000000000a0000)
1998 15:07:54.582127
1999 15:07:54.585379 [0x00000000100000, 0x00000030000000)
2000 15:07:54.651736
2001 15:07:54.654912 [0x00000030657430, 0x00000099a2c000)
2002 15:07:54.802039
2003 15:07:54.805235 [0x00000100000000, 0x0000045e800000)
2004 15:07:56.261038
2005 15:07:56.261219 R8152: Initializing
2006 15:07:56.261335
2007 15:07:56.263883 Version 9 (ocp_data = 6010)
2008 15:07:56.268005
2009 15:07:56.268097 R8152: Done initializing
2010 15:07:56.268170
2011 15:07:56.271440 Adding net device
2012 15:07:56.754201
2013 15:07:56.754379 R8152: Initializing
2014 15:07:56.754506
2015 15:07:56.757239 Version 6 (ocp_data = 5c30)
2016 15:07:56.757374
2017 15:07:56.761137 R8152: Done initializing
2018 15:07:56.761263
2019 15:07:56.764468 net_add_device: Attemp to include the same device
2020 15:07:56.767668
2021 15:07:56.774988 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2022 15:07:56.775090
2023 15:07:56.775160
2024 15:07:56.775227
2025 15:07:56.775515 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2027 15:07:56.875854 hatch: tftpboot 192.168.201.1 10660955/tftp-deploy-khoypiv0/kernel/bzImage 10660955/tftp-deploy-khoypiv0/kernel/cmdline 10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
2028 15:07:56.876037 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2029 15:07:56.876136 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2030 15:07:56.880215 tftpboot 192.168.201.1 10660955/tftp-deploy-khoypiv0/kernel/bzIploy-khoypiv0/kernel/cmdline 10660955/tftp-deploy-khoypiv0/ramdisk/ramdisk.cpio.gz
2031 15:07:56.880314
2032 15:07:56.880387 Waiting for link
2033 15:07:57.081062
2034 15:07:57.081202 done.
2035 15:07:57.081279
2036 15:07:57.081347 MAC: 00:24:32:50:1a:59
2037 15:07:57.081414
2038 15:07:57.084491 Sending DHCP discover... done.
2039 15:07:57.084585
2040 15:07:57.087812 Waiting for reply... done.
2041 15:07:57.087928
2042 15:07:57.091101 Sending DHCP request... done.
2043 15:07:57.091224
2044 15:07:57.093959 Waiting for reply... done.
2045 15:07:57.094071
2046 15:07:57.097244 My ip is 192.168.201.14
2047 15:07:57.097329
2048 15:07:57.100557 The DHCP server ip is 192.168.201.1
2049 15:07:57.100663
2050 15:07:57.104021 TFTP server IP predefined by user: 192.168.201.1
2051 15:07:57.104141
2052 15:07:57.110685 Bootfile predefined by user: 10660955/tftp-deploy-khoypiv0/kernel/bzImage
2053 15:07:57.110787
2054 15:07:57.113990 Sending tftp read request... done.
2055 15:07:57.117390
2056 15:07:57.121163 Waiting for the transfer...
2057 15:07:57.121295
2058 15:07:57.649502 00000000 ################################################################
2059 15:07:57.649702
2060 15:07:58.166676 00080000 ################################################################
2061 15:07:58.166819
2062 15:07:58.686941 00100000 ################################################################
2063 15:07:58.687085
2064 15:07:59.213203 00180000 ################################################################
2065 15:07:59.213349
2066 15:07:59.753927 00200000 ################################################################
2067 15:07:59.754122
2068 15:08:00.400815 00280000 ################################################################
2069 15:08:00.401001
2070 15:08:01.080129 00300000 ################################################################
2071 15:08:01.080317
2072 15:08:01.742115 00380000 ################################################################
2073 15:08:01.742295
2074 15:08:02.352912 00400000 ################################################################
2075 15:08:02.353067
2076 15:08:02.932348 00480000 ################################################################
2077 15:08:02.932494
2078 15:08:03.496814 00500000 ################################################################
2079 15:08:03.496994
2080 15:08:04.070516 00580000 ################################################################
2081 15:08:04.070700
2082 15:08:04.640920 00600000 ################################################################
2083 15:08:04.641107
2084 15:08:05.212170 00680000 ################################################################
2085 15:08:05.212360
2086 15:08:05.793292 00700000 ################################################################
2087 15:08:05.793484
2088 15:08:06.333164 00780000 ################################################################
2089 15:08:06.333360
2090 15:08:06.847454 00800000 ################################################################
2091 15:08:06.847670
2092 15:08:07.365159 00880000 ################################################################
2093 15:08:07.365363
2094 15:08:07.884196 00900000 ################################################################
2095 15:08:07.884387
2096 15:08:08.392894 00980000 ################################################################
2097 15:08:08.393106
2098 15:08:08.754696 00a00000 ############################################## done.
2099 15:08:08.754880
2100 15:08:08.758559 The bootfile was 10858496 bytes long.
2101 15:08:08.758696
2102 15:08:08.761881 Sending tftp read request... done.
2103 15:08:08.762006
2104 15:08:08.765019 Waiting for the transfer...
2105 15:08:08.765138
2106 15:08:09.274113 00000000 ################################################################
2107 15:08:09.274282
2108 15:08:09.786063 00080000 ################################################################
2109 15:08:09.786219
2110 15:08:10.323751 00100000 ################################################################
2111 15:08:10.323956
2112 15:08:10.814123 00180000 ################################################################
2113 15:08:10.814326
2114 15:08:11.327855 00200000 ################################################################
2115 15:08:11.328027
2116 15:08:11.839815 00280000 ################################################################
2117 15:08:11.839957
2118 15:08:12.352316 00300000 ################################################################
2119 15:08:12.352484
2120 15:08:12.865856 00380000 ################################################################
2121 15:08:12.866047
2122 15:08:13.383427 00400000 ################################################################
2123 15:08:13.383598
2124 15:08:13.895770 00480000 ################################################################
2125 15:08:13.895933
2126 15:08:14.408238 00500000 ################################################################
2127 15:08:14.408450
2128 15:08:14.944247 00580000 ################################################################
2129 15:08:14.944432
2130 15:08:15.488184 00600000 ################################################################
2131 15:08:15.488354
2132 15:08:16.044782 00680000 ################################################################
2133 15:08:16.044985
2134 15:08:16.607188 00700000 ################################################################
2135 15:08:16.607345
2136 15:08:17.168945 00780000 ################################################################
2137 15:08:17.169130
2138 15:08:17.742007 00800000 ################################################################
2139 15:08:17.742154
2140 15:08:18.071348 00880000 ###################################### done.
2141 15:08:18.071518
2142 15:08:18.074449 Sending tftp read request... done.
2143 15:08:18.074540
2144 15:08:18.078148 Waiting for the transfer...
2145 15:08:18.078238
2146 15:08:18.078309 00000000 # done.
2147 15:08:18.078376
2148 15:08:18.087590 Command line loaded dynamically from TFTP file: 10660955/tftp-deploy-khoypiv0/kernel/cmdline
2149 15:08:18.087681
2150 15:08:18.104117 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2151 15:08:18.104227
2152 15:08:18.110943 ec_init(0): CrosEC protocol v3 supported (256, 256)
2153 15:08:18.116175
2154 15:08:18.119316 Shutting down all USB controllers.
2155 15:08:18.119408
2156 15:08:18.119494 Removing current net device
2157 15:08:18.123192
2158 15:08:18.123282 Finalizing coreboot
2159 15:08:18.123355
2160 15:08:18.129732 Exiting depthcharge with code 4 at timestamp: 30947232
2161 15:08:18.129825
2162 15:08:18.129910
2163 15:08:18.130011 Starting kernel ...
2164 15:08:18.130112
2165 15:08:18.130208
2166 15:08:18.130612 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
2167 15:08:18.130715 start: 2.2.5 auto-login-action (timeout 00:04:18) [common]
2168 15:08:18.130796 Setting prompt string to ['Linux version [0-9]']
2169 15:08:18.130870 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2170 15:08:18.130943 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2172 15:12:36.131006 end: 2.2.5 auto-login-action (duration 00:04:18) [common]
2174 15:12:36.131240 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 258 seconds'
2176 15:12:36.131418 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2179 15:12:36.131732 end: 2 depthcharge-action (duration 00:05:00) [common]
2181 15:12:36.131988 Cleaning after the job
2182 15:12:36.132089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/ramdisk
2183 15:12:36.133363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/kernel
2184 15:12:36.134762 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10660955/tftp-deploy-khoypiv0/modules
2185 15:12:36.135352 start: 5.1 power-off (timeout 00:00:30) [common]
2186 15:12:36.135555 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=off'
2187 15:12:36.214419 >> Command sent successfully.
2188 15:12:36.216964 Returned 0 in 0 seconds
2189 15:12:36.317327 end: 5.1 power-off (duration 00:00:00) [common]
2191 15:12:36.317696 start: 5.2 read-feedback (timeout 00:10:00) [common]
2192 15:12:36.318020 Listened to connection for namespace 'common' for up to 1s
2194 15:12:36.318429 Listened to connection for namespace 'common' for up to 1s
2195 15:12:37.318962 Finalising connection for namespace 'common'
2196 15:12:37.319149 Disconnecting from shell: Finalise
2197 15:12:37.319235
2198 15:12:37.419594 end: 5.2 read-feedback (duration 00:00:01) [common]
2199 15:12:37.419795 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10660955
2200 15:12:37.436621 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10660955
2201 15:12:37.436819 JobError: Your job cannot terminate cleanly.