Boot log: acer-cb317-1h-c3z6-dedede
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
1 11:51:33.582659 lava-dispatcher, installed at version: 2023.05.1
2 11:51:33.582880 start: 0 validate
3 11:51:33.583017 Start time: 2023-06-23 11:51:33.583010+00:00 (UTC)
4 11:51:33.583155 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:51:33.583291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230609.0%2Fx86%2Frootfs.cpio.gz exists
6 11:51:33.843052 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:51:33.843250 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.287-cip100%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 11:51:34.109547 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:51:34.110287 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.287-cip100%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 11:51:42.634366 validate duration: 9.05
12 11:51:42.634752 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 11:51:42.634903 start: 1.1 download-retry (timeout 00:10:00) [common]
14 11:51:42.635034 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 11:51:42.635204 Not decompressing ramdisk as can be used compressed.
16 11:51:42.635326 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230609.0/x86/rootfs.cpio.gz
17 11:51:42.635427 saving as /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/ramdisk/rootfs.cpio.gz
18 11:51:42.635522 total size: 8435745 (8MB)
19 11:51:43.296928 progress 0% (0MB)
20 11:51:43.299271 progress 5% (0MB)
21 11:51:43.301515 progress 10% (0MB)
22 11:51:43.303719 progress 15% (1MB)
23 11:51:43.305964 progress 20% (1MB)
24 11:51:43.308161 progress 25% (2MB)
25 11:51:43.310410 progress 30% (2MB)
26 11:51:43.312650 progress 35% (2MB)
27 11:51:43.315093 progress 40% (3MB)
28 11:51:43.317662 progress 45% (3MB)
29 11:51:43.319949 progress 50% (4MB)
30 11:51:43.322181 progress 55% (4MB)
31 11:51:43.324381 progress 60% (4MB)
32 11:51:43.326602 progress 65% (5MB)
33 11:51:43.328811 progress 70% (5MB)
34 11:51:43.331095 progress 75% (6MB)
35 11:51:43.333130 progress 80% (6MB)
36 11:51:43.335285 progress 85% (6MB)
37 11:51:43.337477 progress 90% (7MB)
38 11:51:43.339657 progress 95% (7MB)
39 11:51:43.341910 progress 100% (8MB)
40 11:51:43.342073 8MB downloaded in 0.71s (11.39MB/s)
41 11:51:43.342226 end: 1.1.1 http-download (duration 00:00:01) [common]
43 11:51:43.342471 end: 1.1 download-retry (duration 00:00:01) [common]
44 11:51:43.342559 start: 1.2 download-retry (timeout 00:09:59) [common]
45 11:51:43.342655 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 11:51:43.342788 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.287-cip100/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 11:51:43.342858 saving as /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/kernel/bzImage
48 11:51:43.342920 total size: 10859008 (10MB)
49 11:51:43.342980 No compression specified
50 11:51:43.344085 progress 0% (0MB)
51 11:51:43.346884 progress 5% (0MB)
52 11:51:43.349810 progress 10% (1MB)
53 11:51:43.352639 progress 15% (1MB)
54 11:51:43.355569 progress 20% (2MB)
55 11:51:43.358311 progress 25% (2MB)
56 11:51:43.361200 progress 30% (3MB)
57 11:51:43.363878 progress 35% (3MB)
58 11:51:43.366816 progress 40% (4MB)
59 11:51:43.369852 progress 45% (4MB)
60 11:51:43.372593 progress 50% (5MB)
61 11:51:43.375432 progress 55% (5MB)
62 11:51:43.378162 progress 60% (6MB)
63 11:51:43.381031 progress 65% (6MB)
64 11:51:43.383666 progress 70% (7MB)
65 11:51:43.386502 progress 75% (7MB)
66 11:51:43.389350 progress 80% (8MB)
67 11:51:43.391979 progress 85% (8MB)
68 11:51:43.394817 progress 90% (9MB)
69 11:51:43.397532 progress 95% (9MB)
70 11:51:43.400483 progress 100% (10MB)
71 11:51:43.400640 10MB downloaded in 0.06s (179.43MB/s)
72 11:51:43.400785 end: 1.2.1 http-download (duration 00:00:00) [common]
74 11:51:43.401013 end: 1.2 download-retry (duration 00:00:00) [common]
75 11:51:43.401103 start: 1.3 download-retry (timeout 00:09:59) [common]
76 11:51:43.401188 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 11:51:43.401318 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.287-cip100/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 11:51:43.401387 saving as /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/modules/modules.tar
79 11:51:43.401449 total size: 483808 (0MB)
80 11:51:43.401510 Using unxz to decompress xz
81 11:51:43.405180 progress 6% (0MB)
82 11:51:43.405575 progress 13% (0MB)
83 11:51:43.405812 progress 20% (0MB)
84 11:51:43.407273 progress 27% (0MB)
85 11:51:43.409412 progress 33% (0MB)
86 11:51:43.411510 progress 40% (0MB)
87 11:51:43.413565 progress 47% (0MB)
88 11:51:43.415312 progress 54% (0MB)
89 11:51:43.417722 progress 60% (0MB)
90 11:51:43.420129 progress 67% (0MB)
91 11:51:43.422220 progress 74% (0MB)
92 11:51:43.424185 progress 81% (0MB)
93 11:51:43.426388 progress 88% (0MB)
94 11:51:43.428372 progress 94% (0MB)
95 11:51:43.430371 progress 100% (0MB)
96 11:51:43.436460 0MB downloaded in 0.04s (13.18MB/s)
97 11:51:43.436836 end: 1.3.1 http-download (duration 00:00:00) [common]
99 11:51:43.437268 end: 1.3 download-retry (duration 00:00:00) [common]
100 11:51:43.437423 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
101 11:51:43.437547 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
102 11:51:43.437696 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 11:51:43.437816 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
104 11:51:43.438036 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk
105 11:51:43.438164 makedir: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin
106 11:51:43.438299 makedir: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/tests
107 11:51:43.438415 makedir: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/results
108 11:51:43.438529 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-add-keys
109 11:51:43.438703 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-add-sources
110 11:51:43.438860 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-background-process-start
111 11:51:43.439026 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-background-process-stop
112 11:51:43.439149 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-common-functions
113 11:51:43.439270 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-echo-ipv4
114 11:51:43.439452 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-install-packages
115 11:51:43.439608 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-installed-packages
116 11:51:43.439746 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-os-build
117 11:51:43.439899 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-probe-channel
118 11:51:43.440063 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-probe-ip
119 11:51:43.440232 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-target-ip
120 11:51:43.440399 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-target-mac
121 11:51:43.440522 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-target-storage
122 11:51:43.440651 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-case
123 11:51:43.440775 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-event
124 11:51:43.440911 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-feedback
125 11:51:43.441045 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-raise
126 11:51:43.441199 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-reference
127 11:51:43.441321 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-runner
128 11:51:43.441493 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-set
129 11:51:43.441686 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-test-shell
130 11:51:43.441878 Updating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-install-packages (oe)
131 11:51:43.442054 Updating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/bin/lava-installed-packages (oe)
132 11:51:43.442175 Creating /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/environment
133 11:51:43.442277 LAVA metadata
134 11:51:43.442351 - LAVA_JOB_ID=10875898
135 11:51:43.442448 - LAVA_DISPATCHER_IP=192.168.201.1
136 11:51:43.442548 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
137 11:51:43.442619 skipped lava-vland-overlay
138 11:51:43.442694 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 11:51:43.442794 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
140 11:51:43.442871 skipped lava-multinode-overlay
141 11:51:43.442945 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 11:51:43.443029 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
143 11:51:43.443107 Loading test definitions
144 11:51:43.443212 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
145 11:51:43.443326 Using /lava-10875898 at stage 0
146 11:51:43.443751 uuid=10875898_1.4.2.3.1 testdef=None
147 11:51:43.443895 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 11:51:43.444018 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
149 11:51:43.444717 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 11:51:43.445005 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
152 11:51:43.445741 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 11:51:43.446177 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
155 11:51:43.447328 runner path: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/0/tests/0_dmesg test_uuid 10875898_1.4.2.3.1
156 11:51:43.447562 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 11:51:43.447828 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
159 11:51:43.447899 Using /lava-10875898 at stage 1
160 11:51:43.448205 uuid=10875898_1.4.2.3.5 testdef=None
161 11:51:43.448302 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 11:51:43.448402 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
163 11:51:43.449054 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 11:51:43.449460 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
166 11:51:43.450483 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 11:51:43.450869 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
169 11:51:43.451866 runner path: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/1/tests/1_bootrr test_uuid 10875898_1.4.2.3.5
170 11:51:43.452078 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 11:51:43.452438 Creating lava-test-runner.conf files
173 11:51:43.452559 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/0 for stage 0
174 11:51:43.452719 - 0_dmesg
175 11:51:43.452869 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10875898/lava-overlay-i8207rlk/lava-10875898/1 for stage 1
176 11:51:43.452990 - 1_bootrr
177 11:51:43.453142 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 11:51:43.453275 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
179 11:51:43.463837 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 11:51:43.463976 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
181 11:51:43.464068 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 11:51:43.464158 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 11:51:43.464245 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
184 11:51:43.720071 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 11:51:43.720465 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
186 11:51:43.720592 extracting modules file /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10875898/extract-overlay-ramdisk-sj92ipi2/ramdisk
187 11:51:43.742797 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 11:51:43.743006 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
189 11:51:43.743144 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10875898/compress-overlay-ctwnjv8r/overlay-1.4.2.4.tar.gz to ramdisk
190 11:51:43.743248 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10875898/compress-overlay-ctwnjv8r/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10875898/extract-overlay-ramdisk-sj92ipi2/ramdisk
191 11:51:43.752662 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 11:51:43.752805 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
193 11:51:43.752908 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 11:51:43.753000 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
195 11:51:43.753087 Building ramdisk /var/lib/lava/dispatcher/tmp/10875898/extract-overlay-ramdisk-sj92ipi2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10875898/extract-overlay-ramdisk-sj92ipi2/ramdisk
196 11:51:43.892107 >> 53980 blocks
197 11:51:44.817119 rename /var/lib/lava/dispatcher/tmp/10875898/extract-overlay-ramdisk-sj92ipi2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
198 11:51:44.817580 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 11:51:44.817716 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 11:51:44.817827 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 11:51:44.817925 No mkimage arch provided, not using FIT.
202 11:51:44.818016 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 11:51:44.818110 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 11:51:44.818218 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 11:51:44.818305 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 11:51:44.818382 No LXC device requested
207 11:51:44.818460 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 11:51:44.818553 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 11:51:44.818633 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 11:51:44.818704 Checking files for TFTP limit of 4294967296 bytes.
211 11:51:44.819111 end: 1 tftp-deploy (duration 00:00:02) [common]
212 11:51:44.819212 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 11:51:44.819301 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 11:51:44.819432 substitutions:
215 11:51:44.819499 - {DTB}: None
216 11:51:44.819560 - {INITRD}: 10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
217 11:51:44.819619 - {KERNEL}: 10875898/tftp-deploy-2dr24zd4/kernel/bzImage
218 11:51:44.819676 - {LAVA_MAC}: None
219 11:51:44.819740 - {PRESEED_CONFIG}: None
220 11:51:44.819797 - {PRESEED_LOCAL}: None
221 11:51:44.819852 - {RAMDISK}: 10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
222 11:51:44.819912 - {ROOT_PART}: None
223 11:51:44.819968 - {ROOT}: None
224 11:51:44.820021 - {SERVER_IP}: 192.168.201.1
225 11:51:44.820075 - {TEE}: None
226 11:51:44.820128 Parsed boot commands:
227 11:51:44.820180 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 11:51:44.820382 Parsed boot commands: tftpboot 192.168.201.1 10875898/tftp-deploy-2dr24zd4/kernel/bzImage 10875898/tftp-deploy-2dr24zd4/kernel/cmdline 10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
229 11:51:44.820470 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 11:51:44.820565 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 11:51:44.820657 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 11:51:44.820748 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 11:51:44.820818 Not connected, no need to disconnect.
234 11:51:44.820891 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 11:51:44.820972 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 11:51:44.821037 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost acer-cb317-1h-c3z6-dedede-cbg-8'
237 11:51:44.824947 Setting prompt string to ['lava-test: # ']
238 11:51:44.825335 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 11:51:44.825462 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 11:51:44.825580 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 11:51:44.825675 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 11:51:44.825890 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cb317-1h-c3z6-dedede-cbg-8' '--port=1' '--command=reboot'
243 11:51:49.961801 >> Command sent successfully.
244 11:51:49.964521 Returned 0 in 5 seconds
245 11:51:50.064956 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 11:51:50.065403 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 11:51:50.065548 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 11:51:50.065674 Setting prompt string to 'Starting depthcharge on Magolor...'
250 11:51:50.065776 Changing prompt to 'Starting depthcharge on Magolor...'
251 11:51:50.065879 depthcharge-start: Wait for prompt Starting depthcharge on Magolor... (timeout 00:05:00)
252 11:51:50.066269 [Enter `^Ec?' for help]
253 11:51:51.611472
254 11:51:51.611661
255 11:51:51.611773 coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 bootblock starting (log level: 8)...
256 11:51:51.611875 CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz
257 11:51:51.611978 CPU: ID 906c0, Jasperlake A0, ucode: 2400001f
258 11:51:51.612080 CPU: AES supported, TXT NOT supported, VT supported
259 11:51:51.612184 MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1
260 11:51:51.612277 PCH: device id 4d87 (rev 01) is Jasperlake Super
261 11:51:51.612372 IGD: device id 4e55 (rev 01) is Jasperlake GT4
262 11:51:51.612435 VBOOT: Loading verstage.
263 11:51:51.612497 FMAP: Found "FLASH" version 1.1 at 0xc04000.
264 11:51:51.612557 FMAP: base = 0xff000000 size = 0x1000000 #areas = 32
265 11:51:51.612616 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
266 11:51:51.612674 CBFS: Found 'fallback/verstage' @0xfa740 size 0x155ec
267 11:51:51.612731
268 11:51:51.612788
269 11:51:51.612844 coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 verstage starting (log level: 8)...
270 11:51:51.612901 Probing TPM: . done!
271 11:51:51.612958 TPM ready after 0 ms
272 11:51:51.613014 Connected to device vid:did:rid of 1ae0:0028:00
273 11:51:51.613070 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
274 11:51:51.613128 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
275 11:51:51.613184 Initialized TPM device CR50 revision 0
276 11:51:51.613240 tlcl_send_startup: Startup return code is 0
277 11:51:51.613297 TPM: setup succeeded
278 11:51:51.613353 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
279 11:51:51.613409 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
280 11:51:51.613465 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
281 11:51:51.613521 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
282 11:51:51.613576 Chrome EC: UHEPI supported
283 11:51:51.613632 Phase 1
284 11:51:51.613688 FMAP: area GBB found @ c05000 (12288 bytes)
285 11:51:51.613744 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
286 11:51:51.613800 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
287 11:51:51.613856 Recovery requested (1009000e)
288 11:51:51.613911 TPM: Extending digest for VBOOT: boot mode into PCR 0
289 11:51:51.613967 tlcl_extend: response is 0
290 11:51:51.614022 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
291 11:51:51.614077 tlcl_extend: response is 0
292 11:51:51.614133 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
293 11:51:51.614188 CBFS: Found 'fallback/romstage' @0x80 size 0x1bde4
294 11:51:51.614244 BS: verstage times (exec / console): total (unknown) / 124 ms
295 11:51:51.614299
296 11:51:51.614355
297 11:51:51.614410 coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 romstage starting (log level: 8)...
298 11:51:51.614467 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
299 11:51:51.614523 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
300 11:51:51.614578 gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000
301 11:51:51.614634 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
302 11:51:51.614689 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
303 11:51:51.614744 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
304 11:51:51.614799 TCO_STS: 0000 0001
305 11:51:51.614854 GEN_PMCON: d0015038 00002200
306 11:51:51.614909 GBLRST_CAUSE: 00000000 00000000
307 11:51:51.614965 prev_sleep_state 5
308 11:51:51.615019 Boot Count incremented to 353
309 11:51:51.615074 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
310 11:51:51.615130 CBFS: Found 'fspm.bin' @0x44fc0 size 0x79000
311 11:51:51.615185 Chrome EC: UHEPI supported
312 11:51:51.615240 FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes)
313 11:51:51.615296 Probing TPM: done!
314 11:51:51.615351 Connected to device vid:did:rid of 1ae0:0028:00
315 11:51:51.615407 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
316 11:51:51.615463 Initialized TPM device CR50 revision 0
317 11:51:51.624746 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
318 11:51:51.628128 MRC: Hash idx 0x100b comparison successful.
319 11:51:51.631688 MRC cache found, size 5458
320 11:51:51.635736 bootmode is set to: 2
321 11:51:51.635858 SPD INDEX = 0
322 11:51:51.642548 CBFS: Found 'spd.bin' @0x40c40 size 0x600
323 11:51:51.642678 SPD: module type is LPDDR4X
324 11:51:51.649416 SPD: module part number is MT53E512M32D2NP-046 WT:E
325 11:51:51.656135 SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb
326 11:51:51.659328 SPD: device width 16 bits, bus width 32 bits
327 11:51:51.662649 SPD: module size is 4096 MB (per channel)
328 11:51:51.669319 meminit_channels: DRAM half-populated
329 11:51:51.750209 CBMEM:
330 11:51:51.753784 IMD: root @ 0x76fff000 254 entries.
331 11:51:51.756878 IMD: root @ 0x76ffec00 62 entries.
332 11:51:51.760049 FMAP: area RO_VPD found @ c00000 (16384 bytes)
333 11:51:51.766690 WARNING: RO_VPD is uninitialized or empty.
334 11:51:51.770056 FMAP: area RW_VPD found @ bfc000 (8192 bytes)
335 11:51:51.774071 External stage cache:
336 11:51:51.777329 IMD: root @ 0x7b3ff000 254 entries.
337 11:51:51.780713 IMD: root @ 0x7b3fec00 62 entries.
338 11:51:51.790367 FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes)
339 11:51:51.797280 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
340 11:51:51.803795 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
341 11:51:51.811705 MRC: 'RECOVERY_MRC_CACHE' does not need update.
342 11:51:51.818348 cse_lite: Skip switching to RW in the recovery path
343 11:51:51.818470 1 DIMMs found
344 11:51:51.818571 SMM Memory Map
345 11:51:51.821706 SMRAM : 0x7b000000 0x800000
346 11:51:51.828139 Subregion 0: 0x7b000000 0x200000
347 11:51:51.831628 Subregion 1: 0x7b200000 0x200000
348 11:51:51.835103 Subregion 2: 0x7b400000 0x400000
349 11:51:51.835219 top_of_ram = 0x77000000
350 11:51:51.841589 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
351 11:51:51.848142 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
352 11:51:51.851398 MTRR Range: Start=ff000000 End=0 (Size 1000000)
353 11:51:51.858059 CBFS: Found 'fallback/postcar' @0xf5940 size 0x4d9c
354 11:51:51.864495 Decompressing stage fallback/postcar @ 0x76c0dfc0 (36304 bytes)
355 11:51:51.874548 Loading module at 0x76c0e000 with entry 0x76c0e000. filesize: 0x4a50 memsize: 0x8d90
356 11:51:51.877920 Processing 188 relocs. Offset value of 0x74c0e000
357 11:51:51.887273 BS: romstage times (exec / console): total (unknown) / 255 ms
358 11:51:51.891291
359 11:51:51.891419
360 11:51:51.901783 coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 postcar starting (log level: 8)...
361 11:51:51.904758 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
362 11:51:51.911742 CBFS: Found 'fallback/ramstage' @0x20f80 size 0x1f488
363 11:51:51.918112 Decompressing stage fallback/ramstage @ 0x76ba7fc0 (413104 bytes)
364 11:51:51.973811 Loading module at 0x76ba8000 with entry 0x76ba8000. filesize: 0x4ec20 memsize: 0x64d70
365 11:51:51.980274 Processing 4805 relocs. Offset value of 0x75da8000
366 11:51:51.986852 BS: postcar times (exec / console): total (unknown) / 42 ms
367 11:51:51.986994
368 11:51:51.987098
369 11:51:51.996728 coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 ramstage starting (log level: 8)...
370 11:51:51.996842 Normal boot
371 11:51:52.000628 EC returned error result code 3
372 11:51:52.004122 FW_CONFIG value is 0x204
373 11:51:52.007706 GENERIC: 0.0 disabled by fw_config
374 11:51:52.013939 fw_config match found: TS_SOURCE=TS_UNPROVISIONED
375 11:51:52.017387 I2C: 00:10 disabled by fw_config
376 11:51:52.020971 I2C: 00:10 disabled by fw_config
377 11:51:52.023822 fw_config match found: TS_SOURCE=TS_UNPROVISIONED
378 11:51:52.030392 fw_config match found: TS_SOURCE=TS_UNPROVISIONED
379 11:51:52.034142 fw_config match found: TS_SOURCE=TS_UNPROVISIONED
380 11:51:52.040792 fw_config match found: TS_SOURCE=TS_UNPROVISIONED
381 11:51:52.043654 fw_config match found: CAMERA_WFC=CAMERA_UNPROVISIONED
382 11:51:52.047013 I2C: 00:10 disabled by fw_config
383 11:51:52.053660 fw_config match found: CAMERA_VCM=CAMERA_VCM_UNPROVISIONED
384 11:51:52.060522 fw_config match found: AUDIO_CODEC_SOURCE=AUDIO_CODEC_UNPROVISIONED
385 11:51:52.063467 I2C: 00:1a disabled by fw_config
386 11:51:52.066954 I2C: 00:1a disabled by fw_config
387 11:51:52.073422 fw_config match found: AUDIO_AMP=UNPROVISIONED
388 11:51:52.077016 fw_config match found: AUDIO_AMP=UNPROVISIONED
389 11:51:52.079996 GENERIC: 0.0 disabled by fw_config
390 11:51:52.086813 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
391 11:51:52.090157 CBFS: Found 'cpu_microcode_blob.bin' @0x1bf00 size 0x5000
392 11:51:52.096802 microcode: sig=0x906c0 pf=0x1 revision=0x2400001f
393 11:51:52.100026 microcode: Update skipped, already up-to-date
394 11:51:52.106388 CBFS: Found 'fsps.bin' @0xbefc0 size 0x36906
395 11:51:52.132577 Detected 2 core, 2 thread CPU.
396 11:51:52.135995 Setting up SMI for CPU
397 11:51:52.139174 IED base = 0x7b400000
398 11:51:52.139289 IED size = 0x00400000
399 11:51:52.142829 Will perform SMM setup.
400 11:51:52.145671 CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz.
401 11:51:52.155918 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
402 11:51:52.159371 Processing 16 relocs. Offset value of 0x00030000
403 11:51:52.162886 Attempting to start 1 APs
404 11:51:52.166195 Waiting for 10ms after sending INIT.
405 11:51:52.182616 Waiting for 1st SIPI to complete...done.
406 11:51:52.182754 AP: slot 1 apic_id 2.
407 11:51:52.188920 Waiting for 2nd SIPI to complete...done.
408 11:51:52.195485 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
409 11:51:52.202566 Processing 13 relocs. Offset value of 0x00038000
410 11:51:52.202702 Unable to locate Global NVS
411 11:51:52.211990 SMM Module: stub loaded at 0x00038000. Will call 0x76bc5fe2(0x00000000)
412 11:51:52.215484 Installing permanent SMM handler to 0x7b000000
413 11:51:52.225140 Loading module at 0x7b010000 with entry 0x7b010a91. filesize: 0xba48 memsize: 0x10b10
414 11:51:52.228755 Processing 704 relocs. Offset value of 0x7b010000
415 11:51:52.238324 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
416 11:51:52.241810 Processing 13 relocs. Offset value of 0x7b008000
417 11:51:52.248436 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
418 11:51:52.251762 Unable to locate Global NVS
419 11:51:52.258332 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010a91(0x00000000)
420 11:51:52.261753 Clearing SMI status registers
421 11:51:52.261837 SMI_STS: PM1
422 11:51:52.264783 PM1_STS: PWRBTN
423 11:51:52.264861 TCO_STS: INTRD_DET
424 11:51:52.275006 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
425 11:51:52.278036 In relocation handler: CPU 0
426 11:51:52.281473 New SMBASE=0x7b000000 IEDBASE=0x7b400000
427 11:51:52.285129 Writing SMRR. base = 0x7b000006, mask=0xff800800
428 11:51:52.287904 Relocation complete.
429 11:51:52.294742 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
430 11:51:52.298932 In relocation handler: CPU 1
431 11:51:52.302742 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
432 11:51:52.306223 Writing SMRR. base = 0x7b000006, mask=0xff800800
433 11:51:52.308941 Relocation complete.
434 11:51:52.312225 Initializing CPU #0
435 11:51:52.315647 CPU: vendor Intel device 906c0
436 11:51:52.318989 CPU: family 06, model 9c, stepping 00
437 11:51:52.322288 Clearing out pending MCEs
438 11:51:52.322366 Setting up local APIC...
439 11:51:52.325382 apic_id: 0x00 done.
440 11:51:52.328730 Turbo is available but hidden
441 11:51:52.332472 Turbo is available and visible
442 11:51:52.335440 microcode: Update skipped, already up-to-date
443 11:51:52.339091 CPU #0 initialized
444 11:51:52.339168 Initializing CPU #1
445 11:51:52.342631 CPU: vendor Intel device 906c0
446 11:51:52.349177 CPU: family 06, model 9c, stepping 00
447 11:51:52.349266 Clearing out pending MCEs
448 11:51:52.352348 Setting up local APIC...
449 11:51:52.355345 apic_id: 0x02 done.
450 11:51:52.358700 microcode: Update skipped, already up-to-date
451 11:51:52.361928 CPU #1 initialized
452 11:51:52.365210 bsp_do_flight_plan done after 173 msecs.
453 11:51:52.368788 CPU: frequency set to 2800 MHz
454 11:51:52.368877 Enabling SMIs.
455 11:51:52.375145 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 85 / 287 ms
456 11:51:52.386707 Probing TPM: done!
457 11:51:52.392955 Connected to device vid:did:rid of 1ae0:0028:00
458 11:51:52.402927 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
459 11:51:52.406235 Initialized TPM device CR50 revision 0
460 11:51:52.410230 CBFS: Found 'vbt.bin' @0x445c0 size 0x4bc
461 11:51:52.416489 Found a VBT of 7680 bytes after decompression
462 11:51:52.423047 WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called
463 11:51:52.458560 Detected 2 core, 2 thread CPU.
464 11:51:52.461683 Detected 2 core, 2 thread CPU.
465 11:51:52.823289 Display FSP Version Info HOB
466 11:51:52.826547 Reference Code - CPU = 8.7.22.30
467 11:51:52.829579 uCode Version = 24.0.0.1f
468 11:51:52.833075 TXT ACM version = ff.ff.ff.ffff
469 11:51:52.836558 Reference Code - ME = 8.7.22.30
470 11:51:52.839757 MEBx version = 0.0.0.0
471 11:51:52.843373 ME Firmware Version = Consumer SKU
472 11:51:52.846072 Reference Code - PCH = 8.7.22.30
473 11:51:52.849496 PCH-CRID Status = Disabled
474 11:51:52.852980 PCH-CRID Original Value = ff.ff.ff.ffff
475 11:51:52.856143 PCH-CRID New Value = ff.ff.ff.ffff
476 11:51:52.859346 OPROM - RST - RAID = ff.ff.ff.ffff
477 11:51:52.862794 PCH Hsio Version = 4.0.0.0
478 11:51:52.866067 Reference Code - SA - System Agent = 8.7.22.30
479 11:51:52.869761 Reference Code - MRC = 0.0.4.68
480 11:51:52.872967 SA - PCIe Version = 8.7.22.30
481 11:51:52.877220 SA-CRID Status = Disabled
482 11:51:52.880625 SA-CRID Original Value = 0.0.0.0
483 11:51:52.880783 SA-CRID New Value = 0.0.0.0
484 11:51:52.884123 OPROM - VBIOS = ff.ff.ff.ffff
485 11:51:52.891109 IO Manageability Engine FW Version = ff.ff.ff.ffff
486 11:51:52.894678 PHY Build Version = ff.ff.ff.ffff
487 11:51:52.898240 Thunderbolt(TM) FW Version = ff.ff.ff.ffff
488 11:51:52.904653 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
489 11:51:52.908257 ITSS IRQ Polarities Before:
490 11:51:52.908395 IPC0: 0xffffffff
491 11:51:52.911100 IPC1: 0xffffffff
492 11:51:52.911219 IPC2: 0xffffffff
493 11:51:52.914507 IPC3: 0xffffffff
494 11:51:52.914631 ITSS IRQ Polarities After:
495 11:51:52.917887 IPC0: 0xffffffff
496 11:51:52.921288 IPC1: 0xffffffff
497 11:51:52.921412 IPC2: 0xffffffff
498 11:51:52.924878 IPC3: 0xffffffff
499 11:51:52.934524 pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:1c.7) which was enabled in devicetree, removing.
500 11:51:52.940980 BS: BS_DEV_INIT_CHIPS run times (exec / console): 403 / 156 ms
501 11:51:52.944465 Enumerating buses...
502 11:51:52.947933 Show all devs... Before device enumeration.
503 11:51:52.950774 Root Device: enabled 1
504 11:51:52.954214 CPU_CLUSTER: 0: enabled 1
505 11:51:52.954405 DOMAIN: 0000: enabled 1
506 11:51:52.957706 PCI: 00:00.0: enabled 1
507 11:51:52.960741 PCI: 00:02.0: enabled 1
508 11:51:52.964486 PCI: 00:04.0: enabled 1
509 11:51:52.964589 PCI: 00:05.0: enabled 1
510 11:51:52.967708 PCI: 00:09.0: enabled 0
511 11:51:52.971066 PCI: 00:12.6: enabled 0
512 11:51:52.974299 PCI: 00:14.0: enabled 1
513 11:51:52.974431 PCI: 00:14.1: enabled 0
514 11:51:52.977588 PCI: 00:14.2: enabled 0
515 11:51:52.980866 PCI: 00:14.3: enabled 1
516 11:51:52.980998 PCI: 00:14.5: enabled 1
517 11:51:52.984467 PCI: 00:15.0: enabled 1
518 11:51:52.987408 PCI: 00:15.1: enabled 1
519 11:51:52.990786 PCI: 00:15.2: enabled 1
520 11:51:52.990913 PCI: 00:15.3: enabled 1
521 11:51:52.994083 PCI: 00:16.0: enabled 1
522 11:51:52.997385 PCI: 00:16.1: enabled 0
523 11:51:53.000636 PCI: 00:16.4: enabled 0
524 11:51:53.000767 PCI: 00:16.5: enabled 0
525 11:51:53.004012 PCI: 00:17.0: enabled 0
526 11:51:53.007333 PCI: 00:19.0: enabled 1
527 11:51:53.010619 PCI: 00:19.1: enabled 0
528 11:51:53.010739 PCI: 00:19.2: enabled 1
529 11:51:53.014094 PCI: 00:1a.0: enabled 1
530 11:51:53.017253 PCI: 00:1c.0: enabled 0
531 11:51:53.017378 PCI: 00:1c.1: enabled 0
532 11:51:53.020282 PCI: 00:1c.2: enabled 0
533 11:51:53.023829 PCI: 00:1c.3: enabled 0
534 11:51:53.027206 PCI: 00:1c.4: enabled 0
535 11:51:53.027319 PCI: 00:1c.5: enabled 0
536 11:51:53.030118 PCI: 00:1c.6: enabled 0
537 11:51:53.033428 PCI: 00:1c.7: enabled 1
538 11:51:53.036879 PCI: 00:1e.0: enabled 0
539 11:51:53.036991 PCI: 00:1e.1: enabled 0
540 11:51:53.040387 PCI: 00:1e.2: enabled 1
541 11:51:53.043403 PCI: 00:1e.3: enabled 0
542 11:51:53.046995 PCI: 00:1f.0: enabled 1
543 11:51:53.047117 PCI: 00:1f.1: enabled 1
544 11:51:53.050245 PCI: 00:1f.2: enabled 1
545 11:51:53.053738 PCI: 00:1f.3: enabled 1
546 11:51:53.056480 PCI: 00:1f.4: enabled 0
547 11:51:53.056602 PCI: 00:1f.5: enabled 1
548 11:51:53.060050 PCI: 00:1f.7: enabled 0
549 11:51:53.063515 GENERIC: 0.0: enabled 1
550 11:51:53.063620 GENERIC: 0.0: enabled 1
551 11:51:53.066444 USB0 port 0: enabled 1
552 11:51:53.070090 GENERIC: 0.0: enabled 1
553 11:51:53.073234 I2C: 00:2c: enabled 1
554 11:51:53.073383 I2C: 00:15: enabled 1
555 11:51:53.076632 GENERIC: 0.0: enabled 0
556 11:51:53.079834 I2C: 00:15: enabled 1
557 11:51:53.079947 I2C: 00:10: enabled 0
558 11:51:53.083017 I2C: 00:10: enabled 0
559 11:51:53.086476 I2C: 00:2c: enabled 1
560 11:51:53.086660 I2C: 00:40: enabled 1
561 11:51:53.089671 I2C: 00:10: enabled 1
562 11:51:53.093170 I2C: 00:39: enabled 1
563 11:51:53.093282 I2C: 00:36: enabled 1
564 11:51:53.096003 I2C: 00:10: enabled 0
565 11:51:53.099545 I2C: 00:0c: enabled 1
566 11:51:53.099653 I2C: 00:50: enabled 1
567 11:51:53.102863 I2C: 00:1a: enabled 1
568 11:51:53.105963 I2C: 00:1a: enabled 0
569 11:51:53.106057 I2C: 00:1a: enabled 0
570 11:51:53.109287 I2C: 00:28: enabled 1
571 11:51:53.112988 I2C: 00:29: enabled 1
572 11:51:53.116166 PCI: 00:00.0: enabled 1
573 11:51:53.116252 SPI: 00: enabled 1
574 11:51:53.119522 PNP: 0c09.0: enabled 1
575 11:51:53.122404 GENERIC: 0.0: enabled 0
576 11:51:53.122495 USB2 port 0: enabled 1
577 11:51:53.125704 USB2 port 1: enabled 1
578 11:51:53.129320 USB2 port 2: enabled 1
579 11:51:53.129410 USB2 port 3: enabled 1
580 11:51:53.132812 USB2 port 4: enabled 0
581 11:51:53.136155 USB2 port 5: enabled 1
582 11:51:53.139521 USB2 port 6: enabled 0
583 11:51:53.139613 USB2 port 7: enabled 1
584 11:51:53.142317 USB3 port 0: enabled 1
585 11:51:53.146055 USB3 port 1: enabled 1
586 11:51:53.146175 USB3 port 2: enabled 1
587 11:51:53.148989 USB3 port 3: enabled 1
588 11:51:53.152234 APIC: 00: enabled 1
589 11:51:53.152368 APIC: 02: enabled 1
590 11:51:53.155837 Compare with tree...
591 11:51:53.158729 Root Device: enabled 1
592 11:51:53.158861 CPU_CLUSTER: 0: enabled 1
593 11:51:53.162445 APIC: 00: enabled 1
594 11:51:53.165313 APIC: 02: enabled 1
595 11:51:53.169011 DOMAIN: 0000: enabled 1
596 11:51:53.169123 PCI: 00:00.0: enabled 1
597 11:51:53.172102 PCI: 00:02.0: enabled 1
598 11:51:53.175928 PCI: 00:04.0: enabled 1
599 11:51:53.178759 GENERIC: 0.0: enabled 1
600 11:51:53.182209 PCI: 00:05.0: enabled 1
601 11:51:53.182295 GENERIC: 0.0: enabled 1
602 11:51:53.185457 PCI: 00:09.0: enabled 0
603 11:51:53.188878 PCI: 00:12.6: enabled 0
604 11:51:53.192123 PCI: 00:14.0: enabled 1
605 11:51:53.195541 USB0 port 0: enabled 1
606 11:51:53.195683 USB2 port 0: enabled 1
607 11:51:53.198509 USB2 port 1: enabled 1
608 11:51:53.201992 USB2 port 2: enabled 1
609 11:51:53.205554 USB2 port 3: enabled 1
610 11:51:53.208831 USB2 port 4: enabled 0
611 11:51:53.212136 USB2 port 5: enabled 1
612 11:51:53.212251 USB2 port 6: enabled 0
613 11:51:53.215099 USB2 port 7: enabled 1
614 11:51:53.218606 USB3 port 0: enabled 1
615 11:51:53.221995 USB3 port 1: enabled 1
616 11:51:53.225243 USB3 port 2: enabled 1
617 11:51:53.225338 USB3 port 3: enabled 1
618 11:51:53.228386 PCI: 00:14.1: enabled 0
619 11:51:53.231668 PCI: 00:14.2: enabled 0
620 11:51:53.235143 PCI: 00:14.3: enabled 1
621 11:51:53.238646 GENERIC: 0.0: enabled 1
622 11:51:53.238734 PCI: 00:14.5: enabled 1
623 11:51:53.241866 PCI: 00:15.0: enabled 1
624 11:51:53.244893 I2C: 00:2c: enabled 1
625 11:51:53.248438 I2C: 00:15: enabled 1
626 11:51:53.251278 PCI: 00:15.1: enabled 1
627 11:51:53.251393 PCI: 00:15.2: enabled 1
628 11:51:53.254719 GENERIC: 0.0: enabled 0
629 11:51:53.258156 I2C: 00:15: enabled 1
630 11:51:53.261567 I2C: 00:10: enabled 0
631 11:51:53.264847 I2C: 00:10: enabled 0
632 11:51:53.264937 I2C: 00:2c: enabled 1
633 11:51:53.267836 I2C: 00:40: enabled 1
634 11:51:53.271256 I2C: 00:10: enabled 1
635 11:51:53.274687 I2C: 00:39: enabled 1
636 11:51:53.274801 PCI: 00:15.3: enabled 1
637 11:51:53.277740 I2C: 00:36: enabled 1
638 11:51:53.281028 I2C: 00:10: enabled 0
639 11:51:53.284667 I2C: 00:0c: enabled 1
640 11:51:53.284798 I2C: 00:50: enabled 1
641 11:51:53.287525 PCI: 00:16.0: enabled 1
642 11:51:53.290820 PCI: 00:16.1: enabled 0
643 11:51:53.294125 PCI: 00:16.4: enabled 0
644 11:51:53.297903 PCI: 00:16.5: enabled 0
645 11:51:53.298023 PCI: 00:17.0: enabled 0
646 11:51:53.301086 PCI: 00:19.0: enabled 1
647 11:51:53.304641 I2C: 00:1a: enabled 1
648 11:51:53.307682 I2C: 00:1a: enabled 0
649 11:51:53.307798 I2C: 00:1a: enabled 0
650 11:51:53.310873 I2C: 00:28: enabled 1
651 11:51:53.314415 I2C: 00:29: enabled 1
652 11:51:53.317373 PCI: 00:19.1: enabled 0
653 11:51:53.320945 PCI: 00:19.2: enabled 1
654 11:51:53.321060 PCI: 00:1a.0: enabled 1
655 11:51:53.324164 PCI: 00:1e.0: enabled 0
656 11:51:53.327428 PCI: 00:1e.1: enabled 0
657 11:51:53.330515 PCI: 00:1e.2: enabled 1
658 11:51:53.330632 SPI: 00: enabled 1
659 11:51:53.333891 PCI: 00:1e.3: enabled 0
660 11:51:53.337201 PCI: 00:1f.0: enabled 1
661 11:51:53.340676 PNP: 0c09.0: enabled 1
662 11:51:53.344065 PCI: 00:1f.1: enabled 1
663 11:51:53.344180 PCI: 00:1f.2: enabled 1
664 11:51:53.347487 PCI: 00:1f.3: enabled 1
665 11:51:53.350456 GENERIC: 0.0: enabled 0
666 11:51:53.354080 PCI: 00:1f.4: enabled 0
667 11:51:53.356988 PCI: 00:1f.5: enabled 1
668 11:51:53.357117 PCI: 00:1f.7: enabled 0
669 11:51:53.360155 Root Device scanning...
670 11:51:53.363819 scan_static_bus for Root Device
671 11:51:53.367110 CPU_CLUSTER: 0 enabled
672 11:51:53.370596 DOMAIN: 0000 enabled
673 11:51:53.370732 DOMAIN: 0000 scanning...
674 11:51:53.373661 PCI: pci_scan_bus for bus 00
675 11:51:53.377159 PCI: 00:00.0 [8086/0000] ops
676 11:51:53.380101 PCI: 00:00.0 [8086/4e22] enabled
677 11:51:53.383467 PCI: 00:02.0 [8086/0000] bus ops
678 11:51:53.387125 PCI: 00:02.0 [8086/4e55] enabled
679 11:51:53.390157 PCI: 00:04.0 [8086/0000] bus ops
680 11:51:53.393585 PCI: 00:04.0 [8086/4e03] enabled
681 11:51:53.396823 PCI: 00:05.0 [8086/0000] bus ops
682 11:51:53.400034 PCI: 00:05.0 [8086/4e19] enabled
683 11:51:53.403162 PCI: 00:08.0 [8086/4e11] enabled
684 11:51:53.406482 PCI: 00:14.0 [8086/0000] bus ops
685 11:51:53.410050 PCI: 00:14.0 [8086/4ded] enabled
686 11:51:53.413370 PCI: 00:14.2 [8086/4def] disabled
687 11:51:53.416888 PCI: 00:14.3 [8086/0000] bus ops
688 11:51:53.420192 PCI: 00:14.3 [8086/4df0] enabled
689 11:51:53.423115 PCI: 00:14.5 [8086/0000] ops
690 11:51:53.426806 PCI: 00:14.5 [8086/4df8] enabled
691 11:51:53.430379 PCI: 00:15.0 [8086/0000] bus ops
692 11:51:53.433105 PCI: 00:15.0 [8086/4de8] enabled
693 11:51:53.436501 PCI: 00:15.1 [8086/0000] bus ops
694 11:51:53.439527 PCI: 00:15.1 [8086/4de9] enabled
695 11:51:53.443110 PCI: 00:15.2 [8086/0000] bus ops
696 11:51:53.446414 PCI: 00:15.2 [8086/4dea] enabled
697 11:51:53.449696 PCI: 00:15.3 [8086/0000] bus ops
698 11:51:53.453021 PCI: 00:15.3 [8086/4deb] enabled
699 11:51:53.456464 PCI: 00:16.0 [8086/0000] ops
700 11:51:53.459489 PCI: 00:16.0 [8086/4de0] enabled
701 11:51:53.462791 PCI: 00:19.0 [8086/0000] bus ops
702 11:51:53.466195 PCI: 00:19.0 [8086/4dc5] enabled
703 11:51:53.469820 PCI: 00:19.2 [8086/0000] ops
704 11:51:53.472977 PCI: 00:19.2 [8086/4dc7] enabled
705 11:51:53.476559 PCI: 00:1a.0 [8086/0000] ops
706 11:51:53.479472 PCI: 00:1a.0 [8086/4dc4] enabled
707 11:51:53.482957 PCI: 00:1e.0 [8086/0000] ops
708 11:51:53.485838 PCI: 00:1e.0 [8086/4da8] disabled
709 11:51:53.489387 PCI: 00:1e.2 [8086/0000] bus ops
710 11:51:53.492834 PCI: 00:1e.2 [8086/4daa] enabled
711 11:51:53.495835 PCI: 00:1f.0 [8086/0000] bus ops
712 11:51:53.499608 PCI: 00:1f.0 [8086/4d87] enabled
713 11:51:53.502579 PCI: Static device PCI: 00:1f.1 not found, disabling it.
714 11:51:53.505832 RTC Init
715 11:51:53.509052 Set power on after power failure.
716 11:51:53.509282 Disabling Deep S3
717 11:51:53.512462 Disabling Deep S3
718 11:51:53.512675 Disabling Deep S4
719 11:51:53.515776 Disabling Deep S4
720 11:51:53.519040 Disabling Deep S5
721 11:51:53.519250 Disabling Deep S5
722 11:51:53.522642 PCI: 00:1f.2 [0000/0000] hidden
723 11:51:53.525573 PCI: 00:1f.3 [8086/0000] bus ops
724 11:51:53.529052 PCI: 00:1f.3 [8086/4dc8] enabled
725 11:51:53.532661 PCI: 00:1f.5 [8086/0000] bus ops
726 11:51:53.535450 PCI: 00:1f.5 [8086/4da4] enabled
727 11:51:53.538689 PCI: Leftover static devices:
728 11:51:53.538880 PCI: 00:12.6
729 11:51:53.542387 PCI: 00:09.0
730 11:51:53.542559 PCI: 00:14.1
731 11:51:53.545569 PCI: 00:16.1
732 11:51:53.545704 PCI: 00:16.4
733 11:51:53.548935 PCI: 00:16.5
734 11:51:53.549057 PCI: 00:17.0
735 11:51:53.549129 PCI: 00:19.1
736 11:51:53.552728 PCI: 00:1e.1
737 11:51:53.552829 PCI: 00:1e.3
738 11:51:53.552945 PCI: 00:1f.1
739 11:51:53.556603 PCI: 00:1f.4
740 11:51:53.556729 PCI: 00:1f.7
741 11:51:53.560351 PCI: Check your devicetree.cb.
742 11:51:53.563913 PCI: 00:02.0 scanning...
743 11:51:53.566702 scan_generic_bus for PCI: 00:02.0
744 11:51:53.570191 scan_generic_bus for PCI: 00:02.0 done
745 11:51:53.573600 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
746 11:51:53.576855 PCI: 00:04.0 scanning...
747 11:51:53.580458 scan_generic_bus for PCI: 00:04.0
748 11:51:53.583372 GENERIC: 0.0 enabled
749 11:51:53.589906 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
750 11:51:53.593190 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
751 11:51:53.596691 PCI: 00:05.0 scanning...
752 11:51:53.600059 scan_generic_bus for PCI: 00:05.0
753 11:51:53.603100 GENERIC: 0.0 enabled
754 11:51:53.606604 bus: PCI: 00:05.0[0]->scan_generic_bus for PCI: 00:05.0 done
755 11:51:53.613240 scan_bus: bus PCI: 00:05.0 finished in 11 msecs
756 11:51:53.616279 PCI: 00:14.0 scanning...
757 11:51:53.619771 scan_static_bus for PCI: 00:14.0
758 11:51:53.619950 USB0 port 0 enabled
759 11:51:53.622789 USB0 port 0 scanning...
760 11:51:53.626157 scan_static_bus for USB0 port 0
761 11:51:53.629633 USB2 port 0 enabled
762 11:51:53.629784 USB2 port 1 enabled
763 11:51:53.632698 USB2 port 2 enabled
764 11:51:53.636038 USB2 port 3 enabled
765 11:51:53.636165 USB2 port 4 disabled
766 11:51:53.639727 USB2 port 5 enabled
767 11:51:53.639864 USB2 port 6 disabled
768 11:51:53.642644 USB2 port 7 enabled
769 11:51:53.646102 USB3 port 0 enabled
770 11:51:53.646257 USB3 port 1 enabled
771 11:51:53.649691 USB3 port 2 enabled
772 11:51:53.652479 USB3 port 3 enabled
773 11:51:53.652650 USB2 port 0 scanning...
774 11:51:53.656135 scan_static_bus for USB2 port 0
775 11:51:53.659521 scan_static_bus for USB2 port 0 done
776 11:51:53.666084 scan_bus: bus USB2 port 0 finished in 6 msecs
777 11:51:53.669263 USB2 port 1 scanning...
778 11:51:53.672392 scan_static_bus for USB2 port 1
779 11:51:53.675743 scan_static_bus for USB2 port 1 done
780 11:51:53.679152 scan_bus: bus USB2 port 1 finished in 6 msecs
781 11:51:53.682541 USB2 port 2 scanning...
782 11:51:53.685562 scan_static_bus for USB2 port 2
783 11:51:53.688981 scan_static_bus for USB2 port 2 done
784 11:51:53.692608 scan_bus: bus USB2 port 2 finished in 6 msecs
785 11:51:53.695447 USB2 port 3 scanning...
786 11:51:53.699098 scan_static_bus for USB2 port 3
787 11:51:53.701914 scan_static_bus for USB2 port 3 done
788 11:51:53.709121 scan_bus: bus USB2 port 3 finished in 6 msecs
789 11:51:53.709225 USB2 port 5 scanning...
790 11:51:53.711916 scan_static_bus for USB2 port 5
791 11:51:53.715196 scan_static_bus for USB2 port 5 done
792 11:51:53.721917 scan_bus: bus USB2 port 5 finished in 6 msecs
793 11:51:53.725486 USB2 port 7 scanning...
794 11:51:53.728765 scan_static_bus for USB2 port 7
795 11:51:53.731951 scan_static_bus for USB2 port 7 done
796 11:51:53.735406 scan_bus: bus USB2 port 7 finished in 6 msecs
797 11:51:53.738653 USB3 port 0 scanning...
798 11:51:53.741820 scan_static_bus for USB3 port 0
799 11:51:53.745256 scan_static_bus for USB3 port 0 done
800 11:51:53.748211 scan_bus: bus USB3 port 0 finished in 6 msecs
801 11:51:53.751742 USB3 port 1 scanning...
802 11:51:53.755401 scan_static_bus for USB3 port 1
803 11:51:53.758125 scan_static_bus for USB3 port 1 done
804 11:51:53.764880 scan_bus: bus USB3 port 1 finished in 6 msecs
805 11:51:53.765011 USB3 port 2 scanning...
806 11:51:53.768057 scan_static_bus for USB3 port 2
807 11:51:53.774996 scan_static_bus for USB3 port 2 done
808 11:51:53.778034 scan_bus: bus USB3 port 2 finished in 6 msecs
809 11:51:53.781170 USB3 port 3 scanning...
810 11:51:53.784865 scan_static_bus for USB3 port 3
811 11:51:53.788077 scan_static_bus for USB3 port 3 done
812 11:51:53.791541 scan_bus: bus USB3 port 3 finished in 6 msecs
813 11:51:53.794473 scan_static_bus for USB0 port 0 done
814 11:51:53.801272 scan_bus: bus USB0 port 0 finished in 172 msecs
815 11:51:53.804630 scan_static_bus for PCI: 00:14.0 done
816 11:51:53.807749 scan_bus: bus PCI: 00:14.0 finished in 188 msecs
817 11:51:53.811144 PCI: 00:14.3 scanning...
818 11:51:53.814156 scan_static_bus for PCI: 00:14.3
819 11:51:53.817700 GENERIC: 0.0 enabled
820 11:51:53.821191 scan_static_bus for PCI: 00:14.3 done
821 11:51:53.824431 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
822 11:51:53.827625 PCI: 00:15.0 scanning...
823 11:51:53.830924 scan_static_bus for PCI: 00:15.0
824 11:51:53.834019 I2C: 00:2c enabled
825 11:51:53.834141 I2C: 00:15 enabled
826 11:51:53.841080 scan_static_bus for PCI: 00:15.0 done
827 11:51:53.843942 scan_bus: bus PCI: 00:15.0 finished in 10 msecs
828 11:51:53.847392 PCI: 00:15.1 scanning...
829 11:51:53.850400 scan_static_bus for PCI: 00:15.1
830 11:51:53.853908 scan_static_bus for PCI: 00:15.1 done
831 11:51:53.857374 scan_bus: bus PCI: 00:15.1 finished in 7 msecs
832 11:51:53.860321 PCI: 00:15.2 scanning...
833 11:51:53.863905 scan_static_bus for PCI: 00:15.2
834 11:51:53.867124 GENERIC: 0.0 disabled
835 11:51:53.867243 I2C: 00:15 enabled
836 11:51:53.870599 I2C: 00:10 disabled
837 11:51:53.874004 I2C: 00:10 disabled
838 11:51:53.874127 I2C: 00:2c enabled
839 11:51:53.877109 I2C: 00:40 enabled
840 11:51:53.877221 I2C: 00:10 enabled
841 11:51:53.880348 I2C: 00:39 enabled
842 11:51:53.883875 scan_static_bus for PCI: 00:15.2 done
843 11:51:53.890346 scan_bus: bus PCI: 00:15.2 finished in 23 msecs
844 11:51:53.890468 PCI: 00:15.3 scanning...
845 11:51:53.893550 scan_static_bus for PCI: 00:15.3
846 11:51:53.896691 I2C: 00:36 enabled
847 11:51:53.900147 I2C: 00:10 disabled
848 11:51:53.900261 I2C: 00:0c enabled
849 11:51:53.903769 I2C: 00:50 enabled
850 11:51:53.907137 scan_static_bus for PCI: 00:15.3 done
851 11:51:53.910172 scan_bus: bus PCI: 00:15.3 finished in 14 msecs
852 11:51:53.913585 PCI: 00:19.0 scanning...
853 11:51:53.916636 scan_static_bus for PCI: 00:19.0
854 11:51:53.920196 I2C: 00:1a enabled
855 11:51:53.920337 I2C: 00:1a disabled
856 11:51:53.923601 I2C: 00:1a disabled
857 11:51:53.926506 I2C: 00:28 enabled
858 11:51:53.926602 I2C: 00:29 enabled
859 11:51:53.929942 scan_static_bus for PCI: 00:19.0 done
860 11:51:53.936928 scan_bus: bus PCI: 00:19.0 finished in 17 msecs
861 11:51:53.940056 PCI: 00:1e.2 scanning...
862 11:51:53.943075 scan_generic_bus for PCI: 00:1e.2
863 11:51:53.943185 SPI: 00 enabled
864 11:51:53.949986 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
865 11:51:53.953466 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
866 11:51:53.956451 PCI: 00:1f.0 scanning...
867 11:51:53.960072 scan_static_bus for PCI: 00:1f.0
868 11:51:53.962881 PNP: 0c09.0 enabled
869 11:51:53.966276 PNP: 0c09.0 scanning...
870 11:51:53.969803 scan_static_bus for PNP: 0c09.0
871 11:51:53.973346 scan_static_bus for PNP: 0c09.0 done
872 11:51:53.976150 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
873 11:51:53.979806 scan_static_bus for PCI: 00:1f.0 done
874 11:51:53.986010 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
875 11:51:53.989827 PCI: 00:1f.3 scanning...
876 11:51:53.992703 scan_static_bus for PCI: 00:1f.3
877 11:51:53.992812 GENERIC: 0.0 disabled
878 11:51:53.996401 scan_static_bus for PCI: 00:1f.3 done
879 11:51:54.002793 scan_bus: bus PCI: 00:1f.3 finished in 9 msecs
880 11:51:54.005674 PCI: 00:1f.5 scanning...
881 11:51:54.009655 scan_generic_bus for PCI: 00:1f.5
882 11:51:54.012433 scan_generic_bus for PCI: 00:1f.5 done
883 11:51:54.016000 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
884 11:51:54.022545 scan_bus: bus DOMAIN: 0000 finished in 645 msecs
885 11:51:54.025983 scan_static_bus for Root Device done
886 11:51:54.029063 scan_bus: bus Root Device finished in 664 msecs
887 11:51:54.031970 done
888 11:51:54.035573 BS: BS_DEV_ENUMERATE run times (exec / console): 7 / 1083 ms
889 11:51:54.038938 Chrome EC: UHEPI supported
890 11:51:54.045476 FMAP: area UNIFIED_MRC_CACHE found @ bca000 (196608 bytes)
891 11:51:54.052153 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
892 11:51:54.055477 SPI flash protection: WPSW=0 SRP0=1
893 11:51:54.062033 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
894 11:51:54.065017 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
895 11:51:54.068432 found VGA at PCI: 00:02.0
896 11:51:54.071959 Setting up VGA for PCI: 00:02.0
897 11:51:54.078478 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
898 11:51:54.082004 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
899 11:51:54.085381 Allocating resources...
900 11:51:54.088775 Reading resources...
901 11:51:54.092098 Root Device read_resources bus 0 link: 0
902 11:51:54.095206 CPU_CLUSTER: 0 read_resources bus 0 link: 0
903 11:51:54.101447 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
904 11:51:54.104647 DOMAIN: 0000 read_resources bus 0 link: 0
905 11:51:54.111654 PCI: 00:04.0 read_resources bus 1 link: 0
906 11:51:54.114795 PCI: 00:04.0 read_resources bus 1 link: 0 done
907 11:51:54.121227 PCI: 00:05.0 read_resources bus 2 link: 0
908 11:51:54.124678 PCI: 00:05.0 read_resources bus 2 link: 0 done
909 11:51:54.127620 PCI: 00:14.0 read_resources bus 0 link: 0
910 11:51:54.135300 USB0 port 0 read_resources bus 0 link: 0
911 11:51:54.138876 USB0 port 0 read_resources bus 0 link: 0 done
912 11:51:54.145298 PCI: 00:14.0 read_resources bus 0 link: 0 done
913 11:51:54.201391 PCI: 00:14.3 read_resources bus 0 link: 0
914 11:51:54.201747 PCI: 00:14.3 read_resources bus 0 link: 0 done
915 11:51:54.201832 PCI: 00:15.0 read_resources bus 0 link: 0
916 11:51:54.201899 PCI: 00:15.0 read_resources bus 0 link: 0 done
917 11:51:54.201964 PCI: 00:15.2 read_resources bus 0 link: 0
918 11:51:54.202034 PCI: 00:15.2 read_resources bus 0 link: 0 done
919 11:51:54.202416 PCI: 00:15.3 read_resources bus 0 link: 0
920 11:51:54.202679 PCI: 00:15.3 read_resources bus 0 link: 0 done
921 11:51:54.202822 PCI: 00:19.0 read_resources bus 0 link: 0
922 11:51:54.202930 PCI: 00:19.0 read_resources bus 0 link: 0 done
923 11:51:54.203042 PCI: 00:1e.2 read_resources bus 3 link: 0
924 11:51:54.206198 PCI: 00:1e.2 read_resources bus 3 link: 0 done
925 11:51:54.209528 PCI: 00:1f.0 read_resources bus 0 link: 0
926 11:51:54.212723 PCI: 00:1f.0 read_resources bus 0 link: 0 done
927 11:51:54.219439 PCI: 00:1f.3 read_resources bus 0 link: 0
928 11:51:54.222617 PCI: 00:1f.3 read_resources bus 0 link: 0 done
929 11:51:54.229359 DOMAIN: 0000 read_resources bus 0 link: 0 done
930 11:51:54.232413 Root Device read_resources bus 0 link: 0 done
931 11:51:54.235926 Done reading resources.
932 11:51:54.242418 Show resources in subtree (Root Device)...After reading.
933 11:51:54.246000 Root Device child on link 0 CPU_CLUSTER: 0
934 11:51:54.249337 CPU_CLUSTER: 0 child on link 0 APIC: 00
935 11:51:54.252711 APIC: 00
936 11:51:54.252791 APIC: 02
937 11:51:54.256005 DOMAIN: 0000 child on link 0 PCI: 00:00.0
938 11:51:54.265683 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
939 11:51:54.275685 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
940 11:51:54.279246 PCI: 00:00.0
941 11:51:54.288898 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
942 11:51:54.295308 PCI: 00:00.0 resource base fea80000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
943 11:51:54.305595 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
944 11:51:54.315094 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
945 11:51:54.325187 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
946 11:51:54.334717 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
947 11:51:54.341281 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
948 11:51:54.351163 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
949 11:51:54.361286 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
950 11:51:54.371221 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
951 11:51:54.381205 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
952 11:51:54.390932 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
953 11:51:54.397490 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
954 11:51:54.407286 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
955 11:51:54.417639 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
956 11:51:54.427155 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
957 11:51:54.437482 PCI: 00:00.0 resource base 100000000 size 80400000 align 0 gran 0 limit 0 flags e0004200 index 10
958 11:51:54.447304 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
959 11:51:54.453747 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
960 11:51:54.456728 PCI: 00:02.0
961 11:51:54.467070 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
962 11:51:54.476851 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
963 11:51:54.486751 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
964 11:51:54.489828 PCI: 00:04.0 child on link 0 GENERIC: 0.0
965 11:51:54.499969 PCI: 00:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
966 11:51:54.502907 GENERIC: 0.0
967 11:51:54.506455 PCI: 00:05.0 child on link 0 GENERIC: 0.0
968 11:51:54.516574 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
969 11:51:54.519455 GENERIC: 0.0
970 11:51:54.519555 PCI: 00:08.0
971 11:51:54.529259 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
972 11:51:54.532673 PCI: 00:14.0 child on link 0 USB0 port 0
973 11:51:54.542476 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
974 11:51:54.549430 USB0 port 0 child on link 0 USB2 port 0
975 11:51:54.549558 USB2 port 0
976 11:51:54.552446 USB2 port 1
977 11:51:54.552607 USB2 port 2
978 11:51:54.555853 USB2 port 3
979 11:51:54.555947 USB2 port 4
980 11:51:54.559492 USB2 port 5
981 11:51:54.559583 USB2 port 6
982 11:51:54.562438 USB2 port 7
983 11:51:54.562528 USB3 port 0
984 11:51:54.565942 USB3 port 1
985 11:51:54.569330 USB3 port 2
986 11:51:54.569422 USB3 port 3
987 11:51:54.572212 PCI: 00:14.2
988 11:51:54.575618 PCI: 00:14.3 child on link 0 GENERIC: 0.0
989 11:51:54.585432 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
990 11:51:54.585547 GENERIC: 0.0
991 11:51:54.588938 PCI: 00:14.5
992 11:51:54.599220 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
993 11:51:54.602008 PCI: 00:15.0 child on link 0 I2C: 00:2c
994 11:51:54.611918 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
995 11:51:54.615299 I2C: 00:2c
996 11:51:54.615464 I2C: 00:15
997 11:51:54.618768 PCI: 00:15.1
998 11:51:54.628497 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
999 11:51:54.631881 PCI: 00:15.2 child on link 0 GENERIC: 0.0
1000 11:51:54.641661 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1001 11:51:54.644865 GENERIC: 0.0
1002 11:51:54.645009 I2C: 00:15
1003 11:51:54.645106 I2C: 00:10
1004 11:51:54.648679 I2C: 00:10
1005 11:51:54.648777 I2C: 00:2c
1006 11:51:54.651690 I2C: 00:40
1007 11:51:54.651777 I2C: 00:10
1008 11:51:54.655110 I2C: 00:39
1009 11:51:54.658112 PCI: 00:15.3 child on link 0 I2C: 00:36
1010 11:51:54.668134 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1011 11:51:54.671661 I2C: 00:36
1012 11:51:54.671778 I2C: 00:10
1013 11:51:54.675041 I2C: 00:0c
1014 11:51:54.675152 I2C: 00:50
1015 11:51:54.678309 PCI: 00:16.0
1016 11:51:54.688123 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1017 11:51:54.691317 PCI: 00:19.0 child on link 0 I2C: 00:1a
1018 11:51:54.701294 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1019 11:51:54.701451 I2C: 00:1a
1020 11:51:54.704718 I2C: 00:1a
1021 11:51:54.704831 I2C: 00:1a
1022 11:51:54.708221 I2C: 00:28
1023 11:51:54.708350 I2C: 00:29
1024 11:51:54.711192 PCI: 00:19.2
1025 11:51:54.721076 PCI: 00:19.2 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1026 11:51:54.730711 PCI: 00:19.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1027 11:51:54.734136 PCI: 00:1a.0
1028 11:51:54.744031 PCI: 00:1a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1029 11:51:54.744164 PCI: 00:1e.0
1030 11:51:54.747422 PCI: 00:1e.2 child on link 0 SPI: 00
1031 11:51:54.756983 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1032 11:51:54.760746 SPI: 00
1033 11:51:54.763850 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1034 11:51:54.773412 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1035 11:51:54.773573 PNP: 0c09.0
1036 11:51:54.783831 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1037 11:51:54.783958 PCI: 00:1f.2
1038 11:51:54.793468 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1039 11:51:54.803310 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 1901 flags c0000100 index 1
1040 11:51:54.806628 PCI: 00:1f.3 child on link 0 GENERIC: 0.0
1041 11:51:54.817636 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1042 11:51:54.827867 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1043 11:51:54.827993 GENERIC: 0.0
1044 11:51:54.830761 PCI: 00:1f.5
1045 11:51:54.841040 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1046 11:51:54.847325 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1047 11:51:54.853776 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1048 11:51:54.860591 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1049 11:51:54.867013 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1050 11:51:54.876863 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1051 11:51:54.883771 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1052 11:51:54.887134 DOMAIN: 0000: Resource ranges:
1053 11:51:54.890140 * Base: 1000, Size: 800, Tag: 100
1054 11:51:54.893641 * Base: 1900, Size: e700, Tag: 100
1055 11:51:54.900398 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1056 11:51:54.906609 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1057 11:51:54.913170 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1058 11:51:54.919732 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1059 11:51:54.926451 update_constraints: PCI: 00:00.0 01 base fea80000 limit fea87fff mem (fixed)
1060 11:51:54.936761 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1061 11:51:54.943123 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1062 11:51:54.949459 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1063 11:51:54.959918 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1064 11:51:54.966056 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1065 11:51:54.972710 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1066 11:51:54.982634 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1067 11:51:54.989181 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1068 11:51:54.995510 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1069 11:51:55.005988 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1070 11:51:55.012245 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1071 11:51:55.018868 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1072 11:51:55.028645 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1073 11:51:55.035246 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1074 11:51:55.041814 update_constraints: PCI: 00:00.0 10 base 100000000 limit 1803fffff mem (fixed)
1075 11:51:55.052008 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1076 11:51:55.058287 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1077 11:51:55.064725 update_constraints: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
1078 11:51:55.075217 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1079 11:51:55.077945 DOMAIN: 0000: Resource ranges:
1080 11:51:55.081350 * Base: 7fc00000, Size: 40400000, Tag: 200
1081 11:51:55.084641 * Base: d0000000, Size: 2b000000, Tag: 200
1082 11:51:55.088562 * Base: fb001000, Size: 2fff000, Tag: 200
1083 11:51:55.094604 * Base: fe010000, Size: 22000, Tag: 200
1084 11:51:55.097731 * Base: fe033000, Size: a4d000, Tag: 200
1085 11:51:55.101303 * Base: fea88000, Size: 2f8000, Tag: 200
1086 11:51:55.104689 * Base: fed88000, Size: 8000, Tag: 200
1087 11:51:55.111149 * Base: fed93000, Size: d000, Tag: 200
1088 11:51:55.114674 * Base: feda2000, Size: 125e000, Tag: 200
1089 11:51:55.118024 * Base: 180400000, Size: 7e7fc00000, Tag: 100200
1090 11:51:55.127821 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1091 11:51:55.134357 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1092 11:51:55.141015 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1093 11:51:55.147796 PCI: 00:1f.3 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1094 11:51:55.154344 PCI: 00:04.0 10 * [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem
1095 11:51:55.160607 PCI: 00:14.0 10 * [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem
1096 11:51:55.167360 PCI: 00:14.3 10 * [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem
1097 11:51:55.173963 PCI: 00:1f.3 10 * [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem
1098 11:51:55.180292 PCI: 00:08.0 10 * [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem
1099 11:51:55.187264 PCI: 00:14.5 10 * [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem
1100 11:51:55.193750 PCI: 00:15.0 10 * [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem
1101 11:51:55.199989 PCI: 00:15.1 10 * [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem
1102 11:51:55.206740 PCI: 00:15.2 10 * [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem
1103 11:51:55.213646 PCI: 00:15.3 10 * [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem
1104 11:51:55.220071 PCI: 00:16.0 10 * [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem
1105 11:51:55.226828 PCI: 00:19.0 10 * [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem
1106 11:51:55.232951 PCI: 00:19.2 18 * [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem
1107 11:51:55.239737 PCI: 00:1a.0 10 * [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem
1108 11:51:55.246139 PCI: 00:1e.2 10 * [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem
1109 11:51:55.252960 PCI: 00:1f.5 10 * [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem
1110 11:51:55.260005 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1111 11:51:55.266320 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1112 11:51:55.269360 Root Device assign_resources, bus 0 link: 0
1113 11:51:55.276440 DOMAIN: 0000 assign_resources, bus 0 link: 0
1114 11:51:55.282814 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1115 11:51:55.292379 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1116 11:51:55.299140 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1117 11:51:55.308768 PCI: 00:04.0 10 <- [0x007fd00000 - 0x007fd0ffff] size 0x00010000 gran 0x10 mem64
1118 11:51:55.312435 PCI: 00:04.0 assign_resources, bus 1 link: 0
1119 11:51:55.315529 PCI: 00:04.0 assign_resources, bus 1 link: 0
1120 11:51:55.325736 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1121 11:51:55.328929 PCI: 00:05.0 assign_resources, bus 2 link: 0
1122 11:51:55.335631 PCI: 00:05.0 assign_resources, bus 2 link: 0
1123 11:51:55.342263 PCI: 00:08.0 10 <- [0x007fd28000 - 0x007fd28fff] size 0x00001000 gran 0x0c mem64
1124 11:51:55.348945 PCI: 00:14.0 10 <- [0x007fd10000 - 0x007fd1ffff] size 0x00010000 gran 0x10 mem64
1125 11:51:55.355565 PCI: 00:14.0 assign_resources, bus 0 link: 0
1126 11:51:55.358515 PCI: 00:14.0 assign_resources, bus 0 link: 0
1127 11:51:55.368702 PCI: 00:14.3 10 <- [0x007fd20000 - 0x007fd23fff] size 0x00004000 gran 0x0e mem64
1128 11:51:55.372111 PCI: 00:14.3 assign_resources, bus 0 link: 0
1129 11:51:55.375039 PCI: 00:14.3 assign_resources, bus 0 link: 0
1130 11:51:55.385071 PCI: 00:14.5 10 <- [0x007fd29000 - 0x007fd29fff] size 0x00001000 gran 0x0c mem64
1131 11:51:55.392058 PCI: 00:15.0 10 <- [0x007fd2a000 - 0x007fd2afff] size 0x00001000 gran 0x0c mem64
1132 11:51:55.398633 PCI: 00:15.0 assign_resources, bus 0 link: 0
1133 11:51:55.402129 PCI: 00:15.0 assign_resources, bus 0 link: 0
1134 11:51:55.408657 PCI: 00:15.1 10 <- [0x007fd2b000 - 0x007fd2bfff] size 0x00001000 gran 0x0c mem64
1135 11:51:55.418630 PCI: 00:15.2 10 <- [0x007fd2c000 - 0x007fd2cfff] size 0x00001000 gran 0x0c mem64
1136 11:51:55.421684 PCI: 00:15.2 assign_resources, bus 0 link: 0
1137 11:51:55.428323 PCI: 00:15.2 assign_resources, bus 0 link: 0
1138 11:51:55.435204 PCI: 00:15.3 10 <- [0x007fd2d000 - 0x007fd2dfff] size 0x00001000 gran 0x0c mem64
1139 11:51:55.438668 PCI: 00:15.3 assign_resources, bus 0 link: 0
1140 11:51:55.445223 PCI: 00:15.3 assign_resources, bus 0 link: 0
1141 11:51:55.451441 PCI: 00:16.0 10 <- [0x007fd2e000 - 0x007fd2efff] size 0x00001000 gran 0x0c mem64
1142 11:51:55.461396 PCI: 00:19.0 10 <- [0x007fd2f000 - 0x007fd2ffff] size 0x00001000 gran 0x0c mem64
1143 11:51:55.465049 PCI: 00:19.0 assign_resources, bus 0 link: 0
1144 11:51:55.471288 PCI: 00:19.0 assign_resources, bus 0 link: 0
1145 11:51:55.478046 PCI: 00:19.2 18 <- [0x007fd30000 - 0x007fd30fff] size 0x00001000 gran 0x0c mem64
1146 11:51:55.484616 PCI: 00:1a.0 10 <- [0x007fd31000 - 0x007fd31fff] size 0x00001000 gran 0x0c mem64
1147 11:51:55.494478 PCI: 00:1e.2 10 <- [0x007fd32000 - 0x007fd32fff] size 0x00001000 gran 0x0c mem64
1148 11:51:55.497958 PCI: 00:1e.2 assign_resources, bus 3 link: 0
1149 11:51:55.504939 PCI: 00:1e.2 assign_resources, bus 3 link: 0
1150 11:51:55.507828 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1151 11:51:55.514822 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1152 11:51:55.517959 LPC: Trying to open IO window from 800 size 1ff
1153 11:51:55.527682 PCI: 00:1f.3 10 <- [0x007fd24000 - 0x007fd27fff] size 0x00004000 gran 0x0e mem64
1154 11:51:55.534335 PCI: 00:1f.3 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 mem64
1155 11:51:55.537284 PCI: 00:1f.3 assign_resources, bus 0 link: 0
1156 11:51:55.544037 PCI: 00:1f.3 assign_resources, bus 0 link: 0
1157 11:51:55.550748 PCI: 00:1f.5 10 <- [0x007fd33000 - 0x007fd33fff] size 0x00001000 gran 0x0c mem
1158 11:51:55.557016 DOMAIN: 0000 assign_resources, bus 0 link: 0
1159 11:51:55.560778 Root Device assign_resources, bus 0 link: 0
1160 11:51:55.563974 Done setting resources.
1161 11:51:55.570701 Show resources in subtree (Root Device)...After assigning values.
1162 11:51:55.573696 Root Device child on link 0 CPU_CLUSTER: 0
1163 11:51:55.577148 CPU_CLUSTER: 0 child on link 0 APIC: 00
1164 11:51:55.580607 APIC: 00
1165 11:51:55.580736 APIC: 02
1166 11:51:55.583469 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1167 11:51:55.593344 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1168 11:51:55.603428 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1169 11:51:55.606919 PCI: 00:00.0
1170 11:51:55.613345 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1171 11:51:55.623384 PCI: 00:00.0 resource base fea80000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1172 11:51:55.633489 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1173 11:51:55.643006 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1174 11:51:55.653067 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1175 11:51:55.662950 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1176 11:51:55.669632 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1177 11:51:55.679329 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1178 11:51:55.689176 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1179 11:51:55.699005 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1180 11:51:55.708908 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1181 11:51:55.718701 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1182 11:51:55.725461 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1183 11:51:55.735854 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1184 11:51:55.745645 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1185 11:51:55.754965 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1186 11:51:55.765382 PCI: 00:00.0 resource base 100000000 size 80400000 align 0 gran 0 limit 0 flags e0004200 index 10
1187 11:51:55.775038 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1188 11:51:55.781468 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1189 11:51:55.784754 PCI: 00:02.0
1190 11:51:55.794890 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1191 11:51:55.804635 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1192 11:51:55.814644 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1193 11:51:55.817999 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1194 11:51:55.830909 PCI: 00:04.0 resource base 7fd00000 size 10000 align 16 gran 16 limit 7fd0ffff flags 60000201 index 10
1195 11:51:55.831088 GENERIC: 0.0
1196 11:51:55.834382 PCI: 00:05.0 child on link 0 GENERIC: 0.0
1197 11:51:55.847986 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1198 11:51:55.848164 GENERIC: 0.0
1199 11:51:55.851020 PCI: 00:08.0
1200 11:51:55.861024 PCI: 00:08.0 resource base 7fd28000 size 1000 align 12 gran 12 limit 7fd28fff flags 60000201 index 10
1201 11:51:55.863898 PCI: 00:14.0 child on link 0 USB0 port 0
1202 11:51:55.874046 PCI: 00:14.0 resource base 7fd10000 size 10000 align 16 gran 16 limit 7fd1ffff flags 60000201 index 10
1203 11:51:55.880253 USB0 port 0 child on link 0 USB2 port 0
1204 11:51:55.880383 USB2 port 0
1205 11:51:55.883999 USB2 port 1
1206 11:51:55.884112 USB2 port 2
1207 11:51:55.887258 USB2 port 3
1208 11:51:55.887373 USB2 port 4
1209 11:51:55.890668 USB2 port 5
1210 11:51:55.890797 USB2 port 6
1211 11:51:55.894197 USB2 port 7
1212 11:51:55.894300 USB3 port 0
1213 11:51:55.896990 USB3 port 1
1214 11:51:55.897095 USB3 port 2
1215 11:51:55.900530 USB3 port 3
1216 11:51:55.900646 PCI: 00:14.2
1217 11:51:55.906926 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1218 11:51:55.917468 PCI: 00:14.3 resource base 7fd20000 size 4000 align 14 gran 14 limit 7fd23fff flags 60000201 index 10
1219 11:51:55.917692 GENERIC: 0.0
1220 11:51:55.920262 PCI: 00:14.5
1221 11:51:55.930141 PCI: 00:14.5 resource base 7fd29000 size 1000 align 12 gran 12 limit 7fd29fff flags 60000201 index 10
1222 11:51:55.933687 PCI: 00:15.0 child on link 0 I2C: 00:2c
1223 11:51:55.943915 PCI: 00:15.0 resource base 7fd2a000 size 1000 align 12 gran 12 limit 7fd2afff flags 60000201 index 10
1224 11:51:55.946454 I2C: 00:2c
1225 11:51:55.946579 I2C: 00:15
1226 11:51:55.949721 PCI: 00:15.1
1227 11:51:55.959664 PCI: 00:15.1 resource base 7fd2b000 size 1000 align 12 gran 12 limit 7fd2bfff flags 60000201 index 10
1228 11:51:55.963161 PCI: 00:15.2 child on link 0 GENERIC: 0.0
1229 11:51:55.976068 PCI: 00:15.2 resource base 7fd2c000 size 1000 align 12 gran 12 limit 7fd2cfff flags 60000201 index 10
1230 11:51:55.976238 GENERIC: 0.0
1231 11:51:55.979216 I2C: 00:15
1232 11:51:55.979333 I2C: 00:10
1233 11:51:55.979424 I2C: 00:10
1234 11:51:55.982717 I2C: 00:2c
1235 11:51:55.982837 I2C: 00:40
1236 11:51:55.986086 I2C: 00:10
1237 11:51:55.986200 I2C: 00:39
1238 11:51:55.992499 PCI: 00:15.3 child on link 0 I2C: 00:36
1239 11:51:56.002625 PCI: 00:15.3 resource base 7fd2d000 size 1000 align 12 gran 12 limit 7fd2dfff flags 60000201 index 10
1240 11:51:56.002795 I2C: 00:36
1241 11:51:56.005633 I2C: 00:10
1242 11:51:56.005747 I2C: 00:0c
1243 11:51:56.008950 I2C: 00:50
1244 11:51:56.009070 PCI: 00:16.0
1245 11:51:56.018883 PCI: 00:16.0 resource base 7fd2e000 size 1000 align 12 gran 12 limit 7fd2efff flags 60000201 index 10
1246 11:51:56.025299 PCI: 00:19.0 child on link 0 I2C: 00:1a
1247 11:51:56.035655 PCI: 00:19.0 resource base 7fd2f000 size 1000 align 12 gran 12 limit 7fd2ffff flags 60000201 index 10
1248 11:51:56.035829 I2C: 00:1a
1249 11:51:56.038540 I2C: 00:1a
1250 11:51:56.038657 I2C: 00:1a
1251 11:51:56.041900 I2C: 00:28
1252 11:51:56.042018 I2C: 00:29
1253 11:51:56.045235 PCI: 00:19.2
1254 11:51:56.055063 PCI: 00:19.2 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1255 11:51:56.064943 PCI: 00:19.2 resource base 7fd30000 size 1000 align 12 gran 12 limit 7fd30fff flags 60000201 index 18
1256 11:51:56.068125 PCI: 00:1a.0
1257 11:51:56.078690 PCI: 00:1a.0 resource base 7fd31000 size 1000 align 12 gran 12 limit 7fd31fff flags 60000201 index 10
1258 11:51:56.078866 PCI: 00:1e.0
1259 11:51:56.081282 PCI: 00:1e.2 child on link 0 SPI: 00
1260 11:51:56.094741 PCI: 00:1e.2 resource base 7fd32000 size 1000 align 12 gran 12 limit 7fd32fff flags 60000201 index 10
1261 11:51:56.094997 SPI: 00
1262 11:51:56.097967 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1263 11:51:56.107611 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1264 11:51:56.107766 PNP: 0c09.0
1265 11:51:56.117744 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1266 11:51:56.121077 PCI: 00:1f.2
1267 11:51:56.127459 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1268 11:51:56.137312 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 1901 flags c0000100 index 1
1269 11:51:56.144378 PCI: 00:1f.3 child on link 0 GENERIC: 0.0
1270 11:51:56.153973 PCI: 00:1f.3 resource base 7fd24000 size 4000 align 14 gran 14 limit 7fd27fff flags 60000201 index 10
1271 11:51:56.163739 PCI: 00:1f.3 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60000201 index 20
1272 11:51:56.163985 GENERIC: 0.0
1273 11:51:56.167022 PCI: 00:1f.5
1274 11:51:56.177112 PCI: 00:1f.5 resource base 7fd33000 size 1000 align 12 gran 12 limit 7fd33fff flags 60000200 index 10
1275 11:51:56.180478 Done allocating resources.
1276 11:51:56.186988 BS: BS_DEV_RESOURCES run times (exec / console): 21 / 2093 ms
1277 11:51:56.187203 Enabling resources...
1278 11:51:56.194041 PCI: 00:00.0 subsystem <- 8086/4e22
1279 11:51:56.194197 PCI: 00:00.0 cmd <- 06
1280 11:51:56.197448 PCI: 00:02.0 subsystem <- 8086/4e55
1281 11:51:56.200675 PCI: 00:02.0 cmd <- 03
1282 11:51:56.204038 PCI: 00:04.0 subsystem <- 8086/4e03
1283 11:51:56.207525 PCI: 00:04.0 cmd <- 02
1284 11:51:56.210806 PCI: 00:05.0 bridge ctrl <- 0003
1285 11:51:56.213746 PCI: 00:05.0 subsystem <- 8086/4e19
1286 11:51:56.217084 PCI: 00:05.0 cmd <- 02
1287 11:51:56.220390 PCI: 00:08.0 cmd <- 06
1288 11:51:56.223998 PCI: 00:14.0 subsystem <- 8086/4ded
1289 11:51:56.224154 PCI: 00:14.0 cmd <- 02
1290 11:51:56.230379 PCI: 00:14.3 subsystem <- 8086/4df0
1291 11:51:56.230557 PCI: 00:14.3 cmd <- 02
1292 11:51:56.233905 PCI: 00:14.5 subsystem <- 8086/4df8
1293 11:51:56.236924 PCI: 00:14.5 cmd <- 06
1294 11:51:56.240191 PCI: 00:15.0 subsystem <- 8086/4de8
1295 11:51:56.243610 PCI: 00:15.0 cmd <- 02
1296 11:51:56.246674 PCI: 00:15.1 subsystem <- 8086/4de9
1297 11:51:56.250149 PCI: 00:15.1 cmd <- 02
1298 11:51:56.253417 PCI: 00:15.2 subsystem <- 8086/4dea
1299 11:51:56.257012 PCI: 00:15.2 cmd <- 02
1300 11:51:56.259840 PCI: 00:15.3 subsystem <- 8086/4deb
1301 11:51:56.263446 PCI: 00:15.3 cmd <- 02
1302 11:51:56.266727 PCI: 00:16.0 subsystem <- 8086/4de0
1303 11:51:56.266839 PCI: 00:16.0 cmd <- 02
1304 11:51:56.273229 PCI: 00:19.0 subsystem <- 8086/4dc5
1305 11:51:56.273337 PCI: 00:19.0 cmd <- 02
1306 11:51:56.276997 PCI: 00:19.2 subsystem <- 8086/4dc7
1307 11:51:56.279874 PCI: 00:19.2 cmd <- 06
1308 11:51:56.283425 PCI: 00:1a.0 subsystem <- 8086/4dc4
1309 11:51:56.286292 PCI: 00:1a.0 cmd <- 06
1310 11:51:56.289563 PCI: 00:1e.2 subsystem <- 8086/4daa
1311 11:51:56.292957 PCI: 00:1e.2 cmd <- 06
1312 11:51:56.296136 PCI: 00:1f.0 subsystem <- 8086/4d87
1313 11:51:56.299563 PCI: 00:1f.0 cmd <- 407
1314 11:51:56.302938 PCI: 00:1f.3 subsystem <- 8086/4dc8
1315 11:51:56.306217 PCI: 00:1f.3 cmd <- 02
1316 11:51:56.309514 PCI: 00:1f.5 subsystem <- 8086/4da4
1317 11:51:56.309636 PCI: 00:1f.5 cmd <- 406
1318 11:51:56.315394 done.
1319 11:51:56.318310 BS: BS_DEV_ENABLE run times (exec / console): 7 / 121 ms
1320 11:51:56.321827 Initializing devices...
1321 11:51:56.325156 Root Device init
1322 11:51:56.325280 mainboard: EC init
1323 11:51:56.331680 Chrome EC: Set SMI mask to 0x0000000000000000
1324 11:51:56.338046 Chrome EC: clear events_b mask to 0x0000000000000000
1325 11:51:56.341601 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1326 11:51:56.348333 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
1327 11:51:56.354885 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001000101e
1328 11:51:56.358132 Chrome EC: Set WAKE mask to 0x0000000000000000
1329 11:51:56.364524 Root Device init finished in 35 msecs
1330 11:51:56.364660 PCI: 00:00.0 init
1331 11:51:56.368745 CPU TDP = 6 Watts
1332 11:51:56.372071 CPU PL1 = 7 Watts
1333 11:51:56.372192 CPU PL2 = 12 Watts
1334 11:51:56.375859 PCI: 00:00.0 init finished in 6 msecs
1335 11:51:56.379193 PCI: 00:02.0 init
1336 11:51:56.382343 GMA: Found VBT in CBFS
1337 11:51:56.385838 GMA: Found valid VBT in CBFS
1338 11:51:56.388619 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1339 11:51:56.398916 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1340 11:51:56.402296 PCI: 00:02.0 init finished in 18 msecs
1341 11:51:56.405498 PCI: 00:08.0 init
1342 11:51:56.409009 PCI: 00:08.0 init finished in 0 msecs
1343 11:51:56.409130 PCI: 00:14.0 init
1344 11:51:56.415040 XHCI: Updated LFPS sampling OFF time to 9 ms
1345 11:51:56.418705 PCI: 00:14.0 init finished in 4 msecs
1346 11:51:56.422031 PCI: 00:15.0 init
1347 11:51:56.425117 I2C bus 0 version 0x3230302a
1348 11:51:56.428783 DW I2C bus 0 at 0x7fd2a000 (400 KHz)
1349 11:51:56.431673 PCI: 00:15.0 init finished in 6 msecs
1350 11:51:56.431789 PCI: 00:15.1 init
1351 11:51:56.435088 I2C bus 1 version 0x3230302a
1352 11:51:56.438619 DW I2C bus 1 at 0x7fd2b000 (400 KHz)
1353 11:51:56.445063 PCI: 00:15.1 init finished in 6 msecs
1354 11:51:56.445200 PCI: 00:15.2 init
1355 11:51:56.448139 I2C bus 2 version 0x3230302a
1356 11:51:56.451547 DW I2C bus 2 at 0x7fd2c000 (400 KHz)
1357 11:51:56.455069 PCI: 00:15.2 init finished in 6 msecs
1358 11:51:56.458526 PCI: 00:15.3 init
1359 11:51:56.461915 I2C bus 3 version 0x3230302a
1360 11:51:56.465281 DW I2C bus 3 at 0x7fd2d000 (400 KHz)
1361 11:51:56.468132 PCI: 00:15.3 init finished in 6 msecs
1362 11:51:56.471673 PCI: 00:16.0 init
1363 11:51:56.475243 PCI: 00:16.0 init finished in 0 msecs
1364 11:51:56.478120 PCI: 00:19.0 init
1365 11:51:56.478245 I2C bus 4 version 0x3230302a
1366 11:51:56.484639 DW I2C bus 4 at 0x7fd2f000 (400 KHz)
1367 11:51:56.488427 PCI: 00:19.0 init finished in 6 msecs
1368 11:51:56.488559 PCI: 00:1a.0 init
1369 11:51:56.494623 PCI: 00:1a.0 init finished in 0 msecs
1370 11:51:56.494791 PCI: 00:1f.0 init
1371 11:51:56.501476 IOAPIC: Initializing IOAPIC at 0xfec00000
1372 11:51:56.504918 IOAPIC: Bootstrap Processor Local APIC = 0x00
1373 11:51:56.507736 IOAPIC: ID = 0x02
1374 11:51:56.507862 IOAPIC: Dumping registers
1375 11:51:56.511422 reg 0x0000: 0x02000000
1376 11:51:56.514705 reg 0x0001: 0x00770020
1377 11:51:56.517949 reg 0x0002: 0x00000000
1378 11:51:56.521349 PCI: 00:1f.0 init finished in 21 msecs
1379 11:51:56.521472 PCI: 00:1f.2 init
1380 11:51:56.524580 Disabling ACPI via APMC.
1381 11:51:56.529522 APMC done.
1382 11:51:56.532764 PCI: 00:1f.2 init finished in 6 msecs
1383 11:51:56.543927 PNP: 0c09.0 init
1384 11:51:56.546703 Google Chrome EC uptime: 6.534 seconds
1385 11:51:56.553529 Google Chrome AP resets since EC boot: 0
1386 11:51:56.557130 Google Chrome most recent AP reset causes:
1387 11:51:56.563437 Google Chrome EC reset flags at last EC boot: reset-pin
1388 11:51:56.566836 PNP: 0c09.0 init finished in 18 msecs
1389 11:51:56.566969 Devices initialized
1390 11:51:56.570125 Show all devs... After init.
1391 11:51:56.573708 Root Device: enabled 1
1392 11:51:56.576611 CPU_CLUSTER: 0: enabled 1
1393 11:51:56.580113 DOMAIN: 0000: enabled 1
1394 11:51:56.580245 PCI: 00:00.0: enabled 1
1395 11:51:56.583181 PCI: 00:02.0: enabled 1
1396 11:51:56.586526 PCI: 00:04.0: enabled 1
1397 11:51:56.586655 PCI: 00:05.0: enabled 1
1398 11:51:56.589805 PCI: 00:09.0: enabled 0
1399 11:51:56.593145 PCI: 00:12.6: enabled 0
1400 11:51:56.596612 PCI: 00:14.0: enabled 1
1401 11:51:56.596734 PCI: 00:14.1: enabled 0
1402 11:51:56.599603 PCI: 00:14.2: enabled 0
1403 11:51:56.603082 PCI: 00:14.3: enabled 1
1404 11:51:56.606508 PCI: 00:14.5: enabled 1
1405 11:51:56.606639 PCI: 00:15.0: enabled 1
1406 11:51:56.609980 PCI: 00:15.1: enabled 1
1407 11:51:56.612713 PCI: 00:15.2: enabled 1
1408 11:51:56.616119 PCI: 00:15.3: enabled 1
1409 11:51:56.616241 PCI: 00:16.0: enabled 1
1410 11:51:56.619364 PCI: 00:16.1: enabled 0
1411 11:51:56.622878 PCI: 00:16.4: enabled 0
1412 11:51:56.626240 PCI: 00:16.5: enabled 0
1413 11:51:56.626357 PCI: 00:17.0: enabled 0
1414 11:51:56.629247 PCI: 00:19.0: enabled 1
1415 11:51:56.633156 PCI: 00:19.1: enabled 0
1416 11:51:56.633269 PCI: 00:19.2: enabled 1
1417 11:51:56.635860 PCI: 00:1a.0: enabled 1
1418 11:51:56.639260 PCI: 00:1c.0: enabled 0
1419 11:51:56.642748 PCI: 00:1c.1: enabled 0
1420 11:51:56.642867 PCI: 00:1c.2: enabled 0
1421 11:51:56.646252 PCI: 00:1c.3: enabled 0
1422 11:51:56.649222 PCI: 00:1c.4: enabled 0
1423 11:51:56.652839 PCI: 00:1c.5: enabled 0
1424 11:51:56.652958 PCI: 00:1c.6: enabled 0
1425 11:51:56.655685 PCI: 00:1c.7: enabled 1
1426 11:51:56.659111 PCI: 00:1e.0: enabled 0
1427 11:51:56.662525 PCI: 00:1e.1: enabled 0
1428 11:51:56.662642 PCI: 00:1e.2: enabled 1
1429 11:51:56.665620 PCI: 00:1e.3: enabled 0
1430 11:51:56.669087 PCI: 00:1f.0: enabled 1
1431 11:51:56.669206 PCI: 00:1f.1: enabled 0
1432 11:51:56.672306 PCI: 00:1f.2: enabled 1
1433 11:51:56.675689 PCI: 00:1f.3: enabled 1
1434 11:51:56.679241 PCI: 00:1f.4: enabled 0
1435 11:51:56.679366 PCI: 00:1f.5: enabled 1
1436 11:51:56.682284 PCI: 00:1f.7: enabled 0
1437 11:51:56.685768 GENERIC: 0.0: enabled 1
1438 11:51:56.689209 GENERIC: 0.0: enabled 1
1439 11:51:56.689337 USB0 port 0: enabled 1
1440 11:51:56.691986 GENERIC: 0.0: enabled 1
1441 11:51:56.695856 I2C: 00:2c: enabled 1
1442 11:51:56.695977 I2C: 00:15: enabled 1
1443 11:51:56.699033 GENERIC: 0.0: enabled 0
1444 11:51:56.702250 I2C: 00:15: enabled 1
1445 11:51:56.702352 I2C: 00:10: enabled 0
1446 11:51:56.705686 I2C: 00:10: enabled 0
1447 11:51:56.708575 I2C: 00:2c: enabled 1
1448 11:51:56.712006 I2C: 00:40: enabled 1
1449 11:51:56.712123 I2C: 00:10: enabled 1
1450 11:51:56.715498 I2C: 00:39: enabled 1
1451 11:51:56.718691 I2C: 00:36: enabled 1
1452 11:51:56.718806 I2C: 00:10: enabled 0
1453 11:51:56.722095 I2C: 00:0c: enabled 1
1454 11:51:56.725439 I2C: 00:50: enabled 1
1455 11:51:56.725549 I2C: 00:1a: enabled 1
1456 11:51:56.728281 I2C: 00:1a: enabled 0
1457 11:51:56.731753 I2C: 00:1a: enabled 0
1458 11:51:56.731844 I2C: 00:28: enabled 1
1459 11:51:56.734980 I2C: 00:29: enabled 1
1460 11:51:56.738193 PCI: 00:00.0: enabled 1
1461 11:51:56.738315 SPI: 00: enabled 1
1462 11:51:56.742064 PNP: 0c09.0: enabled 1
1463 11:51:56.745159 GENERIC: 0.0: enabled 0
1464 11:51:56.745291 USB2 port 0: enabled 1
1465 11:51:56.748130 USB2 port 1: enabled 1
1466 11:51:56.751668 USB2 port 2: enabled 1
1467 11:51:56.755186 USB2 port 3: enabled 1
1468 11:51:56.755303 USB2 port 4: enabled 0
1469 11:51:56.758088 USB2 port 5: enabled 1
1470 11:51:56.761390 USB2 port 6: enabled 0
1471 11:51:56.761509 USB2 port 7: enabled 1
1472 11:51:56.764741 USB3 port 0: enabled 1
1473 11:51:56.768370 USB3 port 1: enabled 1
1474 11:51:56.771187 USB3 port 2: enabled 1
1475 11:51:56.771302 USB3 port 3: enabled 1
1476 11:51:56.774476 APIC: 00: enabled 1
1477 11:51:56.774588 APIC: 02: enabled 1
1478 11:51:56.778021 PCI: 00:08.0: enabled 1
1479 11:51:56.784905 BS: BS_DEV_INIT run times (exec / console): 22 / 437 ms
1480 11:51:56.787727 FMAP: area RW_ELOG found @ bfa000 (4096 bytes)
1481 11:51:56.791294 ELOG: NV offset 0xbfa000 size 0x1000
1482 11:51:56.799390 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1483 11:51:56.806001 ELOG: Event(17) added with size 13 at 2023-06-23 11:51:56 UTC
1484 11:51:56.812465 ELOG: Event(92) added with size 9 at 2023-06-23 11:51:56 UTC
1485 11:51:56.819304 ELOG: Event(93) added with size 9 at 2023-06-23 11:51:56 UTC
1486 11:51:56.825745 ELOG: Event(9E) added with size 10 at 2023-06-23 11:51:56 UTC
1487 11:51:56.832499 ELOG: Event(9F) added with size 14 at 2023-06-23 11:51:56 UTC
1488 11:51:56.838817 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1489 11:51:56.841985 ELOG: Event(A1) added with size 10 at 2023-06-23 11:51:57 UTC
1490 11:51:56.852332 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1491 11:51:56.858933 ELOG: Event(A0) added with size 9 at 2023-06-23 11:51:57 UTC
1492 11:51:56.861915 elog_add_boot_reason: Logged dev mode boot
1493 11:51:56.868679 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1494 11:51:56.868844 Finalize devices...
1495 11:51:56.872188 Devices finalized
1496 11:51:56.878498 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1497 11:51:56.881983 FMAP: area RW_NVRAM found @ bfe000 (8192 bytes)
1498 11:51:56.888410 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1499 11:51:56.891940 ME: HFSTS1 : 0x80030045
1500 11:51:56.895422 ME: HFSTS2 : 0x30280136
1501 11:51:56.901726 ME: HFSTS3 : 0x00000050
1502 11:51:56.904793 ME: HFSTS4 : 0x00004000
1503 11:51:56.908200 ME: HFSTS5 : 0x00000000
1504 11:51:56.911712 ME: HFSTS6 : 0x40400006
1505 11:51:56.914977 ME: Manufacturing Mode : NO
1506 11:51:56.918041 ME: FW Partition Table : OK
1507 11:51:56.921601 ME: Bringup Loader Failure : NO
1508 11:51:56.924844 ME: Firmware Init Complete : NO
1509 11:51:56.927708 ME: Boot Options Present : NO
1510 11:51:56.931011 ME: Update In Progress : NO
1511 11:51:56.934844 ME: D0i3 Support : YES
1512 11:51:56.937997 ME: Low Power State Enabled : NO
1513 11:51:56.941492 ME: CPU Replaced : YES
1514 11:51:56.944747 ME: CPU Replacement Valid : YES
1515 11:51:56.947634 ME: Current Working State : 5
1516 11:51:56.951084 ME: Current Operation State : 1
1517 11:51:56.954310 ME: Current Operation Mode : 3
1518 11:51:56.957642 ME: Error Code : 0
1519 11:51:56.961141 ME: CPU Debug Disabled : YES
1520 11:51:56.964586 ME: TXT Support : NO
1521 11:51:56.970646 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 77 ms
1522 11:51:56.977747 CBFS: Found 'fallback/dsdt.aml' @0x41280 size 0x32d2
1523 11:51:56.980639 ACPI: Writing ACPI tables at 76b27000.
1524 11:51:56.983950 ACPI: * FACS
1525 11:51:56.984104 ACPI: * DSDT
1526 11:51:56.987408 Ramoops buffer: 0x100000@0x76a26000.
1527 11:51:56.993962 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1528 11:51:56.997389 FMAP: area RW_VPD found @ bfc000 (8192 bytes)
1529 11:51:57.000927 Google Chrome EC: version:
1530 11:51:57.003995 ro: magolor_1.1.9999-103b6f9
1531 11:51:57.007380 rw: magolor_1.1.9999-103b6f9
1532 11:51:57.010825 running image: 1
1533 11:51:57.017733 PCI space above 4GB MMIO is at 0x180400000, len = 0x7e7fc00000
1534 11:51:57.020693 ACPI: * FADT
1535 11:51:57.020838 SCI is IRQ9
1536 11:51:57.024548 ACPI: added table 1/32, length now 40
1537 11:51:57.027878 ACPI: * SSDT
1538 11:51:57.031011 Found 1 CPU(s) with 2 core(s) each.
1539 11:51:57.034439 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1540 11:51:57.040650 \_SB.PCI0.IPU0.IPU0: Intel MIPI Camera Device I2C address 00h
1541 11:51:57.043867 Could not locate 'wifi_sar' in VPD.
1542 11:51:57.046993 Checking CBFS for default SAR values
1543 11:51:57.050679 wifi_sar_defaults.hex has bad len in CBFS
1544 11:51:57.053783 failed from getting SAR limits!
1545 11:51:57.060241 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1546 11:51:57.063655 \_SB.PCI0.I2C0.H02C: Synaptics Touchpad at I2C: 00:2c
1547 11:51:57.070361 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 00:15
1548 11:51:57.073554 \_SB.PCI0.I2C2.H015: ELAN Touchscreen at I2C: 00:15
1549 11:51:57.080151 \_SB.PCI0.I2C2.H02C: WDT Touchscreen at I2C: 00:2c
1550 11:51:57.083796 \_SB.PCI0.I2C2.H040: G2 Touchscreen at I2C: 00:40
1551 11:51:57.089943 \_SB.PCI0.I2C2.D010: ELAN Touchscreen at I2C: 00:10
1552 11:51:57.093545 \_SB.PCI0.I2C2.D039: Raydium Touchscreen at I2C: 00:39
1553 11:51:57.100042 \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device I2C address 036h
1554 11:51:57.106566 \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device I2C address 0ch
1555 11:51:57.113587 \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device I2C address 050h
1556 11:51:57.119715 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 00:1a
1557 11:51:57.123254 \_SB.PCI0.I2C4.D028: Realtek SPK AMP L at I2C: 00:28
1558 11:51:57.129971 \_SB.PCI0.I2C4.D029: Realtek SPK AMP R at I2C: 00:29
1559 11:51:57.133409 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1560 11:51:57.140741 PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
1561 11:51:57.144031 PS2K: Passing 101 keymaps to kernel
1562 11:51:57.150463 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1563 11:51:57.156888 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1
1564 11:51:57.160351 \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2
1565 11:51:57.167024 \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3
1566 11:51:57.173635 \_SB.PCI0.XHCI.RHUB.HS06: Camera at USB2 port 5
1567 11:51:57.177371 \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7
1568 11:51:57.183533 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1569 11:51:57.190083 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1
1570 11:51:57.193432 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1571 11:51:57.200488 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port at USB3 port 3
1572 11:51:57.203568 ACPI: added table 2/32, length now 44
1573 11:51:57.206981 ACPI: * MCFG
1574 11:51:57.210056 ACPI: added table 3/32, length now 48
1575 11:51:57.210196 ACPI: * TPM2
1576 11:51:57.213636 TPM2 log created at 0x76a16000
1577 11:51:57.217001 ACPI: added table 4/32, length now 52
1578 11:51:57.219937 ACPI: * MADT
1579 11:51:57.220072 SCI is IRQ9
1580 11:51:57.223222 ACPI: added table 5/32, length now 56
1581 11:51:57.226821 current = 76b2d580
1582 11:51:57.229681 ACPI: * DMAR
1583 11:51:57.233353 ACPI: added table 6/32, length now 60
1584 11:51:57.236833 ACPI: added table 7/32, length now 64
1585 11:51:57.237002 ACPI: * HPET
1586 11:51:57.243395 ACPI: added table 8/32, length now 68
1587 11:51:57.243647 ACPI: done.
1588 11:51:57.246365 ACPI tables: 26304 bytes.
1589 11:51:57.250172 smbios_write_tables: 76a15000
1590 11:51:57.253513 EC returned error result code 3
1591 11:51:57.256297 Couldn't obtain OEM name from CBI
1592 11:51:57.259653 Create SMBIOS type 16
1593 11:51:57.259803 Create SMBIOS type 17
1594 11:51:57.263090 GENERIC: 0.0 (WIFI Device)
1595 11:51:57.266689 SMBIOS tables: 913 bytes.
1596 11:51:57.269998 Writing table forward entry at 0x00000500
1597 11:51:57.276672 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d929
1598 11:51:57.279972 Writing coreboot table at 0x76b4b000
1599 11:51:57.286482 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1600 11:51:57.289424 1. 0000000000001000-000000000009ffff: RAM
1601 11:51:57.296143 2. 00000000000a0000-00000000000fffff: RESERVED
1602 11:51:57.299563 3. 0000000000100000-0000000076a14fff: RAM
1603 11:51:57.306055 4. 0000000076a15000-0000000076ba7fff: CONFIGURATION TABLES
1604 11:51:57.309528 5. 0000000076ba8000-0000000076c0cfff: RAMSTAGE
1605 11:51:57.315938 6. 0000000076c0d000-0000000076ffffff: CONFIGURATION TABLES
1606 11:51:57.319431 7. 0000000077000000-000000007fbfffff: RESERVED
1607 11:51:57.325811 8. 00000000c0000000-00000000cfffffff: RESERVED
1608 11:51:57.329305 9. 00000000fb000000-00000000fb000fff: RESERVED
1609 11:51:57.335754 10. 00000000fe000000-00000000fe00ffff: RESERVED
1610 11:51:57.339205 11. 00000000fea80000-00000000fea87fff: RESERVED
1611 11:51:57.345915 12. 00000000fed80000-00000000fed87fff: RESERVED
1612 11:51:57.349434 13. 00000000fed90000-00000000fed92fff: RESERVED
1613 11:51:57.355887 14. 00000000feda0000-00000000feda1fff: RESERVED
1614 11:51:57.358697 15. 0000000100000000-00000001803fffff: RAM
1615 11:51:57.362487 Passing 4 GPIOs to payload:
1616 11:51:57.365639 NAME | PORT | POLARITY | VALUE
1617 11:51:57.372255 lid | undefined | high | high
1618 11:51:57.375501 power | undefined | high | low
1619 11:51:57.382081 oprom | undefined | high | low
1620 11:51:57.388467 EC in RW | 0x000000b9 | high | low
1621 11:51:57.395139 Wrote coreboot table at: 0x76b4b000, 0x5c8 bytes, checksum 9b10
1622 11:51:57.395318 coreboot table: 1504 bytes.
1623 11:51:57.401869 IMD ROOT 0. 0x76fff000 0x00001000
1624 11:51:57.405259 IMD SMALL 1. 0x76ffe000 0x00001000
1625 11:51:57.408306 FSP MEMORY 2. 0x76c4e000 0x003b0000
1626 11:51:57.411907 CONSOLE 3. 0x76c2e000 0x00020000
1627 11:51:57.415303 FMAP 4. 0x76c2d000 0x00000578
1628 11:51:57.418357 TIME STAMP 5. 0x76c2c000 0x00000910
1629 11:51:57.421826 VBOOT WORK 6. 0x76c18000 0x00014000
1630 11:51:57.424858 ROMSTG STCK 7. 0x76c17000 0x00001000
1631 11:51:57.431794 AFTER CAR 8. 0x76c0d000 0x0000a000
1632 11:51:57.435227 RAMSTAGE 9. 0x76ba7000 0x00066000
1633 11:51:57.438066 REFCODE 10. 0x76b67000 0x00040000
1634 11:51:57.441608 SMM BACKUP 11. 0x76b57000 0x00010000
1635 11:51:57.445103 4f444749 12. 0x76b55000 0x00002000
1636 11:51:57.447863 EXT VBT13. 0x76b53000 0x00001c43
1637 11:51:57.451768 COREBOOT 14. 0x76b4b000 0x00008000
1638 11:51:57.454967 ACPI 15. 0x76b27000 0x00024000
1639 11:51:57.457919 ACPI GNVS 16. 0x76b26000 0x00001000
1640 11:51:57.461344 RAMOOPS 17. 0x76a26000 0x00100000
1641 11:51:57.467959 TPM2 TCGLOG18. 0x76a16000 0x00010000
1642 11:51:57.471106 SMBIOS 19. 0x76a15000 0x00000800
1643 11:51:57.471225 IMD small region:
1644 11:51:57.474381 IMD ROOT 0. 0x76ffec00 0x00000400
1645 11:51:57.481210 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1646 11:51:57.484865 VPD 2. 0x76ffeb60 0x0000006c
1647 11:51:57.487928 POWER STATE 3. 0x76ffeb20 0x00000040
1648 11:51:57.491176 ROMSTAGE 4. 0x76ffeb00 0x00000004
1649 11:51:57.494257 MEM INFO 5. 0x76ffe920 0x000001e0
1650 11:51:57.501309 BS: BS_WRITE_TABLES run times (exec / console): 8 / 516 ms
1651 11:51:57.504659 MTRR: Physical address space:
1652 11:51:57.510958 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1653 11:51:57.517946 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1654 11:51:57.524465 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1655 11:51:57.530790 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1656 11:51:57.534296 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1657 11:51:57.540525 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1658 11:51:57.547529 0x0000000100000000 - 0x0000000180400000 size 0x80400000 type 6
1659 11:51:57.550885 MTRR: Fixed MSR 0x250 0x0606060606060606
1660 11:51:57.557581 MTRR: Fixed MSR 0x258 0x0606060606060606
1661 11:51:57.560649 MTRR: Fixed MSR 0x259 0x0000000000000000
1662 11:51:57.563629 MTRR: Fixed MSR 0x268 0x0606060606060606
1663 11:51:57.567195 MTRR: Fixed MSR 0x269 0x0606060606060606
1664 11:51:57.574016 MTRR: Fixed MSR 0x26a 0x0606060606060606
1665 11:51:57.577066 MTRR: Fixed MSR 0x26b 0x0606060606060606
1666 11:51:57.580543 MTRR: Fixed MSR 0x26c 0x0606060606060606
1667 11:51:57.583801 MTRR: Fixed MSR 0x26d 0x0606060606060606
1668 11:51:57.590374 MTRR: Fixed MSR 0x26e 0x0606060606060606
1669 11:51:57.593595 MTRR: Fixed MSR 0x26f 0x0606060606060606
1670 11:51:57.596801 call enable_fixed_mtrr()
1671 11:51:57.600248 CPU physical address size: 39 bits
1672 11:51:57.603449 MTRR: default type WB/UC MTRR counts: 6/5.
1673 11:51:57.606810 MTRR: UC selected as default type.
1674 11:51:57.613334 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1675 11:51:57.619826 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1676 11:51:57.626922 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1677 11:51:57.632962 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1678 11:51:57.639626 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1679 11:51:57.639746
1680 11:51:57.639843 MTRR check
1681 11:51:57.643136 Fixed MTRRs : Enabled
1682 11:51:57.646179 Variable MTRRs: Enabled
1683 11:51:57.646289
1684 11:51:57.649479 MTRR: Fixed MSR 0x250 0x0606060606060606
1685 11:51:57.653011 MTRR: Fixed MSR 0x258 0x0606060606060606
1686 11:51:57.656481 MTRR: Fixed MSR 0x259 0x0000000000000000
1687 11:51:57.662776 MTRR: Fixed MSR 0x268 0x0606060606060606
1688 11:51:57.666538 MTRR: Fixed MSR 0x269 0x0606060606060606
1689 11:51:57.669721 MTRR: Fixed MSR 0x26a 0x0606060606060606
1690 11:51:57.672582 MTRR: Fixed MSR 0x26b 0x0606060606060606
1691 11:51:57.679586 MTRR: Fixed MSR 0x26c 0x0606060606060606
1692 11:51:57.682896 MTRR: Fixed MSR 0x26d 0x0606060606060606
1693 11:51:57.685673 MTRR: Fixed MSR 0x26e 0x0606060606060606
1694 11:51:57.689461 MTRR: Fixed MSR 0x26f 0x0606060606060606
1695 11:51:57.695965 BS: BS_WRITE_TABLES exit times (exec / console): 1 / 143 ms
1696 11:51:57.699155 call enable_fixed_mtrr()
1697 11:51:57.702221 Checking cr50 for pending updates
1698 11:51:57.705822 CPU physical address size: 39 bits
1699 11:51:57.709675 Reading cr50 TPM mode
1700 11:51:57.718663 BS: BS_PAYLOAD_LOAD entry times (exec / console): 11 / 6 ms
1701 11:51:57.726036 CBFS: Found 'fallback/payload' @0x395580 size 0x4ae38
1702 11:51:57.729589 Checking segment from ROM address 0xfff9d5b8
1703 11:51:57.736019 Checking segment from ROM address 0xfff9d5d4
1704 11:51:57.739691 Loading segment from ROM address 0xfff9d5b8
1705 11:51:57.742547 code (compression=0)
1706 11:51:57.749461 New segment dstaddr 0x30000000 memsize 0x1062170 srcaddr 0xfff9d5f0 filesize 0x4ae00
1707 11:51:57.759265 Loading Segment: addr: 0x30000000 memsz: 0x0000000001062170 filesz: 0x000000000004ae00
1708 11:51:57.762299 it's not compressed!
1709 11:51:57.888278 [ 0x30000000, 3004ae00, 0x31062170) <- fff9d5f0
1710 11:51:57.895360 Clearing Segment: addr: 0x000000003004ae00 memsz: 0x0000000001017370
1711 11:51:57.902255 Loading segment from ROM address 0xfff9d5d4
1712 11:51:57.905624 Entry Point 0x30000000
1713 11:51:57.905713 Loaded segments
1714 11:51:57.912278 BS: BS_PAYLOAD_LOAD run times (exec / console): 126 / 60 ms
1715 11:51:57.928883 Finalizing chipset.
1716 11:51:57.931548 Finalizing SMM.
1717 11:51:57.931642 APMC done.
1718 11:51:57.938392 BS: BS_PAYLOAD_LOAD exit times (exec / console): 15 / 5 ms
1719 11:51:57.941927 mp_park_aps done after 0 msecs.
1720 11:51:57.944839 Jumping to boot code at 0x30000000(0x76b4b000)
1721 11:51:57.955271 CPU0: stack: 0x76bfb000 - 0x76bfc000, lowest used address 0x76bfb918, stack used: 1768 bytes
1722 11:51:57.955365
1723 11:51:57.955433
1724 11:51:57.955497
1725 11:51:57.958167 Starting depthcharge on Magolor...
1726 11:51:57.958513 end: 2.2.3 depthcharge-start (duration 00:00:08) [common]
1727 11:51:57.958623 start: 2.2.4 bootloader-commands (timeout 00:04:47) [common]
1728 11:51:57.958709 Setting prompt string to ['dedede:']
1729 11:51:57.958789 bootloader-commands: Wait for prompt ['dedede:'] (timeout 00:04:47)
1730 11:51:57.961689
1731 11:51:57.968248 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1732 11:51:57.968366
1733 11:51:57.974551 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1734 11:51:57.974656
1735 11:51:57.978003 fw_config match found: AUDIO_AMP=UNPROVISIONED
1736 11:51:57.981203
1737 11:51:57.981275 Wipe memory regions:
1738 11:51:57.981339
1739 11:51:57.984744 [0x00000000001000, 0x000000000a0000)
1740 11:51:57.984818
1741 11:51:57.987846 [0x00000000100000, 0x00000030000000)
1742 11:51:58.117347
1743 11:51:58.120621 [0x00000031062170, 0x00000076a15000)
1744 11:51:58.290278
1745 11:51:58.293094 [0x00000100000000, 0x00000180400000)
1746 11:51:59.356966
1747 11:51:59.357244 R8152: Initializing
1748 11:51:59.357315
1749 11:51:59.359761 Version 6 (ocp_data = 5c30)
1750 11:51:59.363263
1751 11:51:59.363402 R8152: Done initializing
1752 11:51:59.363564
1753 11:51:59.366683 Adding net device
1754 11:51:59.366806
1755 11:51:59.370254 [firmware-dedede-13606.B-collabora] Apr 28 2022 09:20:48
1756 11:51:59.373131
1757 11:51:59.373215
1758 11:51:59.373280
1759 11:51:59.373560 Setting prompt string to ['dedede:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
1761 11:51:59.473920 dedede: tftpboot 192.168.201.1 10875898/tftp-deploy-2dr24zd4/kernel/bzImage 10875898/tftp-deploy-2dr24zd4/kernel/cmdline 10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
1762 11:51:59.474116 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
1763 11:51:59.474215 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:45)
1764 11:51:59.478054 tftpboot 192.168.201.1 10875898/tftp-deploy-2dr24zd4/kernel/bzIploy-2dr24zd4/kernel/cmdline 10875898/tftp-deploy-2dr24zd4/ramdisk/ramdisk.cpio.gz
1765 11:51:59.478142
1766 11:51:59.478221 Waiting for link
1767 11:51:59.680214
1768 11:51:59.680386 done.
1769 11:51:59.680461
1770 11:51:59.680526 MAC: 00:24:32:30:7b:c4
1771 11:51:59.680588
1772 11:51:59.683635 Sending DHCP discover... done.
1773 11:51:59.683714
1774 11:51:59.687098 Waiting for reply... done.
1775 11:51:59.687210
1776 11:51:59.690035 Sending DHCP request... done.
1777 11:51:59.690160
1778 11:51:59.693639 Waiting for reply... done.
1779 11:51:59.696641
1780 11:51:59.696729 My ip is 192.168.201.12
1781 11:51:59.696795
1782 11:51:59.700055 The DHCP server ip is 192.168.201.1
1783 11:51:59.700163
1784 11:51:59.706516 TFTP server IP predefined by user: 192.168.201.1
1785 11:51:59.706607
1786 11:51:59.713589 Bootfile predefined by user: 10875898/tftp-deploy-2dr24zd4/kernel/bzImage
1787 11:51:59.713680
1788 11:51:59.716476 Sending tftp read request... done.
1789 11:51:59.716554
1790 11:51:59.719942 Waiting for the transfer...
1791 11:51:59.720057
1792 11:52:00.304175 00000000 ################################################################
1793 11:52:00.304369
1794 11:52:00.866784 00080000 ################################################################
1795 11:52:00.866964
1796 11:52:01.416682 00100000 ################################################################
1797 11:52:01.416852
1798 11:52:01.977180 00180000 ################################################################
1799 11:52:01.977337
1800 11:52:02.541682 00200000 ################################################################
1801 11:52:02.541858
1802 11:52:03.108669 00280000 ################################################################
1803 11:52:03.108821
1804 11:52:03.676122 00300000 ################################################################
1805 11:52:03.676324
1806 11:52:04.249850 00380000 ################################################################
1807 11:52:04.250011
1808 11:52:04.829169 00400000 ################################################################
1809 11:52:04.829333
1810 11:52:05.411216 00480000 ################################################################
1811 11:52:05.411360
1812 11:52:06.012664 00500000 ################################################################
1813 11:52:06.012818
1814 11:52:06.578710 00580000 ################################################################
1815 11:52:06.578891
1816 11:52:07.137417 00600000 ################################################################
1817 11:52:07.137619
1818 11:52:07.702224 00680000 ################################################################
1819 11:52:07.702406
1820 11:52:08.260623 00700000 ################################################################
1821 11:52:08.260766
1822 11:52:08.804970 00780000 ################################################################
1823 11:52:08.805133
1824 11:52:09.341764 00800000 ################################################################
1825 11:52:09.341933
1826 11:52:09.888419 00880000 ################################################################
1827 11:52:09.888585
1828 11:52:10.434979 00900000 ################################################################
1829 11:52:10.435156
1830 11:52:11.021668 00980000 ################################################################
1831 11:52:11.021831
1832 11:52:11.419048 00a00000 ############################################## done.
1833 11:52:11.419190
1834 11:52:11.422158 The bootfile was 10859008 bytes long.
1835 11:52:11.422246
1836 11:52:11.425552 Sending tftp read request... done.
1837 11:52:11.425643
1838 11:52:11.429083 Waiting for the transfer...
1839 11:52:11.429172
1840 11:52:11.976294 00000000 ################################################################
1841 11:52:11.976433
1842 11:52:12.527123 00080000 ################################################################
1843 11:52:12.527255
1844 11:52:13.067359 00100000 ################################################################
1845 11:52:13.067498
1846 11:52:13.605021 00180000 ################################################################
1847 11:52:13.605176
1848 11:52:14.163440 00200000 ################################################################
1849 11:52:14.163571
1850 11:52:14.720900 00280000 ################################################################
1851 11:52:14.721086
1852 11:52:15.279077 00300000 ################################################################
1853 11:52:15.279238
1854 11:52:15.838364 00380000 ################################################################
1855 11:52:15.838536
1856 11:52:16.442440 00400000 ################################################################
1857 11:52:16.442616
1858 11:52:17.006990 00480000 ################################################################
1859 11:52:17.007157
1860 11:52:17.554964 00500000 ################################################################
1861 11:52:17.555103
1862 11:52:18.120879 00580000 ################################################################
1863 11:52:18.121024
1864 11:52:18.659643 00600000 ################################################################
1865 11:52:18.659784
1866 11:52:19.239407 00680000 ################################################################
1867 11:52:19.239562
1868 11:52:19.780225 00700000 ################################################################
1869 11:52:19.780379
1870 11:52:20.324433 00780000 ################################################################
1871 11:52:20.324601
1872 11:52:20.862191 00800000 ################################################################
1873 11:52:20.862328
1874 11:52:21.177003 00880000 ###################################### done.
1875 11:52:21.177174
1876 11:52:21.180098 Sending tftp read request... done.
1877 11:52:21.180212
1878 11:52:21.180323 Waiting for the transfer...
1879 11:52:21.183318
1880 11:52:21.183435 00000000 # done.
1881 11:52:21.183535
1882 11:52:21.193490 Command line loaded dynamically from TFTP file: 10875898/tftp-deploy-2dr24zd4/kernel/cmdline
1883 11:52:21.193604
1884 11:52:21.206269 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
1885 11:52:21.206355
1886 11:52:21.209490 ec_init: CrosEC protocol v3 supported (256, 256)
1887 11:52:21.217810
1888 11:52:21.221646 Shutting down all USB controllers.
1889 11:52:21.221728
1890 11:52:21.221794 Removing current net device
1891 11:52:21.221856
1892 11:52:21.224633 Finalizing coreboot
1893 11:52:21.224712
1894 11:52:21.231211 Exiting depthcharge with code 4 at timestamp: 30068319
1895 11:52:21.231324
1896 11:52:21.231419
1897 11:52:21.231513 Starting kernel ...
1898 11:52:21.231578
1899 11:52:21.231638
1900 11:52:21.232020 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
1901 11:52:21.232166 start: 2.2.5 auto-login-action (timeout 00:04:24) [common]
1902 11:52:21.232273 Setting prompt string to ['Linux version [0-9]']
1903 11:52:21.232357 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
1904 11:52:21.232428 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
1906 11:56:45.232702 end: 2.2.5 auto-login-action (duration 00:04:24) [common]
1908 11:56:45.233202 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 264 seconds'
1910 11:56:45.233575 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
1913 11:56:45.234127 end: 2 depthcharge-action (duration 00:05:00) [common]
1915 11:56:45.234587 Cleaning after the job
1916 11:56:45.234771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/ramdisk
1917 11:56:45.236863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/kernel
1918 11:56:45.238123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875898/tftp-deploy-2dr24zd4/modules
1919 11:56:45.238655 start: 5.1 power-off (timeout 00:00:30) [common]
1920 11:56:45.238820 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cb317-1h-c3z6-dedede-cbg-8' '--port=1' '--command=off'
1921 11:56:45.319994 >> Command sent successfully.
1922 11:56:45.331261 Returned 0 in 0 seconds
1923 11:56:45.432643 end: 5.1 power-off (duration 00:00:00) [common]
1925 11:56:45.434292 start: 5.2 read-feedback (timeout 00:10:00) [common]
1926 11:56:45.435676 Listened to connection for namespace 'common' for up to 1s
1928 11:56:45.437126 Listened to connection for namespace 'common' for up to 1s
1929 11:56:46.436348 Finalising connection for namespace 'common'
1930 11:56:46.436970 Disconnecting from shell: Finalise
1931 11:56:46.437341
1932 11:56:46.538324 end: 5.2 read-feedback (duration 00:00:01) [common]
1933 11:56:46.538907 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10875898
1934 11:56:46.590137 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10875898
1935 11:56:46.590376 JobError: Your job cannot terminate cleanly.