Boot log: asus-cx9400-volteer
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
1 11:51:31.708460 lava-dispatcher, installed at version: 2023.05.1
2 11:51:31.708678 start: 0 validate
3 11:51:31.708810 Start time: 2023-06-23 11:51:31.708803+00:00 (UTC)
4 11:51:31.708936 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:51:31.709068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230609.0%2Fx86%2Frootfs.cpio.gz exists
6 11:51:31.967958 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:51:31.968201 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.287-cip100%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 11:51:35.977083 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:51:35.978015 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.19.y-cip%2Fv4.19.287-cip100%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 11:51:36.984181 validate duration: 5.28
12 11:51:36.984481 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 11:51:36.984582 start: 1.1 download-retry (timeout 00:10:00) [common]
14 11:51:36.984670 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 11:51:36.984792 Not decompressing ramdisk as can be used compressed.
16 11:51:36.984879 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230609.0/x86/rootfs.cpio.gz
17 11:51:36.984945 saving as /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/ramdisk/rootfs.cpio.gz
18 11:51:36.985007 total size: 8435745 (8MB)
19 11:51:36.986213 progress 0% (0MB)
20 11:51:36.988486 progress 5% (0MB)
21 11:51:36.990830 progress 10% (0MB)
22 11:51:36.993218 progress 15% (1MB)
23 11:51:36.995541 progress 20% (1MB)
24 11:51:36.997872 progress 25% (2MB)
25 11:51:37.000202 progress 30% (2MB)
26 11:51:37.002535 progress 35% (2MB)
27 11:51:37.004744 progress 40% (3MB)
28 11:51:37.006990 progress 45% (3MB)
29 11:51:37.009340 progress 50% (4MB)
30 11:51:37.011578 progress 55% (4MB)
31 11:51:37.013860 progress 60% (4MB)
32 11:51:37.016167 progress 65% (5MB)
33 11:51:37.018437 progress 70% (5MB)
34 11:51:37.020708 progress 75% (6MB)
35 11:51:37.022711 progress 80% (6MB)
36 11:51:37.024927 progress 85% (6MB)
37 11:51:37.027181 progress 90% (7MB)
38 11:51:37.029494 progress 95% (7MB)
39 11:51:37.031787 progress 100% (8MB)
40 11:51:37.031975 8MB downloaded in 0.05s (171.30MB/s)
41 11:51:37.032166 end: 1.1.1 http-download (duration 00:00:00) [common]
43 11:51:37.032547 end: 1.1 download-retry (duration 00:00:00) [common]
44 11:51:37.032634 start: 1.2 download-retry (timeout 00:10:00) [common]
45 11:51:37.032717 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 11:51:37.032843 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.287-cip100/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 11:51:37.032915 saving as /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/kernel/bzImage
48 11:51:37.032976 total size: 10859008 (10MB)
49 11:51:37.033033 No compression specified
50 11:51:37.034485 progress 0% (0MB)
51 11:51:37.037315 progress 5% (0MB)
52 11:51:37.040152 progress 10% (1MB)
53 11:51:37.042878 progress 15% (1MB)
54 11:51:37.045943 progress 20% (2MB)
55 11:51:37.049099 progress 25% (2MB)
56 11:51:37.052384 progress 30% (3MB)
57 11:51:37.055466 progress 35% (3MB)
58 11:51:37.058688 progress 40% (4MB)
59 11:51:37.062086 progress 45% (4MB)
60 11:51:37.065509 progress 50% (5MB)
61 11:51:37.068833 progress 55% (5MB)
62 11:51:37.071683 progress 60% (6MB)
63 11:51:37.074662 progress 65% (6MB)
64 11:51:37.077663 progress 70% (7MB)
65 11:51:37.081143 progress 75% (7MB)
66 11:51:37.084387 progress 80% (8MB)
67 11:51:37.087514 progress 85% (8MB)
68 11:51:37.090855 progress 90% (9MB)
69 11:51:37.094244 progress 95% (9MB)
70 11:51:37.097912 progress 100% (10MB)
71 11:51:37.098199 10MB downloaded in 0.07s (158.79MB/s)
72 11:51:37.098420 end: 1.2.1 http-download (duration 00:00:00) [common]
74 11:51:37.098812 end: 1.2 download-retry (duration 00:00:00) [common]
75 11:51:37.098951 start: 1.3 download-retry (timeout 00:10:00) [common]
76 11:51:37.099079 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 11:51:37.099267 downloading http://storage.kernelci.org/cip/linux-4.19.y-cip/v4.19.287-cip100/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 11:51:37.099376 saving as /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/modules/modules.tar
79 11:51:37.099485 total size: 483808 (0MB)
80 11:51:37.099586 Using unxz to decompress xz
81 11:51:37.104019 progress 6% (0MB)
82 11:51:37.104632 progress 13% (0MB)
83 11:51:37.104923 progress 20% (0MB)
84 11:51:37.106347 progress 27% (0MB)
85 11:51:37.108638 progress 33% (0MB)
86 11:51:37.111357 progress 40% (0MB)
87 11:51:37.113866 progress 47% (0MB)
88 11:51:37.115898 progress 54% (0MB)
89 11:51:37.118438 progress 60% (0MB)
90 11:51:37.121295 progress 67% (0MB)
91 11:51:37.123409 progress 74% (0MB)
92 11:51:37.125675 progress 81% (0MB)
93 11:51:37.127952 progress 88% (0MB)
94 11:51:37.130046 progress 94% (0MB)
95 11:51:37.132420 progress 100% (0MB)
96 11:51:37.139197 0MB downloaded in 0.04s (11.62MB/s)
97 11:51:37.139612 end: 1.3.1 http-download (duration 00:00:00) [common]
99 11:51:37.139907 end: 1.3 download-retry (duration 00:00:00) [common]
100 11:51:37.140056 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
101 11:51:37.140211 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
102 11:51:37.140342 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 11:51:37.140510 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
104 11:51:37.140857 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu
105 11:51:37.141051 makedir: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin
106 11:51:37.141198 makedir: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/tests
107 11:51:37.141316 makedir: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/results
108 11:51:37.141454 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-add-keys
109 11:51:37.141662 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-add-sources
110 11:51:37.141852 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-background-process-start
111 11:51:37.142070 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-background-process-stop
112 11:51:37.142310 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-common-functions
113 11:51:37.142480 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-echo-ipv4
114 11:51:37.142650 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-install-packages
115 11:51:37.142820 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-installed-packages
116 11:51:37.142991 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-os-build
117 11:51:37.143161 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-probe-channel
118 11:51:37.143338 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-probe-ip
119 11:51:37.143520 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-target-ip
120 11:51:37.143779 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-target-mac
121 11:51:37.143994 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-target-storage
122 11:51:37.144167 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-case
123 11:51:37.144337 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-event
124 11:51:37.144530 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-feedback
125 11:51:37.144670 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-raise
126 11:51:37.144881 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-reference
127 11:51:37.145134 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-runner
128 11:51:37.145346 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-set
129 11:51:37.145519 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-test-shell
130 11:51:37.145695 Updating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-install-packages (oe)
131 11:51:37.145937 Updating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/bin/lava-installed-packages (oe)
132 11:51:37.146144 Creating /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/environment
133 11:51:37.146293 LAVA metadata
134 11:51:37.146403 - LAVA_JOB_ID=10875908
135 11:51:37.146511 - LAVA_DISPATCHER_IP=192.168.201.1
136 11:51:37.146659 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
137 11:51:37.146766 skipped lava-vland-overlay
138 11:51:37.146892 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 11:51:37.147023 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
140 11:51:37.147123 skipped lava-multinode-overlay
141 11:51:37.147247 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 11:51:37.147375 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
143 11:51:37.147497 Loading test definitions
144 11:51:37.147637 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
145 11:51:37.147753 Using /lava-10875908 at stage 0
146 11:51:37.148225 uuid=10875908_1.4.2.3.1 testdef=None
147 11:51:37.148352 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 11:51:37.148503 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
149 11:51:37.149275 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 11:51:37.149649 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
152 11:51:37.150587 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 11:51:37.150975 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
155 11:51:37.151846 runner path: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/0/tests/0_dmesg test_uuid 10875908_1.4.2.3.1
156 11:51:37.152045 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 11:51:37.152425 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
159 11:51:37.152544 Using /lava-10875908 at stage 1
160 11:51:37.152914 uuid=10875908_1.4.2.3.5 testdef=None
161 11:51:37.153013 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 11:51:37.153138 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
163 11:51:37.153838 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 11:51:37.154202 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
166 11:51:37.155163 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 11:51:37.155547 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
169 11:51:37.156312 runner path: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/1/tests/1_bootrr test_uuid 10875908_1.4.2.3.5
170 11:51:37.156533 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 11:51:37.156761 Creating lava-test-runner.conf files
173 11:51:37.156842 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/0 for stage 0
174 11:51:37.156956 - 0_dmesg
175 11:51:37.157049 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10875908/lava-overlay-a33ihcvu/lava-10875908/1 for stage 1
176 11:51:37.157180 - 1_bootrr
177 11:51:37.157314 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 11:51:37.157439 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
179 11:51:37.167161 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 11:51:37.167368 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
181 11:51:37.167508 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 11:51:37.167631 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 11:51:37.167756 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
184 11:51:37.426194 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 11:51:37.426610 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
186 11:51:37.426761 extracting modules file /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10875908/extract-overlay-ramdisk-f2a53i8r/ramdisk
187 11:51:37.451677 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 11:51:37.451846 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
189 11:51:37.452082 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10875908/compress-overlay-o5whyp0z/overlay-1.4.2.4.tar.gz to ramdisk
190 11:51:37.452213 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10875908/compress-overlay-o5whyp0z/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10875908/extract-overlay-ramdisk-f2a53i8r/ramdisk
191 11:51:37.464975 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 11:51:37.465138 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
193 11:51:37.465269 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 11:51:37.465396 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
195 11:51:37.465512 Building ramdisk /var/lib/lava/dispatcher/tmp/10875908/extract-overlay-ramdisk-f2a53i8r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10875908/extract-overlay-ramdisk-f2a53i8r/ramdisk
196 11:51:37.598918 >> 53980 blocks
197 11:51:38.568412 rename /var/lib/lava/dispatcher/tmp/10875908/extract-overlay-ramdisk-f2a53i8r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
198 11:51:38.568877 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 11:51:38.569020 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 11:51:38.569140 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 11:51:38.569264 No mkimage arch provided, not using FIT.
202 11:51:38.569369 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 11:51:38.569473 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 11:51:38.569601 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 11:51:38.569737 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 11:51:38.569859 No LXC device requested
207 11:51:38.569984 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 11:51:38.570121 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 11:51:38.570245 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 11:51:38.570359 Checking files for TFTP limit of 4294967296 bytes.
211 11:51:38.570888 end: 1 tftp-deploy (duration 00:00:02) [common]
212 11:51:38.571030 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 11:51:38.571168 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 11:51:38.571347 substitutions:
215 11:51:38.571447 - {DTB}: None
216 11:51:38.571550 - {INITRD}: 10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
217 11:51:38.571652 - {KERNEL}: 10875908/tftp-deploy-rausi4ru/kernel/bzImage
218 11:51:38.571753 - {LAVA_MAC}: None
219 11:51:38.571852 - {PRESEED_CONFIG}: None
220 11:51:38.571951 - {PRESEED_LOCAL}: None
221 11:51:38.572050 - {RAMDISK}: 10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
222 11:51:38.572148 - {ROOT_PART}: None
223 11:51:38.572245 - {ROOT}: None
224 11:51:38.572342 - {SERVER_IP}: 192.168.201.1
225 11:51:38.572446 - {TEE}: None
226 11:51:38.572544 Parsed boot commands:
227 11:51:38.572639 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 11:51:38.572864 Parsed boot commands: tftpboot 192.168.201.1 10875908/tftp-deploy-rausi4ru/kernel/bzImage 10875908/tftp-deploy-rausi4ru/kernel/cmdline 10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
229 11:51:38.572992 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 11:51:38.573126 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 11:51:38.573263 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 11:51:38.573395 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 11:51:38.573504 Not connected, no need to disconnect.
234 11:51:38.573624 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 11:51:38.573751 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 11:51:38.573853 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-0'
237 11:51:38.577268 Setting prompt string to ['lava-test: # ']
238 11:51:38.577675 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 11:51:38.577823 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 11:51:38.577965 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 11:51:38.578102 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 11:51:38.578442 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-0' '--port=1' '--command=reboot'
243 11:51:43.717317 >> Command sent successfully.
244 11:51:43.719777 Returned 0 in 5 seconds
245 11:51:43.820489 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 11:51:43.822465 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 11:51:43.823222 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 11:51:43.823837 Setting prompt string to 'Starting depthcharge on Voema...'
250 11:51:43.824378 Changing prompt to 'Starting depthcharge on Voema...'
251 11:51:43.824891 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
252 11:51:43.826586 [Enter `^Ec?' for help]
253 11:51:45.422587
254 11:51:45.422777
255 11:51:45.432286 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
256 11:51:45.436007 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
257 11:51:45.442760 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
258 11:51:45.445824 CPU: AES supported, TXT NOT supported, VT supported
259 11:51:45.452601 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
260 11:51:45.459327 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
261 11:51:45.462490 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
262 11:51:45.465587 VBOOT: Loading verstage.
263 11:51:45.469258 FMAP: Found "FLASH" version 1.1 at 0x1804000.
264 11:51:45.475486 FMAP: base = 0x0 size = 0x2000000 #areas = 32
265 11:51:45.479120 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
266 11:51:45.489539 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
267 11:51:45.496387 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
268 11:51:45.496498
269 11:51:45.496578
270 11:51:45.509669 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
271 11:51:45.523080 Probing TPM: . done!
272 11:51:45.526604 TPM ready after 0 ms
273 11:51:45.529645 Connected to device vid:did:rid of 1ae0:0028:00
274 11:51:45.541457 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
275 11:51:45.547686 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
276 11:51:45.551203 Initialized TPM device CR50 revision 0
277 11:51:45.708965 tlcl_send_startup: Startup return code is 0
278 11:51:45.709118 TPM: setup succeeded
279 11:51:45.722799 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
280 11:51:45.737665 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
281 11:51:45.749995 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
282 11:51:45.759855 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
283 11:51:45.763603 Chrome EC: UHEPI supported
284 11:51:45.766748 Phase 1
285 11:51:45.770438 FMAP: area GBB found @ 1805000 (458752 bytes)
286 11:51:45.780506 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
287 11:51:45.786750 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
288 11:51:45.793537 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
289 11:51:45.799953 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
290 11:51:45.803612 Recovery requested (1009000e)
291 11:51:45.807042 TPM: Extending digest for VBOOT: boot mode into PCR 0
292 11:51:45.818247 tlcl_extend: response is 0
293 11:51:45.824995 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
294 11:51:45.834974 tlcl_extend: response is 0
295 11:51:45.841315 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 11:51:45.847805 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
297 11:51:45.854575 BS: verstage times (exec / console): total (unknown) / 142 ms
298 11:51:45.854686
299 11:51:45.854792
300 11:51:45.868258 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
301 11:51:45.871933 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
302 11:51:45.878720 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
303 11:51:45.882551 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
304 11:51:45.885621 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
305 11:51:45.891903 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
306 11:51:45.895586 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
307 11:51:45.898748 TCO_STS: 0000 0000
308 11:51:45.901765 GEN_PMCON: d0015038 00002200
309 11:51:45.905275 GBLRST_CAUSE: 00000000 00000000
310 11:51:45.905364 HPR_CAUSE0: 00000000
311 11:51:45.908759 prev_sleep_state 5
312 11:51:45.911648 Boot Count incremented to 21417
313 11:51:45.918451 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
314 11:51:45.924902 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
315 11:51:45.931411 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
316 11:51:45.937925 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
317 11:51:45.942240 Chrome EC: UHEPI supported
318 11:51:45.948724 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
319 11:51:45.961943 Probing TPM: done!
320 11:51:45.968627 Connected to device vid:did:rid of 1ae0:0028:00
321 11:51:45.978681 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
322 11:51:45.981793 Initialized TPM device CR50 revision 0
323 11:51:45.995508 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
324 11:51:46.002345 MRC: Hash idx 0x100b comparison successful.
325 11:51:46.005445 MRC cache found, size faa8
326 11:51:46.005551 bootmode is set to: 2
327 11:51:46.008989 SPD index = 0
328 11:51:46.015495 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
329 11:51:46.018840 SPD: module type is LPDDR4X
330 11:51:46.025687 SPD: module part number is MT53E512M64D4NW-046
331 11:51:46.028749 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
332 11:51:46.035669 SPD: device width 16 bits, bus width 16 bits
333 11:51:46.038493 SPD: module size is 1024 MB (per channel)
334 11:51:46.472923 CBMEM:
335 11:51:46.476292 IMD: root @ 0x76fff000 254 entries.
336 11:51:46.479174 IMD: root @ 0x76ffec00 62 entries.
337 11:51:46.482491 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
338 11:51:46.489185 FMAP: area RW_VPD found @ f35000 (8192 bytes)
339 11:51:46.492752 External stage cache:
340 11:51:46.495972 IMD: root @ 0x7b3ff000 254 entries.
341 11:51:46.498980 IMD: root @ 0x7b3fec00 62 entries.
342 11:51:46.514662 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
343 11:51:46.521280 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
344 11:51:46.527508 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
345 11:51:46.541753 MRC: 'RECOVERY_MRC_CACHE' does not need update.
346 11:51:46.548565 cse_lite: Skip switching to RW in the recovery path
347 11:51:46.548994 8 DIMMs found
348 11:51:46.549399 SMM Memory Map
349 11:51:46.554975 SMRAM : 0x7b000000 0x800000
350 11:51:46.558633 Subregion 0: 0x7b000000 0x200000
351 11:51:46.561544 Subregion 1: 0x7b200000 0x200000
352 11:51:46.565231 Subregion 2: 0x7b400000 0x400000
353 11:51:46.565679 top_of_ram = 0x77000000
354 11:51:46.571737 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
355 11:51:46.578160 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
356 11:51:46.581704 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
357 11:51:46.588030 MTRR Range: Start=ff000000 End=0 (Size 1000000)
358 11:51:46.594747 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
359 11:51:46.601269 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
360 11:51:46.611317 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
361 11:51:46.617580 Processing 211 relocs. Offset value of 0x74c0b000
362 11:51:46.624287 BS: romstage times (exec / console): total (unknown) / 277 ms
363 11:51:46.630457
364 11:51:46.630543
365 11:51:46.641480 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
366 11:51:46.644676 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
367 11:51:46.651267 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
368 11:51:46.661396 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
369 11:51:46.667919 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
370 11:51:46.674415 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
371 11:51:46.720580 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
372 11:51:46.727380 Processing 5008 relocs. Offset value of 0x75d98000
373 11:51:46.730561 BS: postcar times (exec / console): total (unknown) / 59 ms
374 11:51:46.733587
375 11:51:46.733687
376 11:51:46.743607 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
377 11:51:46.743714 Normal boot
378 11:51:46.747299 FW_CONFIG value is 0x804c02
379 11:51:46.750320 PCI: 00:07.0 disabled by fw_config
380 11:51:46.754056 PCI: 00:07.1 disabled by fw_config
381 11:51:46.757040 PCI: 00:0d.2 disabled by fw_config
382 11:51:46.763721 PCI: 00:1c.7 disabled by fw_config
383 11:51:46.767311 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
384 11:51:46.773306 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
385 11:51:46.776696 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
386 11:51:46.783688 GENERIC: 0.0 disabled by fw_config
387 11:51:46.786563 GENERIC: 1.0 disabled by fw_config
388 11:51:46.789923 fw_config match found: DB_USB=USB3_ACTIVE
389 11:51:46.793365 fw_config match found: DB_USB=USB3_ACTIVE
390 11:51:46.796828 fw_config match found: DB_USB=USB3_ACTIVE
391 11:51:46.803282 fw_config match found: DB_USB=USB3_ACTIVE
392 11:51:46.806684 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
393 11:51:46.813273 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
394 11:51:46.823114 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
395 11:51:46.829936 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
396 11:51:46.832923 microcode: sig=0x806c1 pf=0x80 revision=0x86
397 11:51:46.839846 microcode: Update skipped, already up-to-date
398 11:51:46.846102 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
399 11:51:46.873837 Detected 4 core, 8 thread CPU.
400 11:51:46.877374 Setting up SMI for CPU
401 11:51:46.880848 IED base = 0x7b400000
402 11:51:46.880959 IED size = 0x00400000
403 11:51:46.884315 Will perform SMM setup.
404 11:51:46.890778 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
405 11:51:46.897085 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
406 11:51:46.903970 Processing 16 relocs. Offset value of 0x00030000
407 11:51:46.907563 Attempting to start 7 APs
408 11:51:46.910339 Waiting for 10ms after sending INIT.
409 11:51:46.925920 Waiting for 1st SIPI to complete...done.
410 11:51:46.926021 AP: slot 7 apic_id 7.
411 11:51:46.929669 AP: slot 3 apic_id 6.
412 11:51:46.932661 Waiting for 2nd SIPI to complete...done.
413 11:51:46.936267 AP: slot 1 apic_id 1.
414 11:51:46.939449 AP: slot 5 apic_id 4.
415 11:51:46.939535 AP: slot 2 apic_id 3.
416 11:51:46.942522 AP: slot 6 apic_id 2.
417 11:51:46.946261 AP: slot 4 apic_id 5.
418 11:51:46.953022 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
419 11:51:46.959223 Processing 13 relocs. Offset value of 0x00038000
420 11:51:46.963059 Unable to locate Global NVS
421 11:51:46.969654 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
422 11:51:46.972776 Installing permanent SMM handler to 0x7b000000
423 11:51:46.982861 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
424 11:51:46.985704 Processing 794 relocs. Offset value of 0x7b010000
425 11:51:46.996106 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
426 11:51:46.999271 Processing 13 relocs. Offset value of 0x7b008000
427 11:51:47.005834 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
428 11:51:47.012628 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
429 11:51:47.015619 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
430 11:51:47.022438 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
431 11:51:47.029221 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
432 11:51:47.035385 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
433 11:51:47.042149 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
434 11:51:47.042245 Unable to locate Global NVS
435 11:51:47.052060 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
436 11:51:47.055246 Clearing SMI status registers
437 11:51:47.055331 SMI_STS: PM1
438 11:51:47.058922 PM1_STS: PWRBTN
439 11:51:47.065772 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
440 11:51:47.068890 In relocation handler: CPU 0
441 11:51:47.071945 New SMBASE=0x7b000000 IEDBASE=0x7b400000
442 11:51:47.078861 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 11:51:47.078946 Relocation complete.
444 11:51:47.088358 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
445 11:51:47.091842 In relocation handler: CPU 1
446 11:51:47.095267 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
447 11:51:47.095353 Relocation complete.
448 11:51:47.105023 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
449 11:51:47.105110 In relocation handler: CPU 5
450 11:51:47.112095 New SMBASE=0x7affec00 IEDBASE=0x7b400000
451 11:51:47.116137 Writing SMRR. base = 0x7b000006, mask=0xff800c00
452 11:51:47.119630 Relocation complete.
453 11:51:47.126092 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
454 11:51:47.129606 In relocation handler: CPU 4
455 11:51:47.132694 New SMBASE=0x7afff000 IEDBASE=0x7b400000
456 11:51:47.135847 Relocation complete.
457 11:51:47.142727 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
458 11:51:47.145849 In relocation handler: CPU 2
459 11:51:47.149026 New SMBASE=0x7afff800 IEDBASE=0x7b400000
460 11:51:47.152781 Relocation complete.
461 11:51:47.159062 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
462 11:51:47.162802 In relocation handler: CPU 6
463 11:51:47.165834 New SMBASE=0x7affe800 IEDBASE=0x7b400000
464 11:51:47.168974 Writing SMRR. base = 0x7b000006, mask=0xff800c00
465 11:51:47.172691 Relocation complete.
466 11:51:47.178842 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
467 11:51:47.182484 In relocation handler: CPU 3
468 11:51:47.185525 New SMBASE=0x7afff400 IEDBASE=0x7b400000
469 11:51:47.191986 Writing SMRR. base = 0x7b000006, mask=0xff800c00
470 11:51:47.192071 Relocation complete.
471 11:51:47.202270 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
472 11:51:47.205495 In relocation handler: CPU 7
473 11:51:47.208771 New SMBASE=0x7affe400 IEDBASE=0x7b400000
474 11:51:47.208857 Relocation complete.
475 11:51:47.212275 Initializing CPU #0
476 11:51:47.215220 CPU: vendor Intel device 806c1
477 11:51:47.218997 CPU: family 06, model 8c, stepping 01
478 11:51:47.221795 Clearing out pending MCEs
479 11:51:47.225308 Setting up local APIC...
480 11:51:47.228636 apic_id: 0x00 done.
481 11:51:47.228724 Turbo is available but hidden
482 11:51:47.231788 Turbo is available and visible
483 11:51:47.238953 microcode: Update skipped, already up-to-date
484 11:51:47.239034 CPU #0 initialized
485 11:51:47.242002 Initializing CPU #4
486 11:51:47.244917 Initializing CPU #5
487 11:51:47.248684 CPU: vendor Intel device 806c1
488 11:51:47.251776 CPU: family 06, model 8c, stepping 01
489 11:51:47.254876 CPU: vendor Intel device 806c1
490 11:51:47.258534 CPU: family 06, model 8c, stepping 01
491 11:51:47.261707 Clearing out pending MCEs
492 11:51:47.261820 Clearing out pending MCEs
493 11:51:47.264712 Setting up local APIC...
494 11:51:47.268370 Initializing CPU #6
495 11:51:47.271636 Setting up local APIC...
496 11:51:47.274747 CPU: vendor Intel device 806c1
497 11:51:47.278338 CPU: family 06, model 8c, stepping 01
498 11:51:47.278422 Initializing CPU #2
499 11:51:47.281412 Clearing out pending MCEs
500 11:51:47.284564 CPU: vendor Intel device 806c1
501 11:51:47.288161 CPU: family 06, model 8c, stepping 01
502 11:51:47.291251 Setting up local APIC...
503 11:51:47.294895 apic_id: 0x04 done.
504 11:51:47.294981 Initializing CPU #7
505 11:51:47.298269 Initializing CPU #3
506 11:51:47.301396 CPU: vendor Intel device 806c1
507 11:51:47.304738 CPU: family 06, model 8c, stepping 01
508 11:51:47.308120 CPU: vendor Intel device 806c1
509 11:51:47.311666 CPU: family 06, model 8c, stepping 01
510 11:51:47.314510 Clearing out pending MCEs
511 11:51:47.318056 Clearing out pending MCEs
512 11:51:47.318142 apic_id: 0x05 done.
513 11:51:47.324653 microcode: Update skipped, already up-to-date
514 11:51:47.324740 Setting up local APIC...
515 11:51:47.327572 Initializing CPU #1
516 11:51:47.331065 Clearing out pending MCEs
517 11:51:47.331152 apic_id: 0x02 done.
518 11:51:47.334520 Setting up local APIC...
519 11:51:47.337965 CPU #5 initialized
520 11:51:47.340909 microcode: Update skipped, already up-to-date
521 11:51:47.348008 microcode: Update skipped, already up-to-date
522 11:51:47.348092 apic_id: 0x03 done.
523 11:51:47.351131 CPU #6 initialized
524 11:51:47.354233 microcode: Update skipped, already up-to-date
525 11:51:47.358014 CPU: vendor Intel device 806c1
526 11:51:47.361111 CPU: family 06, model 8c, stepping 01
527 11:51:47.364249 apic_id: 0x07 done.
528 11:51:47.367914 Setting up local APIC...
529 11:51:47.371004 Clearing out pending MCEs
530 11:51:47.371114 CPU #4 initialized
531 11:51:47.374142 Setting up local APIC...
532 11:51:47.377881 apic_id: 0x06 done.
533 11:51:47.380947 microcode: Update skipped, already up-to-date
534 11:51:47.383998 microcode: Update skipped, already up-to-date
535 11:51:47.387104 CPU #7 initialized
536 11:51:47.390836 CPU #3 initialized
537 11:51:47.390943 CPU #2 initialized
538 11:51:47.393926 apic_id: 0x01 done.
539 11:51:47.397094 microcode: Update skipped, already up-to-date
540 11:51:47.400763 CPU #1 initialized
541 11:51:47.403734 bsp_do_flight_plan done after 466 msecs.
542 11:51:47.407262 CPU: frequency set to 4000 MHz
543 11:51:47.407363 Enabling SMIs.
544 11:51:47.414087 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
545 11:51:47.431067 SATAXPCIE1 indicates PCIe NVMe is present
546 11:51:47.434406 Probing TPM: done!
547 11:51:47.437985 Connected to device vid:did:rid of 1ae0:0028:00
548 11:51:47.448401 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
549 11:51:47.451805 Initialized TPM device CR50 revision 0
550 11:51:47.455372 Enabling S0i3.4
551 11:51:47.461725 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
552 11:51:47.465511 Found a VBT of 8704 bytes after decompression
553 11:51:47.471697 cse_lite: CSE RO boot. HybridStorageMode disabled
554 11:51:47.478450 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
555 11:51:47.554985 FSPS returned 0
556 11:51:47.558501 Executing Phase 1 of FspMultiPhaseSiInit
557 11:51:47.568232 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
558 11:51:47.571317 port C0 DISC req: usage 1 usb3 1 usb2 5
559 11:51:47.575043 Raw Buffer output 0 00000511
560 11:51:47.578235 Raw Buffer output 1 00000000
561 11:51:47.582004 pmc_send_ipc_cmd succeeded
562 11:51:47.588835 port C1 DISC req: usage 1 usb3 2 usb2 3
563 11:51:47.589295 Raw Buffer output 0 00000321
564 11:51:47.591744 Raw Buffer output 1 00000000
565 11:51:47.596180 pmc_send_ipc_cmd succeeded
566 11:51:47.601151 Detected 4 core, 8 thread CPU.
567 11:51:47.604160 Detected 4 core, 8 thread CPU.
568 11:51:47.838341 Display FSP Version Info HOB
569 11:51:47.841751 Reference Code - CPU = a.0.4c.31
570 11:51:47.845280 uCode Version = 0.0.0.86
571 11:51:47.848227 TXT ACM version = ff.ff.ff.ffff
572 11:51:47.851578 Reference Code - ME = a.0.4c.31
573 11:51:47.855188 MEBx version = 0.0.0.0
574 11:51:47.858037 ME Firmware Version = Consumer SKU
575 11:51:47.861517 Reference Code - PCH = a.0.4c.31
576 11:51:47.864654 PCH-CRID Status = Disabled
577 11:51:47.868227 PCH-CRID Original Value = ff.ff.ff.ffff
578 11:51:47.871820 PCH-CRID New Value = ff.ff.ff.ffff
579 11:51:47.874590 OPROM - RST - RAID = ff.ff.ff.ffff
580 11:51:47.878192 PCH Hsio Version = 4.0.0.0
581 11:51:47.881224 Reference Code - SA - System Agent = a.0.4c.31
582 11:51:47.884872 Reference Code - MRC = 2.0.0.1
583 11:51:47.887969 SA - PCIe Version = a.0.4c.31
584 11:51:47.891067 SA-CRID Status = Disabled
585 11:51:47.894773 SA-CRID Original Value = 0.0.0.1
586 11:51:47.897895 SA-CRID New Value = 0.0.0.1
587 11:51:47.901493 OPROM - VBIOS = ff.ff.ff.ffff
588 11:51:47.904670 IO Manageability Engine FW Version = 11.1.4.0
589 11:51:47.907564 PHY Build Version = 0.0.0.e0
590 11:51:47.911156 Thunderbolt(TM) FW Version = 0.0.0.0
591 11:51:47.917487 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
592 11:51:47.921294 ITSS IRQ Polarities Before:
593 11:51:47.921729 IPC0: 0xffffffff
594 11:51:47.924424 IPC1: 0xffffffff
595 11:51:47.924897 IPC2: 0xffffffff
596 11:51:47.927495 IPC3: 0xffffffff
597 11:51:47.931293 ITSS IRQ Polarities After:
598 11:51:47.931730 IPC0: 0xffffffff
599 11:51:47.934307 IPC1: 0xffffffff
600 11:51:47.934743 IPC2: 0xffffffff
601 11:51:47.937871 IPC3: 0xffffffff
602 11:51:47.940862 Found PCIe Root Port #9 at PCI: 00:1d.0.
603 11:51:47.954174 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
604 11:51:47.964179 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
605 11:51:47.977083 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
606 11:51:47.984021 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
607 11:51:47.987072 Enumerating buses...
608 11:51:47.990169 Show all devs... Before device enumeration.
609 11:51:47.993932 Root Device: enabled 1
610 11:51:47.997054 DOMAIN: 0000: enabled 1
611 11:51:47.997487 CPU_CLUSTER: 0: enabled 1
612 11:51:48.000090 PCI: 00:00.0: enabled 1
613 11:51:48.003862 PCI: 00:02.0: enabled 1
614 11:51:48.006953 PCI: 00:04.0: enabled 1
615 11:51:48.007386 PCI: 00:05.0: enabled 1
616 11:51:48.010538 PCI: 00:06.0: enabled 0
617 11:51:48.013679 PCI: 00:07.0: enabled 0
618 11:51:48.014191 PCI: 00:07.1: enabled 0
619 11:51:48.017354 PCI: 00:07.2: enabled 0
620 11:51:48.020515 PCI: 00:07.3: enabled 0
621 11:51:48.023496 PCI: 00:08.0: enabled 1
622 11:51:48.023928 PCI: 00:09.0: enabled 0
623 11:51:48.027142 PCI: 00:0a.0: enabled 0
624 11:51:48.030246 PCI: 00:0d.0: enabled 1
625 11:51:48.033526 PCI: 00:0d.1: enabled 0
626 11:51:48.033959 PCI: 00:0d.2: enabled 0
627 11:51:48.036695 PCI: 00:0d.3: enabled 0
628 11:51:48.040220 PCI: 00:0e.0: enabled 0
629 11:51:48.043764 PCI: 00:10.2: enabled 1
630 11:51:48.044198 PCI: 00:10.6: enabled 0
631 11:51:48.046503 PCI: 00:10.7: enabled 0
632 11:51:48.050096 PCI: 00:12.0: enabled 0
633 11:51:48.050623 PCI: 00:12.6: enabled 0
634 11:51:48.053579 PCI: 00:13.0: enabled 0
635 11:51:48.056617 PCI: 00:14.0: enabled 1
636 11:51:48.060085 PCI: 00:14.1: enabled 0
637 11:51:48.060586 PCI: 00:14.2: enabled 1
638 11:51:48.063517 PCI: 00:14.3: enabled 1
639 11:51:48.066672 PCI: 00:15.0: enabled 1
640 11:51:48.070127 PCI: 00:15.1: enabled 1
641 11:51:48.070559 PCI: 00:15.2: enabled 1
642 11:51:48.073097 PCI: 00:15.3: enabled 1
643 11:51:48.076788 PCI: 00:16.0: enabled 1
644 11:51:48.080367 PCI: 00:16.1: enabled 0
645 11:51:48.080911 PCI: 00:16.2: enabled 0
646 11:51:48.083362 PCI: 00:16.3: enabled 0
647 11:51:48.086690 PCI: 00:16.4: enabled 0
648 11:51:48.090140 PCI: 00:16.5: enabled 0
649 11:51:48.090576 PCI: 00:17.0: enabled 1
650 11:51:48.093025 PCI: 00:19.0: enabled 0
651 11:51:48.096681 PCI: 00:19.1: enabled 1
652 11:51:48.097114 PCI: 00:19.2: enabled 0
653 11:51:48.099935 PCI: 00:1c.0: enabled 1
654 11:51:48.103042 PCI: 00:1c.1: enabled 0
655 11:51:48.106692 PCI: 00:1c.2: enabled 0
656 11:51:48.107128 PCI: 00:1c.3: enabled 0
657 11:51:48.110015 PCI: 00:1c.4: enabled 0
658 11:51:48.113105 PCI: 00:1c.5: enabled 0
659 11:51:48.116671 PCI: 00:1c.6: enabled 1
660 11:51:48.117176 PCI: 00:1c.7: enabled 0
661 11:51:48.119587 PCI: 00:1d.0: enabled 1
662 11:51:48.123322 PCI: 00:1d.1: enabled 0
663 11:51:48.126585 PCI: 00:1d.2: enabled 1
664 11:51:48.127019 PCI: 00:1d.3: enabled 0
665 11:51:48.129631 PCI: 00:1e.0: enabled 1
666 11:51:48.133363 PCI: 00:1e.1: enabled 0
667 11:51:48.136474 PCI: 00:1e.2: enabled 1
668 11:51:48.136909 PCI: 00:1e.3: enabled 1
669 11:51:48.139610 PCI: 00:1f.0: enabled 1
670 11:51:48.142709 PCI: 00:1f.1: enabled 0
671 11:51:48.143142 PCI: 00:1f.2: enabled 1
672 11:51:48.146610 PCI: 00:1f.3: enabled 1
673 11:51:48.149559 PCI: 00:1f.4: enabled 0
674 11:51:48.153160 PCI: 00:1f.5: enabled 1
675 11:51:48.153904 PCI: 00:1f.6: enabled 0
676 11:51:48.156475 PCI: 00:1f.7: enabled 0
677 11:51:48.159884 APIC: 00: enabled 1
678 11:51:48.162866 GENERIC: 0.0: enabled 1
679 11:51:48.163528 GENERIC: 0.0: enabled 1
680 11:51:48.166343 GENERIC: 1.0: enabled 1
681 11:51:48.169754 GENERIC: 0.0: enabled 1
682 11:51:48.170369 GENERIC: 1.0: enabled 1
683 11:51:48.172716 USB0 port 0: enabled 1
684 11:51:48.176254 GENERIC: 0.0: enabled 1
685 11:51:48.179774 USB0 port 0: enabled 1
686 11:51:48.180366 GENERIC: 0.0: enabled 1
687 11:51:48.182593 I2C: 00:1a: enabled 1
688 11:51:48.186179 I2C: 00:31: enabled 1
689 11:51:48.186866 I2C: 00:32: enabled 1
690 11:51:48.189264 I2C: 00:10: enabled 1
691 11:51:48.192894 I2C: 00:15: enabled 1
692 11:51:48.193607 GENERIC: 0.0: enabled 0
693 11:51:48.196289 GENERIC: 1.0: enabled 0
694 11:51:48.199408 GENERIC: 0.0: enabled 1
695 11:51:48.202438 SPI: 00: enabled 1
696 11:51:48.203124 SPI: 00: enabled 1
697 11:51:48.206007 PNP: 0c09.0: enabled 1
698 11:51:48.209132 GENERIC: 0.0: enabled 1
699 11:51:48.209595 USB3 port 0: enabled 1
700 11:51:48.212832 USB3 port 1: enabled 1
701 11:51:48.215827 USB3 port 2: enabled 0
702 11:51:48.216230 USB3 port 3: enabled 0
703 11:51:48.219508 USB2 port 0: enabled 0
704 11:51:48.222523 USB2 port 1: enabled 1
705 11:51:48.222945 USB2 port 2: enabled 1
706 11:51:48.225631 USB2 port 3: enabled 0
707 11:51:48.229427 USB2 port 4: enabled 1
708 11:51:48.232697 USB2 port 5: enabled 0
709 11:51:48.233163 USB2 port 6: enabled 0
710 11:51:48.235708 USB2 port 7: enabled 0
711 11:51:48.239404 USB2 port 8: enabled 0
712 11:51:48.239849 USB2 port 9: enabled 0
713 11:51:48.242474 USB3 port 0: enabled 0
714 11:51:48.245545 USB3 port 1: enabled 1
715 11:51:48.249276 USB3 port 2: enabled 0
716 11:51:48.249695 USB3 port 3: enabled 0
717 11:51:48.252363 GENERIC: 0.0: enabled 1
718 11:51:48.255956 GENERIC: 1.0: enabled 1
719 11:51:48.256409 APIC: 01: enabled 1
720 11:51:48.258909 APIC: 03: enabled 1
721 11:51:48.262326 APIC: 06: enabled 1
722 11:51:48.262735 APIC: 05: enabled 1
723 11:51:48.265708 APIC: 04: enabled 1
724 11:51:48.266151 APIC: 02: enabled 1
725 11:51:48.268675 APIC: 07: enabled 1
726 11:51:48.272233 Compare with tree...
727 11:51:48.272702 Root Device: enabled 1
728 11:51:48.275488 DOMAIN: 0000: enabled 1
729 11:51:48.278943 PCI: 00:00.0: enabled 1
730 11:51:48.282541 PCI: 00:02.0: enabled 1
731 11:51:48.285593 PCI: 00:04.0: enabled 1
732 11:51:48.285917 GENERIC: 0.0: enabled 1
733 11:51:48.289002 PCI: 00:05.0: enabled 1
734 11:51:48.292381 PCI: 00:06.0: enabled 0
735 11:51:48.295723 PCI: 00:07.0: enabled 0
736 11:51:48.299257 GENERIC: 0.0: enabled 1
737 11:51:48.299577 PCI: 00:07.1: enabled 0
738 11:51:48.302238 GENERIC: 1.0: enabled 1
739 11:51:48.305409 PCI: 00:07.2: enabled 0
740 11:51:48.309123 GENERIC: 0.0: enabled 1
741 11:51:48.312298 PCI: 00:07.3: enabled 0
742 11:51:48.312652 GENERIC: 1.0: enabled 1
743 11:51:48.315336 PCI: 00:08.0: enabled 1
744 11:51:48.319097 PCI: 00:09.0: enabled 0
745 11:51:48.322119 PCI: 00:0a.0: enabled 0
746 11:51:48.325658 PCI: 00:0d.0: enabled 1
747 11:51:48.325998 USB0 port 0: enabled 1
748 11:51:48.328745 USB3 port 0: enabled 1
749 11:51:48.331859 USB3 port 1: enabled 1
750 11:51:48.335453 USB3 port 2: enabled 0
751 11:51:48.338519 USB3 port 3: enabled 0
752 11:51:48.342321 PCI: 00:0d.1: enabled 0
753 11:51:48.342643 PCI: 00:0d.2: enabled 0
754 11:51:48.345419 GENERIC: 0.0: enabled 1
755 11:51:48.348417 PCI: 00:0d.3: enabled 0
756 11:51:48.352197 PCI: 00:0e.0: enabled 0
757 11:51:48.355996 PCI: 00:10.2: enabled 1
758 11:51:48.356346 PCI: 00:10.6: enabled 0
759 11:51:48.359845 PCI: 00:10.7: enabled 0
760 11:51:48.362632 PCI: 00:12.0: enabled 0
761 11:51:48.363068 PCI: 00:12.6: enabled 0
762 11:51:48.366199 PCI: 00:13.0: enabled 0
763 11:51:48.368994 PCI: 00:14.0: enabled 1
764 11:51:48.372474 USB0 port 0: enabled 1
765 11:51:48.422310 USB2 port 0: enabled 0
766 11:51:48.422685 USB2 port 1: enabled 1
767 11:51:48.422946 USB2 port 2: enabled 1
768 11:51:48.423188 USB2 port 3: enabled 0
769 11:51:48.423431 USB2 port 4: enabled 1
770 11:51:48.423941 USB2 port 5: enabled 0
771 11:51:48.424183 USB2 port 6: enabled 0
772 11:51:48.424406 USB2 port 7: enabled 0
773 11:51:48.424659 USB2 port 8: enabled 0
774 11:51:48.424882 USB2 port 9: enabled 0
775 11:51:48.425097 USB3 port 0: enabled 0
776 11:51:48.425310 USB3 port 1: enabled 1
777 11:51:48.425521 USB3 port 2: enabled 0
778 11:51:48.425740 USB3 port 3: enabled 0
779 11:51:48.426008 PCI: 00:14.1: enabled 0
780 11:51:48.426221 PCI: 00:14.2: enabled 1
781 11:51:48.426430 PCI: 00:14.3: enabled 1
782 11:51:48.426638 GENERIC: 0.0: enabled 1
783 11:51:48.426897 PCI: 00:15.0: enabled 1
784 11:51:48.471988 I2C: 00:1a: enabled 1
785 11:51:48.472123 I2C: 00:31: enabled 1
786 11:51:48.472380 I2C: 00:32: enabled 1
787 11:51:48.472465 PCI: 00:15.1: enabled 1
788 11:51:48.472536 I2C: 00:10: enabled 1
789 11:51:48.472600 PCI: 00:15.2: enabled 1
790 11:51:48.472662 PCI: 00:15.3: enabled 1
791 11:51:48.472722 PCI: 00:16.0: enabled 1
792 11:51:48.472780 PCI: 00:16.1: enabled 0
793 11:51:48.472851 PCI: 00:16.2: enabled 0
794 11:51:48.472912 PCI: 00:16.3: enabled 0
795 11:51:48.472971 PCI: 00:16.4: enabled 0
796 11:51:48.473030 PCI: 00:16.5: enabled 0
797 11:51:48.473087 PCI: 00:17.0: enabled 1
798 11:51:48.473144 PCI: 00:19.0: enabled 0
799 11:51:48.473201 PCI: 00:19.1: enabled 1
800 11:51:48.473269 I2C: 00:15: enabled 1
801 11:51:48.473332 PCI: 00:19.2: enabled 0
802 11:51:48.473394 PCI: 00:1d.0: enabled 1
803 11:51:48.515136 GENERIC: 0.0: enabled 1
804 11:51:48.515300 PCI: 00:1e.0: enabled 1
805 11:51:48.515569 PCI: 00:1e.1: enabled 0
806 11:51:48.515644 PCI: 00:1e.2: enabled 1
807 11:51:48.515722 SPI: 00: enabled 1
808 11:51:48.515821 PCI: 00:1e.3: enabled 1
809 11:51:48.515889 SPI: 00: enabled 1
810 11:51:48.515953 PCI: 00:1f.0: enabled 1
811 11:51:48.516013 PNP: 0c09.0: enabled 1
812 11:51:48.516072 PCI: 00:1f.1: enabled 0
813 11:51:48.516329 PCI: 00:1f.2: enabled 1
814 11:51:48.516444 GENERIC: 0.0: enabled 1
815 11:51:48.516527 GENERIC: 0.0: enabled 1
816 11:51:48.516609 GENERIC: 1.0: enabled 1
817 11:51:48.516683 PCI: 00:1f.3: enabled 1
818 11:51:48.516744 PCI: 00:1f.4: enabled 0
819 11:51:48.520019 PCI: 00:1f.5: enabled 1
820 11:51:48.520133 PCI: 00:1f.6: enabled 0
821 11:51:48.523127 PCI: 00:1f.7: enabled 0
822 11:51:48.526877 CPU_CLUSTER: 0: enabled 1
823 11:51:48.526964 APIC: 00: enabled 1
824 11:51:48.529768 APIC: 01: enabled 1
825 11:51:48.533448 APIC: 03: enabled 1
826 11:51:48.533535 APIC: 06: enabled 1
827 11:51:48.536260 APIC: 05: enabled 1
828 11:51:48.539990 APIC: 04: enabled 1
829 11:51:48.543085 APIC: 02: enabled 1
830 11:51:48.543210 APIC: 07: enabled 1
831 11:51:48.546853 Root Device scanning...
832 11:51:48.550116 scan_static_bus for Root Device
833 11:51:48.553773 DOMAIN: 0000 enabled
834 11:51:48.557428 CPU_CLUSTER: 0 enabled
835 11:51:48.557543 DOMAIN: 0000 scanning...
836 11:51:48.559919 PCI: pci_scan_bus for bus 00
837 11:51:48.563741 PCI: 00:00.0 [8086/0000] ops
838 11:51:48.566819 PCI: 00:00.0 [8086/9a12] enabled
839 11:51:48.569911 PCI: 00:02.0 [8086/0000] bus ops
840 11:51:48.573128 PCI: 00:02.0 [8086/9a40] enabled
841 11:51:48.576820 PCI: 00:04.0 [8086/0000] bus ops
842 11:51:48.579821 PCI: 00:04.0 [8086/9a03] enabled
843 11:51:48.583179 PCI: 00:05.0 [8086/9a19] enabled
844 11:51:48.586833 PCI: 00:07.0 [0000/0000] hidden
845 11:51:48.589567 PCI: 00:08.0 [8086/9a11] enabled
846 11:51:48.592894 PCI: 00:0a.0 [8086/9a0d] disabled
847 11:51:48.596556 PCI: 00:0d.0 [8086/0000] bus ops
848 11:51:48.599911 PCI: 00:0d.0 [8086/9a13] enabled
849 11:51:48.602877 PCI: 00:14.0 [8086/0000] bus ops
850 11:51:48.606300 PCI: 00:14.0 [8086/a0ed] enabled
851 11:51:48.609286 PCI: 00:14.2 [8086/a0ef] enabled
852 11:51:48.612751 PCI: 00:14.3 [8086/0000] bus ops
853 11:51:48.616294 PCI: 00:14.3 [8086/a0f0] enabled
854 11:51:48.619269 PCI: 00:15.0 [8086/0000] bus ops
855 11:51:48.622604 PCI: 00:15.0 [8086/a0e8] enabled
856 11:51:48.626255 PCI: 00:15.1 [8086/0000] bus ops
857 11:51:48.629312 PCI: 00:15.1 [8086/a0e9] enabled
858 11:51:48.633073 PCI: 00:15.2 [8086/0000] bus ops
859 11:51:48.636167 PCI: 00:15.2 [8086/a0ea] enabled
860 11:51:48.639792 PCI: 00:15.3 [8086/0000] bus ops
861 11:51:48.642895 PCI: 00:15.3 [8086/a0eb] enabled
862 11:51:48.646013 PCI: 00:16.0 [8086/0000] ops
863 11:51:48.649698 PCI: 00:16.0 [8086/a0e0] enabled
864 11:51:48.655888 PCI: Static device PCI: 00:17.0 not found, disabling it.
865 11:51:48.658991 PCI: 00:19.0 [8086/0000] bus ops
866 11:51:48.662741 PCI: 00:19.0 [8086/a0c5] disabled
867 11:51:48.665805 PCI: 00:19.1 [8086/0000] bus ops
868 11:51:48.668977 PCI: 00:19.1 [8086/a0c6] enabled
869 11:51:48.672773 PCI: 00:1d.0 [8086/0000] bus ops
870 11:51:48.675939 PCI: 00:1d.0 [8086/a0b0] enabled
871 11:51:48.678948 PCI: 00:1e.0 [8086/0000] ops
872 11:51:48.682659 PCI: 00:1e.0 [8086/a0a8] enabled
873 11:51:48.685643 PCI: 00:1e.2 [8086/0000] bus ops
874 11:51:48.689272 PCI: 00:1e.2 [8086/a0aa] enabled
875 11:51:48.692670 PCI: 00:1e.3 [8086/0000] bus ops
876 11:51:48.695539 PCI: 00:1e.3 [8086/a0ab] enabled
877 11:51:48.698976 PCI: 00:1f.0 [8086/0000] bus ops
878 11:51:48.702194 PCI: 00:1f.0 [8086/a087] enabled
879 11:51:48.702277 RTC Init
880 11:51:48.709297 Set power on after power failure.
881 11:51:48.709376 Disabling Deep S3
882 11:51:48.712326 Disabling Deep S3
883 11:51:48.712465 Disabling Deep S4
884 11:51:48.715693 Disabling Deep S4
885 11:51:48.715794 Disabling Deep S5
886 11:51:48.719097 Disabling Deep S5
887 11:51:48.722626 PCI: 00:1f.2 [0000/0000] hidden
888 11:51:48.725933 PCI: 00:1f.3 [8086/0000] bus ops
889 11:51:48.728773 PCI: 00:1f.3 [8086/a0c8] enabled
890 11:51:48.732202 PCI: 00:1f.5 [8086/0000] bus ops
891 11:51:48.735340 PCI: 00:1f.5 [8086/a0a4] enabled
892 11:51:48.738994 PCI: Leftover static devices:
893 11:51:48.739068 PCI: 00:10.2
894 11:51:48.742039 PCI: 00:10.6
895 11:51:48.742121 PCI: 00:10.7
896 11:51:48.745630 PCI: 00:06.0
897 11:51:48.745706 PCI: 00:07.1
898 11:51:48.745769 PCI: 00:07.2
899 11:51:48.748694 PCI: 00:07.3
900 11:51:48.748847 PCI: 00:09.0
901 11:51:48.751843 PCI: 00:0d.1
902 11:51:48.751925 PCI: 00:0d.2
903 11:51:48.751997 PCI: 00:0d.3
904 11:51:48.755599 PCI: 00:0e.0
905 11:51:48.755673 PCI: 00:12.0
906 11:51:48.758650 PCI: 00:12.6
907 11:51:48.758773 PCI: 00:13.0
908 11:51:48.762320 PCI: 00:14.1
909 11:51:48.762393 PCI: 00:16.1
910 11:51:48.762454 PCI: 00:16.2
911 11:51:48.765458 PCI: 00:16.3
912 11:51:48.765542 PCI: 00:16.4
913 11:51:48.768548 PCI: 00:16.5
914 11:51:48.768620 PCI: 00:17.0
915 11:51:48.768697 PCI: 00:19.2
916 11:51:48.771646 PCI: 00:1e.1
917 11:51:48.771725 PCI: 00:1f.1
918 11:51:48.775288 PCI: 00:1f.4
919 11:51:48.775366 PCI: 00:1f.6
920 11:51:48.778398 PCI: 00:1f.7
921 11:51:48.778477 PCI: Check your devicetree.cb.
922 11:51:48.781591 PCI: 00:02.0 scanning...
923 11:51:48.785270 scan_generic_bus for PCI: 00:02.0
924 11:51:48.792000 scan_generic_bus for PCI: 00:02.0 done
925 11:51:48.795043 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
926 11:51:48.798105 PCI: 00:04.0 scanning...
927 11:51:48.801464 scan_generic_bus for PCI: 00:04.0
928 11:51:48.801543 GENERIC: 0.0 enabled
929 11:51:48.808082 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
930 11:51:48.815105 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
931 11:51:48.815226 PCI: 00:0d.0 scanning...
932 11:51:48.818535 scan_static_bus for PCI: 00:0d.0
933 11:51:48.822083 USB0 port 0 enabled
934 11:51:48.824912 USB0 port 0 scanning...
935 11:51:48.828250 scan_static_bus for USB0 port 0
936 11:51:48.831847 USB3 port 0 enabled
937 11:51:48.831925 USB3 port 1 enabled
938 11:51:48.834959 USB3 port 2 disabled
939 11:51:48.835066 USB3 port 3 disabled
940 11:51:48.838474 USB3 port 0 scanning...
941 11:51:48.841969 scan_static_bus for USB3 port 0
942 11:51:48.844972 scan_static_bus for USB3 port 0 done
943 11:51:48.851741 scan_bus: bus USB3 port 0 finished in 6 msecs
944 11:51:48.851825 USB3 port 1 scanning...
945 11:51:48.854807 scan_static_bus for USB3 port 1
946 11:51:48.861761 scan_static_bus for USB3 port 1 done
947 11:51:48.864814 scan_bus: bus USB3 port 1 finished in 6 msecs
948 11:51:48.868650 scan_static_bus for USB0 port 0 done
949 11:51:48.871660 scan_bus: bus USB0 port 0 finished in 43 msecs
950 11:51:48.878625 scan_static_bus for PCI: 00:0d.0 done
951 11:51:48.881774 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
952 11:51:48.884780 PCI: 00:14.0 scanning...
953 11:51:48.888425 scan_static_bus for PCI: 00:14.0
954 11:51:48.891580 USB0 port 0 enabled
955 11:51:48.891671 USB0 port 0 scanning...
956 11:51:48.894558 scan_static_bus for USB0 port 0
957 11:51:48.898286 USB2 port 0 disabled
958 11:51:48.901377 USB2 port 1 enabled
959 11:51:48.901492 USB2 port 2 enabled
960 11:51:48.905019 USB2 port 3 disabled
961 11:51:48.905133 USB2 port 4 enabled
962 11:51:48.907965 USB2 port 5 disabled
963 11:51:48.911371 USB2 port 6 disabled
964 11:51:48.911485 USB2 port 7 disabled
965 11:51:48.914932 USB2 port 8 disabled
966 11:51:48.917819 USB2 port 9 disabled
967 11:51:48.917936 USB3 port 0 disabled
968 11:51:48.921220 USB3 port 1 enabled
969 11:51:48.924922 USB3 port 2 disabled
970 11:51:48.925005 USB3 port 3 disabled
971 11:51:48.928173 USB2 port 1 scanning...
972 11:51:48.931127 scan_static_bus for USB2 port 1
973 11:51:48.935186 scan_static_bus for USB2 port 1 done
974 11:51:48.938689 scan_bus: bus USB2 port 1 finished in 6 msecs
975 11:51:48.942190 USB2 port 2 scanning...
976 11:51:48.945108 scan_static_bus for USB2 port 2
977 11:51:48.948565 scan_static_bus for USB2 port 2 done
978 11:51:48.955249 scan_bus: bus USB2 port 2 finished in 6 msecs
979 11:51:48.955331 USB2 port 4 scanning...
980 11:51:48.958371 scan_static_bus for USB2 port 4
981 11:51:48.965280 scan_static_bus for USB2 port 4 done
982 11:51:48.968413 scan_bus: bus USB2 port 4 finished in 6 msecs
983 11:51:48.972002 USB3 port 1 scanning...
984 11:51:48.975109 scan_static_bus for USB3 port 1
985 11:51:48.978212 scan_static_bus for USB3 port 1 done
986 11:51:48.981347 scan_bus: bus USB3 port 1 finished in 6 msecs
987 11:51:48.984514 scan_static_bus for USB0 port 0 done
988 11:51:48.991358 scan_bus: bus USB0 port 0 finished in 93 msecs
989 11:51:48.995003 scan_static_bus for PCI: 00:14.0 done
990 11:51:48.997950 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
991 11:51:49.001182 PCI: 00:14.3 scanning...
992 11:51:49.004965 scan_static_bus for PCI: 00:14.3
993 11:51:49.008073 GENERIC: 0.0 enabled
994 11:51:49.011061 scan_static_bus for PCI: 00:14.3 done
995 11:51:49.018059 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
996 11:51:49.018213 PCI: 00:15.0 scanning...
997 11:51:49.020790 scan_static_bus for PCI: 00:15.0
998 11:51:49.024479 I2C: 00:1a enabled
999 11:51:49.027834 I2C: 00:31 enabled
1000 11:51:49.027940 I2C: 00:32 enabled
1001 11:51:49.030844 scan_static_bus for PCI: 00:15.0 done
1002 11:51:49.037689 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1003 11:51:49.041006 PCI: 00:15.1 scanning...
1004 11:51:49.044049 scan_static_bus for PCI: 00:15.1
1005 11:51:49.044235 I2C: 00:10 enabled
1006 11:51:49.047276 scan_static_bus for PCI: 00:15.1 done
1007 11:51:49.054264 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1008 11:51:49.057142 PCI: 00:15.2 scanning...
1009 11:51:49.060338 scan_static_bus for PCI: 00:15.2
1010 11:51:49.064067 scan_static_bus for PCI: 00:15.2 done
1011 11:51:49.067165 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1012 11:51:49.070196 PCI: 00:15.3 scanning...
1013 11:51:49.073900 scan_static_bus for PCI: 00:15.3
1014 11:51:49.077064 scan_static_bus for PCI: 00:15.3 done
1015 11:51:49.083971 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1016 11:51:49.084049 PCI: 00:19.1 scanning...
1017 11:51:49.086903 scan_static_bus for PCI: 00:19.1
1018 11:51:49.090087 I2C: 00:15 enabled
1019 11:51:49.093882 scan_static_bus for PCI: 00:19.1 done
1020 11:51:49.100034 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1021 11:51:49.100146 PCI: 00:1d.0 scanning...
1022 11:51:49.106713 do_pci_scan_bridge for PCI: 00:1d.0
1023 11:51:49.106833 PCI: pci_scan_bus for bus 01
1024 11:51:49.113601 PCI: 01:00.0 [1c5c/174a] enabled
1025 11:51:49.113701 GENERIC: 0.0 enabled
1026 11:51:49.116739 Enabling Common Clock Configuration
1027 11:51:49.123268 L1 Sub-State supported from root port 29
1028 11:51:49.123363 L1 Sub-State Support = 0xf
1029 11:51:49.126709 CommonModeRestoreTime = 0x28
1030 11:51:49.133482 Power On Value = 0x16, Power On Scale = 0x0
1031 11:51:49.133570 ASPM: Enabled L1
1032 11:51:49.136318 PCIe: Max_Payload_Size adjusted to 128
1033 11:51:49.142817 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1034 11:51:49.146268 PCI: 00:1e.2 scanning...
1035 11:51:49.149809 scan_generic_bus for PCI: 00:1e.2
1036 11:51:49.149892 SPI: 00 enabled
1037 11:51:49.155965 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1038 11:51:49.162737 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1039 11:51:49.162865 PCI: 00:1e.3 scanning...
1040 11:51:49.166271 scan_generic_bus for PCI: 00:1e.3
1041 11:51:49.169732 SPI: 00 enabled
1042 11:51:49.175803 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1043 11:51:49.179575 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1044 11:51:49.182693 PCI: 00:1f.0 scanning...
1045 11:51:49.185798 scan_static_bus for PCI: 00:1f.0
1046 11:51:49.189624 PNP: 0c09.0 enabled
1047 11:51:49.189760 PNP: 0c09.0 scanning...
1048 11:51:49.192862 scan_static_bus for PNP: 0c09.0
1049 11:51:49.199549 scan_static_bus for PNP: 0c09.0 done
1050 11:51:49.202730 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1051 11:51:49.206290 scan_static_bus for PCI: 00:1f.0 done
1052 11:51:49.212421 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1053 11:51:49.212869 PCI: 00:1f.2 scanning...
1054 11:51:49.216245 scan_static_bus for PCI: 00:1f.2
1055 11:51:49.219479 GENERIC: 0.0 enabled
1056 11:51:49.222537 GENERIC: 0.0 scanning...
1057 11:51:49.226207 scan_static_bus for GENERIC: 0.0
1058 11:51:49.229495 GENERIC: 0.0 enabled
1059 11:51:49.229899 GENERIC: 1.0 enabled
1060 11:51:49.232600 scan_static_bus for GENERIC: 0.0 done
1061 11:51:49.239279 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1062 11:51:49.242680 scan_static_bus for PCI: 00:1f.2 done
1063 11:51:49.246106 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1064 11:51:49.249036 PCI: 00:1f.3 scanning...
1065 11:51:49.252151 scan_static_bus for PCI: 00:1f.3
1066 11:51:49.255662 scan_static_bus for PCI: 00:1f.3 done
1067 11:51:49.262408 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1068 11:51:49.265408 PCI: 00:1f.5 scanning...
1069 11:51:49.269248 scan_generic_bus for PCI: 00:1f.5
1070 11:51:49.271971 scan_generic_bus for PCI: 00:1f.5 done
1071 11:51:49.275459 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1072 11:51:49.282420 scan_bus: bus DOMAIN: 0000 finished in 718 msecs
1073 11:51:49.285503 scan_static_bus for Root Device done
1074 11:51:49.288667 scan_bus: bus Root Device finished in 737 msecs
1075 11:51:49.292382 done
1076 11:51:49.295561 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1077 11:51:49.298645 Chrome EC: UHEPI supported
1078 11:51:49.305564 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1079 11:51:49.312133 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1080 11:51:49.315800 SPI flash protection: WPSW=0 SRP0=0
1081 11:51:49.322034 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1082 11:51:49.325773 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1083 11:51:49.328853 found VGA at PCI: 00:02.0
1084 11:51:49.331861 Setting up VGA for PCI: 00:02.0
1085 11:51:49.338732 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1086 11:51:49.341809 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1087 11:51:49.345310 Allocating resources...
1088 11:51:49.348825 Reading resources...
1089 11:51:49.351926 Root Device read_resources bus 0 link: 0
1090 11:51:49.355256 DOMAIN: 0000 read_resources bus 0 link: 0
1091 11:51:49.362066 PCI: 00:04.0 read_resources bus 1 link: 0
1092 11:51:49.364980 PCI: 00:04.0 read_resources bus 1 link: 0 done
1093 11:51:49.371881 PCI: 00:0d.0 read_resources bus 0 link: 0
1094 11:51:49.375227 USB0 port 0 read_resources bus 0 link: 0
1095 11:51:49.381895 USB0 port 0 read_resources bus 0 link: 0 done
1096 11:51:49.385292 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1097 11:51:49.391743 PCI: 00:14.0 read_resources bus 0 link: 0
1098 11:51:49.394975 USB0 port 0 read_resources bus 0 link: 0
1099 11:51:49.401738 USB0 port 0 read_resources bus 0 link: 0 done
1100 11:51:49.404898 PCI: 00:14.0 read_resources bus 0 link: 0 done
1101 11:51:49.411647 PCI: 00:14.3 read_resources bus 0 link: 0
1102 11:51:49.414449 PCI: 00:14.3 read_resources bus 0 link: 0 done
1103 11:51:49.421182 PCI: 00:15.0 read_resources bus 0 link: 0
1104 11:51:49.425009 PCI: 00:15.0 read_resources bus 0 link: 0 done
1105 11:51:49.431234 PCI: 00:15.1 read_resources bus 0 link: 0
1106 11:51:49.434335 PCI: 00:15.1 read_resources bus 0 link: 0 done
1107 11:51:49.441518 PCI: 00:19.1 read_resources bus 0 link: 0
1108 11:51:49.444542 PCI: 00:19.1 read_resources bus 0 link: 0 done
1109 11:51:49.451180 PCI: 00:1d.0 read_resources bus 1 link: 0
1110 11:51:49.454214 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1111 11:51:49.461325 PCI: 00:1e.2 read_resources bus 2 link: 0
1112 11:51:49.464490 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1113 11:51:49.471443 PCI: 00:1e.3 read_resources bus 3 link: 0
1114 11:51:49.474811 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1115 11:51:49.481130 PCI: 00:1f.0 read_resources bus 0 link: 0
1116 11:51:49.484476 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1117 11:51:49.491281 PCI: 00:1f.2 read_resources bus 0 link: 0
1118 11:51:49.494116 GENERIC: 0.0 read_resources bus 0 link: 0
1119 11:51:49.500533 GENERIC: 0.0 read_resources bus 0 link: 0 done
1120 11:51:49.504286 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1121 11:51:49.511069 DOMAIN: 0000 read_resources bus 0 link: 0 done
1122 11:51:49.514222 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1123 11:51:49.521066 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1124 11:51:49.523952 Root Device read_resources bus 0 link: 0 done
1125 11:51:49.527153 Done reading resources.
1126 11:51:49.533988 Show resources in subtree (Root Device)...After reading.
1127 11:51:49.537169 Root Device child on link 0 DOMAIN: 0000
1128 11:51:49.540650 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1129 11:51:49.550459 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1130 11:51:49.560309 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1131 11:51:49.560808 PCI: 00:00.0
1132 11:51:49.570429 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1133 11:51:49.580216 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1134 11:51:49.590506 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1135 11:51:49.600040 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1136 11:51:49.609914 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1137 11:51:49.619983 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1138 11:51:49.626548 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1139 11:51:49.636401 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1140 11:51:49.646881 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1141 11:51:49.656398 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1142 11:51:49.666426 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1143 11:51:49.673204 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1144 11:51:49.683039 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1145 11:51:49.693338 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1146 11:51:49.703039 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1147 11:51:49.713237 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1148 11:51:49.722880 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1149 11:51:49.732608 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1150 11:51:49.739359 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1151 11:51:49.749480 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1152 11:51:49.752448 PCI: 00:02.0
1153 11:51:49.762939 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 11:51:49.772813 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1155 11:51:49.782810 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1156 11:51:49.785747 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 11:51:49.795611 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 11:51:49.796223 GENERIC: 0.0
1159 11:51:49.799019 PCI: 00:05.0
1160 11:51:49.808819 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 11:51:49.812130 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 11:51:49.815395 GENERIC: 0.0
1163 11:51:49.815841 PCI: 00:08.0
1164 11:51:49.825747 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 11:51:49.828747 PCI: 00:0a.0
1166 11:51:49.831870 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 11:51:49.842143 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 11:51:49.848928 USB0 port 0 child on link 0 USB3 port 0
1169 11:51:49.849373 USB3 port 0
1170 11:51:49.852041 USB3 port 1
1171 11:51:49.852517 USB3 port 2
1172 11:51:49.855105 USB3 port 3
1173 11:51:49.858593 PCI: 00:14.0 child on link 0 USB0 port 0
1174 11:51:49.868592 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1175 11:51:49.875271 USB0 port 0 child on link 0 USB2 port 0
1176 11:51:49.875740 USB2 port 0
1177 11:51:49.878378 USB2 port 1
1178 11:51:49.878776 USB2 port 2
1179 11:51:49.881597 USB2 port 3
1180 11:51:49.882039 USB2 port 4
1181 11:51:49.884653 USB2 port 5
1182 11:51:49.885087 USB2 port 6
1183 11:51:49.888397 USB2 port 7
1184 11:51:49.888875 USB2 port 8
1185 11:51:49.891382 USB2 port 9
1186 11:51:49.891841 USB3 port 0
1187 11:51:49.895127 USB3 port 1
1188 11:51:49.898474 USB3 port 2
1189 11:51:49.898905 USB3 port 3
1190 11:51:49.901288 PCI: 00:14.2
1191 11:51:49.911571 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1192 11:51:49.921361 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1193 11:51:49.924889 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1194 11:51:49.934737 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1195 11:51:49.935170 GENERIC: 0.0
1196 11:51:49.940793 PCI: 00:15.0 child on link 0 I2C: 00:1a
1197 11:51:49.951237 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 11:51:49.951695 I2C: 00:1a
1199 11:51:49.954239 I2C: 00:31
1200 11:51:49.954700 I2C: 00:32
1201 11:51:49.961061 PCI: 00:15.1 child on link 0 I2C: 00:10
1202 11:51:49.970629 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 11:51:49.971063 I2C: 00:10
1204 11:51:49.974390 PCI: 00:15.2
1205 11:51:49.984173 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 11:51:49.984993 PCI: 00:15.3
1207 11:51:49.994089 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1208 11:51:49.997395 PCI: 00:16.0
1209 11:51:50.007255 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 11:51:50.007856 PCI: 00:19.0
1211 11:51:50.010669 PCI: 00:19.1 child on link 0 I2C: 00:15
1212 11:51:50.020490 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 11:51:50.023889 I2C: 00:15
1214 11:51:50.026807 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1215 11:51:50.037072 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1216 11:51:50.046893 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1217 11:51:50.056573 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1218 11:51:50.057026 GENERIC: 0.0
1219 11:51:50.060210 PCI: 01:00.0
1220 11:51:50.069720 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1221 11:51:50.076514 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1222 11:51:50.086404 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1223 11:51:50.090167 PCI: 00:1e.0
1224 11:51:50.099997 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1225 11:51:50.103097 PCI: 00:1e.2 child on link 0 SPI: 00
1226 11:51:50.113341 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 11:51:50.116375 SPI: 00
1228 11:51:50.119832 PCI: 00:1e.3 child on link 0 SPI: 00
1229 11:51:50.129878 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 11:51:50.130484 SPI: 00
1231 11:51:50.136133 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1232 11:51:50.142742 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1233 11:51:50.146168 PNP: 0c09.0
1234 11:51:50.152499 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1235 11:51:50.159417 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1236 11:51:50.169380 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1237 11:51:50.175936 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1238 11:51:50.182676 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1239 11:51:50.183117 GENERIC: 0.0
1240 11:51:50.185843 GENERIC: 1.0
1241 11:51:50.186274 PCI: 00:1f.3
1242 11:51:50.195754 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1243 11:51:50.208704 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1244 11:51:50.209365 PCI: 00:1f.5
1245 11:51:50.218834 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1246 11:51:50.221896 CPU_CLUSTER: 0 child on link 0 APIC: 00
1247 11:51:50.225634 APIC: 00
1248 11:51:50.226252 APIC: 01
1249 11:51:50.226816 APIC: 03
1250 11:51:50.228341 APIC: 06
1251 11:51:50.228923 APIC: 05
1252 11:51:50.229336 APIC: 04
1253 11:51:50.231983 APIC: 02
1254 11:51:50.232780 APIC: 07
1255 11:51:50.242031 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1256 11:51:50.245330 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1257 11:51:50.251614 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1258 11:51:50.258542 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1259 11:51:50.261537 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1260 11:51:50.268368 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1261 11:51:50.271481 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1262 11:51:50.278530 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1263 11:51:50.285400 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1264 11:51:50.295042 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1265 11:51:50.301513 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1266 11:51:50.308331 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1267 11:51:50.315031 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1268 11:51:50.321436 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1269 11:51:50.328153 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1270 11:51:50.331119 DOMAIN: 0000: Resource ranges:
1271 11:51:50.334554 * Base: 1000, Size: 800, Tag: 100
1272 11:51:50.340993 * Base: 1900, Size: e700, Tag: 100
1273 11:51:50.344772 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1274 11:51:50.350826 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1275 11:51:50.357853 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1276 11:51:50.367767 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1277 11:51:50.373966 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1278 11:51:50.380566 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1279 11:51:50.390921 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1280 11:51:50.397241 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1281 11:51:50.404121 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1282 11:51:50.414066 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1283 11:51:50.420702 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1284 11:51:50.427332 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1285 11:51:50.437209 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1286 11:51:50.443516 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1287 11:51:50.449945 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1288 11:51:50.460304 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1289 11:51:50.466977 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1290 11:51:50.473230 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1291 11:51:50.483115 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1292 11:51:50.489624 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1293 11:51:50.496576 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1294 11:51:50.506576 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1295 11:51:50.512959 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1296 11:51:50.519658 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1297 11:51:50.529340 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1298 11:51:50.532875 DOMAIN: 0000: Resource ranges:
1299 11:51:50.535937 * Base: 7fc00000, Size: 40400000, Tag: 200
1300 11:51:50.539606 * Base: d0000000, Size: 28000000, Tag: 200
1301 11:51:50.546015 * Base: fa000000, Size: 1000000, Tag: 200
1302 11:51:50.549464 * Base: fb001000, Size: 2fff000, Tag: 200
1303 11:51:50.552886 * Base: fe010000, Size: 2e000, Tag: 200
1304 11:51:50.556292 * Base: fe03f000, Size: d41000, Tag: 200
1305 11:51:50.562564 * Base: fed88000, Size: 8000, Tag: 200
1306 11:51:50.566188 * Base: fed93000, Size: d000, Tag: 200
1307 11:51:50.569115 * Base: feda2000, Size: 1e000, Tag: 200
1308 11:51:50.572500 * Base: fede0000, Size: 1220000, Tag: 200
1309 11:51:50.578963 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1310 11:51:50.585577 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1311 11:51:50.592225 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1312 11:51:50.598940 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1313 11:51:50.605774 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1314 11:51:50.612614 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1315 11:51:50.618854 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1316 11:51:50.625601 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1317 11:51:50.632372 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1318 11:51:50.638430 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1319 11:51:50.645272 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1320 11:51:50.651850 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1321 11:51:50.658947 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1322 11:51:50.665438 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1323 11:51:50.671835 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1324 11:51:50.678661 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1325 11:51:50.684946 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1326 11:51:50.692159 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1327 11:51:50.698389 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1328 11:51:50.705349 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1329 11:51:50.711556 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1330 11:51:50.718235 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1331 11:51:50.725106 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1332 11:51:50.730970 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1333 11:51:50.741465 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1334 11:51:50.744556 PCI: 00:1d.0: Resource ranges:
1335 11:51:50.748148 * Base: 7fc00000, Size: 100000, Tag: 200
1336 11:51:50.754328 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1337 11:51:50.760860 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1338 11:51:50.767803 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1339 11:51:50.774137 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1340 11:51:50.784550 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1341 11:51:50.787624 Root Device assign_resources, bus 0 link: 0
1342 11:51:50.790895 DOMAIN: 0000 assign_resources, bus 0 link: 0
1343 11:51:50.801224 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1344 11:51:50.807823 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1345 11:51:50.817302 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1346 11:51:50.823998 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1347 11:51:50.830582 PCI: 00:04.0 assign_resources, bus 1 link: 0
1348 11:51:50.833696 PCI: 00:04.0 assign_resources, bus 1 link: 0
1349 11:51:50.843566 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1350 11:51:50.850271 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1351 11:51:50.860045 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1352 11:51:50.863578 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1353 11:51:50.866963 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1354 11:51:50.876961 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1355 11:51:50.880081 PCI: 00:14.0 assign_resources, bus 0 link: 0
1356 11:51:50.886976 PCI: 00:14.0 assign_resources, bus 0 link: 0
1357 11:51:50.893502 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1358 11:51:50.903197 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1359 11:51:50.909749 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1360 11:51:50.913565 PCI: 00:14.3 assign_resources, bus 0 link: 0
1361 11:51:50.919695 PCI: 00:14.3 assign_resources, bus 0 link: 0
1362 11:51:50.926405 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1363 11:51:50.933224 PCI: 00:15.0 assign_resources, bus 0 link: 0
1364 11:51:50.936163 PCI: 00:15.0 assign_resources, bus 0 link: 0
1365 11:51:50.946044 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1366 11:51:50.949584 PCI: 00:15.1 assign_resources, bus 0 link: 0
1367 11:51:50.952595 PCI: 00:15.1 assign_resources, bus 0 link: 0
1368 11:51:50.962446 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1369 11:51:50.969379 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1370 11:51:50.979329 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1371 11:51:50.986282 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1372 11:51:50.992461 PCI: 00:19.1 assign_resources, bus 0 link: 0
1373 11:51:50.995870 PCI: 00:19.1 assign_resources, bus 0 link: 0
1374 11:51:51.005777 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1375 11:51:51.015651 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1376 11:51:51.022608 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1377 11:51:51.028744 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1378 11:51:51.035622 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1379 11:51:51.045290 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1380 11:51:51.052041 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1381 11:51:51.055052 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1382 11:51:51.064872 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1383 11:51:51.068730 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1384 11:51:51.074806 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1385 11:51:51.081678 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1386 11:51:51.087909 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1387 11:51:51.091356 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1388 11:51:51.094722 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1389 11:51:51.101857 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1390 11:51:51.105327 LPC: Trying to open IO window from 800 size 1ff
1391 11:51:51.114677 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1392 11:51:51.121674 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1393 11:51:51.131661 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1394 11:51:51.134770 DOMAIN: 0000 assign_resources, bus 0 link: 0
1395 11:51:51.141552 Root Device assign_resources, bus 0 link: 0
1396 11:51:51.141661 Done setting resources.
1397 11:51:51.147617 Show resources in subtree (Root Device)...After assigning values.
1398 11:51:51.154531 Root Device child on link 0 DOMAIN: 0000
1399 11:51:51.157554 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1400 11:51:51.167377 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1401 11:51:51.177437 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1402 11:51:51.177524 PCI: 00:00.0
1403 11:51:51.187354 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1404 11:51:51.197027 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1405 11:51:51.206866 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1406 11:51:51.217113 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1407 11:51:51.227091 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1408 11:51:51.233316 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1409 11:51:51.243190 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1410 11:51:51.252942 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1411 11:51:51.262833 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1412 11:51:51.273335 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1413 11:51:51.283221 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1414 11:51:51.292624 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1415 11:51:51.299570 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1416 11:51:51.309325 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1417 11:51:51.319258 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1418 11:51:51.329230 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1419 11:51:51.338950 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1420 11:51:51.348800 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1421 11:51:51.355501 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1422 11:51:51.365238 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1423 11:51:51.368931 PCI: 00:02.0
1424 11:51:51.378837 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1425 11:51:51.388220 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1426 11:51:51.398570 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1427 11:51:51.402032 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1428 11:51:51.415488 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1429 11:51:51.415743 GENERIC: 0.0
1430 11:51:51.418295 PCI: 00:05.0
1431 11:51:51.428252 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1432 11:51:51.431769 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1433 11:51:51.435163 GENERIC: 0.0
1434 11:51:51.435716 PCI: 00:08.0
1435 11:51:51.444797 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1436 11:51:51.448356 PCI: 00:0a.0
1437 11:51:51.451497 PCI: 00:0d.0 child on link 0 USB0 port 0
1438 11:51:51.461458 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1439 11:51:51.468192 USB0 port 0 child on link 0 USB3 port 0
1440 11:51:51.468956 USB3 port 0
1441 11:51:51.471122 USB3 port 1
1442 11:51:51.471908 USB3 port 2
1443 11:51:51.474785 USB3 port 3
1444 11:51:51.477947 PCI: 00:14.0 child on link 0 USB0 port 0
1445 11:51:51.487876 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1446 11:51:51.494144 USB0 port 0 child on link 0 USB2 port 0
1447 11:51:51.494733 USB2 port 0
1448 11:51:51.497990 USB2 port 1
1449 11:51:51.498537 USB2 port 2
1450 11:51:51.500879 USB2 port 3
1451 11:51:51.501308 USB2 port 4
1452 11:51:51.504412 USB2 port 5
1453 11:51:51.505292 USB2 port 6
1454 11:51:51.507747 USB2 port 7
1455 11:51:51.511155 USB2 port 8
1456 11:51:51.511584 USB2 port 9
1457 11:51:51.514131 USB3 port 0
1458 11:51:51.514744 USB3 port 1
1459 11:51:51.517651 USB3 port 2
1460 11:51:51.518262 USB3 port 3
1461 11:51:51.520639 PCI: 00:14.2
1462 11:51:51.530363 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1463 11:51:51.540608 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1464 11:51:51.543946 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1465 11:51:51.557192 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1466 11:51:51.558110 GENERIC: 0.0
1467 11:51:51.560128 PCI: 00:15.0 child on link 0 I2C: 00:1a
1468 11:51:51.573669 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1469 11:51:51.574345 I2C: 00:1a
1470 11:51:51.575065 I2C: 00:31
1471 11:51:51.576727 I2C: 00:32
1472 11:51:51.580509 PCI: 00:15.1 child on link 0 I2C: 00:10
1473 11:51:51.589848 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1474 11:51:51.593509 I2C: 00:10
1475 11:51:51.594039 PCI: 00:15.2
1476 11:51:51.606451 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1477 11:51:51.607110 PCI: 00:15.3
1478 11:51:51.616418 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1479 11:51:51.619871 PCI: 00:16.0
1480 11:51:51.629430 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1481 11:51:51.629768 PCI: 00:19.0
1482 11:51:51.636217 PCI: 00:19.1 child on link 0 I2C: 00:15
1483 11:51:51.646191 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1484 11:51:51.646314 I2C: 00:15
1485 11:51:51.652554 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1486 11:51:51.659171 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1487 11:51:51.672196 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1488 11:51:51.682482 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1489 11:51:51.685611 GENERIC: 0.0
1490 11:51:51.685720 PCI: 01:00.0
1491 11:51:51.695459 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1492 11:51:51.705375 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1493 11:51:51.718924 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1494 11:51:51.719037 PCI: 00:1e.0
1495 11:51:51.728639 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1496 11:51:51.735520 PCI: 00:1e.2 child on link 0 SPI: 00
1497 11:51:51.745352 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1498 11:51:51.745474 SPI: 00
1499 11:51:51.748773 PCI: 00:1e.3 child on link 0 SPI: 00
1500 11:51:51.758526 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1501 11:51:51.761603 SPI: 00
1502 11:51:51.765321 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1503 11:51:51.775121 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1504 11:51:51.775238 PNP: 0c09.0
1505 11:51:51.784891 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1506 11:51:51.788090 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1507 11:51:51.798079 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1508 11:51:51.808063 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1509 11:51:51.811172 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1510 11:51:51.814192 GENERIC: 0.0
1511 11:51:51.817915 GENERIC: 1.0
1512 11:51:51.818023 PCI: 00:1f.3
1513 11:51:51.827609 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1514 11:51:51.837998 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1515 11:51:51.840784 PCI: 00:1f.5
1516 11:51:51.850678 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1517 11:51:51.854233 CPU_CLUSTER: 0 child on link 0 APIC: 00
1518 11:51:51.857726 APIC: 00
1519 11:51:51.857901 APIC: 01
1520 11:51:51.858057 APIC: 03
1521 11:51:51.860935 APIC: 06
1522 11:51:51.861126 APIC: 05
1523 11:51:51.864242 APIC: 04
1524 11:51:51.864421 APIC: 02
1525 11:51:51.864591 APIC: 07
1526 11:51:51.867741 Done allocating resources.
1527 11:51:51.873917 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1528 11:51:51.880688 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1529 11:51:51.883754 Configure GPIOs for I2S audio on UP4.
1530 11:51:51.890894 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1531 11:51:51.893963 Enabling resources...
1532 11:51:51.897166 PCI: 00:00.0 subsystem <- 8086/9a12
1533 11:51:51.900214 PCI: 00:00.0 cmd <- 06
1534 11:51:51.903972 PCI: 00:02.0 subsystem <- 8086/9a40
1535 11:51:51.907086 PCI: 00:02.0 cmd <- 03
1536 11:51:51.910213 PCI: 00:04.0 subsystem <- 8086/9a03
1537 11:51:51.910331 PCI: 00:04.0 cmd <- 02
1538 11:51:51.917604 PCI: 00:05.0 subsystem <- 8086/9a19
1539 11:51:51.917712 PCI: 00:05.0 cmd <- 02
1540 11:51:51.920641 PCI: 00:08.0 subsystem <- 8086/9a11
1541 11:51:51.923824 PCI: 00:08.0 cmd <- 06
1542 11:51:51.927374 PCI: 00:0d.0 subsystem <- 8086/9a13
1543 11:51:51.930547 PCI: 00:0d.0 cmd <- 02
1544 11:51:51.933901 PCI: 00:14.0 subsystem <- 8086/a0ed
1545 11:51:51.936805 PCI: 00:14.0 cmd <- 02
1546 11:51:51.940389 PCI: 00:14.2 subsystem <- 8086/a0ef
1547 11:51:51.943339 PCI: 00:14.2 cmd <- 02
1548 11:51:51.946790 PCI: 00:14.3 subsystem <- 8086/a0f0
1549 11:51:51.950435 PCI: 00:14.3 cmd <- 02
1550 11:51:51.953799 PCI: 00:15.0 subsystem <- 8086/a0e8
1551 11:51:51.956758 PCI: 00:15.0 cmd <- 02
1552 11:51:51.960302 PCI: 00:15.1 subsystem <- 8086/a0e9
1553 11:51:51.960410 PCI: 00:15.1 cmd <- 02
1554 11:51:51.966773 PCI: 00:15.2 subsystem <- 8086/a0ea
1555 11:51:51.966858 PCI: 00:15.2 cmd <- 02
1556 11:51:51.970201 PCI: 00:15.3 subsystem <- 8086/a0eb
1557 11:51:51.973141 PCI: 00:15.3 cmd <- 02
1558 11:51:51.976888 PCI: 00:16.0 subsystem <- 8086/a0e0
1559 11:51:51.979808 PCI: 00:16.0 cmd <- 02
1560 11:51:51.983441 PCI: 00:19.1 subsystem <- 8086/a0c6
1561 11:51:51.986533 PCI: 00:19.1 cmd <- 02
1562 11:51:51.990075 PCI: 00:1d.0 bridge ctrl <- 0013
1563 11:51:51.993139 PCI: 00:1d.0 subsystem <- 8086/a0b0
1564 11:51:51.996928 PCI: 00:1d.0 cmd <- 06
1565 11:51:51.999982 PCI: 00:1e.0 subsystem <- 8086/a0a8
1566 11:51:52.003157 PCI: 00:1e.0 cmd <- 06
1567 11:51:52.006223 PCI: 00:1e.2 subsystem <- 8086/a0aa
1568 11:51:52.009904 PCI: 00:1e.2 cmd <- 06
1569 11:51:52.013043 PCI: 00:1e.3 subsystem <- 8086/a0ab
1570 11:51:52.013186 PCI: 00:1e.3 cmd <- 02
1571 11:51:52.019829 PCI: 00:1f.0 subsystem <- 8086/a087
1572 11:51:52.019942 PCI: 00:1f.0 cmd <- 407
1573 11:51:52.023009 PCI: 00:1f.3 subsystem <- 8086/a0c8
1574 11:51:52.026706 PCI: 00:1f.3 cmd <- 02
1575 11:51:52.029815 PCI: 00:1f.5 subsystem <- 8086/a0a4
1576 11:51:52.032748 PCI: 00:1f.5 cmd <- 406
1577 11:51:52.037640 PCI: 01:00.0 cmd <- 02
1578 11:51:52.042376 done.
1579 11:51:52.045671 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1580 11:51:52.048665 Initializing devices...
1581 11:51:52.052067 Root Device init
1582 11:51:52.055519 Chrome EC: Set SMI mask to 0x0000000000000000
1583 11:51:52.062134 Chrome EC: clear events_b mask to 0x0000000000000000
1584 11:51:52.068848 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1585 11:51:52.072016 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1586 11:51:52.078749 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1587 11:51:52.085486 Chrome EC: Set WAKE mask to 0x0000000000000000
1588 11:51:52.088568 fw_config match found: DB_USB=USB3_ACTIVE
1589 11:51:52.095199 Configure Right Type-C port orientation for retimer
1590 11:51:52.098318 Root Device init finished in 42 msecs
1591 11:51:52.102203 PCI: 00:00.0 init
1592 11:51:52.102287 CPU TDP = 9 Watts
1593 11:51:52.105203 CPU PL1 = 9 Watts
1594 11:51:52.108330 CPU PL2 = 40 Watts
1595 11:51:52.108439 CPU PL4 = 83 Watts
1596 11:51:52.111929 PCI: 00:00.0 init finished in 8 msecs
1597 11:51:52.115070 PCI: 00:02.0 init
1598 11:51:52.118171 GMA: Found VBT in CBFS
1599 11:51:52.121875 GMA: Found valid VBT in CBFS
1600 11:51:52.124903 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1601 11:51:52.135198 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1602 11:51:52.138344 PCI: 00:02.0 init finished in 18 msecs
1603 11:51:52.141937 PCI: 00:05.0 init
1604 11:51:52.145013 PCI: 00:05.0 init finished in 0 msecs
1605 11:51:52.145090 PCI: 00:08.0 init
1606 11:51:52.151389 PCI: 00:08.0 init finished in 0 msecs
1607 11:51:52.151499 PCI: 00:14.0 init
1608 11:51:52.157825 PCI: 00:14.0 init finished in 0 msecs
1609 11:51:52.157938 PCI: 00:14.2 init
1610 11:51:52.161306 PCI: 00:14.2 init finished in 0 msecs
1611 11:51:52.165243 PCI: 00:15.0 init
1612 11:51:52.168549 I2C bus 0 version 0x3230302a
1613 11:51:52.171889 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1614 11:51:52.175264 PCI: 00:15.0 init finished in 6 msecs
1615 11:51:52.178249 PCI: 00:15.1 init
1616 11:51:52.181534 I2C bus 1 version 0x3230302a
1617 11:51:52.184962 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1618 11:51:52.188446 PCI: 00:15.1 init finished in 6 msecs
1619 11:51:52.191384 PCI: 00:15.2 init
1620 11:51:52.195113 I2C bus 2 version 0x3230302a
1621 11:51:52.198184 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1622 11:51:52.201812 PCI: 00:15.2 init finished in 6 msecs
1623 11:51:52.201943 PCI: 00:15.3 init
1624 11:51:52.205023 I2C bus 3 version 0x3230302a
1625 11:51:52.208148 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1626 11:51:52.214956 PCI: 00:15.3 init finished in 6 msecs
1627 11:51:52.215095 PCI: 00:16.0 init
1628 11:51:52.218003 PCI: 00:16.0 init finished in 0 msecs
1629 11:51:52.221734 PCI: 00:19.1 init
1630 11:51:52.225541 I2C bus 5 version 0x3230302a
1631 11:51:52.228785 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1632 11:51:52.231808 PCI: 00:19.1 init finished in 6 msecs
1633 11:51:52.235448 PCI: 00:1d.0 init
1634 11:51:52.238561 Initializing PCH PCIe bridge.
1635 11:51:52.241590 PCI: 00:1d.0 init finished in 3 msecs
1636 11:51:52.245259 PCI: 00:1f.0 init
1637 11:51:52.248302 IOAPIC: Initializing IOAPIC at 0xfec00000
1638 11:51:52.255197 IOAPIC: Bootstrap Processor Local APIC = 0x00
1639 11:51:52.255304 IOAPIC: ID = 0x02
1640 11:51:52.258090 IOAPIC: Dumping registers
1641 11:51:52.261319 reg 0x0000: 0x02000000
1642 11:51:52.261421 reg 0x0001: 0x00770020
1643 11:51:52.264895 reg 0x0002: 0x00000000
1644 11:51:52.271327 PCI: 00:1f.0 init finished in 21 msecs
1645 11:51:52.271432 PCI: 00:1f.2 init
1646 11:51:52.274327 Disabling ACPI via APMC.
1647 11:51:52.279497 APMC done.
1648 11:51:52.282349 PCI: 00:1f.2 init finished in 6 msecs
1649 11:51:52.294414 PCI: 01:00.0 init
1650 11:51:52.297941 PCI: 01:00.0 init finished in 0 msecs
1651 11:51:52.300975 PNP: 0c09.0 init
1652 11:51:52.307660 Google Chrome EC uptime: 8.504 seconds
1653 11:51:52.310751 Google Chrome AP resets since EC boot: 1
1654 11:51:52.314581 Google Chrome most recent AP reset causes:
1655 11:51:52.317675 0.348: 32775 shutdown: entering G3
1656 11:51:52.324425 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1657 11:51:52.327601 PNP: 0c09.0 init finished in 24 msecs
1658 11:51:52.334425 Devices initialized
1659 11:51:52.337526 Show all devs... After init.
1660 11:51:52.341299 Root Device: enabled 1
1661 11:51:52.341409 DOMAIN: 0000: enabled 1
1662 11:51:52.344291 CPU_CLUSTER: 0: enabled 1
1663 11:51:52.347450 PCI: 00:00.0: enabled 1
1664 11:51:52.351119 PCI: 00:02.0: enabled 1
1665 11:51:52.351222 PCI: 00:04.0: enabled 1
1666 11:51:52.354227 PCI: 00:05.0: enabled 1
1667 11:51:52.357333 PCI: 00:06.0: enabled 0
1668 11:51:52.361137 PCI: 00:07.0: enabled 0
1669 11:51:52.361255 PCI: 00:07.1: enabled 0
1670 11:51:52.364087 PCI: 00:07.2: enabled 0
1671 11:51:52.367573 PCI: 00:07.3: enabled 0
1672 11:51:52.371067 PCI: 00:08.0: enabled 1
1673 11:51:52.371168 PCI: 00:09.0: enabled 0
1674 11:51:52.374484 PCI: 00:0a.0: enabled 0
1675 11:51:52.377243 PCI: 00:0d.0: enabled 1
1676 11:51:52.380694 PCI: 00:0d.1: enabled 0
1677 11:51:52.380792 PCI: 00:0d.2: enabled 0
1678 11:51:52.384133 PCI: 00:0d.3: enabled 0
1679 11:51:52.387421 PCI: 00:0e.0: enabled 0
1680 11:51:52.390809 PCI: 00:10.2: enabled 1
1681 11:51:52.390908 PCI: 00:10.6: enabled 0
1682 11:51:52.393654 PCI: 00:10.7: enabled 0
1683 11:51:52.397182 PCI: 00:12.0: enabled 0
1684 11:51:52.397285 PCI: 00:12.6: enabled 0
1685 11:51:52.400434 PCI: 00:13.0: enabled 0
1686 11:51:52.403743 PCI: 00:14.0: enabled 1
1687 11:51:52.407359 PCI: 00:14.1: enabled 0
1688 11:51:52.407492 PCI: 00:14.2: enabled 1
1689 11:51:52.410596 PCI: 00:14.3: enabled 1
1690 11:51:52.413663 PCI: 00:15.0: enabled 1
1691 11:51:52.417420 PCI: 00:15.1: enabled 1
1692 11:51:52.417505 PCI: 00:15.2: enabled 1
1693 11:51:52.420621 PCI: 00:15.3: enabled 1
1694 11:51:52.423675 PCI: 00:16.0: enabled 1
1695 11:51:52.427262 PCI: 00:16.1: enabled 0
1696 11:51:52.427389 PCI: 00:16.2: enabled 0
1697 11:51:52.430305 PCI: 00:16.3: enabled 0
1698 11:51:52.433556 PCI: 00:16.4: enabled 0
1699 11:51:52.437251 PCI: 00:16.5: enabled 0
1700 11:51:52.437337 PCI: 00:17.0: enabled 0
1701 11:51:52.440278 PCI: 00:19.0: enabled 0
1702 11:51:52.443425 PCI: 00:19.1: enabled 1
1703 11:51:52.446555 PCI: 00:19.2: enabled 0
1704 11:51:52.446655 PCI: 00:1c.0: enabled 1
1705 11:51:52.450219 PCI: 00:1c.1: enabled 0
1706 11:51:52.453398 PCI: 00:1c.2: enabled 0
1707 11:51:52.453480 PCI: 00:1c.3: enabled 0
1708 11:51:52.456637 PCI: 00:1c.4: enabled 0
1709 11:51:52.460283 PCI: 00:1c.5: enabled 0
1710 11:51:52.463348 PCI: 00:1c.6: enabled 1
1711 11:51:52.463451 PCI: 00:1c.7: enabled 0
1712 11:51:52.466481 PCI: 00:1d.0: enabled 1
1713 11:51:52.470133 PCI: 00:1d.1: enabled 0
1714 11:51:52.473173 PCI: 00:1d.2: enabled 1
1715 11:51:52.473255 PCI: 00:1d.3: enabled 0
1716 11:51:52.477214 PCI: 00:1e.0: enabled 1
1717 11:51:52.479989 PCI: 00:1e.1: enabled 0
1718 11:51:52.483453 PCI: 00:1e.2: enabled 1
1719 11:51:52.484002 PCI: 00:1e.3: enabled 1
1720 11:51:52.486902 PCI: 00:1f.0: enabled 1
1721 11:51:52.490225 PCI: 00:1f.1: enabled 0
1722 11:51:52.493662 PCI: 00:1f.2: enabled 1
1723 11:51:52.494222 PCI: 00:1f.3: enabled 1
1724 11:51:52.496423 PCI: 00:1f.4: enabled 0
1725 11:51:52.499849 PCI: 00:1f.5: enabled 1
1726 11:51:52.500396 PCI: 00:1f.6: enabled 0
1727 11:51:52.503219 PCI: 00:1f.7: enabled 0
1728 11:51:52.506664 APIC: 00: enabled 1
1729 11:51:52.510237 GENERIC: 0.0: enabled 1
1730 11:51:52.510796 GENERIC: 0.0: enabled 1
1731 11:51:52.513033 GENERIC: 1.0: enabled 1
1732 11:51:52.516513 GENERIC: 0.0: enabled 1
1733 11:51:52.520075 GENERIC: 1.0: enabled 1
1734 11:51:52.520558 USB0 port 0: enabled 1
1735 11:51:52.522983 GENERIC: 0.0: enabled 1
1736 11:51:52.526661 USB0 port 0: enabled 1
1737 11:51:52.527107 GENERIC: 0.0: enabled 1
1738 11:51:52.529717 I2C: 00:1a: enabled 1
1739 11:51:52.533437 I2C: 00:31: enabled 1
1740 11:51:52.533867 I2C: 00:32: enabled 1
1741 11:51:52.536695 I2C: 00:10: enabled 1
1742 11:51:52.539620 I2C: 00:15: enabled 1
1743 11:51:52.543336 GENERIC: 0.0: enabled 0
1744 11:51:52.543768 GENERIC: 1.0: enabled 0
1745 11:51:52.546514 GENERIC: 0.0: enabled 1
1746 11:51:52.549691 SPI: 00: enabled 1
1747 11:51:52.550129 SPI: 00: enabled 1
1748 11:51:52.553344 PNP: 0c09.0: enabled 1
1749 11:51:52.556337 GENERIC: 0.0: enabled 1
1750 11:51:52.556912 USB3 port 0: enabled 1
1751 11:51:52.560057 USB3 port 1: enabled 1
1752 11:51:52.563076 USB3 port 2: enabled 0
1753 11:51:52.563493 USB3 port 3: enabled 0
1754 11:51:52.566305 USB2 port 0: enabled 0
1755 11:51:52.569953 USB2 port 1: enabled 1
1756 11:51:52.573075 USB2 port 2: enabled 1
1757 11:51:52.573712 USB2 port 3: enabled 0
1758 11:51:52.576573 USB2 port 4: enabled 1
1759 11:51:52.579744 USB2 port 5: enabled 0
1760 11:51:52.580233 USB2 port 6: enabled 0
1761 11:51:52.582821 USB2 port 7: enabled 0
1762 11:51:52.586447 USB2 port 8: enabled 0
1763 11:51:52.589802 USB2 port 9: enabled 0
1764 11:51:52.590248 USB3 port 0: enabled 0
1765 11:51:52.592734 USB3 port 1: enabled 1
1766 11:51:52.596135 USB3 port 2: enabled 0
1767 11:51:52.596611 USB3 port 3: enabled 0
1768 11:51:52.599650 GENERIC: 0.0: enabled 1
1769 11:51:52.602695 GENERIC: 1.0: enabled 1
1770 11:51:52.602779 APIC: 01: enabled 1
1771 11:51:52.606103 APIC: 03: enabled 1
1772 11:51:52.608989 APIC: 06: enabled 1
1773 11:51:52.609070 APIC: 05: enabled 1
1774 11:51:52.612519 APIC: 04: enabled 1
1775 11:51:52.616076 APIC: 02: enabled 1
1776 11:51:52.616165 APIC: 07: enabled 1
1777 11:51:52.619033 PCI: 01:00.0: enabled 1
1778 11:51:52.625750 BS: BS_DEV_INIT run times (exec / console): 32 / 540 ms
1779 11:51:52.629153 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1780 11:51:52.632135 ELOG: NV offset 0xf30000 size 0x1000
1781 11:51:52.639628 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1782 11:51:52.646339 ELOG: Event(17) added with size 13 at 2023-06-23 11:51:52 UTC
1783 11:51:52.652592 ELOG: Event(92) added with size 9 at 2023-06-23 11:51:52 UTC
1784 11:51:52.659459 ELOG: Event(93) added with size 9 at 2023-06-23 11:51:52 UTC
1785 11:51:52.666264 ELOG: Event(9E) added with size 10 at 2023-06-23 11:51:52 UTC
1786 11:51:52.672831 ELOG: Event(9F) added with size 14 at 2023-06-23 11:51:52 UTC
1787 11:51:52.679631 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1788 11:51:52.685988 ELOG: Event(A1) added with size 10 at 2023-06-23 11:51:52 UTC
1789 11:51:52.688974 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1790 11:51:52.695547 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1791 11:51:52.698947 Finalize devices...
1792 11:51:52.699027 Devices finalized
1793 11:51:52.705944 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1794 11:51:52.712147 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1795 11:51:52.715561 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1796 11:51:52.722121 ME: HFSTS1 : 0x80030055
1797 11:51:52.725625 ME: HFSTS2 : 0x30280116
1798 11:51:52.728952 ME: HFSTS3 : 0x00000050
1799 11:51:52.735309 ME: HFSTS4 : 0x00004000
1800 11:51:52.738614 ME: HFSTS5 : 0x00000000
1801 11:51:52.745260 ME: HFSTS6 : 0x00400006
1802 11:51:52.748950 ME: Manufacturing Mode : YES
1803 11:51:52.752036 ME: SPI Protection Mode Enabled : NO
1804 11:51:52.755133 ME: FW Partition Table : OK
1805 11:51:52.758890 ME: Bringup Loader Failure : NO
1806 11:51:52.762007 ME: Firmware Init Complete : NO
1807 11:51:52.765129 ME: Boot Options Present : NO
1808 11:51:52.768919 ME: Update In Progress : NO
1809 11:51:52.775035 ME: D0i3 Support : YES
1810 11:51:52.778738 ME: Low Power State Enabled : NO
1811 11:51:52.781736 ME: CPU Replaced : YES
1812 11:51:52.785334 ME: CPU Replacement Valid : YES
1813 11:51:52.788462 ME: Current Working State : 5
1814 11:51:52.791627 ME: Current Operation State : 1
1815 11:51:52.795316 ME: Current Operation Mode : 3
1816 11:51:52.798416 ME: Error Code : 0
1817 11:51:52.801999 ME: Enhanced Debug Mode : NO
1818 11:51:52.808588 ME: CPU Debug Disabled : YES
1819 11:51:52.811450 ME: TXT Support : NO
1820 11:51:52.818294 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1821 11:51:52.824670 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1822 11:51:52.828124 CBFS: 'fallback/slic' not found.
1823 11:51:52.831615 ACPI: Writing ACPI tables at 76b01000.
1824 11:51:52.835129 ACPI: * FACS
1825 11:51:52.835226 ACPI: * DSDT
1826 11:51:52.837936 Ramoops buffer: 0x100000@0x76a00000.
1827 11:51:52.844575 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1828 11:51:52.847969 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1829 11:51:52.851342 Google Chrome EC: version:
1830 11:51:52.854596 ro: voema_v2.0.7540-147f8d37d1
1831 11:51:52.858198 rw: voema_v2.0.7540-147f8d37d1
1832 11:51:52.861317 running image: 2
1833 11:51:52.865030 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1834 11:51:52.870662 ACPI: * FADT
1835 11:51:52.870751 SCI is IRQ9
1836 11:51:52.876842 ACPI: added table 1/32, length now 40
1837 11:51:52.876925 ACPI: * SSDT
1838 11:51:52.880495 Found 1 CPU(s) with 8 core(s) each.
1839 11:51:52.886595 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1840 11:51:52.890217 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1841 11:51:52.893335 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1842 11:51:52.897034 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1843 11:51:52.903236 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1844 11:51:52.910071 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1845 11:51:52.913338 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1846 11:51:52.920052 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1847 11:51:52.926864 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1848 11:51:52.929693 \_SB.PCI0.RP09: Added StorageD3Enable property
1849 11:51:52.936576 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1850 11:51:52.940006 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1851 11:51:52.946359 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1852 11:51:52.949796 PS2K: Passing 80 keymaps to kernel
1853 11:51:52.956113 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1854 11:51:52.962641 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1855 11:51:52.969551 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1856 11:51:52.976192 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1857 11:51:52.982546 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1858 11:51:52.989339 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1859 11:51:52.996046 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1860 11:51:53.002819 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1861 11:51:53.005932 ACPI: added table 2/32, length now 44
1862 11:51:53.006015 ACPI: * MCFG
1863 11:51:53.009114 ACPI: added table 3/32, length now 48
1864 11:51:53.012872 ACPI: * TPM2
1865 11:51:53.015973 TPM2 log created at 0x769f0000
1866 11:51:53.018982 ACPI: added table 4/32, length now 52
1867 11:51:53.022602 ACPI: * MADT
1868 11:51:53.022711 SCI is IRQ9
1869 11:51:53.025590 ACPI: added table 5/32, length now 56
1870 11:51:53.028901 current = 76b09850
1871 11:51:53.028979 ACPI: * DMAR
1872 11:51:53.032352 ACPI: added table 6/32, length now 60
1873 11:51:53.035762 ACPI: added table 7/32, length now 64
1874 11:51:53.039093 ACPI: * HPET
1875 11:51:53.042192 ACPI: added table 8/32, length now 68
1876 11:51:53.045618 ACPI: done.
1877 11:51:53.045701 ACPI tables: 35216 bytes.
1878 11:51:53.049144 smbios_write_tables: 769ef000
1879 11:51:53.052677 EC returned error result code 3
1880 11:51:53.055386 Couldn't obtain OEM name from CBI
1881 11:51:53.059291 Create SMBIOS type 16
1882 11:51:53.062895 Create SMBIOS type 17
1883 11:51:53.066233 GENERIC: 0.0 (WIFI Device)
1884 11:51:53.066310 SMBIOS tables: 1750 bytes.
1885 11:51:53.072766 Writing table forward entry at 0x00000500
1886 11:51:53.079658 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1887 11:51:53.082748 Writing coreboot table at 0x76b25000
1888 11:51:53.089513 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1889 11:51:53.092594 1. 0000000000001000-000000000009ffff: RAM
1890 11:51:53.096133 2. 00000000000a0000-00000000000fffff: RESERVED
1891 11:51:53.102317 3. 0000000000100000-00000000769eefff: RAM
1892 11:51:53.106031 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1893 11:51:53.112269 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1894 11:51:53.118959 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1895 11:51:53.122576 7. 0000000077000000-000000007fbfffff: RESERVED
1896 11:51:53.128710 8. 00000000c0000000-00000000cfffffff: RESERVED
1897 11:51:53.132244 9. 00000000f8000000-00000000f9ffffff: RESERVED
1898 11:51:53.135635 10. 00000000fb000000-00000000fb000fff: RESERVED
1899 11:51:53.142464 11. 00000000fe000000-00000000fe00ffff: RESERVED
1900 11:51:53.145483 12. 00000000fed80000-00000000fed87fff: RESERVED
1901 11:51:53.151836 13. 00000000fed90000-00000000fed92fff: RESERVED
1902 11:51:53.155314 14. 00000000feda0000-00000000feda1fff: RESERVED
1903 11:51:53.162322 15. 00000000fedc0000-00000000feddffff: RESERVED
1904 11:51:53.165470 16. 0000000100000000-00000002803fffff: RAM
1905 11:51:53.168670 Passing 4 GPIOs to payload:
1906 11:51:53.172066 NAME | PORT | POLARITY | VALUE
1907 11:51:53.178613 lid | undefined | high | high
1908 11:51:53.184836 power | undefined | high | low
1909 11:51:53.188674 oprom | undefined | high | low
1910 11:51:53.194931 EC in RW | 0x000000e5 | high | high
1911 11:51:53.201551 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum b9e0
1912 11:51:53.205220 coreboot table: 1576 bytes.
1913 11:51:53.208254 IMD ROOT 0. 0x76fff000 0x00001000
1914 11:51:53.211376 IMD SMALL 1. 0x76ffe000 0x00001000
1915 11:51:53.215067 FSP MEMORY 2. 0x76c4e000 0x003b0000
1916 11:51:53.218092 VPD 3. 0x76c4d000 0x00000367
1917 11:51:53.221915 RO MCACHE 4. 0x76c4c000 0x00000fdc
1918 11:51:53.224910 CONSOLE 5. 0x76c2c000 0x00020000
1919 11:51:53.227890 FMAP 6. 0x76c2b000 0x00000578
1920 11:51:53.234701 TIME STAMP 7. 0x76c2a000 0x00000910
1921 11:51:53.238191 VBOOT WORK 8. 0x76c16000 0x00014000
1922 11:51:53.241316 ROMSTG STCK 9. 0x76c15000 0x00001000
1923 11:51:53.244336 AFTER CAR 10. 0x76c0a000 0x0000b000
1924 11:51:53.247738 RAMSTAGE 11. 0x76b97000 0x00073000
1925 11:51:53.251260 REFCODE 12. 0x76b42000 0x00055000
1926 11:51:53.254616 SMM BACKUP 13. 0x76b32000 0x00010000
1927 11:51:53.258095 4f444749 14. 0x76b30000 0x00002000
1928 11:51:53.261050 EXT VBT15. 0x76b2d000 0x0000219f
1929 11:51:53.267550 COREBOOT 16. 0x76b25000 0x00008000
1930 11:51:53.271013 ACPI 17. 0x76b01000 0x00024000
1931 11:51:53.274305 ACPI GNVS 18. 0x76b00000 0x00001000
1932 11:51:53.277761 RAMOOPS 19. 0x76a00000 0x00100000
1933 11:51:53.280688 TPM2 TCGLOG20. 0x769f0000 0x00010000
1934 11:51:53.284161 SMBIOS 21. 0x769ef000 0x00000800
1935 11:51:53.287917 IMD small region:
1936 11:51:53.291013 IMD ROOT 0. 0x76ffec00 0x00000400
1937 11:51:53.294146 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1938 11:51:53.297211 POWER STATE 2. 0x76ffeb80 0x00000044
1939 11:51:53.303914 ROMSTAGE 3. 0x76ffeb60 0x00000004
1940 11:51:53.307582 MEM INFO 4. 0x76ffe980 0x000001e0
1941 11:51:53.313811 BS: BS_WRITE_TABLES run times (exec / console): 6 / 484 ms
1942 11:51:53.313900 MTRR: Physical address space:
1943 11:51:53.320658 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1944 11:51:53.327457 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1945 11:51:53.333539 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1946 11:51:53.340242 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1947 11:51:53.346834 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1948 11:51:53.353587 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1949 11:51:53.360494 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1950 11:51:53.363852 MTRR: Fixed MSR 0x250 0x0606060606060606
1951 11:51:53.366619 MTRR: Fixed MSR 0x258 0x0606060606060606
1952 11:51:53.370225 MTRR: Fixed MSR 0x259 0x0000000000000000
1953 11:51:53.376426 MTRR: Fixed MSR 0x268 0x0606060606060606
1954 11:51:53.379877 MTRR: Fixed MSR 0x269 0x0606060606060606
1955 11:51:53.383259 MTRR: Fixed MSR 0x26a 0x0606060606060606
1956 11:51:53.386773 MTRR: Fixed MSR 0x26b 0x0606060606060606
1957 11:51:53.393158 MTRR: Fixed MSR 0x26c 0x0606060606060606
1958 11:51:53.396273 MTRR: Fixed MSR 0x26d 0x0606060606060606
1959 11:51:53.400004 MTRR: Fixed MSR 0x26e 0x0606060606060606
1960 11:51:53.403106 MTRR: Fixed MSR 0x26f 0x0606060606060606
1961 11:51:53.407241 call enable_fixed_mtrr()
1962 11:51:53.410821 CPU physical address size: 39 bits
1963 11:51:53.417105 MTRR: default type WB/UC MTRR counts: 6/6.
1964 11:51:53.420869 MTRR: UC selected as default type.
1965 11:51:53.427056 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1966 11:51:53.430813 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1967 11:51:53.437579 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1968 11:51:53.443665 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1969 11:51:53.450655 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1970 11:51:53.456858 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1971 11:51:53.463502 MTRR: Fixed MSR 0x250 0x0606060606060606
1972 11:51:53.466969 MTRR: Fixed MSR 0x258 0x0606060606060606
1973 11:51:53.470581 MTRR: Fixed MSR 0x259 0x0000000000000000
1974 11:51:53.473515 MTRR: Fixed MSR 0x268 0x0606060606060606
1975 11:51:53.480288 MTRR: Fixed MSR 0x269 0x0606060606060606
1976 11:51:53.483726 MTRR: Fixed MSR 0x26a 0x0606060606060606
1977 11:51:53.486746 MTRR: Fixed MSR 0x26b 0x0606060606060606
1978 11:51:53.490117 MTRR: Fixed MSR 0x26c 0x0606060606060606
1979 11:51:53.493558 MTRR: Fixed MSR 0x26d 0x0606060606060606
1980 11:51:53.499976 MTRR: Fixed MSR 0x26e 0x0606060606060606
1981 11:51:53.503640 MTRR: Fixed MSR 0x26f 0x0606060606060606
1982 11:51:53.503726
1983 11:51:53.506801 MTRR check
1984 11:51:53.506875 Fixed MTRRs : Enabled
1985 11:51:53.509778 Variable MTRRs: Enabled
1986 11:51:53.509877
1987 11:51:53.513333 call enable_fixed_mtrr()
1988 11:51:53.519983 BS: BS_WRITE_TABLES exit times (exec / console): 48 / 151 ms
1989 11:51:53.523089 CPU physical address size: 39 bits
1990 11:51:53.527531 Checking cr50 for pending updates
1991 11:51:53.531183 MTRR: Fixed MSR 0x250 0x0606060606060606
1992 11:51:53.535034 MTRR: Fixed MSR 0x250 0x0606060606060606
1993 11:51:53.541718 MTRR: Fixed MSR 0x258 0x0606060606060606
1994 11:51:53.544833 MTRR: Fixed MSR 0x259 0x0000000000000000
1995 11:51:53.547920 MTRR: Fixed MSR 0x268 0x0606060606060606
1996 11:51:53.551422 MTRR: Fixed MSR 0x269 0x0606060606060606
1997 11:51:53.554524 MTRR: Fixed MSR 0x26a 0x0606060606060606
1998 11:51:53.561255 MTRR: Fixed MSR 0x26b 0x0606060606060606
1999 11:51:53.564872 MTRR: Fixed MSR 0x26c 0x0606060606060606
2000 11:51:53.567748 MTRR: Fixed MSR 0x26d 0x0606060606060606
2001 11:51:53.571249 MTRR: Fixed MSR 0x26e 0x0606060606060606
2002 11:51:53.577732 MTRR: Fixed MSR 0x26f 0x0606060606060606
2003 11:51:53.581226 MTRR: Fixed MSR 0x258 0x0606060606060606
2004 11:51:53.584143 call enable_fixed_mtrr()
2005 11:51:53.587721 MTRR: Fixed MSR 0x259 0x0000000000000000
2006 11:51:53.591343 MTRR: Fixed MSR 0x268 0x0606060606060606
2007 11:51:53.597749 MTRR: Fixed MSR 0x269 0x0606060606060606
2008 11:51:53.601348 MTRR: Fixed MSR 0x26a 0x0606060606060606
2009 11:51:53.604298 MTRR: Fixed MSR 0x26b 0x0606060606060606
2010 11:51:53.607883 MTRR: Fixed MSR 0x26c 0x0606060606060606
2011 11:51:53.613994 MTRR: Fixed MSR 0x26d 0x0606060606060606
2012 11:51:53.617596 MTRR: Fixed MSR 0x26e 0x0606060606060606
2013 11:51:53.620548 MTRR: Fixed MSR 0x26f 0x0606060606060606
2014 11:51:53.624272 CPU physical address size: 39 bits
2015 11:51:53.630540 call enable_fixed_mtrr()
2016 11:51:53.634318 MTRR: Fixed MSR 0x250 0x0606060606060606
2017 11:51:53.637424 MTRR: Fixed MSR 0x250 0x0606060606060606
2018 11:51:53.640574 MTRR: Fixed MSR 0x258 0x0606060606060606
2019 11:51:53.647184 MTRR: Fixed MSR 0x259 0x0000000000000000
2020 11:51:53.650337 MTRR: Fixed MSR 0x268 0x0606060606060606
2021 11:51:53.653842 MTRR: Fixed MSR 0x269 0x0606060606060606
2022 11:51:53.657391 MTRR: Fixed MSR 0x26a 0x0606060606060606
2023 11:51:53.660453 MTRR: Fixed MSR 0x26b 0x0606060606060606
2024 11:51:53.667387 MTRR: Fixed MSR 0x26c 0x0606060606060606
2025 11:51:53.670310 MTRR: Fixed MSR 0x26d 0x0606060606060606
2026 11:51:53.673827 MTRR: Fixed MSR 0x26e 0x0606060606060606
2027 11:51:53.677290 MTRR: Fixed MSR 0x26f 0x0606060606060606
2028 11:51:53.683778 MTRR: Fixed MSR 0x258 0x0606060606060606
2029 11:51:53.686544 MTRR: Fixed MSR 0x259 0x0000000000000000
2030 11:51:53.693602 MTRR: Fixed MSR 0x268 0x0606060606060606
2031 11:51:53.696517 MTRR: Fixed MSR 0x269 0x0606060606060606
2032 11:51:53.699988 MTRR: Fixed MSR 0x26a 0x0606060606060606
2033 11:51:53.703469 MTRR: Fixed MSR 0x26b 0x0606060606060606
2034 11:51:53.706429 MTRR: Fixed MSR 0x26c 0x0606060606060606
2035 11:51:53.713109 MTRR: Fixed MSR 0x26d 0x0606060606060606
2036 11:51:53.716787 MTRR: Fixed MSR 0x26e 0x0606060606060606
2037 11:51:53.719954 MTRR: Fixed MSR 0x26f 0x0606060606060606
2038 11:51:53.723515 call enable_fixed_mtrr()
2039 11:51:53.727196 call enable_fixed_mtrr()
2040 11:51:53.730307 MTRR: Fixed MSR 0x250 0x0606060606060606
2041 11:51:53.733421 MTRR: Fixed MSR 0x250 0x0606060606060606
2042 11:51:53.740355 MTRR: Fixed MSR 0x258 0x0606060606060606
2043 11:51:53.743509 MTRR: Fixed MSR 0x259 0x0000000000000000
2044 11:51:53.746569 MTRR: Fixed MSR 0x268 0x0606060606060606
2045 11:51:53.749645 MTRR: Fixed MSR 0x269 0x0606060606060606
2046 11:51:53.756408 MTRR: Fixed MSR 0x26a 0x0606060606060606
2047 11:51:53.759940 MTRR: Fixed MSR 0x26b 0x0606060606060606
2048 11:51:53.763131 MTRR: Fixed MSR 0x26c 0x0606060606060606
2049 11:51:53.766267 MTRR: Fixed MSR 0x26d 0x0606060606060606
2050 11:51:53.773163 MTRR: Fixed MSR 0x26e 0x0606060606060606
2051 11:51:53.776136 MTRR: Fixed MSR 0x26f 0x0606060606060606
2052 11:51:53.779720 MTRR: Fixed MSR 0x258 0x0606060606060606
2053 11:51:53.782723 call enable_fixed_mtrr()
2054 11:51:53.786179 MTRR: Fixed MSR 0x259 0x0000000000000000
2055 11:51:53.792724 MTRR: Fixed MSR 0x268 0x0606060606060606
2056 11:51:53.796217 MTRR: Fixed MSR 0x269 0x0606060606060606
2057 11:51:53.799118 MTRR: Fixed MSR 0x26a 0x0606060606060606
2058 11:51:53.802636 MTRR: Fixed MSR 0x26b 0x0606060606060606
2059 11:51:53.809079 MTRR: Fixed MSR 0x26c 0x0606060606060606
2060 11:51:53.812607 MTRR: Fixed MSR 0x26d 0x0606060606060606
2061 11:51:53.816118 MTRR: Fixed MSR 0x26e 0x0606060606060606
2062 11:51:53.819039 MTRR: Fixed MSR 0x26f 0x0606060606060606
2063 11:51:53.823341 CPU physical address size: 39 bits
2064 11:51:53.831000 call enable_fixed_mtrr()
2065 11:51:53.831084 Reading cr50 TPM mode
2066 11:51:53.834727 CPU physical address size: 39 bits
2067 11:51:53.837837 CPU physical address size: 39 bits
2068 11:51:53.844641 BS: BS_PAYLOAD_LOAD entry times (exec / console): 309 / 7 ms
2069 11:51:53.847760 CPU physical address size: 39 bits
2070 11:51:53.851302 CPU physical address size: 39 bits
2071 11:51:53.861067 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2072 11:51:53.864538 Checking segment from ROM address 0xffc02b38
2073 11:51:53.867643 Checking segment from ROM address 0xffc02b54
2074 11:51:53.873971 Loading segment from ROM address 0xffc02b38
2075 11:51:53.874052 code (compression=0)
2076 11:51:53.884445 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2077 11:51:53.893891 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2078 11:51:53.893973 it's not compressed!
2079 11:51:54.033688 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2080 11:51:54.039883 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2081 11:51:54.046824 Loading segment from ROM address 0xffc02b54
2082 11:51:54.046912 Entry Point 0x30000000
2083 11:51:54.050529 Loaded segments
2084 11:51:54.056648 BS: BS_PAYLOAD_LOAD run times (exec / console): 142 / 63 ms
2085 11:51:54.099394 Finalizing chipset.
2086 11:51:54.102888 Finalizing SMM.
2087 11:51:54.103003 APMC done.
2088 11:51:54.109428 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2089 11:51:54.112889 mp_park_aps done after 0 msecs.
2090 11:51:54.116298 Jumping to boot code at 0x30000000(0x76b25000)
2091 11:51:54.125875 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2092 11:51:54.125992
2093 11:51:54.126087
2094 11:51:54.129552
2095 11:51:54.129637 Starting depthcharge on Voema...
2096 11:51:54.129977 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2097 11:51:54.130079 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2098 11:51:54.130194 Setting prompt string to ['volteer:']
2099 11:51:54.130273 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2100 11:51:54.132441
2101 11:51:54.139559 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2102 11:51:54.139672
2103 11:51:54.145884 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2104 11:51:54.146010
2105 11:51:54.152846 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2106 11:51:54.153001
2107 11:51:54.155875 Failed to find eMMC card reader
2108 11:51:54.156003
2109 11:51:54.156105 Wipe memory regions:
2110 11:51:54.158974
2111 11:51:54.162632 [0x00000000001000, 0x000000000a0000)
2112 11:51:54.162730
2113 11:51:54.165764 [0x00000000100000, 0x00000030000000)
2114 11:51:54.190952
2115 11:51:54.194058 [0x00000032662db0, 0x000000769ef000)
2116 11:51:54.230365
2117 11:51:54.233796 [0x00000100000000, 0x00000280400000)
2118 11:51:54.436064
2119 11:51:54.439299 ec_init: CrosEC protocol v3 supported (256, 256)
2120 11:51:54.439384
2121 11:51:54.445647 update_port_state: port C0 state: usb enable 1 mux conn 0
2122 11:51:54.445733
2123 11:51:54.452583 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2124 11:51:54.455425
2125 11:51:54.458928 pmc_check_ipc_sts: STS_BUSY done after 1562 us
2126 11:51:54.459013
2127 11:51:54.465777 send_conn_disc_msg: pmc_send_cmd succeeded
2128 11:51:54.895327
2129 11:51:54.895461 R8152: Initializing
2130 11:51:54.895533
2131 11:51:54.898716 Version 6 (ocp_data = 5c30)
2132 11:51:54.898792
2133 11:51:54.902226 R8152: Done initializing
2134 11:51:54.902304
2135 11:51:54.905259 Adding net device
2136 11:51:55.206687
2137 11:51:55.210016 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2138 11:51:55.210111
2139 11:51:55.210178
2140 11:51:55.210242
2141 11:51:55.213041 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2143 11:51:55.313523 volteer: tftpboot 192.168.201.1 10875908/tftp-deploy-rausi4ru/kernel/bzImage 10875908/tftp-deploy-rausi4ru/kernel/cmdline 10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
2144 11:51:55.314107 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2145 11:51:55.314552 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2146 11:51:55.319366 tftpboot 192.168.201.1 10875908/tftp-deploy-rausi4ru/kernel/bzIploy-rausi4ru/kernel/cmdline 10875908/tftp-deploy-rausi4ru/ramdisk/ramdisk.cpio.gz
2147 11:51:55.319853
2148 11:51:55.320279 Waiting for link
2149 11:51:55.521246
2150 11:51:55.521556 done.
2151 11:51:55.521753
2152 11:51:55.521933 MAC: 00:24:32:30:7b:ec
2153 11:51:55.522121
2154 11:51:55.524860 Sending DHCP discover... done.
2155 11:51:55.525088
2156 11:51:55.527715 Waiting for reply... done.
2157 11:51:55.527949
2158 11:51:55.531151 Sending DHCP request... done.
2159 11:51:55.531471
2160 11:51:55.537994 Waiting for reply... done.
2161 11:51:55.538234
2162 11:51:55.538420 My ip is 192.168.201.11
2163 11:51:55.538591
2164 11:51:55.541356 The DHCP server ip is 192.168.201.1
2165 11:51:55.541702
2166 11:51:55.547651 TFTP server IP predefined by user: 192.168.201.1
2167 11:51:55.547789
2168 11:51:55.554441 Bootfile predefined by user: 10875908/tftp-deploy-rausi4ru/kernel/bzImage
2169 11:51:55.554559
2170 11:51:55.557551 Sending tftp read request... done.
2171 11:51:55.557667
2172 11:51:55.561218 Waiting for the transfer...
2173 11:51:55.561334
2174 11:51:56.086514 00000000 ################################################################
2175 11:51:56.086657
2176 11:51:56.615485 00080000 ################################################################
2177 11:51:56.615623
2178 11:51:57.144985 00100000 ################################################################
2179 11:51:57.145123
2180 11:51:57.665103 00180000 ################################################################
2181 11:51:57.665269
2182 11:51:58.184817 00200000 ################################################################
2183 11:51:58.185005
2184 11:51:58.717228 00280000 ################################################################
2185 11:51:58.717396
2186 11:51:59.240697 00300000 ################################################################
2187 11:51:59.240836
2188 11:51:59.762430 00380000 ################################################################
2189 11:51:59.762587
2190 11:52:00.286658 00400000 ################################################################
2191 11:52:00.286868
2192 11:52:00.836837 00480000 ################################################################
2193 11:52:00.836977
2194 11:52:01.356115 00500000 ################################################################
2195 11:52:01.356298
2196 11:52:01.895870 00580000 ################################################################
2197 11:52:01.896014
2198 11:52:02.437761 00600000 ################################################################
2199 11:52:02.437911
2200 11:52:02.969518 00680000 ################################################################
2201 11:52:02.969680
2202 11:52:03.509620 00700000 ################################################################
2203 11:52:03.509766
2204 11:52:04.031388 00780000 ################################################################
2205 11:52:04.031540
2206 11:52:04.539329 00800000 ################################################################
2207 11:52:04.539486
2208 11:52:05.051429 00880000 ################################################################
2209 11:52:05.051580
2210 11:52:05.561746 00900000 ################################################################
2211 11:52:05.561922
2212 11:52:06.075142 00980000 ################################################################
2213 11:52:06.075334
2214 11:52:06.436116 00a00000 ############################################## done.
2215 11:52:06.436295
2216 11:52:06.439247 The bootfile was 10859008 bytes long.
2217 11:52:06.439361
2218 11:52:06.442865 Sending tftp read request... done.
2219 11:52:06.442957
2220 11:52:06.445952 Waiting for the transfer...
2221 11:52:06.446039
2222 11:52:06.961786 00000000 ################################################################
2223 11:52:06.961933
2224 11:52:07.479718 00080000 ################################################################
2225 11:52:07.479902
2226 11:52:07.990418 00100000 ################################################################
2227 11:52:07.990601
2228 11:52:08.500387 00180000 ################################################################
2229 11:52:08.500552
2230 11:52:09.006596 00200000 ################################################################
2231 11:52:09.006774
2232 11:52:09.521187 00280000 ################################################################
2233 11:52:09.521369
2234 11:52:10.029901 00300000 ################################################################
2235 11:52:10.030066
2236 11:52:10.542594 00380000 ################################################################
2237 11:52:10.542774
2238 11:52:11.058010 00400000 ################################################################
2239 11:52:11.058162
2240 11:52:11.565146 00480000 ################################################################
2241 11:52:11.565322
2242 11:52:12.073697 00500000 ################################################################
2243 11:52:12.073888
2244 11:52:12.597945 00580000 ################################################################
2245 11:52:12.598080
2246 11:52:13.120326 00600000 ################################################################
2247 11:52:13.120510
2248 11:52:13.635430 00680000 ################################################################
2249 11:52:13.635613
2250 11:52:14.161724 00700000 ################################################################
2251 11:52:14.161899
2252 11:52:14.672588 00780000 ################################################################
2253 11:52:14.672738
2254 11:52:15.180747 00800000 ################################################################
2255 11:52:15.180937
2256 11:52:15.473613 00880000 ##################################### done.
2257 11:52:15.473798
2258 11:52:15.476993 Sending tftp read request... done.
2259 11:52:15.477100
2260 11:52:15.480522 Waiting for the transfer...
2261 11:52:15.480644
2262 11:52:15.480743 00000000 # done.
2263 11:52:15.480840
2264 11:52:15.490663 Command line loaded dynamically from TFTP file: 10875908/tftp-deploy-rausi4ru/kernel/cmdline
2265 11:52:15.490784
2266 11:52:15.503696 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2267 11:52:15.507934
2268 11:52:15.511599 Shutting down all USB controllers.
2269 11:52:15.511701
2270 11:52:15.511777 Removing current net device
2271 11:52:15.511849
2272 11:52:15.514477 Finalizing coreboot
2273 11:52:15.514570
2274 11:52:15.521365 Exiting depthcharge with code 4 at timestamp: 30138823
2275 11:52:15.521452
2276 11:52:15.521531
2277 11:52:15.521596 Starting kernel ...
2278 11:52:15.521666
2279 11:52:15.521726
2280 11:52:15.522115 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
2281 11:52:15.522241 start: 2.2.5 auto-login-action (timeout 00:04:23) [common]
2282 11:52:15.522322 Setting prompt string to ['Linux version [0-9]']
2283 11:52:15.522400 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2284 11:52:15.522472 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2286 11:56:38.522489 end: 2.2.5 auto-login-action (duration 00:04:23) [common]
2288 11:56:38.522697 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 263 seconds'
2290 11:56:38.522859 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2293 11:56:38.523111 end: 2 depthcharge-action (duration 00:05:00) [common]
2295 11:56:38.523325 Cleaning after the job
2296 11:56:38.523416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/ramdisk
2297 11:56:38.524606 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/kernel
2298 11:56:38.525807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10875908/tftp-deploy-rausi4ru/modules
2299 11:56:38.526342 start: 5.1 power-off (timeout 00:00:30) [common]
2300 11:56:38.526499 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-0' '--port=1' '--command=off'
2301 11:56:38.602141 >> Command sent successfully.
2302 11:56:38.604404 Returned 0 in 0 seconds
2303 11:56:38.704829 end: 5.1 power-off (duration 00:00:00) [common]
2305 11:56:38.705144 start: 5.2 read-feedback (timeout 00:10:00) [common]
2306 11:56:38.705394 Listened to connection for namespace 'common' for up to 1s
2307 11:56:39.705377 Finalising connection for namespace 'common'
2308 11:56:39.705557 Disconnecting from shell: Finalise
2309 11:56:39.705637
2310 11:56:39.805958 end: 5.2 read-feedback (duration 00:00:01) [common]
2311 11:56:39.806115 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10875908
2312 11:56:39.820325 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10875908
2313 11:56:39.820471 JobError: Your job cannot terminate cleanly.