Boot log: asus-cx9400-volteer
- Errors: 2
- Warnings: 0
- Kernel Warnings: 0
- Boot result: FAIL
- Kernel Errors: 0
1 12:44:48.386412 lava-dispatcher, installed at version: 2022.04
2 12:44:48.386591 start: 0 validate
3 12:44:48.386720 Start time: 2022-07-14 12:44:48.386712+00:00 (UTC)
4 12:44:48.386838 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:44:48.386963 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20220708.0%2Fx86%2Frootfs.cpio.gz exists
6 12:44:48.682416 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:44:48.683145 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip69-508-gd887d54a1be6%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:44:48.973176 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:44:48.973917 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip69-508-gd887d54a1be6%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:44:49.274296 validate duration: 0.89
12 12:44:49.275632 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:44:49.276218 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:44:49.276769 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:44:49.277331 Not decompressing ramdisk as can be used compressed.
16 12:44:49.277817 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220708.0/x86/rootfs.cpio.gz
17 12:44:49.278190 saving as /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/ramdisk/rootfs.cpio.gz
18 12:44:49.278539 total size: 8415743 (8MB)
19 12:44:49.283860 progress 0% (0MB)
20 12:44:49.295725 progress 5% (0MB)
21 12:44:49.304450 progress 10% (0MB)
22 12:44:49.310159 progress 15% (1MB)
23 12:44:49.314724 progress 20% (1MB)
24 12:44:49.318688 progress 25% (2MB)
25 12:44:49.322102 progress 30% (2MB)
26 12:44:49.325030 progress 35% (2MB)
27 12:44:49.328008 progress 40% (3MB)
28 12:44:49.330724 progress 45% (3MB)
29 12:44:49.333337 progress 50% (4MB)
30 12:44:49.335706 progress 55% (4MB)
31 12:44:49.338055 progress 60% (4MB)
32 12:44:49.340073 progress 65% (5MB)
33 12:44:49.342215 progress 70% (5MB)
34 12:44:49.344300 progress 75% (6MB)
35 12:44:49.346333 progress 80% (6MB)
36 12:44:49.348362 progress 85% (6MB)
37 12:44:49.350369 progress 90% (7MB)
38 12:44:49.352267 progress 95% (7MB)
39 12:44:49.354298 progress 100% (8MB)
40 12:44:49.354572 8MB downloaded in 0.08s (105.55MB/s)
41 12:44:49.354726 end: 1.1.1 http-download (duration 00:00:00) [common]
43 12:44:49.354974 end: 1.1 download-retry (duration 00:00:00) [common]
44 12:44:49.355063 start: 1.2 download-retry (timeout 00:10:00) [common]
45 12:44:49.355150 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 12:44:49.355255 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip69-508-gd887d54a1be6/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:44:49.355327 saving as /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/kernel/bzImage
48 12:44:49.355388 total size: 6811536 (6MB)
49 12:44:49.355449 No compression specified
50 12:44:52.863927 progress 0% (0MB)
51 12:44:52.868809 progress 5% (0MB)
52 12:44:52.870444 progress 10% (0MB)
53 12:44:52.872193 progress 15% (1MB)
54 12:44:52.873783 progress 20% (1MB)
55 12:44:52.875360 progress 25% (1MB)
56 12:44:52.877266 progress 30% (1MB)
57 12:44:52.878919 progress 35% (2MB)
58 12:44:52.880632 progress 40% (2MB)
59 12:44:52.882247 progress 45% (2MB)
60 12:44:52.883847 progress 50% (3MB)
61 12:44:52.885555 progress 55% (3MB)
62 12:44:52.887168 progress 60% (3MB)
63 12:44:52.888869 progress 65% (4MB)
64 12:44:52.890480 progress 70% (4MB)
65 12:44:52.892032 progress 75% (4MB)
66 12:44:52.893800 progress 80% (5MB)
67 12:44:52.895355 progress 85% (5MB)
68 12:44:52.897053 progress 90% (5MB)
69 12:44:52.898652 progress 95% (6MB)
70 12:44:52.900227 progress 100% (6MB)
71 12:44:52.900485 6MB downloaded in 3.55s (1.83MB/s)
72 12:44:52.900637 end: 1.2.1 http-download (duration 00:00:04) [common]
74 12:44:52.900871 end: 1.2 download-retry (duration 00:00:04) [common]
75 12:44:52.900960 start: 1.3 download-retry (timeout 00:09:56) [common]
76 12:44:52.901047 start: 1.3.1 http-download (timeout 00:09:56) [common]
77 12:44:52.901151 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip69-508-gd887d54a1be6/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:44:52.901219 saving as /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/modules/modules.tar
79 12:44:52.901279 total size: 51960 (0MB)
80 12:44:52.901340 Using unxz to decompress xz
81 12:44:52.904509 progress 63% (0MB)
82 12:44:52.904865 progress 100% (0MB)
83 12:44:52.908241 0MB downloaded in 0.01s (7.14MB/s)
84 12:44:52.908493 end: 1.3.1 http-download (duration 00:00:00) [common]
86 12:44:52.908756 end: 1.3 download-retry (duration 00:00:00) [common]
87 12:44:52.908854 start: 1.4 prepare-tftp-overlay (timeout 00:09:56) [common]
88 12:44:52.908949 start: 1.4.1 extract-nfsrootfs (timeout 00:09:56) [common]
89 12:44:52.909033 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 12:44:52.909120 start: 1.4.2 lava-overlay (timeout 00:09:56) [common]
91 12:44:52.909277 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr
92 12:44:52.909381 makedir: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin
93 12:44:52.909464 makedir: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/tests
94 12:44:52.909543 makedir: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/results
95 12:44:52.909688 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-add-keys
96 12:44:52.909814 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-add-sources
97 12:44:52.909929 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-background-process-start
98 12:44:52.910039 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-background-process-stop
99 12:44:52.910147 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-common-functions
100 12:44:52.910283 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-echo-ipv4
101 12:44:52.910392 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-install-packages
102 12:44:52.910499 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-installed-packages
103 12:44:52.910603 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-os-build
104 12:44:52.910709 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-probe-channel
105 12:44:52.910817 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-probe-ip
106 12:44:52.910923 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-target-ip
107 12:44:52.911031 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-target-mac
108 12:44:52.911136 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-target-storage
109 12:44:52.911246 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-case
110 12:44:52.911353 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-event
111 12:44:52.911460 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-feedback
112 12:44:52.911564 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-raise
113 12:44:52.911674 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-reference
114 12:44:52.911780 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-runner
115 12:44:52.911886 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-set
116 12:44:52.911990 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-test-shell
117 12:44:52.912096 Updating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-install-packages (oe)
118 12:44:52.912223 Updating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/bin/lava-installed-packages (oe)
119 12:44:52.912333 Creating /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/environment
120 12:44:52.912420 LAVA metadata
121 12:44:52.912488 - LAVA_JOB_ID=6819473
122 12:44:52.912551 - LAVA_DISPATCHER_IP=192.168.201.1
123 12:44:52.912651 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:56) [common]
124 12:44:52.912715 skipped lava-vland-overlay
125 12:44:52.912791 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 12:44:52.912873 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
127 12:44:52.912937 skipped lava-multinode-overlay
128 12:44:52.913010 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 12:44:52.913092 start: 1.4.2.3 test-definition (timeout 00:09:56) [common]
130 12:44:52.913167 Loading test definitions
131 12:44:52.913261 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:56) [common]
132 12:44:52.913339 Using /lava-6819473 at stage 0
133 12:44:52.913643 uuid=6819473_1.4.2.3.1 testdef=None
134 12:44:52.913734 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 12:44:52.913821 start: 1.4.2.3.2 test-overlay (timeout 00:09:56) [common]
136 12:44:52.914335 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 12:44:52.914559 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:56) [common]
139 12:44:52.915123 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 12:44:52.915364 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
142 12:44:52.915898 runner path: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/0/tests/0_dmesg test_uuid 6819473_1.4.2.3.1
143 12:44:52.916045 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 12:44:52.916275 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:56) [common]
146 12:44:52.916349 Using /lava-6819473 at stage 1
147 12:44:52.916585 uuid=6819473_1.4.2.3.5 testdef=None
148 12:44:52.916673 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 12:44:52.916762 start: 1.4.2.3.6 test-overlay (timeout 00:09:56) [common]
150 12:44:52.917195 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 12:44:52.917418 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:56) [common]
153 12:44:52.918020 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 12:44:52.918256 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
156 12:44:52.918800 runner path: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/1/tests/1_bootrr test_uuid 6819473_1.4.2.3.5
157 12:44:52.918940 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 12:44:52.919148 Creating lava-test-runner.conf files
160 12:44:52.919211 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/0 for stage 0
161 12:44:52.919291 - 0_dmesg
162 12:44:52.919364 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/6819473/lava-overlay-dcw88tbr/lava-6819473/1 for stage 1
163 12:44:52.919446 - 1_bootrr
164 12:44:52.919536 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 12:44:52.919624 start: 1.4.2.4 compress-overlay (timeout 00:09:56) [common]
166 12:44:52.925517 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 12:44:52.925698 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
168 12:44:52.925787 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 12:44:52.925872 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 12:44:52.925958 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
171 12:44:53.106319 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 12:44:53.106652 start: 1.4.4 extract-modules (timeout 00:09:56) [common]
173 12:44:53.106764 extracting modules file /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/modules/modules.tar to /var/lib/lava/dispatcher/tmp/6819473/extract-overlay-ramdisk-ndn4hw6s/ramdisk
174 12:44:53.110906 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 12:44:53.111016 start: 1.4.5 apply-overlay-tftp (timeout 00:09:56) [common]
176 12:44:53.111104 [common] Applying overlay /var/lib/lava/dispatcher/tmp/6819473/compress-overlay-y2v3btpi/overlay-1.4.2.4.tar.gz to ramdisk
177 12:44:53.111177 [common] Applying overlay /var/lib/lava/dispatcher/tmp/6819473/compress-overlay-y2v3btpi/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/6819473/extract-overlay-ramdisk-ndn4hw6s/ramdisk
178 12:44:53.114851 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 12:44:53.114956 start: 1.4.6 configure-preseed-file (timeout 00:09:56) [common]
180 12:44:53.115049 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 12:44:53.115140 start: 1.4.7 compress-ramdisk (timeout 00:09:56) [common]
182 12:44:53.115216 Building ramdisk /var/lib/lava/dispatcher/tmp/6819473/extract-overlay-ramdisk-ndn4hw6s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/6819473/extract-overlay-ramdisk-ndn4hw6s/ramdisk
183 12:44:53.178379 >> 48008 blocks
184 12:44:53.906217 rename /var/lib/lava/dispatcher/tmp/6819473/extract-overlay-ramdisk-ndn4hw6s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
185 12:44:53.906616 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 12:44:53.906743 start: 1.4.8 prepare-kernel (timeout 00:09:55) [common]
187 12:44:53.906899 start: 1.4.8.1 prepare-fit (timeout 00:09:55) [common]
188 12:44:53.906991 No mkimage arch provided, not using FIT.
189 12:44:53.907080 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 12:44:53.907160 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 12:44:53.907262 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 12:44:53.907354 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:55) [common]
193 12:44:53.907427 No LXC device requested
194 12:44:53.907505 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 12:44:53.907592 start: 1.6 deploy-device-env (timeout 00:09:55) [common]
196 12:44:53.907672 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 12:44:53.907741 Checking files for TFTP limit of 4294967296 bytes.
198 12:44:53.908110 end: 1 tftp-deploy (duration 00:00:05) [common]
199 12:44:53.908209 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 12:44:53.908301 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 12:44:53.908420 substitutions:
202 12:44:53.908484 - {DTB}: None
203 12:44:53.908548 - {INITRD}: 6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
204 12:44:53.908606 - {KERNEL}: 6819473/tftp-deploy-a7c9kj42/kernel/bzImage
205 12:44:53.908665 - {LAVA_MAC}: None
206 12:44:53.908721 - {PRESEED_CONFIG}: None
207 12:44:53.908778 - {PRESEED_LOCAL}: None
208 12:44:53.908831 - {RAMDISK}: 6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
209 12:44:53.908885 - {ROOT_PART}: None
210 12:44:53.908937 - {ROOT}: None
211 12:44:53.908990 - {SERVER_IP}: 192.168.201.1
212 12:44:53.909043 - {TEE}: None
213 12:44:53.909095 Parsed boot commands:
214 12:44:53.909156 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 12:44:53.909304 Parsed boot commands: tftpboot 192.168.201.1 6819473/tftp-deploy-a7c9kj42/kernel/bzImage 6819473/tftp-deploy-a7c9kj42/kernel/cmdline 6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
216 12:44:53.909410 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 12:44:53.909499 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 12:44:53.909673 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 12:44:53.909765 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 12:44:53.909836 Not connected, no need to disconnect.
221 12:44:53.909912 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 12:44:53.909997 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 12:44:53.910063 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-1'
224 12:44:53.912723 Setting prompt string to ['lava-test: # ']
225 12:44:53.912996 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 12:44:53.913097 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 12:44:53.913191 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 12:44:53.913281 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 12:44:53.913464 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-1' '--port=1' '--command=reboot'
230 12:44:53.932396 >> Command sent successfully.
231 12:44:53.934213 Returned 0 in 0 seconds
232 12:44:54.035325 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 12:44:54.036944 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 12:44:54.037044 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 12:44:54.037133 Setting prompt string to 'Starting depthcharge on Voema...'
237 12:44:54.037197 Changing prompt to 'Starting depthcharge on Voema...'
238 12:44:54.037262 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
239 12:44:54.037521 [Enter `^Ec?' for help]
240 12:45:00.898423
241 12:45:00.899070
242 12:45:00.908317 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
243 12:45:00.912038 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
244 12:45:00.918170 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
245 12:45:00.921446 CPU: AES supported, TXT NOT supported, VT supported
246 12:45:00.928268 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
247 12:45:00.935147 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
248 12:45:00.938005 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
249 12:45:00.941090 VBOOT: Loading verstage.
250 12:45:00.944777 FMAP: Found \"FLASH\" version 1.1 at 0x1804000.
251 12:45:00.951325 FMAP: base = 0x0 size = 0x2000000 #areas = 32
252 12:45:00.955006 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
253 12:45:00.965701 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
254 12:45:00.971911 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
255 12:45:00.972502
256 12:45:00.972892
257 12:45:00.985498 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
258 12:45:00.998877 Probing TPM: . done!
259 12:45:01.002431 TPM ready after 0 ms
260 12:45:01.005685 Connected to device vid:did:rid of 1ae0:0028:00
261 12:45:01.017648 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
262 12:45:01.023400 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
263 12:45:01.026517 Initialized TPM device CR50 revision 0
264 12:45:01.077096 tlcl_send_startup: Startup return code is 0
265 12:45:01.077758 TPM: setup succeeded
266 12:45:01.092996 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
267 12:45:01.107038 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
268 12:45:01.119543 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
269 12:45:01.129021 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
270 12:45:01.132863 Chrome EC: UHEPI supported
271 12:45:01.136402 Phase 1
272 12:45:01.139938 FMAP: area GBB found @ 1805000 (458752 bytes)
273 12:45:01.149508 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
274 12:45:01.155965 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
275 12:45:01.162610 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
276 12:45:01.169511 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
277 12:45:01.173056 Recovery requested (1009000e)
278 12:45:01.176289 TPM: Extending digest for VBOOT: boot mode into PCR 0
279 12:45:01.187900 tlcl_extend: response is 0
280 12:45:01.194932 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
281 12:45:01.204755 tlcl_extend: response is 0
282 12:45:01.211385 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
283 12:45:01.218105 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
284 12:45:01.224341 BS: verstage times (exec / console): total (unknown) / 142 ms
285 12:45:01.224937
286 12:45:01.225329
287 12:45:01.237933 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
288 12:45:01.244287 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
289 12:45:01.247686 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
290 12:45:01.251003 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
291 12:45:01.257414 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
292 12:45:01.260647 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
293 12:45:01.263856 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
294 12:45:01.267333 TCO_STS: 0000 0000
295 12:45:01.270636 GEN_PMCON: d0015038 00002200
296 12:45:01.274206 GBLRST_CAUSE: 00000000 00000000
297 12:45:01.274693 HPR_CAUSE0: 00000000
298 12:45:01.277940 prev_sleep_state 5
299 12:45:01.281269 Boot Count incremented to 9997
300 12:45:01.287550 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
301 12:45:01.293995 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
302 12:45:01.300940 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
303 12:45:01.307315 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
304 12:45:01.312616 Chrome EC: UHEPI supported
305 12:45:01.318751 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
306 12:45:01.331280 Probing TPM: done!
307 12:45:01.338822 Connected to device vid:did:rid of 1ae0:0028:00
308 12:45:01.349162 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
309 12:45:01.356186 Initialized TPM device CR50 revision 0
310 12:45:01.366327 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
311 12:45:01.373315 MRC: Hash idx 0x100b comparison successful.
312 12:45:01.376051 MRC cache found, size faa8
313 12:45:01.376551 bootmode is set to: 2
314 12:45:01.379776 SPD index = 0
315 12:45:01.386209 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
316 12:45:01.389723 SPD: module type is LPDDR4X
317 12:45:01.393281 SPD: module part number is MT53E512M64D4NW-046
318 12:45:01.399701 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
319 12:45:01.402949 SPD: device width 16 bits, bus width 16 bits
320 12:45:01.409621 SPD: module size is 1024 MB (per channel)
321 12:45:01.839477 CBMEM:
322 12:45:01.842809 IMD: root @ 0x76fff000 254 entries.
323 12:45:01.845503 IMD: root @ 0x76ffec00 62 entries.
324 12:45:01.849161 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
325 12:45:01.856230 FMAP: area RW_VPD found @ f35000 (8192 bytes)
326 12:45:01.859372 External stage cache:
327 12:45:01.862274 IMD: root @ 0x7b3ff000 254 entries.
328 12:45:01.865486 IMD: root @ 0x7b3fec00 62 entries.
329 12:45:01.881209 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
330 12:45:01.887447 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
331 12:45:01.894043 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
332 12:45:01.908386 MRC: 'RECOVERY_MRC_CACHE' does not need update.
333 12:45:01.912138 cse_lite: Skip switching to RW in the recovery path
334 12:45:01.915341 8 DIMMs found
335 12:45:01.915843 SMM Memory Map
336 12:45:01.919480 SMRAM : 0x7b000000 0x800000
337 12:45:01.923162 Subregion 0: 0x7b000000 0x200000
338 12:45:01.926307 Subregion 1: 0x7b200000 0x200000
339 12:45:01.929267 Subregion 2: 0x7b400000 0x400000
340 12:45:01.931998 top_of_ram = 0x77000000
341 12:45:01.939040 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
342 12:45:01.942165 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
343 12:45:01.948531 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
344 12:45:01.952001 MTRR Range: Start=ff000000 End=0 (Size 1000000)
345 12:45:01.962296 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
346 12:45:01.969140 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
347 12:45:01.978904 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
348 12:45:01.981818 Processing 211 relocs. Offset value of 0x74c0b000
349 12:45:01.990815 BS: romstage times (exec / console): total (unknown) / 277 ms
350 12:45:01.997360
351 12:45:01.997992
352 12:45:02.006951 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
353 12:45:02.010463 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
354 12:45:02.020326 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
355 12:45:02.027377 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
356 12:45:02.033630 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
357 12:45:02.040204 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
358 12:45:02.087065 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
359 12:45:02.093431 Processing 5008 relocs. Offset value of 0x75d98000
360 12:45:02.096979 BS: postcar times (exec / console): total (unknown) / 59 ms
361 12:45:02.100519
362 12:45:02.101119
363 12:45:02.110480 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
364 12:45:02.111092 Normal boot
365 12:45:02.114422 FW_CONFIG value is 0x804c02
366 12:45:02.116943 PCI: 00:07.0 disabled by fw_config
367 12:45:02.120726 PCI: 00:07.1 disabled by fw_config
368 12:45:02.123762 PCI: 00:0d.2 disabled by fw_config
369 12:45:02.128280 PCI: 00:1c.7 disabled by fw_config
370 12:45:02.134209 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
371 12:45:02.140644 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
372 12:45:02.143621 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
373 12:45:02.147130 GENERIC: 0.0 disabled by fw_config
374 12:45:02.150245 GENERIC: 1.0 disabled by fw_config
375 12:45:02.157545 fw_config match found: DB_USB=USB3_ACTIVE
376 12:45:02.160290 fw_config match found: DB_USB=USB3_ACTIVE
377 12:45:02.163623 fw_config match found: DB_USB=USB3_ACTIVE
378 12:45:02.170189 fw_config match found: DB_USB=USB3_ACTIVE
379 12:45:02.173830 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
380 12:45:02.181074 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
381 12:45:02.189872 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
382 12:45:02.196579 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
383 12:45:02.200303 microcode: sig=0x806c1 pf=0x80 revision=0x86
384 12:45:02.206908 microcode: Update skipped, already up-to-date
385 12:45:02.213223 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
386 12:45:02.240699 Detected 4 core, 8 thread CPU.
387 12:45:02.244218 Setting up SMI for CPU
388 12:45:02.247317 IED base = 0x7b400000
389 12:45:02.247842 IED size = 0x00400000
390 12:45:02.250301 Will perform SMM setup.
391 12:45:02.256895 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
392 12:45:02.263749 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
393 12:45:02.270256 Processing 16 relocs. Offset value of 0x00030000
394 12:45:02.273732 Attempting to start 7 APs
395 12:45:02.277117 Waiting for 10ms after sending INIT.
396 12:45:02.292775 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
397 12:45:02.293398 done.
398 12:45:02.295841 AP: slot 5 apic_id 4.
399 12:45:02.299231 AP: slot 4 apic_id 5.
400 12:45:02.302324 Waiting for 2nd SIPI to complete...done.
401 12:45:02.306411 AP: slot 3 apic_id 7.
402 12:45:02.306998 AP: slot 7 apic_id 6.
403 12:45:02.309607 AP: slot 2 apic_id 3.
404 12:45:02.312905 AP: slot 6 apic_id 2.
405 12:45:02.319503 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
406 12:45:02.326099 Processing 13 relocs. Offset value of 0x00038000
407 12:45:02.326701 Unable to locate Global NVS
408 12:45:02.335698 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
409 12:45:02.339241 Installing permanent SMM handler to 0x7b000000
410 12:45:02.348908 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
411 12:45:02.352177 Processing 794 relocs. Offset value of 0x7b010000
412 12:45:02.362556 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
413 12:45:02.365904 Processing 13 relocs. Offset value of 0x7b008000
414 12:45:02.372833 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
415 12:45:02.378777 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
416 12:45:02.382184 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
417 12:45:02.388681 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
418 12:45:02.395964 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
419 12:45:02.402155 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
420 12:45:02.408973 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
421 12:45:02.409558 Unable to locate Global NVS
422 12:45:02.419173 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
423 12:45:02.422269 Clearing SMI status registers
424 12:45:02.422852 SMI_STS: PM1
425 12:45:02.425740 PM1_STS: PWRBTN
426 12:45:02.431724 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
427 12:45:02.435195 In relocation handler: CPU 0
428 12:45:02.438547 New SMBASE=0x7b000000 IEDBASE=0x7b400000
429 12:45:02.445497 Writing SMRR. base = 0x7b000006, mask=0xff800c00
430 12:45:02.446144 Relocation complete.
431 12:45:02.454930 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
432 12:45:02.455517 In relocation handler: CPU 1
433 12:45:02.461892 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
434 12:45:02.462481 Relocation complete.
435 12:45:02.471830 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
436 12:45:02.472417 In relocation handler: CPU 4
437 12:45:02.478892 New SMBASE=0x7afff000 IEDBASE=0x7b400000
438 12:45:02.479489 Relocation complete.
439 12:45:02.488390 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
440 12:45:02.488978 In relocation handler: CPU 5
441 12:45:02.494987 New SMBASE=0x7affec00 IEDBASE=0x7b400000
442 12:45:02.498612 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 12:45:02.501457 Relocation complete.
444 12:45:02.508260 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
445 12:45:02.511745 In relocation handler: CPU 6
446 12:45:02.514880 New SMBASE=0x7affe800 IEDBASE=0x7b400000
447 12:45:02.521756 Writing SMRR. base = 0x7b000006, mask=0xff800c00
448 12:45:02.522337 Relocation complete.
449 12:45:02.528485 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
450 12:45:02.531803 In relocation handler: CPU 2
451 12:45:02.537745 New SMBASE=0x7afff800 IEDBASE=0x7b400000
452 12:45:02.538255 Relocation complete.
453 12:45:02.544741 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
454 12:45:02.548195 In relocation handler: CPU 3
455 12:45:02.551430 New SMBASE=0x7afff400 IEDBASE=0x7b400000
456 12:45:02.554818 Relocation complete.
457 12:45:02.562029 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
458 12:45:02.564619 In relocation handler: CPU 7
459 12:45:02.568028 New SMBASE=0x7affe400 IEDBASE=0x7b400000
460 12:45:02.575364 Writing SMRR. base = 0x7b000006, mask=0xff800c00
461 12:45:02.575967 Relocation complete.
462 12:45:02.578935 Initializing CPU #0
463 12:45:02.582550 CPU: vendor Intel device 806c1
464 12:45:02.585837 CPU: family 06, model 8c, stepping 01
465 12:45:02.589050 Clearing out pending MCEs
466 12:45:02.592461 Setting up local APIC...
467 12:45:02.592949 apic_id: 0x00 done.
468 12:45:02.596062 Turbo is available but hidden
469 12:45:02.599342 Turbo is available and visible
470 12:45:02.602587 microcode: Update skipped, already up-to-date
471 12:45:02.606188 CPU #0 initialized
472 12:45:02.609987 Initializing CPU #3
473 12:45:02.610566 Initializing CPU #7
474 12:45:02.612600 CPU: vendor Intel device 806c1
475 12:45:02.617073 CPU: family 06, model 8c, stepping 01
476 12:45:02.619606 CPU: vendor Intel device 806c1
477 12:45:02.622891 CPU: family 06, model 8c, stepping 01
478 12:45:02.626160 Clearing out pending MCEs
479 12:45:02.629730 Clearing out pending MCEs
480 12:45:02.632836 Setting up local APIC...
481 12:45:02.633475 Initializing CPU #1
482 12:45:02.635811 apic_id: 0x07 done.
483 12:45:02.639029 Setting up local APIC...
484 12:45:02.639508 Initializing CPU #6
485 12:45:02.642624 Initializing CPU #2
486 12:45:02.646145 CPU: vendor Intel device 806c1
487 12:45:02.649149 CPU: family 06, model 8c, stepping 01
488 12:45:02.653068 CPU: vendor Intel device 806c1
489 12:45:02.656478 CPU: family 06, model 8c, stepping 01
490 12:45:02.659427 Clearing out pending MCEs
491 12:45:02.662402 Clearing out pending MCEs
492 12:45:02.665830 microcode: Update skipped, already up-to-date
493 12:45:02.669023 apic_id: 0x06 done.
494 12:45:02.669510 CPU #3 initialized
495 12:45:02.676218 microcode: Update skipped, already up-to-date
496 12:45:02.676807 Initializing CPU #5
497 12:45:02.679258 Initializing CPU #4
498 12:45:02.682649 CPU: vendor Intel device 806c1
499 12:45:02.686199 CPU: family 06, model 8c, stepping 01
500 12:45:02.689532 CPU: vendor Intel device 806c1
501 12:45:02.692517 CPU: family 06, model 8c, stepping 01
502 12:45:02.695776 Clearing out pending MCEs
503 12:45:02.699091 Clearing out pending MCEs
504 12:45:02.702888 Setting up local APIC...
505 12:45:02.703447 CPU #7 initialized
506 12:45:02.705907 Setting up local APIC...
507 12:45:02.709119 Setting up local APIC...
508 12:45:02.709627 Setting up local APIC...
509 12:45:02.712374 CPU: vendor Intel device 806c1
510 12:45:02.718976 CPU: family 06, model 8c, stepping 01
511 12:45:02.719570 apic_id: 0x05 done.
512 12:45:02.722562 apic_id: 0x04 done.
513 12:45:02.726291 microcode: Update skipped, already up-to-date
514 12:45:02.732423 microcode: Update skipped, already up-to-date
515 12:45:02.733143 Clearing out pending MCEs
516 12:45:02.735742 CPU #5 initialized
517 12:45:02.738688 CPU #4 initialized
518 12:45:02.739179 Setting up local APIC...
519 12:45:02.742656 apic_id: 0x03 done.
520 12:45:02.746146 apic_id: 0x02 done.
521 12:45:02.749121 microcode: Update skipped, already up-to-date
522 12:45:02.752310 microcode: Update skipped, already up-to-date
523 12:45:02.755601 CPU #2 initialized
524 12:45:02.759055 CPU #6 initialized
525 12:45:02.759647 apic_id: 0x01 done.
526 12:45:02.765294 microcode: Update skipped, already up-to-date
527 12:45:02.765809 CPU #1 initialized
528 12:45:02.772151 bsp_do_flight_plan done after 464 msecs.
529 12:45:02.772640 CPU: frequency set to 4000 MHz
530 12:45:02.775428 Enabling SMIs.
531 12:45:02.782323 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
532 12:45:02.797540 SATAXPCIE1 indicates PCIe NVMe is present
533 12:45:02.800993 Probing TPM: done!
534 12:45:02.804239 Connected to device vid:did:rid of 1ae0:0028:00
535 12:45:02.815661 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
536 12:45:02.818340 Initialized TPM device CR50 revision 0
537 12:45:02.821449 Enabling S0i3.4
538 12:45:02.828154 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
539 12:45:02.832038 Found a VBT of 8704 bytes after decompression
540 12:45:02.838064 cse_lite: CSE RO boot. HybridStorageMode disabled
541 12:45:02.844946 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
542 12:45:02.921007 FSPS returned 0
543 12:45:02.924126 Executing Phase 1 of FspMultiPhaseSiInit
544 12:45:02.933934 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
545 12:45:02.937215 port C0 DISC req: usage 1 usb3 1 usb2 5
546 12:45:02.940693 Raw Buffer output 0 00000511
547 12:45:02.943939 Raw Buffer output 1 00000000
548 12:45:02.947679 pmc_send_ipc_cmd succeeded
549 12:45:02.954515 port C1 DISC req: usage 1 usb3 2 usb2 3
550 12:45:02.955107 Raw Buffer output 0 00000321
551 12:45:02.957881 Raw Buffer output 1 00000000
552 12:45:02.962174 pmc_send_ipc_cmd succeeded
553 12:45:02.966984 Detected 4 core, 8 thread CPU.
554 12:45:02.970359 Detected 4 core, 8 thread CPU.
555 12:45:03.204242 Display FSP Version Info HOB
556 12:45:03.207931 Reference Code - CPU = a.0.4c.31
557 12:45:03.211066 uCode Version = 0.0.0.86
558 12:45:03.214303 TXT ACM version = ff.ff.ff.ffff
559 12:45:03.217489 Reference Code - ME = a.0.4c.31
560 12:45:03.220901 MEBx version = 0.0.0.0
561 12:45:03.224637 ME Firmware Version = Consumer SKU
562 12:45:03.227654 Reference Code - PCH = a.0.4c.31
563 12:45:03.230819 PCH-CRID Status = Disabled
564 12:45:03.234414 PCH-CRID Original Value = ff.ff.ff.ffff
565 12:45:03.237268 PCH-CRID New Value = ff.ff.ff.ffff
566 12:45:03.240424 OPROM - RST - RAID = ff.ff.ff.ffff
567 12:45:03.244338 PCH Hsio Version = 4.0.0.0
568 12:45:03.247382 Reference Code - SA - System Agent = a.0.4c.31
569 12:45:03.251071 Reference Code - MRC = 2.0.0.1
570 12:45:03.254268 SA - PCIe Version = a.0.4c.31
571 12:45:03.257960 SA-CRID Status = Disabled
572 12:45:03.261062 SA-CRID Original Value = 0.0.0.1
573 12:45:03.264054 SA-CRID New Value = 0.0.0.1
574 12:45:03.267712 OPROM - VBIOS = ff.ff.ff.ffff
575 12:45:03.270541 IO Manageability Engine FW Version = 11.1.4.0
576 12:45:03.274191 PHY Build Version = 0.0.0.e0
577 12:45:03.277661 Thunderbolt(TM) FW Version = 0.0.0.0
578 12:45:03.284238 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
579 12:45:03.287496 ITSS IRQ Polarities Before:
580 12:45:03.288093 IPC0: 0xffffffff
581 12:45:03.290596 IPC1: 0xffffffff
582 12:45:03.291086 IPC2: 0xffffffff
583 12:45:03.293951 IPC3: 0xffffffff
584 12:45:03.297383 ITSS IRQ Polarities After:
585 12:45:03.298034 IPC0: 0xffffffff
586 12:45:03.301099 IPC1: 0xffffffff
587 12:45:03.301620 IPC2: 0xffffffff
588 12:45:03.304891 IPC3: 0xffffffff
589 12:45:03.308238 Found PCIe Root Port #9 at PCI: 00:1d.0.
590 12:45:03.320900 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
591 12:45:03.330841 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
592 12:45:03.344348 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
593 12:45:03.350745 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
594 12:45:03.351366 Enumerating buses...
595 12:45:03.357413 Show all devs... Before device enumeration.
596 12:45:03.358078 Root Device: enabled 1
597 12:45:03.360663 DOMAIN: 0000: enabled 1
598 12:45:03.365168 CPU_CLUSTER: 0: enabled 1
599 12:45:03.367003 PCI: 00:00.0: enabled 1
600 12:45:03.367497 PCI: 00:02.0: enabled 1
601 12:45:03.370365 PCI: 00:04.0: enabled 1
602 12:45:03.373955 PCI: 00:05.0: enabled 1
603 12:45:03.377315 PCI: 00:06.0: enabled 0
604 12:45:03.377951 PCI: 00:07.0: enabled 0
605 12:45:03.380214 PCI: 00:07.1: enabled 0
606 12:45:03.384135 PCI: 00:07.2: enabled 0
607 12:45:03.387560 PCI: 00:07.3: enabled 0
608 12:45:03.388156 PCI: 00:08.0: enabled 1
609 12:45:03.390634 PCI: 00:09.0: enabled 0
610 12:45:03.393768 PCI: 00:0a.0: enabled 0
611 12:45:03.397312 PCI: 00:0d.0: enabled 1
612 12:45:03.397938 PCI: 00:0d.1: enabled 0
613 12:45:03.400391 PCI: 00:0d.2: enabled 0
614 12:45:03.404005 PCI: 00:0d.3: enabled 0
615 12:45:03.404601 PCI: 00:0e.0: enabled 0
616 12:45:03.406855 PCI: 00:10.2: enabled 1
617 12:45:03.410390 PCI: 00:10.6: enabled 0
618 12:45:03.413975 PCI: 00:10.7: enabled 0
619 12:45:03.414564 PCI: 00:12.0: enabled 0
620 12:45:03.416798 PCI: 00:12.6: enabled 0
621 12:45:03.420073 PCI: 00:13.0: enabled 0
622 12:45:03.423775 PCI: 00:14.0: enabled 1
623 12:45:03.424372 PCI: 00:14.1: enabled 0
624 12:45:03.427062 PCI: 00:14.2: enabled 1
625 12:45:03.430296 PCI: 00:14.3: enabled 1
626 12:45:03.433767 PCI: 00:15.0: enabled 1
627 12:45:03.434354 PCI: 00:15.1: enabled 1
628 12:45:03.437461 PCI: 00:15.2: enabled 1
629 12:45:03.440056 PCI: 00:15.3: enabled 1
630 12:45:03.443685 PCI: 00:16.0: enabled 1
631 12:45:03.444176 PCI: 00:16.1: enabled 0
632 12:45:03.446656 PCI: 00:16.2: enabled 0
633 12:45:03.450086 PCI: 00:16.3: enabled 0
634 12:45:03.450578 PCI: 00:16.4: enabled 0
635 12:45:03.453342 PCI: 00:16.5: enabled 0
636 12:45:03.457077 PCI: 00:17.0: enabled 1
637 12:45:03.460497 PCI: 00:19.0: enabled 0
638 12:45:03.461078 PCI: 00:19.1: enabled 1
639 12:45:03.463684 PCI: 00:19.2: enabled 0
640 12:45:03.467827 PCI: 00:1c.0: enabled 1
641 12:45:03.470093 PCI: 00:1c.1: enabled 0
642 12:45:03.470587 PCI: 00:1c.2: enabled 0
643 12:45:03.474032 PCI: 00:1c.3: enabled 0
644 12:45:03.476966 PCI: 00:1c.4: enabled 0
645 12:45:03.480252 PCI: 00:1c.5: enabled 0
646 12:45:03.480836 PCI: 00:1c.6: enabled 1
647 12:45:03.483484 PCI: 00:1c.7: enabled 0
648 12:45:03.486597 PCI: 00:1d.0: enabled 1
649 12:45:03.487186 PCI: 00:1d.1: enabled 0
650 12:45:03.490327 PCI: 00:1d.2: enabled 1
651 12:45:03.493326 PCI: 00:1d.3: enabled 0
652 12:45:03.497392 PCI: 00:1e.0: enabled 1
653 12:45:03.498017 PCI: 00:1e.1: enabled 0
654 12:45:03.500048 PCI: 00:1e.2: enabled 1
655 12:45:03.503034 PCI: 00:1e.3: enabled 1
656 12:45:03.506540 PCI: 00:1f.0: enabled 1
657 12:45:03.507034 PCI: 00:1f.1: enabled 0
658 12:45:03.510064 PCI: 00:1f.2: enabled 1
659 12:45:03.513236 PCI: 00:1f.3: enabled 1
660 12:45:03.516491 PCI: 00:1f.4: enabled 0
661 12:45:03.517072 PCI: 00:1f.5: enabled 1
662 12:45:03.520125 PCI: 00:1f.6: enabled 0
663 12:45:03.523449 PCI: 00:1f.7: enabled 0
664 12:45:03.523944 APIC: 00: enabled 1
665 12:45:03.526712 GENERIC: 0.0: enabled 1
666 12:45:03.530355 GENERIC: 0.0: enabled 1
667 12:45:03.533524 GENERIC: 1.0: enabled 1
668 12:45:03.534141 GENERIC: 0.0: enabled 1
669 12:45:03.536465 GENERIC: 1.0: enabled 1
670 12:45:03.540009 USB0 port 0: enabled 1
671 12:45:03.543828 GENERIC: 0.0: enabled 1
672 12:45:03.544452 USB0 port 0: enabled 1
673 12:45:03.546345 GENERIC: 0.0: enabled 1
674 12:45:03.550361 I2C: 00:1a: enabled 1
675 12:45:03.550944 I2C: 00:31: enabled 1
676 12:45:03.553068 I2C: 00:32: enabled 1
677 12:45:03.556530 I2C: 00:10: enabled 1
678 12:45:03.557111 I2C: 00:15: enabled 1
679 12:45:03.560141 GENERIC: 0.0: enabled 0
680 12:45:03.563438 GENERIC: 1.0: enabled 0
681 12:45:03.566715 GENERIC: 0.0: enabled 1
682 12:45:03.567295 SPI: 00: enabled 1
683 12:45:03.569766 SPI: 00: enabled 1
684 12:45:03.570258 PNP: 0c09.0: enabled 1
685 12:45:03.573713 GENERIC: 0.0: enabled 1
686 12:45:03.576652 USB3 port 0: enabled 1
687 12:45:03.579957 USB3 port 1: enabled 1
688 12:45:03.580540 USB3 port 2: enabled 0
689 12:45:03.582833 USB3 port 3: enabled 0
690 12:45:03.586390 USB2 port 0: enabled 0
691 12:45:03.586986 USB2 port 1: enabled 1
692 12:45:03.589738 USB2 port 2: enabled 1
693 12:45:03.593177 USB2 port 3: enabled 0
694 12:45:03.597384 USB2 port 4: enabled 1
695 12:45:03.598001 USB2 port 5: enabled 0
696 12:45:03.599883 USB2 port 6: enabled 0
697 12:45:03.602731 USB2 port 7: enabled 0
698 12:45:03.603230 USB2 port 8: enabled 0
699 12:45:03.606517 USB2 port 9: enabled 0
700 12:45:03.609774 USB3 port 0: enabled 0
701 12:45:03.610361 USB3 port 1: enabled 1
702 12:45:03.613022 USB3 port 2: enabled 0
703 12:45:03.616499 USB3 port 3: enabled 0
704 12:45:03.619642 GENERIC: 0.0: enabled 1
705 12:45:03.620241 GENERIC: 1.0: enabled 1
706 12:45:03.623156 APIC: 01: enabled 1
707 12:45:03.626084 APIC: 03: enabled 1
708 12:45:03.626582 APIC: 07: enabled 1
709 12:45:03.629746 APIC: 05: enabled 1
710 12:45:03.630337 APIC: 04: enabled 1
711 12:45:03.633085 APIC: 02: enabled 1
712 12:45:03.636112 APIC: 06: enabled 1
713 12:45:03.636615 Compare with tree...
714 12:45:03.639393 Root Device: enabled 1
715 12:45:03.642824 DOMAIN: 0000: enabled 1
716 12:45:03.645966 PCI: 00:00.0: enabled 1
717 12:45:03.646481 PCI: 00:02.0: enabled 1
718 12:45:03.650018 PCI: 00:04.0: enabled 1
719 12:45:03.653311 GENERIC: 0.0: enabled 1
720 12:45:03.656617 PCI: 00:05.0: enabled 1
721 12:45:03.659845 PCI: 00:06.0: enabled 0
722 12:45:03.660456 PCI: 00:07.0: enabled 0
723 12:45:03.662881 GENERIC: 0.0: enabled 1
724 12:45:03.666164 PCI: 00:07.1: enabled 0
725 12:45:03.669514 GENERIC: 1.0: enabled 1
726 12:45:03.673144 PCI: 00:07.2: enabled 0
727 12:45:03.673770 GENERIC: 0.0: enabled 1
728 12:45:03.676769 PCI: 00:07.3: enabled 0
729 12:45:03.679360 GENERIC: 1.0: enabled 1
730 12:45:03.682673 PCI: 00:08.0: enabled 1
731 12:45:03.686002 PCI: 00:09.0: enabled 0
732 12:45:03.686683 PCI: 00:0a.0: enabled 0
733 12:45:03.689511 PCI: 00:0d.0: enabled 1
734 12:45:03.692634 USB0 port 0: enabled 1
735 12:45:03.695859 USB3 port 0: enabled 1
736 12:45:03.699083 USB3 port 1: enabled 1
737 12:45:03.699573 USB3 port 2: enabled 0
738 12:45:03.703564 USB3 port 3: enabled 0
739 12:45:03.705802 PCI: 00:0d.1: enabled 0
740 12:45:03.709708 PCI: 00:0d.2: enabled 0
741 12:45:03.712970 GENERIC: 0.0: enabled 1
742 12:45:03.716328 PCI: 00:0d.3: enabled 0
743 12:45:03.716933 PCI: 00:0e.0: enabled 0
744 12:45:03.719036 PCI: 00:10.2: enabled 1
745 12:45:03.722562 PCI: 00:10.6: enabled 0
746 12:45:03.725752 PCI: 00:10.7: enabled 0
747 12:45:03.726249 PCI: 00:12.0: enabled 0
748 12:45:03.729076 PCI: 00:12.6: enabled 0
749 12:45:03.732884 PCI: 00:13.0: enabled 0
750 12:45:03.735742 PCI: 00:14.0: enabled 1
751 12:45:03.738975 USB0 port 0: enabled 1
752 12:45:03.739483 USB2 port 0: enabled 0
753 12:45:03.742477 USB2 port 1: enabled 1
754 12:45:03.745756 USB2 port 2: enabled 1
755 12:45:03.749795 USB2 port 3: enabled 0
756 12:45:03.752597 USB2 port 4: enabled 1
757 12:45:03.755897 USB2 port 5: enabled 0
758 12:45:03.756403 USB2 port 6: enabled 0
759 12:45:03.759050 USB2 port 7: enabled 0
760 12:45:03.762335 USB2 port 8: enabled 0
761 12:45:03.765966 USB2 port 9: enabled 0
762 12:45:03.769195 USB3 port 0: enabled 0
763 12:45:03.772411 USB3 port 1: enabled 1
764 12:45:03.772900 USB3 port 2: enabled 0
765 12:45:03.776327 USB3 port 3: enabled 0
766 12:45:03.779113 PCI: 00:14.1: enabled 0
767 12:45:03.782790 PCI: 00:14.2: enabled 1
768 12:45:03.785531 PCI: 00:14.3: enabled 1
769 12:45:03.786041 GENERIC: 0.0: enabled 1
770 12:45:03.788768 PCI: 00:15.0: enabled 1
771 12:45:03.792341 I2C: 00:1a: enabled 1
772 12:45:03.795754 I2C: 00:31: enabled 1
773 12:45:03.796353 I2C: 00:32: enabled 1
774 12:45:03.798961 PCI: 00:15.1: enabled 1
775 12:45:03.802433 I2C: 00:10: enabled 1
776 12:45:03.805701 PCI: 00:15.2: enabled 1
777 12:45:03.808650 PCI: 00:15.3: enabled 1
778 12:45:03.809146 PCI: 00:16.0: enabled 1
779 12:45:03.812545 PCI: 00:16.1: enabled 0
780 12:45:03.816359 PCI: 00:16.2: enabled 0
781 12:45:03.819724 PCI: 00:16.3: enabled 0
782 12:45:03.820219 PCI: 00:16.4: enabled 0
783 12:45:03.823466 PCI: 00:16.5: enabled 0
784 12:45:03.826320 PCI: 00:17.0: enabled 1
785 12:45:03.829840 PCI: 00:19.0: enabled 0
786 12:45:03.830421 PCI: 00:19.1: enabled 1
787 12:45:03.833054 I2C: 00:15: enabled 1
788 12:45:03.836598 PCI: 00:19.2: enabled 0
789 12:45:03.839725 PCI: 00:1d.0: enabled 1
790 12:45:03.843360 GENERIC: 0.0: enabled 1
791 12:45:03.843850 PCI: 00:1e.0: enabled 1
792 12:45:03.846246 PCI: 00:1e.1: enabled 0
793 12:45:03.849702 PCI: 00:1e.2: enabled 1
794 12:45:03.853163 SPI: 00: enabled 1
795 12:45:03.856327 PCI: 00:1e.3: enabled 1
796 12:45:03.856822 SPI: 00: enabled 1
797 12:45:03.859790 PCI: 00:1f.0: enabled 1
798 12:45:03.863658 PNP: 0c09.0: enabled 1
799 12:45:03.915041 PCI: 00:1f.1: enabled 0
800 12:45:03.915648 PCI: 00:1f.2: enabled 1
801 12:45:03.916043 GENERIC: 0.0: enabled 1
802 12:45:03.916788 GENERIC: 0.0: enabled 1
803 12:45:03.917198 GENERIC: 1.0: enabled 1
804 12:45:03.917552 PCI: 00:1f.3: enabled 1
805 12:45:03.917941 PCI: 00:1f.4: enabled 0
806 12:45:03.918273 PCI: 00:1f.5: enabled 1
807 12:45:03.918599 PCI: 00:1f.6: enabled 0
808 12:45:03.918923 PCI: 00:1f.7: enabled 0
809 12:45:03.919624 CPU_CLUSTER: 0: enabled 1
810 12:45:03.919996 APIC: 00: enabled 1
811 12:45:03.920329 APIC: 01: enabled 1
812 12:45:03.920655 APIC: 03: enabled 1
813 12:45:03.920973 APIC: 07: enabled 1
814 12:45:03.921288 APIC: 05: enabled 1
815 12:45:03.921659 APIC: 04: enabled 1
816 12:45:03.922003 APIC: 02: enabled 1
817 12:45:03.922322 APIC: 06: enabled 1
818 12:45:03.922637 Root Device scanning...
819 12:45:03.965157 scan_static_bus for Root Device
820 12:45:03.965794 DOMAIN: 0000 enabled
821 12:45:03.966194 CPU_CLUSTER: 0 enabled
822 12:45:03.966969 DOMAIN: 0000 scanning...
823 12:45:03.967369 PCI: pci_scan_bus for bus 00
824 12:45:03.967720 PCI: 00:00.0 [8086/0000] ops
825 12:45:03.968060 PCI: 00:00.0 [8086/9a12] enabled
826 12:45:03.968390 PCI: 00:02.0 [8086/0000] bus ops
827 12:45:03.968715 PCI: 00:02.0 [8086/9a40] enabled
828 12:45:03.969036 PCI: 00:04.0 [8086/0000] bus ops
829 12:45:03.969408 PCI: 00:04.0 [8086/9a03] enabled
830 12:45:03.969762 PCI: 00:05.0 [8086/9a19] enabled
831 12:45:03.970082 PCI: 00:07.0 [0000/0000] hidden
832 12:45:03.970397 PCI: 00:08.0 [8086/9a11] enabled
833 12:45:03.970712 PCI: 00:0a.0 [8086/9a0d] disabled
834 12:45:03.971399 PCI: 00:0d.0 [8086/0000] bus ops
835 12:45:03.994283 PCI: 00:0d.0 [8086/9a13] enabled
836 12:45:03.994881 PCI: 00:14.0 [8086/0000] bus ops
837 12:45:03.995658 PCI: 00:14.0 [8086/a0ed] enabled
838 12:45:03.996070 PCI: 00:14.2 [8086/a0ef] enabled
839 12:45:03.996429 PCI: 00:14.3 [8086/0000] bus ops
840 12:45:03.996771 PCI: 00:14.3 [8086/a0f0] enabled
841 12:45:03.997101 PCI: 00:15.0 [8086/0000] bus ops
842 12:45:03.997425 PCI: 00:15.0 [8086/a0e8] enabled
843 12:45:03.998152 PCI: 00:15.1 [8086/0000] bus ops
844 12:45:03.998517 PCI: 00:15.1 [8086/a0e9] enabled
845 12:45:04.001597 PCI: 00:15.2 [8086/0000] bus ops
846 12:45:04.004373 PCI: 00:15.2 [8086/a0ea] enabled
847 12:45:04.008186 PCI: 00:15.3 [8086/0000] bus ops
848 12:45:04.011415 PCI: 00:15.3 [8086/a0eb] enabled
849 12:45:04.014855 PCI: 00:16.0 [8086/0000] ops
850 12:45:04.017751 PCI: 00:16.0 [8086/a0e0] enabled
851 12:45:04.021435 PCI: Static device PCI: 00:17.0 not found, disabling it.
852 12:45:04.024485 PCI: 00:19.0 [8086/0000] bus ops
853 12:45:04.029136 PCI: 00:19.0 [8086/a0c5] disabled
854 12:45:04.030961 PCI: 00:19.1 [8086/0000] bus ops
855 12:45:04.034744 PCI: 00:19.1 [8086/a0c6] enabled
856 12:45:04.037546 PCI: 00:1d.0 [8086/0000] bus ops
857 12:45:04.041193 PCI: 00:1d.0 [8086/a0b0] enabled
858 12:45:04.044085 PCI: 00:1e.0 [8086/0000] ops
859 12:45:04.047435 PCI: 00:1e.0 [8086/a0a8] enabled
860 12:45:04.051410 PCI: 00:1e.2 [8086/0000] bus ops
861 12:45:04.054049 PCI: 00:1e.2 [8086/a0aa] enabled
862 12:45:04.057517 PCI: 00:1e.3 [8086/0000] bus ops
863 12:45:04.060857 PCI: 00:1e.3 [8086/a0ab] enabled
864 12:45:04.064131 PCI: 00:1f.0 [8086/0000] bus ops
865 12:45:04.067770 PCI: 00:1f.0 [8086/a087] enabled
866 12:45:04.070894 RTC Init
867 12:45:04.074209 Set power on after power failure.
868 12:45:04.074693 Disabling Deep S3
869 12:45:04.078164 Disabling Deep S3
870 12:45:04.080864 Disabling Deep S4
871 12:45:04.081349 Disabling Deep S4
872 12:45:04.085103 Disabling Deep S5
873 12:45:04.085718 Disabling Deep S5
874 12:45:04.087555 PCI: 00:1f.2 [0000/0000] hidden
875 12:45:04.090884 PCI: 00:1f.3 [8086/0000] bus ops
876 12:45:04.094132 PCI: 00:1f.3 [8086/a0c8] enabled
877 12:45:04.097706 PCI: 00:1f.5 [8086/0000] bus ops
878 12:45:04.100561 PCI: 00:1f.5 [8086/a0a4] enabled
879 12:45:04.103998 PCI: Leftover static devices:
880 12:45:04.107777 PCI: 00:10.2
881 12:45:04.108364 PCI: 00:10.6
882 12:45:04.108746 PCI: 00:10.7
883 12:45:04.111249 PCI: 00:06.0
884 12:45:04.111839 PCI: 00:07.1
885 12:45:04.113947 PCI: 00:07.2
886 12:45:04.114431 PCI: 00:07.3
887 12:45:04.114813 PCI: 00:09.0
888 12:45:04.118802 PCI: 00:0d.1
889 12:45:04.119391 PCI: 00:0d.2
890 12:45:04.120503 PCI: 00:0d.3
891 12:45:04.121110 PCI: 00:0e.0
892 12:45:04.121504 PCI: 00:12.0
893 12:45:04.124285 PCI: 00:12.6
894 12:45:04.124885 PCI: 00:13.0
895 12:45:04.127378 PCI: 00:14.1
896 12:45:04.127861 PCI: 00:16.1
897 12:45:04.130925 PCI: 00:16.2
898 12:45:04.131410 PCI: 00:16.3
899 12:45:04.131789 PCI: 00:16.4
900 12:45:04.134002 PCI: 00:16.5
901 12:45:04.134487 PCI: 00:17.0
902 12:45:04.137295 PCI: 00:19.2
903 12:45:04.137826 PCI: 00:1e.1
904 12:45:04.138283 PCI: 00:1f.1
905 12:45:04.141265 PCI: 00:1f.4
906 12:45:04.141928 PCI: 00:1f.6
907 12:45:04.143986 PCI: 00:1f.7
908 12:45:04.147214 PCI: Check your devicetree.cb.
909 12:45:04.147714 PCI: 00:02.0 scanning...
910 12:45:04.150685 scan_generic_bus for PCI: 00:02.0
911 12:45:04.157440 scan_generic_bus for PCI: 00:02.0 done
912 12:45:04.160534 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
913 12:45:04.163990 PCI: 00:04.0 scanning...
914 12:45:04.167104 scan_generic_bus for PCI: 00:04.0
915 12:45:04.170272 GENERIC: 0.0 enabled
916 12:45:04.173641 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
917 12:45:04.181039 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
918 12:45:04.183889 PCI: 00:0d.0 scanning...
919 12:45:04.187418 scan_static_bus for PCI: 00:0d.0
920 12:45:04.188088 USB0 port 0 enabled
921 12:45:04.190631 USB0 port 0 scanning...
922 12:45:04.193560 scan_static_bus for USB0 port 0
923 12:45:04.196912 USB3 port 0 enabled
924 12:45:04.197341 USB3 port 1 enabled
925 12:45:04.200611 USB3 port 2 disabled
926 12:45:04.203539 USB3 port 3 disabled
927 12:45:04.203968 USB3 port 0 scanning...
928 12:45:04.207217 scan_static_bus for USB3 port 0
929 12:45:04.214015 scan_static_bus for USB3 port 0 done
930 12:45:04.217241 scan_bus: bus USB3 port 0 finished in 6 msecs
931 12:45:04.220451 USB3 port 1 scanning...
932 12:45:04.223736 scan_static_bus for USB3 port 1
933 12:45:04.227376 scan_static_bus for USB3 port 1 done
934 12:45:04.230507 scan_bus: bus USB3 port 1 finished in 6 msecs
935 12:45:04.234369 scan_static_bus for USB0 port 0 done
936 12:45:04.240307 scan_bus: bus USB0 port 0 finished in 43 msecs
937 12:45:04.243261 scan_static_bus for PCI: 00:0d.0 done
938 12:45:04.246860 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
939 12:45:04.250005 PCI: 00:14.0 scanning...
940 12:45:04.253516 scan_static_bus for PCI: 00:14.0
941 12:45:04.256600 USB0 port 0 enabled
942 12:45:04.257128 USB0 port 0 scanning...
943 12:45:04.260803 scan_static_bus for USB0 port 0
944 12:45:04.264295 USB2 port 0 disabled
945 12:45:04.267118 USB2 port 1 enabled
946 12:45:04.267644 USB2 port 2 enabled
947 12:45:04.270370 USB2 port 3 disabled
948 12:45:04.273932 USB2 port 4 enabled
949 12:45:04.274475 USB2 port 5 disabled
950 12:45:04.277067 USB2 port 6 disabled
951 12:45:04.280810 USB2 port 7 disabled
952 12:45:04.281350 USB2 port 8 disabled
953 12:45:04.283543 USB2 port 9 disabled
954 12:45:04.284077 USB3 port 0 disabled
955 12:45:04.287148 USB3 port 1 enabled
956 12:45:04.290367 USB3 port 2 disabled
957 12:45:04.290910 USB3 port 3 disabled
958 12:45:04.293810 USB2 port 1 scanning...
959 12:45:04.296994 scan_static_bus for USB2 port 1
960 12:45:04.300464 scan_static_bus for USB2 port 1 done
961 12:45:04.306442 scan_bus: bus USB2 port 1 finished in 6 msecs
962 12:45:04.306884 USB2 port 2 scanning...
963 12:45:04.310462 scan_static_bus for USB2 port 2
964 12:45:04.317101 scan_static_bus for USB2 port 2 done
965 12:45:04.319841 scan_bus: bus USB2 port 2 finished in 6 msecs
966 12:45:04.323945 USB2 port 4 scanning...
967 12:45:04.326479 scan_static_bus for USB2 port 4
968 12:45:04.330074 scan_static_bus for USB2 port 4 done
969 12:45:04.333508 scan_bus: bus USB2 port 4 finished in 6 msecs
970 12:45:04.336927 USB3 port 1 scanning...
971 12:45:04.340213 scan_static_bus for USB3 port 1
972 12:45:04.343138 scan_static_bus for USB3 port 1 done
973 12:45:04.350558 scan_bus: bus USB3 port 1 finished in 6 msecs
974 12:45:04.354185 scan_static_bus for USB0 port 0 done
975 12:45:04.356874 scan_bus: bus USB0 port 0 finished in 93 msecs
976 12:45:04.360081 scan_static_bus for PCI: 00:14.0 done
977 12:45:04.366374 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
978 12:45:04.366925 PCI: 00:14.3 scanning...
979 12:45:04.370005 scan_static_bus for PCI: 00:14.3
980 12:45:04.373836 GENERIC: 0.0 enabled
981 12:45:04.376709 scan_static_bus for PCI: 00:14.3 done
982 12:45:04.383934 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
983 12:45:04.384474 PCI: 00:15.0 scanning...
984 12:45:04.387124 scan_static_bus for PCI: 00:15.0
985 12:45:04.390123 I2C: 00:1a enabled
986 12:45:04.394564 I2C: 00:31 enabled
987 12:45:04.395096 I2C: 00:32 enabled
988 12:45:04.397677 scan_static_bus for PCI: 00:15.0 done
989 12:45:04.404032 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
990 12:45:04.404516 PCI: 00:15.1 scanning...
991 12:45:04.407634 scan_static_bus for PCI: 00:15.1
992 12:45:04.410725 I2C: 00:10 enabled
993 12:45:04.414393 scan_static_bus for PCI: 00:15.1 done
994 12:45:04.421058 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
995 12:45:04.421626 PCI: 00:15.2 scanning...
996 12:45:04.424977 scan_static_bus for PCI: 00:15.2
997 12:45:04.430640 scan_static_bus for PCI: 00:15.2 done
998 12:45:04.434060 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
999 12:45:04.437118 PCI: 00:15.3 scanning...
1000 12:45:04.440423 scan_static_bus for PCI: 00:15.3
1001 12:45:04.443746 scan_static_bus for PCI: 00:15.3 done
1002 12:45:04.447459 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1003 12:45:04.451255 PCI: 00:19.1 scanning...
1004 12:45:04.453887 scan_static_bus for PCI: 00:19.1
1005 12:45:04.457533 I2C: 00:15 enabled
1006 12:45:04.460814 scan_static_bus for PCI: 00:19.1 done
1007 12:45:04.464429 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1008 12:45:04.467413 PCI: 00:1d.0 scanning...
1009 12:45:04.471247 do_pci_scan_bridge for PCI: 00:1d.0
1010 12:45:04.473633 PCI: pci_scan_bus for bus 01
1011 12:45:04.477427 PCI: 01:00.0 [1c5c/174a] enabled
1012 12:45:04.480976 GENERIC: 0.0 enabled
1013 12:45:04.484098 Enabling Common Clock Configuration
1014 12:45:04.487231 L1 Sub-State supported from root port 29
1015 12:45:04.490485 L1 Sub-State Support = 0xf
1016 12:45:04.493822 CommonModeRestoreTime = 0x28
1017 12:45:04.497103 Power On Value = 0x16, Power On Scale = 0x0
1018 12:45:04.501325 ASPM: Enabled L1
1019 12:45:04.503970 PCIe: Max_Payload_Size adjusted to 128
1020 12:45:04.507268 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1021 12:45:04.510490 PCI: 00:1e.2 scanning...
1022 12:45:04.513664 scan_generic_bus for PCI: 00:1e.2
1023 12:45:04.517348 SPI: 00 enabled
1024 12:45:04.523807 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1025 12:45:04.527117 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1026 12:45:04.530303 PCI: 00:1e.3 scanning...
1027 12:45:04.533674 scan_generic_bus for PCI: 00:1e.3
1028 12:45:04.534247 SPI: 00 enabled
1029 12:45:04.540212 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1030 12:45:04.546780 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1031 12:45:04.547322 PCI: 00:1f.0 scanning...
1032 12:45:04.550343 scan_static_bus for PCI: 00:1f.0
1033 12:45:04.553847 PNP: 0c09.0 enabled
1034 12:45:04.556759 PNP: 0c09.0 scanning...
1035 12:45:04.560398 scan_static_bus for PNP: 0c09.0
1036 12:45:04.563736 scan_static_bus for PNP: 0c09.0 done
1037 12:45:04.567258 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1038 12:45:04.573966 scan_static_bus for PCI: 00:1f.0 done
1039 12:45:04.577280 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1040 12:45:04.580209 PCI: 00:1f.2 scanning...
1041 12:45:04.583835 scan_static_bus for PCI: 00:1f.2
1042 12:45:04.584423 GENERIC: 0.0 enabled
1043 12:45:04.587260 GENERIC: 0.0 scanning...
1044 12:45:04.589983 scan_static_bus for GENERIC: 0.0
1045 12:45:04.593617 GENERIC: 0.0 enabled
1046 12:45:04.597110 GENERIC: 1.0 enabled
1047 12:45:04.600015 scan_static_bus for GENERIC: 0.0 done
1048 12:45:04.603447 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1049 12:45:04.606533 scan_static_bus for PCI: 00:1f.2 done
1050 12:45:04.613865 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1051 12:45:04.617403 PCI: 00:1f.3 scanning...
1052 12:45:04.620641 scan_static_bus for PCI: 00:1f.3
1053 12:45:04.623704 scan_static_bus for PCI: 00:1f.3 done
1054 12:45:04.626826 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1055 12:45:04.629948 PCI: 00:1f.5 scanning...
1056 12:45:04.633814 scan_generic_bus for PCI: 00:1f.5
1057 12:45:04.636693 scan_generic_bus for PCI: 00:1f.5 done
1058 12:45:04.643037 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1059 12:45:04.646782 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1060 12:45:04.649772 scan_static_bus for Root Device done
1061 12:45:04.656639 scan_bus: bus Root Device finished in 736 msecs
1062 12:45:04.657146 done
1063 12:45:04.663321 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1064 12:45:04.666453 Chrome EC: UHEPI supported
1065 12:45:04.673737 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1066 12:45:04.676726 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1067 12:45:04.683003 SPI flash protection: WPSW=0 SRP0=0
1068 12:45:04.686669 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1069 12:45:04.692674 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1070 12:45:04.696555 found VGA at PCI: 00:02.0
1071 12:45:04.699492 Setting up VGA for PCI: 00:02.0
1072 12:45:04.703824 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1073 12:45:04.710155 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1074 12:45:04.710746 Allocating resources...
1075 12:45:04.713377 Reading resources...
1076 12:45:04.716559 Root Device read_resources bus 0 link: 0
1077 12:45:04.720012 DOMAIN: 0000 read_resources bus 0 link: 0
1078 12:45:04.727118 PCI: 00:04.0 read_resources bus 1 link: 0
1079 12:45:04.730430 PCI: 00:04.0 read_resources bus 1 link: 0 done
1080 12:45:04.737679 PCI: 00:0d.0 read_resources bus 0 link: 0
1081 12:45:04.740789 USB0 port 0 read_resources bus 0 link: 0
1082 12:45:04.747019 USB0 port 0 read_resources bus 0 link: 0 done
1083 12:45:04.750699 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1084 12:45:04.757047 PCI: 00:14.0 read_resources bus 0 link: 0
1085 12:45:04.760450 USB0 port 0 read_resources bus 0 link: 0
1086 12:45:04.767665 USB0 port 0 read_resources bus 0 link: 0 done
1087 12:45:04.770392 PCI: 00:14.0 read_resources bus 0 link: 0 done
1088 12:45:04.776884 PCI: 00:14.3 read_resources bus 0 link: 0
1089 12:45:04.780417 PCI: 00:14.3 read_resources bus 0 link: 0 done
1090 12:45:04.786803 PCI: 00:15.0 read_resources bus 0 link: 0
1091 12:45:04.790221 PCI: 00:15.0 read_resources bus 0 link: 0 done
1092 12:45:04.797035 PCI: 00:15.1 read_resources bus 0 link: 0
1093 12:45:04.800166 PCI: 00:15.1 read_resources bus 0 link: 0 done
1094 12:45:04.807030 PCI: 00:19.1 read_resources bus 0 link: 0
1095 12:45:04.810503 PCI: 00:19.1 read_resources bus 0 link: 0 done
1096 12:45:04.816532 PCI: 00:1d.0 read_resources bus 1 link: 0
1097 12:45:04.820135 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1098 12:45:04.826699 PCI: 00:1e.2 read_resources bus 2 link: 0
1099 12:45:04.830174 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1100 12:45:04.836900 PCI: 00:1e.3 read_resources bus 3 link: 0
1101 12:45:04.840085 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1102 12:45:04.846502 PCI: 00:1f.0 read_resources bus 0 link: 0
1103 12:45:04.850107 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1104 12:45:04.853394 PCI: 00:1f.2 read_resources bus 0 link: 0
1105 12:45:04.860188 GENERIC: 0.0 read_resources bus 0 link: 0
1106 12:45:04.863439 GENERIC: 0.0 read_resources bus 0 link: 0 done
1107 12:45:04.869977 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1108 12:45:04.876580 DOMAIN: 0000 read_resources bus 0 link: 0 done
1109 12:45:04.880020 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1110 12:45:04.886551 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1111 12:45:04.889620 Root Device read_resources bus 0 link: 0 done
1112 12:45:04.893139 Done reading resources.
1113 12:45:04.896327 Show resources in subtree (Root Device)...After reading.
1114 12:45:04.902822 Root Device child on link 0 DOMAIN: 0000
1115 12:45:04.906488 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1116 12:45:04.916700 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1117 12:45:04.926191 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1118 12:45:04.926783 PCI: 00:00.0
1119 12:45:04.936609 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1120 12:45:04.945893 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1121 12:45:04.956191 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1122 12:45:04.966201 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1123 12:45:04.976325 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1124 12:45:04.982288 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1125 12:45:04.992452 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1126 12:45:05.002487 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1127 12:45:05.012425 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1128 12:45:05.022378 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1129 12:45:05.032691 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1130 12:45:05.039144 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1131 12:45:05.048607 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1132 12:45:05.058896 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1133 12:45:05.068959 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1134 12:45:05.078450 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1135 12:45:05.088625 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1136 12:45:05.095268 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1137 12:45:05.105484 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1138 12:45:05.115401 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1139 12:45:05.118540 PCI: 00:02.0
1140 12:45:05.128477 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1141 12:45:05.138462 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1142 12:45:05.145073 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1143 12:45:05.151709 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1144 12:45:05.161529 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1145 12:45:05.162152 GENERIC: 0.0
1146 12:45:05.164752 PCI: 00:05.0
1147 12:45:05.175433 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1148 12:45:05.178403 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1149 12:45:05.181962 GENERIC: 0.0
1150 12:45:05.182541 PCI: 00:08.0
1151 12:45:05.191334 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1152 12:45:05.194746 PCI: 00:0a.0
1153 12:45:05.198179 PCI: 00:0d.0 child on link 0 USB0 port 0
1154 12:45:05.207905 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1155 12:45:05.212053 USB0 port 0 child on link 0 USB3 port 0
1156 12:45:05.215117 USB3 port 0
1157 12:45:05.218750 USB3 port 1
1158 12:45:05.219335 USB3 port 2
1159 12:45:05.221560 USB3 port 3
1160 12:45:05.225360 PCI: 00:14.0 child on link 0 USB0 port 0
1161 12:45:05.234657 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1162 12:45:05.238353 USB0 port 0 child on link 0 USB2 port 0
1163 12:45:05.241635 USB2 port 0
1164 12:45:05.242132 USB2 port 1
1165 12:45:05.244832 USB2 port 2
1166 12:45:05.245322 USB2 port 3
1167 12:45:05.247897 USB2 port 4
1168 12:45:05.248386 USB2 port 5
1169 12:45:05.251459 USB2 port 6
1170 12:45:05.251976 USB2 port 7
1171 12:45:05.254742 USB2 port 8
1172 12:45:05.258229 USB2 port 9
1173 12:45:05.258812 USB3 port 0
1174 12:45:05.261499 USB3 port 1
1175 12:45:05.262123 USB3 port 2
1176 12:45:05.264755 USB3 port 3
1177 12:45:05.265350 PCI: 00:14.2
1178 12:45:05.274772 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1179 12:45:05.284848 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1180 12:45:05.291539 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1181 12:45:05.298245 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1182 12:45:05.301322 GENERIC: 0.0
1183 12:45:05.304779 PCI: 00:15.0 child on link 0 I2C: 00:1a
1184 12:45:05.315055 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1185 12:45:05.318224 I2C: 00:1a
1186 12:45:05.318808 I2C: 00:31
1187 12:45:05.321470 I2C: 00:32
1188 12:45:05.324555 PCI: 00:15.1 child on link 0 I2C: 00:10
1189 12:45:05.335152 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1190 12:45:05.335770 I2C: 00:10
1191 12:45:05.338276 PCI: 00:15.2
1192 12:45:05.348442 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1193 12:45:05.348946 PCI: 00:15.3
1194 12:45:05.358381 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1195 12:45:05.361105 PCI: 00:16.0
1196 12:45:05.370975 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1197 12:45:05.371553 PCI: 00:19.0
1198 12:45:05.377898 PCI: 00:19.1 child on link 0 I2C: 00:15
1199 12:45:05.388410 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1200 12:45:05.389002 I2C: 00:15
1201 12:45:05.394380 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1202 12:45:05.401315 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1203 12:45:05.411166 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1204 12:45:05.421610 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1205 12:45:05.422199 GENERIC: 0.0
1206 12:45:05.423947 PCI: 01:00.0
1207 12:45:05.434490 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1208 12:45:05.444287 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1209 12:45:05.454028 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1210 12:45:05.454620 PCI: 00:1e.0
1211 12:45:05.464558 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1212 12:45:05.470518 PCI: 00:1e.2 child on link 0 SPI: 00
1213 12:45:05.480480 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1214 12:45:05.480997 SPI: 00
1215 12:45:05.484320 PCI: 00:1e.3 child on link 0 SPI: 00
1216 12:45:05.494150 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1217 12:45:05.497278 SPI: 00
1218 12:45:05.500956 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1219 12:45:05.510626 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1220 12:45:05.511235 PNP: 0c09.0
1221 12:45:05.520755 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1222 12:45:05.524001 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1223 12:45:05.533548 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1224 12:45:05.543798 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1225 12:45:05.546955 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1226 12:45:05.550764 GENERIC: 0.0
1227 12:45:05.551297 GENERIC: 1.0
1228 12:45:05.553801 PCI: 00:1f.3
1229 12:45:05.563575 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1230 12:45:05.573535 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1231 12:45:05.574058 PCI: 00:1f.5
1232 12:45:05.583866 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1233 12:45:05.587451 CPU_CLUSTER: 0 child on link 0 APIC: 00
1234 12:45:05.590167 APIC: 00
1235 12:45:05.590746 APIC: 01
1236 12:45:05.591128 APIC: 03
1237 12:45:05.594409 APIC: 07
1238 12:45:05.594994 APIC: 05
1239 12:45:05.596741 APIC: 04
1240 12:45:05.597321 APIC: 02
1241 12:45:05.597748 APIC: 06
1242 12:45:05.606760 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1243 12:45:05.610224 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1244 12:45:05.616756 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1245 12:45:05.623521 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1246 12:45:05.627146 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1247 12:45:05.633731 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1248 12:45:05.636361 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1249 12:45:05.643691 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1250 12:45:05.650160 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1251 12:45:05.659949 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1252 12:45:05.666297 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1253 12:45:05.672943 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1254 12:45:05.679646 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1255 12:45:05.686296 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1256 12:45:05.692811 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1257 12:45:05.696642 DOMAIN: 0000: Resource ranges:
1258 12:45:05.700149 * Base: 1000, Size: 800, Tag: 100
1259 12:45:05.706519 * Base: 1900, Size: e700, Tag: 100
1260 12:45:05.709562 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1261 12:45:05.716275 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1262 12:45:05.723198 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1263 12:45:05.732888 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1264 12:45:05.739670 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1265 12:45:05.746047 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1266 12:45:05.756114 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1267 12:45:05.762750 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1268 12:45:05.769520 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1269 12:45:05.779691 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1270 12:45:05.786251 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1271 12:45:05.792825 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1272 12:45:05.799199 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1273 12:45:05.809851 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1274 12:45:05.815987 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1275 12:45:05.822478 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1276 12:45:05.833387 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1277 12:45:05.839006 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1278 12:45:05.845834 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1279 12:45:05.855383 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1280 12:45:05.862003 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1281 12:45:05.868828 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1282 12:45:05.878613 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1283 12:45:05.885651 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1284 12:45:05.892466 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1285 12:45:05.895744 DOMAIN: 0000: Resource ranges:
1286 12:45:05.902015 * Base: 7fc00000, Size: 40400000, Tag: 200
1287 12:45:05.905918 * Base: d0000000, Size: 28000000, Tag: 200
1288 12:45:05.908618 * Base: fa000000, Size: 1000000, Tag: 200
1289 12:45:05.915455 * Base: fb001000, Size: 2fff000, Tag: 200
1290 12:45:05.918494 * Base: fe010000, Size: 2e000, Tag: 200
1291 12:45:05.922363 * Base: fe03f000, Size: d41000, Tag: 200
1292 12:45:05.925836 * Base: fed88000, Size: 8000, Tag: 200
1293 12:45:05.929200 * Base: fed93000, Size: d000, Tag: 200
1294 12:45:05.935192 * Base: feda2000, Size: 1e000, Tag: 200
1295 12:45:05.938776 * Base: fede0000, Size: 1220000, Tag: 200
1296 12:45:05.945277 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1297 12:45:05.951756 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1298 12:45:05.958728 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1299 12:45:05.965313 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1300 12:45:05.972288 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1301 12:45:05.978476 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1302 12:45:05.984823 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1303 12:45:05.992031 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1304 12:45:05.998261 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1305 12:45:06.005267 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1306 12:45:06.011510 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1307 12:45:06.018444 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1308 12:45:06.025195 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1309 12:45:06.032175 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1310 12:45:06.039196 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1311 12:45:06.044579 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1312 12:45:06.051253 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1313 12:45:06.058108 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1314 12:45:06.064620 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1315 12:45:06.070983 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1316 12:45:06.077609 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1317 12:45:06.084571 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1318 12:45:06.091108 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1319 12:45:06.097760 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1320 12:45:06.104565 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1321 12:45:06.108358 PCI: 00:1d.0: Resource ranges:
1322 12:45:06.111221 * Base: 7fc00000, Size: 100000, Tag: 200
1323 12:45:06.118197 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1324 12:45:06.124525 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1325 12:45:06.130896 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1326 12:45:06.141382 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1327 12:45:06.147801 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1328 12:45:06.150871 Root Device assign_resources, bus 0 link: 0
1329 12:45:06.157869 DOMAIN: 0000 assign_resources, bus 0 link: 0
1330 12:45:06.164572 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1331 12:45:06.174702 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1332 12:45:06.181121 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1333 12:45:06.190693 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1334 12:45:06.194284 PCI: 00:04.0 assign_resources, bus 1 link: 0
1335 12:45:06.200401 PCI: 00:04.0 assign_resources, bus 1 link: 0
1336 12:45:06.207546 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1337 12:45:06.216870 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1338 12:45:06.223870 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1339 12:45:06.227054 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1340 12:45:06.233718 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1341 12:45:06.240723 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1342 12:45:06.246972 PCI: 00:14.0 assign_resources, bus 0 link: 0
1343 12:45:06.250120 PCI: 00:14.0 assign_resources, bus 0 link: 0
1344 12:45:06.260679 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1345 12:45:06.266800 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1346 12:45:06.274178 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1347 12:45:06.280322 PCI: 00:14.3 assign_resources, bus 0 link: 0
1348 12:45:06.283451 PCI: 00:14.3 assign_resources, bus 0 link: 0
1349 12:45:06.293333 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1350 12:45:06.296686 PCI: 00:15.0 assign_resources, bus 0 link: 0
1351 12:45:06.303452 PCI: 00:15.0 assign_resources, bus 0 link: 0
1352 12:45:06.310437 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1353 12:45:06.313831 PCI: 00:15.1 assign_resources, bus 0 link: 0
1354 12:45:06.319942 PCI: 00:15.1 assign_resources, bus 0 link: 0
1355 12:45:06.326728 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1356 12:45:06.336867 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1357 12:45:06.343507 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1358 12:45:06.352803 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1359 12:45:06.356038 PCI: 00:19.1 assign_resources, bus 0 link: 0
1360 12:45:06.363657 PCI: 00:19.1 assign_resources, bus 0 link: 0
1361 12:45:06.369459 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1362 12:45:06.379866 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1363 12:45:06.389325 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1364 12:45:06.392832 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1365 12:45:06.402539 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1366 12:45:06.409223 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1367 12:45:06.415663 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1368 12:45:06.422701 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1369 12:45:06.429084 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1370 12:45:06.436043 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1371 12:45:06.439484 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1372 12:45:06.448976 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1373 12:45:06.452321 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1374 12:45:06.455418 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1375 12:45:06.462483 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1376 12:45:06.465943 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1377 12:45:06.472152 LPC: Trying to open IO window from 800 size 1ff
1378 12:45:06.479121 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1379 12:45:06.488981 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1380 12:45:06.495906 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1381 12:45:06.502178 DOMAIN: 0000 assign_resources, bus 0 link: 0
1382 12:45:06.505370 Root Device assign_resources, bus 0 link: 0
1383 12:45:06.508776 Done setting resources.
1384 12:45:06.515434 Show resources in subtree (Root Device)...After assigning values.
1385 12:45:06.518927 Root Device child on link 0 DOMAIN: 0000
1386 12:45:06.522107 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1387 12:45:06.531966 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1388 12:45:06.542087 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1389 12:45:06.545357 PCI: 00:00.0
1390 12:45:06.551621 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1391 12:45:06.562539 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1392 12:45:06.571719 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1393 12:45:06.581525 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1394 12:45:06.591631 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1395 12:45:06.602041 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1396 12:45:06.608442 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1397 12:45:06.618322 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1398 12:45:06.628666 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1399 12:45:06.638131 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1400 12:45:06.648301 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1401 12:45:06.658464 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1402 12:45:06.664996 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1403 12:45:06.674496 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1404 12:45:06.684203 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1405 12:45:06.694385 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1406 12:45:06.704597 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1407 12:45:06.714484 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1408 12:45:06.721025 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1409 12:45:06.731349 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1410 12:45:06.734421 PCI: 00:02.0
1411 12:45:06.744143 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1412 12:45:06.754142 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1413 12:45:06.765038 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1414 12:45:06.767546 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1415 12:45:06.780743 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1416 12:45:06.781335 GENERIC: 0.0
1417 12:45:06.783813 PCI: 00:05.0
1418 12:45:06.794170 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1419 12:45:06.797170 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1420 12:45:06.800666 GENERIC: 0.0
1421 12:45:06.801258 PCI: 00:08.0
1422 12:45:06.810658 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1423 12:45:06.813952 PCI: 00:0a.0
1424 12:45:06.817009 PCI: 00:0d.0 child on link 0 USB0 port 0
1425 12:45:06.827178 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1426 12:45:06.834011 USB0 port 0 child on link 0 USB3 port 0
1427 12:45:06.834584 USB3 port 0
1428 12:45:06.837076 USB3 port 1
1429 12:45:06.837693 USB3 port 2
1430 12:45:06.840433 USB3 port 3
1431 12:45:06.843824 PCI: 00:14.0 child on link 0 USB0 port 0
1432 12:45:06.853686 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1433 12:45:06.860539 USB0 port 0 child on link 0 USB2 port 0
1434 12:45:06.861026 USB2 port 0
1435 12:45:06.863666 USB2 port 1
1436 12:45:06.864254 USB2 port 2
1437 12:45:06.866706 USB2 port 3
1438 12:45:06.867187 USB2 port 4
1439 12:45:06.870093 USB2 port 5
1440 12:45:06.870573 USB2 port 6
1441 12:45:06.873728 USB2 port 7
1442 12:45:06.874208 USB2 port 8
1443 12:45:06.877486 USB2 port 9
1444 12:45:06.878099 USB3 port 0
1445 12:45:06.880069 USB3 port 1
1446 12:45:06.880548 USB3 port 2
1447 12:45:06.883544 USB3 port 3
1448 12:45:06.884119 PCI: 00:14.2
1449 12:45:06.896882 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1450 12:45:06.906944 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1451 12:45:06.910347 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1452 12:45:06.920255 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1453 12:45:06.924048 GENERIC: 0.0
1454 12:45:06.927113 PCI: 00:15.0 child on link 0 I2C: 00:1a
1455 12:45:06.937097 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1456 12:45:06.940326 I2C: 00:1a
1457 12:45:06.940912 I2C: 00:31
1458 12:45:06.943477 I2C: 00:32
1459 12:45:06.947272 PCI: 00:15.1 child on link 0 I2C: 00:10
1460 12:45:06.957084 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1461 12:45:06.957722 I2C: 00:10
1462 12:45:06.960631 PCI: 00:15.2
1463 12:45:06.970970 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1464 12:45:06.971559 PCI: 00:15.3
1465 12:45:06.983709 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1466 12:45:06.984313 PCI: 00:16.0
1467 12:45:06.993382 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1468 12:45:06.996595 PCI: 00:19.0
1469 12:45:07.000118 PCI: 00:19.1 child on link 0 I2C: 00:15
1470 12:45:07.009770 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1471 12:45:07.013227 I2C: 00:15
1472 12:45:07.016663 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1473 12:45:07.026503 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1474 12:45:07.036529 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1475 12:45:07.046866 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1476 12:45:07.049837 GENERIC: 0.0
1477 12:45:07.050422 PCI: 01:00.0
1478 12:45:07.063360 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1479 12:45:07.073428 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1480 12:45:07.083163 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1481 12:45:07.083760 PCI: 00:1e.0
1482 12:45:07.096762 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1483 12:45:07.099404 PCI: 00:1e.2 child on link 0 SPI: 00
1484 12:45:07.109384 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1485 12:45:07.109997 SPI: 00
1486 12:45:07.116290 PCI: 00:1e.3 child on link 0 SPI: 00
1487 12:45:07.126469 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1488 12:45:07.127062 SPI: 00
1489 12:45:07.129669 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1490 12:45:07.139825 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1491 12:45:07.143099 PNP: 0c09.0
1492 12:45:07.149495 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1493 12:45:07.155917 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1494 12:45:07.162589 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1495 12:45:07.172567 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1496 12:45:07.179187 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1497 12:45:07.179780 GENERIC: 0.0
1498 12:45:07.182657 GENERIC: 1.0
1499 12:45:07.183147 PCI: 00:1f.3
1500 12:45:07.192657 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1501 12:45:07.202174 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1502 12:45:07.206456 PCI: 00:1f.5
1503 12:45:07.215615 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1504 12:45:07.218909 CPU_CLUSTER: 0 child on link 0 APIC: 00
1505 12:45:07.222143 APIC: 00
1506 12:45:07.222625 APIC: 01
1507 12:45:07.226480 APIC: 03
1508 12:45:07.227061 APIC: 07
1509 12:45:07.227445 APIC: 05
1510 12:45:07.229464 APIC: 04
1511 12:45:07.230086 APIC: 02
1512 12:45:07.230474 APIC: 06
1513 12:45:07.233216 Done allocating resources.
1514 12:45:07.238983 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1515 12:45:07.245893 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1516 12:45:07.249082 Configure GPIOs for I2S audio on UP4.
1517 12:45:07.255379 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1518 12:45:07.258737 Enabling resources...
1519 12:45:07.262407 PCI: 00:00.0 subsystem <- 8086/9a12
1520 12:45:07.265744 PCI: 00:00.0 cmd <- 06
1521 12:45:07.269319 PCI: 00:02.0 subsystem <- 8086/9a40
1522 12:45:07.272399 PCI: 00:02.0 cmd <- 03
1523 12:45:07.275520 PCI: 00:04.0 subsystem <- 8086/9a03
1524 12:45:07.278695 PCI: 00:04.0 cmd <- 02
1525 12:45:07.282273 PCI: 00:05.0 subsystem <- 8086/9a19
1526 12:45:07.282867 PCI: 00:05.0 cmd <- 02
1527 12:45:07.288635 PCI: 00:08.0 subsystem <- 8086/9a11
1528 12:45:07.289261 PCI: 00:08.0 cmd <- 06
1529 12:45:07.292014 PCI: 00:0d.0 subsystem <- 8086/9a13
1530 12:45:07.295207 PCI: 00:0d.0 cmd <- 02
1531 12:45:07.298784 PCI: 00:14.0 subsystem <- 8086/a0ed
1532 12:45:07.301779 PCI: 00:14.0 cmd <- 02
1533 12:45:07.305754 PCI: 00:14.2 subsystem <- 8086/a0ef
1534 12:45:07.308679 PCI: 00:14.2 cmd <- 02
1535 12:45:07.311721 PCI: 00:14.3 subsystem <- 8086/a0f0
1536 12:45:07.315682 PCI: 00:14.3 cmd <- 02
1537 12:45:07.318573 PCI: 00:15.0 subsystem <- 8086/a0e8
1538 12:45:07.321947 PCI: 00:15.0 cmd <- 02
1539 12:45:07.325208 PCI: 00:15.1 subsystem <- 8086/a0e9
1540 12:45:07.328956 PCI: 00:15.1 cmd <- 02
1541 12:45:07.332114 PCI: 00:15.2 subsystem <- 8086/a0ea
1542 12:45:07.332700 PCI: 00:15.2 cmd <- 02
1543 12:45:07.338401 PCI: 00:15.3 subsystem <- 8086/a0eb
1544 12:45:07.338987 PCI: 00:15.3 cmd <- 02
1545 12:45:07.341930 PCI: 00:16.0 subsystem <- 8086/a0e0
1546 12:45:07.344919 PCI: 00:16.0 cmd <- 02
1547 12:45:07.348615 PCI: 00:19.1 subsystem <- 8086/a0c6
1548 12:45:07.351493 PCI: 00:19.1 cmd <- 02
1549 12:45:07.354618 PCI: 00:1d.0 bridge ctrl <- 0013
1550 12:45:07.358370 PCI: 00:1d.0 subsystem <- 8086/a0b0
1551 12:45:07.361925 PCI: 00:1d.0 cmd <- 06
1552 12:45:07.364830 PCI: 00:1e.0 subsystem <- 8086/a0a8
1553 12:45:07.368147 PCI: 00:1e.0 cmd <- 06
1554 12:45:07.372079 PCI: 00:1e.2 subsystem <- 8086/a0aa
1555 12:45:07.374507 PCI: 00:1e.2 cmd <- 06
1556 12:45:07.378035 PCI: 00:1e.3 subsystem <- 8086/a0ab
1557 12:45:07.381483 PCI: 00:1e.3 cmd <- 02
1558 12:45:07.384719 PCI: 00:1f.0 subsystem <- 8086/a087
1559 12:45:07.385309 PCI: 00:1f.0 cmd <- 407
1560 12:45:07.391616 PCI: 00:1f.3 subsystem <- 8086/a0c8
1561 12:45:07.392241 PCI: 00:1f.3 cmd <- 02
1562 12:45:07.394841 PCI: 00:1f.5 subsystem <- 8086/a0a4
1563 12:45:07.398045 PCI: 00:1f.5 cmd <- 406
1564 12:45:07.402908 PCI: 01:00.0 cmd <- 02
1565 12:45:07.407767 done.
1566 12:45:07.410891 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1567 12:45:07.414013 Initializing devices...
1568 12:45:07.417515 Root Device init
1569 12:45:07.420542 Chrome EC: Set SMI mask to 0x0000000000000000
1570 12:45:07.428535 Chrome EC: clear events_b mask to 0x0000000000000000
1571 12:45:07.435651 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1572 12:45:07.442189 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1573 12:45:07.447975 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1574 12:45:07.451314 Chrome EC: Set WAKE mask to 0x0000000000000000
1575 12:45:07.459667 fw_config match found: DB_USB=USB3_ACTIVE
1576 12:45:07.463337 Configure Right Type-C port orientation for retimer
1577 12:45:07.465877 Root Device init finished in 47 msecs
1578 12:45:07.470433 PCI: 00:00.0 init
1579 12:45:07.473559 CPU TDP = 9 Watts
1580 12:45:07.474195 CPU PL1 = 9 Watts
1581 12:45:07.476698 CPU PL2 = 40 Watts
1582 12:45:07.480332 CPU PL4 = 83 Watts
1583 12:45:07.483545 PCI: 00:00.0 init finished in 8 msecs
1584 12:45:07.484140 PCI: 00:02.0 init
1585 12:45:07.486911 GMA: Found VBT in CBFS
1586 12:45:07.489982 GMA: Found valid VBT in CBFS
1587 12:45:07.497479 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1588 12:45:07.503517 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1589 12:45:07.506690 PCI: 00:02.0 init finished in 18 msecs
1590 12:45:07.510120 PCI: 00:05.0 init
1591 12:45:07.513610 PCI: 00:05.0 init finished in 0 msecs
1592 12:45:07.516554 PCI: 00:08.0 init
1593 12:45:07.519835 PCI: 00:08.0 init finished in 0 msecs
1594 12:45:07.523717 PCI: 00:14.0 init
1595 12:45:07.527487 PCI: 00:14.0 init finished in 0 msecs
1596 12:45:07.530158 PCI: 00:14.2 init
1597 12:45:07.533645 PCI: 00:14.2 init finished in 0 msecs
1598 12:45:07.537374 PCI: 00:15.0 init
1599 12:45:07.537993 I2C bus 0 version 0x3230302a
1600 12:45:07.543596 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1601 12:45:07.546639 PCI: 00:15.0 init finished in 6 msecs
1602 12:45:07.547152 PCI: 00:15.1 init
1603 12:45:07.549968 I2C bus 1 version 0x3230302a
1604 12:45:07.553220 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1605 12:45:07.560067 PCI: 00:15.1 init finished in 6 msecs
1606 12:45:07.560696 PCI: 00:15.2 init
1607 12:45:07.563734 I2C bus 2 version 0x3230302a
1608 12:45:07.566237 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1609 12:45:07.570078 PCI: 00:15.2 init finished in 6 msecs
1610 12:45:07.572937 PCI: 00:15.3 init
1611 12:45:07.576059 I2C bus 3 version 0x3230302a
1612 12:45:07.579632 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1613 12:45:07.583247 PCI: 00:15.3 init finished in 6 msecs
1614 12:45:07.586392 PCI: 00:16.0 init
1615 12:45:07.589449 PCI: 00:16.0 init finished in 0 msecs
1616 12:45:07.592815 PCI: 00:19.1 init
1617 12:45:07.596399 I2C bus 5 version 0x3230302a
1618 12:45:07.600040 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1619 12:45:07.602656 PCI: 00:19.1 init finished in 6 msecs
1620 12:45:07.606152 PCI: 00:1d.0 init
1621 12:45:07.606633 Initializing PCH PCIe bridge.
1622 12:45:07.612970 PCI: 00:1d.0 init finished in 3 msecs
1623 12:45:07.616099 PCI: 00:1f.0 init
1624 12:45:07.619364 IOAPIC: Initializing IOAPIC at 0xfec00000
1625 12:45:07.622686 IOAPIC: Bootstrap Processor Local APIC = 0x00
1626 12:45:07.626119 IOAPIC: ID = 0x02
1627 12:45:07.629284 IOAPIC: Dumping registers
1628 12:45:07.629903 reg 0x0000: 0x02000000
1629 12:45:07.632906 reg 0x0001: 0x00770020
1630 12:45:07.636265 reg 0x0002: 0x00000000
1631 12:45:07.639312 PCI: 00:1f.0 init finished in 21 msecs
1632 12:45:07.642997 PCI: 00:1f.2 init
1633 12:45:07.646506 Disabling ACPI via APMC.
1634 12:45:07.647095 APMC done.
1635 12:45:07.649118 PCI: 00:1f.2 init finished in 5 msecs
1636 12:45:07.663444 PCI: 01:00.0 init
1637 12:45:07.666737 PCI: 01:00.0 init finished in 0 msecs
1638 12:45:07.670173 PNP: 0c09.0 init
1639 12:45:07.672940 Google Chrome EC uptime: 8.434 seconds
1640 12:45:07.679394 Google Chrome AP resets since EC boot: 1
1641 12:45:07.682733 Google Chrome most recent AP reset causes:
1642 12:45:07.686239 0.349: 32775 shutdown: entering G3
1643 12:45:07.692925 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1644 12:45:07.695705 PNP: 0c09.0 init finished in 22 msecs
1645 12:45:07.701638 Devices initialized
1646 12:45:07.705272 Show all devs... After init.
1647 12:45:07.708189 Root Device: enabled 1
1648 12:45:07.708734 DOMAIN: 0000: enabled 1
1649 12:45:07.711451 CPU_CLUSTER: 0: enabled 1
1650 12:45:07.714762 PCI: 00:00.0: enabled 1
1651 12:45:07.718307 PCI: 00:02.0: enabled 1
1652 12:45:07.718901 PCI: 00:04.0: enabled 1
1653 12:45:07.721873 PCI: 00:05.0: enabled 1
1654 12:45:07.724904 PCI: 00:06.0: enabled 0
1655 12:45:07.728227 PCI: 00:07.0: enabled 0
1656 12:45:07.728818 PCI: 00:07.1: enabled 0
1657 12:45:07.731284 PCI: 00:07.2: enabled 0
1658 12:45:07.734910 PCI: 00:07.3: enabled 0
1659 12:45:07.738369 PCI: 00:08.0: enabled 1
1660 12:45:07.738956 PCI: 00:09.0: enabled 0
1661 12:45:07.741645 PCI: 00:0a.0: enabled 0
1662 12:45:07.745182 PCI: 00:0d.0: enabled 1
1663 12:45:07.748314 PCI: 00:0d.1: enabled 0
1664 12:45:07.748899 PCI: 00:0d.2: enabled 0
1665 12:45:07.751424 PCI: 00:0d.3: enabled 0
1666 12:45:07.754833 PCI: 00:0e.0: enabled 0
1667 12:45:07.755418 PCI: 00:10.2: enabled 1
1668 12:45:07.758536 PCI: 00:10.6: enabled 0
1669 12:45:07.761184 PCI: 00:10.7: enabled 0
1670 12:45:07.764899 PCI: 00:12.0: enabled 0
1671 12:45:07.765518 PCI: 00:12.6: enabled 0
1672 12:45:07.768175 PCI: 00:13.0: enabled 0
1673 12:45:07.771791 PCI: 00:14.0: enabled 1
1674 12:45:07.774924 PCI: 00:14.1: enabled 0
1675 12:45:07.775514 PCI: 00:14.2: enabled 1
1676 12:45:07.777763 PCI: 00:14.3: enabled 1
1677 12:45:07.781656 PCI: 00:15.0: enabled 1
1678 12:45:07.784857 PCI: 00:15.1: enabled 1
1679 12:45:07.785441 PCI: 00:15.2: enabled 1
1680 12:45:07.787676 PCI: 00:15.3: enabled 1
1681 12:45:07.791018 PCI: 00:16.0: enabled 1
1682 12:45:07.791506 PCI: 00:16.1: enabled 0
1683 12:45:07.794791 PCI: 00:16.2: enabled 0
1684 12:45:07.798087 PCI: 00:16.3: enabled 0
1685 12:45:07.801179 PCI: 00:16.4: enabled 0
1686 12:45:07.801700 PCI: 00:16.5: enabled 0
1687 12:45:07.805402 PCI: 00:17.0: enabled 0
1688 12:45:07.808086 PCI: 00:19.0: enabled 0
1689 12:45:07.811300 PCI: 00:19.1: enabled 1
1690 12:45:07.811895 PCI: 00:19.2: enabled 0
1691 12:45:07.814601 PCI: 00:1c.0: enabled 1
1692 12:45:07.818018 PCI: 00:1c.1: enabled 0
1693 12:45:07.821330 PCI: 00:1c.2: enabled 0
1694 12:45:07.821887 PCI: 00:1c.3: enabled 0
1695 12:45:07.824227 PCI: 00:1c.4: enabled 0
1696 12:45:07.828453 PCI: 00:1c.5: enabled 0
1697 12:45:07.830993 PCI: 00:1c.6: enabled 1
1698 12:45:07.831481 PCI: 00:1c.7: enabled 0
1699 12:45:07.834828 PCI: 00:1d.0: enabled 1
1700 12:45:07.837796 PCI: 00:1d.1: enabled 0
1701 12:45:07.838406 PCI: 00:1d.2: enabled 1
1702 12:45:07.841725 PCI: 00:1d.3: enabled 0
1703 12:45:07.844850 PCI: 00:1e.0: enabled 1
1704 12:45:07.847408 PCI: 00:1e.1: enabled 0
1705 12:45:07.847893 PCI: 00:1e.2: enabled 1
1706 12:45:07.851296 PCI: 00:1e.3: enabled 1
1707 12:45:07.854467 PCI: 00:1f.0: enabled 1
1708 12:45:07.857787 PCI: 00:1f.1: enabled 0
1709 12:45:07.858390 PCI: 00:1f.2: enabled 1
1710 12:45:07.861212 PCI: 00:1f.3: enabled 1
1711 12:45:07.864443 PCI: 00:1f.4: enabled 0
1712 12:45:07.867825 PCI: 00:1f.5: enabled 1
1713 12:45:07.868406 PCI: 00:1f.6: enabled 0
1714 12:45:07.871420 PCI: 00:1f.7: enabled 0
1715 12:45:07.874360 APIC: 00: enabled 1
1716 12:45:07.874850 GENERIC: 0.0: enabled 1
1717 12:45:07.877931 GENERIC: 0.0: enabled 1
1718 12:45:07.880913 GENERIC: 1.0: enabled 1
1719 12:45:07.884257 GENERIC: 0.0: enabled 1
1720 12:45:07.884843 GENERIC: 1.0: enabled 1
1721 12:45:07.887910 USB0 port 0: enabled 1
1722 12:45:07.891334 GENERIC: 0.0: enabled 1
1723 12:45:07.891820 USB0 port 0: enabled 1
1724 12:45:07.894071 GENERIC: 0.0: enabled 1
1725 12:45:07.897537 I2C: 00:1a: enabled 1
1726 12:45:07.900642 I2C: 00:31: enabled 1
1727 12:45:07.901129 I2C: 00:32: enabled 1
1728 12:45:07.904106 I2C: 00:10: enabled 1
1729 12:45:07.907389 I2C: 00:15: enabled 1
1730 12:45:07.907874 GENERIC: 0.0: enabled 0
1731 12:45:07.911411 GENERIC: 1.0: enabled 0
1732 12:45:07.914264 GENERIC: 0.0: enabled 1
1733 12:45:07.914751 SPI: 00: enabled 1
1734 12:45:07.917346 SPI: 00: enabled 1
1735 12:45:07.920836 PNP: 0c09.0: enabled 1
1736 12:45:07.921261 GENERIC: 0.0: enabled 1
1737 12:45:07.924468 USB3 port 0: enabled 1
1738 12:45:07.927584 USB3 port 1: enabled 1
1739 12:45:07.927923 USB3 port 2: enabled 0
1740 12:45:07.930494 USB3 port 3: enabled 0
1741 12:45:07.934174 USB2 port 0: enabled 0
1742 12:45:07.937254 USB2 port 1: enabled 1
1743 12:45:07.937717 USB2 port 2: enabled 1
1744 12:45:07.940305 USB2 port 3: enabled 0
1745 12:45:07.944433 USB2 port 4: enabled 1
1746 12:45:07.944873 USB2 port 5: enabled 0
1747 12:45:07.947476 USB2 port 6: enabled 0
1748 12:45:07.950814 USB2 port 7: enabled 0
1749 12:45:07.954624 USB2 port 8: enabled 0
1750 12:45:07.955059 USB2 port 9: enabled 0
1751 12:45:07.957460 USB3 port 0: enabled 0
1752 12:45:07.960454 USB3 port 1: enabled 1
1753 12:45:07.960805 USB3 port 2: enabled 0
1754 12:45:07.964214 USB3 port 3: enabled 0
1755 12:45:07.967856 GENERIC: 0.0: enabled 1
1756 12:45:07.970329 GENERIC: 1.0: enabled 1
1757 12:45:07.970682 APIC: 01: enabled 1
1758 12:45:07.973907 APIC: 03: enabled 1
1759 12:45:07.974346 APIC: 07: enabled 1
1760 12:45:07.977356 APIC: 05: enabled 1
1761 12:45:07.980662 APIC: 04: enabled 1
1762 12:45:07.981097 APIC: 02: enabled 1
1763 12:45:07.984140 APIC: 06: enabled 1
1764 12:45:07.987121 PCI: 01:00.0: enabled 1
1765 12:45:07.990971 BS: BS_DEV_INIT run times (exec / console): 34 / 540 ms
1766 12:45:07.997107 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1767 12:45:08.000934 ELOG: NV offset 0xf30000 size 0x1000
1768 12:45:08.007064 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1769 12:45:08.013734 ELOG: Event(17) added with size 13 at 2022-07-14 12:39:56 UTC
1770 12:45:08.020635 ELOG: Event(92) added with size 9 at 2022-07-14 12:39:56 UTC
1771 12:45:08.026849 ELOG: Event(93) added with size 9 at 2022-07-14 12:39:56 UTC
1772 12:45:08.033726 ELOG: Event(9E) added with size 10 at 2022-07-14 12:39:56 UTC
1773 12:45:08.040182 ELOG: Event(9F) added with size 14 at 2022-07-14 12:39:56 UTC
1774 12:45:08.047418 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1775 12:45:08.050375 ELOG: Event(A1) added with size 10 at 2022-07-14 12:39:56 UTC
1776 12:45:08.059690 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1777 12:45:08.067175 ELOG: Event(A0) added with size 9 at 2022-07-14 12:39:56 UTC
1778 12:45:08.070130 elog_add_boot_reason: Logged dev mode boot
1779 12:45:08.077461 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
1780 12:45:08.078079 Finalize devices...
1781 12:45:08.080244 Devices finalized
1782 12:45:08.086733 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1783 12:45:08.090254 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1784 12:45:08.096554 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1785 12:45:08.100069 ME: HFSTS1 : 0x80030055
1786 12:45:08.106211 ME: HFSTS2 : 0x30280116
1787 12:45:08.109610 ME: HFSTS3 : 0x00000050
1788 12:45:08.113255 ME: HFSTS4 : 0x00004000
1789 12:45:08.120382 ME: HFSTS5 : 0x00000000
1790 12:45:08.123252 ME: HFSTS6 : 0x00400006
1791 12:45:08.126683 ME: Manufacturing Mode : YES
1792 12:45:08.129954 ME: SPI Protection Mode Enabled : NO
1793 12:45:08.133650 ME: FW Partition Table : OK
1794 12:45:08.140056 ME: Bringup Loader Failure : NO
1795 12:45:08.143141 ME: Firmware Init Complete : NO
1796 12:45:08.146143 ME: Boot Options Present : NO
1797 12:45:08.149872 ME: Update In Progress : NO
1798 12:45:08.153194 ME: D0i3 Support : YES
1799 12:45:08.156318 ME: Low Power State Enabled : NO
1800 12:45:08.159291 ME: CPU Replaced : YES
1801 12:45:08.163160 ME: CPU Replacement Valid : YES
1802 12:45:08.166491 ME: Current Working State : 5
1803 12:45:08.173272 ME: Current Operation State : 1
1804 12:45:08.176111 ME: Current Operation Mode : 3
1805 12:45:08.179618 ME: Error Code : 0
1806 12:45:08.182683 ME: Enhanced Debug Mode : NO
1807 12:45:08.186273 ME: CPU Debug Disabled : YES
1808 12:45:08.189559 ME: TXT Support : NO
1809 12:45:08.196230 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1810 12:45:08.202717 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1811 12:45:08.206005 CBFS: 'fallback/slic' not found.
1812 12:45:08.209167 ACPI: Writing ACPI tables at 76b01000.
1813 12:45:08.212544 ACPI: * FACS
1814 12:45:08.213135 ACPI: * DSDT
1815 12:45:08.219663 Ramoops buffer: 0x100000@0x76a00000.
1816 12:45:08.222630 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1817 12:45:08.225954 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1818 12:45:08.230175 Google Chrome EC: version:
1819 12:45:08.233157 ro: voema_v2.0.7540-147f8d37d1
1820 12:45:08.236719 rw: voema_v2.0.7540-147f8d37d1
1821 12:45:08.240199 running image: 2
1822 12:45:08.246546 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1823 12:45:08.249736 ACPI: * FADT
1824 12:45:08.250231 SCI is IRQ9
1825 12:45:08.253272 ACPI: added table 1/32, length now 40
1826 12:45:08.257110 ACPI: * SSDT
1827 12:45:08.259635 Found 1 CPU(s) with 8 core(s) each.
1828 12:45:08.263248 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1829 12:45:08.270142 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1830 12:45:08.273690 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1831 12:45:08.276914 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1832 12:45:08.282905 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1833 12:45:08.289801 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1834 12:45:08.293075 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1835 12:45:08.299769 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1836 12:45:08.306226 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1837 12:45:08.309731 \_SB.PCI0.RP09: Added StorageD3Enable property
1838 12:45:08.312709 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1839 12:45:08.319508 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1840 12:45:08.326182 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1841 12:45:08.329603 PS2K: Passing 80 keymaps to kernel
1842 12:45:08.336647 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1843 12:45:08.342805 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1844 12:45:08.348990 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1845 12:45:08.356108 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1846 12:45:08.362495 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1847 12:45:08.369021 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1848 12:45:08.375705 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1849 12:45:08.382409 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1850 12:45:08.386187 ACPI: added table 2/32, length now 44
1851 12:45:08.386812 ACPI: * MCFG
1852 12:45:08.389041 ACPI: added table 3/32, length now 48
1853 12:45:08.392236 ACPI: * TPM2
1854 12:45:08.396462 TPM2 log created at 0x769f0000
1855 12:45:08.398903 ACPI: added table 4/32, length now 52
1856 12:45:08.399505 ACPI: * MADT
1857 12:45:08.402296 SCI is IRQ9
1858 12:45:08.406208 ACPI: added table 5/32, length now 56
1859 12:45:08.409147 current = 76b09850
1860 12:45:08.409760 ACPI: * DMAR
1861 12:45:08.412367 ACPI: added table 6/32, length now 60
1862 12:45:08.415836 ACPI: added table 7/32, length now 64
1863 12:45:08.418812 ACPI: * HPET
1864 12:45:08.422504 ACPI: added table 8/32, length now 68
1865 12:45:08.423102 ACPI: done.
1866 12:45:08.425714 ACPI tables: 35216 bytes.
1867 12:45:08.429281 smbios_write_tables: 769ef000
1868 12:45:08.432401 EC returned error result code 3
1869 12:45:08.435533 Couldn't obtain OEM name from CBI
1870 12:45:08.438739 Create SMBIOS type 16
1871 12:45:08.441935 Create SMBIOS type 17
1872 12:45:08.445819 GENERIC: 0.0 (WIFI Device)
1873 12:45:08.446406 SMBIOS tables: 1750 bytes.
1874 12:45:08.452142 Writing table forward entry at 0x00000500
1875 12:45:08.455270 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1876 12:45:08.461704 Writing coreboot table at 0x76b25000
1877 12:45:08.465553 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1878 12:45:08.471894 1. 0000000000001000-000000000009ffff: RAM
1879 12:45:08.474945 2. 00000000000a0000-00000000000fffff: RESERVED
1880 12:45:08.478326 3. 0000000000100000-00000000769eefff: RAM
1881 12:45:08.485998 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1882 12:45:08.492028 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1883 12:45:08.494848 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1884 12:45:08.501776 7. 0000000077000000-000000007fbfffff: RESERVED
1885 12:45:08.504814 8. 00000000c0000000-00000000cfffffff: RESERVED
1886 12:45:08.511088 9. 00000000f8000000-00000000f9ffffff: RESERVED
1887 12:45:08.514505 10. 00000000fb000000-00000000fb000fff: RESERVED
1888 12:45:08.521323 11. 00000000fe000000-00000000fe00ffff: RESERVED
1889 12:45:08.524858 12. 00000000fed80000-00000000fed87fff: RESERVED
1890 12:45:08.531304 13. 00000000fed90000-00000000fed92fff: RESERVED
1891 12:45:08.534973 14. 00000000feda0000-00000000feda1fff: RESERVED
1892 12:45:08.538019 15. 00000000fedc0000-00000000feddffff: RESERVED
1893 12:45:08.544585 16. 0000000100000000-00000002803fffff: RAM
1894 12:45:08.547705 Passing 4 GPIOs to payload:
1895 12:45:08.551317 NAME | PORT | POLARITY | VALUE
1896 12:45:08.558099 lid | undefined | high | high
1897 12:45:08.561033 power | undefined | high | low
1898 12:45:08.568278 oprom | undefined | high | low
1899 12:45:08.574307 EC in RW | 0x000000e5 | high | high
1900 12:45:08.581106 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 9270
1901 12:45:08.581750 coreboot table: 1576 bytes.
1902 12:45:08.584752 IMD ROOT 0. 0x76fff000 0x00001000
1903 12:45:08.591286 IMD SMALL 1. 0x76ffe000 0x00001000
1904 12:45:08.594307 FSP MEMORY 2. 0x76c4e000 0x003b0000
1905 12:45:08.598004 VPD 3. 0x76c4d000 0x00000367
1906 12:45:08.601558 RO MCACHE 4. 0x76c4c000 0x00000fdc
1907 12:45:08.604471 CONSOLE 5. 0x76c2c000 0x00020000
1908 12:45:08.607419 FMAP 6. 0x76c2b000 0x00000578
1909 12:45:08.610548 TIME STAMP 7. 0x76c2a000 0x00000910
1910 12:45:08.614377 VBOOT WORK 8. 0x76c16000 0x00014000
1911 12:45:08.620957 ROMSTG STCK 9. 0x76c15000 0x00001000
1912 12:45:08.624109 AFTER CAR 10. 0x76c0a000 0x0000b000
1913 12:45:08.627441 RAMSTAGE 11. 0x76b97000 0x00073000
1914 12:45:08.631070 REFCODE 12. 0x76b42000 0x00055000
1915 12:45:08.634057 SMM BACKUP 13. 0x76b32000 0x00010000
1916 12:45:08.637377 4f444749 14. 0x76b30000 0x00002000
1917 12:45:08.641066 EXT VBT15. 0x76b2d000 0x0000219f
1918 12:45:08.644764 COREBOOT 16. 0x76b25000 0x00008000
1919 12:45:08.647299 ACPI 17. 0x76b01000 0x00024000
1920 12:45:08.654235 ACPI GNVS 18. 0x76b00000 0x00001000
1921 12:45:08.658302 RAMOOPS 19. 0x76a00000 0x00100000
1922 12:45:08.660574 TPM2 TCGLOG20. 0x769f0000 0x00010000
1923 12:45:08.664194 SMBIOS 21. 0x769ef000 0x00000800
1924 12:45:08.664541 IMD small region:
1925 12:45:08.670626 IMD ROOT 0. 0x76ffec00 0x00000400
1926 12:45:08.674363 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1927 12:45:08.677905 POWER STATE 2. 0x76ffeb80 0x00000044
1928 12:45:08.681072 ROMSTAGE 3. 0x76ffeb60 0x00000004
1929 12:45:08.684755 MEM INFO 4. 0x76ffe980 0x000001e0
1930 12:45:08.691088 BS: BS_WRITE_TABLES run times (exec / console): 5 / 484 ms
1931 12:45:08.693977 MTRR: Physical address space:
1932 12:45:08.700841 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1933 12:45:08.707404 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1934 12:45:08.713824 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1935 12:45:08.720644 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1936 12:45:08.724160 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1937 12:45:08.730473 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1938 12:45:08.737004 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1939 12:45:08.743819 MTRR: Fixed MSR 0x250 0x0606060606060606
1940 12:45:08.746859 MTRR: Fixed MSR 0x258 0x0606060606060606
1941 12:45:08.750109 MTRR: Fixed MSR 0x259 0x0000000000000000
1942 12:45:08.753691 MTRR: Fixed MSR 0x268 0x0606060606060606
1943 12:45:08.756906 MTRR: Fixed MSR 0x269 0x0606060606060606
1944 12:45:08.763540 MTRR: Fixed MSR 0x26a 0x0606060606060606
1945 12:45:08.766803 MTRR: Fixed MSR 0x26b 0x0606060606060606
1946 12:45:08.770379 MTRR: Fixed MSR 0x26c 0x0606060606060606
1947 12:45:08.774092 MTRR: Fixed MSR 0x26d 0x0606060606060606
1948 12:45:08.780438 MTRR: Fixed MSR 0x26e 0x0606060606060606
1949 12:45:08.783821 MTRR: Fixed MSR 0x26f 0x0606060606060606
1950 12:45:08.787179 call enable_fixed_mtrr()
1951 12:45:08.790170 CPU physical address size: 39 bits
1952 12:45:08.793529 MTRR: default type WB/UC MTRR counts: 6/6.
1953 12:45:08.796842 MTRR: UC selected as default type.
1954 12:45:08.803605 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1955 12:45:08.810320 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1956 12:45:08.816564 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1957 12:45:08.823471 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1958 12:45:08.830153 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1959 12:45:08.836485 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1960 12:45:08.837064
1961 12:45:08.840417 MTRR check
1962 12:45:08.841002 Fixed MTRRs : Enabled
1963 12:45:08.842961 Variable MTRRs: Enabled
1964 12:45:08.843452
1965 12:45:08.846482 MTRR: Fixed MSR 0x250 0x0606060606060606
1966 12:45:08.852919 MTRR: Fixed MSR 0x258 0x0606060606060606
1967 12:45:08.856538 MTRR: Fixed MSR 0x259 0x0000000000000000
1968 12:45:08.859958 MTRR: Fixed MSR 0x268 0x0606060606060606
1969 12:45:08.862827 MTRR: Fixed MSR 0x269 0x0606060606060606
1970 12:45:08.869461 MTRR: Fixed MSR 0x26a 0x0606060606060606
1971 12:45:08.873039 MTRR: Fixed MSR 0x26b 0x0606060606060606
1972 12:45:08.876165 MTRR: Fixed MSR 0x26c 0x0606060606060606
1973 12:45:08.879494 MTRR: Fixed MSR 0x26d 0x0606060606060606
1974 12:45:08.882982 MTRR: Fixed MSR 0x26e 0x0606060606060606
1975 12:45:08.890533 MTRR: Fixed MSR 0x26f 0x0606060606060606
1976 12:45:08.896013 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1977 12:45:08.899935 call enable_fixed_mtrr()
1978 12:45:08.903766 Checking cr50 for pending updates
1979 12:45:08.904349 CPU physical address size: 39 bits
1980 12:45:08.910232 MTRR: Fixed MSR 0x250 0x0606060606060606
1981 12:45:08.913235 MTRR: Fixed MSR 0x250 0x0606060606060606
1982 12:45:08.916875 MTRR: Fixed MSR 0x258 0x0606060606060606
1983 12:45:08.920208 MTRR: Fixed MSR 0x259 0x0000000000000000
1984 12:45:08.926817 MTRR: Fixed MSR 0x268 0x0606060606060606
1985 12:45:08.930274 MTRR: Fixed MSR 0x269 0x0606060606060606
1986 12:45:08.934019 MTRR: Fixed MSR 0x26a 0x0606060606060606
1987 12:45:08.936516 MTRR: Fixed MSR 0x26b 0x0606060606060606
1988 12:45:08.943120 MTRR: Fixed MSR 0x26c 0x0606060606060606
1989 12:45:08.946903 MTRR: Fixed MSR 0x26d 0x0606060606060606
1990 12:45:08.949894 MTRR: Fixed MSR 0x26e 0x0606060606060606
1991 12:45:08.953299 MTRR: Fixed MSR 0x26f 0x0606060606060606
1992 12:45:08.961185 MTRR: Fixed MSR 0x258 0x0606060606060606
1993 12:45:08.961812 call enable_fixed_mtrr()
1994 12:45:08.967182 MTRR: Fixed MSR 0x259 0x0000000000000000
1995 12:45:08.970642 MTRR: Fixed MSR 0x268 0x0606060606060606
1996 12:45:08.973618 MTRR: Fixed MSR 0x269 0x0606060606060606
1997 12:45:08.977266 MTRR: Fixed MSR 0x26a 0x0606060606060606
1998 12:45:08.983686 MTRR: Fixed MSR 0x26b 0x0606060606060606
1999 12:45:08.986943 MTRR: Fixed MSR 0x26c 0x0606060606060606
2000 12:45:08.990527 MTRR: Fixed MSR 0x26d 0x0606060606060606
2001 12:45:08.993474 MTRR: Fixed MSR 0x26e 0x0606060606060606
2002 12:45:09.000376 MTRR: Fixed MSR 0x26f 0x0606060606060606
2003 12:45:09.003858 CPU physical address size: 39 bits
2004 12:45:09.007067 call enable_fixed_mtrr()
2005 12:45:09.010117 Reading cr50 TPM mode
2006 12:45:09.014631 MTRR: Fixed MSR 0x250 0x0606060606060606
2007 12:45:09.017777 MTRR: Fixed MSR 0x250 0x0606060606060606
2008 12:45:09.021212 MTRR: Fixed MSR 0x258 0x0606060606060606
2009 12:45:09.024618 MTRR: Fixed MSR 0x259 0x0000000000000000
2010 12:45:09.031022 MTRR: Fixed MSR 0x268 0x0606060606060606
2011 12:45:09.034165 MTRR: Fixed MSR 0x269 0x0606060606060606
2012 12:45:09.037694 MTRR: Fixed MSR 0x26a 0x0606060606060606
2013 12:45:09.040729 MTRR: Fixed MSR 0x26b 0x0606060606060606
2014 12:45:09.047501 MTRR: Fixed MSR 0x26c 0x0606060606060606
2015 12:45:09.051367 MTRR: Fixed MSR 0x26d 0x0606060606060606
2016 12:45:09.054471 MTRR: Fixed MSR 0x26e 0x0606060606060606
2017 12:45:09.057692 MTRR: Fixed MSR 0x26f 0x0606060606060606
2018 12:45:09.064698 MTRR: Fixed MSR 0x258 0x0606060606060606
2019 12:45:09.065406 call enable_fixed_mtrr()
2020 12:45:09.071198 MTRR: Fixed MSR 0x259 0x0000000000000000
2021 12:45:09.074414 MTRR: Fixed MSR 0x268 0x0606060606060606
2022 12:45:09.077816 MTRR: Fixed MSR 0x269 0x0606060606060606
2023 12:45:09.080969 MTRR: Fixed MSR 0x26a 0x0606060606060606
2024 12:45:09.087795 MTRR: Fixed MSR 0x26b 0x0606060606060606
2025 12:45:09.091120 MTRR: Fixed MSR 0x26c 0x0606060606060606
2026 12:45:09.094530 MTRR: Fixed MSR 0x26d 0x0606060606060606
2027 12:45:09.097888 MTRR: Fixed MSR 0x26e 0x0606060606060606
2028 12:45:09.104688 MTRR: Fixed MSR 0x26f 0x0606060606060606
2029 12:45:09.108474 CPU physical address size: 39 bits
2030 12:45:09.110803 call enable_fixed_mtrr()
2031 12:45:09.114892 MTRR: Fixed MSR 0x250 0x0606060606060606
2032 12:45:09.117978 MTRR: Fixed MSR 0x250 0x0606060606060606
2033 12:45:09.124529 MTRR: Fixed MSR 0x258 0x0606060606060606
2034 12:45:09.127467 MTRR: Fixed MSR 0x259 0x0000000000000000
2035 12:45:09.131139 MTRR: Fixed MSR 0x268 0x0606060606060606
2036 12:45:09.134486 MTRR: Fixed MSR 0x269 0x0606060606060606
2037 12:45:09.141074 MTRR: Fixed MSR 0x26a 0x0606060606060606
2038 12:45:09.144616 MTRR: Fixed MSR 0x26b 0x0606060606060606
2039 12:45:09.147428 MTRR: Fixed MSR 0x26c 0x0606060606060606
2040 12:45:09.150550 MTRR: Fixed MSR 0x26d 0x0606060606060606
2041 12:45:09.157547 MTRR: Fixed MSR 0x26e 0x0606060606060606
2042 12:45:09.161199 MTRR: Fixed MSR 0x26f 0x0606060606060606
2043 12:45:09.164502 MTRR: Fixed MSR 0x258 0x0606060606060606
2044 12:45:09.167470 call enable_fixed_mtrr()
2045 12:45:09.170576 MTRR: Fixed MSR 0x259 0x0000000000000000
2046 12:45:09.177450 MTRR: Fixed MSR 0x268 0x0606060606060606
2047 12:45:09.181006 MTRR: Fixed MSR 0x269 0x0606060606060606
2048 12:45:09.184776 MTRR: Fixed MSR 0x26a 0x0606060606060606
2049 12:45:09.187533 MTRR: Fixed MSR 0x26b 0x0606060606060606
2050 12:45:09.194252 MTRR: Fixed MSR 0x26c 0x0606060606060606
2051 12:45:09.197931 MTRR: Fixed MSR 0x26d 0x0606060606060606
2052 12:45:09.200330 MTRR: Fixed MSR 0x26e 0x0606060606060606
2053 12:45:09.204328 MTRR: Fixed MSR 0x26f 0x0606060606060606
2054 12:45:09.207698 CPU physical address size: 39 bits
2055 12:45:09.214875 call enable_fixed_mtrr()
2056 12:45:09.217834 CPU physical address size: 39 bits
2057 12:45:09.221172 BS: BS_PAYLOAD_LOAD entry times (exec / console): 112 / 6 ms
2058 12:45:09.227418 CPU physical address size: 39 bits
2059 12:45:09.234452 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2060 12:45:09.237903 CPU physical address size: 39 bits
2061 12:45:09.241128 Checking segment from ROM address 0xffc02b38
2062 12:45:09.248056 Checking segment from ROM address 0xffc02b54
2063 12:45:09.250659 Loading segment from ROM address 0xffc02b38
2064 12:45:09.254070 code (compression=0)
2065 12:45:09.260950 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2066 12:45:09.271226 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2067 12:45:09.271718 it's not compressed!
2068 12:45:09.411398 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2069 12:45:09.417904 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2070 12:45:09.424951 Loading segment from ROM address 0xffc02b54
2071 12:45:09.425538 Entry Point 0x30000000
2072 12:45:09.427661 Loaded segments
2073 12:45:09.435122 BS: BS_PAYLOAD_LOAD run times (exec / console): 142 / 63 ms
2074 12:45:09.477632 Finalizing chipset.
2075 12:45:09.480451 Finalizing SMM.
2076 12:45:09.480941 APMC done.
2077 12:45:09.487622 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2078 12:45:09.490782 mp_park_aps done after 0 msecs.
2079 12:45:09.493928 Jumping to boot code at 0x30000000(0x76b25000)
2080 12:45:09.504173 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2081 12:45:09.504759
2082 12:45:09.507745 Starting depthcharge on Voema...
2083 12:45:09.509239 end: 2.2.3 depthcharge-start (duration 00:00:15) [common]
2084 12:45:09.509876 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2085 12:45:09.510359 Setting prompt string to ['volteer:']
2086 12:45:09.510794 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2087 12:45:09.518026 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2088 12:45:09.524210 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2089 12:45:09.527068 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2090 12:45:09.533738 Failed to find eMMC card reader
2091 12:45:09.534324 Wipe memory regions:
2092 12:45:09.540511 [0x00000000001000, 0x000000000a0000)
2093 12:45:09.543536 [0x00000000100000, 0x00000030000000)
2094 12:45:09.571808 [0x00000032662db0, 0x000000769ef000)
2095 12:45:09.611730 [0x00000100000000, 0x00000280400000)
2096 12:45:09.815926 ec_init: CrosEC protocol v3 supported (256, 256)
2097 12:45:09.822214 update_port_state: port C0 state: usb enable 1 mux conn 0
2098 12:45:09.832163 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2099 12:45:09.835509 pmc_check_ipc_sts: STS_BUSY done after 1561 us
2100 12:45:09.842314 send_conn_disc_msg: pmc_send_cmd succeeded
2101 12:45:10.274962 R8152: Initializing
2102 12:45:10.278100 Version 6 (ocp_data = 5c30)
2103 12:45:10.281537 R8152: Done initializing
2104 12:45:10.284470 Adding net device
2105 12:45:10.590958 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2106 12:45:10.591547
2107 12:45:10.594045 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.']
2109 12:45:10.696227 volteer: tftpboot 192.168.201.1 6819473/tftp-deploy-a7c9kj42/kernel/bzImage 6819473/tftp-deploy-a7c9kj42/kernel/cmdline 6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
2110 12:45:10.696938 Setting prompt string to ['Starting kernel']
2111 12:45:10.697499 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.']
2112 12:45:10.698002 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.'] (timeout 00:04:43)
2113 12:45:10.702458 tftpboot 192.168.201.1 6819473/tftp-deploy-a7c9kj42/kernel/bzImaoy-a7c9kj42/kernel/cmdline 6819473/tftp-deploy-a7c9kj42/ramdisk/ramdisk.cpio.gz
2114 12:45:10.702964 Waiting for link
2115 12:45:10.907134 done.
2116 12:45:10.907716 MAC: 00:24:32:30:78:74
2117 12:45:10.909984 Sending DHCP discover... done.
2118 12:45:10.913246 Waiting for reply... done.
2119 12:45:10.916653 Sending DHCP request... done.
2120 12:45:10.920370 Waiting for reply... done.
2121 12:45:10.923539 My ip is 192.168.201.10
2122 12:45:10.926937 The DHCP server ip is 192.168.201.1
2123 12:45:10.933477 TFTP server IP predefined by user: 192.168.201.1
2124 12:45:10.939940 Bootfile predefined by user: 6819473/tftp-deploy-a7c9kj42/kernel/bzImage
2125 12:45:10.943130 Sending tftp read request... done.
2126 12:45:10.946427 Waiting for the transfer...
2127 12:45:11.675898 00000000 ################################################################
2128 12:45:12.405924 00080000 ################################################################
2129 12:45:13.127605 00100000 ################################################################
2130 12:45:13.866011 00180000 ################################################################
2131 12:45:14.594345 00200000 ################################################################
2132 12:45:15.328977 00280000 ################################################################
2133 12:45:16.074470 00300000 ################################################################
2134 12:45:16.817500 00380000 ################################################################
2135 12:45:17.548848 00400000 ################################################################
2136 12:45:18.280955 00480000 ################################################################
2137 12:45:19.020073 00500000 ################################################################
2138 12:45:19.746764 00580000 ################################################################
2139 12:45:20.469318 00600000 ################################################################ done.
2140 12:45:20.472457 The bootfile was 6811536 bytes long.
2141 12:45:20.475925 Sending tftp read request... done.
2142 12:45:20.479544 Waiting for the transfer...
2143 12:45:21.216656 00000000 ################################################################
2144 12:45:21.927433 00080000 ################################################################
2145 12:45:22.630980 00100000 ################################################################
2146 12:45:23.359806 00180000 ################################################################
2147 12:45:24.096487 00200000 ################################################################
2148 12:45:24.836706 00280000 ################################################################
2149 12:45:25.565105 00300000 ################################################################
2150 12:45:26.298991 00380000 ################################################################
2151 12:45:27.058337 00400000 ################################################################
2152 12:45:27.784442 00480000 ################################################################
2153 12:45:28.532879 00500000 ################################################################
2154 12:45:29.272301 00580000 ################################################################
2155 12:45:29.983637 00600000 ################################################################
2156 12:45:30.710559 00680000 ################################################################
2157 12:45:31.431643 00700000 ################################################################
2158 12:45:32.165489 00780000 ################################################################
2159 12:45:32.388284 00800000 #################### done.
2160 12:45:32.391524 Sending tftp read request... done.
2161 12:45:32.394714 Waiting for the transfer...
2162 12:45:32.395160 00000000 # done.
2163 12:45:32.405072 Command line loaded dynamically from TFTP file: 6819473/tftp-deploy-a7c9kj42/kernel/cmdline
2164 12:45:32.418116 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2165 12:45:32.424820 Shutting down all USB controllers.
2166 12:45:32.425396 Removing current net device
2167 12:45:32.428316 Finalizing coreboot
2168 12:45:32.435244 Exiting depthcharge with code 4 at timestamp: 31577301
2169 12:45:32.435829
2170 12:45:32.436327 Starting kernel ...
2171 12:45:32.436786
2172 12:45:32.437236
2173 12:45:32.438273 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
2174 12:45:32.438907 start: 2.2.5 auto-login-action (timeout 00:04:21) [common]
2175 12:45:32.439373 Setting prompt string to ['Linux version [0-9]']
2176 12:45:32.439855 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.']
2177 12:45:32.440346 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.'] (timeout 00:05:00)
2179 12:49:53.439850 end: 2.2.5 auto-login-action (duration 00:04:21) [common]
2181 12:49:53.441696 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 261 seconds'
2183 12:49:53.443103 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2186 12:49:53.444812 end: 2 depthcharge-action (duration 00:05:00) [common]
2188 12:49:53.445005 Cleaning after the job
2189 12:49:53.445087 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/ramdisk
2190 12:49:53.445779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/kernel
2191 12:49:53.446283 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/6819473/tftp-deploy-a7c9kj42/modules
2192 12:49:53.446472 start: 5.1 power-off (timeout 00:00:30) [common]
2193 12:49:53.446620 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-1' '--port=1' '--command=off'
2194 12:49:53.465511 >> Command sent successfully.
2195 12:49:53.467581 Returned 0 in 0 seconds
2196 12:49:53.568800 end: 5.1 power-off (duration 00:00:00) [common]
2198 12:49:53.570501 start: 5.2 read-feedback (timeout 00:10:00) [common]
2199 12:49:53.571679 Listened to connection for namespace 'common' for up to 1s
2200 12:49:54.573706 Finalising connection for namespace 'common'
2201 12:49:54.573881 Disconnecting from shell: Finalise
2202 12:49:54.674695 end: 5.2 read-feedback (duration 00:00:01) [common]
2203 12:49:54.674867 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/6819473
2204 12:49:54.679799 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/6819473
2205 12:49:54.679946 JobError: Your job cannot terminate cleanly.