Boot log: asus-C436FA-Flip-hatch
- Kernel Warnings: 0
- Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
1 07:48:41.869146 lava-dispatcher, installed at version: 2022.10
2 07:48:41.869336 start: 0 validate
3 07:48:41.869467 Start time: 2022-11-25 07:48:41.869460+00:00 (UTC)
4 07:48:41.869603 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:48:41.869765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20221107.1%2Fx86%2Frootfs.cpio.gz exists
6 07:48:42.170938 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:48:42.171674 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:48:42.454553 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:48:42.454720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 07:48:42.758282 validate duration: 0.89
12 07:48:42.758559 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 07:48:42.758665 start: 1.1 download-retry (timeout 00:10:00) [common]
14 07:48:42.758761 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 07:48:42.758871 Not decompressing ramdisk as can be used compressed.
16 07:48:42.758956 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20221107.1/x86/rootfs.cpio.gz
17 07:48:42.759024 saving as /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/ramdisk/rootfs.cpio.gz
18 07:48:42.759086 total size: 8415749 (8MB)
19 07:48:42.760128 progress 0% (0MB)
20 07:48:42.762344 progress 5% (0MB)
21 07:48:42.764592 progress 10% (0MB)
22 07:48:42.766871 progress 15% (1MB)
23 07:48:42.769206 progress 20% (1MB)
24 07:48:42.771559 progress 25% (2MB)
25 07:48:42.773799 progress 30% (2MB)
26 07:48:42.775761 progress 35% (2MB)
27 07:48:42.777910 progress 40% (3MB)
28 07:48:42.779998 progress 45% (3MB)
29 07:48:42.782092 progress 50% (4MB)
30 07:48:42.784175 progress 55% (4MB)
31 07:48:42.786272 progress 60% (4MB)
32 07:48:42.788184 progress 65% (5MB)
33 07:48:42.790263 progress 70% (5MB)
34 07:48:42.792306 progress 75% (6MB)
35 07:48:42.794646 progress 80% (6MB)
36 07:48:42.796803 progress 85% (6MB)
37 07:48:42.798922 progress 90% (7MB)
38 07:48:42.800869 progress 95% (7MB)
39 07:48:42.802977 progress 100% (8MB)
40 07:48:42.803271 8MB downloaded in 0.04s (181.66MB/s)
41 07:48:42.803430 end: 1.1.1 http-download (duration 00:00:00) [common]
43 07:48:42.803674 end: 1.1 download-retry (duration 00:00:00) [common]
44 07:48:42.803765 start: 1.2 download-retry (timeout 00:10:00) [common]
45 07:48:42.803853 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 07:48:42.803963 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 07:48:42.804034 saving as /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/kernel/bzImage
48 07:48:42.804098 total size: 7131024 (6MB)
49 07:48:42.804159 No compression specified
50 07:48:45.309011 progress 0% (0MB)
51 07:48:45.311025 progress 5% (0MB)
52 07:48:45.312916 progress 10% (0MB)
53 07:48:45.314688 progress 15% (1MB)
54 07:48:45.316456 progress 20% (1MB)
55 07:48:45.318297 progress 25% (1MB)
56 07:48:45.320111 progress 30% (2MB)
57 07:48:45.321925 progress 35% (2MB)
58 07:48:45.323665 progress 40% (2MB)
59 07:48:45.325287 progress 45% (3MB)
60 07:48:45.327078 progress 50% (3MB)
61 07:48:45.328814 progress 55% (3MB)
62 07:48:45.330534 progress 60% (4MB)
63 07:48:45.332254 progress 65% (4MB)
64 07:48:45.334030 progress 70% (4MB)
65 07:48:45.335760 progress 75% (5MB)
66 07:48:45.337524 progress 80% (5MB)
67 07:48:45.339098 progress 85% (5MB)
68 07:48:45.340900 progress 90% (6MB)
69 07:48:45.342769 progress 95% (6MB)
70 07:48:45.344534 progress 100% (6MB)
71 07:48:45.344816 6MB downloaded in 2.54s (2.68MB/s)
72 07:48:45.344976 end: 1.2.1 http-download (duration 00:00:03) [common]
74 07:48:45.345219 end: 1.2 download-retry (duration 00:00:03) [common]
75 07:48:45.345309 start: 1.3 download-retry (timeout 00:09:57) [common]
76 07:48:45.345396 start: 1.3.1 http-download (timeout 00:09:57) [common]
77 07:48:45.345506 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 07:48:45.345574 saving as /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/modules/modules.tar
79 07:48:45.345636 total size: 52060 (0MB)
80 07:48:45.345698 Using unxz to decompress xz
81 07:48:45.348980 progress 62% (0MB)
82 07:48:45.349396 progress 100% (0MB)
83 07:48:45.352652 0MB downloaded in 0.01s (7.09MB/s)
84 07:48:45.352941 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:48:45.353214 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:48:45.353312 start: 1.4 prepare-tftp-overlay (timeout 00:09:57) [common]
88 07:48:45.353412 start: 1.4.1 extract-nfsrootfs (timeout 00:09:57) [common]
89 07:48:45.353500 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 07:48:45.353589 start: 1.4.2 lava-overlay (timeout 00:09:57) [common]
91 07:48:45.353760 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v
92 07:48:45.353870 makedir: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin
93 07:48:45.353956 makedir: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/tests
94 07:48:45.354040 makedir: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/results
95 07:48:45.354150 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-add-keys
96 07:48:45.354285 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-add-sources
97 07:48:45.354406 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-background-process-start
98 07:48:45.354520 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-background-process-stop
99 07:48:45.354633 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-common-functions
100 07:48:45.354744 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-echo-ipv4
101 07:48:45.354857 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-install-packages
102 07:48:45.354970 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-installed-packages
103 07:48:45.355080 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-os-build
104 07:48:45.355189 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-probe-channel
105 07:48:45.355304 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-probe-ip
106 07:48:45.355414 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-target-ip
107 07:48:45.355523 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-target-mac
108 07:48:45.355633 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-target-storage
109 07:48:45.355749 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-case
110 07:48:45.355862 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-event
111 07:48:45.355986 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-feedback
112 07:48:45.356097 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-raise
113 07:48:45.356215 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-reference
114 07:48:45.356336 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-runner
115 07:48:45.356457 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-set
116 07:48:45.356576 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-test-shell
117 07:48:45.356700 Updating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-install-packages (oe)
118 07:48:45.356877 Updating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/bin/lava-installed-packages (oe)
119 07:48:45.357014 Creating /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/environment
120 07:48:45.357112 LAVA metadata
121 07:48:45.357187 - LAVA_JOB_ID=8119365
122 07:48:45.357285 - LAVA_DISPATCHER_IP=192.168.201.1
123 07:48:45.357397 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:57) [common]
124 07:48:45.357463 skipped lava-vland-overlay
125 07:48:45.357543 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 07:48:45.357631 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
127 07:48:45.357697 skipped lava-multinode-overlay
128 07:48:45.357777 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 07:48:45.357861 start: 1.4.2.3 test-definition (timeout 00:09:57) [common]
130 07:48:45.357942 Loading test definitions
131 07:48:45.358042 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:57) [common]
132 07:48:45.358123 Using /lava-8119365 at stage 0
133 07:48:45.358404 uuid=8119365_1.4.2.3.1 testdef=None
134 07:48:45.358501 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 07:48:45.358599 start: 1.4.2.3.2 test-overlay (timeout 00:09:57) [common]
136 07:48:45.359109 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 07:48:45.359348 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:57) [common]
139 07:48:45.359925 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 07:48:45.360168 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
142 07:48:45.360717 runner path: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/0/tests/0_dmesg test_uuid 8119365_1.4.2.3.1
143 07:48:45.360911 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 07:48:45.361146 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:57) [common]
146 07:48:45.361221 Using /lava-8119365 at stage 1
147 07:48:45.361470 uuid=8119365_1.4.2.3.5 testdef=None
148 07:48:45.361563 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 07:48:45.361654 start: 1.4.2.3.6 test-overlay (timeout 00:09:57) [common]
150 07:48:45.362113 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 07:48:45.362342 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:57) [common]
153 07:48:45.362916 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 07:48:45.363157 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:57) [common]
156 07:48:45.363711 runner path: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/1/tests/1_bootrr test_uuid 8119365_1.4.2.3.5
157 07:48:45.363887 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 07:48:45.364107 Creating lava-test-runner.conf files
160 07:48:45.364174 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/0 for stage 0
161 07:48:45.364258 - 0_dmesg
162 07:48:45.364335 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8119365/lava-overlay-iwfuj65v/lava-8119365/1 for stage 1
163 07:48:45.364419 - 1_bootrr
164 07:48:45.364512 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 07:48:45.364599 start: 1.4.2.4 compress-overlay (timeout 00:09:57) [common]
166 07:48:45.371342 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 07:48:45.371497 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
168 07:48:45.371596 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 07:48:45.371687 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 07:48:45.371780 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
171 07:48:45.558712 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 07:48:45.559056 start: 1.4.4 extract-modules (timeout 00:09:57) [common]
173 07:48:45.559171 extracting modules file /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8119365/extract-overlay-ramdisk-m9xp03vn/ramdisk
174 07:48:45.563470 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 07:48:45.563612 start: 1.4.5 apply-overlay-tftp (timeout 00:09:57) [common]
176 07:48:45.563702 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119365/compress-overlay-ll6otikj/overlay-1.4.2.4.tar.gz to ramdisk
177 07:48:45.563814 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119365/compress-overlay-ll6otikj/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8119365/extract-overlay-ramdisk-m9xp03vn/ramdisk
178 07:48:45.567882 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 07:48:45.568020 start: 1.4.6 configure-preseed-file (timeout 00:09:57) [common]
180 07:48:45.568118 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 07:48:45.568230 start: 1.4.7 compress-ramdisk (timeout 00:09:57) [common]
182 07:48:45.568345 Building ramdisk /var/lib/lava/dispatcher/tmp/8119365/extract-overlay-ramdisk-m9xp03vn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8119365/extract-overlay-ramdisk-m9xp03vn/ramdisk
183 07:48:45.633460 >> 48008 blocks
184 07:48:46.395735 rename /var/lib/lava/dispatcher/tmp/8119365/extract-overlay-ramdisk-m9xp03vn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
185 07:48:46.396179 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 07:48:46.396316 start: 1.4.8 prepare-kernel (timeout 00:09:56) [common]
187 07:48:46.396420 start: 1.4.8.1 prepare-fit (timeout 00:09:56) [common]
188 07:48:46.396523 No mkimage arch provided, not using FIT.
189 07:48:46.396630 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 07:48:46.396756 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 07:48:46.396864 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 07:48:46.396968 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:56) [common]
193 07:48:46.397052 No LXC device requested
194 07:48:46.397146 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 07:48:46.397252 start: 1.6 deploy-device-env (timeout 00:09:56) [common]
196 07:48:46.397365 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 07:48:46.397444 Checking files for TFTP limit of 4294967296 bytes.
198 07:48:46.397847 end: 1 tftp-deploy (duration 00:00:04) [common]
199 07:48:46.397976 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 07:48:46.398139 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 07:48:46.398312 substitutions:
202 07:48:46.398388 - {DTB}: None
203 07:48:46.398458 - {INITRD}: 8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
204 07:48:46.398522 - {KERNEL}: 8119365/tftp-deploy-qzzzfjpq/kernel/bzImage
205 07:48:46.398590 - {LAVA_MAC}: None
206 07:48:46.398651 - {PRESEED_CONFIG}: None
207 07:48:46.398717 - {PRESEED_LOCAL}: None
208 07:48:46.398776 - {RAMDISK}: 8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
209 07:48:46.398836 - {ROOT_PART}: None
210 07:48:46.398927 - {ROOT}: None
211 07:48:46.398987 - {SERVER_IP}: 192.168.201.1
212 07:48:46.399052 - {TEE}: None
213 07:48:46.399110 Parsed boot commands:
214 07:48:46.399173 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 07:48:46.399336 Parsed boot commands: tftpboot 192.168.201.1 8119365/tftp-deploy-qzzzfjpq/kernel/bzImage 8119365/tftp-deploy-qzzzfjpq/kernel/cmdline 8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
216 07:48:46.399436 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 07:48:46.399564 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 07:48:46.399669 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 07:48:46.399769 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 07:48:46.399845 Not connected, no need to disconnect.
221 07:48:46.399930 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 07:48:46.400023 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 07:48:46.400097 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-3'
224 07:48:46.402949 Setting prompt string to ['lava-test: # ']
225 07:48:46.403339 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 07:48:46.403467 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 07:48:46.403571 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 07:48:46.403673 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 07:48:46.403885 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=reboot'
230 07:48:46.423698 >> Command sent successfully.
231 07:48:46.425834 Returned 0 in 0 seconds
232 07:48:46.526636 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 07:48:46.526980 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 07:48:46.527093 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 07:48:46.527194 Setting prompt string to 'Starting depthcharge on Helios...'
237 07:48:46.527281 Changing prompt to 'Starting depthcharge on Helios...'
238 07:48:46.527359 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
239 07:48:46.527706 [Enter `^Ec?' for help]
240 07:48:53.762160
241 07:48:53.762344
242 07:48:53.771910 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
243 07:48:53.775807 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
244 07:48:53.781872 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
245 07:48:53.785154 CPU: AES supported, TXT NOT supported, VT supported
246 07:48:53.792375 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
247 07:48:53.795494 PCH: device id 0284 (rev 00) is Cometlake-U Premium
248 07:48:53.801871 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
249 07:48:53.805033 VBOOT: Loading verstage.
250 07:48:53.808202 FMAP: Found "FLASH" version 1.1 at 0xc04000.
251 07:48:53.814702 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
252 07:48:53.821578 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
253 07:48:53.821664 CBFS @ c08000 size 3f8000
254 07:48:53.827991 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
255 07:48:53.831282 CBFS: Locating 'fallback/verstage'
256 07:48:53.834423 CBFS: Found @ offset 10fb80 size 1072c
257 07:48:53.838929
258 07:48:53.839002
259 07:48:53.848698 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
260 07:48:53.863201 Probing TPM: . done!
261 07:48:53.866956 TPM ready after 0 ms
262 07:48:53.870073 Connected to device vid:did:rid of 1ae0:0028:00
263 07:48:53.880130 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
264 07:48:53.883226 Initialized TPM device CR50 revision 0
265 07:48:53.925098 tlcl_send_startup: Startup return code is 0
266 07:48:53.925258 TPM: setup succeeded
267 07:48:53.937322 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
268 07:48:53.941032 Chrome EC: UHEPI supported
269 07:48:53.944420 Phase 1
270 07:48:53.947689 FMAP: area GBB found @ c05000 (12288 bytes)
271 07:48:53.954234 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
272 07:48:53.957660 Phase 2
273 07:48:53.957746 Phase 3
274 07:48:53.960839 FMAP: area GBB found @ c05000 (12288 bytes)
275 07:48:53.968118 VB2:vb2_report_dev_firmware() This is developer signed firmware
276 07:48:53.974318 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
277 07:48:53.977578 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
278 07:48:53.984040 VB2:vb2_verify_keyblock() Checking keyblock signature...
279 07:48:53.999771 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
280 07:48:54.002997 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
281 07:48:54.010378 VB2:vb2_verify_fw_preamble() Verifying preamble.
282 07:48:54.013797 Phase 4
283 07:48:54.017174 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
284 07:48:54.024278 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
285 07:48:54.203370 VB2:vb2_rsa_verify_digest() Digest check failed!
286 07:48:54.206654 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
287 07:48:54.210312
288 07:48:54.210392 Saving nvdata
289 07:48:54.213325 Reboot requested (10020007)
290 07:48:54.216948 board_reset() called!
291 07:48:54.217031 full_reset() called!
292 07:48:58.729661
293 07:48:58.729873
294 07:48:58.739346 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
295 07:48:58.742555 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
296 07:48:58.748905 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
297 07:48:58.751938 CPU: AES supported, TXT NOT supported, VT supported
298 07:48:58.758688 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
299 07:48:58.761980 PCH: device id 0284 (rev 00) is Cometlake-U Premium
300 07:48:58.769053 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
301 07:48:58.771817 VBOOT: Loading verstage.
302 07:48:58.775617 FMAP: Found "FLASH" version 1.1 at 0xc04000.
303 07:48:58.781841 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
304 07:48:58.788367 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
305 07:48:58.788455 CBFS @ c08000 size 3f8000
306 07:48:58.795012 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
307 07:48:58.798238 CBFS: Locating 'fallback/verstage'
308 07:48:58.801446 CBFS: Found @ offset 10fb80 size 1072c
309 07:48:58.805775
310 07:48:58.805861
311 07:48:58.815471 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
312 07:48:58.830886 Probing TPM: . done!
313 07:48:58.833838 TPM ready after 0 ms
314 07:48:58.837000 Connected to device vid:did:rid of 1ae0:0028:00
315 07:48:58.846800 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
316 07:48:58.850490 Initialized TPM device CR50 revision 0
317 07:48:58.891610 tlcl_send_startup: Startup return code is 0
318 07:48:58.891760 TPM: setup succeeded
319 07:48:58.904323 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
320 07:48:58.908611 Chrome EC: UHEPI supported
321 07:48:58.911224 Phase 1
322 07:48:58.915080 FMAP: area GBB found @ c05000 (12288 bytes)
323 07:48:58.921350 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
324 07:48:58.927580 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
325 07:48:58.930934 Recovery requested (1009000e)
326 07:48:58.937216 Saving nvdata
327 07:48:58.942235 tlcl_extend: response is 0
328 07:48:58.951894 tlcl_extend: response is 0
329 07:48:58.958923 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
330 07:48:58.962196 CBFS @ c08000 size 3f8000
331 07:48:58.968745 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
332 07:48:58.971999 CBFS: Locating 'fallback/romstage'
333 07:48:58.975679 CBFS: Found @ offset 80 size 145fc
334 07:48:58.978925 Accumulated console time in verstage 98 ms
335 07:48:58.979039
336 07:48:58.979110
337 07:48:58.991752 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
338 07:48:58.998121 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
339 07:48:59.001533 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
340 07:48:59.005310 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
341 07:48:59.011448 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
342 07:48:59.015453 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
343 07:48:59.017899 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
344 07:48:59.021448 TCO_STS: 0000 0000
345 07:48:59.024663 GEN_PMCON: e0015238 00000200
346 07:48:59.027932 GBLRST_CAUSE: 00000000 00000000
347 07:48:59.028018 prev_sleep_state 5
348 07:48:59.031454 Boot Count incremented to 39065
349 07:48:59.038294 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
350 07:48:59.041541 CBFS @ c08000 size 3f8000
351 07:48:59.048077 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
352 07:48:59.048166 CBFS: Locating 'fspm.bin'
353 07:48:59.051692 CBFS: Found @ offset 5ffc0 size 71000
354 07:48:59.055089
355 07:48:59.058166 Chrome EC: UHEPI supported
356 07:48:59.064883 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
357 07:48:59.068095 Probing TPM: done!
358 07:48:59.075263 Connected to device vid:did:rid of 1ae0:0028:00
359 07:48:59.085024 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
360 07:48:59.090926 Initialized TPM device CR50 revision 0
361 07:48:59.099752 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
362 07:48:59.106102 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
363 07:48:59.110070 MRC cache found, size 1948
364 07:48:59.113192 bootmode is set to: 2
365 07:48:59.116361 PRMRR disabled by config.
366 07:48:59.116437 SPD INDEX = 1
367 07:48:59.123272 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
368 07:48:59.126531 CBFS @ c08000 size 3f8000
369 07:48:59.132749 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
370 07:48:59.132839 CBFS: Locating 'spd.bin'
371 07:48:59.136080 CBFS: Found @ offset 5fb80 size 400
372 07:48:59.139313 SPD: module type is LPDDR3
373 07:48:59.142772 SPD: module part is
374 07:48:59.149773 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
375 07:48:59.152594 SPD: device width 4 bits, bus width 8 bits
376 07:48:59.156206 SPD: module size is 4096 MB (per channel)
377 07:48:59.159308 memory slot: 0 configuration done.
378 07:48:59.162560 memory slot: 2 configuration done.
379 07:48:59.214355 CBMEM:
380 07:48:59.217429 IMD: root @ 99fff000 254 entries.
381 07:48:59.220655 IMD: root @ 99ffec00 62 entries.
382 07:48:59.223967 External stage cache:
383 07:48:59.227895 IMD: root @ 9abff000 254 entries.
384 07:48:59.231069 IMD: root @ 9abfec00 62 entries.
385 07:48:59.234289 Chrome EC: clear events_b mask to 0x0000000020004000
386 07:48:59.237601
387 07:48:59.249935 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
388 07:48:59.263164 tlcl_write: response is 0
389 07:48:59.272406 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
390 07:48:59.278421 MRC: TPM MRC hash updated successfully.
391 07:48:59.278507 2 DIMMs found
392 07:48:59.282316 SMM Memory Map
393 07:48:59.285023 SMRAM : 0x9a000000 0x1000000
394 07:48:59.289048 Subregion 0: 0x9a000000 0xa00000
395 07:48:59.291998 Subregion 1: 0x9aa00000 0x200000
396 07:48:59.295447 Subregion 2: 0x9ac00000 0x400000
397 07:48:59.298570 top_of_ram = 0x9a000000
398 07:48:59.301841 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
399 07:48:59.308987 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
400 07:48:59.312204 MTRR Range: Start=ff000000 End=0 (Size 1000000)
401 07:48:59.318504 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
402 07:48:59.321622 CBFS @ c08000 size 3f8000
403 07:48:59.325319 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
404 07:48:59.327940 CBFS: Locating 'fallback/postcar'
405 07:48:59.335171 CBFS: Found @ offset 107000 size 4b44
406 07:48:59.341845 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
407 07:48:59.351358 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
408 07:48:59.354512 Processing 180 relocs. Offset value of 0x97c0c000
409 07:48:59.362576 Accumulated console time in romstage 286 ms
410 07:48:59.362662
411 07:48:59.362731
412 07:48:59.372354 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
413 07:48:59.379013 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
414 07:48:59.382733 CBFS @ c08000 size 3f8000
415 07:48:59.389217 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
416 07:48:59.392421 CBFS: Locating 'fallback/ramstage'
417 07:48:59.395583 CBFS: Found @ offset 43380 size 1b9e8
418 07:48:59.402015 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
419 07:48:59.434552 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
420 07:48:59.437727 Processing 3976 relocs. Offset value of 0x98db0000
421 07:48:59.441050
422 07:48:59.444376 Accumulated console time in postcar 52 ms
423 07:48:59.444464
424 07:48:59.444533
425 07:48:59.454109 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
426 07:48:59.461050 FMAP: area RO_VPD found @ c00000 (16384 bytes)
427 07:48:59.464127 WARNING: RO_VPD is uninitialized or empty.
428 07:48:59.467300 FMAP: area RW_VPD found @ af8000 (8192 bytes)
429 07:48:59.473980 FMAP: area RW_VPD found @ af8000 (8192 bytes)
430 07:48:59.474068 Normal boot.
431 07:48:59.480383 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
432 07:48:59.484393 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
433 07:48:59.487443 CBFS @ c08000 size 3f8000
434 07:48:59.494079 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
435 07:48:59.497120 CBFS: Locating 'cpu_microcode_blob.bin'
436 07:48:59.500575 CBFS: Found @ offset 14700 size 2ec00
437 07:48:59.503609 microcode: sig=0x806ec pf=0x4 revision=0xc9
438 07:48:59.506849 Skip microcode update
439 07:48:59.513617 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
440 07:48:59.513701 CBFS @ c08000 size 3f8000
441 07:48:59.520363 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
442 07:48:59.523627 CBFS: Locating 'fsps.bin'
443 07:48:59.526606 CBFS: Found @ offset d1fc0 size 35000
444 07:48:59.552924 Detected 4 core, 8 thread CPU.
445 07:48:59.556185 Setting up SMI for CPU
446 07:48:59.559174 IED base = 0x9ac00000
447 07:48:59.559258 IED size = 0x00400000
448 07:48:59.562318 Will perform SMM setup.
449 07:48:59.569342 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
450 07:48:59.575836 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
451 07:48:59.579137 Processing 16 relocs. Offset value of 0x00030000
452 07:48:59.582889 Attempting to start 7 APs
453 07:48:59.586220 Waiting for 10ms after sending INIT.
454 07:48:59.602221 Waiting for 1st SIPI to complete...done.
455 07:48:59.602322 AP: slot 4 apic_id 2.
456 07:48:59.605371 AP: slot 1 apic_id 3.
457 07:48:59.609153 AP: slot 5 apic_id 6.
458 07:48:59.609226 AP: slot 2 apic_id 7.
459 07:48:59.612411 AP: slot 6 apic_id 4.
460 07:48:59.615743 AP: slot 7 apic_id 5.
461 07:48:59.618857 Waiting for 2nd SIPI to complete...done.
462 07:48:59.621983 AP: slot 3 apic_id 1.
463 07:48:59.629183 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
464 07:48:59.635336 Processing 13 relocs. Offset value of 0x00038000
465 07:48:59.642071 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
466 07:48:59.645431 Installing SMM handler to 0x9a000000
467 07:48:59.651495 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
468 07:48:59.658782 Processing 658 relocs. Offset value of 0x9a010000
469 07:48:59.665103 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
470 07:48:59.668182 Processing 13 relocs. Offset value of 0x9a008000
471 07:48:59.674781 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
472 07:48:59.681561 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
473 07:48:59.687758 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
474 07:48:59.691631 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
475 07:48:59.698054 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
476 07:48:59.704458 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
477 07:48:59.710753 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
478 07:48:59.717536 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
479 07:48:59.720700 Clearing SMI status registers
480 07:48:59.720801 SMI_STS: PM1
481 07:48:59.724154 PM1_STS: PWRBTN
482 07:48:59.724269 TCO_STS: SECOND_TO
483 07:48:59.727245 New SMBASE 0x9a000000
484 07:48:59.730437 In relocation handler: CPU 0
485 07:48:59.734010 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
486 07:48:59.740572 Writing SMRR. base = 0x9a000006, mask=0xff000800
487 07:48:59.740658 Relocation complete.
488 07:48:59.743717 New SMBASE 0x99fff400
489 07:48:59.747011 In relocation handler: CPU 3
490 07:48:59.750226 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
491 07:48:59.757326 Writing SMRR. base = 0x9a000006, mask=0xff000800
492 07:48:59.757408 Relocation complete.
493 07:48:59.760683 New SMBASE 0x99ffec00
494 07:48:59.763646 In relocation handler: CPU 5
495 07:48:59.767129 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
496 07:48:59.770721 Writing SMRR. base = 0x9a000006, mask=0xff000800
497 07:48:59.774045
498 07:48:59.774131 Relocation complete.
499 07:48:59.777175 New SMBASE 0x99ffe800
500 07:48:59.780480 In relocation handler: CPU 6
501 07:48:59.783746 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
502 07:48:59.786846 Writing SMRR. base = 0x9a000006, mask=0xff000800
503 07:48:59.790008 Relocation complete.
504 07:48:59.793362 New SMBASE 0x99ffe400
505 07:48:59.796419 In relocation handler: CPU 7
506 07:48:59.799922 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
507 07:48:59.803608 Writing SMRR. base = 0x9a000006, mask=0xff000800
508 07:48:59.806497 Relocation complete.
509 07:48:59.809643 New SMBASE 0x99fff800
510 07:48:59.813498 In relocation handler: CPU 2
511 07:48:59.816819 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
512 07:48:59.819921 Writing SMRR. base = 0x9a000006, mask=0xff000800
513 07:48:59.823274 Relocation complete.
514 07:48:59.826373 New SMBASE 0x99fffc00
515 07:48:59.829613 In relocation handler: CPU 1
516 07:48:59.833105 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
517 07:48:59.836395 Writing SMRR. base = 0x9a000006, mask=0xff000800
518 07:48:59.839406 Relocation complete.
519 07:48:59.843398 New SMBASE 0x99fff000
520 07:48:59.846679 In relocation handler: CPU 4
521 07:48:59.849957 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
522 07:48:59.852624 Writing SMRR. base = 0x9a000006, mask=0xff000800
523 07:48:59.856594 Relocation complete.
524 07:48:59.859611 Initializing CPU #0
525 07:48:59.863032 CPU: vendor Intel device 806ec
526 07:48:59.866253 CPU: family 06, model 8e, stepping 0c
527 07:48:59.869172 Clearing out pending MCEs
528 07:48:59.869256 Setting up local APIC...
529 07:48:59.872333 apic_id: 0x00 done.
530 07:48:59.875712 Turbo is available but hidden
531 07:48:59.878700 Turbo is available and visible
532 07:48:59.878794 VMX status: enabled
533 07:48:59.882177
534 07:48:59.885390 IA32_FEATURE_CONTROL status: locked
535 07:48:59.885475 Skip microcode update
536 07:48:59.888464 CPU #0 initialized
537 07:48:59.891936 Initializing CPU #3
538 07:48:59.892054 Initializing CPU #2
539 07:48:59.895619 Initializing CPU #4
540 07:48:59.895717 Initializing CPU #1
541 07:48:59.898923 CPU: vendor Intel device 806ec
542 07:48:59.905524 CPU: family 06, model 8e, stepping 0c
543 07:48:59.905610 CPU: vendor Intel device 806ec
544 07:48:59.908482
545 07:48:59.911871 CPU: family 06, model 8e, stepping 0c
546 07:48:59.911956 Clearing out pending MCEs
547 07:48:59.914938 Clearing out pending MCEs
548 07:48:59.918107 Setting up local APIC...
549 07:48:59.921429 Setting up local APIC...
550 07:48:59.925112 CPU: vendor Intel device 806ec
551 07:48:59.928351 CPU: family 06, model 8e, stepping 0c
552 07:48:59.931366 Clearing out pending MCEs
553 07:48:59.935049 CPU: vendor Intel device 806ec
554 07:48:59.937947 CPU: family 06, model 8e, stepping 0c
555 07:48:59.938037 Initializing CPU #5
556 07:48:59.941159 Clearing out pending MCEs
557 07:48:59.944539 CPU: vendor Intel device 806ec
558 07:48:59.948670 CPU: family 06, model 8e, stepping 0c
559 07:48:59.951605 Setting up local APIC...
560 07:48:59.954755 Setting up local APIC...
561 07:48:59.958228 Clearing out pending MCEs
562 07:48:59.958313 apic_id: 0x01 done.
563 07:48:59.961386 apic_id: 0x02 done.
564 07:48:59.964529 apic_id: 0x03 done.
565 07:48:59.964617 VMX status: enabled
566 07:48:59.967735 VMX status: enabled
567 07:48:59.970935 IA32_FEATURE_CONTROL status: locked
568 07:48:59.974220 IA32_FEATURE_CONTROL status: locked
569 07:48:59.978084 Skip microcode update
570 07:48:59.978167 Skip microcode update
571 07:48:59.980640 CPU #4 initialized
572 07:48:59.984659 CPU #1 initialized
573 07:48:59.984752 apic_id: 0x07 done.
574 07:48:59.987976 Setting up local APIC...
575 07:48:59.991303 Initializing CPU #7
576 07:48:59.991379 Initializing CPU #6
577 07:48:59.994500 CPU: vendor Intel device 806ec
578 07:48:59.997948 CPU: family 06, model 8e, stepping 0c
579 07:49:00.001170 VMX status: enabled
580 07:49:00.004335 apic_id: 0x06 done.
581 07:49:00.007703 IA32_FEATURE_CONTROL status: locked
582 07:49:00.007780 VMX status: enabled
583 07:49:00.010795 Skip microcode update
584 07:49:00.013909 IA32_FEATURE_CONTROL status: locked
585 07:49:00.017732 CPU #2 initialized
586 07:49:00.017832 Skip microcode update
587 07:49:00.020936 CPU: vendor Intel device 806ec
588 07:49:00.024245 CPU: family 06, model 8e, stepping 0c
589 07:49:00.027549 Clearing out pending MCEs
590 07:49:00.030197 Clearing out pending MCEs
591 07:49:00.033939 Setting up local APIC...
592 07:49:00.034014 VMX status: enabled
593 07:49:00.037444 Setting up local APIC...
594 07:49:00.040547 IA32_FEATURE_CONTROL status: locked
595 07:49:00.043595 CPU #5 initialized
596 07:49:00.043667 apic_id: 0x04 done.
597 07:49:00.047109 apic_id: 0x05 done.
598 07:49:00.050376 VMX status: enabled
599 07:49:00.050454 VMX status: enabled
600 07:49:00.053569 IA32_FEATURE_CONTROL status: locked
601 07:49:00.060088 IA32_FEATURE_CONTROL status: locked
602 07:49:00.060165 Skip microcode update
603 07:49:00.063115 Skip microcode update
604 07:49:00.063197 CPU #6 initialized
605 07:49:00.066462
606 07:49:00.066563 CPU #7 initialized
607 07:49:00.070280 Skip microcode update
608 07:49:00.070362 CPU #3 initialized
609 07:49:00.076640 bsp_do_flight_plan done after 454 msecs.
610 07:49:00.080227 CPU: frequency set to 4200 MHz
611 07:49:00.080319 Enabling SMIs.
612 07:49:00.080387 Locking SMM.
613 07:49:00.083545
614 07:49:00.096435 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
615 07:49:00.099741 CBFS @ c08000 size 3f8000
616 07:49:00.106293 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
617 07:49:00.106370 CBFS: Locating 'vbt.bin'
618 07:49:00.112542 CBFS: Found @ offset 5f5c0 size 499
619 07:49:00.115773 Found a VBT of 4608 bytes after decompression
620 07:49:00.296509 Display FSP Version Info HOB
621 07:49:00.299783 Reference Code - CPU = 9.0.1e.30
622 07:49:00.303208 uCode Version = 0.0.0.ca
623 07:49:00.306348 TXT ACM version = ff.ff.ff.ffff
624 07:49:00.309510 Display FSP Version Info HOB
625 07:49:00.312710 Reference Code - ME = 9.0.1e.30
626 07:49:00.315845 MEBx version = 0.0.0.0
627 07:49:00.319732 ME Firmware Version = Consumer SKU
628 07:49:00.322432 Display FSP Version Info HOB
629 07:49:00.325874 Reference Code - CML PCH = 9.0.1e.30
630 07:49:00.329279 PCH-CRID Status = Disabled
631 07:49:00.332399 PCH-CRID Original Value = ff.ff.ff.ffff
632 07:49:00.335617 PCH-CRID New Value = ff.ff.ff.ffff
633 07:49:00.338762 OPROM - RST - RAID = ff.ff.ff.ffff
634 07:49:00.342542 ChipsetInit Base Version = ff.ff.ff.ffff
635 07:49:00.345622 ChipsetInit Oem Version = ff.ff.ff.ffff
636 07:49:00.348682 Display FSP Version Info HOB
637 07:49:00.355114 Reference Code - SA - System Agent = 9.0.1e.30
638 07:49:00.358831 Reference Code - MRC = 0.7.1.6c
639 07:49:00.362191 SA - PCIe Version = 9.0.1e.30
640 07:49:00.362272 SA-CRID Status = Disabled
641 07:49:00.365371 SA-CRID Original Value = 0.0.0.c
642 07:49:00.368539
643 07:49:00.368631 SA-CRID New Value = 0.0.0.c
644 07:49:00.371905 OPROM - VBIOS = ff.ff.ff.ffff
645 07:49:00.375132 RTC Init
646 07:49:00.378199 Set power on after power failure.
647 07:49:00.378279 Disabling Deep S3
648 07:49:00.381455
649 07:49:00.381542 Disabling Deep S3
650 07:49:00.385206 Disabling Deep S4
651 07:49:00.385283 Disabling Deep S4
652 07:49:00.388375 Disabling Deep S5
653 07:49:00.388464 Disabling Deep S5
654 07:49:00.394382 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 190 exit 1
655 07:49:00.398202 Enumerating buses...
656 07:49:00.401483 Show all devs... Before device enumeration.
657 07:49:00.404648 Root Device: enabled 1
658 07:49:00.407921 CPU_CLUSTER: 0: enabled 1
659 07:49:00.407997 DOMAIN: 0000: enabled 1
660 07:49:00.411092 APIC: 00: enabled 1
661 07:49:00.414236 PCI: 00:00.0: enabled 1
662 07:49:00.414311 PCI: 00:02.0: enabled 1
663 07:49:00.417500 PCI: 00:04.0: enabled 0
664 07:49:00.421306 PCI: 00:05.0: enabled 0
665 07:49:00.424632 PCI: 00:12.0: enabled 1
666 07:49:00.424709 PCI: 00:12.5: enabled 0
667 07:49:00.427720 PCI: 00:12.6: enabled 0
668 07:49:00.430877 PCI: 00:14.0: enabled 1
669 07:49:00.434052 PCI: 00:14.1: enabled 0
670 07:49:00.434137 PCI: 00:14.3: enabled 1
671 07:49:00.437208 PCI: 00:14.5: enabled 0
672 07:49:00.440626 PCI: 00:15.0: enabled 1
673 07:49:00.443733 PCI: 00:15.1: enabled 1
674 07:49:00.443814 PCI: 00:15.2: enabled 0
675 07:49:00.446920 PCI: 00:15.3: enabled 0
676 07:49:00.450185 PCI: 00:16.0: enabled 1
677 07:49:00.453860 PCI: 00:16.1: enabled 0
678 07:49:00.453947 PCI: 00:16.2: enabled 0
679 07:49:00.456880 PCI: 00:16.3: enabled 0
680 07:49:00.460124 PCI: 00:16.4: enabled 0
681 07:49:00.463346 PCI: 00:16.5: enabled 0
682 07:49:00.463435 PCI: 00:17.0: enabled 1
683 07:49:00.467277 PCI: 00:19.0: enabled 1
684 07:49:00.470525 PCI: 00:19.1: enabled 0
685 07:49:00.473559 PCI: 00:19.2: enabled 0
686 07:49:00.473636 PCI: 00:1a.0: enabled 0
687 07:49:00.476899 PCI: 00:1c.0: enabled 0
688 07:49:00.480191 PCI: 00:1c.1: enabled 0
689 07:49:00.480286 PCI: 00:1c.2: enabled 0
690 07:49:00.483353
691 07:49:00.483453 PCI: 00:1c.3: enabled 0
692 07:49:00.486594 PCI: 00:1c.4: enabled 0
693 07:49:00.489711 PCI: 00:1c.5: enabled 0
694 07:49:00.489787 PCI: 00:1c.6: enabled 0
695 07:49:00.493130 PCI: 00:1c.7: enabled 0
696 07:49:00.496478 PCI: 00:1d.0: enabled 1
697 07:49:00.499688 PCI: 00:1d.1: enabled 0
698 07:49:00.499780 PCI: 00:1d.2: enabled 0
699 07:49:00.503021 PCI: 00:1d.3: enabled 0
700 07:49:00.506008 PCI: 00:1d.4: enabled 0
701 07:49:00.509239 PCI: 00:1d.5: enabled 1
702 07:49:00.509313 PCI: 00:1e.0: enabled 1
703 07:49:00.512584 PCI: 00:1e.1: enabled 0
704 07:49:00.515746 PCI: 00:1e.2: enabled 1
705 07:49:00.519248 PCI: 00:1e.3: enabled 1
706 07:49:00.519326 PCI: 00:1f.0: enabled 1
707 07:49:00.522749 PCI: 00:1f.1: enabled 1
708 07:49:00.525938 PCI: 00:1f.2: enabled 1
709 07:49:00.529142 PCI: 00:1f.3: enabled 1
710 07:49:00.529219 PCI: 00:1f.4: enabled 1
711 07:49:00.532390 PCI: 00:1f.5: enabled 1
712 07:49:00.535684 PCI: 00:1f.6: enabled 0
713 07:49:00.538984 USB0 port 0: enabled 1
714 07:49:00.539064 I2C: 00:15: enabled 1
715 07:49:00.541939 I2C: 00:5d: enabled 1
716 07:49:00.545906 GENERIC: 0.0: enabled 1
717 07:49:00.545994 I2C: 00:1a: enabled 1
718 07:49:00.549014 I2C: 00:38: enabled 1
719 07:49:00.551708 I2C: 00:39: enabled 1
720 07:49:00.551816 I2C: 00:3a: enabled 1
721 07:49:00.555444 I2C: 00:3b: enabled 1
722 07:49:00.558665 PCI: 00:00.0: enabled 1
723 07:49:00.558744 SPI: 00: enabled 1
724 07:49:00.561738 SPI: 01: enabled 1
725 07:49:00.564766 PNP: 0c09.0: enabled 1
726 07:49:00.564916 USB2 port 0: enabled 1
727 07:49:00.568218
728 07:49:00.568341 USB2 port 1: enabled 1
729 07:49:00.571373 USB2 port 2: enabled 0
730 07:49:00.574591 USB2 port 3: enabled 0
731 07:49:00.574666 USB2 port 5: enabled 0
732 07:49:00.577945 USB2 port 6: enabled 1
733 07:49:00.581204 USB2 port 9: enabled 1
734 07:49:00.581307 USB3 port 0: enabled 1
735 07:49:00.584822 USB3 port 1: enabled 1
736 07:49:00.588011 USB3 port 2: enabled 1
737 07:49:00.591370 USB3 port 3: enabled 1
738 07:49:00.591469 USB3 port 4: enabled 0
739 07:49:00.594472 APIC: 03: enabled 1
740 07:49:00.597786 APIC: 07: enabled 1
741 07:49:00.597862 APIC: 01: enabled 1
742 07:49:00.600989 APIC: 02: enabled 1
743 07:49:00.601061 APIC: 06: enabled 1
744 07:49:00.604219 APIC: 04: enabled 1
745 07:49:00.607433 APIC: 05: enabled 1
746 07:49:00.607513 Compare with tree...
747 07:49:00.610724 Root Device: enabled 1
748 07:49:00.613817 CPU_CLUSTER: 0: enabled 1
749 07:49:00.617352 APIC: 00: enabled 1
750 07:49:00.617423 APIC: 03: enabled 1
751 07:49:00.621088 APIC: 07: enabled 1
752 07:49:00.624083 APIC: 01: enabled 1
753 07:49:00.624200 APIC: 02: enabled 1
754 07:49:00.627199 APIC: 06: enabled 1
755 07:49:00.630475 APIC: 04: enabled 1
756 07:49:00.630554 APIC: 05: enabled 1
757 07:49:00.633532 DOMAIN: 0000: enabled 1
758 07:49:00.636947 PCI: 00:00.0: enabled 1
759 07:49:00.640118 PCI: 00:02.0: enabled 1
760 07:49:00.643858 PCI: 00:04.0: enabled 0
761 07:49:00.643936 PCI: 00:05.0: enabled 0
762 07:49:00.646900 PCI: 00:12.0: enabled 1
763 07:49:00.650004 PCI: 00:12.5: enabled 0
764 07:49:00.653299 PCI: 00:12.6: enabled 0
765 07:49:00.656655 PCI: 00:14.0: enabled 1
766 07:49:00.656770 USB0 port 0: enabled 1
767 07:49:00.659761 USB2 port 0: enabled 1
768 07:49:00.663363 USB2 port 1: enabled 1
769 07:49:00.666475 USB2 port 2: enabled 0
770 07:49:00.669633 USB2 port 3: enabled 0
771 07:49:00.672822 USB2 port 5: enabled 0
772 07:49:00.672909 USB2 port 6: enabled 1
773 07:49:00.676704 USB2 port 9: enabled 1
774 07:49:00.679337 USB3 port 0: enabled 1
775 07:49:00.683245 USB3 port 1: enabled 1
776 07:49:00.686515 USB3 port 2: enabled 1
777 07:49:00.689603 USB3 port 3: enabled 1
778 07:49:00.689689 USB3 port 4: enabled 0
779 07:49:00.692874 PCI: 00:14.1: enabled 0
780 07:49:00.696075 PCI: 00:14.3: enabled 1
781 07:49:00.699435 PCI: 00:14.5: enabled 0
782 07:49:00.702811 PCI: 00:15.0: enabled 1
783 07:49:00.702897 I2C: 00:15: enabled 1
784 07:49:00.706096 PCI: 00:15.1: enabled 1
785 07:49:00.709292 I2C: 00:5d: enabled 1
786 07:49:00.712782 GENERIC: 0.0: enabled 1
787 07:49:00.715800 PCI: 00:15.2: enabled 0
788 07:49:00.715884 PCI: 00:15.3: enabled 0
789 07:49:00.719057 PCI: 00:16.0: enabled 1
790 07:49:00.722240 PCI: 00:16.1: enabled 0
791 07:49:00.725400 PCI: 00:16.2: enabled 0
792 07:49:00.729143 PCI: 00:16.3: enabled 0
793 07:49:00.729230 PCI: 00:16.4: enabled 0
794 07:49:00.732426 PCI: 00:16.5: enabled 0
795 07:49:00.735590 PCI: 00:17.0: enabled 1
796 07:49:00.738869 PCI: 00:19.0: enabled 1
797 07:49:00.738957 I2C: 00:1a: enabled 1
798 07:49:00.742089
799 07:49:00.742166 I2C: 00:38: enabled 1
800 07:49:00.745307 I2C: 00:39: enabled 1
801 07:49:00.748499 I2C: 00:3a: enabled 1
802 07:49:00.752324 I2C: 00:3b: enabled 1
803 07:49:00.752413 PCI: 00:19.1: enabled 0
804 07:49:00.755310 PCI: 00:19.2: enabled 0
805 07:49:00.758669 PCI: 00:1a.0: enabled 0
806 07:49:00.761768 PCI: 00:1c.0: enabled 0
807 07:49:00.764939 PCI: 00:1c.1: enabled 0
808 07:49:00.765025 PCI: 00:1c.2: enabled 0
809 07:49:00.768142 PCI: 00:1c.3: enabled 0
810 07:49:00.771316 PCI: 00:1c.4: enabled 0
811 07:49:00.774762 PCI: 00:1c.5: enabled 0
812 07:49:00.777987 PCI: 00:1c.6: enabled 0
813 07:49:00.778079 PCI: 00:1c.7: enabled 0
814 07:49:00.781334 PCI: 00:1d.0: enabled 1
815 07:49:00.784366 PCI: 00:1d.1: enabled 0
816 07:49:00.788289 PCI: 00:1d.2: enabled 0
817 07:49:00.791430 PCI: 00:1d.3: enabled 0
818 07:49:00.791516 PCI: 00:1d.4: enabled 0
819 07:49:00.794655 PCI: 00:1d.5: enabled 1
820 07:49:00.797453 PCI: 00:00.0: enabled 1
821 07:49:00.800746 PCI: 00:1e.0: enabled 1
822 07:49:00.803918 PCI: 00:1e.1: enabled 0
823 07:49:00.803992 PCI: 00:1e.2: enabled 1
824 07:49:00.807684
825 07:49:00.807762 SPI: 00: enabled 1
826 07:49:00.811075 PCI: 00:1e.3: enabled 1
827 07:49:00.814238 SPI: 01: enabled 1
828 07:49:00.814315 PCI: 00:1f.0: enabled 1
829 07:49:00.817513 PNP: 0c09.0: enabled 1
830 07:49:00.820925 PCI: 00:1f.1: enabled 1
831 07:49:00.824215 PCI: 00:1f.2: enabled 1
832 07:49:00.827176 PCI: 00:1f.3: enabled 1
833 07:49:00.827264 PCI: 00:1f.4: enabled 1
834 07:49:00.830313 PCI: 00:1f.5: enabled 1
835 07:49:00.833436 PCI: 00:1f.6: enabled 0
836 07:49:00.836622 Root Device scanning...
837 07:49:00.840353 scan_static_bus for Root Device
838 07:49:00.843673 CPU_CLUSTER: 0 enabled
839 07:49:00.843755 DOMAIN: 0000 enabled
840 07:49:00.846982 DOMAIN: 0000 scanning...
841 07:49:00.850206 PCI: pci_scan_bus for bus 00
842 07:49:00.853277 PCI: 00:00.0 [8086/0000] ops
843 07:49:00.856568 PCI: 00:00.0 [8086/9b61] enabled
844 07:49:00.860150 PCI: 00:02.0 [8086/0000] bus ops
845 07:49:00.863546 PCI: 00:02.0 [8086/9b41] enabled
846 07:49:00.866531 PCI: 00:04.0 [8086/1903] disabled
847 07:49:00.869598 PCI: 00:08.0 [8086/1911] enabled
848 07:49:00.873424 PCI: 00:12.0 [8086/02f9] enabled
849 07:49:00.876670 PCI: 00:14.0 [8086/0000] bus ops
850 07:49:00.880007 PCI: 00:14.0 [8086/02ed] enabled
851 07:49:00.883290 PCI: 00:14.2 [8086/02ef] enabled
852 07:49:00.886303 PCI: 00:14.3 [8086/02f0] enabled
853 07:49:00.889624 PCI: 00:15.0 [8086/0000] bus ops
854 07:49:00.892510 PCI: 00:15.0 [8086/02e8] enabled
855 07:49:00.895941 PCI: 00:15.1 [8086/0000] bus ops
856 07:49:00.899082 PCI: 00:15.1 [8086/02e9] enabled
857 07:49:00.902320 PCI: 00:16.0 [8086/0000] ops
858 07:49:00.905582 PCI: 00:16.0 [8086/02e0] enabled
859 07:49:00.908858 PCI: 00:17.0 [8086/0000] ops
860 07:49:00.912221 PCI: 00:17.0 [8086/02d3] enabled
861 07:49:00.915450 PCI: 00:19.0 [8086/0000] bus ops
862 07:49:00.919226 PCI: 00:19.0 [8086/02c5] enabled
863 07:49:00.922508 PCI: 00:1d.0 [8086/0000] bus ops
864 07:49:00.925519 PCI: 00:1d.0 [8086/02b0] enabled
865 07:49:00.932024 PCI: Static device PCI: 00:1d.5 not found, disabling it.
866 07:49:00.935224 PCI: 00:1e.0 [8086/0000] ops
867 07:49:00.938458 PCI: 00:1e.0 [8086/02a8] enabled
868 07:49:00.941676 PCI: 00:1e.2 [8086/0000] bus ops
869 07:49:00.944820 PCI: 00:1e.2 [8086/02aa] enabled
870 07:49:00.948151 PCI: 00:1e.3 [8086/0000] bus ops
871 07:49:00.951254 PCI: 00:1e.3 [8086/02ab] enabled
872 07:49:00.954479 PCI: 00:1f.0 [8086/0000] bus ops
873 07:49:00.958419 PCI: 00:1f.0 [8086/0284] enabled
874 07:49:00.964701 PCI: Static device PCI: 00:1f.1 not found, disabling it.
875 07:49:00.968020 PCI: Static device PCI: 00:1f.2 not found, disabling it.
876 07:49:00.971068 PCI: 00:1f.3 [8086/0000] bus ops
877 07:49:00.974308 PCI: 00:1f.3 [8086/02c8] enabled
878 07:49:00.977471 PCI: 00:1f.4 [8086/0000] bus ops
879 07:49:00.981394 PCI: 00:1f.4 [8086/02a3] enabled
880 07:49:00.983993 PCI: 00:1f.5 [8086/0000] bus ops
881 07:49:00.987669 PCI: 00:1f.5 [8086/02a4] enabled
882 07:49:00.990763 PCI: Leftover static devices:
883 07:49:00.994244 PCI: 00:05.0
884 07:49:00.994339 PCI: 00:12.5
885 07:49:00.997183 PCI: 00:12.6
886 07:49:00.997293 PCI: 00:14.1
887 07:49:00.997365 PCI: 00:14.5
888 07:49:01.000414 PCI: 00:15.2
889 07:49:01.000505 PCI: 00:15.3
890 07:49:01.003678 PCI: 00:16.1
891 07:49:01.003758 PCI: 00:16.2
892 07:49:01.003824 PCI: 00:16.3
893 07:49:01.007607 PCI: 00:16.4
894 07:49:01.007697 PCI: 00:16.5
895 07:49:01.010786 PCI: 00:19.1
896 07:49:01.010876 PCI: 00:19.2
897 07:49:01.014004 PCI: 00:1a.0
898 07:49:01.014138 PCI: 00:1c.0
899 07:49:01.014223 PCI: 00:1c.1
900 07:49:01.017124 PCI: 00:1c.2
901 07:49:01.017222 PCI: 00:1c.3
902 07:49:01.020473 PCI: 00:1c.4
903 07:49:01.020561 PCI: 00:1c.5
904 07:49:01.020644 PCI: 00:1c.6
905 07:49:01.023628 PCI: 00:1c.7
906 07:49:01.023724 PCI: 00:1d.1
907 07:49:01.026939 PCI: 00:1d.2
908 07:49:01.027052 PCI: 00:1d.3
909 07:49:01.030209 PCI: 00:1d.4
910 07:49:01.030303 PCI: 00:1d.5
911 07:49:01.030390 PCI: 00:1e.1
912 07:49:01.033331 PCI: 00:1f.1
913 07:49:01.033421 PCI: 00:1f.2
914 07:49:01.036655 PCI: 00:1f.6
915 07:49:01.039781 PCI: Check your devicetree.cb.
916 07:49:01.039930 PCI: 00:02.0 scanning...
917 07:49:01.046283 scan_generic_bus for PCI: 00:02.0
918 07:49:01.049612 scan_generic_bus for PCI: 00:02.0 done
919 07:49:01.052694 scan_bus: scanning of bus PCI: 00:02.0 took 10190 usecs
920 07:49:01.056026 PCI: 00:14.0 scanning...
921 07:49:01.059983 scan_static_bus for PCI: 00:14.0
922 07:49:01.063011 USB0 port 0 enabled
923 07:49:01.066272 USB0 port 0 scanning...
924 07:49:01.069174 scan_static_bus for USB0 port 0
925 07:49:01.069272 USB2 port 0 enabled
926 07:49:01.072448 USB2 port 1 enabled
927 07:49:01.075568 USB2 port 2 disabled
928 07:49:01.075656 USB2 port 3 disabled
929 07:49:01.078899 USB2 port 5 disabled
930 07:49:01.082109 USB2 port 6 enabled
931 07:49:01.082201 USB2 port 9 enabled
932 07:49:01.086055 USB3 port 0 enabled
933 07:49:01.086140 USB3 port 1 enabled
934 07:49:01.088576 USB3 port 2 enabled
935 07:49:01.092375 USB3 port 3 enabled
936 07:49:01.092463 USB3 port 4 disabled
937 07:49:01.095454 USB2 port 0 scanning...
938 07:49:01.098839 scan_static_bus for USB2 port 0
939 07:49:01.102105 scan_static_bus for USB2 port 0 done
940 07:49:01.108641 scan_bus: scanning of bus USB2 port 0 took 9701 usecs
941 07:49:01.111955 USB2 port 1 scanning...
942 07:49:01.115278 scan_static_bus for USB2 port 1
943 07:49:01.118538 scan_static_bus for USB2 port 1 done
944 07:49:01.124949 scan_bus: scanning of bus USB2 port 1 took 9708 usecs
945 07:49:01.125049 USB2 port 6 scanning...
946 07:49:01.128136 scan_static_bus for USB2 port 6
947 07:49:01.131325 scan_static_bus for USB2 port 6 done
948 07:49:01.134522
949 07:49:01.137887 scan_bus: scanning of bus USB2 port 6 took 9703 usecs
950 07:49:01.141034 USB2 port 9 scanning...
951 07:49:01.144336 scan_static_bus for USB2 port 9
952 07:49:01.147947 scan_static_bus for USB2 port 9 done
953 07:49:01.154571 scan_bus: scanning of bus USB2 port 9 took 9710 usecs
954 07:49:01.154686 USB3 port 0 scanning...
955 07:49:01.157761 scan_static_bus for USB3 port 0
956 07:49:01.164290 scan_static_bus for USB3 port 0 done
957 07:49:01.168261 scan_bus: scanning of bus USB3 port 0 took 9694 usecs
958 07:49:01.171349 USB3 port 1 scanning...
959 07:49:01.174426 scan_static_bus for USB3 port 1
960 07:49:01.177715 scan_static_bus for USB3 port 1 done
961 07:49:01.184250 scan_bus: scanning of bus USB3 port 1 took 9702 usecs
962 07:49:01.187519 USB3 port 2 scanning...
963 07:49:01.190791 scan_static_bus for USB3 port 2
964 07:49:01.193919 scan_static_bus for USB3 port 2 done
965 07:49:01.197179 scan_bus: scanning of bus USB3 port 2 took 9707 usecs
966 07:49:01.200259 USB3 port 3 scanning...
967 07:49:01.203544 scan_static_bus for USB3 port 3
968 07:49:01.206811 scan_static_bus for USB3 port 3 done
969 07:49:01.213518 scan_bus: scanning of bus USB3 port 3 took 9703 usecs
970 07:49:01.217186 scan_static_bus for USB0 port 0 done
971 07:49:01.223050 scan_bus: scanning of bus USB0 port 0 took 155445 usecs
972 07:49:01.226353 scan_static_bus for PCI: 00:14.0 done
973 07:49:01.233453 scan_bus: scanning of bus PCI: 00:14.0 took 173083 usecs
974 07:49:01.233557 PCI: 00:15.0 scanning...
975 07:49:01.239701 scan_generic_bus for PCI: 00:15.0
976 07:49:01.242952 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
977 07:49:01.246722 scan_generic_bus for PCI: 00:15.0 done
978 07:49:01.253111 scan_bus: scanning of bus PCI: 00:15.0 took 14306 usecs
979 07:49:01.253209 PCI: 00:15.1 scanning...
980 07:49:01.259831 scan_generic_bus for PCI: 00:15.1
981 07:49:01.262918 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
982 07:49:01.266303 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
983 07:49:01.269643 scan_generic_bus for PCI: 00:15.1 done
984 07:49:01.276011 scan_bus: scanning of bus PCI: 00:15.1 took 18660 usecs
985 07:49:01.279223 PCI: 00:19.0 scanning...
986 07:49:01.282687 scan_generic_bus for PCI: 00:19.0
987 07:49:01.285664 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
988 07:49:01.289541 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
989 07:49:01.295516 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
990 07:49:01.299403 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
991 07:49:01.302555 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
992 07:49:01.305731 scan_generic_bus for PCI: 00:19.0 done
993 07:49:01.312442 scan_bus: scanning of bus PCI: 00:19.0 took 30754 usecs
994 07:49:01.315713 PCI: 00:1d.0 scanning...
995 07:49:01.318871 do_pci_scan_bridge for PCI: 00:1d.0
996 07:49:01.322092 PCI: pci_scan_bus for bus 01
997 07:49:01.325503 PCI: 01:00.0 [1c5c/1327] enabled
998 07:49:01.328617 Enabling Common Clock Configuration
999 07:49:01.331873 L1 Sub-State supported from root port 29
1000 07:49:01.335028 L1 Sub-State Support = 0xf
1001 07:49:01.338381 CommonModeRestoreTime = 0x28
1002 07:49:01.341512 Power On Value = 0x16, Power On Scale = 0x0
1003 07:49:01.344701 ASPM: Enabled L1
1004 07:49:01.351213 scan_bus: scanning of bus PCI: 00:1d.0 took 32783 usecs
1005 07:49:01.351330 PCI: 00:1e.2 scanning...
1006 07:49:01.355219 scan_generic_bus for PCI: 00:1e.2
1007 07:49:01.358235
1008 07:49:01.361635 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1009 07:49:01.364662 scan_generic_bus for PCI: 00:1e.2 done
1010 07:49:01.371688 scan_bus: scanning of bus PCI: 00:1e.2 took 14011 usecs
1011 07:49:01.371782 PCI: 00:1e.3 scanning...
1012 07:49:01.374880 scan_generic_bus for PCI: 00:1e.3
1013 07:49:01.380980 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1014 07:49:01.384596 scan_generic_bus for PCI: 00:1e.3 done
1015 07:49:01.387639 scan_bus: scanning of bus PCI: 00:1e.3 took 14010 usecs
1016 07:49:01.390840 PCI: 00:1f.0 scanning...
1017 07:49:01.394129 scan_static_bus for PCI: 00:1f.0
1018 07:49:01.397241 PNP: 0c09.0 enabled
1019 07:49:01.400572 scan_static_bus for PCI: 00:1f.0 done
1020 07:49:01.407684 scan_bus: scanning of bus PCI: 00:1f.0 took 12046 usecs
1021 07:49:01.411087 PCI: 00:1f.3 scanning...
1022 07:49:01.413703 scan_bus: scanning of bus PCI: 00:1f.3 took 2861 usecs
1023 07:49:01.417567 PCI: 00:1f.4 scanning...
1024 07:49:01.420254 scan_generic_bus for PCI: 00:1f.4
1025 07:49:01.423663 scan_generic_bus for PCI: 00:1f.4 done
1026 07:49:01.430130 scan_bus: scanning of bus PCI: 00:1f.4 took 10190 usecs
1027 07:49:01.433453 PCI: 00:1f.5 scanning...
1028 07:49:01.436647 scan_generic_bus for PCI: 00:1f.5
1029 07:49:01.439896 scan_generic_bus for PCI: 00:1f.5 done
1030 07:49:01.446461 scan_bus: scanning of bus PCI: 00:1f.5 took 10198 usecs
1031 07:49:01.453138 scan_bus: scanning of bus DOMAIN: 0000 took 605349 usecs
1032 07:49:01.456953 scan_static_bus for Root Device done
1033 07:49:01.463300 scan_bus: scanning of bus Root Device took 625228 usecs
1034 07:49:01.463385 done
1035 07:49:01.466355 Chrome EC: UHEPI supported
1036 07:49:01.473082 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1037 07:49:01.476447 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1038 07:49:01.482298 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1039 07:49:01.489857 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1040 07:49:01.493039 SPI flash protection: WPSW=0 SRP0=1
1041 07:49:01.499369 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1042 07:49:01.502600 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1043 07:49:01.505936 found VGA at PCI: 00:02.0
1044 07:49:01.509782 Setting up VGA for PCI: 00:02.0
1045 07:49:01.516191 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1046 07:49:01.519477 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1047 07:49:01.522808 Allocating resources...
1048 07:49:01.526048 Reading resources...
1049 07:49:01.529201 Root Device read_resources bus 0 link: 0
1050 07:49:01.532633 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1051 07:49:01.538972 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1052 07:49:01.542282 DOMAIN: 0000 read_resources bus 0 link: 0
1053 07:49:01.550053 PCI: 00:14.0 read_resources bus 0 link: 0
1054 07:49:01.553248 USB0 port 0 read_resources bus 0 link: 0
1055 07:49:01.561719 USB0 port 0 read_resources bus 0 link: 0 done
1056 07:49:01.564937 PCI: 00:14.0 read_resources bus 0 link: 0 done
1057 07:49:01.571929 PCI: 00:15.0 read_resources bus 1 link: 0
1058 07:49:01.575770 PCI: 00:15.0 read_resources bus 1 link: 0 done
1059 07:49:01.582044 PCI: 00:15.1 read_resources bus 2 link: 0
1060 07:49:01.585087 PCI: 00:15.1 read_resources bus 2 link: 0 done
1061 07:49:01.592708 PCI: 00:19.0 read_resources bus 3 link: 0
1062 07:49:01.599288 PCI: 00:19.0 read_resources bus 3 link: 0 done
1063 07:49:01.602450 PCI: 00:1d.0 read_resources bus 1 link: 0
1064 07:49:01.608897 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1065 07:49:01.612648 PCI: 00:1e.2 read_resources bus 4 link: 0
1066 07:49:01.619145 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1067 07:49:01.622430 PCI: 00:1e.3 read_resources bus 5 link: 0
1068 07:49:01.628943 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1069 07:49:01.631791 PCI: 00:1f.0 read_resources bus 0 link: 0
1070 07:49:01.638698 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1071 07:49:01.645243 DOMAIN: 0000 read_resources bus 0 link: 0 done
1072 07:49:01.648576 Root Device read_resources bus 0 link: 0 done
1073 07:49:01.651843 Done reading resources.
1074 07:49:01.658825 Show resources in subtree (Root Device)...After reading.
1075 07:49:01.661532 Root Device child on link 0 CPU_CLUSTER: 0
1076 07:49:01.665245 CPU_CLUSTER: 0 child on link 0 APIC: 00
1077 07:49:01.668462 APIC: 00
1078 07:49:01.668547 APIC: 03
1079 07:49:01.668613 APIC: 07
1080 07:49:01.671756 APIC: 01
1081 07:49:01.671840 APIC: 02
1082 07:49:01.674848 APIC: 06
1083 07:49:01.674939 APIC: 04
1084 07:49:01.675004 APIC: 05
1085 07:49:01.681216 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1086 07:49:01.691620 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1087 07:49:01.744252 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1088 07:49:01.744374 PCI: 00:00.0
1089 07:49:01.744675 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1090 07:49:01.744780 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1091 07:49:01.745099 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1092 07:49:01.745408 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1093 07:49:01.794141 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1094 07:49:01.794472 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1095 07:49:01.795198 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1096 07:49:01.795786 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1097 07:49:01.797245 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1098 07:49:01.797881 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1099 07:49:01.804966 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1100 07:49:01.814734 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1101 07:49:01.824551 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1102 07:49:01.834434 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1103 07:49:01.840919 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1104 07:49:01.850438 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1105 07:49:01.853730 PCI: 00:02.0
1106 07:49:01.864166 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1107 07:49:01.873712 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1108 07:49:01.883351 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1109 07:49:01.883511 PCI: 00:04.0
1110 07:49:01.886475 PCI: 00:08.0
1111 07:49:01.896518 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1112 07:49:01.896655 PCI: 00:12.0
1113 07:49:01.906230 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1114 07:49:01.909411 PCI: 00:14.0 child on link 0 USB0 port 0
1115 07:49:01.919406 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1116 07:49:01.922514
1117 07:49:01.925785 USB0 port 0 child on link 0 USB2 port 0
1118 07:49:01.925882 USB2 port 0
1119 07:49:01.928985 USB2 port 1
1120 07:49:01.929107 USB2 port 2
1121 07:49:01.932270 USB2 port 3
1122 07:49:01.935550 USB2 port 5
1123 07:49:01.935684 USB2 port 6
1124 07:49:01.938697 USB2 port 9
1125 07:49:01.938820 USB3 port 0
1126 07:49:01.942631 USB3 port 1
1127 07:49:01.942755 USB3 port 2
1128 07:49:01.945172 USB3 port 3
1129 07:49:01.945249 USB3 port 4
1130 07:49:01.948464 PCI: 00:14.2
1131 07:49:01.958715 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1132 07:49:01.968547 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1133 07:49:01.968676 PCI: 00:14.3
1134 07:49:01.978263 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1135 07:49:01.984406 PCI: 00:15.0 child on link 0 I2C: 01:15
1136 07:49:01.994760 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1137 07:49:01.994885 I2C: 01:15
1138 07:49:02.000628 PCI: 00:15.1 child on link 0 I2C: 02:5d
1139 07:49:02.010736 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1140 07:49:02.010831 I2C: 02:5d
1141 07:49:02.013852 GENERIC: 0.0
1142 07:49:02.013940 PCI: 00:16.0
1143 07:49:02.023940 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1144 07:49:02.027329 PCI: 00:17.0
1145 07:49:02.033748 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1146 07:49:02.037039
1147 07:49:02.043580 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1148 07:49:02.053234 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1149 07:49:02.059722 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1150 07:49:02.069585 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1151 07:49:02.079144 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1152 07:49:02.082354 PCI: 00:19.0 child on link 0 I2C: 03:1a
1153 07:49:02.092434 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1154 07:49:02.092524 I2C: 03:1a
1155 07:49:02.095414 I2C: 03:38
1156 07:49:02.095499 I2C: 03:39
1157 07:49:02.098785 I2C: 03:3a
1158 07:49:02.098870 I2C: 03:3b
1159 07:49:02.105253 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1160 07:49:02.112353 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1161 07:49:02.121936 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1162 07:49:02.131926 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1163 07:49:02.135123 PCI: 01:00.0
1164 07:49:02.144679 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1165 07:49:02.144790 PCI: 00:1e.0
1166 07:49:02.157681 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1167 07:49:02.167271 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1168 07:49:02.170657 PCI: 00:1e.2 child on link 0 SPI: 00
1169 07:49:02.180337 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1170 07:49:02.180435 SPI: 00
1171 07:49:02.186892 PCI: 00:1e.3 child on link 0 SPI: 01
1172 07:49:02.196720 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1173 07:49:02.196845 SPI: 01
1174 07:49:02.199847 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1175 07:49:02.209942 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1176 07:49:02.219795 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1177 07:49:02.219879 PNP: 0c09.0
1178 07:49:02.229231 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1179 07:49:02.229328 PCI: 00:1f.3
1180 07:49:02.232996
1181 07:49:02.239598 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1182 07:49:02.242364
1183 07:49:02.252507 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1184 07:49:02.252606 PCI: 00:1f.4
1185 07:49:02.262221 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1186 07:49:02.271879 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1187 07:49:02.271985 PCI: 00:1f.5
1188 07:49:02.281774 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1189 07:49:02.288168 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1190 07:49:02.294426 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1191 07:49:02.301260 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1192 07:49:02.304584 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1193 07:49:02.307866 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1194 07:49:02.311691 PCI: 00:17.0 18 * [0x60 - 0x67] io
1195 07:49:02.318049 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1196 07:49:02.324016 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1197 07:49:02.331166 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1198 07:49:02.337653 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1199 07:49:02.346823 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1200 07:49:02.353908 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1201 07:49:02.357237 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1202 07:49:02.363791 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1203 07:49:02.370153 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1204 07:49:02.373435 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1205 07:49:02.379787 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1206 07:49:02.383088 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1207 07:49:02.389885 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1208 07:49:02.393202 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1209 07:49:02.399429 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1210 07:49:02.402874 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1211 07:49:02.409611 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1212 07:49:02.413091 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1213 07:49:02.419238 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1214 07:49:02.422470 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1215 07:49:02.425719 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1216 07:49:02.429063
1217 07:49:02.432226 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1218 07:49:02.435571 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1219 07:49:02.438977
1220 07:49:02.442180 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1221 07:49:02.445442 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1222 07:49:02.452015 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1223 07:49:02.455470 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1224 07:49:02.462168 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1225 07:49:02.464838 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1226 07:49:02.471340 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1227 07:49:02.474808 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1228 07:49:02.484676 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1229 07:49:02.488090 avoid_fixed_resources: DOMAIN: 0000
1230 07:49:02.494557 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1231 07:49:02.501210 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1232 07:49:02.507769 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1233 07:49:02.514416 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1234 07:49:02.524084 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1235 07:49:02.530527 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1236 07:49:02.537346 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1237 07:49:02.546567 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1238 07:49:02.553966 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1239 07:49:02.559844 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1240 07:49:02.569779 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1241 07:49:02.576327 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1242 07:49:02.576414 Setting resources...
1243 07:49:02.583507 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1244 07:49:02.589590 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1245 07:49:02.593495 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1246 07:49:02.596257 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1247 07:49:02.599329 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1248 07:49:02.606535 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1249 07:49:02.612621 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1250 07:49:02.619849 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1251 07:49:02.626308 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1252 07:49:02.632853 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1253 07:49:02.636072 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1254 07:49:02.642897 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1255 07:49:02.646197 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1256 07:49:02.652060 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1257 07:49:02.655528 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1258 07:49:02.662104 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1259 07:49:02.665559 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1260 07:49:02.672260 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1261 07:49:02.675340 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1262 07:49:02.682007 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1263 07:49:02.685317 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1264 07:49:02.691791 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1265 07:49:02.695106 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1266 07:49:02.701350 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1267 07:49:02.704889 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1268 07:49:02.710853 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1269 07:49:02.714229 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1270 07:49:02.720838 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1271 07:49:02.724099 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1272 07:49:02.730521 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1273 07:49:02.733838 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1274 07:49:02.737126 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1275 07:49:02.740474
1276 07:49:02.747172 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1277 07:49:02.753680 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1278 07:49:02.760252 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1279 07:49:02.769895 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1280 07:49:02.773160 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1281 07:49:02.779652 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1282 07:49:02.786210 Root Device assign_resources, bus 0 link: 0
1283 07:49:02.789588 DOMAIN: 0000 assign_resources, bus 0 link: 0
1284 07:49:02.799152 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1285 07:49:02.806241 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1286 07:49:02.816230 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1287 07:49:02.822452 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1288 07:49:02.832046 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1289 07:49:02.838932 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1290 07:49:02.845604 PCI: 00:14.0 assign_resources, bus 0 link: 0
1291 07:49:02.848891 PCI: 00:14.0 assign_resources, bus 0 link: 0
1292 07:49:02.858351 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1293 07:49:02.864916 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1294 07:49:02.874763 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1295 07:49:02.881346 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1296 07:49:02.884556 PCI: 00:15.0 assign_resources, bus 1 link: 0
1297 07:49:02.891122 PCI: 00:15.0 assign_resources, bus 1 link: 0
1298 07:49:02.897993 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1299 07:49:02.904506 PCI: 00:15.1 assign_resources, bus 2 link: 0
1300 07:49:02.907780 PCI: 00:15.1 assign_resources, bus 2 link: 0
1301 07:49:02.917408 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1302 07:49:02.924089 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1303 07:49:02.933578 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1304 07:49:02.940059 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1305 07:49:02.946600 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1306 07:49:02.956399 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1307 07:49:02.963163 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1308 07:49:02.972990 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1309 07:49:02.976293 PCI: 00:19.0 assign_resources, bus 3 link: 0
1310 07:49:02.979623 PCI: 00:19.0 assign_resources, bus 3 link: 0
1311 07:49:02.989672 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1312 07:49:02.999350 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1313 07:49:03.006065 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1314 07:49:03.012225 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1315 07:49:03.019093 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1316 07:49:03.025495 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1317 07:49:03.032033 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1318 07:49:03.041792 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1319 07:49:03.045043 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1320 07:49:03.051828 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1321 07:49:03.058308 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1322 07:49:03.064257 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1323 07:49:03.067505 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1324 07:49:03.070982 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1325 07:49:03.078455 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1326 07:49:03.081529 LPC: Trying to open IO window from 800 size 1ff
1327 07:49:03.091093 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1328 07:49:03.098127 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1329 07:49:03.107404 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1330 07:49:03.113973 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1331 07:49:03.120914 DOMAIN: 0000 assign_resources, bus 0 link: 0
1332 07:49:03.124206 Root Device assign_resources, bus 0 link: 0
1333 07:49:03.127675 Done setting resources.
1334 07:49:03.134058 Show resources in subtree (Root Device)...After assigning values.
1335 07:49:03.137146 Root Device child on link 0 CPU_CLUSTER: 0
1336 07:49:03.143715 CPU_CLUSTER: 0 child on link 0 APIC: 00
1337 07:49:03.143843 APIC: 00
1338 07:49:03.143915 APIC: 03
1339 07:49:03.147031 APIC: 07
1340 07:49:03.147109 APIC: 01
1341 07:49:03.147175 APIC: 02
1342 07:49:03.150481 APIC: 06
1343 07:49:03.150555 APIC: 04
1344 07:49:03.153862 APIC: 05
1345 07:49:03.156611 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1346 07:49:03.166504 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1347 07:49:03.176271 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1348 07:49:03.179584 PCI: 00:00.0
1349 07:49:03.189310 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1350 07:49:03.199128 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1351 07:49:03.205750 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1352 07:49:03.215634 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1353 07:49:03.225521 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1354 07:49:03.235603 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1355 07:49:03.245243 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1356 07:49:03.255201 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1357 07:49:03.264859 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1358 07:49:03.271604 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1359 07:49:03.281364 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1360 07:49:03.291187 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1361 07:49:03.301253 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1362 07:49:03.310834 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1363 07:49:03.320448 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1364 07:49:03.330660 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1365 07:49:03.330748 PCI: 00:02.0
1366 07:49:03.340355 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1367 07:49:03.353556 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1368 07:49:03.359508 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1369 07:49:03.362854 PCI: 00:04.0
1370 07:49:03.362938 PCI: 00:08.0
1371 07:49:03.376049 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1372 07:49:03.376139 PCI: 00:12.0
1373 07:49:03.386127 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1374 07:49:03.392613 PCI: 00:14.0 child on link 0 USB0 port 0
1375 07:49:03.402112 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1376 07:49:03.405458 USB0 port 0 child on link 0 USB2 port 0
1377 07:49:03.408661 USB2 port 0
1378 07:49:03.408780 USB2 port 1
1379 07:49:03.412067 USB2 port 2
1380 07:49:03.412153 USB2 port 3
1381 07:49:03.415450 USB2 port 5
1382 07:49:03.415534 USB2 port 6
1383 07:49:03.418729 USB2 port 9
1384 07:49:03.418812 USB3 port 0
1385 07:49:03.421844 USB3 port 1
1386 07:49:03.425401 USB3 port 2
1387 07:49:03.425511 USB3 port 3
1388 07:49:03.428465 USB3 port 4
1389 07:49:03.428549 PCI: 00:14.2
1390 07:49:03.438271 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1391 07:49:03.448261 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1392 07:49:03.451643 PCI: 00:14.3
1393 07:49:03.460981 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1394 07:49:03.464365 PCI: 00:15.0 child on link 0 I2C: 01:15
1395 07:49:03.477579 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1396 07:49:03.477668 I2C: 01:15
1397 07:49:03.480929 PCI: 00:15.1 child on link 0 I2C: 02:5d
1398 07:49:03.493397 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1399 07:49:03.493483 I2C: 02:5d
1400 07:49:03.496669 GENERIC: 0.0
1401 07:49:03.496788 PCI: 00:16.0
1402 07:49:03.506467 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1403 07:49:03.509758 PCI: 00:17.0
1404 07:49:03.519603 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1405 07:49:03.529524 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1406 07:49:03.539482 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1407 07:49:03.545670 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1408 07:49:03.555365 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1409 07:49:03.565546 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1410 07:49:03.572216 PCI: 00:19.0 child on link 0 I2C: 03:1a
1411 07:49:03.582073 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1412 07:49:03.582163 I2C: 03:1a
1413 07:49:03.585198 I2C: 03:38
1414 07:49:03.585284 I2C: 03:39
1415 07:49:03.588617 I2C: 03:3a
1416 07:49:03.588702 I2C: 03:3b
1417 07:49:03.595131 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1418 07:49:03.601844 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1419 07:49:03.611749 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1420 07:49:03.624906 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1421 07:49:03.624996 PCI: 01:00.0
1422 07:49:03.634530 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1423 07:49:03.638069 PCI: 00:1e.0
1424 07:49:03.647979 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1425 07:49:03.657926 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1426 07:49:03.663926 PCI: 00:1e.2 child on link 0 SPI: 00
1427 07:49:03.673825 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1428 07:49:03.673914 SPI: 00
1429 07:49:03.677068 PCI: 00:1e.3 child on link 0 SPI: 01
1430 07:49:03.687084 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1431 07:49:03.690339 SPI: 01
1432 07:49:03.693561 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1433 07:49:03.703647 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1434 07:49:03.713013 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1435 07:49:03.713099 PNP: 0c09.0
1436 07:49:03.723047 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1437 07:49:03.723133 PCI: 00:1f.3
1438 07:49:03.732539 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1439 07:49:03.746326 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1440 07:49:03.746465 PCI: 00:1f.4
1441 07:49:03.755797 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1442 07:49:03.765349 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1443 07:49:03.765445 PCI: 00:1f.5
1444 07:49:03.778573 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1445 07:49:03.778664 Done allocating resources.
1446 07:49:03.785252 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1447 07:49:03.788654 Enabling resources...
1448 07:49:03.792066 PCI: 00:00.0 subsystem <- 8086/9b61
1449 07:49:03.795281 PCI: 00:00.0 cmd <- 06
1450 07:49:03.798692 PCI: 00:02.0 subsystem <- 8086/9b41
1451 07:49:03.801831 PCI: 00:02.0 cmd <- 03
1452 07:49:03.804548 PCI: 00:08.0 cmd <- 06
1453 07:49:03.807955 PCI: 00:12.0 subsystem <- 8086/02f9
1454 07:49:03.811176 PCI: 00:12.0 cmd <- 02
1455 07:49:03.814419 PCI: 00:14.0 subsystem <- 8086/02ed
1456 07:49:03.817745 PCI: 00:14.0 cmd <- 02
1457 07:49:03.817828 PCI: 00:14.2 cmd <- 02
1458 07:49:03.824613 PCI: 00:14.3 subsystem <- 8086/02f0
1459 07:49:03.824697 PCI: 00:14.3 cmd <- 02
1460 07:49:03.827697 PCI: 00:15.0 subsystem <- 8086/02e8
1461 07:49:03.830896
1462 07:49:03.830981 PCI: 00:15.0 cmd <- 02
1463 07:49:03.834267 PCI: 00:15.1 subsystem <- 8086/02e9
1464 07:49:03.837568 PCI: 00:15.1 cmd <- 02
1465 07:49:03.841061 PCI: 00:16.0 subsystem <- 8086/02e0
1466 07:49:03.844328 PCI: 00:16.0 cmd <- 02
1467 07:49:03.847460 PCI: 00:17.0 subsystem <- 8086/02d3
1468 07:49:03.850965 PCI: 00:17.0 cmd <- 03
1469 07:49:03.854105 PCI: 00:19.0 subsystem <- 8086/02c5
1470 07:49:03.857468 PCI: 00:19.0 cmd <- 02
1471 07:49:03.860251 PCI: 00:1d.0 bridge ctrl <- 0013
1472 07:49:03.863607 PCI: 00:1d.0 subsystem <- 8086/02b0
1473 07:49:03.867063 PCI: 00:1d.0 cmd <- 06
1474 07:49:03.870149 PCI: 00:1e.0 subsystem <- 8086/02a8
1475 07:49:03.873571 PCI: 00:1e.0 cmd <- 06
1476 07:49:03.877084 PCI: 00:1e.2 subsystem <- 8086/02aa
1477 07:49:03.880177 PCI: 00:1e.2 cmd <- 06
1478 07:49:03.883635 PCI: 00:1e.3 subsystem <- 8086/02ab
1479 07:49:03.886351 PCI: 00:1e.3 cmd <- 02
1480 07:49:03.889704 PCI: 00:1f.0 subsystem <- 8086/0284
1481 07:49:03.889800 PCI: 00:1f.0 cmd <- 407
1482 07:49:03.896699 PCI: 00:1f.3 subsystem <- 8086/02c8
1483 07:49:03.896820 PCI: 00:1f.3 cmd <- 02
1484 07:49:03.900119 PCI: 00:1f.4 subsystem <- 8086/02a3
1485 07:49:03.903337 PCI: 00:1f.4 cmd <- 03
1486 07:49:03.906842 PCI: 00:1f.5 subsystem <- 8086/02a4
1487 07:49:03.910277 PCI: 00:1f.5 cmd <- 406
1488 07:49:03.919594 PCI: 01:00.0 cmd <- 02
1489 07:49:03.924724 done.
1490 07:49:03.936480 ME: Version: 14.0.39.1367
1491 07:49:03.943080 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 11
1492 07:49:03.946482 Initializing devices...
1493 07:49:03.946585 Root Device init ...
1494 07:49:03.952969 Chrome EC: Set SMI mask to 0x0000000000000000
1495 07:49:03.958841 Chrome EC: clear events_b mask to 0x0000000000000000
1496 07:49:03.962167 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1497 07:49:03.968909 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1498 07:49:03.975459 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1499 07:49:03.978955 Chrome EC: Set WAKE mask to 0x0000000000000000
1500 07:49:03.985593 Root Device init finished in 35149 usecs
1501 07:49:03.988683 CPU_CLUSTER: 0 init ...
1502 07:49:03.991436 CPU_CLUSTER: 0 init finished in 2447 usecs
1503 07:49:03.996884 PCI: 00:00.0 init ...
1504 07:49:04.000227 CPU TDP: 15 Watts
1505 07:49:04.003451 CPU PL2 = 64 Watts
1506 07:49:04.006882 PCI: 00:00.0 init finished in 7077 usecs
1507 07:49:04.010166 PCI: 00:02.0 init ...
1508 07:49:04.013411 PCI: 00:02.0 init finished in 2253 usecs
1509 07:49:04.016722 PCI: 00:08.0 init ...
1510 07:49:04.020945 PCI: 00:08.0 init finished in 2251 usecs
1511 07:49:04.023536 PCI: 00:12.0 init ...
1512 07:49:04.026837 PCI: 00:12.0 init finished in 2252 usecs
1513 07:49:04.030090 PCI: 00:14.0 init ...
1514 07:49:04.033180 PCI: 00:14.0 init finished in 2242 usecs
1515 07:49:04.036482 PCI: 00:14.2 init ...
1516 07:49:04.039835 PCI: 00:14.2 init finished in 2251 usecs
1517 07:49:04.043386 PCI: 00:14.3 init ...
1518 07:49:04.046191 PCI: 00:14.3 init finished in 2270 usecs
1519 07:49:04.049305 PCI: 00:15.0 init ...
1520 07:49:04.052603 DW I2C bus 0 at 0xd121f000 (400 KHz)
1521 07:49:04.059009 PCI: 00:15.0 init finished in 5975 usecs
1522 07:49:04.059095 PCI: 00:15.1 init ...
1523 07:49:04.062585 DW I2C bus 1 at 0xd1220000 (400 KHz)
1524 07:49:04.065873
1525 07:49:04.069197 PCI: 00:15.1 init finished in 5966 usecs
1526 07:49:04.072589 PCI: 00:16.0 init ...
1527 07:49:04.075986 PCI: 00:16.0 init finished in 2252 usecs
1528 07:49:04.078605 PCI: 00:19.0 init ...
1529 07:49:04.082021 DW I2C bus 4 at 0xd1222000 (400 KHz)
1530 07:49:04.085251 PCI: 00:19.0 init finished in 5975 usecs
1531 07:49:04.088615 PCI: 00:1d.0 init ...
1532 07:49:04.091977 Initializing PCH PCIe bridge.
1533 07:49:04.095602 PCI: 00:1d.0 init finished in 5282 usecs
1534 07:49:04.098892 PCI: 00:1f.0 init ...
1535 07:49:04.102160 IOAPIC: Initializing IOAPIC at 0xfec00000
1536 07:49:04.108896 IOAPIC: Bootstrap Processor Local APIC = 0x00
1537 07:49:04.108983 IOAPIC: ID = 0x02
1538 07:49:04.112170 IOAPIC: Dumping registers
1539 07:49:04.115618 reg 0x0000: 0x02000000
1540 07:49:04.118938 reg 0x0001: 0x00770020
1541 07:49:04.122151 reg 0x0002: 0x00000000
1542 07:49:04.124947 PCI: 00:1f.0 init finished in 23536 usecs
1543 07:49:04.128233 PCI: 00:1f.4 init ...
1544 07:49:04.131558 PCI: 00:1f.4 init finished in 2261 usecs
1545 07:49:04.142969 PCI: 01:00.0 init ...
1546 07:49:04.146207 PCI: 01:00.0 init finished in 2251 usecs
1547 07:49:04.150859 PNP: 0c09.0 init ...
1548 07:49:04.154147 Google Chrome EC uptime: 11.092 seconds
1549 07:49:04.160508 Google Chrome AP resets since EC boot: 0
1550 07:49:04.163945 Google Chrome most recent AP reset causes:
1551 07:49:04.170618 Google Chrome EC reset flags at last EC boot: reset-pin
1552 07:49:04.174003 PNP: 0c09.0 init finished in 20602 usecs
1553 07:49:04.177314 Devices initialized
1554 07:49:04.180645 Show all devs... After init.
1555 07:49:04.180734 Root Device: enabled 1
1556 07:49:04.183388 CPU_CLUSTER: 0: enabled 1
1557 07:49:04.186736 DOMAIN: 0000: enabled 1
1558 07:49:04.186820 APIC: 00: enabled 1
1559 07:49:04.190160 PCI: 00:00.0: enabled 1
1560 07:49:04.193387 PCI: 00:02.0: enabled 1
1561 07:49:04.196622 PCI: 00:04.0: enabled 0
1562 07:49:04.196706 PCI: 00:05.0: enabled 0
1563 07:49:04.200071 PCI: 00:12.0: enabled 1
1564 07:49:04.203347 PCI: 00:12.5: enabled 0
1565 07:49:04.206535 PCI: 00:12.6: enabled 0
1566 07:49:04.206621 PCI: 00:14.0: enabled 1
1567 07:49:04.209965 PCI: 00:14.1: enabled 0
1568 07:49:04.213348 PCI: 00:14.3: enabled 1
1569 07:49:04.216553 PCI: 00:14.5: enabled 0
1570 07:49:04.216637 PCI: 00:15.0: enabled 1
1571 07:49:04.219955 PCI: 00:15.1: enabled 1
1572 07:49:04.223419 PCI: 00:15.2: enabled 0
1573 07:49:04.226727 PCI: 00:15.3: enabled 0
1574 07:49:04.226811 PCI: 00:16.0: enabled 1
1575 07:49:04.229392 PCI: 00:16.1: enabled 0
1576 07:49:04.233108 PCI: 00:16.2: enabled 0
1577 07:49:04.236413 PCI: 00:16.3: enabled 0
1578 07:49:04.236497 PCI: 00:16.4: enabled 0
1579 07:49:04.239567 PCI: 00:16.5: enabled 0
1580 07:49:04.242835 PCI: 00:17.0: enabled 1
1581 07:49:04.242918 PCI: 00:19.0: enabled 1
1582 07:49:04.246095 PCI: 00:19.1: enabled 0
1583 07:49:04.249565 PCI: 00:19.2: enabled 0
1584 07:49:04.252725 PCI: 00:1a.0: enabled 0
1585 07:49:04.252847 PCI: 00:1c.0: enabled 0
1586 07:49:04.255571 PCI: 00:1c.1: enabled 0
1587 07:49:04.259291 PCI: 00:1c.2: enabled 0
1588 07:49:04.262546 PCI: 00:1c.3: enabled 0
1589 07:49:04.262629 PCI: 00:1c.4: enabled 0
1590 07:49:04.265909 PCI: 00:1c.5: enabled 0
1591 07:49:04.268454 PCI: 00:1c.6: enabled 0
1592 07:49:04.271822 PCI: 00:1c.7: enabled 0
1593 07:49:04.271907 PCI: 00:1d.0: enabled 1
1594 07:49:04.275239 PCI: 00:1d.1: enabled 0
1595 07:49:04.278609 PCI: 00:1d.2: enabled 0
1596 07:49:04.281950 PCI: 00:1d.3: enabled 0
1597 07:49:04.282034 PCI: 00:1d.4: enabled 0
1598 07:49:04.285169 PCI: 00:1d.5: enabled 0
1599 07:49:04.288584 PCI: 00:1e.0: enabled 1
1600 07:49:04.292031 PCI: 00:1e.1: enabled 0
1601 07:49:04.292115 PCI: 00:1e.2: enabled 1
1602 07:49:04.295249 PCI: 00:1e.3: enabled 1
1603 07:49:04.297874 PCI: 00:1f.0: enabled 1
1604 07:49:04.301297 PCI: 00:1f.1: enabled 0
1605 07:49:04.301381 PCI: 00:1f.2: enabled 0
1606 07:49:04.304531 PCI: 00:1f.3: enabled 1
1607 07:49:04.307856 PCI: 00:1f.4: enabled 1
1608 07:49:04.311346 PCI: 00:1f.5: enabled 1
1609 07:49:04.311430 PCI: 00:1f.6: enabled 0
1610 07:49:04.314689 USB0 port 0: enabled 1
1611 07:49:04.317961 I2C: 01:15: enabled 1
1612 07:49:04.318044 I2C: 02:5d: enabled 1
1613 07:49:04.321215 GENERIC: 0.0: enabled 1
1614 07:49:04.324576 I2C: 03:1a: enabled 1
1615 07:49:04.324660 I2C: 03:38: enabled 1
1616 07:49:04.327943
1617 07:49:04.328033 I2C: 03:39: enabled 1
1618 07:49:04.330632 I2C: 03:3a: enabled 1
1619 07:49:04.334047 I2C: 03:3b: enabled 1
1620 07:49:04.334150 PCI: 00:00.0: enabled 1
1621 07:49:04.337163 SPI: 00: enabled 1
1622 07:49:04.337257 SPI: 01: enabled 1
1623 07:49:04.341230 PNP: 0c09.0: enabled 1
1624 07:49:04.344003 USB2 port 0: enabled 1
1625 07:49:04.347196 USB2 port 1: enabled 1
1626 07:49:04.347287 USB2 port 2: enabled 0
1627 07:49:04.350545 USB2 port 3: enabled 0
1628 07:49:04.353786 USB2 port 5: enabled 0
1629 07:49:04.353871 USB2 port 6: enabled 1
1630 07:49:04.356968 USB2 port 9: enabled 1
1631 07:49:04.360671 USB3 port 0: enabled 1
1632 07:49:04.364011 USB3 port 1: enabled 1
1633 07:49:04.364096 USB3 port 2: enabled 1
1634 07:49:04.367370 USB3 port 3: enabled 1
1635 07:49:04.370728 USB3 port 4: enabled 0
1636 07:49:04.370812 APIC: 03: enabled 1
1637 07:49:04.374055 APIC: 07: enabled 1
1638 07:49:04.377364 APIC: 01: enabled 1
1639 07:49:04.377448 APIC: 02: enabled 1
1640 07:49:04.380496 APIC: 06: enabled 1
1641 07:49:04.380588 APIC: 04: enabled 1
1642 07:49:04.383262 APIC: 05: enabled 1
1643 07:49:04.386703 PCI: 00:08.0: enabled 1
1644 07:49:04.390149 PCI: 00:14.2: enabled 1
1645 07:49:04.390233 PCI: 01:00.0: enabled 1
1646 07:49:04.394193 Disabling ACPI via APMC:
1647 07:49:04.398070 done.
1648 07:49:04.401564 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1649 07:49:04.405027 ELOG: NV offset 0xaf0000 size 0x4000
1650 07:49:04.412419 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1651 07:49:04.419017 ELOG: Event(17) added with size 13 at 2022-11-25 07:49:04 UTC
1652 07:49:04.425419 POST: Unexpected post code in previous boot: 0x73
1653 07:49:04.432355 ELOG: Event(A3) added with size 11 at 2022-11-25 07:49:04 UTC
1654 07:49:04.438173 ELOG: Event(A6) added with size 13 at 2022-11-25 07:49:04 UTC
1655 07:49:04.444949 ELOG: Event(92) added with size 9 at 2022-11-25 07:49:04 UTC
1656 07:49:04.451610 ELOG: Event(93) added with size 9 at 2022-11-25 07:49:04 UTC
1657 07:49:04.454873 ELOG: Event(9A) added with size 9 at 2022-11-25 07:49:04 UTC
1658 07:49:04.461472 ELOG: Event(9E) added with size 10 at 2022-11-25 07:49:04 UTC
1659 07:49:04.468035 ELOG: Event(9F) added with size 14 at 2022-11-25 07:49:04 UTC
1660 07:49:04.474465 BS: BS_DEV_INIT times (ms): entry 0 run 28 exit 6
1661 07:49:04.481359 ELOG: Event(A1) added with size 10 at 2022-11-25 07:49:04 UTC
1662 07:49:04.487906 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1663 07:49:04.494706 ELOG: Event(A0) added with size 9 at 2022-11-25 07:49:04 UTC
1664 07:49:04.500709 elog_add_boot_reason: Logged dev mode boot
1665 07:49:04.500828 Finalize devices...
1666 07:49:04.504056 PCI: 00:17.0 final
1667 07:49:04.504139 Devices finalized
1668 07:49:04.510545 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1669 07:49:04.517372 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1670 07:49:04.520692 ME: HFSTS1 : 0x90000245
1671 07:49:04.523888 ME: HFSTS2 : 0x3B850126
1672 07:49:04.527061 ME: HFSTS3 : 0x00000020
1673 07:49:04.533934 ME: HFSTS4 : 0x00004800
1674 07:49:04.537198 ME: HFSTS5 : 0x00000000
1675 07:49:04.540644 ME: HFSTS6 : 0x40400006
1676 07:49:04.543703 ME: Manufacturing Mode : NO
1677 07:49:04.547087 ME: FW Partition Table : OK
1678 07:49:04.550473 ME: Bringup Loader Failure : NO
1679 07:49:04.553126 ME: Firmware Init Complete : YES
1680 07:49:04.556662 ME: Boot Options Present : NO
1681 07:49:04.559866 ME: Update In Progress : NO
1682 07:49:04.563018 ME: D0i3 Support : YES
1683 07:49:04.566244 ME: Low Power State Enabled : NO
1684 07:49:04.569645 ME: CPU Replaced : NO
1685 07:49:04.572713 ME: CPU Replacement Valid : YES
1686 07:49:04.576102 ME: Current Working State : 5
1687 07:49:04.579458 ME: Current Operation State : 1
1688 07:49:04.582893 ME: Current Operation Mode : 0
1689 07:49:04.586104 ME: Error Code : 0
1690 07:49:04.589464 ME: CPU Debug Disabled : YES
1691 07:49:04.592604 ME: TXT Support : NO
1692 07:49:04.599353 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1693 07:49:04.605247 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1694 07:49:04.605334 CBFS @ c08000 size 3f8000
1695 07:49:04.611849 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1696 07:49:04.615210 CBFS: Locating 'fallback/dsdt.aml'
1697 07:49:04.618425 CBFS: Found @ offset 10bb80 size 3fa5
1698 07:49:04.621859
1699 07:49:04.625229 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1700 07:49:04.628487 CBFS @ c08000 size 3f8000
1701 07:49:04.635213 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1702 07:49:04.638604 CBFS: Locating 'fallback/slic'
1703 07:49:04.641284 CBFS: 'fallback/slic' not found.
1704 07:49:04.644428 ACPI: Writing ACPI tables at 99b3e000.
1705 07:49:04.647795 ACPI: * FACS
1706 07:49:04.647878 ACPI: * DSDT
1707 07:49:04.654445 Ramoops buffer: 0x100000@0x99a3d000.
1708 07:49:04.657834 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1709 07:49:04.661209 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1710 07:49:04.665196 Google Chrome EC: version:
1711 07:49:04.668372 ro: helios_v2.0.2659-56403530b
1712 07:49:04.671753 rw: helios_v2.0.2849-c41de27e7d
1713 07:49:04.675206 running image: 1
1714 07:49:04.677849 ACPI: * FADT
1715 07:49:04.677931 SCI is IRQ9
1716 07:49:04.681668 ACPI: added table 1/32, length now 40
1717 07:49:04.684324 ACPI: * SSDT
1718 07:49:04.687650 Found 1 CPU(s) with 8 core(s) each.
1719 07:49:04.691125 Error: Could not locate 'wifi_sar' in VPD.
1720 07:49:04.697549 Checking CBFS for default SAR values
1721 07:49:04.700876 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1722 07:49:04.704036 CBFS @ c08000 size 3f8000
1723 07:49:04.710853 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1724 07:49:04.714246 CBFS: Locating 'wifi_sar_defaults.hex'
1725 07:49:04.717501 CBFS: Found @ offset 5fac0 size 77
1726 07:49:04.720916 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1727 07:49:04.726877 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1728 07:49:04.730306 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1729 07:49:04.736927 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1730 07:49:04.740238 failed to find key in VPD: dsm_calib_r0_0
1731 07:49:04.750092 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1732 07:49:04.753462 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1733 07:49:04.760496 failed to find key in VPD: dsm_calib_r0_1
1734 07:49:04.766312 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1735 07:49:04.773007 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1736 07:49:04.776157 failed to find key in VPD: dsm_calib_r0_2
1737 07:49:04.786265 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1738 07:49:04.792974 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1739 07:49:04.796125 failed to find key in VPD: dsm_calib_r0_3
1740 07:49:04.806066 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1741 07:49:04.809574 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1742 07:49:04.812311 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1743 07:49:04.815672
1744 07:49:04.818932 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1745 07:49:04.822374 EC returned error result code 1
1746 07:49:04.825721 EC returned error result code 1
1747 07:49:04.829092 EC returned error result code 1
1748 07:49:04.832409 PS2K: Bad resp from EC. Vivaldi disabled!
1749 07:49:04.839046 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1750 07:49:04.845767 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1751 07:49:04.848925 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1752 07:49:04.852238
1753 07:49:04.855749 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1754 07:49:04.862373 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1755 07:49:04.868306 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1756 07:49:04.872048 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1757 07:49:04.878098 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1758 07:49:04.882049 ACPI: added table 2/32, length now 44
1759 07:49:04.884645 ACPI: * MCFG
1760 07:49:04.888129 ACPI: added table 3/32, length now 48
1761 07:49:04.888214 ACPI: * TPM2
1762 07:49:04.891522
1763 07:49:04.891606 TPM2 log created at 99a2d000
1764 07:49:04.898157 ACPI: added table 4/32, length now 52
1765 07:49:04.898242 ACPI: * MADT
1766 07:49:04.898308 SCI is IRQ9
1767 07:49:04.904863 ACPI: added table 5/32, length now 56
1768 07:49:04.904947 current = 99b43ac0
1769 07:49:04.907552 ACPI: * DMAR
1770 07:49:04.910863 ACPI: added table 6/32, length now 60
1771 07:49:04.914389 ACPI: * IGD OpRegion
1772 07:49:04.914497 GMA: Found VBT in CBFS
1773 07:49:04.917491 GMA: Found valid VBT in CBFS
1774 07:49:04.920764 ACPI: added table 7/32, length now 64
1775 07:49:04.924239 ACPI: * HPET
1776 07:49:04.927440 ACPI: added table 8/32, length now 68
1777 07:49:04.927525 ACPI: done.
1778 07:49:04.930951 ACPI tables: 31744 bytes.
1779 07:49:04.933988 smbios_write_tables: 99a2c000
1780 07:49:04.937366 EC returned error result code 3
1781 07:49:04.940633 Couldn't obtain OEM name from CBI
1782 07:49:04.943856 Create SMBIOS type 17
1783 07:49:04.947185 PCI: 00:00.0 (Intel Cannonlake)
1784 07:49:04.950469 PCI: 00:14.3 (Intel WiFi)
1785 07:49:04.953861 SMBIOS tables: 939 bytes.
1786 07:49:04.957028 Writing table forward entry at 0x00000500
1787 07:49:04.963750 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1788 07:49:04.967075 Writing coreboot table at 0x99b62000
1789 07:49:04.973585 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1790 07:49:04.976935 1. 0000000000001000-000000000009ffff: RAM
1791 07:49:04.983639 2. 00000000000a0000-00000000000fffff: RESERVED
1792 07:49:04.986971 3. 0000000000100000-0000000099a2bfff: RAM
1793 07:49:04.992956 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1794 07:49:04.996322 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1795 07:49:05.003015 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1796 07:49:05.006306 7. 000000009a000000-000000009f7fffff: RESERVED
1797 07:49:05.013060 8. 00000000e0000000-00000000efffffff: RESERVED
1798 07:49:05.016514 9. 00000000fc000000-00000000fc000fff: RESERVED
1799 07:49:05.022934 10. 00000000fe000000-00000000fe00ffff: RESERVED
1800 07:49:05.026430 11. 00000000fed10000-00000000fed17fff: RESERVED
1801 07:49:05.032511 12. 00000000fed80000-00000000fed83fff: RESERVED
1802 07:49:05.035682 13. 00000000fed90000-00000000fed91fff: RESERVED
1803 07:49:05.039480 14. 00000000feda0000-00000000feda1fff: RESERVED
1804 07:49:05.045809 15. 0000000100000000-000000045e7fffff: RAM
1805 07:49:05.049109 Graphics framebuffer located at 0xc0000000
1806 07:49:05.052429 Passing 5 GPIOs to payload:
1807 07:49:05.058847 NAME | PORT | POLARITY | VALUE
1808 07:49:05.062145 write protect | undefined | high | low
1809 07:49:05.068706 lid | undefined | high | high
1810 07:49:05.072309 power | undefined | high | low
1811 07:49:05.078820 oprom | undefined | high | low
1812 07:49:05.084900 EC in RW | 0x000000cb | high | low
1813 07:49:05.084997 Board ID: 4
1814 07:49:05.091515 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1815 07:49:05.091602 CBFS @ c08000 size 3f8000
1816 07:49:05.098275 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1817 07:49:05.104788 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 4d87
1818 07:49:05.108105 coreboot table: 1492 bytes.
1819 07:49:05.111328 IMD ROOT 0. 99fff000 00001000
1820 07:49:05.114592 IMD SMALL 1. 99ffe000 00001000
1821 07:49:05.118098 FSP MEMORY 2. 99c4e000 003b0000
1822 07:49:05.121353 CONSOLE 3. 99c2e000 00020000
1823 07:49:05.124692 FMAP 4. 99c2d000 0000054e
1824 07:49:05.127989 TIME STAMP 5. 99c2c000 00000910
1825 07:49:05.131324 VBOOT WORK 6. 99c18000 00014000
1826 07:49:05.134769 MRC DATA 7. 99c16000 00001958
1827 07:49:05.137506 ROMSTG STCK 8. 99c15000 00001000
1828 07:49:05.140776 AFTER CAR 9. 99c0b000 0000a000
1829 07:49:05.144148 RAMSTAGE 10. 99baf000 0005c000
1830 07:49:05.147484 REFCODE 11. 99b7a000 00035000
1831 07:49:05.150946 SMM BACKUP 12. 99b6a000 00010000
1832 07:49:05.154254 COREBOOT 13. 99b62000 00008000
1833 07:49:05.157485 ACPI 14. 99b3e000 00024000
1834 07:49:05.160690 ACPI GNVS 15. 99b3d000 00001000
1835 07:49:05.163841 RAMOOPS 16. 99a3d000 00100000
1836 07:49:05.167344 TPM2 TCGLOG17. 99a2d000 00010000
1837 07:49:05.170618 SMBIOS 18. 99a2c000 00000800
1838 07:49:05.173241 IMD small region:
1839 07:49:05.176617 IMD ROOT 0. 99ffec00 00000400
1840 07:49:05.179944 FSP RUNTIME 1. 99ffebe0 00000004
1841 07:49:05.183149 EC HOSTEVENT 2. 99ffebc0 00000008
1842 07:49:05.186655 POWER STATE 3. 99ffeb80 00000040
1843 07:49:05.189770 ROMSTAGE 4. 99ffeb60 00000004
1844 07:49:05.193118 MEM INFO 5. 99ffe9a0 000001b9
1845 07:49:05.196445 VPD 6. 99ffe920 0000006c
1846 07:49:05.199938 MTRR: Physical address space:
1847 07:49:05.206063 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1848 07:49:05.212671 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1849 07:49:05.219216 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1850 07:49:05.225945 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1851 07:49:05.232664 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1852 07:49:05.239089 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1853 07:49:05.245145 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1854 07:49:05.248418 MTRR: Fixed MSR 0x250 0x0606060606060606
1855 07:49:05.251749 MTRR: Fixed MSR 0x258 0x0606060606060606
1856 07:49:05.255048 MTRR: Fixed MSR 0x259 0x0000000000000000
1857 07:49:05.258420 MTRR: Fixed MSR 0x268 0x0606060606060606
1858 07:49:05.261670
1859 07:49:05.264954 MTRR: Fixed MSR 0x269 0x0606060606060606
1860 07:49:05.268263 MTRR: Fixed MSR 0x26a 0x0606060606060606
1861 07:49:05.271454 MTRR: Fixed MSR 0x26b 0x0606060606060606
1862 07:49:05.274853 MTRR: Fixed MSR 0x26c 0x0606060606060606
1863 07:49:05.281386 MTRR: Fixed MSR 0x26d 0x0606060606060606
1864 07:49:05.284656 MTRR: Fixed MSR 0x26e 0x0606060606060606
1865 07:49:05.288178 MTRR: Fixed MSR 0x26f 0x0606060606060606
1866 07:49:05.291266 call enable_fixed_mtrr()
1867 07:49:05.294576 CPU physical address size: 39 bits
1868 07:49:05.301233 MTRR: default type WB/UC MTRR counts: 6/8.
1869 07:49:05.304708 MTRR: WB selected as default type.
1870 07:49:05.311328 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1871 07:49:05.317390 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1872 07:49:05.320941 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1873 07:49:05.327537 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1874 07:49:05.334065 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1875 07:49:05.340668 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1876 07:49:05.347368 MTRR: Fixed MSR 0x250 0x0606060606060606
1877 07:49:05.349839 MTRR: Fixed MSR 0x258 0x0606060606060606
1878 07:49:05.353295 MTRR: Fixed MSR 0x259 0x0000000000000000
1879 07:49:05.356658 MTRR: Fixed MSR 0x268 0x0606060606060606
1880 07:49:05.363351 MTRR: Fixed MSR 0x269 0x0606060606060606
1881 07:49:05.366668 MTRR: Fixed MSR 0x26a 0x0606060606060606
1882 07:49:05.369941 MTRR: Fixed MSR 0x26b 0x0606060606060606
1883 07:49:05.373142 MTRR: Fixed MSR 0x26c 0x0606060606060606
1884 07:49:05.379401 MTRR: Fixed MSR 0x26d 0x0606060606060606
1885 07:49:05.383034 MTRR: Fixed MSR 0x26e 0x0606060606060606
1886 07:49:05.385821 MTRR: Fixed MSR 0x26f 0x0606060606060606
1887 07:49:05.385916
1888 07:49:05.389171 MTRR check
1889 07:49:05.389259 Fixed MTRRs : Enabled
1890 07:49:05.392567
1891 07:49:05.392652 Variable MTRRs: Enabled
1892 07:49:05.392757
1893 07:49:05.395814 call enable_fixed_mtrr()
1894 07:49:05.402572 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1895 07:49:05.405499 CPU physical address size: 39 bits
1896 07:49:05.409317 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1897 07:49:05.415397 MTRR: Fixed MSR 0x250 0x0606060606060606
1898 07:49:05.418498 MTRR: Fixed MSR 0x258 0x0606060606060606
1899 07:49:05.422043 MTRR: Fixed MSR 0x259 0x0000000000000000
1900 07:49:05.425276 MTRR: Fixed MSR 0x268 0x0606060606060606
1901 07:49:05.431894 MTRR: Fixed MSR 0x269 0x0606060606060606
1902 07:49:05.435326 MTRR: Fixed MSR 0x26a 0x0606060606060606
1903 07:49:05.438606 MTRR: Fixed MSR 0x26b 0x0606060606060606
1904 07:49:05.441921 MTRR: Fixed MSR 0x26c 0x0606060606060606
1905 07:49:05.448399 MTRR: Fixed MSR 0x26d 0x0606060606060606
1906 07:49:05.451730 MTRR: Fixed MSR 0x26e 0x0606060606060606
1907 07:49:05.455000 MTRR: Fixed MSR 0x26f 0x0606060606060606
1908 07:49:05.458319 MTRR: Fixed MSR 0x250 0x0606060606060606
1909 07:49:05.461483
1910 07:49:05.461568 call enable_fixed_mtrr()
1911 07:49:05.464709 MTRR: Fixed MSR 0x258 0x0606060606060606
1912 07:49:05.468337
1913 07:49:05.471517 MTRR: Fixed MSR 0x259 0x0000000000000000
1914 07:49:05.474767 MTRR: Fixed MSR 0x268 0x0606060606060606
1915 07:49:05.478112 MTRR: Fixed MSR 0x269 0x0606060606060606
1916 07:49:05.480996 MTRR: Fixed MSR 0x26a 0x0606060606060606
1917 07:49:05.487710 MTRR: Fixed MSR 0x26b 0x0606060606060606
1918 07:49:05.490749 MTRR: Fixed MSR 0x26c 0x0606060606060606
1919 07:49:05.494068 MTRR: Fixed MSR 0x26d 0x0606060606060606
1920 07:49:05.497450 MTRR: Fixed MSR 0x26e 0x0606060606060606
1921 07:49:05.504200 MTRR: Fixed MSR 0x26f 0x0606060606060606
1922 07:49:05.507498 CPU physical address size: 39 bits
1923 07:49:05.510737 call enable_fixed_mtrr()
1924 07:49:05.514318 MTRR: Fixed MSR 0x250 0x0606060606060606
1925 07:49:05.517030 MTRR: Fixed MSR 0x258 0x0606060606060606
1926 07:49:05.523630 MTRR: Fixed MSR 0x259 0x0000000000000000
1927 07:49:05.526934 MTRR: Fixed MSR 0x268 0x0606060606060606
1928 07:49:05.530403 MTRR: Fixed MSR 0x269 0x0606060606060606
1929 07:49:05.533689 MTRR: Fixed MSR 0x26a 0x0606060606060606
1930 07:49:05.540204 MTRR: Fixed MSR 0x26b 0x0606060606060606
1931 07:49:05.543644 MTRR: Fixed MSR 0x26c 0x0606060606060606
1932 07:49:05.546286 MTRR: Fixed MSR 0x26d 0x0606060606060606
1933 07:49:05.549518 MTRR: Fixed MSR 0x26e 0x0606060606060606
1934 07:49:05.556177 MTRR: Fixed MSR 0x26f 0x0606060606060606
1935 07:49:05.559415 MTRR: Fixed MSR 0x250 0x0606060606060606
1936 07:49:05.562873 call enable_fixed_mtrr()
1937 07:49:05.566109 MTRR: Fixed MSR 0x258 0x0606060606060606
1938 07:49:05.569375 MTRR: Fixed MSR 0x259 0x0000000000000000
1939 07:49:05.572746 MTRR: Fixed MSR 0x268 0x0606060606060606
1940 07:49:05.579404 MTRR: Fixed MSR 0x269 0x0606060606060606
1941 07:49:05.582144 MTRR: Fixed MSR 0x26a 0x0606060606060606
1942 07:49:05.585561 MTRR: Fixed MSR 0x26b 0x0606060606060606
1943 07:49:05.588715 MTRR: Fixed MSR 0x26c 0x0606060606060606
1944 07:49:05.595361 MTRR: Fixed MSR 0x26d 0x0606060606060606
1945 07:49:05.598614 MTRR: Fixed MSR 0x26e 0x0606060606060606
1946 07:49:05.602029 MTRR: Fixed MSR 0x26f 0x0606060606060606
1947 07:49:05.605343 CPU physical address size: 39 bits
1948 07:49:05.608713 call enable_fixed_mtrr()
1949 07:49:05.612075 CPU physical address size: 39 bits
1950 07:49:05.617987 MTRR: Fixed MSR 0x250 0x0606060606060606
1951 07:49:05.621363 MTRR: Fixed MSR 0x250 0x0606060606060606
1952 07:49:05.624706 MTRR: Fixed MSR 0x258 0x0606060606060606
1953 07:49:05.628033 MTRR: Fixed MSR 0x259 0x0000000000000000
1954 07:49:05.631374 MTRR: Fixed MSR 0x268 0x0606060606060606
1955 07:49:05.634626
1956 07:49:05.637905 MTRR: Fixed MSR 0x269 0x0606060606060606
1957 07:49:05.641310 MTRR: Fixed MSR 0x26a 0x0606060606060606
1958 07:49:05.644499 MTRR: Fixed MSR 0x26b 0x0606060606060606
1959 07:49:05.647858 MTRR: Fixed MSR 0x26c 0x0606060606060606
1960 07:49:05.651016
1961 07:49:05.654310 MTRR: Fixed MSR 0x26d 0x0606060606060606
1962 07:49:05.657844 MTRR: Fixed MSR 0x26e 0x0606060606060606
1963 07:49:05.661064 MTRR: Fixed MSR 0x26f 0x0606060606060606
1964 07:49:05.667508 MTRR: Fixed MSR 0x258 0x0606060606060606
1965 07:49:05.670882 MTRR: Fixed MSR 0x259 0x0000000000000000
1966 07:49:05.674143 MTRR: Fixed MSR 0x268 0x0606060606060606
1967 07:49:05.677459 MTRR: Fixed MSR 0x269 0x0606060606060606
1968 07:49:05.684167 MTRR: Fixed MSR 0x26a 0x0606060606060606
1969 07:49:05.687287 MTRR: Fixed MSR 0x26b 0x0606060606060606
1970 07:49:05.690639 MTRR: Fixed MSR 0x26c 0x0606060606060606
1971 07:49:05.694058 MTRR: Fixed MSR 0x26d 0x0606060606060606
1972 07:49:05.699990 MTRR: Fixed MSR 0x26e 0x0606060606060606
1973 07:49:05.703906 MTRR: Fixed MSR 0x26f 0x0606060606060606
1974 07:49:05.706602 call enable_fixed_mtrr()
1975 07:49:05.706687 call enable_fixed_mtrr()
1976 07:49:05.709853 CPU physical address size: 39 bits
1977 07:49:05.713162
1978 07:49:05.713247 CBFS @ c08000 size 3f8000
1979 07:49:05.719950 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1980 07:49:05.723373 CPU physical address size: 39 bits
1981 07:49:05.726546 CPU physical address size: 39 bits
1982 07:49:05.730049 CBFS: Locating 'fallback/payload'
1983 07:49:05.737281 CBFS: Found @ offset 1c96c0 size 3f798
1984 07:49:05.739871 Checking segment from ROM address 0xffdd16f8
1985 07:49:05.743274 Checking segment from ROM address 0xffdd1714
1986 07:49:05.749825 Loading segment from ROM address 0xffdd16f8
1987 07:49:05.749910 code (compression=0)
1988 07:49:05.759607 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1989 07:49:05.769504 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1990 07:49:05.769589 it's not compressed!
1991 07:49:05.862485 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1992 07:49:05.869318 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1993 07:49:05.875622 Loading segment from ROM address 0xffdd1714
1994 07:49:05.875709 Entry Point 0x30000000
1995 07:49:05.878917 Loaded segments
1996 07:49:05.884898 Finalizing chipset.
1997 07:49:05.888100 Finalizing SMM.
1998 07:49:05.891518 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 89 exit 5
1999 07:49:05.894778 mp_park_aps done after 0 msecs.
2000 07:49:05.901300 Jumping to boot code at 30000000(99b62000)
2001 07:49:05.907493 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
2002 07:49:05.907579
2003 07:49:05.907648
2004 07:49:05.907710
2005 07:49:05.910751 Starting depthcharge on Helios...
2006 07:49:05.910835
2007 07:49:05.911169 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
2008 07:49:05.911272 start: 2.2.4 bootloader-commands (timeout 00:04:40) [common]
2009 07:49:05.911358 Setting prompt string to ['hatch:']
2010 07:49:05.911438 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:40)
2011 07:49:05.920838 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2012 07:49:05.920926
2013 07:49:05.927298 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2014 07:49:05.927384
2015 07:49:05.934041 board_setup: Info: eMMC controller not present; skipping
2016 07:49:05.934126
2017 07:49:05.937174 New NVMe Controller 0x30053ac0 @ 00:1d:00
2018 07:49:05.937259
2019 07:49:05.943876 board_setup: Info: SDHCI controller not present; skipping
2020 07:49:05.943960
2021 07:49:05.950432 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2022 07:49:05.950517
2023 07:49:05.950586 Wipe memory regions:
2024 07:49:05.950648
2025 07:49:05.957052 [0x00000000001000, 0x000000000a0000)
2026 07:49:05.957137
2027 07:49:05.959750 [0x00000000100000, 0x00000030000000)
2028 07:49:05.959834
2029 07:49:06.026842 [0x00000030657430, 0x00000099a2c000)
2030 07:49:06.026961
2031 07:49:06.168135 [0x00000100000000, 0x0000045e800000)
2032 07:49:06.168269
2033 07:49:07.550655 R8152: Initializing
2034 07:49:07.550801
2035 07:49:07.553900 Version 9 (ocp_data = 6010)
2036 07:49:07.553974
2037 07:49:07.557739 R8152: Done initializing
2038 07:49:07.557827
2039 07:49:07.561244 Adding net device
2040 07:49:07.561319
2041 07:49:08.044311 R8152: Initializing
2042 07:49:08.044456
2043 07:49:08.047806 Version 6 (ocp_data = 5c30)
2044 07:49:08.047911
2045 07:49:08.050349 R8152: Done initializing
2046 07:49:08.050420
2047 07:49:08.057216 net_add_device: Attemp to include the same device
2048 07:49:08.057289
2049 07:49:08.063907 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2050 07:49:08.064001
2051 07:49:08.064066
2052 07:49:08.064131
2053 07:49:08.064401 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2055 07:49:08.164943 hatch: tftpboot 192.168.201.1 8119365/tftp-deploy-qzzzfjpq/kernel/bzImage 8119365/tftp-deploy-qzzzfjpq/kernel/cmdline 8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
2056 07:49:08.165113 Setting prompt string to 'Starting kernel'
2057 07:49:08.165200 Setting prompt string to ['Starting kernel']
2058 07:49:08.165278 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2059 07:49:08.165354 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
2060 07:49:08.169658 tftpboot 192.168.201.1 8119365/tftp-deploy-qzzzfjpq/kernel/bzImoy-qzzzfjpq/kernel/cmdline 8119365/tftp-deploy-qzzzfjpq/ramdisk/ramdisk.cpio.gz
2061 07:49:08.169741
2062 07:49:08.169806 Waiting for link
2063 07:49:08.169874
2064 07:49:08.370756 done.
2065 07:49:08.370903
2066 07:49:08.370973 MAC: 00:24:32:50:19:be
2067 07:49:08.371035
2068 07:49:08.373992 Sending DHCP discover... done.
2069 07:49:08.374077
2070 07:49:08.377359 Waiting for reply... done.
2071 07:49:08.377447
2072 07:49:08.380538 Sending DHCP request... done.
2073 07:49:08.380617
2074 07:49:08.383741 Waiting for reply... done.
2075 07:49:08.383820
2076 07:49:08.387207 My ip is 192.168.201.15
2077 07:49:08.387283
2078 07:49:08.390286 The DHCP server ip is 192.168.201.1
2079 07:49:08.390366
2080 07:49:08.393546 TFTP server IP predefined by user: 192.168.201.1
2081 07:49:08.393619
2082 07:49:08.400089 Bootfile predefined by user: 8119365/tftp-deploy-qzzzfjpq/kernel/bzImage
2083 07:49:08.400173
2084 07:49:08.403628 Sending tftp read request... done.
2085 07:49:08.406914
2086 07:49:08.410188 Waiting for the transfer...
2087 07:49:08.410262
2088 07:49:08.930994 00000000 ################################################################
2089 07:49:08.931141
2090 07:49:09.455138 00080000 ################################################################
2091 07:49:09.455296
2092 07:49:10.007189 00100000 ################################################################
2093 07:49:10.007323
2094 07:49:10.554306 00180000 ################################################################
2095 07:49:10.554447
2096 07:49:11.098458 00200000 ################################################################
2097 07:49:11.098613
2098 07:49:11.635222 00280000 ################################################################
2099 07:49:11.635370
2100 07:49:12.168445 00300000 ################################################################
2101 07:49:12.168610
2102 07:49:12.719974 00380000 ################################################################
2103 07:49:12.720361
2104 07:49:13.415962 00400000 ################################################################
2105 07:49:13.416523
2106 07:49:14.117682 00480000 ################################################################
2107 07:49:14.118190
2108 07:49:14.797270 00500000 ################################################################
2109 07:49:14.797769
2110 07:49:15.413687 00580000 ################################################################
2111 07:49:15.413824
2112 07:49:16.051241 00600000 ################################################################
2113 07:49:16.051384
2114 07:49:16.421672 00680000 ####################################### done.
2115 07:49:16.421885
2116 07:49:16.425004 The bootfile was 7131024 bytes long.
2117 07:49:16.425163
2118 07:49:16.428365 Sending tftp read request... done.
2119 07:49:16.428521
2120 07:49:16.431533 Waiting for the transfer...
2121 07:49:16.431690
2122 07:49:17.065247 00000000 ################################################################
2123 07:49:17.065389
2124 07:49:17.644246 00080000 ################################################################
2125 07:49:17.644387
2126 07:49:18.239377 00100000 ################################################################
2127 07:49:18.239513
2128 07:49:18.833563 00180000 ################################################################
2129 07:49:18.833874
2130 07:49:19.426291 00200000 ################################################################
2131 07:49:19.426431
2132 07:49:20.080577 00280000 ################################################################
2133 07:49:20.081123
2134 07:49:20.721245 00300000 ################################################################
2135 07:49:20.721384
2136 07:49:21.323918 00380000 ################################################################
2137 07:49:21.324060
2138 07:49:22.284493 00400000 ################################################################
2139 07:49:22.284647
2140 07:49:22.922183 00480000 ################################################################
2141 07:49:22.922323
2142 07:49:23.549878 00500000 ################################################################
2143 07:49:23.550018
2144 07:49:24.152939 00580000 ################################################################
2145 07:49:24.153073
2146 07:49:24.703688 00600000 ################################################################
2147 07:49:24.703822
2148 07:49:25.248650 00680000 ################################################################
2149 07:49:25.248798
2150 07:49:25.768652 00700000 ################################################################
2151 07:49:25.768800
2152 07:49:26.288797 00780000 ################################################################
2153 07:49:26.288934
2154 07:49:26.444114 00800000 #################### done.
2155 07:49:26.444256
2156 07:49:26.447357 Sending tftp read request... done.
2157 07:49:26.447445
2158 07:49:26.450838 Waiting for the transfer...
2159 07:49:26.450927
2160 07:49:26.450994 00000000 # done.
2161 07:49:26.451059
2162 07:49:26.460379 Command line loaded dynamically from TFTP file: 8119365/tftp-deploy-qzzzfjpq/kernel/cmdline
2163 07:49:26.460468
2164 07:49:26.477081 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2165 07:49:26.477174
2166 07:49:26.483121 ec_init(0): CrosEC protocol v3 supported (256, 256)
2167 07:49:26.483221
2168 07:49:26.491553 Shutting down all USB controllers.
2169 07:49:26.491635
2170 07:49:26.491715 Removing current net device
2171 07:49:26.491779
2172 07:49:26.495141 Finalizing coreboot
2173 07:49:26.495232
2174 07:49:26.502095 Exiting depthcharge with code 4 at timestamp: 27944835
2175 07:49:26.502183
2176 07:49:26.502254
2177 07:49:26.502345 Starting kernel ...
2178 07:49:26.502434
2179 07:49:26.502505
2180 07:49:26.502577
2181 07:49:26.502998 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
2182 07:49:26.503115 start: 2.2.5 auto-login-action (timeout 00:04:20) [common]
2183 07:49:26.503207 Setting prompt string to ['Linux version [0-9]']
2184 07:49:26.503281 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2185 07:49:26.503353 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2187 07:53:46.503366 end: 2.2.5 auto-login-action (duration 00:04:20) [common]
2189 07:53:46.503631 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 260 seconds'
2191 07:53:46.503789 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2194 07:53:46.504055 end: 2 depthcharge-action (duration 00:05:00) [common]
2196 07:53:46.504282 Cleaning after the job
2197 07:53:46.504367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/ramdisk
2198 07:53:46.505049 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/kernel
2199 07:53:46.505547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119365/tftp-deploy-qzzzfjpq/modules
2200 07:53:46.505730 start: 5.1 power-off (timeout 00:00:30) [common]
2201 07:53:46.505878 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=off'
2202 07:53:46.525352 >> Command sent successfully.
2203 07:53:46.527465 Returned 0 in 0 seconds
2204 07:53:46.628272 end: 5.1 power-off (duration 00:00:00) [common]
2206 07:53:46.628609 start: 5.2 read-feedback (timeout 00:10:00) [common]
2207 07:53:46.628896 Listened to connection for namespace 'common' for up to 1s
2208 07:53:47.632853 Finalising connection for namespace 'common'
2209 07:53:47.633036 Disconnecting from shell: Finalise
2210 07:53:47.733805 end: 5.2 read-feedback (duration 00:00:01) [common]
2211 07:53:47.733971 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8119365
2212 07:53:47.738644 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8119365
2213 07:53:47.738768 JobError: Your job cannot terminate cleanly.