Boot log: asus-cx9400-volteer
- Kernel Warnings: 0
- Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
1 07:49:05.654651 lava-dispatcher, installed at version: 2022.10
2 07:49:05.654841 start: 0 validate
3 07:49:05.655011 Start time: 2022-11-25 07:49:05.655004+00:00 (UTC)
4 07:49:05.655135 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:49:05.655263 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20221107.1%2Fx86%2Frootfs.cpio.gz exists
6 07:49:05.941405 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:49:05.941576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:49:05.953163 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:49:05.953279 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 07:49:05.964335 validate duration: 0.31
12 07:49:05.964569 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 07:49:05.964676 start: 1.1 download-retry (timeout 00:10:00) [common]
14 07:49:05.964777 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 07:49:05.964880 Not decompressing ramdisk as can be used compressed.
16 07:49:05.964963 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20221107.1/x86/rootfs.cpio.gz
17 07:49:05.965027 saving as /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/ramdisk/rootfs.cpio.gz
18 07:49:05.965089 total size: 8415749 (8MB)
19 07:49:05.986283 progress 0% (0MB)
20 07:49:06.016010 progress 5% (0MB)
21 07:49:06.046775 progress 10% (0MB)
22 07:49:06.074789 progress 15% (1MB)
23 07:49:06.115164 progress 20% (1MB)
24 07:49:06.154576 progress 25% (2MB)
25 07:49:06.208475 progress 30% (2MB)
26 07:49:06.251336 progress 35% (2MB)
27 07:49:06.301355 progress 40% (3MB)
28 07:49:06.362656 progress 45% (3MB)
29 07:49:06.415062 progress 50% (4MB)
30 07:49:06.475407 progress 55% (4MB)
31 07:49:06.519948 progress 60% (4MB)
32 07:49:06.562336 progress 65% (5MB)
33 07:49:06.625949 progress 70% (5MB)
34 07:49:06.700370 progress 75% (6MB)
35 07:49:06.776581 progress 80% (6MB)
36 07:49:06.866359 progress 85% (6MB)
37 07:49:06.937254 progress 90% (7MB)
38 07:49:07.002837 progress 95% (7MB)
39 07:49:07.060468 progress 100% (8MB)
40 07:49:07.060799 8MB downloaded in 1.10s (7.32MB/s)
41 07:49:07.060970 end: 1.1.1 http-download (duration 00:00:01) [common]
43 07:49:07.061223 end: 1.1 download-retry (duration 00:00:01) [common]
44 07:49:07.061314 start: 1.2 download-retry (timeout 00:09:59) [common]
45 07:49:07.061405 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 07:49:07.061514 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 07:49:07.061583 saving as /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/kernel/bzImage
48 07:49:07.061646 total size: 7131024 (6MB)
49 07:49:07.061708 No compression specified
50 07:49:07.064454 progress 0% (0MB)
51 07:49:07.076106 progress 5% (0MB)
52 07:49:07.088736 progress 10% (0MB)
53 07:49:07.100023 progress 15% (1MB)
54 07:49:07.112124 progress 20% (1MB)
55 07:49:07.125357 progress 25% (1MB)
56 07:49:07.137108 progress 30% (2MB)
57 07:49:07.149357 progress 35% (2MB)
58 07:49:07.162425 progress 40% (2MB)
59 07:49:07.173368 progress 45% (3MB)
60 07:49:07.185657 progress 50% (3MB)
61 07:49:07.197210 progress 55% (3MB)
62 07:49:07.209502 progress 60% (4MB)
63 07:49:07.223719 progress 65% (4MB)
64 07:49:07.241931 progress 70% (4MB)
65 07:49:07.256782 progress 75% (5MB)
66 07:49:07.280025 progress 80% (5MB)
67 07:49:07.297559 progress 85% (5MB)
68 07:49:07.319268 progress 90% (6MB)
69 07:49:07.340162 progress 95% (6MB)
70 07:49:07.357754 progress 100% (6MB)
71 07:49:07.358005 6MB downloaded in 0.30s (22.95MB/s)
72 07:49:07.358189 end: 1.2.1 http-download (duration 00:00:00) [common]
74 07:49:07.358439 end: 1.2 download-retry (duration 00:00:00) [common]
75 07:49:07.358529 start: 1.3 download-retry (timeout 00:09:59) [common]
76 07:49:07.358616 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 07:49:07.358722 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 07:49:07.358790 saving as /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/modules/modules.tar
79 07:49:07.358853 total size: 52060 (0MB)
80 07:49:07.358953 Using unxz to decompress xz
81 07:49:07.421127 progress 62% (0MB)
82 07:49:07.438935 progress 100% (0MB)
83 07:49:07.440484 0MB downloaded in 0.08s (0.61MB/s)
84 07:49:07.440716 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:49:07.440981 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:49:07.441080 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
88 07:49:07.441176 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
89 07:49:07.441265 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 07:49:07.441356 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
91 07:49:07.441525 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97
92 07:49:07.441633 makedir: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin
93 07:49:07.441717 makedir: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/tests
94 07:49:07.441797 makedir: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/results
95 07:49:07.441900 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-add-keys
96 07:49:07.442029 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-add-sources
97 07:49:07.442175 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-background-process-start
98 07:49:07.442306 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-background-process-stop
99 07:49:07.442421 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-common-functions
100 07:49:07.442534 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-echo-ipv4
101 07:49:07.442647 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-install-packages
102 07:49:07.442759 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-installed-packages
103 07:49:07.442869 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-os-build
104 07:49:07.443019 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-probe-channel
105 07:49:07.443130 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-probe-ip
106 07:49:07.443239 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-target-ip
107 07:49:07.443347 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-target-mac
108 07:49:07.443455 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-target-storage
109 07:49:07.443568 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-case
110 07:49:07.443678 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-event
111 07:49:07.443789 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-feedback
112 07:49:07.443899 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-raise
113 07:49:07.444013 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-reference
114 07:49:07.444140 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-runner
115 07:49:07.444251 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-set
116 07:49:07.444359 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-test-shell
117 07:49:07.444471 Updating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-install-packages (oe)
118 07:49:07.444586 Updating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/bin/lava-installed-packages (oe)
119 07:49:07.444686 Creating /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/environment
120 07:49:07.444774 LAVA metadata
121 07:49:07.444844 - LAVA_JOB_ID=8119452
122 07:49:07.444913 - LAVA_DISPATCHER_IP=192.168.201.1
123 07:49:07.445018 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
124 07:49:07.445085 skipped lava-vland-overlay
125 07:49:07.445163 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 07:49:07.445247 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
127 07:49:07.445312 skipped lava-multinode-overlay
128 07:49:07.445387 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 07:49:07.445469 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
130 07:49:07.445547 Loading test definitions
131 07:49:07.445643 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
132 07:49:07.445721 Using /lava-8119452 at stage 0
133 07:49:07.445988 uuid=8119452_1.4.2.3.1 testdef=None
134 07:49:07.446087 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 07:49:07.446206 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
136 07:49:07.446706 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 07:49:07.446981 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
139 07:49:07.447600 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 07:49:07.447845 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
142 07:49:07.448424 runner path: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/0/tests/0_dmesg test_uuid 8119452_1.4.2.3.1
143 07:49:07.448578 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 07:49:07.448812 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
146 07:49:07.448885 Using /lava-8119452 at stage 1
147 07:49:07.449128 uuid=8119452_1.4.2.3.5 testdef=None
148 07:49:07.449224 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 07:49:07.449317 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
150 07:49:07.449761 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 07:49:07.449990 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
153 07:49:07.450584 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 07:49:07.450826 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
156 07:49:07.451449 runner path: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/1/tests/1_bootrr test_uuid 8119452_1.4.2.3.5
157 07:49:07.451593 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 07:49:07.451806 Creating lava-test-runner.conf files
160 07:49:07.451871 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/0 for stage 0
161 07:49:07.451953 - 0_dmesg
162 07:49:07.452028 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8119452/lava-overlay-7dlc_d97/lava-8119452/1 for stage 1
163 07:49:07.452111 - 1_bootrr
164 07:49:07.452207 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 07:49:07.452329 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
166 07:49:07.458492 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 07:49:07.458600 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
168 07:49:07.458692 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 07:49:07.458780 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 07:49:07.458867 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
171 07:49:07.641481 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 07:49:07.641853 start: 1.4.4 extract-modules (timeout 00:09:58) [common]
173 07:49:07.641972 extracting modules file /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8119452/extract-overlay-ramdisk-6d0djs3w/ramdisk
174 07:49:07.646148 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 07:49:07.646259 start: 1.4.5 apply-overlay-tftp (timeout 00:09:58) [common]
176 07:49:07.646357 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119452/compress-overlay-si1cgeoo/overlay-1.4.2.4.tar.gz to ramdisk
177 07:49:07.646462 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119452/compress-overlay-si1cgeoo/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8119452/extract-overlay-ramdisk-6d0djs3w/ramdisk
178 07:49:07.650318 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 07:49:07.650460 start: 1.4.6 configure-preseed-file (timeout 00:09:58) [common]
180 07:49:07.650557 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 07:49:07.650653 start: 1.4.7 compress-ramdisk (timeout 00:09:58) [common]
182 07:49:07.650733 Building ramdisk /var/lib/lava/dispatcher/tmp/8119452/extract-overlay-ramdisk-6d0djs3w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8119452/extract-overlay-ramdisk-6d0djs3w/ramdisk
183 07:49:07.713947 >> 48008 blocks
184 07:49:08.476008 rename /var/lib/lava/dispatcher/tmp/8119452/extract-overlay-ramdisk-6d0djs3w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
185 07:49:08.476400 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 07:49:08.476524 start: 1.4.8 prepare-kernel (timeout 00:09:57) [common]
187 07:49:08.476627 start: 1.4.8.1 prepare-fit (timeout 00:09:57) [common]
188 07:49:08.476717 No mkimage arch provided, not using FIT.
189 07:49:08.476806 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 07:49:08.476891 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 07:49:08.476995 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 07:49:08.477087 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:57) [common]
193 07:49:08.477164 No LXC device requested
194 07:49:08.477244 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 07:49:08.477332 start: 1.6 deploy-device-env (timeout 00:09:57) [common]
196 07:49:08.477412 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 07:49:08.477485 Checking files for TFTP limit of 4294967296 bytes.
198 07:49:08.477857 end: 1 tftp-deploy (duration 00:00:03) [common]
199 07:49:08.477966 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 07:49:08.478062 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 07:49:08.478189 substitutions:
202 07:49:08.478257 - {DTB}: None
203 07:49:08.478324 - {INITRD}: 8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
204 07:49:08.478385 - {KERNEL}: 8119452/tftp-deploy-pti9jti9/kernel/bzImage
205 07:49:08.478444 - {LAVA_MAC}: None
206 07:49:08.478502 - {PRESEED_CONFIG}: None
207 07:49:08.478559 - {PRESEED_LOCAL}: None
208 07:49:08.478616 - {RAMDISK}: 8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
209 07:49:08.478672 - {ROOT_PART}: None
210 07:49:08.478728 - {ROOT}: None
211 07:49:08.478785 - {SERVER_IP}: 192.168.201.1
212 07:49:08.478840 - {TEE}: None
213 07:49:08.478905 Parsed boot commands:
214 07:49:08.478963 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 07:49:08.479110 Parsed boot commands: tftpboot 192.168.201.1 8119452/tftp-deploy-pti9jti9/kernel/bzImage 8119452/tftp-deploy-pti9jti9/kernel/cmdline 8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
216 07:49:08.479205 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 07:49:08.479296 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 07:49:08.479398 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 07:49:08.479501 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 07:49:08.479574 Not connected, no need to disconnect.
221 07:49:08.479652 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 07:49:08.479734 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 07:49:08.479805 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-12'
224 07:49:08.482360 Setting prompt string to ['lava-test: # ']
225 07:49:08.482633 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 07:49:08.482735 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 07:49:08.482831 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 07:49:08.482930 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 07:49:08.483104 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-12' '--port=1' '--command=reboot'
230 07:49:08.501826 >> Command sent successfully.
231 07:49:08.503743 Returned 0 in 0 seconds
232 07:49:08.604525 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 07:49:08.605083 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 07:49:08.605185 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 07:49:08.605273 Setting prompt string to 'Starting depthcharge on Voema...'
237 07:49:08.605339 Changing prompt to 'Starting depthcharge on Voema...'
238 07:49:08.605407 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
239 07:49:08.605685 [Enter `^Ec?' for help]
240 07:49:16.435417
241 07:49:16.436066
242 07:49:16.445555 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
243 07:49:16.448751 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
244 07:49:16.455526 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
245 07:49:16.458829 CPU: AES supported, TXT NOT supported, VT supported
246 07:49:16.465858 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
247 07:49:16.468974 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
248 07:49:16.475826 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
249 07:49:16.479029 VBOOT: Loading verstage.
250 07:49:16.482509 FMAP: Found "FLASH" version 1.1 at 0x1804000.
251 07:49:16.489209 FMAP: base = 0x0 size = 0x2000000 #areas = 32
252 07:49:16.492446 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
253 07:49:16.503069 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
254 07:49:16.508787 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
255 07:49:16.509321
256 07:49:16.509718
257 07:49:16.519502 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
258 07:49:16.536291 Probing TPM: . done!
259 07:49:16.539402 TPM ready after 0 ms
260 07:49:16.543174 Connected to device vid:did:rid of 1ae0:0028:00
261 07:49:16.553905 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
262 07:49:16.560428 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
263 07:49:16.563911 Initialized TPM device CR50 revision 0
264 07:49:16.623850 tlcl_send_startup: Startup return code is 0
265 07:49:16.624436 TPM: setup succeeded
266 07:49:16.639501 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
267 07:49:16.653366 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
268 07:49:16.666254 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
269 07:49:16.676057 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
270 07:49:16.679659 Chrome EC: UHEPI supported
271 07:49:16.683404 Phase 1
272 07:49:16.686788 FMAP: area GBB found @ 1805000 (458752 bytes)
273 07:49:16.696229 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
274 07:49:16.703240 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
275 07:49:16.709500 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
276 07:49:16.716239 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
277 07:49:16.719382 Recovery requested (1009000e)
278 07:49:16.722340 TPM: Extending digest for VBOOT: boot mode into PCR 0
279 07:49:16.734746 tlcl_extend: response is 0
280 07:49:16.740950 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
281 07:49:16.750738 tlcl_extend: response is 0
282 07:49:16.757619 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
283 07:49:16.764062 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
284 07:49:16.770468 BS: verstage times (exec / console): total (unknown) / 142 ms
285 07:49:16.770974
286 07:49:16.771334
287 07:49:16.783643 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
288 07:49:16.790410 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
289 07:49:16.794434 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
290 07:49:16.796997 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
291 07:49:16.803742 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
292 07:49:16.806951 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
293 07:49:16.810686 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
294 07:49:16.813700 TCO_STS: 0000 0000
295 07:49:16.817146 GEN_PMCON: d0015038 00002200
296 07:49:16.820122 GBLRST_CAUSE: 00000000 00000000
297 07:49:16.820566 HPR_CAUSE0: 00000000
298 07:49:16.823886
299 07:49:16.824334 prev_sleep_state 5
300 07:49:16.826639 Boot Count incremented to 10479
301 07:49:16.833469 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
302 07:49:16.840653 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
303 07:49:16.847352 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
304 07:49:16.850813
305 07:49:16.856861 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
306 07:49:16.859983 Chrome EC: UHEPI supported
307 07:49:16.866479 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
308 07:49:16.877542 Probing TPM: done!
309 07:49:16.884623 Connected to device vid:did:rid of 1ae0:0028:00
310 07:49:16.894173 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
311 07:49:16.897749 Initialized TPM device CR50 revision 0
312 07:49:16.912576 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
313 07:49:16.919126 MRC: Hash idx 0x100b comparison successful.
314 07:49:16.922646 MRC cache found, size faa8
315 07:49:16.923235 bootmode is set to: 2
316 07:49:16.925761 SPD index = 2
317 07:49:16.932310 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
318 07:49:16.935631 SPD: module type is LPDDR4X
319 07:49:16.939674 SPD: module part number is MT53D1G64D4NW-046
320 07:49:16.945944 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
321 07:49:16.952658 SPD: device width 16 bits, bus width 16 bits
322 07:49:16.955315 SPD: module size is 2048 MB (per channel)
323 07:49:17.386200 CBMEM:
324 07:49:17.389197 IMD: root @ 0x76fff000 254 entries.
325 07:49:17.392546 IMD: root @ 0x76ffec00 62 entries.
326 07:49:17.395824 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
327 07:49:17.402149 FMAP: area RW_VPD found @ f35000 (8192 bytes)
328 07:49:17.405770 External stage cache:
329 07:49:17.409200 IMD: root @ 0x7b3ff000 254 entries.
330 07:49:17.411980 IMD: root @ 0x7b3fec00 62 entries.
331 07:49:17.427427 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
332 07:49:17.434246 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
333 07:49:17.440237 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
334 07:49:17.454305 MRC: 'RECOVERY_MRC_CACHE' does not need update.
335 07:49:17.461527 cse_lite: Skip switching to RW in the recovery path
336 07:49:17.462137 8 DIMMs found
337 07:49:17.462538 SMM Memory Map
338 07:49:17.464293 SMRAM : 0x7b000000 0x800000
339 07:49:17.467175
340 07:49:17.470452 Subregion 0: 0x7b000000 0x200000
341 07:49:17.474064 Subregion 1: 0x7b200000 0x200000
342 07:49:17.477621 Subregion 2: 0x7b400000 0x400000
343 07:49:17.478207 top_of_ram = 0x77000000
344 07:49:17.484216 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
345 07:49:17.490537 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
346 07:49:17.494373 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
347 07:49:17.500576 MTRR Range: Start=ff000000 End=0 (Size 1000000)
348 07:49:17.506952 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
349 07:49:17.513786 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
350 07:49:17.524109 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
351 07:49:17.527579 Processing 211 relocs. Offset value of 0x74c0b000
352 07:49:17.530375
353 07:49:17.537196 BS: romstage times (exec / console): total (unknown) / 277 ms
354 07:49:17.543045
355 07:49:17.543637
356 07:49:17.550463 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
357 07:49:17.557401 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
358 07:49:17.564025 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
359 07:49:17.570632 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
360 07:49:17.580347 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
361 07:49:17.586832 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
362 07:49:17.629742 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
363 07:49:17.636280 Processing 5008 relocs. Offset value of 0x75d98000
364 07:49:17.639574 BS: postcar times (exec / console): total (unknown) / 59 ms
365 07:49:17.640161
366 07:49:17.643537
367 07:49:17.644139
368 07:49:17.652492 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
369 07:49:17.653066 Normal boot
370 07:49:17.655958 FW_CONFIG value is 0x804c02
371 07:49:17.659358 PCI: 00:07.0 disabled by fw_config
372 07:49:17.662780 PCI: 00:07.1 disabled by fw_config
373 07:49:17.665909 PCI: 00:0d.2 disabled by fw_config
374 07:49:17.669234
375 07:49:17.672891 PCI: 00:1c.7 disabled by fw_config
376 07:49:17.675820 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
377 07:49:17.682558 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
378 07:49:17.689229 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
379 07:49:17.692713 GENERIC: 0.0 disabled by fw_config
380 07:49:17.695351 GENERIC: 1.0 disabled by fw_config
381 07:49:17.698572 fw_config match found: DB_USB=USB3_ACTIVE
382 07:49:17.702561 fw_config match found: DB_USB=USB3_ACTIVE
383 07:49:17.705606 fw_config match found: DB_USB=USB3_ACTIVE
384 07:49:17.711892 fw_config match found: DB_USB=USB3_ACTIVE
385 07:49:17.715377 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
386 07:49:17.725121 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
387 07:49:17.732074 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
388 07:49:17.738290 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
389 07:49:17.741502 microcode: sig=0x806c1 pf=0x80 revision=0x86
390 07:49:17.745038
391 07:49:17.748476 microcode: Update skipped, already up-to-date
392 07:49:17.755130 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
393 07:49:17.782802 Detected 4 core, 8 thread CPU.
394 07:49:17.786362 Setting up SMI for CPU
395 07:49:17.789769 IED base = 0x7b400000
396 07:49:17.789863 IED size = 0x00400000
397 07:49:17.792937 Will perform SMM setup.
398 07:49:17.799326 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
399 07:49:17.806344 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
400 07:49:17.813100 Processing 16 relocs. Offset value of 0x00030000
401 07:49:17.816333 Attempting to start 7 APs
402 07:49:17.819173 Waiting for 10ms after sending INIT.
403 07:49:17.834876 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
404 07:49:17.838208 AP: slot 7 apic_id 3.
405 07:49:17.841395 AP: slot 4 apic_id 2.
406 07:49:17.841606 AP: slot 6 apic_id 6.
407 07:49:17.844692 AP: slot 3 apic_id 7.
408 07:49:17.844828 done.
409 07:49:17.848117 AP: slot 5 apic_id 4.
410 07:49:17.848260 AP: slot 2 apic_id 5.
411 07:49:17.851382
412 07:49:17.855058 Waiting for 2nd SIPI to complete...done.
413 07:49:17.862036 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
414 07:49:17.867635 Processing 13 relocs. Offset value of 0x00038000
415 07:49:17.871141 Unable to locate Global NVS
416 07:49:17.878209 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
417 07:49:17.881694 Installing permanent SMM handler to 0x7b000000
418 07:49:17.891176 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
419 07:49:17.894622 Processing 794 relocs. Offset value of 0x7b010000
420 07:49:17.904380 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
421 07:49:17.908330 Processing 13 relocs. Offset value of 0x7b008000
422 07:49:17.914446 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
423 07:49:17.920953 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
424 07:49:17.927917 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
425 07:49:17.930599 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
426 07:49:17.937501 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
427 07:49:17.944134 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
428 07:49:17.951159 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
429 07:49:17.954075 Unable to locate Global NVS
430 07:49:17.960940 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
431 07:49:17.963672 Clearing SMI status registers
432 07:49:17.968043 SMI_STS: PM1
433 07:49:17.968485 PM1_STS: PWRBTN
434 07:49:17.974067 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
435 07:49:17.977397 In relocation handler: CPU 0
436 07:49:17.980292 New SMBASE=0x7b000000 IEDBASE=0x7b400000
437 07:49:17.986875 Writing SMRR. base = 0x7b000006, mask=0xff800c00
438 07:49:17.990278 Relocation complete.
439 07:49:17.996910 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
440 07:49:18.000340 In relocation handler: CPU 1
441 07:49:18.004128 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
442 07:49:18.006718 Relocation complete.
443 07:49:18.013506 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
444 07:49:18.016803 In relocation handler: CPU 7
445 07:49:18.020290 New SMBASE=0x7affe400 IEDBASE=0x7b400000
446 07:49:18.023093 Relocation complete.
447 07:49:18.030417 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
448 07:49:18.033469 In relocation handler: CPU 4
449 07:49:18.036449 New SMBASE=0x7afff000 IEDBASE=0x7b400000
450 07:49:18.040090 Writing SMRR. base = 0x7b000006, mask=0xff800c00
451 07:49:18.043323 Relocation complete.
452 07:49:18.049853 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
453 07:49:18.052804 In relocation handler: CPU 5
454 07:49:18.056442 New SMBASE=0x7affec00 IEDBASE=0x7b400000
455 07:49:18.063061 Writing SMRR. base = 0x7b000006, mask=0xff800c00
456 07:49:18.063613 Relocation complete.
457 07:49:18.073607 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
458 07:49:18.076380 In relocation handler: CPU 2
459 07:49:18.080037 New SMBASE=0x7afff800 IEDBASE=0x7b400000
460 07:49:18.080590 Relocation complete.
461 07:49:18.089389 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
462 07:49:18.089836 In relocation handler: CPU 6
463 07:49:18.093406
464 07:49:18.096017 New SMBASE=0x7affe800 IEDBASE=0x7b400000
465 07:49:18.099560 Writing SMRR. base = 0x7b000006, mask=0xff800c00
466 07:49:18.102730 Relocation complete.
467 07:49:18.109684 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
468 07:49:18.112796 In relocation handler: CPU 3
469 07:49:18.116532 New SMBASE=0x7afff400 IEDBASE=0x7b400000
470 07:49:18.119190 Relocation complete.
471 07:49:18.122490 Initializing CPU #0
472 07:49:18.125969 CPU: vendor Intel device 806c1
473 07:49:18.129534 CPU: family 06, model 8c, stepping 01
474 07:49:18.132436 Clearing out pending MCEs
475 07:49:18.132876 Setting up local APIC...
476 07:49:18.135756 apic_id: 0x00 done.
477 07:49:18.139160 Turbo is available but hidden
478 07:49:18.142831 Turbo is available and visible
479 07:49:18.145550 microcode: Update skipped, already up-to-date
480 07:49:18.149227 CPU #0 initialized
481 07:49:18.152412 Initializing CPU #6
482 07:49:18.152963 Initializing CPU #3
483 07:49:18.155994 CPU: vendor Intel device 806c1
484 07:49:18.158933 CPU: family 06, model 8c, stepping 01
485 07:49:18.162503 CPU: vendor Intel device 806c1
486 07:49:18.165470 CPU: family 06, model 8c, stepping 01
487 07:49:18.168562 Clearing out pending MCEs
488 07:49:18.171802 Clearing out pending MCEs
489 07:49:18.176358 Setting up local APIC...
490 07:49:18.176868 Initializing CPU #7
491 07:49:18.178590 Initializing CPU #4
492 07:49:18.182035 CPU: vendor Intel device 806c1
493 07:49:18.185477 CPU: family 06, model 8c, stepping 01
494 07:49:18.188412 CPU: vendor Intel device 806c1
495 07:49:18.191822 CPU: family 06, model 8c, stepping 01
496 07:49:18.195533 Clearing out pending MCEs
497 07:49:18.198607 Clearing out pending MCEs
498 07:49:18.199192 Setting up local APIC...
499 07:49:18.201484
500 07:49:18.201976 Initializing CPU #5
501 07:49:18.204924 Initializing CPU #2
502 07:49:18.208505 CPU: vendor Intel device 806c1
503 07:49:18.212247 CPU: family 06, model 8c, stepping 01
504 07:49:18.215938 CPU: vendor Intel device 806c1
505 07:49:18.219555 CPU: family 06, model 8c, stepping 01
506 07:49:18.220009 Clearing out pending MCEs
507 07:49:18.222626 Clearing out pending MCEs
508 07:49:18.226164 Setting up local APIC...
509 07:49:18.229702 apic_id: 0x03 done.
510 07:49:18.230148 Setting up local APIC...
511 07:49:18.232724 apic_id: 0x04 done.
512 07:49:18.236389 Setting up local APIC...
513 07:49:18.236932 apic_id: 0x06 done.
514 07:49:18.239808 Setting up local APIC...
515 07:49:18.246033 microcode: Update skipped, already up-to-date
516 07:49:18.246586 apic_id: 0x02 done.
517 07:49:18.249435 CPU #7 initialized
518 07:49:18.253031 microcode: Update skipped, already up-to-date
519 07:49:18.255864 apic_id: 0x05 done.
520 07:49:18.260204 microcode: Update skipped, already up-to-date
521 07:49:18.265919 microcode: Update skipped, already up-to-date
522 07:49:18.266466 CPU #5 initialized
523 07:49:18.269506 CPU #2 initialized
524 07:49:18.272794 microcode: Update skipped, already up-to-date
525 07:49:18.275819 apic_id: 0x07 done.
526 07:49:18.276265 CPU #6 initialized
527 07:49:18.282975 microcode: Update skipped, already up-to-date
528 07:49:18.283518 Initializing CPU #1
529 07:49:18.286229 CPU #4 initialized
530 07:49:18.289398 CPU #3 initialized
531 07:49:18.289846 CPU: vendor Intel device 806c1
532 07:49:18.295829 CPU: family 06, model 8c, stepping 01
533 07:49:18.296383 Clearing out pending MCEs
534 07:49:18.299262 Setting up local APIC...
535 07:49:18.302783 apic_id: 0x01 done.
536 07:49:18.305557 microcode: Update skipped, already up-to-date
537 07:49:18.308961 CPU #1 initialized
538 07:49:18.312246 bsp_do_flight_plan done after 454 msecs.
539 07:49:18.316399 CPU: frequency set to 4400 MHz
540 07:49:18.318856 Enabling SMIs.
541 07:49:18.325668 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
542 07:49:18.339992 SATAXPCIE1 indicates PCIe NVMe is present
543 07:49:18.343440 Probing TPM: done!
544 07:49:18.346819 Connected to device vid:did:rid of 1ae0:0028:00
545 07:49:18.357346 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
546 07:49:18.360508 Initialized TPM device CR50 revision 0
547 07:49:18.363889 Enabling S0i3.4
548 07:49:18.370801 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
549 07:49:18.373686 Found a VBT of 8704 bytes after decompression
550 07:49:18.380390 cse_lite: CSE RO boot. HybridStorageMode disabled
551 07:49:18.386832 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
552 07:49:18.462806 FSPS returned 0
553 07:49:18.466253 Executing Phase 1 of FspMultiPhaseSiInit
554 07:49:18.475645 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
555 07:49:18.479218 port C0 DISC req: usage 1 usb3 1 usb2 5
556 07:49:18.482773 Raw Buffer output 0 00000511
557 07:49:18.485405 Raw Buffer output 1 00000000
558 07:49:18.489887 pmc_send_ipc_cmd succeeded
559 07:49:18.492900 port C1 DISC req: usage 1 usb3 2 usb2 3
560 07:49:18.496467
561 07:49:18.497073 Raw Buffer output 0 00000321
562 07:49:18.499563 Raw Buffer output 1 00000000
563 07:49:18.503444 pmc_send_ipc_cmd succeeded
564 07:49:18.508793 Detected 4 core, 8 thread CPU.
565 07:49:18.512256 Detected 4 core, 8 thread CPU.
566 07:49:18.712695 Display FSP Version Info HOB
567 07:49:18.715906 Reference Code - CPU = a.0.4c.31
568 07:49:18.719488 uCode Version = 0.0.0.86
569 07:49:18.721783 TXT ACM version = ff.ff.ff.ffff
570 07:49:18.725858 Reference Code - ME = a.0.4c.31
571 07:49:18.729004 MEBx version = 0.0.0.0
572 07:49:18.731928 ME Firmware Version = Consumer SKU
573 07:49:18.735106 Reference Code - PCH = a.0.4c.31
574 07:49:18.738935 PCH-CRID Status = Disabled
575 07:49:18.742412 PCH-CRID Original Value = ff.ff.ff.ffff
576 07:49:18.745354 PCH-CRID New Value = ff.ff.ff.ffff
577 07:49:18.748594 OPROM - RST - RAID = ff.ff.ff.ffff
578 07:49:18.752311 PCH Hsio Version = 4.0.0.0
579 07:49:18.755634 Reference Code - SA - System Agent = a.0.4c.31
580 07:49:18.759093 Reference Code - MRC = 2.0.0.1
581 07:49:18.762552 SA - PCIe Version = a.0.4c.31
582 07:49:18.765922 SA-CRID Status = Disabled
583 07:49:18.768540 SA-CRID Original Value = 0.0.0.1
584 07:49:18.772026 SA-CRID New Value = 0.0.0.1
585 07:49:18.775202 OPROM - VBIOS = ff.ff.ff.ffff
586 07:49:18.778787 IO Manageability Engine FW Version = 11.1.4.0
587 07:49:18.782446 PHY Build Version = 0.0.0.e0
588 07:49:18.785289 Thunderbolt(TM) FW Version = 0.0.0.0
589 07:49:18.792513 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
590 07:49:18.795603 ITSS IRQ Polarities Before:
591 07:49:18.796083 IPC0: 0xffffffff
592 07:49:18.799506 IPC1: 0xffffffff
593 07:49:18.799983 IPC2: 0xffffffff
594 07:49:18.802298 IPC3: 0xffffffff
595 07:49:18.802828 ITSS IRQ Polarities After:
596 07:49:18.805710 IPC0: 0xffffffff
597 07:49:18.809432 IPC1: 0xffffffff
598 07:49:18.810004 IPC2: 0xffffffff
599 07:49:18.812458 IPC3: 0xffffffff
600 07:49:18.815642 Found PCIe Root Port #9 at PCI: 00:1d.0.
601 07:49:18.825585 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
602 07:49:18.839238 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
603 07:49:18.852035 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
604 07:49:18.859161 BS: BS_DEV_INIT_CHIPS run times (exec / console): 291 / 236 ms
605 07:49:18.859750 Enumerating buses...
606 07:49:18.865305 Show all devs... Before device enumeration.
607 07:49:18.865894 Root Device: enabled 1
608 07:49:18.869070 DOMAIN: 0000: enabled 1
609 07:49:18.872138 CPU_CLUSTER: 0: enabled 1
610 07:49:18.875557 PCI: 00:00.0: enabled 1
611 07:49:18.876041 PCI: 00:02.0: enabled 1
612 07:49:18.878514 PCI: 00:04.0: enabled 1
613 07:49:18.882286 PCI: 00:05.0: enabled 1
614 07:49:18.886149 PCI: 00:06.0: enabled 0
615 07:49:18.886741 PCI: 00:07.0: enabled 0
616 07:49:18.888607 PCI: 00:07.1: enabled 0
617 07:49:18.891925 PCI: 00:07.2: enabled 0
618 07:49:18.892511 PCI: 00:07.3: enabled 0
619 07:49:18.895207
620 07:49:18.895695 PCI: 00:08.0: enabled 1
621 07:49:18.899047 PCI: 00:09.0: enabled 0
622 07:49:18.901865 PCI: 00:0a.0: enabled 0
623 07:49:18.902352 PCI: 00:0d.0: enabled 1
624 07:49:18.905010 PCI: 00:0d.1: enabled 0
625 07:49:18.908752 PCI: 00:0d.2: enabled 0
626 07:49:18.912135 PCI: 00:0d.3: enabled 0
627 07:49:18.912736 PCI: 00:0e.0: enabled 0
628 07:49:18.915350 PCI: 00:10.2: enabled 1
629 07:49:18.918959 PCI: 00:10.6: enabled 0
630 07:49:18.921707 PCI: 00:10.7: enabled 0
631 07:49:18.922293 PCI: 00:12.0: enabled 0
632 07:49:18.925256 PCI: 00:12.6: enabled 0
633 07:49:18.928177 PCI: 00:13.0: enabled 0
634 07:49:18.931339 PCI: 00:14.0: enabled 1
635 07:49:18.931827 PCI: 00:14.1: enabled 0
636 07:49:18.935138 PCI: 00:14.2: enabled 1
637 07:49:18.937890 PCI: 00:14.3: enabled 1
638 07:49:18.941420 PCI: 00:15.0: enabled 1
639 07:49:18.941908 PCI: 00:15.1: enabled 1
640 07:49:18.944810 PCI: 00:15.2: enabled 1
641 07:49:18.948017 PCI: 00:15.3: enabled 1
642 07:49:18.948508 PCI: 00:16.0: enabled 1
643 07:49:18.951419 PCI: 00:16.1: enabled 0
644 07:49:18.954703 PCI: 00:16.2: enabled 0
645 07:49:18.957828 PCI: 00:16.3: enabled 0
646 07:49:18.958270 PCI: 00:16.4: enabled 0
647 07:49:18.961648 PCI: 00:16.5: enabled 0
648 07:49:18.965169 PCI: 00:17.0: enabled 1
649 07:49:18.968209 PCI: 00:19.0: enabled 0
650 07:49:18.968701 PCI: 00:19.1: enabled 1
651 07:49:18.971270 PCI: 00:19.2: enabled 0
652 07:49:18.974679 PCI: 00:1c.0: enabled 1
653 07:49:18.978454 PCI: 00:1c.1: enabled 0
654 07:49:18.979084 PCI: 00:1c.2: enabled 0
655 07:49:18.981823 PCI: 00:1c.3: enabled 0
656 07:49:18.984881 PCI: 00:1c.4: enabled 0
657 07:49:18.985478 PCI: 00:1c.5: enabled 0
658 07:49:18.988226
659 07:49:18.988721 PCI: 00:1c.6: enabled 1
660 07:49:18.991237 PCI: 00:1c.7: enabled 0
661 07:49:18.994842 PCI: 00:1d.0: enabled 1
662 07:49:18.995501 PCI: 00:1d.1: enabled 0
663 07:49:18.998346 PCI: 00:1d.2: enabled 1
664 07:49:19.001207 PCI: 00:1d.3: enabled 0
665 07:49:19.004827 PCI: 00:1e.0: enabled 1
666 07:49:19.005290 PCI: 00:1e.1: enabled 0
667 07:49:19.007839 PCI: 00:1e.2: enabled 1
668 07:49:19.011434 PCI: 00:1e.3: enabled 1
669 07:49:19.014978 PCI: 00:1f.0: enabled 1
670 07:49:19.015459 PCI: 00:1f.1: enabled 0
671 07:49:19.018131 PCI: 00:1f.2: enabled 1
672 07:49:19.021377 PCI: 00:1f.3: enabled 1
673 07:49:19.025024 PCI: 00:1f.4: enabled 0
674 07:49:19.025649 PCI: 00:1f.5: enabled 1
675 07:49:19.027352 PCI: 00:1f.6: enabled 0
676 07:49:19.031217 PCI: 00:1f.7: enabled 0
677 07:49:19.031698 APIC: 00: enabled 1
678 07:49:19.034802 GENERIC: 0.0: enabled 1
679 07:49:19.037825 GENERIC: 0.0: enabled 1
680 07:49:19.040777 GENERIC: 1.0: enabled 1
681 07:49:19.041264 GENERIC: 0.0: enabled 1
682 07:49:19.044473 GENERIC: 1.0: enabled 1
683 07:49:19.047696 USB0 port 0: enabled 1
684 07:49:19.051056 GENERIC: 0.0: enabled 1
685 07:49:19.051497 USB0 port 0: enabled 1
686 07:49:19.054114 GENERIC: 0.0: enabled 1
687 07:49:19.057822 I2C: 00:1a: enabled 1
688 07:49:19.058263 I2C: 00:31: enabled 1
689 07:49:19.060871 I2C: 00:32: enabled 1
690 07:49:19.064233 I2C: 00:10: enabled 1
691 07:49:19.064691 I2C: 00:15: enabled 1
692 07:49:19.067368 GENERIC: 0.0: enabled 0
693 07:49:19.070921 GENERIC: 1.0: enabled 0
694 07:49:19.074246 GENERIC: 0.0: enabled 1
695 07:49:19.074685 SPI: 00: enabled 1
696 07:49:19.077321 SPI: 00: enabled 1
697 07:49:19.077769 PNP: 0c09.0: enabled 1
698 07:49:19.080725 GENERIC: 0.0: enabled 1
699 07:49:19.083977 USB3 port 0: enabled 1
700 07:49:19.086866 USB3 port 1: enabled 1
701 07:49:19.087355 USB3 port 2: enabled 0
702 07:49:19.090503 USB3 port 3: enabled 0
703 07:49:19.094144 USB2 port 0: enabled 0
704 07:49:19.094592 USB2 port 1: enabled 1
705 07:49:19.097110
706 07:49:19.097648 USB2 port 2: enabled 1
707 07:49:19.100589 USB2 port 3: enabled 0
708 07:49:19.103675 USB2 port 4: enabled 1
709 07:49:19.104139 USB2 port 5: enabled 0
710 07:49:19.107514 USB2 port 6: enabled 0
711 07:49:19.110171 USB2 port 7: enabled 0
712 07:49:19.110618 USB2 port 8: enabled 0
713 07:49:19.113960 USB2 port 9: enabled 0
714 07:49:19.117214 USB3 port 0: enabled 0
715 07:49:19.120039 USB3 port 1: enabled 1
716 07:49:19.120531 USB3 port 2: enabled 0
717 07:49:19.123828 USB3 port 3: enabled 0
718 07:49:19.127141 GENERIC: 0.0: enabled 1
719 07:49:19.127699 GENERIC: 1.0: enabled 1
720 07:49:19.130319 APIC: 01: enabled 1
721 07:49:19.133587 APIC: 05: enabled 1
722 07:49:19.134182 APIC: 07: enabled 1
723 07:49:19.137028 APIC: 02: enabled 1
724 07:49:19.140396 APIC: 04: enabled 1
725 07:49:19.140889 APIC: 06: enabled 1
726 07:49:19.143835 APIC: 03: enabled 1
727 07:49:19.144419 Compare with tree...
728 07:49:19.147006 Root Device: enabled 1
729 07:49:19.150107 DOMAIN: 0000: enabled 1
730 07:49:19.153417 PCI: 00:00.0: enabled 1
731 07:49:19.156669 PCI: 00:02.0: enabled 1
732 07:49:19.157160 PCI: 00:04.0: enabled 1
733 07:49:19.159688 GENERIC: 0.0: enabled 1
734 07:49:19.163381 PCI: 00:05.0: enabled 1
735 07:49:19.166353 PCI: 00:06.0: enabled 0
736 07:49:19.169525 PCI: 00:07.0: enabled 0
737 07:49:19.170055 GENERIC: 0.0: enabled 1
738 07:49:19.173158 PCI: 00:07.1: enabled 0
739 07:49:19.176521 GENERIC: 1.0: enabled 1
740 07:49:19.179894 PCI: 00:07.2: enabled 0
741 07:49:19.183003 GENERIC: 0.0: enabled 1
742 07:49:19.183439 PCI: 00:07.3: enabled 0
743 07:49:19.186573 GENERIC: 1.0: enabled 1
744 07:49:19.189511 PCI: 00:08.0: enabled 1
745 07:49:19.193109 PCI: 00:09.0: enabled 0
746 07:49:19.196875 PCI: 00:0a.0: enabled 0
747 07:49:19.197417 PCI: 00:0d.0: enabled 1
748 07:49:19.199435 USB0 port 0: enabled 1
749 07:49:19.203093 USB3 port 0: enabled 1
750 07:49:19.206202 USB3 port 1: enabled 1
751 07:49:19.210291 USB3 port 2: enabled 0
752 07:49:19.213438 USB3 port 3: enabled 0
753 07:49:19.214257 PCI: 00:0d.1: enabled 0
754 07:49:19.215930 PCI: 00:0d.2: enabled 0
755 07:49:19.219622 GENERIC: 0.0: enabled 1
756 07:49:19.222762 PCI: 00:0d.3: enabled 0
757 07:49:19.226291 PCI: 00:0e.0: enabled 0
758 07:49:19.226944 PCI: 00:10.2: enabled 1
759 07:49:19.229146 PCI: 00:10.6: enabled 0
760 07:49:19.232469 PCI: 00:10.7: enabled 0
761 07:49:19.236464 PCI: 00:12.0: enabled 0
762 07:49:19.239870 PCI: 00:12.6: enabled 0
763 07:49:19.240369 PCI: 00:13.0: enabled 0
764 07:49:19.242592 PCI: 00:14.0: enabled 1
765 07:49:19.245638 USB0 port 0: enabled 1
766 07:49:19.249195 USB2 port 0: enabled 0
767 07:49:19.252924 USB2 port 1: enabled 1
768 07:49:19.253483 USB2 port 2: enabled 1
769 07:49:19.255667 USB2 port 3: enabled 0
770 07:49:19.259735 USB2 port 4: enabled 1
771 07:49:19.262569 USB2 port 5: enabled 0
772 07:49:19.265419 USB2 port 6: enabled 0
773 07:49:19.269231 USB2 port 7: enabled 0
774 07:49:19.269716 USB2 port 8: enabled 0
775 07:49:19.272192 USB2 port 9: enabled 0
776 07:49:19.275673 USB3 port 0: enabled 0
777 07:49:19.279022 USB3 port 1: enabled 1
778 07:49:19.281751 USB3 port 2: enabled 0
779 07:49:19.285090 USB3 port 3: enabled 0
780 07:49:19.285531 PCI: 00:14.1: enabled 0
781 07:49:19.288663 PCI: 00:14.2: enabled 1
782 07:49:19.292393 PCI: 00:14.3: enabled 1
783 07:49:19.295636 GENERIC: 0.0: enabled 1
784 07:49:19.298846 PCI: 00:15.0: enabled 1
785 07:49:19.299331 I2C: 00:1a: enabled 1
786 07:49:19.302033 I2C: 00:31: enabled 1
787 07:49:19.305453 I2C: 00:32: enabled 1
788 07:49:19.308960 PCI: 00:15.1: enabled 1
789 07:49:19.309552 I2C: 00:10: enabled 1
790 07:49:19.311905 PCI: 00:15.2: enabled 1
791 07:49:19.315224 PCI: 00:15.3: enabled 1
792 07:49:19.318666 PCI: 00:16.0: enabled 1
793 07:49:19.322293 PCI: 00:16.1: enabled 0
794 07:49:19.322919 PCI: 00:16.2: enabled 0
795 07:49:19.325305 PCI: 00:16.3: enabled 0
796 07:49:19.328348 PCI: 00:16.4: enabled 0
797 07:49:19.331469 PCI: 00:16.5: enabled 0
798 07:49:19.335301 PCI: 00:17.0: enabled 1
799 07:49:19.335894 PCI: 00:19.0: enabled 0
800 07:49:19.338338 PCI: 00:19.1: enabled 1
801 07:49:19.341424 I2C: 00:15: enabled 1
802 07:49:19.345320 PCI: 00:19.2: enabled 0
803 07:49:19.348372 PCI: 00:1d.0: enabled 1
804 07:49:19.348863 GENERIC: 0.0: enabled 1
805 07:49:19.351966 PCI: 00:1e.0: enabled 1
806 07:49:19.354848 PCI: 00:1e.1: enabled 0
807 07:49:19.358015 PCI: 00:1e.2: enabled 1
808 07:49:19.358514 SPI: 00: enabled 1
809 07:49:19.361857 PCI: 00:1e.3: enabled 1
810 07:49:19.364590 SPI: 00: enabled 1
811 07:49:19.368390 PCI: 00:1f.0: enabled 1
812 07:49:19.368838 PNP: 0c09.0: enabled 1
813 07:49:19.371412
814 07:49:19.371862 PCI: 00:1f.1: enabled 0
815 07:49:19.374652 PCI: 00:1f.2: enabled 1
816 07:49:19.378120 GENERIC: 0.0: enabled 1
817 07:49:19.381660 GENERIC: 0.0: enabled 1
818 07:49:19.384962 GENERIC: 1.0: enabled 1
819 07:49:19.385407 PCI: 00:1f.3: enabled 1
820 07:49:19.388259 PCI: 00:1f.4: enabled 0
821 07:49:19.439768 PCI: 00:1f.5: enabled 1
822 07:49:19.440349 PCI: 00:1f.6: enabled 0
823 07:49:19.441132 PCI: 00:1f.7: enabled 0
824 07:49:19.441531 CPU_CLUSTER: 0: enabled 1
825 07:49:19.441893 APIC: 00: enabled 1
826 07:49:19.442239 APIC: 01: enabled 1
827 07:49:19.442580 APIC: 05: enabled 1
828 07:49:19.442932 APIC: 07: enabled 1
829 07:49:19.443262 APIC: 02: enabled 1
830 07:49:19.443590 APIC: 04: enabled 1
831 07:49:19.444283 APIC: 06: enabled 1
832 07:49:19.444644 APIC: 03: enabled 1
833 07:49:19.444978 Root Device scanning...
834 07:49:19.445308 scan_static_bus for Root Device
835 07:49:19.445631 DOMAIN: 0000 enabled
836 07:49:19.445948 CPU_CLUSTER: 0 enabled
837 07:49:19.446266 DOMAIN: 0000 scanning...
838 07:49:19.446582 PCI: pci_scan_bus for bus 00
839 07:49:19.446929 PCI: 00:00.0 [8086/0000] ops
840 07:49:19.447258 PCI: 00:00.0 [8086/9a12] enabled
841 07:49:19.490348 PCI: 00:02.0 [8086/0000] bus ops
842 07:49:19.491027 PCI: 00:02.0 [8086/9a40] enabled
843 07:49:19.491433 PCI: 00:04.0 [8086/0000] bus ops
844 07:49:19.492195 PCI: 00:04.0 [8086/9a03] enabled
845 07:49:19.492589 PCI: 00:05.0 [8086/9a19] enabled
846 07:49:19.492950 PCI: 00:07.0 [0000/0000] hidden
847 07:49:19.493294 PCI: 00:08.0 [8086/9a11] enabled
848 07:49:19.493632 PCI: 00:0a.0 [8086/9a0d] disabled
849 07:49:19.493968 PCI: 00:0d.0 [8086/0000] bus ops
850 07:49:19.494299 PCI: 00:0d.0 [8086/9a13] enabled
851 07:49:19.494620 PCI: 00:14.0 [8086/0000] bus ops
852 07:49:19.495399 PCI: 00:14.0 [8086/a0ed] enabled
853 07:49:19.495777 PCI: 00:14.2 [8086/a0ef] enabled
854 07:49:19.496114 PCI: 00:14.3 [8086/0000] bus ops
855 07:49:19.496442 PCI: 00:14.3 [8086/a0f0] enabled
856 07:49:19.540413 PCI: 00:15.0 [8086/0000] bus ops
857 07:49:19.540995 PCI: 00:15.0 [8086/a0e8] enabled
858 07:49:19.541775 PCI: 00:15.1 [8086/0000] bus ops
859 07:49:19.542185 PCI: 00:15.1 [8086/a0e9] enabled
860 07:49:19.542547 PCI: 00:15.2 [8086/0000] bus ops
861 07:49:19.543307 PCI: 00:15.2 [8086/a0ea] enabled
862 07:49:19.543697 PCI: 00:15.3 [8086/0000] bus ops
863 07:49:19.544047 PCI: 00:15.3 [8086/a0eb] enabled
864 07:49:19.544386 PCI: 00:16.0 [8086/0000] ops
865 07:49:19.544718 PCI: 00:16.0 [8086/a0e0] enabled
866 07:49:19.545414 PCI: Static device PCI: 00:17.0 not found, disabling it.
867 07:49:19.545777 PCI: 00:19.0 [8086/0000] bus ops
868 07:49:19.546114 PCI: 00:19.0 [8086/a0c5] disabled
869 07:49:19.546438 PCI: 00:19.1 [8086/0000] bus ops
870 07:49:19.549028 PCI: 00:19.1 [8086/a0c6] enabled
871 07:49:19.549531 PCI: 00:1d.0 [8086/0000] bus ops
872 07:49:19.552545 PCI: 00:1d.0 [8086/a0b0] enabled
873 07:49:19.553051 PCI: 00:1e.0 [8086/0000] ops
874 07:49:19.555948 PCI: 00:1e.0 [8086/a0a8] enabled
875 07:49:19.559809 PCI: 00:1e.2 [8086/0000] bus ops
876 07:49:19.562951 PCI: 00:1e.2 [8086/a0aa] enabled
877 07:49:19.566043 PCI: 00:1e.3 [8086/0000] bus ops
878 07:49:19.569198 PCI: 00:1e.3 [8086/a0ab] enabled
879 07:49:19.572623 PCI: 00:1f.0 [8086/0000] bus ops
880 07:49:19.575871 PCI: 00:1f.0 [8086/a087] enabled
881 07:49:19.576400 RTC Init
882 07:49:19.579380 Set power on after power failure.
883 07:49:19.582664
884 07:49:19.583300 Disabling Deep S3
885 07:49:19.585799 Disabling Deep S3
886 07:49:19.586283 Disabling Deep S4
887 07:49:19.589139 Disabling Deep S4
888 07:49:19.589628 Disabling Deep S5
889 07:49:19.592896 Disabling Deep S5
890 07:49:19.596171 PCI: 00:1f.2 [0000/0000] hidden
891 07:49:19.599280 PCI: 00:1f.3 [8086/0000] bus ops
892 07:49:19.603192 PCI: 00:1f.3 [8086/a0c8] enabled
893 07:49:19.605546 PCI: 00:1f.5 [8086/0000] bus ops
894 07:49:19.609031 PCI: 00:1f.5 [8086/a0a4] enabled
895 07:49:19.612466 PCI: Leftover static devices:
896 07:49:19.613057 PCI: 00:10.2
897 07:49:19.616206 PCI: 00:10.6
898 07:49:19.616797 PCI: 00:10.7
899 07:49:19.617183 PCI: 00:06.0
900 07:49:19.619231 PCI: 00:07.1
901 07:49:19.619823 PCI: 00:07.2
902 07:49:19.622618 PCI: 00:07.3
903 07:49:19.623264 PCI: 00:09.0
904 07:49:19.626068 PCI: 00:0d.1
905 07:49:19.626653 PCI: 00:0d.2
906 07:49:19.627082 PCI: 00:0d.3
907 07:49:19.628725 PCI: 00:0e.0
908 07:49:19.629215 PCI: 00:12.0
909 07:49:19.632343 PCI: 00:12.6
910 07:49:19.632847 PCI: 00:13.0
911 07:49:19.633252 PCI: 00:14.1
912 07:49:19.635906 PCI: 00:16.1
913 07:49:19.636490 PCI: 00:16.2
914 07:49:19.639123 PCI: 00:16.3
915 07:49:19.639611 PCI: 00:16.4
916 07:49:19.640000 PCI: 00:16.5
917 07:49:19.642605
918 07:49:19.643163 PCI: 00:17.0
919 07:49:19.643554 PCI: 00:19.2
920 07:49:19.645667 PCI: 00:1e.1
921 07:49:19.646154 PCI: 00:1f.1
922 07:49:19.648755 PCI: 00:1f.4
923 07:49:19.649241 PCI: 00:1f.6
924 07:49:19.649622 PCI: 00:1f.7
925 07:49:19.651931 PCI: Check your devicetree.cb.
926 07:49:19.655727 PCI: 00:02.0 scanning...
927 07:49:19.658544 scan_generic_bus for PCI: 00:02.0
928 07:49:19.662062 scan_generic_bus for PCI: 00:02.0 done
929 07:49:19.669163 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
930 07:49:19.671733 PCI: 00:04.0 scanning...
931 07:49:19.675052 scan_generic_bus for PCI: 00:04.0
932 07:49:19.675621 GENERIC: 0.0 enabled
933 07:49:19.682055 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
934 07:49:19.688366 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
935 07:49:19.688810 PCI: 00:0d.0 scanning...
936 07:49:19.691913 scan_static_bus for PCI: 00:0d.0
937 07:49:19.695111 USB0 port 0 enabled
938 07:49:19.698871 USB0 port 0 scanning...
939 07:49:19.701634 scan_static_bus for USB0 port 0
940 07:49:19.702079 USB3 port 0 enabled
941 07:49:19.704894
942 07:49:19.705340 USB3 port 1 enabled
943 07:49:19.708533 USB3 port 2 disabled
944 07:49:19.708974 USB3 port 3 disabled
945 07:49:19.711203 USB3 port 0 scanning...
946 07:49:19.715002 scan_static_bus for USB3 port 0
947 07:49:19.718555 scan_static_bus for USB3 port 0 done
948 07:49:19.724842 scan_bus: bus USB3 port 0 finished in 6 msecs
949 07:49:19.725404 USB3 port 1 scanning...
950 07:49:19.728365 scan_static_bus for USB3 port 1
951 07:49:19.734642 scan_static_bus for USB3 port 1 done
952 07:49:19.738124 scan_bus: bus USB3 port 1 finished in 6 msecs
953 07:49:19.741499 scan_static_bus for USB0 port 0 done
954 07:49:19.745035 scan_bus: bus USB0 port 0 finished in 43 msecs
955 07:49:19.751552 scan_static_bus for PCI: 00:0d.0 done
956 07:49:19.754863 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
957 07:49:19.758303 PCI: 00:14.0 scanning...
958 07:49:19.761339 scan_static_bus for PCI: 00:14.0
959 07:49:19.764574 USB0 port 0 enabled
960 07:49:19.765061 USB0 port 0 scanning...
961 07:49:19.768343 scan_static_bus for USB0 port 0
962 07:49:19.771622 USB2 port 0 disabled
963 07:49:19.774569 USB2 port 1 enabled
964 07:49:19.775085 USB2 port 2 enabled
965 07:49:19.777752 USB2 port 3 disabled
966 07:49:19.778268 USB2 port 4 enabled
967 07:49:19.781279 USB2 port 5 disabled
968 07:49:19.784799 USB2 port 6 disabled
969 07:49:19.785304 USB2 port 7 disabled
970 07:49:19.788015 USB2 port 8 disabled
971 07:49:19.790752 USB2 port 9 disabled
972 07:49:19.791240 USB3 port 0 disabled
973 07:49:19.794324 USB3 port 1 enabled
974 07:49:19.797778 USB3 port 2 disabled
975 07:49:19.798329 USB3 port 3 disabled
976 07:49:19.801073 USB2 port 1 scanning...
977 07:49:19.804532 scan_static_bus for USB2 port 1
978 07:49:19.807715 scan_static_bus for USB2 port 1 done
979 07:49:19.814694 scan_bus: bus USB2 port 1 finished in 6 msecs
980 07:49:19.815520 USB2 port 2 scanning...
981 07:49:19.818121 scan_static_bus for USB2 port 2
982 07:49:19.820989 scan_static_bus for USB2 port 2 done
983 07:49:19.827711 scan_bus: bus USB2 port 2 finished in 6 msecs
984 07:49:19.830592 USB2 port 4 scanning...
985 07:49:19.834241 scan_static_bus for USB2 port 4
986 07:49:19.837438 scan_static_bus for USB2 port 4 done
987 07:49:19.840518 scan_bus: bus USB2 port 4 finished in 6 msecs
988 07:49:19.844612 USB3 port 1 scanning...
989 07:49:19.847180 scan_static_bus for USB3 port 1
990 07:49:19.850757 scan_static_bus for USB3 port 1 done
991 07:49:19.854529 scan_bus: bus USB3 port 1 finished in 6 msecs
992 07:49:19.860885 scan_static_bus for USB0 port 0 done
993 07:49:19.863980 scan_bus: bus USB0 port 0 finished in 93 msecs
994 07:49:19.867818 scan_static_bus for PCI: 00:14.0 done
995 07:49:19.873762 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
996 07:49:19.874348 PCI: 00:14.3 scanning...
997 07:49:19.877249 scan_static_bus for PCI: 00:14.3
998 07:49:19.880219 GENERIC: 0.0 enabled
999 07:49:19.883578 scan_static_bus for PCI: 00:14.3 done
1000 07:49:19.890165 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1001 07:49:19.890707 PCI: 00:15.0 scanning...
1002 07:49:19.893808 scan_static_bus for PCI: 00:15.0
1003 07:49:19.897301 I2C: 00:1a enabled
1004 07:49:19.900480 I2C: 00:31 enabled
1005 07:49:19.900975 I2C: 00:32 enabled
1006 07:49:19.903557 scan_static_bus for PCI: 00:15.0 done
1007 07:49:19.910088 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1008 07:49:19.913492 PCI: 00:15.1 scanning...
1009 07:49:19.917333 scan_static_bus for PCI: 00:15.1
1010 07:49:19.917779 I2C: 00:10 enabled
1011 07:49:19.920475 scan_static_bus for PCI: 00:15.1 done
1012 07:49:19.926940 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1013 07:49:19.930308 PCI: 00:15.2 scanning...
1014 07:49:19.933287 scan_static_bus for PCI: 00:15.2
1015 07:49:19.936732 scan_static_bus for PCI: 00:15.2 done
1016 07:49:19.939978 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1017 07:49:19.943377 PCI: 00:15.3 scanning...
1018 07:49:19.947021 scan_static_bus for PCI: 00:15.3
1019 07:49:19.949808 scan_static_bus for PCI: 00:15.3 done
1020 07:49:19.956370 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1021 07:49:19.956815 PCI: 00:19.1 scanning...
1022 07:49:19.960164 scan_static_bus for PCI: 00:19.1
1023 07:49:19.963180 I2C: 00:15 enabled
1024 07:49:19.966582 scan_static_bus for PCI: 00:19.1 done
1025 07:49:19.973330 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1026 07:49:19.973784 PCI: 00:1d.0 scanning...
1027 07:49:19.980024 do_pci_scan_bridge for PCI: 00:1d.0
1028 07:49:19.980471 PCI: pci_scan_bus for bus 01
1029 07:49:19.983347 PCI: 01:00.0 [15b7/5009] enabled
1030 07:49:19.986533 GENERIC: 0.0 enabled
1031 07:49:19.990167 Enabling Common Clock Configuration
1032 07:49:19.993205 L1 Sub-State supported from root port 29
1033 07:49:19.996659
1034 07:49:19.997115 L1 Sub-State Support = 0x5
1035 07:49:20.000186 CommonModeRestoreTime = 0x28
1036 07:49:20.006956 Power On Value = 0x16, Power On Scale = 0x0
1037 07:49:20.007524 ASPM: Enabled L1
1038 07:49:20.009767 PCIe: Max_Payload_Size adjusted to 128
1039 07:49:20.016409 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1040 07:49:20.016927 PCI: 00:1e.2 scanning...
1041 07:49:20.020226 scan_generic_bus for PCI: 00:1e.2
1042 07:49:20.023765
1043 07:49:20.024309 SPI: 00 enabled
1044 07:49:20.030335 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1045 07:49:20.033058 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1046 07:49:20.036820 PCI: 00:1e.3 scanning...
1047 07:49:20.039812 scan_generic_bus for PCI: 00:1e.3
1048 07:49:20.043301 SPI: 00 enabled
1049 07:49:20.050279 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1050 07:49:20.053592 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1051 07:49:20.054082 PCI: 00:1f.0 scanning...
1052 07:49:20.057206
1053 07:49:20.060573 scan_static_bus for PCI: 00:1f.0
1054 07:49:20.061177 PNP: 0c09.0 enabled
1055 07:49:20.063521 PNP: 0c09.0 scanning...
1056 07:49:20.067425 scan_static_bus for PNP: 0c09.0
1057 07:49:20.070051 scan_static_bus for PNP: 0c09.0 done
1058 07:49:20.073332 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1059 07:49:20.076966
1060 07:49:20.079903 scan_static_bus for PCI: 00:1f.0 done
1061 07:49:20.083169 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1062 07:49:20.087090 PCI: 00:1f.2 scanning...
1063 07:49:20.090022 scan_static_bus for PCI: 00:1f.2
1064 07:49:20.093543 GENERIC: 0.0 enabled
1065 07:49:20.093989 GENERIC: 0.0 scanning...
1066 07:49:20.096547 scan_static_bus for GENERIC: 0.0
1067 07:49:20.100074 GENERIC: 0.0 enabled
1068 07:49:20.103748 GENERIC: 1.0 enabled
1069 07:49:20.107078 scan_static_bus for GENERIC: 0.0 done
1070 07:49:20.109895 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1071 07:49:20.113646 scan_static_bus for PCI: 00:1f.2 done
1072 07:49:20.119732 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1073 07:49:20.122998 PCI: 00:1f.3 scanning...
1074 07:49:20.126368 scan_static_bus for PCI: 00:1f.3
1075 07:49:20.130144 scan_static_bus for PCI: 00:1f.3 done
1076 07:49:20.132839 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1077 07:49:20.136295 PCI: 00:1f.5 scanning...
1078 07:49:20.139524 scan_generic_bus for PCI: 00:1f.5
1079 07:49:20.142801 scan_generic_bus for PCI: 00:1f.5 done
1080 07:49:20.149550 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1081 07:49:20.153076 scan_bus: bus DOMAIN: 0000 finished in 716 msecs
1082 07:49:20.156274 scan_static_bus for Root Device done
1083 07:49:20.163227 scan_bus: bus Root Device finished in 736 msecs
1084 07:49:20.163755 done
1085 07:49:20.169457 BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 1295 ms
1086 07:49:20.172491 Chrome EC: UHEPI supported
1087 07:49:20.179391 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1088 07:49:20.185756 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1089 07:49:20.189054 SPI flash protection: WPSW=0 SRP0=1
1090 07:49:20.192870 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1091 07:49:20.199356 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1092 07:49:20.202905 found VGA at PCI: 00:02.0
1093 07:49:20.205860 Setting up VGA for PCI: 00:02.0
1094 07:49:20.209394 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1095 07:49:20.216074 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1096 07:49:20.216591 Allocating resources...
1097 07:49:20.219097 Reading resources...
1098 07:49:20.222456 Root Device read_resources bus 0 link: 0
1099 07:49:20.228846 DOMAIN: 0000 read_resources bus 0 link: 0
1100 07:49:20.232159 PCI: 00:04.0 read_resources bus 1 link: 0
1101 07:49:20.239199 PCI: 00:04.0 read_resources bus 1 link: 0 done
1102 07:49:20.242240 PCI: 00:0d.0 read_resources bus 0 link: 0
1103 07:49:20.248543 USB0 port 0 read_resources bus 0 link: 0
1104 07:49:20.251834 USB0 port 0 read_resources bus 0 link: 0 done
1105 07:49:20.258923 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1106 07:49:20.262382 PCI: 00:14.0 read_resources bus 0 link: 0
1107 07:49:20.265618 USB0 port 0 read_resources bus 0 link: 0
1108 07:49:20.272672 USB0 port 0 read_resources bus 0 link: 0 done
1109 07:49:20.275939 PCI: 00:14.0 read_resources bus 0 link: 0 done
1110 07:49:20.282574 PCI: 00:14.3 read_resources bus 0 link: 0
1111 07:49:20.285998 PCI: 00:14.3 read_resources bus 0 link: 0 done
1112 07:49:20.292984 PCI: 00:15.0 read_resources bus 0 link: 0
1113 07:49:20.295890 PCI: 00:15.0 read_resources bus 0 link: 0 done
1114 07:49:20.302586 PCI: 00:15.1 read_resources bus 0 link: 0
1115 07:49:20.306078 PCI: 00:15.1 read_resources bus 0 link: 0 done
1116 07:49:20.313405 PCI: 00:19.1 read_resources bus 0 link: 0
1117 07:49:20.316642 PCI: 00:19.1 read_resources bus 0 link: 0 done
1118 07:49:20.323845 PCI: 00:1d.0 read_resources bus 1 link: 0
1119 07:49:20.326018 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1120 07:49:20.332849 PCI: 00:1e.2 read_resources bus 2 link: 0
1121 07:49:20.336437 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1122 07:49:20.342735 PCI: 00:1e.3 read_resources bus 3 link: 0
1123 07:49:20.346286 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1124 07:49:20.353021 PCI: 00:1f.0 read_resources bus 0 link: 0
1125 07:49:20.355833 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1126 07:49:20.359451 PCI: 00:1f.2 read_resources bus 0 link: 0
1127 07:49:20.362726
1128 07:49:20.365580 GENERIC: 0.0 read_resources bus 0 link: 0
1129 07:49:20.369162 GENERIC: 0.0 read_resources bus 0 link: 0 done
1130 07:49:20.372521
1131 07:49:20.375536 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1132 07:49:20.382335 DOMAIN: 0000 read_resources bus 0 link: 0 done
1133 07:49:20.385427 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1134 07:49:20.392203 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1135 07:49:20.395286 Root Device read_resources bus 0 link: 0 done
1136 07:49:20.398820 Done reading resources.
1137 07:49:20.405280 Show resources in subtree (Root Device)...After reading.
1138 07:49:20.408924 Root Device child on link 0 DOMAIN: 0000
1139 07:49:20.411636 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1140 07:49:20.422108 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1141 07:49:20.431733 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1142 07:49:20.432303 PCI: 00:00.0
1143 07:49:20.442009 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1144 07:49:20.452053 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1145 07:49:20.461772 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1146 07:49:20.471738 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1147 07:49:20.481233 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1148 07:49:20.491546 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1149 07:49:20.498289 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1150 07:49:20.508347 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1151 07:49:20.518126 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1152 07:49:20.528179 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1153 07:49:20.538826 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1154 07:49:20.544492 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1155 07:49:20.547764
1156 07:49:20.554505 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1157 07:49:20.564573 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1158 07:49:20.574269 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1159 07:49:20.584533 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1160 07:49:20.594410 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1161 07:49:20.604162 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1162 07:49:20.610735 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1163 07:49:20.621176 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1164 07:49:20.624608 PCI: 00:02.0
1165 07:49:20.633927 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1166 07:49:20.644006 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1167 07:49:20.653861 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1168 07:49:20.657454 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1169 07:49:20.667326 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1170 07:49:20.667835 GENERIC: 0.0
1171 07:49:20.670645 PCI: 00:05.0
1172 07:49:20.680336 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1173 07:49:20.683951 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1174 07:49:20.687327 GENERIC: 0.0
1175 07:49:20.687773 PCI: 00:08.0
1176 07:49:20.697072 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1177 07:49:20.700232 PCI: 00:0a.0
1178 07:49:20.703419 PCI: 00:0d.0 child on link 0 USB0 port 0
1179 07:49:20.713875 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1180 07:49:20.720417 USB0 port 0 child on link 0 USB3 port 0
1181 07:49:20.720972 USB3 port 0
1182 07:49:20.723634 USB3 port 1
1183 07:49:20.724189 USB3 port 2
1184 07:49:20.726752 USB3 port 3
1185 07:49:20.730325 PCI: 00:14.0 child on link 0 USB0 port 0
1186 07:49:20.740199 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1187 07:49:20.747328 USB0 port 0 child on link 0 USB2 port 0
1188 07:49:20.747881 USB2 port 0
1189 07:49:20.749783 USB2 port 1
1190 07:49:20.750282 USB2 port 2
1191 07:49:20.753387 USB2 port 3
1192 07:49:20.753882 USB2 port 4
1193 07:49:20.756761 USB2 port 5
1194 07:49:20.757237 USB2 port 6
1195 07:49:20.760129 USB2 port 7
1196 07:49:20.760688 USB2 port 8
1197 07:49:20.762785 USB2 port 9
1198 07:49:20.763267 USB3 port 0
1199 07:49:20.766427 USB3 port 1
1200 07:49:20.767109 USB3 port 2
1201 07:49:20.769367 USB3 port 3
1202 07:49:20.772739 PCI: 00:14.2
1203 07:49:20.782772 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1204 07:49:20.792581 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1205 07:49:20.795948 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1206 07:49:20.806184 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1207 07:49:20.806729 GENERIC: 0.0
1208 07:49:20.812548 PCI: 00:15.0 child on link 0 I2C: 00:1a
1209 07:49:20.822976 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 07:49:20.823596 I2C: 00:1a
1211 07:49:20.826301 I2C: 00:31
1212 07:49:20.826817 I2C: 00:32
1213 07:49:20.829786 PCI: 00:15.1 child on link 0 I2C: 00:10
1214 07:49:20.839069 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1215 07:49:20.842651
1216 07:49:20.843207 I2C: 00:10
1217 07:49:20.843604 PCI: 00:15.2
1218 07:49:20.852450 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1219 07:49:20.855674 PCI: 00:15.3
1220 07:49:20.865511 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1221 07:49:20.866021 PCI: 00:16.0
1222 07:49:20.875539 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1223 07:49:20.878732
1224 07:49:20.879250 PCI: 00:19.0
1225 07:49:20.882981 PCI: 00:19.1 child on link 0 I2C: 00:15
1226 07:49:20.892335 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 07:49:20.895420 I2C: 00:15
1228 07:49:20.898697 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1229 07:49:20.908933 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1230 07:49:20.918441 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1231 07:49:20.925143 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1232 07:49:20.928161 GENERIC: 0.0
1233 07:49:20.932059 PCI: 01:00.0
1234 07:49:20.941912 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1235 07:49:20.951968 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1236 07:49:20.952518 PCI: 00:1e.0
1237 07:49:20.961751 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1238 07:49:20.967813 PCI: 00:1e.2 child on link 0 SPI: 00
1239 07:49:20.977914 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1240 07:49:20.978438 SPI: 00
1241 07:49:20.981237 PCI: 00:1e.3 child on link 0 SPI: 00
1242 07:49:20.991240 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1243 07:49:20.994656 SPI: 00
1244 07:49:20.998028 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1245 07:49:21.007902 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1246 07:49:21.008353 PNP: 0c09.0
1247 07:49:21.017751 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1248 07:49:21.021184 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1249 07:49:21.030788 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1250 07:49:21.040918 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1251 07:49:21.044537 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1252 07:49:21.047501 GENERIC: 0.0
1253 07:49:21.048015 GENERIC: 1.0
1254 07:49:21.050367 PCI: 00:1f.3
1255 07:49:21.060361 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1256 07:49:21.070486 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1257 07:49:21.071022 PCI: 00:1f.5
1258 07:49:21.080791 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1259 07:49:21.084015 CPU_CLUSTER: 0 child on link 0 APIC: 00
1260 07:49:21.087136 APIC: 00
1261 07:49:21.087578 APIC: 01
1262 07:49:21.090038 APIC: 05
1263 07:49:21.090606 APIC: 07
1264 07:49:21.090988 APIC: 02
1265 07:49:21.093432 APIC: 04
1266 07:49:21.093872 APIC: 06
1267 07:49:21.094221 APIC: 03
1268 07:49:21.103496 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1269 07:49:21.107086 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1270 07:49:21.113593 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1271 07:49:21.120214 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1272 07:49:21.123712 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1273 07:49:21.129968 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1274 07:49:21.137182 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1275 07:49:21.143423 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1276 07:49:21.150593 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1277 07:49:21.160064 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1278 07:49:21.163486 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1279 07:49:21.173086 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1280 07:49:21.179551 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1281 07:49:21.186406 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1282 07:49:21.189582 DOMAIN: 0000: Resource ranges:
1283 07:49:21.192967 * Base: 1000, Size: 800, Tag: 100
1284 07:49:21.196234 * Base: 1900, Size: e700, Tag: 100
1285 07:49:21.199740
1286 07:49:21.202758 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1287 07:49:21.209034 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1288 07:49:21.215728 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1289 07:49:21.226066 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1290 07:49:21.232145 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1291 07:49:21.239202 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1292 07:49:21.248714 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1293 07:49:21.255562 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1294 07:49:21.262244 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1295 07:49:21.272421 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1296 07:49:21.278736 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1297 07:49:21.284851 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1298 07:49:21.295142 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1299 07:49:21.302081 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1300 07:49:21.308526 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1301 07:49:21.318616 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1302 07:49:21.324836 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1303 07:49:21.331411 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1304 07:49:21.341651 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1305 07:49:21.348404 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1306 07:49:21.355240 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1307 07:49:21.365316 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1308 07:49:21.370995 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1309 07:49:21.378305 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1310 07:49:21.387914 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1311 07:49:21.391116 DOMAIN: 0000: Resource ranges:
1312 07:49:21.394581 * Base: 7fc00000, Size: 40400000, Tag: 200
1313 07:49:21.398097 * Base: d0000000, Size: 28000000, Tag: 200
1314 07:49:21.401267 * Base: fa000000, Size: 1000000, Tag: 200
1315 07:49:21.408116 * Base: fb001000, Size: 2fff000, Tag: 200
1316 07:49:21.410764 * Base: fe010000, Size: 2e000, Tag: 200
1317 07:49:21.414145 * Base: fe03f000, Size: d41000, Tag: 200
1318 07:49:21.418080 * Base: fed88000, Size: 8000, Tag: 200
1319 07:49:21.425079 * Base: fed93000, Size: d000, Tag: 200
1320 07:49:21.427899 * Base: feda2000, Size: 1e000, Tag: 200
1321 07:49:21.430914 * Base: fede0000, Size: 1220000, Tag: 200
1322 07:49:21.437773 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1323 07:49:21.443977 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1324 07:49:21.450966 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1325 07:49:21.457628 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1326 07:49:21.464008 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1327 07:49:21.470776 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1328 07:49:21.477371 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1329 07:49:21.483610 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1330 07:49:21.490528 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1331 07:49:21.497353 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1332 07:49:21.503597 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1333 07:49:21.510539 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1334 07:49:21.516746 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1335 07:49:21.523587 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1336 07:49:21.529874 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1337 07:49:21.536947 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1338 07:49:21.543282 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1339 07:49:21.550274 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1340 07:49:21.556598 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1341 07:49:21.563370 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1342 07:49:21.569691 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1343 07:49:21.576836 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1344 07:49:21.583177 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1345 07:49:21.589656 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1346 07:49:21.596526 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1347 07:49:21.599437
1348 07:49:21.599908 PCI: 00:1d.0: Resource ranges:
1349 07:49:21.606491 * Base: 7fc00000, Size: 100000, Tag: 200
1350 07:49:21.613278 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1351 07:49:21.619349 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1352 07:49:21.626078 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1353 07:49:21.632520 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1354 07:49:21.639297 Root Device assign_resources, bus 0 link: 0
1355 07:49:21.642731 DOMAIN: 0000 assign_resources, bus 0 link: 0
1356 07:49:21.652799 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1357 07:49:21.659365 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1358 07:49:21.669476 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1359 07:49:21.675907 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1360 07:49:21.679548 PCI: 00:04.0 assign_resources, bus 1 link: 0
1361 07:49:21.685786 PCI: 00:04.0 assign_resources, bus 1 link: 0
1362 07:49:21.692573 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1363 07:49:21.702974 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1364 07:49:21.709091 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1365 07:49:21.716094 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1366 07:49:21.719320 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1367 07:49:21.728904 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1368 07:49:21.732141 PCI: 00:14.0 assign_resources, bus 0 link: 0
1369 07:49:21.735683 PCI: 00:14.0 assign_resources, bus 0 link: 0
1370 07:49:21.745517 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1371 07:49:21.752416 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1372 07:49:21.762412 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1373 07:49:21.766099 PCI: 00:14.3 assign_resources, bus 0 link: 0
1374 07:49:21.768852 PCI: 00:14.3 assign_resources, bus 0 link: 0
1375 07:49:21.772240
1376 07:49:21.778464 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1377 07:49:21.781938 PCI: 00:15.0 assign_resources, bus 0 link: 0
1378 07:49:21.788768 PCI: 00:15.0 assign_resources, bus 0 link: 0
1379 07:49:21.795292 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1380 07:49:21.802002 PCI: 00:15.1 assign_resources, bus 0 link: 0
1381 07:49:21.805491 PCI: 00:15.1 assign_resources, bus 0 link: 0
1382 07:49:21.814805 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1383 07:49:21.821502 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1384 07:49:21.831358 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1385 07:49:21.838403 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1386 07:49:21.841075 PCI: 00:19.1 assign_resources, bus 0 link: 0
1387 07:49:21.848367 PCI: 00:19.1 assign_resources, bus 0 link: 0
1388 07:49:21.854345 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1389 07:49:21.864890 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1390 07:49:21.874228 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1391 07:49:21.877427 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1392 07:49:21.887520 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1393 07:49:21.894202 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1394 07:49:21.900601 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1395 07:49:21.907363 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1396 07:49:21.913979 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1397 07:49:21.917662 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1398 07:49:21.927169 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1399 07:49:21.930463 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1400 07:49:21.933826 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1401 07:49:21.940860 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1402 07:49:21.943462 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1403 07:49:21.950509 LPC: Trying to open IO window from 800 size 1ff
1404 07:49:21.956773 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1405 07:49:21.967019 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1406 07:49:21.973584 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1407 07:49:21.980146 DOMAIN: 0000 assign_resources, bus 0 link: 0
1408 07:49:21.983301 Root Device assign_resources, bus 0 link: 0
1409 07:49:21.986703 Done setting resources.
1410 07:49:21.993179 Show resources in subtree (Root Device)...After assigning values.
1411 07:49:21.996384 Root Device child on link 0 DOMAIN: 0000
1412 07:49:22.000095 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1413 07:49:22.009489 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1414 07:49:22.020158 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1415 07:49:22.022928 PCI: 00:00.0
1416 07:49:22.029890 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1417 07:49:22.032953
1418 07:49:22.039432 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1419 07:49:22.049975 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1420 07:49:22.059863 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1421 07:49:22.069240 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1422 07:49:22.079049 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1423 07:49:22.088973 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1424 07:49:22.095642 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1425 07:49:22.105999 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1426 07:49:22.115565 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1427 07:49:22.125505 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1428 07:49:22.135194 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1429 07:49:22.142223 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1430 07:49:22.145199
1431 07:49:22.151699 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1432 07:49:22.161891 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1433 07:49:22.171992 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1434 07:49:22.181765 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1435 07:49:22.191595 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1436 07:49:22.201571 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1437 07:49:22.211152 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1438 07:49:22.211671 PCI: 00:02.0
1439 07:49:22.221194 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1440 07:49:22.230967 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1441 07:49:22.234306
1442 07:49:22.241044 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1443 07:49:22.248190 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1444 07:49:22.257879 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1445 07:49:22.258403 GENERIC: 0.0
1446 07:49:22.261167 PCI: 00:05.0
1447 07:49:22.270995 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1448 07:49:22.274105 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1449 07:49:22.277396 GENERIC: 0.0
1450 07:49:22.277844 PCI: 00:08.0
1451 07:49:22.290393 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1452 07:49:22.290925 PCI: 00:0a.0
1453 07:49:22.293772 PCI: 00:0d.0 child on link 0 USB0 port 0
1454 07:49:22.307116 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1455 07:49:22.311095 USB0 port 0 child on link 0 USB3 port 0
1456 07:49:22.311538 USB3 port 0
1457 07:49:22.313648 USB3 port 1
1458 07:49:22.314086 USB3 port 2
1459 07:49:22.317246 USB3 port 3
1460 07:49:22.320307 PCI: 00:14.0 child on link 0 USB0 port 0
1461 07:49:22.333402 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1462 07:49:22.336877 USB0 port 0 child on link 0 USB2 port 0
1463 07:49:22.337322 USB2 port 0
1464 07:49:22.340214 USB2 port 1
1465 07:49:22.340661 USB2 port 2
1466 07:49:22.343347 USB2 port 3
1467 07:49:22.346474 USB2 port 4
1468 07:49:22.346945 USB2 port 5
1469 07:49:22.350199 USB2 port 6
1470 07:49:22.350646 USB2 port 7
1471 07:49:22.353140 USB2 port 8
1472 07:49:22.353598 USB2 port 9
1473 07:49:22.356608 USB3 port 0
1474 07:49:22.357055 USB3 port 1
1475 07:49:22.359926 USB3 port 2
1476 07:49:22.360367 USB3 port 3
1477 07:49:22.363440 PCI: 00:14.2
1478 07:49:22.373539 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1479 07:49:22.383549 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1480 07:49:22.386582 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1481 07:49:22.399595 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1482 07:49:22.400109 GENERIC: 0.0
1483 07:49:22.403148 PCI: 00:15.0 child on link 0 I2C: 00:1a
1484 07:49:22.416342 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1485 07:49:22.416793 I2C: 00:1a
1486 07:49:22.417139 I2C: 00:31
1487 07:49:22.419948 I2C: 00:32
1488 07:49:22.422765 PCI: 00:15.1 child on link 0 I2C: 00:10
1489 07:49:22.432570 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1490 07:49:22.435839 I2C: 00:10
1491 07:49:22.436302 PCI: 00:15.2
1492 07:49:22.446352 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1493 07:49:22.449462 PCI: 00:15.3
1494 07:49:22.459398 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1495 07:49:22.462448 PCI: 00:16.0
1496 07:49:22.472372 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1497 07:49:22.472884 PCI: 00:19.0
1498 07:49:22.478857 PCI: 00:19.1 child on link 0 I2C: 00:15
1499 07:49:22.489280 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1500 07:49:22.489776 I2C: 00:15
1501 07:49:22.495418 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1502 07:49:22.501986 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1503 07:49:22.515117 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1504 07:49:22.525227 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1505 07:49:22.528996 GENERIC: 0.0
1506 07:49:22.529434 PCI: 01:00.0
1507 07:49:22.538676 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1508 07:49:22.548769 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1509 07:49:22.551581 PCI: 00:1e.0
1510 07:49:22.561459 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1511 07:49:22.565038 PCI: 00:1e.2 child on link 0 SPI: 00
1512 07:49:22.574544 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1513 07:49:22.578416
1514 07:49:22.578959 SPI: 00
1515 07:49:22.581411 PCI: 00:1e.3 child on link 0 SPI: 00
1516 07:49:22.591411 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1517 07:49:22.594643 SPI: 00
1518 07:49:22.598016 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1519 07:49:22.608045 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1520 07:49:22.608499 PNP: 0c09.0
1521 07:49:22.617964 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1522 07:49:22.620941 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1523 07:49:22.630901 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1524 07:49:22.640831 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1525 07:49:22.644283 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1526 07:49:22.647488 GENERIC: 0.0
1527 07:49:22.648012 GENERIC: 1.0
1528 07:49:22.650838 PCI: 00:1f.3
1529 07:49:22.662088 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1530 07:49:22.670787 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1531 07:49:22.674084 PCI: 00:1f.5
1532 07:49:22.683923 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1533 07:49:22.687416 CPU_CLUSTER: 0 child on link 0 APIC: 00
1534 07:49:22.688001 APIC: 00
1535 07:49:22.690713 APIC: 01
1536 07:49:22.691220 APIC: 05
1537 07:49:22.691577 APIC: 07
1538 07:49:22.693877
1539 07:49:22.694319 APIC: 02
1540 07:49:22.694670 APIC: 04
1541 07:49:22.697177 APIC: 06
1542 07:49:22.697619 APIC: 03
1543 07:49:22.700352 Done allocating resources.
1544 07:49:22.707158 BS: BS_DEV_RESOURCES run times (exec / console): 26 / 2475 ms
1545 07:49:22.710563 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1546 07:49:22.714231
1547 07:49:22.717028 Configure GPIOs for I2S audio on UP4.
1548 07:49:22.723640 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1549 07:49:22.724087 Enabling resources...
1550 07:49:22.727644
1551 07:49:22.730407 PCI: 00:00.0 subsystem <- 8086/9a12
1552 07:49:22.730850 PCI: 00:00.0 cmd <- 06
1553 07:49:22.737005 PCI: 00:02.0 subsystem <- 8086/9a40
1554 07:49:22.737515 PCI: 00:02.0 cmd <- 03
1555 07:49:22.740487 PCI: 00:04.0 subsystem <- 8086/9a03
1556 07:49:22.743609 PCI: 00:04.0 cmd <- 02
1557 07:49:22.746758 PCI: 00:05.0 subsystem <- 8086/9a19
1558 07:49:22.750080 PCI: 00:05.0 cmd <- 02
1559 07:49:22.753311 PCI: 00:08.0 subsystem <- 8086/9a11
1560 07:49:22.756949 PCI: 00:08.0 cmd <- 06
1561 07:49:22.759964 PCI: 00:0d.0 subsystem <- 8086/9a13
1562 07:49:22.762934 PCI: 00:0d.0 cmd <- 02
1563 07:49:22.766583 PCI: 00:14.0 subsystem <- 8086/a0ed
1564 07:49:22.769911 PCI: 00:14.0 cmd <- 02
1565 07:49:22.773013 PCI: 00:14.2 subsystem <- 8086/a0ef
1566 07:49:22.776311 PCI: 00:14.2 cmd <- 02
1567 07:49:22.779486 PCI: 00:14.3 subsystem <- 8086/a0f0
1568 07:49:22.779948 PCI: 00:14.3 cmd <- 02
1569 07:49:22.786165 PCI: 00:15.0 subsystem <- 8086/a0e8
1570 07:49:22.786598 PCI: 00:15.0 cmd <- 02
1571 07:49:22.789447 PCI: 00:15.1 subsystem <- 8086/a0e9
1572 07:49:22.792960 PCI: 00:15.1 cmd <- 02
1573 07:49:22.795986 PCI: 00:15.2 subsystem <- 8086/a0ea
1574 07:49:22.799487 PCI: 00:15.2 cmd <- 02
1575 07:49:22.802779 PCI: 00:15.3 subsystem <- 8086/a0eb
1576 07:49:22.805836 PCI: 00:15.3 cmd <- 02
1577 07:49:22.809173 PCI: 00:16.0 subsystem <- 8086/a0e0
1578 07:49:22.812613 PCI: 00:16.0 cmd <- 02
1579 07:49:22.816293 PCI: 00:19.1 subsystem <- 8086/a0c6
1580 07:49:22.819464 PCI: 00:19.1 cmd <- 02
1581 07:49:22.822742 PCI: 00:1d.0 bridge ctrl <- 0013
1582 07:49:22.826203 PCI: 00:1d.0 subsystem <- 8086/a0b0
1583 07:49:22.829190 PCI: 00:1d.0 cmd <- 06
1584 07:49:22.832514 PCI: 00:1e.0 subsystem <- 8086/a0a8
1585 07:49:22.832827 PCI: 00:1e.0 cmd <- 06
1586 07:49:22.839199 PCI: 00:1e.2 subsystem <- 8086/a0aa
1587 07:49:22.839541 PCI: 00:1e.2 cmd <- 06
1588 07:49:22.842381 PCI: 00:1e.3 subsystem <- 8086/a0ab
1589 07:49:22.845959 PCI: 00:1e.3 cmd <- 02
1590 07:49:22.849293 PCI: 00:1f.0 subsystem <- 8086/a087
1591 07:49:22.852984 PCI: 00:1f.0 cmd <- 407
1592 07:49:22.855867 PCI: 00:1f.3 subsystem <- 8086/a0c8
1593 07:49:22.859188 PCI: 00:1f.3 cmd <- 02
1594 07:49:22.862358 PCI: 00:1f.5 subsystem <- 8086/a0a4
1595 07:49:22.865636 PCI: 00:1f.5 cmd <- 406
1596 07:49:22.869629 PCI: 01:00.0 cmd <- 02
1597 07:49:22.874272 done.
1598 07:49:22.877304 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1599 07:49:22.880769 Initializing devices...
1600 07:49:22.883762 Root Device init
1601 07:49:22.887258 Chrome EC: Set SMI mask to 0x0000000000000000
1602 07:49:22.893855 Chrome EC: clear events_b mask to 0x0000000000000000
1603 07:49:22.900647 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1604 07:49:22.903616 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1605 07:49:22.910358 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1606 07:49:22.917530 Chrome EC: Set WAKE mask to 0x0000000000000000
1607 07:49:22.920014 fw_config match found: DB_USB=USB3_ACTIVE
1608 07:49:22.926715 Configure Right Type-C port orientation for retimer
1609 07:49:22.930225 Root Device init finished in 43 msecs
1610 07:49:22.933700 PCI: 00:00.0 init
1611 07:49:22.936653 CPU TDP = 9 Watts
1612 07:49:22.937084 CPU PL1 = 9 Watts
1613 07:49:22.940037 CPU PL2 = 40 Watts
1614 07:49:22.940468 CPU PL4 = 83 Watts
1615 07:49:22.946793 PCI: 00:00.0 init finished in 8 msecs
1616 07:49:22.947257 PCI: 00:02.0 init
1617 07:49:22.950001 GMA: Found VBT in CBFS
1618 07:49:22.953145 GMA: Found valid VBT in CBFS
1619 07:49:22.959957 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1620 07:49:22.966582 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1621 07:49:22.969613 PCI: 00:02.0 init finished in 18 msecs
1622 07:49:22.973124 PCI: 00:05.0 init
1623 07:49:22.976672 PCI: 00:05.0 init finished in 0 msecs
1624 07:49:22.980114 PCI: 00:08.0 init
1625 07:49:22.983102 PCI: 00:08.0 init finished in 0 msecs
1626 07:49:22.986160 PCI: 00:14.0 init
1627 07:49:22.989908 PCI: 00:14.0 init finished in 0 msecs
1628 07:49:22.992674 PCI: 00:14.2 init
1629 07:49:22.996305 PCI: 00:14.2 init finished in 0 msecs
1630 07:49:22.996757 PCI: 00:15.0 init
1631 07:49:22.999749 I2C bus 0 version 0x3230302a
1632 07:49:23.002783 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1633 07:49:23.009734 PCI: 00:15.0 init finished in 6 msecs
1634 07:49:23.010181 PCI: 00:15.1 init
1635 07:49:23.012412 I2C bus 1 version 0x3230302a
1636 07:49:23.016211 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1637 07:49:23.019244 PCI: 00:15.1 init finished in 6 msecs
1638 07:49:23.022674 PCI: 00:15.2 init
1639 07:49:23.026065 I2C bus 2 version 0x3230302a
1640 07:49:23.029312 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1641 07:49:23.032923 PCI: 00:15.2 init finished in 6 msecs
1642 07:49:23.035979 PCI: 00:15.3 init
1643 07:49:23.039324 I2C bus 3 version 0x3230302a
1644 07:49:23.042831 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1645 07:49:23.045790 PCI: 00:15.3 init finished in 6 msecs
1646 07:49:23.049778 PCI: 00:16.0 init
1647 07:49:23.052401 PCI: 00:16.0 init finished in 0 msecs
1648 07:49:23.055737 PCI: 00:19.1 init
1649 07:49:23.056185 I2C bus 5 version 0x3230302a
1650 07:49:23.062162 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1651 07:49:23.065540 PCI: 00:19.1 init finished in 6 msecs
1652 07:49:23.065989 PCI: 00:1d.0 init
1653 07:49:23.069118 Initializing PCH PCIe bridge.
1654 07:49:23.072979 PCI: 00:1d.0 init finished in 3 msecs
1655 07:49:23.077042 PCI: 00:1f.0 init
1656 07:49:23.080099 IOAPIC: Initializing IOAPIC at 0xfec00000
1657 07:49:23.086402 IOAPIC: Bootstrap Processor Local APIC = 0x00
1658 07:49:23.086853 IOAPIC: ID = 0x02
1659 07:49:23.089656 IOAPIC: Dumping registers
1660 07:49:23.092868 reg 0x0000: 0x02000000
1661 07:49:23.096534 reg 0x0001: 0x00770020
1662 07:49:23.096978 reg 0x0002: 0x00000000
1663 07:49:23.103008 PCI: 00:1f.0 init finished in 21 msecs
1664 07:49:23.103513 PCI: 00:1f.2 init
1665 07:49:23.106439 Disabling ACPI via APMC.
1666 07:49:23.109823 APMC done.
1667 07:49:23.113230 PCI: 00:1f.2 init finished in 5 msecs
1668 07:49:23.125423 PCI: 01:00.0 init
1669 07:49:23.128437 PCI: 01:00.0 init finished in 0 msecs
1670 07:49:23.131753 PNP: 0c09.0 init
1671 07:49:23.135064 Google Chrome EC uptime: 8.229 seconds
1672 07:49:23.141522 Google Chrome AP resets since EC boot: 1
1673 07:49:23.144609 Google Chrome most recent AP reset causes:
1674 07:49:23.147708 0.451: 32775 shutdown: entering G3
1675 07:49:23.154404 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1676 07:49:23.158209 PNP: 0c09.0 init finished in 23 msecs
1677 07:49:23.164153 Devices initialized
1678 07:49:23.167149 Show all devs... After init.
1679 07:49:23.170491 Root Device: enabled 1
1680 07:49:23.170976 DOMAIN: 0000: enabled 1
1681 07:49:23.174293 CPU_CLUSTER: 0: enabled 1
1682 07:49:23.177178 PCI: 00:00.0: enabled 1
1683 07:49:23.180676 PCI: 00:02.0: enabled 1
1684 07:49:23.181116 PCI: 00:04.0: enabled 1
1685 07:49:23.184004 PCI: 00:05.0: enabled 1
1686 07:49:23.187303 PCI: 00:06.0: enabled 0
1687 07:49:23.190379 PCI: 00:07.0: enabled 0
1688 07:49:23.190876 PCI: 00:07.1: enabled 0
1689 07:49:23.193971 PCI: 00:07.2: enabled 0
1690 07:49:23.196736 PCI: 00:07.3: enabled 0
1691 07:49:23.200782 PCI: 00:08.0: enabled 1
1692 07:49:23.201334 PCI: 00:09.0: enabled 0
1693 07:49:23.203615 PCI: 00:0a.0: enabled 0
1694 07:49:23.207151 PCI: 00:0d.0: enabled 1
1695 07:49:23.207606 PCI: 00:0d.1: enabled 0
1696 07:49:23.210293
1697 07:49:23.210732 PCI: 00:0d.2: enabled 0
1698 07:49:23.213805 PCI: 00:0d.3: enabled 0
1699 07:49:23.216918 PCI: 00:0e.0: enabled 0
1700 07:49:23.217364 PCI: 00:10.2: enabled 1
1701 07:49:23.220754 PCI: 00:10.6: enabled 0
1702 07:49:23.224022 PCI: 00:10.7: enabled 0
1703 07:49:23.227006 PCI: 00:12.0: enabled 0
1704 07:49:23.227456 PCI: 00:12.6: enabled 0
1705 07:49:23.230468 PCI: 00:13.0: enabled 0
1706 07:49:23.233268 PCI: 00:14.0: enabled 1
1707 07:49:23.236802 PCI: 00:14.1: enabled 0
1708 07:49:23.237247 PCI: 00:14.2: enabled 1
1709 07:49:23.240114 PCI: 00:14.3: enabled 1
1710 07:49:23.243813 PCI: 00:15.0: enabled 1
1711 07:49:23.247098 PCI: 00:15.1: enabled 1
1712 07:49:23.247555 PCI: 00:15.2: enabled 1
1713 07:49:23.250301 PCI: 00:15.3: enabled 1
1714 07:49:23.253365 PCI: 00:16.0: enabled 1
1715 07:49:23.253807 PCI: 00:16.1: enabled 0
1716 07:49:23.256578
1717 07:49:23.257017 PCI: 00:16.2: enabled 0
1718 07:49:23.260203 PCI: 00:16.3: enabled 0
1719 07:49:23.263546 PCI: 00:16.4: enabled 0
1720 07:49:23.264072 PCI: 00:16.5: enabled 0
1721 07:49:23.266414 PCI: 00:17.0: enabled 0
1722 07:49:23.269963 PCI: 00:19.0: enabled 0
1723 07:49:23.273325 PCI: 00:19.1: enabled 1
1724 07:49:23.273868 PCI: 00:19.2: enabled 0
1725 07:49:23.276596 PCI: 00:1c.0: enabled 1
1726 07:49:23.279900 PCI: 00:1c.1: enabled 0
1727 07:49:23.283401 PCI: 00:1c.2: enabled 0
1728 07:49:23.283851 PCI: 00:1c.3: enabled 0
1729 07:49:23.286720 PCI: 00:1c.4: enabled 0
1730 07:49:23.289958 PCI: 00:1c.5: enabled 0
1731 07:49:23.293129 PCI: 00:1c.6: enabled 1
1732 07:49:23.293582 PCI: 00:1c.7: enabled 0
1733 07:49:23.296487 PCI: 00:1d.0: enabled 1
1734 07:49:23.299781 PCI: 00:1d.1: enabled 0
1735 07:49:23.300227 PCI: 00:1d.2: enabled 1
1736 07:49:23.303210 PCI: 00:1d.3: enabled 0
1737 07:49:23.306587 PCI: 00:1e.0: enabled 1
1738 07:49:23.310103 PCI: 00:1e.1: enabled 0
1739 07:49:23.310550 PCI: 00:1e.2: enabled 1
1740 07:49:23.313757 PCI: 00:1e.3: enabled 1
1741 07:49:23.316364 PCI: 00:1f.0: enabled 1
1742 07:49:23.319838 PCI: 00:1f.1: enabled 0
1743 07:49:23.320290 PCI: 00:1f.2: enabled 1
1744 07:49:23.323046 PCI: 00:1f.3: enabled 1
1745 07:49:23.326397 PCI: 00:1f.4: enabled 0
1746 07:49:23.330070 PCI: 00:1f.5: enabled 1
1747 07:49:23.330515 PCI: 00:1f.6: enabled 0
1748 07:49:23.333094 PCI: 00:1f.7: enabled 0
1749 07:49:23.336348 APIC: 00: enabled 1
1750 07:49:23.336813 GENERIC: 0.0: enabled 1
1751 07:49:23.339913 GENERIC: 0.0: enabled 1
1752 07:49:23.342840 GENERIC: 1.0: enabled 1
1753 07:49:23.346257 GENERIC: 0.0: enabled 1
1754 07:49:23.346701 GENERIC: 1.0: enabled 1
1755 07:49:23.349722 USB0 port 0: enabled 1
1756 07:49:23.353232 GENERIC: 0.0: enabled 1
1757 07:49:23.353675 USB0 port 0: enabled 1
1758 07:49:23.356664 GENERIC: 0.0: enabled 1
1759 07:49:23.359580 I2C: 00:1a: enabled 1
1760 07:49:23.363008 I2C: 00:31: enabled 1
1761 07:49:23.363602 I2C: 00:32: enabled 1
1762 07:49:23.366413 I2C: 00:10: enabled 1
1763 07:49:23.369517 I2C: 00:15: enabled 1
1764 07:49:23.370039 GENERIC: 0.0: enabled 0
1765 07:49:23.372988 GENERIC: 1.0: enabled 0
1766 07:49:23.376231 GENERIC: 0.0: enabled 1
1767 07:49:23.376675 SPI: 00: enabled 1
1768 07:49:23.379202 SPI: 00: enabled 1
1769 07:49:23.382498 PNP: 0c09.0: enabled 1
1770 07:49:23.382981 GENERIC: 0.0: enabled 1
1771 07:49:23.386361 USB3 port 0: enabled 1
1772 07:49:23.389155 USB3 port 1: enabled 1
1773 07:49:23.392849 USB3 port 2: enabled 0
1774 07:49:23.393292 USB3 port 3: enabled 0
1775 07:49:23.396335 USB2 port 0: enabled 0
1776 07:49:23.399155 USB2 port 1: enabled 1
1777 07:49:23.399596 USB2 port 2: enabled 1
1778 07:49:23.402415 USB2 port 3: enabled 0
1779 07:49:23.406058 USB2 port 4: enabled 1
1780 07:49:23.409112 USB2 port 5: enabled 0
1781 07:49:23.409556 USB2 port 6: enabled 0
1782 07:49:23.412622 USB2 port 7: enabled 0
1783 07:49:23.415881 USB2 port 8: enabled 0
1784 07:49:23.416329 USB2 port 9: enabled 0
1785 07:49:23.419204 USB3 port 0: enabled 0
1786 07:49:23.422824 USB3 port 1: enabled 1
1787 07:49:23.423304 USB3 port 2: enabled 0
1788 07:49:23.426000 USB3 port 3: enabled 0
1789 07:49:23.429083 GENERIC: 0.0: enabled 1
1790 07:49:23.432370 GENERIC: 1.0: enabled 1
1791 07:49:23.432819 APIC: 01: enabled 1
1792 07:49:23.435638 APIC: 05: enabled 1
1793 07:49:23.436110 APIC: 07: enabled 1
1794 07:49:23.438975
1795 07:49:23.439428 APIC: 02: enabled 1
1796 07:49:23.442566 APIC: 04: enabled 1
1797 07:49:23.443243 APIC: 06: enabled 1
1798 07:49:23.445281 APIC: 03: enabled 1
1799 07:49:23.448743 PCI: 01:00.0: enabled 1
1800 07:49:23.452067 BS: BS_DEV_INIT run times (exec / console): 29 / 540 ms
1801 07:49:23.459016 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1802 07:49:23.462382 ELOG: NV offset 0xf30000 size 0x1000
1803 07:49:23.468828 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1804 07:49:23.475686 ELOG: Event(17) added with size 13 at 2022-11-25 07:49:23 UTC
1805 07:49:23.482442 ELOG: Event(92) added with size 9 at 2022-11-25 07:49:23 UTC
1806 07:49:23.488740 ELOG: Event(93) added with size 9 at 2022-11-25 07:49:23 UTC
1807 07:49:23.495163 ELOG: Event(9E) added with size 10 at 2022-11-25 07:49:23 UTC
1808 07:49:23.502148 ELOG: Event(9F) added with size 14 at 2022-11-25 07:49:23 UTC
1809 07:49:23.508880 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1810 07:49:23.514989 ELOG: Event(A1) added with size 10 at 2022-11-25 07:49:23 UTC
1811 07:49:23.521767 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1812 07:49:23.528239 ELOG: Event(A0) added with size 9 at 2022-11-25 07:49:23 UTC
1813 07:49:23.531335 elog_add_boot_reason: Logged dev mode boot
1814 07:49:23.538082 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1815 07:49:23.541261 Finalize devices...
1816 07:49:23.541762 Devices finalized
1817 07:49:23.548140 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1818 07:49:23.551179 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1819 07:49:23.557650 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1820 07:49:23.561050 ME: HFSTS1 : 0x80030055
1821 07:49:23.567555 ME: HFSTS2 : 0x30280116
1822 07:49:23.571316 ME: HFSTS3 : 0x00000050
1823 07:49:23.577627 ME: HFSTS4 : 0x00004000
1824 07:49:23.580821 ME: HFSTS5 : 0x00000000
1825 07:49:23.584402 ME: HFSTS6 : 0x40400006
1826 07:49:23.587940 ME: Manufacturing Mode : YES
1827 07:49:23.594307 ME: SPI Protection Mode Enabled : NO
1828 07:49:23.597384 ME: FW Partition Table : OK
1829 07:49:23.601140 ME: Bringup Loader Failure : NO
1830 07:49:23.603968 ME: Firmware Init Complete : NO
1831 07:49:23.607300 ME: Boot Options Present : NO
1832 07:49:23.610926 ME: Update In Progress : NO
1833 07:49:23.613791 ME: D0i3 Support : YES
1834 07:49:23.617782 ME: Low Power State Enabled : NO
1835 07:49:23.623924 ME: CPU Replaced : YES
1836 07:49:23.627189 ME: CPU Replacement Valid : YES
1837 07:49:23.630407 ME: Current Working State : 5
1838 07:49:23.634051 ME: Current Operation State : 1
1839 07:49:23.637003 ME: Current Operation Mode : 3
1840 07:49:23.640522 ME: Error Code : 0
1841 07:49:23.644078 ME: Enhanced Debug Mode : NO
1842 07:49:23.646838 ME: CPU Debug Disabled : YES
1843 07:49:23.650679 ME: TXT Support : NO
1844 07:49:23.656565 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1845 07:49:23.667026 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1846 07:49:23.670398 CBFS: 'fallback/slic' not found.
1847 07:49:23.673168 ACPI: Writing ACPI tables at 76b01000.
1848 07:49:23.673649 ACPI: * FACS
1849 07:49:23.676992 ACPI: * DSDT
1850 07:49:23.680158 Ramoops buffer: 0x100000@0x76a00000.
1851 07:49:23.683914 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1852 07:49:23.690139 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1853 07:49:23.692964 Google Chrome EC: version:
1854 07:49:23.696509 ro: voema_v2.0.10114-a447f03e46
1855 07:49:23.699861 rw: voema_v2.0.10114-a447f03e46
1856 07:49:23.703292 running image: 2
1857 07:49:23.710031 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1858 07:49:23.713048 ACPI: * FADT
1859 07:49:23.713594 SCI is IRQ9
1860 07:49:23.716806 ACPI: added table 1/32, length now 40
1861 07:49:23.719404 ACPI: * SSDT
1862 07:49:23.723423 Found 1 CPU(s) with 8 core(s) each.
1863 07:49:23.726554 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1864 07:49:23.729873 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1865 07:49:23.732678
1866 07:49:23.736354 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1867 07:49:23.739264 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1868 07:49:23.745972 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1869 07:49:23.752845 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1870 07:49:23.756019 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1871 07:49:23.762815 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1872 07:49:23.769508 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1873 07:49:23.772390 \_SB.PCI0.RP09: Added StorageD3Enable property
1874 07:49:23.775894 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1875 07:49:23.782322 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1876 07:49:23.789348 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1877 07:49:23.792207 PS2K: Passing 80 keymaps to kernel
1878 07:49:23.798781 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1879 07:49:23.805255 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1880 07:49:23.812346 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1881 07:49:23.818819 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1882 07:49:23.825586 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1883 07:49:23.832145 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1884 07:49:23.838746 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1885 07:49:23.845376 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1886 07:49:23.849302 ACPI: added table 2/32, length now 44
1887 07:49:23.849805 ACPI: * MCFG
1888 07:49:23.855292 ACPI: added table 3/32, length now 48
1889 07:49:23.855742 ACPI: * TPM2
1890 07:49:23.858488 TPM2 log created at 0x769f0000
1891 07:49:23.862085 ACPI: added table 4/32, length now 52
1892 07:49:23.865179 ACPI: * MADT
1893 07:49:23.865626 SCI is IRQ9
1894 07:49:23.868422 ACPI: added table 5/32, length now 56
1895 07:49:23.872363 current = 76b09850
1896 07:49:23.872916 ACPI: * DMAR
1897 07:49:23.875052 ACPI: added table 6/32, length now 60
1898 07:49:23.881798 ACPI: added table 7/32, length now 64
1899 07:49:23.882249 ACPI: * HPET
1900 07:49:23.885049 ACPI: added table 8/32, length now 68
1901 07:49:23.888385 ACPI: done.
1902 07:49:23.888833 ACPI tables: 35216 bytes.
1903 07:49:23.892140 smbios_write_tables: 769ef000
1904 07:49:23.894811 EC returned error result code 3
1905 07:49:23.898129 Couldn't obtain OEM name from CBI
1906 07:49:23.902187 Create SMBIOS type 16
1907 07:49:23.905709 Create SMBIOS type 17
1908 07:49:23.908629 GENERIC: 0.0 (WIFI Device)
1909 07:49:23.909194 SMBIOS tables: 1734 bytes.
1910 07:49:23.912154
1911 07:49:23.915423 Writing table forward entry at 0x00000500
1912 07:49:23.921932 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1913 07:49:23.925430 Writing coreboot table at 0x76b25000
1914 07:49:23.931804 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1915 07:49:23.935123 1. 0000000000001000-000000000009ffff: RAM
1916 07:49:23.938051 2. 00000000000a0000-00000000000fffff: RESERVED
1917 07:49:23.944546 3. 0000000000100000-00000000769eefff: RAM
1918 07:49:23.948013 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1919 07:49:23.955194 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1920 07:49:23.961817 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1921 07:49:23.964979 7. 0000000077000000-000000007fbfffff: RESERVED
1922 07:49:23.971367 8. 00000000c0000000-00000000cfffffff: RESERVED
1923 07:49:23.974897 9. 00000000f8000000-00000000f9ffffff: RESERVED
1924 07:49:23.978189 10. 00000000fb000000-00000000fb000fff: RESERVED
1925 07:49:23.984839 11. 00000000fe000000-00000000fe00ffff: RESERVED
1926 07:49:23.988121 12. 00000000fed80000-00000000fed87fff: RESERVED
1927 07:49:23.994680 13. 00000000fed90000-00000000fed92fff: RESERVED
1928 07:49:23.997829 14. 00000000feda0000-00000000feda1fff: RESERVED
1929 07:49:24.004567 15. 00000000fedc0000-00000000feddffff: RESERVED
1930 07:49:24.007721 16. 0000000100000000-00000004803fffff: RAM
1931 07:49:24.011002 Passing 4 GPIOs to payload:
1932 07:49:24.014503 NAME | PORT | POLARITY | VALUE
1933 07:49:24.021581 lid | undefined | high | high
1934 07:49:24.027627 power | undefined | high | low
1935 07:49:24.031221 oprom | undefined | high | low
1936 07:49:24.037615 EC in RW | 0x000000e5 | high | high
1937 07:49:24.044494 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum e94e
1938 07:49:24.047448 coreboot table: 1576 bytes.
1939 07:49:24.050692 IMD ROOT 0. 0x76fff000 0x00001000
1940 07:49:24.054216 IMD SMALL 1. 0x76ffe000 0x00001000
1941 07:49:24.057489 FSP MEMORY 2. 0x76c4e000 0x003b0000
1942 07:49:24.061204 VPD 3. 0x76c4d000 0x00000367
1943 07:49:24.063720 RO MCACHE 4. 0x76c4c000 0x00000fdc
1944 07:49:24.067449 CONSOLE 5. 0x76c2c000 0x00020000
1945 07:49:24.070930 FMAP 6. 0x76c2b000 0x00000578
1946 07:49:24.077535 TIME STAMP 7. 0x76c2a000 0x00000910
1947 07:49:24.080335 VBOOT WORK 8. 0x76c16000 0x00014000
1948 07:49:24.083786 ROMSTG STCK 9. 0x76c15000 0x00001000
1949 07:49:24.087300 AFTER CAR 10. 0x76c0a000 0x0000b000
1950 07:49:24.090785 RAMSTAGE 11. 0x76b97000 0x00073000
1951 07:49:24.093400 REFCODE 12. 0x76b42000 0x00055000
1952 07:49:24.096790 SMM BACKUP 13. 0x76b32000 0x00010000
1953 07:49:24.100617 4f444749 14. 0x76b30000 0x00002000
1954 07:49:24.103821
1955 07:49:24.106992 EXT VBT15. 0x76b2d000 0x0000219f
1956 07:49:24.110446 COREBOOT 16. 0x76b25000 0x00008000
1957 07:49:24.114017 ACPI 17. 0x76b01000 0x00024000
1958 07:49:24.116741 ACPI GNVS 18. 0x76b00000 0x00001000
1959 07:49:24.120173 RAMOOPS 19. 0x76a00000 0x00100000
1960 07:49:24.124076 TPM2 TCGLOG20. 0x769f0000 0x00010000
1961 07:49:24.126816 SMBIOS 21. 0x769ef000 0x00000800
1962 07:49:24.130150 IMD small region:
1963 07:49:24.133494 IMD ROOT 0. 0x76ffec00 0x00000400
1964 07:49:24.137284 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1965 07:49:24.139965 POWER STATE 2. 0x76ffeb80 0x00000044
1966 07:49:24.146626 ROMSTAGE 3. 0x76ffeb60 0x00000004
1967 07:49:24.150163 MEM INFO 4. 0x76ffe980 0x000001e0
1968 07:49:24.156406 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1969 07:49:24.156843 MTRR: Physical address space:
1970 07:49:24.159812
1971 07:49:24.163548 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1972 07:49:24.169457 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1973 07:49:24.175978 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1974 07:49:24.182936 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1975 07:49:24.189626 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1976 07:49:24.196272 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1977 07:49:24.202689 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1978 07:49:24.206533 MTRR: Fixed MSR 0x250 0x0606060606060606
1979 07:49:24.209477 MTRR: Fixed MSR 0x258 0x0606060606060606
1980 07:49:24.212827 MTRR: Fixed MSR 0x259 0x0000000000000000
1981 07:49:24.219608 MTRR: Fixed MSR 0x268 0x0606060606060606
1982 07:49:24.222675 MTRR: Fixed MSR 0x269 0x0606060606060606
1983 07:49:24.225922 MTRR: Fixed MSR 0x26a 0x0606060606060606
1984 07:49:24.229370 MTRR: Fixed MSR 0x26b 0x0606060606060606
1985 07:49:24.236003 MTRR: Fixed MSR 0x26c 0x0606060606060606
1986 07:49:24.239645 MTRR: Fixed MSR 0x26d 0x0606060606060606
1987 07:49:24.242446 MTRR: Fixed MSR 0x26e 0x0606060606060606
1988 07:49:24.246015 MTRR: Fixed MSR 0x26f 0x0606060606060606
1989 07:49:24.250805 call enable_fixed_mtrr()
1990 07:49:24.253898 CPU physical address size: 39 bits
1991 07:49:24.260971 MTRR: default type WB/UC MTRR counts: 6/7.
1992 07:49:24.264071 MTRR: WB selected as default type.
1993 07:49:24.270326 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1994 07:49:24.274061 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1995 07:49:24.280199 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1996 07:49:24.287295 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
1997 07:49:24.293542 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1998 07:49:24.300484 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
1999 07:49:24.307323 MTRR: Fixed MSR 0x250 0x0606060606060606
2000 07:49:24.310429 MTRR: Fixed MSR 0x258 0x0606060606060606
2001 07:49:24.313940 MTRR: Fixed MSR 0x259 0x0000000000000000
2002 07:49:24.317406 MTRR: Fixed MSR 0x268 0x0606060606060606
2003 07:49:24.323704 MTRR: Fixed MSR 0x269 0x0606060606060606
2004 07:49:24.327170 MTRR: Fixed MSR 0x26a 0x0606060606060606
2005 07:49:24.330326 MTRR: Fixed MSR 0x26b 0x0606060606060606
2006 07:49:24.334012 MTRR: Fixed MSR 0x26c 0x0606060606060606
2007 07:49:24.340095 MTRR: Fixed MSR 0x26d 0x0606060606060606
2008 07:49:24.343600 MTRR: Fixed MSR 0x26e 0x0606060606060606
2009 07:49:24.346815 MTRR: Fixed MSR 0x26f 0x0606060606060606
2010 07:49:24.347318
2011 07:49:24.350723 MTRR check
2012 07:49:24.354462 call enable_fixed_mtrr()
2013 07:49:24.354922 Fixed MTRRs : Enabled
2014 07:49:24.358006 Variable MTRRs: Enabled
2015 07:49:24.358449
2016 07:49:24.361030 CPU physical address size: 39 bits
2017 07:49:24.368538 BS: BS_WRITE_TABLES exit times (exec / console): 52 / 151 ms
2018 07:49:24.374907 MTRR: Fixed MSR 0x250 0x0606060606060606
2019 07:49:24.378509 MTRR: Fixed MSR 0x250 0x0606060606060606
2020 07:49:24.381479 MTRR: Fixed MSR 0x258 0x0606060606060606
2021 07:49:24.384842 MTRR: Fixed MSR 0x259 0x0000000000000000
2022 07:49:24.388264 MTRR: Fixed MSR 0x268 0x0606060606060606
2023 07:49:24.395029 MTRR: Fixed MSR 0x269 0x0606060606060606
2024 07:49:24.397805 MTRR: Fixed MSR 0x26a 0x0606060606060606
2025 07:49:24.401216 MTRR: Fixed MSR 0x26b 0x0606060606060606
2026 07:49:24.404444 MTRR: Fixed MSR 0x26c 0x0606060606060606
2027 07:49:24.410989 MTRR: Fixed MSR 0x26d 0x0606060606060606
2028 07:49:24.414626 MTRR: Fixed MSR 0x26e 0x0606060606060606
2029 07:49:24.417708 MTRR: Fixed MSR 0x26f 0x0606060606060606
2030 07:49:24.425425 MTRR: Fixed MSR 0x258 0x0606060606060606
2031 07:49:24.425869 call enable_fixed_mtrr()
2032 07:49:24.432712 MTRR: Fixed MSR 0x259 0x0000000000000000
2033 07:49:24.435400 MTRR: Fixed MSR 0x268 0x0606060606060606
2034 07:49:24.439262 MTRR: Fixed MSR 0x269 0x0606060606060606
2035 07:49:24.442368 MTRR: Fixed MSR 0x26a 0x0606060606060606
2036 07:49:24.448956 MTRR: Fixed MSR 0x26b 0x0606060606060606
2037 07:49:24.452180 MTRR: Fixed MSR 0x26c 0x0606060606060606
2038 07:49:24.455782 MTRR: Fixed MSR 0x26d 0x0606060606060606
2039 07:49:24.458532 MTRR: Fixed MSR 0x26e 0x0606060606060606
2040 07:49:24.465259 MTRR: Fixed MSR 0x26f 0x0606060606060606
2041 07:49:24.469197 CPU physical address size: 39 bits
2042 07:49:24.472537 call enable_fixed_mtrr()
2043 07:49:24.475809 MTRR: Fixed MSR 0x250 0x0606060606060606
2044 07:49:24.482660 MTRR: Fixed MSR 0x250 0x0606060606060606
2045 07:49:24.486083 MTRR: Fixed MSR 0x258 0x0606060606060606
2046 07:49:24.489341 MTRR: Fixed MSR 0x259 0x0000000000000000
2047 07:49:24.493019 MTRR: Fixed MSR 0x268 0x0606060606060606
2048 07:49:24.499629 MTRR: Fixed MSR 0x269 0x0606060606060606
2049 07:49:24.502650 MTRR: Fixed MSR 0x26a 0x0606060606060606
2050 07:49:24.505666 MTRR: Fixed MSR 0x26b 0x0606060606060606
2051 07:49:24.509230 MTRR: Fixed MSR 0x26c 0x0606060606060606
2052 07:49:24.515623 MTRR: Fixed MSR 0x26d 0x0606060606060606
2053 07:49:24.519031 MTRR: Fixed MSR 0x26e 0x0606060606060606
2054 07:49:24.522159 MTRR: Fixed MSR 0x26f 0x0606060606060606
2055 07:49:24.529310 MTRR: Fixed MSR 0x258 0x0606060606060606
2056 07:49:24.529748 call enable_fixed_mtrr()
2057 07:49:24.535987 MTRR: Fixed MSR 0x259 0x0000000000000000
2058 07:49:24.539271 MTRR: Fixed MSR 0x268 0x0606060606060606
2059 07:49:24.542694 MTRR: Fixed MSR 0x269 0x0606060606060606
2060 07:49:24.546074 MTRR: Fixed MSR 0x26a 0x0606060606060606
2061 07:49:24.552603 MTRR: Fixed MSR 0x26b 0x0606060606060606
2062 07:49:24.556221 MTRR: Fixed MSR 0x26c 0x0606060606060606
2063 07:49:24.558843 MTRR: Fixed MSR 0x26d 0x0606060606060606
2064 07:49:24.562302 MTRR: Fixed MSR 0x26e 0x0606060606060606
2065 07:49:24.569107 MTRR: Fixed MSR 0x26f 0x0606060606060606
2066 07:49:24.572113 CPU physical address size: 39 bits
2067 07:49:24.575532 call enable_fixed_mtrr()
2068 07:49:24.582150 CPU physical address size: 39 bits
2069 07:49:24.585435 MTRR: Fixed MSR 0x250 0x0606060606060606
2070 07:49:24.588647 MTRR: Fixed MSR 0x250 0x0606060606060606
2071 07:49:24.591917 MTRR: Fixed MSR 0x258 0x0606060606060606
2072 07:49:24.595342 MTRR: Fixed MSR 0x259 0x0000000000000000
2073 07:49:24.601802 MTRR: Fixed MSR 0x268 0x0606060606060606
2074 07:49:24.605020 MTRR: Fixed MSR 0x269 0x0606060606060606
2075 07:49:24.609173 MTRR: Fixed MSR 0x26a 0x0606060606060606
2076 07:49:24.612066 MTRR: Fixed MSR 0x26b 0x0606060606060606
2077 07:49:24.618972 MTRR: Fixed MSR 0x26c 0x0606060606060606
2078 07:49:24.621765 MTRR: Fixed MSR 0x26d 0x0606060606060606
2079 07:49:24.625676 MTRR: Fixed MSR 0x26e 0x0606060606060606
2080 07:49:24.628301 MTRR: Fixed MSR 0x26f 0x0606060606060606
2081 07:49:24.636896 MTRR: Fixed MSR 0x258 0x0606060606060606
2082 07:49:24.637340 call enable_fixed_mtrr()
2083 07:49:24.643809 MTRR: Fixed MSR 0x259 0x0000000000000000
2084 07:49:24.646961 MTRR: Fixed MSR 0x268 0x0606060606060606
2085 07:49:24.650212 MTRR: Fixed MSR 0x269 0x0606060606060606
2086 07:49:24.653596 MTRR: Fixed MSR 0x26a 0x0606060606060606
2087 07:49:24.660038 MTRR: Fixed MSR 0x26b 0x0606060606060606
2088 07:49:24.663500 MTRR: Fixed MSR 0x26c 0x0606060606060606
2089 07:49:24.666564 MTRR: Fixed MSR 0x26d 0x0606060606060606
2090 07:49:24.669850 MTRR: Fixed MSR 0x26e 0x0606060606060606
2091 07:49:24.676225 MTRR: Fixed MSR 0x26f 0x0606060606060606
2092 07:49:24.679587 CPU physical address size: 39 bits
2093 07:49:24.684247 call enable_fixed_mtrr()
2094 07:49:24.688701 Checking cr50 for pending updates
2095 07:49:24.691770 CPU physical address size: 39 bits
2096 07:49:24.695644 CPU physical address size: 39 bits
2097 07:49:24.698805 Reading cr50 TPM mode
2098 07:49:24.707306 BS: BS_PAYLOAD_LOAD entry times (exec / console): 326 / 6 ms
2099 07:49:24.717433 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2100 07:49:24.720770 Checking segment from ROM address 0xffc02b38
2101 07:49:24.723829 Checking segment from ROM address 0xffc02b54
2102 07:49:24.730631 Loading segment from ROM address 0xffc02b38
2103 07:49:24.731188 code (compression=0)
2104 07:49:24.740290 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2105 07:49:24.750203 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2106 07:49:24.750720 it's not compressed!
2107 07:49:24.891204 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2108 07:49:24.897871 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2109 07:49:24.905002 Loading segment from ROM address 0xffc02b54
2110 07:49:24.908104 Entry Point 0x30000000
2111 07:49:24.908609 Loaded segments
2112 07:49:24.914871 BS: BS_PAYLOAD_LOAD run times (exec / console): 137 / 63 ms
2113 07:49:24.959404 Finalizing chipset.
2114 07:49:24.962914 Finalizing SMM.
2115 07:49:24.963406 APMC done.
2116 07:49:24.969352 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2117 07:49:24.972714 mp_park_aps done after 0 msecs.
2118 07:49:24.975920 Jumping to boot code at 0x30000000(0x76b25000)
2119 07:49:24.985851 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2120 07:49:24.986363
2121 07:49:24.986714
2122 07:49:24.989254
2123 07:49:24.989694 Starting depthcharge on Voema...
2124 07:49:24.990774 end: 2.2.3 depthcharge-start (duration 00:00:16) [common]
2125 07:49:24.991339 start: 2.2.4 bootloader-commands (timeout 00:04:43) [common]
2126 07:49:24.991756 Setting prompt string to ['volteer:']
2127 07:49:24.992176 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:43)
2128 07:49:24.992976
2129 07:49:24.999191 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2130 07:49:24.999733
2131 07:49:25.005496 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2132 07:49:25.005942
2133 07:49:25.012382 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2134 07:49:25.012831
2135 07:49:25.015951 Failed to find eMMC card reader
2136 07:49:25.016496
2137 07:49:25.016852 Wipe memory regions:
2138 07:49:25.019224
2139 07:49:25.021958 [0x00000000001000, 0x000000000a0000)
2140 07:49:25.022403
2141 07:49:25.025478 [0x00000000100000, 0x00000030000000)
2142 07:49:25.025989
2143 07:49:25.062739 [0x00000032662db0, 0x000000769ef000)
2144 07:49:25.063324
2145 07:49:25.113975 [0x00000100000000, 0x00000480400000)
2146 07:49:25.114556
2147 07:49:25.745417 ec_init: CrosEC protocol v3 supported (256, 256)
2148 07:49:25.745970
2149 07:49:26.176285 R8152: Initializing
2150 07:49:26.176434
2151 07:49:26.179472 Version 6 (ocp_data = 5c30)
2152 07:49:26.179558
2153 07:49:26.182814 R8152: Done initializing
2154 07:49:26.182939
2155 07:49:26.186101 Adding net device
2156 07:49:26.186177
2157 07:49:26.492134 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2158 07:49:26.492273
2159 07:49:26.492345
2160 07:49:26.492416
2161 07:49:26.495694 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2163 07:49:26.596413 volteer: tftpboot 192.168.201.1 8119452/tftp-deploy-pti9jti9/kernel/bzImage 8119452/tftp-deploy-pti9jti9/kernel/cmdline 8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
2164 07:49:26.596569 Setting prompt string to 'Starting kernel'
2165 07:49:26.596665 Setting prompt string to ['Starting kernel']
2166 07:49:26.596737 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2167 07:49:26.596824 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:42)
2168 07:49:26.600697 tftpboot 192.168.201.1 8119452/tftp-deploy-pti9jti9/kernel/bzImaoy-pti9jti9/kernel/cmdline 8119452/tftp-deploy-pti9jti9/ramdisk/ramdisk.cpio.gz
2169 07:49:26.600792
2170 07:49:26.600861 Waiting for link
2171 07:49:26.600925
2172 07:49:26.803601 done.
2173 07:49:26.803779
2174 07:49:26.803891 MAC: 00:24:32:30:78:e4
2175 07:49:26.803961
2176 07:49:26.806673 Sending DHCP discover... done.
2177 07:49:26.806750
2178 07:49:26.810295 Waiting for reply... done.
2179 07:49:26.810371
2180 07:49:26.813156 Sending DHCP request... done.
2181 07:49:26.813241
2182 07:49:26.816640 Waiting for reply... done.
2183 07:49:26.816715
2184 07:49:26.819879 My ip is 192.168.201.15
2185 07:49:26.819954
2186 07:49:26.823473 The DHCP server ip is 192.168.201.1
2187 07:49:26.823548
2188 07:49:26.826514 TFTP server IP predefined by user: 192.168.201.1
2189 07:49:26.826588
2190 07:49:26.832986 Bootfile predefined by user: 8119452/tftp-deploy-pti9jti9/kernel/bzImage
2191 07:49:26.833069
2192 07:49:26.836699 Sending tftp read request... done.
2193 07:49:26.839339
2194 07:49:26.843055 Waiting for the transfer...
2195 07:49:26.843143
2196 07:49:27.365405 00000000 ################################################################
2197 07:49:27.365559
2198 07:49:27.882788 00080000 ################################################################
2199 07:49:27.882990
2200 07:49:28.407285 00100000 ################################################################
2201 07:49:28.407425
2202 07:49:28.941009 00180000 ################################################################
2203 07:49:28.941150
2204 07:49:29.453712 00200000 ################################################################
2205 07:49:29.453855
2206 07:49:29.974356 00280000 ################################################################
2207 07:49:29.974513
2208 07:49:30.496183 00300000 ################################################################
2209 07:49:30.496334
2210 07:49:31.018563 00380000 ################################################################
2211 07:49:31.018730
2212 07:49:31.525326 00400000 ################################################################
2213 07:49:31.525486
2214 07:49:32.048678 00480000 ################################################################
2215 07:49:32.048819
2216 07:49:32.608861 00500000 ################################################################
2217 07:49:32.608998
2218 07:49:33.182487 00580000 ################################################################
2219 07:49:33.182629
2220 07:49:33.756507 00600000 ################################################################
2221 07:49:33.756649
2222 07:49:34.112947 00680000 ####################################### done.
2223 07:49:34.113221
2224 07:49:34.116496 The bootfile was 7131024 bytes long.
2225 07:49:34.116713
2226 07:49:34.119638 Sending tftp read request... done.
2227 07:49:34.119851
2228 07:49:34.122655 Waiting for the transfer...
2229 07:49:34.122868
2230 07:49:34.743917 00000000 ################################################################
2231 07:49:34.744221
2232 07:49:35.395627 00080000 ################################################################
2233 07:49:35.396191
2234 07:49:36.069000 00100000 ################################################################
2235 07:49:36.069386
2236 07:49:36.733943 00180000 ################################################################
2237 07:49:36.734333
2238 07:49:37.361550 00200000 ################################################################
2239 07:49:37.361769
2240 07:49:38.005110 00280000 ################################################################
2241 07:49:38.005330
2242 07:49:38.686110 00300000 ################################################################
2243 07:49:38.686657
2244 07:49:39.401368 00380000 ################################################################
2245 07:49:39.401921
2246 07:49:40.122173 00400000 ################################################################
2247 07:49:40.122842
2248 07:49:40.824614 00480000 ################################################################
2249 07:49:40.825217
2250 07:49:41.558347 00500000 ################################################################
2251 07:49:41.558973
2252 07:49:42.269198 00580000 ################################################################
2253 07:49:42.269763
2254 07:49:42.981931 00600000 ################################################################
2255 07:49:42.982535
2256 07:49:43.691972 00680000 ################################################################
2257 07:49:43.692516
2258 07:49:44.399295 00700000 ################################################################
2259 07:49:44.399838
2260 07:49:45.100247 00780000 ################################################################
2261 07:49:45.100810
2262 07:49:45.314068 00800000 #################### done.
2263 07:49:45.314600
2264 07:49:45.317211 Sending tftp read request... done.
2265 07:49:45.317608
2266 07:49:45.320567 Waiting for the transfer...
2267 07:49:45.321006
2268 07:49:45.321384 00000000 # done.
2269 07:49:45.321746
2270 07:49:45.330416 Command line loaded dynamically from TFTP file: 8119452/tftp-deploy-pti9jti9/kernel/cmdline
2271 07:49:45.330856
2272 07:49:45.343953 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2273 07:49:45.344615
2274 07:49:45.351153 Shutting down all USB controllers.
2275 07:49:45.351680
2276 07:49:45.352029 Removing current net device
2277 07:49:45.352355
2278 07:49:45.354548 Finalizing coreboot
2279 07:49:45.355015
2280 07:49:45.360532 Exiting depthcharge with code 4 at timestamp: 28952086
2281 07:49:45.360975
2282 07:49:45.361323
2283 07:49:45.361647 Starting kernel ...
2284 07:49:45.361962
2285 07:49:45.362295
2286 07:49:45.362601
2287 07:49:45.363786 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
2288 07:49:45.364313 start: 2.2.5 auto-login-action (timeout 00:04:23) [common]
2289 07:49:45.364701 Setting prompt string to ['Linux version [0-9]']
2290 07:49:45.365062 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2291 07:49:45.365419 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2293 07:54:08.365275 end: 2.2.5 auto-login-action (duration 00:04:23) [common]
2295 07:54:08.366413 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 263 seconds'
2297 07:54:08.367296 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2300 07:54:08.368858 end: 2 depthcharge-action (duration 00:05:00) [common]
2302 07:54:08.370110 Cleaning after the job
2303 07:54:08.370561 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/ramdisk
2304 07:54:08.373699 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/kernel
2305 07:54:08.376306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119452/tftp-deploy-pti9jti9/modules
2306 07:54:08.377273 start: 5.1 power-off (timeout 00:00:30) [common]
2307 07:54:08.378093 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-12' '--port=1' '--command=off'
2308 07:54:08.404243 >> Command sent successfully.
2309 07:54:08.406104 Returned 0 in 0 seconds
2310 07:54:08.507446 end: 5.1 power-off (duration 00:00:00) [common]
2312 07:54:08.509032 start: 5.2 read-feedback (timeout 00:10:00) [common]
2313 07:54:08.510273 Listened to connection for namespace 'common' for up to 1s
2314 07:54:09.511008 Finalising connection for namespace 'common'
2315 07:54:09.511217 Disconnecting from shell: Finalise
2316 07:54:09.612322 end: 5.2 read-feedback (duration 00:00:01) [common]
2317 07:54:09.612973 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8119452
2318 07:54:09.621045 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8119452
2319 07:54:09.621175 JobError: Your job cannot terminate cleanly.