[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-16497-g60a4be297d Thu Oct 8 23:13:58 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00820f01 PSP boot mode: Production Silicon level: Pre-Production PMxC0 STATUS: 0x800 BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d124 BS: bootblock times (exec / console): total (unknown) / 36 ms coreboot-v1.9308_26_0.0.22-16497-g60a4be297d Thu Oct 8 23:13:58 UTC 2020 romstage starting (log level: 8)... POST: 0x41 POST: 0x42 Family_Model: 00820f01 GPIO Control Switch: 0xef000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 POST: 0x43 Boot Count incremented to 4932 FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 2fc80 size 1845e Spec version: v2.0 Revision: 0.0.0, Build Number 1 Type: release/test image ID: AMD_PCS0, base 0x20c0000 + 0x4b000 Config region 0x46ce4 + 0x104 Memory init offset 0x7b8 POST: 0x34 bootmode is set to: 0 POST: 0x36 Calling FspMemoryInit: 0x020c07b8 0x02000dec: raminit_upd 0x0204d1cc: &hob_list_ptr POST: 0x92 POST: 0x98 CBMEM: IMD: root @ 0xcb7ff000 254 entries. IMD: root @ 0xcb7fec00 62 entries. FMAP: area RO_VPD found @ 800000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 615000 (8192 bytes) External stage cache: IMD: root @ 0xcbfff000 254 entries. IMD: root @ 0xcbffec00 62 entries. FspMemoryInit returned 0x00000000 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) APOB RAM copy differs from flash Copy APOB from RAM 0x0x02001000/0xa3a4 to flash 0x0/0x10000 spi_init: SPI BAR at 0xfec10000 Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Successfully erased 65536 bytes @ 0x0 Updated APOB in flash POST: 0x44 FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset f800 size 1bec6 Decompressing stage fallback/ramstage @ 0xca6b5fc0 (1119216 bytes) Loading module at 0xca6b6000 with entry 0xca6b6000. filesize: 0x405c0 memsize: 0x1113b0 Processing 4368 relocs. Offset value of 0xba6b6000 BS: romstage times (exec / console): total (unknown) / 155 ms coreboot-v1.9308_26_0.0.22-16497-g60a4be297d Thu Oct 8 23:13:58 UTC 2020 ramstage starting (log level: 8)... POST: 0x39 POST: 0x80 Normal boot POST: 0x70 BS: BS_PRE_DEVICE run times (exec / console): 0 / 1 ms POST: 0x71 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: clear events_b mask to 0x0000000000000000 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000010001206 Chrome EC: Set WAKE mask to 0x0000000000000000 Board ID: 5 FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fsps.bin' CBFS: Found @ offset 48fc0 size 10cbd Spec version: v2.0 Revision: 0.0.0, Build Number 1 Type: release/test image ID: AMD_PCS0, base 0xca683000 + 0x32000 Config region 0x2ec14 + 0x152 Silicon init offset 0x3c2 Notify phase offset 0x3b8 Calling FspSiliconInit: 0xca6833c2 0xca7073b0: upd POST: 0x93 POST: 0x99 FspSiliconInit returned 0x00000000 I2C bus 2 version 0x3132322a DW I2C bus 2 at 0xfedc4000 (400 KHz) FMAP: area RW_ELOG found @ 610000 (4096 bytes) spi_init: SPI BAR at 0xfec10000 Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x610000 size 0x1000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2022-11-25 07:49:25 UTC ELOG: Event(9F) added with size 14 at 2022-11-25 07:49:25 UTC PM1_STS: PWRBTN BS: BS_DEV_INIT_CHIPS run times (exec / console): 261 / 110 ms POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc5000: enabled 1 MMIO: fedca000: enabled 1 MMIO: fedce000: enabled 0 MMIO: fedcf000: enabled 0 MMIO: fedc4000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 0 PCI: 00:01.2: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:01.4: enabled 0 PCI: 00:01.5: enabled 0 PCI: 00:01.6: enabled 0 PCI: 00:01.7: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:08.1: enabled 1 PCI: 00:08.2: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 I2C: 00:50: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:5d: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.5: enabled 1 PCI: 00:00.6: enabled 0 PCI: 00:00.7: enabled 1 PCI: 00:00.0: enabled 0 PNP: 0c09.0: enabled 1 USB0 port 0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB2 port 4: enabled 1 USB2 port 5: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB3 port 0: enabled 1 I2C: 00:1a: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 0 PCI: 00:01.2: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:01.4: enabled 0 PCI: 00:01.5: enabled 0 PCI: 00:01.6: enabled 0 PCI: 00:01.7: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:08.1: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB2 port 4: enabled 1 USB2 port 5: enabled 1 PCI: 00:00.4: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB3 port 0: enabled 1 PCI: 00:00.5: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:00.6: enabled 0 PCI: 00:00.7: enabled 1 PCI: 00:08.2: enabled 0 PCI: 00:00.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedca000: enabled 1 GENERIC: 0.0: enabled 1 MMIO: fedce000: enabled 0 MMIO: fedcf000: enabled 0 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:5d: enabled 1 GENERIC: 0.0: enabled 1 Mainboard Morphius Enable. Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled GENERIC: 0.1 enabled MMIO: fedc5000 enabled MMIO: fedca000 enabled MMIO: fedce000 disabled MMIO: fedcf000 disabled MMIO: fedc4000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [1022/15d0] ops PCI: 00:00.0 [1022/15d0] enabled PCI: 00:00.2 [1022/0000] ops PCI: 00:00.2 [1022/15d1] enabled PCI: 00:01.0 [1022/1452] enabled PCI: 00:01.2 [1022/15d3] bus ops PCI: 00:01.2 [1022/15d3] enabled PCI: 00:01.3 [1022/15d3] bus ops PCI: 00:01.3 [1022/15d3] enabled PCI: 00:01.7 [1022/15d3] bus ops PCI: 00:01.7 [1022/15d3] enabled PCI: 00:08.0 [1022/1452] enabled PCI: 00:08.1 [1022/0000] bus ops PCI: 00:08.1 [1022/15db] enabled PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled PCI: 00:18.0 [1022/0000] ops PCI: 00:18.0 [1022/15e8] enabled PCI: 00:18.1 [1022/0000] ops PCI: 00:18.1 [1022/15e9] enabled PCI: 00:18.2 [1022/0000] ops PCI: 00:18.2 [1022/15ea] enabled PCI: 00:18.3 [1022/0000] ops PCI: 00:18.3 [1022/15eb] enabled PCI: 00:18.4 [1022/0000] ops PCI: 00:18.4 [1022/15ec] enabled PCI: 00:18.5 [1022/0000] ops PCI: 00:18.5 [1022/15ed] enabled PCI: 00:18.6 [1022/0000] ops PCI: 00:18.6 [1022/15ee] enabled PCI: 00:18.7 [1022/15ef] enabled POST: 0x25 PCI: Leftover static devices: PCI: 00:01.1 PCI: 00:01.4 PCI: 00:01.5 PCI: 00:01.6 PCI: 00:08.2 PCI: 00:14.6 PCI: Check your devicetree.cb. PCI: 00:01.2 scanning... do_pci_scan_bridge for PCI: 00:01.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [8086/0000] ops PCI: 01:00.0 [8086/2723] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration L1 Sub-State supported from root port 1 L1 Sub-State Support = 0xf CommonModeRestoreTime = 0x1e Power On Value = 0x9, Power On Scale = 0x0 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:01.2 finished in 36 msecs PCI: 00:01.3 scanning... do_pci_scan_bridge for PCI: 00:01.3 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [17a0/9750] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration L1 Sub-State supported from root port 1 L1 Sub-State Support = 0xf CommonModeRestoreTime = 0xff Power On Value = 0x1f, Power On Scale = 0x2 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:01.3 finished in 40 msecs PCI: 00:01.7 scanning... do_pci_scan_bridge for PCI: 00:01.7 PCI: pci_scan_bus for bus 03 POST: 0x24 PCI: 03:00.0 [1e0f/0001] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint L1 Sub-State supported from root port 1 L1 Sub-State Support = 0x5 CommonModeRestoreTime = 0x3c Power On Value = 0x5, Power On Scale = 0x0 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 256 scan_bus: bus PCI: 00:01.7 finished in 36 msecs PCI: 00:08.1 scanning... do_pci_scan_bridge for PCI: 00:08.1 PCI: pci_scan_bus for bus 04 POST: 0x24 PCI: 04:00.0 [1002/0000] ops PCI: 04:00.0 [1002/15d8] enabled PCI: 04:00.1 [1002/15de] enabled PCI: 04:00.2 [1022/15df] enabled PCI: 04:00.3 [1022/0000] bus ops PCI: 04:00.3 [1022/15e5] enabled PCI: Static device PCI: 04:00.4 not found, disabling it. PCI: 04:00.5 [1022/15e2] bus ops PCI: 04:00.5 [1022/15e2] enabled PCI: 04:00.7 [1022/15e4] enabled POST: 0x25 PCI: Leftover static devices: PCI: 04:00.4 PCI: 04:00.6 PCI: Check your devicetree.cb. PCI: 04:00.3 scanning... scan_static_bus for PCI: 04:00.3 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB2 port 0 enabled USB2 port 1 enabled USB2 port 2 enabled USB2 port 3 enabled USB3 port 0 enabled USB3 port 1 enabled USB3 port 2 enabled USB3 port 3 enabled USB2 port 4 enabled USB2 port 5 enabled USB2 port 0 scanning... scan_static_bus for USB2 port 0 scan_static_bus for USB2 port 0 done scan_bus: bus USB2 port 0 finished in 6 msecs USB2 port 1 scanning... scan_static_bus for USB2 port 1 scan_static_bus for USB2 port 1 done scan_bus: bus USB2 port 1 finished in 6 msecs USB2 port 2 scanning... scan_static_bus for USB2 port 2 scan_static_bus for USB2 port 2 done scan_bus: bus USB2 port 2 finished in 6 msecs USB2 port 3 scanning... scan_static_bus for USB2 port 3 scan_static_bus for USB2 port 3 done scan_bus: bus USB2 port 3 finished in 6 msecs USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs USB3 port 1 scanning... scan_static_bus for USB3 port 1 scan_static_bus for USB3 port 1 done scan_bus: bus USB3 port 1 finished in 6 msecs USB3 port 2 scanning... scan_static_bus for USB3 port 2 scan_static_bus for USB3 port 2 done scan_bus: bus USB3 port 2 finished in 6 msecs USB3 port 3 scanning... scan_static_bus for USB3 port 3 scan_static_bus for USB3 port 3 done scan_bus: bus USB3 port 3 finished in 6 msecs USB2 port 4 scanning... scan_static_bus for USB2 port 4 scan_static_bus for USB2 port 4 done scan_bus: bus USB2 port 4 finished in 6 msecs USB2 port 5 scanning... scan_static_bus for USB2 port 5 scan_static_bus for USB2 port 5 done scan_bus: bus USB2 port 5 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 149 msecs scan_static_bus for PCI: 04:00.3 done scan_bus: bus PCI: 04:00.3 finished in 163 msecs PCI: 04:00.5 scanning... scan_static_bus for PCI: 04:00.5 GENERIC: 0.0 enabled scan_static_bus for PCI: 04:00.5 done scan_bus: bus PCI: 04:00.5 finished in 8 msecs POST: 0x55 scan_bus: bus PCI: 00:08.1 finished in 233 msecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: bus PCI: 00:14.0 finished in 6 msecs PCI: 00:14.3 scanning... scan_static_bus for PCI: 00:14.3 PNP: 0c09.0 enabled PNP: 0c09.0 scanning... scan_static_bus for PNP: 0c09.0 GENERIC: 0.0 enabled GENERIC: 1.0 enabled GENERIC: 0.0 enabled GENERIC: 0.0 scanning... scan_static_bus for GENERIC: 0.0 I2C: 00:1a enabled scan_static_bus for GENERIC: 0.0 done scan_bus: bus GENERIC: 0.0 finished in 8 msecs GENERIC: 1.0 scanning... scan_static_bus for GENERIC: 1.0 scan_static_bus for GENERIC: 1.0 done scan_bus: bus GENERIC: 1.0 finished in 6 msecs GENERIC: 0.0 scanning... scan_static_bus for GENERIC: 0.0 scan_static_bus for GENERIC: 0.0 done scan_bus: bus GENERIC: 0.0 finished in 6 msecs scan_static_bus for PNP: 0c09.0 done scan_bus: bus PNP: 0c09.0 finished in 52 msecs scan_static_bus for PCI: 00:14.3 done scan_bus: bus PCI: 00:14.3 finished in 66 msecs POST: 0x55 scan_bus: bus DOMAIN: 0000 finished in 571 msecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 01:50 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: bus MMIO: fedc5000 finished in 10 msecs MMIO: fedca000 scanning... scan_static_bus for MMIO: fedca000 GENERIC: 0.0 enabled scan_static_bus for MMIO: fedca000 done scan_bus: bus MMIO: fedca000 finished in 8 msecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 02:15 enabled bus: MMIO: fedc4000[0]->I2C: 02:2c enabled bus: MMIO: fedc4000[0]->I2C: 02:5d enabled bus: MMIO: fedc4000[0]->GENERIC: 0.0 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: bus MMIO: fedc4000 finished in 22 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 663 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 984 ms POST: 0x73 found VGA at PCI: 04:00.0 Setting up VGA for PCI: 04:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:08.1 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. PCI: 00:01.2 read_resources bus 1 link: 0 PCI: 00:01.2 read_resources bus 1 link: 0 done PCI: 00:01.3 read_resources bus 2 link: 0 PCI: 00:01.3 read_resources bus 2 link: 0 done PCI: 00:01.7 read_resources bus 3 link: 0 PCI: 00:01.7 read_resources bus 3 link: 0 done PCI: 00:08.1 read_resources bus 4 link: 0 PCI: 04:00.3 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 04:00.3 read_resources bus 0 link: 0 done PCI: 04:00.5 read_resources bus 0 link: 0 PCI: 04:00.5 read_resources bus 0 link: 0 done PCI: 00:08.1 read_resources bus 4 link: 0 done ACPI GNVS at 0xca682000 PCI: 00:14.3 read_resources bus 0 link: 0 PNP: 0c09.0 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 done PNP: 0c09.0 read_resources bus 0 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc5000 read_resources bus 1 link: 0 MMIO: fedc5000 read_resources bus 1 link: 0 done MMIO: fedca000 read_resources bus 0 link: 0 MMIO: fedca000 read_resources bus 0 link: 0 done MMIO: fedc4000 read_resources bus 2 link: 0 MMIO: fedc4000 read_resources bus 2 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size c9640000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base cc000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base 100000000 size 2f340000 align 0 gran 0 limit 0 flags e0004200 index 7 PCI: 00:00.0 resource base 12f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cb800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cb7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ca7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b PCI: 00:00.0 resource base fec01000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec01000 PCI: 00:00.2 PCI: 00:00.2 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 44 PCI: 00:01.0 PCI: 00:01.2 child on link 0 PCI: 01:00.0 PCI: 00:01.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:01.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:01.3 child on link 0 PCI: 02:00.0 PCI: 00:01.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:01.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:01.7 child on link 0 PCI: 03:00.0 PCI: 00:01.7 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:01.7 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.7 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:08.0 PCI: 00:08.1 child on link 0 PCI: 04:00.0 PCI: 00:08.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:08.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:08.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10 PCI: 04:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 18 PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 04:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 24 PCI: 04:00.1 PCI: 04:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 04:00.2 PCI: 04:00.2 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 04:00.2 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 04:00.3 child on link 0 USB0 port 0 PCI: 04:00.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 USB2 port 4 USB2 port 5 PCI: 04:00.5 child on link 0 GENERIC: 0.0 PCI: 04:00.5 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 10 GENERIC: 0.0 PCI: 04:00.7 PCI: 04:00.7 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 04:00.7 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc4000 size 2000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 child on link 0 GENERIC: 0.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 GENERIC: 0.0 child on link 0 I2C: 00:1a I2C: 00:1a GENERIC: 1.0 GENERIC: 0.0 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:18.6 PCI: 00:18.7 GENERIC: 0.1 MMIO: fedc5000 child on link 0 I2C: 01:50 I2C: 01:50 MMIO: fedca000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 MMIO: fedce000 MMIO: fedcf000 MMIO: fedc4000 child on link 0 I2C: 02:15 I2C: 02:15 I2C: 02:2c I2C: 02:5d GENERIC: 0.0 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:01.2 io: size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:01.2 io: size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x3fff] mem PCI: 00:01.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:01.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:01.3 io: size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:01.3 io: size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 00:01.3 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:01.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:01.7 io: size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:01.7 io: size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.7 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x3fff] mem PCI: 00:01.7 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:01.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:08.1 io: size: 0 align: 12 gran: 12 limit: ffffffff PCI: 04:00.0 20 * [0x0 - 0xff] io PCI: 00:08.1 io: size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:08.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:00.2 18 * [0x0 - 0xfffff] mem PCI: 04:00.3 10 * [0x100000 - 0x1fffff] mem PCI: 04:00.7 18 * [0x200000 - 0x2fffff] mem PCI: 04:00.0 24 * [0x300000 - 0x37ffff] mem PCI: 04:00.5 10 * [0x380000 - 0x3bffff] mem PCI: 04:00.1 10 * [0x3c0000 - 0x3c3fff] mem PCI: 04:00.2 24 * [0x3c4000 - 0x3c5fff] mem PCI: 04:00.7 24 * [0x3c6000 - 0x3c7fff] mem PCI: 00:08.1 mem: size: 400000 align: 20 gran: 20 limit: ffffffff done PCI: 00:08.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 04:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 04:00.0 18 * [0x10000000 - 0x101fffff] prefmem PCI: 00:08.1 prefmem: size: 10200000 align: 28 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: f000, Tag: 100 PCI: 00:08.1 1c * [0x1000 - 0x1fff] limit: 1fff io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffffff update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 01 base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 02 base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:00.0 03 base 00100000 limit 01ffffff mem (fixed) update_constraints: PCI: 00:00.0 04 base 02000000 limit 021bffff mem (fixed) update_constraints: PCI: 00:00.0 05 base 021c0000 limit cb7fffff mem (fixed) update_constraints: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) update_constraints: PCI: 00:00.0 06 base cc000000 limit cfffffff mem (fixed) update_constraints: PCI: 00:00.0 07 base 100000000 limit 12f33ffff mem (fixed) update_constraints: PCI: 00:00.0 08 base 12f340000 limit 12fffffff mem (fixed) update_constraints: PCI: 00:00.0 09 base cb800000 limit cbffffff mem (fixed) update_constraints: PCI: 00:00.0 0a base cb7fe000 limit cb7fffff mem (fixed) update_constraints: PCI: 00:00.0 0b base ca7fe000 limit cb7fdfff mem (fixed) update_constraints: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) update_constraints: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) update_constraints: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) update_constraints: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) update_constraints: PCI: 00:14.3 04 base fedc4000 limit fedc5fff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: d0000000, Size: 28000000, Tag: 200 * Base: fc000000, Size: 2c00000, Tag: 200 * Base: fec02000, Size: e000, Tag: 200 * Base: fec11000, Size: 1b3000, Tag: 200 * Base: fedc6000, Size: 23a000, Tag: 200 * Base: 130000000, Size: fffed0000000, Tag: 100200 PCI: 00:08.1 24 * [0xd0000000 - 0xe01fffff] limit: e01fffff prefmem PCI: 00:08.1 20 * [0xe0200000 - 0xe05fffff] limit: e05fffff mem PCI: 00:01.2 20 * [0xe0600000 - 0xe06fffff] limit: e06fffff mem PCI: 00:01.3 20 * [0xe0700000 - 0xe07fffff] limit: e07fffff mem PCI: 00:01.7 20 * [0xe0800000 - 0xe08fffff] limit: e08fffff mem PCI: 00:00.2 44 * [0xe0900000 - 0xe097ffff] limit: e097ffff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffffff done PCI: 00:01.2 mem: base: e0600000 size: 100000 align: 20 gran: 20 limit: e06fffff PCI: 00:01.2: Resource ranges: * Base: e0600000, Size: 100000, Tag: 200 PCI: 01:00.0 10 * [0xe0600000 - 0xe0603fff] limit: e0603fff mem PCI: 00:01.2 mem: base: e0600000 size: 100000 align: 20 gran: 20 limit: e06fffff done PCI: 00:01.3 mem: base: e0700000 size: 100000 align: 20 gran: 20 limit: e07fffff PCI: 00:01.3: Resource ranges: * Base: e0700000, Size: 100000, Tag: 200 PCI: 02:00.0 10 * [0xe0700000 - 0xe0700fff] limit: e0700fff mem PCI: 00:01.3 mem: base: e0700000 size: 100000 align: 20 gran: 20 limit: e07fffff done PCI: 00:01.7 mem: base: e0800000 size: 100000 align: 20 gran: 20 limit: e08fffff PCI: 00:01.7: Resource ranges: * Base: e0800000, Size: 100000, Tag: 200 PCI: 03:00.0 10 * [0xe0800000 - 0xe0803fff] limit: e0803fff mem PCI: 00:01.7 mem: base: e0800000 size: 100000 align: 20 gran: 20 limit: e08fffff done PCI: 00:08.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff PCI: 00:08.1: Resource ranges: * Base: 1000, Size: 1000, Tag: 100 PCI: 04:00.0 20 * [0x1000 - 0x10ff] limit: 10ff io PCI: 00:08.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done PCI: 00:08.1 prefmem: base: d0000000 size: 10200000 align: 28 gran: 20 limit: e01fffff PCI: 00:08.1: Resource ranges: * Base: d0000000, Size: 10200000, Tag: 1200 PCI: 04:00.0 10 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem PCI: 04:00.0 18 * [0xe0000000 - 0xe01fffff] limit: e01fffff prefmem PCI: 00:08.1 prefmem: base: d0000000 size: 10200000 align: 28 gran: 20 limit: e01fffff done PCI: 00:08.1 mem: base: e0200000 size: 400000 align: 20 gran: 20 limit: e05fffff PCI: 00:08.1: Resource ranges: * Base: e0200000, Size: 400000, Tag: 200 PCI: 04:00.2 18 * [0xe0200000 - 0xe02fffff] limit: e02fffff mem PCI: 04:00.3 10 * [0xe0300000 - 0xe03fffff] limit: e03fffff mem PCI: 04:00.7 18 * [0xe0400000 - 0xe04fffff] limit: e04fffff mem PCI: 04:00.0 24 * [0xe0500000 - 0xe057ffff] limit: e057ffff mem PCI: 04:00.5 10 * [0xe0580000 - 0xe05bffff] limit: e05bffff mem PCI: 04:00.1 10 * [0xe05c0000 - 0xe05c3fff] limit: e05c3fff mem PCI: 04:00.2 24 * [0xe05c4000 - 0xe05c5fff] limit: e05c5fff mem PCI: 04:00.7 24 * [0xe05c6000 - 0xe05c7fff] limit: e05c7fff mem PCI: 00:08.1 mem: base: e0200000 size: 400000 align: 20 gran: 20 limit: e05fffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 missing set_resources PCI: 00:00.2 44 <- [0x00e0900000 - 0x00e097ffff] size 0x00080000 gran 0x13 mem PCI: 00:01.2 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.2 20 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:01.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00e0600000 - 0x00e0603fff] size 0x00004000 gran 0x0e mem64 PCI: 00:01.2 assign_resources, bus 1 link: 0 PCI: 00:01.3 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:01.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:01.3 20 <- [0x00e0700000 - 0x00e07fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:01.3 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00e0700000 - 0x00e0700fff] size 0x00001000 gran 0x0c mem PCI: 00:01.3 assign_resources, bus 2 link: 0 PCI: 00:01.7 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:01.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:01.7 20 <- [0x00e0800000 - 0x00e08fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:01.7 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00e0800000 - 0x00e0803fff] size 0x00004000 gran 0x0e mem64 PCI: 00:01.7 assign_resources, bus 3 link: 0 PCI: 00:08.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:08.1 24 <- [0x00d0000000 - 0x00e01fffff] size 0x10200000 gran 0x14 bus 04 prefmem PCI: 00:08.1 20 <- [0x00e0200000 - 0x00e05fffff] size 0x00400000 gran 0x14 bus 04 mem PCI: 00:08.1 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 04:00.0 18 <- [0x00e0000000 - 0x00e01fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 04:00.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 04:00.0 24 <- [0x00e0500000 - 0x00e057ffff] size 0x00080000 gran 0x13 mem PCI: 04:00.1 10 <- [0x00e05c0000 - 0x00e05c3fff] size 0x00004000 gran 0x0e mem PCI: 04:00.2 18 <- [0x00e0200000 - 0x00e02fffff] size 0x00100000 gran 0x14 mem PCI: 04:00.2 24 <- [0x00e05c4000 - 0x00e05c5fff] size 0x00002000 gran 0x0d mem PCI: 04:00.3 10 <- [0x00e0300000 - 0x00e03fffff] size 0x00100000 gran 0x14 mem64 PCI: 04:00.3 assign_resources, bus 0 link: 0 PCI: 04:00.3 assign_resources, bus 0 link: 0 PCI: 04:00.5 10 <- [0x00e0580000 - 0x00e05bffff] size 0x00040000 gran 0x12 mem PCI: 04:00.5 assign_resources, bus 0 link: 0 PCI: 04:00.5 assign_resources, bus 0 link: 0 PCI: 04:00.7 18 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 mem PCI: 04:00.7 24 <- [0x00e05c6000 - 0x00e05c7fff] size 0x00002000 gran 0x0d mem PCI: 00:08.1 assign_resources, bus 4 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size c9640000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base cc000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base 100000000 size 2f340000 align 0 gran 0 limit 0 flags e0004200 index 7 PCI: 00:00.0 resource base 12f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cb800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cb7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ca7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b PCI: 00:00.0 resource base fec01000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec01000 PCI: 00:00.2 PCI: 00:00.2 resource base e0900000 size 80000 align 19 gran 19 limit e097ffff flags 60000200 index 44 PCI: 00:01.0 PCI: 00:01.2 child on link 0 PCI: 01:00.0 PCI: 00:01.2 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c PCI: 00:01.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 PCI: 00:01.2 resource base e0600000 size 100000 align 20 gran 20 limit e06fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base e0600000 size 4000 align 14 gran 14 limit e0603fff flags 60000201 index 10 PCI: 00:01.3 child on link 0 PCI: 02:00.0 PCI: 00:01.3 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c PCI: 00:01.3 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 PCI: 00:01.3 resource base e0700000 size 100000 align 20 gran 20 limit e07fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base e0700000 size 1000 align 12 gran 12 limit e0700fff flags 60000200 index 10 PCI: 00:01.7 child on link 0 PCI: 03:00.0 PCI: 00:01.7 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c PCI: 00:01.7 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 PCI: 00:01.7 resource base e0800000 size 100000 align 20 gran 20 limit e08fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base e0800000 size 4000 align 14 gran 14 limit e0803fff flags 60000201 index 10 PCI: 00:08.0 PCI: 00:08.1 child on link 0 PCI: 04:00.0 PCI: 00:08.1 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:08.1 resource base d0000000 size 10200000 align 28 gran 20 limit e01fffff flags 60081202 index 24 PCI: 00:08.1 resource base e0200000 size 400000 align 20 gran 20 limit e05fffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 10 PCI: 04:00.0 resource base e0000000 size 200000 align 21 gran 21 limit e01fffff flags 60001201 index 18 PCI: 04:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 04:00.0 resource base e0500000 size 80000 align 19 gran 19 limit e057ffff flags 60000200 index 24 PCI: 04:00.1 PCI: 04:00.1 resource base e05c0000 size 4000 align 14 gran 14 limit e05c3fff flags 60000200 index 10 PCI: 04:00.2 PCI: 04:00.2 resource base e0200000 size 100000 align 20 gran 20 limit e02fffff flags 60000200 index 18 PCI: 04:00.2 resource base e05c4000 size 2000 align 13 gran 13 limit e05c5fff flags 60000200 index 24 PCI: 04:00.3 child on link 0 USB0 port 0 PCI: 04:00.3 resource base e0300000 size 100000 align 20 gran 20 limit e03fffff flags 60000201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 USB2 port 4 USB2 port 5 PCI: 04:00.5 child on link 0 GENERIC: 0.0 PCI: 04:00.5 resource base e0580000 size 40000 align 18 gran 18 limit e05bffff flags 60000200 index 10 GENERIC: 0.0 PCI: 04:00.7 PCI: 04:00.7 resource base e0400000 size 100000 align 20 gran 20 limit e04fffff flags 60000200 index 18 PCI: 04:00.7 resource base e05c6000 size 2000 align 13 gran 13 limit e05c7fff flags 60000200 index 24 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc4000 size 2000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 child on link 0 GENERIC: 0.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 GENERIC: 0.0 child on link 0 I2C: 00:1a I2C: 00:1a GENERIC: 1.0 GENERIC: 0.0 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:18.6 PCI: 00:18.7 GENERIC: 0.1 MMIO: fedc5000 child on link 0 I2C: 01:50 I2C: 01:50 MMIO: fedca000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 MMIO: fedce000 MMIO: fedcf000 MMIO: fedc4000 child on link 0 I2C: 02:15 I2C: 02:15 I2C: 02:2c I2C: 02:5d GENERIC: 0.0 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 18 / 2231 ms 0x00000020: notify_params->phase Calling FspNotify: 0xca6833b8 0xca6fff7c: notify_params POST: 0x94 POST: 0x94 FspNotify returned 0x00000000 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x06 0x10 0x01 INTB# 0x06 0x11 0x02 INTC# 0x0E 0x12 0x03 INTD# 0x0F 0x13 0x04 INTE# 0x1F 0x1F 0x05 INTF#/GENINT2 0x1F 0x1F 0x06 INTG# 0x1F 0x1F 0x07 INTH# 0x1F 0x1F 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x1F 0x1F 0x1A SDIO 0x1F 0x1F 0x20 CIR 0x1F 0x1F 0x21 GPIOa 0x1F 0x1F 0x22 GPIOb 0x1F 0x1F 0x23 GPIOc 0x1F 0x1F 0x41 SATA 0x1F 0x1F 0x43 eMMC 0x05 0x05 0x50 GPP0 0x1F 0x1F 0x51 GPP1 0x1F 0x1F 0x52 GPP2 0x1F 0x1F 0x53 GPP3 0x1F 0x1F 0x62 GPIO 0x07 0x07 0x70 I2C0 0x1F 0x1F 0x71 I2C1 0x1F 0x1F 0x72 I2C2 0x0A 0x0A 0x73 I2C3 0x0B 0x0B 0x74 UART0 0x04 0x04 0x75 UART1 0x03 0x03 0x76 I2C4 0x1F 0x1F 0x77 I2C5 0x1F 0x1F 0x78 UART2 0x1F 0x1F 0x79 UART3 0x1F 0x1F PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:00.02 using PIN A PCI Devfn (0x2) not found in pirq_data table PCI IRQ: Found device 0:08.01 using PIN A Found this device in pirq_data table entry 7 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x00 (INTA#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 4:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x00 (INTA#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 4:00.01 using PIN B With INT_PIN swizzled to PIN B Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 4:00.02 using PIN C With INT_PIN swizzled to PIN C Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 3 (PIN C) PCI_INTR idx : 0x02 (INTC#) INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 4:00.03 using PIN D With INT_PIN swizzled to PIN D Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 4 (PIN D) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 4:00.05 using PIN B With INT_PIN swizzled to PIN B Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 4:00.07 using PIN D With INT_PIN swizzled to PIN D Attached to bridge device 0:08h.01h Found this device in pirq_data table entry 7 Orig INT_PIN : 4 (PIN D) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:01h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x00 (INTA#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:01h.03h Found this device in pirq_data table entry 2 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x00 (INTA#) INT_LINE : 0x6 (IRQ 6) PCI IRQ: Found device 3:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:01h.07h Found this device in pirq_data table entry 6 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x00 (INTA#) INT_LINE : 0x6 (IRQ 6) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments BS: BS_DEV_ENABLE entry times (exec / console): 28 / 387 ms POST: 0x74 Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:00.2 subsystem <- 1022/1510 PCI: 00:00.2 cmd <- 06 PCI: 00:01.0 subsystem <- 1022/1510 PCI: 00:01.0 cmd <- 00 PCI: 00:01.2 bridge ctrl <- 0013 PCI: 00:01.2 cmd <- 06 PCI: 00:01.3 bridge ctrl <- 0013 PCI: 00:01.3 cmd <- 06 PCI: 00:01.7 bridge ctrl <- 0013 PCI: 00:01.7 cmd <- 06 PCI: 00:08.0 subsystem <- 1022/1510 PCI: 00:08.0 cmd <- 00 PCI: 00:08.1 bridge ctrl <- 001b PCI: 00:08.1 cmd <- 07 PCI: 00:14.0 subsystem <- 1022/1510 PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/1510 PCI: 00:14.3 cmd <- 0f PCI: 00:18.7 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 cmd <- 06 PCI: 03:00.0 cmd <- 02 PCI: 04:00.0 subsystem <- 1022/1510 PCI: 04:00.0 cmd <- 03 PCI: 04:00.1 subsystem <- 1022/1510 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 subsystem <- 1022/1510 PCI: 04:00.2 cmd <- 02 PCI: 04:00.3 subsystem <- 1022/1510 PCI: 04:00.3 cmd <- 02 PCI: 04:00.5 subsystem <- 1022/1510 PCI: 04:00.5 cmd <- 02 PCI: 04:00.7 subsystem <- 1022/1510 PCI: 04:00.7 cmd <- 02 done. BS: BS_DEV_ENABLE run times (exec / console): 9 / 93 ms POST: 0x75 Initializing devices... POST: 0x75 CPU_CLUSTER: 0 init MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000e0200000 size 0x10200000 type 1 0x00000000e0200000 - 0x0000000100000000 size 0x1fe00000 type 0 0x0000000100000000 - 0x0000000130000000 size 0x30000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 10/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000d0000000 mask 0x0000fffff0000000 type 1 MTRR: 4 base 0x00000000e0000000 mask 0x0000ffffffe00000 type 1 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up SMI for CPU Will perform SMM setup. CPU: AMD Ryzen 3 3250C 15W with Radeon Graphics . Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 2. done. AP: slot 2 apic_id 3. AP: slot 3 apic_id 1. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 0x00038000. Will call 0xca6d2604(0x00000000) Installing permanent SMM handler to 0xcb800000 Loading module at 0xcb810000 with entry 0xcb8114d2. filesize: 0x6b90 memsize: 0xd468 Processing 425 relocs. Offset value of 0xcb810000 Loading module at 0xcb808000 with entry 0xcb808000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0xcb808000 SMM Module: placing jmp sequence at 0xcb807e00 rel16 0x01fd SMM Module: placing jmp sequence at 0xcb807c00 rel16 0x03fd SMM Module: placing jmp sequence at 0xcb807a00 rel16 0x05fd SMM Module: stub loaded at 0xcb808000. Will call 0xcb8114d2(0x00000000) smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcb800000, cpu = 0 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcb7ffe00, cpu = 1 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcb7ffc00, cpu = 2 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcb7ffa00, cpu = 3 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 820f01 CPU: family 17, model 20, stepping 01 Setting up local APIC... apic_id: 0x00 done. FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset d200 size 2580 microcode: patch id to apply = 0x08200103 microcode: being updated to patch id = 0x08200103 succeeded CPU #0 initialized Initializing CPU #2 Initializing CPU #3 Initializing CPU #1 CPU: vendor AMD device 820f01 CPU: family 17, model 20, stepping 01 CPU: vendor AMD device 820f01 Setting up local APIC... CPU: vendor AMD device 820f01 apic_id: 0x01 done. CPU: family 17, model 20, stepping 01 FMAP: area COREBOOT found @ 875000 (7909376 bytes) Setting up local APIC... CBFS: Locating 'cpu_microcode_blob.bin' apic_id: 0x03 CBFS: Found @ offset d200 size 2580 done. CPU: family 17, model 20, stepping 01 microcode: patch id to apply = 0x08200103 Setting up local APIC... FMAP: area COREBOOT found @ 875000 (7909376 bytes) microcode: being updated to patch id = 0x08200103 succeeded CBFS: Locating 'cpu_microcode_blob.bin' apic_id: 0x02 CBFS: Found @ offset d200 size 2580 done. microcode: patch id to apply = 0x08200103 FMAP: area COREBOOT found @ 875000 (7909376 bytes) CPU #3 initialized CBFS: Locating 'cpu_microcode_blob.bin' microcode: being updated to patch id = 0x08200103 succeeded CBFS: Found @ offset d200 size 2580 CPU #2 initialized microcode: patch id to apply = 0x08200103 microcode: being updated to patch id = 0x08200103 succeeded CPU #1 initialized bsp_do_flight_plan done after 245 msecs. coreboot-v1.9308_26_0.0.22-16497-g60a4be297d Thu Oct 8 23:13:58 UTC 2020 smm starting (log level: 8)... SMI# #1 spi_init: SPI BAR at 0xfec10000 PSP: Notify SMM info... OK MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x0000000130000000 size 0x30000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 501 msecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:01.0 init PCI: 00:01.0 init finished in 0 msecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:08.0 init PCI: 00:08.0 init finished in 0 msecs POST: 0x75 POST: 0x75 PCI: 00:14.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x08 IOAPIC: Dumping registers reg 0x0000: 0x08000000 reg 0x0001: 0x00178021 reg 0x0002: 0x08000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 132 msecs POST: 0x75 PCI: 00:14.3 init RTC Init PCI: 00:14.3 init finished in 0 msecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:18.7 init PCI: 00:18.7 init finished in 0 msecs POST: 0x75 PCI: 01:00.0 init PCI: 01:00.0 init finished in 0 msecs POST: 0x75 PCI: 02:00.0 init PCI: 02:00.0 init finished in 0 msecs POST: 0x75 PCI: 03:00.0 init PCI: 03:00.0 init finished in 0 msecs POST: 0x75 PCI: 04:00.0 init FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'pci1002,15d8,c4.rom' CBFS: 'pci1002,15d8,c4.rom' not found. Using RV2 VBIOS. FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'pci1002,15dd,c4.rom' CBFS: Found @ offset 67140 size d400 In CBFS, ROM address for PCI: 04:00.0 = 0xff8dc188 PCI expansion ROM, signature 0xaa55, INIT size 0xd400, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 15dd, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from 0xff8dc188 to 0xc0000, 0xd400 bytes Real mode stub @0x00000600: 889 bytes Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 41d4 VBE: resolution: 1920x1080@32 VBE: framebuffer: 0xd0000000 VBE: Setting VESA mode 41d4 VGA Option ROM was run PCI: 04:00.0 init finished in 113 msecs POST: 0x75 PCI: 04:00.1 init PCI: 04:00.1 init finished in 0 msecs POST: 0x75 PCI: 04:00.2 init PCI: 04:00.2 init finished in 0 msecs POST: 0x75 PCI: 04:00.3 init PCI: 04:00.3 init finished in 0 msecs POST: 0x75 PCI: 04:00.5 init PCI: 04:00.5 init finished in 0 msecs POST: 0x75 PCI: 04:00.7 init PCI: 04:00.7 init finished in 0 msecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PNP: 0c09.0 init Google Chrome EC uptime: 8.059 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin | sysjump PNP: 0c09.0 init finished in 17 msecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc5000: enabled 1 MMIO: fedca000: enabled 1 MMIO: fedce000: enabled 0 MMIO: fedcf000: enabled 0 MMIO: fedc4000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 0 PCI: 00:01.2: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:01.4: enabled 0 PCI: 00:01.5: enabled 0 PCI: 00:01.6: enabled 0 PCI: 00:01.7: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:08.1: enabled 1 PCI: 00:08.2: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.6: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 I2C: 01:50: enabled 1 GENERIC: 0.0: enabled 1 I2C: 02:15: enabled 1 I2C: 02:2c: enabled 1 I2C: 02:5d: enabled 1 GENERIC: 0.0: enabled 1 PCI: 04:00.0: enabled 1 PCI: 04:00.1: enabled 1 PCI: 04:00.2: enabled 1 PCI: 04:00.3: enabled 1 PCI: 04:00.4: enabled 0 PCI: 04:00.5: enabled 1 PCI: 04:00.6: enabled 0 PCI: 04:00.7: enabled 1 PCI: 00:00.0: enabled 0 PNP: 0c09.0: enabled 1 USB0 port 0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB2 port 4: enabled 1 USB2 port 5: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB3 port 0: enabled 1 I2C: 00:1a: enabled 1 PCI: 00:18.7: enabled 1 PCI: 01:00.0: enabled 1 PCI: 02:00.0: enabled 1 PCI: 03:00.0: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 01: enabled 1 BS: BS_DEV_INIT run times (exec / console): 211 / 875 ms SCIMAP 56 maps to GPE 31 (active high, edge trigger) ELOG: Event(A1) added with size 10 at 2022-11-25 07:49:29 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2022-11-25 07:49:29 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 0 / 26 ms POST: 0x76 Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 5 ms FMAP: area RW_NVRAM found @ 617000 (20480 bytes) BS: BS_POST_DEVICE exit times (exec / console): 1 / 4 ms POST: 0x77 BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 1 ms Saving dimm info for smbios type 17 AMD_FSP_DMI_HOB found AGESA TYPE 17 DMI INFO: Handle: 1 TotalWidth: 64 DataWidth: 64 MemorySize: 4096 DeviceSet: 0 Speed: 1600 ManufacturerIdCode: 0 Attributes: 1 ExtSize: 0 ConfigSpeed: 1200 MemoryType: 0x1a FormFactor: 0xd DeviceLocator: DIMM 0 BankLocator: P0 CHANNEL A SerialNumber(8): 00000000 PartNumber(0): CBMEM_ID_MEMINFO: dimm_size: 4096 ddr_type: 0x1a ddr_frequency: 0 rank_per_dimm: 1 channel_num: 0 dimm_num: 0 bank_locator: 0 mod_id: 0 mod_type: 0x4 bus_width: 3 serial: 00000000 module_part_number(20): MT40A512M16TB-062E:J BS: BS_WRITE_TABLES entry times (exec / console): 1 / 59 ms POST: 0x79 POST: 0x9c FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 2be80 size 3d79 FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at ca646000. ACPI: * FACS ACPI: * DSDT Ramoops buffer: 0x100000@0xca546000. FMAP: area RO_VPD found @ 800000 (16384 bytes) FMAP: area RW_VPD found @ 615000 (8192 bytes) ACPI: * FADT pm_base: 0x0400 ACPI: added table 1/32, length now 40 ACPI: * SSDT PSS: 2600MHz power 3166 control 0x0 status 0x0 PSS: 1700MHz power 1615 control 0x1 status 0x1 PSS: 1400MHz power 1276 control 0x2 status 0x2 PSS: 2600MHz power 3166 control 0x0 status 0x0 PSS: 1700MHz power 1615 control 0x1 status 0x1 PSS: 1400MHz power 1276 control 0x2 status 0x2 PSS: 2600MHz power 3166 control 0x0 status 0x0 PSS: 1700MHz power 1615 control 0x1 status 0x1 PSS: 1400MHz power 1276 control 0x2 status 0x2 PSS: 2600MHz power 3166 control 0x0 status 0x0 PSS: 1700MHz power 1615 control 0x1 status 0x1 PSS: 1400MHz power 1276 control 0x2 status 0x2 \_SB.MAXM: Maxim Integrated 98357A Amplifier \_SB.I2C3.TPMI: I2C TPM at I2C: 01:50 \_SB.FUR1.CRFP: Fingerprint Reader at GENERIC: 0.0 \_SB.I2C2.D015: ELAN Touchpad at I2C: 02:15 \_SB.I2C2.H02C: Synaptics Touchpad at I2C: 02:2c \_SB.I2C2.H05D: Goodix Touchscreen at I2C: 02:5d FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'pci1002,15d8,c4.rom' CBFS: 'pci1002,15d8,c4.rom' not found. Using RV2 VBIOS. FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'pci1002,15dd,c4.rom' CBFS: Found @ offset 67140 size d400 In CBFS, ROM address for PCI: 04:00.0 = 0xff8dc188 PCI expansion ROM, signature 0xaa55, INIT size 0xd400, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 15dd, PCI ROM image, Class Code 030000, Code Type 00 xHCI SSDT generation xhci_fill_ssdt: Got GPE 31 for PCI: 04:00.3 xHCI Supported Protocol: Major: 0x2, Minor: 0x0, Protocol: 'USB ' Port Offset: 1, Port Count: 6 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 7, Port Count: 1 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 8, Port Count: 1 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 9, Port Count: 1 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 10, Port Count: 1 EC returned error result code 1 PS2K: Bad resp from EC. Vivaldi disabled! \_SB.PCI0.PBRA.ACPD.I2S0: I2S machine driver at GENERIC: 0.0 \_SB.PCI0.LPCB.EC0.CREC.TUN0: Cros EC I2C Tunnel at GENERIC: 0.0 \_SB.PCI0.LPCB.EC0.CREC.MSTH: Cros EC I2C Tunnel at GENERIC: 1.0 \_SB.PCI0.LPCB.EC0.CREC.ECA0: Cros EC audio codec at GENERIC: 0.0 \_SB.PCI0.PBRA.XHC0.RHUB.HS01: Left Type-C Port at USB2 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.HS02: Left Type-A Port at USB2 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.HS03: Right Type-A Port at USB2 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.HS04: Right Type-C Port at USB2 port 3 \_SB.PCI0.PBRA.XHC0.RHUB.SS01: Left Type-C Port at USB3 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.SS02: Left Type-A Port at USB3 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.SS03: Right Type-A Port at USB3 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.SS04: Right Type-C Port at USB3 port 3 \_SB.PCI0.PBRA.XHC0.RHUB.HS05: User-Facing Camera at USB2 port 4 \_SB.PCI0.PBRA.XHC0.RHUB.HS06: Bluetooth at USB2 port 5 \_SB.PCI0.LPCB.EC0.CREC.TUN0.RT58: Realtek RT5682 at I2C: 00:1a Error: Could not locate 'wifi_sar' in VPD. Checking CBFS for default SAR values FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'wifi_sar_defaults.hex' CBFS: Found @ offset 48140 size 77 \_SB.PCI0.PBR1.WF00.WF00: PCI: 01:00.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xca528000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = ca64c8a0 Searching for AGESA FSP ACPI Tables ACPI: * CRAT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * ALIB (AGESA). ACPI: added table 7/32, length now 64 ACPI: added table 8/32, length now 68 ACPI: * HPET ACPI: added table 9/32, length now 72 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at ca652310 ACPI: added table 10/32, length now 76 ACPI: done. ACPI tables: 104320 bytes. smbios_write_tables: ca527000 Create SMBIOS type 16 Create SMBIOS type 17 PCI: 01:00.0 (unknown) SMBIOS tables: 891 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 9577 Writing coreboot table at 0xca66a000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000001ffffff: RAM 4. 0000000002000000-00000000021bffff: RESERVED 5. 00000000021c0000-00000000ca526fff: RAM 6. 00000000ca527000-00000000ca6b5fff: CONFIGURATION TABLES 7. 00000000ca6b6000-00000000ca7c7fff: RAMSTAGE 8. 00000000ca7c8000-00000000cb7fffff: CONFIGURATION TABLES 9. 00000000cb800000-00000000cfffffff: RESERVED 10. 00000000f8000000-00000000fbffffff: RESERVED 11. 0000000100000000-000000012f33ffff: RAM 12. 000000012f340000-000000012fffffff: RESERVED Passing 3 GPIOs to payload: NAME | PORT | POLARITY | VALUE lid | undefined | high | high power | undefined | high | low EC in RW | 0x00000082 | high | high Board ID: 5 SKU ID: 1510014996 FMAP: area COREBOOT found @ 875000 (7909376 bytes) Wrote coreboot table at: 0xca66a000, 0x53c bytes, checksum f5ef coreboot table: 1364 bytes. IMD ROOT 0. 0xcb7ff000 0x00001000 IMD SMALL 1. 0xcb7fe000 0x00001000 FSP MEMORY 2. 0xca7fe000 0x01000000 CONSOLE 3. 0xca7de000 0x00020000 FMAP 4. 0xca7dd000 0x00000452 TIME STAMP 5. 0xca7dc000 0x00000910 VBOOT WORK 6. 0xca7c8000 0x00014000 RAMSTAGE 7. 0xca6b5000 0x00113000 REFCODE 8. 0xca683000 0x00032000 ACPI GNVS 9. 0xca682000 0x00001000 SMM BACKUP 10. 0xca672000 0x00010000 COREBOOT 11. 0xca66a000 0x00008000 ACPI 12. 0xca646000 0x00024000 RAMOOPS 13. 0xca546000 0x00100000 VGA ROM #0 14. 0xca538000 0x0000d400 TPM2 TCGLOG15. 0xca528000 0x00010000 SMBIOS 16. 0xca527000 0x00000800 IMD small region: IMD ROOT 0. 0xcb7fec00 0x00000400 FSP RUNTIME 1. 0xcb7febe0 0x00000004 VPD 2. 0xcb7feb80 0x0000004c POWER STATE 3. 0xcb7feb40 0x00000030 ROMSTAGE 4. 0xcb7feb20 0x00000004 EARLY DRAM USAGE 5. 0xcb7feb00 0x00000008 MEM INFO 6. 0xcb7fe920 0x000001e0 Reset backlight GPIO BS: BS_WRITE_TABLES run times (exec / console): 13 / 592 ms Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 3:0x50 id 0x28) Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 16 / 14 ms POST: 0x7a FMAP: area COREBOOT found @ 875000 (7909376 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 51e680 size 4d114 Checking segment from ROM address 0xffd936b8 Checking segment from ROM address 0xffd936d4 Loading segment from ROM address 0xffd936b8 code (compression=0) New segment dstaddr 0x30000000 memsize 0x10651f0 srcaddr 0xffd936f0 filesize 0x4d0dc Loading Segment: addr: 0x30000000 memsz: 0x00000000010651f0 filesz: 0x000000000004d0dc it's not compressed! [ 0x30000000, 3004d0dc, 0x310651f0) <- ffd936f0 Clearing Segment: addr: 0x000000003004d0dc memsz: 0x0000000001018114 Loading segment from ROM address 0xffd936d4 Entry Point 0x30000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 31 / 61 ms 0x00000040: notify_params->phase Calling FspNotify: 0xca6833b8 0xca6fff6c: notify_params POST: 0x95 POST: 0x95 FspNotify returned 0x00000000 0x000000f0: notify_params->phase Calling FspNotify: 0xca6833b8 0xca6fff7c: notify_params POST: 0x88 POST: 0x89 FspNotify returned 0x00000000 Lock SMM configuration POST: 0xfe BS: BS_PAYLOAD_LOAD exit times (exec / console): 3 / 29 ms PSP: Notify that POST is finishing... OK BS: BS_PAYLOAD_BOOT entry times (exec / console): 0 / 4 ms POST: 0x7b mp_park_aps done after 0 msecs. Jumping to boot code at 0x30000000(0xca66a000) POST: 0xf8 CPU0: stack: 0xca6ff000 - 0xca700000, lowest used address 0xca6ff92c, stack used: 1748 bytes Starting depthcharge on Morphius... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x300617a8 @ 00:01:07 Wipe memory regions: [0x00000000001000, 0x000000000a0000) [0x00000000100000, 0x00000002000000) [0x000000021c0000, 0x00000030000000) [0x000000310651f0, 0x000000ca527000) [0x00000100000000, 0x0000012f340000) R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device [firmware-zork-13434.B-collabora] Jan 25 2022 09:17:46 zork: tftpboot 192.168.201.1 8119404/tftp-deploy-heqw8oi3/kernel/bzImage 8119404/tftp-deploy-heqw8oi3/kernel/cmdline 8119404/tftp-deploy-heqw8oi3/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 8119404/tftp-deploy-heqw8oi3/kernel/bzImage 83/kernel/cmdline 8119404/tftp-deploy-heqw8oi3/ramdisk/ramdisk.cpio.gz Waiting for link done. MAC: f4:f5:e8:50:eb:67 Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.18 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 8119404/tftp-deploy-heqw8oi3/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ##########################################################