Boot log: asus-cx9400-volteer
- Kernel Warnings: 0
- Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
1 07:49:06.505814 lava-dispatcher, installed at version: 2022.10
2 07:49:06.506008 start: 0 validate
3 07:49:06.506146 Start time: 2022-11-25 07:49:06.506139+00:00 (UTC)
4 07:49:06.506276 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:49:06.506403 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20221107.1%2Famd64%2Frootfs.cpio.gz exists
6 07:49:06.520973 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:49:06.521100 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:49:06.536010 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:49:06.536134 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip70-98-g7f7838c92740%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 07:49:06.539336 validate duration: 0.03
12 07:49:06.539573 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 07:49:06.539677 start: 1.1 download-retry (timeout 00:10:00) [common]
14 07:49:06.539772 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 07:49:06.539879 Not decompressing ramdisk as can be used compressed.
16 07:49:06.539964 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20221107.1/amd64/rootfs.cpio.gz
17 07:49:06.540032 saving as /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/ramdisk/rootfs.cpio.gz
18 07:49:06.540093 total size: 35753913 (34MB)
19 07:49:06.595255 progress 0% (0MB)
20 07:49:06.905779 progress 5% (1MB)
21 07:49:07.199133 progress 10% (3MB)
22 07:49:07.462590 progress 15% (5MB)
23 07:49:07.668472 progress 20% (6MB)
24 07:49:07.922975 progress 25% (8MB)
25 07:49:08.242136 progress 30% (10MB)
26 07:49:08.510891 progress 35% (11MB)
27 07:49:08.817389 progress 40% (13MB)
28 07:49:09.123114 progress 45% (15MB)
29 07:49:09.433190 progress 50% (17MB)
30 07:49:09.747888 progress 55% (18MB)
31 07:49:10.054026 progress 60% (20MB)
32 07:49:10.352189 progress 65% (22MB)
33 07:49:10.668440 progress 70% (23MB)
34 07:49:10.972613 progress 75% (25MB)
35 07:49:11.280495 progress 80% (27MB)
36 07:49:11.598431 progress 85% (29MB)
37 07:49:11.914582 progress 90% (30MB)
38 07:49:12.211243 progress 95% (32MB)
39 07:49:12.504659 progress 100% (34MB)
40 07:49:12.504921 34MB downloaded in 5.96s (5.72MB/s)
41 07:49:12.505089 end: 1.1.1 http-download (duration 00:00:06) [common]
43 07:49:12.505337 end: 1.1 download-retry (duration 00:00:06) [common]
44 07:49:12.505428 start: 1.2 download-retry (timeout 00:09:54) [common]
45 07:49:12.505582 start: 1.2.1 http-download (timeout 00:09:54) [common]
46 07:49:12.505692 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 07:49:12.505760 saving as /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/kernel/bzImage
48 07:49:12.505860 total size: 7131024 (6MB)
49 07:49:12.505921 No compression specified
50 07:49:12.563990 progress 0% (0MB)
51 07:49:12.605809 progress 5% (0MB)
52 07:49:12.660096 progress 10% (0MB)
53 07:49:12.714969 progress 15% (1MB)
54 07:49:12.760441 progress 20% (1MB)
55 07:49:12.813470 progress 25% (1MB)
56 07:49:12.858657 progress 30% (2MB)
57 07:49:12.912865 progress 35% (2MB)
58 07:49:12.955308 progress 40% (2MB)
59 07:49:13.000872 progress 45% (3MB)
60 07:49:13.038265 progress 50% (3MB)
61 07:49:13.102721 progress 55% (3MB)
62 07:49:13.133694 progress 60% (4MB)
63 07:49:13.178455 progress 65% (4MB)
64 07:49:13.227002 progress 70% (4MB)
65 07:49:13.277126 progress 75% (5MB)
66 07:49:13.326220 progress 80% (5MB)
67 07:49:13.380062 progress 85% (5MB)
68 07:49:13.429986 progress 90% (6MB)
69 07:49:13.495377 progress 95% (6MB)
70 07:49:13.544068 progress 100% (6MB)
71 07:49:13.544376 6MB downloaded in 1.04s (6.55MB/s)
72 07:49:13.544531 end: 1.2.1 http-download (duration 00:00:01) [common]
74 07:49:13.544772 end: 1.2 download-retry (duration 00:00:01) [common]
75 07:49:13.544862 start: 1.3 download-retry (timeout 00:09:53) [common]
76 07:49:13.544950 start: 1.3.1 http-download (timeout 00:09:53) [common]
77 07:49:13.545065 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip70-98-g7f7838c92740/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 07:49:13.545136 saving as /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/modules/modules.tar
79 07:49:13.545199 total size: 52060 (0MB)
80 07:49:13.545260 Using unxz to decompress xz
81 07:49:13.552439 progress 62% (0MB)
82 07:49:13.553051 progress 100% (0MB)
83 07:49:13.556154 0MB downloaded in 0.01s (4.54MB/s)
84 07:49:13.556388 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:49:13.556654 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:49:13.556757 start: 1.4 prepare-tftp-overlay (timeout 00:09:53) [common]
88 07:49:13.556853 start: 1.4.1 extract-nfsrootfs (timeout 00:09:53) [common]
89 07:49:13.556940 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 07:49:13.557026 start: 1.4.2 lava-overlay (timeout 00:09:53) [common]
91 07:49:13.557194 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql
92 07:49:13.557301 makedir: /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin
93 07:49:13.557386 makedir: /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/tests
94 07:49:13.557466 makedir: /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/results
95 07:49:13.557608 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-add-keys
96 07:49:13.557738 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-add-sources
97 07:49:13.557851 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-background-process-start
98 07:49:13.557961 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-background-process-stop
99 07:49:13.558071 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-common-functions
100 07:49:13.558178 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-echo-ipv4
101 07:49:13.558288 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-install-packages
102 07:49:13.558396 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-installed-packages
103 07:49:13.558502 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-os-build
104 07:49:13.558608 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-probe-channel
105 07:49:13.558714 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-probe-ip
106 07:49:13.558846 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-target-ip
107 07:49:13.558956 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-target-mac
108 07:49:13.559098 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-target-storage
109 07:49:13.559237 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-case
110 07:49:13.559364 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-event
111 07:49:13.559491 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-feedback
112 07:49:13.559603 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-raise
113 07:49:13.559717 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-reference
114 07:49:13.559825 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-runner
115 07:49:13.559933 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-set
116 07:49:13.560039 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-test-shell
117 07:49:13.560149 Updating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-install-packages (oe)
118 07:49:13.560260 Updating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/bin/lava-installed-packages (oe)
119 07:49:13.560358 Creating /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/environment
120 07:49:13.560446 LAVA metadata
121 07:49:13.560517 - LAVA_JOB_ID=8119387
122 07:49:13.560583 - LAVA_DISPATCHER_IP=192.168.201.1
123 07:49:13.560688 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:53) [common]
124 07:49:13.560754 skipped lava-vland-overlay
125 07:49:13.560831 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 07:49:13.560916 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
127 07:49:13.560980 skipped lava-multinode-overlay
128 07:49:13.561055 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 07:49:13.561139 start: 1.4.2.3 test-definition (timeout 00:09:53) [common]
130 07:49:13.561225 Loading test definitions
131 07:49:13.561324 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:53) [common]
132 07:49:13.561400 Using /lava-8119387 at stage 0
133 07:49:13.561704 uuid=8119387_1.4.2.3.1 testdef=None
134 07:49:13.561795 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 07:49:13.561886 start: 1.4.2.3.2 test-overlay (timeout 00:09:53) [common]
136 07:49:13.562388 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 07:49:13.562617 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:53) [common]
139 07:49:13.563154 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 07:49:13.563395 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
142 07:49:13.563899 runner path: /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/0/tests/0_cros-ec test_uuid 8119387_1.4.2.3.1
143 07:49:13.564046 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 07:49:13.564254 Creating lava-test-runner.conf files
146 07:49:13.564319 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8119387/lava-overlay-pshk9kql/lava-8119387/0 for stage 0
147 07:49:13.564400 - 0_cros-ec
148 07:49:13.564492 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
149 07:49:13.564582 start: 1.4.2.4 compress-overlay (timeout 00:09:53) [common]
150 07:49:13.569692 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
151 07:49:13.569893 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
152 07:49:13.569982 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
153 07:49:13.570069 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
154 07:49:13.570155 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
155 07:49:14.320282 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:01) [common]
156 07:49:14.320618 start: 1.4.4 extract-modules (timeout 00:09:52) [common]
157 07:49:14.320734 extracting modules file /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8119387/extract-overlay-ramdisk-upoqoyd2/ramdisk
158 07:49:14.324900 end: 1.4.4 extract-modules (duration 00:00:00) [common]
159 07:49:14.325014 start: 1.4.5 apply-overlay-tftp (timeout 00:09:52) [common]
160 07:49:14.325099 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119387/compress-overlay-ar1qa24z/overlay-1.4.2.4.tar.gz to ramdisk
161 07:49:14.325174 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8119387/compress-overlay-ar1qa24z/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8119387/extract-overlay-ramdisk-upoqoyd2/ramdisk
162 07:49:14.328338 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
163 07:49:14.328449 start: 1.4.6 configure-preseed-file (timeout 00:09:52) [common]
164 07:49:14.328542 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
165 07:49:14.328636 start: 1.4.7 compress-ramdisk (timeout 00:09:52) [common]
166 07:49:14.328733 Building ramdisk /var/lib/lava/dispatcher/tmp/8119387/extract-overlay-ramdisk-upoqoyd2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8119387/extract-overlay-ramdisk-upoqoyd2/ramdisk
167 07:49:14.574473 >> 182463 blocks
168 07:49:17.791317 rename /var/lib/lava/dispatcher/tmp/8119387/extract-overlay-ramdisk-upoqoyd2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
169 07:49:17.791741 end: 1.4.7 compress-ramdisk (duration 00:00:03) [common]
170 07:49:17.791869 start: 1.4.8 prepare-kernel (timeout 00:09:49) [common]
171 07:49:17.791975 start: 1.4.8.1 prepare-fit (timeout 00:09:49) [common]
172 07:49:17.792074 No mkimage arch provided, not using FIT.
173 07:49:17.792163 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
174 07:49:17.792249 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
175 07:49:17.792355 end: 1.4 prepare-tftp-overlay (duration 00:00:04) [common]
176 07:49:17.792471 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:49) [common]
177 07:49:17.792582 No LXC device requested
178 07:49:17.792662 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
179 07:49:17.792752 start: 1.6 deploy-device-env (timeout 00:09:49) [common]
180 07:49:17.792838 end: 1.6 deploy-device-env (duration 00:00:00) [common]
181 07:49:17.792910 Checking files for TFTP limit of 4294967296 bytes.
182 07:49:17.793322 end: 1 tftp-deploy (duration 00:00:11) [common]
183 07:49:17.793427 start: 2 depthcharge-action (timeout 00:05:00) [common]
184 07:49:17.793587 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
185 07:49:17.793714 substitutions:
186 07:49:17.793780 - {DTB}: None
187 07:49:17.793849 - {INITRD}: 8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
188 07:49:17.793909 - {KERNEL}: 8119387/tftp-deploy-2gy0ytrs/kernel/bzImage
189 07:49:17.793968 - {LAVA_MAC}: None
190 07:49:17.794026 - {PRESEED_CONFIG}: None
191 07:49:17.794080 - {PRESEED_LOCAL}: None
192 07:49:17.794135 - {RAMDISK}: 8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
193 07:49:17.794189 - {ROOT_PART}: None
194 07:49:17.794242 - {ROOT}: None
195 07:49:17.794296 - {SERVER_IP}: 192.168.201.1
196 07:49:17.794349 - {TEE}: None
197 07:49:17.794402 Parsed boot commands:
198 07:49:17.794455 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
199 07:49:17.794604 Parsed boot commands: tftpboot 192.168.201.1 8119387/tftp-deploy-2gy0ytrs/kernel/bzImage 8119387/tftp-deploy-2gy0ytrs/kernel/cmdline 8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
200 07:49:17.794692 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
201 07:49:17.794778 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
202 07:49:17.794869 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
203 07:49:17.794964 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
204 07:49:17.795035 Not connected, no need to disconnect.
205 07:49:17.795119 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
206 07:49:17.795201 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
207 07:49:17.795266 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-9'
208 07:49:17.798249 Setting prompt string to ['lava-test: # ']
209 07:49:17.798633 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
210 07:49:17.798742 end: 2.2.1 reset-connection (duration 00:00:00) [common]
211 07:49:17.798838 start: 2.2.2 reset-device (timeout 00:05:00) [common]
212 07:49:17.798929 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
213 07:49:17.799116 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-9' '--port=1' '--command=reboot'
214 07:49:17.819901 >> Command sent successfully.
215 07:49:17.822116 Returned 0 in 0 seconds
216 07:49:17.922983 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
218 07:49:17.923513 end: 2.2.2 reset-device (duration 00:00:00) [common]
219 07:49:17.923675 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
220 07:49:17.923814 Setting prompt string to 'Starting depthcharge on Voema...'
221 07:49:17.923929 Changing prompt to 'Starting depthcharge on Voema...'
222 07:49:17.924045 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
223 07:49:17.924468 [Enter `^Ec?' for help]
224 07:49:25.300904
225 07:49:25.301068
226 07:49:25.310592 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
227 07:49:25.313785 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
228 07:49:25.317074
229 07:49:25.320335 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
230 07:49:25.323842 CPU: AES supported, TXT NOT supported, VT supported
231 07:49:25.330622 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
232 07:49:25.337074 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
233 07:49:25.340031 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
234 07:49:25.343942 VBOOT: Loading verstage.
235 07:49:25.350372 FMAP: Found "FLASH" version 1.1 at 0x1804000.
236 07:49:25.353854 FMAP: base = 0x0 size = 0x2000000 #areas = 32
237 07:49:25.356815 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
238 07:49:25.367805 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
239 07:49:25.374273 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
240 07:49:25.374370
241 07:49:25.374437
242 07:49:25.387524 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
243 07:49:25.401435 Probing TPM: . done!
244 07:49:25.404466 TPM ready after 0 ms
245 07:49:25.408222 Connected to device vid:did:rid of 1ae0:0028:00
246 07:49:25.419234 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
247 07:49:25.425693 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
248 07:49:25.429227 Initialized TPM device CR50 revision 0
249 07:49:25.479803 tlcl_send_startup: Startup return code is 0
250 07:49:25.479954 TPM: setup succeeded
251 07:49:25.495356 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
252 07:49:25.510423 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
253 07:49:25.524320 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
254 07:49:25.534330 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
255 07:49:25.537961 Chrome EC: UHEPI supported
256 07:49:25.541416 Phase 1
257 07:49:25.545020 FMAP: area GBB found @ 1805000 (458752 bytes)
258 07:49:25.554692 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
259 07:49:25.562068 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
260 07:49:25.567844 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
261 07:49:25.574979 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
262 07:49:25.577754 Recovery requested (1009000e)
263 07:49:25.581350 TPM: Extending digest for VBOOT: boot mode into PCR 0
264 07:49:25.586965
265 07:49:25.593447 tlcl_extend: response is 0
266 07:49:25.599703 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
267 07:49:25.609876 tlcl_extend: response is 0
268 07:49:25.616262 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
269 07:49:25.622775 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
270 07:49:25.629484 BS: verstage times (exec / console): total (unknown) / 142 ms
271 07:49:25.629616
272 07:49:25.629686
273 07:49:25.642622 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
274 07:49:25.649579 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
275 07:49:25.652655 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
276 07:49:25.656125 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
277 07:49:25.662686 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
278 07:49:25.666088 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
279 07:49:25.669318 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
280 07:49:25.672637 TCO_STS: 0000 0000
281 07:49:25.676585 GEN_PMCON: d0015038 00002200
282 07:49:25.679473 GBLRST_CAUSE: 00000000 00000000
283 07:49:25.679584 HPR_CAUSE0: 00000000
284 07:49:25.682609 prev_sleep_state 5
285 07:49:25.685865 Boot Count incremented to 12932
286 07:49:25.692704 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
287 07:49:25.699172 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
288 07:49:25.705736 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
289 07:49:25.709304
290 07:49:25.715684 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
291 07:49:25.719072 Chrome EC: UHEPI supported
292 07:49:25.725865 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
293 07:49:25.736586 Probing TPM: done!
294 07:49:25.744098 Connected to device vid:did:rid of 1ae0:0028:00
295 07:49:25.754625 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
296 07:49:25.761958 Initialized TPM device CR50 revision 0
297 07:49:25.771672 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
298 07:49:25.775168
299 07:49:25.778613 MRC: Hash idx 0x100b comparison successful.
300 07:49:25.781978 MRC cache found, size faa8
301 07:49:25.782064 bootmode is set to: 2
302 07:49:25.785087 SPD index = 0
303 07:49:25.792191 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
304 07:49:25.795257 SPD: module type is LPDDR4X
305 07:49:25.798399 SPD: module part number is MT53E512M64D4NW-046
306 07:49:25.805074 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
307 07:49:25.808259 SPD: device width 16 bits, bus width 16 bits
308 07:49:25.811533
309 07:49:25.814816 SPD: module size is 1024 MB (per channel)
310 07:49:26.246227 CBMEM:
311 07:49:26.249927 IMD: root @ 0x76fff000 254 entries.
312 07:49:26.252938 IMD: root @ 0x76ffec00 62 entries.
313 07:49:26.256270 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
314 07:49:26.262774 FMAP: area RW_VPD found @ f35000 (8192 bytes)
315 07:49:26.266258 External stage cache:
316 07:49:26.269547 IMD: root @ 0x7b3ff000 254 entries.
317 07:49:26.272519 IMD: root @ 0x7b3fec00 62 entries.
318 07:49:26.288019 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
319 07:49:26.295024 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
320 07:49:26.301354 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
321 07:49:26.315480 MRC: 'RECOVERY_MRC_CACHE' does not need update.
322 07:49:26.319005 cse_lite: Skip switching to RW in the recovery path
323 07:49:26.322529 8 DIMMs found
324 07:49:26.322617 SMM Memory Map
325 07:49:26.326293 SMRAM : 0x7b000000 0x800000
326 07:49:26.329242 Subregion 0: 0x7b000000 0x200000
327 07:49:26.332547 Subregion 1: 0x7b200000 0x200000
328 07:49:26.335925 Subregion 2: 0x7b400000 0x400000
329 07:49:26.339454 top_of_ram = 0x77000000
330 07:49:26.345919 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
331 07:49:26.349204 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
332 07:49:26.356176 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
333 07:49:26.359367 MTRR Range: Start=ff000000 End=0 (Size 1000000)
334 07:49:26.369367 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
335 07:49:26.375911 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
336 07:49:26.385599 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
337 07:49:26.388828 Processing 211 relocs. Offset value of 0x74c0b000
338 07:49:26.398482 BS: romstage times (exec / console): total (unknown) / 277 ms
339 07:49:26.404488
340 07:49:26.404624
341 07:49:26.413976 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
342 07:49:26.417282 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
343 07:49:26.427324 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
344 07:49:26.434245 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
345 07:49:26.440541 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
346 07:49:26.446943 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
347 07:49:26.494333 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
348 07:49:26.500848 Processing 5008 relocs. Offset value of 0x75d98000
349 07:49:26.504009 BS: postcar times (exec / console): total (unknown) / 59 ms
350 07:49:26.507507
351 07:49:26.507601
352 07:49:26.517976 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
353 07:49:26.518100 Normal boot
354 07:49:26.521342 FW_CONFIG value is 0x804c02
355 07:49:26.524630 PCI: 00:07.0 disabled by fw_config
356 07:49:26.528208 PCI: 00:07.1 disabled by fw_config
357 07:49:26.531136 PCI: 00:0d.2 disabled by fw_config
358 07:49:26.534691 PCI: 00:1c.7 disabled by fw_config
359 07:49:26.541165 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
360 07:49:26.547865 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
361 07:49:26.551430 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
362 07:49:26.554238 GENERIC: 0.0 disabled by fw_config
363 07:49:26.557974 GENERIC: 1.0 disabled by fw_config
364 07:49:26.564449 fw_config match found: DB_USB=USB3_ACTIVE
365 07:49:26.567519 fw_config match found: DB_USB=USB3_ACTIVE
366 07:49:26.571164 fw_config match found: DB_USB=USB3_ACTIVE
367 07:49:26.574390 fw_config match found: DB_USB=USB3_ACTIVE
368 07:49:26.580976 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
369 07:49:26.587512 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
370 07:49:26.594130 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
371 07:49:26.604248 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
372 07:49:26.607248 microcode: sig=0x806c1 pf=0x80 revision=0x86
373 07:49:26.614047 microcode: Update skipped, already up-to-date
374 07:49:26.620892 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
375 07:49:26.647648 Detected 4 core, 8 thread CPU.
376 07:49:26.650952 Setting up SMI for CPU
377 07:49:26.654291 IED base = 0x7b400000
378 07:49:26.654380 IED size = 0x00400000
379 07:49:26.657771 Will perform SMM setup.
380 07:49:26.664608 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
381 07:49:26.671290 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
382 07:49:26.677837 Processing 16 relocs. Offset value of 0x00030000
383 07:49:26.681221 Attempting to start 7 APs
384 07:49:26.684410 Waiting for 10ms after sending INIT.
385 07:49:26.699909 Waiting for 1st SIPI to complete...done.
386 07:49:26.700073 AP: slot 6 apic_id 2.
387 07:49:26.703003 AP: slot 2 apic_id 3.
388 07:49:26.706547 AP: slot 7 apic_id 7.
389 07:49:26.706664 AP: slot 1 apic_id 1.
390 07:49:26.709683 AP: slot 4 apic_id 5.
391 07:49:26.713281 AP: slot 5 apic_id 4.
392 07:49:26.716368 Waiting for 2nd SIPI to complete...done.
393 07:49:26.719919 AP: slot 3 apic_id 6.
394 07:49:26.726178 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
395 07:49:26.732957 Processing 13 relocs. Offset value of 0x00038000
396 07:49:26.733056 Unable to locate Global NVS
397 07:49:26.736503
398 07:49:26.742946 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
399 07:49:26.746188 Installing permanent SMM handler to 0x7b000000
400 07:49:26.756050 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
401 07:49:26.759583 Processing 794 relocs. Offset value of 0x7b010000
402 07:49:26.769386 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
403 07:49:26.773026 Processing 13 relocs. Offset value of 0x7b008000
404 07:49:26.779497 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
405 07:49:26.786282 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
406 07:49:26.789288 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
407 07:49:26.795860 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
408 07:49:26.802654 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
409 07:49:26.809651 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
410 07:49:26.816058 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
411 07:49:26.816173 Unable to locate Global NVS
412 07:49:26.825820 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
413 07:49:26.828951 Clearing SMI status registers
414 07:49:26.829042 SMI_STS: PM1
415 07:49:26.832487 PM1_STS: PWRBTN
416 07:49:26.839100 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
417 07:49:26.842359 In relocation handler: CPU 0
418 07:49:26.845924 New SMBASE=0x7b000000 IEDBASE=0x7b400000
419 07:49:26.852372 Writing SMRR. base = 0x7b000006, mask=0xff800c00
420 07:49:26.852493 Relocation complete.
421 07:49:26.862650 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
422 07:49:26.862758 In relocation handler: CPU 1
423 07:49:26.868897 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
424 07:49:26.868998 Relocation complete.
425 07:49:26.878774 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
426 07:49:26.878936 In relocation handler: CPU 4
427 07:49:26.885718 New SMBASE=0x7afff000 IEDBASE=0x7b400000
428 07:49:26.885810 Relocation complete.
429 07:49:26.895368 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
430 07:49:26.895468 In relocation handler: CPU 5
431 07:49:26.902103 New SMBASE=0x7affec00 IEDBASE=0x7b400000
432 07:49:26.905321 Writing SMRR. base = 0x7b000006, mask=0xff800c00
433 07:49:26.908480 Relocation complete.
434 07:49:26.915162 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
435 07:49:26.918751 In relocation handler: CPU 6
436 07:49:26.921804 New SMBASE=0x7affe800 IEDBASE=0x7b400000
437 07:49:26.928325 Writing SMRR. base = 0x7b000006, mask=0xff800c00
438 07:49:26.928434 Relocation complete.
439 07:49:26.935523 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
440 07:49:26.938252 In relocation handler: CPU 2
441 07:49:26.945559 New SMBASE=0x7afff800 IEDBASE=0x7b400000
442 07:49:26.945653 Relocation complete.
443 07:49:26.951503 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
444 07:49:26.954852 In relocation handler: CPU 7
445 07:49:26.961383 New SMBASE=0x7affe400 IEDBASE=0x7b400000
446 07:49:26.961517 Relocation complete.
447 07:49:26.968173 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
448 07:49:26.971754 In relocation handler: CPU 3
449 07:49:26.974853 New SMBASE=0x7afff400 IEDBASE=0x7b400000
450 07:49:26.977989
451 07:49:26.981572 Writing SMRR. base = 0x7b000006, mask=0xff800c00
452 07:49:26.985516 Relocation complete.
453 07:49:26.985636 Initializing CPU #0
454 07:49:26.989498 CPU: vendor Intel device 806c1
455 07:49:26.992532 CPU: family 06, model 8c, stepping 01
456 07:49:26.996210 Clearing out pending MCEs
457 07:49:26.999125 Setting up local APIC...
458 07:49:26.999221 apic_id: 0x00 done.
459 07:49:27.002704 Turbo is available but hidden
460 07:49:27.005898 Turbo is available and visible
461 07:49:27.012794 microcode: Update skipped, already up-to-date
462 07:49:27.012887 CPU #0 initialized
463 07:49:27.015795 Initializing CPU #2
464 07:49:27.015882 Initializing CPU #1
465 07:49:27.019024 Initializing CPU #6
466 07:49:27.022517 CPU: vendor Intel device 806c1
467 07:49:27.025996 CPU: family 06, model 8c, stepping 01
468 07:49:27.028954 CPU: vendor Intel device 806c1
469 07:49:27.032568 CPU: family 06, model 8c, stepping 01
470 07:49:27.035689 Clearing out pending MCEs
471 07:49:27.038971 Clearing out pending MCEs
472 07:49:27.042497 Setting up local APIC...
473 07:49:27.042589 Initializing CPU #7
474 07:49:27.045682 Initializing CPU #3
475 07:49:27.049380 CPU: vendor Intel device 806c1
476 07:49:27.052213 CPU: family 06, model 8c, stepping 01
477 07:49:27.055937 CPU: vendor Intel device 806c1
478 07:49:27.058939 CPU: family 06, model 8c, stepping 01
479 07:49:27.062517 Clearing out pending MCEs
480 07:49:27.065681 Clearing out pending MCEs
481 07:49:27.065768 Initializing CPU #5
482 07:49:27.068887 Initializing CPU #4
483 07:49:27.072470 CPU: vendor Intel device 806c1
484 07:49:27.075568 CPU: family 06, model 8c, stepping 01
485 07:49:27.078880 Setting up local APIC...
486 07:49:27.078968 Setting up local APIC...
487 07:49:27.082227 CPU: vendor Intel device 806c1
488 07:49:27.088871 CPU: family 06, model 8c, stepping 01
489 07:49:27.088957 CPU: vendor Intel device 806c1
490 07:49:27.092091
491 07:49:27.095656 CPU: family 06, model 8c, stepping 01
492 07:49:27.095768 apic_id: 0x02 done.
493 07:49:27.098974 apic_id: 0x03 done.
494 07:49:27.102139 microcode: Update skipped, already up-to-date
495 07:49:27.109075 microcode: Update skipped, already up-to-date
496 07:49:27.109172 CPU #6 initialized
497 07:49:27.112111 CPU #2 initialized
498 07:49:27.115550 apic_id: 0x07 done.
499 07:49:27.115633 Setting up local APIC...
500 07:49:27.118538 Clearing out pending MCEs
501 07:49:27.121932 Clearing out pending MCEs
502 07:49:27.125266 Setting up local APIC...
503 07:49:27.128712 microcode: Update skipped, already up-to-date
504 07:49:27.132038 apic_id: 0x05 done.
505 07:49:27.132146 Setting up local APIC...
506 07:49:27.135209 CPU #7 initialized
507 07:49:27.138465 apic_id: 0x06 done.
508 07:49:27.138547 apic_id: 0x04 done.
509 07:49:27.145350 microcode: Update skipped, already up-to-date
510 07:49:27.148458 microcode: Update skipped, already up-to-date
511 07:49:27.151845 CPU #4 initialized
512 07:49:27.151951 CPU #5 initialized
513 07:49:27.158887 microcode: Update skipped, already up-to-date
514 07:49:27.158994 Clearing out pending MCEs
515 07:49:27.161934 CPU #3 initialized
516 07:49:27.165309 Setting up local APIC...
517 07:49:27.165415 apic_id: 0x01 done.
518 07:49:27.168871
519 07:49:27.172224 microcode: Update skipped, already up-to-date
520 07:49:27.175005 CPU #1 initialized
521 07:49:27.178698 bsp_do_flight_plan done after 457 msecs.
522 07:49:27.181699 CPU: frequency set to 4000 MHz
523 07:49:27.181822 Enabling SMIs.
524 07:49:27.188705 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
525 07:49:27.204795 SATAXPCIE1 indicates PCIe NVMe is present
526 07:49:27.204940 Probing TPM: done!
527 07:49:27.208206
528 07:49:27.211738 Connected to device vid:did:rid of 1ae0:0028:00
529 07:49:27.222230 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
530 07:49:27.225374 Initialized TPM device CR50 revision 0
531 07:49:27.228899 Enabling S0i3.4
532 07:49:27.235573 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
533 07:49:27.239078 Found a VBT of 8704 bytes after decompression
534 07:49:27.245656 cse_lite: CSE RO boot. HybridStorageMode disabled
535 07:49:27.251846 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
536 07:49:27.327144 FSPS returned 0
537 07:49:27.330418 Executing Phase 1 of FspMultiPhaseSiInit
538 07:49:27.340528 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
539 07:49:27.343837 port C0 DISC req: usage 1 usb3 1 usb2 5
540 07:49:27.347182 Raw Buffer output 0 00000511
541 07:49:27.350474 Raw Buffer output 1 00000000
542 07:49:27.354357 pmc_send_ipc_cmd succeeded
543 07:49:27.357903 port C1 DISC req: usage 1 usb3 2 usb2 3
544 07:49:27.361131
545 07:49:27.361219 Raw Buffer output 0 00000321
546 07:49:27.364061 Raw Buffer output 1 00000000
547 07:49:27.368248 pmc_send_ipc_cmd succeeded
548 07:49:27.373339 Detected 4 core, 8 thread CPU.
549 07:49:27.376735 Detected 4 core, 8 thread CPU.
550 07:49:27.610299 Display FSP Version Info HOB
551 07:49:27.613941 Reference Code - CPU = a.0.4c.31
552 07:49:27.617109 uCode Version = 0.0.0.86
553 07:49:27.620210 TXT ACM version = ff.ff.ff.ffff
554 07:49:27.624061 Reference Code - ME = a.0.4c.31
555 07:49:27.627173 MEBx version = 0.0.0.0
556 07:49:27.630476 ME Firmware Version = Consumer SKU
557 07:49:27.633853 Reference Code - PCH = a.0.4c.31
558 07:49:27.636913 PCH-CRID Status = Disabled
559 07:49:27.640356 PCH-CRID Original Value = ff.ff.ff.ffff
560 07:49:27.643453 PCH-CRID New Value = ff.ff.ff.ffff
561 07:49:27.646972 OPROM - RST - RAID = ff.ff.ff.ffff
562 07:49:27.650169 PCH Hsio Version = 4.0.0.0
563 07:49:27.653423 Reference Code - SA - System Agent = a.0.4c.31
564 07:49:27.656849 Reference Code - MRC = 2.0.0.1
565 07:49:27.659992 SA - PCIe Version = a.0.4c.31
566 07:49:27.663688 SA-CRID Status = Disabled
567 07:49:27.667134 SA-CRID Original Value = 0.0.0.1
568 07:49:27.670135 SA-CRID New Value = 0.0.0.1
569 07:49:27.673390 OPROM - VBIOS = ff.ff.ff.ffff
570 07:49:27.676862 IO Manageability Engine FW Version = 11.1.4.0
571 07:49:27.679885 PHY Build Version = 0.0.0.e0
572 07:49:27.683899 Thunderbolt(TM) FW Version = 0.0.0.0
573 07:49:27.690090 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
574 07:49:27.693426 ITSS IRQ Polarities Before:
575 07:49:27.693581 IPC0: 0xffffffff
576 07:49:27.696553 IPC1: 0xffffffff
577 07:49:27.696633 IPC2: 0xffffffff
578 07:49:27.700174 IPC3: 0xffffffff
579 07:49:27.703078 ITSS IRQ Polarities After:
580 07:49:27.703205 IPC0: 0xffffffff
581 07:49:27.706551 IPC1: 0xffffffff
582 07:49:27.706634 IPC2: 0xffffffff
583 07:49:27.710050 IPC3: 0xffffffff
584 07:49:27.713272 Found PCIe Root Port #9 at PCI: 00:1d.0.
585 07:49:27.726750 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
586 07:49:27.736713 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
587 07:49:27.749748 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
588 07:49:27.756305 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
589 07:49:27.756422 Enumerating buses...
590 07:49:27.759579
591 07:49:27.763178 Show all devs... Before device enumeration.
592 07:49:27.766303 Root Device: enabled 1
593 07:49:27.766403 DOMAIN: 0000: enabled 1
594 07:49:27.769757 CPU_CLUSTER: 0: enabled 1
595 07:49:27.773019 PCI: 00:00.0: enabled 1
596 07:49:27.776344 PCI: 00:02.0: enabled 1
597 07:49:27.776434 PCI: 00:04.0: enabled 1
598 07:49:27.779501 PCI: 00:05.0: enabled 1
599 07:49:27.782988 PCI: 00:06.0: enabled 0
600 07:49:27.783077 PCI: 00:07.0: enabled 0
601 07:49:27.786059
602 07:49:27.786146 PCI: 00:07.1: enabled 0
603 07:49:27.789494 PCI: 00:07.2: enabled 0
604 07:49:27.792650 PCI: 00:07.3: enabled 0
605 07:49:27.792736 PCI: 00:08.0: enabled 1
606 07:49:27.796361 PCI: 00:09.0: enabled 0
607 07:49:27.799213 PCI: 00:0a.0: enabled 0
608 07:49:27.803136 PCI: 00:0d.0: enabled 1
609 07:49:27.803232 PCI: 00:0d.1: enabled 0
610 07:49:27.805948 PCI: 00:0d.2: enabled 0
611 07:49:27.809542 PCI: 00:0d.3: enabled 0
612 07:49:27.812383 PCI: 00:0e.0: enabled 0
613 07:49:27.812488 PCI: 00:10.2: enabled 1
614 07:49:27.815901 PCI: 00:10.6: enabled 0
615 07:49:27.819118 PCI: 00:10.7: enabled 0
616 07:49:27.822669 PCI: 00:12.0: enabled 0
617 07:49:27.822756 PCI: 00:12.6: enabled 0
618 07:49:27.826037 PCI: 00:13.0: enabled 0
619 07:49:27.829083 PCI: 00:14.0: enabled 1
620 07:49:27.829162 PCI: 00:14.1: enabled 0
621 07:49:27.832492
622 07:49:27.832577 PCI: 00:14.2: enabled 1
623 07:49:27.835579 PCI: 00:14.3: enabled 1
624 07:49:27.839156 PCI: 00:15.0: enabled 1
625 07:49:27.839252 PCI: 00:15.1: enabled 1
626 07:49:27.842555 PCI: 00:15.2: enabled 1
627 07:49:27.845648 PCI: 00:15.3: enabled 1
628 07:49:27.848863 PCI: 00:16.0: enabled 1
629 07:49:27.848953 PCI: 00:16.1: enabled 0
630 07:49:27.852301 PCI: 00:16.2: enabled 0
631 07:49:27.855863 PCI: 00:16.3: enabled 0
632 07:49:27.858940 PCI: 00:16.4: enabled 0
633 07:49:27.859033 PCI: 00:16.5: enabled 0
634 07:49:27.862366 PCI: 00:17.0: enabled 1
635 07:49:27.865496 PCI: 00:19.0: enabled 0
636 07:49:27.868673 PCI: 00:19.1: enabled 1
637 07:49:27.868767 PCI: 00:19.2: enabled 0
638 07:49:27.872266 PCI: 00:1c.0: enabled 1
639 07:49:27.875432 PCI: 00:1c.1: enabled 0
640 07:49:27.878862 PCI: 00:1c.2: enabled 0
641 07:49:27.878955 PCI: 00:1c.3: enabled 0
642 07:49:27.881872 PCI: 00:1c.4: enabled 0
643 07:49:27.885563 PCI: 00:1c.5: enabled 0
644 07:49:27.885652 PCI: 00:1c.6: enabled 1
645 07:49:27.888552
646 07:49:27.888635 PCI: 00:1c.7: enabled 0
647 07:49:27.891922 PCI: 00:1d.0: enabled 1
648 07:49:27.895361 PCI: 00:1d.1: enabled 0
649 07:49:27.895450 PCI: 00:1d.2: enabled 1
650 07:49:27.898854 PCI: 00:1d.3: enabled 0
651 07:49:27.902273 PCI: 00:1e.0: enabled 1
652 07:49:27.905261 PCI: 00:1e.1: enabled 0
653 07:49:27.905347 PCI: 00:1e.2: enabled 1
654 07:49:27.908424 PCI: 00:1e.3: enabled 1
655 07:49:27.911664 PCI: 00:1f.0: enabled 1
656 07:49:27.915253 PCI: 00:1f.1: enabled 0
657 07:49:27.915340 PCI: 00:1f.2: enabled 1
658 07:49:27.918363 PCI: 00:1f.3: enabled 1
659 07:49:27.921844 PCI: 00:1f.4: enabled 0
660 07:49:27.924933 PCI: 00:1f.5: enabled 1
661 07:49:27.925026 PCI: 00:1f.6: enabled 0
662 07:49:27.928488 PCI: 00:1f.7: enabled 0
663 07:49:27.931871 APIC: 00: enabled 1
664 07:49:27.931965 GENERIC: 0.0: enabled 1
665 07:49:27.934986 GENERIC: 0.0: enabled 1
666 07:49:27.938537 GENERIC: 1.0: enabled 1
667 07:49:27.941932 GENERIC: 0.0: enabled 1
668 07:49:27.942020 GENERIC: 1.0: enabled 1
669 07:49:27.945209 USB0 port 0: enabled 1
670 07:49:27.948501 GENERIC: 0.0: enabled 1
671 07:49:27.948584 USB0 port 0: enabled 1
672 07:49:27.951965 GENERIC: 0.0: enabled 1
673 07:49:27.955011 I2C: 00:1a: enabled 1
674 07:49:27.958211 I2C: 00:31: enabled 1
675 07:49:27.958302 I2C: 00:32: enabled 1
676 07:49:27.961433 I2C: 00:10: enabled 1
677 07:49:27.965069 I2C: 00:15: enabled 1
678 07:49:27.965181 GENERIC: 0.0: enabled 0
679 07:49:27.968164 GENERIC: 1.0: enabled 0
680 07:49:27.971414 GENERIC: 0.0: enabled 1
681 07:49:27.971521 SPI: 00: enabled 1
682 07:49:27.974760 SPI: 00: enabled 1
683 07:49:27.978394 PNP: 0c09.0: enabled 1
684 07:49:27.978478 GENERIC: 0.0: enabled 1
685 07:49:27.981593 USB3 port 0: enabled 1
686 07:49:27.984659 USB3 port 1: enabled 1
687 07:49:27.988138 USB3 port 2: enabled 0
688 07:49:27.988224 USB3 port 3: enabled 0
689 07:49:27.991669 USB2 port 0: enabled 0
690 07:49:27.994982 USB2 port 1: enabled 1
691 07:49:27.995069 USB2 port 2: enabled 1
692 07:49:27.998112 USB2 port 3: enabled 0
693 07:49:28.001298 USB2 port 4: enabled 1
694 07:49:28.001420 USB2 port 5: enabled 0
695 07:49:28.004754
696 07:49:28.004838 USB2 port 6: enabled 0
697 07:49:28.007996 USB2 port 7: enabled 0
698 07:49:28.011309 USB2 port 8: enabled 0
699 07:49:28.011403 USB2 port 9: enabled 0
700 07:49:28.014513 USB3 port 0: enabled 0
701 07:49:28.018524 USB3 port 1: enabled 1
702 07:49:28.018643 USB3 port 2: enabled 0
703 07:49:28.021403 USB3 port 3: enabled 0
704 07:49:28.024839 GENERIC: 0.0: enabled 1
705 07:49:28.028057 GENERIC: 1.0: enabled 1
706 07:49:28.028151 APIC: 01: enabled 1
707 07:49:28.031474 APIC: 03: enabled 1
708 07:49:28.031591 APIC: 06: enabled 1
709 07:49:28.034662
710 07:49:28.034748 APIC: 05: enabled 1
711 07:49:28.037763 APIC: 04: enabled 1
712 07:49:28.037848 APIC: 02: enabled 1
713 07:49:28.041134 APIC: 07: enabled 1
714 07:49:28.044444 Compare with tree...
715 07:49:28.044531 Root Device: enabled 1
716 07:49:28.047622 DOMAIN: 0000: enabled 1
717 07:49:28.051124 PCI: 00:00.0: enabled 1
718 07:49:28.054517 PCI: 00:02.0: enabled 1
719 07:49:28.054607 PCI: 00:04.0: enabled 1
720 07:49:28.058100
721 07:49:28.058185 GENERIC: 0.0: enabled 1
722 07:49:28.061054 PCI: 00:05.0: enabled 1
723 07:49:28.064223 PCI: 00:06.0: enabled 0
724 07:49:28.067713 PCI: 00:07.0: enabled 0
725 07:49:28.070974 GENERIC: 0.0: enabled 1
726 07:49:28.071058 PCI: 00:07.1: enabled 0
727 07:49:28.074455 GENERIC: 1.0: enabled 1
728 07:49:28.077749 PCI: 00:07.2: enabled 0
729 07:49:28.080822 GENERIC: 0.0: enabled 1
730 07:49:28.084463 PCI: 00:07.3: enabled 0
731 07:49:28.084555 GENERIC: 1.0: enabled 1
732 07:49:28.087352 PCI: 00:08.0: enabled 1
733 07:49:28.091059 PCI: 00:09.0: enabled 0
734 07:49:28.094330 PCI: 00:0a.0: enabled 0
735 07:49:28.097688 PCI: 00:0d.0: enabled 1
736 07:49:28.097778 USB0 port 0: enabled 1
737 07:49:28.100704 USB3 port 0: enabled 1
738 07:49:28.104104 USB3 port 1: enabled 1
739 07:49:28.107466 USB3 port 2: enabled 0
740 07:49:28.110895 USB3 port 3: enabled 0
741 07:49:28.110983 PCI: 00:0d.1: enabled 0
742 07:49:28.113973
743 07:49:28.114061 PCI: 00:0d.2: enabled 0
744 07:49:28.117090 GENERIC: 0.0: enabled 1
745 07:49:28.120849 PCI: 00:0d.3: enabled 0
746 07:49:28.123868 PCI: 00:0e.0: enabled 0
747 07:49:28.123963 PCI: 00:10.2: enabled 1
748 07:49:28.127640
749 07:49:28.127754 PCI: 00:10.6: enabled 0
750 07:49:28.130817 PCI: 00:10.7: enabled 0
751 07:49:28.134118 PCI: 00:12.0: enabled 0
752 07:49:28.137138 PCI: 00:12.6: enabled 0
753 07:49:28.137236 PCI: 00:13.0: enabled 0
754 07:49:28.140580 PCI: 00:14.0: enabled 1
755 07:49:28.143882 USB0 port 0: enabled 1
756 07:49:28.147355 USB2 port 0: enabled 0
757 07:49:28.150449 USB2 port 1: enabled 1
758 07:49:28.153721 USB2 port 2: enabled 1
759 07:49:28.153803 USB2 port 3: enabled 0
760 07:49:28.157209 USB2 port 4: enabled 1
761 07:49:28.160412 USB2 port 5: enabled 0
762 07:49:28.163730 USB2 port 6: enabled 0
763 07:49:28.167033 USB2 port 7: enabled 0
764 07:49:28.167127 USB2 port 8: enabled 0
765 07:49:28.170464
766 07:49:28.170547 USB2 port 9: enabled 0
767 07:49:28.173819 USB3 port 0: enabled 0
768 07:49:28.176781 USB3 port 1: enabled 1
769 07:49:28.180283 USB3 port 2: enabled 0
770 07:49:28.183277 USB3 port 3: enabled 0
771 07:49:28.183389 PCI: 00:14.1: enabled 0
772 07:49:28.186914 PCI: 00:14.2: enabled 1
773 07:49:28.189998 PCI: 00:14.3: enabled 1
774 07:49:28.193705 GENERIC: 0.0: enabled 1
775 07:49:28.196769 PCI: 00:15.0: enabled 1
776 07:49:28.196859 I2C: 00:1a: enabled 1
777 07:49:28.200139 I2C: 00:31: enabled 1
778 07:49:28.203357 I2C: 00:32: enabled 1
779 07:49:28.206619 PCI: 00:15.1: enabled 1
780 07:49:28.209964 I2C: 00:10: enabled 1
781 07:49:28.210056 PCI: 00:15.2: enabled 1
782 07:49:28.213226 PCI: 00:15.3: enabled 1
783 07:49:28.216601 PCI: 00:16.0: enabled 1
784 07:49:28.220003 PCI: 00:16.1: enabled 0
785 07:49:28.223131 PCI: 00:16.2: enabled 0
786 07:49:28.223220 PCI: 00:16.3: enabled 0
787 07:49:28.226916 PCI: 00:16.4: enabled 0
788 07:49:28.230636 PCI: 00:16.5: enabled 0
789 07:49:28.230748 PCI: 00:17.0: enabled 1
790 07:49:28.234444
791 07:49:28.234603 PCI: 00:19.0: enabled 0
792 07:49:28.237852 PCI: 00:19.1: enabled 1
793 07:49:28.240924 I2C: 00:15: enabled 1
794 07:49:28.244239 PCI: 00:19.2: enabled 0
795 07:49:28.244346 PCI: 00:1d.0: enabled 1
796 07:49:28.247861 GENERIC: 0.0: enabled 1
797 07:49:28.251132 PCI: 00:1e.0: enabled 1
798 07:49:28.254071 PCI: 00:1e.1: enabled 0
799 07:49:28.304089 PCI: 00:1e.2: enabled 1
800 07:49:28.304259 SPI: 00: enabled 1
801 07:49:28.304327 PCI: 00:1e.3: enabled 1
802 07:49:28.304587 SPI: 00: enabled 1
803 07:49:28.304653 PCI: 00:1f.0: enabled 1
804 07:49:28.304750 PNP: 0c09.0: enabled 1
805 07:49:28.305000
806 07:49:28.305087 PCI: 00:1f.1: enabled 0
807 07:49:28.305163 PCI: 00:1f.2: enabled 1
808 07:49:28.305267 GENERIC: 0.0: enabled 1
809 07:49:28.305326 GENERIC: 0.0: enabled 1
810 07:49:28.305573 GENERIC: 1.0: enabled 1
811 07:49:28.305639 PCI: 00:1f.3: enabled 1
812 07:49:28.305730 PCI: 00:1f.4: enabled 0
813 07:49:28.305789 PCI: 00:1f.5: enabled 1
814 07:49:28.305847 PCI: 00:1f.6: enabled 0
815 07:49:28.306098 PCI: 00:1f.7: enabled 0
816 07:49:28.306164 CPU_CLUSTER: 0: enabled 1
817 07:49:28.306420 APIC: 00: enabled 1
818 07:49:28.306499 APIC: 01: enabled 1
819 07:49:28.306589 APIC: 03: enabled 1
820 07:49:28.316822 APIC: 06: enabled 1
821 07:49:28.317019 APIC: 05: enabled 1
822 07:49:28.317119 APIC: 04: enabled 1
823 07:49:28.323140 APIC: 02: enabled 1
824 07:49:28.323308 APIC: 07: enabled 1
825 07:49:28.323423 Root Device scanning...
826 07:49:28.326213
827 07:49:28.326305 scan_static_bus for Root Device
828 07:49:28.326405 DOMAIN: 0000 enabled
829 07:49:28.329812 CPU_CLUSTER: 0 enabled
830 07:49:28.329960 DOMAIN: 0000 scanning...
831 07:49:28.332626 PCI: pci_scan_bus for bus 00
832 07:49:28.336079 PCI: 00:00.0 [8086/0000] ops
833 07:49:28.339371 PCI: 00:00.0 [8086/9a12] enabled
834 07:49:28.342603 PCI: 00:02.0 [8086/0000] bus ops
835 07:49:28.346253 PCI: 00:02.0 [8086/9a40] enabled
836 07:49:28.349227 PCI: 00:04.0 [8086/0000] bus ops
837 07:49:28.352413 PCI: 00:04.0 [8086/9a03] enabled
838 07:49:28.355858 PCI: 00:05.0 [8086/9a19] enabled
839 07:49:28.359371 PCI: 00:07.0 [0000/0000] hidden
840 07:49:28.362600 PCI: 00:08.0 [8086/9a11] enabled
841 07:49:28.365983 PCI: 00:0a.0 [8086/9a0d] disabled
842 07:49:28.369299 PCI: 00:0d.0 [8086/0000] bus ops
843 07:49:28.372569 PCI: 00:0d.0 [8086/9a13] enabled
844 07:49:28.376003 PCI: 00:14.0 [8086/0000] bus ops
845 07:49:28.379555 PCI: 00:14.0 [8086/a0ed] enabled
846 07:49:28.382486 PCI: 00:14.2 [8086/a0ef] enabled
847 07:49:28.386065 PCI: 00:14.3 [8086/0000] bus ops
848 07:49:28.388922 PCI: 00:14.3 [8086/a0f0] enabled
849 07:49:28.392760 PCI: 00:15.0 [8086/0000] bus ops
850 07:49:28.395725 PCI: 00:15.0 [8086/a0e8] enabled
851 07:49:28.399511 PCI: 00:15.1 [8086/0000] bus ops
852 07:49:28.402331 PCI: 00:15.1 [8086/a0e9] enabled
853 07:49:28.405653 PCI: 00:15.2 [8086/0000] bus ops
854 07:49:28.408985 PCI: 00:15.2 [8086/a0ea] enabled
855 07:49:28.412384 PCI: 00:15.3 [8086/0000] bus ops
856 07:49:28.415496 PCI: 00:15.3 [8086/a0eb] enabled
857 07:49:28.418965 PCI: 00:16.0 [8086/0000] ops
858 07:49:28.422485 PCI: 00:16.0 [8086/a0e0] enabled
859 07:49:28.429285 PCI: Static device PCI: 00:17.0 not found, disabling it.
860 07:49:28.432270 PCI: 00:19.0 [8086/0000] bus ops
861 07:49:28.435570 PCI: 00:19.0 [8086/a0c5] disabled
862 07:49:28.438872 PCI: 00:19.1 [8086/0000] bus ops
863 07:49:28.442301 PCI: 00:19.1 [8086/a0c6] enabled
864 07:49:28.445474 PCI: 00:1d.0 [8086/0000] bus ops
865 07:49:28.448975 PCI: 00:1d.0 [8086/a0b0] enabled
866 07:49:28.452148 PCI: 00:1e.0 [8086/0000] ops
867 07:49:28.455308 PCI: 00:1e.0 [8086/a0a8] enabled
868 07:49:28.458629 PCI: 00:1e.2 [8086/0000] bus ops
869 07:49:28.462107 PCI: 00:1e.2 [8086/a0aa] enabled
870 07:49:28.465365 PCI: 00:1e.3 [8086/0000] bus ops
871 07:49:28.468827 PCI: 00:1e.3 [8086/a0ab] enabled
872 07:49:28.471974 PCI: 00:1f.0 [8086/0000] bus ops
873 07:49:28.475564 PCI: 00:1f.0 [8086/a087] enabled
874 07:49:28.475663 RTC Init
875 07:49:28.478593 Set power on after power failure.
876 07:49:28.482021 Disabling Deep S3
877 07:49:28.482127 Disabling Deep S3
878 07:49:28.485412 Disabling Deep S4
879 07:49:28.488742 Disabling Deep S4
880 07:49:28.488826 Disabling Deep S5
881 07:49:28.491804 Disabling Deep S5
882 07:49:28.495238 PCI: 00:1f.2 [0000/0000] hidden
883 07:49:28.498791 PCI: 00:1f.3 [8086/0000] bus ops
884 07:49:28.502355 PCI: 00:1f.3 [8086/a0c8] enabled
885 07:49:28.505447 PCI: 00:1f.5 [8086/0000] bus ops
886 07:49:28.508478 PCI: 00:1f.5 [8086/a0a4] enabled
887 07:49:28.512068 PCI: Leftover static devices:
888 07:49:28.512176 PCI: 00:10.2
889 07:49:28.512244 PCI: 00:10.6
890 07:49:28.515405 PCI: 00:10.7
891 07:49:28.515500 PCI: 00:06.0
892 07:49:28.518720 PCI: 00:07.1
893 07:49:28.518807 PCI: 00:07.2
894 07:49:28.518872 PCI: 00:07.3
895 07:49:28.522005 PCI: 00:09.0
896 07:49:28.522091 PCI: 00:0d.1
897 07:49:28.525184 PCI: 00:0d.2
898 07:49:28.525266 PCI: 00:0d.3
899 07:49:28.528702 PCI: 00:0e.0
900 07:49:28.528778 PCI: 00:12.0
901 07:49:28.528844 PCI: 00:12.6
902 07:49:28.532094 PCI: 00:13.0
903 07:49:28.532187 PCI: 00:14.1
904 07:49:28.535291 PCI: 00:16.1
905 07:49:28.535381 PCI: 00:16.2
906 07:49:28.535449 PCI: 00:16.3
907 07:49:28.538615 PCI: 00:16.4
908 07:49:28.538701 PCI: 00:16.5
909 07:49:28.541864 PCI: 00:17.0
910 07:49:28.541950 PCI: 00:19.2
911 07:49:28.542017 PCI: 00:1e.1
912 07:49:28.545217
913 07:49:28.545304 PCI: 00:1f.1
914 07:49:28.545372 PCI: 00:1f.4
915 07:49:28.548395 PCI: 00:1f.6
916 07:49:28.548481 PCI: 00:1f.7
917 07:49:28.551602 PCI: Check your devicetree.cb.
918 07:49:28.555122 PCI: 00:02.0 scanning...
919 07:49:28.558539 scan_generic_bus for PCI: 00:02.0
920 07:49:28.561858 scan_generic_bus for PCI: 00:02.0 done
921 07:49:28.568227 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
922 07:49:28.568329 PCI: 00:04.0 scanning...
923 07:49:28.571638 scan_generic_bus for PCI: 00:04.0
924 07:49:28.575493 GENERIC: 0.0 enabled
925 07:49:28.581496 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
926 07:49:28.584887 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
927 07:49:28.588354 PCI: 00:0d.0 scanning...
928 07:49:28.591597 scan_static_bus for PCI: 00:0d.0
929 07:49:28.594766 USB0 port 0 enabled
930 07:49:28.598297 USB0 port 0 scanning...
931 07:49:28.601288 scan_static_bus for USB0 port 0
932 07:49:28.601384 USB3 port 0 enabled
933 07:49:28.604746 USB3 port 1 enabled
934 07:49:28.604829 USB3 port 2 disabled
935 07:49:28.608078
936 07:49:28.608168 USB3 port 3 disabled
937 07:49:28.611290 USB3 port 0 scanning...
938 07:49:28.614687 scan_static_bus for USB3 port 0
939 07:49:28.618273 scan_static_bus for USB3 port 0 done
940 07:49:28.621145 scan_bus: bus USB3 port 0 finished in 6 msecs
941 07:49:28.624537 USB3 port 1 scanning...
942 07:49:28.627938 scan_static_bus for USB3 port 1
943 07:49:28.631436 scan_static_bus for USB3 port 1 done
944 07:49:28.637703 scan_bus: bus USB3 port 1 finished in 6 msecs
945 07:49:28.641166 scan_static_bus for USB0 port 0 done
946 07:49:28.644745 scan_bus: bus USB0 port 0 finished in 43 msecs
947 07:49:28.648004 scan_static_bus for PCI: 00:0d.0 done
948 07:49:28.654543 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
949 07:49:28.657484 PCI: 00:14.0 scanning...
950 07:49:28.660790 scan_static_bus for PCI: 00:14.0
951 07:49:28.660877 USB0 port 0 enabled
952 07:49:28.664058 USB0 port 0 scanning...
953 07:49:28.667413 scan_static_bus for USB0 port 0
954 07:49:28.670634 USB2 port 0 disabled
955 07:49:28.670728 USB2 port 1 enabled
956 07:49:28.674072 USB2 port 2 enabled
957 07:49:28.677372 USB2 port 3 disabled
958 07:49:28.677481 USB2 port 4 enabled
959 07:49:28.680711 USB2 port 5 disabled
960 07:49:28.684122 USB2 port 6 disabled
961 07:49:28.684242 USB2 port 7 disabled
962 07:49:28.687842 USB2 port 8 disabled
963 07:49:28.687929 USB2 port 9 disabled
964 07:49:28.690682
965 07:49:28.690801 USB3 port 0 disabled
966 07:49:28.694388 USB3 port 1 enabled
967 07:49:28.694478 USB3 port 2 disabled
968 07:49:28.697663 USB3 port 3 disabled
969 07:49:28.700520 USB2 port 1 scanning...
970 07:49:28.704375 scan_static_bus for USB2 port 1
971 07:49:28.707344 scan_static_bus for USB2 port 1 done
972 07:49:28.710573 scan_bus: bus USB2 port 1 finished in 6 msecs
973 07:49:28.714262 USB2 port 2 scanning...
974 07:49:28.717277 scan_static_bus for USB2 port 2
975 07:49:28.720458 scan_static_bus for USB2 port 2 done
976 07:49:28.727144 scan_bus: bus USB2 port 2 finished in 6 msecs
977 07:49:28.727280 USB2 port 4 scanning...
978 07:49:28.730488 scan_static_bus for USB2 port 4
979 07:49:28.737155 scan_static_bus for USB2 port 4 done
980 07:49:28.740472 scan_bus: bus USB2 port 4 finished in 6 msecs
981 07:49:28.743650 USB3 port 1 scanning...
982 07:49:28.746980 scan_static_bus for USB3 port 1
983 07:49:28.750096 scan_static_bus for USB3 port 1 done
984 07:49:28.753463 scan_bus: bus USB3 port 1 finished in 6 msecs
985 07:49:28.757140 scan_static_bus for USB0 port 0 done
986 07:49:28.763598 scan_bus: bus USB0 port 0 finished in 93 msecs
987 07:49:28.766666 scan_static_bus for PCI: 00:14.0 done
988 07:49:28.770175 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
989 07:49:28.773640 PCI: 00:14.3 scanning...
990 07:49:28.776703 scan_static_bus for PCI: 00:14.3
991 07:49:28.779928 GENERIC: 0.0 enabled
992 07:49:28.783901 scan_static_bus for PCI: 00:14.3 done
993 07:49:28.786911 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
994 07:49:28.789973 PCI: 00:15.0 scanning...
995 07:49:28.793281 scan_static_bus for PCI: 00:15.0
996 07:49:28.796601 I2C: 00:1a enabled
997 07:49:28.796679 I2C: 00:31 enabled
998 07:49:28.799822
999 07:49:28.799898 I2C: 00:32 enabled
1000 07:49:28.803122 scan_static_bus for PCI: 00:15.0 done
1001 07:49:28.810801 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1002 07:49:28.810923 PCI: 00:15.1 scanning...
1003 07:49:28.814155 scan_static_bus for PCI: 00:15.1
1004 07:49:28.817853 I2C: 00:10 enabled
1005 07:49:28.820903 scan_static_bus for PCI: 00:15.1 done
1006 07:49:28.824144 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1007 07:49:28.827473 PCI: 00:15.2 scanning...
1008 07:49:28.830634 scan_static_bus for PCI: 00:15.2
1009 07:49:28.834188 scan_static_bus for PCI: 00:15.2 done
1010 07:49:28.840855 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1011 07:49:28.844214 PCI: 00:15.3 scanning...
1012 07:49:28.847538 scan_static_bus for PCI: 00:15.3
1013 07:49:28.850455 scan_static_bus for PCI: 00:15.3 done
1014 07:49:28.854152 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1015 07:49:28.857288 PCI: 00:19.1 scanning...
1016 07:49:28.860446 scan_static_bus for PCI: 00:19.1
1017 07:49:28.863870 I2C: 00:15 enabled
1018 07:49:28.867213 scan_static_bus for PCI: 00:19.1 done
1019 07:49:28.870778 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1020 07:49:28.873754 PCI: 00:1d.0 scanning...
1021 07:49:28.877259 do_pci_scan_bridge for PCI: 00:1d.0
1022 07:49:28.880647 PCI: pci_scan_bus for bus 01
1023 07:49:28.883621 PCI: 01:00.0 [1c5c/174a] enabled
1024 07:49:28.886877 GENERIC: 0.0 enabled
1025 07:49:28.890033 Enabling Common Clock Configuration
1026 07:49:28.893607 L1 Sub-State supported from root port 29
1027 07:49:28.896710 L1 Sub-State Support = 0xf
1028 07:49:28.900221 CommonModeRestoreTime = 0x28
1029 07:49:28.903744 Power On Value = 0x16, Power On Scale = 0x0
1030 07:49:28.906857 ASPM: Enabled L1
1031 07:49:28.910310 PCIe: Max_Payload_Size adjusted to 128
1032 07:49:28.913693 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1033 07:49:28.916644 PCI: 00:1e.2 scanning...
1034 07:49:28.920327 scan_generic_bus for PCI: 00:1e.2
1035 07:49:28.923221 SPI: 00 enabled
1036 07:49:28.930286 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1037 07:49:28.933189 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1038 07:49:28.936294 PCI: 00:1e.3 scanning...
1039 07:49:28.940125 scan_generic_bus for PCI: 00:1e.3
1040 07:49:28.940225 SPI: 00 enabled
1041 07:49:28.946709 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1042 07:49:28.953096 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1043 07:49:28.953248 PCI: 00:1f.0 scanning...
1044 07:49:28.956712 scan_static_bus for PCI: 00:1f.0
1045 07:49:28.959995 PNP: 0c09.0 enabled
1046 07:49:28.963146 PNP: 0c09.0 scanning...
1047 07:49:28.966566 scan_static_bus for PNP: 0c09.0
1048 07:49:28.969976 scan_static_bus for PNP: 0c09.0 done
1049 07:49:28.972982 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1050 07:49:28.979906 scan_static_bus for PCI: 00:1f.0 done
1051 07:49:28.983448 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1052 07:49:28.986395 PCI: 00:1f.2 scanning...
1053 07:49:28.989880 scan_static_bus for PCI: 00:1f.2
1054 07:49:28.990003 GENERIC: 0.0 enabled
1055 07:49:28.993137 GENERIC: 0.0 scanning...
1056 07:49:28.996994 scan_static_bus for GENERIC: 0.0
1057 07:49:28.999863 GENERIC: 0.0 enabled
1058 07:49:29.003058 GENERIC: 1.0 enabled
1059 07:49:29.006458 scan_static_bus for GENERIC: 0.0 done
1060 07:49:29.009591 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1061 07:49:29.013226 scan_static_bus for PCI: 00:1f.2 done
1062 07:49:29.019922 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1063 07:49:29.023036 PCI: 00:1f.3 scanning...
1064 07:49:29.026273 scan_static_bus for PCI: 00:1f.3
1065 07:49:29.029880 scan_static_bus for PCI: 00:1f.3 done
1066 07:49:29.033130 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1067 07:49:29.036214 PCI: 00:1f.5 scanning...
1068 07:49:29.039418 scan_generic_bus for PCI: 00:1f.5
1069 07:49:29.042937 scan_generic_bus for PCI: 00:1f.5 done
1070 07:49:29.049295 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1071 07:49:29.052522 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1072 07:49:29.056190 scan_static_bus for Root Device done
1073 07:49:29.062694 scan_bus: bus Root Device finished in 736 msecs
1074 07:49:29.062835 done
1075 07:49:29.069295 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1076 07:49:29.072815 Chrome EC: UHEPI supported
1077 07:49:29.079580 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1078 07:49:29.086148 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1079 07:49:29.089390 SPI flash protection: WPSW=0 SRP0=0
1080 07:49:29.092517 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1081 07:49:29.099135 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1082 07:49:29.102611 found VGA at PCI: 00:02.0
1083 07:49:29.105702 Setting up VGA for PCI: 00:02.0
1084 07:49:29.109181 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1085 07:49:29.115605 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1086 07:49:29.119245 Allocating resources...
1087 07:49:29.119346 Reading resources...
1088 07:49:29.125766 Root Device read_resources bus 0 link: 0
1089 07:49:29.129066 DOMAIN: 0000 read_resources bus 0 link: 0
1090 07:49:29.132184 PCI: 00:04.0 read_resources bus 1 link: 0
1091 07:49:29.139246 PCI: 00:04.0 read_resources bus 1 link: 0 done
1092 07:49:29.142472 PCI: 00:0d.0 read_resources bus 0 link: 0
1093 07:49:29.148972 USB0 port 0 read_resources bus 0 link: 0
1094 07:49:29.152321 USB0 port 0 read_resources bus 0 link: 0 done
1095 07:49:29.159027 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1096 07:49:29.162359 PCI: 00:14.0 read_resources bus 0 link: 0
1097 07:49:29.165418 USB0 port 0 read_resources bus 0 link: 0
1098 07:49:29.173250 USB0 port 0 read_resources bus 0 link: 0 done
1099 07:49:29.176664 PCI: 00:14.0 read_resources bus 0 link: 0 done
1100 07:49:29.183442 PCI: 00:14.3 read_resources bus 0 link: 0
1101 07:49:29.186945 PCI: 00:14.3 read_resources bus 0 link: 0 done
1102 07:49:29.193520 PCI: 00:15.0 read_resources bus 0 link: 0
1103 07:49:29.196723 PCI: 00:15.0 read_resources bus 0 link: 0 done
1104 07:49:29.203595 PCI: 00:15.1 read_resources bus 0 link: 0
1105 07:49:29.206804 PCI: 00:15.1 read_resources bus 0 link: 0 done
1106 07:49:29.214144 PCI: 00:19.1 read_resources bus 0 link: 0
1107 07:49:29.217274 PCI: 00:19.1 read_resources bus 0 link: 0 done
1108 07:49:29.223785 PCI: 00:1d.0 read_resources bus 1 link: 0
1109 07:49:29.227125 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1110 07:49:29.234383 PCI: 00:1e.2 read_resources bus 2 link: 0
1111 07:49:29.237228 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1112 07:49:29.243737 PCI: 00:1e.3 read_resources bus 3 link: 0
1113 07:49:29.247417 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1114 07:49:29.253832 PCI: 00:1f.0 read_resources bus 0 link: 0
1115 07:49:29.257105 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1116 07:49:29.260554 PCI: 00:1f.2 read_resources bus 0 link: 0
1117 07:49:29.263643
1118 07:49:29.267109 GENERIC: 0.0 read_resources bus 0 link: 0
1119 07:49:29.270228 GENERIC: 0.0 read_resources bus 0 link: 0 done
1120 07:49:29.277154 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1121 07:49:29.283813 DOMAIN: 0000 read_resources bus 0 link: 0 done
1122 07:49:29.286928 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1123 07:49:29.293721 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1124 07:49:29.296940 Root Device read_resources bus 0 link: 0 done
1125 07:49:29.300085 Done reading resources.
1126 07:49:29.303458 Show resources in subtree (Root Device)...After reading.
1127 07:49:29.310429 Root Device child on link 0 DOMAIN: 0000
1128 07:49:29.313744 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1129 07:49:29.323483 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1130 07:49:29.333627 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1131 07:49:29.333781 PCI: 00:00.0
1132 07:49:29.343137 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1133 07:49:29.353209 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1134 07:49:29.363379 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1135 07:49:29.373062 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1136 07:49:29.383214 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1137 07:49:29.389646 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1138 07:49:29.399482 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1139 07:49:29.410017 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1140 07:49:29.419528 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1141 07:49:29.429825 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1142 07:49:29.439552 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1143 07:49:29.446509 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1144 07:49:29.455944 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1145 07:49:29.466070 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1146 07:49:29.475813 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1147 07:49:29.486056 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1148 07:49:29.495796 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1149 07:49:29.502442 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1150 07:49:29.512406 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1151 07:49:29.522240 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1152 07:49:29.525527 PCI: 00:02.0
1153 07:49:29.535815 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 07:49:29.545381 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1155 07:49:29.552479 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1156 07:49:29.558683 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 07:49:29.568923 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 07:49:29.569089 GENERIC: 0.0
1159 07:49:29.572198 PCI: 00:05.0
1160 07:49:29.582183 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 07:49:29.585868 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 07:49:29.588983 GENERIC: 0.0
1163 07:49:29.589159 PCI: 00:08.0
1164 07:49:29.598924 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 07:49:29.602196 PCI: 00:0a.0
1166 07:49:29.605201 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 07:49:29.615679 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 07:49:29.618754 USB0 port 0 child on link 0 USB3 port 0
1169 07:49:29.621922
1170 07:49:29.622031 USB3 port 0
1171 07:49:29.625733 USB3 port 1
1172 07:49:29.625840 USB3 port 2
1173 07:49:29.628738 USB3 port 3
1174 07:49:29.631838 PCI: 00:14.0 child on link 0 USB0 port 0
1175 07:49:29.641794 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1176 07:49:29.645056 USB0 port 0 child on link 0 USB2 port 0
1177 07:49:29.648236 USB2 port 0
1178 07:49:29.648357 USB2 port 1
1179 07:49:29.651621 USB2 port 2
1180 07:49:29.651741 USB2 port 3
1181 07:49:29.655472 USB2 port 4
1182 07:49:29.655567 USB2 port 5
1183 07:49:29.658514 USB2 port 6
1184 07:49:29.661616 USB2 port 7
1185 07:49:29.661743 USB2 port 8
1186 07:49:29.665049 USB2 port 9
1187 07:49:29.665164 USB3 port 0
1188 07:49:29.668359 USB3 port 1
1189 07:49:29.668497 USB3 port 2
1190 07:49:29.671769 USB3 port 3
1191 07:49:29.671900 PCI: 00:14.2
1192 07:49:29.681393 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1193 07:49:29.691289 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1194 07:49:29.697888 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1195 07:49:29.707802 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1196 07:49:29.707976 GENERIC: 0.0
1197 07:49:29.711094 PCI: 00:15.0 child on link 0 I2C: 00:1a
1198 07:49:29.721170 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1199 07:49:29.724706 I2C: 00:1a
1200 07:49:29.724811 I2C: 00:31
1201 07:49:29.727799 I2C: 00:32
1202 07:49:29.731503 PCI: 00:15.1 child on link 0 I2C: 00:10
1203 07:49:29.741183 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1204 07:49:29.744457 I2C: 00:10
1205 07:49:29.744559 PCI: 00:15.2
1206 07:49:29.754662 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1207 07:49:29.758018 PCI: 00:15.3
1208 07:49:29.767694 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1209 07:49:29.767867 PCI: 00:16.0
1210 07:49:29.777675 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1211 07:49:29.780817 PCI: 00:19.0
1212 07:49:29.783945 PCI: 00:19.1 child on link 0 I2C: 00:15
1213 07:49:29.794110 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1214 07:49:29.794264 I2C: 00:15
1215 07:49:29.800737 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1216 07:49:29.807419 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1217 07:49:29.817308 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1218 07:49:29.827300 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1219 07:49:29.830679 GENERIC: 0.0
1220 07:49:29.830789 PCI: 01:00.0
1221 07:49:29.840509 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1222 07:49:29.850505 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1223 07:49:29.860488 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1224 07:49:29.860621 PCI: 00:1e.0
1225 07:49:29.873437 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1226 07:49:29.876739 PCI: 00:1e.2 child on link 0 SPI: 00
1227 07:49:29.886679 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1228 07:49:29.886820 SPI: 00
1229 07:49:29.893425 PCI: 00:1e.3 child on link 0 SPI: 00
1230 07:49:29.903342 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1231 07:49:29.903509 SPI: 00
1232 07:49:29.906543 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1233 07:49:29.916449 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1234 07:49:29.916614 PNP: 0c09.0
1235 07:49:29.926854 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1236 07:49:29.929771 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1237 07:49:29.939927 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1238 07:49:29.949953 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1239 07:49:29.952962 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1240 07:49:29.956420 GENERIC: 0.0
1241 07:49:29.956624 GENERIC: 1.0
1242 07:49:29.959589
1243 07:49:29.959691 PCI: 00:1f.3
1244 07:49:29.969701 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1245 07:49:29.979336 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1246 07:49:29.982648 PCI: 00:1f.5
1247 07:49:29.989538 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1248 07:49:29.996103 CPU_CLUSTER: 0 child on link 0 APIC: 00
1249 07:49:29.996268 APIC: 00
1250 07:49:29.996338 APIC: 01
1251 07:49:29.999206 APIC: 03
1252 07:49:29.999297 APIC: 06
1253 07:49:30.002642 APIC: 05
1254 07:49:30.002751 APIC: 04
1255 07:49:30.002820 APIC: 02
1256 07:49:30.006079 APIC: 07
1257 07:49:30.012549 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1258 07:49:30.019295 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1259 07:49:30.026017 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1260 07:49:30.029122 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1261 07:49:30.035892 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1262 07:49:30.038853 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1263 07:49:30.042764 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1264 07:49:30.049352 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1265 07:49:30.058955 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1266 07:49:30.065426 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1267 07:49:30.072121 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1268 07:49:30.078768 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1269 07:49:30.085369 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1270 07:49:30.095503 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1271 07:49:30.102033 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1272 07:49:30.105421 DOMAIN: 0000: Resource ranges:
1273 07:49:30.108663 * Base: 1000, Size: 800, Tag: 100
1274 07:49:30.112048 * Base: 1900, Size: e700, Tag: 100
1275 07:49:30.118365 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1276 07:49:30.125328 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1277 07:49:30.131770 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1278 07:49:30.138494 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1279 07:49:30.144824 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1280 07:49:30.155291 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1281 07:49:30.161515 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1282 07:49:30.168074 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1283 07:49:30.178145 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1284 07:49:30.184863 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1285 07:49:30.191712 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1286 07:49:30.201405 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1287 07:49:30.207803 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1288 07:49:30.214641 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1289 07:49:30.224430 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1290 07:49:30.231307 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1291 07:49:30.237418 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1292 07:49:30.247874 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1293 07:49:30.254242 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1294 07:49:30.261032 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1295 07:49:30.270810 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1296 07:49:30.277421 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1297 07:49:30.284183 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1298 07:49:30.294000 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1299 07:49:30.300434 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1300 07:49:30.303653 DOMAIN: 0000: Resource ranges:
1301 07:49:30.307282 * Base: 7fc00000, Size: 40400000, Tag: 200
1302 07:49:30.313940 * Base: d0000000, Size: 28000000, Tag: 200
1303 07:49:30.317071 * Base: fa000000, Size: 1000000, Tag: 200
1304 07:49:30.320308 * Base: fb001000, Size: 2fff000, Tag: 200
1305 07:49:30.323645 * Base: fe010000, Size: 2e000, Tag: 200
1306 07:49:30.330355 * Base: fe03f000, Size: d41000, Tag: 200
1307 07:49:30.333931 * Base: fed88000, Size: 8000, Tag: 200
1308 07:49:30.336782 * Base: fed93000, Size: d000, Tag: 200
1309 07:49:30.340187 * Base: feda2000, Size: 1e000, Tag: 200
1310 07:49:30.347018 * Base: fede0000, Size: 1220000, Tag: 200
1311 07:49:30.350143 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1312 07:49:30.356966 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1313 07:49:30.363571 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1314 07:49:30.370466 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1315 07:49:30.376929 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1316 07:49:30.383221 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1317 07:49:30.389702 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1318 07:49:30.396284 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1319 07:49:30.403448 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1320 07:49:30.410190 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1321 07:49:30.416377 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1322 07:49:30.423225 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1323 07:49:30.429501 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1324 07:49:30.435975 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1325 07:49:30.442858 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1326 07:49:30.449456 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1327 07:49:30.456189 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1328 07:49:30.462783 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1329 07:49:30.469465 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1330 07:49:30.475784 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1331 07:49:30.482571 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1332 07:49:30.489242 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1333 07:49:30.496058 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1334 07:49:30.505519 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1335 07:49:30.512251 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1336 07:49:30.515864 PCI: 00:1d.0: Resource ranges:
1337 07:49:30.518976 * Base: 7fc00000, Size: 100000, Tag: 200
1338 07:49:30.525536 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1339 07:49:30.532929 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1340 07:49:30.538970 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1341 07:49:30.548787 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1342 07:49:30.555195 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1343 07:49:30.558739 Root Device assign_resources, bus 0 link: 0
1344 07:49:30.565318 DOMAIN: 0000 assign_resources, bus 0 link: 0
1345 07:49:30.572029 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1346 07:49:30.582186 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1347 07:49:30.588403 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1348 07:49:30.598452 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1349 07:49:30.601875 PCI: 00:04.0 assign_resources, bus 1 link: 0
1350 07:49:30.604827 PCI: 00:04.0 assign_resources, bus 1 link: 0
1351 07:49:30.615101 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1352 07:49:30.621807 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1353 07:49:30.631581 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1354 07:49:30.634929 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1355 07:49:30.641437 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1356 07:49:30.648320 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1357 07:49:30.654892 PCI: 00:14.0 assign_resources, bus 0 link: 0
1358 07:49:30.657929 PCI: 00:14.0 assign_resources, bus 0 link: 0
1359 07:49:30.664490 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1360 07:49:30.674367 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1361 07:49:30.680913 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1362 07:49:30.687709 PCI: 00:14.3 assign_resources, bus 0 link: 0
1363 07:49:30.691217 PCI: 00:14.3 assign_resources, bus 0 link: 0
1364 07:49:30.701376 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1365 07:49:30.704185 PCI: 00:15.0 assign_resources, bus 0 link: 0
1366 07:49:30.707440 PCI: 00:15.0 assign_resources, bus 0 link: 0
1367 07:49:30.718101 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1368 07:49:30.721172 PCI: 00:15.1 assign_resources, bus 0 link: 0
1369 07:49:30.727234 PCI: 00:15.1 assign_resources, bus 0 link: 0
1370 07:49:30.734288 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1371 07:49:30.743881 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1372 07:49:30.750413 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1373 07:49:30.760594 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1374 07:49:30.763580 PCI: 00:19.1 assign_resources, bus 0 link: 0
1375 07:49:30.766920 PCI: 00:19.1 assign_resources, bus 0 link: 0
1376 07:49:30.777366 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1377 07:49:30.787065 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1378 07:49:30.797156 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1379 07:49:30.800667 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1380 07:49:30.807077 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1381 07:49:30.817152 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1382 07:49:30.823545 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1383 07:49:30.830186 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1384 07:49:30.836491 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1385 07:49:30.843134 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1386 07:49:30.846681 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1387 07:49:30.853000 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1388 07:49:30.856411
1389 07:49:30.859598 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1390 07:49:30.863223 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1391 07:49:30.869404 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1392 07:49:30.873207 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1393 07:49:30.879985 LPC: Trying to open IO window from 800 size 1ff
1394 07:49:30.886080 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1395 07:49:30.896268 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1396 07:49:30.902404 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1397 07:49:30.909219 DOMAIN: 0000 assign_resources, bus 0 link: 0
1398 07:49:30.912417 Root Device assign_resources, bus 0 link: 0
1399 07:49:30.916223 Done setting resources.
1400 07:49:30.922617 Show resources in subtree (Root Device)...After assigning values.
1401 07:49:30.925755 Root Device child on link 0 DOMAIN: 0000
1402 07:49:30.929075 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1403 07:49:30.939065 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1404 07:49:30.948966 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1405 07:49:30.952165 PCI: 00:00.0
1406 07:49:30.962345 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1407 07:49:30.968725 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1408 07:49:30.978536 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1409 07:49:30.988574 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1410 07:49:30.998279 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1411 07:49:31.008125 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1412 07:49:31.018271 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1413 07:49:31.024805 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1414 07:49:31.034673 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1415 07:49:31.044507 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1416 07:49:31.054807 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1417 07:49:31.064459 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1418 07:49:31.074545 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1419 07:49:31.081255 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1420 07:49:31.090888 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1421 07:49:31.100939 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1422 07:49:31.110721 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1423 07:49:31.120410 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1424 07:49:31.130882 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1425 07:49:31.140323 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1426 07:49:31.140435 PCI: 00:02.0
1427 07:49:31.150310 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1428 07:49:31.163853 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1429 07:49:31.170148 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1430 07:49:31.177001 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1431 07:49:31.186765 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1432 07:49:31.186905 GENERIC: 0.0
1433 07:49:31.190157 PCI: 00:05.0
1434 07:49:31.199859 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1435 07:49:31.203461 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1436 07:49:31.206523
1437 07:49:31.206657 GENERIC: 0.0
1438 07:49:31.209720 PCI: 00:08.0
1439 07:49:31.219531 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1440 07:49:31.219679 PCI: 00:0a.0
1441 07:49:31.223038 PCI: 00:0d.0 child on link 0 USB0 port 0
1442 07:49:31.226756
1443 07:49:31.236070 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1444 07:49:31.239355 USB0 port 0 child on link 0 USB3 port 0
1445 07:49:31.242659 USB3 port 0
1446 07:49:31.242774 USB3 port 1
1447 07:49:31.246361 USB3 port 2
1448 07:49:31.246447 USB3 port 3
1449 07:49:31.249541 PCI: 00:14.0 child on link 0 USB0 port 0
1450 07:49:31.252975
1451 07:49:31.262895 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1452 07:49:31.266007 USB0 port 0 child on link 0 USB2 port 0
1453 07:49:31.268884 USB2 port 0
1454 07:49:31.268998 USB2 port 1
1455 07:49:31.272367 USB2 port 2
1456 07:49:31.272482 USB2 port 3
1457 07:49:31.275884 USB2 port 4
1458 07:49:31.275982 USB2 port 5
1459 07:49:31.279258 USB2 port 6
1460 07:49:31.279343 USB2 port 7
1461 07:49:31.282474 USB2 port 8
1462 07:49:31.282566 USB2 port 9
1463 07:49:31.285764 USB3 port 0
1464 07:49:31.285848 USB3 port 1
1465 07:49:31.289284 USB3 port 2
1466 07:49:31.289368 USB3 port 3
1467 07:49:31.292343 PCI: 00:14.2
1468 07:49:31.302214 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1469 07:49:31.311945 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1470 07:49:31.318615 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1471 07:49:31.328393 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1472 07:49:31.328586 GENERIC: 0.0
1473 07:49:31.335415 PCI: 00:15.0 child on link 0 I2C: 00:1a
1474 07:49:31.345116 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1475 07:49:31.345265 I2C: 00:1a
1476 07:49:31.348552 I2C: 00:31
1477 07:49:31.348644 I2C: 00:32
1478 07:49:31.351922 PCI: 00:15.1 child on link 0 I2C: 00:10
1479 07:49:31.364931 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1480 07:49:31.365065 I2C: 00:10
1481 07:49:31.368579 PCI: 00:15.2
1482 07:49:31.378320 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1483 07:49:31.378470 PCI: 00:15.3
1484 07:49:31.388341 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1485 07:49:31.391751 PCI: 00:16.0
1486 07:49:31.401362 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1487 07:49:31.401547 PCI: 00:19.0
1488 07:49:31.408118 PCI: 00:19.1 child on link 0 I2C: 00:15
1489 07:49:31.418317 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1490 07:49:31.418458 I2C: 00:15
1491 07:49:31.424948 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1492 07:49:31.431636 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1493 07:49:31.444802 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1494 07:49:31.455061 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1495 07:49:31.458036 GENERIC: 0.0
1496 07:49:31.458146 PCI: 01:00.0
1497 07:49:31.467881 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1498 07:49:31.477698 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1499 07:49:31.491623 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1500 07:49:31.491775 PCI: 00:1e.0
1501 07:49:31.501384 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1502 07:49:31.507905 PCI: 00:1e.2 child on link 0 SPI: 00
1503 07:49:31.518145 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1504 07:49:31.518292 SPI: 00
1505 07:49:31.521005 PCI: 00:1e.3 child on link 0 SPI: 00
1506 07:49:31.530992 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1507 07:49:31.534626 SPI: 00
1508 07:49:31.537683 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1509 07:49:31.547591 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1510 07:49:31.547733 PNP: 0c09.0
1511 07:49:31.557264 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1512 07:49:31.560959 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1513 07:49:31.570815 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1514 07:49:31.580647 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1515 07:49:31.584375 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1516 07:49:31.588052 GENERIC: 0.0
1517 07:49:31.588202 GENERIC: 1.0
1518 07:49:31.590522 PCI: 00:1f.3
1519 07:49:31.600616 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1520 07:49:31.610504 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1521 07:49:31.613875 PCI: 00:1f.5
1522 07:49:31.623696 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1523 07:49:31.627248 CPU_CLUSTER: 0 child on link 0 APIC: 00
1524 07:49:31.627343 APIC: 00
1525 07:49:31.630639 APIC: 01
1526 07:49:31.630715 APIC: 03
1527 07:49:31.634084 APIC: 06
1528 07:49:31.634182 APIC: 05
1529 07:49:31.634252 APIC: 04
1530 07:49:31.637380 APIC: 02
1531 07:49:31.637537 APIC: 07
1532 07:49:31.640319 Done allocating resources.
1533 07:49:31.647074 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1534 07:49:31.654085 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1535 07:49:31.657073 Configure GPIOs for I2S audio on UP4.
1536 07:49:31.663770 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1537 07:49:31.666863 Enabling resources...
1538 07:49:31.670243 PCI: 00:00.0 subsystem <- 8086/9a12
1539 07:49:31.673799 PCI: 00:00.0 cmd <- 06
1540 07:49:31.676613 PCI: 00:02.0 subsystem <- 8086/9a40
1541 07:49:31.676700 PCI: 00:02.0 cmd <- 03
1542 07:49:31.683463 PCI: 00:04.0 subsystem <- 8086/9a03
1543 07:49:31.683613 PCI: 00:04.0 cmd <- 02
1544 07:49:31.686752 PCI: 00:05.0 subsystem <- 8086/9a19
1545 07:49:31.690164 PCI: 00:05.0 cmd <- 02
1546 07:49:31.693750 PCI: 00:08.0 subsystem <- 8086/9a11
1547 07:49:31.696682 PCI: 00:08.0 cmd <- 06
1548 07:49:31.700214 PCI: 00:0d.0 subsystem <- 8086/9a13
1549 07:49:31.703371 PCI: 00:0d.0 cmd <- 02
1550 07:49:31.706730 PCI: 00:14.0 subsystem <- 8086/a0ed
1551 07:49:31.709954 PCI: 00:14.0 cmd <- 02
1552 07:49:31.713196 PCI: 00:14.2 subsystem <- 8086/a0ef
1553 07:49:31.716764 PCI: 00:14.2 cmd <- 02
1554 07:49:31.719809 PCI: 00:14.3 subsystem <- 8086/a0f0
1555 07:49:31.723195 PCI: 00:14.3 cmd <- 02
1556 07:49:31.726653 PCI: 00:15.0 subsystem <- 8086/a0e8
1557 07:49:31.726840 PCI: 00:15.0 cmd <- 02
1558 07:49:31.733416 PCI: 00:15.1 subsystem <- 8086/a0e9
1559 07:49:31.733584 PCI: 00:15.1 cmd <- 02
1560 07:49:31.736215 PCI: 00:15.2 subsystem <- 8086/a0ea
1561 07:49:31.739570 PCI: 00:15.2 cmd <- 02
1562 07:49:31.742929 PCI: 00:15.3 subsystem <- 8086/a0eb
1563 07:49:31.746738 PCI: 00:15.3 cmd <- 02
1564 07:49:31.749875 PCI: 00:16.0 subsystem <- 8086/a0e0
1565 07:49:31.752956 PCI: 00:16.0 cmd <- 02
1566 07:49:31.756461 PCI: 00:19.1 subsystem <- 8086/a0c6
1567 07:49:31.760049 PCI: 00:19.1 cmd <- 02
1568 07:49:31.762774 PCI: 00:1d.0 bridge ctrl <- 0013
1569 07:49:31.766856 PCI: 00:1d.0 subsystem <- 8086/a0b0
1570 07:49:31.769505 PCI: 00:1d.0 cmd <- 06
1571 07:49:31.772819 PCI: 00:1e.0 subsystem <- 8086/a0a8
1572 07:49:31.775990 PCI: 00:1e.0 cmd <- 06
1573 07:49:31.779572 PCI: 00:1e.2 subsystem <- 8086/a0aa
1574 07:49:31.779662 PCI: 00:1e.2 cmd <- 06
1575 07:49:31.786025 PCI: 00:1e.3 subsystem <- 8086/a0ab
1576 07:49:31.786136 PCI: 00:1e.3 cmd <- 02
1577 07:49:31.789303 PCI: 00:1f.0 subsystem <- 8086/a087
1578 07:49:31.792510 PCI: 00:1f.0 cmd <- 407
1579 07:49:31.795948 PCI: 00:1f.3 subsystem <- 8086/a0c8
1580 07:49:31.799509 PCI: 00:1f.3 cmd <- 02
1581 07:49:31.802647 PCI: 00:1f.5 subsystem <- 8086/a0a4
1582 07:49:31.805732 PCI: 00:1f.5 cmd <- 406
1583 07:49:31.810273 PCI: 01:00.0 cmd <- 02
1584 07:49:31.814662 done.
1585 07:49:31.817974 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1586 07:49:31.821506 Initializing devices...
1587 07:49:31.825139 Root Device init
1588 07:49:31.828049 Chrome EC: Set SMI mask to 0x0000000000000000
1589 07:49:31.834722 Chrome EC: clear events_b mask to 0x0000000000000000
1590 07:49:31.841340 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1591 07:49:31.844766 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1592 07:49:31.851512 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1593 07:49:31.858145 Chrome EC: Set WAKE mask to 0x0000000000000000
1594 07:49:31.861752 fw_config match found: DB_USB=USB3_ACTIVE
1595 07:49:31.867867 Configure Right Type-C port orientation for retimer
1596 07:49:31.871494 Root Device init finished in 42 msecs
1597 07:49:31.874934 PCI: 00:00.0 init
1598 07:49:31.875078 CPU TDP = 9 Watts
1599 07:49:31.878083 CPU PL1 = 9 Watts
1600 07:49:31.881621 CPU PL2 = 40 Watts
1601 07:49:31.881725 CPU PL4 = 83 Watts
1602 07:49:31.884662 PCI: 00:00.0 init finished in 8 msecs
1603 07:49:31.887765 PCI: 00:02.0 init
1604 07:49:31.890998 GMA: Found VBT in CBFS
1605 07:49:31.894267 GMA: Found valid VBT in CBFS
1606 07:49:31.897783 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1607 07:49:31.907501 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1608 07:49:31.911198 PCI: 00:02.0 init finished in 18 msecs
1609 07:49:31.914359 PCI: 00:05.0 init
1610 07:49:31.917699 PCI: 00:05.0 init finished in 0 msecs
1611 07:49:31.917808 PCI: 00:08.0 init
1612 07:49:31.924167 PCI: 00:08.0 init finished in 0 msecs
1613 07:49:31.924332 PCI: 00:14.0 init
1614 07:49:31.931067 PCI: 00:14.0 init finished in 0 msecs
1615 07:49:31.931161 PCI: 00:14.2 init
1616 07:49:31.934163 PCI: 00:14.2 init finished in 0 msecs
1617 07:49:31.937688 PCI: 00:15.0 init
1618 07:49:31.941248 I2C bus 0 version 0x3230302a
1619 07:49:31.944749 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1620 07:49:31.947904 PCI: 00:15.0 init finished in 6 msecs
1621 07:49:31.951249 PCI: 00:15.1 init
1622 07:49:31.954762 I2C bus 1 version 0x3230302a
1623 07:49:31.957623 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1624 07:49:31.961134 PCI: 00:15.1 init finished in 6 msecs
1625 07:49:31.964290 PCI: 00:15.2 init
1626 07:49:31.967742 I2C bus 2 version 0x3230302a
1627 07:49:31.970938 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1628 07:49:31.974445 PCI: 00:15.2 init finished in 6 msecs
1629 07:49:31.974533 PCI: 00:15.3 init
1630 07:49:31.977771 I2C bus 3 version 0x3230302a
1631 07:49:31.981089 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1632 07:49:31.987854 PCI: 00:15.3 init finished in 6 msecs
1633 07:49:31.987974 PCI: 00:16.0 init
1634 07:49:31.990906 PCI: 00:16.0 init finished in 0 msecs
1635 07:49:31.994709 PCI: 00:19.1 init
1636 07:49:31.998059 I2C bus 5 version 0x3230302a
1637 07:49:32.001458 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1638 07:49:32.004838 PCI: 00:19.1 init finished in 6 msecs
1639 07:49:32.008524 PCI: 00:1d.0 init
1640 07:49:32.011453 Initializing PCH PCIe bridge.
1641 07:49:32.014766 PCI: 00:1d.0 init finished in 3 msecs
1642 07:49:32.017896 PCI: 00:1f.0 init
1643 07:49:32.021159 IOAPIC: Initializing IOAPIC at 0xfec00000
1644 07:49:32.024538 IOAPIC: Bootstrap Processor Local APIC = 0x00
1645 07:49:32.027735
1646 07:49:32.027832 IOAPIC: ID = 0x02
1647 07:49:32.031085 IOAPIC: Dumping registers
1648 07:49:32.034643 reg 0x0000: 0x02000000
1649 07:49:32.034735 reg 0x0001: 0x00770020
1650 07:49:32.037696 reg 0x0002: 0x00000000
1651 07:49:32.040956 PCI: 00:1f.0 init finished in 21 msecs
1652 07:49:32.044683 PCI: 00:1f.2 init
1653 07:49:32.048167 Disabling ACPI via APMC.
1654 07:49:32.051475 APMC done.
1655 07:49:32.055224 PCI: 00:1f.2 init finished in 6 msecs
1656 07:49:32.067197 PCI: 01:00.0 init
1657 07:49:32.070461 PCI: 01:00.0 init finished in 0 msecs
1658 07:49:32.073682 PNP: 0c09.0 init
1659 07:49:32.076794 Google Chrome EC uptime: 8.414 seconds
1660 07:49:32.083386 Google Chrome AP resets since EC boot: 0
1661 07:49:32.086848 Google Chrome most recent AP reset causes:
1662 07:49:32.093215 Google Chrome EC reset flags at last EC boot: reset-pin
1663 07:49:32.096452 PNP: 0c09.0 init finished in 18 msecs
1664 07:49:32.101648 Devices initialized
1665 07:49:32.104520 Show all devs... After init.
1666 07:49:32.108051 Root Device: enabled 1
1667 07:49:32.108195 DOMAIN: 0000: enabled 1
1668 07:49:32.111486 CPU_CLUSTER: 0: enabled 1
1669 07:49:32.114753 PCI: 00:00.0: enabled 1
1670 07:49:32.118149 PCI: 00:02.0: enabled 1
1671 07:49:32.118254 PCI: 00:04.0: enabled 1
1672 07:49:32.121445 PCI: 00:05.0: enabled 1
1673 07:49:32.124810 PCI: 00:06.0: enabled 0
1674 07:49:32.127827 PCI: 00:07.0: enabled 0
1675 07:49:32.127952 PCI: 00:07.1: enabled 0
1676 07:49:32.131347 PCI: 00:07.2: enabled 0
1677 07:49:32.134778 PCI: 00:07.3: enabled 0
1678 07:49:32.137948 PCI: 00:08.0: enabled 1
1679 07:49:32.138061 PCI: 00:09.0: enabled 0
1680 07:49:32.141284 PCI: 00:0a.0: enabled 0
1681 07:49:32.144624 PCI: 00:0d.0: enabled 1
1682 07:49:32.144710 PCI: 00:0d.1: enabled 0
1683 07:49:32.147991
1684 07:49:32.148082 PCI: 00:0d.2: enabled 0
1685 07:49:32.151029 PCI: 00:0d.3: enabled 0
1686 07:49:32.154322 PCI: 00:0e.0: enabled 0
1687 07:49:32.154421 PCI: 00:10.2: enabled 1
1688 07:49:32.157779 PCI: 00:10.6: enabled 0
1689 07:49:32.161082 PCI: 00:10.7: enabled 0
1690 07:49:32.165012 PCI: 00:12.0: enabled 0
1691 07:49:32.165152 PCI: 00:12.6: enabled 0
1692 07:49:32.167901 PCI: 00:13.0: enabled 0
1693 07:49:32.171079 PCI: 00:14.0: enabled 1
1694 07:49:32.174512 PCI: 00:14.1: enabled 0
1695 07:49:32.174684 PCI: 00:14.2: enabled 1
1696 07:49:32.177693 PCI: 00:14.3: enabled 1
1697 07:49:32.181241 PCI: 00:15.0: enabled 1
1698 07:49:32.184526 PCI: 00:15.1: enabled 1
1699 07:49:32.184631 PCI: 00:15.2: enabled 1
1700 07:49:32.187676 PCI: 00:15.3: enabled 1
1701 07:49:32.190906 PCI: 00:16.0: enabled 1
1702 07:49:32.191006 PCI: 00:16.1: enabled 0
1703 07:49:32.194429 PCI: 00:16.2: enabled 0
1704 07:49:32.197677 PCI: 00:16.3: enabled 0
1705 07:49:32.201243 PCI: 00:16.4: enabled 0
1706 07:49:32.201376 PCI: 00:16.5: enabled 0
1707 07:49:32.204333 PCI: 00:17.0: enabled 0
1708 07:49:32.207899 PCI: 00:19.0: enabled 0
1709 07:49:32.211011 PCI: 00:19.1: enabled 1
1710 07:49:32.211125 PCI: 00:19.2: enabled 0
1711 07:49:32.214307 PCI: 00:1c.0: enabled 1
1712 07:49:32.217833 PCI: 00:1c.1: enabled 0
1713 07:49:32.220894 PCI: 00:1c.2: enabled 0
1714 07:49:32.220989 PCI: 00:1c.3: enabled 0
1715 07:49:32.224252 PCI: 00:1c.4: enabled 0
1716 07:49:32.227549 PCI: 00:1c.5: enabled 0
1717 07:49:32.227671 PCI: 00:1c.6: enabled 1
1718 07:49:32.230953
1719 07:49:32.231065 PCI: 00:1c.7: enabled 0
1720 07:49:32.234332 PCI: 00:1d.0: enabled 1
1721 07:49:32.237590 PCI: 00:1d.1: enabled 0
1722 07:49:32.237737 PCI: 00:1d.2: enabled 1
1723 07:49:32.240877 PCI: 00:1d.3: enabled 0
1724 07:49:32.244289 PCI: 00:1e.0: enabled 1
1725 07:49:32.247744 PCI: 00:1e.1: enabled 0
1726 07:49:32.247842 PCI: 00:1e.2: enabled 1
1727 07:49:32.250921 PCI: 00:1e.3: enabled 1
1728 07:49:32.254136 PCI: 00:1f.0: enabled 1
1729 07:49:32.257660 PCI: 00:1f.1: enabled 0
1730 07:49:32.257748 PCI: 00:1f.2: enabled 1
1731 07:49:32.261060 PCI: 00:1f.3: enabled 1
1732 07:49:32.264366 PCI: 00:1f.4: enabled 0
1733 07:49:32.267813 PCI: 00:1f.5: enabled 1
1734 07:49:32.267943 PCI: 00:1f.6: enabled 0
1735 07:49:32.270901 PCI: 00:1f.7: enabled 0
1736 07:49:32.274233 APIC: 00: enabled 1
1737 07:49:32.274311 GENERIC: 0.0: enabled 1
1738 07:49:32.277342 GENERIC: 0.0: enabled 1
1739 07:49:32.280992 GENERIC: 1.0: enabled 1
1740 07:49:32.284404 GENERIC: 0.0: enabled 1
1741 07:49:32.284529 GENERIC: 1.0: enabled 1
1742 07:49:32.287433 USB0 port 0: enabled 1
1743 07:49:32.290393 GENERIC: 0.0: enabled 1
1744 07:49:32.290490 USB0 port 0: enabled 1
1745 07:49:32.294024 GENERIC: 0.0: enabled 1
1746 07:49:32.297416 I2C: 00:1a: enabled 1
1747 07:49:32.300320 I2C: 00:31: enabled 1
1748 07:49:32.300406 I2C: 00:32: enabled 1
1749 07:49:32.304261 I2C: 00:10: enabled 1
1750 07:49:32.307384 I2C: 00:15: enabled 1
1751 07:49:32.307502 GENERIC: 0.0: enabled 0
1752 07:49:32.310633 GENERIC: 1.0: enabled 0
1753 07:49:32.313905 GENERIC: 0.0: enabled 1
1754 07:49:32.314028 SPI: 00: enabled 1
1755 07:49:32.317047 SPI: 00: enabled 1
1756 07:49:32.320791 PNP: 0c09.0: enabled 1
1757 07:49:32.320876 GENERIC: 0.0: enabled 1
1758 07:49:32.323839 USB3 port 0: enabled 1
1759 07:49:32.327537 USB3 port 1: enabled 1
1760 07:49:32.327669 USB3 port 2: enabled 0
1761 07:49:32.330596
1762 07:49:32.330690 USB3 port 3: enabled 0
1763 07:49:32.333805 USB2 port 0: enabled 0
1764 07:49:32.337290 USB2 port 1: enabled 1
1765 07:49:32.337403 USB2 port 2: enabled 1
1766 07:49:32.340492 USB2 port 3: enabled 0
1767 07:49:32.343784 USB2 port 4: enabled 1
1768 07:49:32.343883 USB2 port 5: enabled 0
1769 07:49:32.347094 USB2 port 6: enabled 0
1770 07:49:32.350490 USB2 port 7: enabled 0
1771 07:49:32.353836 USB2 port 8: enabled 0
1772 07:49:32.353945 USB2 port 9: enabled 0
1773 07:49:32.357022 USB3 port 0: enabled 0
1774 07:49:32.360263 USB3 port 1: enabled 1
1775 07:49:32.360374 USB3 port 2: enabled 0
1776 07:49:32.363918 USB3 port 3: enabled 0
1777 07:49:32.367009 GENERIC: 0.0: enabled 1
1778 07:49:32.370581 GENERIC: 1.0: enabled 1
1779 07:49:32.370724 APIC: 01: enabled 1
1780 07:49:32.373743 APIC: 03: enabled 1
1781 07:49:32.373881 APIC: 06: enabled 1
1782 07:49:32.376910 APIC: 05: enabled 1
1783 07:49:32.380238 APIC: 04: enabled 1
1784 07:49:32.380326 APIC: 02: enabled 1
1785 07:49:32.383889 APIC: 07: enabled 1
1786 07:49:32.386764 PCI: 01:00.0: enabled 1
1787 07:49:32.390530 BS: BS_DEV_INIT run times (exec / console): 30 / 536 ms
1788 07:49:32.396932 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1789 07:49:32.400648 ELOG: NV offset 0xf30000 size 0x1000
1790 07:49:32.406879 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1791 07:49:32.413400 ELOG: Event(17) added with size 13 at 2022-11-25 07:49:31 UTC
1792 07:49:32.420129 ELOG: Event(92) added with size 9 at 2022-11-25 07:49:31 UTC
1793 07:49:32.427462 ELOG: Event(93) added with size 9 at 2022-11-25 07:49:31 UTC
1794 07:49:32.433363 ELOG: Event(9E) added with size 10 at 2022-11-25 07:49:31 UTC
1795 07:49:32.439991 ELOG: Event(9F) added with size 14 at 2022-11-25 07:49:31 UTC
1796 07:49:32.443293 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1797 07:49:32.447016
1798 07:49:32.450020 ELOG: Event(A1) added with size 10 at 2022-11-25 07:49:31 UTC
1799 07:49:32.456390 ELOG: Event(16) added with size 11 at 2022-11-25 07:49:31 UTC
1800 07:49:32.460036 Erasing flash addr f30000 + 4 KiB
1801 07:49:32.520755 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1802 07:49:32.527334 ELOG: Event(A0) added with size 9 at 2022-11-25 07:49:31 UTC
1803 07:49:32.530565 elog_add_boot_reason: Logged dev mode boot
1804 07:49:32.537474 BS: BS_POST_DEVICE entry times (exec / console): 28 / 34 ms
1805 07:49:32.537702 Finalize devices...
1806 07:49:32.540383 Devices finalized
1807 07:49:32.547111 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1808 07:49:32.550449 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1809 07:49:32.557237 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1810 07:49:32.560332 ME: HFSTS1 : 0x80030055
1811 07:49:32.567193 ME: HFSTS2 : 0x30280116
1812 07:49:32.570365 ME: HFSTS3 : 0x00000050
1813 07:49:32.573590 ME: HFSTS4 : 0x00004000
1814 07:49:32.580278 ME: HFSTS5 : 0x00000000
1815 07:49:32.583605 ME: HFSTS6 : 0x00400006
1816 07:49:32.587094 ME: Manufacturing Mode : YES
1817 07:49:32.590124 ME: SPI Protection Mode Enabled : NO
1818 07:49:32.593355 ME: FW Partition Table : OK
1819 07:49:32.596855
1820 07:49:32.600012 ME: Bringup Loader Failure : NO
1821 07:49:32.603665 ME: Firmware Init Complete : NO
1822 07:49:32.606900 ME: Boot Options Present : NO
1823 07:49:32.610203 ME: Update In Progress : NO
1824 07:49:32.613185 ME: D0i3 Support : YES
1825 07:49:32.616582 ME: Low Power State Enabled : NO
1826 07:49:32.620323 ME: CPU Replaced : YES
1827 07:49:32.626438 ME: CPU Replacement Valid : YES
1828 07:49:32.630572 ME: Current Working State : 5
1829 07:49:32.633231 ME: Current Operation State : 1
1830 07:49:32.637243 ME: Current Operation Mode : 3
1831 07:49:32.639758 ME: Error Code : 0
1832 07:49:32.643558 ME: Enhanced Debug Mode : NO
1833 07:49:32.646397 ME: CPU Debug Disabled : YES
1834 07:49:32.649707 ME: TXT Support : NO
1835 07:49:32.656267 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1836 07:49:32.663236 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1837 07:49:32.666417 CBFS: 'fallback/slic' not found.
1838 07:49:32.672930 ACPI: Writing ACPI tables at 76b01000.
1839 07:49:32.673041 ACPI: * FACS
1840 07:49:32.676528 ACPI: * DSDT
1841 07:49:32.679827 Ramoops buffer: 0x100000@0x76a00000.
1842 07:49:32.683090 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1843 07:49:32.689917 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1844 07:49:32.693270 Google Chrome EC: version:
1845 07:49:32.696119 ro: voema_v2.0.10114-a447f03e46
1846 07:49:32.699732 rw: voema_v2.0.10114-a447f03e46
1847 07:49:32.699828 running image: 1
1848 07:49:32.706177 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1849 07:49:32.710715 ACPI: * FADT
1850 07:49:32.710849 SCI is IRQ9
1851 07:49:32.713897 ACPI: added table 1/32, length now 40
1852 07:49:32.717355
1853 07:49:32.717446 ACPI: * SSDT
1854 07:49:32.720735 Found 1 CPU(s) with 8 core(s) each.
1855 07:49:32.727402 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1856 07:49:32.730657 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1857 07:49:32.733942 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1858 07:49:32.737406 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1859 07:49:32.743990 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1860 07:49:32.750237 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1861 07:49:32.753979 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1862 07:49:32.760413 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1863 07:49:32.766908 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1864 07:49:32.770356 \_SB.PCI0.RP09: Added StorageD3Enable property
1865 07:49:32.773727 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1866 07:49:32.776888
1867 07:49:32.780165 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1868 07:49:32.786763 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1869 07:49:32.790416 PS2K: Passing 80 keymaps to kernel
1870 07:49:32.796761 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1871 07:49:32.803819 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1872 07:49:32.810084 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1873 07:49:32.816802 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1874 07:49:32.823034 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1875 07:49:32.829763 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1876 07:49:32.836381 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1877 07:49:32.843001 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1878 07:49:32.846364 ACPI: added table 2/32, length now 44
1879 07:49:32.846482 ACPI: * MCFG
1880 07:49:32.853123 ACPI: added table 3/32, length now 48
1881 07:49:32.853238 ACPI: * TPM2
1882 07:49:32.856138 TPM2 log created at 0x769f0000
1883 07:49:32.859818 ACPI: added table 4/32, length now 52
1884 07:49:32.863238 ACPI: * MADT
1885 07:49:32.863352 SCI is IRQ9
1886 07:49:32.866197 ACPI: added table 5/32, length now 56
1887 07:49:32.869793 current = 76b09850
1888 07:49:32.869907 ACPI: * DMAR
1889 07:49:32.873059 ACPI: added table 6/32, length now 60
1890 07:49:32.879368 ACPI: added table 7/32, length now 64
1891 07:49:32.879496 ACPI: * HPET
1892 07:49:32.882651 ACPI: added table 8/32, length now 68
1893 07:49:32.886044 ACPI: done.
1894 07:49:32.886151 ACPI tables: 35216 bytes.
1895 07:49:32.889643
1896 07:49:32.889764 smbios_write_tables: 769ef000
1897 07:49:32.892987 EC returned error result code 3
1898 07:49:32.895848 Couldn't obtain OEM name from CBI
1899 07:49:32.900621 Create SMBIOS type 16
1900 07:49:32.904119 Create SMBIOS type 17
1901 07:49:32.907290 GENERIC: 0.0 (WIFI Device)
1902 07:49:32.907399 SMBIOS tables: 1750 bytes.
1903 07:49:32.913905 Writing table forward entry at 0x00000500
1904 07:49:32.920840 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1905 07:49:32.924224 Writing coreboot table at 0x76b25000
1906 07:49:32.930796 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1907 07:49:32.933878 1. 0000000000001000-000000000009ffff: RAM
1908 07:49:32.937461 2. 00000000000a0000-00000000000fffff: RESERVED
1909 07:49:32.944357 3. 0000000000100000-00000000769eefff: RAM
1910 07:49:32.947248 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1911 07:49:32.954205 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1912 07:49:32.960672 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1913 07:49:32.963742 7. 0000000077000000-000000007fbfffff: RESERVED
1914 07:49:32.967142 8. 00000000c0000000-00000000cfffffff: RESERVED
1915 07:49:32.970418
1916 07:49:32.973611 9. 00000000f8000000-00000000f9ffffff: RESERVED
1917 07:49:32.977127 10. 00000000fb000000-00000000fb000fff: RESERVED
1918 07:49:32.983799 11. 00000000fe000000-00000000fe00ffff: RESERVED
1919 07:49:32.987195 12. 00000000fed80000-00000000fed87fff: RESERVED
1920 07:49:32.993386 13. 00000000fed90000-00000000fed92fff: RESERVED
1921 07:49:32.997296 14. 00000000feda0000-00000000feda1fff: RESERVED
1922 07:49:33.003751 15. 00000000fedc0000-00000000feddffff: RESERVED
1923 07:49:33.007203 16. 0000000100000000-00000002803fffff: RAM
1924 07:49:33.010459 Passing 4 GPIOs to payload:
1925 07:49:33.013384 NAME | PORT | POLARITY | VALUE
1926 07:49:33.020027 lid | undefined | high | high
1927 07:49:33.023471 power | undefined | high | low
1928 07:49:33.027066
1929 07:49:33.030060 oprom | undefined | high | low
1930 07:49:33.036684 EC in RW | 0x000000e5 | high | low
1931 07:49:33.043252 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum d5a9
1932 07:49:33.043341 coreboot table: 1576 bytes.
1933 07:49:33.050076 IMD ROOT 0. 0x76fff000 0x00001000
1934 07:49:33.053257 IMD SMALL 1. 0x76ffe000 0x00001000
1935 07:49:33.056748 FSP MEMORY 2. 0x76c4e000 0x003b0000
1936 07:49:33.059803 VPD 3. 0x76c4d000 0x00000367
1937 07:49:33.063225 RO MCACHE 4. 0x76c4c000 0x00000fdc
1938 07:49:33.066888 CONSOLE 5. 0x76c2c000 0x00020000
1939 07:49:33.070015 FMAP 6. 0x76c2b000 0x00000578
1940 07:49:33.073031 TIME STAMP 7. 0x76c2a000 0x00000910
1941 07:49:33.079701 VBOOT WORK 8. 0x76c16000 0x00014000
1942 07:49:33.083260 ROMSTG STCK 9. 0x76c15000 0x00001000
1943 07:49:33.086306 AFTER CAR 10. 0x76c0a000 0x0000b000
1944 07:49:33.089938 RAMSTAGE 11. 0x76b97000 0x00073000
1945 07:49:33.093135 REFCODE 12. 0x76b42000 0x00055000
1946 07:49:33.096549 SMM BACKUP 13. 0x76b32000 0x00010000
1947 07:49:33.099580 4f444749 14. 0x76b30000 0x00002000
1948 07:49:33.102940 EXT VBT15. 0x76b2d000 0x0000219f
1949 07:49:33.106427 COREBOOT 16. 0x76b25000 0x00008000
1950 07:49:33.113330 ACPI 17. 0x76b01000 0x00024000
1951 07:49:33.116953 ACPI GNVS 18. 0x76b00000 0x00001000
1952 07:49:33.119897 RAMOOPS 19. 0x76a00000 0x00100000
1953 07:49:33.122689 TPM2 TCGLOG20. 0x769f0000 0x00010000
1954 07:49:33.126433 SMBIOS 21. 0x769ef000 0x00000800
1955 07:49:33.129606 IMD small region:
1956 07:49:33.132776 IMD ROOT 0. 0x76ffec00 0x00000400
1957 07:49:33.136069 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1958 07:49:33.139425 POWER STATE 2. 0x76ffeb80 0x00000044
1959 07:49:33.143155 ROMSTAGE 3. 0x76ffeb60 0x00000004
1960 07:49:33.149641 MEM INFO 4. 0x76ffe980 0x000001e0
1961 07:49:33.152879 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1962 07:49:33.156138 MTRR: Physical address space:
1963 07:49:33.162993 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1964 07:49:33.169237 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1965 07:49:33.175841 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1966 07:49:33.182467 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1967 07:49:33.189495 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1968 07:49:33.192413 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1969 07:49:33.195752
1970 07:49:33.199388 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1971 07:49:33.205842 MTRR: Fixed MSR 0x250 0x0606060606060606
1972 07:49:33.209117 MTRR: Fixed MSR 0x258 0x0606060606060606
1973 07:49:33.212628 MTRR: Fixed MSR 0x259 0x0000000000000000
1974 07:49:33.216081 MTRR: Fixed MSR 0x268 0x0606060606060606
1975 07:49:33.222594 MTRR: Fixed MSR 0x269 0x0606060606060606
1976 07:49:33.225820 MTRR: Fixed MSR 0x26a 0x0606060606060606
1977 07:49:33.228993 MTRR: Fixed MSR 0x26b 0x0606060606060606
1978 07:49:33.232652 MTRR: Fixed MSR 0x26c 0x0606060606060606
1979 07:49:33.239297 MTRR: Fixed MSR 0x26d 0x0606060606060606
1980 07:49:33.242304 MTRR: Fixed MSR 0x26e 0x0606060606060606
1981 07:49:33.245691 MTRR: Fixed MSR 0x26f 0x0606060606060606
1982 07:49:33.248901 call enable_fixed_mtrr()
1983 07:49:33.252068 CPU physical address size: 39 bits
1984 07:49:33.258670 MTRR: default type WB/UC MTRR counts: 6/6.
1985 07:49:33.262045 MTRR: UC selected as default type.
1986 07:49:33.265737 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1987 07:49:33.272195 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1988 07:49:33.278684 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1989 07:49:33.285293 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1990 07:49:33.291974 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1991 07:49:33.298767 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1992 07:49:33.298853
1993 07:49:33.302034 MTRR check
1994 07:49:33.302112 Fixed MTRRs : Enabled
1995 07:49:33.305439 Variable MTRRs: Enabled
1996 07:49:33.305555
1997 07:49:33.308382 MTRR: Fixed MSR 0x250 0x0606060606060606
1998 07:49:33.311959
1999 07:49:33.315282 MTRR: Fixed MSR 0x258 0x0606060606060606
2000 07:49:33.318378 MTRR: Fixed MSR 0x259 0x0000000000000000
2001 07:49:33.321885 MTRR: Fixed MSR 0x268 0x0606060606060606
2002 07:49:33.325060 MTRR: Fixed MSR 0x269 0x0606060606060606
2003 07:49:33.332078 MTRR: Fixed MSR 0x26a 0x0606060606060606
2004 07:49:33.335072 MTRR: Fixed MSR 0x26b 0x0606060606060606
2005 07:49:33.338216 MTRR: Fixed MSR 0x26c 0x0606060606060606
2006 07:49:33.341641 MTRR: Fixed MSR 0x26d 0x0606060606060606
2007 07:49:33.348353 MTRR: Fixed MSR 0x26e 0x0606060606060606
2008 07:49:33.351657 MTRR: Fixed MSR 0x26f 0x0606060606060606
2009 07:49:33.358574 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
2010 07:49:33.361664 call enable_fixed_mtrr()
2011 07:49:33.364943 Checking cr50 for pending updates
2012 07:49:33.368753 CPU physical address size: 39 bits
2013 07:49:33.372085 MTRR: Fixed MSR 0x250 0x0606060606060606
2014 07:49:33.375273 MTRR: Fixed MSR 0x250 0x0606060606060606
2015 07:49:33.378532 MTRR: Fixed MSR 0x258 0x0606060606060606
2016 07:49:33.385191 MTRR: Fixed MSR 0x259 0x0000000000000000
2017 07:49:33.388351 MTRR: Fixed MSR 0x268 0x0606060606060606
2018 07:49:33.391965 MTRR: Fixed MSR 0x269 0x0606060606060606
2019 07:49:33.395196 MTRR: Fixed MSR 0x26a 0x0606060606060606
2020 07:49:33.401916 MTRR: Fixed MSR 0x26b 0x0606060606060606
2021 07:49:33.405061 MTRR: Fixed MSR 0x26c 0x0606060606060606
2022 07:49:33.408405 MTRR: Fixed MSR 0x26d 0x0606060606060606
2023 07:49:33.412010 MTRR: Fixed MSR 0x26e 0x0606060606060606
2024 07:49:33.418633 MTRR: Fixed MSR 0x26f 0x0606060606060606
2025 07:49:33.421711 MTRR: Fixed MSR 0x258 0x0606060606060606
2026 07:49:33.424921 call enable_fixed_mtrr()
2027 07:49:33.428174 MTRR: Fixed MSR 0x259 0x0000000000000000
2028 07:49:33.431547 MTRR: Fixed MSR 0x268 0x0606060606060606
2029 07:49:33.438308 MTRR: Fixed MSR 0x269 0x0606060606060606
2030 07:49:33.441695 MTRR: Fixed MSR 0x26a 0x0606060606060606
2031 07:49:33.444746 MTRR: Fixed MSR 0x26b 0x0606060606060606
2032 07:49:33.448242 MTRR: Fixed MSR 0x26c 0x0606060606060606
2033 07:49:33.454641 MTRR: Fixed MSR 0x26d 0x0606060606060606
2034 07:49:33.458133 MTRR: Fixed MSR 0x26e 0x0606060606060606
2035 07:49:33.461468 MTRR: Fixed MSR 0x26f 0x0606060606060606
2036 07:49:33.464604 CPU physical address size: 39 bits
2037 07:49:33.468954 call enable_fixed_mtrr()
2038 07:49:33.472285 MTRR: Fixed MSR 0x250 0x0606060606060606
2039 07:49:33.478661 MTRR: Fixed MSR 0x250 0x0606060606060606
2040 07:49:33.482501 MTRR: Fixed MSR 0x258 0x0606060606060606
2041 07:49:33.485397 MTRR: Fixed MSR 0x259 0x0000000000000000
2042 07:49:33.489042 MTRR: Fixed MSR 0x268 0x0606060606060606
2043 07:49:33.495764 MTRR: Fixed MSR 0x269 0x0606060606060606
2044 07:49:33.498929 MTRR: Fixed MSR 0x26a 0x0606060606060606
2045 07:49:33.501975 MTRR: Fixed MSR 0x26b 0x0606060606060606
2046 07:49:33.505388 MTRR: Fixed MSR 0x26c 0x0606060606060606
2047 07:49:33.511996 MTRR: Fixed MSR 0x26d 0x0606060606060606
2048 07:49:33.515267 MTRR: Fixed MSR 0x26e 0x0606060606060606
2049 07:49:33.518991 MTRR: Fixed MSR 0x26f 0x0606060606060606
2050 07:49:33.525240 MTRR: Fixed MSR 0x258 0x0606060606060606
2051 07:49:33.529378 MTRR: Fixed MSR 0x259 0x0000000000000000
2052 07:49:33.532070 MTRR: Fixed MSR 0x268 0x0606060606060606
2053 07:49:33.535553 MTRR: Fixed MSR 0x269 0x0606060606060606
2054 07:49:33.538639 MTRR: Fixed MSR 0x26a 0x0606060606060606
2055 07:49:33.545150 MTRR: Fixed MSR 0x26b 0x0606060606060606
2056 07:49:33.548454 MTRR: Fixed MSR 0x26c 0x0606060606060606
2057 07:49:33.551885 MTRR: Fixed MSR 0x26d 0x0606060606060606
2058 07:49:33.555020 MTRR: Fixed MSR 0x26e 0x0606060606060606
2059 07:49:33.561681 MTRR: Fixed MSR 0x26f 0x0606060606060606
2060 07:49:33.564929 call enable_fixed_mtrr()
2061 07:49:33.565022 call enable_fixed_mtrr()
2062 07:49:33.568659
2063 07:49:33.571546 CPU physical address size: 39 bits
2064 07:49:33.574874 MTRR: Fixed MSR 0x250 0x0606060606060606
2065 07:49:33.578236 MTRR: Fixed MSR 0x250 0x0606060606060606
2066 07:49:33.581723 MTRR: Fixed MSR 0x258 0x0606060606060606
2067 07:49:33.585064 MTRR: Fixed MSR 0x259 0x0000000000000000
2068 07:49:33.588534
2069 07:49:33.591808 MTRR: Fixed MSR 0x268 0x0606060606060606
2070 07:49:33.594773 MTRR: Fixed MSR 0x269 0x0606060606060606
2071 07:49:33.598235 MTRR: Fixed MSR 0x26a 0x0606060606060606
2072 07:49:33.602031 MTRR: Fixed MSR 0x26b 0x0606060606060606
2073 07:49:33.608321 MTRR: Fixed MSR 0x26c 0x0606060606060606
2074 07:49:33.611651 MTRR: Fixed MSR 0x26d 0x0606060606060606
2075 07:49:33.615092 MTRR: Fixed MSR 0x26e 0x0606060606060606
2076 07:49:33.618361 MTRR: Fixed MSR 0x26f 0x0606060606060606
2077 07:49:33.626078 MTRR: Fixed MSR 0x258 0x0606060606060606
2078 07:49:33.626208 call enable_fixed_mtrr()
2079 07:49:33.632704 MTRR: Fixed MSR 0x259 0x0000000000000000
2080 07:49:33.635808 MTRR: Fixed MSR 0x268 0x0606060606060606
2081 07:49:33.638893 MTRR: Fixed MSR 0x269 0x0606060606060606
2082 07:49:33.642113 MTRR: Fixed MSR 0x26a 0x0606060606060606
2083 07:49:33.649039 MTRR: Fixed MSR 0x26b 0x0606060606060606
2084 07:49:33.652286 MTRR: Fixed MSR 0x26c 0x0606060606060606
2085 07:49:33.655683 MTRR: Fixed MSR 0x26d 0x0606060606060606
2086 07:49:33.658619 MTRR: Fixed MSR 0x26e 0x0606060606060606
2087 07:49:33.665333 MTRR: Fixed MSR 0x26f 0x0606060606060606
2088 07:49:33.668620 CPU physical address size: 39 bits
2089 07:49:33.671900 call enable_fixed_mtrr()
2090 07:49:33.675786 CPU physical address size: 39 bits
2091 07:49:33.678820 CPU physical address size: 39 bits
2092 07:49:33.685412 CPU physical address size: 39 bits
2093 07:49:33.685526 Reading cr50 TPM mode
2094 07:49:33.695990 BS: BS_PAYLOAD_LOAD entry times (exec / console): 326 / 6 ms
2095 07:49:33.706348 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2096 07:49:33.709550 Checking segment from ROM address 0xffc02b38
2097 07:49:33.712713 Checking segment from ROM address 0xffc02b54
2098 07:49:33.719580 Loading segment from ROM address 0xffc02b38
2099 07:49:33.719707 code (compression=0)
2100 07:49:33.729447 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2101 07:49:33.735966 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2102 07:49:33.739032
2103 07:49:33.739129 it's not compressed!
2104 07:49:33.878824 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2105 07:49:33.885448 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2106 07:49:33.892009 Loading segment from ROM address 0xffc02b54
2107 07:49:33.892151 Entry Point 0x30000000
2108 07:49:33.895167 Loaded segments
2109 07:49:33.901897 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2110 07:49:33.945096 Finalizing chipset.
2111 07:49:33.948257 Finalizing SMM.
2112 07:49:33.948367 APMC done.
2113 07:49:33.954956 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2114 07:49:33.958138 mp_park_aps done after 0 msecs.
2115 07:49:33.961347 Jumping to boot code at 0x30000000(0x76b25000)
2116 07:49:33.971207 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2117 07:49:33.971319
2118 07:49:33.971397
2119 07:49:33.971462
2120 07:49:33.974561 Starting depthcharge on Voema...
2121 07:49:33.974674
2122 07:49:33.975091 end: 2.2.3 depthcharge-start (duration 00:00:16) [common]
2123 07:49:33.975232 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2124 07:49:33.975327 Setting prompt string to ['volteer:']
2125 07:49:33.975425 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2126 07:49:33.984620 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2127 07:49:33.984769
2128 07:49:33.991150 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2129 07:49:33.991238
2130 07:49:33.997797 Looking for NVMe Controller 0x3005f238 @ 00:1d:00
2131 07:49:33.997925
2132 07:49:34.001115 Failed to find eMMC card reader
2133 07:49:34.001209
2134 07:49:34.001286 Wipe memory regions:
2135 07:49:34.001352
2136 07:49:34.007864 [0x00000000001000, 0x000000000a0000)
2137 07:49:34.007970
2138 07:49:34.011103 [0x00000000100000, 0x00000030000000)
2139 07:49:34.011199
2140 07:49:34.039647 [0x00000032662db0, 0x000000769ef000)
2141 07:49:34.039799
2142 07:49:34.078807 [0x00000100000000, 0x00000280400000)
2143 07:49:34.078962
2144 07:49:34.280548 ec_init: CrosEC protocol v3 supported (256, 256)
2145 07:49:34.280706
2146 07:49:34.712185 R8152: Initializing
2147 07:49:34.712339
2148 07:49:34.716024 Version 6 (ocp_data = 5c30)
2149 07:49:34.716136
2150 07:49:34.719136 R8152: Done initializing
2151 07:49:34.719227
2152 07:49:34.722479 Adding net device
2153 07:49:34.722573
2154 07:49:35.026525 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2155 07:49:35.026678
2156 07:49:35.026762
2157 07:49:35.026827
2158 07:49:35.030063 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2160 07:49:35.130825 volteer: tftpboot 192.168.201.1 8119387/tftp-deploy-2gy0ytrs/kernel/bzImage 8119387/tftp-deploy-2gy0ytrs/kernel/cmdline 8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
2161 07:49:35.130999 Setting prompt string to 'Starting kernel'
2162 07:49:35.131078 Setting prompt string to ['Starting kernel']
2163 07:49:35.131150 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2164 07:49:35.131230 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2165 07:49:35.135149 tftpboot 192.168.201.1 8119387/tftp-deploy-2gy0ytrs/kernel/bzImoy-2gy0ytrs/kernel/cmdline 8119387/tftp-deploy-2gy0ytrs/ramdisk/ramdisk.cpio.gz
2166 07:49:35.135290
2167 07:49:35.135363 Waiting for link
2168 07:49:35.135440
2169 07:49:35.339360 done.
2170 07:49:35.339507
2171 07:49:35.339577 MAC: 00:24:32:30:77:76
2172 07:49:35.339641
2173 07:49:35.342349 Sending DHCP discover... done.
2174 07:49:35.342444
2175 07:49:35.345719 Waiting for reply... done.
2176 07:49:35.345821
2177 07:49:35.349591 Sending DHCP request... done.
2178 07:49:35.349707
2179 07:49:35.352284 Waiting for reply... done.
2180 07:49:35.352395
2181 07:49:35.355920 My ip is 192.168.201.16
2182 07:49:35.356071
2183 07:49:35.359262 The DHCP server ip is 192.168.201.1
2184 07:49:35.359379
2185 07:49:35.362245 TFTP server IP predefined by user: 192.168.201.1
2186 07:49:35.362332
2187 07:49:35.368901 Bootfile predefined by user: 8119387/tftp-deploy-2gy0ytrs/kernel/bzImage
2188 07:49:35.369030
2189 07:49:35.372683 Sending tftp read request... done.
2190 07:49:35.372794
2191 07:49:35.379017 Waiting for the transfer...
2192 07:49:35.379157
2193 07:49:35.949251 00000000 ################################################################
2194 07:49:35.949408
2195 07:49:36.518064 00080000 ################################################################
2196 07:49:36.518267
2197 07:49:37.086571 00100000 ################################################################
2198 07:49:37.086771
2199 07:49:37.653772 00180000 ################################################################
2200 07:49:37.653923
2201 07:49:38.221103 00200000 ################################################################
2202 07:49:38.221255
2203 07:49:38.795340 00280000 ################################################################
2204 07:49:38.795490
2205 07:49:39.341441 00300000 ################################################################
2206 07:49:39.341620
2207 07:49:39.891041 00380000 ################################################################
2208 07:49:39.891198
2209 07:49:40.447224 00400000 ################################################################
2210 07:49:40.447360
2211 07:49:41.008698 00480000 ################################################################
2212 07:49:41.008842
2213 07:49:41.563784 00500000 ################################################################
2214 07:49:41.563928
2215 07:49:42.083281 00580000 ################################################################
2216 07:49:42.083422
2217 07:49:42.649045 00600000 ################################################################
2218 07:49:42.649184
2219 07:49:42.986190 00680000 ####################################### done.
2220 07:49:42.986340
2221 07:49:42.990109 The bootfile was 7131024 bytes long.
2222 07:49:42.990222
2223 07:49:42.992819 Sending tftp read request... done.
2224 07:49:42.992906
2225 07:49:42.996564 Waiting for the transfer...
2226 07:49:42.996653
2227 07:49:43.545125 00000000 ################################################################
2228 07:49:43.545266
2229 07:49:44.092697 00080000 ################################################################
2230 07:49:44.092837
2231 07:49:44.765522 00100000 ################################################################
2232 07:49:44.766002
2233 07:49:45.473432 00180000 ################################################################
2234 07:49:45.474086
2235 07:49:46.103444 00200000 ################################################################
2236 07:49:46.103951
2237 07:49:46.788819 00280000 ################################################################
2238 07:49:46.788959
2239 07:49:47.367479 00300000 ################################################################
2240 07:49:47.367616
2241 07:49:47.963009 00380000 ################################################################
2242 07:49:47.963545
2243 07:49:48.576159 00400000 ################################################################
2244 07:49:48.576313
2245 07:49:49.135333 00480000 ################################################################
2246 07:49:49.135527
2247 07:49:49.711301 00500000 ################################################################
2248 07:49:49.711878
2249 07:49:50.302893 00580000 ################################################################
2250 07:49:50.303055
2251 07:49:50.859179 00600000 ################################################################
2252 07:49:50.859332
2253 07:49:51.437188 00680000 ################################################################
2254 07:49:51.437336
2255 07:49:51.992760 00700000 ################################################################
2256 07:49:51.992920
2257 07:49:52.523074 00780000 ################################################################
2258 07:49:52.523221
2259 07:49:53.068195 00800000 ################################################################
2260 07:49:53.068344
2261 07:49:53.618424 00880000 ################################################################
2262 07:49:53.618565
2263 07:49:54.172330 00900000 ################################################################
2264 07:49:54.172469
2265 07:49:54.703936 00980000 ################################################################
2266 07:49:54.704088
2267 07:49:55.257416 00a00000 ################################################################
2268 07:49:55.257595
2269 07:49:55.838598 00a80000 ################################################################
2270 07:49:55.838739
2271 07:49:56.430532 00b00000 ################################################################
2272 07:49:56.430671
2273 07:49:57.015686 00b80000 ################################################################
2274 07:49:57.015822
2275 07:49:57.600269 00c00000 ################################################################
2276 07:49:57.600403
2277 07:49:58.151440 00c80000 ################################################################
2278 07:49:58.151575
2279 07:49:58.706595 00d00000 ################################################################
2280 07:49:58.706733
2281 07:49:59.257010 00d80000 ################################################################
2282 07:49:59.257150
2283 07:49:59.816952 00e00000 ################################################################
2284 07:49:59.817090
2285 07:50:00.373325 00e80000 ################################################################
2286 07:50:00.373460
2287 07:50:00.902917 00f00000 ################################################################
2288 07:50:00.903070
2289 07:50:01.428639 00f80000 ################################################################
2290 07:50:01.428791
2291 07:50:01.950633 01000000 ################################################################
2292 07:50:01.950804
2293 07:50:02.467708 01080000 ################################################################
2294 07:50:02.467879
2295 07:50:03.000698 01100000 ################################################################
2296 07:50:03.000849
2297 07:50:03.537433 01180000 ################################################################
2298 07:50:03.537595
2299 07:50:04.068982 01200000 ################################################################
2300 07:50:04.069133
2301 07:50:04.601005 01280000 ################################################################
2302 07:50:04.601162
2303 07:50:05.133323 01300000 ################################################################
2304 07:50:05.133486
2305 07:50:05.654175 01380000 ################################################################
2306 07:50:05.654327
2307 07:50:06.190367 01400000 ################################################################
2308 07:50:06.190527
2309 07:50:06.714768 01480000 ################################################################
2310 07:50:06.714923
2311 07:50:07.227935 01500000 ################################################################
2312 07:50:07.228085
2313 07:50:07.754097 01580000 ################################################################
2314 07:50:07.754269
2315 07:50:08.269760 01600000 ################################################################
2316 07:50:08.269905
2317 07:50:08.810811 01680000 ################################################################
2318 07:50:08.810951
2319 07:50:09.345017 01700000 ################################################################
2320 07:50:09.345166
2321 07:50:09.874918 01780000 ################################################################
2322 07:50:09.875106
2323 07:50:10.398871 01800000 ################################################################
2324 07:50:10.399031
2325 07:50:10.913938 01880000 ################################################################
2326 07:50:10.914096
2327 07:50:11.444655 01900000 ################################################################
2328 07:50:11.444808
2329 07:50:11.969023 01980000 ################################################################
2330 07:50:11.969175
2331 07:50:12.482058 01a00000 ################################################################
2332 07:50:12.482200
2333 07:50:13.153001 01a80000 ################################################################
2334 07:50:13.153610
2335 07:50:13.835863 01b00000 ################################################################
2336 07:50:13.836414
2337 07:50:14.397211 01b80000 ################################################################
2338 07:50:14.397363
2339 07:50:14.958297 01c00000 ################################################################
2340 07:50:14.958450
2341 07:50:15.542145 01c80000 ################################################################
2342 07:50:15.542278
2343 07:50:16.130088 01d00000 ################################################################
2344 07:50:16.130235
2345 07:50:16.695926 01d80000 ################################################################
2346 07:50:16.696067
2347 07:50:17.265657 01e00000 ################################################################
2348 07:50:17.265809
2349 07:50:17.827388 01e80000 ################################################################
2350 07:50:17.827599
2351 07:50:18.387771 01f00000 ################################################################
2352 07:50:18.387914
2353 07:50:18.950922 01f80000 ################################################################
2354 07:50:18.951114
2355 07:50:19.518123 02000000 ################################################################
2356 07:50:19.518265
2357 07:50:20.074782 02080000 ################################################################
2358 07:50:20.075001
2359 07:50:20.630572 02100000 ################################################################
2360 07:50:20.630717
2361 07:50:21.204361 02180000 ################################################################
2362 07:50:21.204501
2363 07:50:21.388203 02200000 ##################### done.
2364 07:50:21.388341
2365 07:50:21.391427 Sending tftp read request... done.
2366 07:50:21.391504
2367 07:50:21.394747 Waiting for the transfer...
2368 07:50:21.394824
2369 07:50:21.394889 00000000 # done.
2370 07:50:21.394955
2371 07:50:21.405035 Command line loaded dynamically from TFTP file: 8119387/tftp-deploy-2gy0ytrs/kernel/cmdline
2372 07:50:21.405117
2373 07:50:21.418005 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2374 07:50:21.418097
2375 07:50:21.427195 Shutting down all USB controllers.
2376 07:50:21.427291
2377 07:50:21.427357 Removing current net device
2378 07:50:21.427427
2379 07:50:21.430437 Finalizing coreboot
2380 07:50:21.430517
2381 07:50:21.437149 Exiting depthcharge with code 4 at timestamp: 56187894
2382 07:50:21.437231
2383 07:50:21.437321
2384 07:50:21.437398 Starting kernel ...
2385 07:50:21.437473
2386 07:50:21.437597
2387 07:50:21.438092 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
2388 07:50:21.438214 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
2389 07:50:21.438298 Setting prompt string to ['Linux version [0-9]']
2390 07:50:21.438384 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2391 07:50:21.438475 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2392 07:50:21.440179
2394 07:54:17.439137 end: 2.2.5 auto-login-action (duration 00:03:56) [common]
2396 07:54:17.441127 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 236 seconds'
2398 07:54:17.442060 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2401 07:54:17.443583 end: 2 depthcharge-action (duration 00:05:00) [common]
2403 07:54:17.444773 Cleaning after the job
2404 07:54:17.445227 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/ramdisk
2405 07:54:17.456254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/kernel
2406 07:54:17.459049 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8119387/tftp-deploy-2gy0ytrs/modules
2407 07:54:17.460074 start: 4.1 power-off (timeout 00:00:30) [common]
2408 07:54:17.460914 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-9' '--port=1' '--command=off'
2409 07:54:17.486575 >> Command sent successfully.
2410 07:54:17.488390 Returned 0 in 0 seconds
2411 07:54:17.589573 end: 4.1 power-off (duration 00:00:00) [common]
2413 07:54:17.591097 start: 4.2 read-feedback (timeout 00:10:00) [common]
2414 07:54:17.592318 Listened to connection for namespace 'common' for up to 1s
2415 07:54:18.596768 Finalising connection for namespace 'common'
2416 07:54:18.597161 Disconnecting from shell: Finalise
2417 07:54:18.698401 end: 4.2 read-feedback (duration 00:00:01) [common]
2418 07:54:18.699236 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8119387
2419 07:54:18.762479 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8119387
2420 07:54:18.762670 JobError: Your job cannot terminate cleanly.