Boot log: asus-C436FA-Flip-hatch
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 0
- Warnings: 0
1 02:47:31.841955 lava-dispatcher, installed at version: 2022.11
2 02:47:31.842166 start: 0 validate
3 02:47:31.842313 Start time: 2023-01-25 02:47:31.842305+00:00 (UTC)
4 02:47:31.842455 Using caching service: 'http://localhost/cache/?uri=%s'
5 02:47:31.842600 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230120.0%2Fx86%2Frootfs.cpio.gz exists
6 02:47:32.134538 Using caching service: 'http://localhost/cache/?uri=%s'
7 02:47:32.135272 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip71-590-g22fc523bf881%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 02:47:32.422942 Using caching service: 'http://localhost/cache/?uri=%s'
9 02:47:32.423628 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip71-590-g22fc523bf881%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 02:47:32.722476 validate duration: 0.88
12 02:47:32.723711 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 02:47:32.724297 start: 1.1 download-retry (timeout 00:10:00) [common]
14 02:47:32.724760 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 02:47:32.725304 Not decompressing ramdisk as can be used compressed.
16 02:47:32.725739 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230120.0/x86/rootfs.cpio.gz
17 02:47:32.726091 saving as /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/ramdisk/rootfs.cpio.gz
18 02:47:32.726411 total size: 8423992 (8MB)
19 02:47:32.731256 progress 0% (0MB)
20 02:47:32.742114 progress 5% (0MB)
21 02:47:32.749122 progress 10% (0MB)
22 02:47:32.754544 progress 15% (1MB)
23 02:47:32.758915 progress 20% (1MB)
24 02:47:32.762710 progress 25% (2MB)
25 02:47:32.766025 progress 30% (2MB)
26 02:47:32.768893 progress 35% (2MB)
27 02:47:32.771913 progress 40% (3MB)
28 02:47:32.774577 progress 45% (3MB)
29 02:47:32.777185 progress 50% (4MB)
30 02:47:32.779500 progress 55% (4MB)
31 02:47:32.781801 progress 60% (4MB)
32 02:47:32.784138 progress 65% (5MB)
33 02:47:32.786252 progress 70% (5MB)
34 02:47:32.788559 progress 75% (6MB)
35 02:47:32.790846 progress 80% (6MB)
36 02:47:32.793124 progress 85% (6MB)
37 02:47:32.795404 progress 90% (7MB)
38 02:47:32.797739 progress 95% (7MB)
39 02:47:32.800040 progress 100% (8MB)
40 02:47:32.800249 8MB downloaded in 0.07s (108.80MB/s)
41 02:47:32.800419 end: 1.1.1 http-download (duration 00:00:00) [common]
43 02:47:32.800695 end: 1.1 download-retry (duration 00:00:00) [common]
44 02:47:32.800794 start: 1.2 download-retry (timeout 00:10:00) [common]
45 02:47:32.800892 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 02:47:32.801010 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip71-590-g22fc523bf881/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 02:47:32.801086 saving as /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/kernel/bzImage
48 02:47:32.801157 total size: 7569296 (7MB)
49 02:47:32.801226 No compression specified
50 02:47:32.802418 progress 0% (0MB)
51 02:47:32.804584 progress 5% (0MB)
52 02:47:32.806848 progress 10% (0MB)
53 02:47:32.808857 progress 15% (1MB)
54 02:47:32.811078 progress 20% (1MB)
55 02:47:32.813096 progress 25% (1MB)
56 02:47:32.815258 progress 30% (2MB)
57 02:47:32.817268 progress 35% (2MB)
58 02:47:32.819425 progress 40% (2MB)
59 02:47:32.821388 progress 45% (3MB)
60 02:47:32.823546 progress 50% (3MB)
61 02:47:32.825685 progress 55% (4MB)
62 02:47:32.827638 progress 60% (4MB)
63 02:47:32.829750 progress 65% (4MB)
64 02:47:32.831689 progress 70% (5MB)
65 02:47:32.833809 progress 75% (5MB)
66 02:47:32.835770 progress 80% (5MB)
67 02:47:32.837902 progress 85% (6MB)
68 02:47:32.839866 progress 90% (6MB)
69 02:47:32.841990 progress 95% (6MB)
70 02:47:32.843964 progress 100% (7MB)
71 02:47:32.844296 7MB downloaded in 0.04s (167.36MB/s)
72 02:47:32.844464 end: 1.2.1 http-download (duration 00:00:00) [common]
74 02:47:32.844731 end: 1.2 download-retry (duration 00:00:00) [common]
75 02:47:32.844831 start: 1.3 download-retry (timeout 00:10:00) [common]
76 02:47:32.844930 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 02:47:32.845045 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip71-590-g22fc523bf881/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 02:47:32.845122 saving as /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/modules/modules.tar
79 02:47:32.845193 total size: 51848 (0MB)
80 02:47:32.845262 Using unxz to decompress xz
81 02:47:32.848729 progress 63% (0MB)
82 02:47:32.849173 progress 100% (0MB)
83 02:47:32.852784 0MB downloaded in 0.01s (6.52MB/s)
84 02:47:32.853052 end: 1.3.1 http-download (duration 00:00:00) [common]
86 02:47:32.853352 end: 1.3 download-retry (duration 00:00:00) [common]
87 02:47:32.853461 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
88 02:47:32.853569 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
89 02:47:32.853665 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 02:47:32.853763 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
91 02:47:32.853958 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70
92 02:47:32.854083 makedir: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin
93 02:47:32.854202 makedir: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/tests
94 02:47:32.854300 makedir: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/results
95 02:47:32.854421 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-add-keys
96 02:47:32.854566 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-add-sources
97 02:47:32.854697 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-background-process-start
98 02:47:32.854825 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-background-process-stop
99 02:47:32.854952 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-common-functions
100 02:47:32.855075 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-echo-ipv4
101 02:47:32.855202 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-install-packages
102 02:47:32.855327 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-installed-packages
103 02:47:32.855449 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-os-build
104 02:47:32.855579 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-probe-channel
105 02:47:32.855705 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-probe-ip
106 02:47:32.855831 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-target-ip
107 02:47:32.855954 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-target-mac
108 02:47:32.856107 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-target-storage
109 02:47:32.856239 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-case
110 02:47:32.856362 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-event
111 02:47:32.856485 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-feedback
112 02:47:32.856608 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-raise
113 02:47:32.856736 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-reference
114 02:47:32.856860 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-runner
115 02:47:32.856981 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-set
116 02:47:32.857102 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-test-shell
117 02:47:32.857227 Updating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-install-packages (oe)
118 02:47:32.857353 Updating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/bin/lava-installed-packages (oe)
119 02:47:32.857464 Creating /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/environment
120 02:47:32.857564 LAVA metadata
121 02:47:32.857644 - LAVA_JOB_ID=8867187
122 02:47:32.857719 - LAVA_DISPATCHER_IP=192.168.201.1
123 02:47:32.857836 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
124 02:47:32.857911 skipped lava-vland-overlay
125 02:47:32.857998 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 02:47:32.858096 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
127 02:47:32.858206 skipped lava-multinode-overlay
128 02:47:32.858317 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 02:47:32.858415 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
130 02:47:32.858510 Loading test definitions
131 02:47:32.858622 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
132 02:47:32.858707 Using /lava-8867187 at stage 0
133 02:47:32.859002 uuid=8867187_1.4.2.3.1 testdef=None
134 02:47:32.859106 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 02:47:32.859208 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
136 02:47:32.859759 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 02:47:32.860015 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
139 02:47:32.860677 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 02:47:32.860951 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
142 02:47:32.861587 runner path: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/0/tests/0_dmesg test_uuid 8867187_1.4.2.3.1
143 02:47:32.861753 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 02:47:32.862016 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
146 02:47:32.862098 Using /lava-8867187 at stage 1
147 02:47:32.862379 uuid=8867187_1.4.2.3.5 testdef=None
148 02:47:32.862483 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
149 02:47:32.862582 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
150 02:47:32.863086 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
152 02:47:32.863342 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
153 02:47:32.863983 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
155 02:47:32.864263 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
156 02:47:32.864876 runner path: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/1/tests/1_bootrr test_uuid 8867187_1.4.2.3.5
157 02:47:32.865035 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
159 02:47:32.865273 Creating lava-test-runner.conf files
160 02:47:32.865346 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/0 for stage 0
161 02:47:32.865447 - 0_dmesg
162 02:47:32.865534 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8867187/lava-overlay-xh1xlw70/lava-8867187/1 for stage 1
163 02:47:32.865628 - 1_bootrr
164 02:47:32.865731 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
165 02:47:32.865828 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
166 02:47:32.872761 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
167 02:47:32.872892 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
168 02:47:32.872994 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
169 02:47:32.873094 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
170 02:47:32.873194 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
171 02:47:33.075839 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
172 02:47:33.076309 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
173 02:47:33.076483 extracting modules file /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8867187/extract-overlay-ramdisk-yvkcd3dx/ramdisk
174 02:47:33.082956 end: 1.4.4 extract-modules (duration 00:00:00) [common]
175 02:47:33.083127 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
176 02:47:33.083264 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8867187/compress-overlay-889pw5i3/overlay-1.4.2.4.tar.gz to ramdisk
177 02:47:33.083386 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8867187/compress-overlay-889pw5i3/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8867187/extract-overlay-ramdisk-yvkcd3dx/ramdisk
178 02:47:33.087728 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
179 02:47:33.087852 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
180 02:47:33.087957 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
181 02:47:33.088067 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
182 02:47:33.088156 Building ramdisk /var/lib/lava/dispatcher/tmp/8867187/extract-overlay-ramdisk-yvkcd3dx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8867187/extract-overlay-ramdisk-yvkcd3dx/ramdisk
183 02:47:33.157813 >> 48122 blocks
184 02:47:33.993517 rename /var/lib/lava/dispatcher/tmp/8867187/extract-overlay-ramdisk-yvkcd3dx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
185 02:47:33.993963 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
186 02:47:33.994097 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
187 02:47:33.994212 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
188 02:47:33.994317 No mkimage arch provided, not using FIT.
189 02:47:33.994419 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
190 02:47:33.994513 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
191 02:47:33.994623 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
192 02:47:33.994726 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
193 02:47:33.994823 No LXC device requested
194 02:47:33.994919 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
195 02:47:33.995020 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
196 02:47:33.995115 end: 1.6 deploy-device-env (duration 00:00:00) [common]
197 02:47:33.995194 Checking files for TFTP limit of 4294967296 bytes.
198 02:47:33.995619 end: 1 tftp-deploy (duration 00:00:01) [common]
199 02:47:33.995741 start: 2 depthcharge-action (timeout 00:05:00) [common]
200 02:47:33.995870 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
201 02:47:33.996014 substitutions:
202 02:47:33.996098 - {DTB}: None
203 02:47:33.996172 - {INITRD}: 8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
204 02:47:33.996242 - {KERNEL}: 8867187/tftp-deploy-rcbrk828/kernel/bzImage
205 02:47:33.996309 - {LAVA_MAC}: None
206 02:47:33.996375 - {PRESEED_CONFIG}: None
207 02:47:33.996440 - {PRESEED_LOCAL}: None
208 02:47:33.996504 - {RAMDISK}: 8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
209 02:47:33.996568 - {ROOT_PART}: None
210 02:47:33.996633 - {ROOT}: None
211 02:47:33.996696 - {SERVER_IP}: 192.168.201.1
212 02:47:33.996759 - {TEE}: None
213 02:47:33.996823 Parsed boot commands:
214 02:47:33.996885 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
215 02:47:33.997052 Parsed boot commands: tftpboot 192.168.201.1 8867187/tftp-deploy-rcbrk828/kernel/bzImage 8867187/tftp-deploy-rcbrk828/kernel/cmdline 8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
216 02:47:33.997155 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
217 02:47:33.997259 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
218 02:47:33.997365 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
219 02:47:33.997461 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
220 02:47:33.997540 Not connected, no need to disconnect.
221 02:47:33.997624 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
222 02:47:33.997719 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
223 02:47:33.997795 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-4'
224 02:47:34.000541 Setting prompt string to ['lava-test: # ']
225 02:47:34.000865 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
226 02:47:34.000981 end: 2.2.1 reset-connection (duration 00:00:00) [common]
227 02:47:34.001092 start: 2.2.2 reset-device (timeout 00:05:00) [common]
228 02:47:34.001192 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
229 02:47:34.001381 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=reboot'
230 02:47:34.022120 >> Command sent successfully.
231 02:47:34.024166 Returned 0 in 0 seconds
232 02:47:34.125244 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
234 02:47:34.127306 end: 2.2.2 reset-device (duration 00:00:00) [common]
235 02:47:34.127777 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
236 02:47:34.128193 Setting prompt string to 'Starting depthcharge on Helios...'
237 02:47:34.128506 Changing prompt to 'Starting depthcharge on Helios...'
238 02:47:34.128838 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
239 02:47:34.129919 [Enter `^Ec?' for help]
240 02:47:41.430280
241 02:47:41.430834
242 02:47:41.440844 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
243 02:47:41.443899 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
244 02:47:41.450934 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
245 02:47:41.453955 CPU: AES supported, TXT NOT supported, VT supported
246 02:47:41.460882 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
247 02:47:41.463923 PCH: device id 0284 (rev 00) is Cometlake-U Premium
248 02:47:41.470400 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
249 02:47:41.473756 VBOOT: Loading verstage.
250 02:47:41.477344 FMAP: Found "FLASH" version 1.1 at 0xc04000.
251 02:47:41.483824 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
252 02:47:41.487018 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
253 02:47:41.490167 CBFS @ c08000 size 3f8000
254 02:47:41.497023 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
255 02:47:41.500775 CBFS: Locating 'fallback/verstage'
256 02:47:41.503881 CBFS: Found @ offset 10fb80 size 1072c
257 02:47:41.507054
258 02:47:41.507538
259 02:47:41.517092 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
260 02:47:41.531461 Probing TPM: . done!
261 02:47:41.535268 TPM ready after 0 ms
262 02:47:41.538372 Connected to device vid:did:rid of 1ae0:0028:00
263 02:47:41.548496 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
264 02:47:41.551683 Initialized TPM device CR50 revision 0
265 02:47:41.595453 tlcl_send_startup: Startup return code is 0
266 02:47:41.595991 TPM: setup succeeded
267 02:47:41.608098 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
268 02:47:41.611927 Chrome EC: UHEPI supported
269 02:47:41.614969 Phase 1
270 02:47:41.618840 FMAP: area GBB found @ c05000 (12288 bytes)
271 02:47:41.625125 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
272 02:47:41.625588 Phase 2
273 02:47:41.628239
274 02:47:41.628702 Phase 3
275 02:47:41.632093 FMAP: area GBB found @ c05000 (12288 bytes)
276 02:47:41.638377 VB2:vb2_report_dev_firmware() This is developer signed firmware
277 02:47:41.644662 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
278 02:47:41.648435 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
279 02:47:41.654652 VB2:vb2_verify_keyblock() Checking keyblock signature...
280 02:47:41.670955 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
281 02:47:41.673884 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
282 02:47:41.680672 VB2:vb2_verify_fw_preamble() Verifying preamble.
283 02:47:41.684518 Phase 4
284 02:47:41.688229 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
285 02:47:41.694449 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
286 02:47:41.873632 VB2:vb2_rsa_verify_digest() Digest check failed!
287 02:47:41.877375 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
288 02:47:41.880357
289 02:47:41.880454 Saving nvdata
290 02:47:41.883994 Reboot requested (10020007)
291 02:47:41.886979 board_reset() called!
292 02:47:41.887077 full_reset() called!
293 02:47:46.397221
294 02:47:46.397373
295 02:47:46.407547 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
296 02:47:46.410774 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
297 02:47:46.417475 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
298 02:47:46.420597 CPU: AES supported, TXT NOT supported, VT supported
299 02:47:46.427345 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
300 02:47:46.430486 PCH: device id 0284 (rev 00) is Cometlake-U Premium
301 02:47:46.437187 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
302 02:47:46.440368 VBOOT: Loading verstage.
303 02:47:46.443641 FMAP: Found "FLASH" version 1.1 at 0xc04000.
304 02:47:46.450188 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
305 02:47:46.453715 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
306 02:47:46.456874 CBFS @ c08000 size 3f8000
307 02:47:46.463445 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
308 02:47:46.466739 CBFS: Locating 'fallback/verstage'
309 02:47:46.470083 CBFS: Found @ offset 10fb80 size 1072c
310 02:47:46.473971
311 02:47:46.474085
312 02:47:46.483997 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
313 02:47:46.498467 Probing TPM: . done!
314 02:47:46.501545 TPM ready after 0 ms
315 02:47:46.504944 Connected to device vid:did:rid of 1ae0:0028:00
316 02:47:46.515615 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
317 02:47:46.518649 Initialized TPM device CR50 revision 0
318 02:47:46.562204 tlcl_send_startup: Startup return code is 0
319 02:47:46.562328 TPM: setup succeeded
320 02:47:46.574603 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
321 02:47:46.578632 Chrome EC: UHEPI supported
322 02:47:46.581960 Phase 1
323 02:47:46.585274 FMAP: area GBB found @ c05000 (12288 bytes)
324 02:47:46.592016 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
325 02:47:46.598919 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
326 02:47:46.601597 Recovery requested (1009000e)
327 02:47:46.607944 Saving nvdata
328 02:47:46.613463 tlcl_extend: response is 0
329 02:47:46.622584 tlcl_extend: response is 0
330 02:47:46.629750 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
331 02:47:46.633130 CBFS @ c08000 size 3f8000
332 02:47:46.639753 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
333 02:47:46.642923 CBFS: Locating 'fallback/romstage'
334 02:47:46.646449 CBFS: Found @ offset 80 size 145fc
335 02:47:46.649709 Accumulated console time in verstage 98 ms
336 02:47:46.649825
337 02:47:46.649925
338 02:47:46.662783 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
339 02:47:46.669637 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
340 02:47:46.672926 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
341 02:47:46.676210 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
342 02:47:46.682912 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
343 02:47:46.685561 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
344 02:47:46.689375 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
345 02:47:46.692594 TCO_STS: 0000 0000
346 02:47:46.695819 GEN_PMCON: e0015238 00000200
347 02:47:46.699171 GBLRST_CAUSE: 00000000 00000000
348 02:47:46.699287 prev_sleep_state 5
349 02:47:46.702329 Boot Count incremented to 42963
350 02:47:46.709378 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
351 02:47:46.712608 CBFS @ c08000 size 3f8000
352 02:47:46.719188 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
353 02:47:46.719284 CBFS: Locating 'fspm.bin'
354 02:47:46.726180 CBFS: Found @ offset 5ffc0 size 71000
355 02:47:46.729425 Chrome EC: UHEPI supported
356 02:47:46.735975 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
357 02:47:46.739249 Probing TPM: done!
358 02:47:46.746541 Connected to device vid:did:rid of 1ae0:0028:00
359 02:47:46.756192 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
360 02:47:46.762288 Initialized TPM device CR50 revision 0
361 02:47:46.770780 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
362 02:47:46.777452 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
363 02:47:46.780749 MRC cache found, size 1948
364 02:47:46.783957 bootmode is set to: 2
365 02:47:46.787897 PRMRR disabled by config.
366 02:47:46.787987 SPD INDEX = 1
367 02:47:46.790590
368 02:47:46.794059 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
369 02:47:46.797769 CBFS @ c08000 size 3f8000
370 02:47:46.803864 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
371 02:47:46.803956 CBFS: Locating 'spd.bin'
372 02:47:46.807630 CBFS: Found @ offset 5fb80 size 400
373 02:47:46.810976 SPD: module type is LPDDR3
374 02:47:46.813853 SPD: module part is
375 02:47:46.820486 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
376 02:47:46.823825 SPD: device width 4 bits, bus width 8 bits
377 02:47:46.827688 SPD: module size is 4096 MB (per channel)
378 02:47:46.830803 memory slot: 0 configuration done.
379 02:47:46.834094 memory slot: 2 configuration done.
380 02:47:46.885537 CBMEM:
381 02:47:46.888923 IMD: root @ 99fff000 254 entries.
382 02:47:46.892305 IMD: root @ 99ffec00 62 entries.
383 02:47:46.895568 External stage cache:
384 02:47:46.898385 IMD: root @ 9abff000 254 entries.
385 02:47:46.902418 IMD: root @ 9abfec00 62 entries.
386 02:47:46.905554 Chrome EC: clear events_b mask to 0x0000000020004000
387 02:47:46.908907
388 02:47:46.921474 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
389 02:47:46.935023 tlcl_write: response is 0
390 02:47:46.943936 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
391 02:47:46.950383 MRC: TPM MRC hash updated successfully.
392 02:47:46.950504 2 DIMMs found
393 02:47:46.953562 SMM Memory Map
394 02:47:46.956965 SMRAM : 0x9a000000 0x1000000
395 02:47:46.960152 Subregion 0: 0x9a000000 0xa00000
396 02:47:46.963342 Subregion 1: 0x9aa00000 0x200000
397 02:47:46.966636 Subregion 2: 0x9ac00000 0x400000
398 02:47:46.970549 top_of_ram = 0x9a000000
399 02:47:46.973400 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
400 02:47:46.980118 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
401 02:47:46.983327 MTRR Range: Start=ff000000 End=0 (Size 1000000)
402 02:47:46.989893 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
403 02:47:46.993502 CBFS @ c08000 size 3f8000
404 02:47:46.996748 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
405 02:47:47.000057 CBFS: Locating 'fallback/postcar'
406 02:47:47.006446 CBFS: Found @ offset 107000 size 4b44
407 02:47:47.010048 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
408 02:47:47.022303 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
409 02:47:47.025454 Processing 180 relocs. Offset value of 0x97c0c000
410 02:47:47.033986 Accumulated console time in romstage 286 ms
411 02:47:47.034102
412 02:47:47.034182
413 02:47:47.044069 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
414 02:47:47.050782 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
415 02:47:47.054113 CBFS @ c08000 size 3f8000
416 02:47:47.057034 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
417 02:47:47.063723 CBFS: Locating 'fallback/ramstage'
418 02:47:47.067061 CBFS: Found @ offset 43380 size 1b9e8
419 02:47:47.073872 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
420 02:47:47.106007 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
421 02:47:47.109102 Processing 3976 relocs. Offset value of 0x98db0000
422 02:47:47.115608 Accumulated console time in postcar 52 ms
423 02:47:47.115707
424 02:47:47.115785
425 02:47:47.125695 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
426 02:47:47.132273 FMAP: area RO_VPD found @ c00000 (16384 bytes)
427 02:47:47.135568 WARNING: RO_VPD is uninitialized or empty.
428 02:47:47.138819 FMAP: area RW_VPD found @ af8000 (8192 bytes)
429 02:47:47.145616 FMAP: area RW_VPD found @ af8000 (8192 bytes)
430 02:47:47.145715 Normal boot.
431 02:47:47.151984 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
432 02:47:47.155339 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
433 02:47:47.158804 CBFS @ c08000 size 3f8000
434 02:47:47.165081 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
435 02:47:47.169154 CBFS: Locating 'cpu_microcode_blob.bin'
436 02:47:47.172113 CBFS: Found @ offset 14700 size 2ec00
437 02:47:47.175398 microcode: sig=0x806ec pf=0x4 revision=0xc9
438 02:47:47.178470 Skip microcode update
439 02:47:47.185072 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
440 02:47:47.185171 CBFS @ c08000 size 3f8000
441 02:47:47.191762 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
442 02:47:47.195315 CBFS: Locating 'fsps.bin'
443 02:47:47.198544 CBFS: Found @ offset d1fc0 size 35000
444 02:47:47.224397 Detected 4 core, 8 thread CPU.
445 02:47:47.227525 Setting up SMI for CPU
446 02:47:47.230772 IED base = 0x9ac00000
447 02:47:47.230865 IED size = 0x00400000
448 02:47:47.234006 Will perform SMM setup.
449 02:47:47.240382 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
450 02:47:47.246757 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
451 02:47:47.253256 Processing 16 relocs. Offset value of 0x00030000
452 02:47:47.253358 Attempting to start 7 APs
453 02:47:47.259744 Waiting for 10ms after sending INIT.
454 02:47:47.273978 Waiting for 1st SIPI to complete...AP: slot 3 apic_id 1.
455 02:47:47.274084 done.
456 02:47:47.277232 AP: slot 2 apic_id 4.
457 02:47:47.280673 AP: slot 5 apic_id 5.
458 02:47:47.283843 Waiting for 2nd SIPI to complete...done.
459 02:47:47.287121 AP: slot 6 apic_id 7.
460 02:47:47.287217 AP: slot 7 apic_id 6.
461 02:47:47.290537 AP: slot 4 apic_id 2.
462 02:47:47.293919 AP: slot 1 apic_id 3.
463 02:47:47.300462 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
464 02:47:47.303576 Processing 13 relocs. Offset value of 0x00038000
465 02:47:47.310158 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
466 02:47:47.316686 Installing SMM handler to 0x9a000000
467 02:47:47.323701 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
468 02:47:47.326892 Processing 658 relocs. Offset value of 0x9a010000
469 02:47:47.336544 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
470 02:47:47.340585 Processing 13 relocs. Offset value of 0x9a008000
471 02:47:47.346452 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
472 02:47:47.352963 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
473 02:47:47.359459 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
474 02:47:47.362936 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
475 02:47:47.369636 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
476 02:47:47.376485 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
477 02:47:47.379574 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
478 02:47:47.386151 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
479 02:47:47.390030 Clearing SMI status registers
480 02:47:47.393370 SMI_STS: PM1
481 02:47:47.393468 PM1_STS: PWRBTN
482 02:47:47.396736 TCO_STS: SECOND_TO
483 02:47:47.400070 New SMBASE 0x9a000000
484 02:47:47.403264 In relocation handler: CPU 0
485 02:47:47.406547 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
486 02:47:47.409741 Writing SMRR. base = 0x9a000006, mask=0xff000800
487 02:47:47.413111 Relocation complete.
488 02:47:47.416486 New SMBASE 0x99fff400
489 02:47:47.416574 In relocation handler: CPU 3
490 02:47:47.419711
491 02:47:47.422765 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
492 02:47:47.426183 Writing SMRR. base = 0x9a000006, mask=0xff000800
493 02:47:47.429294 Relocation complete.
494 02:47:47.433065 New SMBASE 0x99fff000
495 02:47:47.433155 In relocation handler: CPU 4
496 02:47:47.439266 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
497 02:47:47.443301 Writing SMRR. base = 0x9a000006, mask=0xff000800
498 02:47:47.446542 Relocation complete.
499 02:47:47.449247 New SMBASE 0x99fffc00
500 02:47:47.449346 In relocation handler: CPU 1
501 02:47:47.455760 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
502 02:47:47.459243 Writing SMRR. base = 0x9a000006, mask=0xff000800
503 02:47:47.462581 Relocation complete.
504 02:47:47.462676 New SMBASE 0x99ffe800
505 02:47:47.465954 In relocation handler: CPU 6
506 02:47:47.472419 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
507 02:47:47.475820 Writing SMRR. base = 0x9a000006, mask=0xff000800
508 02:47:47.479591 Relocation complete.
509 02:47:47.479682 New SMBASE 0x99ffe400
510 02:47:47.482652 In relocation handler: CPU 7
511 02:47:47.489283 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
512 02:47:47.492586 Writing SMRR. base = 0x9a000006, mask=0xff000800
513 02:47:47.495746 Relocation complete.
514 02:47:47.495842 New SMBASE 0x99fff800
515 02:47:47.499037 In relocation handler: CPU 2
516 02:47:47.502382 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
517 02:47:47.508921 Writing SMRR. base = 0x9a000006, mask=0xff000800
518 02:47:47.512182 Relocation complete.
519 02:47:47.512273 New SMBASE 0x99ffec00
520 02:47:47.515377 In relocation handler: CPU 5
521 02:47:47.518830 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
522 02:47:47.525443 Writing SMRR. base = 0x9a000006, mask=0xff000800
523 02:47:47.528568 Relocation complete.
524 02:47:47.528661 Initializing CPU #0
525 02:47:47.532598 CPU: vendor Intel device 806ec
526 02:47:47.535462 CPU: family 06, model 8e, stepping 0c
527 02:47:47.538695 Clearing out pending MCEs
528 02:47:47.541881 Setting up local APIC...
529 02:47:47.545555 apic_id: 0x00 done.
530 02:47:47.545644 Turbo is available but hidden
531 02:47:47.549046 Turbo is available and visible
532 02:47:47.552163 VMX status: enabled
533 02:47:47.555380 IA32_FEATURE_CONTROL status: locked
534 02:47:47.558721 Skip microcode update
535 02:47:47.558817 CPU #0 initialized
536 02:47:47.562092 Initializing CPU #3
537 02:47:47.565422 Initializing CPU #6
538 02:47:47.568607 CPU: vendor Intel device 806ec
539 02:47:47.572020 CPU: family 06, model 8e, stepping 0c
540 02:47:47.575227 Clearing out pending MCEs
541 02:47:47.575340 Initializing CPU #4
542 02:47:47.578535 Initializing CPU #1
543 02:47:47.581708 CPU: vendor Intel device 806ec
544 02:47:47.585471 CPU: family 06, model 8e, stepping 0c
545 02:47:47.588618 CPU: vendor Intel device 806ec
546 02:47:47.592032 CPU: family 06, model 8e, stepping 0c
547 02:47:47.594923 Clearing out pending MCEs
548 02:47:47.598420 Clearing out pending MCEs
549 02:47:47.598516 Setting up local APIC...
550 02:47:47.601678 Initializing CPU #7
551 02:47:47.604795 CPU: vendor Intel device 806ec
552 02:47:47.608649 CPU: family 06, model 8e, stepping 0c
553 02:47:47.611752 CPU: vendor Intel device 806ec
554 02:47:47.615074 CPU: family 06, model 8e, stepping 0c
555 02:47:47.618298 Clearing out pending MCEs
556 02:47:47.621587 Clearing out pending MCEs
557 02:47:47.621673 Setting up local APIC...
558 02:47:47.624774 Setting up local APIC...
559 02:47:47.628477 Setting up local APIC...
560 02:47:47.631759 apic_id: 0x02 done.
561 02:47:47.631855 Setting up local APIC...
562 02:47:47.634865 apic_id: 0x01 done.
563 02:47:47.638064 Initializing CPU #2
564 02:47:47.638160 Initializing CPU #5
565 02:47:47.641559 CPU: vendor Intel device 806ec
566 02:47:47.644738 CPU: family 06, model 8e, stepping 0c
567 02:47:47.647925 CPU: vendor Intel device 806ec
568 02:47:47.651330 CPU: family 06, model 8e, stepping 0c
569 02:47:47.654707 Clearing out pending MCEs
570 02:47:47.658056 Clearing out pending MCEs
571 02:47:47.661418 Setting up local APIC...
572 02:47:47.661516 VMX status: enabled
573 02:47:47.664668 apic_id: 0x03 done.
574 02:47:47.668063 IA32_FEATURE_CONTROL status: locked
575 02:47:47.671373 VMX status: enabled
576 02:47:47.671469 Skip microcode update
577 02:47:47.677733 IA32_FEATURE_CONTROL status: locked
578 02:47:47.677828 CPU #4 initialized
579 02:47:47.681303 Skip microcode update
580 02:47:47.684284 Setting up local APIC...
581 02:47:47.684386 apic_id: 0x07 done.
582 02:47:47.687585 apic_id: 0x06 done.
583 02:47:47.687683 VMX status: enabled
584 02:47:47.691045 VMX status: enabled
585 02:47:47.694380 IA32_FEATURE_CONTROL status: locked
586 02:47:47.697707 IA32_FEATURE_CONTROL status: locked
587 02:47:47.701081 Skip microcode update
588 02:47:47.704388 Skip microcode update
589 02:47:47.704502 CPU #6 initialized
590 02:47:47.707610 CPU #7 initialized
591 02:47:47.707705 apic_id: 0x04 done.
592 02:47:47.710727 apic_id: 0x05 done.
593 02:47:47.714176 VMX status: enabled
594 02:47:47.714264 VMX status: enabled
595 02:47:47.717416 IA32_FEATURE_CONTROL status: locked
596 02:47:47.721393 IA32_FEATURE_CONTROL status: locked
597 02:47:47.724370 Skip microcode update
598 02:47:47.727681 Skip microcode update
599 02:47:47.727771 CPU #2 initialized
600 02:47:47.730742 CPU #5 initialized
601 02:47:47.734505 VMX status: enabled
602 02:47:47.734587 CPU #1 initialized
603 02:47:47.737636 IA32_FEATURE_CONTROL status: locked
604 02:47:47.740945 Skip microcode update
605 02:47:47.744105 CPU #3 initialized
606 02:47:47.747352 bsp_do_flight_plan done after 461 msecs.
607 02:47:47.750696 CPU: frequency set to 4200 MHz
608 02:47:47.750801 Enabling SMIs.
609 02:47:47.753921 Locking SMM.
610 02:47:47.768257 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
611 02:47:47.771646 CBFS @ c08000 size 3f8000
612 02:47:47.778018 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
613 02:47:47.778119 CBFS: Locating 'vbt.bin'
614 02:47:47.781107 CBFS: Found @ offset 5f5c0 size 499
615 02:47:47.787907 Found a VBT of 4608 bytes after decompression
616 02:47:47.971308 Display FSP Version Info HOB
617 02:47:47.974322 Reference Code - CPU = 9.0.1e.30
618 02:47:47.977780 uCode Version = 0.0.0.ca
619 02:47:47.981003 TXT ACM version = ff.ff.ff.ffff
620 02:47:47.984192 Display FSP Version Info HOB
621 02:47:47.987630 Reference Code - ME = 9.0.1e.30
622 02:47:47.990846 MEBx version = 0.0.0.0
623 02:47:47.994042 ME Firmware Version = Consumer SKU
624 02:47:47.997890 Display FSP Version Info HOB
625 02:47:48.001114 Reference Code - CML PCH = 9.0.1e.30
626 02:47:48.004429 PCH-CRID Status = Disabled
627 02:47:48.007524 PCH-CRID Original Value = ff.ff.ff.ffff
628 02:47:48.010934 PCH-CRID New Value = ff.ff.ff.ffff
629 02:47:48.014129 OPROM - RST - RAID = ff.ff.ff.ffff
630 02:47:48.017336 ChipsetInit Base Version = ff.ff.ff.ffff
631 02:47:48.020583 ChipsetInit Oem Version = ff.ff.ff.ffff
632 02:47:48.023602 Display FSP Version Info HOB
633 02:47:48.030083 Reference Code - SA - System Agent = 9.0.1e.30
634 02:47:48.033785 Reference Code - MRC = 0.7.1.6c
635 02:47:48.037326 SA - PCIe Version = 9.0.1e.30
636 02:47:48.037424 SA-CRID Status = Disabled
637 02:47:48.040386 SA-CRID Original Value = 0.0.0.c
638 02:47:48.043571 SA-CRID New Value = 0.0.0.c
639 02:47:48.046749 OPROM - VBIOS = ff.ff.ff.ffff
640 02:47:48.049971 RTC Init
641 02:47:48.053330 Set power on after power failure.
642 02:47:48.053429 Disabling Deep S3
643 02:47:48.057207 Disabling Deep S3
644 02:47:48.057304 Disabling Deep S4
645 02:47:48.060485 Disabling Deep S4
646 02:47:48.063375 Disabling Deep S5
647 02:47:48.063482 Disabling Deep S5
648 02:47:48.070113 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 193 exit 1
649 02:47:48.070210 Enumerating buses...
650 02:47:48.073434
651 02:47:48.076746 Show all devs... Before device enumeration.
652 02:47:48.080065 Root Device: enabled 1
653 02:47:48.080172 CPU_CLUSTER: 0: enabled 1
654 02:47:48.083458 DOMAIN: 0000: enabled 1
655 02:47:48.086606 APIC: 00: enabled 1
656 02:47:48.086701 PCI: 00:00.0: enabled 1
657 02:47:48.089929 PCI: 00:02.0: enabled 1
658 02:47:48.093172 PCI: 00:04.0: enabled 0
659 02:47:48.096471 PCI: 00:05.0: enabled 0
660 02:47:48.096570 PCI: 00:12.0: enabled 1
661 02:47:48.099680 PCI: 00:12.5: enabled 0
662 02:47:48.102773 PCI: 00:12.6: enabled 0
663 02:47:48.105934 PCI: 00:14.0: enabled 1
664 02:47:48.106038 PCI: 00:14.1: enabled 0
665 02:47:48.109242 PCI: 00:14.3: enabled 1
666 02:47:48.112890 PCI: 00:14.5: enabled 0
667 02:47:48.116213 PCI: 00:15.0: enabled 1
668 02:47:48.116310 PCI: 00:15.1: enabled 1
669 02:47:48.119339 PCI: 00:15.2: enabled 0
670 02:47:48.123289 PCI: 00:15.3: enabled 0
671 02:47:48.123384 PCI: 00:16.0: enabled 1
672 02:47:48.126405 PCI: 00:16.1: enabled 0
673 02:47:48.129554 PCI: 00:16.2: enabled 0
674 02:47:48.132769 PCI: 00:16.3: enabled 0
675 02:47:48.132857 PCI: 00:16.4: enabled 0
676 02:47:48.136069 PCI: 00:16.5: enabled 0
677 02:47:48.139245 PCI: 00:17.0: enabled 1
678 02:47:48.142453 PCI: 00:19.0: enabled 1
679 02:47:48.142541 PCI: 00:19.1: enabled 0
680 02:47:48.146083 PCI: 00:19.2: enabled 0
681 02:47:48.149213 PCI: 00:1a.0: enabled 0
682 02:47:48.152483 PCI: 00:1c.0: enabled 0
683 02:47:48.152582 PCI: 00:1c.1: enabled 0
684 02:47:48.155717 PCI: 00:1c.2: enabled 0
685 02:47:48.158904 PCI: 00:1c.3: enabled 0
686 02:47:48.162728 PCI: 00:1c.4: enabled 0
687 02:47:48.162828 PCI: 00:1c.5: enabled 0
688 02:47:48.165935 PCI: 00:1c.6: enabled 0
689 02:47:48.169017 PCI: 00:1c.7: enabled 0
690 02:47:48.169105 PCI: 00:1d.0: enabled 1
691 02:47:48.172124 PCI: 00:1d.1: enabled 0
692 02:47:48.175996 PCI: 00:1d.2: enabled 0
693 02:47:48.179124 PCI: 00:1d.3: enabled 0
694 02:47:48.179214 PCI: 00:1d.4: enabled 0
695 02:47:48.182296 PCI: 00:1d.5: enabled 1
696 02:47:48.185488 PCI: 00:1e.0: enabled 1
697 02:47:48.188617 PCI: 00:1e.1: enabled 0
698 02:47:48.188705 PCI: 00:1e.2: enabled 1
699 02:47:48.192326 PCI: 00:1e.3: enabled 1
700 02:47:48.195664 PCI: 00:1f.0: enabled 1
701 02:47:48.198665 PCI: 00:1f.1: enabled 1
702 02:47:48.198751 PCI: 00:1f.2: enabled 1
703 02:47:48.202038 PCI: 00:1f.3: enabled 1
704 02:47:48.205376 PCI: 00:1f.4: enabled 1
705 02:47:48.205461 PCI: 00:1f.5: enabled 1
706 02:47:48.208592
707 02:47:48.208679 PCI: 00:1f.6: enabled 0
708 02:47:48.211918 USB0 port 0: enabled 1
709 02:47:48.215723 I2C: 00:15: enabled 1
710 02:47:48.215812 I2C: 00:5d: enabled 1
711 02:47:48.218862 GENERIC: 0.0: enabled 1
712 02:47:48.222069 I2C: 00:1a: enabled 1
713 02:47:48.222158 I2C: 00:38: enabled 1
714 02:47:48.225309 I2C: 00:39: enabled 1
715 02:47:48.228373 I2C: 00:3a: enabled 1
716 02:47:48.228460 I2C: 00:3b: enabled 1
717 02:47:48.231693 PCI: 00:00.0: enabled 1
718 02:47:48.235504 SPI: 00: enabled 1
719 02:47:48.235592 SPI: 01: enabled 1
720 02:47:48.238616 PNP: 0c09.0: enabled 1
721 02:47:48.241820 USB2 port 0: enabled 1
722 02:47:48.241907 USB2 port 1: enabled 1
723 02:47:48.245027 USB2 port 2: enabled 0
724 02:47:48.248216 USB2 port 3: enabled 0
725 02:47:48.252105 USB2 port 5: enabled 0
726 02:47:48.252199 USB2 port 6: enabled 1
727 02:47:48.255302 USB2 port 9: enabled 1
728 02:47:48.258497 USB3 port 0: enabled 1
729 02:47:48.258586 USB3 port 1: enabled 1
730 02:47:48.261565 USB3 port 2: enabled 1
731 02:47:48.264816 USB3 port 3: enabled 1
732 02:47:48.264904 USB3 port 4: enabled 0
733 02:47:48.268140 APIC: 03: enabled 1
734 02:47:48.271944 APIC: 04: enabled 1
735 02:47:48.272043 APIC: 01: enabled 1
736 02:47:48.275239 APIC: 02: enabled 1
737 02:47:48.278299 APIC: 05: enabled 1
738 02:47:48.278386 APIC: 07: enabled 1
739 02:47:48.281604 APIC: 06: enabled 1
740 02:47:48.281690 Compare with tree...
741 02:47:48.284724 Root Device: enabled 1
742 02:47:48.287947 CPU_CLUSTER: 0: enabled 1
743 02:47:48.291777 APIC: 00: enabled 1
744 02:47:48.291881 APIC: 03: enabled 1
745 02:47:48.295122 APIC: 04: enabled 1
746 02:47:48.298264 APIC: 01: enabled 1
747 02:47:48.298356 APIC: 02: enabled 1
748 02:47:48.301396 APIC: 05: enabled 1
749 02:47:48.304547 APIC: 07: enabled 1
750 02:47:48.304634 APIC: 06: enabled 1
751 02:47:48.307896 DOMAIN: 0000: enabled 1
752 02:47:48.311085 PCI: 00:00.0: enabled 1
753 02:47:48.314906 PCI: 00:02.0: enabled 1
754 02:47:48.318025 PCI: 00:04.0: enabled 0
755 02:47:48.318112 PCI: 00:05.0: enabled 0
756 02:47:48.321285 PCI: 00:12.0: enabled 1
757 02:47:48.324469 PCI: 00:12.5: enabled 0
758 02:47:48.328229 PCI: 00:12.6: enabled 0
759 02:47:48.328320 PCI: 00:14.0: enabled 1
760 02:47:48.331542
761 02:47:48.331635 USB0 port 0: enabled 1
762 02:47:48.334777 USB2 port 0: enabled 1
763 02:47:48.337818 USB2 port 1: enabled 1
764 02:47:48.341320 USB2 port 2: enabled 0
765 02:47:48.344486 USB2 port 3: enabled 0
766 02:47:48.344584 USB2 port 5: enabled 0
767 02:47:48.347750 USB2 port 6: enabled 1
768 02:47:48.351638 USB2 port 9: enabled 1
769 02:47:48.354621 USB3 port 0: enabled 1
770 02:47:48.357835 USB3 port 1: enabled 1
771 02:47:48.361170 USB3 port 2: enabled 1
772 02:47:48.361271 USB3 port 3: enabled 1
773 02:47:48.364265 USB3 port 4: enabled 0
774 02:47:48.367552 PCI: 00:14.1: enabled 0
775 02:47:48.370730 PCI: 00:14.3: enabled 1
776 02:47:48.374591 PCI: 00:14.5: enabled 0
777 02:47:48.374695 PCI: 00:15.0: enabled 1
778 02:47:48.377298 I2C: 00:15: enabled 1
779 02:47:48.381112 PCI: 00:15.1: enabled 1
780 02:47:48.384333 I2C: 00:5d: enabled 1
781 02:47:48.384436 GENERIC: 0.0: enabled 1
782 02:47:48.387485
783 02:47:48.387592 PCI: 00:15.2: enabled 0
784 02:47:48.390560 PCI: 00:15.3: enabled 0
785 02:47:48.394420 PCI: 00:16.0: enabled 1
786 02:47:48.397690 PCI: 00:16.1: enabled 0
787 02:47:48.397792 PCI: 00:16.2: enabled 0
788 02:47:48.400737 PCI: 00:16.3: enabled 0
789 02:47:48.403941 PCI: 00:16.4: enabled 0
790 02:47:48.407064 PCI: 00:16.5: enabled 0
791 02:47:48.410350 PCI: 00:17.0: enabled 1
792 02:47:48.410450 PCI: 00:19.0: enabled 1
793 02:47:48.414303 I2C: 00:1a: enabled 1
794 02:47:48.417466 I2C: 00:38: enabled 1
795 02:47:48.420555 I2C: 00:39: enabled 1
796 02:47:48.420656 I2C: 00:3a: enabled 1
797 02:47:48.423840
798 02:47:48.423947 I2C: 00:3b: enabled 1
799 02:47:48.426945 PCI: 00:19.1: enabled 0
800 02:47:48.430833 PCI: 00:19.2: enabled 0
801 02:47:48.433946 PCI: 00:1a.0: enabled 0
802 02:47:48.434045 PCI: 00:1c.0: enabled 0
803 02:47:48.437152 PCI: 00:1c.1: enabled 0
804 02:47:48.440387 PCI: 00:1c.2: enabled 0
805 02:47:48.443507 PCI: 00:1c.3: enabled 0
806 02:47:48.446830 PCI: 00:1c.4: enabled 0
807 02:47:48.446932 PCI: 00:1c.5: enabled 0
808 02:47:48.450512 PCI: 00:1c.6: enabled 0
809 02:47:48.453851 PCI: 00:1c.7: enabled 0
810 02:47:48.456880 PCI: 00:1d.0: enabled 1
811 02:47:48.460109 PCI: 00:1d.1: enabled 0
812 02:47:48.460208 PCI: 00:1d.2: enabled 0
813 02:47:48.463264 PCI: 00:1d.3: enabled 0
814 02:47:48.467022 PCI: 00:1d.4: enabled 0
815 02:47:48.470382 PCI: 00:1d.5: enabled 1
816 02:47:48.473653 PCI: 00:00.0: enabled 1
817 02:47:48.473750 PCI: 00:1e.0: enabled 1
818 02:47:48.476772 PCI: 00:1e.1: enabled 0
819 02:47:48.479982 PCI: 00:1e.2: enabled 1
820 02:47:48.483282 SPI: 00: enabled 1
821 02:47:48.483378 PCI: 00:1e.3: enabled 1
822 02:47:48.486515 SPI: 01: enabled 1
823 02:47:48.490376 PCI: 00:1f.0: enabled 1
824 02:47:48.493779 PNP: 0c09.0: enabled 1
825 02:47:48.493893 PCI: 00:1f.1: enabled 1
826 02:47:48.496970 PCI: 00:1f.2: enabled 1
827 02:47:48.500196 PCI: 00:1f.3: enabled 1
828 02:47:48.503371 PCI: 00:1f.4: enabled 1
829 02:47:48.506503 PCI: 00:1f.5: enabled 1
830 02:47:48.506640 PCI: 00:1f.6: enabled 0
831 02:47:48.510005 Root Device scanning...
832 02:47:48.513704 scan_static_bus for Root Device
833 02:47:48.516353 CPU_CLUSTER: 0 enabled
834 02:47:48.519609 DOMAIN: 0000 enabled
835 02:47:48.519810 DOMAIN: 0000 scanning...
836 02:47:48.523694 PCI: pci_scan_bus for bus 00
837 02:47:48.526695 PCI: 00:00.0 [8086/0000] ops
838 02:47:48.530020 PCI: 00:00.0 [8086/9b61] enabled
839 02:47:48.533225 PCI: 00:02.0 [8086/0000] bus ops
840 02:47:48.537202 PCI: 00:02.0 [8086/9b41] enabled
841 02:47:48.540220 PCI: 00:04.0 [8086/1903] disabled
842 02:47:48.543533 PCI: 00:08.0 [8086/1911] enabled
843 02:47:48.546901 PCI: 00:12.0 [8086/02f9] enabled
844 02:47:48.549829 PCI: 00:14.0 [8086/0000] bus ops
845 02:47:48.553528 PCI: 00:14.0 [8086/02ed] enabled
846 02:47:48.556763 PCI: 00:14.2 [8086/02ef] enabled
847 02:47:48.559904 PCI: 00:14.3 [8086/02f0] enabled
848 02:47:48.563653 PCI: 00:15.0 [8086/0000] bus ops
849 02:47:48.566455 PCI: 00:15.0 [8086/02e8] enabled
850 02:47:48.569687 PCI: 00:15.1 [8086/0000] bus ops
851 02:47:48.573426 PCI: 00:15.1 [8086/02e9] enabled
852 02:47:48.576480 PCI: 00:16.0 [8086/0000] ops
853 02:47:48.579879 PCI: 00:16.0 [8086/02e0] enabled
854 02:47:48.582987 PCI: 00:17.0 [8086/0000] ops
855 02:47:48.586737 PCI: 00:17.0 [8086/02d3] enabled
856 02:47:48.590068 PCI: 00:19.0 [8086/0000] bus ops
857 02:47:48.593228 PCI: 00:19.0 [8086/02c5] enabled
858 02:47:48.596322 PCI: 00:1d.0 [8086/0000] bus ops
859 02:47:48.599707 PCI: 00:1d.0 [8086/02b0] enabled
860 02:47:48.605887 PCI: Static device PCI: 00:1d.5 not found, disabling it.
861 02:47:48.609934 PCI: 00:1e.0 [8086/0000] ops
862 02:47:48.613006 PCI: 00:1e.0 [8086/02a8] enabled
863 02:47:48.616388 PCI: 00:1e.2 [8086/0000] bus ops
864 02:47:48.619387 PCI: 00:1e.2 [8086/02aa] enabled
865 02:47:48.622697 PCI: 00:1e.3 [8086/0000] bus ops
866 02:47:48.625953 PCI: 00:1e.3 [8086/02ab] enabled
867 02:47:48.629252 PCI: 00:1f.0 [8086/0000] bus ops
868 02:47:48.632961 PCI: 00:1f.0 [8086/0284] enabled
869 02:47:48.636230 PCI: Static device PCI: 00:1f.1 not found, disabling it.
870 02:47:48.642807 PCI: Static device PCI: 00:1f.2 not found, disabling it.
871 02:47:48.646171 PCI: 00:1f.3 [8086/0000] bus ops
872 02:47:48.649449 PCI: 00:1f.3 [8086/02c8] enabled
873 02:47:48.652364 PCI: 00:1f.4 [8086/0000] bus ops
874 02:47:48.656321 PCI: 00:1f.4 [8086/02a3] enabled
875 02:47:48.659436 PCI: 00:1f.5 [8086/0000] bus ops
876 02:47:48.662612 PCI: 00:1f.5 [8086/02a4] enabled
877 02:47:48.665983 PCI: Leftover static devices:
878 02:47:48.669129 PCI: 00:05.0
879 02:47:48.669602 PCI: 00:12.5
880 02:47:48.669962 PCI: 00:12.6
881 02:47:48.672581 PCI: 00:14.1
882 02:47:48.673027 PCI: 00:14.5
883 02:47:48.675896 PCI: 00:15.2
884 02:47:48.676380 PCI: 00:15.3
885 02:47:48.676734 PCI: 00:16.1
886 02:47:48.678911 PCI: 00:16.2
887 02:47:48.679279 PCI: 00:16.3
888 02:47:48.682850 PCI: 00:16.4
889 02:47:48.683343 PCI: 00:16.5
890 02:47:48.683722 PCI: 00:19.1
891 02:47:48.686022 PCI: 00:19.2
892 02:47:48.686467 PCI: 00:1a.0
893 02:47:48.689183 PCI: 00:1c.0
894 02:47:48.689628 PCI: 00:1c.1
895 02:47:48.692637 PCI: 00:1c.2
896 02:47:48.693085 PCI: 00:1c.3
897 02:47:48.693434 PCI: 00:1c.4
898 02:47:48.695803 PCI: 00:1c.5
899 02:47:48.696289 PCI: 00:1c.6
900 02:47:48.698924 PCI: 00:1c.7
901 02:47:48.699368 PCI: 00:1d.1
902 02:47:48.699711 PCI: 00:1d.2
903 02:47:48.702148 PCI: 00:1d.3
904 02:47:48.702602 PCI: 00:1d.4
905 02:47:48.705273 PCI: 00:1d.5
906 02:47:48.705718 PCI: 00:1e.1
907 02:47:48.706067 PCI: 00:1f.1
908 02:47:48.708842 PCI: 00:1f.2
909 02:47:48.709284 PCI: 00:1f.6
910 02:47:48.712497 PCI: Check your devicetree.cb.
911 02:47:48.715476 PCI: 00:02.0 scanning...
912 02:47:48.718828 scan_generic_bus for PCI: 00:02.0
913 02:47:48.721933 scan_generic_bus for PCI: 00:02.0 done
914 02:47:48.729112 scan_bus: scanning of bus PCI: 00:02.0 took 10180 usecs
915 02:47:48.732336 PCI: 00:14.0 scanning...
916 02:47:48.735483 scan_static_bus for PCI: 00:14.0
917 02:47:48.735992 USB0 port 0 enabled
918 02:47:48.738661 USB0 port 0 scanning...
919 02:47:48.741693 scan_static_bus for USB0 port 0
920 02:47:48.745745 USB2 port 0 enabled
921 02:47:48.746164 USB2 port 1 enabled
922 02:47:48.748796 USB2 port 2 disabled
923 02:47:48.752189 USB2 port 3 disabled
924 02:47:48.752693 USB2 port 5 disabled
925 02:47:48.755233 USB2 port 6 enabled
926 02:47:48.758453 USB2 port 9 enabled
927 02:47:48.758943 USB3 port 0 enabled
928 02:47:48.762229 USB3 port 1 enabled
929 02:47:48.762722 USB3 port 2 enabled
930 02:47:48.765327 USB3 port 3 enabled
931 02:47:48.768419 USB3 port 4 disabled
932 02:47:48.768859 USB2 port 0 scanning...
933 02:47:48.772341 scan_static_bus for USB2 port 0
934 02:47:48.779012 scan_static_bus for USB2 port 0 done
935 02:47:48.782137 scan_bus: scanning of bus USB2 port 0 took 9696 usecs
936 02:47:48.785285 USB2 port 1 scanning...
937 02:47:48.788446 scan_static_bus for USB2 port 1
938 02:47:48.792255 scan_static_bus for USB2 port 1 done
939 02:47:48.798731 scan_bus: scanning of bus USB2 port 1 took 9748 usecs
940 02:47:48.799177 USB2 port 6 scanning...
941 02:47:48.802642 scan_static_bus for USB2 port 6
942 02:47:48.809034 scan_static_bus for USB2 port 6 done
943 02:47:48.812186 scan_bus: scanning of bus USB2 port 6 took 9694 usecs
944 02:47:48.815202 USB2 port 9 scanning...
945 02:47:48.819051 scan_static_bus for USB2 port 9
946 02:47:48.821876 scan_static_bus for USB2 port 9 done
947 02:47:48.828757 scan_bus: scanning of bus USB2 port 9 took 9685 usecs
948 02:47:48.829201 USB3 port 0 scanning...
949 02:47:48.832161 scan_static_bus for USB3 port 0
950 02:47:48.838583 scan_static_bus for USB3 port 0 done
951 02:47:48.842358 scan_bus: scanning of bus USB3 port 0 took 9702 usecs
952 02:47:48.845625 USB3 port 1 scanning...
953 02:47:48.848688 scan_static_bus for USB3 port 1
954 02:47:48.851999 scan_static_bus for USB3 port 1 done
955 02:47:48.858388 scan_bus: scanning of bus USB3 port 1 took 9703 usecs
956 02:47:48.858860 USB3 port 2 scanning...
957 02:47:48.862193 scan_static_bus for USB3 port 2
958 02:47:48.868549 scan_static_bus for USB3 port 2 done
959 02:47:48.872464 scan_bus: scanning of bus USB3 port 2 took 9694 usecs
960 02:47:48.875744 USB3 port 3 scanning...
961 02:47:48.878796 scan_static_bus for USB3 port 3
962 02:47:48.881910 scan_static_bus for USB3 port 3 done
963 02:47:48.888555 scan_bus: scanning of bus USB3 port 3 took 9702 usecs
964 02:47:48.891634 scan_static_bus for USB0 port 0 done
965 02:47:48.895472 scan_bus: scanning of bus USB0 port 0 took 155340 usecs
966 02:47:48.898649
967 02:47:48.901890 scan_static_bus for PCI: 00:14.0 done
968 02:47:48.904999 scan_bus: scanning of bus PCI: 00:14.0 took 172957 usecs
969 02:47:48.908976 PCI: 00:15.0 scanning...
970 02:47:48.912133 scan_generic_bus for PCI: 00:15.0
971 02:47:48.914915 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
972 02:47:48.921672 scan_generic_bus for PCI: 00:15.0 done
973 02:47:48.925000 scan_bus: scanning of bus PCI: 00:15.0 took 14301 usecs
974 02:47:48.928894 PCI: 00:15.1 scanning...
975 02:47:48.932010 scan_generic_bus for PCI: 00:15.1
976 02:47:48.935157 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
977 02:47:48.941662 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
978 02:47:48.944831 scan_generic_bus for PCI: 00:15.1 done
979 02:47:48.951853 scan_bus: scanning of bus PCI: 00:15.1 took 18606 usecs
980 02:47:48.952397 PCI: 00:19.0 scanning...
981 02:47:48.955107 scan_generic_bus for PCI: 00:19.0
982 02:47:48.961526 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
983 02:47:48.964873 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
984 02:47:48.968084 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
985 02:47:48.971340 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
986 02:47:48.977867 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
987 02:47:48.981658 scan_generic_bus for PCI: 00:19.0 done
988 02:47:48.984887 scan_bus: scanning of bus PCI: 00:19.0 took 30727 usecs
989 02:47:48.988002 PCI: 00:1d.0 scanning...
990 02:47:48.991131 do_pci_scan_bridge for PCI: 00:1d.0
991 02:47:48.995058 PCI: pci_scan_bus for bus 01
992 02:47:48.998161 PCI: 01:00.0 [1c5c/1327] enabled
993 02:47:49.001480 Enabling Common Clock Configuration
994 02:47:49.007999 L1 Sub-State supported from root port 29
995 02:47:49.011339 L1 Sub-State Support = 0xf
996 02:47:49.011788 CommonModeRestoreTime = 0x28
997 02:47:49.018207 Power On Value = 0x16, Power On Scale = 0x0
998 02:47:49.018695 ASPM: Enabled L1
999 02:47:49.024753 scan_bus: scanning of bus PCI: 00:1d.0 took 32767 usecs
1000 02:47:49.027780 PCI: 00:1e.2 scanning...
1001 02:47:49.031095 scan_generic_bus for PCI: 00:1e.2
1002 02:47:49.034311 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1003 02:47:49.038217 scan_generic_bus for PCI: 00:1e.2 done
1004 02:47:49.044469 scan_bus: scanning of bus PCI: 00:1e.2 took 14003 usecs
1005 02:47:49.048107 PCI: 00:1e.3 scanning...
1006 02:47:49.050853 scan_generic_bus for PCI: 00:1e.3
1007 02:47:49.054657 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1008 02:47:49.057810 scan_generic_bus for PCI: 00:1e.3 done
1009 02:47:49.064207 scan_bus: scanning of bus PCI: 00:1e.3 took 13998 usecs
1010 02:47:49.064659 PCI: 00:1f.0 scanning...
1011 02:47:49.068075 scan_static_bus for PCI: 00:1f.0
1012 02:47:49.071331 PNP: 0c09.0 enabled
1013 02:47:49.074414 scan_static_bus for PCI: 00:1f.0 done
1014 02:47:49.080930 scan_bus: scanning of bus PCI: 00:1f.0 took 12041 usecs
1015 02:47:49.084851 PCI: 00:1f.3 scanning...
1016 02:47:49.087973 scan_bus: scanning of bus PCI: 00:1f.3 took 2859 usecs
1017 02:47:49.091118 PCI: 00:1f.4 scanning...
1018 02:47:49.094289 scan_generic_bus for PCI: 00:1f.4
1019 02:47:49.098066 scan_generic_bus for PCI: 00:1f.4 done
1020 02:47:49.104037 scan_bus: scanning of bus PCI: 00:1f.4 took 10175 usecs
1021 02:47:49.107999 PCI: 00:1f.5 scanning...
1022 02:47:49.110939 scan_generic_bus for PCI: 00:1f.5
1023 02:47:49.114154 scan_generic_bus for PCI: 00:1f.5 done
1024 02:47:49.120694 scan_bus: scanning of bus PCI: 00:1f.5 took 10190 usecs
1025 02:47:49.127746 scan_bus: scanning of bus DOMAIN: 0000 took 604899 usecs
1026 02:47:49.130965 scan_static_bus for Root Device done
1027 02:47:49.134175 scan_bus: scanning of bus Root Device took 624768 usecs
1028 02:47:49.137348 done
1029 02:47:49.140795 Chrome EC: UHEPI supported
1030 02:47:49.144639 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1031 02:47:49.150331 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1032 02:47:49.156946 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1033 02:47:49.164086 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1034 02:47:49.167375 SPI flash protection: WPSW=0 SRP0=0
1035 02:47:49.173718 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1036 02:47:49.177622 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1037 02:47:49.180837 found VGA at PCI: 00:02.0
1038 02:47:49.183855 Setting up VGA for PCI: 00:02.0
1039 02:47:49.190544 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1040 02:47:49.193654 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1041 02:47:49.196893 Allocating resources...
1042 02:47:49.200725 Reading resources...
1043 02:47:49.204093 Root Device read_resources bus 0 link: 0
1044 02:47:49.207259 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1045 02:47:49.213448 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1046 02:47:49.216965 DOMAIN: 0000 read_resources bus 0 link: 0
1047 02:47:49.223979 PCI: 00:14.0 read_resources bus 0 link: 0
1048 02:47:49.227893 USB0 port 0 read_resources bus 0 link: 0
1049 02:47:49.235789 USB0 port 0 read_resources bus 0 link: 0 done
1050 02:47:49.238773 PCI: 00:14.0 read_resources bus 0 link: 0 done
1051 02:47:49.246023 PCI: 00:15.0 read_resources bus 1 link: 0
1052 02:47:49.248904 PCI: 00:15.0 read_resources bus 1 link: 0 done
1053 02:47:49.255851 PCI: 00:15.1 read_resources bus 2 link: 0
1054 02:47:49.259224 PCI: 00:15.1 read_resources bus 2 link: 0 done
1055 02:47:49.266567 PCI: 00:19.0 read_resources bus 3 link: 0
1056 02:47:49.273119 PCI: 00:19.0 read_resources bus 3 link: 0 done
1057 02:47:49.276342 PCI: 00:1d.0 read_resources bus 1 link: 0
1058 02:47:49.282845 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1059 02:47:49.286685 PCI: 00:1e.2 read_resources bus 4 link: 0
1060 02:47:49.293120 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1061 02:47:49.296339 PCI: 00:1e.3 read_resources bus 5 link: 0
1062 02:47:49.302680 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1063 02:47:49.305983 PCI: 00:1f.0 read_resources bus 0 link: 0
1064 02:47:49.312531 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1065 02:47:49.319757 DOMAIN: 0000 read_resources bus 0 link: 0 done
1066 02:47:49.322907 Root Device read_resources bus 0 link: 0 done
1067 02:47:49.326127 Done reading resources.
1068 02:47:49.332704 Show resources in subtree (Root Device)...After reading.
1069 02:47:49.335920 Root Device child on link 0 CPU_CLUSTER: 0
1070 02:47:49.339125 CPU_CLUSTER: 0 child on link 0 APIC: 00
1071 02:47:49.339222 APIC: 00
1072 02:47:49.342300
1073 02:47:49.342397 APIC: 03
1074 02:47:49.342472 APIC: 04
1075 02:47:49.346098 APIC: 01
1076 02:47:49.346227 APIC: 02
1077 02:47:49.346308 APIC: 05
1078 02:47:49.349386 APIC: 07
1079 02:47:49.349483 APIC: 06
1080 02:47:49.352378 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1081 02:47:49.355651
1082 02:47:49.362281 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1083 02:47:49.412260 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1084 02:47:49.412373 PCI: 00:00.0
1085 02:47:49.412650 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1086 02:47:49.412732 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1087 02:47:49.413665 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1088 02:47:49.413947 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1089 02:47:49.462704 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1090 02:47:49.463350 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1091 02:47:49.464654 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1092 02:47:49.464952 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1093 02:47:49.465035 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1094 02:47:49.492711 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1095 02:47:49.493571 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1096 02:47:49.493847 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1097 02:47:49.497429 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1098 02:47:49.506802 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1099 02:47:49.517107 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1100 02:47:49.523460 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1101 02:47:49.526546 PCI: 00:02.0
1102 02:47:49.536861 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1103 02:47:49.546585 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1104 02:47:49.556214 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1105 02:47:49.556314 PCI: 00:04.0
1106 02:47:49.560187 PCI: 00:08.0
1107 02:47:49.569785 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1108 02:47:49.569881 PCI: 00:12.0
1109 02:47:49.579867 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1110 02:47:49.583275 PCI: 00:14.0 child on link 0 USB0 port 0
1111 02:47:49.596004 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1112 02:47:49.599432 USB0 port 0 child on link 0 USB2 port 0
1113 02:47:49.599617 USB2 port 0
1114 02:47:49.602616 USB2 port 1
1115 02:47:49.602809 USB2 port 2
1116 02:47:49.605772 USB2 port 3
1117 02:47:49.605950 USB2 port 5
1118 02:47:49.609080
1119 02:47:49.609309 USB2 port 6
1120 02:47:49.612822 USB2 port 9
1121 02:47:49.613079 USB3 port 0
1122 02:47:49.616147 USB3 port 1
1123 02:47:49.616407 USB3 port 2
1124 02:47:49.619455 USB3 port 3
1125 02:47:49.619780 USB3 port 4
1126 02:47:49.622915 PCI: 00:14.2
1127 02:47:49.632363 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1128 02:47:49.642667 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1129 02:47:49.642767 PCI: 00:14.3
1130 02:47:49.652420 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1131 02:47:49.655849 PCI: 00:15.0 child on link 0 I2C: 01:15
1132 02:47:49.658996
1133 02:47:49.665253 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1134 02:47:49.668740
1135 02:47:49.668839 I2C: 01:15
1136 02:47:49.671988 PCI: 00:15.1 child on link 0 I2C: 02:5d
1137 02:47:49.682016 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1138 02:47:49.685200 I2C: 02:5d
1139 02:47:49.685307 GENERIC: 0.0
1140 02:47:49.688531 PCI: 00:16.0
1141 02:47:49.698507 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1142 02:47:49.698612 PCI: 00:17.0
1143 02:47:49.708616 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1144 02:47:49.718670 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1145 02:47:49.725154 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1146 02:47:49.734984 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1147 02:47:49.741392 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1148 02:47:49.751518 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1149 02:47:49.754878 PCI: 00:19.0 child on link 0 I2C: 03:1a
1150 02:47:49.764560 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1151 02:47:49.767828 I2C: 03:1a
1152 02:47:49.767926 I2C: 03:38
1153 02:47:49.771101 I2C: 03:39
1154 02:47:49.771199 I2C: 03:3a
1155 02:47:49.774240 I2C: 03:3b
1156 02:47:49.777518 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1157 02:47:49.787856 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1158 02:47:49.797311 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1159 02:47:49.803972 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1160 02:47:49.807260 PCI: 01:00.0
1161 02:47:49.817104 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1162 02:47:49.817204 PCI: 00:1e.0
1163 02:47:49.820180
1164 02:47:49.830066 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1165 02:47:49.839970 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1166 02:47:49.843134 PCI: 00:1e.2 child on link 0 SPI: 00
1167 02:47:49.853346 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1168 02:47:49.853450 SPI: 00
1169 02:47:49.860006 PCI: 00:1e.3 child on link 0 SPI: 01
1170 02:47:49.869650 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1171 02:47:49.869757 SPI: 01
1172 02:47:49.873451 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1173 02:47:49.882934 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1174 02:47:49.893262 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1175 02:47:49.893363 PNP: 0c09.0
1176 02:47:49.903180 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1177 02:47:49.903278 PCI: 00:1f.3
1178 02:47:49.912809 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1179 02:47:49.923016 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1180 02:47:49.926262 PCI: 00:1f.4
1181 02:47:49.935984 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1182 02:47:49.945800 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1183 02:47:49.945901 PCI: 00:1f.5
1184 02:47:49.955594 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1185 02:47:49.962569 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1186 02:47:49.969141 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1187 02:47:49.975646 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1188 02:47:49.978971 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1189 02:47:49.982013 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1190 02:47:49.985721 PCI: 00:17.0 18 * [0x60 - 0x67] io
1191 02:47:49.988978 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1192 02:47:49.995218 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1193 02:47:50.002516 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1194 02:47:50.011906 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1195 02:47:50.018567 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1196 02:47:50.024888 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1197 02:47:50.028671 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1198 02:47:50.038359 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1199 02:47:50.042126 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1200 02:47:50.048668 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1201 02:47:50.051774 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1202 02:47:50.058676 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1203 02:47:50.061691 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1204 02:47:50.064860 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1205 02:47:50.071708 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1206 02:47:50.074854 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1207 02:47:50.081892 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1208 02:47:50.085130 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1209 02:47:50.091748 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1210 02:47:50.094935 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1211 02:47:50.101346 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1212 02:47:50.105741 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1213 02:47:50.111690 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1214 02:47:50.114836 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1215 02:47:50.121395 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1216 02:47:50.124681 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1217 02:47:50.131687 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1218 02:47:50.135081 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1219 02:47:50.141131 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1220 02:47:50.144481 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1221 02:47:50.147797 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1222 02:47:50.157767 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1223 02:47:50.161254 avoid_fixed_resources: DOMAIN: 0000
1224 02:47:50.167545 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1225 02:47:50.174598 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1226 02:47:50.180996 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1227 02:47:50.187508 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1228 02:47:50.197587 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1229 02:47:50.204145 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1230 02:47:50.210568 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1231 02:47:50.220895 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1232 02:47:50.227612 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1233 02:47:50.233971 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1234 02:47:50.240038 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1235 02:47:50.249845 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1236 02:47:50.249949 Setting resources...
1237 02:47:50.257101 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1238 02:47:50.260027 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1239 02:47:50.266466 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1240 02:47:50.269743 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1241 02:47:50.273449 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1242 02:47:50.279869 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1243 02:47:50.286342 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1244 02:47:50.293022 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1245 02:47:50.299529 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1246 02:47:50.306651 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1247 02:47:50.309787 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1248 02:47:50.316250 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1249 02:47:50.319589 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1250 02:47:50.322792 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1251 02:47:50.329482 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1252 02:47:50.332526 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1253 02:47:50.339518 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1254 02:47:50.342908 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1255 02:47:50.349237 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1256 02:47:50.352663 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1257 02:47:50.359549 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1258 02:47:50.362841 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1259 02:47:50.369362 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1260 02:47:50.372438 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1261 02:47:50.379049 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1262 02:47:50.382126 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1263 02:47:50.389621 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1264 02:47:50.392477 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1265 02:47:50.395537 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1266 02:47:50.398859
1267 02:47:50.402553 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1268 02:47:50.405883 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1269 02:47:50.412255 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1270 02:47:50.418596 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1271 02:47:50.425631 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1272 02:47:50.435235 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1273 02:47:50.441704 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1274 02:47:50.445509 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1275 02:47:50.455410 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1276 02:47:50.458407 Root Device assign_resources, bus 0 link: 0
1277 02:47:50.461714 DOMAIN: 0000 assign_resources, bus 0 link: 0
1278 02:47:50.471746 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1279 02:47:50.478220 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1280 02:47:50.488036 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1281 02:47:50.494789 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1282 02:47:50.505060 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1283 02:47:50.511384 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1284 02:47:50.518120 PCI: 00:14.0 assign_resources, bus 0 link: 0
1285 02:47:50.521196 PCI: 00:14.0 assign_resources, bus 0 link: 0
1286 02:47:50.531494 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1287 02:47:50.538150 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1288 02:47:50.544560 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1289 02:47:50.547923
1290 02:47:50.554402 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1291 02:47:50.557778 PCI: 00:15.0 assign_resources, bus 1 link: 0
1292 02:47:50.564691 PCI: 00:15.0 assign_resources, bus 1 link: 0
1293 02:47:50.571288 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1294 02:47:50.577490 PCI: 00:15.1 assign_resources, bus 2 link: 0
1295 02:47:50.580784 PCI: 00:15.1 assign_resources, bus 2 link: 0
1296 02:47:50.591287 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1297 02:47:50.597565 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1298 02:47:50.603816 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1299 02:47:50.614148 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1300 02:47:50.620711 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1301 02:47:50.627233 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1302 02:47:50.636979 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1303 02:47:50.643981 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1304 02:47:50.650442 PCI: 00:19.0 assign_resources, bus 3 link: 0
1305 02:47:50.653561 PCI: 00:19.0 assign_resources, bus 3 link: 0
1306 02:47:50.663467 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1307 02:47:50.670076 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1308 02:47:50.680312 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1309 02:47:50.683472 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1310 02:47:50.693548 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1311 02:47:50.696349 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1312 02:47:50.706155 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1313 02:47:50.713309 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1314 02:47:50.719535 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1315 02:47:50.722951 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1316 02:47:50.732592 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1317 02:47:50.735935 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1318 02:47:50.739090 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1319 02:47:50.746113 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1320 02:47:50.749283 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1321 02:47:50.755805 LPC: Trying to open IO window from 800 size 1ff
1322 02:47:50.762787 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1323 02:47:50.772317 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1324 02:47:50.778699 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1325 02:47:50.789051 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1326 02:47:50.792190 DOMAIN: 0000 assign_resources, bus 0 link: 0
1327 02:47:50.798751 Root Device assign_resources, bus 0 link: 0
1328 02:47:50.798844 Done setting resources.
1329 02:47:50.805572 Show resources in subtree (Root Device)...After assigning values.
1330 02:47:50.811866 Root Device child on link 0 CPU_CLUSTER: 0
1331 02:47:50.815628 CPU_CLUSTER: 0 child on link 0 APIC: 00
1332 02:47:50.815724 APIC: 00
1333 02:47:50.818512 APIC: 03
1334 02:47:50.818621 APIC: 04
1335 02:47:50.818697 APIC: 01
1336 02:47:50.822167 APIC: 02
1337 02:47:50.822267 APIC: 05
1338 02:47:50.825373 APIC: 07
1339 02:47:50.825472 APIC: 06
1340 02:47:50.828779 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1341 02:47:50.838455 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1342 02:47:50.851861 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1343 02:47:50.851962 PCI: 00:00.0
1344 02:47:50.861641 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1345 02:47:50.871453 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1346 02:47:50.881861 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1347 02:47:50.888145 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1348 02:47:50.897739 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1349 02:47:50.907736 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1350 02:47:50.917969 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1351 02:47:50.927998 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1352 02:47:50.937590 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1353 02:47:50.944460 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1354 02:47:50.954079 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1355 02:47:50.964226 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1356 02:47:50.973801 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1357 02:47:50.984080 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1358 02:47:50.993998 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1359 02:47:51.000397 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1360 02:47:51.003757
1361 02:47:51.003853 PCI: 00:02.0
1362 02:47:51.013631 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1363 02:47:51.023220 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1364 02:47:51.033528 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1365 02:47:51.036672 PCI: 00:04.0
1366 02:47:51.036759 PCI: 00:08.0
1367 02:47:51.046346 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1368 02:47:51.049532 PCI: 00:12.0
1369 02:47:51.059672 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1370 02:47:51.063490 PCI: 00:14.0 child on link 0 USB0 port 0
1371 02:47:51.072813 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1372 02:47:51.079564 USB0 port 0 child on link 0 USB2 port 0
1373 02:47:51.079668 USB2 port 0
1374 02:47:51.082800 USB2 port 1
1375 02:47:51.082887 USB2 port 2
1376 02:47:51.086520 USB2 port 3
1377 02:47:51.086606 USB2 port 5
1378 02:47:51.089694 USB2 port 6
1379 02:47:51.089780 USB2 port 9
1380 02:47:51.092936 USB3 port 0
1381 02:47:51.096057 USB3 port 1
1382 02:47:51.096143 USB3 port 2
1383 02:47:51.099478 USB3 port 3
1384 02:47:51.099563 USB3 port 4
1385 02:47:51.102537 PCI: 00:14.2
1386 02:47:51.112818 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1387 02:47:51.122438 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1388 02:47:51.122531 PCI: 00:14.3
1389 02:47:51.132560 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1390 02:47:51.139359 PCI: 00:15.0 child on link 0 I2C: 01:15
1391 02:47:51.148862 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1392 02:47:51.148954 I2C: 01:15
1393 02:47:51.155723 PCI: 00:15.1 child on link 0 I2C: 02:5d
1394 02:47:51.165254 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1395 02:47:51.165349 I2C: 02:5d
1396 02:47:51.168955 GENERIC: 0.0
1397 02:47:51.169046 PCI: 00:16.0
1398 02:47:51.178949 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1399 02:47:51.182238 PCI: 00:17.0
1400 02:47:51.191646 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1401 02:47:51.201753 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1402 02:47:51.211478 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1403 02:47:51.221732 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1404 02:47:51.228696 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1405 02:47:51.238347 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1406 02:47:51.244552 PCI: 00:19.0 child on link 0 I2C: 03:1a
1407 02:47:51.254500 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1408 02:47:51.254598 I2C: 03:1a
1409 02:47:51.258389 I2C: 03:38
1410 02:47:51.258496 I2C: 03:39
1411 02:47:51.261426 I2C: 03:3a
1412 02:47:51.261524 I2C: 03:3b
1413 02:47:51.268253 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1414 02:47:51.274606 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1415 02:47:51.284662 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1416 02:47:51.297797 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1417 02:47:51.297898 PCI: 01:00.0
1418 02:47:51.307672 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1419 02:47:51.310909 PCI: 00:1e.0
1420 02:47:51.320745 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1421 02:47:51.330977 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1422 02:47:51.334539 PCI: 00:1e.2 child on link 0 SPI: 00
1423 02:47:51.347045 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1424 02:47:51.347144 SPI: 00
1425 02:47:51.351032 PCI: 00:1e.3 child on link 0 SPI: 01
1426 02:47:51.360420 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1427 02:47:51.363702 SPI: 01
1428 02:47:51.366891 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1429 02:47:51.376884 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1430 02:47:51.383653 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1431 02:47:51.386919 PNP: 0c09.0
1432 02:47:51.393619 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1433 02:47:51.396950 PCI: 00:1f.3
1434 02:47:51.406882 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1435 02:47:51.416719 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1436 02:47:51.419772 PCI: 00:1f.4
1437 02:47:51.426708 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1438 02:47:51.429758
1439 02:47:51.439827 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1440 02:47:51.439931 PCI: 00:1f.5
1441 02:47:51.449697 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1442 02:47:51.452934 Done allocating resources.
1443 02:47:51.459733 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1444 02:47:51.459832 Enabling resources...
1445 02:47:51.462939
1446 02:47:51.466059 PCI: 00:00.0 subsystem <- 8086/9b61
1447 02:47:51.469790 PCI: 00:00.0 cmd <- 06
1448 02:47:51.472821 PCI: 00:02.0 subsystem <- 8086/9b41
1449 02:47:51.472919 PCI: 00:02.0 cmd <- 03
1450 02:47:51.475984
1451 02:47:51.476089 PCI: 00:08.0 cmd <- 06
1452 02:47:51.479191 PCI: 00:12.0 subsystem <- 8086/02f9
1453 02:47:51.482876
1454 02:47:51.482972 PCI: 00:12.0 cmd <- 02
1455 02:47:51.485977 PCI: 00:14.0 subsystem <- 8086/02ed
1456 02:47:51.489368 PCI: 00:14.0 cmd <- 02
1457 02:47:51.492351 PCI: 00:14.2 cmd <- 02
1458 02:47:51.496045 PCI: 00:14.3 subsystem <- 8086/02f0
1459 02:47:51.499157 PCI: 00:14.3 cmd <- 02
1460 02:47:51.502320 PCI: 00:15.0 subsystem <- 8086/02e8
1461 02:47:51.505621 PCI: 00:15.0 cmd <- 02
1462 02:47:51.508783 PCI: 00:15.1 subsystem <- 8086/02e9
1463 02:47:51.512554 PCI: 00:15.1 cmd <- 02
1464 02:47:51.515652 PCI: 00:16.0 subsystem <- 8086/02e0
1465 02:47:51.518647 PCI: 00:16.0 cmd <- 02
1466 02:47:51.521772 PCI: 00:17.0 subsystem <- 8086/02d3
1467 02:47:51.521869 PCI: 00:17.0 cmd <- 03
1468 02:47:51.528795 PCI: 00:19.0 subsystem <- 8086/02c5
1469 02:47:51.528892 PCI: 00:19.0 cmd <- 02
1470 02:47:51.532025 PCI: 00:1d.0 bridge ctrl <- 0013
1471 02:47:51.535216 PCI: 00:1d.0 subsystem <- 8086/02b0
1472 02:47:51.538830 PCI: 00:1d.0 cmd <- 06
1473 02:47:51.542040 PCI: 00:1e.0 subsystem <- 8086/02a8
1474 02:47:51.545114 PCI: 00:1e.0 cmd <- 06
1475 02:47:51.548882 PCI: 00:1e.2 subsystem <- 8086/02aa
1476 02:47:51.552069 PCI: 00:1e.2 cmd <- 06
1477 02:47:51.555340 PCI: 00:1e.3 subsystem <- 8086/02ab
1478 02:47:51.558329 PCI: 00:1e.3 cmd <- 02
1479 02:47:51.561521 PCI: 00:1f.0 subsystem <- 8086/0284
1480 02:47:51.565076 PCI: 00:1f.0 cmd <- 407
1481 02:47:51.568372 PCI: 00:1f.3 subsystem <- 8086/02c8
1482 02:47:51.571363 PCI: 00:1f.3 cmd <- 02
1483 02:47:51.575349 PCI: 00:1f.4 subsystem <- 8086/02a3
1484 02:47:51.578590 PCI: 00:1f.4 cmd <- 03
1485 02:47:51.581744 PCI: 00:1f.5 subsystem <- 8086/02a4
1486 02:47:51.584723 PCI: 00:1f.5 cmd <- 406
1487 02:47:51.592292 PCI: 01:00.0 cmd <- 02
1488 02:47:51.597385 done.
1489 02:47:51.609137 ME: Version: 14.0.39.1367
1490 02:47:51.616200 BS: BS_DEV_ENABLE times (ms): entry 0 run 18 exit 11
1491 02:47:51.619403 Initializing devices...
1492 02:47:51.619500 Root Device init ...
1493 02:47:51.626140 Chrome EC: Set SMI mask to 0x0000000000000000
1494 02:47:51.629358 Chrome EC: clear events_b mask to 0x0000000000000000
1495 02:47:51.636143 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1496 02:47:51.642334 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1497 02:47:51.648713 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1498 02:47:51.651995 Chrome EC: Set WAKE mask to 0x0000000000000000
1499 02:47:51.655555 Root Device init finished in 35225 usecs
1500 02:47:51.659366 CPU_CLUSTER: 0 init ...
1501 02:47:51.662643 CPU_CLUSTER: 0 init finished in 2439 usecs
1502 02:47:51.665925
1503 02:47:51.670179 PCI: 00:00.0 init ...
1504 02:47:51.673315 CPU TDP: 15 Watts
1505 02:47:51.676576 CPU PL2 = 64 Watts
1506 02:47:51.679942 PCI: 00:00.0 init finished in 7081 usecs
1507 02:47:51.683055 PCI: 00:02.0 init ...
1508 02:47:51.686229 PCI: 00:02.0 init finished in 2252 usecs
1509 02:47:51.690030 PCI: 00:08.0 init ...
1510 02:47:51.692953 PCI: 00:08.0 init finished in 2254 usecs
1511 02:47:51.696790 PCI: 00:12.0 init ...
1512 02:47:51.700004 PCI: 00:12.0 init finished in 2252 usecs
1513 02:47:51.703203 PCI: 00:14.0 init ...
1514 02:47:51.706359 PCI: 00:14.0 init finished in 2254 usecs
1515 02:47:51.709469 PCI: 00:14.2 init ...
1516 02:47:51.712753 PCI: 00:14.2 init finished in 2253 usecs
1517 02:47:51.716144 PCI: 00:14.3 init ...
1518 02:47:51.719849 PCI: 00:14.3 init finished in 2272 usecs
1519 02:47:51.723020 PCI: 00:15.0 init ...
1520 02:47:51.726328 DW I2C bus 0 at 0xd121f000 (400 KHz)
1521 02:47:51.729477 PCI: 00:15.0 init finished in 5972 usecs
1522 02:47:51.732785 PCI: 00:15.1 init ...
1523 02:47:51.736513 DW I2C bus 1 at 0xd1220000 (400 KHz)
1524 02:47:51.739812 PCI: 00:15.1 init finished in 5976 usecs
1525 02:47:51.742943
1526 02:47:51.743033 PCI: 00:16.0 init ...
1527 02:47:51.749354 PCI: 00:16.0 init finished in 2253 usecs
1528 02:47:51.749442 PCI: 00:19.0 init ...
1529 02:47:51.755750 DW I2C bus 4 at 0xd1222000 (400 KHz)
1530 02:47:51.759062 PCI: 00:19.0 init finished in 5978 usecs
1531 02:47:51.762281 PCI: 00:1d.0 init ...
1532 02:47:51.766229 Initializing PCH PCIe bridge.
1533 02:47:51.769320 PCI: 00:1d.0 init finished in 5283 usecs
1534 02:47:51.772788 PCI: 00:1f.0 init ...
1535 02:47:51.775808 IOAPIC: Initializing IOAPIC at 0xfec00000
1536 02:47:51.782486 IOAPIC: Bootstrap Processor Local APIC = 0x00
1537 02:47:51.782579 IOAPIC: ID = 0x02
1538 02:47:51.785647 IOAPIC: Dumping registers
1539 02:47:51.789049 reg 0x0000: 0x02000000
1540 02:47:51.792020 reg 0x0001: 0x00770020
1541 02:47:51.792159 reg 0x0002: 0x00000000
1542 02:47:51.799097 PCI: 00:1f.0 init finished in 23545 usecs
1543 02:47:51.802240 PCI: 00:1f.4 init ...
1544 02:47:51.805362 PCI: 00:1f.4 init finished in 2263 usecs
1545 02:47:51.815925 PCI: 01:00.0 init ...
1546 02:47:51.819735 PCI: 01:00.0 init finished in 2251 usecs
1547 02:47:51.823687 PNP: 0c09.0 init ...
1548 02:47:51.826882 Google Chrome EC uptime: 11.099 seconds
1549 02:47:51.833231 Google Chrome AP resets since EC boot: 0
1550 02:47:51.837032 Google Chrome most recent AP reset causes:
1551 02:47:51.843224 Google Chrome EC reset flags at last EC boot: reset-pin
1552 02:47:51.846534 PNP: 0c09.0 init finished in 20571 usecs
1553 02:47:51.849735 Devices initialized
1554 02:47:51.853511 Show all devs... After init.
1555 02:47:51.853610 Root Device: enabled 1
1556 02:47:51.856274 CPU_CLUSTER: 0: enabled 1
1557 02:47:51.860153 DOMAIN: 0000: enabled 1
1558 02:47:51.860252 APIC: 00: enabled 1
1559 02:47:51.863291 PCI: 00:00.0: enabled 1
1560 02:47:51.866101 PCI: 00:02.0: enabled 1
1561 02:47:51.869669 PCI: 00:04.0: enabled 0
1562 02:47:51.869769 PCI: 00:05.0: enabled 0
1563 02:47:51.873031 PCI: 00:12.0: enabled 1
1564 02:47:51.876227 PCI: 00:12.5: enabled 0
1565 02:47:51.879520 PCI: 00:12.6: enabled 0
1566 02:47:51.879620 PCI: 00:14.0: enabled 1
1567 02:47:51.882850 PCI: 00:14.1: enabled 0
1568 02:47:51.886022 PCI: 00:14.3: enabled 1
1569 02:47:51.889393 PCI: 00:14.5: enabled 0
1570 02:47:51.889494 PCI: 00:15.0: enabled 1
1571 02:47:51.892644 PCI: 00:15.1: enabled 1
1572 02:47:51.896015 PCI: 00:15.2: enabled 0
1573 02:47:51.899494 PCI: 00:15.3: enabled 0
1574 02:47:51.899618 PCI: 00:16.0: enabled 1
1575 02:47:51.902561 PCI: 00:16.1: enabled 0
1576 02:47:51.905712 PCI: 00:16.2: enabled 0
1577 02:47:51.905812 PCI: 00:16.3: enabled 0
1578 02:47:51.908998 PCI: 00:16.4: enabled 0
1579 02:47:51.912304 PCI: 00:16.5: enabled 0
1580 02:47:51.915523 PCI: 00:17.0: enabled 1
1581 02:47:51.915621 PCI: 00:19.0: enabled 1
1582 02:47:51.919442 PCI: 00:19.1: enabled 0
1583 02:47:51.922551 PCI: 00:19.2: enabled 0
1584 02:47:51.925518 PCI: 00:1a.0: enabled 0
1585 02:47:51.925617 PCI: 00:1c.0: enabled 0
1586 02:47:51.929339 PCI: 00:1c.1: enabled 0
1587 02:47:51.932543 PCI: 00:1c.2: enabled 0
1588 02:47:51.935774 PCI: 00:1c.3: enabled 0
1589 02:47:51.935873 PCI: 00:1c.4: enabled 0
1590 02:47:51.938999 PCI: 00:1c.5: enabled 0
1591 02:47:51.942022 PCI: 00:1c.6: enabled 0
1592 02:47:51.942146 PCI: 00:1c.7: enabled 0
1593 02:47:51.946114
1594 02:47:51.946231 PCI: 00:1d.0: enabled 1
1595 02:47:51.948847 PCI: 00:1d.1: enabled 0
1596 02:47:51.952554 PCI: 00:1d.2: enabled 0
1597 02:47:51.952695 PCI: 00:1d.3: enabled 0
1598 02:47:51.955757 PCI: 00:1d.4: enabled 0
1599 02:47:51.958716 PCI: 00:1d.5: enabled 0
1600 02:47:51.962221 PCI: 00:1e.0: enabled 1
1601 02:47:51.962395 PCI: 00:1e.1: enabled 0
1602 02:47:51.965518 PCI: 00:1e.2: enabled 1
1603 02:47:51.968685 PCI: 00:1e.3: enabled 1
1604 02:47:51.971906 PCI: 00:1f.0: enabled 1
1605 02:47:51.972147 PCI: 00:1f.1: enabled 0
1606 02:47:51.975763 PCI: 00:1f.2: enabled 0
1607 02:47:51.978905 PCI: 00:1f.3: enabled 1
1608 02:47:51.982041 PCI: 00:1f.4: enabled 1
1609 02:47:51.982418 PCI: 00:1f.5: enabled 1
1610 02:47:51.985415 PCI: 00:1f.6: enabled 0
1611 02:47:51.988586 USB0 port 0: enabled 1
1612 02:47:51.988965 I2C: 01:15: enabled 1
1613 02:47:51.992408 I2C: 02:5d: enabled 1
1614 02:47:51.995715 GENERIC: 0.0: enabled 1
1615 02:47:51.996121 I2C: 03:1a: enabled 1
1616 02:47:51.998804
1617 02:47:51.999183 I2C: 03:38: enabled 1
1618 02:47:52.002159 I2C: 03:39: enabled 1
1619 02:47:52.005288 I2C: 03:3a: enabled 1
1620 02:47:52.005668 I2C: 03:3b: enabled 1
1621 02:47:52.008594 PCI: 00:00.0: enabled 1
1622 02:47:52.011816 SPI: 00: enabled 1
1623 02:47:52.012230 SPI: 01: enabled 1
1624 02:47:52.015597 PNP: 0c09.0: enabled 1
1625 02:47:52.018711 USB2 port 0: enabled 1
1626 02:47:52.019115 USB2 port 1: enabled 1
1627 02:47:52.021950 USB2 port 2: enabled 0
1628 02:47:52.024875 USB2 port 3: enabled 0
1629 02:47:52.025252 USB2 port 5: enabled 0
1630 02:47:52.028735 USB2 port 6: enabled 1
1631 02:47:52.032004 USB2 port 9: enabled 1
1632 02:47:52.032400 USB3 port 0: enabled 1
1633 02:47:52.035100 USB3 port 1: enabled 1
1634 02:47:52.038158 USB3 port 2: enabled 1
1635 02:47:52.041428 USB3 port 3: enabled 1
1636 02:47:52.041796 USB3 port 4: enabled 0
1637 02:47:52.045312 APIC: 03: enabled 1
1638 02:47:52.048442 APIC: 04: enabled 1
1639 02:47:52.048721 APIC: 01: enabled 1
1640 02:47:52.051713 APIC: 02: enabled 1
1641 02:47:52.051999 APIC: 05: enabled 1
1642 02:47:52.054875 APIC: 07: enabled 1
1643 02:47:52.057969 APIC: 06: enabled 1
1644 02:47:52.058246 PCI: 00:08.0: enabled 1
1645 02:47:52.061511 PCI: 00:14.2: enabled 1
1646 02:47:52.064894 PCI: 01:00.0: enabled 1
1647 02:47:52.067802 Disabling ACPI via APMC:
1648 02:47:52.071601 done.
1649 02:47:52.074782 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1650 02:47:52.077814 ELOG: NV offset 0xaf0000 size 0x4000
1651 02:47:52.085655 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1652 02:47:52.092486 ELOG: Event(17) added with size 13 at 2023-01-25 02:47:51 UTC
1653 02:47:52.098679 ELOG: Event(92) added with size 9 at 2023-01-25 02:47:51 UTC
1654 02:47:52.105120 ELOG: Event(93) added with size 9 at 2023-01-25 02:47:51 UTC
1655 02:47:52.112009 ELOG: Event(9A) added with size 9 at 2023-01-25 02:47:51 UTC
1656 02:47:52.118305 ELOG: Event(9E) added with size 10 at 2023-01-25 02:47:51 UTC
1657 02:47:52.125117 ELOG: Event(9F) added with size 14 at 2023-01-25 02:47:51 UTC
1658 02:47:52.128170 BS: BS_DEV_INIT times (ms): entry 0 run 28 exit 6
1659 02:47:52.135975 ELOG: Event(A1) added with size 10 at 2023-01-25 02:47:51 UTC
1660 02:47:52.145501 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1661 02:47:52.152314 ELOG: Event(A0) added with size 9 at 2023-01-25 02:47:51 UTC
1662 02:47:52.155507 elog_add_boot_reason: Logged dev mode boot
1663 02:47:52.158658 Finalize devices...
1664 02:47:52.158753 PCI: 00:17.0 final
1665 02:47:52.161703 Devices finalized
1666 02:47:52.165522 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1667 02:47:52.172021 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1668 02:47:52.175039 ME: HFSTS1 : 0x90000245
1669 02:47:52.178828 ME: HFSTS2 : 0x3B850126
1670 02:47:52.185379 ME: HFSTS3 : 0x00000020
1671 02:47:52.188665 ME: HFSTS4 : 0x00004800
1672 02:47:52.192017 ME: HFSTS5 : 0x00000000
1673 02:47:52.195318 ME: HFSTS6 : 0x40400006
1674 02:47:52.198519 ME: Manufacturing Mode : NO
1675 02:47:52.201878 ME: FW Partition Table : OK
1676 02:47:52.205101 ME: Bringup Loader Failure : NO
1677 02:47:52.208653 ME: Firmware Init Complete : YES
1678 02:47:52.211813 ME: Boot Options Present : NO
1679 02:47:52.215200 ME: Update In Progress : NO
1680 02:47:52.218672 ME: D0i3 Support : YES
1681 02:47:52.221724 ME: Low Power State Enabled : NO
1682 02:47:52.225091 ME: CPU Replaced : NO
1683 02:47:52.228151 ME: CPU Replacement Valid : YES
1684 02:47:52.231471 ME: Current Working State : 5
1685 02:47:52.234722 ME: Current Operation State : 1
1686 02:47:52.238282 ME: Current Operation Mode : 0
1687 02:47:52.241695 ME: Error Code : 0
1688 02:47:52.245116 ME: CPU Debug Disabled : YES
1689 02:47:52.248154 ME: TXT Support : NO
1690 02:47:52.254917 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1691 02:47:52.261329 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1692 02:47:52.261733 CBFS @ c08000 size 3f8000
1693 02:47:52.267946 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1694 02:47:52.271108 CBFS: Locating 'fallback/dsdt.aml'
1695 02:47:52.274231 CBFS: Found @ offset 10bb80 size 3fa5
1696 02:47:52.281140 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1697 02:47:52.284216 CBFS @ c08000 size 3f8000
1698 02:47:52.290820 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1699 02:47:52.291297 CBFS: Locating 'fallback/slic'
1700 02:47:52.296000 CBFS: 'fallback/slic' not found.
1701 02:47:52.302907 ACPI: Writing ACPI tables at 99b3e000.
1702 02:47:52.303371 ACPI: * FACS
1703 02:47:52.306211 ACPI: * DSDT
1704 02:47:52.309313 Ramoops buffer: 0x100000@0x99a3d000.
1705 02:47:52.313204 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1706 02:47:52.319554 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1707 02:47:52.322862 Google Chrome EC: version:
1708 02:47:52.326191 ro: helios_v2.0.2659-56403530b
1709 02:47:52.329065 rw: helios_v2.0.2849-c41de27e7d
1710 02:47:52.329408 running image: 1
1711 02:47:52.333544 ACPI: * FADT
1712 02:47:52.333990 SCI is IRQ9
1713 02:47:52.340034 ACPI: added table 1/32, length now 40
1714 02:47:52.340446 ACPI: * SSDT
1715 02:47:52.343751 Found 1 CPU(s) with 8 core(s) each.
1716 02:47:52.347058 Error: Could not locate 'wifi_sar' in VPD.
1717 02:47:52.353674 Checking CBFS for default SAR values
1718 02:47:52.356629 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1719 02:47:52.359807 CBFS @ c08000 size 3f8000
1720 02:47:52.366916 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1721 02:47:52.369611 CBFS: Locating 'wifi_sar_defaults.hex'
1722 02:47:52.372800 CBFS: Found @ offset 5fac0 size 77
1723 02:47:52.376027 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1724 02:47:52.382969 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1725 02:47:52.386089 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1726 02:47:52.393057 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1727 02:47:52.396117 failed to find key in VPD: dsm_calib_r0_0
1728 02:47:52.405780 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1729 02:47:52.408996 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1730 02:47:52.415862 failed to find key in VPD: dsm_calib_r0_1
1731 02:47:52.422756 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1732 02:47:52.429102 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1733 02:47:52.432069 failed to find key in VPD: dsm_calib_r0_2
1734 02:47:52.442158 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1735 02:47:52.445366 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1736 02:47:52.452642 failed to find key in VPD: dsm_calib_r0_3
1737 02:47:52.459005 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1738 02:47:52.465429 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1739 02:47:52.468712 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1740 02:47:52.475296 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1741 02:47:52.479248 EC returned error result code 1
1742 02:47:52.482557 EC returned error result code 1
1743 02:47:52.485690 EC returned error result code 1
1744 02:47:52.488990 PS2K: Bad resp from EC. Vivaldi disabled!
1745 02:47:52.495968 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1746 02:47:52.502323 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1747 02:47:52.506022 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1748 02:47:52.512343 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1749 02:47:52.515688 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1750 02:47:52.522383 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1751 02:47:52.528639 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1752 02:47:52.534840 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1753 02:47:52.538678 ACPI: added table 2/32, length now 44
1754 02:47:52.541705 ACPI: * MCFG
1755 02:47:52.544832 ACPI: added table 3/32, length now 48
1756 02:47:52.545027 ACPI: * TPM2
1757 02:47:52.547992 TPM2 log created at 99a2d000
1758 02:47:52.551625 ACPI: added table 4/32, length now 52
1759 02:47:52.554679 ACPI: * MADT
1760 02:47:52.554767 SCI is IRQ9
1761 02:47:52.557946 ACPI: added table 5/32, length now 56
1762 02:47:52.561101 current = 99b43ac0
1763 02:47:52.561201 ACPI: * DMAR
1764 02:47:52.567988 ACPI: added table 6/32, length now 60
1765 02:47:52.568086 ACPI: * IGD OpRegion
1766 02:47:52.571174 GMA: Found VBT in CBFS
1767 02:47:52.574346 GMA: Found valid VBT in CBFS
1768 02:47:52.577999 ACPI: added table 7/32, length now 64
1769 02:47:52.580961 ACPI: * HPET
1770 02:47:52.584060 ACPI: added table 8/32, length now 68
1771 02:47:52.584146 ACPI: done.
1772 02:47:52.587758 ACPI tables: 31744 bytes.
1773 02:47:52.591374 smbios_write_tables: 99a2c000
1774 02:47:52.594504 EC returned error result code 3
1775 02:47:52.597724 Couldn't obtain OEM name from CBI
1776 02:47:52.600964 Create SMBIOS type 17
1777 02:47:52.604694 PCI: 00:00.0 (Intel Cannonlake)
1778 02:47:52.607877 PCI: 00:14.3 (Intel WiFi)
1779 02:47:52.607978 SMBIOS tables: 939 bytes.
1780 02:47:52.614030 Writing table forward entry at 0x00000500
1781 02:47:52.617860 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1782 02:47:52.623957 Writing coreboot table at 0x99b62000
1783 02:47:52.627212 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1784 02:47:52.634085 1. 0000000000001000-000000000009ffff: RAM
1785 02:47:52.637232 2. 00000000000a0000-00000000000fffff: RESERVED
1786 02:47:52.640873 3. 0000000000100000-0000000099a2bfff: RAM
1787 02:47:52.647175 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1788 02:47:52.653970 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1789 02:47:52.657238 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1790 02:47:52.664001 7. 000000009a000000-000000009f7fffff: RESERVED
1791 02:47:52.667154 8. 00000000e0000000-00000000efffffff: RESERVED
1792 02:47:52.673360 9. 00000000fc000000-00000000fc000fff: RESERVED
1793 02:47:52.676587 10. 00000000fe000000-00000000fe00ffff: RESERVED
1794 02:47:52.683463 11. 00000000fed10000-00000000fed17fff: RESERVED
1795 02:47:52.686547 12. 00000000fed80000-00000000fed83fff: RESERVED
1796 02:47:52.693394 13. 00000000fed90000-00000000fed91fff: RESERVED
1797 02:47:52.696572 14. 00000000feda0000-00000000feda1fff: RESERVED
1798 02:47:52.699999 15. 0000000100000000-000000045e7fffff: RAM
1799 02:47:52.706379 Graphics framebuffer located at 0xc0000000
1800 02:47:52.709511 Passing 5 GPIOs to payload:
1801 02:47:52.713263 NAME | PORT | POLARITY | VALUE
1802 02:47:52.719387 write protect | undefined | high | low
1803 02:47:52.722605 lid | undefined | high | high
1804 02:47:52.729499 power | undefined | high | low
1805 02:47:52.735779 oprom | undefined | high | low
1806 02:47:52.739533 EC in RW | 0x000000cb | high | low
1807 02:47:52.739619 Board ID: 4
1808 02:47:52.742692
1809 02:47:52.745685 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1810 02:47:52.749398 CBFS @ c08000 size 3f8000
1811 02:47:52.755720 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1812 02:47:52.759319 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6264
1813 02:47:52.762416 coreboot table: 1492 bytes.
1814 02:47:52.765726 IMD ROOT 0. 99fff000 00001000
1815 02:47:52.768708 IMD SMALL 1. 99ffe000 00001000
1816 02:47:52.772459 FSP MEMORY 2. 99c4e000 003b0000
1817 02:47:52.775523 CONSOLE 3. 99c2e000 00020000
1818 02:47:52.778812 FMAP 4. 99c2d000 0000054e
1819 02:47:52.782395 TIME STAMP 5. 99c2c000 00000910
1820 02:47:52.785539 VBOOT WORK 6. 99c18000 00014000
1821 02:47:52.788591 MRC DATA 7. 99c16000 00001958
1822 02:47:52.791868 ROMSTG STCK 8. 99c15000 00001000
1823 02:47:52.795740 AFTER CAR 9. 99c0b000 0000a000
1824 02:47:52.798849 RAMSTAGE 10. 99baf000 0005c000
1825 02:47:52.801757 REFCODE 11. 99b7a000 00035000
1826 02:47:52.804973 SMM BACKUP 12. 99b6a000 00010000
1827 02:47:52.808745 COREBOOT 13. 99b62000 00008000
1828 02:47:52.811441 ACPI 14. 99b3e000 00024000
1829 02:47:52.815023 ACPI GNVS 15. 99b3d000 00001000
1830 02:47:52.818038
1831 02:47:52.818148 RAMOOPS 16. 99a3d000 00100000
1832 02:47:52.821340
1833 02:47:52.821437 TPM2 TCGLOG17. 99a2d000 00010000
1834 02:47:52.824910
1835 02:47:52.825007 SMBIOS 18. 99a2c000 00000800
1836 02:47:52.828177
1837 02:47:52.828272 IMD small region:
1838 02:47:52.831324 IMD ROOT 0. 99ffec00 00000400
1839 02:47:52.834529 FSP RUNTIME 1. 99ffebe0 00000004
1840 02:47:52.838172 EC HOSTEVENT 2. 99ffebc0 00000008
1841 02:47:52.841299 POWER STATE 3. 99ffeb80 00000040
1842 02:47:52.844524 ROMSTAGE 4. 99ffeb60 00000004
1843 02:47:52.848300 MEM INFO 5. 99ffe9a0 000001b9
1844 02:47:52.851506
1845 02:47:52.854754 VPD 6. 99ffe920 0000006c
1846 02:47:52.854850 MTRR: Physical address space:
1847 02:47:52.857952
1848 02:47:52.860863 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1849 02:47:52.867788 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1850 02:47:52.874097 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1851 02:47:52.881067 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1852 02:47:52.887435 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1853 02:47:52.894262 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1854 02:47:52.900997 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1855 02:47:52.903940 MTRR: Fixed MSR 0x250 0x0606060606060606
1856 02:47:52.907263 MTRR: Fixed MSR 0x258 0x0606060606060606
1857 02:47:52.910908 MTRR: Fixed MSR 0x259 0x0000000000000000
1858 02:47:52.917080 MTRR: Fixed MSR 0x268 0x0606060606060606
1859 02:47:52.921097 MTRR: Fixed MSR 0x269 0x0606060606060606
1860 02:47:52.924042 MTRR: Fixed MSR 0x26a 0x0606060606060606
1861 02:47:52.927100 MTRR: Fixed MSR 0x26b 0x0606060606060606
1862 02:47:52.934062 MTRR: Fixed MSR 0x26c 0x0606060606060606
1863 02:47:52.937354 MTRR: Fixed MSR 0x26d 0x0606060606060606
1864 02:47:52.940358 MTRR: Fixed MSR 0x26e 0x0606060606060606
1865 02:47:52.943959 MTRR: Fixed MSR 0x26f 0x0606060606060606
1866 02:47:52.947600 call enable_fixed_mtrr()
1867 02:47:52.950769 CPU physical address size: 39 bits
1868 02:47:52.957409 MTRR: default type WB/UC MTRR counts: 6/8.
1869 02:47:52.960553 MTRR: WB selected as default type.
1870 02:47:52.967409 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1871 02:47:52.970618 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1872 02:47:52.977315 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1873 02:47:52.983744 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1874 02:47:52.990742 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1875 02:47:52.997037 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1876 02:47:53.000018 MTRR: Fixed MSR 0x250 0x0606060606060606
1877 02:47:53.007047 MTRR: Fixed MSR 0x258 0x0606060606060606
1878 02:47:53.010205 MTRR: Fixed MSR 0x259 0x0000000000000000
1879 02:47:53.013290 MTRR: Fixed MSR 0x268 0x0606060606060606
1880 02:47:53.017034 MTRR: Fixed MSR 0x269 0x0606060606060606
1881 02:47:53.023462 MTRR: Fixed MSR 0x26a 0x0606060606060606
1882 02:47:53.026932 MTRR: Fixed MSR 0x26b 0x0606060606060606
1883 02:47:53.030033 MTRR: Fixed MSR 0x26c 0x0606060606060606
1884 02:47:53.033184 MTRR: Fixed MSR 0x26d 0x0606060606060606
1885 02:47:53.039970 MTRR: Fixed MSR 0x26e 0x0606060606060606
1886 02:47:53.043144 MTRR: Fixed MSR 0x26f 0x0606060606060606
1887 02:47:53.043242
1888 02:47:53.043320 MTRR check
1889 02:47:53.046887 Fixed MTRRs : Enabled
1890 02:47:53.049978 Variable MTRRs: Enabled
1891 02:47:53.050075
1892 02:47:53.053110 call enable_fixed_mtrr()
1893 02:47:53.056813 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1894 02:47:53.059845 CPU physical address size: 39 bits
1895 02:47:53.066042 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1896 02:47:53.069690 CBFS @ c08000 size 3f8000
1897 02:47:53.072725 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1898 02:47:53.076609
1899 02:47:53.079640 MTRR: Fixed MSR 0x250 0x0606060606060606
1900 02:47:53.082813 MTRR: Fixed MSR 0x250 0x0606060606060606
1901 02:47:53.085898 MTRR: Fixed MSR 0x258 0x0606060606060606
1902 02:47:53.089608 MTRR: Fixed MSR 0x259 0x0000000000000000
1903 02:47:53.095847 MTRR: Fixed MSR 0x268 0x0606060606060606
1904 02:47:53.098954 MTRR: Fixed MSR 0x269 0x0606060606060606
1905 02:47:53.102543 MTRR: Fixed MSR 0x26a 0x0606060606060606
1906 02:47:53.105759 MTRR: Fixed MSR 0x26b 0x0606060606060606
1907 02:47:53.112491 MTRR: Fixed MSR 0x26c 0x0606060606060606
1908 02:47:53.115560 MTRR: Fixed MSR 0x26d 0x0606060606060606
1909 02:47:53.118783 MTRR: Fixed MSR 0x26e 0x0606060606060606
1910 02:47:53.122575 MTRR: Fixed MSR 0x26f 0x0606060606060606
1911 02:47:53.128753 MTRR: Fixed MSR 0x258 0x0606060606060606
1912 02:47:53.128850 call enable_fixed_mtrr()
1913 02:47:53.132464
1914 02:47:53.135671 MTRR: Fixed MSR 0x259 0x0000000000000000
1915 02:47:53.138753 MTRR: Fixed MSR 0x268 0x0606060606060606
1916 02:47:53.141962 MTRR: Fixed MSR 0x269 0x0606060606060606
1917 02:47:53.145819 MTRR: Fixed MSR 0x26a 0x0606060606060606
1918 02:47:53.151893 MTRR: Fixed MSR 0x26b 0x0606060606060606
1919 02:47:53.155726 MTRR: Fixed MSR 0x26c 0x0606060606060606
1920 02:47:53.158841 MTRR: Fixed MSR 0x26d 0x0606060606060606
1921 02:47:53.161893 MTRR: Fixed MSR 0x26e 0x0606060606060606
1922 02:47:53.168663 MTRR: Fixed MSR 0x26f 0x0606060606060606
1923 02:47:53.171836 CPU physical address size: 39 bits
1924 02:47:53.175097 call enable_fixed_mtrr()
1925 02:47:53.178293 MTRR: Fixed MSR 0x250 0x0606060606060606
1926 02:47:53.181877 MTRR: Fixed MSR 0x258 0x0606060606060606
1927 02:47:53.185129 MTRR: Fixed MSR 0x259 0x0000000000000000
1928 02:47:53.191355 MTRR: Fixed MSR 0x268 0x0606060606060606
1929 02:47:53.194612 MTRR: Fixed MSR 0x269 0x0606060606060606
1930 02:47:53.198296 MTRR: Fixed MSR 0x26a 0x0606060606060606
1931 02:47:53.201471 MTRR: Fixed MSR 0x26b 0x0606060606060606
1932 02:47:53.208127 MTRR: Fixed MSR 0x26c 0x0606060606060606
1933 02:47:53.211400 MTRR: Fixed MSR 0x26d 0x0606060606060606
1934 02:47:53.214437 MTRR: Fixed MSR 0x26e 0x0606060606060606
1935 02:47:53.218260 MTRR: Fixed MSR 0x26f 0x0606060606060606
1936 02:47:53.225139 MTRR: Fixed MSR 0x250 0x0606060606060606
1937 02:47:53.225237 call enable_fixed_mtrr()
1938 02:47:53.231375 MTRR: Fixed MSR 0x258 0x0606060606060606
1939 02:47:53.235164 MTRR: Fixed MSR 0x259 0x0000000000000000
1940 02:47:53.238327 MTRR: Fixed MSR 0x268 0x0606060606060606
1941 02:47:53.241485 MTRR: Fixed MSR 0x269 0x0606060606060606
1942 02:47:53.244613 MTRR: Fixed MSR 0x26a 0x0606060606060606
1943 02:47:53.248437
1944 02:47:53.251372 MTRR: Fixed MSR 0x26b 0x0606060606060606
1945 02:47:53.254490 MTRR: Fixed MSR 0x26c 0x0606060606060606
1946 02:47:53.258160 MTRR: Fixed MSR 0x26d 0x0606060606060606
1947 02:47:53.261279 MTRR: Fixed MSR 0x26e 0x0606060606060606
1948 02:47:53.268033 MTRR: Fixed MSR 0x26f 0x0606060606060606
1949 02:47:53.271448 CPU physical address size: 39 bits
1950 02:47:53.274569 call enable_fixed_mtrr()
1951 02:47:53.277675 MTRR: Fixed MSR 0x250 0x0606060606060606
1952 02:47:53.281257 MTRR: Fixed MSR 0x250 0x0606060606060606
1953 02:47:53.284435 MTRR: Fixed MSR 0x258 0x0606060606060606
1954 02:47:53.290900 MTRR: Fixed MSR 0x259 0x0000000000000000
1955 02:47:53.294402 MTRR: Fixed MSR 0x268 0x0606060606060606
1956 02:47:53.297561 MTRR: Fixed MSR 0x269 0x0606060606060606
1957 02:47:53.301299 MTRR: Fixed MSR 0x26a 0x0606060606060606
1958 02:47:53.307519 MTRR: Fixed MSR 0x26b 0x0606060606060606
1959 02:47:53.310572 MTRR: Fixed MSR 0x26c 0x0606060606060606
1960 02:47:53.313886 MTRR: Fixed MSR 0x26d 0x0606060606060606
1961 02:47:53.317526 MTRR: Fixed MSR 0x26e 0x0606060606060606
1962 02:47:53.323796 MTRR: Fixed MSR 0x26f 0x0606060606060606
1963 02:47:53.327591 MTRR: Fixed MSR 0x258 0x0606060606060606
1964 02:47:53.330841 call enable_fixed_mtrr()
1965 02:47:53.333894 MTRR: Fixed MSR 0x259 0x0000000000000000
1966 02:47:53.336999 MTRR: Fixed MSR 0x268 0x0606060606060606
1967 02:47:53.340699 MTRR: Fixed MSR 0x269 0x0606060606060606
1968 02:47:53.347024 MTRR: Fixed MSR 0x26a 0x0606060606060606
1969 02:47:53.350322 MTRR: Fixed MSR 0x26b 0x0606060606060606
1970 02:47:53.354032 MTRR: Fixed MSR 0x26c 0x0606060606060606
1971 02:47:53.357036 MTRR: Fixed MSR 0x26d 0x0606060606060606
1972 02:47:53.364076 MTRR: Fixed MSR 0x26e 0x0606060606060606
1973 02:47:53.367180 MTRR: Fixed MSR 0x26f 0x0606060606060606
1974 02:47:53.370295 CPU physical address size: 39 bits
1975 02:47:53.373356 call enable_fixed_mtrr()
1976 02:47:53.377143 CPU physical address size: 39 bits
1977 02:47:53.380097 CPU physical address size: 39 bits
1978 02:47:53.383454 CBFS: Locating 'fallback/payload'
1979 02:47:53.386627 CPU physical address size: 39 bits
1980 02:47:53.389773 CBFS: Found @ offset 1c96c0 size 3f798
1981 02:47:53.396696 Checking segment from ROM address 0xffdd16f8
1982 02:47:53.399977 Checking segment from ROM address 0xffdd1714
1983 02:47:53.403203 Loading segment from ROM address 0xffdd16f8
1984 02:47:53.406353 code (compression=0)
1985 02:47:53.416267 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1986 02:47:53.422997 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1987 02:47:53.426061 it's not compressed!
1988 02:47:53.518295 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1989 02:47:53.524286 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1990 02:47:53.527987 Loading segment from ROM address 0xffdd1714
1991 02:47:53.531159 Entry Point 0x30000000
1992 02:47:53.534244 Loaded segments
1993 02:47:53.539952 Finalizing chipset.
1994 02:47:53.543055 Finalizing SMM.
1995 02:47:53.546882 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1996 02:47:53.550023 mp_park_aps done after 0 msecs.
1997 02:47:53.556771 Jumping to boot code at 30000000(99b62000)
1998 02:47:53.563368 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1999 02:47:53.563467
2000 02:47:53.563546
2001 02:47:53.563622
2002 02:47:53.566211 Starting depthcharge on Helios...
2003 02:47:53.566301
2004 02:47:53.566672 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
2005 02:47:53.566788 start: 2.2.4 bootloader-commands (timeout 00:04:40) [common]
2006 02:47:53.566884 Setting prompt string to ['hatch:']
2007 02:47:53.566980 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:40)
2008 02:47:53.576363 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2009 02:47:53.576464
2010 02:47:53.582706 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2011 02:47:53.582799
2012 02:47:53.589547 board_setup: Info: eMMC controller not present; skipping
2013 02:47:53.589635
2014 02:47:53.592807 New NVMe Controller 0x30053ac0 @ 00:1d:00
2015 02:47:53.592895
2016 02:47:53.599567 board_setup: Info: SDHCI controller not present; skipping
2017 02:47:53.599654
2018 02:47:53.605885 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2019 02:47:53.605967
2020 02:47:53.606039 Wipe memory regions:
2021 02:47:53.606108
2022 02:47:53.609568 [0x00000000001000, 0x000000000a0000)
2023 02:47:53.609648
2024 02:47:53.612747 [0x00000000100000, 0x00000030000000)
2025 02:47:53.615907
2026 02:47:53.682391 [0x00000030657430, 0x00000099a2c000)
2027 02:47:53.682518
2028 02:47:53.832297 [0x00000100000000, 0x0000045e800000)
2029 02:47:53.832457
2030 02:47:55.288738 R8152: Initializing
2031 02:47:55.289280
2032 02:47:55.291594 Version 9 (ocp_data = 6010)
2033 02:47:55.291997
2034 02:47:55.295842 R8152: Done initializing
2035 02:47:55.296337
2036 02:47:55.299553 Adding net device
2037 02:47:55.300003
2038 02:47:55.781669 R8152: Initializing
2039 02:47:55.781828
2040 02:47:55.785229 Version 6 (ocp_data = 5c30)
2041 02:47:55.785331
2042 02:47:55.788579 R8152: Done initializing
2043 02:47:55.788679
2044 02:47:55.791700 net_add_device: Attemp to include the same device
2045 02:47:55.795442
2046 02:47:55.802461 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2047 02:47:55.802560
2048 02:47:55.802638
2049 02:47:55.802712
2050 02:47:55.803000 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2052 02:47:55.903758 hatch: tftpboot 192.168.201.1 8867187/tftp-deploy-rcbrk828/kernel/bzImage 8867187/tftp-deploy-rcbrk828/kernel/cmdline 8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
2053 02:47:55.903929 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2054 02:47:55.904033 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
2055 02:47:55.908071 tftpboot 192.168.201.1 8867187/tftp-deploy-rcbrk828/kernel/bzImoy-rcbrk828/kernel/cmdline 8867187/tftp-deploy-rcbrk828/ramdisk/ramdisk.cpio.gz
2056 02:47:55.908171
2057 02:47:55.908251 Waiting for link
2058 02:47:55.908323
2059 02:47:56.109274 done.
2060 02:47:56.109797
2061 02:47:56.110159 MAC: 00:24:32:50:1a:59
2062 02:47:56.110494
2063 02:47:56.112419 Sending DHCP discover... done.
2064 02:47:56.112866
2065 02:47:56.116143 Waiting for reply... done.
2066 02:47:56.116610
2067 02:47:56.119538 Sending DHCP request... done.
2068 02:47:56.119984
2069 02:47:56.126602 Waiting for reply... done.
2070 02:47:56.127052
2071 02:47:56.127401 My ip is 192.168.201.14
2072 02:47:56.127729
2073 02:47:56.129739 The DHCP server ip is 192.168.201.1
2074 02:47:56.133509
2075 02:47:56.136755 TFTP server IP predefined by user: 192.168.201.1
2076 02:47:56.137229
2077 02:47:56.143598 Bootfile predefined by user: 8867187/tftp-deploy-rcbrk828/kernel/bzImage
2078 02:47:56.144150
2079 02:47:56.146694 Sending tftp read request... done.
2080 02:47:56.147164
2081 02:47:56.153460 Waiting for the transfer...
2082 02:47:56.153975
2083 02:47:56.755005 00000000 ################################################################
2084 02:47:56.755158
2085 02:47:57.306540 00080000 ################################################################
2086 02:47:57.306709
2087 02:47:57.832236 00100000 ################################################################
2088 02:47:57.832393
2089 02:47:58.394534 00180000 ################################################################
2090 02:47:58.394694
2091 02:47:58.933483 00200000 ################################################################
2092 02:47:58.933641
2093 02:47:59.528881 00280000 ################################################################
2094 02:47:59.529042
2095 02:48:00.097969 00300000 ################################################################
2096 02:48:00.098121
2097 02:48:00.668340 00380000 ################################################################
2098 02:48:00.668498
2099 02:48:01.272306 00400000 ################################################################
2100 02:48:01.272468
2101 02:48:01.842610 00480000 ################################################################
2102 02:48:01.842773
2103 02:48:02.430165 00500000 ################################################################
2104 02:48:02.430758
2105 02:48:03.113750 00580000 ################################################################
2106 02:48:03.113919
2107 02:48:03.694240 00600000 ################################################################
2108 02:48:03.694406
2109 02:48:04.286659 00680000 ################################################################
2110 02:48:04.286823
2111 02:48:04.549566 00700000 ############################ done.
2112 02:48:04.550111
2113 02:48:04.553368 The bootfile was 7569296 bytes long.
2114 02:48:04.553829
2115 02:48:04.556176 Sending tftp read request... done.
2116 02:48:04.556631
2117 02:48:04.559480 Waiting for the transfer...
2118 02:48:04.559940
2119 02:48:05.176896 00000000 ################################################################
2120 02:48:05.177063
2121 02:48:05.802187 00080000 ################################################################
2122 02:48:05.802733
2123 02:48:06.459220 00100000 ################################################################
2124 02:48:06.459769
2125 02:48:07.134073 00180000 ################################################################
2126 02:48:07.134644
2127 02:48:07.803906 00200000 ################################################################
2128 02:48:07.804494
2129 02:48:08.470119 00280000 ################################################################
2130 02:48:08.470711
2131 02:48:09.149055 00300000 ################################################################
2132 02:48:09.149225
2133 02:48:09.788805 00380000 ################################################################
2134 02:48:09.789367
2135 02:48:10.470455 00400000 ################################################################
2136 02:48:10.471043
2137 02:48:11.071807 00480000 ################################################################
2138 02:48:11.071977
2139 02:48:11.719443 00500000 ################################################################
2140 02:48:11.719994
2141 02:48:12.317841 00580000 ################################################################
2142 02:48:12.318000
2143 02:48:12.933547 00600000 ################################################################
2144 02:48:12.934125
2145 02:48:13.608731 00680000 ################################################################
2146 02:48:13.609292
2147 02:48:14.172642 00700000 ################################################################
2148 02:48:14.172806
2149 02:48:14.789226 00780000 ################################################################
2150 02:48:14.789760
2151 02:48:15.014176 00800000 ##################### done.
2152 02:48:15.014762
2153 02:48:15.017102 Sending tftp read request... done.
2154 02:48:15.017561
2155 02:48:15.020848 Waiting for the transfer...
2156 02:48:15.021308
2157 02:48:15.021759 00000000 # done.
2158 02:48:15.022198
2159 02:48:15.030197 Command line loaded dynamically from TFTP file: 8867187/tftp-deploy-rcbrk828/kernel/cmdline
2160 02:48:15.030669
2161 02:48:15.046555 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2162 02:48:15.047063
2163 02:48:15.053273 ec_init(0): CrosEC protocol v3 supported (256, 256)
2164 02:48:15.053741
2165 02:48:15.061386 Shutting down all USB controllers.
2166 02:48:15.061859
2167 02:48:15.062215 Removing current net device
2168 02:48:15.062579
2169 02:48:15.065159 Finalizing coreboot
2170 02:48:15.065630
2171 02:48:15.071462 Exiting depthcharge with code 4 at timestamp: 28851267
2172 02:48:15.071937
2173 02:48:15.072347
2174 02:48:15.072720 Starting kernel ...
2175 02:48:15.073053
2176 02:48:15.073377
2177 02:48:15.074626 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
2178 02:48:15.075150 start: 2.2.5 auto-login-action (timeout 00:04:19) [common]
2179 02:48:15.075545 Setting prompt string to ['Linux version [0-9]']
2180 02:48:15.075928 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2181 02:48:15.076346 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2182 02:48:15.077239
2183 02:48:15.077637
2185 02:52:34.075999 end: 2.2.5 auto-login-action (duration 00:04:19) [common]
2187 02:52:34.077054 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 259 seconds'
2189 02:52:34.077856 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2192 02:52:34.079211 end: 2 depthcharge-action (duration 00:05:00) [common]
2194 02:52:34.080320 Cleaning after the job
2195 02:52:34.080750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/ramdisk
2196 02:52:34.083507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/kernel
2197 02:52:34.085955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8867187/tftp-deploy-rcbrk828/modules
2198 02:52:34.086834 start: 5.1 power-off (timeout 00:00:30) [common]
2199 02:52:34.087603 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=off'
2200 02:52:34.142385 >> Command sent successfully.
2201 02:52:34.144982 Returned 0 in 0 seconds
2202 02:52:34.246126 end: 5.1 power-off (duration 00:00:00) [common]
2204 02:52:34.247685 start: 5.2 read-feedback (timeout 00:10:00) [common]
2205 02:52:34.248870 Listened to connection for namespace 'common' for up to 1s
2206 02:52:35.252118 Finalising connection for namespace 'common'
2207 02:52:35.252315 Disconnecting from shell: Finalise
2208 02:52:35.353101 end: 5.2 read-feedback (duration 00:00:01) [common]
2209 02:52:35.353285 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8867187
2210 02:52:35.359532 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8867187
2211 02:52:35.359707 JobError: Your job cannot terminate cleanly.