Boot log: asus-cx9400-volteer
- Kernel Warnings: 0
- Errors: 2
- Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
1 07:40:43.190590 lava-dispatcher, installed at version: 2023.10
2 07:40:43.190859 start: 0 validate
3 07:40:43.191028 Start time: 2024-01-03 07:40:43.191019+00:00 (UTC)
4 07:40:43.191190 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:40:43.191374 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 07:40:43.459847 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:40:43.460011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72-1224-ga0ac575eeff8%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:40:43.461028 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:40:43.461144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72-1224-ga0ac575eeff8%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fmodules.tar.xz exists
10 07:40:43.727747 validate duration: 0.54
12 07:40:43.728033 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 07:40:43.728143 start: 1.1 download-retry (timeout 00:10:00) [common]
14 07:40:43.728234 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 07:40:43.728363 Not decompressing ramdisk as can be used compressed.
16 07:40:43.728448 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 07:40:43.728515 saving as /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/ramdisk/rootfs.cpio.gz
18 07:40:43.728577 total size: 8418130 (8 MB)
19 07:40:43.729723 progress 0 % (0 MB)
20 07:40:43.732341 progress 5 % (0 MB)
21 07:40:43.734600 progress 10 % (0 MB)
22 07:40:43.736885 progress 15 % (1 MB)
23 07:40:43.739164 progress 20 % (1 MB)
24 07:40:43.741413 progress 25 % (2 MB)
25 07:40:43.743732 progress 30 % (2 MB)
26 07:40:43.745869 progress 35 % (2 MB)
27 07:40:43.748137 progress 40 % (3 MB)
28 07:40:43.750428 progress 45 % (3 MB)
29 07:40:43.752655 progress 50 % (4 MB)
30 07:40:43.754930 progress 55 % (4 MB)
31 07:40:43.757203 progress 60 % (4 MB)
32 07:40:43.759310 progress 65 % (5 MB)
33 07:40:43.761606 progress 70 % (5 MB)
34 07:40:43.763910 progress 75 % (6 MB)
35 07:40:43.766271 progress 80 % (6 MB)
36 07:40:43.768613 progress 85 % (6 MB)
37 07:40:43.770894 progress 90 % (7 MB)
38 07:40:43.773089 progress 95 % (7 MB)
39 07:40:43.775198 progress 100 % (8 MB)
40 07:40:43.775429 8 MB downloaded in 0.05 s (171.36 MB/s)
41 07:40:43.775583 end: 1.1.1 http-download (duration 00:00:00) [common]
43 07:40:43.775822 end: 1.1 download-retry (duration 00:00:00) [common]
44 07:40:43.775908 start: 1.2 download-retry (timeout 00:10:00) [common]
45 07:40:43.775990 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 07:40:43.776126 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72-1224-ga0ac575eeff8/x86_64/x86_64_defconfig+x86-board/gcc-10/kernel/bzImage
47 07:40:43.776199 saving as /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/kernel/bzImage
48 07:40:43.776261 total size: 8572816 (8 MB)
49 07:40:43.776320 No compression specified
50 07:40:43.777561 progress 0 % (0 MB)
51 07:40:43.780159 progress 5 % (0 MB)
52 07:40:43.782446 progress 10 % (0 MB)
53 07:40:43.784690 progress 15 % (1 MB)
54 07:40:43.786985 progress 20 % (1 MB)
55 07:40:43.789230 progress 25 % (2 MB)
56 07:40:43.791477 progress 30 % (2 MB)
57 07:40:43.793784 progress 35 % (2 MB)
58 07:40:43.796036 progress 40 % (3 MB)
59 07:40:43.798362 progress 45 % (3 MB)
60 07:40:43.800600 progress 50 % (4 MB)
61 07:40:43.803061 progress 55 % (4 MB)
62 07:40:43.805436 progress 60 % (4 MB)
63 07:40:43.807948 progress 65 % (5 MB)
64 07:40:43.810212 progress 70 % (5 MB)
65 07:40:43.812456 progress 75 % (6 MB)
66 07:40:43.814789 progress 80 % (6 MB)
67 07:40:43.817056 progress 85 % (6 MB)
68 07:40:43.819367 progress 90 % (7 MB)
69 07:40:43.821664 progress 95 % (7 MB)
70 07:40:43.823987 progress 100 % (8 MB)
71 07:40:43.824187 8 MB downloaded in 0.05 s (170.63 MB/s)
72 07:40:43.824332 end: 1.2.1 http-download (duration 00:00:00) [common]
74 07:40:43.824554 end: 1.2 download-retry (duration 00:00:00) [common]
75 07:40:43.824643 start: 1.3 download-retry (timeout 00:10:00) [common]
76 07:40:43.824729 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 07:40:43.824865 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72-1224-ga0ac575eeff8/x86_64/x86_64_defconfig+x86-board/gcc-10/modules.tar.xz
78 07:40:43.824937 saving as /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/modules/modules.tar
79 07:40:43.825005 total size: 251144 (0 MB)
80 07:40:43.825068 Using unxz to decompress xz
81 07:40:43.829409 progress 13 % (0 MB)
82 07:40:43.829878 progress 26 % (0 MB)
83 07:40:43.830125 progress 39 % (0 MB)
84 07:40:43.831729 progress 52 % (0 MB)
85 07:40:43.833684 progress 65 % (0 MB)
86 07:40:43.835548 progress 78 % (0 MB)
87 07:40:43.837293 progress 91 % (0 MB)
88 07:40:43.839255 progress 100 % (0 MB)
89 07:40:43.844878 0 MB downloaded in 0.02 s (12.06 MB/s)
90 07:40:43.845124 end: 1.3.1 http-download (duration 00:00:00) [common]
92 07:40:43.845565 end: 1.3 download-retry (duration 00:00:00) [common]
93 07:40:43.845682 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
94 07:40:43.845808 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
95 07:40:43.845903 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 07:40:43.846012 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
97 07:40:43.846251 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh
98 07:40:43.846409 makedir: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin
99 07:40:43.846532 makedir: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/tests
100 07:40:43.846684 makedir: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/results
101 07:40:43.846839 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-add-keys
102 07:40:43.847001 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-add-sources
103 07:40:43.847150 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-background-process-start
104 07:40:43.847301 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-background-process-stop
105 07:40:43.847468 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-common-functions
106 07:40:43.847613 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-echo-ipv4
107 07:40:43.847781 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-install-packages
108 07:40:43.847926 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-installed-packages
109 07:40:43.848117 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-os-build
110 07:40:43.848262 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-probe-channel
111 07:40:43.848402 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-probe-ip
112 07:40:43.848544 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-target-ip
113 07:40:43.848689 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-target-mac
114 07:40:43.848858 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-target-storage
115 07:40:43.849032 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-case
116 07:40:43.849202 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-event
117 07:40:43.849369 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-feedback
118 07:40:43.849583 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-raise
119 07:40:43.849755 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-reference
120 07:40:43.849926 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-runner
121 07:40:43.850095 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-set
122 07:40:43.850265 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-test-shell
123 07:40:43.850438 Updating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-install-packages (oe)
124 07:40:43.850635 Updating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/bin/lava-installed-packages (oe)
125 07:40:43.850797 Creating /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/environment
126 07:40:43.850941 LAVA metadata
127 07:40:43.851047 - LAVA_JOB_ID=12435165
128 07:40:43.851150 - LAVA_DISPATCHER_IP=192.168.201.1
129 07:40:43.851299 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
130 07:40:43.851398 skipped lava-vland-overlay
131 07:40:43.851515 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 07:40:43.851637 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
133 07:40:43.851737 skipped lava-multinode-overlay
134 07:40:43.851861 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 07:40:43.851984 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
136 07:40:43.852093 Loading test definitions
137 07:40:43.852235 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
138 07:40:43.852349 Using /lava-12435165 at stage 0
139 07:40:43.852795 uuid=12435165_1.4.2.3.1 testdef=None
140 07:40:43.852922 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 07:40:43.853044 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
142 07:40:43.853803 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 07:40:43.854058 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
145 07:40:43.854705 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 07:40:43.854976 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
148 07:40:43.855862 runner path: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/0/tests/0_dmesg test_uuid 12435165_1.4.2.3.1
149 07:40:43.856052 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 07:40:43.856404 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
152 07:40:43.856484 Using /lava-12435165 at stage 1
153 07:40:43.856824 uuid=12435165_1.4.2.3.5 testdef=None
154 07:40:43.856918 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 07:40:43.857016 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
156 07:40:43.857691 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 07:40:43.857941 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
159 07:40:43.858613 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 07:40:43.858876 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
162 07:40:43.859518 runner path: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/1/tests/1_bootrr test_uuid 12435165_1.4.2.3.5
163 07:40:43.859705 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 07:40:43.860069 Creating lava-test-runner.conf files
166 07:40:43.860206 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/0 for stage 0
167 07:40:43.860343 - 0_dmesg
168 07:40:43.860459 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12435165/lava-overlay-rdcwf4eh/lava-12435165/1 for stage 1
169 07:40:43.860608 - 1_bootrr
170 07:40:43.860717 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 07:40:43.860841 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
172 07:40:43.869537 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 07:40:43.869664 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
174 07:40:43.869764 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 07:40:43.869864 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 07:40:43.869965 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
177 07:40:44.135224 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 07:40:44.135618 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
179 07:40:44.135737 extracting modules file /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12435165/extract-overlay-ramdisk-n6w18nc5/ramdisk
180 07:40:44.149664 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 07:40:44.149822 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
182 07:40:44.149918 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12435165/compress-overlay-xbg201uf/overlay-1.4.2.4.tar.gz to ramdisk
183 07:40:44.149989 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12435165/compress-overlay-xbg201uf/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12435165/extract-overlay-ramdisk-n6w18nc5/ramdisk
184 07:40:44.161415 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 07:40:44.161588 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
186 07:40:44.161689 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 07:40:44.161783 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
188 07:40:44.161861 Building ramdisk /var/lib/lava/dispatcher/tmp/12435165/extract-overlay-ramdisk-n6w18nc5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12435165/extract-overlay-ramdisk-n6w18nc5/ramdisk
189 07:40:44.300022 >> 49790 blocks
190 07:40:45.181275 rename /var/lib/lava/dispatcher/tmp/12435165/extract-overlay-ramdisk-n6w18nc5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
191 07:40:45.181780 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 07:40:45.181899 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
193 07:40:45.182004 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
194 07:40:45.182101 No mkimage arch provided, not using FIT.
195 07:40:45.182193 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 07:40:45.182291 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 07:40:45.182395 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 07:40:45.182486 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
199 07:40:45.182563 No LXC device requested
200 07:40:45.182641 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 07:40:45.182728 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
202 07:40:45.182813 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 07:40:45.182889 Checking files for TFTP limit of 4294967296 bytes.
204 07:40:45.183292 end: 1 tftp-deploy (duration 00:00:01) [common]
205 07:40:45.183393 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 07:40:45.183480 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 07:40:45.183599 substitutions:
208 07:40:45.183663 - {DTB}: None
209 07:40:45.183725 - {INITRD}: 12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
210 07:40:45.183783 - {KERNEL}: 12435165/tftp-deploy-thjgx_1y/kernel/bzImage
211 07:40:45.183839 - {LAVA_MAC}: None
212 07:40:45.183893 - {PRESEED_CONFIG}: None
213 07:40:45.183946 - {PRESEED_LOCAL}: None
214 07:40:45.184000 - {RAMDISK}: 12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
215 07:40:45.184054 - {ROOT_PART}: None
216 07:40:45.184108 - {ROOT}: None
217 07:40:45.184161 - {SERVER_IP}: 192.168.201.1
218 07:40:45.184214 - {TEE}: None
219 07:40:45.184269 Parsed boot commands:
220 07:40:45.184322 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 07:40:45.184503 Parsed boot commands: tftpboot 192.168.201.1 12435165/tftp-deploy-thjgx_1y/kernel/bzImage 12435165/tftp-deploy-thjgx_1y/kernel/cmdline 12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
222 07:40:45.184588 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 07:40:45.184667 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 07:40:45.184758 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 07:40:45.184846 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 07:40:45.184914 Not connected, no need to disconnect.
227 07:40:45.184986 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 07:40:45.185066 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 07:40:45.185129 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-3'
230 07:40:45.189301 Setting prompt string to ['lava-test: # ']
231 07:40:45.189743 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 07:40:45.189852 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 07:40:45.189949 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 07:40:45.190055 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 07:40:45.190254 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=reboot'
236 07:40:50.324706 >> Command sent successfully.
237 07:40:50.327631 Returned 0 in 5 seconds
238 07:40:50.427999 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 07:40:50.428386 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 07:40:50.428510 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 07:40:50.428608 Setting prompt string to 'Starting depthcharge on Voema...'
243 07:40:50.428676 Changing prompt to 'Starting depthcharge on Voema...'
244 07:40:50.428756 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
245 07:40:50.429042 [Enter `^Ec?' for help]
246 07:40:52.029850
247 07:40:52.030012
248 07:40:52.039681 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
249 07:40:52.042978 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
250 07:40:52.049661 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
251 07:40:52.052697 CPU: AES supported, TXT NOT supported, VT supported
252 07:40:52.059330 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
253 07:40:52.062701 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
254 07:40:52.069663 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
255 07:40:52.072899 VBOOT: Loading verstage.
256 07:40:52.076083 FMAP: Found "FLASH" version 1.1 at 0x1804000.
257 07:40:52.082846 FMAP: base = 0x0 size = 0x2000000 #areas = 32
258 07:40:52.086024 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
259 07:40:52.096726 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
260 07:40:52.103018 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
261 07:40:52.103118
262 07:40:52.103198
263 07:40:52.116316 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
264 07:40:52.129955 Probing TPM: . done!
265 07:40:52.133305 TPM ready after 0 ms
266 07:40:52.137089 Connected to device vid:did:rid of 1ae0:0028:00
267 07:40:52.147773 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
268 07:40:52.154811 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
269 07:40:52.158086 Initialized TPM device CR50 revision 0
270 07:40:52.207003 tlcl_send_startup: Startup return code is 0
271 07:40:52.207122 TPM: setup succeeded
272 07:40:52.221716 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
273 07:40:52.235650 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
274 07:40:52.248706 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
275 07:40:52.258734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
276 07:40:52.262130 Chrome EC: UHEPI supported
277 07:40:52.265854 Phase 1
278 07:40:52.269116 FMAP: area GBB found @ 1805000 (458752 bytes)
279 07:40:52.279058 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
280 07:40:52.285357 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
281 07:40:52.292340 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
282 07:40:52.299037 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
283 07:40:52.302118 Recovery requested (1009000e)
284 07:40:52.305718 TPM: Extending digest for VBOOT: boot mode into PCR 0
285 07:40:52.317055 tlcl_extend: response is 0
286 07:40:52.323873 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
287 07:40:52.333481 tlcl_extend: response is 0
288 07:40:52.340620 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
289 07:40:52.346831 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
290 07:40:52.353709 BS: verstage times (exec / console): total (unknown) / 142 ms
291 07:40:52.353870
292 07:40:52.353981
293 07:40:52.367256 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
294 07:40:52.373796 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
295 07:40:52.376671 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
296 07:40:52.380096 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
297 07:40:52.386801 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
298 07:40:52.390145 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
299 07:40:52.393638 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
300 07:40:52.396771 TCO_STS: 0000 0000
301 07:40:52.400342 GEN_PMCON: d0015038 00002200
302 07:40:52.403174 GBLRST_CAUSE: 00000000 00000000
303 07:40:52.403267 HPR_CAUSE0: 00000000
304 07:40:52.406521 prev_sleep_state 5
305 07:40:52.410036 Boot Count incremented to 26238
306 07:40:52.416922 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
307 07:40:52.423554 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
308 07:40:52.430127 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
309 07:40:52.436380 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
310 07:40:52.441183 Chrome EC: UHEPI supported
311 07:40:52.447628 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
312 07:40:52.460382 Probing TPM: done!
313 07:40:52.467154 Connected to device vid:did:rid of 1ae0:0028:00
314 07:40:52.478783 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
315 07:40:52.485483 Initialized TPM device CR50 revision 0
316 07:40:52.495653 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
317 07:40:52.502345 MRC: Hash idx 0x100b comparison successful.
318 07:40:52.505739 MRC cache found, size faa8
319 07:40:52.505838 bootmode is set to: 2
320 07:40:52.508839 SPD index = 0
321 07:40:52.515661 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
322 07:40:52.519074 SPD: module type is LPDDR4X
323 07:40:52.522259 SPD: module part number is MT53E512M64D4NW-046
324 07:40:52.528804 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
325 07:40:52.532325 SPD: device width 16 bits, bus width 16 bits
326 07:40:52.538742 SPD: module size is 1024 MB (per channel)
327 07:40:52.971461 CBMEM:
328 07:40:52.974808 IMD: root @ 0x76fff000 254 entries.
329 07:40:52.978215 IMD: root @ 0x76ffec00 62 entries.
330 07:40:52.981403 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
331 07:40:52.988233 FMAP: area RW_VPD found @ f35000 (8192 bytes)
332 07:40:52.991393 External stage cache:
333 07:40:52.994637 IMD: root @ 0x7b3ff000 254 entries.
334 07:40:52.997857 IMD: root @ 0x7b3fec00 62 entries.
335 07:40:53.013281 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
336 07:40:53.019872 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
337 07:40:53.026373 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
338 07:40:53.040428 MRC: 'RECOVERY_MRC_CACHE' does not need update.
339 07:40:53.047003 cse_lite: Skip switching to RW in the recovery path
340 07:40:53.047153 8 DIMMs found
341 07:40:53.047229 SMM Memory Map
342 07:40:53.051696 SMRAM : 0x7b000000 0x800000
343 07:40:53.055401 Subregion 0: 0x7b000000 0x200000
344 07:40:53.058344 Subregion 1: 0x7b200000 0x200000
345 07:40:53.061763 Subregion 2: 0x7b400000 0x400000
346 07:40:53.065115 top_of_ram = 0x77000000
347 07:40:53.071812 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
348 07:40:53.075022 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
349 07:40:53.081799 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
350 07:40:53.085087 MTRR Range: Start=ff000000 End=0 (Size 1000000)
351 07:40:53.091779 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
352 07:40:53.098341 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
353 07:40:53.110358 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
354 07:40:53.116565 Processing 211 relocs. Offset value of 0x74c0b000
355 07:40:53.123343 BS: romstage times (exec / console): total (unknown) / 277 ms
356 07:40:53.129693
357 07:40:53.129797
358 07:40:53.139555 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
359 07:40:53.142640 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
360 07:40:53.152642 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
361 07:40:53.159636 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
362 07:40:53.165706 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
363 07:40:53.172317 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
364 07:40:53.219185 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
365 07:40:53.226288 Processing 5008 relocs. Offset value of 0x75d98000
366 07:40:53.229435 BS: postcar times (exec / console): total (unknown) / 59 ms
367 07:40:53.232666
368 07:40:53.232773
369 07:40:53.242416 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
370 07:40:53.242566 Normal boot
371 07:40:53.246470 FW_CONFIG value is 0x804c02
372 07:40:53.249957 PCI: 00:07.0 disabled by fw_config
373 07:40:53.253309 PCI: 00:07.1 disabled by fw_config
374 07:40:53.256476 PCI: 00:0d.2 disabled by fw_config
375 07:40:53.259845 PCI: 00:1c.7 disabled by fw_config
376 07:40:53.266514 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
377 07:40:53.273323 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
378 07:40:53.276759 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
379 07:40:53.280042 GENERIC: 0.0 disabled by fw_config
380 07:40:53.283409 GENERIC: 1.0 disabled by fw_config
381 07:40:53.290017 fw_config match found: DB_USB=USB3_ACTIVE
382 07:40:53.292916 fw_config match found: DB_USB=USB3_ACTIVE
383 07:40:53.296292 fw_config match found: DB_USB=USB3_ACTIVE
384 07:40:53.299660 fw_config match found: DB_USB=USB3_ACTIVE
385 07:40:53.306522 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
386 07:40:53.313146 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
387 07:40:53.320002 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
388 07:40:53.329507 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
389 07:40:53.332779 microcode: sig=0x806c1 pf=0x80 revision=0x86
390 07:40:53.339740 microcode: Update skipped, already up-to-date
391 07:40:53.346101 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
392 07:40:53.373278 Detected 4 core, 8 thread CPU.
393 07:40:53.376197 Setting up SMI for CPU
394 07:40:53.379904 IED base = 0x7b400000
395 07:40:53.380013 IED size = 0x00400000
396 07:40:53.382741 Will perform SMM setup.
397 07:40:53.389447 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
398 07:40:53.396369 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
399 07:40:53.403100 Processing 16 relocs. Offset value of 0x00030000
400 07:40:53.406023 Attempting to start 7 APs
401 07:40:53.409328 Waiting for 10ms after sending INIT.
402 07:40:53.425293 Waiting for 1st SIPI to complete...done.
403 07:40:53.425434 AP: slot 1 apic_id 1.
404 07:40:53.428174 AP: slot 6 apic_id 2.
405 07:40:53.431461 AP: slot 2 apic_id 3.
406 07:40:53.434934 Waiting for 2nd SIPI to complete...done.
407 07:40:53.438503 AP: slot 4 apic_id 7.
408 07:40:53.438643 AP: slot 7 apic_id 4.
409 07:40:53.441647 AP: slot 3 apic_id 5.
410 07:40:53.444754 AP: slot 5 apic_id 6.
411 07:40:53.451699 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
412 07:40:53.458379 Processing 13 relocs. Offset value of 0x00038000
413 07:40:53.458510 Unable to locate Global NVS
414 07:40:53.468495 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
415 07:40:53.471596 Installing permanent SMM handler to 0x7b000000
416 07:40:53.481242 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
417 07:40:53.484757 Processing 794 relocs. Offset value of 0x7b010000
418 07:40:53.494956 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
419 07:40:53.497979 Processing 13 relocs. Offset value of 0x7b008000
420 07:40:53.504770 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
421 07:40:53.511531 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
422 07:40:53.514871 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
423 07:40:53.521085 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
424 07:40:53.527912 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
425 07:40:53.534543 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
426 07:40:53.540903 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
427 07:40:53.540994 Unable to locate Global NVS
428 07:40:53.551175 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
429 07:40:53.554463 Clearing SMI status registers
430 07:40:53.554568 SMI_STS: PM1
431 07:40:53.557900 PM1_STS: PWRBTN
432 07:40:53.564302 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
433 07:40:53.567656 In relocation handler: CPU 0
434 07:40:53.571176 New SMBASE=0x7b000000 IEDBASE=0x7b400000
435 07:40:53.577844 Writing SMRR. base = 0x7b000006, mask=0xff800c00
436 07:40:53.577976 Relocation complete.
437 07:40:53.587363 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
438 07:40:53.587492 In relocation handler: CPU 1
439 07:40:53.594113 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
440 07:40:53.594240 Relocation complete.
441 07:40:53.603916 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
442 07:40:53.604045 In relocation handler: CPU 3
443 07:40:53.610846 New SMBASE=0x7afff400 IEDBASE=0x7b400000
444 07:40:53.610948 Relocation complete.
445 07:40:53.621005 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
446 07:40:53.621094 In relocation handler: CPU 7
447 07:40:53.627177 New SMBASE=0x7affe400 IEDBASE=0x7b400000
448 07:40:53.630662 Writing SMRR. base = 0x7b000006, mask=0xff800c00
449 07:40:53.634145 Relocation complete.
450 07:40:53.640915 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
451 07:40:53.644321 In relocation handler: CPU 4
452 07:40:53.647445 New SMBASE=0x7afff000 IEDBASE=0x7b400000
453 07:40:53.650844 Relocation complete.
454 07:40:53.657416 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
455 07:40:53.660859 In relocation handler: CPU 5
456 07:40:53.664345 New SMBASE=0x7affec00 IEDBASE=0x7b400000
457 07:40:53.667816 Writing SMRR. base = 0x7b000006, mask=0xff800c00
458 07:40:53.670818 Relocation complete.
459 07:40:53.677335 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
460 07:40:53.680768 In relocation handler: CPU 2
461 07:40:53.684038 New SMBASE=0x7afff800 IEDBASE=0x7b400000
462 07:40:53.687623 Relocation complete.
463 07:40:53.693951 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
464 07:40:53.697321 In relocation handler: CPU 6
465 07:40:53.700666 New SMBASE=0x7affe800 IEDBASE=0x7b400000
466 07:40:53.707134 Writing SMRR. base = 0x7b000006, mask=0xff800c00
467 07:40:53.707217 Relocation complete.
468 07:40:53.710874 Initializing CPU #0
469 07:40:53.714194 CPU: vendor Intel device 806c1
470 07:40:53.718101 CPU: family 06, model 8c, stepping 01
471 07:40:53.721669 Clearing out pending MCEs
472 07:40:53.724772 Setting up local APIC...
473 07:40:53.724857 apic_id: 0x00 done.
474 07:40:53.728152 Turbo is available but hidden
475 07:40:53.731499 Turbo is available and visible
476 07:40:53.734925 microcode: Update skipped, already up-to-date
477 07:40:53.738330 CPU #0 initialized
478 07:40:53.741663 Initializing CPU #7
479 07:40:53.741745 Initializing CPU #3
480 07:40:53.744887 CPU: vendor Intel device 806c1
481 07:40:53.748394 CPU: family 06, model 8c, stepping 01
482 07:40:53.751747 CPU: vendor Intel device 806c1
483 07:40:53.755249 CPU: family 06, model 8c, stepping 01
484 07:40:53.758631 Initializing CPU #6
485 07:40:53.761854 Initializing CPU #2
486 07:40:53.764909 CPU: vendor Intel device 806c1
487 07:40:53.768650 CPU: family 06, model 8c, stepping 01
488 07:40:53.771853 CPU: vendor Intel device 806c1
489 07:40:53.775145 CPU: family 06, model 8c, stepping 01
490 07:40:53.778300 Clearing out pending MCEs
491 07:40:53.778382 Clearing out pending MCEs
492 07:40:53.781381 Setting up local APIC...
493 07:40:53.784855 Initializing CPU #5
494 07:40:53.784938 Initializing CPU #4
495 07:40:53.788013 CPU: vendor Intel device 806c1
496 07:40:53.795109 CPU: family 06, model 8c, stepping 01
497 07:40:53.798092 CPU: vendor Intel device 806c1
498 07:40:53.801390 CPU: family 06, model 8c, stepping 01
499 07:40:53.801499 Clearing out pending MCEs
500 07:40:53.804745 Clearing out pending MCEs
501 07:40:53.808127 Setting up local APIC...
502 07:40:53.811537 Clearing out pending MCEs
503 07:40:53.814936 Clearing out pending MCEs
504 07:40:53.815065 Setting up local APIC...
505 07:40:53.818153 Initializing CPU #1
506 07:40:53.821509 apic_id: 0x05 done.
507 07:40:53.821644 Setting up local APIC...
508 07:40:53.828022 microcode: Update skipped, already up-to-date
509 07:40:53.828165 apic_id: 0x04 done.
510 07:40:53.831448 CPU #3 initialized
511 07:40:53.834521 Setting up local APIC...
512 07:40:53.838071 Setting up local APIC...
513 07:40:53.838197 apic_id: 0x02 done.
514 07:40:53.841420 apic_id: 0x03 done.
515 07:40:53.844725 microcode: Update skipped, already up-to-date
516 07:40:53.848111 apic_id: 0x07 done.
517 07:40:53.851477 apic_id: 0x06 done.
518 07:40:53.854874 microcode: Update skipped, already up-to-date
519 07:40:53.857705 microcode: Update skipped, already up-to-date
520 07:40:53.861201 CPU #6 initialized
521 07:40:53.864454 microcode: Update skipped, already up-to-date
522 07:40:53.867790 CPU #5 initialized
523 07:40:53.867873 CPU #4 initialized
524 07:40:53.871089 CPU: vendor Intel device 806c1
525 07:40:53.877920 CPU: family 06, model 8c, stepping 01
526 07:40:53.881305 microcode: Update skipped, already up-to-date
527 07:40:53.881392 CPU #2 initialized
528 07:40:53.884696 CPU #7 initialized
529 07:40:53.887840 Clearing out pending MCEs
530 07:40:53.890985 Setting up local APIC...
531 07:40:53.891067 apic_id: 0x01 done.
532 07:40:53.897838 microcode: Update skipped, already up-to-date
533 07:40:53.897923 CPU #1 initialized
534 07:40:53.904639 bsp_do_flight_plan done after 464 msecs.
535 07:40:53.907686 CPU: frequency set to 4000 MHz
536 07:40:53.907827 Enabling SMIs.
537 07:40:53.914459 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
538 07:40:53.930216 SATAXPCIE1 indicates PCIe NVMe is present
539 07:40:53.933453 Probing TPM: done!
540 07:40:53.936851 Connected to device vid:did:rid of 1ae0:0028:00
541 07:40:53.947256 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
542 07:40:53.950856 Initialized TPM device CR50 revision 0
543 07:40:53.954011 Enabling S0i3.4
544 07:40:53.960825 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
545 07:40:53.964050 Found a VBT of 8704 bytes after decompression
546 07:40:53.970849 cse_lite: CSE RO boot. HybridStorageMode disabled
547 07:40:53.977580 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
548 07:40:54.052858 FSPS returned 0
549 07:40:54.055948 Executing Phase 1 of FspMultiPhaseSiInit
550 07:40:54.066183 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
551 07:40:54.069185 port C0 DISC req: usage 1 usb3 1 usb2 5
552 07:40:54.072633 Raw Buffer output 0 00000511
553 07:40:54.075778 Raw Buffer output 1 00000000
554 07:40:54.079592 pmc_send_ipc_cmd succeeded
555 07:40:54.086156 port C1 DISC req: usage 1 usb3 2 usb2 3
556 07:40:54.086240 Raw Buffer output 0 00000321
557 07:40:54.089278 Raw Buffer output 1 00000000
558 07:40:54.093783 pmc_send_ipc_cmd succeeded
559 07:40:54.098889 Detected 4 core, 8 thread CPU.
560 07:40:54.102266 Detected 4 core, 8 thread CPU.
561 07:40:54.336126 Display FSP Version Info HOB
562 07:40:54.339841 Reference Code - CPU = a.0.4c.31
563 07:40:54.343060 uCode Version = 0.0.0.86
564 07:40:54.346517 TXT ACM version = ff.ff.ff.ffff
565 07:40:54.349883 Reference Code - ME = a.0.4c.31
566 07:40:54.352719 MEBx version = 0.0.0.0
567 07:40:54.356222 ME Firmware Version = Consumer SKU
568 07:40:54.359561 Reference Code - PCH = a.0.4c.31
569 07:40:54.363132 PCH-CRID Status = Disabled
570 07:40:54.366372 PCH-CRID Original Value = ff.ff.ff.ffff
571 07:40:54.369825 PCH-CRID New Value = ff.ff.ff.ffff
572 07:40:54.372678 OPROM - RST - RAID = ff.ff.ff.ffff
573 07:40:54.376047 PCH Hsio Version = 4.0.0.0
574 07:40:54.379332 Reference Code - SA - System Agent = a.0.4c.31
575 07:40:54.383109 Reference Code - MRC = 2.0.0.1
576 07:40:54.385899 SA - PCIe Version = a.0.4c.31
577 07:40:54.389243 SA-CRID Status = Disabled
578 07:40:54.392671 SA-CRID Original Value = 0.0.0.1
579 07:40:54.396073 SA-CRID New Value = 0.0.0.1
580 07:40:54.399495 OPROM - VBIOS = ff.ff.ff.ffff
581 07:40:54.402785 IO Manageability Engine FW Version = 11.1.4.0
582 07:40:54.406151 PHY Build Version = 0.0.0.e0
583 07:40:54.409543 Thunderbolt(TM) FW Version = 0.0.0.0
584 07:40:54.415881 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
585 07:40:54.419305 ITSS IRQ Polarities Before:
586 07:40:54.419388 IPC0: 0xffffffff
587 07:40:54.422813 IPC1: 0xffffffff
588 07:40:54.422895 IPC2: 0xffffffff
589 07:40:54.426246 IPC3: 0xffffffff
590 07:40:54.429820 ITSS IRQ Polarities After:
591 07:40:54.429902 IPC0: 0xffffffff
592 07:40:54.432780 IPC1: 0xffffffff
593 07:40:54.432862 IPC2: 0xffffffff
594 07:40:54.435991 IPC3: 0xffffffff
595 07:40:54.439439 Found PCIe Root Port #9 at PCI: 00:1d.0.
596 07:40:54.452897 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
597 07:40:54.462945 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
598 07:40:54.475923 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
599 07:40:54.482678 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
600 07:40:54.482808 Enumerating buses...
601 07:40:54.489339 Show all devs... Before device enumeration.
602 07:40:54.489441 Root Device: enabled 1
603 07:40:54.492298 DOMAIN: 0000: enabled 1
604 07:40:54.495803 CPU_CLUSTER: 0: enabled 1
605 07:40:54.499206 PCI: 00:00.0: enabled 1
606 07:40:54.499293 PCI: 00:02.0: enabled 1
607 07:40:54.502776 PCI: 00:04.0: enabled 1
608 07:40:54.505621 PCI: 00:05.0: enabled 1
609 07:40:54.509405 PCI: 00:06.0: enabled 0
610 07:40:54.509512 PCI: 00:07.0: enabled 0
611 07:40:54.512675 PCI: 00:07.1: enabled 0
612 07:40:54.515600 PCI: 00:07.2: enabled 0
613 07:40:54.519212 PCI: 00:07.3: enabled 0
614 07:40:54.519576 PCI: 00:08.0: enabled 1
615 07:40:54.522560 PCI: 00:09.0: enabled 0
616 07:40:54.525878 PCI: 00:0a.0: enabled 0
617 07:40:54.529162 PCI: 00:0d.0: enabled 1
618 07:40:54.529557 PCI: 00:0d.1: enabled 0
619 07:40:54.532665 PCI: 00:0d.2: enabled 0
620 07:40:54.535971 PCI: 00:0d.3: enabled 0
621 07:40:54.539377 PCI: 00:0e.0: enabled 0
622 07:40:54.539739 PCI: 00:10.2: enabled 1
623 07:40:54.542633 PCI: 00:10.6: enabled 0
624 07:40:54.546085 PCI: 00:10.7: enabled 0
625 07:40:54.546459 PCI: 00:12.0: enabled 0
626 07:40:54.549460 PCI: 00:12.6: enabled 0
627 07:40:54.552578 PCI: 00:13.0: enabled 0
628 07:40:54.555819 PCI: 00:14.0: enabled 1
629 07:40:54.556189 PCI: 00:14.1: enabled 0
630 07:40:54.559043 PCI: 00:14.2: enabled 1
631 07:40:54.562654 PCI: 00:14.3: enabled 1
632 07:40:54.566064 PCI: 00:15.0: enabled 1
633 07:40:54.566422 PCI: 00:15.1: enabled 1
634 07:40:54.569016 PCI: 00:15.2: enabled 1
635 07:40:54.572581 PCI: 00:15.3: enabled 1
636 07:40:54.576007 PCI: 00:16.0: enabled 1
637 07:40:54.576362 PCI: 00:16.1: enabled 0
638 07:40:54.578965 PCI: 00:16.2: enabled 0
639 07:40:54.582470 PCI: 00:16.3: enabled 0
640 07:40:54.582883 PCI: 00:16.4: enabled 0
641 07:40:54.585878 PCI: 00:16.5: enabled 0
642 07:40:54.589361 PCI: 00:17.0: enabled 1
643 07:40:54.592290 PCI: 00:19.0: enabled 0
644 07:40:54.592706 PCI: 00:19.1: enabled 1
645 07:40:54.595688 PCI: 00:19.2: enabled 0
646 07:40:54.598836 PCI: 00:1c.0: enabled 1
647 07:40:54.602450 PCI: 00:1c.1: enabled 0
648 07:40:54.602863 PCI: 00:1c.2: enabled 0
649 07:40:54.605870 PCI: 00:1c.3: enabled 0
650 07:40:54.608758 PCI: 00:1c.4: enabled 0
651 07:40:54.612364 PCI: 00:1c.5: enabled 0
652 07:40:54.612776 PCI: 00:1c.6: enabled 1
653 07:40:54.615763 PCI: 00:1c.7: enabled 0
654 07:40:54.619097 PCI: 00:1d.0: enabled 1
655 07:40:54.622557 PCI: 00:1d.1: enabled 0
656 07:40:54.622944 PCI: 00:1d.2: enabled 1
657 07:40:54.625334 PCI: 00:1d.3: enabled 0
658 07:40:54.628895 PCI: 00:1e.0: enabled 1
659 07:40:54.629326 PCI: 00:1e.1: enabled 0
660 07:40:54.632223 PCI: 00:1e.2: enabled 1
661 07:40:54.635789 PCI: 00:1e.3: enabled 1
662 07:40:54.639159 PCI: 00:1f.0: enabled 1
663 07:40:54.639691 PCI: 00:1f.1: enabled 0
664 07:40:54.642109 PCI: 00:1f.2: enabled 1
665 07:40:54.645573 PCI: 00:1f.3: enabled 1
666 07:40:54.649129 PCI: 00:1f.4: enabled 0
667 07:40:54.649694 PCI: 00:1f.5: enabled 1
668 07:40:54.652436 PCI: 00:1f.6: enabled 0
669 07:40:54.655851 PCI: 00:1f.7: enabled 0
670 07:40:54.656359 APIC: 00: enabled 1
671 07:40:54.659055 GENERIC: 0.0: enabled 1
672 07:40:54.662429 GENERIC: 0.0: enabled 1
673 07:40:54.665590 GENERIC: 1.0: enabled 1
674 07:40:54.666096 GENERIC: 0.0: enabled 1
675 07:40:54.669066 GENERIC: 1.0: enabled 1
676 07:40:54.672254 USB0 port 0: enabled 1
677 07:40:54.675301 GENERIC: 0.0: enabled 1
678 07:40:54.675860 USB0 port 0: enabled 1
679 07:40:54.678783 GENERIC: 0.0: enabled 1
680 07:40:54.682189 I2C: 00:1a: enabled 1
681 07:40:54.682582 I2C: 00:31: enabled 1
682 07:40:54.685731 I2C: 00:32: enabled 1
683 07:40:54.688694 I2C: 00:10: enabled 1
684 07:40:54.689084 I2C: 00:15: enabled 1
685 07:40:54.692179 GENERIC: 0.0: enabled 0
686 07:40:54.695613 GENERIC: 1.0: enabled 0
687 07:40:54.699034 GENERIC: 0.0: enabled 1
688 07:40:54.699425 SPI: 00: enabled 1
689 07:40:54.702031 SPI: 00: enabled 1
690 07:40:54.702460 PNP: 0c09.0: enabled 1
691 07:40:54.705378 GENERIC: 0.0: enabled 1
692 07:40:54.708677 USB3 port 0: enabled 1
693 07:40:54.712269 USB3 port 1: enabled 1
694 07:40:54.712774 USB3 port 2: enabled 0
695 07:40:54.715241 USB3 port 3: enabled 0
696 07:40:54.718697 USB2 port 0: enabled 0
697 07:40:54.719125 USB2 port 1: enabled 1
698 07:40:54.722164 USB2 port 2: enabled 1
699 07:40:54.725613 USB2 port 3: enabled 0
700 07:40:54.728808 USB2 port 4: enabled 1
701 07:40:54.729170 USB2 port 5: enabled 0
702 07:40:54.731809 USB2 port 6: enabled 0
703 07:40:54.735379 USB2 port 7: enabled 0
704 07:40:54.735845 USB2 port 8: enabled 0
705 07:40:54.738894 USB2 port 9: enabled 0
706 07:40:54.741821 USB3 port 0: enabled 0
707 07:40:54.742179 USB3 port 1: enabled 1
708 07:40:54.745094 USB3 port 2: enabled 0
709 07:40:54.748498 USB3 port 3: enabled 0
710 07:40:54.751930 GENERIC: 0.0: enabled 1
711 07:40:54.752361 GENERIC: 1.0: enabled 1
712 07:40:54.755338 APIC: 01: enabled 1
713 07:40:54.758779 APIC: 03: enabled 1
714 07:40:54.759245 APIC: 05: enabled 1
715 07:40:54.762096 APIC: 07: enabled 1
716 07:40:54.762482 APIC: 06: enabled 1
717 07:40:54.765622 APIC: 02: enabled 1
718 07:40:54.768532 APIC: 04: enabled 1
719 07:40:54.768905 Compare with tree...
720 07:40:54.772066 Root Device: enabled 1
721 07:40:54.775493 DOMAIN: 0000: enabled 1
722 07:40:54.778843 PCI: 00:00.0: enabled 1
723 07:40:54.779238 PCI: 00:02.0: enabled 1
724 07:40:54.781962 PCI: 00:04.0: enabled 1
725 07:40:54.785504 GENERIC: 0.0: enabled 1
726 07:40:54.788439 PCI: 00:05.0: enabled 1
727 07:40:54.791790 PCI: 00:06.0: enabled 0
728 07:40:54.792146 PCI: 00:07.0: enabled 0
729 07:40:54.795361 GENERIC: 0.0: enabled 1
730 07:40:54.798293 PCI: 00:07.1: enabled 0
731 07:40:54.801652 GENERIC: 1.0: enabled 1
732 07:40:54.805234 PCI: 00:07.2: enabled 0
733 07:40:54.805685 GENERIC: 0.0: enabled 1
734 07:40:54.808603 PCI: 00:07.3: enabled 0
735 07:40:54.811964 GENERIC: 1.0: enabled 1
736 07:40:54.815472 PCI: 00:08.0: enabled 1
737 07:40:54.818269 PCI: 00:09.0: enabled 0
738 07:40:54.818644 PCI: 00:0a.0: enabled 0
739 07:40:54.821648 PCI: 00:0d.0: enabled 1
740 07:40:54.825125 USB0 port 0: enabled 1
741 07:40:54.828567 USB3 port 0: enabled 1
742 07:40:54.831570 USB3 port 1: enabled 1
743 07:40:54.834958 USB3 port 2: enabled 0
744 07:40:54.835342 USB3 port 3: enabled 0
745 07:40:54.838477 PCI: 00:0d.1: enabled 0
746 07:40:54.842008 PCI: 00:0d.2: enabled 0
747 07:40:54.844968 GENERIC: 0.0: enabled 1
748 07:40:54.848398 PCI: 00:0d.3: enabled 0
749 07:40:54.848890 PCI: 00:0e.0: enabled 0
750 07:40:54.851444 PCI: 00:10.2: enabled 1
751 07:40:54.855183 PCI: 00:10.6: enabled 0
752 07:40:54.858267 PCI: 00:10.7: enabled 0
753 07:40:54.861419 PCI: 00:12.0: enabled 0
754 07:40:54.861849 PCI: 00:12.6: enabled 0
755 07:40:54.864880 PCI: 00:13.0: enabled 0
756 07:40:54.868105 PCI: 00:14.0: enabled 1
757 07:40:54.871547 USB0 port 0: enabled 1
758 07:40:54.875050 USB2 port 0: enabled 0
759 07:40:54.875414 USB2 port 1: enabled 1
760 07:40:54.878039 USB2 port 2: enabled 1
761 07:40:54.881601 USB2 port 3: enabled 0
762 07:40:54.884874 USB2 port 4: enabled 1
763 07:40:54.888300 USB2 port 5: enabled 0
764 07:40:54.888657 USB2 port 6: enabled 0
765 07:40:54.891651 USB2 port 7: enabled 0
766 07:40:54.894957 USB2 port 8: enabled 0
767 07:40:54.897870 USB2 port 9: enabled 0
768 07:40:54.901337 USB3 port 0: enabled 0
769 07:40:54.904473 USB3 port 1: enabled 1
770 07:40:54.904839 USB3 port 2: enabled 0
771 07:40:54.908248 USB3 port 3: enabled 0
772 07:40:54.911355 PCI: 00:14.1: enabled 0
773 07:40:54.914890 PCI: 00:14.2: enabled 1
774 07:40:54.918040 PCI: 00:14.3: enabled 1
775 07:40:54.918461 GENERIC: 0.0: enabled 1
776 07:40:54.921082 PCI: 00:15.0: enabled 1
777 07:40:54.924490 I2C: 00:1a: enabled 1
778 07:40:54.928074 I2C: 00:31: enabled 1
779 07:40:54.931506 I2C: 00:32: enabled 1
780 07:40:54.931930 PCI: 00:15.1: enabled 1
781 07:40:54.934360 I2C: 00:10: enabled 1
782 07:40:54.937925 PCI: 00:15.2: enabled 1
783 07:40:54.941336 PCI: 00:15.3: enabled 1
784 07:40:54.941791 PCI: 00:16.0: enabled 1
785 07:40:54.944876 PCI: 00:16.1: enabled 0
786 07:40:54.947695 PCI: 00:16.2: enabled 0
787 07:40:54.951295 PCI: 00:16.3: enabled 0
788 07:40:54.954730 PCI: 00:16.4: enabled 0
789 07:40:54.955121 PCI: 00:16.5: enabled 0
790 07:40:54.957849 PCI: 00:17.0: enabled 1
791 07:40:54.961275 PCI: 00:19.0: enabled 0
792 07:40:54.965156 PCI: 00:19.1: enabled 1
793 07:40:54.965697 I2C: 00:15: enabled 1
794 07:40:54.968741 PCI: 00:19.2: enabled 0
795 07:40:54.972546 PCI: 00:1d.0: enabled 1
796 07:40:54.972931 GENERIC: 0.0: enabled 1
797 07:40:54.976385 PCI: 00:1e.0: enabled 1
798 07:40:54.979491 PCI: 00:1e.1: enabled 0
799 07:40:54.982439 PCI: 00:1e.2: enabled 1
800 07:40:54.986057 SPI: 00: enabled 1
801 07:40:54.986443 PCI: 00:1e.3: enabled 1
802 07:40:54.989557 SPI: 00: enabled 1
803 07:40:55.039121 PCI: 00:1f.0: enabled 1
804 07:40:55.039577 PNP: 0c09.0: enabled 1
805 07:40:55.040220 PCI: 00:1f.1: enabled 0
806 07:40:55.040533 PCI: 00:1f.2: enabled 1
807 07:40:55.040820 GENERIC: 0.0: enabled 1
808 07:40:55.041095 GENERIC: 0.0: enabled 1
809 07:40:55.041364 GENERIC: 1.0: enabled 1
810 07:40:55.041662 PCI: 00:1f.3: enabled 1
811 07:40:55.041929 PCI: 00:1f.4: enabled 0
812 07:40:55.042189 PCI: 00:1f.5: enabled 1
813 07:40:55.042447 PCI: 00:1f.6: enabled 0
814 07:40:55.042700 PCI: 00:1f.7: enabled 0
815 07:40:55.042956 CPU_CLUSTER: 0: enabled 1
816 07:40:55.043211 APIC: 00: enabled 1
817 07:40:55.043469 APIC: 01: enabled 1
818 07:40:55.043718 APIC: 03: enabled 1
819 07:40:55.043968 APIC: 05: enabled 1
820 07:40:55.044219 APIC: 07: enabled 1
821 07:40:55.044470 APIC: 06: enabled 1
822 07:40:55.044720 APIC: 02: enabled 1
823 07:40:55.072618 APIC: 04: enabled 1
824 07:40:55.073007 Root Device scanning...
825 07:40:55.073316 scan_static_bus for Root Device
826 07:40:55.073663 DOMAIN: 0000 enabled
827 07:40:55.073951 CPU_CLUSTER: 0 enabled
828 07:40:55.074547 DOMAIN: 0000 scanning...
829 07:40:55.074847 PCI: pci_scan_bus for bus 00
830 07:40:55.075121 PCI: 00:00.0 [8086/0000] ops
831 07:40:55.075387 PCI: 00:00.0 [8086/9a12] enabled
832 07:40:55.075649 PCI: 00:02.0 [8086/0000] bus ops
833 07:40:55.075907 PCI: 00:02.0 [8086/9a40] enabled
834 07:40:55.076602 PCI: 00:04.0 [8086/0000] bus ops
835 07:40:55.080069 PCI: 00:04.0 [8086/9a03] enabled
836 07:40:55.083494 PCI: 00:05.0 [8086/9a19] enabled
837 07:40:55.086688 PCI: 00:07.0 [0000/0000] hidden
838 07:40:55.089870 PCI: 00:08.0 [8086/9a11] enabled
839 07:40:55.093158 PCI: 00:0a.0 [8086/9a0d] disabled
840 07:40:55.096676 PCI: 00:0d.0 [8086/0000] bus ops
841 07:40:55.100056 PCI: 00:0d.0 [8086/9a13] enabled
842 07:40:55.103543 PCI: 00:14.0 [8086/0000] bus ops
843 07:40:55.106346 PCI: 00:14.0 [8086/a0ed] enabled
844 07:40:55.109901 PCI: 00:14.2 [8086/a0ef] enabled
845 07:40:55.113262 PCI: 00:14.3 [8086/0000] bus ops
846 07:40:55.116682 PCI: 00:14.3 [8086/a0f0] enabled
847 07:40:55.120183 PCI: 00:15.0 [8086/0000] bus ops
848 07:40:55.123031 PCI: 00:15.0 [8086/a0e8] enabled
849 07:40:55.126522 PCI: 00:15.1 [8086/0000] bus ops
850 07:40:55.129993 PCI: 00:15.1 [8086/a0e9] enabled
851 07:40:55.133302 PCI: 00:15.2 [8086/0000] bus ops
852 07:40:55.136486 PCI: 00:15.2 [8086/a0ea] enabled
853 07:40:55.139819 PCI: 00:15.3 [8086/0000] bus ops
854 07:40:55.143415 PCI: 00:15.3 [8086/a0eb] enabled
855 07:40:55.146615 PCI: 00:16.0 [8086/0000] ops
856 07:40:55.149672 PCI: 00:16.0 [8086/a0e0] enabled
857 07:40:55.152990 PCI: Static device PCI: 00:17.0 not found, disabling it.
858 07:40:55.156571 PCI: 00:19.0 [8086/0000] bus ops
859 07:40:55.162976 PCI: 00:19.0 [8086/a0c5] disabled
860 07:40:55.166508 PCI: 00:19.1 [8086/0000] bus ops
861 07:40:55.169890 PCI: 00:19.1 [8086/a0c6] enabled
862 07:40:55.173348 PCI: 00:1d.0 [8086/0000] bus ops
863 07:40:55.176257 PCI: 00:1d.0 [8086/a0b0] enabled
864 07:40:55.176647 PCI: 00:1e.0 [8086/0000] ops
865 07:40:55.179699 PCI: 00:1e.0 [8086/a0a8] enabled
866 07:40:55.183148 PCI: 00:1e.2 [8086/0000] bus ops
867 07:40:55.186655 PCI: 00:1e.2 [8086/a0aa] enabled
868 07:40:55.190127 PCI: 00:1e.3 [8086/0000] bus ops
869 07:40:55.193372 PCI: 00:1e.3 [8086/a0ab] enabled
870 07:40:55.196636 PCI: 00:1f.0 [8086/0000] bus ops
871 07:40:55.199893 PCI: 00:1f.0 [8086/a087] enabled
872 07:40:55.203198 RTC Init
873 07:40:55.206007 Set power on after power failure.
874 07:40:55.206394 Disabling Deep S3
875 07:40:55.209315 Disabling Deep S3
876 07:40:55.212996 Disabling Deep S4
877 07:40:55.213381 Disabling Deep S4
878 07:40:55.216342 Disabling Deep S5
879 07:40:55.216724 Disabling Deep S5
880 07:40:55.219650 PCI: 00:1f.2 [0000/0000] hidden
881 07:40:55.223163 PCI: 00:1f.3 [8086/0000] bus ops
882 07:40:55.226045 PCI: 00:1f.3 [8086/a0c8] enabled
883 07:40:55.229407 PCI: 00:1f.5 [8086/0000] bus ops
884 07:40:55.232963 PCI: 00:1f.5 [8086/a0a4] enabled
885 07:40:55.236453 PCI: Leftover static devices:
886 07:40:55.239516 PCI: 00:10.2
887 07:40:55.239923 PCI: 00:10.6
888 07:40:55.240246 PCI: 00:10.7
889 07:40:55.242801 PCI: 00:06.0
890 07:40:55.243184 PCI: 00:07.1
891 07:40:55.246132 PCI: 00:07.2
892 07:40:55.246585 PCI: 00:07.3
893 07:40:55.246897 PCI: 00:09.0
894 07:40:55.249393 PCI: 00:0d.1
895 07:40:55.249936 PCI: 00:0d.2
896 07:40:55.252920 PCI: 00:0d.3
897 07:40:55.253303 PCI: 00:0e.0
898 07:40:55.256305 PCI: 00:12.0
899 07:40:55.256690 PCI: 00:12.6
900 07:40:55.256992 PCI: 00:13.0
901 07:40:55.259596 PCI: 00:14.1
902 07:40:55.259993 PCI: 00:16.1
903 07:40:55.262855 PCI: 00:16.2
904 07:40:55.263237 PCI: 00:16.3
905 07:40:55.263540 PCI: 00:16.4
906 07:40:55.266365 PCI: 00:16.5
907 07:40:55.266749 PCI: 00:17.0
908 07:40:55.269372 PCI: 00:19.2
909 07:40:55.269799 PCI: 00:1e.1
910 07:40:55.270107 PCI: 00:1f.1
911 07:40:55.272725 PCI: 00:1f.4
912 07:40:55.273109 PCI: 00:1f.6
913 07:40:55.275977 PCI: 00:1f.7
914 07:40:55.279509 PCI: Check your devicetree.cb.
915 07:40:55.279988 PCI: 00:02.0 scanning...
916 07:40:55.285904 scan_generic_bus for PCI: 00:02.0
917 07:40:55.289519 scan_generic_bus for PCI: 00:02.0 done
918 07:40:55.293085 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
919 07:40:55.296289 PCI: 00:04.0 scanning...
920 07:40:55.299714 scan_generic_bus for PCI: 00:04.0
921 07:40:55.302912 GENERIC: 0.0 enabled
922 07:40:55.306259 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
923 07:40:55.313072 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
924 07:40:55.315972 PCI: 00:0d.0 scanning...
925 07:40:55.319457 scan_static_bus for PCI: 00:0d.0
926 07:40:55.319872 USB0 port 0 enabled
927 07:40:55.322871 USB0 port 0 scanning...
928 07:40:55.326224 scan_static_bus for USB0 port 0
929 07:40:55.329580 USB3 port 0 enabled
930 07:40:55.329999 USB3 port 1 enabled
931 07:40:55.332621 USB3 port 2 disabled
932 07:40:55.336162 USB3 port 3 disabled
933 07:40:55.336578 USB3 port 0 scanning...
934 07:40:55.339184 scan_static_bus for USB3 port 0
935 07:40:55.346108 scan_static_bus for USB3 port 0 done
936 07:40:55.349542 scan_bus: bus USB3 port 0 finished in 6 msecs
937 07:40:55.352441 USB3 port 1 scanning...
938 07:40:55.356219 scan_static_bus for USB3 port 1
939 07:40:55.359072 scan_static_bus for USB3 port 1 done
940 07:40:55.362536 scan_bus: bus USB3 port 1 finished in 6 msecs
941 07:40:55.366033 scan_static_bus for USB0 port 0 done
942 07:40:55.372371 scan_bus: bus USB0 port 0 finished in 43 msecs
943 07:40:55.375817 scan_static_bus for PCI: 00:0d.0 done
944 07:40:55.379132 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
945 07:40:55.382361 PCI: 00:14.0 scanning...
946 07:40:55.385907 scan_static_bus for PCI: 00:14.0
947 07:40:55.388954 USB0 port 0 enabled
948 07:40:55.392555 USB0 port 0 scanning...
949 07:40:55.395931 scan_static_bus for USB0 port 0
950 07:40:55.396351 USB2 port 0 disabled
951 07:40:55.398960 USB2 port 1 enabled
952 07:40:55.399381 USB2 port 2 enabled
953 07:40:55.402199 USB2 port 3 disabled
954 07:40:55.405620 USB2 port 4 enabled
955 07:40:55.406044 USB2 port 5 disabled
956 07:40:55.409108 USB2 port 6 disabled
957 07:40:55.412375 USB2 port 7 disabled
958 07:40:55.412793 USB2 port 8 disabled
959 07:40:55.415841 USB2 port 9 disabled
960 07:40:55.419153 USB3 port 0 disabled
961 07:40:55.419586 USB3 port 1 enabled
962 07:40:55.422012 USB3 port 2 disabled
963 07:40:55.425463 USB3 port 3 disabled
964 07:40:55.425915 USB2 port 1 scanning...
965 07:40:55.428894 scan_static_bus for USB2 port 1
966 07:40:55.432464 scan_static_bus for USB2 port 1 done
967 07:40:55.438789 scan_bus: bus USB2 port 1 finished in 6 msecs
968 07:40:55.442189 USB2 port 2 scanning...
969 07:40:55.445214 scan_static_bus for USB2 port 2
970 07:40:55.448593 scan_static_bus for USB2 port 2 done
971 07:40:55.452120 scan_bus: bus USB2 port 2 finished in 6 msecs
972 07:40:55.455532 USB2 port 4 scanning...
973 07:40:55.458869 scan_static_bus for USB2 port 4
974 07:40:55.462210 scan_static_bus for USB2 port 4 done
975 07:40:55.465114 scan_bus: bus USB2 port 4 finished in 6 msecs
976 07:40:55.468536 USB3 port 1 scanning...
977 07:40:55.472050 scan_static_bus for USB3 port 1
978 07:40:55.474994 scan_static_bus for USB3 port 1 done
979 07:40:55.481552 scan_bus: bus USB3 port 1 finished in 6 msecs
980 07:40:55.484993 scan_static_bus for USB0 port 0 done
981 07:40:55.488498 scan_bus: bus USB0 port 0 finished in 93 msecs
982 07:40:55.492041 scan_static_bus for PCI: 00:14.0 done
983 07:40:55.498193 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
984 07:40:55.501388 PCI: 00:14.3 scanning...
985 07:40:55.505055 scan_static_bus for PCI: 00:14.3
986 07:40:55.505472 GENERIC: 0.0 enabled
987 07:40:55.511282 scan_static_bus for PCI: 00:14.3 done
988 07:40:55.515095 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
989 07:40:55.517967 PCI: 00:15.0 scanning...
990 07:40:55.521304 scan_static_bus for PCI: 00:15.0
991 07:40:55.521801 I2C: 00:1a enabled
992 07:40:55.524550 I2C: 00:31 enabled
993 07:40:55.528106 I2C: 00:32 enabled
994 07:40:55.531389 scan_static_bus for PCI: 00:15.0 done
995 07:40:55.534577 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
996 07:40:55.538153 PCI: 00:15.1 scanning...
997 07:40:55.541625 scan_static_bus for PCI: 00:15.1
998 07:40:55.545040 I2C: 00:10 enabled
999 07:40:55.548540 scan_static_bus for PCI: 00:15.1 done
1000 07:40:55.551857 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1001 07:40:55.555602 PCI: 00:15.2 scanning...
1002 07:40:55.558318 scan_static_bus for PCI: 00:15.2
1003 07:40:55.561855 scan_static_bus for PCI: 00:15.2 done
1004 07:40:55.565103 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1005 07:40:55.568425 PCI: 00:15.3 scanning...
1006 07:40:55.571781 scan_static_bus for PCI: 00:15.3
1007 07:40:55.575220 scan_static_bus for PCI: 00:15.3 done
1008 07:40:55.582089 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1009 07:40:55.584884 PCI: 00:19.1 scanning...
1010 07:40:55.588570 scan_static_bus for PCI: 00:19.1
1011 07:40:55.588992 I2C: 00:15 enabled
1012 07:40:55.591980 scan_static_bus for PCI: 00:19.1 done
1013 07:40:55.598277 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1014 07:40:55.601744 PCI: 00:1d.0 scanning...
1015 07:40:55.605092 do_pci_scan_bridge for PCI: 00:1d.0
1016 07:40:55.608071 PCI: pci_scan_bus for bus 01
1017 07:40:55.611469 PCI: 01:00.0 [1c5c/174a] enabled
1018 07:40:55.611887 GENERIC: 0.0 enabled
1019 07:40:55.614647 Enabling Common Clock Configuration
1020 07:40:55.621645 L1 Sub-State supported from root port 29
1021 07:40:55.624938 L1 Sub-State Support = 0xf
1022 07:40:55.625354 CommonModeRestoreTime = 0x28
1023 07:40:55.631591 Power On Value = 0x16, Power On Scale = 0x0
1024 07:40:55.632014 ASPM: Enabled L1
1025 07:40:55.634551 PCIe: Max_Payload_Size adjusted to 128
1026 07:40:55.641078 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1027 07:40:55.644728 PCI: 00:1e.2 scanning...
1028 07:40:55.647940 scan_generic_bus for PCI: 00:1e.2
1029 07:40:55.648355 SPI: 00 enabled
1030 07:40:55.654427 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1031 07:40:55.661425 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1032 07:40:55.661900 PCI: 00:1e.3 scanning...
1033 07:40:55.664327 scan_generic_bus for PCI: 00:1e.3
1034 07:40:55.667598 SPI: 00 enabled
1035 07:40:55.674699 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1036 07:40:55.678138 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1037 07:40:55.681059 PCI: 00:1f.0 scanning...
1038 07:40:55.684390 scan_static_bus for PCI: 00:1f.0
1039 07:40:55.687822 PNP: 0c09.0 enabled
1040 07:40:55.688426 PNP: 0c09.0 scanning...
1041 07:40:55.691483 scan_static_bus for PNP: 0c09.0
1042 07:40:55.697588 scan_static_bus for PNP: 0c09.0 done
1043 07:40:55.701147 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1044 07:40:55.704615 scan_static_bus for PCI: 00:1f.0 done
1045 07:40:55.707514 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1046 07:40:55.710875 PCI: 00:1f.2 scanning...
1047 07:40:55.714634 scan_static_bus for PCI: 00:1f.2
1048 07:40:55.717428 GENERIC: 0.0 enabled
1049 07:40:55.720917 GENERIC: 0.0 scanning...
1050 07:40:55.724188 scan_static_bus for GENERIC: 0.0
1051 07:40:55.724604 GENERIC: 0.0 enabled
1052 07:40:55.727345 GENERIC: 1.0 enabled
1053 07:40:55.731017 scan_static_bus for GENERIC: 0.0 done
1054 07:40:55.737550 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1055 07:40:55.741035 scan_static_bus for PCI: 00:1f.2 done
1056 07:40:55.747895 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1057 07:40:55.748608 PCI: 00:1f.3 scanning...
1058 07:40:55.751063 scan_static_bus for PCI: 00:1f.3
1059 07:40:55.754329 scan_static_bus for PCI: 00:1f.3 done
1060 07:40:55.760457 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1061 07:40:55.761104 PCI: 00:1f.5 scanning...
1062 07:40:55.767424 scan_generic_bus for PCI: 00:1f.5
1063 07:40:55.770757 scan_generic_bus for PCI: 00:1f.5 done
1064 07:40:55.774151 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1065 07:40:55.780856 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1066 07:40:55.783688 scan_static_bus for Root Device done
1067 07:40:55.787152 scan_bus: bus Root Device finished in 736 msecs
1068 07:40:55.787303 done
1069 07:40:55.794134 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1070 07:40:55.797099 Chrome EC: UHEPI supported
1071 07:40:55.803917 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1072 07:40:55.810318 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1073 07:40:55.813742 SPI flash protection: WPSW=0 SRP0=0
1074 07:40:55.817195 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1075 07:40:55.823602 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1076 07:40:55.827086 found VGA at PCI: 00:02.0
1077 07:40:55.830586 Setting up VGA for PCI: 00:02.0
1078 07:40:55.834005 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1079 07:40:55.840240 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1080 07:40:55.844016 Allocating resources...
1081 07:40:55.844368 Reading resources...
1082 07:40:55.850488 Root Device read_resources bus 0 link: 0
1083 07:40:55.853925 DOMAIN: 0000 read_resources bus 0 link: 0
1084 07:40:55.857276 PCI: 00:04.0 read_resources bus 1 link: 0
1085 07:40:55.864512 PCI: 00:04.0 read_resources bus 1 link: 0 done
1086 07:40:55.867804 PCI: 00:0d.0 read_resources bus 0 link: 0
1087 07:40:55.874639 USB0 port 0 read_resources bus 0 link: 0
1088 07:40:55.877590 USB0 port 0 read_resources bus 0 link: 0 done
1089 07:40:55.884270 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1090 07:40:55.887616 PCI: 00:14.0 read_resources bus 0 link: 0
1091 07:40:55.890877 USB0 port 0 read_resources bus 0 link: 0
1092 07:40:55.898934 USB0 port 0 read_resources bus 0 link: 0 done
1093 07:40:55.901844 PCI: 00:14.0 read_resources bus 0 link: 0 done
1094 07:40:55.908845 PCI: 00:14.3 read_resources bus 0 link: 0
1095 07:40:55.912289 PCI: 00:14.3 read_resources bus 0 link: 0 done
1096 07:40:55.919021 PCI: 00:15.0 read_resources bus 0 link: 0
1097 07:40:55.922195 PCI: 00:15.0 read_resources bus 0 link: 0 done
1098 07:40:55.928869 PCI: 00:15.1 read_resources bus 0 link: 0
1099 07:40:55.932216 PCI: 00:15.1 read_resources bus 0 link: 0 done
1100 07:40:55.939415 PCI: 00:19.1 read_resources bus 0 link: 0
1101 07:40:55.942633 PCI: 00:19.1 read_resources bus 0 link: 0 done
1102 07:40:55.949284 PCI: 00:1d.0 read_resources bus 1 link: 0
1103 07:40:55.952378 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1104 07:40:55.959174 PCI: 00:1e.2 read_resources bus 2 link: 0
1105 07:40:55.962623 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1106 07:40:55.969285 PCI: 00:1e.3 read_resources bus 3 link: 0
1107 07:40:55.972470 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1108 07:40:55.979410 PCI: 00:1f.0 read_resources bus 0 link: 0
1109 07:40:55.982727 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1110 07:40:55.985754 PCI: 00:1f.2 read_resources bus 0 link: 0
1111 07:40:55.992702 GENERIC: 0.0 read_resources bus 0 link: 0
1112 07:40:55.996168 GENERIC: 0.0 read_resources bus 0 link: 0 done
1113 07:40:56.002450 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1114 07:40:56.008776 DOMAIN: 0000 read_resources bus 0 link: 0 done
1115 07:40:56.012262 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1116 07:40:56.018779 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1117 07:40:56.021707 Root Device read_resources bus 0 link: 0 done
1118 07:40:56.025236 Done reading resources.
1119 07:40:56.028737 Show resources in subtree (Root Device)...After reading.
1120 07:40:56.035136 Root Device child on link 0 DOMAIN: 0000
1121 07:40:56.038620 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1122 07:40:56.048449 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1123 07:40:56.058216 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1124 07:40:56.058298 PCI: 00:00.0
1125 07:40:56.068360 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1126 07:40:56.078505 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1127 07:40:56.088311 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1128 07:40:56.098189 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1129 07:40:56.108232 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1130 07:40:56.115207 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1131 07:40:56.124697 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1132 07:40:56.135285 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1133 07:40:56.145271 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1134 07:40:56.155188 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1135 07:40:56.161535 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1136 07:40:56.171596 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1137 07:40:56.181513 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1138 07:40:56.191186 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1139 07:40:56.201134 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1140 07:40:56.211289 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1141 07:40:56.220993 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1142 07:40:56.227842 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1143 07:40:56.237794 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1144 07:40:56.247735 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1145 07:40:56.251225 PCI: 00:02.0
1146 07:40:56.261121 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1147 07:40:56.270629 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1148 07:40:56.277534 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1149 07:40:56.284196 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1150 07:40:56.294337 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1151 07:40:56.294834 GENERIC: 0.0
1152 07:40:56.297151 PCI: 00:05.0
1153 07:40:56.307470 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 07:40:56.310855 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1155 07:40:56.314205 GENERIC: 0.0
1156 07:40:56.314635 PCI: 00:08.0
1157 07:40:56.323600 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1158 07:40:56.327281 PCI: 00:0a.0
1159 07:40:56.330388 PCI: 00:0d.0 child on link 0 USB0 port 0
1160 07:40:56.340260 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1161 07:40:56.344016 USB0 port 0 child on link 0 USB3 port 0
1162 07:40:56.346887 USB3 port 0
1163 07:40:56.350414 USB3 port 1
1164 07:40:56.350857 USB3 port 2
1165 07:40:56.353886 USB3 port 3
1166 07:40:56.357339 PCI: 00:14.0 child on link 0 USB0 port 0
1167 07:40:56.367304 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 07:40:56.370309 USB0 port 0 child on link 0 USB2 port 0
1169 07:40:56.373772 USB2 port 0
1170 07:40:56.374234 USB2 port 1
1171 07:40:56.376972 USB2 port 2
1172 07:40:56.377384 USB2 port 3
1173 07:40:56.380573 USB2 port 4
1174 07:40:56.381072 USB2 port 5
1175 07:40:56.383291 USB2 port 6
1176 07:40:56.387119 USB2 port 7
1177 07:40:56.387534 USB2 port 8
1178 07:40:56.390435 USB2 port 9
1179 07:40:56.390849 USB3 port 0
1180 07:40:56.393713 USB3 port 1
1181 07:40:56.394130 USB3 port 2
1182 07:40:56.396971 USB3 port 3
1183 07:40:56.397384 PCI: 00:14.2
1184 07:40:56.407079 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1185 07:40:56.416978 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1186 07:40:56.423758 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1187 07:40:56.433681 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1188 07:40:56.434108 GENERIC: 0.0
1189 07:40:56.437115 PCI: 00:15.0 child on link 0 I2C: 00:1a
1190 07:40:56.446609 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1191 07:40:56.449770 I2C: 00:1a
1192 07:40:56.449850 I2C: 00:31
1193 07:40:56.452932 I2C: 00:32
1194 07:40:56.456460 PCI: 00:15.1 child on link 0 I2C: 00:10
1195 07:40:56.466102 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1196 07:40:56.469686 I2C: 00:10
1197 07:40:56.469766 PCI: 00:15.2
1198 07:40:56.479385 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1199 07:40:56.482701 PCI: 00:15.3
1200 07:40:56.492962 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 07:40:56.493057 PCI: 00:16.0
1202 07:40:56.503086 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 07:40:56.506021 PCI: 00:19.0
1204 07:40:56.509250 PCI: 00:19.1 child on link 0 I2C: 00:15
1205 07:40:56.519321 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 07:40:56.519404 I2C: 00:15
1207 07:40:56.526143 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1208 07:40:56.532416 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1209 07:40:56.542998 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1210 07:40:56.552871 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1211 07:40:56.552952 GENERIC: 0.0
1212 07:40:56.555901 PCI: 01:00.0
1213 07:40:56.565934 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1214 07:40:56.576111 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1215 07:40:56.586132 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1216 07:40:56.586221 PCI: 00:1e.0
1217 07:40:56.595937 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1218 07:40:56.602279 PCI: 00:1e.2 child on link 0 SPI: 00
1219 07:40:56.612671 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1220 07:40:56.612758 SPI: 00
1221 07:40:56.615732 PCI: 00:1e.3 child on link 0 SPI: 00
1222 07:40:56.625926 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1223 07:40:56.629210 SPI: 00
1224 07:40:56.632077 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1225 07:40:56.642348 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1226 07:40:56.642432 PNP: 0c09.0
1227 07:40:56.652285 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1228 07:40:56.655841 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1229 07:40:56.665803 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1230 07:40:56.675490 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1231 07:40:56.678893 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1232 07:40:56.682415 GENERIC: 0.0
1233 07:40:56.682558 GENERIC: 1.0
1234 07:40:56.685497 PCI: 00:1f.3
1235 07:40:56.695863 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1236 07:40:56.705521 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1237 07:40:56.705833 PCI: 00:1f.5
1238 07:40:56.715708 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1239 07:40:56.719393 CPU_CLUSTER: 0 child on link 0 APIC: 00
1240 07:40:56.722413 APIC: 00
1241 07:40:56.722869 APIC: 01
1242 07:40:56.723202 APIC: 03
1243 07:40:56.725595 APIC: 05
1244 07:40:56.726009 APIC: 07
1245 07:40:56.729308 APIC: 06
1246 07:40:56.729768 APIC: 02
1247 07:40:56.730101 APIC: 04
1248 07:40:56.738905 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1249 07:40:56.742042 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1250 07:40:56.749333 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1251 07:40:56.755704 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1252 07:40:56.759414 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1253 07:40:56.765642 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1254 07:40:56.769028 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1255 07:40:56.775775 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1256 07:40:56.782252 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1257 07:40:56.792294 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1258 07:40:56.798680 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1259 07:40:56.805728 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1260 07:40:56.812072 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1261 07:40:56.818974 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1262 07:40:56.825279 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1263 07:40:56.828749 DOMAIN: 0000: Resource ranges:
1264 07:40:56.835115 * Base: 1000, Size: 800, Tag: 100
1265 07:40:56.838390 * Base: 1900, Size: e700, Tag: 100
1266 07:40:56.841713 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1267 07:40:56.848731 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1268 07:40:56.855096 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1269 07:40:56.864814 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1270 07:40:56.871908 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1271 07:40:56.878371 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1272 07:40:56.888341 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1273 07:40:56.894815 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1274 07:40:56.901365 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1275 07:40:56.911645 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1276 07:40:56.918255 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1277 07:40:56.924586 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1278 07:40:56.934913 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1279 07:40:56.941221 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1280 07:40:56.948057 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1281 07:40:56.957724 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1282 07:40:56.964314 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1283 07:40:56.970928 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1284 07:40:56.977993 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1285 07:40:56.987685 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1286 07:40:56.994250 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1287 07:40:57.004038 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1288 07:40:57.010750 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1289 07:40:57.017123 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1290 07:40:57.023490 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1291 07:40:57.026933 DOMAIN: 0000: Resource ranges:
1292 07:40:57.033670 * Base: 7fc00000, Size: 40400000, Tag: 200
1293 07:40:57.036906 * Base: d0000000, Size: 28000000, Tag: 200
1294 07:40:57.040153 * Base: fa000000, Size: 1000000, Tag: 200
1295 07:40:57.046998 * Base: fb001000, Size: 2fff000, Tag: 200
1296 07:40:57.050442 * Base: fe010000, Size: 2e000, Tag: 200
1297 07:40:57.053670 * Base: fe03f000, Size: d41000, Tag: 200
1298 07:40:57.057151 * Base: fed88000, Size: 8000, Tag: 200
1299 07:40:57.063453 * Base: fed93000, Size: d000, Tag: 200
1300 07:40:57.067248 * Base: feda2000, Size: 1e000, Tag: 200
1301 07:40:57.070326 * Base: fede0000, Size: 1220000, Tag: 200
1302 07:40:57.076572 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1303 07:40:57.083675 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1304 07:40:57.090041 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1305 07:40:57.096898 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1306 07:40:57.103283 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1307 07:40:57.110149 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1308 07:40:57.116824 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1309 07:40:57.123330 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1310 07:40:57.129737 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1311 07:40:57.136627 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1312 07:40:57.142874 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1313 07:40:57.149447 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1314 07:40:57.156123 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1315 07:40:57.162917 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1316 07:40:57.169880 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1317 07:40:57.176250 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1318 07:40:57.183038 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1319 07:40:57.189339 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1320 07:40:57.195962 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1321 07:40:57.203014 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1322 07:40:57.209382 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1323 07:40:57.216294 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1324 07:40:57.222504 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1325 07:40:57.229380 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1326 07:40:57.236253 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1327 07:40:57.239084 PCI: 00:1d.0: Resource ranges:
1328 07:40:57.246113 * Base: 7fc00000, Size: 100000, Tag: 200
1329 07:40:57.252553 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1330 07:40:57.259314 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1331 07:40:57.265741 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1332 07:40:57.272692 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1333 07:40:57.279038 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1334 07:40:57.286040 Root Device assign_resources, bus 0 link: 0
1335 07:40:57.288982 DOMAIN: 0000 assign_resources, bus 0 link: 0
1336 07:40:57.299113 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1337 07:40:57.305882 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1338 07:40:57.312443 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1339 07:40:57.322349 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1340 07:40:57.325782 PCI: 00:04.0 assign_resources, bus 1 link: 0
1341 07:40:57.332057 PCI: 00:04.0 assign_resources, bus 1 link: 0
1342 07:40:57.339037 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1343 07:40:57.348779 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1344 07:40:57.355561 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1345 07:40:57.359100 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1346 07:40:57.366063 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1347 07:40:57.372635 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1348 07:40:57.379065 PCI: 00:14.0 assign_resources, bus 0 link: 0
1349 07:40:57.382258 PCI: 00:14.0 assign_resources, bus 0 link: 0
1350 07:40:57.392220 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1351 07:40:57.399109 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1352 07:40:57.405363 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1353 07:40:57.412216 PCI: 00:14.3 assign_resources, bus 0 link: 0
1354 07:40:57.415529 PCI: 00:14.3 assign_resources, bus 0 link: 0
1355 07:40:57.425866 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1356 07:40:57.428907 PCI: 00:15.0 assign_resources, bus 0 link: 0
1357 07:40:57.432277 PCI: 00:15.0 assign_resources, bus 0 link: 0
1358 07:40:57.442424 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1359 07:40:57.445887 PCI: 00:15.1 assign_resources, bus 0 link: 0
1360 07:40:57.452641 PCI: 00:15.1 assign_resources, bus 0 link: 0
1361 07:40:57.459004 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1362 07:40:57.468896 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1363 07:40:57.475789 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1364 07:40:57.485717 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1365 07:40:57.488955 PCI: 00:19.1 assign_resources, bus 0 link: 0
1366 07:40:57.492135 PCI: 00:19.1 assign_resources, bus 0 link: 0
1367 07:40:57.502487 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1368 07:40:57.512108 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1369 07:40:57.521922 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1370 07:40:57.525749 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1371 07:40:57.532229 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1372 07:40:57.541962 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1373 07:40:57.548704 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1374 07:40:57.555069 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1375 07:40:57.562204 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1376 07:40:57.565033 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1377 07:40:57.572041 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1378 07:40:57.578639 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1379 07:40:57.585278 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1380 07:40:57.588658 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1381 07:40:57.595502 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1382 07:40:57.598833 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1383 07:40:57.601810 LPC: Trying to open IO window from 800 size 1ff
1384 07:40:57.612423 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1385 07:40:57.618979 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1386 07:40:57.628630 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1387 07:40:57.631941 DOMAIN: 0000 assign_resources, bus 0 link: 0
1388 07:40:57.638788 Root Device assign_resources, bus 0 link: 0
1389 07:40:57.638870 Done setting resources.
1390 07:40:57.645225 Show resources in subtree (Root Device)...After assigning values.
1391 07:40:57.652176 Root Device child on link 0 DOMAIN: 0000
1392 07:40:57.655506 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1393 07:40:57.665379 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1394 07:40:57.675306 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1395 07:40:57.675390 PCI: 00:00.0
1396 07:40:57.685137 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1397 07:40:57.695466 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1398 07:40:57.705007 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1399 07:40:57.715039 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1400 07:40:57.722186 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1401 07:40:57.731465 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1402 07:40:57.741798 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1403 07:40:57.751748 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1404 07:40:57.761631 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1405 07:40:57.768426 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1406 07:40:57.777983 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1407 07:40:57.788481 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1408 07:40:57.797960 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1409 07:40:57.807816 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1410 07:40:57.814753 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1411 07:40:57.824476 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1412 07:40:57.834767 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1413 07:40:57.844546 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1414 07:40:57.854298 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1415 07:40:57.864663 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1416 07:40:57.864745 PCI: 00:02.0
1417 07:40:57.877437 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1418 07:40:57.887359 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1419 07:40:57.897795 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1420 07:40:57.900775 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1421 07:40:57.910991 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1422 07:40:57.914225 GENERIC: 0.0
1423 07:40:57.914307 PCI: 00:05.0
1424 07:40:57.923911 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1425 07:40:57.930907 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1426 07:40:57.930989 GENERIC: 0.0
1427 07:40:57.933784 PCI: 00:08.0
1428 07:40:57.944309 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1429 07:40:57.944423 PCI: 00:0a.0
1430 07:40:57.951012 PCI: 00:0d.0 child on link 0 USB0 port 0
1431 07:40:57.960882 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1432 07:40:57.964444 USB0 port 0 child on link 0 USB3 port 0
1433 07:40:57.967305 USB3 port 0
1434 07:40:57.967385 USB3 port 1
1435 07:40:57.970743 USB3 port 2
1436 07:40:57.970855 USB3 port 3
1437 07:40:57.977334 PCI: 00:14.0 child on link 0 USB0 port 0
1438 07:40:57.987396 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1439 07:40:57.990887 USB0 port 0 child on link 0 USB2 port 0
1440 07:40:57.993724 USB2 port 0
1441 07:40:57.993835 USB2 port 1
1442 07:40:57.997700 USB2 port 2
1443 07:40:57.997801 USB2 port 3
1444 07:40:58.000545 USB2 port 4
1445 07:40:58.000638 USB2 port 5
1446 07:40:58.003964 USB2 port 6
1447 07:40:58.004048 USB2 port 7
1448 07:40:58.007448 USB2 port 8
1449 07:40:58.007519 USB2 port 9
1450 07:40:58.010381 USB3 port 0
1451 07:40:58.010449 USB3 port 1
1452 07:40:58.013795 USB3 port 2
1453 07:40:58.013875 USB3 port 3
1454 07:40:58.017097 PCI: 00:14.2
1455 07:40:58.027463 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1456 07:40:58.037333 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1457 07:40:58.043514 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1458 07:40:58.053496 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1459 07:40:58.053594 GENERIC: 0.0
1460 07:40:58.060187 PCI: 00:15.0 child on link 0 I2C: 00:1a
1461 07:40:58.070562 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1462 07:40:58.070645 I2C: 00:1a
1463 07:40:58.073453 I2C: 00:31
1464 07:40:58.073554 I2C: 00:32
1465 07:40:58.076931 PCI: 00:15.1 child on link 0 I2C: 00:10
1466 07:40:58.086753 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1467 07:40:58.090291 I2C: 00:10
1468 07:40:58.090371 PCI: 00:15.2
1469 07:40:58.103650 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1470 07:40:58.103733 PCI: 00:15.3
1471 07:40:58.113328 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1472 07:40:58.116877 PCI: 00:16.0
1473 07:40:58.126332 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1474 07:40:58.126416 PCI: 00:19.0
1475 07:40:58.133398 PCI: 00:19.1 child on link 0 I2C: 00:15
1476 07:40:58.143266 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1477 07:40:58.143350 I2C: 00:15
1478 07:40:58.149703 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1479 07:40:58.156743 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1480 07:40:58.169997 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1481 07:40:58.179814 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1482 07:40:58.183285 GENERIC: 0.0
1483 07:40:58.183385 PCI: 01:00.0
1484 07:40:58.193226 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1485 07:40:58.203254 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1486 07:40:58.213064 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1487 07:40:58.215930 PCI: 00:1e.0
1488 07:40:58.226374 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1489 07:40:58.232843 PCI: 00:1e.2 child on link 0 SPI: 00
1490 07:40:58.242468 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1491 07:40:58.242578 SPI: 00
1492 07:40:58.246219 PCI: 00:1e.3 child on link 0 SPI: 00
1493 07:40:58.256006 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1494 07:40:58.259607 SPI: 00
1495 07:40:58.262485 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1496 07:40:58.272276 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1497 07:40:58.272360 PNP: 0c09.0
1498 07:40:58.282473 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1499 07:40:58.285687 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1500 07:40:58.296009 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1501 07:40:58.305856 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1502 07:40:58.308824 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1503 07:40:58.312282 GENERIC: 0.0
1504 07:40:58.312405 GENERIC: 1.0
1505 07:40:58.315731 PCI: 00:1f.3
1506 07:40:58.325596 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1507 07:40:58.335508 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1508 07:40:58.339088 PCI: 00:1f.5
1509 07:40:58.348661 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1510 07:40:58.352209 CPU_CLUSTER: 0 child on link 0 APIC: 00
1511 07:40:58.352324 APIC: 00
1512 07:40:58.355560 APIC: 01
1513 07:40:58.355650 APIC: 03
1514 07:40:58.358857 APIC: 05
1515 07:40:58.358940 APIC: 07
1516 07:40:58.359004 APIC: 06
1517 07:40:58.362044 APIC: 02
1518 07:40:58.362128 APIC: 04
1519 07:40:58.365855 Done allocating resources.
1520 07:40:58.372268 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1521 07:40:58.378720 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1522 07:40:58.382147 Configure GPIOs for I2S audio on UP4.
1523 07:40:58.388682 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1524 07:40:58.392174 Enabling resources...
1525 07:40:58.395467 PCI: 00:00.0 subsystem <- 8086/9a12
1526 07:40:58.395549 PCI: 00:00.0 cmd <- 06
1527 07:40:58.401951 PCI: 00:02.0 subsystem <- 8086/9a40
1528 07:40:58.402034 PCI: 00:02.0 cmd <- 03
1529 07:40:58.405049 PCI: 00:04.0 subsystem <- 8086/9a03
1530 07:40:58.408603 PCI: 00:04.0 cmd <- 02
1531 07:40:58.412152 PCI: 00:05.0 subsystem <- 8086/9a19
1532 07:40:58.415047 PCI: 00:05.0 cmd <- 02
1533 07:40:58.418527 PCI: 00:08.0 subsystem <- 8086/9a11
1534 07:40:58.422071 PCI: 00:08.0 cmd <- 06
1535 07:40:58.425050 PCI: 00:0d.0 subsystem <- 8086/9a13
1536 07:40:58.428486 PCI: 00:0d.0 cmd <- 02
1537 07:40:58.431944 PCI: 00:14.0 subsystem <- 8086/a0ed
1538 07:40:58.434944 PCI: 00:14.0 cmd <- 02
1539 07:40:58.438461 PCI: 00:14.2 subsystem <- 8086/a0ef
1540 07:40:58.441738 PCI: 00:14.2 cmd <- 02
1541 07:40:58.445254 PCI: 00:14.3 subsystem <- 8086/a0f0
1542 07:40:58.445365 PCI: 00:14.3 cmd <- 02
1543 07:40:58.451660 PCI: 00:15.0 subsystem <- 8086/a0e8
1544 07:40:58.451742 PCI: 00:15.0 cmd <- 02
1545 07:40:58.455011 PCI: 00:15.1 subsystem <- 8086/a0e9
1546 07:40:58.458232 PCI: 00:15.1 cmd <- 02
1547 07:40:58.461720 PCI: 00:15.2 subsystem <- 8086/a0ea
1548 07:40:58.465023 PCI: 00:15.2 cmd <- 02
1549 07:40:58.468355 PCI: 00:15.3 subsystem <- 8086/a0eb
1550 07:40:58.471668 PCI: 00:15.3 cmd <- 02
1551 07:40:58.475033 PCI: 00:16.0 subsystem <- 8086/a0e0
1552 07:40:58.478574 PCI: 00:16.0 cmd <- 02
1553 07:40:58.482009 PCI: 00:19.1 subsystem <- 8086/a0c6
1554 07:40:58.484939 PCI: 00:19.1 cmd <- 02
1555 07:40:58.488496 PCI: 00:1d.0 bridge ctrl <- 0013
1556 07:40:58.491392 PCI: 00:1d.0 subsystem <- 8086/a0b0
1557 07:40:58.491474 PCI: 00:1d.0 cmd <- 06
1558 07:40:58.498403 PCI: 00:1e.0 subsystem <- 8086/a0a8
1559 07:40:58.498497 PCI: 00:1e.0 cmd <- 06
1560 07:40:58.502040 PCI: 00:1e.2 subsystem <- 8086/a0aa
1561 07:40:58.504941 PCI: 00:1e.2 cmd <- 06
1562 07:40:58.508381 PCI: 00:1e.3 subsystem <- 8086/a0ab
1563 07:40:58.511599 PCI: 00:1e.3 cmd <- 02
1564 07:40:58.515159 PCI: 00:1f.0 subsystem <- 8086/a087
1565 07:40:58.518050 PCI: 00:1f.0 cmd <- 407
1566 07:40:58.521672 PCI: 00:1f.3 subsystem <- 8086/a0c8
1567 07:40:58.525009 PCI: 00:1f.3 cmd <- 02
1568 07:40:58.528617 PCI: 00:1f.5 subsystem <- 8086/a0a4
1569 07:40:58.531539 PCI: 00:1f.5 cmd <- 406
1570 07:40:58.535054 PCI: 01:00.0 cmd <- 02
1571 07:40:58.539763 done.
1572 07:40:58.542938 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1573 07:40:58.546323 Initializing devices...
1574 07:40:58.549213 Root Device init
1575 07:40:58.552619 Chrome EC: Set SMI mask to 0x0000000000000000
1576 07:40:58.559147 Chrome EC: clear events_b mask to 0x0000000000000000
1577 07:40:58.565923 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1578 07:40:58.569020 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1579 07:40:58.575999 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1580 07:40:58.582430 Chrome EC: Set WAKE mask to 0x0000000000000000
1581 07:40:58.585746 fw_config match found: DB_USB=USB3_ACTIVE
1582 07:40:58.592660 Configure Right Type-C port orientation for retimer
1583 07:40:58.595713 Root Device init finished in 43 msecs
1584 07:40:58.599134 PCI: 00:00.0 init
1585 07:40:58.602701 CPU TDP = 9 Watts
1586 07:40:58.602782 CPU PL1 = 9 Watts
1587 07:40:58.605524 CPU PL2 = 40 Watts
1588 07:40:58.609088 CPU PL4 = 83 Watts
1589 07:40:58.612647 PCI: 00:00.0 init finished in 8 msecs
1590 07:40:58.612727 PCI: 00:02.0 init
1591 07:40:58.615555 GMA: Found VBT in CBFS
1592 07:40:58.619056 GMA: Found valid VBT in CBFS
1593 07:40:58.625764 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1594 07:40:58.632528 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1595 07:40:58.636002 PCI: 00:02.0 init finished in 18 msecs
1596 07:40:58.638863 PCI: 00:05.0 init
1597 07:40:58.642351 PCI: 00:05.0 init finished in 0 msecs
1598 07:40:58.645722 PCI: 00:08.0 init
1599 07:40:58.648990 PCI: 00:08.0 init finished in 0 msecs
1600 07:40:58.652399 PCI: 00:14.0 init
1601 07:40:58.655511 PCI: 00:14.0 init finished in 0 msecs
1602 07:40:58.658957 PCI: 00:14.2 init
1603 07:40:58.662389 PCI: 00:14.2 init finished in 0 msecs
1604 07:40:58.662546 PCI: 00:15.0 init
1605 07:40:58.665696 I2C bus 0 version 0x3230302a
1606 07:40:58.669110 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1607 07:40:58.675468 PCI: 00:15.0 init finished in 6 msecs
1608 07:40:58.675630 PCI: 00:15.1 init
1609 07:40:58.678838 I2C bus 1 version 0x3230302a
1610 07:40:58.681983 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1611 07:40:58.685586 PCI: 00:15.1 init finished in 6 msecs
1612 07:40:58.688976 PCI: 00:15.2 init
1613 07:40:58.692150 I2C bus 2 version 0x3230302a
1614 07:40:58.695488 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1615 07:40:58.699050 PCI: 00:15.2 init finished in 6 msecs
1616 07:40:58.702474 PCI: 00:15.3 init
1617 07:40:58.705353 I2C bus 3 version 0x3230302a
1618 07:40:58.708888 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1619 07:40:58.712440 PCI: 00:15.3 init finished in 6 msecs
1620 07:40:58.715418 PCI: 00:16.0 init
1621 07:40:58.718854 PCI: 00:16.0 init finished in 0 msecs
1622 07:40:58.722294 PCI: 00:19.1 init
1623 07:40:58.722381 I2C bus 5 version 0x3230302a
1624 07:40:58.728723 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1625 07:40:58.732219 PCI: 00:19.1 init finished in 6 msecs
1626 07:40:58.732321 PCI: 00:1d.0 init
1627 07:40:58.735660 Initializing PCH PCIe bridge.
1628 07:40:58.738906 PCI: 00:1d.0 init finished in 3 msecs
1629 07:40:58.743209 PCI: 00:1f.0 init
1630 07:40:58.746486 IOAPIC: Initializing IOAPIC at 0xfec00000
1631 07:40:58.753102 IOAPIC: Bootstrap Processor Local APIC = 0x00
1632 07:40:58.753205 IOAPIC: ID = 0x02
1633 07:40:58.756665 IOAPIC: Dumping registers
1634 07:40:58.759485 reg 0x0000: 0x02000000
1635 07:40:58.762986 reg 0x0001: 0x00770020
1636 07:40:58.763084 reg 0x0002: 0x00000000
1637 07:40:58.769859 PCI: 00:1f.0 init finished in 21 msecs
1638 07:40:58.769936 PCI: 00:1f.2 init
1639 07:40:58.773024 Disabling ACPI via APMC.
1640 07:40:58.776452 APMC done.
1641 07:40:58.780055 PCI: 00:1f.2 init finished in 5 msecs
1642 07:40:58.791229 PCI: 01:00.0 init
1643 07:40:58.794511 PCI: 01:00.0 init finished in 0 msecs
1644 07:40:58.797773 PNP: 0c09.0 init
1645 07:40:58.801104 Google Chrome EC uptime: 8.393 seconds
1646 07:40:58.807898 Google Chrome AP resets since EC boot: 1
1647 07:40:58.811469 Google Chrome most recent AP reset causes:
1648 07:40:58.814392 0.348: 32775 shutdown: entering G3
1649 07:40:58.821243 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1650 07:40:58.824210 PNP: 0c09.0 init finished in 22 msecs
1651 07:40:58.830011 Devices initialized
1652 07:40:58.833512 Show all devs... After init.
1653 07:40:58.837077 Root Device: enabled 1
1654 07:40:58.837193 DOMAIN: 0000: enabled 1
1655 07:40:58.840028 CPU_CLUSTER: 0: enabled 1
1656 07:40:58.843473 PCI: 00:00.0: enabled 1
1657 07:40:58.846978 PCI: 00:02.0: enabled 1
1658 07:40:58.847064 PCI: 00:04.0: enabled 1
1659 07:40:58.850342 PCI: 00:05.0: enabled 1
1660 07:40:58.853596 PCI: 00:06.0: enabled 0
1661 07:40:58.856473 PCI: 00:07.0: enabled 0
1662 07:40:58.856556 PCI: 00:07.1: enabled 0
1663 07:40:58.860104 PCI: 00:07.2: enabled 0
1664 07:40:58.863048 PCI: 00:07.3: enabled 0
1665 07:40:58.866645 PCI: 00:08.0: enabled 1
1666 07:40:58.866753 PCI: 00:09.0: enabled 0
1667 07:40:58.870107 PCI: 00:0a.0: enabled 0
1668 07:40:58.872955 PCI: 00:0d.0: enabled 1
1669 07:40:58.876369 PCI: 00:0d.1: enabled 0
1670 07:40:58.876448 PCI: 00:0d.2: enabled 0
1671 07:40:58.879729 PCI: 00:0d.3: enabled 0
1672 07:40:58.883054 PCI: 00:0e.0: enabled 0
1673 07:40:58.886509 PCI: 00:10.2: enabled 1
1674 07:40:58.886592 PCI: 00:10.6: enabled 0
1675 07:40:58.890017 PCI: 00:10.7: enabled 0
1676 07:40:58.892782 PCI: 00:12.0: enabled 0
1677 07:40:58.892865 PCI: 00:12.6: enabled 0
1678 07:40:58.896192 PCI: 00:13.0: enabled 0
1679 07:40:58.899450 PCI: 00:14.0: enabled 1
1680 07:40:58.902919 PCI: 00:14.1: enabled 0
1681 07:40:58.903004 PCI: 00:14.2: enabled 1
1682 07:40:58.906291 PCI: 00:14.3: enabled 1
1683 07:40:58.909709 PCI: 00:15.0: enabled 1
1684 07:40:58.913040 PCI: 00:15.1: enabled 1
1685 07:40:58.913124 PCI: 00:15.2: enabled 1
1686 07:40:58.916403 PCI: 00:15.3: enabled 1
1687 07:40:58.919852 PCI: 00:16.0: enabled 1
1688 07:40:58.922757 PCI: 00:16.1: enabled 0
1689 07:40:58.922841 PCI: 00:16.2: enabled 0
1690 07:40:58.926239 PCI: 00:16.3: enabled 0
1691 07:40:58.929755 PCI: 00:16.4: enabled 0
1692 07:40:58.929838 PCI: 00:16.5: enabled 0
1693 07:40:58.932663 PCI: 00:17.0: enabled 0
1694 07:40:58.936171 PCI: 00:19.0: enabled 0
1695 07:40:58.939632 PCI: 00:19.1: enabled 1
1696 07:40:58.939715 PCI: 00:19.2: enabled 0
1697 07:40:58.943178 PCI: 00:1c.0: enabled 1
1698 07:40:58.945991 PCI: 00:1c.1: enabled 0
1699 07:40:58.949472 PCI: 00:1c.2: enabled 0
1700 07:40:58.949566 PCI: 00:1c.3: enabled 0
1701 07:40:58.952932 PCI: 00:1c.4: enabled 0
1702 07:40:58.955854 PCI: 00:1c.5: enabled 0
1703 07:40:58.959327 PCI: 00:1c.6: enabled 1
1704 07:40:58.959411 PCI: 00:1c.7: enabled 0
1705 07:40:58.962549 PCI: 00:1d.0: enabled 1
1706 07:40:58.966230 PCI: 00:1d.1: enabled 0
1707 07:40:58.969302 PCI: 00:1d.2: enabled 1
1708 07:40:58.969388 PCI: 00:1d.3: enabled 0
1709 07:40:58.972883 PCI: 00:1e.0: enabled 1
1710 07:40:58.975892 PCI: 00:1e.1: enabled 0
1711 07:40:58.975980 PCI: 00:1e.2: enabled 1
1712 07:40:58.979194 PCI: 00:1e.3: enabled 1
1713 07:40:58.982656 PCI: 00:1f.0: enabled 1
1714 07:40:58.985941 PCI: 00:1f.1: enabled 0
1715 07:40:58.986045 PCI: 00:1f.2: enabled 1
1716 07:40:58.989263 PCI: 00:1f.3: enabled 1
1717 07:40:58.992682 PCI: 00:1f.4: enabled 0
1718 07:40:58.996013 PCI: 00:1f.5: enabled 1
1719 07:40:58.996102 PCI: 00:1f.6: enabled 0
1720 07:40:58.999350 PCI: 00:1f.7: enabled 0
1721 07:40:59.002899 APIC: 00: enabled 1
1722 07:40:59.002988 GENERIC: 0.0: enabled 1
1723 07:40:59.006092 GENERIC: 0.0: enabled 1
1724 07:40:59.008995 GENERIC: 1.0: enabled 1
1725 07:40:59.012386 GENERIC: 0.0: enabled 1
1726 07:40:59.012470 GENERIC: 1.0: enabled 1
1727 07:40:59.015844 USB0 port 0: enabled 1
1728 07:40:59.019089 GENERIC: 0.0: enabled 1
1729 07:40:59.022413 USB0 port 0: enabled 1
1730 07:40:59.022524 GENERIC: 0.0: enabled 1
1731 07:40:59.025994 I2C: 00:1a: enabled 1
1732 07:40:59.029383 I2C: 00:31: enabled 1
1733 07:40:59.029529 I2C: 00:32: enabled 1
1734 07:40:59.032301 I2C: 00:10: enabled 1
1735 07:40:59.035748 I2C: 00:15: enabled 1
1736 07:40:59.035832 GENERIC: 0.0: enabled 0
1737 07:40:59.039164 GENERIC: 1.0: enabled 0
1738 07:40:59.042738 GENERIC: 0.0: enabled 1
1739 07:40:59.042822 SPI: 00: enabled 1
1740 07:40:59.045743 SPI: 00: enabled 1
1741 07:40:59.049132 PNP: 0c09.0: enabled 1
1742 07:40:59.049212 GENERIC: 0.0: enabled 1
1743 07:40:59.052539 USB3 port 0: enabled 1
1744 07:40:59.055590 USB3 port 1: enabled 1
1745 07:40:59.058952 USB3 port 2: enabled 0
1746 07:40:59.059032 USB3 port 3: enabled 0
1747 07:40:59.062460 USB2 port 0: enabled 0
1748 07:40:59.065904 USB2 port 1: enabled 1
1749 07:40:59.065984 USB2 port 2: enabled 1
1750 07:40:59.068802 USB2 port 3: enabled 0
1751 07:40:59.072226 USB2 port 4: enabled 1
1752 07:40:59.075706 USB2 port 5: enabled 0
1753 07:40:59.075787 USB2 port 6: enabled 0
1754 07:40:59.078744 USB2 port 7: enabled 0
1755 07:40:59.082315 USB2 port 8: enabled 0
1756 07:40:59.082395 USB2 port 9: enabled 0
1757 07:40:59.085363 USB3 port 0: enabled 0
1758 07:40:59.088631 USB3 port 1: enabled 1
1759 07:40:59.088711 USB3 port 2: enabled 0
1760 07:40:59.092404 USB3 port 3: enabled 0
1761 07:40:59.095716 GENERIC: 0.0: enabled 1
1762 07:40:59.098857 GENERIC: 1.0: enabled 1
1763 07:40:59.098946 APIC: 01: enabled 1
1764 07:40:59.102052 APIC: 03: enabled 1
1765 07:40:59.102136 APIC: 05: enabled 1
1766 07:40:59.105357 APIC: 07: enabled 1
1767 07:40:59.108726 APIC: 06: enabled 1
1768 07:40:59.108809 APIC: 02: enabled 1
1769 07:40:59.112091 APIC: 04: enabled 1
1770 07:40:59.115563 PCI: 01:00.0: enabled 1
1771 07:40:59.118985 BS: BS_DEV_INIT run times (exec / console): 30 / 540 ms
1772 07:40:59.125209 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1773 07:40:59.128406 ELOG: NV offset 0xf30000 size 0x1000
1774 07:40:59.135417 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1775 07:40:59.141977 ELOG: Event(17) added with size 13 at 2024-01-03 07:40:59 UTC
1776 07:40:59.149050 ELOG: Event(92) added with size 9 at 2024-01-03 07:40:59 UTC
1777 07:40:59.155209 ELOG: Event(93) added with size 9 at 2024-01-03 07:40:59 UTC
1778 07:40:59.162172 ELOG: Event(9E) added with size 10 at 2024-01-03 07:40:59 UTC
1779 07:40:59.168632 ELOG: Event(9F) added with size 14 at 2024-01-03 07:40:59 UTC
1780 07:40:59.175089 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1781 07:40:59.178573 ELOG: Event(A1) added with size 10 at 2024-01-03 07:40:59 UTC
1782 07:40:59.185156 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1783 07:40:59.191481 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1784 07:40:59.195271 Finalize devices...
1785 07:40:59.195388 Devices finalized
1786 07:40:59.201889 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1787 07:40:59.205146 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1788 07:40:59.211732 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1789 07:40:59.218646 ME: HFSTS1 : 0x80030055
1790 07:40:59.221645 ME: HFSTS2 : 0x30280116
1791 07:40:59.225041 ME: HFSTS3 : 0x00000050
1792 07:40:59.231699 ME: HFSTS4 : 0x00004000
1793 07:40:59.234933 ME: HFSTS5 : 0x00000000
1794 07:40:59.238282 ME: HFSTS6 : 0x00400006
1795 07:40:59.241847 ME: Manufacturing Mode : YES
1796 07:40:59.248154 ME: SPI Protection Mode Enabled : NO
1797 07:40:59.251688 ME: FW Partition Table : OK
1798 07:40:59.255026 ME: Bringup Loader Failure : NO
1799 07:40:59.258526 ME: Firmware Init Complete : NO
1800 07:40:59.261388 ME: Boot Options Present : NO
1801 07:40:59.264908 ME: Update In Progress : NO
1802 07:40:59.268387 ME: D0i3 Support : YES
1803 07:40:59.271346 ME: Low Power State Enabled : NO
1804 07:40:59.278352 ME: CPU Replaced : YES
1805 07:40:59.281174 ME: CPU Replacement Valid : YES
1806 07:40:59.284814 ME: Current Working State : 5
1807 07:40:59.288368 ME: Current Operation State : 1
1808 07:40:59.291223 ME: Current Operation Mode : 3
1809 07:40:59.294527 ME: Error Code : 0
1810 07:40:59.297995 ME: Enhanced Debug Mode : NO
1811 07:40:59.301411 ME: CPU Debug Disabled : YES
1812 07:40:59.304602 ME: TXT Support : NO
1813 07:40:59.311447 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1814 07:40:59.321403 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1815 07:40:59.324710 CBFS: 'fallback/slic' not found.
1816 07:40:59.327914 ACPI: Writing ACPI tables at 76b01000.
1817 07:40:59.328031 ACPI: * FACS
1818 07:40:59.331272 ACPI: * DSDT
1819 07:40:59.334659 Ramoops buffer: 0x100000@0x76a00000.
1820 07:40:59.337920 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1821 07:40:59.344320 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1822 07:40:59.347992 Google Chrome EC: version:
1823 07:40:59.351108 ro: voema_v2.0.7540-147f8d37d1
1824 07:40:59.354563 rw: voema_v2.0.7540-147f8d37d1
1825 07:40:59.357891 running image: 2
1826 07:40:59.364205 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1827 07:40:59.367838 ACPI: * FADT
1828 07:40:59.367942 SCI is IRQ9
1829 07:40:59.370728 ACPI: added table 1/32, length now 40
1830 07:40:59.374170 ACPI: * SSDT
1831 07:40:59.377605 Found 1 CPU(s) with 8 core(s) each.
1832 07:40:59.381109 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1833 07:40:59.387422 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1834 07:40:59.390881 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1835 07:40:59.394384 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1836 07:40:59.400643 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1837 07:40:59.407457 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1838 07:40:59.410451 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1839 07:40:59.417200 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1840 07:40:59.423727 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1841 07:40:59.427119 \_SB.PCI0.RP09: Added StorageD3Enable property
1842 07:40:59.430060 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1843 07:40:59.437188 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1844 07:40:59.443914 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1845 07:40:59.446831 PS2K: Passing 80 keymaps to kernel
1846 07:40:59.453734 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1847 07:40:59.460241 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1848 07:40:59.466789 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1849 07:40:59.470382 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1850 07:40:59.476803 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1851 07:40:59.483701 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1852 07:40:59.490089 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1853 07:40:59.496522 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1854 07:40:59.503287 ACPI: added table 2/32, length now 44
1855 07:40:59.503372 ACPI: * MCFG
1856 07:40:59.506755 ACPI: added table 3/32, length now 48
1857 07:40:59.510162 ACPI: * TPM2
1858 07:40:59.513236 TPM2 log created at 0x769f0000
1859 07:40:59.516707 ACPI: added table 4/32, length now 52
1860 07:40:59.516807 ACPI: * MADT
1861 07:40:59.519975 SCI is IRQ9
1862 07:40:59.523552 ACPI: added table 5/32, length now 56
1863 07:40:59.523682 current = 76b09850
1864 07:40:59.526471 ACPI: * DMAR
1865 07:40:59.529953 ACPI: added table 6/32, length now 60
1866 07:40:59.532862 ACPI: added table 7/32, length now 64
1867 07:40:59.536338 ACPI: * HPET
1868 07:40:59.539851 ACPI: added table 8/32, length now 68
1869 07:40:59.539949 ACPI: done.
1870 07:40:59.543301 ACPI tables: 35216 bytes.
1871 07:40:59.546618 smbios_write_tables: 769ef000
1872 07:40:59.549930 EC returned error result code 3
1873 07:40:59.552822 Couldn't obtain OEM name from CBI
1874 07:40:59.556346 Create SMBIOS type 16
1875 07:40:59.559797 Create SMBIOS type 17
1876 07:40:59.559931 GENERIC: 0.0 (WIFI Device)
1877 07:40:59.562872 SMBIOS tables: 1750 bytes.
1878 07:40:59.569752 Writing table forward entry at 0x00000500
1879 07:40:59.573023 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1880 07:40:59.579698 Writing coreboot table at 0x76b25000
1881 07:40:59.582886 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1882 07:40:59.589352 1. 0000000000001000-000000000009ffff: RAM
1883 07:40:59.592633 2. 00000000000a0000-00000000000fffff: RESERVED
1884 07:40:59.596177 3. 0000000000100000-00000000769eefff: RAM
1885 07:40:59.602683 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1886 07:40:59.609421 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1887 07:40:59.612815 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1888 07:40:59.619432 7. 0000000077000000-000000007fbfffff: RESERVED
1889 07:40:59.622899 8. 00000000c0000000-00000000cfffffff: RESERVED
1890 07:40:59.629178 9. 00000000f8000000-00000000f9ffffff: RESERVED
1891 07:40:59.632714 10. 00000000fb000000-00000000fb000fff: RESERVED
1892 07:40:59.639641 11. 00000000fe000000-00000000fe00ffff: RESERVED
1893 07:40:59.642447 12. 00000000fed80000-00000000fed87fff: RESERVED
1894 07:40:59.645945 13. 00000000fed90000-00000000fed92fff: RESERVED
1895 07:40:59.652282 14. 00000000feda0000-00000000feda1fff: RESERVED
1896 07:40:59.655661 15. 00000000fedc0000-00000000feddffff: RESERVED
1897 07:40:59.662812 16. 0000000100000000-00000002803fffff: RAM
1898 07:40:59.662900 Passing 4 GPIOs to payload:
1899 07:40:59.669320 NAME | PORT | POLARITY | VALUE
1900 07:40:59.675968 lid | undefined | high | high
1901 07:40:59.678920 power | undefined | high | low
1902 07:40:59.685605 oprom | undefined | high | low
1903 07:40:59.689079 EC in RW | 0x000000e5 | high | high
1904 07:40:59.695651 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum c62a
1905 07:40:59.698846 coreboot table: 1576 bytes.
1906 07:40:59.702433 IMD ROOT 0. 0x76fff000 0x00001000
1907 07:40:59.705632 IMD SMALL 1. 0x76ffe000 0x00001000
1908 07:40:59.712702 FSP MEMORY 2. 0x76c4e000 0x003b0000
1909 07:40:59.715946 VPD 3. 0x76c4d000 0x00000367
1910 07:40:59.719359 RO MCACHE 4. 0x76c4c000 0x00000fdc
1911 07:40:59.722114 CONSOLE 5. 0x76c2c000 0x00020000
1912 07:40:59.725785 FMAP 6. 0x76c2b000 0x00000578
1913 07:40:59.729184 TIME STAMP 7. 0x76c2a000 0x00000910
1914 07:40:59.732581 VBOOT WORK 8. 0x76c16000 0x00014000
1915 07:40:59.735550 ROMSTG STCK 9. 0x76c15000 0x00001000
1916 07:40:59.739119 AFTER CAR 10. 0x76c0a000 0x0000b000
1917 07:40:59.745921 RAMSTAGE 11. 0x76b97000 0x00073000
1918 07:40:59.748821 REFCODE 12. 0x76b42000 0x00055000
1919 07:40:59.752269 SMM BACKUP 13. 0x76b32000 0x00010000
1920 07:40:59.755865 4f444749 14. 0x76b30000 0x00002000
1921 07:40:59.759189 EXT VBT15. 0x76b2d000 0x0000219f
1922 07:40:59.762150 COREBOOT 16. 0x76b25000 0x00008000
1923 07:40:59.765670 ACPI 17. 0x76b01000 0x00024000
1924 07:40:59.769023 ACPI GNVS 18. 0x76b00000 0x00001000
1925 07:40:59.772565 RAMOOPS 19. 0x76a00000 0x00100000
1926 07:40:59.779000 TPM2 TCGLOG20. 0x769f0000 0x00010000
1927 07:40:59.782518 SMBIOS 21. 0x769ef000 0x00000800
1928 07:40:59.782599 IMD small region:
1929 07:40:59.785981 IMD ROOT 0. 0x76ffec00 0x00000400
1930 07:40:59.792171 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1931 07:40:59.795543 POWER STATE 2. 0x76ffeb80 0x00000044
1932 07:40:59.799176 ROMSTAGE 3. 0x76ffeb60 0x00000004
1933 07:40:59.802626 MEM INFO 4. 0x76ffe980 0x000001e0
1934 07:40:59.809289 BS: BS_WRITE_TABLES run times (exec / console): 6 / 484 ms
1935 07:40:59.812474 MTRR: Physical address space:
1936 07:40:59.819209 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1937 07:40:59.825437 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1938 07:40:59.828714 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1939 07:40:59.835749 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1940 07:40:59.842088 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1941 07:40:59.849118 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1942 07:40:59.855318 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1943 07:40:59.858761 MTRR: Fixed MSR 0x250 0x0606060606060606
1944 07:40:59.862222 MTRR: Fixed MSR 0x258 0x0606060606060606
1945 07:40:59.868507 MTRR: Fixed MSR 0x259 0x0000000000000000
1946 07:40:59.872002 MTRR: Fixed MSR 0x268 0x0606060606060606
1947 07:40:59.875533 MTRR: Fixed MSR 0x269 0x0606060606060606
1948 07:40:59.878474 MTRR: Fixed MSR 0x26a 0x0606060606060606
1949 07:40:59.885403 MTRR: Fixed MSR 0x26b 0x0606060606060606
1950 07:40:59.888937 MTRR: Fixed MSR 0x26c 0x0606060606060606
1951 07:40:59.891799 MTRR: Fixed MSR 0x26d 0x0606060606060606
1952 07:40:59.895149 MTRR: Fixed MSR 0x26e 0x0606060606060606
1953 07:40:59.901965 MTRR: Fixed MSR 0x26f 0x0606060606060606
1954 07:40:59.905381 call enable_fixed_mtrr()
1955 07:40:59.908311 CPU physical address size: 39 bits
1956 07:40:59.911774 MTRR: default type WB/UC MTRR counts: 6/6.
1957 07:40:59.915293 MTRR: UC selected as default type.
1958 07:40:59.921662 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1959 07:40:59.928394 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1960 07:40:59.935172 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1961 07:40:59.941696 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1962 07:40:59.948389 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1963 07:40:59.951380 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1964 07:40:59.956453
1965 07:40:59.956534 MTRR check
1966 07:40:59.959793 Fixed MTRRs : Enabled
1967 07:40:59.959875 Variable MTRRs: Enabled
1968 07:40:59.959939
1969 07:40:59.966026 MTRR: Fixed MSR 0x250 0x0606060606060606
1970 07:40:59.969375 MTRR: Fixed MSR 0x258 0x0606060606060606
1971 07:40:59.972937 MTRR: Fixed MSR 0x259 0x0000000000000000
1972 07:40:59.975846 MTRR: Fixed MSR 0x268 0x0606060606060606
1973 07:40:59.982738 MTRR: Fixed MSR 0x269 0x0606060606060606
1974 07:40:59.986238 MTRR: Fixed MSR 0x26a 0x0606060606060606
1975 07:40:59.989053 MTRR: Fixed MSR 0x26b 0x0606060606060606
1976 07:40:59.992527 MTRR: Fixed MSR 0x26c 0x0606060606060606
1977 07:40:59.999330 MTRR: Fixed MSR 0x26d 0x0606060606060606
1978 07:41:00.002682 MTRR: Fixed MSR 0x26e 0x0606060606060606
1979 07:41:00.006091 MTRR: Fixed MSR 0x26f 0x0606060606060606
1980 07:41:00.012681 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1981 07:41:00.016076 call enable_fixed_mtrr()
1982 07:41:00.019558 Checking cr50 for pending updates
1983 07:41:00.023400 CPU physical address size: 39 bits
1984 07:41:00.026303 MTRR: Fixed MSR 0x250 0x0606060606060606
1985 07:41:00.029719 MTRR: Fixed MSR 0x250 0x0606060606060606
1986 07:41:00.033222 MTRR: Fixed MSR 0x258 0x0606060606060606
1987 07:41:00.039611 MTRR: Fixed MSR 0x259 0x0000000000000000
1988 07:41:00.043151 MTRR: Fixed MSR 0x268 0x0606060606060606
1989 07:41:00.046471 MTRR: Fixed MSR 0x269 0x0606060606060606
1990 07:41:00.049643 MTRR: Fixed MSR 0x26a 0x0606060606060606
1991 07:41:00.056683 MTRR: Fixed MSR 0x26b 0x0606060606060606
1992 07:41:00.059828 MTRR: Fixed MSR 0x26c 0x0606060606060606
1993 07:41:00.063069 MTRR: Fixed MSR 0x26d 0x0606060606060606
1994 07:41:00.066246 MTRR: Fixed MSR 0x26e 0x0606060606060606
1995 07:41:00.073016 MTRR: Fixed MSR 0x26f 0x0606060606060606
1996 07:41:00.076472 MTRR: Fixed MSR 0x258 0x0606060606060606
1997 07:41:00.079809 call enable_fixed_mtrr()
1998 07:41:00.082678 MTRR: Fixed MSR 0x259 0x0000000000000000
1999 07:41:00.086196 MTRR: Fixed MSR 0x268 0x0606060606060606
2000 07:41:00.092660 MTRR: Fixed MSR 0x269 0x0606060606060606
2001 07:41:00.096213 MTRR: Fixed MSR 0x26a 0x0606060606060606
2002 07:41:00.099745 MTRR: Fixed MSR 0x26b 0x0606060606060606
2003 07:41:00.102676 MTRR: Fixed MSR 0x26c 0x0606060606060606
2004 07:41:00.109459 MTRR: Fixed MSR 0x26d 0x0606060606060606
2005 07:41:00.113050 MTRR: Fixed MSR 0x26e 0x0606060606060606
2006 07:41:00.115966 MTRR: Fixed MSR 0x26f 0x0606060606060606
2007 07:41:00.119394 CPU physical address size: 39 bits
2008 07:41:00.124022 call enable_fixed_mtrr()
2009 07:41:00.127362 MTRR: Fixed MSR 0x250 0x0606060606060606
2010 07:41:00.133648 MTRR: Fixed MSR 0x250 0x0606060606060606
2011 07:41:00.137212 MTRR: Fixed MSR 0x258 0x0606060606060606
2012 07:41:00.140709 MTRR: Fixed MSR 0x259 0x0000000000000000
2013 07:41:00.143627 MTRR: Fixed MSR 0x268 0x0606060606060606
2014 07:41:00.150476 MTRR: Fixed MSR 0x269 0x0606060606060606
2015 07:41:00.153698 MTRR: Fixed MSR 0x26a 0x0606060606060606
2016 07:41:00.157011 MTRR: Fixed MSR 0x26b 0x0606060606060606
2017 07:41:00.160531 MTRR: Fixed MSR 0x26c 0x0606060606060606
2018 07:41:00.167011 MTRR: Fixed MSR 0x26d 0x0606060606060606
2019 07:41:00.170627 MTRR: Fixed MSR 0x26e 0x0606060606060606
2020 07:41:00.173391 MTRR: Fixed MSR 0x26f 0x0606060606060606
2021 07:41:00.180544 MTRR: Fixed MSR 0x258 0x0606060606060606
2022 07:41:00.180643 call enable_fixed_mtrr()
2023 07:41:00.186998 MTRR: Fixed MSR 0x259 0x0000000000000000
2024 07:41:00.190365 MTRR: Fixed MSR 0x268 0x0606060606060606
2025 07:41:00.193380 MTRR: Fixed MSR 0x269 0x0606060606060606
2026 07:41:00.196937 MTRR: Fixed MSR 0x26a 0x0606060606060606
2027 07:41:00.203125 MTRR: Fixed MSR 0x26b 0x0606060606060606
2028 07:41:00.206867 MTRR: Fixed MSR 0x26c 0x0606060606060606
2029 07:41:00.210113 MTRR: Fixed MSR 0x26d 0x0606060606060606
2030 07:41:00.213685 MTRR: Fixed MSR 0x26e 0x0606060606060606
2031 07:41:00.216498 MTRR: Fixed MSR 0x26f 0x0606060606060606
2032 07:41:00.222960 CPU physical address size: 39 bits
2033 07:41:00.226426 call enable_fixed_mtrr()
2034 07:41:00.230514 Reading cr50 TPM mode
2035 07:41:00.234089 CPU physical address size: 39 bits
2036 07:41:00.234172 CPU physical address size: 39 bits
2037 07:41:00.240437 BS: BS_PAYLOAD_LOAD entry times (exec / console): 214 / 6 ms
2038 07:41:00.247372 MTRR: Fixed MSR 0x250 0x0606060606060606
2039 07:41:00.250445 MTRR: Fixed MSR 0x250 0x0606060606060606
2040 07:41:00.253904 MTRR: Fixed MSR 0x258 0x0606060606060606
2041 07:41:00.257298 MTRR: Fixed MSR 0x259 0x0000000000000000
2042 07:41:00.260692 MTRR: Fixed MSR 0x268 0x0606060606060606
2043 07:41:00.267099 MTRR: Fixed MSR 0x269 0x0606060606060606
2044 07:41:00.270665 MTRR: Fixed MSR 0x26a 0x0606060606060606
2045 07:41:00.273519 MTRR: Fixed MSR 0x26b 0x0606060606060606
2046 07:41:00.277061 MTRR: Fixed MSR 0x26c 0x0606060606060606
2047 07:41:00.283452 MTRR: Fixed MSR 0x26d 0x0606060606060606
2048 07:41:00.287045 MTRR: Fixed MSR 0x26e 0x0606060606060606
2049 07:41:00.290610 MTRR: Fixed MSR 0x26f 0x0606060606060606
2050 07:41:00.296925 MTRR: Fixed MSR 0x258 0x0606060606060606
2051 07:41:00.297011 call enable_fixed_mtrr()
2052 07:41:00.303509 MTRR: Fixed MSR 0x259 0x0000000000000000
2053 07:41:00.306768 MTRR: Fixed MSR 0x268 0x0606060606060606
2054 07:41:00.310462 MTRR: Fixed MSR 0x269 0x0606060606060606
2055 07:41:00.313502 MTRR: Fixed MSR 0x26a 0x0606060606060606
2056 07:41:00.320306 MTRR: Fixed MSR 0x26b 0x0606060606060606
2057 07:41:00.323600 MTRR: Fixed MSR 0x26c 0x0606060606060606
2058 07:41:00.326827 MTRR: Fixed MSR 0x26d 0x0606060606060606
2059 07:41:00.330508 MTRR: Fixed MSR 0x26e 0x0606060606060606
2060 07:41:00.336885 MTRR: Fixed MSR 0x26f 0x0606060606060606
2061 07:41:00.340164 CPU physical address size: 39 bits
2062 07:41:00.343694 call enable_fixed_mtrr()
2063 07:41:00.350286 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2064 07:41:00.353049 CPU physical address size: 39 bits
2065 07:41:00.360041 Checking segment from ROM address 0xffc02b38
2066 07:41:00.363308 Checking segment from ROM address 0xffc02b54
2067 07:41:00.366639 Loading segment from ROM address 0xffc02b38
2068 07:41:00.370119 code (compression=0)
2069 07:41:00.380114 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2070 07:41:00.386500 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2071 07:41:00.389993 it's not compressed!
2072 07:41:00.528721 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2073 07:41:00.534996 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2074 07:41:00.541879 Loading segment from ROM address 0xffc02b54
2075 07:41:00.541964 Entry Point 0x30000000
2076 07:41:00.545445 Loaded segments
2077 07:41:00.551768 BS: BS_PAYLOAD_LOAD run times (exec / console): 241 / 63 ms
2078 07:41:00.594703 Finalizing chipset.
2079 07:41:00.597768 Finalizing SMM.
2080 07:41:00.597863 APMC done.
2081 07:41:00.604642 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2082 07:41:00.607695 mp_park_aps done after 0 msecs.
2083 07:41:00.611267 Jumping to boot code at 0x30000000(0x76b25000)
2084 07:41:00.620974 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2085 07:41:00.621058
2086 07:41:00.621122
2087 07:41:00.621195
2088 07:41:00.624189 Starting depthcharge on Voema...
2089 07:41:00.624281
2090 07:41:00.624629 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2091 07:41:00.624731 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2092 07:41:00.624812 Setting prompt string to ['volteer:']
2093 07:41:00.624888 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2094 07:41:00.634216 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2095 07:41:00.634305
2096 07:41:00.641368 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2097 07:41:00.641450
2098 07:41:00.647651 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2099 07:41:00.647733
2100 07:41:00.650661 Failed to find eMMC card reader
2101 07:41:00.650743
2102 07:41:00.650808 Wipe memory regions:
2103 07:41:00.650868
2104 07:41:00.657620 [0x00000000001000, 0x000000000a0000)
2105 07:41:00.657702
2106 07:41:00.660884 [0x00000000100000, 0x00000030000000)
2107 07:41:00.686248
2108 07:41:00.689365 [0x00000032662db0, 0x000000769ef000)
2109 07:41:00.725186
2110 07:41:00.728465 [0x00000100000000, 0x00000280400000)
2111 07:41:00.930201
2112 07:41:00.933176 ec_init: CrosEC protocol v3 supported (256, 256)
2113 07:41:00.933263
2114 07:41:00.939964 update_port_state: port C0 state: usb enable 1 mux conn 0
2115 07:41:00.940048
2116 07:41:00.950203 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2117 07:41:00.950288
2118 07:41:00.953058 pmc_check_ipc_sts: STS_BUSY done after 1513 us
2119 07:41:00.953160
2120 07:41:00.959754 send_conn_disc_msg: pmc_send_cmd succeeded
2121 07:41:01.391044
2122 07:41:01.391181 R8152: Initializing
2123 07:41:01.391248
2124 07:41:01.394284 Version 6 (ocp_data = 5c30)
2125 07:41:01.394366
2126 07:41:01.397750 R8152: Done initializing
2127 07:41:01.397847
2128 07:41:01.400828 Adding net device
2129 07:41:01.702592
2130 07:41:01.706121 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2131 07:41:01.706212
2132 07:41:01.706276
2133 07:41:01.706350
2134 07:41:01.709300 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2136 07:41:01.809715 volteer: tftpboot 192.168.201.1 12435165/tftp-deploy-thjgx_1y/kernel/bzImage 12435165/tftp-deploy-thjgx_1y/kernel/cmdline 12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
2137 07:41:01.809891 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2138 07:41:01.809984 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2139 07:41:01.814582 tftpboot 192.168.201.1 12435165/tftp-deploy-thjgx_1y/kernel/bzIploy-thjgx_1y/kernel/cmdline 12435165/tftp-deploy-thjgx_1y/ramdisk/ramdisk.cpio.gz
2140 07:41:01.814670
2141 07:41:01.814734 Waiting for link
2142 07:41:02.019520
2143 07:41:02.019649 done.
2144 07:41:02.019721
2145 07:41:02.019787 MAC: 00:24:32:30:7c:e4
2146 07:41:02.019847
2147 07:41:02.022485 Sending DHCP discover... done.
2148 07:41:02.022561
2149 07:41:02.026014 Waiting for reply... done.
2150 07:41:02.026092
2151 07:41:02.028942 Sending DHCP request... done.
2152 07:41:02.029020
2153 07:41:02.032421 Waiting for reply... done.
2154 07:41:02.032504
2155 07:41:02.035972 My ip is 192.168.201.23
2156 07:41:02.036050
2157 07:41:02.039320 The DHCP server ip is 192.168.201.1
2158 07:41:02.039398
2159 07:41:02.046013 TFTP server IP predefined by user: 192.168.201.1
2160 07:41:02.046121
2161 07:41:02.052446 Bootfile predefined by user: 12435165/tftp-deploy-thjgx_1y/kernel/bzImage
2162 07:41:02.052530
2163 07:41:02.055499 Sending tftp read request... done.
2164 07:41:02.055589
2165 07:41:02.058993 Waiting for the transfer...
2166 07:41:02.059078
2167 07:41:02.701204 00000000 ################################################################
2168 07:41:02.701345
2169 07:41:03.342233 00080000 ################################################################
2170 07:41:03.342369
2171 07:41:03.986802 00100000 ################################################################
2172 07:41:03.986970
2173 07:41:04.625391 00180000 ################################################################
2174 07:41:04.625547
2175 07:41:05.261714 00200000 ################################################################
2176 07:41:05.261852
2177 07:41:05.781631 00280000 ################################################################
2178 07:41:05.781758
2179 07:41:06.299987 00300000 ################################################################
2180 07:41:06.300149
2181 07:41:06.843916 00380000 ################################################################
2182 07:41:06.844062
2183 07:41:07.380902 00400000 ################################################################
2184 07:41:07.381045
2185 07:41:07.921733 00480000 ################################################################
2186 07:41:07.921867
2187 07:41:08.535960 00500000 ################################################################
2188 07:41:08.536131
2189 07:41:09.169743 00580000 ################################################################
2190 07:41:09.169904
2191 07:41:09.761749 00600000 ################################################################
2192 07:41:09.761893
2193 07:41:10.280015 00680000 ################################################################
2194 07:41:10.280179
2195 07:41:10.805571 00700000 ################################################################
2196 07:41:10.805741
2197 07:41:11.321649 00780000 ################################################################
2198 07:41:11.321788
2199 07:41:11.503606 00800000 ####################### done.
2200 07:41:11.503738
2201 07:41:11.507086 The bootfile was 8572816 bytes long.
2202 07:41:11.507176
2203 07:41:11.510485 Sending tftp read request... done.
2204 07:41:11.510564
2205 07:41:11.513940 Waiting for the transfer...
2206 07:41:11.514020
2207 07:41:12.031354 00000000 ################################################################
2208 07:41:12.031493
2209 07:41:12.553817 00080000 ################################################################
2210 07:41:12.553951
2211 07:41:13.071904 00100000 ################################################################
2212 07:41:13.072088
2213 07:41:13.593876 00180000 ################################################################
2214 07:41:13.594037
2215 07:41:14.111360 00200000 ################################################################
2216 07:41:14.111492
2217 07:41:14.630058 00280000 ################################################################
2218 07:41:14.630197
2219 07:41:15.152731 00300000 ################################################################
2220 07:41:15.152872
2221 07:41:15.675904 00380000 ################################################################
2222 07:41:15.676052
2223 07:41:16.194734 00400000 ################################################################
2224 07:41:16.194864
2225 07:41:16.711299 00480000 ################################################################
2226 07:41:16.711496
2227 07:41:17.234406 00500000 ################################################################
2228 07:41:17.234548
2229 07:41:17.755325 00580000 ################################################################
2230 07:41:17.755481
2231 07:41:18.283650 00600000 ################################################################
2232 07:41:18.283827
2233 07:41:18.798652 00680000 ################################################################
2234 07:41:18.798828
2235 07:41:19.312751 00700000 ################################################################
2236 07:41:19.312902
2237 07:41:19.829777 00780000 ################################################################
2238 07:41:19.829937
2239 07:41:20.254960 00800000 ##################################################### done.
2240 07:41:20.255112
2241 07:41:20.258392 Sending tftp read request... done.
2242 07:41:20.258476
2243 07:41:20.261854 Waiting for the transfer...
2244 07:41:20.261932
2245 07:41:20.262023 00000000 # done.
2246 07:41:20.262089
2247 07:41:20.271550 Command line loaded dynamically from TFTP file: 12435165/tftp-deploy-thjgx_1y/kernel/cmdline
2248 07:41:20.271664
2249 07:41:20.288068 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2250 07:41:20.291047
2251 07:41:20.294487 Shutting down all USB controllers.
2252 07:41:20.294562
2253 07:41:20.294625 Removing current net device
2254 07:41:20.294690
2255 07:41:20.297995 Finalizing coreboot
2256 07:41:20.298070
2257 07:41:20.304469 Exiting depthcharge with code 4 at timestamp: 28313747
2258 07:41:20.304566
2259 07:41:20.304654
2260 07:41:20.304740 Starting kernel ...
2261 07:41:20.304825
2262 07:41:20.304908
2263 07:41:20.305519 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
2264 07:41:20.305646 start: 2.2.5 auto-login-action (timeout 00:04:25) [common]
2265 07:41:20.305753 Setting prompt string to ['Linux version [0-9]']
2266 07:41:20.305828 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2267 07:41:20.305896 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2269 07:45:45.305871 end: 2.2.5 auto-login-action (duration 00:04:25) [common]
2271 07:45:45.306159 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 265 seconds'
2273 07:45:45.306395 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2276 07:45:45.306786 end: 2 depthcharge-action (duration 00:05:00) [common]
2278 07:45:45.307039 Cleaning after the job
2279 07:45:45.307123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/ramdisk
2280 07:45:45.308601 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/kernel
2281 07:45:45.310171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435165/tftp-deploy-thjgx_1y/modules
2282 07:45:45.310502 start: 5.1 power-off (timeout 00:00:30) [common]
2283 07:45:45.310652 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=off'
2284 07:45:45.386443 >> Command sent successfully.
2285 07:45:45.388976 Returned 0 in 0 seconds
2286 07:45:45.489410 end: 5.1 power-off (duration 00:00:00) [common]
2288 07:45:45.489814 start: 5.2 read-feedback (timeout 00:10:00) [common]
2289 07:45:45.490096 Listened to connection for namespace 'common' for up to 1s
2290 07:45:46.491057 Finalising connection for namespace 'common'
2291 07:45:46.491245 Disconnecting from shell: Finalise
2292 07:45:46.491353
2293 07:45:46.591707 end: 5.2 read-feedback (duration 00:00:01) [common]
2294 07:45:46.591885 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12435165
2295 07:45:46.608552 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12435165
2296 07:45:46.608749 JobError: Your job cannot terminate cleanly.