Boot log: asus-cx9400-volteer
- Kernel Warnings: 0
- Errors: 2
- Warnings: 0
- Kernel Errors: 0
- Boot result: FAIL
1 07:40:23.274800 lava-dispatcher, installed at version: 2023.10
2 07:40:23.275017 start: 0 validate
3 07:40:23.275156 Start time: 2024-01-03 07:40:23.275148+00:00 (UTC)
4 07:40:23.275278 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:40:23.275425 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Famd64%2Finitrd.cpio.gz exists
6 07:40:23.542863 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:40:23.543090 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72-1224-ga0ac575eeff8%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:40:23.810657 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:40:23.810841 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 07:40:26.626419 Using caching service: 'http://localhost/cache/?uri=%s'
11 07:40:26.626622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72-1224-ga0ac575eeff8%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fmodules.tar.xz exists
12 07:40:26.894743 validate duration: 3.62
14 07:40:26.895124 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:40:26.895259 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:40:26.895390 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:40:26.895522 Not decompressing ramdisk as can be used compressed.
18 07:40:26.895612 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/amd64/initrd.cpio.gz
19 07:40:26.895707 saving as /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/ramdisk/initrd.cpio.gz
20 07:40:26.895774 total size: 5432690 (5 MB)
21 07:40:27.424659 progress 0 % (0 MB)
22 07:40:27.426394 progress 5 % (0 MB)
23 07:40:27.427885 progress 10 % (0 MB)
24 07:40:27.429335 progress 15 % (0 MB)
25 07:40:27.430950 progress 20 % (1 MB)
26 07:40:27.432438 progress 25 % (1 MB)
27 07:40:27.433863 progress 30 % (1 MB)
28 07:40:27.435517 progress 35 % (1 MB)
29 07:40:27.436946 progress 40 % (2 MB)
30 07:40:27.438368 progress 45 % (2 MB)
31 07:40:27.439869 progress 50 % (2 MB)
32 07:40:27.441454 progress 55 % (2 MB)
33 07:40:27.442878 progress 60 % (3 MB)
34 07:40:27.444298 progress 65 % (3 MB)
35 07:40:27.445893 progress 70 % (3 MB)
36 07:40:27.447304 progress 75 % (3 MB)
37 07:40:27.448728 progress 80 % (4 MB)
38 07:40:27.450142 progress 85 % (4 MB)
39 07:40:27.451732 progress 90 % (4 MB)
40 07:40:27.453175 progress 95 % (4 MB)
41 07:40:27.454608 progress 100 % (5 MB)
42 07:40:27.454824 5 MB downloaded in 0.56 s (9.27 MB/s)
43 07:40:27.454994 end: 1.1.1 http-download (duration 00:00:01) [common]
45 07:40:27.455242 end: 1.1 download-retry (duration 00:00:01) [common]
46 07:40:27.455335 start: 1.2 download-retry (timeout 00:09:59) [common]
47 07:40:27.455439 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 07:40:27.455581 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72-1224-ga0ac575eeff8/x86_64/x86_64_defconfig+x86-board/gcc-10/kernel/bzImage
49 07:40:27.455659 saving as /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/kernel/bzImage
50 07:40:27.455721 total size: 8572816 (8 MB)
51 07:40:27.455782 No compression specified
52 07:40:27.456886 progress 0 % (0 MB)
53 07:40:27.459236 progress 5 % (0 MB)
54 07:40:27.461575 progress 10 % (0 MB)
55 07:40:27.463876 progress 15 % (1 MB)
56 07:40:27.466208 progress 20 % (1 MB)
57 07:40:27.468531 progress 25 % (2 MB)
58 07:40:27.470824 progress 30 % (2 MB)
59 07:40:27.473117 progress 35 % (2 MB)
60 07:40:27.475421 progress 40 % (3 MB)
61 07:40:27.477708 progress 45 % (3 MB)
62 07:40:27.479999 progress 50 % (4 MB)
63 07:40:27.482293 progress 55 % (4 MB)
64 07:40:27.484543 progress 60 % (4 MB)
65 07:40:27.486952 progress 65 % (5 MB)
66 07:40:27.489260 progress 70 % (5 MB)
67 07:40:27.491517 progress 75 % (6 MB)
68 07:40:27.493784 progress 80 % (6 MB)
69 07:40:27.496056 progress 85 % (6 MB)
70 07:40:27.498296 progress 90 % (7 MB)
71 07:40:27.500571 progress 95 % (7 MB)
72 07:40:27.502828 progress 100 % (8 MB)
73 07:40:27.503018 8 MB downloaded in 0.05 s (172.87 MB/s)
74 07:40:27.503169 end: 1.2.1 http-download (duration 00:00:00) [common]
76 07:40:27.503408 end: 1.2 download-retry (duration 00:00:00) [common]
77 07:40:27.503494 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:40:27.503585 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:40:27.503729 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/amd64/full.rootfs.tar.xz
80 07:40:27.503797 saving as /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/nfsrootfs/full.rootfs.tar
81 07:40:27.503858 total size: 133380384 (127 MB)
82 07:40:27.503919 Using unxz to decompress xz
83 07:40:27.509690 progress 0 % (0 MB)
84 07:40:27.871132 progress 5 % (6 MB)
85 07:40:28.232475 progress 10 % (12 MB)
86 07:40:28.530257 progress 15 % (19 MB)
87 07:40:28.721493 progress 20 % (25 MB)
88 07:40:28.978001 progress 25 % (31 MB)
89 07:40:29.345091 progress 30 % (38 MB)
90 07:40:29.710965 progress 35 % (44 MB)
91 07:40:30.143989 progress 40 % (50 MB)
92 07:40:30.562304 progress 45 % (57 MB)
93 07:40:30.934657 progress 50 % (63 MB)
94 07:40:31.317860 progress 55 % (69 MB)
95 07:40:31.689244 progress 60 % (76 MB)
96 07:40:32.068958 progress 65 % (82 MB)
97 07:40:32.463652 progress 70 % (89 MB)
98 07:40:32.854602 progress 75 % (95 MB)
99 07:40:33.321956 progress 80 % (101 MB)
100 07:40:33.794385 progress 85 % (108 MB)
101 07:40:34.078887 progress 90 % (114 MB)
102 07:40:34.440550 progress 95 % (120 MB)
103 07:40:34.850819 progress 100 % (127 MB)
104 07:40:34.856969 127 MB downloaded in 7.35 s (17.30 MB/s)
105 07:40:34.857250 end: 1.3.1 http-download (duration 00:00:07) [common]
107 07:40:34.857555 end: 1.3 download-retry (duration 00:00:07) [common]
108 07:40:34.857647 start: 1.4 download-retry (timeout 00:09:52) [common]
109 07:40:34.857745 start: 1.4.1 http-download (timeout 00:09:52) [common]
110 07:40:34.857905 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72-1224-ga0ac575eeff8/x86_64/x86_64_defconfig+x86-board/gcc-10/modules.tar.xz
111 07:40:34.857986 saving as /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/modules/modules.tar
112 07:40:34.858048 total size: 251144 (0 MB)
113 07:40:34.858123 Using unxz to decompress xz
114 07:40:34.862677 progress 13 % (0 MB)
115 07:40:34.863116 progress 26 % (0 MB)
116 07:40:34.863399 progress 39 % (0 MB)
117 07:40:34.864794 progress 52 % (0 MB)
118 07:40:34.866803 progress 65 % (0 MB)
119 07:40:34.868769 progress 78 % (0 MB)
120 07:40:34.870642 progress 91 % (0 MB)
121 07:40:34.872684 progress 100 % (0 MB)
122 07:40:34.878367 0 MB downloaded in 0.02 s (11.79 MB/s)
123 07:40:34.878657 end: 1.4.1 http-download (duration 00:00:00) [common]
125 07:40:34.879093 end: 1.4 download-retry (duration 00:00:00) [common]
126 07:40:34.879235 start: 1.5 prepare-tftp-overlay (timeout 00:09:52) [common]
127 07:40:34.879373 start: 1.5.1 extract-nfsrootfs (timeout 00:09:52) [common]
128 07:40:37.375103 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12435141/extract-nfsrootfs-i6emnpk7
129 07:40:37.375317 end: 1.5.1 extract-nfsrootfs (duration 00:00:02) [common]
130 07:40:37.375434 start: 1.5.2 lava-overlay (timeout 00:09:50) [common]
131 07:40:37.375609 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n
132 07:40:37.375750 makedir: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin
133 07:40:37.375857 makedir: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/tests
134 07:40:37.375963 makedir: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/results
135 07:40:37.376068 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-add-keys
136 07:40:37.376217 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-add-sources
137 07:40:37.376356 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-background-process-start
138 07:40:37.376489 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-background-process-stop
139 07:40:37.376622 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-common-functions
140 07:40:37.376752 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-echo-ipv4
141 07:40:37.376881 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-install-packages
142 07:40:37.377010 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-installed-packages
143 07:40:37.377142 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-os-build
144 07:40:37.377273 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-probe-channel
145 07:40:37.377402 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-probe-ip
146 07:40:37.377531 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-target-ip
147 07:40:37.377659 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-target-mac
148 07:40:37.377789 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-target-storage
149 07:40:37.377920 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-case
150 07:40:37.378050 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-event
151 07:40:37.378179 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-feedback
152 07:40:37.378308 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-raise
153 07:40:37.378437 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-reference
154 07:40:37.378567 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-runner
155 07:40:37.378696 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-set
156 07:40:37.378833 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-test-shell
157 07:40:37.378997 Updating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-install-packages (oe)
158 07:40:37.379194 Updating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/bin/lava-installed-packages (oe)
159 07:40:37.379351 Creating /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/environment
160 07:40:37.379466 LAVA metadata
161 07:40:37.379539 - LAVA_JOB_ID=12435141
162 07:40:37.379605 - LAVA_DISPATCHER_IP=192.168.201.1
163 07:40:37.379708 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:50) [common]
164 07:40:37.379779 skipped lava-vland-overlay
165 07:40:37.379856 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
166 07:40:37.379937 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
167 07:40:37.379999 skipped lava-multinode-overlay
168 07:40:37.380073 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
169 07:40:37.380152 start: 1.5.2.3 test-definition (timeout 00:09:50) [common]
170 07:40:37.380225 Loading test definitions
171 07:40:37.380317 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:50) [common]
172 07:40:37.380389 Using /lava-12435141 at stage 0
173 07:40:37.380714 uuid=12435141_1.5.2.3.1 testdef=None
174 07:40:37.380805 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
175 07:40:37.380890 start: 1.5.2.3.2 test-overlay (timeout 00:09:50) [common]
176 07:40:37.381406 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
178 07:40:37.381627 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:50) [common]
179 07:40:37.382277 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
181 07:40:37.382508 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
182 07:40:37.383135 runner path: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/0/tests/0_dmesg test_uuid 12435141_1.5.2.3.1
183 07:40:37.383293 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
185 07:40:37.383537 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:50) [common]
186 07:40:37.383616 Using /lava-12435141 at stage 1
187 07:40:37.383932 uuid=12435141_1.5.2.3.5 testdef=None
188 07:40:37.384022 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
189 07:40:37.384107 start: 1.5.2.3.6 test-overlay (timeout 00:09:50) [common]
190 07:40:37.384592 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
192 07:40:37.384807 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:50) [common]
193 07:40:37.385462 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
195 07:40:37.385692 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
196 07:40:37.386327 runner path: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/1/tests/1_bootrr test_uuid 12435141_1.5.2.3.5
197 07:40:37.386483 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
199 07:40:37.386687 Creating lava-test-runner.conf files
200 07:40:37.386751 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/0 for stage 0
201 07:40:37.386843 - 0_dmesg
202 07:40:37.386923 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12435141/lava-overlay-bevoup9n/lava-12435141/1 for stage 1
203 07:40:37.387015 - 1_bootrr
204 07:40:37.387112 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
205 07:40:37.387198 start: 1.5.2.4 compress-overlay (timeout 00:09:50) [common]
206 07:40:37.394906 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
207 07:40:37.395010 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
208 07:40:37.395097 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
209 07:40:37.395183 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
210 07:40:37.395271 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
211 07:40:37.539854 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
212 07:40:37.540252 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
213 07:40:37.540375 extracting modules file /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12435141/extract-nfsrootfs-i6emnpk7
214 07:40:37.557896 extracting modules file /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12435141/extract-overlay-ramdisk-equqqtj8/ramdisk
215 07:40:37.574898 end: 1.5.4 extract-modules (duration 00:00:00) [common]
216 07:40:37.575061 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
217 07:40:37.575180 [common] Applying overlay to NFS
218 07:40:37.575286 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12435141/compress-overlay-oy4cbr0n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12435141/extract-nfsrootfs-i6emnpk7
219 07:40:37.588126 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
220 07:40:37.588293 start: 1.5.6 configure-preseed-file (timeout 00:09:49) [common]
221 07:40:37.588429 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
222 07:40:37.588567 start: 1.5.7 compress-ramdisk (timeout 00:09:49) [common]
223 07:40:37.588683 Building ramdisk /var/lib/lava/dispatcher/tmp/12435141/extract-overlay-ramdisk-equqqtj8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12435141/extract-overlay-ramdisk-equqqtj8/ramdisk
224 07:40:37.674152 >> 26162 blocks
225 07:40:38.249363 rename /var/lib/lava/dispatcher/tmp/12435141/extract-overlay-ramdisk-equqqtj8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
226 07:40:38.249836 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
227 07:40:38.249969 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
228 07:40:38.250069 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
229 07:40:38.250165 No mkimage arch provided, not using FIT.
230 07:40:38.250256 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
231 07:40:38.250343 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
232 07:40:38.250457 end: 1.5 prepare-tftp-overlay (duration 00:00:03) [common]
233 07:40:38.250544 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:49) [common]
234 07:40:38.250623 No LXC device requested
235 07:40:38.250703 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
236 07:40:38.250789 start: 1.7 deploy-device-env (timeout 00:09:49) [common]
237 07:40:38.250877 end: 1.7 deploy-device-env (duration 00:00:00) [common]
238 07:40:38.250950 Checking files for TFTP limit of 4294967296 bytes.
239 07:40:38.251382 end: 1 tftp-deploy (duration 00:00:11) [common]
240 07:40:38.251522 start: 2 depthcharge-action (timeout 00:05:00) [common]
241 07:40:38.251663 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
242 07:40:38.251800 substitutions:
243 07:40:38.251872 - {DTB}: None
244 07:40:38.251938 - {INITRD}: 12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
245 07:40:38.251999 - {KERNEL}: 12435141/tftp-deploy-qck00fxx/kernel/bzImage
246 07:40:38.252057 - {LAVA_MAC}: None
247 07:40:38.252115 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12435141/extract-nfsrootfs-i6emnpk7
248 07:40:38.252172 - {NFS_SERVER_IP}: 192.168.201.1
249 07:40:38.252229 - {PRESEED_CONFIG}: None
250 07:40:38.252285 - {PRESEED_LOCAL}: None
251 07:40:38.252340 - {RAMDISK}: 12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
252 07:40:38.252396 - {ROOT_PART}: None
253 07:40:38.252451 - {ROOT}: None
254 07:40:38.252506 - {SERVER_IP}: 192.168.201.1
255 07:40:38.252560 - {TEE}: None
256 07:40:38.252615 Parsed boot commands:
257 07:40:38.252669 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
258 07:40:38.252853 Parsed boot commands: tftpboot 192.168.201.1 12435141/tftp-deploy-qck00fxx/kernel/bzImage 12435141/tftp-deploy-qck00fxx/kernel/cmdline 12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
259 07:40:38.252942 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
260 07:40:38.253033 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
261 07:40:38.253130 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
262 07:40:38.253219 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
263 07:40:38.253292 Not connected, no need to disconnect.
264 07:40:38.253369 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
265 07:40:38.253455 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
266 07:40:38.253522 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-5'
267 07:40:38.257362 Setting prompt string to ['lava-test: # ']
268 07:40:38.257752 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
269 07:40:38.257882 end: 2.2.1 reset-connection (duration 00:00:00) [common]
270 07:40:38.258009 start: 2.2.2 reset-device (timeout 00:05:00) [common]
271 07:40:38.258106 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
272 07:40:38.258402 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-5' '--port=1' '--command=reboot'
273 07:40:43.401147 >> Command sent successfully.
274 07:40:43.404045 Returned 0 in 5 seconds
275 07:40:43.504465 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
277 07:40:43.504933 end: 2.2.2 reset-device (duration 00:00:05) [common]
278 07:40:43.505070 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
279 07:40:43.505193 Setting prompt string to 'Starting depthcharge on Voema...'
280 07:40:43.505309 Changing prompt to 'Starting depthcharge on Voema...'
281 07:40:43.505427 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
282 07:40:43.505822 [Enter `^Ec?' for help]
283 07:40:45.108180
284 07:40:45.108350
285 07:40:45.117760 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
286 07:40:45.120957 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
287 07:40:45.128005 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
288 07:40:45.131052 CPU: AES supported, TXT NOT supported, VT supported
289 07:40:45.138046 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
290 07:40:45.144830 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
291 07:40:45.147847 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
292 07:40:45.151359 VBOOT: Loading verstage.
293 07:40:45.154629 FMAP: Found "FLASH" version 1.1 at 0x1804000.
294 07:40:45.160978 FMAP: base = 0x0 size = 0x2000000 #areas = 32
295 07:40:45.164120 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 07:40:45.175153 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
297 07:40:45.181852 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
298 07:40:45.181951
299 07:40:45.182021
300 07:40:45.194824 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
301 07:40:45.208542 Probing TPM: . done!
302 07:40:45.212202 TPM ready after 0 ms
303 07:40:45.215311 Connected to device vid:did:rid of 1ae0:0028:00
304 07:40:45.226821 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
305 07:40:45.233378 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
306 07:40:45.236575 Initialized TPM device CR50 revision 0
307 07:40:45.286936 tlcl_send_startup: Startup return code is 0
308 07:40:45.287081 TPM: setup succeeded
309 07:40:45.301622 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
310 07:40:45.315720 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
311 07:40:45.328122 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
312 07:40:45.338175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
313 07:40:45.341695 Chrome EC: UHEPI supported
314 07:40:45.345705 Phase 1
315 07:40:45.348739 FMAP: area GBB found @ 1805000 (458752 bytes)
316 07:40:45.359009 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
317 07:40:45.365474 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
318 07:40:45.371995 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
319 07:40:45.379037 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
320 07:40:45.382249 Recovery requested (1009000e)
321 07:40:45.386076 TPM: Extending digest for VBOOT: boot mode into PCR 0
322 07:40:45.397394 tlcl_extend: response is 0
323 07:40:45.403699 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
324 07:40:45.413498 tlcl_extend: response is 0
325 07:40:45.420609 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
326 07:40:45.427050 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
327 07:40:45.433458 BS: verstage times (exec / console): total (unknown) / 142 ms
328 07:40:45.433570
329 07:40:45.433665
330 07:40:45.446768 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
331 07:40:45.450225 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
332 07:40:45.457668 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
333 07:40:45.460694 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
334 07:40:45.464482 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
335 07:40:45.470635 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
336 07:40:45.474390 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
337 07:40:45.477418 TCO_STS: 0000 0000
338 07:40:45.480715 GEN_PMCON: d0015038 00002200
339 07:40:45.484318 GBLRST_CAUSE: 00000000 00000000
340 07:40:45.484403 HPR_CAUSE0: 00000000
341 07:40:45.487414 prev_sleep_state 5
342 07:40:45.491157 Boot Count incremented to 25796
343 07:40:45.497314 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
344 07:40:45.504416 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
345 07:40:45.510542 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
346 07:40:45.517744 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
347 07:40:45.520821 Chrome EC: UHEPI supported
348 07:40:45.527708 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
349 07:40:45.540322 Probing TPM: done!
350 07:40:45.547316 Connected to device vid:did:rid of 1ae0:0028:00
351 07:40:45.558198 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
352 07:40:45.564990 Initialized TPM device CR50 revision 0
353 07:40:45.575381 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
354 07:40:45.582559 MRC: Hash idx 0x100b comparison successful.
355 07:40:45.585503 MRC cache found, size faa8
356 07:40:45.585618 bootmode is set to: 2
357 07:40:45.589075 SPD index = 0
358 07:40:45.595444 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
359 07:40:45.599032 SPD: module type is LPDDR4X
360 07:40:45.602019 SPD: module part number is MT53E512M64D4NW-046
361 07:40:45.608704 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
362 07:40:45.612499 SPD: device width 16 bits, bus width 16 bits
363 07:40:45.618773 SPD: module size is 1024 MB (per channel)
364 07:40:46.051919 CBMEM:
365 07:40:46.055255 IMD: root @ 0x76fff000 254 entries.
366 07:40:46.058099 IMD: root @ 0x76ffec00 62 entries.
367 07:40:46.061938 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
368 07:40:46.068665 FMAP: area RW_VPD found @ f35000 (8192 bytes)
369 07:40:46.071925 External stage cache:
370 07:40:46.075081 IMD: root @ 0x7b3ff000 254 entries.
371 07:40:46.078304 IMD: root @ 0x7b3fec00 62 entries.
372 07:40:46.093652 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
373 07:40:46.100034 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
374 07:40:46.106924 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
375 07:40:46.120995 MRC: 'RECOVERY_MRC_CACHE' does not need update.
376 07:40:46.127438 cse_lite: Skip switching to RW in the recovery path
377 07:40:46.127527 8 DIMMs found
378 07:40:46.127597 SMM Memory Map
379 07:40:46.131601 SMRAM : 0x7b000000 0x800000
380 07:40:46.135211 Subregion 0: 0x7b000000 0x200000
381 07:40:46.138760 Subregion 1: 0x7b200000 0x200000
382 07:40:46.142398 Subregion 2: 0x7b400000 0x400000
383 07:40:46.145697 top_of_ram = 0x77000000
384 07:40:46.149182 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
385 07:40:46.155799 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
386 07:40:46.162577 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
387 07:40:46.165619 MTRR Range: Start=ff000000 End=0 (Size 1000000)
388 07:40:46.172115 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
389 07:40:46.178898 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
390 07:40:46.190766 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
391 07:40:46.197236 Processing 211 relocs. Offset value of 0x74c0b000
392 07:40:46.203689 BS: romstage times (exec / console): total (unknown) / 277 ms
393 07:40:46.209475
394 07:40:46.209606
395 07:40:46.219765 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
396 07:40:46.222967 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
397 07:40:46.233132 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
398 07:40:46.239572 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
399 07:40:46.246633 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
400 07:40:46.253208 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
401 07:40:46.299600 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
402 07:40:46.306640 Processing 5008 relocs. Offset value of 0x75d98000
403 07:40:46.309893 BS: postcar times (exec / console): total (unknown) / 59 ms
404 07:40:46.309972
405 07:40:46.313163
406 07:40:46.323485 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
407 07:40:46.323609 Normal boot
408 07:40:46.326687 FW_CONFIG value is 0x804c02
409 07:40:46.330335 PCI: 00:07.0 disabled by fw_config
410 07:40:46.333409 PCI: 00:07.1 disabled by fw_config
411 07:40:46.337271 PCI: 00:0d.2 disabled by fw_config
412 07:40:46.340405 PCI: 00:1c.7 disabled by fw_config
413 07:40:46.346759 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
414 07:40:46.350446 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
415 07:40:46.356943 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
416 07:40:46.360291 GENERIC: 0.0 disabled by fw_config
417 07:40:46.363852 GENERIC: 1.0 disabled by fw_config
418 07:40:46.366899 fw_config match found: DB_USB=USB3_ACTIVE
419 07:40:46.373807 fw_config match found: DB_USB=USB3_ACTIVE
420 07:40:46.377155 fw_config match found: DB_USB=USB3_ACTIVE
421 07:40:46.380121 fw_config match found: DB_USB=USB3_ACTIVE
422 07:40:46.387072 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
423 07:40:46.394049 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
424 07:40:46.400456 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
425 07:40:46.410689 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
426 07:40:46.413866 microcode: sig=0x806c1 pf=0x80 revision=0x86
427 07:40:46.417093 microcode: Update skipped, already up-to-date
428 07:40:46.423611 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
429 07:40:46.453488 Detected 4 core, 8 thread CPU.
430 07:40:46.456556 Setting up SMI for CPU
431 07:40:46.460083 IED base = 0x7b400000
432 07:40:46.460164 IED size = 0x00400000
433 07:40:46.462913 Will perform SMM setup.
434 07:40:46.469917 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
435 07:40:46.476201 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
436 07:40:46.483239 Processing 16 relocs. Offset value of 0x00030000
437 07:40:46.486902 Attempting to start 7 APs
438 07:40:46.489894 Waiting for 10ms after sending INIT.
439 07:40:46.505355 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
440 07:40:46.508279 AP: slot 2 apic_id 3.
441 07:40:46.511966 AP: slot 6 apic_id 2.
442 07:40:46.512088 AP: slot 7 apic_id 6.
443 07:40:46.514992 AP: slot 3 apic_id 7.
444 07:40:46.515120 done.
445 07:40:46.518846 AP: slot 4 apic_id 5.
446 07:40:46.518957 AP: slot 5 apic_id 4.
447 07:40:46.525184 Waiting for 2nd SIPI to complete...done.
448 07:40:46.531591 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
449 07:40:46.538636 Processing 13 relocs. Offset value of 0x00038000
450 07:40:46.538755 Unable to locate Global NVS
451 07:40:46.548686 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
452 07:40:46.551791 Installing permanent SMM handler to 0x7b000000
453 07:40:46.561982 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
454 07:40:46.565267 Processing 794 relocs. Offset value of 0x7b010000
455 07:40:46.571834 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
456 07:40:46.578604 Processing 13 relocs. Offset value of 0x7b008000
457 07:40:46.585126 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
458 07:40:46.592180 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
459 07:40:46.594972 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
460 07:40:46.601630 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
461 07:40:46.608658 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
462 07:40:46.615281 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
463 07:40:46.618751 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
464 07:40:46.621848 Unable to locate Global NVS
465 07:40:46.628839 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
466 07:40:46.633419 Clearing SMI status registers
467 07:40:46.636066 SMI_STS: PM1
468 07:40:46.636150 PM1_STS: PWRBTN
469 07:40:46.646516 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
470 07:40:46.646600 In relocation handler: CPU 0
471 07:40:46.652971 New SMBASE=0x7b000000 IEDBASE=0x7b400000
472 07:40:46.656623 Writing SMRR. base = 0x7b000006, mask=0xff800c00
473 07:40:46.659909 Relocation complete.
474 07:40:46.666652 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
475 07:40:46.669742 In relocation handler: CPU 1
476 07:40:46.673055 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
477 07:40:46.676002 Relocation complete.
478 07:40:46.683185 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
479 07:40:46.686606 In relocation handler: CPU 3
480 07:40:46.689845 New SMBASE=0x7afff400 IEDBASE=0x7b400000
481 07:40:46.693327 Relocation complete.
482 07:40:46.699966 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
483 07:40:46.702840 In relocation handler: CPU 7
484 07:40:46.706448 New SMBASE=0x7affe400 IEDBASE=0x7b400000
485 07:40:46.710101 Writing SMRR. base = 0x7b000006, mask=0xff800c00
486 07:40:46.713232 Relocation complete.
487 07:40:46.719573 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
488 07:40:46.723463 In relocation handler: CPU 5
489 07:40:46.726343 New SMBASE=0x7affec00 IEDBASE=0x7b400000
490 07:40:46.733538 Writing SMRR. base = 0x7b000006, mask=0xff800c00
491 07:40:46.733622 Relocation complete.
492 07:40:46.743165 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
493 07:40:46.746356 In relocation handler: CPU 4
494 07:40:46.750129 New SMBASE=0x7afff000 IEDBASE=0x7b400000
495 07:40:46.750204 Relocation complete.
496 07:40:46.760229 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
497 07:40:46.760316 In relocation handler: CPU 2
498 07:40:46.766831 New SMBASE=0x7afff800 IEDBASE=0x7b400000
499 07:40:46.766941 Relocation complete.
500 07:40:46.776487 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
501 07:40:46.776596 In relocation handler: CPU 6
502 07:40:46.783584 New SMBASE=0x7affe800 IEDBASE=0x7b400000
503 07:40:46.786635 Writing SMRR. base = 0x7b000006, mask=0xff800c00
504 07:40:46.789783 Relocation complete.
505 07:40:46.789890 Initializing CPU #0
506 07:40:46.793311 CPU: vendor Intel device 806c1
507 07:40:46.800338 CPU: family 06, model 8c, stepping 01
508 07:40:46.800442 Clearing out pending MCEs
509 07:40:46.804206 Setting up local APIC...
510 07:40:46.807662 apic_id: 0x00 done.
511 07:40:46.807778 Turbo is available but hidden
512 07:40:46.811436 Turbo is available and visible
513 07:40:46.817810 microcode: Update skipped, already up-to-date
514 07:40:46.817918 CPU #0 initialized
515 07:40:46.820874 Initializing CPU #1
516 07:40:46.824594 Initializing CPU #6
517 07:40:46.824702 Initializing CPU #4
518 07:40:46.827916 Initializing CPU #5
519 07:40:46.828018 Initializing CPU #2
520 07:40:46.830822 CPU: vendor Intel device 806c1
521 07:40:46.837584 CPU: family 06, model 8c, stepping 01
522 07:40:46.837690 CPU: vendor Intel device 806c1
523 07:40:46.844175 CPU: family 06, model 8c, stepping 01
524 07:40:46.844282 Clearing out pending MCEs
525 07:40:46.847381 Clearing out pending MCEs
526 07:40:46.851188 Setting up local APIC...
527 07:40:46.854418 CPU: vendor Intel device 806c1
528 07:40:46.857576 CPU: family 06, model 8c, stepping 01
529 07:40:46.860854 CPU: vendor Intel device 806c1
530 07:40:46.864208 CPU: family 06, model 8c, stepping 01
531 07:40:46.867821 Clearing out pending MCEs
532 07:40:46.870782 Clearing out pending MCEs
533 07:40:46.870861 Setting up local APIC...
534 07:40:46.873971 apic_id: 0x02 done.
535 07:40:46.877833 Setting up local APIC...
536 07:40:46.881080 Setting up local APIC...
537 07:40:46.884337 CPU: vendor Intel device 806c1
538 07:40:46.887455 CPU: family 06, model 8c, stepping 01
539 07:40:46.890819 microcode: Update skipped, already up-to-date
540 07:40:46.894645 apic_id: 0x03 done.
541 07:40:46.894722 CPU #6 initialized
542 07:40:46.900860 microcode: Update skipped, already up-to-date
543 07:40:46.900941 apic_id: 0x04 done.
544 07:40:46.904684 apic_id: 0x05 done.
545 07:40:46.907682 microcode: Update skipped, already up-to-date
546 07:40:46.914505 microcode: Update skipped, already up-to-date
547 07:40:46.914585 CPU #5 initialized
548 07:40:46.917543 CPU #4 initialized
549 07:40:46.917617 CPU #2 initialized
550 07:40:46.920950 Initializing CPU #7
551 07:40:46.924192 Initializing CPU #3
552 07:40:46.927444 CPU: vendor Intel device 806c1
553 07:40:46.931180 CPU: family 06, model 8c, stepping 01
554 07:40:46.934305 CPU: vendor Intel device 806c1
555 07:40:46.937455 CPU: family 06, model 8c, stepping 01
556 07:40:46.940646 Clearing out pending MCEs
557 07:40:46.940722 Clearing out pending MCEs
558 07:40:46.944308 Clearing out pending MCEs
559 07:40:46.947862 Setting up local APIC...
560 07:40:46.950820 Setting up local APIC...
561 07:40:46.950898 apic_id: 0x07 done.
562 07:40:46.954098 Setting up local APIC...
563 07:40:46.957231 apic_id: 0x01 done.
564 07:40:46.957335 apic_id: 0x06 done.
565 07:40:46.964562 microcode: Update skipped, already up-to-date
566 07:40:46.967805 microcode: Update skipped, already up-to-date
567 07:40:46.970947 CPU #3 initialized
568 07:40:46.971062 CPU #7 initialized
569 07:40:46.977689 microcode: Update skipped, already up-to-date
570 07:40:46.977813 CPU #1 initialized
571 07:40:46.984583 bsp_do_flight_plan done after 455 msecs.
572 07:40:46.987860 CPU: frequency set to 4000 MHz
573 07:40:46.987946 Enabling SMIs.
574 07:40:46.994258 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
575 07:40:47.010237 SATAXPCIE1 indicates PCIe NVMe is present
576 07:40:47.013385 Probing TPM: done!
577 07:40:47.016988 Connected to device vid:did:rid of 1ae0:0028:00
578 07:40:47.027919 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
579 07:40:47.030887 Initialized TPM device CR50 revision 0
580 07:40:47.033944 Enabling S0i3.4
581 07:40:47.041222 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
582 07:40:47.044699 Found a VBT of 8704 bytes after decompression
583 07:40:47.051157 cse_lite: CSE RO boot. HybridStorageMode disabled
584 07:40:47.057605 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
585 07:40:47.132743 FSPS returned 0
586 07:40:47.136216 Executing Phase 1 of FspMultiPhaseSiInit
587 07:40:47.146190 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
588 07:40:47.149265 port C0 DISC req: usage 1 usb3 1 usb2 5
589 07:40:47.152642 Raw Buffer output 0 00000511
590 07:40:47.156160 Raw Buffer output 1 00000000
591 07:40:47.160172 pmc_send_ipc_cmd succeeded
592 07:40:47.166816 port C1 DISC req: usage 1 usb3 2 usb2 3
593 07:40:47.166900 Raw Buffer output 0 00000321
594 07:40:47.169789 Raw Buffer output 1 00000000
595 07:40:47.174156 pmc_send_ipc_cmd succeeded
596 07:40:47.179287 Detected 4 core, 8 thread CPU.
597 07:40:47.182569 Detected 4 core, 8 thread CPU.
598 07:40:47.416661 Display FSP Version Info HOB
599 07:40:47.420501 Reference Code - CPU = a.0.4c.31
600 07:40:47.423625 uCode Version = 0.0.0.86
601 07:40:47.426954 TXT ACM version = ff.ff.ff.ffff
602 07:40:47.429945 Reference Code - ME = a.0.4c.31
603 07:40:47.433769 MEBx version = 0.0.0.0
604 07:40:47.436874 ME Firmware Version = Consumer SKU
605 07:40:47.440231 Reference Code - PCH = a.0.4c.31
606 07:40:47.443271 PCH-CRID Status = Disabled
607 07:40:47.447037 PCH-CRID Original Value = ff.ff.ff.ffff
608 07:40:47.450216 PCH-CRID New Value = ff.ff.ff.ffff
609 07:40:47.453524 OPROM - RST - RAID = ff.ff.ff.ffff
610 07:40:47.456810 PCH Hsio Version = 4.0.0.0
611 07:40:47.460159 Reference Code - SA - System Agent = a.0.4c.31
612 07:40:47.463803 Reference Code - MRC = 2.0.0.1
613 07:40:47.467000 SA - PCIe Version = a.0.4c.31
614 07:40:47.470195 SA-CRID Status = Disabled
615 07:40:47.473463 SA-CRID Original Value = 0.0.0.1
616 07:40:47.477130 SA-CRID New Value = 0.0.0.1
617 07:40:47.480393 OPROM - VBIOS = ff.ff.ff.ffff
618 07:40:47.483586 IO Manageability Engine FW Version = 11.1.4.0
619 07:40:47.487150 PHY Build Version = 0.0.0.e0
620 07:40:47.490430 Thunderbolt(TM) FW Version = 0.0.0.0
621 07:40:47.497129 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
622 07:40:47.500104 ITSS IRQ Polarities Before:
623 07:40:47.500185 IPC0: 0xffffffff
624 07:40:47.503515 IPC1: 0xffffffff
625 07:40:47.503596 IPC2: 0xffffffff
626 07:40:47.506785 IPC3: 0xffffffff
627 07:40:47.510318 ITSS IRQ Polarities After:
628 07:40:47.510399 IPC0: 0xffffffff
629 07:40:47.513785 IPC1: 0xffffffff
630 07:40:47.513882 IPC2: 0xffffffff
631 07:40:47.516730 IPC3: 0xffffffff
632 07:40:47.519937 Found PCIe Root Port #9 at PCI: 00:1d.0.
633 07:40:47.533362 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
634 07:40:47.543645 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
635 07:40:47.556731 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
636 07:40:47.563472 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
637 07:40:47.563573 Enumerating buses...
638 07:40:47.570312 Show all devs... Before device enumeration.
639 07:40:47.570406 Root Device: enabled 1
640 07:40:47.573554 DOMAIN: 0000: enabled 1
641 07:40:47.576680 CPU_CLUSTER: 0: enabled 1
642 07:40:47.579914 PCI: 00:00.0: enabled 1
643 07:40:47.579998 PCI: 00:02.0: enabled 1
644 07:40:47.583704 PCI: 00:04.0: enabled 1
645 07:40:47.587003 PCI: 00:05.0: enabled 1
646 07:40:47.589952 PCI: 00:06.0: enabled 0
647 07:40:47.590037 PCI: 00:07.0: enabled 0
648 07:40:47.593439 PCI: 00:07.1: enabled 0
649 07:40:47.597082 PCI: 00:07.2: enabled 0
650 07:40:47.597168 PCI: 00:07.3: enabled 0
651 07:40:47.600012 PCI: 00:08.0: enabled 1
652 07:40:47.603231 PCI: 00:09.0: enabled 0
653 07:40:47.607019 PCI: 00:0a.0: enabled 0
654 07:40:47.607106 PCI: 00:0d.0: enabled 1
655 07:40:47.610233 PCI: 00:0d.1: enabled 0
656 07:40:47.613251 PCI: 00:0d.2: enabled 0
657 07:40:47.616775 PCI: 00:0d.3: enabled 0
658 07:40:47.616860 PCI: 00:0e.0: enabled 0
659 07:40:47.619985 PCI: 00:10.2: enabled 1
660 07:40:47.623332 PCI: 00:10.6: enabled 0
661 07:40:47.626500 PCI: 00:10.7: enabled 0
662 07:40:47.626585 PCI: 00:12.0: enabled 0
663 07:40:47.630047 PCI: 00:12.6: enabled 0
664 07:40:47.633337 PCI: 00:13.0: enabled 0
665 07:40:47.633422 PCI: 00:14.0: enabled 1
666 07:40:47.637079 PCI: 00:14.1: enabled 0
667 07:40:47.640327 PCI: 00:14.2: enabled 1
668 07:40:47.643255 PCI: 00:14.3: enabled 1
669 07:40:47.643340 PCI: 00:15.0: enabled 1
670 07:40:47.647244 PCI: 00:15.1: enabled 1
671 07:40:47.650303 PCI: 00:15.2: enabled 1
672 07:40:47.653510 PCI: 00:15.3: enabled 1
673 07:40:47.653594 PCI: 00:16.0: enabled 1
674 07:40:47.656667 PCI: 00:16.1: enabled 0
675 07:40:47.659941 PCI: 00:16.2: enabled 0
676 07:40:47.663354 PCI: 00:16.3: enabled 0
677 07:40:47.663451 PCI: 00:16.4: enabled 0
678 07:40:47.666989 PCI: 00:16.5: enabled 0
679 07:40:47.670057 PCI: 00:17.0: enabled 1
680 07:40:47.673339 PCI: 00:19.0: enabled 0
681 07:40:47.673423 PCI: 00:19.1: enabled 1
682 07:40:47.676610 PCI: 00:19.2: enabled 0
683 07:40:47.679793 PCI: 00:1c.0: enabled 1
684 07:40:47.679876 PCI: 00:1c.1: enabled 0
685 07:40:47.683641 PCI: 00:1c.2: enabled 0
686 07:40:47.686730 PCI: 00:1c.3: enabled 0
687 07:40:47.689981 PCI: 00:1c.4: enabled 0
688 07:40:47.690064 PCI: 00:1c.5: enabled 0
689 07:40:47.693154 PCI: 00:1c.6: enabled 1
690 07:40:47.696464 PCI: 00:1c.7: enabled 0
691 07:40:47.700032 PCI: 00:1d.0: enabled 1
692 07:40:47.700143 PCI: 00:1d.1: enabled 0
693 07:40:47.703466 PCI: 00:1d.2: enabled 1
694 07:40:47.706806 PCI: 00:1d.3: enabled 0
695 07:40:47.709857 PCI: 00:1e.0: enabled 1
696 07:40:47.709968 PCI: 00:1e.1: enabled 0
697 07:40:47.713534 PCI: 00:1e.2: enabled 1
698 07:40:47.716655 PCI: 00:1e.3: enabled 1
699 07:40:47.716739 PCI: 00:1f.0: enabled 1
700 07:40:47.720274 PCI: 00:1f.1: enabled 0
701 07:40:47.723526 PCI: 00:1f.2: enabled 1
702 07:40:47.726744 PCI: 00:1f.3: enabled 1
703 07:40:47.726828 PCI: 00:1f.4: enabled 0
704 07:40:47.729716 PCI: 00:1f.5: enabled 1
705 07:40:47.733311 PCI: 00:1f.6: enabled 0
706 07:40:47.736498 PCI: 00:1f.7: enabled 0
707 07:40:47.736581 APIC: 00: enabled 1
708 07:40:47.740040 GENERIC: 0.0: enabled 1
709 07:40:47.742957 GENERIC: 0.0: enabled 1
710 07:40:47.743075 GENERIC: 1.0: enabled 1
711 07:40:47.746806 GENERIC: 0.0: enabled 1
712 07:40:47.749850 GENERIC: 1.0: enabled 1
713 07:40:47.753316 USB0 port 0: enabled 1
714 07:40:47.753401 GENERIC: 0.0: enabled 1
715 07:40:47.756530 USB0 port 0: enabled 1
716 07:40:47.760249 GENERIC: 0.0: enabled 1
717 07:40:47.760333 I2C: 00:1a: enabled 1
718 07:40:47.763466 I2C: 00:31: enabled 1
719 07:40:47.766536 I2C: 00:32: enabled 1
720 07:40:47.766659 I2C: 00:10: enabled 1
721 07:40:47.769997 I2C: 00:15: enabled 1
722 07:40:47.773006 GENERIC: 0.0: enabled 0
723 07:40:47.776599 GENERIC: 1.0: enabled 0
724 07:40:47.776709 GENERIC: 0.0: enabled 1
725 07:40:47.779758 SPI: 00: enabled 1
726 07:40:47.783070 SPI: 00: enabled 1
727 07:40:47.783180 PNP: 0c09.0: enabled 1
728 07:40:47.786417 GENERIC: 0.0: enabled 1
729 07:40:47.789563 USB3 port 0: enabled 1
730 07:40:47.789647 USB3 port 1: enabled 1
731 07:40:47.792739 USB3 port 2: enabled 0
732 07:40:47.796591 USB3 port 3: enabled 0
733 07:40:47.799966 USB2 port 0: enabled 0
734 07:40:47.800070 USB2 port 1: enabled 1
735 07:40:47.803182 USB2 port 2: enabled 1
736 07:40:47.806289 USB2 port 3: enabled 0
737 07:40:47.806399 USB2 port 4: enabled 1
738 07:40:47.809535 USB2 port 5: enabled 0
739 07:40:47.813105 USB2 port 6: enabled 0
740 07:40:47.813215 USB2 port 7: enabled 0
741 07:40:47.816165 USB2 port 8: enabled 0
742 07:40:47.819600 USB2 port 9: enabled 0
743 07:40:47.823000 USB3 port 0: enabled 0
744 07:40:47.823111 USB3 port 1: enabled 1
745 07:40:47.826729 USB3 port 2: enabled 0
746 07:40:47.829406 USB3 port 3: enabled 0
747 07:40:47.829490 GENERIC: 0.0: enabled 1
748 07:40:47.832842 GENERIC: 1.0: enabled 1
749 07:40:47.836500 APIC: 01: enabled 1
750 07:40:47.836607 APIC: 03: enabled 1
751 07:40:47.839781 APIC: 07: enabled 1
752 07:40:47.842762 APIC: 05: enabled 1
753 07:40:47.842861 APIC: 04: enabled 1
754 07:40:47.846072 APIC: 02: enabled 1
755 07:40:47.846155 APIC: 06: enabled 1
756 07:40:47.849756 Compare with tree...
757 07:40:47.852625 Root Device: enabled 1
758 07:40:47.856217 DOMAIN: 0000: enabled 1
759 07:40:47.856301 PCI: 00:00.0: enabled 1
760 07:40:47.859894 PCI: 00:02.0: enabled 1
761 07:40:47.862454 PCI: 00:04.0: enabled 1
762 07:40:47.866229 GENERIC: 0.0: enabled 1
763 07:40:47.869452 PCI: 00:05.0: enabled 1
764 07:40:47.869537 PCI: 00:06.0: enabled 0
765 07:40:47.872534 PCI: 00:07.0: enabled 0
766 07:40:47.876256 GENERIC: 0.0: enabled 1
767 07:40:47.879571 PCI: 00:07.1: enabled 0
768 07:40:47.882600 GENERIC: 1.0: enabled 1
769 07:40:47.882683 PCI: 00:07.2: enabled 0
770 07:40:47.885787 GENERIC: 0.0: enabled 1
771 07:40:47.889686 PCI: 00:07.3: enabled 0
772 07:40:47.892937 GENERIC: 1.0: enabled 1
773 07:40:47.896233 PCI: 00:08.0: enabled 1
774 07:40:47.896318 PCI: 00:09.0: enabled 0
775 07:40:47.899316 PCI: 00:0a.0: enabled 0
776 07:40:47.902484 PCI: 00:0d.0: enabled 1
777 07:40:47.905784 USB0 port 0: enabled 1
778 07:40:47.909029 USB3 port 0: enabled 1
779 07:40:47.912355 USB3 port 1: enabled 1
780 07:40:47.912439 USB3 port 2: enabled 0
781 07:40:47.916200 USB3 port 3: enabled 0
782 07:40:47.919512 PCI: 00:0d.1: enabled 0
783 07:40:47.922682 PCI: 00:0d.2: enabled 0
784 07:40:47.925956 GENERIC: 0.0: enabled 1
785 07:40:47.926040 PCI: 00:0d.3: enabled 0
786 07:40:47.929187 PCI: 00:0e.0: enabled 0
787 07:40:47.932742 PCI: 00:10.2: enabled 1
788 07:40:47.935516 PCI: 00:10.6: enabled 0
789 07:40:47.939239 PCI: 00:10.7: enabled 0
790 07:40:47.939322 PCI: 00:12.0: enabled 0
791 07:40:47.942706 PCI: 00:12.6: enabled 0
792 07:40:47.945754 PCI: 00:13.0: enabled 0
793 07:40:47.948922 PCI: 00:14.0: enabled 1
794 07:40:47.949022 USB0 port 0: enabled 1
795 07:40:47.952514 USB2 port 0: enabled 0
796 07:40:47.955848 USB2 port 1: enabled 1
797 07:40:47.959023 USB2 port 2: enabled 1
798 07:40:47.962480 USB2 port 3: enabled 0
799 07:40:47.965445 USB2 port 4: enabled 1
800 07:40:47.965528 USB2 port 5: enabled 0
801 07:40:47.969217 USB2 port 6: enabled 0
802 07:40:47.972504 USB2 port 7: enabled 0
803 07:40:47.975555 USB2 port 8: enabled 0
804 07:40:47.978908 USB2 port 9: enabled 0
805 07:40:47.982635 USB3 port 0: enabled 0
806 07:40:47.982718 USB3 port 1: enabled 1
807 07:40:47.985512 USB3 port 2: enabled 0
808 07:40:47.989129 USB3 port 3: enabled 0
809 07:40:47.992128 PCI: 00:14.1: enabled 0
810 07:40:47.995477 PCI: 00:14.2: enabled 1
811 07:40:47.995598 PCI: 00:14.3: enabled 1
812 07:40:47.998690 GENERIC: 0.0: enabled 1
813 07:40:48.002513 PCI: 00:15.0: enabled 1
814 07:40:48.005731 I2C: 00:1a: enabled 1
815 07:40:48.008978 I2C: 00:31: enabled 1
816 07:40:48.009060 I2C: 00:32: enabled 1
817 07:40:48.012409 PCI: 00:15.1: enabled 1
818 07:40:48.015326 I2C: 00:10: enabled 1
819 07:40:48.018780 PCI: 00:15.2: enabled 1
820 07:40:48.018923 PCI: 00:15.3: enabled 1
821 07:40:48.022513 PCI: 00:16.0: enabled 1
822 07:40:48.025623 PCI: 00:16.1: enabled 0
823 07:40:48.028870 PCI: 00:16.2: enabled 0
824 07:40:48.032237 PCI: 00:16.3: enabled 0
825 07:40:48.032318 PCI: 00:16.4: enabled 0
826 07:40:48.035640 PCI: 00:16.5: enabled 0
827 07:40:48.038779 PCI: 00:17.0: enabled 1
828 07:40:48.041993 PCI: 00:19.0: enabled 0
829 07:40:48.045583 PCI: 00:19.1: enabled 1
830 07:40:48.045666 I2C: 00:15: enabled 1
831 07:40:48.049374 PCI: 00:19.2: enabled 0
832 07:40:48.053977 PCI: 00:1d.0: enabled 1
833 07:40:48.054136 GENERIC: 0.0: enabled 1
834 07:40:48.056865 PCI: 00:1e.0: enabled 1
835 07:40:48.060165 PCI: 00:1e.1: enabled 0
836 07:40:48.063528 PCI: 00:1e.2: enabled 1
837 07:40:48.063612 SPI: 00: enabled 1
838 07:40:48.066638 PCI: 00:1e.3: enabled 1
839 07:40:48.070185 SPI: 00: enabled 1
840 07:40:48.073571 PCI: 00:1f.0: enabled 1
841 07:40:48.073655 PNP: 0c09.0: enabled 1
842 07:40:48.076641 PCI: 00:1f.1: enabled 0
843 07:40:48.079980 PCI: 00:1f.2: enabled 1
844 07:40:48.131854 GENERIC: 0.0: enabled 1
845 07:40:48.131961 GENERIC: 0.0: enabled 1
846 07:40:48.132219 GENERIC: 1.0: enabled 1
847 07:40:48.132329 PCI: 00:1f.3: enabled 1
848 07:40:48.132421 PCI: 00:1f.4: enabled 0
849 07:40:48.132511 PCI: 00:1f.5: enabled 1
850 07:40:48.132569 PCI: 00:1f.6: enabled 0
851 07:40:48.132636 PCI: 00:1f.7: enabled 0
852 07:40:48.132694 CPU_CLUSTER: 0: enabled 1
853 07:40:48.132749 APIC: 00: enabled 1
854 07:40:48.132804 APIC: 01: enabled 1
855 07:40:48.132858 APIC: 03: enabled 1
856 07:40:48.132913 APIC: 07: enabled 1
857 07:40:48.132967 APIC: 05: enabled 1
858 07:40:48.133021 APIC: 04: enabled 1
859 07:40:48.133261 APIC: 02: enabled 1
860 07:40:48.133346 APIC: 06: enabled 1
861 07:40:48.133409 Root Device scanning...
862 07:40:48.133478 scan_static_bus for Root Device
863 07:40:48.133540 DOMAIN: 0000 enabled
864 07:40:48.142239 CPU_CLUSTER: 0 enabled
865 07:40:48.142355 DOMAIN: 0000 scanning...
866 07:40:48.145569 PCI: pci_scan_bus for bus 00
867 07:40:48.145652 PCI: 00:00.0 [8086/0000] ops
868 07:40:48.148645 PCI: 00:00.0 [8086/9a12] enabled
869 07:40:48.148728 PCI: 00:02.0 [8086/0000] bus ops
870 07:40:48.152435 PCI: 00:02.0 [8086/9a40] enabled
871 07:40:48.155544 PCI: 00:04.0 [8086/0000] bus ops
872 07:40:48.158715 PCI: 00:04.0 [8086/9a03] enabled
873 07:40:48.162026 PCI: 00:05.0 [8086/9a19] enabled
874 07:40:48.165851 PCI: 00:07.0 [0000/0000] hidden
875 07:40:48.168940 PCI: 00:08.0 [8086/9a11] enabled
876 07:40:48.172627 PCI: 00:0a.0 [8086/9a0d] disabled
877 07:40:48.175508 PCI: 00:0d.0 [8086/0000] bus ops
878 07:40:48.178991 PCI: 00:0d.0 [8086/9a13] enabled
879 07:40:48.182508 PCI: 00:14.0 [8086/0000] bus ops
880 07:40:48.186144 PCI: 00:14.0 [8086/a0ed] enabled
881 07:40:48.189460 PCI: 00:14.2 [8086/a0ef] enabled
882 07:40:48.192133 PCI: 00:14.3 [8086/0000] bus ops
883 07:40:48.195628 PCI: 00:14.3 [8086/a0f0] enabled
884 07:40:48.198900 PCI: 00:15.0 [8086/0000] bus ops
885 07:40:48.202279 PCI: 00:15.0 [8086/a0e8] enabled
886 07:40:48.205604 PCI: 00:15.1 [8086/0000] bus ops
887 07:40:48.208873 PCI: 00:15.1 [8086/a0e9] enabled
888 07:40:48.212502 PCI: 00:15.2 [8086/0000] bus ops
889 07:40:48.215951 PCI: 00:15.2 [8086/a0ea] enabled
890 07:40:48.219181 PCI: 00:15.3 [8086/0000] bus ops
891 07:40:48.222483 PCI: 00:15.3 [8086/a0eb] enabled
892 07:40:48.225882 PCI: 00:16.0 [8086/0000] ops
893 07:40:48.228929 PCI: 00:16.0 [8086/a0e0] enabled
894 07:40:48.236045 PCI: Static device PCI: 00:17.0 not found, disabling it.
895 07:40:48.239387 PCI: 00:19.0 [8086/0000] bus ops
896 07:40:48.242437 PCI: 00:19.0 [8086/a0c5] disabled
897 07:40:48.245610 PCI: 00:19.1 [8086/0000] bus ops
898 07:40:48.249369 PCI: 00:19.1 [8086/a0c6] enabled
899 07:40:48.252562 PCI: 00:1d.0 [8086/0000] bus ops
900 07:40:48.255735 PCI: 00:1d.0 [8086/a0b0] enabled
901 07:40:48.259541 PCI: 00:1e.0 [8086/0000] ops
902 07:40:48.262714 PCI: 00:1e.0 [8086/a0a8] enabled
903 07:40:48.265910 PCI: 00:1e.2 [8086/0000] bus ops
904 07:40:48.269135 PCI: 00:1e.2 [8086/a0aa] enabled
905 07:40:48.272255 PCI: 00:1e.3 [8086/0000] bus ops
906 07:40:48.276035 PCI: 00:1e.3 [8086/a0ab] enabled
907 07:40:48.279115 PCI: 00:1f.0 [8086/0000] bus ops
908 07:40:48.282317 PCI: 00:1f.0 [8086/a087] enabled
909 07:40:48.282399 RTC Init
910 07:40:48.286003 Set power on after power failure.
911 07:40:48.289243 Disabling Deep S3
912 07:40:48.289328 Disabling Deep S3
913 07:40:48.292378 Disabling Deep S4
914 07:40:48.292460 Disabling Deep S4
915 07:40:48.295969 Disabling Deep S5
916 07:40:48.296051 Disabling Deep S5
917 07:40:48.298968 PCI: 00:1f.2 [0000/0000] hidden
918 07:40:48.302626 PCI: 00:1f.3 [8086/0000] bus ops
919 07:40:48.305547 PCI: 00:1f.3 [8086/a0c8] enabled
920 07:40:48.309099 PCI: 00:1f.5 [8086/0000] bus ops
921 07:40:48.312644 PCI: 00:1f.5 [8086/a0a4] enabled
922 07:40:48.315565 PCI: Leftover static devices:
923 07:40:48.318905 PCI: 00:10.2
924 07:40:48.318986 PCI: 00:10.6
925 07:40:48.322154 PCI: 00:10.7
926 07:40:48.322235 PCI: 00:06.0
927 07:40:48.322298 PCI: 00:07.1
928 07:40:48.325475 PCI: 00:07.2
929 07:40:48.325600 PCI: 00:07.3
930 07:40:48.329233 PCI: 00:09.0
931 07:40:48.329315 PCI: 00:0d.1
932 07:40:48.332547 PCI: 00:0d.2
933 07:40:48.332629 PCI: 00:0d.3
934 07:40:48.332696 PCI: 00:0e.0
935 07:40:48.335698 PCI: 00:12.0
936 07:40:48.335781 PCI: 00:12.6
937 07:40:48.338930 PCI: 00:13.0
938 07:40:48.339012 PCI: 00:14.1
939 07:40:48.339078 PCI: 00:16.1
940 07:40:48.342700 PCI: 00:16.2
941 07:40:48.342783 PCI: 00:16.3
942 07:40:48.346061 PCI: 00:16.4
943 07:40:48.346144 PCI: 00:16.5
944 07:40:48.346209 PCI: 00:17.0
945 07:40:48.349122 PCI: 00:19.2
946 07:40:48.349209 PCI: 00:1e.1
947 07:40:48.352750 PCI: 00:1f.1
948 07:40:48.352836 PCI: 00:1f.4
949 07:40:48.352902 PCI: 00:1f.6
950 07:40:48.355998 PCI: 00:1f.7
951 07:40:48.359234 PCI: Check your devicetree.cb.
952 07:40:48.362457 PCI: 00:02.0 scanning...
953 07:40:48.365802 scan_generic_bus for PCI: 00:02.0
954 07:40:48.368956 scan_generic_bus for PCI: 00:02.0 done
955 07:40:48.372839 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
956 07:40:48.376027 PCI: 00:04.0 scanning...
957 07:40:48.379148 scan_generic_bus for PCI: 00:04.0
958 07:40:48.382329 GENERIC: 0.0 enabled
959 07:40:48.389213 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
960 07:40:48.392453 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
961 07:40:48.395616 PCI: 00:0d.0 scanning...
962 07:40:48.399476 scan_static_bus for PCI: 00:0d.0
963 07:40:48.399564 USB0 port 0 enabled
964 07:40:48.402514 USB0 port 0 scanning...
965 07:40:48.406053 scan_static_bus for USB0 port 0
966 07:40:48.409129 USB3 port 0 enabled
967 07:40:48.409212 USB3 port 1 enabled
968 07:40:48.412390 USB3 port 2 disabled
969 07:40:48.415819 USB3 port 3 disabled
970 07:40:48.419494 USB3 port 0 scanning...
971 07:40:48.422666 scan_static_bus for USB3 port 0
972 07:40:48.425738 scan_static_bus for USB3 port 0 done
973 07:40:48.429305 scan_bus: bus USB3 port 0 finished in 6 msecs
974 07:40:48.432467 USB3 port 1 scanning...
975 07:40:48.435684 scan_static_bus for USB3 port 1
976 07:40:48.439236 scan_static_bus for USB3 port 1 done
977 07:40:48.442533 scan_bus: bus USB3 port 1 finished in 6 msecs
978 07:40:48.446250 scan_static_bus for USB0 port 0 done
979 07:40:48.452799 scan_bus: bus USB0 port 0 finished in 43 msecs
980 07:40:48.455784 scan_static_bus for PCI: 00:0d.0 done
981 07:40:48.459657 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
982 07:40:48.462779 PCI: 00:14.0 scanning...
983 07:40:48.466409 scan_static_bus for PCI: 00:14.0
984 07:40:48.469521 USB0 port 0 enabled
985 07:40:48.472709 USB0 port 0 scanning...
986 07:40:48.475862 scan_static_bus for USB0 port 0
987 07:40:48.475947 USB2 port 0 disabled
988 07:40:48.479129 USB2 port 1 enabled
989 07:40:48.479205 USB2 port 2 enabled
990 07:40:48.482386 USB2 port 3 disabled
991 07:40:48.486042 USB2 port 4 enabled
992 07:40:48.486140 USB2 port 5 disabled
993 07:40:48.489188 USB2 port 6 disabled
994 07:40:48.492465 USB2 port 7 disabled
995 07:40:48.492547 USB2 port 8 disabled
996 07:40:48.496202 USB2 port 9 disabled
997 07:40:48.499506 USB3 port 0 disabled
998 07:40:48.499590 USB3 port 1 enabled
999 07:40:48.502680 USB3 port 2 disabled
1000 07:40:48.506057 USB3 port 3 disabled
1001 07:40:48.506139 USB2 port 1 scanning...
1002 07:40:48.509004 scan_static_bus for USB2 port 1
1003 07:40:48.512727 scan_static_bus for USB2 port 1 done
1004 07:40:48.518970 scan_bus: bus USB2 port 1 finished in 6 msecs
1005 07:40:48.522546 USB2 port 2 scanning...
1006 07:40:48.526000 scan_static_bus for USB2 port 2
1007 07:40:48.529003 scan_static_bus for USB2 port 2 done
1008 07:40:48.532770 scan_bus: bus USB2 port 2 finished in 6 msecs
1009 07:40:48.536029 USB2 port 4 scanning...
1010 07:40:48.539118 scan_static_bus for USB2 port 4
1011 07:40:48.542565 scan_static_bus for USB2 port 4 done
1012 07:40:48.546153 scan_bus: bus USB2 port 4 finished in 6 msecs
1013 07:40:48.549268 USB3 port 1 scanning...
1014 07:40:48.552434 scan_static_bus for USB3 port 1
1015 07:40:48.555540 scan_static_bus for USB3 port 1 done
1016 07:40:48.562542 scan_bus: bus USB3 port 1 finished in 6 msecs
1017 07:40:48.565706 scan_static_bus for USB0 port 0 done
1018 07:40:48.569479 scan_bus: bus USB0 port 0 finished in 93 msecs
1019 07:40:48.572464 scan_static_bus for PCI: 00:14.0 done
1020 07:40:48.578741 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
1021 07:40:48.582628 PCI: 00:14.3 scanning...
1022 07:40:48.585813 scan_static_bus for PCI: 00:14.3
1023 07:40:48.585896 GENERIC: 0.0 enabled
1024 07:40:48.588947 scan_static_bus for PCI: 00:14.3 done
1025 07:40:48.595871 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1026 07:40:48.599072 PCI: 00:15.0 scanning...
1027 07:40:48.602278 scan_static_bus for PCI: 00:15.0
1028 07:40:48.602360 I2C: 00:1a enabled
1029 07:40:48.605467 I2C: 00:31 enabled
1030 07:40:48.605573 I2C: 00:32 enabled
1031 07:40:48.611811 scan_static_bus for PCI: 00:15.0 done
1032 07:40:48.615493 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1033 07:40:48.618685 PCI: 00:15.1 scanning...
1034 07:40:48.622291 scan_static_bus for PCI: 00:15.1
1035 07:40:48.622373 I2C: 00:10 enabled
1036 07:40:48.629226 scan_static_bus for PCI: 00:15.1 done
1037 07:40:48.633138 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1038 07:40:48.633264 PCI: 00:15.2 scanning...
1039 07:40:48.636601 scan_static_bus for PCI: 00:15.2
1040 07:40:48.643609 scan_static_bus for PCI: 00:15.2 done
1041 07:40:48.646649 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1042 07:40:48.649709 PCI: 00:15.3 scanning...
1043 07:40:48.653384 scan_static_bus for PCI: 00:15.3
1044 07:40:48.656333 scan_static_bus for PCI: 00:15.3 done
1045 07:40:48.659756 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1046 07:40:48.663311 PCI: 00:19.1 scanning...
1047 07:40:48.666469 scan_static_bus for PCI: 00:19.1
1048 07:40:48.669800 I2C: 00:15 enabled
1049 07:40:48.673689 scan_static_bus for PCI: 00:19.1 done
1050 07:40:48.676780 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1051 07:40:48.679835 PCI: 00:1d.0 scanning...
1052 07:40:48.683174 do_pci_scan_bridge for PCI: 00:1d.0
1053 07:40:48.686376 PCI: pci_scan_bus for bus 01
1054 07:40:48.689612 PCI: 01:00.0 [1c5c/174a] enabled
1055 07:40:48.693186 GENERIC: 0.0 enabled
1056 07:40:48.696307 Enabling Common Clock Configuration
1057 07:40:48.699608 L1 Sub-State supported from root port 29
1058 07:40:48.703204 L1 Sub-State Support = 0xf
1059 07:40:48.706593 CommonModeRestoreTime = 0x28
1060 07:40:48.709667 Power On Value = 0x16, Power On Scale = 0x0
1061 07:40:48.713392 ASPM: Enabled L1
1062 07:40:48.716565 PCIe: Max_Payload_Size adjusted to 128
1063 07:40:48.719862 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1064 07:40:48.723144 PCI: 00:1e.2 scanning...
1065 07:40:48.726660 scan_generic_bus for PCI: 00:1e.2
1066 07:40:48.729649 SPI: 00 enabled
1067 07:40:48.736400 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1068 07:40:48.740007 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1069 07:40:48.742909 PCI: 00:1e.3 scanning...
1070 07:40:48.746597 scan_generic_bus for PCI: 00:1e.3
1071 07:40:48.746680 SPI: 00 enabled
1072 07:40:48.752954 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1073 07:40:48.760112 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1074 07:40:48.760195 PCI: 00:1f.0 scanning...
1075 07:40:48.763073 scan_static_bus for PCI: 00:1f.0
1076 07:40:48.766673 PNP: 0c09.0 enabled
1077 07:40:48.769664 PNP: 0c09.0 scanning...
1078 07:40:48.773179 scan_static_bus for PNP: 0c09.0
1079 07:40:48.776267 scan_static_bus for PNP: 0c09.0 done
1080 07:40:48.780087 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1081 07:40:48.786367 scan_static_bus for PCI: 00:1f.0 done
1082 07:40:48.789497 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1083 07:40:48.792844 PCI: 00:1f.2 scanning...
1084 07:40:48.796560 scan_static_bus for PCI: 00:1f.2
1085 07:40:48.796644 GENERIC: 0.0 enabled
1086 07:40:48.799661 GENERIC: 0.0 scanning...
1087 07:40:48.803517 scan_static_bus for GENERIC: 0.0
1088 07:40:48.806634 GENERIC: 0.0 enabled
1089 07:40:48.809899 GENERIC: 1.0 enabled
1090 07:40:48.812992 scan_static_bus for GENERIC: 0.0 done
1091 07:40:48.816357 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1092 07:40:48.820145 scan_static_bus for PCI: 00:1f.2 done
1093 07:40:48.826505 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1094 07:40:48.826588 PCI: 00:1f.3 scanning...
1095 07:40:48.829810 scan_static_bus for PCI: 00:1f.3
1096 07:40:48.836543 scan_static_bus for PCI: 00:1f.3 done
1097 07:40:48.839949 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1098 07:40:48.843642 PCI: 00:1f.5 scanning...
1099 07:40:48.846486 scan_generic_bus for PCI: 00:1f.5
1100 07:40:48.850370 scan_generic_bus for PCI: 00:1f.5 done
1101 07:40:48.853244 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1102 07:40:48.860313 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1103 07:40:48.863607 scan_static_bus for Root Device done
1104 07:40:48.869814 scan_bus: bus Root Device finished in 736 msecs
1105 07:40:48.869896 done
1106 07:40:48.876684 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1107 07:40:48.879680 Chrome EC: UHEPI supported
1108 07:40:48.883310 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1109 07:40:48.890192 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1110 07:40:48.893433 SPI flash protection: WPSW=0 SRP0=0
1111 07:40:48.899662 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1112 07:40:48.906627 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1113 07:40:48.906708 found VGA at PCI: 00:02.0
1114 07:40:48.909786 Setting up VGA for PCI: 00:02.0
1115 07:40:48.916774 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1116 07:40:48.920121 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1117 07:40:48.923284 Allocating resources...
1118 07:40:48.926565 Reading resources...
1119 07:40:48.929664 Root Device read_resources bus 0 link: 0
1120 07:40:48.933491 DOMAIN: 0000 read_resources bus 0 link: 0
1121 07:40:48.939781 PCI: 00:04.0 read_resources bus 1 link: 0
1122 07:40:48.942995 PCI: 00:04.0 read_resources bus 1 link: 0 done
1123 07:40:48.950347 PCI: 00:0d.0 read_resources bus 0 link: 0
1124 07:40:48.953193 USB0 port 0 read_resources bus 0 link: 0
1125 07:40:48.960317 USB0 port 0 read_resources bus 0 link: 0 done
1126 07:40:48.963222 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1127 07:40:48.966698 PCI: 00:14.0 read_resources bus 0 link: 0
1128 07:40:48.973462 USB0 port 0 read_resources bus 0 link: 0
1129 07:40:48.976706 USB0 port 0 read_resources bus 0 link: 0 done
1130 07:40:48.983948 PCI: 00:14.0 read_resources bus 0 link: 0 done
1131 07:40:48.986895 PCI: 00:14.3 read_resources bus 0 link: 0
1132 07:40:48.993577 PCI: 00:14.3 read_resources bus 0 link: 0 done
1133 07:40:48.996627 PCI: 00:15.0 read_resources bus 0 link: 0
1134 07:40:49.003835 PCI: 00:15.0 read_resources bus 0 link: 0 done
1135 07:40:49.006787 PCI: 00:15.1 read_resources bus 0 link: 0
1136 07:40:49.013810 PCI: 00:15.1 read_resources bus 0 link: 0 done
1137 07:40:49.017075 PCI: 00:19.1 read_resources bus 0 link: 0
1138 07:40:49.024129 PCI: 00:19.1 read_resources bus 0 link: 0 done
1139 07:40:49.027223 PCI: 00:1d.0 read_resources bus 1 link: 0
1140 07:40:49.034174 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1141 07:40:49.037380 PCI: 00:1e.2 read_resources bus 2 link: 0
1142 07:40:49.043867 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1143 07:40:49.047646 PCI: 00:1e.3 read_resources bus 3 link: 0
1144 07:40:49.054066 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1145 07:40:49.057337 PCI: 00:1f.0 read_resources bus 0 link: 0
1146 07:40:49.064180 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1147 07:40:49.067254 PCI: 00:1f.2 read_resources bus 0 link: 0
1148 07:40:49.070606 GENERIC: 0.0 read_resources bus 0 link: 0
1149 07:40:49.077607 GENERIC: 0.0 read_resources bus 0 link: 0 done
1150 07:40:49.080990 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1151 07:40:49.088573 DOMAIN: 0000 read_resources bus 0 link: 0 done
1152 07:40:49.091562 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1153 07:40:49.098262 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1154 07:40:49.101361 Root Device read_resources bus 0 link: 0 done
1155 07:40:49.105065 Done reading resources.
1156 07:40:49.112016 Show resources in subtree (Root Device)...After reading.
1157 07:40:49.115184 Root Device child on link 0 DOMAIN: 0000
1158 07:40:49.118185 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1159 07:40:49.128402 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1160 07:40:49.138007 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1161 07:40:49.141283 PCI: 00:00.0
1162 07:40:49.148140 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1163 07:40:49.158309 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1164 07:40:49.167964 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1165 07:40:49.178039 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1166 07:40:49.188168 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1167 07:40:49.198326 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1168 07:40:49.205151 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1169 07:40:49.215044 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1170 07:40:49.224564 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1171 07:40:49.234972 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1172 07:40:49.245065 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1173 07:40:49.251408 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1174 07:40:49.261565 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1175 07:40:49.271756 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1176 07:40:49.281577 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1177 07:40:49.291705 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1178 07:40:49.301802 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1179 07:40:49.308248 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1180 07:40:49.318349 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1181 07:40:49.328008 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1182 07:40:49.331204 PCI: 00:02.0
1183 07:40:49.341618 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1184 07:40:49.351171 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1185 07:40:49.358168 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1186 07:40:49.364566 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1187 07:40:49.374774 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1188 07:40:49.374865 GENERIC: 0.0
1189 07:40:49.377950 PCI: 00:05.0
1190 07:40:49.388086 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1191 07:40:49.391211 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1192 07:40:49.394877 GENERIC: 0.0
1193 07:40:49.394958 PCI: 00:08.0
1194 07:40:49.404809 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1195 07:40:49.408088 PCI: 00:0a.0
1196 07:40:49.411152 PCI: 00:0d.0 child on link 0 USB0 port 0
1197 07:40:49.421044 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1198 07:40:49.424603 USB0 port 0 child on link 0 USB3 port 0
1199 07:40:49.428094 USB3 port 0
1200 07:40:49.428175 USB3 port 1
1201 07:40:49.431292 USB3 port 2
1202 07:40:49.431420 USB3 port 3
1203 07:40:49.438239 PCI: 00:14.0 child on link 0 USB0 port 0
1204 07:40:49.448622 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1205 07:40:49.451768 USB0 port 0 child on link 0 USB2 port 0
1206 07:40:49.454918 USB2 port 0
1207 07:40:49.454999 USB2 port 1
1208 07:40:49.458046 USB2 port 2
1209 07:40:49.458127 USB2 port 3
1210 07:40:49.461824 USB2 port 4
1211 07:40:49.461905 USB2 port 5
1212 07:40:49.464862 USB2 port 6
1213 07:40:49.464943 USB2 port 7
1214 07:40:49.468123 USB2 port 8
1215 07:40:49.468204 USB2 port 9
1216 07:40:49.471866 USB3 port 0
1217 07:40:49.471947 USB3 port 1
1218 07:40:49.475160 USB3 port 2
1219 07:40:49.475241 USB3 port 3
1220 07:40:49.478388 PCI: 00:14.2
1221 07:40:49.488249 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1222 07:40:49.498012 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1223 07:40:49.501208 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1224 07:40:49.511578 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1225 07:40:49.514895 GENERIC: 0.0
1226 07:40:49.517887 PCI: 00:15.0 child on link 0 I2C: 00:1a
1227 07:40:49.528239 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1228 07:40:49.531461 I2C: 00:1a
1229 07:40:49.531541 I2C: 00:31
1230 07:40:49.534650 I2C: 00:32
1231 07:40:49.537771 PCI: 00:15.1 child on link 0 I2C: 00:10
1232 07:40:49.547789 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1233 07:40:49.547871 I2C: 00:10
1234 07:40:49.551475 PCI: 00:15.2
1235 07:40:49.561268 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1236 07:40:49.561352 PCI: 00:15.3
1237 07:40:49.570853 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1238 07:40:49.574216 PCI: 00:16.0
1239 07:40:49.584437 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1240 07:40:49.584542 PCI: 00:19.0
1241 07:40:49.590909 PCI: 00:19.1 child on link 0 I2C: 00:15
1242 07:40:49.600881 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1243 07:40:49.600988 I2C: 00:15
1244 07:40:49.604531 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1245 07:40:49.614182 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1246 07:40:49.624080 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1247 07:40:49.634396 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1248 07:40:49.634475 GENERIC: 0.0
1249 07:40:49.637564 PCI: 01:00.0
1250 07:40:49.647601 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1251 07:40:49.657230 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1252 07:40:49.664462 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1253 07:40:49.667161 PCI: 00:1e.0
1254 07:40:49.677111 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1255 07:40:49.680902 PCI: 00:1e.2 child on link 0 SPI: 00
1256 07:40:49.690445 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1257 07:40:49.694245 SPI: 00
1258 07:40:49.697326 PCI: 00:1e.3 child on link 0 SPI: 00
1259 07:40:49.707536 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1260 07:40:49.707621 SPI: 00
1261 07:40:49.714229 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1262 07:40:49.721062 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1263 07:40:49.723934 PNP: 0c09.0
1264 07:40:49.731101 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1265 07:40:49.737570 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1266 07:40:49.747131 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1267 07:40:49.753893 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1268 07:40:49.760758 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1269 07:40:49.760864 GENERIC: 0.0
1270 07:40:49.763793 GENERIC: 1.0
1271 07:40:49.763894 PCI: 00:1f.3
1272 07:40:49.774277 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1273 07:40:49.784151 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1274 07:40:49.787305 PCI: 00:1f.5
1275 07:40:49.797467 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1276 07:40:49.800621 CPU_CLUSTER: 0 child on link 0 APIC: 00
1277 07:40:49.800727 APIC: 00
1278 07:40:49.804232 APIC: 01
1279 07:40:49.804316 APIC: 03
1280 07:40:49.804381 APIC: 07
1281 07:40:49.807446 APIC: 05
1282 07:40:49.807545 APIC: 04
1283 07:40:49.810561 APIC: 02
1284 07:40:49.810664 APIC: 06
1285 07:40:49.817522 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1286 07:40:49.823945 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1287 07:40:49.830315 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1288 07:40:49.836923 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1289 07:40:49.840325 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1290 07:40:49.843653 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1291 07:40:49.850643 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1292 07:40:49.856846 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1293 07:40:49.863620 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1294 07:40:49.870409 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1295 07:40:49.876850 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1296 07:40:49.883644 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1297 07:40:49.893873 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1298 07:40:49.900180 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1299 07:40:49.907129 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1300 07:40:49.910439 DOMAIN: 0000: Resource ranges:
1301 07:40:49.913541 * Base: 1000, Size: 800, Tag: 100
1302 07:40:49.916764 * Base: 1900, Size: e700, Tag: 100
1303 07:40:49.923608 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1304 07:40:49.930191 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1305 07:40:49.936970 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1306 07:40:49.943762 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1307 07:40:49.950178 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1308 07:40:49.960280 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1309 07:40:49.966765 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1310 07:40:49.973692 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1311 07:40:49.983826 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1312 07:40:49.990368 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1313 07:40:49.996869 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1314 07:40:50.006829 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1315 07:40:50.013603 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1316 07:40:50.020318 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1317 07:40:50.030248 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1318 07:40:50.036841 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1319 07:40:50.043256 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1320 07:40:50.053525 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1321 07:40:50.060461 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1322 07:40:50.067000 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1323 07:40:50.076898 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1324 07:40:50.083255 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1325 07:40:50.090120 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1326 07:40:50.096702 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1327 07:40:50.107084 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1328 07:40:50.110002 DOMAIN: 0000: Resource ranges:
1329 07:40:50.113672 * Base: 7fc00000, Size: 40400000, Tag: 200
1330 07:40:50.116612 * Base: d0000000, Size: 28000000, Tag: 200
1331 07:40:50.123148 * Base: fa000000, Size: 1000000, Tag: 200
1332 07:40:50.126564 * Base: fb001000, Size: 2fff000, Tag: 200
1333 07:40:50.130481 * Base: fe010000, Size: 2e000, Tag: 200
1334 07:40:50.133766 * Base: fe03f000, Size: d41000, Tag: 200
1335 07:40:50.140000 * Base: fed88000, Size: 8000, Tag: 200
1336 07:40:50.143657 * Base: fed93000, Size: d000, Tag: 200
1337 07:40:50.146438 * Base: feda2000, Size: 1e000, Tag: 200
1338 07:40:50.149902 * Base: fede0000, Size: 1220000, Tag: 200
1339 07:40:50.156942 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1340 07:40:50.163229 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1341 07:40:50.170099 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1342 07:40:50.176882 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1343 07:40:50.183438 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1344 07:40:50.189649 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1345 07:40:50.196500 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1346 07:40:50.203567 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1347 07:40:50.209888 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1348 07:40:50.216616 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1349 07:40:50.223505 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1350 07:40:50.230106 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1351 07:40:50.236504 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1352 07:40:50.243497 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1353 07:40:50.249752 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1354 07:40:50.256934 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1355 07:40:50.263109 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1356 07:40:50.270162 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1357 07:40:50.276554 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1358 07:40:50.283281 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1359 07:40:50.289957 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1360 07:40:50.296899 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1361 07:40:50.303137 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1362 07:40:50.309608 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1363 07:40:50.316822 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1364 07:40:50.319962 PCI: 00:1d.0: Resource ranges:
1365 07:40:50.326330 * Base: 7fc00000, Size: 100000, Tag: 200
1366 07:40:50.333296 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1367 07:40:50.339416 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1368 07:40:50.346589 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1369 07:40:50.352961 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1370 07:40:50.359664 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1371 07:40:50.366306 Root Device assign_resources, bus 0 link: 0
1372 07:40:50.369688 DOMAIN: 0000 assign_resources, bus 0 link: 0
1373 07:40:50.379847 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1374 07:40:50.386970 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1375 07:40:50.393444 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1376 07:40:50.403006 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1377 07:40:50.406286 PCI: 00:04.0 assign_resources, bus 1 link: 0
1378 07:40:50.413348 PCI: 00:04.0 assign_resources, bus 1 link: 0
1379 07:40:50.419734 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1380 07:40:50.429859 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1381 07:40:50.436487 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1382 07:40:50.439522 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1383 07:40:50.446817 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1384 07:40:50.453211 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1385 07:40:50.459727 PCI: 00:14.0 assign_resources, bus 0 link: 0
1386 07:40:50.463531 PCI: 00:14.0 assign_resources, bus 0 link: 0
1387 07:40:50.473354 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1388 07:40:50.479903 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1389 07:40:50.486816 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1390 07:40:50.493251 PCI: 00:14.3 assign_resources, bus 0 link: 0
1391 07:40:50.496815 PCI: 00:14.3 assign_resources, bus 0 link: 0
1392 07:40:50.506476 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1393 07:40:50.510293 PCI: 00:15.0 assign_resources, bus 0 link: 0
1394 07:40:50.513382 PCI: 00:15.0 assign_resources, bus 0 link: 0
1395 07:40:50.523575 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1396 07:40:50.526779 PCI: 00:15.1 assign_resources, bus 0 link: 0
1397 07:40:50.533180 PCI: 00:15.1 assign_resources, bus 0 link: 0
1398 07:40:50.540082 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1399 07:40:50.549772 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1400 07:40:50.556426 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1401 07:40:50.566243 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1402 07:40:50.570136 PCI: 00:19.1 assign_resources, bus 0 link: 0
1403 07:40:50.573264 PCI: 00:19.1 assign_resources, bus 0 link: 0
1404 07:40:50.582921 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1405 07:40:50.593398 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1406 07:40:50.603378 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1407 07:40:50.606343 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1408 07:40:50.612981 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1409 07:40:50.623044 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1410 07:40:50.629399 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1411 07:40:50.635941 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1412 07:40:50.643029 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1413 07:40:50.646268 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1414 07:40:50.653160 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1415 07:40:50.659249 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1416 07:40:50.666270 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1417 07:40:50.669510 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1418 07:40:50.675968 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1419 07:40:50.679568 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1420 07:40:50.682513 LPC: Trying to open IO window from 800 size 1ff
1421 07:40:50.693033 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1422 07:40:50.699584 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1423 07:40:50.709594 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1424 07:40:50.713213 DOMAIN: 0000 assign_resources, bus 0 link: 0
1425 07:40:50.719855 Root Device assign_resources, bus 0 link: 0
1426 07:40:50.719955 Done setting resources.
1427 07:40:50.726401 Show resources in subtree (Root Device)...After assigning values.
1428 07:40:50.732719 Root Device child on link 0 DOMAIN: 0000
1429 07:40:50.736726 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1430 07:40:50.746264 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1431 07:40:50.756507 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1432 07:40:50.756620 PCI: 00:00.0
1433 07:40:50.765909 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1434 07:40:50.776314 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1435 07:40:50.786208 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1436 07:40:50.795792 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1437 07:40:50.802547 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1438 07:40:50.812944 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1439 07:40:50.822910 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1440 07:40:50.833064 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1441 07:40:50.842734 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1442 07:40:50.849739 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1443 07:40:50.859406 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1444 07:40:50.869664 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1445 07:40:50.879798 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1446 07:40:50.886227 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1447 07:40:50.896247 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1448 07:40:50.905842 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1449 07:40:50.916248 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1450 07:40:50.926083 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1451 07:40:50.935852 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1452 07:40:50.946290 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1453 07:40:50.946374 PCI: 00:02.0
1454 07:40:50.955794 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1455 07:40:50.968894 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1456 07:40:50.975974 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1457 07:40:50.982407 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1458 07:40:50.992828 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1459 07:40:50.992911 GENERIC: 0.0
1460 07:40:50.995743 PCI: 00:05.0
1461 07:40:51.005857 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1462 07:40:51.008804 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1463 07:40:51.012704 GENERIC: 0.0
1464 07:40:51.012829 PCI: 00:08.0
1465 07:40:51.025815 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1466 07:40:51.025897 PCI: 00:0a.0
1467 07:40:51.029356 PCI: 00:0d.0 child on link 0 USB0 port 0
1468 07:40:51.042638 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1469 07:40:51.045412 USB0 port 0 child on link 0 USB3 port 0
1470 07:40:51.045495 USB3 port 0
1471 07:40:51.048799 USB3 port 1
1472 07:40:51.048881 USB3 port 2
1473 07:40:51.052207 USB3 port 3
1474 07:40:51.055610 PCI: 00:14.0 child on link 0 USB0 port 0
1475 07:40:51.065707 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1476 07:40:51.072252 USB0 port 0 child on link 0 USB2 port 0
1477 07:40:51.072336 USB2 port 0
1478 07:40:51.075575 USB2 port 1
1479 07:40:51.075666 USB2 port 2
1480 07:40:51.079504 USB2 port 3
1481 07:40:51.079585 USB2 port 4
1482 07:40:51.082519 USB2 port 5
1483 07:40:51.082601 USB2 port 6
1484 07:40:51.085729 USB2 port 7
1485 07:40:51.085811 USB2 port 8
1486 07:40:51.088939 USB2 port 9
1487 07:40:51.092739 USB3 port 0
1488 07:40:51.092821 USB3 port 1
1489 07:40:51.095867 USB3 port 2
1490 07:40:51.095949 USB3 port 3
1491 07:40:51.099518 PCI: 00:14.2
1492 07:40:51.109025 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1493 07:40:51.118995 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1494 07:40:51.122633 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1495 07:40:51.132649 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1496 07:40:51.135599 GENERIC: 0.0
1497 07:40:51.139159 PCI: 00:15.0 child on link 0 I2C: 00:1a
1498 07:40:51.148786 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1499 07:40:51.152694 I2C: 00:1a
1500 07:40:51.152777 I2C: 00:31
1501 07:40:51.155610 I2C: 00:32
1502 07:40:51.159148 PCI: 00:15.1 child on link 0 I2C: 00:10
1503 07:40:51.168710 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1504 07:40:51.172477 I2C: 00:10
1505 07:40:51.172557 PCI: 00:15.2
1506 07:40:51.182094 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1507 07:40:51.185871 PCI: 00:15.3
1508 07:40:51.195557 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1509 07:40:51.195637 PCI: 00:16.0
1510 07:40:51.205570 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1511 07:40:51.209059 PCI: 00:19.0
1512 07:40:51.212333 PCI: 00:19.1 child on link 0 I2C: 00:15
1513 07:40:51.222347 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1514 07:40:51.225315 I2C: 00:15
1515 07:40:51.228757 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1516 07:40:51.239229 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1517 07:40:51.248833 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1518 07:40:51.261982 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1519 07:40:51.262063 GENERIC: 0.0
1520 07:40:51.265485 PCI: 01:00.0
1521 07:40:51.275195 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1522 07:40:51.285554 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1523 07:40:51.295616 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1524 07:40:51.295697 PCI: 00:1e.0
1525 07:40:51.309021 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1526 07:40:51.312010 PCI: 00:1e.2 child on link 0 SPI: 00
1527 07:40:51.322424 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1528 07:40:51.322506 SPI: 00
1529 07:40:51.328939 PCI: 00:1e.3 child on link 0 SPI: 00
1530 07:40:51.338866 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1531 07:40:51.338963 SPI: 00
1532 07:40:51.342062 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1533 07:40:51.352348 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1534 07:40:51.355444 PNP: 0c09.0
1535 07:40:51.362053 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1536 07:40:51.369018 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1537 07:40:51.375534 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1538 07:40:51.385157 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1539 07:40:51.392206 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1540 07:40:51.392307 GENERIC: 0.0
1541 07:40:51.395420 GENERIC: 1.0
1542 07:40:51.395534 PCI: 00:1f.3
1543 07:40:51.405829 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1544 07:40:51.415605 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1545 07:40:51.418692 PCI: 00:1f.5
1546 07:40:51.428990 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1547 07:40:51.432460 CPU_CLUSTER: 0 child on link 0 APIC: 00
1548 07:40:51.435530 APIC: 00
1549 07:40:51.435604 APIC: 01
1550 07:40:51.435665 APIC: 03
1551 07:40:51.439244 APIC: 07
1552 07:40:51.439343 APIC: 05
1553 07:40:51.442372 APIC: 04
1554 07:40:51.442452 APIC: 02
1555 07:40:51.442514 APIC: 06
1556 07:40:51.445433 Done allocating resources.
1557 07:40:51.452315 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1558 07:40:51.458784 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1559 07:40:51.462373 Configure GPIOs for I2S audio on UP4.
1560 07:40:51.469171 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1561 07:40:51.472184 Enabling resources...
1562 07:40:51.475528 PCI: 00:00.0 subsystem <- 8086/9a12
1563 07:40:51.479110 PCI: 00:00.0 cmd <- 06
1564 07:40:51.482718 PCI: 00:02.0 subsystem <- 8086/9a40
1565 07:40:51.482798 PCI: 00:02.0 cmd <- 03
1566 07:40:51.489499 PCI: 00:04.0 subsystem <- 8086/9a03
1567 07:40:51.489581 PCI: 00:04.0 cmd <- 02
1568 07:40:51.492284 PCI: 00:05.0 subsystem <- 8086/9a19
1569 07:40:51.496127 PCI: 00:05.0 cmd <- 02
1570 07:40:51.499483 PCI: 00:08.0 subsystem <- 8086/9a11
1571 07:40:51.502603 PCI: 00:08.0 cmd <- 06
1572 07:40:51.505799 PCI: 00:0d.0 subsystem <- 8086/9a13
1573 07:40:51.509087 PCI: 00:0d.0 cmd <- 02
1574 07:40:51.512363 PCI: 00:14.0 subsystem <- 8086/a0ed
1575 07:40:51.516191 PCI: 00:14.0 cmd <- 02
1576 07:40:51.519392 PCI: 00:14.2 subsystem <- 8086/a0ef
1577 07:40:51.522611 PCI: 00:14.2 cmd <- 02
1578 07:40:51.525931 PCI: 00:14.3 subsystem <- 8086/a0f0
1579 07:40:51.526010 PCI: 00:14.3 cmd <- 02
1580 07:40:51.532335 PCI: 00:15.0 subsystem <- 8086/a0e8
1581 07:40:51.532415 PCI: 00:15.0 cmd <- 02
1582 07:40:51.535958 PCI: 00:15.1 subsystem <- 8086/a0e9
1583 07:40:51.539572 PCI: 00:15.1 cmd <- 02
1584 07:40:51.542370 PCI: 00:15.2 subsystem <- 8086/a0ea
1585 07:40:51.546022 PCI: 00:15.2 cmd <- 02
1586 07:40:51.549366 PCI: 00:15.3 subsystem <- 8086/a0eb
1587 07:40:51.552394 PCI: 00:15.3 cmd <- 02
1588 07:40:51.556230 PCI: 00:16.0 subsystem <- 8086/a0e0
1589 07:40:51.559140 PCI: 00:16.0 cmd <- 02
1590 07:40:51.562899 PCI: 00:19.1 subsystem <- 8086/a0c6
1591 07:40:51.566098 PCI: 00:19.1 cmd <- 02
1592 07:40:51.569224 PCI: 00:1d.0 bridge ctrl <- 0013
1593 07:40:51.572818 PCI: 00:1d.0 subsystem <- 8086/a0b0
1594 07:40:51.572903 PCI: 00:1d.0 cmd <- 06
1595 07:40:51.579546 PCI: 00:1e.0 subsystem <- 8086/a0a8
1596 07:40:51.579626 PCI: 00:1e.0 cmd <- 06
1597 07:40:51.582709 PCI: 00:1e.2 subsystem <- 8086/a0aa
1598 07:40:51.585867 PCI: 00:1e.2 cmd <- 06
1599 07:40:51.589809 PCI: 00:1e.3 subsystem <- 8086/a0ab
1600 07:40:51.593036 PCI: 00:1e.3 cmd <- 02
1601 07:40:51.596132 PCI: 00:1f.0 subsystem <- 8086/a087
1602 07:40:51.599732 PCI: 00:1f.0 cmd <- 407
1603 07:40:51.603130 PCI: 00:1f.3 subsystem <- 8086/a0c8
1604 07:40:51.606342 PCI: 00:1f.3 cmd <- 02
1605 07:40:51.609629 PCI: 00:1f.5 subsystem <- 8086/a0a4
1606 07:40:51.612849 PCI: 00:1f.5 cmd <- 406
1607 07:40:51.615991 PCI: 01:00.0 cmd <- 02
1608 07:40:51.620557 done.
1609 07:40:51.623749 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1610 07:40:51.626991 Initializing devices...
1611 07:40:51.630118 Root Device init
1612 07:40:51.634066 Chrome EC: Set SMI mask to 0x0000000000000000
1613 07:40:51.640508 Chrome EC: clear events_b mask to 0x0000000000000000
1614 07:40:51.647195 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1615 07:40:51.650168 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1616 07:40:51.656787 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1617 07:40:51.663788 Chrome EC: Set WAKE mask to 0x0000000000000000
1618 07:40:51.667261 fw_config match found: DB_USB=USB3_ACTIVE
1619 07:40:51.670645 Configure Right Type-C port orientation for retimer
1620 07:40:51.676876 Root Device init finished in 42 msecs
1621 07:40:51.676957 PCI: 00:00.0 init
1622 07:40:51.681143 CPU TDP = 9 Watts
1623 07:40:51.684697 CPU PL1 = 9 Watts
1624 07:40:51.684777 CPU PL2 = 40 Watts
1625 07:40:51.688148 CPU PL4 = 83 Watts
1626 07:40:51.691241 PCI: 00:00.0 init finished in 8 msecs
1627 07:40:51.694535 PCI: 00:02.0 init
1628 07:40:51.694634 GMA: Found VBT in CBFS
1629 07:40:51.698322 GMA: Found valid VBT in CBFS
1630 07:40:51.704774 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1631 07:40:51.711321 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1632 07:40:51.714900 PCI: 00:02.0 init finished in 18 msecs
1633 07:40:51.718206 PCI: 00:05.0 init
1634 07:40:51.721378 PCI: 00:05.0 init finished in 0 msecs
1635 07:40:51.724774 PCI: 00:08.0 init
1636 07:40:51.727958 PCI: 00:08.0 init finished in 0 msecs
1637 07:40:51.731136 PCI: 00:14.0 init
1638 07:40:51.735002 PCI: 00:14.0 init finished in 0 msecs
1639 07:40:51.738293 PCI: 00:14.2 init
1640 07:40:51.741417 PCI: 00:14.2 init finished in 0 msecs
1641 07:40:51.744583 PCI: 00:15.0 init
1642 07:40:51.744663 I2C bus 0 version 0x3230302a
1643 07:40:51.751443 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1644 07:40:51.754557 PCI: 00:15.0 init finished in 6 msecs
1645 07:40:51.754637 PCI: 00:15.1 init
1646 07:40:51.758215 I2C bus 1 version 0x3230302a
1647 07:40:51.761048 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1648 07:40:51.768142 PCI: 00:15.1 init finished in 6 msecs
1649 07:40:51.768227 PCI: 00:15.2 init
1650 07:40:51.771131 I2C bus 2 version 0x3230302a
1651 07:40:51.774706 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1652 07:40:51.778083 PCI: 00:15.2 init finished in 6 msecs
1653 07:40:51.781327 PCI: 00:15.3 init
1654 07:40:51.784862 I2C bus 3 version 0x3230302a
1655 07:40:51.788139 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1656 07:40:51.791054 PCI: 00:15.3 init finished in 6 msecs
1657 07:40:51.794632 PCI: 00:16.0 init
1658 07:40:51.797805 PCI: 00:16.0 init finished in 0 msecs
1659 07:40:51.801610 PCI: 00:19.1 init
1660 07:40:51.804379 I2C bus 5 version 0x3230302a
1661 07:40:51.808037 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1662 07:40:51.811176 PCI: 00:19.1 init finished in 6 msecs
1663 07:40:51.811259 PCI: 00:1d.0 init
1664 07:40:51.814759 Initializing PCH PCIe bridge.
1665 07:40:51.821446 PCI: 00:1d.0 init finished in 3 msecs
1666 07:40:51.821529 PCI: 00:1f.0 init
1667 07:40:51.827684 IOAPIC: Initializing IOAPIC at 0xfec00000
1668 07:40:51.831350 IOAPIC: Bootstrap Processor Local APIC = 0x00
1669 07:40:51.834660 IOAPIC: ID = 0x02
1670 07:40:51.837905 IOAPIC: Dumping registers
1671 07:40:51.837987 reg 0x0000: 0x02000000
1672 07:40:51.841001 reg 0x0001: 0x00770020
1673 07:40:51.844342 reg 0x0002: 0x00000000
1674 07:40:51.848126 PCI: 00:1f.0 init finished in 21 msecs
1675 07:40:51.851374 PCI: 00:1f.2 init
1676 07:40:51.851470 Disabling ACPI via APMC.
1677 07:40:51.856330 APMC done.
1678 07:40:51.860030 PCI: 00:1f.2 init finished in 5 msecs
1679 07:40:51.871280 PCI: 01:00.0 init
1680 07:40:51.874781 PCI: 01:00.0 init finished in 0 msecs
1681 07:40:51.877953 PNP: 0c09.0 init
1682 07:40:51.881732 Google Chrome EC uptime: 8.382 seconds
1683 07:40:51.888187 Google Chrome AP resets since EC boot: 1
1684 07:40:51.891489 Google Chrome most recent AP reset causes:
1685 07:40:51.894532 0.350: 32775 shutdown: entering G3
1686 07:40:51.901122 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1687 07:40:51.904794 PNP: 0c09.0 init finished in 22 msecs
1688 07:40:51.910680 Devices initialized
1689 07:40:51.913779 Show all devs... After init.
1690 07:40:51.916827 Root Device: enabled 1
1691 07:40:51.916909 DOMAIN: 0000: enabled 1
1692 07:40:51.919946 CPU_CLUSTER: 0: enabled 1
1693 07:40:51.923933 PCI: 00:00.0: enabled 1
1694 07:40:51.926870 PCI: 00:02.0: enabled 1
1695 07:40:51.926952 PCI: 00:04.0: enabled 1
1696 07:40:51.930590 PCI: 00:05.0: enabled 1
1697 07:40:51.933834 PCI: 00:06.0: enabled 0
1698 07:40:51.936987 PCI: 00:07.0: enabled 0
1699 07:40:51.937066 PCI: 00:07.1: enabled 0
1700 07:40:51.940124 PCI: 00:07.2: enabled 0
1701 07:40:51.943470 PCI: 00:07.3: enabled 0
1702 07:40:51.947292 PCI: 00:08.0: enabled 1
1703 07:40:51.947396 PCI: 00:09.0: enabled 0
1704 07:40:51.950452 PCI: 00:0a.0: enabled 0
1705 07:40:51.953719 PCI: 00:0d.0: enabled 1
1706 07:40:51.953804 PCI: 00:0d.1: enabled 0
1707 07:40:51.957074 PCI: 00:0d.2: enabled 0
1708 07:40:51.960120 PCI: 00:0d.3: enabled 0
1709 07:40:51.963306 PCI: 00:0e.0: enabled 0
1710 07:40:51.963425 PCI: 00:10.2: enabled 1
1711 07:40:51.966942 PCI: 00:10.6: enabled 0
1712 07:40:51.970573 PCI: 00:10.7: enabled 0
1713 07:40:51.973613 PCI: 00:12.0: enabled 0
1714 07:40:51.973694 PCI: 00:12.6: enabled 0
1715 07:40:51.976652 PCI: 00:13.0: enabled 0
1716 07:40:51.980112 PCI: 00:14.0: enabled 1
1717 07:40:51.983295 PCI: 00:14.1: enabled 0
1718 07:40:51.983397 PCI: 00:14.2: enabled 1
1719 07:40:51.986784 PCI: 00:14.3: enabled 1
1720 07:40:51.990405 PCI: 00:15.0: enabled 1
1721 07:40:51.990484 PCI: 00:15.1: enabled 1
1722 07:40:51.993514 PCI: 00:15.2: enabled 1
1723 07:40:51.996763 PCI: 00:15.3: enabled 1
1724 07:40:52.000004 PCI: 00:16.0: enabled 1
1725 07:40:52.000083 PCI: 00:16.1: enabled 0
1726 07:40:52.003690 PCI: 00:16.2: enabled 0
1727 07:40:52.006741 PCI: 00:16.3: enabled 0
1728 07:40:52.010334 PCI: 00:16.4: enabled 0
1729 07:40:52.010413 PCI: 00:16.5: enabled 0
1730 07:40:52.013527 PCI: 00:17.0: enabled 0
1731 07:40:52.016630 PCI: 00:19.0: enabled 0
1732 07:40:52.019968 PCI: 00:19.1: enabled 1
1733 07:40:52.020047 PCI: 00:19.2: enabled 0
1734 07:40:52.023166 PCI: 00:1c.0: enabled 1
1735 07:40:52.026775 PCI: 00:1c.1: enabled 0
1736 07:40:52.030152 PCI: 00:1c.2: enabled 0
1737 07:40:52.030231 PCI: 00:1c.3: enabled 0
1738 07:40:52.033132 PCI: 00:1c.4: enabled 0
1739 07:40:52.036788 PCI: 00:1c.5: enabled 0
1740 07:40:52.036868 PCI: 00:1c.6: enabled 1
1741 07:40:52.039742 PCI: 00:1c.7: enabled 0
1742 07:40:52.043433 PCI: 00:1d.0: enabled 1
1743 07:40:52.046693 PCI: 00:1d.1: enabled 0
1744 07:40:52.046790 PCI: 00:1d.2: enabled 1
1745 07:40:52.049991 PCI: 00:1d.3: enabled 0
1746 07:40:52.053149 PCI: 00:1e.0: enabled 1
1747 07:40:52.056377 PCI: 00:1e.1: enabled 0
1748 07:40:52.056456 PCI: 00:1e.2: enabled 1
1749 07:40:52.059644 PCI: 00:1e.3: enabled 1
1750 07:40:52.063310 PCI: 00:1f.0: enabled 1
1751 07:40:52.066509 PCI: 00:1f.1: enabled 0
1752 07:40:52.066589 PCI: 00:1f.2: enabled 1
1753 07:40:52.069715 PCI: 00:1f.3: enabled 1
1754 07:40:52.073292 PCI: 00:1f.4: enabled 0
1755 07:40:52.073375 PCI: 00:1f.5: enabled 1
1756 07:40:52.076436 PCI: 00:1f.6: enabled 0
1757 07:40:52.080312 PCI: 00:1f.7: enabled 0
1758 07:40:52.083479 APIC: 00: enabled 1
1759 07:40:52.083561 GENERIC: 0.0: enabled 1
1760 07:40:52.086383 GENERIC: 0.0: enabled 1
1761 07:40:52.090058 GENERIC: 1.0: enabled 1
1762 07:40:52.090140 GENERIC: 0.0: enabled 1
1763 07:40:52.093020 GENERIC: 1.0: enabled 1
1764 07:40:52.096460 USB0 port 0: enabled 1
1765 07:40:52.099707 GENERIC: 0.0: enabled 1
1766 07:40:52.099818 USB0 port 0: enabled 1
1767 07:40:52.103325 GENERIC: 0.0: enabled 1
1768 07:40:52.106316 I2C: 00:1a: enabled 1
1769 07:40:52.106398 I2C: 00:31: enabled 1
1770 07:40:52.109874 I2C: 00:32: enabled 1
1771 07:40:52.113137 I2C: 00:10: enabled 1
1772 07:40:52.113219 I2C: 00:15: enabled 1
1773 07:40:52.116196 GENERIC: 0.0: enabled 0
1774 07:40:52.119810 GENERIC: 1.0: enabled 0
1775 07:40:52.123123 GENERIC: 0.0: enabled 1
1776 07:40:52.123229 SPI: 00: enabled 1
1777 07:40:52.126113 SPI: 00: enabled 1
1778 07:40:52.129915 PNP: 0c09.0: enabled 1
1779 07:40:52.129998 GENERIC: 0.0: enabled 1
1780 07:40:52.132977 USB3 port 0: enabled 1
1781 07:40:52.136234 USB3 port 1: enabled 1
1782 07:40:52.136316 USB3 port 2: enabled 0
1783 07:40:52.139254 USB3 port 3: enabled 0
1784 07:40:52.142996 USB2 port 0: enabled 0
1785 07:40:52.146192 USB2 port 1: enabled 1
1786 07:40:52.146275 USB2 port 2: enabled 1
1787 07:40:52.149361 USB2 port 3: enabled 0
1788 07:40:52.152545 USB2 port 4: enabled 1
1789 07:40:52.152626 USB2 port 5: enabled 0
1790 07:40:52.156369 USB2 port 6: enabled 0
1791 07:40:52.159616 USB2 port 7: enabled 0
1792 07:40:52.162798 USB2 port 8: enabled 0
1793 07:40:52.162908 USB2 port 9: enabled 0
1794 07:40:52.166038 USB3 port 0: enabled 0
1795 07:40:52.169485 USB3 port 1: enabled 1
1796 07:40:52.169567 USB3 port 2: enabled 0
1797 07:40:52.172538 USB3 port 3: enabled 0
1798 07:40:52.176337 GENERIC: 0.0: enabled 1
1799 07:40:52.179483 GENERIC: 1.0: enabled 1
1800 07:40:52.179565 APIC: 01: enabled 1
1801 07:40:52.182438 APIC: 03: enabled 1
1802 07:40:52.182536 APIC: 07: enabled 1
1803 07:40:52.186050 APIC: 05: enabled 1
1804 07:40:52.189247 APIC: 04: enabled 1
1805 07:40:52.189328 APIC: 02: enabled 1
1806 07:40:52.192551 APIC: 06: enabled 1
1807 07:40:52.195684 PCI: 01:00.0: enabled 1
1808 07:40:52.199306 BS: BS_DEV_INIT run times (exec / console): 30 / 540 ms
1809 07:40:52.206132 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1810 07:40:52.208997 ELOG: NV offset 0xf30000 size 0x1000
1811 07:40:52.216172 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1812 07:40:52.222508 ELOG: Event(17) added with size 13 at 2024-01-03 07:40:52 UTC
1813 07:40:52.228771 ELOG: Event(92) added with size 9 at 2024-01-03 07:40:52 UTC
1814 07:40:52.235656 ELOG: Event(93) added with size 9 at 2024-01-03 07:40:52 UTC
1815 07:40:52.242602 ELOG: Event(9E) added with size 10 at 2024-01-03 07:40:52 UTC
1816 07:40:52.249011 ELOG: Event(9F) added with size 14 at 2024-01-03 07:40:52 UTC
1817 07:40:52.252359 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1818 07:40:52.259184 ELOG: Event(A1) added with size 10 at 2024-01-03 07:40:52 UTC
1819 07:40:52.265553 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1820 07:40:52.272099 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1821 07:40:52.275861 Finalize devices...
1822 07:40:52.275965 Devices finalized
1823 07:40:52.282270 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1824 07:40:52.285571 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1825 07:40:52.292232 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1826 07:40:52.295737 ME: HFSTS1 : 0x80030055
1827 07:40:52.302544 ME: HFSTS2 : 0x30280116
1828 07:40:52.305713 ME: HFSTS3 : 0x00000050
1829 07:40:52.312192 ME: HFSTS4 : 0x00004000
1830 07:40:52.315374 ME: HFSTS5 : 0x00000000
1831 07:40:52.318924 ME: HFSTS6 : 0x00400006
1832 07:40:52.322632 ME: Manufacturing Mode : YES
1833 07:40:52.325631 ME: SPI Protection Mode Enabled : NO
1834 07:40:52.332275 ME: FW Partition Table : OK
1835 07:40:52.335607 ME: Bringup Loader Failure : NO
1836 07:40:52.338919 ME: Firmware Init Complete : NO
1837 07:40:52.342215 ME: Boot Options Present : NO
1838 07:40:52.345950 ME: Update In Progress : NO
1839 07:40:52.348993 ME: D0i3 Support : YES
1840 07:40:52.352190 ME: Low Power State Enabled : NO
1841 07:40:52.355551 ME: CPU Replaced : YES
1842 07:40:52.362436 ME: CPU Replacement Valid : YES
1843 07:40:52.365672 ME: Current Working State : 5
1844 07:40:52.368780 ME: Current Operation State : 1
1845 07:40:52.372058 ME: Current Operation Mode : 3
1846 07:40:52.375275 ME: Error Code : 0
1847 07:40:52.379171 ME: Enhanced Debug Mode : NO
1848 07:40:52.382436 ME: CPU Debug Disabled : YES
1849 07:40:52.385820 ME: TXT Support : NO
1850 07:40:52.392270 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1851 07:40:52.399030 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1852 07:40:52.402208 CBFS: 'fallback/slic' not found.
1853 07:40:52.408860 ACPI: Writing ACPI tables at 76b01000.
1854 07:40:52.408965 ACPI: * FACS
1855 07:40:52.412473 ACPI: * DSDT
1856 07:40:52.415710 Ramoops buffer: 0x100000@0x76a00000.
1857 07:40:52.418954 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1858 07:40:52.422073 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1859 07:40:52.426934 Google Chrome EC: version:
1860 07:40:52.429987 ro: voema_v2.0.7540-147f8d37d1
1861 07:40:52.433139 rw: voema_v2.0.7540-147f8d37d1
1862 07:40:52.436833 running image: 2
1863 07:40:52.443093 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1864 07:40:52.446695 ACPI: * FADT
1865 07:40:52.446798 SCI is IRQ9
1866 07:40:52.450238 ACPI: added table 1/32, length now 40
1867 07:40:52.453446 ACPI: * SSDT
1868 07:40:52.456512 Found 1 CPU(s) with 8 core(s) each.
1869 07:40:52.459791 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1870 07:40:52.466485 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1871 07:40:52.470187 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1872 07:40:52.473230 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1873 07:40:52.480369 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1874 07:40:52.486606 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1875 07:40:52.489772 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1876 07:40:52.497103 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1877 07:40:52.503603 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1878 07:40:52.506844 \_SB.PCI0.RP09: Added StorageD3Enable property
1879 07:40:52.510438 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1880 07:40:52.516933 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1881 07:40:52.520459 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1882 07:40:52.523658 PS2K: Passing 80 keymaps to kernel
1883 07:40:52.529941 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1884 07:40:52.536452 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1885 07:40:52.543470 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1886 07:40:52.549921 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1887 07:40:52.556962 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1888 07:40:52.563185 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1889 07:40:52.569824 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1890 07:40:52.576837 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1891 07:40:52.580257 ACPI: added table 2/32, length now 44
1892 07:40:52.583580 ACPI: * MCFG
1893 07:40:52.587185 ACPI: added table 3/32, length now 48
1894 07:40:52.587303 ACPI: * TPM2
1895 07:40:52.589963 TPM2 log created at 0x769f0000
1896 07:40:52.596544 ACPI: added table 4/32, length now 52
1897 07:40:52.596652 ACPI: * MADT
1898 07:40:52.596743 SCI is IRQ9
1899 07:40:52.603730 ACPI: added table 5/32, length now 56
1900 07:40:52.603810 current = 76b09850
1901 07:40:52.606882 ACPI: * DMAR
1902 07:40:52.610236 ACPI: added table 6/32, length now 60
1903 07:40:52.613477 ACPI: added table 7/32, length now 64
1904 07:40:52.613558 ACPI: * HPET
1905 07:40:52.620409 ACPI: added table 8/32, length now 68
1906 07:40:52.620491 ACPI: done.
1907 07:40:52.623208 ACPI tables: 35216 bytes.
1908 07:40:52.626782 smbios_write_tables: 769ef000
1909 07:40:52.629983 EC returned error result code 3
1910 07:40:52.633810 Couldn't obtain OEM name from CBI
1911 07:40:52.636750 Create SMBIOS type 16
1912 07:40:52.639855 Create SMBIOS type 17
1913 07:40:52.639960 GENERIC: 0.0 (WIFI Device)
1914 07:40:52.643526 SMBIOS tables: 1750 bytes.
1915 07:40:52.649909 Writing table forward entry at 0x00000500
1916 07:40:52.653229 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1917 07:40:52.660179 Writing coreboot table at 0x76b25000
1918 07:40:52.663332 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1919 07:40:52.669928 1. 0000000000001000-000000000009ffff: RAM
1920 07:40:52.673126 2. 00000000000a0000-00000000000fffff: RESERVED
1921 07:40:52.676984 3. 0000000000100000-00000000769eefff: RAM
1922 07:40:52.682957 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1923 07:40:52.689645 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1924 07:40:52.693188 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1925 07:40:52.699739 7. 0000000077000000-000000007fbfffff: RESERVED
1926 07:40:52.703552 8. 00000000c0000000-00000000cfffffff: RESERVED
1927 07:40:52.709963 9. 00000000f8000000-00000000f9ffffff: RESERVED
1928 07:40:52.713195 10. 00000000fb000000-00000000fb000fff: RESERVED
1929 07:40:52.719811 11. 00000000fe000000-00000000fe00ffff: RESERVED
1930 07:40:52.723620 12. 00000000fed80000-00000000fed87fff: RESERVED
1931 07:40:52.726861 13. 00000000fed90000-00000000fed92fff: RESERVED
1932 07:40:52.733376 14. 00000000feda0000-00000000feda1fff: RESERVED
1933 07:40:52.736457 15. 00000000fedc0000-00000000feddffff: RESERVED
1934 07:40:52.743348 16. 0000000100000000-00000002803fffff: RAM
1935 07:40:52.743502 Passing 4 GPIOs to payload:
1936 07:40:52.749967 NAME | PORT | POLARITY | VALUE
1937 07:40:52.756476 lid | undefined | high | high
1938 07:40:52.759601 power | undefined | high | low
1939 07:40:52.766606 oprom | undefined | high | low
1940 07:40:52.769798 EC in RW | 0x000000e5 | high | high
1941 07:40:52.776304 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 25e7
1942 07:40:52.780242 coreboot table: 1576 bytes.
1943 07:40:52.783536 IMD ROOT 0. 0x76fff000 0x00001000
1944 07:40:52.786623 IMD SMALL 1. 0x76ffe000 0x00001000
1945 07:40:52.789815 FSP MEMORY 2. 0x76c4e000 0x003b0000
1946 07:40:52.796536 VPD 3. 0x76c4d000 0x00000367
1947 07:40:52.799855 RO MCACHE 4. 0x76c4c000 0x00000fdc
1948 07:40:52.802945 CONSOLE 5. 0x76c2c000 0x00020000
1949 07:40:52.806848 FMAP 6. 0x76c2b000 0x00000578
1950 07:40:52.809888 TIME STAMP 7. 0x76c2a000 0x00000910
1951 07:40:52.813673 VBOOT WORK 8. 0x76c16000 0x00014000
1952 07:40:52.816468 ROMSTG STCK 9. 0x76c15000 0x00001000
1953 07:40:52.819653 AFTER CAR 10. 0x76c0a000 0x0000b000
1954 07:40:52.826343 RAMSTAGE 11. 0x76b97000 0x00073000
1955 07:40:52.830113 REFCODE 12. 0x76b42000 0x00055000
1956 07:40:52.833418 SMM BACKUP 13. 0x76b32000 0x00010000
1957 07:40:52.836658 4f444749 14. 0x76b30000 0x00002000
1958 07:40:52.839655 EXT VBT15. 0x76b2d000 0x0000219f
1959 07:40:52.843698 COREBOOT 16. 0x76b25000 0x00008000
1960 07:40:52.846689 ACPI 17. 0x76b01000 0x00024000
1961 07:40:52.850280 ACPI GNVS 18. 0x76b00000 0x00001000
1962 07:40:52.853303 RAMOOPS 19. 0x76a00000 0x00100000
1963 07:40:52.856986 TPM2 TCGLOG20. 0x769f0000 0x00010000
1964 07:40:52.863320 SMBIOS 21. 0x769ef000 0x00000800
1965 07:40:52.863451 IMD small region:
1966 07:40:52.866430 IMD ROOT 0. 0x76ffec00 0x00000400
1967 07:40:52.869867 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1968 07:40:52.876683 POWER STATE 2. 0x76ffeb80 0x00000044
1969 07:40:52.879850 ROMSTAGE 3. 0x76ffeb60 0x00000004
1970 07:40:52.883118 MEM INFO 4. 0x76ffe980 0x000001e0
1971 07:40:52.889618 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1972 07:40:52.893366 MTRR: Physical address space:
1973 07:40:52.899656 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1974 07:40:52.903031 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1975 07:40:52.909963 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1976 07:40:52.916275 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1977 07:40:52.923330 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1978 07:40:52.929455 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1979 07:40:52.936443 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1980 07:40:52.939780 MTRR: Fixed MSR 0x250 0x0606060606060606
1981 07:40:52.943280 MTRR: Fixed MSR 0x258 0x0606060606060606
1982 07:40:52.949506 MTRR: Fixed MSR 0x259 0x0000000000000000
1983 07:40:52.952845 MTRR: Fixed MSR 0x268 0x0606060606060606
1984 07:40:52.956380 MTRR: Fixed MSR 0x269 0x0606060606060606
1985 07:40:52.959372 MTRR: Fixed MSR 0x26a 0x0606060606060606
1986 07:40:52.966166 MTRR: Fixed MSR 0x26b 0x0606060606060606
1987 07:40:52.969709 MTRR: Fixed MSR 0x26c 0x0606060606060606
1988 07:40:52.972659 MTRR: Fixed MSR 0x26d 0x0606060606060606
1989 07:40:52.976528 MTRR: Fixed MSR 0x26e 0x0606060606060606
1990 07:40:52.979783 MTRR: Fixed MSR 0x26f 0x0606060606060606
1991 07:40:52.984342 call enable_fixed_mtrr()
1992 07:40:52.987498 CPU physical address size: 39 bits
1993 07:40:52.993917 MTRR: default type WB/UC MTRR counts: 6/6.
1994 07:40:52.997528 MTRR: UC selected as default type.
1995 07:40:53.003827 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1996 07:40:53.007620 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1997 07:40:53.013859 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1998 07:40:53.020755 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1999 07:40:53.027273 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
2000 07:40:53.034355 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
2001 07:40:53.034435
2002 07:40:53.037550 MTRR check
2003 07:40:53.037629 Fixed MTRRs : Enabled
2004 07:40:53.040550 Variable MTRRs: Enabled
2005 07:40:53.040629
2006 07:40:53.044321 MTRR: Fixed MSR 0x250 0x0606060606060606
2007 07:40:53.050826 MTRR: Fixed MSR 0x258 0x0606060606060606
2008 07:40:53.054195 MTRR: Fixed MSR 0x259 0x0000000000000000
2009 07:40:53.057178 MTRR: Fixed MSR 0x268 0x0606060606060606
2010 07:40:53.060894 MTRR: Fixed MSR 0x269 0x0606060606060606
2011 07:40:53.067265 MTRR: Fixed MSR 0x26a 0x0606060606060606
2012 07:40:53.070898 MTRR: Fixed MSR 0x26b 0x0606060606060606
2013 07:40:53.074030 MTRR: Fixed MSR 0x26c 0x0606060606060606
2014 07:40:53.077044 MTRR: Fixed MSR 0x26d 0x0606060606060606
2015 07:40:53.083602 MTRR: Fixed MSR 0x26e 0x0606060606060606
2016 07:40:53.087375 MTRR: Fixed MSR 0x26f 0x0606060606060606
2017 07:40:53.094002 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
2018 07:40:53.097106 call enable_fixed_mtrr()
2019 07:40:53.101626 Checking cr50 for pending updates
2020 07:40:53.101711 CPU physical address size: 39 bits
2021 07:40:53.108571 MTRR: Fixed MSR 0x250 0x0606060606060606
2022 07:40:53.112415 MTRR: Fixed MSR 0x250 0x0606060606060606
2023 07:40:53.116073 MTRR: Fixed MSR 0x258 0x0606060606060606
2024 07:40:53.119836 MTRR: Fixed MSR 0x259 0x0000000000000000
2025 07:40:53.123084 MTRR: Fixed MSR 0x268 0x0606060606060606
2026 07:40:53.127005 MTRR: Fixed MSR 0x269 0x0606060606060606
2027 07:40:53.130260 MTRR: Fixed MSR 0x26a 0x0606060606060606
2028 07:40:53.137292 MTRR: Fixed MSR 0x26b 0x0606060606060606
2029 07:40:53.141246 MTRR: Fixed MSR 0x26c 0x0606060606060606
2030 07:40:53.144988 MTRR: Fixed MSR 0x26d 0x0606060606060606
2031 07:40:53.148549 MTRR: Fixed MSR 0x26e 0x0606060606060606
2032 07:40:53.151829 MTRR: Fixed MSR 0x26f 0x0606060606060606
2033 07:40:53.159483 MTRR: Fixed MSR 0x258 0x0606060606060606
2034 07:40:53.162691 MTRR: Fixed MSR 0x250 0x0606060606060606
2035 07:40:53.166325 MTRR: Fixed MSR 0x250 0x0606060606060606
2036 07:40:53.169788 MTRR: Fixed MSR 0x258 0x0606060606060606
2037 07:40:53.173333 MTRR: Fixed MSR 0x259 0x0000000000000000
2038 07:40:53.177192 MTRR: Fixed MSR 0x268 0x0606060606060606
2039 07:40:53.180479 MTRR: Fixed MSR 0x269 0x0606060606060606
2040 07:40:53.187820 MTRR: Fixed MSR 0x26a 0x0606060606060606
2041 07:40:53.191294 MTRR: Fixed MSR 0x26b 0x0606060606060606
2042 07:40:53.195193 MTRR: Fixed MSR 0x26c 0x0606060606060606
2043 07:40:53.198382 MTRR: Fixed MSR 0x26d 0x0606060606060606
2044 07:40:53.202203 MTRR: Fixed MSR 0x26e 0x0606060606060606
2045 07:40:53.205503 MTRR: Fixed MSR 0x26f 0x0606060606060606
2046 07:40:53.213392 MTRR: Fixed MSR 0x258 0x0606060606060606
2047 07:40:53.213474 call enable_fixed_mtrr()
2048 07:40:53.219637 MTRR: Fixed MSR 0x259 0x0000000000000000
2049 07:40:53.222858 MTRR: Fixed MSR 0x268 0x0606060606060606
2050 07:40:53.226106 MTRR: Fixed MSR 0x269 0x0606060606060606
2051 07:40:53.229446 MTRR: Fixed MSR 0x26a 0x0606060606060606
2052 07:40:53.236473 MTRR: Fixed MSR 0x26b 0x0606060606060606
2053 07:40:53.239498 MTRR: Fixed MSR 0x26c 0x0606060606060606
2054 07:40:53.242807 MTRR: Fixed MSR 0x26d 0x0606060606060606
2055 07:40:53.246041 MTRR: Fixed MSR 0x26e 0x0606060606060606
2056 07:40:53.249854 MTRR: Fixed MSR 0x26f 0x0606060606060606
2057 07:40:53.256370 CPU physical address size: 39 bits
2058 07:40:53.259563 call enable_fixed_mtrr()
2059 07:40:53.262686 MTRR: Fixed MSR 0x250 0x0606060606060606
2060 07:40:53.266469 MTRR: Fixed MSR 0x250 0x0606060606060606
2061 07:40:53.273013 MTRR: Fixed MSR 0x258 0x0606060606060606
2062 07:40:53.275955 MTRR: Fixed MSR 0x259 0x0000000000000000
2063 07:40:53.279303 MTRR: Fixed MSR 0x268 0x0606060606060606
2064 07:40:53.282911 MTRR: Fixed MSR 0x269 0x0606060606060606
2065 07:40:53.289310 MTRR: Fixed MSR 0x26a 0x0606060606060606
2066 07:40:53.292821 MTRR: Fixed MSR 0x26b 0x0606060606060606
2067 07:40:53.296270 MTRR: Fixed MSR 0x26c 0x0606060606060606
2068 07:40:53.299663 MTRR: Fixed MSR 0x26d 0x0606060606060606
2069 07:40:53.303023 MTRR: Fixed MSR 0x26e 0x0606060606060606
2070 07:40:53.309147 MTRR: Fixed MSR 0x26f 0x0606060606060606
2071 07:40:53.312997 MTRR: Fixed MSR 0x258 0x0606060606060606
2072 07:40:53.316047 call enable_fixed_mtrr()
2073 07:40:53.319234 MTRR: Fixed MSR 0x259 0x0000000000000000
2074 07:40:53.323013 MTRR: Fixed MSR 0x268 0x0606060606060606
2075 07:40:53.329503 MTRR: Fixed MSR 0x269 0x0606060606060606
2076 07:40:53.332819 MTRR: Fixed MSR 0x26a 0x0606060606060606
2077 07:40:53.336521 MTRR: Fixed MSR 0x26b 0x0606060606060606
2078 07:40:53.339684 MTRR: Fixed MSR 0x26c 0x0606060606060606
2079 07:40:53.346327 MTRR: Fixed MSR 0x26d 0x0606060606060606
2080 07:40:53.349475 MTRR: Fixed MSR 0x26e 0x0606060606060606
2081 07:40:53.352795 MTRR: Fixed MSR 0x26f 0x0606060606060606
2082 07:40:53.355944 CPU physical address size: 39 bits
2083 07:40:53.362962 call enable_fixed_mtrr()
2084 07:40:53.363043 call enable_fixed_mtrr()
2085 07:40:53.369547 MTRR: Fixed MSR 0x259 0x0000000000000000
2086 07:40:53.372640 CPU physical address size: 39 bits
2087 07:40:53.376325 MTRR: Fixed MSR 0x268 0x0606060606060606
2088 07:40:53.379074 MTRR: Fixed MSR 0x269 0x0606060606060606
2089 07:40:53.385962 MTRR: Fixed MSR 0x26a 0x0606060606060606
2090 07:40:53.389160 MTRR: Fixed MSR 0x26b 0x0606060606060606
2091 07:40:53.392765 MTRR: Fixed MSR 0x26c 0x0606060606060606
2092 07:40:53.396105 MTRR: Fixed MSR 0x26d 0x0606060606060606
2093 07:40:53.402922 MTRR: Fixed MSR 0x26e 0x0606060606060606
2094 07:40:53.406260 MTRR: Fixed MSR 0x26f 0x0606060606060606
2095 07:40:53.409239 CPU physical address size: 39 bits
2096 07:40:53.412676 call enable_fixed_mtrr()
2097 07:40:53.416179 CPU physical address size: 39 bits
2098 07:40:53.416290 TPM flow control failure
2099 07:40:53.419111 CPU physical address size: 39 bits
2100 07:40:53.426307 unexpected intermediate status 0x0
2101 07:40:53.426388 tpm transaction failed
2102 07:40:53.432694 ERROR: Attempt to enable CR50 update failed: 1f
2103 07:40:53.435973 BS: BS_PAYLOAD_LOAD entry times (exec / console): 315 / 17 ms
2104 07:40:53.446203 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2105 07:40:53.449457 Checking segment from ROM address 0xffc02b38
2106 07:40:53.452528 Checking segment from ROM address 0xffc02b54
2107 07:40:53.459557 Loading segment from ROM address 0xffc02b38
2108 07:40:53.459639 code (compression=0)
2109 07:40:53.469179 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2110 07:40:53.479541 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2111 07:40:53.479623 it's not compressed!
2112 07:40:53.619020 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2113 07:40:53.625873 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2114 07:40:53.632552 Loading segment from ROM address 0xffc02b54
2115 07:40:53.632649 Entry Point 0x30000000
2116 07:40:53.635866 Loaded segments
2117 07:40:53.642514 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2118 07:40:53.685774 Finalizing chipset.
2119 07:40:53.688959 Finalizing SMM.
2120 07:40:53.689044 APMC done.
2121 07:40:53.695520 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2122 07:40:53.698626 mp_park_aps done after 0 msecs.
2123 07:40:53.702305 Jumping to boot code at 0x30000000(0x76b25000)
2124 07:40:53.712196 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2125 07:40:53.712394
2126 07:40:53.712543
2127 07:40:53.712680
2128 07:40:53.715126 Starting depthcharge on Voema...
2129 07:40:53.715260
2130 07:40:53.715787 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2131 07:40:53.715955 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2132 07:40:53.716102 Setting prompt string to ['volteer:']
2133 07:40:53.716247 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2134 07:40:53.725144 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2135 07:40:53.725345
2136 07:40:53.732097 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2137 07:40:53.732291
2138 07:40:53.735238 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2139 07:40:53.739625
2140 07:40:53.739780 Failed to find eMMC card reader
2141 07:40:53.739909
2142 07:40:53.742874 Wipe memory regions:
2143 07:40:53.743008
2144 07:40:53.745988 [0x00000000001000, 0x000000000a0000)
2145 07:40:53.746119
2146 07:40:53.749887 [0x00000000100000, 0x00000030000000)
2147 07:40:53.776468
2148 07:40:53.780203 [0x00000032662db0, 0x000000769ef000)
2149 07:40:53.815465
2150 07:40:53.819237 [0x00000100000000, 0x00000280400000)
2151 07:40:54.017629
2152 07:40:54.021021 ec_init: CrosEC protocol v3 supported (256, 256)
2153 07:40:54.021126
2154 07:40:54.028022 update_port_state: port C0 state: usb enable 1 mux conn 0
2155 07:40:54.028127
2156 07:40:54.034468 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2157 07:40:54.038808
2158 07:40:54.042564 pmc_check_ipc_sts: STS_BUSY done after 1512 us
2159 07:40:54.042684
2160 07:40:54.045692 send_conn_disc_msg: pmc_send_cmd succeeded
2161 07:40:54.478875
2162 07:40:54.479277 R8152: Initializing
2163 07:40:54.479667
2164 07:40:54.482692 Version 6 (ocp_data = 5c30)
2165 07:40:54.483033
2166 07:40:54.485684 R8152: Done initializing
2167 07:40:54.486021
2168 07:40:54.488770 Adding net device
2169 07:40:54.792155
2170 07:40:54.795441 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2171 07:40:54.795554
2172 07:40:54.795656
2173 07:40:54.795757
2174 07:40:54.798823 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2176 07:40:54.899233 volteer: tftpboot 192.168.201.1 12435141/tftp-deploy-qck00fxx/kernel/bzImage 12435141/tftp-deploy-qck00fxx/kernel/cmdline 12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
2177 07:40:54.899429 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2178 07:40:54.899561 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2179 07:40:54.903510 tftpboot 192.168.201.1 12435141/tftp-deploy-qck00fxx/kernel/bzImloy-qck00fxx/kernel/cmdline 12435141/tftp-deploy-qck00fxx/ramdisk/ramdisk.cpio.gz
2180 07:40:54.903633
2181 07:40:54.903739 Waiting for link
2182 07:40:55.107694
2183 07:40:55.107850 done.
2184 07:40:55.107949
2185 07:40:55.108049 MAC: 00:24:32:30:7d:bc
2186 07:40:55.108145
2187 07:40:55.110964 Sending DHCP discover... done.
2188 07:40:55.111072
2189 07:40:55.114111 Waiting for reply... done.
2190 07:40:55.114213
2191 07:40:55.117439 Sending DHCP request... done.
2192 07:40:55.117587
2193 07:40:55.121284 Waiting for reply... done.
2194 07:40:55.121410
2195 07:40:55.124291 My ip is 192.168.201.22
2196 07:40:55.124406
2197 07:40:55.127679 The DHCP server ip is 192.168.201.1
2198 07:40:55.127785
2199 07:40:55.130694 TFTP server IP predefined by user: 192.168.201.1
2200 07:40:55.130800
2201 07:40:55.140777 Bootfile predefined by user: 12435141/tftp-deploy-qck00fxx/kernel/bzImage
2202 07:40:55.140897
2203 07:40:55.143761 Sending tftp read request... done.
2204 07:40:55.143881
2205 07:40:55.147390 Waiting for the transfer...
2206 07:40:55.147499
2207 07:40:55.741487 00000000 ################################################################
2208 07:40:55.741648
2209 07:40:56.332313 00080000 ################################################################
2210 07:40:56.332809
2211 07:40:56.984092 00100000 ################################################################
2212 07:40:56.984590
2213 07:40:57.561408 00180000 ################################################################
2214 07:40:57.561569
2215 07:40:58.138453 00200000 ################################################################
2216 07:40:58.138587
2217 07:40:58.685241 00280000 ################################################################
2218 07:40:58.685368
2219 07:40:59.271469 00300000 ################################################################
2220 07:40:59.272068
2221 07:40:59.830968 00380000 ################################################################
2222 07:40:59.831131
2223 07:41:00.384971 00400000 ################################################################
2224 07:41:00.385120
2225 07:41:00.934251 00480000 ################################################################
2226 07:41:00.934422
2227 07:41:01.484318 00500000 ################################################################
2228 07:41:01.484488
2229 07:41:02.039261 00580000 ################################################################
2230 07:41:02.039453
2231 07:41:02.625753 00600000 ################################################################
2232 07:41:02.625914
2233 07:41:03.185390 00680000 ################################################################
2234 07:41:03.185561
2235 07:41:03.720211 00700000 ################################################################
2236 07:41:03.720379
2237 07:41:04.256861 00780000 ################################################################
2238 07:41:04.257000
2239 07:41:04.450280 00800000 ####################### done.
2240 07:41:04.450462
2241 07:41:04.453309 The bootfile was 8572816 bytes long.
2242 07:41:04.453388
2243 07:41:04.456695 Sending tftp read request... done.
2244 07:41:04.456785
2245 07:41:04.459934 Waiting for the transfer...
2246 07:41:04.460016
2247 07:41:04.987882 00000000 ################################################################
2248 07:41:04.988015
2249 07:41:05.518671 00080000 ################################################################
2250 07:41:05.518836
2251 07:41:06.086409 00100000 ################################################################
2252 07:41:06.086547
2253 07:41:06.632873 00180000 ################################################################
2254 07:41:06.633019
2255 07:41:07.224000 00200000 ################################################################
2256 07:41:07.224177
2257 07:41:07.791000 00280000 ################################################################
2258 07:41:07.791157
2259 07:41:08.326514 00300000 ################################################################
2260 07:41:08.326678
2261 07:41:08.863724 00380000 ################################################################
2262 07:41:08.863888
2263 07:41:09.391678 00400000 ################################################################
2264 07:41:09.391813
2265 07:41:09.915609 00480000 ################################################################
2266 07:41:09.915751
2267 07:41:10.437134 00500000 ################################################################ done.
2268 07:41:10.437288
2269 07:41:10.440007 Sending tftp read request... done.
2270 07:41:10.440097
2271 07:41:10.443610 Waiting for the transfer...
2272 07:41:10.443701
2273 07:41:10.443789 00000000 # done.
2274 07:41:10.446828
2275 07:41:10.453947 Command line loaded dynamically from TFTP file: 12435141/tftp-deploy-qck00fxx/kernel/cmdline
2276 07:41:10.454037
2277 07:41:10.479933 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12435141/extract-nfsrootfs-i6emnpk7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2278 07:41:10.484169
2279 07:41:10.487508 Shutting down all USB controllers.
2280 07:41:10.487595
2281 07:41:10.487682 Removing current net device
2282 07:41:10.487765
2283 07:41:10.490625 Finalizing coreboot
2284 07:41:10.490711
2285 07:41:10.497452 Exiting depthcharge with code 4 at timestamp: 25427419
2286 07:41:10.497538
2287 07:41:10.497624
2288 07:41:10.497706 Starting kernel ...
2289 07:41:10.497786
2290 07:41:10.497865
2291 07:41:10.498460 end: 2.2.4 bootloader-commands (duration 00:00:17) [common]
2292 07:41:10.498598 start: 2.2.5 auto-login-action (timeout 00:04:28) [common]
2293 07:41:10.498686 Setting prompt string to ['Linux version [0-9]']
2294 07:41:10.498794 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2295 07:41:10.498900 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2297 07:45:38.498871 end: 2.2.5 auto-login-action (duration 00:04:28) [common]
2299 07:45:38.499255 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 268 seconds'
2301 07:45:38.499546 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2304 07:45:38.499969 end: 2 depthcharge-action (duration 00:05:00) [common]
2306 07:45:38.500232 Cleaning after the job
2307 07:45:38.500334 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/ramdisk
2308 07:45:38.501241 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/kernel
2309 07:45:38.502578 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/nfsrootfs
2310 07:45:38.577372 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12435141/tftp-deploy-qck00fxx/modules
2311 07:45:38.577828 start: 5.1 power-off (timeout 00:00:30) [common]
2312 07:45:38.577996 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-5' '--port=1' '--command=off'
2313 07:45:38.656941 >> Command sent successfully.
2314 07:45:38.661568 Returned 0 in 0 seconds
2315 07:45:38.762621 end: 5.1 power-off (duration 00:00:00) [common]
2317 07:45:38.764220 start: 5.2 read-feedback (timeout 00:10:00) [common]
2318 07:45:38.765469 Listened to connection for namespace 'common' for up to 1s
2319 07:45:39.766223 Finalising connection for namespace 'common'
2320 07:45:39.766905 Disconnecting from shell: Finalise
2321 07:45:39.767407
2322 07:45:39.868463 end: 5.2 read-feedback (duration 00:00:01) [common]
2323 07:45:39.869201 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12435141
2324 07:45:40.221026 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12435141
2325 07:45:40.221220 JobError: Your job cannot terminate cleanly.