Boot log: asus-cx9400-volteer
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 0
- Warnings: 0
1 12:16:59.011058 lava-dispatcher, installed at version: 2022.11
2 12:16:59.011238 start: 0 validate
3 12:16:59.011367 Start time: 2023-01-31 12:16:59.011360+00:00 (UTC)
4 12:16:59.011492 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:59.011613 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230127.0%2Famd64%2Frootfs.cpio.gz exists
6 12:16:59.309522 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:59.309732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:16:59.312197 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:59.312390 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:16:59.315961 validate duration: 0.30
12 12:16:59.316278 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:16:59.316469 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:16:59.316616 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:16:59.316755 Not decompressing ramdisk as can be used compressed.
16 12:16:59.316937 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230127.0/amd64/rootfs.cpio.gz
17 12:16:59.317039 saving as /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/ramdisk/rootfs.cpio.gz
18 12:16:59.317146 total size: 35749839 (34MB)
19 12:16:59.319728 progress 0% (0MB)
20 12:16:59.335086 progress 5% (1MB)
21 12:16:59.350498 progress 10% (3MB)
22 12:16:59.365178 progress 15% (5MB)
23 12:16:59.380592 progress 20% (6MB)
24 12:16:59.395688 progress 25% (8MB)
25 12:16:59.411089 progress 30% (10MB)
26 12:16:59.426067 progress 35% (11MB)
27 12:16:59.441376 progress 40% (13MB)
28 12:16:59.456556 progress 45% (15MB)
29 12:16:59.471916 progress 50% (17MB)
30 12:16:59.487287 progress 55% (18MB)
31 12:16:59.502427 progress 60% (20MB)
32 12:16:59.517586 progress 65% (22MB)
33 12:16:59.532958 progress 70% (23MB)
34 12:16:59.548120 progress 75% (25MB)
35 12:16:59.563095 progress 80% (27MB)
36 12:16:59.578646 progress 85% (29MB)
37 12:16:59.593668 progress 90% (30MB)
38 12:16:59.609039 progress 95% (32MB)
39 12:16:59.623983 progress 100% (34MB)
40 12:16:59.624319 34MB downloaded in 0.31s (111.00MB/s)
41 12:16:59.624497 end: 1.1.1 http-download (duration 00:00:00) [common]
43 12:16:59.624768 end: 1.1 download-retry (duration 00:00:00) [common]
44 12:16:59.624891 start: 1.2 download-retry (timeout 00:10:00) [common]
45 12:16:59.625025 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 12:16:59.625163 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:16:59.625230 saving as /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/kernel/bzImage
48 12:16:59.625292 total size: 7569296 (7MB)
49 12:16:59.625354 No compression specified
50 12:16:59.627125 progress 0% (0MB)
51 12:16:59.630559 progress 5% (0MB)
52 12:16:59.633663 progress 10% (0MB)
53 12:16:59.636894 progress 15% (1MB)
54 12:16:59.639988 progress 20% (1MB)
55 12:16:59.643042 progress 25% (1MB)
56 12:16:59.646490 progress 30% (2MB)
57 12:16:59.649567 progress 35% (2MB)
58 12:16:59.652847 progress 40% (2MB)
59 12:16:59.655900 progress 45% (3MB)
60 12:16:59.659213 progress 50% (3MB)
61 12:16:59.662719 progress 55% (4MB)
62 12:16:59.665736 progress 60% (4MB)
63 12:16:59.669001 progress 65% (4MB)
64 12:16:59.672027 progress 70% (5MB)
65 12:16:59.675525 progress 75% (5MB)
66 12:16:59.678701 progress 80% (5MB)
67 12:16:59.682207 progress 85% (6MB)
68 12:16:59.684892 progress 90% (6MB)
69 12:16:59.688420 progress 95% (6MB)
70 12:16:59.691285 progress 100% (7MB)
71 12:16:59.691615 7MB downloaded in 0.07s (108.85MB/s)
72 12:16:59.691838 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:16:59.692108 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:16:59.692198 start: 1.3 download-retry (timeout 00:10:00) [common]
76 12:16:59.692285 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 12:16:59.692425 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:16:59.692493 saving as /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/modules/modules.tar
79 12:16:59.692554 total size: 51860 (0MB)
80 12:16:59.692616 Using unxz to decompress xz
81 12:16:59.696599 progress 63% (0MB)
82 12:16:59.696991 progress 100% (0MB)
83 12:16:59.700376 0MB downloaded in 0.01s (6.34MB/s)
84 12:16:59.700624 end: 1.3.1 http-download (duration 00:00:00) [common]
86 12:16:59.700893 end: 1.3 download-retry (duration 00:00:00) [common]
87 12:16:59.700994 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
88 12:16:59.701093 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
89 12:16:59.701181 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
90 12:16:59.701272 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
91 12:16:59.701444 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg
92 12:16:59.701552 makedir: /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin
93 12:16:59.701638 makedir: /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/tests
94 12:16:59.701719 makedir: /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/results
95 12:16:59.701826 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-add-keys
96 12:16:59.701959 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-add-sources
97 12:16:59.702078 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-background-process-start
98 12:16:59.702190 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-background-process-stop
99 12:16:59.702302 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-common-functions
100 12:16:59.702412 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-echo-ipv4
101 12:16:59.702523 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-install-packages
102 12:16:59.702634 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-installed-packages
103 12:16:59.702741 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-os-build
104 12:16:59.702849 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-probe-channel
105 12:16:59.702959 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-probe-ip
106 12:16:59.703066 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-target-ip
107 12:16:59.703174 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-target-mac
108 12:16:59.703280 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-target-storage
109 12:16:59.703390 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-case
110 12:16:59.703499 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-event
111 12:16:59.703607 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-feedback
112 12:16:59.703713 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-raise
113 12:16:59.703825 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-reference
114 12:16:59.703934 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-runner
115 12:16:59.704040 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-set
116 12:16:59.704146 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-test-shell
117 12:16:59.704256 Updating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-install-packages (oe)
118 12:16:59.704406 Updating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/bin/lava-installed-packages (oe)
119 12:16:59.704506 Creating /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/environment
120 12:16:59.704594 LAVA metadata
121 12:16:59.704666 - LAVA_JOB_ID=8948145
122 12:16:59.704733 - LAVA_DISPATCHER_IP=192.168.201.1
123 12:16:59.704834 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
124 12:16:59.704899 skipped lava-vland-overlay
125 12:16:59.704978 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
126 12:16:59.705063 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
127 12:16:59.705127 skipped lava-multinode-overlay
128 12:16:59.705204 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
129 12:16:59.705288 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
130 12:16:59.705364 Loading test definitions
131 12:16:59.705463 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
132 12:16:59.705540 Using /lava-8948145 at stage 0
133 12:16:59.705837 uuid=8948145_1.4.2.3.1 testdef=None
134 12:16:59.705934 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
135 12:16:59.706032 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
136 12:16:59.706505 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
138 12:16:59.706743 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
139 12:16:59.707281 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
141 12:16:59.707521 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
142 12:16:59.708028 runner path: /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/0/tests/0_cros-ec test_uuid 8948145_1.4.2.3.1
143 12:16:59.708173 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
145 12:16:59.708424 Creating lava-test-runner.conf files
146 12:16:59.708489 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8948145/lava-overlay-nirubydg/lava-8948145/0 for stage 0
147 12:16:59.708572 - 0_cros-ec
148 12:16:59.708667 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
149 12:16:59.708757 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
150 12:16:59.714071 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
151 12:16:59.714187 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
152 12:16:59.714294 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
153 12:16:59.714395 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
154 12:16:59.714482 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
155 12:17:00.464954 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:01) [common]
156 12:17:00.465278 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
157 12:17:00.465389 extracting modules file /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8948145/extract-overlay-ramdisk-45dnc0bx/ramdisk
158 12:17:00.469522 end: 1.4.4 extract-modules (duration 00:00:00) [common]
159 12:17:00.469634 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
160 12:17:00.469717 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8948145/compress-overlay-1yl3ur1q/overlay-1.4.2.4.tar.gz to ramdisk
161 12:17:00.469791 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8948145/compress-overlay-1yl3ur1q/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8948145/extract-overlay-ramdisk-45dnc0bx/ramdisk
162 12:17:00.472831 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
163 12:17:00.472942 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
164 12:17:00.473038 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
165 12:17:00.473136 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
166 12:17:00.473219 Building ramdisk /var/lib/lava/dispatcher/tmp/8948145/extract-overlay-ramdisk-45dnc0bx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8948145/extract-overlay-ramdisk-45dnc0bx/ramdisk
167 12:17:00.715371 >> 182445 blocks
168 12:17:03.852433 rename /var/lib/lava/dispatcher/tmp/8948145/extract-overlay-ramdisk-45dnc0bx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
169 12:17:03.852827 end: 1.4.7 compress-ramdisk (duration 00:00:03) [common]
170 12:17:03.852947 start: 1.4.8 prepare-kernel (timeout 00:09:55) [common]
171 12:17:03.853050 start: 1.4.8.1 prepare-fit (timeout 00:09:55) [common]
172 12:17:03.853140 No mkimage arch provided, not using FIT.
173 12:17:03.853229 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
174 12:17:03.853314 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
175 12:17:03.853409 end: 1.4 prepare-tftp-overlay (duration 00:00:04) [common]
176 12:17:03.853496 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:55) [common]
177 12:17:03.853572 No LXC device requested
178 12:17:03.853655 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
179 12:17:03.853752 start: 1.6 deploy-device-env (timeout 00:09:55) [common]
180 12:17:03.853838 end: 1.6 deploy-device-env (duration 00:00:00) [common]
181 12:17:03.853910 Checking files for TFTP limit of 4294967296 bytes.
182 12:17:03.854296 end: 1 tftp-deploy (duration 00:00:05) [common]
183 12:17:03.854405 start: 2 depthcharge-action (timeout 00:05:00) [common]
184 12:17:03.854506 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
185 12:17:03.854634 substitutions:
186 12:17:03.854702 - {DTB}: None
187 12:17:03.854768 - {INITRD}: 8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
188 12:17:03.854829 - {KERNEL}: 8948145/tftp-deploy-m3zcztrl/kernel/bzImage
189 12:17:03.854888 - {LAVA_MAC}: None
190 12:17:03.854945 - {PRESEED_CONFIG}: None
191 12:17:03.855004 - {PRESEED_LOCAL}: None
192 12:17:03.855069 - {RAMDISK}: 8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
193 12:17:03.855126 - {ROOT_PART}: None
194 12:17:03.855182 - {ROOT}: None
195 12:17:03.855237 - {SERVER_IP}: 192.168.201.1
196 12:17:03.855293 - {TEE}: None
197 12:17:03.855348 Parsed boot commands:
198 12:17:03.855401 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
199 12:17:03.855555 Parsed boot commands: tftpboot 192.168.201.1 8948145/tftp-deploy-m3zcztrl/kernel/bzImage 8948145/tftp-deploy-m3zcztrl/kernel/cmdline 8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
200 12:17:03.855647 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
201 12:17:03.855736 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
202 12:17:03.855864 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
203 12:17:03.855950 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
204 12:17:03.856029 Not connected, no need to disconnect.
205 12:17:03.856109 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
206 12:17:03.856191 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
207 12:17:03.856275 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-9'
208 12:17:03.858949 Setting prompt string to ['lava-test: # ']
209 12:17:03.859283 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
210 12:17:03.859384 end: 2.2.1 reset-connection (duration 00:00:00) [common]
211 12:17:03.859479 start: 2.2.2 reset-device (timeout 00:05:00) [common]
212 12:17:03.859569 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
213 12:17:03.859740 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-9' '--port=1' '--command=reboot'
214 12:17:03.878125 >> Command sent successfully.
215 12:17:03.879865 Returned 0 in 0 seconds
216 12:17:03.980809 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
218 12:17:03.982717 end: 2.2.2 reset-device (duration 00:00:00) [common]
219 12:17:03.983143 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
220 12:17:03.983501 Setting prompt string to 'Starting depthcharge on Voema...'
221 12:17:03.983788 Changing prompt to 'Starting depthcharge on Voema...'
222 12:17:03.984074 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
223 12:17:03.985141 [Enter `^Ec?' for help]
224 12:17:11.615632
225 12:17:11.616436
226 12:17:11.626817 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
227 12:17:11.630771 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
228 12:17:11.635047 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
229 12:17:11.638424 CPU: AES supported, TXT NOT supported, VT supported
230 12:17:11.645822 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
231 12:17:11.649684 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
232 12:17:11.657051 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
233 12:17:11.660845 VBOOT: Loading verstage.
234 12:17:11.664533 FMAP: Found "FLASH" version 1.1 at 0x1804000.
235 12:17:11.668156 FMAP: base = 0x0 size = 0x2000000 #areas = 32
236 12:17:11.671603 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
237 12:17:11.680592 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
238 12:17:11.690121 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
239 12:17:11.690594
240 12:17:11.690948
241 12:17:11.700221 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
242 12:17:11.716479 Probing TPM: . done!
243 12:17:11.719260 TPM ready after 0 ms
244 12:17:11.722821 Connected to device vid:did:rid of 1ae0:0028:00
245 12:17:11.734105 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
246 12:17:11.740742 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
247 12:17:11.743978 Initialized TPM device CR50 revision 0
248 12:17:11.852442 tlcl_send_startup: Startup return code is 0
249 12:17:11.853067 TPM: setup succeeded
250 12:17:11.867628 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
251 12:17:11.883648 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
252 12:17:11.896770 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
253 12:17:11.907040 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
254 12:17:11.910800 Chrome EC: UHEPI supported
255 12:17:11.914348 Phase 1
256 12:17:11.917377 FMAP: area GBB found @ 1805000 (458752 bytes)
257 12:17:11.923974 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
258 12:17:11.927380
259 12:17:11.934111 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
260 12:17:11.940768 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
261 12:17:11.947261 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
262 12:17:11.950399 Recovery requested (1009000e)
263 12:17:11.953769 TPM: Extending digest for VBOOT: boot mode into PCR 0
264 12:17:11.965718 tlcl_extend: response is 0
265 12:17:11.971931 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
266 12:17:11.982164 tlcl_extend: response is 0
267 12:17:11.988786 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
268 12:17:11.995169 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
269 12:17:12.001863 BS: verstage times (exec / console): total (unknown) / 142 ms
270 12:17:12.002328
271 12:17:12.002684
272 12:17:12.015316 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
273 12:17:12.021573 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
274 12:17:12.024940 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
275 12:17:12.028463 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
276 12:17:12.035055 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
277 12:17:12.038517 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
278 12:17:12.041555 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
279 12:17:12.044696 TCO_STS: 0000 0000
280 12:17:12.048537 GEN_PMCON: d0015038 00002200
281 12:17:12.051667 GBLRST_CAUSE: 00000000 00000000
282 12:17:12.052108 HPR_CAUSE0: 00000000
283 12:17:12.055365 prev_sleep_state 5
284 12:17:12.059399 Boot Count incremented to 15883
285 12:17:12.066072 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
286 12:17:12.072444 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
287 12:17:12.079274 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
288 12:17:12.085991 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
289 12:17:12.089218 Chrome EC: UHEPI supported
290 12:17:12.096124 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
291 12:17:12.108728 Probing TPM: done!
292 12:17:12.115654 Connected to device vid:did:rid of 1ae0:0028:00
293 12:17:12.125862 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
294 12:17:12.128848 Initialized TPM device CR50 revision 0
295 12:17:12.143960 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
296 12:17:12.150502 MRC: Hash idx 0x100b comparison successful.
297 12:17:12.153871 MRC cache found, size faa8
298 12:17:12.154351 bootmode is set to: 2
299 12:17:12.157071 SPD index = 0
300 12:17:12.163952 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
301 12:17:12.167371 SPD: module type is LPDDR4X
302 12:17:12.170318 SPD: module part number is MT53E512M64D4NW-046
303 12:17:12.176964 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
304 12:17:12.180281 SPD: device width 16 bits, bus width 16 bits
305 12:17:12.187428 SPD: module size is 1024 MB (per channel)
306 12:17:12.624466 CBMEM:
307 12:17:12.627497 IMD: root @ 0x76fff000 254 entries.
308 12:17:12.631416 IMD: root @ 0x76ffec00 62 entries.
309 12:17:12.634967 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
310 12:17:12.638329 FMAP: area RW_VPD found @ f35000 (8192 bytes)
311 12:17:12.643432 External stage cache:
312 12:17:12.647360 IMD: root @ 0x7b3ff000 254 entries.
313 12:17:12.650181 IMD: root @ 0x7b3fec00 62 entries.
314 12:17:12.665902 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
315 12:17:12.672287 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
316 12:17:12.679213 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
317 12:17:12.692721 MRC: 'RECOVERY_MRC_CACHE' does not need update.
318 12:17:12.699467 cse_lite: Skip switching to RW in the recovery path
319 12:17:12.699938 8 DIMMs found
320 12:17:12.700295 SMM Memory Map
321 12:17:12.702990 SMRAM : 0x7b000000 0x800000
322 12:17:12.706494
323 12:17:12.709547 Subregion 0: 0x7b000000 0x200000
324 12:17:12.713331 Subregion 1: 0x7b200000 0x200000
325 12:17:12.716162 Subregion 2: 0x7b400000 0x400000
326 12:17:12.716642 top_of_ram = 0x77000000
327 12:17:12.722979 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
328 12:17:12.729782 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
329 12:17:12.732995 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
330 12:17:12.740290 MTRR Range: Start=ff000000 End=0 (Size 1000000)
331 12:17:12.746382 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
332 12:17:12.753052 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
333 12:17:12.763005 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
334 12:17:12.766529 Processing 211 relocs. Offset value of 0x74c0b000
335 12:17:12.769419
336 12:17:12.776001 BS: romstage times (exec / console): total (unknown) / 277 ms
337 12:17:12.782402
338 12:17:12.782917
339 12:17:12.792170 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
340 12:17:12.795546 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
341 12:17:12.805082 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
342 12:17:12.811985 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
343 12:17:12.818343 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
344 12:17:12.825070 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
345 12:17:12.872347 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
346 12:17:12.878625 Processing 5008 relocs. Offset value of 0x75d98000
347 12:17:12.881905 BS: postcar times (exec / console): total (unknown) / 59 ms
348 12:17:12.885050
349 12:17:12.885550
350 12:17:12.895300 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
351 12:17:12.895835 Normal boot
352 12:17:12.898244 FW_CONFIG value is 0x804c02
353 12:17:12.901475 PCI: 00:07.0 disabled by fw_config
354 12:17:12.905129 PCI: 00:07.1 disabled by fw_config
355 12:17:12.908761 PCI: 00:0d.2 disabled by fw_config
356 12:17:12.915479 PCI: 00:1c.7 disabled by fw_config
357 12:17:12.918616 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
358 12:17:12.925189 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
359 12:17:12.928155 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
360 12:17:12.935134 GENERIC: 0.0 disabled by fw_config
361 12:17:12.938420 GENERIC: 1.0 disabled by fw_config
362 12:17:12.941836 fw_config match found: DB_USB=USB3_ACTIVE
363 12:17:12.945187 fw_config match found: DB_USB=USB3_ACTIVE
364 12:17:12.948073 fw_config match found: DB_USB=USB3_ACTIVE
365 12:17:12.954656 fw_config match found: DB_USB=USB3_ACTIVE
366 12:17:12.958058 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
367 12:17:12.964612 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
368 12:17:12.974855 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
369 12:17:12.981335 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
370 12:17:12.984911 microcode: sig=0x806c1 pf=0x80 revision=0x86
371 12:17:12.991041 microcode: Update skipped, already up-to-date
372 12:17:12.997757 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
373 12:17:13.025870 Detected 4 core, 8 thread CPU.
374 12:17:13.029074 Setting up SMI for CPU
375 12:17:13.032379 IED base = 0x7b400000
376 12:17:13.032900 IED size = 0x00400000
377 12:17:13.035856 Will perform SMM setup.
378 12:17:13.042483 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
379 12:17:13.049259 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
380 12:17:13.055788 Processing 16 relocs. Offset value of 0x00030000
381 12:17:13.059458 Attempting to start 7 APs
382 12:17:13.062353 Waiting for 10ms after sending INIT.
383 12:17:13.077524 Waiting for 1st SIPI to complete...done.
384 12:17:13.078193 AP: slot 1 apic_id 1.
385 12:17:13.080869 AP: slot 4 apic_id 7.
386 12:17:13.084563 AP: slot 5 apic_id 6.
387 12:17:13.085008 AP: slot 3 apic_id 4.
388 12:17:13.088232 AP: slot 7 apic_id 5.
389 12:17:13.091079 Waiting for 2nd SIPI to complete...done.
390 12:17:13.094867 AP: slot 6 apic_id 2.
391 12:17:13.097537 AP: slot 2 apic_id 3.
392 12:17:13.104394 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
393 12:17:13.111051 Processing 13 relocs. Offset value of 0x00038000
394 12:17:13.111495 Unable to locate Global NVS
395 12:17:13.114086
396 12:17:13.120581 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
397 12:17:13.123857 Installing permanent SMM handler to 0x7b000000
398 12:17:13.133841 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
399 12:17:13.137514 Processing 794 relocs. Offset value of 0x7b010000
400 12:17:13.147380 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
401 12:17:13.150721 Processing 13 relocs. Offset value of 0x7b008000
402 12:17:13.157439 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
403 12:17:13.163851 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
404 12:17:13.167045 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
405 12:17:13.173679 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
406 12:17:13.180228 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
407 12:17:13.187315 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
408 12:17:13.193697 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
409 12:17:13.194201 Unable to locate Global NVS
410 12:17:13.203594 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
411 12:17:13.207161 Clearing SMI status registers
412 12:17:13.207646 SMI_STS: PM1
413 12:17:13.210203 PM1_STS: PWRBTN
414 12:17:13.217113 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
415 12:17:13.220365 In relocation handler: CPU 0
416 12:17:13.223350 New SMBASE=0x7b000000 IEDBASE=0x7b400000
417 12:17:13.230367 Writing SMRR. base = 0x7b000006, mask=0xff800c00
418 12:17:13.230842 Relocation complete.
419 12:17:13.240361 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
420 12:17:13.240810 In relocation handler: CPU 1
421 12:17:13.243114
422 12:17:13.246807 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
423 12:17:13.247267 Relocation complete.
424 12:17:13.256254 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
425 12:17:13.256744 In relocation handler: CPU 2
426 12:17:13.263658 New SMBASE=0x7afff800 IEDBASE=0x7b400000
427 12:17:13.264117 Relocation complete.
428 12:17:13.273331 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
429 12:17:13.273782 In relocation handler: CPU 6
430 12:17:13.279917 New SMBASE=0x7affe800 IEDBASE=0x7b400000
431 12:17:13.283092 Writing SMRR. base = 0x7b000006, mask=0xff800c00
432 12:17:13.286426 Relocation complete.
433 12:17:13.293015 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
434 12:17:13.296037 In relocation handler: CPU 5
435 12:17:13.299934 New SMBASE=0x7affec00 IEDBASE=0x7b400000
436 12:17:13.304137 Writing SMRR. base = 0x7b000006, mask=0xff800c00
437 12:17:13.307299 Relocation complete.
438 12:17:13.314132 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
439 12:17:13.316987 In relocation handler: CPU 4
440 12:17:13.320408 New SMBASE=0x7afff000 IEDBASE=0x7b400000
441 12:17:13.323537 Relocation complete.
442 12:17:13.330381 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
443 12:17:13.333927 In relocation handler: CPU 3
444 12:17:13.337083 New SMBASE=0x7afff400 IEDBASE=0x7b400000
445 12:17:13.343753 Writing SMRR. base = 0x7b000006, mask=0xff800c00
446 12:17:13.344189 Relocation complete.
447 12:17:13.353664 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
448 12:17:13.354331 In relocation handler: CPU 7
449 12:17:13.356822
450 12:17:13.360393 New SMBASE=0x7affe400 IEDBASE=0x7b400000
451 12:17:13.360888 Relocation complete.
452 12:17:13.363788 Initializing CPU #0
453 12:17:13.366793 CPU: vendor Intel device 806c1
454 12:17:13.370371 CPU: family 06, model 8c, stepping 01
455 12:17:13.373734 Clearing out pending MCEs
456 12:17:13.376813 Setting up local APIC...
457 12:17:13.377270 apic_id: 0x00 done.
458 12:17:13.380057 Turbo is available but hidden
459 12:17:13.383435 Turbo is available and visible
460 12:17:13.390247 microcode: Update skipped, already up-to-date
461 12:17:13.390725 CPU #0 initialized
462 12:17:13.393678 Initializing CPU #7
463 12:17:13.396553 Initializing CPU #3
464 12:17:13.397042 CPU: vendor Intel device 806c1
465 12:17:13.400010
466 12:17:13.403443 CPU: family 06, model 8c, stepping 01
467 12:17:13.406840 CPU: vendor Intel device 806c1
468 12:17:13.410069 CPU: family 06, model 8c, stepping 01
469 12:17:13.413423 Clearing out pending MCEs
470 12:17:13.413859 Clearing out pending MCEs
471 12:17:13.416777 Setting up local APIC...
472 12:17:13.420181 Initializing CPU #1
473 12:17:13.420655 Initializing CPU #5
474 12:17:13.423930 Initializing CPU #4
475 12:17:13.426771 CPU: vendor Intel device 806c1
476 12:17:13.429996 CPU: family 06, model 8c, stepping 01
477 12:17:13.433263 CPU: vendor Intel device 806c1
478 12:17:13.436951 CPU: family 06, model 8c, stepping 01
479 12:17:13.439936 Clearing out pending MCEs
480 12:17:13.443538 Clearing out pending MCEs
481 12:17:13.444021 Setting up local APIC...
482 12:17:13.446874 Setting up local APIC...
483 12:17:13.450046 Initializing CPU #6
484 12:17:13.450530 Initializing CPU #2
485 12:17:13.453349 CPU: vendor Intel device 806c1
486 12:17:13.460081 CPU: family 06, model 8c, stepping 01
487 12:17:13.460592 CPU: vendor Intel device 806c1
488 12:17:13.463266
489 12:17:13.466769 CPU: family 06, model 8c, stepping 01
490 12:17:13.467518 Clearing out pending MCEs
491 12:17:13.469964 Clearing out pending MCEs
492 12:17:13.473184 Setting up local APIC...
493 12:17:13.476405 Setting up local APIC...
494 12:17:13.476911 apic_id: 0x02 done.
495 12:17:13.479743 Setting up local APIC...
496 12:17:13.483182 apic_id: 0x07 done.
497 12:17:13.483720 apic_id: 0x06 done.
498 12:17:13.489550 microcode: Update skipped, already up-to-date
499 12:17:13.492931 microcode: Update skipped, already up-to-date
500 12:17:13.499463 microcode: Update skipped, already up-to-date
501 12:17:13.499956 apic_id: 0x03 done.
502 12:17:13.503001 CPU: vendor Intel device 806c1
503 12:17:13.506102 CPU: family 06, model 8c, stepping 01
504 12:17:13.509966 apic_id: 0x04 done.
505 12:17:13.513065 apic_id: 0x05 done.
506 12:17:13.516474 microcode: Update skipped, already up-to-date
507 12:17:13.520064 microcode: Update skipped, already up-to-date
508 12:17:13.522729 CPU #3 initialized
509 12:17:13.526433 CPU #7 initialized
510 12:17:13.526999 CPU #5 initialized
511 12:17:13.529807 CPU #4 initialized
512 12:17:13.533033 Clearing out pending MCEs
513 12:17:13.533487 CPU #6 initialized
514 12:17:13.539911 microcode: Update skipped, already up-to-date
515 12:17:13.540400 Setting up local APIC...
516 12:17:13.542611 CPU #2 initialized
517 12:17:13.546549 apic_id: 0x01 done.
518 12:17:13.549738 microcode: Update skipped, already up-to-date
519 12:17:13.552825 CPU #1 initialized
520 12:17:13.556193 bsp_do_flight_plan done after 459 msecs.
521 12:17:13.559303 CPU: frequency set to 4000 MHz
522 12:17:13.559740 Enabling SMIs.
523 12:17:13.565870 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
524 12:17:13.582628 SATAXPCIE1 indicates PCIe NVMe is present
525 12:17:13.585850 Probing TPM: done!
526 12:17:13.589365 Connected to device vid:did:rid of 1ae0:0028:00
527 12:17:13.600179 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.51/cr50_v1.9308_B.1054-0e610b99f9
528 12:17:13.603046 Initialized TPM device CR50 revision 0
529 12:17:13.606595 Enabling S0i3.4
530 12:17:13.613283 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
531 12:17:13.616610 Found a VBT of 8704 bytes after decompression
532 12:17:13.623191 cse_lite: CSE RO boot. HybridStorageMode disabled
533 12:17:13.629599 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
534 12:17:13.705880 FSPS returned 0
535 12:17:13.709306 Executing Phase 1 of FspMultiPhaseSiInit
536 12:17:13.719649 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
537 12:17:13.722798 port C0 DISC req: usage 1 usb3 1 usb2 5
538 12:17:13.726318 Raw Buffer output 0 00000511
539 12:17:13.728972 Raw Buffer output 1 00000000
540 12:17:13.733232 pmc_send_ipc_cmd succeeded
541 12:17:13.736660 port C1 DISC req: usage 1 usb3 2 usb2 3
542 12:17:13.739299
543 12:17:13.739739 Raw Buffer output 0 00000321
544 12:17:13.742758 Raw Buffer output 1 00000000
545 12:17:13.746789 pmc_send_ipc_cmd succeeded
546 12:17:13.751967 Detected 4 core, 8 thread CPU.
547 12:17:13.755418 Detected 4 core, 8 thread CPU.
548 12:17:13.989177 Display FSP Version Info HOB
549 12:17:13.992274 Reference Code - CPU = a.0.4c.31
550 12:17:13.995833 uCode Version = 0.0.0.86
551 12:17:13.999469 TXT ACM version = ff.ff.ff.ffff
552 12:17:14.002343 Reference Code - ME = a.0.4c.31
553 12:17:14.006001 MEBx version = 0.0.0.0
554 12:17:14.008788 ME Firmware Version = Consumer SKU
555 12:17:14.012264 Reference Code - PCH = a.0.4c.31
556 12:17:14.015727 PCH-CRID Status = Disabled
557 12:17:14.018713 PCH-CRID Original Value = ff.ff.ff.ffff
558 12:17:14.022452 PCH-CRID New Value = ff.ff.ff.ffff
559 12:17:14.025582 OPROM - RST - RAID = ff.ff.ff.ffff
560 12:17:14.028957 PCH Hsio Version = 4.0.0.0
561 12:17:14.032421 Reference Code - SA - System Agent = a.0.4c.31
562 12:17:14.035353 Reference Code - MRC = 2.0.0.1
563 12:17:14.038807 SA - PCIe Version = a.0.4c.31
564 12:17:14.041960 SA-CRID Status = Disabled
565 12:17:14.045698 SA-CRID Original Value = 0.0.0.1
566 12:17:14.049262 SA-CRID New Value = 0.0.0.1
567 12:17:14.052304 OPROM - VBIOS = ff.ff.ff.ffff
568 12:17:14.055541 IO Manageability Engine FW Version = 11.1.4.0
569 12:17:14.058638 PHY Build Version = 0.0.0.e0
570 12:17:14.062120 Thunderbolt(TM) FW Version = 0.0.0.0
571 12:17:14.068609 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
572 12:17:14.072027 ITSS IRQ Polarities Before:
573 12:17:14.072113 IPC0: 0xffffffff
574 12:17:14.075318 IPC1: 0xffffffff
575 12:17:14.075404 IPC2: 0xffffffff
576 12:17:14.078870 IPC3: 0xffffffff
577 12:17:14.082296 ITSS IRQ Polarities After:
578 12:17:14.082382 IPC0: 0xffffffff
579 12:17:14.085626 IPC1: 0xffffffff
580 12:17:14.085738 IPC2: 0xffffffff
581 12:17:14.088832 IPC3: 0xffffffff
582 12:17:14.091868 Found PCIe Root Port #9 at PCI: 00:1d.0.
583 12:17:14.105460 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
584 12:17:14.115351 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
585 12:17:14.128402 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
586 12:17:14.135093 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
587 12:17:14.135187 Enumerating buses...
588 12:17:14.138579
589 12:17:14.141518 Show all devs... Before device enumeration.
590 12:17:14.145124 Root Device: enabled 1
591 12:17:14.145217 DOMAIN: 0000: enabled 1
592 12:17:14.148301 CPU_CLUSTER: 0: enabled 1
593 12:17:14.152265 PCI: 00:00.0: enabled 1
594 12:17:14.155105 PCI: 00:02.0: enabled 1
595 12:17:14.155190 PCI: 00:04.0: enabled 1
596 12:17:14.158320 PCI: 00:05.0: enabled 1
597 12:17:14.161713 PCI: 00:06.0: enabled 0
598 12:17:14.161799 PCI: 00:07.0: enabled 0
599 12:17:14.165173 PCI: 00:07.1: enabled 0
600 12:17:14.168108 PCI: 00:07.2: enabled 0
601 12:17:14.171629 PCI: 00:07.3: enabled 0
602 12:17:14.171715 PCI: 00:08.0: enabled 1
603 12:17:14.175078 PCI: 00:09.0: enabled 0
604 12:17:14.178024 PCI: 00:0a.0: enabled 0
605 12:17:14.181891 PCI: 00:0d.0: enabled 1
606 12:17:14.181977 PCI: 00:0d.1: enabled 0
607 12:17:14.184860 PCI: 00:0d.2: enabled 0
608 12:17:14.188136 PCI: 00:0d.3: enabled 0
609 12:17:14.191590 PCI: 00:0e.0: enabled 0
610 12:17:14.191676 PCI: 00:10.2: enabled 1
611 12:17:14.194951 PCI: 00:10.6: enabled 0
612 12:17:14.197977 PCI: 00:10.7: enabled 0
613 12:17:14.198063 PCI: 00:12.0: enabled 0
614 12:17:14.201691
615 12:17:14.201777 PCI: 00:12.6: enabled 0
616 12:17:14.204651 PCI: 00:13.0: enabled 0
617 12:17:14.207856 PCI: 00:14.0: enabled 1
618 12:17:14.207942 PCI: 00:14.1: enabled 0
619 12:17:14.211567 PCI: 00:14.2: enabled 1
620 12:17:14.215146 PCI: 00:14.3: enabled 1
621 12:17:14.217952 PCI: 00:15.0: enabled 1
622 12:17:14.218048 PCI: 00:15.1: enabled 1
623 12:17:14.221367 PCI: 00:15.2: enabled 1
624 12:17:14.224815 PCI: 00:15.3: enabled 1
625 12:17:14.228203 PCI: 00:16.0: enabled 1
626 12:17:14.228282 PCI: 00:16.1: enabled 0
627 12:17:14.231550 PCI: 00:16.2: enabled 0
628 12:17:14.234499 PCI: 00:16.3: enabled 0
629 12:17:14.238169 PCI: 00:16.4: enabled 0
630 12:17:14.238244 PCI: 00:16.5: enabled 0
631 12:17:14.241471 PCI: 00:17.0: enabled 1
632 12:17:14.244791 PCI: 00:19.0: enabled 0
633 12:17:14.244870 PCI: 00:19.1: enabled 1
634 12:17:14.248298 PCI: 00:19.2: enabled 0
635 12:17:14.251120 PCI: 00:1c.0: enabled 1
636 12:17:14.254814 PCI: 00:1c.1: enabled 0
637 12:17:14.254892 PCI: 00:1c.2: enabled 0
638 12:17:14.258240 PCI: 00:1c.3: enabled 0
639 12:17:14.261485 PCI: 00:1c.4: enabled 0
640 12:17:14.264734 PCI: 00:1c.5: enabled 0
641 12:17:14.264814 PCI: 00:1c.6: enabled 1
642 12:17:14.267861 PCI: 00:1c.7: enabled 0
643 12:17:14.271608 PCI: 00:1d.0: enabled 1
644 12:17:14.274694 PCI: 00:1d.1: enabled 0
645 12:17:14.274775 PCI: 00:1d.2: enabled 1
646 12:17:14.278069 PCI: 00:1d.3: enabled 0
647 12:17:14.280956 PCI: 00:1e.0: enabled 1
648 12:17:14.281052 PCI: 00:1e.1: enabled 0
649 12:17:14.284245
650 12:17:14.284351 PCI: 00:1e.2: enabled 1
651 12:17:14.287786 PCI: 00:1e.3: enabled 1
652 12:17:14.290915 PCI: 00:1f.0: enabled 1
653 12:17:14.291001 PCI: 00:1f.1: enabled 0
654 12:17:14.294492 PCI: 00:1f.2: enabled 1
655 12:17:14.297771 PCI: 00:1f.3: enabled 1
656 12:17:14.301288 PCI: 00:1f.4: enabled 0
657 12:17:14.301365 PCI: 00:1f.5: enabled 1
658 12:17:14.304553 PCI: 00:1f.6: enabled 0
659 12:17:14.307578 PCI: 00:1f.7: enabled 0
660 12:17:14.307656 APIC: 00: enabled 1
661 12:17:14.311111 GENERIC: 0.0: enabled 1
662 12:17:14.314286 GENERIC: 0.0: enabled 1
663 12:17:14.317763 GENERIC: 1.0: enabled 1
664 12:17:14.317848 GENERIC: 0.0: enabled 1
665 12:17:14.321373 GENERIC: 1.0: enabled 1
666 12:17:14.324213 USB0 port 0: enabled 1
667 12:17:14.327715 GENERIC: 0.0: enabled 1
668 12:17:14.327796 USB0 port 0: enabled 1
669 12:17:14.330935 GENERIC: 0.0: enabled 1
670 12:17:14.334607 I2C: 00:1a: enabled 1
671 12:17:14.334690 I2C: 00:31: enabled 1
672 12:17:14.337711 I2C: 00:32: enabled 1
673 12:17:14.341081 I2C: 00:10: enabled 1
674 12:17:14.341161 I2C: 00:15: enabled 1
675 12:17:14.344264 GENERIC: 0.0: enabled 0
676 12:17:14.347800 GENERIC: 1.0: enabled 0
677 12:17:14.351012 GENERIC: 0.0: enabled 1
678 12:17:14.351094 SPI: 00: enabled 1
679 12:17:14.354124 SPI: 00: enabled 1
680 12:17:14.354207 PNP: 0c09.0: enabled 1
681 12:17:14.357548
682 12:17:14.357622 GENERIC: 0.0: enabled 1
683 12:17:14.360953 USB3 port 0: enabled 1
684 12:17:14.364223 USB3 port 1: enabled 1
685 12:17:14.364321 USB3 port 2: enabled 0
686 12:17:14.367756 USB3 port 3: enabled 0
687 12:17:14.371125 USB2 port 0: enabled 0
688 12:17:14.371205 USB2 port 1: enabled 1
689 12:17:14.374138 USB2 port 2: enabled 1
690 12:17:14.377421 USB2 port 3: enabled 0
691 12:17:14.380916 USB2 port 4: enabled 1
692 12:17:14.380994 USB2 port 5: enabled 0
693 12:17:14.384099 USB2 port 6: enabled 0
694 12:17:14.387223 USB2 port 7: enabled 0
695 12:17:14.387307 USB2 port 8: enabled 0
696 12:17:14.390637 USB2 port 9: enabled 0
697 12:17:14.394136 USB3 port 0: enabled 0
698 12:17:14.397708 USB3 port 1: enabled 1
699 12:17:14.397808 USB3 port 2: enabled 0
700 12:17:14.401129 USB3 port 3: enabled 0
701 12:17:14.404167 GENERIC: 0.0: enabled 1
702 12:17:14.404242 GENERIC: 1.0: enabled 1
703 12:17:14.407225 APIC: 01: enabled 1
704 12:17:14.410979 APIC: 03: enabled 1
705 12:17:14.411054 APIC: 04: enabled 1
706 12:17:14.414009 APIC: 07: enabled 1
707 12:17:14.414090 APIC: 06: enabled 1
708 12:17:14.416984
709 12:17:14.417058 APIC: 02: enabled 1
710 12:17:14.420430 APIC: 05: enabled 1
711 12:17:14.420503 Compare with tree...
712 12:17:14.424230 Root Device: enabled 1
713 12:17:14.427053 DOMAIN: 0000: enabled 1
714 12:17:14.430483 PCI: 00:00.0: enabled 1
715 12:17:14.430559 PCI: 00:02.0: enabled 1
716 12:17:14.433716 PCI: 00:04.0: enabled 1
717 12:17:14.437195 GENERIC: 0.0: enabled 1
718 12:17:14.440499 PCI: 00:05.0: enabled 1
719 12:17:14.443942 PCI: 00:06.0: enabled 0
720 12:17:14.444024 PCI: 00:07.0: enabled 0
721 12:17:14.447065 GENERIC: 0.0: enabled 1
722 12:17:14.450390 PCI: 00:07.1: enabled 0
723 12:17:14.453651 GENERIC: 1.0: enabled 1
724 12:17:14.456980 PCI: 00:07.2: enabled 0
725 12:17:14.460782 GENERIC: 0.0: enabled 1
726 12:17:14.460854 PCI: 00:07.3: enabled 0
727 12:17:14.463746 GENERIC: 1.0: enabled 1
728 12:17:14.467135 PCI: 00:08.0: enabled 1
729 12:17:14.470629 PCI: 00:09.0: enabled 0
730 12:17:14.473632 PCI: 00:0a.0: enabled 0
731 12:17:14.473707 PCI: 00:0d.0: enabled 1
732 12:17:14.477023 USB0 port 0: enabled 1
733 12:17:14.480474 USB3 port 0: enabled 1
734 12:17:14.483599 USB3 port 1: enabled 1
735 12:17:14.487291 USB3 port 2: enabled 0
736 12:17:14.487364 USB3 port 3: enabled 0
737 12:17:14.490179 PCI: 00:0d.1: enabled 0
738 12:17:14.493933 PCI: 00:0d.2: enabled 0
739 12:17:14.497103 GENERIC: 0.0: enabled 1
740 12:17:14.500227 PCI: 00:0d.3: enabled 0
741 12:17:14.500332 PCI: 00:0e.0: enabled 0
742 12:17:14.503709 PCI: 00:10.2: enabled 1
743 12:17:14.506867 PCI: 00:10.6: enabled 0
744 12:17:14.510378 PCI: 00:10.7: enabled 0
745 12:17:14.513850 PCI: 00:12.0: enabled 0
746 12:17:14.513934 PCI: 00:12.6: enabled 0
747 12:17:14.516572 PCI: 00:13.0: enabled 0
748 12:17:14.519941 PCI: 00:14.0: enabled 1
749 12:17:14.523426 USB0 port 0: enabled 1
750 12:17:14.526440 USB2 port 0: enabled 0
751 12:17:14.526514 USB2 port 1: enabled 1
752 12:17:14.529876
753 12:17:14.529949 USB2 port 2: enabled 1
754 12:17:14.533247 USB2 port 3: enabled 0
755 12:17:14.537699 USB2 port 4: enabled 1
756 12:17:14.540904 USB2 port 5: enabled 0
757 12:17:14.540983 USB2 port 6: enabled 0
758 12:17:14.544899 USB2 port 7: enabled 0
759 12:17:14.548222 USB2 port 8: enabled 0
760 12:17:14.551585 USB2 port 9: enabled 0
761 12:17:14.551663 USB3 port 0: enabled 0
762 12:17:14.554946 USB3 port 1: enabled 1
763 12:17:14.558245 USB3 port 2: enabled 0
764 12:17:14.561305 USB3 port 3: enabled 0
765 12:17:14.564815 PCI: 00:14.1: enabled 0
766 12:17:14.564899 PCI: 00:14.2: enabled 1
767 12:17:14.568026
768 12:17:14.568099 PCI: 00:14.3: enabled 1
769 12:17:14.571300 GENERIC: 0.0: enabled 1
770 12:17:14.574655 PCI: 00:15.0: enabled 1
771 12:17:14.578140 I2C: 00:1a: enabled 1
772 12:17:14.578217 I2C: 00:31: enabled 1
773 12:17:14.628020 I2C: 00:32: enabled 1
774 12:17:14.628126 PCI: 00:15.1: enabled 1
775 12:17:14.628386 I2C: 00:10: enabled 1
776 12:17:14.628456 PCI: 00:15.2: enabled 1
777 12:17:14.629154 PCI: 00:15.3: enabled 1
778 12:17:14.629226 PCI: 00:16.0: enabled 1
779 12:17:14.629328 PCI: 00:16.1: enabled 0
780 12:17:14.629573 PCI: 00:16.2: enabled 0
781 12:17:14.629640 PCI: 00:16.3: enabled 0
782 12:17:14.630136 PCI: 00:16.4: enabled 0
783 12:17:14.630201 PCI: 00:16.5: enabled 0
784 12:17:14.630260 PCI: 00:17.0: enabled 1
785 12:17:14.630499
786 12:17:14.630572 PCI: 00:19.0: enabled 0
787 12:17:14.630632 PCI: 00:19.1: enabled 1
788 12:17:14.630872 I2C: 00:15: enabled 1
789 12:17:14.630933 PCI: 00:19.2: enabled 0
790 12:17:14.630990 PCI: 00:1d.0: enabled 1
791 12:17:14.631055 GENERIC: 0.0: enabled 1
792 12:17:14.631112 PCI: 00:1e.0: enabled 1
793 12:17:14.677694 PCI: 00:1e.1: enabled 0
794 12:17:14.677779 PCI: 00:1e.2: enabled 1
795 12:17:14.678037 SPI: 00: enabled 1
796 12:17:14.678105 PCI: 00:1e.3: enabled 1
797 12:17:14.678178 SPI: 00: enabled 1
798 12:17:14.678421 PCI: 00:1f.0: enabled 1
799 12:17:14.678486 PNP: 0c09.0: enabled 1
800 12:17:14.678727 PCI: 00:1f.1: enabled 0
801 12:17:14.678793 PCI: 00:1f.2: enabled 1
802 12:17:14.679212 GENERIC: 0.0: enabled 1
803 12:17:14.679279 GENERIC: 0.0: enabled 1
804 12:17:14.679337 GENERIC: 1.0: enabled 1
805 12:17:14.679575 PCI: 00:1f.3: enabled 1
806 12:17:14.679636 PCI: 00:1f.4: enabled 0
807 12:17:14.679879 PCI: 00:1f.5: enabled 1
808 12:17:14.679942 PCI: 00:1f.6: enabled 0
809 12:17:14.680455 PCI: 00:1f.7: enabled 0
810 12:17:14.680523 CPU_CLUSTER: 0: enabled 1
811 12:17:14.680580 APIC: 00: enabled 1
812 12:17:14.721997 APIC: 01: enabled 1
813 12:17:14.722092 APIC: 03: enabled 1
814 12:17:14.722160 APIC: 04: enabled 1
815 12:17:14.722416 APIC: 07: enabled 1
816 12:17:14.722485 APIC: 06: enabled 1
817 12:17:14.722729 APIC: 02: enabled 1
818 12:17:14.722793 APIC: 05: enabled 1
819 12:17:14.722861 Root Device scanning...
820 12:17:14.723129 scan_static_bus for Root Device
821 12:17:14.723193 DOMAIN: 0000 enabled
822 12:17:14.723760 CPU_CLUSTER: 0 enabled
823 12:17:14.723833 DOMAIN: 0000 scanning...
824 12:17:14.723894 PCI: pci_scan_bus for bus 00
825 12:17:14.724134 PCI: 00:00.0 [8086/0000] ops
826 12:17:14.724196 PCI: 00:00.0 [8086/9a12] enabled
827 12:17:14.726675 PCI: 00:02.0 [8086/0000] bus ops
828 12:17:14.726763 PCI: 00:02.0 [8086/9a40] enabled
829 12:17:14.730035 PCI: 00:04.0 [8086/0000] bus ops
830 12:17:14.733136 PCI: 00:04.0 [8086/9a03] enabled
831 12:17:14.736713 PCI: 00:05.0 [8086/9a19] enabled
832 12:17:14.739704 PCI: 00:07.0 [0000/0000] hidden
833 12:17:14.743082 PCI: 00:08.0 [8086/9a11] enabled
834 12:17:14.746642 PCI: 00:0a.0 [8086/9a0d] disabled
835 12:17:14.750070 PCI: 00:0d.0 [8086/0000] bus ops
836 12:17:14.752843 PCI: 00:0d.0 [8086/9a13] enabled
837 12:17:14.756256 PCI: 00:14.0 [8086/0000] bus ops
838 12:17:14.759633 PCI: 00:14.0 [8086/a0ed] enabled
839 12:17:14.762831 PCI: 00:14.2 [8086/a0ef] enabled
840 12:17:14.766216 PCI: 00:14.3 [8086/0000] bus ops
841 12:17:14.769272 PCI: 00:14.3 [8086/a0f0] enabled
842 12:17:14.772703 PCI: 00:15.0 [8086/0000] bus ops
843 12:17:14.776348 PCI: 00:15.0 [8086/a0e8] enabled
844 12:17:14.779595 PCI: 00:15.1 [8086/0000] bus ops
845 12:17:14.782759 PCI: 00:15.1 [8086/a0e9] enabled
846 12:17:14.785951 PCI: 00:15.2 [8086/0000] bus ops
847 12:17:14.789282 PCI: 00:15.2 [8086/a0ea] enabled
848 12:17:14.792822 PCI: 00:15.3 [8086/0000] bus ops
849 12:17:14.795989 PCI: 00:15.3 [8086/a0eb] enabled
850 12:17:14.798992 PCI: 00:16.0 [8086/0000] ops
851 12:17:14.802459 PCI: 00:16.0 [8086/a0e0] enabled
852 12:17:14.805760 PCI: Static device PCI: 00:17.0 not found, disabling it.
853 12:17:14.809018 PCI: 00:19.0 [8086/0000] bus ops
854 12:17:14.812636 PCI: 00:19.0 [8086/a0c5] disabled
855 12:17:14.815761 PCI: 00:19.1 [8086/0000] bus ops
856 12:17:14.819296 PCI: 00:19.1 [8086/a0c6] enabled
857 12:17:14.822000 PCI: 00:1d.0 [8086/0000] bus ops
858 12:17:14.825903
859 12:17:14.825990 PCI: 00:1d.0 [8086/a0b0] enabled
860 12:17:14.828635
861 12:17:14.828725 PCI: 00:1e.0 [8086/0000] ops
862 12:17:14.832130 PCI: 00:1e.0 [8086/a0a8] enabled
863 12:17:14.835592 PCI: 00:1e.2 [8086/0000] bus ops
864 12:17:14.838623 PCI: 00:1e.2 [8086/a0aa] enabled
865 12:17:14.841908 PCI: 00:1e.3 [8086/0000] bus ops
866 12:17:14.845560 PCI: 00:1e.3 [8086/a0ab] enabled
867 12:17:14.849228 PCI: 00:1f.0 [8086/0000] bus ops
868 12:17:14.852435 PCI: 00:1f.0 [8086/a087] enabled
869 12:17:14.855253 RTC Init
870 12:17:14.859095 Set power on after power failure.
871 12:17:14.859181 Disabling Deep S3
872 12:17:14.861958
873 12:17:14.862044 Disabling Deep S3
874 12:17:14.865044 Disabling Deep S4
875 12:17:14.865129 Disabling Deep S4
876 12:17:14.868506 Disabling Deep S5
877 12:17:14.868592 Disabling Deep S5
878 12:17:14.871977 PCI: 00:1f.2 [0000/0000] hidden
879 12:17:14.875386 PCI: 00:1f.3 [8086/0000] bus ops
880 12:17:14.878694 PCI: 00:1f.3 [8086/a0c8] enabled
881 12:17:14.881856 PCI: 00:1f.5 [8086/0000] bus ops
882 12:17:14.885296 PCI: 00:1f.5 [8086/a0a4] enabled
883 12:17:14.888421 PCI: Leftover static devices:
884 12:17:14.891929 PCI: 00:10.2
885 12:17:14.892017 PCI: 00:10.6
886 12:17:14.892084 PCI: 00:10.7
887 12:17:14.895211 PCI: 00:06.0
888 12:17:14.895298 PCI: 00:07.1
889 12:17:14.898261 PCI: 00:07.2
890 12:17:14.898347 PCI: 00:07.3
891 12:17:14.901526 PCI: 00:09.0
892 12:17:14.901612 PCI: 00:0d.1
893 12:17:14.901679 PCI: 00:0d.2
894 12:17:14.905136 PCI: 00:0d.3
895 12:17:14.905221 PCI: 00:0e.0
896 12:17:14.908411 PCI: 00:12.0
897 12:17:14.908497 PCI: 00:12.6
898 12:17:14.908564 PCI: 00:13.0
899 12:17:14.911946 PCI: 00:14.1
900 12:17:14.912032 PCI: 00:16.1
901 12:17:14.914884 PCI: 00:16.2
902 12:17:14.914977 PCI: 00:16.3
903 12:17:14.915045 PCI: 00:16.4
904 12:17:14.918246 PCI: 00:16.5
905 12:17:14.918330 PCI: 00:17.0
906 12:17:14.921923 PCI: 00:19.2
907 12:17:14.922001 PCI: 00:1e.1
908 12:17:14.925375 PCI: 00:1f.1
909 12:17:14.925448 PCI: 00:1f.4
910 12:17:14.925510 PCI: 00:1f.6
911 12:17:14.928801 PCI: 00:1f.7
912 12:17:14.931637 PCI: Check your devicetree.cb.
913 12:17:14.931714 PCI: 00:02.0 scanning...
914 12:17:14.935106
915 12:17:14.938044 scan_generic_bus for PCI: 00:02.0
916 12:17:14.941487 scan_generic_bus for PCI: 00:02.0 done
917 12:17:14.945060 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
918 12:17:14.948331 PCI: 00:04.0 scanning...
919 12:17:14.951460 scan_generic_bus for PCI: 00:04.0
920 12:17:14.954732 GENERIC: 0.0 enabled
921 12:17:14.961304 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
922 12:17:14.964604 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
923 12:17:14.967896 PCI: 00:0d.0 scanning...
924 12:17:14.971108 scan_static_bus for PCI: 00:0d.0
925 12:17:14.974404 USB0 port 0 enabled
926 12:17:14.974484 USB0 port 0 scanning...
927 12:17:14.977815 scan_static_bus for USB0 port 0
928 12:17:14.980814 USB3 port 0 enabled
929 12:17:14.984705 USB3 port 1 enabled
930 12:17:14.984788 USB3 port 2 disabled
931 12:17:14.987688 USB3 port 3 disabled
932 12:17:14.991038 USB3 port 0 scanning...
933 12:17:14.994375 scan_static_bus for USB3 port 0
934 12:17:14.997684 scan_static_bus for USB3 port 0 done
935 12:17:15.000908 scan_bus: bus USB3 port 0 finished in 6 msecs
936 12:17:15.004273 USB3 port 1 scanning...
937 12:17:15.008236 scan_static_bus for USB3 port 1
938 12:17:15.011012 scan_static_bus for USB3 port 1 done
939 12:17:15.014254 scan_bus: bus USB3 port 1 finished in 6 msecs
940 12:17:15.020752 scan_static_bus for USB0 port 0 done
941 12:17:15.024044 scan_bus: bus USB0 port 0 finished in 43 msecs
942 12:17:15.027533 scan_static_bus for PCI: 00:0d.0 done
943 12:17:15.034032 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
944 12:17:15.034118 PCI: 00:14.0 scanning...
945 12:17:15.037371 scan_static_bus for PCI: 00:14.0
946 12:17:15.040375 USB0 port 0 enabled
947 12:17:15.043872 USB0 port 0 scanning...
948 12:17:15.047159 scan_static_bus for USB0 port 0
949 12:17:15.047258 USB2 port 0 disabled
950 12:17:15.050560 USB2 port 1 enabled
951 12:17:15.053621 USB2 port 2 enabled
952 12:17:15.053710 USB2 port 3 disabled
953 12:17:15.057446 USB2 port 4 enabled
954 12:17:15.060656 USB2 port 5 disabled
955 12:17:15.060740 USB2 port 6 disabled
956 12:17:15.063624 USB2 port 7 disabled
957 12:17:15.067435 USB2 port 8 disabled
958 12:17:15.067532 USB2 port 9 disabled
959 12:17:15.070781 USB3 port 0 disabled
960 12:17:15.070866 USB3 port 1 enabled
961 12:17:15.074231
962 12:17:15.074316 USB3 port 2 disabled
963 12:17:15.076945 USB3 port 3 disabled
964 12:17:15.080256 USB2 port 1 scanning...
965 12:17:15.083719 scan_static_bus for USB2 port 1
966 12:17:15.086543 scan_static_bus for USB2 port 1 done
967 12:17:15.090013 scan_bus: bus USB2 port 1 finished in 6 msecs
968 12:17:15.093635 USB2 port 2 scanning...
969 12:17:15.096741 scan_static_bus for USB2 port 2
970 12:17:15.100107 scan_static_bus for USB2 port 2 done
971 12:17:15.103394 scan_bus: bus USB2 port 2 finished in 6 msecs
972 12:17:15.106800 USB2 port 4 scanning...
973 12:17:15.109948 scan_static_bus for USB2 port 4
974 12:17:15.113174 scan_static_bus for USB2 port 4 done
975 12:17:15.120197 scan_bus: bus USB2 port 4 finished in 6 msecs
976 12:17:15.120284 USB3 port 1 scanning...
977 12:17:15.123685 scan_static_bus for USB3 port 1
978 12:17:15.127228 scan_static_bus for USB3 port 1 done
979 12:17:15.130116
980 12:17:15.133558 scan_bus: bus USB3 port 1 finished in 6 msecs
981 12:17:15.137358 scan_static_bus for USB0 port 0 done
982 12:17:15.140072 scan_bus: bus USB0 port 0 finished in 93 msecs
983 12:17:15.146712 scan_static_bus for PCI: 00:14.0 done
984 12:17:15.150197 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
985 12:17:15.153483 PCI: 00:14.3 scanning...
986 12:17:15.156761 scan_static_bus for PCI: 00:14.3
987 12:17:15.159983 GENERIC: 0.0 enabled
988 12:17:15.163618 scan_static_bus for PCI: 00:14.3 done
989 12:17:15.166575 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
990 12:17:15.170103 PCI: 00:15.0 scanning...
991 12:17:15.173514 scan_static_bus for PCI: 00:15.0
992 12:17:15.173600 I2C: 00:1a enabled
993 12:17:15.176755
994 12:17:15.176841 I2C: 00:31 enabled
995 12:17:15.180150 I2C: 00:32 enabled
996 12:17:15.183751 scan_static_bus for PCI: 00:15.0 done
997 12:17:15.186504 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
998 12:17:15.189893 PCI: 00:15.1 scanning...
999 12:17:15.193061 scan_static_bus for PCI: 00:15.1
1000 12:17:15.196493 I2C: 00:10 enabled
1001 12:17:15.199953 scan_static_bus for PCI: 00:15.1 done
1002 12:17:15.203122 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1003 12:17:15.206667 PCI: 00:15.2 scanning...
1004 12:17:15.209800 scan_static_bus for PCI: 00:15.2
1005 12:17:15.213009 scan_static_bus for PCI: 00:15.2 done
1006 12:17:15.219794 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1007 12:17:15.219880 PCI: 00:15.3 scanning...
1008 12:17:15.223147 scan_static_bus for PCI: 00:15.3
1009 12:17:15.229722 scan_static_bus for PCI: 00:15.3 done
1010 12:17:15.232896 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1011 12:17:15.236297 PCI: 00:19.1 scanning...
1012 12:17:15.239836 scan_static_bus for PCI: 00:19.1
1013 12:17:15.239921 I2C: 00:15 enabled
1014 12:17:15.246253 scan_static_bus for PCI: 00:19.1 done
1015 12:17:15.249852 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1016 12:17:15.253124 PCI: 00:1d.0 scanning...
1017 12:17:15.256450 do_pci_scan_bridge for PCI: 00:1d.0
1018 12:17:15.259676 PCI: pci_scan_bus for bus 01
1019 12:17:15.263144 PCI: 01:00.0 [1c5c/174a] enabled
1020 12:17:15.266435 GENERIC: 0.0 enabled
1021 12:17:15.269520 Enabling Common Clock Configuration
1022 12:17:15.273027 L1 Sub-State supported from root port 29
1023 12:17:15.276185 L1 Sub-State Support = 0xf
1024 12:17:15.279249 CommonModeRestoreTime = 0x28
1025 12:17:15.282777 Power On Value = 0x16, Power On Scale = 0x0
1026 12:17:15.286227 ASPM: Enabled L1
1027 12:17:15.289904 PCIe: Max_Payload_Size adjusted to 128
1028 12:17:15.292471 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1029 12:17:15.296210 PCI: 00:1e.2 scanning...
1030 12:17:15.299188 scan_generic_bus for PCI: 00:1e.2
1031 12:17:15.302823 SPI: 00 enabled
1032 12:17:15.306108 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1033 12:17:15.312682 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1034 12:17:15.316052 PCI: 00:1e.3 scanning...
1035 12:17:15.319230 scan_generic_bus for PCI: 00:1e.3
1036 12:17:15.319307 SPI: 00 enabled
1037 12:17:15.325786 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1038 12:17:15.329007 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1039 12:17:15.332365 PCI: 00:1f.0 scanning...
1040 12:17:15.335966 scan_static_bus for PCI: 00:1f.0
1041 12:17:15.339218 PNP: 0c09.0 enabled
1042 12:17:15.342394 PNP: 0c09.0 scanning...
1043 12:17:15.345611 scan_static_bus for PNP: 0c09.0
1044 12:17:15.349027 scan_static_bus for PNP: 0c09.0 done
1045 12:17:15.352465 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1046 12:17:15.355543 scan_static_bus for PCI: 00:1f.0 done
1047 12:17:15.361937 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1048 12:17:15.365262 PCI: 00:1f.2 scanning...
1049 12:17:15.369047 scan_static_bus for PCI: 00:1f.2
1050 12:17:15.369126 GENERIC: 0.0 enabled
1051 12:17:15.372290 GENERIC: 0.0 scanning...
1052 12:17:15.375585 scan_static_bus for GENERIC: 0.0
1053 12:17:15.378806 GENERIC: 0.0 enabled
1054 12:17:15.378884 GENERIC: 1.0 enabled
1055 12:17:15.385196 scan_static_bus for GENERIC: 0.0 done
1056 12:17:15.388666 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1057 12:17:15.392218 scan_static_bus for PCI: 00:1f.2 done
1058 12:17:15.398854 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1059 12:17:15.398940 PCI: 00:1f.3 scanning...
1060 12:17:15.402344 scan_static_bus for PCI: 00:1f.3
1061 12:17:15.408574 scan_static_bus for PCI: 00:1f.3 done
1062 12:17:15.412016 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1063 12:17:15.415485 PCI: 00:1f.5 scanning...
1064 12:17:15.418632 scan_generic_bus for PCI: 00:1f.5
1065 12:17:15.421959 scan_generic_bus for PCI: 00:1f.5 done
1066 12:17:15.425345 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1067 12:17:15.428843
1068 12:17:15.431685 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1069 12:17:15.435035 scan_static_bus for Root Device done
1070 12:17:15.441480 scan_bus: bus Root Device finished in 736 msecs
1071 12:17:15.441558 done
1072 12:17:15.448471 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1073 12:17:15.451483 Chrome EC: UHEPI supported
1074 12:17:15.458236 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1075 12:17:15.465156 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1076 12:17:15.468480 SPI flash protection: WPSW=0 SRP0=0
1077 12:17:15.471391 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1078 12:17:15.478135 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1079 12:17:15.481488 found VGA at PCI: 00:02.0
1080 12:17:15.484731 Setting up VGA for PCI: 00:02.0
1081 12:17:15.488089 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1082 12:17:15.494796 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1083 12:17:15.494875 Allocating resources...
1084 12:17:15.498180 Reading resources...
1085 12:17:15.501451 Root Device read_resources bus 0 link: 0
1086 12:17:15.507933 DOMAIN: 0000 read_resources bus 0 link: 0
1087 12:17:15.511187 PCI: 00:04.0 read_resources bus 1 link: 0
1088 12:17:15.518165 PCI: 00:04.0 read_resources bus 1 link: 0 done
1089 12:17:15.521211 PCI: 00:0d.0 read_resources bus 0 link: 0
1090 12:17:15.527861 USB0 port 0 read_resources bus 0 link: 0
1091 12:17:15.531364 USB0 port 0 read_resources bus 0 link: 0 done
1092 12:17:15.537784 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1093 12:17:15.540646 PCI: 00:14.0 read_resources bus 0 link: 0
1094 12:17:15.544261 USB0 port 0 read_resources bus 0 link: 0
1095 12:17:15.551818 USB0 port 0 read_resources bus 0 link: 0 done
1096 12:17:15.555084 PCI: 00:14.0 read_resources bus 0 link: 0 done
1097 12:17:15.561800 PCI: 00:14.3 read_resources bus 0 link: 0
1098 12:17:15.565102 PCI: 00:14.3 read_resources bus 0 link: 0 done
1099 12:17:15.571882 PCI: 00:15.0 read_resources bus 0 link: 0
1100 12:17:15.575046 PCI: 00:15.0 read_resources bus 0 link: 0 done
1101 12:17:15.581809 PCI: 00:15.1 read_resources bus 0 link: 0
1102 12:17:15.585063 PCI: 00:15.1 read_resources bus 0 link: 0 done
1103 12:17:15.592716 PCI: 00:19.1 read_resources bus 0 link: 0
1104 12:17:15.595569 PCI: 00:19.1 read_resources bus 0 link: 0 done
1105 12:17:15.602284 PCI: 00:1d.0 read_resources bus 1 link: 0
1106 12:17:15.605667 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1107 12:17:15.612284 PCI: 00:1e.2 read_resources bus 2 link: 0
1108 12:17:15.615572 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1109 12:17:15.622327 PCI: 00:1e.3 read_resources bus 3 link: 0
1110 12:17:15.625906 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1111 12:17:15.632449 PCI: 00:1f.0 read_resources bus 0 link: 0
1112 12:17:15.635641 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1113 12:17:15.638788 PCI: 00:1f.2 read_resources bus 0 link: 0
1114 12:17:15.642080
1115 12:17:15.645466 GENERIC: 0.0 read_resources bus 0 link: 0
1116 12:17:15.651708 GENERIC: 0.0 read_resources bus 0 link: 0 done
1117 12:17:15.655139 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1118 12:17:15.661835 DOMAIN: 0000 read_resources bus 0 link: 0 done
1119 12:17:15.665348 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1120 12:17:15.671903 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1121 12:17:15.675343 Root Device read_resources bus 0 link: 0 done
1122 12:17:15.678527 Done reading resources.
1123 12:17:15.684965 Show resources in subtree (Root Device)...After reading.
1124 12:17:15.688594 Root Device child on link 0 DOMAIN: 0000
1125 12:17:15.691789 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1126 12:17:15.701784 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1127 12:17:15.711690 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1128 12:17:15.711777 PCI: 00:00.0
1129 12:17:15.721956 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1130 12:17:15.731713 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1131 12:17:15.741710 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1132 12:17:15.751538 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1133 12:17:15.761140 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1134 12:17:15.767878 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1135 12:17:15.771291
1136 12:17:15.778117 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1137 12:17:15.787859 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1138 12:17:15.798001 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1139 12:17:15.807860 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1140 12:17:15.817946 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1141 12:17:15.824488 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1142 12:17:15.834319 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1143 12:17:15.844492 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1144 12:17:15.854145 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1145 12:17:15.864244 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1146 12:17:15.874124 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1147 12:17:15.880743 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1148 12:17:15.883767
1149 12:17:15.890694 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1150 12:17:15.900690 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1151 12:17:15.904075 PCI: 00:02.0
1152 12:17:15.913661 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1153 12:17:15.924006 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1154 12:17:15.930805 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1155 12:17:15.934104
1156 12:17:15.937140 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 12:17:15.947068 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 12:17:15.947160 GENERIC: 0.0
1159 12:17:15.950445 PCI: 00:05.0
1160 12:17:15.960202 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 12:17:15.963526 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 12:17:15.967064 GENERIC: 0.0
1163 12:17:15.967149 PCI: 00:08.0
1164 12:17:15.976742 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 12:17:15.980661 PCI: 00:0a.0
1166 12:17:15.983369 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 12:17:15.993587 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 12:17:16.000086 USB0 port 0 child on link 0 USB3 port 0
1169 12:17:16.000172 USB3 port 0
1170 12:17:16.003358 USB3 port 1
1171 12:17:16.003442 USB3 port 2
1172 12:17:16.006659 USB3 port 3
1173 12:17:16.010029 PCI: 00:14.0 child on link 0 USB0 port 0
1174 12:17:16.020232 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1175 12:17:16.023576 USB0 port 0 child on link 0 USB2 port 0
1176 12:17:16.026669 USB2 port 0
1177 12:17:16.026747 USB2 port 1
1178 12:17:16.029799 USB2 port 2
1179 12:17:16.029880 USB2 port 3
1180 12:17:16.033478
1181 12:17:16.033558 USB2 port 4
1182 12:17:16.036750 USB2 port 5
1183 12:17:16.036831 USB2 port 6
1184 12:17:16.040442 USB2 port 7
1185 12:17:16.040519 USB2 port 8
1186 12:17:16.043097 USB2 port 9
1187 12:17:16.043175 USB3 port 0
1188 12:17:16.046286 USB3 port 1
1189 12:17:16.046360 USB3 port 2
1190 12:17:16.049774 USB3 port 3
1191 12:17:16.049852 PCI: 00:14.2
1192 12:17:16.059797 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1193 12:17:16.069526 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1194 12:17:16.076859 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1195 12:17:16.086507 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1196 12:17:16.086595 GENERIC: 0.0
1197 12:17:16.089798 PCI: 00:15.0 child on link 0 I2C: 00:1a
1198 12:17:16.093093
1199 12:17:16.099361 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1200 12:17:16.102781
1201 12:17:16.102859 I2C: 00:1a
1202 12:17:16.102924 I2C: 00:31
1203 12:17:16.106403 I2C: 00:32
1204 12:17:16.109578 PCI: 00:15.1 child on link 0 I2C: 00:10
1205 12:17:16.119498 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:17:16.122641 I2C: 00:10
1207 12:17:16.122718 PCI: 00:15.2
1208 12:17:16.132787 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1209 12:17:16.136220 PCI: 00:15.3
1210 12:17:16.146094 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1211 12:17:16.146179 PCI: 00:16.0
1212 12:17:16.156094 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 12:17:16.159559 PCI: 00:19.0
1214 12:17:16.162519 PCI: 00:19.1 child on link 0 I2C: 00:15
1215 12:17:16.172464 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1216 12:17:16.172544 I2C: 00:15
1217 12:17:16.179030 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1218 12:17:16.185926 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1219 12:17:16.195713 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1220 12:17:16.205835 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1221 12:17:16.209312 GENERIC: 0.0
1222 12:17:16.209396 PCI: 01:00.0
1223 12:17:16.219346 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1224 12:17:16.229089 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1225 12:17:16.238985 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1226 12:17:16.239071 PCI: 00:1e.0
1227 12:17:16.252082 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1228 12:17:16.255641 PCI: 00:1e.2 child on link 0 SPI: 00
1229 12:17:16.265419 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 12:17:16.265499 SPI: 00
1231 12:17:16.268773 PCI: 00:1e.3 child on link 0 SPI: 00
1232 12:17:16.278753 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1233 12:17:16.282040 SPI: 00
1234 12:17:16.285446 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1235 12:17:16.295473 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1236 12:17:16.295557 PNP: 0c09.0
1237 12:17:16.305740 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1238 12:17:16.308928 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1239 12:17:16.318919 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1240 12:17:16.328642 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1241 12:17:16.331782 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1242 12:17:16.335111 GENERIC: 0.0
1243 12:17:16.335190 GENERIC: 1.0
1244 12:17:16.338879 PCI: 00:1f.3
1245 12:17:16.348930 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1246 12:17:16.358639 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1247 12:17:16.358722 PCI: 00:1f.5
1248 12:17:16.368458 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1249 12:17:16.371545 CPU_CLUSTER: 0 child on link 0 APIC: 00
1250 12:17:16.375043
1251 12:17:16.375122 APIC: 00
1252 12:17:16.375187 APIC: 01
1253 12:17:16.378601 APIC: 03
1254 12:17:16.378686 APIC: 04
1255 12:17:16.378750 APIC: 07
1256 12:17:16.381495 APIC: 06
1257 12:17:16.381573 APIC: 02
1258 12:17:16.385077 APIC: 05
1259 12:17:16.391706 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1260 12:17:16.398671 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1261 12:17:16.401387 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1262 12:17:16.404662
1263 12:17:16.408178 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1264 12:17:16.414915 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1265 12:17:16.418106 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1266 12:17:16.421711 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1267 12:17:16.427841 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1268 12:17:16.434749 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1269 12:17:16.438148
1270 12:17:16.444745 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1271 12:17:16.451274 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1272 12:17:16.458144 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1273 12:17:16.464743 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1274 12:17:16.471190 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1275 12:17:16.480873 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1276 12:17:16.484639 DOMAIN: 0000: Resource ranges:
1277 12:17:16.487553 * Base: 1000, Size: 800, Tag: 100
1278 12:17:16.491084 * Base: 1900, Size: e700, Tag: 100
1279 12:17:16.494340 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1280 12:17:16.497825
1281 12:17:16.500836 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1282 12:17:16.504113
1283 12:17:16.511167 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1284 12:17:16.517776 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1285 12:17:16.524053 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1286 12:17:16.534302 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1287 12:17:16.540714 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1288 12:17:16.547806 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1289 12:17:16.557029 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1290 12:17:16.563724 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1291 12:17:16.570557 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1292 12:17:16.577222 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1293 12:17:16.580540
1294 12:17:16.587213 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1295 12:17:16.593889 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1296 12:17:16.600808 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1297 12:17:16.610356 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1298 12:17:16.616983 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1299 12:17:16.623873 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1300 12:17:16.633569 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1301 12:17:16.640157 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1302 12:17:16.646732 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1303 12:17:16.650066
1304 12:17:16.656394 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1305 12:17:16.663154 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1306 12:17:16.669655 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1307 12:17:16.679834 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1308 12:17:16.683093 DOMAIN: 0000: Resource ranges:
1309 12:17:16.686643 * Base: 7fc00000, Size: 40400000, Tag: 200
1310 12:17:16.689899 * Base: d0000000, Size: 28000000, Tag: 200
1311 12:17:16.696259 * Base: fa000000, Size: 1000000, Tag: 200
1312 12:17:16.699428 * Base: fb001000, Size: 2fff000, Tag: 200
1313 12:17:16.702926 * Base: fe010000, Size: 2e000, Tag: 200
1314 12:17:16.706284 * Base: fe03f000, Size: d41000, Tag: 200
1315 12:17:16.709586
1316 12:17:16.712872 * Base: fed88000, Size: 8000, Tag: 200
1317 12:17:16.716441 * Base: fed93000, Size: d000, Tag: 200
1318 12:17:16.719431 * Base: feda2000, Size: 1e000, Tag: 200
1319 12:17:16.722812 * Base: fede0000, Size: 1220000, Tag: 200
1320 12:17:16.729547 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1321 12:17:16.736212 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1322 12:17:16.742533 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1323 12:17:16.749642 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1324 12:17:16.756365 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1325 12:17:16.762632 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1326 12:17:16.769494 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1327 12:17:16.775838 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1328 12:17:16.782755 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1329 12:17:16.789220 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1330 12:17:16.795481 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1331 12:17:16.802503 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1332 12:17:16.808990 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1333 12:17:16.815774 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1334 12:17:16.822663 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1335 12:17:16.829129 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1336 12:17:16.835210 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1337 12:17:16.842090 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1338 12:17:16.848930 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1339 12:17:16.855519 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1340 12:17:16.862070 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1341 12:17:16.868528 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1342 12:17:16.875219 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1343 12:17:16.881869 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1344 12:17:16.891695 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1345 12:17:16.895088 PCI: 00:1d.0: Resource ranges:
1346 12:17:16.898676 * Base: 7fc00000, Size: 100000, Tag: 200
1347 12:17:16.905326 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1348 12:17:16.911741 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1349 12:17:16.918213 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1350 12:17:16.928724 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1351 12:17:16.934882 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1352 12:17:16.938224 Root Device assign_resources, bus 0 link: 0
1353 12:17:16.941619 DOMAIN: 0000 assign_resources, bus 0 link: 0
1354 12:17:16.951699 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1355 12:17:16.958414 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1356 12:17:16.968604 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1357 12:17:16.974936 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1358 12:17:16.981767 PCI: 00:04.0 assign_resources, bus 1 link: 0
1359 12:17:16.985328 PCI: 00:04.0 assign_resources, bus 1 link: 0
1360 12:17:16.994691 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1361 12:17:17.001504 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1362 12:17:17.011343 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1363 12:17:17.014651 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1364 12:17:17.018017 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1365 12:17:17.027847 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1366 12:17:17.031256 PCI: 00:14.0 assign_resources, bus 0 link: 0
1367 12:17:17.037446 PCI: 00:14.0 assign_resources, bus 0 link: 0
1368 12:17:17.044160 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1369 12:17:17.053894 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1370 12:17:17.060941 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1371 12:17:17.063854 PCI: 00:14.3 assign_resources, bus 0 link: 0
1372 12:17:17.070748 PCI: 00:14.3 assign_resources, bus 0 link: 0
1373 12:17:17.077206 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1374 12:17:17.083721 PCI: 00:15.0 assign_resources, bus 0 link: 0
1375 12:17:17.086871 PCI: 00:15.0 assign_resources, bus 0 link: 0
1376 12:17:17.097228 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1377 12:17:17.100448 PCI: 00:15.1 assign_resources, bus 0 link: 0
1378 12:17:17.103844 PCI: 00:15.1 assign_resources, bus 0 link: 0
1379 12:17:17.113888 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1380 12:17:17.120669 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1381 12:17:17.130497 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1382 12:17:17.137215 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1383 12:17:17.143264 PCI: 00:19.1 assign_resources, bus 0 link: 0
1384 12:17:17.146474 PCI: 00:19.1 assign_resources, bus 0 link: 0
1385 12:17:17.156551 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1386 12:17:17.166653 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1387 12:17:17.173254 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1388 12:17:17.179569 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1389 12:17:17.186483 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1390 12:17:17.196248 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1391 12:17:17.202656 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1392 12:17:17.206072 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1393 12:17:17.216586 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1394 12:17:17.219985 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1395 12:17:17.226688 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1396 12:17:17.233107 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1397 12:17:17.239846 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1398 12:17:17.242568 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1399 12:17:17.246098 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1400 12:17:17.252943 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1401 12:17:17.256197 LPC: Trying to open IO window from 800 size 1ff
1402 12:17:17.266810 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1403 12:17:17.272965 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1404 12:17:17.283183 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1405 12:17:17.286680 DOMAIN: 0000 assign_resources, bus 0 link: 0
1406 12:17:17.293150 Root Device assign_resources, bus 0 link: 0
1407 12:17:17.293241 Done setting resources.
1408 12:17:17.299172 Show resources in subtree (Root Device)...After assigning values.
1409 12:17:17.302629 Root Device child on link 0 DOMAIN: 0000
1410 12:17:17.306121
1411 12:17:17.309660 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1412 12:17:17.319417 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1413 12:17:17.329153 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1414 12:17:17.329240 PCI: 00:00.0
1415 12:17:17.339463 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1416 12:17:17.349499 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1417 12:17:17.359252 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1418 12:17:17.369401 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1419 12:17:17.376066 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1420 12:17:17.385686 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1421 12:17:17.395774 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1422 12:17:17.405602 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1423 12:17:17.415573 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1424 12:17:17.422337 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1425 12:17:17.432268 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1426 12:17:17.442504 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1427 12:17:17.451929 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1428 12:17:17.461882 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1429 12:17:17.468549 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1430 12:17:17.478628 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1431 12:17:17.488493 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1432 12:17:17.498603 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1433 12:17:17.508116 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1434 12:17:17.518295 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1435 12:17:17.518382 PCI: 00:02.0
1436 12:17:17.531251 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1437 12:17:17.541468 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1438 12:17:17.551246 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1439 12:17:17.554963 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1440 12:17:17.564722 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1441 12:17:17.568035 GENERIC: 0.0
1442 12:17:17.568110 PCI: 00:05.0
1443 12:17:17.578115 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1444 12:17:17.584832 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1445 12:17:17.584910 GENERIC: 0.0
1446 12:17:17.587808 PCI: 00:08.0
1447 12:17:17.597852 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1448 12:17:17.597939 PCI: 00:0a.0
1449 12:17:17.604648 PCI: 00:0d.0 child on link 0 USB0 port 0
1450 12:17:17.614554 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1451 12:17:17.617519 USB0 port 0 child on link 0 USB3 port 0
1452 12:17:17.621040 USB3 port 0
1453 12:17:17.621115 USB3 port 1
1454 12:17:17.624546 USB3 port 2
1455 12:17:17.624620 USB3 port 3
1456 12:17:17.630892 PCI: 00:14.0 child on link 0 USB0 port 0
1457 12:17:17.640939 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1458 12:17:17.644466 USB0 port 0 child on link 0 USB2 port 0
1459 12:17:17.647854 USB2 port 0
1460 12:17:17.647929 USB2 port 1
1461 12:17:17.651288 USB2 port 2
1462 12:17:17.651367 USB2 port 3
1463 12:17:17.654825 USB2 port 4
1464 12:17:17.654899 USB2 port 5
1465 12:17:17.657732 USB2 port 6
1466 12:17:17.657807 USB2 port 7
1467 12:17:17.661350 USB2 port 8
1468 12:17:17.661426 USB2 port 9
1469 12:17:17.664299 USB3 port 0
1470 12:17:17.664375 USB3 port 1
1471 12:17:17.667701 USB3 port 2
1472 12:17:17.667795 USB3 port 3
1473 12:17:17.670788 PCI: 00:14.2
1474 12:17:17.681116 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1475 12:17:17.691213 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1476 12:17:17.697576 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1477 12:17:17.707573 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1478 12:17:17.707660 GENERIC: 0.0
1479 12:17:17.710988 PCI: 00:15.0 child on link 0 I2C: 00:1a
1480 12:17:17.724113 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1481 12:17:17.724200 I2C: 00:1a
1482 12:17:17.727529 I2C: 00:31
1483 12:17:17.727615 I2C: 00:32
1484 12:17:17.730829 PCI: 00:15.1 child on link 0 I2C: 00:10
1485 12:17:17.740709 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1486 12:17:17.743888 I2C: 00:10
1487 12:17:17.743974 PCI: 00:15.2
1488 12:17:17.757172 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1489 12:17:17.757258 PCI: 00:15.3
1490 12:17:17.767075 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1491 12:17:17.770452 PCI: 00:16.0
1492 12:17:17.780344 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1493 12:17:17.780446 PCI: 00:19.0
1494 12:17:17.787363 PCI: 00:19.1 child on link 0 I2C: 00:15
1495 12:17:17.797316 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1496 12:17:17.797404 I2C: 00:15
1497 12:17:17.803773 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1498 12:17:17.810320 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1499 12:17:17.823535 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1500 12:17:17.833483 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1501 12:17:17.836806 GENERIC: 0.0
1502 12:17:17.836892 PCI: 01:00.0
1503 12:17:17.846951 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1504 12:17:17.856903 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1505 12:17:17.870114 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1506 12:17:17.870202 PCI: 00:1e.0
1507 12:17:17.879720 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1508 12:17:17.886707 PCI: 00:1e.2 child on link 0 SPI: 00
1509 12:17:17.896626 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1510 12:17:17.896714 SPI: 00
1511 12:17:17.899536 PCI: 00:1e.3 child on link 0 SPI: 00
1512 12:17:17.909870 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1513 12:17:17.913130 SPI: 00
1514 12:17:17.916656 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1515 12:17:17.926433 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1516 12:17:17.926520 PNP: 0c09.0
1517 12:17:17.936689 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1518 12:17:17.939685 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1519 12:17:17.949856 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1520 12:17:17.959374 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1521 12:17:17.963046 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1522 12:17:17.965800 GENERIC: 0.0
1523 12:17:17.965886 GENERIC: 1.0
1524 12:17:17.969697 PCI: 00:1f.3
1525 12:17:17.979315 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1526 12:17:17.989136 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1527 12:17:17.992712 PCI: 00:1f.5
1528 12:17:18.002318 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1529 12:17:18.005601 CPU_CLUSTER: 0 child on link 0 APIC: 00
1530 12:17:18.005696 APIC: 00
1531 12:17:18.009315 APIC: 01
1532 12:17:18.009392 APIC: 03
1533 12:17:18.012276 APIC: 04
1534 12:17:18.012385 APIC: 07
1535 12:17:18.012465 APIC: 06
1536 12:17:18.015811 APIC: 02
1537 12:17:18.015886 APIC: 05
1538 12:17:18.019530 Done allocating resources.
1539 12:17:18.025821 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1540 12:17:18.032401 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1541 12:17:18.035629 Configure GPIOs for I2S audio on UP4.
1542 12:17:18.042833 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1543 12:17:18.045963 Enabling resources...
1544 12:17:18.048793 PCI: 00:00.0 subsystem <- 8086/9a12
1545 12:17:18.048871 PCI: 00:00.0 cmd <- 06
1546 12:17:18.052367
1547 12:17:18.055650 PCI: 00:02.0 subsystem <- 8086/9a40
1548 12:17:18.055724 PCI: 00:02.0 cmd <- 03
1549 12:17:18.062276 PCI: 00:04.0 subsystem <- 8086/9a03
1550 12:17:18.062351 PCI: 00:04.0 cmd <- 02
1551 12:17:18.065367 PCI: 00:05.0 subsystem <- 8086/9a19
1552 12:17:18.068627 PCI: 00:05.0 cmd <- 02
1553 12:17:18.071804 PCI: 00:08.0 subsystem <- 8086/9a11
1554 12:17:18.075165 PCI: 00:08.0 cmd <- 06
1555 12:17:18.078526 PCI: 00:0d.0 subsystem <- 8086/9a13
1556 12:17:18.081767 PCI: 00:0d.0 cmd <- 02
1557 12:17:18.085355 PCI: 00:14.0 subsystem <- 8086/a0ed
1558 12:17:18.088521 PCI: 00:14.0 cmd <- 02
1559 12:17:18.091776 PCI: 00:14.2 subsystem <- 8086/a0ef
1560 12:17:18.095175 PCI: 00:14.2 cmd <- 02
1561 12:17:18.098502 PCI: 00:14.3 subsystem <- 8086/a0f0
1562 12:17:18.101894 PCI: 00:14.3 cmd <- 02
1563 12:17:18.104948 PCI: 00:15.0 subsystem <- 8086/a0e8
1564 12:17:18.105022 PCI: 00:15.0 cmd <- 02
1565 12:17:18.111549 PCI: 00:15.1 subsystem <- 8086/a0e9
1566 12:17:18.111632 PCI: 00:15.1 cmd <- 02
1567 12:17:18.115003 PCI: 00:15.2 subsystem <- 8086/a0ea
1568 12:17:18.118373 PCI: 00:15.2 cmd <- 02
1569 12:17:18.121663 PCI: 00:15.3 subsystem <- 8086/a0eb
1570 12:17:18.125337 PCI: 00:15.3 cmd <- 02
1571 12:17:18.128206 PCI: 00:16.0 subsystem <- 8086/a0e0
1572 12:17:18.131825 PCI: 00:16.0 cmd <- 02
1573 12:17:18.134899 PCI: 00:19.1 subsystem <- 8086/a0c6
1574 12:17:18.138187 PCI: 00:19.1 cmd <- 02
1575 12:17:18.141369 PCI: 00:1d.0 bridge ctrl <- 0013
1576 12:17:18.144961 PCI: 00:1d.0 subsystem <- 8086/a0b0
1577 12:17:18.147963 PCI: 00:1d.0 cmd <- 06
1578 12:17:18.151405 PCI: 00:1e.0 subsystem <- 8086/a0a8
1579 12:17:18.154668 PCI: 00:1e.0 cmd <- 06
1580 12:17:18.158066 PCI: 00:1e.2 subsystem <- 8086/a0aa
1581 12:17:18.158138 PCI: 00:1e.2 cmd <- 06
1582 12:17:18.164503 PCI: 00:1e.3 subsystem <- 8086/a0ab
1583 12:17:18.164580 PCI: 00:1e.3 cmd <- 02
1584 12:17:18.168012 PCI: 00:1f.0 subsystem <- 8086/a087
1585 12:17:18.171070 PCI: 00:1f.0 cmd <- 407
1586 12:17:18.174578 PCI: 00:1f.3 subsystem <- 8086/a0c8
1587 12:17:18.177766 PCI: 00:1f.3 cmd <- 02
1588 12:17:18.181132 PCI: 00:1f.5 subsystem <- 8086/a0a4
1589 12:17:18.184494 PCI: 00:1f.5 cmd <- 406
1590 12:17:18.188754 PCI: 01:00.0 cmd <- 02
1591 12:17:18.193326 done.
1592 12:17:18.196961 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1593 12:17:18.200240 Initializing devices...
1594 12:17:18.203150 Root Device init
1595 12:17:18.206661 Chrome EC: Set SMI mask to 0x0000000000000000
1596 12:17:18.214264 Chrome EC: clear events_b mask to 0x0000000000000000
1597 12:17:18.220818 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1598 12:17:18.227160 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1599 12:17:18.233698 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1600 12:17:18.237177 Chrome EC: Set WAKE mask to 0x0000000000000000
1601 12:17:18.244748 fw_config match found: DB_USB=USB3_ACTIVE
1602 12:17:18.248101 Configure Right Type-C port orientation for retimer
1603 12:17:18.251559 Root Device init finished in 46 msecs
1604 12:17:18.255747 PCI: 00:00.0 init
1605 12:17:18.258853 CPU TDP = 9 Watts
1606 12:17:18.258928 CPU PL1 = 9 Watts
1607 12:17:18.262428 CPU PL2 = 40 Watts
1608 12:17:18.265686 CPU PL4 = 83 Watts
1609 12:17:18.269334 PCI: 00:00.0 init finished in 8 msecs
1610 12:17:18.269418 PCI: 00:02.0 init
1611 12:17:18.272183 GMA: Found VBT in CBFS
1612 12:17:18.275968 GMA: Found valid VBT in CBFS
1613 12:17:18.282288 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1614 12:17:18.288984 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1615 12:17:18.291926 PCI: 00:02.0 init finished in 18 msecs
1616 12:17:18.295602 PCI: 00:05.0 init
1617 12:17:18.298612 PCI: 00:05.0 init finished in 0 msecs
1618 12:17:18.302273 PCI: 00:08.0 init
1619 12:17:18.305181 PCI: 00:08.0 init finished in 0 msecs
1620 12:17:18.308735 PCI: 00:14.0 init
1621 12:17:18.312201 PCI: 00:14.0 init finished in 0 msecs
1622 12:17:18.315342 PCI: 00:14.2 init
1623 12:17:18.318820 PCI: 00:14.2 init finished in 0 msecs
1624 12:17:18.321962 PCI: 00:15.0 init
1625 12:17:18.322046 I2C bus 0 version 0x3230302a
1626 12:17:18.328567 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1627 12:17:18.332336 PCI: 00:15.0 init finished in 6 msecs
1628 12:17:18.332421 PCI: 00:15.1 init
1629 12:17:18.335706 I2C bus 1 version 0x3230302a
1630 12:17:18.338488 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1631 12:17:18.345070 PCI: 00:15.1 init finished in 6 msecs
1632 12:17:18.345155 PCI: 00:15.2 init
1633 12:17:18.348342 I2C bus 2 version 0x3230302a
1634 12:17:18.351939 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1635 12:17:18.355635 PCI: 00:15.2 init finished in 6 msecs
1636 12:17:18.358361 PCI: 00:15.3 init
1637 12:17:18.361699 I2C bus 3 version 0x3230302a
1638 12:17:18.365069 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1639 12:17:18.368556 PCI: 00:15.3 init finished in 6 msecs
1640 12:17:18.372148 PCI: 00:16.0 init
1641 12:17:18.375080 PCI: 00:16.0 init finished in 0 msecs
1642 12:17:18.378483 PCI: 00:19.1 init
1643 12:17:18.381779 I2C bus 5 version 0x3230302a
1644 12:17:18.384873 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1645 12:17:18.388427 PCI: 00:19.1 init finished in 6 msecs
1646 12:17:18.391487 PCI: 00:1d.0 init
1647 12:17:18.391572 Initializing PCH PCIe bridge.
1648 12:17:18.398226 PCI: 00:1d.0 init finished in 3 msecs
1649 12:17:18.401688 PCI: 00:1f.0 init
1650 12:17:18.404925 IOAPIC: Initializing IOAPIC at 0xfec00000
1651 12:17:18.407945 IOAPIC: Bootstrap Processor Local APIC = 0x00
1652 12:17:18.411713 IOAPIC: ID = 0x02
1653 12:17:18.414601 IOAPIC: Dumping registers
1654 12:17:18.414685 reg 0x0000: 0x02000000
1655 12:17:18.418350 reg 0x0001: 0x00770020
1656 12:17:18.421703 reg 0x0002: 0x00000000
1657 12:17:18.424602 PCI: 00:1f.0 init finished in 21 msecs
1658 12:17:18.428210 PCI: 00:1f.2 init
1659 12:17:18.431495 Disabling ACPI via APMC.
1660 12:17:18.435067 APMC done.
1661 12:17:18.438060 PCI: 00:1f.2 init finished in 6 msecs
1662 12:17:18.449454 PCI: 01:00.0 init
1663 12:17:18.452449 PCI: 01:00.0 init finished in 0 msecs
1664 12:17:18.456018 PNP: 0c09.0 init
1665 12:17:18.459110 Google Chrome EC uptime: 8.483 seconds
1666 12:17:18.465641 Google Chrome AP resets since EC boot: 0
1667 12:17:18.469254 Google Chrome most recent AP reset causes:
1668 12:17:18.476114 Google Chrome EC reset flags at last EC boot: reset-pin
1669 12:17:18.478807 PNP: 0c09.0 init finished in 18 msecs
1670 12:17:18.483849 Devices initialized
1671 12:17:18.487071 Show all devs... After init.
1672 12:17:18.490198 Root Device: enabled 1
1673 12:17:18.490283 DOMAIN: 0000: enabled 1
1674 12:17:18.493556 CPU_CLUSTER: 0: enabled 1
1675 12:17:18.497270 PCI: 00:00.0: enabled 1
1676 12:17:18.500294 PCI: 00:02.0: enabled 1
1677 12:17:18.500416 PCI: 00:04.0: enabled 1
1678 12:17:18.503907 PCI: 00:05.0: enabled 1
1679 12:17:18.507334 PCI: 00:06.0: enabled 0
1680 12:17:18.510391 PCI: 00:07.0: enabled 0
1681 12:17:18.510474 PCI: 00:07.1: enabled 0
1682 12:17:18.513827 PCI: 00:07.2: enabled 0
1683 12:17:18.517363 PCI: 00:07.3: enabled 0
1684 12:17:18.520188 PCI: 00:08.0: enabled 1
1685 12:17:18.520273 PCI: 00:09.0: enabled 0
1686 12:17:18.523690 PCI: 00:0a.0: enabled 0
1687 12:17:18.527278 PCI: 00:0d.0: enabled 1
1688 12:17:18.527362 PCI: 00:0d.1: enabled 0
1689 12:17:18.530226
1690 12:17:18.530310 PCI: 00:0d.2: enabled 0
1691 12:17:18.533676 PCI: 00:0d.3: enabled 0
1692 12:17:18.536996 PCI: 00:0e.0: enabled 0
1693 12:17:18.537080 PCI: 00:10.2: enabled 1
1694 12:17:18.540494 PCI: 00:10.6: enabled 0
1695 12:17:18.543700 PCI: 00:10.7: enabled 0
1696 12:17:18.546808 PCI: 00:12.0: enabled 0
1697 12:17:18.546893 PCI: 00:12.6: enabled 0
1698 12:17:18.550245 PCI: 00:13.0: enabled 0
1699 12:17:18.553510 PCI: 00:14.0: enabled 1
1700 12:17:18.556767 PCI: 00:14.1: enabled 0
1701 12:17:18.556851 PCI: 00:14.2: enabled 1
1702 12:17:18.560079 PCI: 00:14.3: enabled 1
1703 12:17:18.563463 PCI: 00:15.0: enabled 1
1704 12:17:18.566889 PCI: 00:15.1: enabled 1
1705 12:17:18.566972 PCI: 00:15.2: enabled 1
1706 12:17:18.570173 PCI: 00:15.3: enabled 1
1707 12:17:18.573532 PCI: 00:16.0: enabled 1
1708 12:17:18.573616 PCI: 00:16.1: enabled 0
1709 12:17:18.576768 PCI: 00:16.2: enabled 0
1710 12:17:18.579899 PCI: 00:16.3: enabled 0
1711 12:17:18.583545 PCI: 00:16.4: enabled 0
1712 12:17:18.583629 PCI: 00:16.5: enabled 0
1713 12:17:18.586902 PCI: 00:17.0: enabled 0
1714 12:17:18.590158 PCI: 00:19.0: enabled 0
1715 12:17:18.593647 PCI: 00:19.1: enabled 1
1716 12:17:18.593730 PCI: 00:19.2: enabled 0
1717 12:17:18.596784 PCI: 00:1c.0: enabled 1
1718 12:17:18.600445 PCI: 00:1c.1: enabled 0
1719 12:17:18.603189 PCI: 00:1c.2: enabled 0
1720 12:17:18.603272 PCI: 00:1c.3: enabled 0
1721 12:17:18.606779 PCI: 00:1c.4: enabled 0
1722 12:17:18.610514 PCI: 00:1c.5: enabled 0
1723 12:17:18.610598 PCI: 00:1c.6: enabled 1
1724 12:17:18.613148
1725 12:17:18.613233 PCI: 00:1c.7: enabled 0
1726 12:17:18.616557 PCI: 00:1d.0: enabled 1
1727 12:17:18.619812 PCI: 00:1d.1: enabled 0
1728 12:17:18.619896 PCI: 00:1d.2: enabled 1
1729 12:17:18.623521 PCI: 00:1d.3: enabled 0
1730 12:17:18.626789 PCI: 00:1e.0: enabled 1
1731 12:17:18.629970 PCI: 00:1e.1: enabled 0
1732 12:17:18.630071 PCI: 00:1e.2: enabled 1
1733 12:17:18.633158 PCI: 00:1e.3: enabled 1
1734 12:17:18.636538 PCI: 00:1f.0: enabled 1
1735 12:17:18.639993 PCI: 00:1f.1: enabled 0
1736 12:17:18.640075 PCI: 00:1f.2: enabled 1
1737 12:17:18.643182 PCI: 00:1f.3: enabled 1
1738 12:17:18.646549 PCI: 00:1f.4: enabled 0
1739 12:17:18.650097 PCI: 00:1f.5: enabled 1
1740 12:17:18.650180 PCI: 00:1f.6: enabled 0
1741 12:17:18.653234 PCI: 00:1f.7: enabled 0
1742 12:17:18.656460 APIC: 00: enabled 1
1743 12:17:18.656544 GENERIC: 0.0: enabled 1
1744 12:17:18.659939 GENERIC: 0.0: enabled 1
1745 12:17:18.663088 GENERIC: 1.0: enabled 1
1746 12:17:18.666748 GENERIC: 0.0: enabled 1
1747 12:17:18.666831 GENERIC: 1.0: enabled 1
1748 12:17:18.669946 USB0 port 0: enabled 1
1749 12:17:18.673200 GENERIC: 0.0: enabled 1
1750 12:17:18.673282 USB0 port 0: enabled 1
1751 12:17:18.676753 GENERIC: 0.0: enabled 1
1752 12:17:18.679823 I2C: 00:1a: enabled 1
1753 12:17:18.683053 I2C: 00:31: enabled 1
1754 12:17:18.683136 I2C: 00:32: enabled 1
1755 12:17:18.686182 I2C: 00:10: enabled 1
1756 12:17:18.689686 I2C: 00:15: enabled 1
1757 12:17:18.689770 GENERIC: 0.0: enabled 0
1758 12:17:18.692990 GENERIC: 1.0: enabled 0
1759 12:17:18.696121 GENERIC: 0.0: enabled 1
1760 12:17:18.696203 SPI: 00: enabled 1
1761 12:17:18.699520 SPI: 00: enabled 1
1762 12:17:18.702794 PNP: 0c09.0: enabled 1
1763 12:17:18.702876 GENERIC: 0.0: enabled 1
1764 12:17:18.706489 USB3 port 0: enabled 1
1765 12:17:18.709711 USB3 port 1: enabled 1
1766 12:17:18.709793 USB3 port 2: enabled 0
1767 12:17:18.713156
1768 12:17:18.713239 USB3 port 3: enabled 0
1769 12:17:18.716650 USB2 port 0: enabled 0
1770 12:17:18.719563 USB2 port 1: enabled 1
1771 12:17:18.719646 USB2 port 2: enabled 1
1772 12:17:18.722623 USB2 port 3: enabled 0
1773 12:17:18.726164 USB2 port 4: enabled 1
1774 12:17:18.726247 USB2 port 5: enabled 0
1775 12:17:18.729672 USB2 port 6: enabled 0
1776 12:17:18.732965 USB2 port 7: enabled 0
1777 12:17:18.736525 USB2 port 8: enabled 0
1778 12:17:18.736607 USB2 port 9: enabled 0
1779 12:17:18.739902 USB3 port 0: enabled 0
1780 12:17:18.742823 USB3 port 1: enabled 1
1781 12:17:18.742905 USB3 port 2: enabled 0
1782 12:17:18.746237 USB3 port 3: enabled 0
1783 12:17:18.749192 GENERIC: 0.0: enabled 1
1784 12:17:18.752482 GENERIC: 1.0: enabled 1
1785 12:17:18.752564 APIC: 01: enabled 1
1786 12:17:18.755829 APIC: 03: enabled 1
1787 12:17:18.755911 APIC: 04: enabled 1
1788 12:17:18.759305 APIC: 07: enabled 1
1789 12:17:18.762701 APIC: 06: enabled 1
1790 12:17:18.762784 APIC: 02: enabled 1
1791 12:17:18.765937 APIC: 05: enabled 1
1792 12:17:18.769675 PCI: 01:00.0: enabled 1
1793 12:17:18.772700 BS: BS_DEV_INIT run times (exec / console): 34 / 536 ms
1794 12:17:18.779282 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1795 12:17:18.782735 ELOG: NV offset 0xf30000 size 0x1000
1796 12:17:18.789082 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1797 12:17:18.795442 ELOG: Event(17) added with size 13 at 2023-01-31 12:17:18 UTC
1798 12:17:18.802099 ELOG: Event(92) added with size 9 at 2023-01-31 12:17:18 UTC
1799 12:17:18.809077 ELOG: Event(93) added with size 9 at 2023-01-31 12:17:18 UTC
1800 12:17:18.815532 ELOG: Event(9E) added with size 10 at 2023-01-31 12:17:18 UTC
1801 12:17:18.822245 ELOG: Event(9F) added with size 14 at 2023-01-31 12:17:18 UTC
1802 12:17:18.828782 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1803 12:17:18.832064 ELOG: Event(A1) added with size 10 at 2023-01-31 12:17:18 UTC
1804 12:17:18.835738
1805 12:17:18.841811 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1806 12:17:18.848444 ELOG: Event(A0) added with size 9 at 2023-01-31 12:17:18 UTC
1807 12:17:18.852035 elog_add_boot_reason: Logged dev mode boot
1808 12:17:18.858814 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1809 12:17:18.858918 Finalize devices...
1810 12:17:18.861816 Devices finalized
1811 12:17:18.868690 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1812 12:17:18.872125 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1813 12:17:18.878559 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1814 12:17:18.881947 ME: HFSTS1 : 0x80030055
1815 12:17:18.888450 ME: HFSTS2 : 0x30280116
1816 12:17:18.891417 ME: HFSTS3 : 0x00000050
1817 12:17:18.894960 ME: HFSTS4 : 0x00004000
1818 12:17:18.901634 ME: HFSTS5 : 0x00000000
1819 12:17:18.904776 ME: HFSTS6 : 0x00400006
1820 12:17:18.908185 ME: Manufacturing Mode : YES
1821 12:17:18.911677 ME: SPI Protection Mode Enabled : NO
1822 12:17:18.915188 ME: FW Partition Table : OK
1823 12:17:18.921325 ME: Bringup Loader Failure : NO
1824 12:17:18.924670 ME: Firmware Init Complete : NO
1825 12:17:18.928256 ME: Boot Options Present : NO
1826 12:17:18.931241 ME: Update In Progress : NO
1827 12:17:18.934663 ME: D0i3 Support : YES
1828 12:17:18.938105 ME: Low Power State Enabled : NO
1829 12:17:18.941664 ME: CPU Replaced : YES
1830 12:17:18.944912 ME: CPU Replacement Valid : YES
1831 12:17:18.948074
1832 12:17:18.951389 ME: Current Working State : 5
1833 12:17:18.954726 ME: Current Operation State : 1
1834 12:17:18.958141 ME: Current Operation Mode : 3
1835 12:17:18.961246 ME: Error Code : 0
1836 12:17:18.964634 ME: Enhanced Debug Mode : NO
1837 12:17:18.968151 ME: CPU Debug Disabled : YES
1838 12:17:18.971031 ME: TXT Support : NO
1839 12:17:18.977990 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1840 12:17:18.984480 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1841 12:17:18.987881 CBFS: 'fallback/slic' not found.
1842 12:17:18.994310 ACPI: Writing ACPI tables at 76b01000.
1843 12:17:18.994396 ACPI: * FACS
1844 12:17:18.997596 ACPI: * DSDT
1845 12:17:19.001122 Ramoops buffer: 0x100000@0x76a00000.
1846 12:17:19.004268 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1847 12:17:19.011114 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1848 12:17:19.014166 Google Chrome EC: version:
1849 12:17:19.017657 ro: voema_v2.0.10114-a447f03e46
1850 12:17:19.020522 rw: voema_v2.0.10114-a447f03e46
1851 12:17:19.020608 running image: 1
1852 12:17:19.027327 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1853 12:17:19.031718 ACPI: * FADT
1854 12:17:19.031804 SCI is IRQ9
1855 12:17:19.035337 ACPI: added table 1/32, length now 40
1856 12:17:19.038672
1857 12:17:19.038759 ACPI: * SSDT
1858 12:17:19.041537 Found 1 CPU(s) with 8 core(s) each.
1859 12:17:19.048680 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1860 12:17:19.051831 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1861 12:17:19.055225 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1862 12:17:19.058147 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1863 12:17:19.064798 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1864 12:17:19.071480 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1865 12:17:19.075192 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1866 12:17:19.081487 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1867 12:17:19.088551 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1868 12:17:19.091817 \_SB.PCI0.RP09: Added StorageD3Enable property
1869 12:17:19.094975 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1870 12:17:19.101193 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1871 12:17:19.108197 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1872 12:17:19.111693 PS2K: Passing 80 keymaps to kernel
1873 12:17:19.118128 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1874 12:17:19.124792 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1875 12:17:19.131565 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1876 12:17:19.137843 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1877 12:17:19.144650 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1878 12:17:19.151068 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1879 12:17:19.157881 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1880 12:17:19.164501 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1881 12:17:19.168026 ACPI: added table 2/32, length now 44
1882 12:17:19.170928 ACPI: * MCFG
1883 12:17:19.174921 ACPI: added table 3/32, length now 48
1884 12:17:19.174998 ACPI: * TPM2
1885 12:17:19.178186 TPM2 log created at 0x769f0000
1886 12:17:19.180803 ACPI: added table 4/32, length now 52
1887 12:17:19.184143 ACPI: * MADT
1888 12:17:19.184221 SCI is IRQ9
1889 12:17:19.187873 ACPI: added table 5/32, length now 56
1890 12:17:19.191109 current = 76b09850
1891 12:17:19.191190 ACPI: * DMAR
1892 12:17:19.197452 ACPI: added table 6/32, length now 60
1893 12:17:19.200817 ACPI: added table 7/32, length now 64
1894 12:17:19.200898 ACPI: * HPET
1895 12:17:19.204169 ACPI: added table 8/32, length now 68
1896 12:17:19.207470 ACPI: done.
1897 12:17:19.207548 ACPI tables: 35216 bytes.
1898 12:17:19.211002
1899 12:17:19.211086 smbios_write_tables: 769ef000
1900 12:17:19.215839 EC returned error result code 3
1901 12:17:19.219168 Couldn't obtain OEM name from CBI
1902 12:17:19.223061 Create SMBIOS type 16
1903 12:17:19.225998 Create SMBIOS type 17
1904 12:17:19.229307 GENERIC: 0.0 (WIFI Device)
1905 12:17:19.229385 SMBIOS tables: 1750 bytes.
1906 12:17:19.232742
1907 12:17:19.236262 Writing table forward entry at 0x00000500
1908 12:17:19.242945 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1909 12:17:19.246207 Writing coreboot table at 0x76b25000
1910 12:17:19.252490 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1911 12:17:19.256194 1. 0000000000001000-000000000009ffff: RAM
1912 12:17:19.259448 2. 00000000000a0000-00000000000fffff: RESERVED
1913 12:17:19.266020 3. 0000000000100000-00000000769eefff: RAM
1914 12:17:19.269024 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1915 12:17:19.276836 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1916 12:17:19.282679 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1917 12:17:19.285509 7. 0000000077000000-000000007fbfffff: RESERVED
1918 12:17:19.292504 8. 00000000c0000000-00000000cfffffff: RESERVED
1919 12:17:19.295826 9. 00000000f8000000-00000000f9ffffff: RESERVED
1920 12:17:19.298897 10. 00000000fb000000-00000000fb000fff: RESERVED
1921 12:17:19.305595 11. 00000000fe000000-00000000fe00ffff: RESERVED
1922 12:17:19.308623 12. 00000000fed80000-00000000fed87fff: RESERVED
1923 12:17:19.315625 13. 00000000fed90000-00000000fed92fff: RESERVED
1924 12:17:19.318743 14. 00000000feda0000-00000000feda1fff: RESERVED
1925 12:17:19.325411 15. 00000000fedc0000-00000000feddffff: RESERVED
1926 12:17:19.328759 16. 0000000100000000-00000002803fffff: RAM
1927 12:17:19.332164 Passing 4 GPIOs to payload:
1928 12:17:19.335215 NAME | PORT | POLARITY | VALUE
1929 12:17:19.341752 lid | undefined | high | high
1930 12:17:19.348296 power | undefined | high | low
1931 12:17:19.352096 oprom | undefined | high | low
1932 12:17:19.358922 EC in RW | 0x000000e5 | high | low
1933 12:17:19.365326 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 162e
1934 12:17:19.368481 coreboot table: 1576 bytes.
1935 12:17:19.371656 IMD ROOT 0. 0x76fff000 0x00001000
1936 12:17:19.375279 IMD SMALL 1. 0x76ffe000 0x00001000
1937 12:17:19.378266 FSP MEMORY 2. 0x76c4e000 0x003b0000
1938 12:17:19.382152 VPD 3. 0x76c4d000 0x00000367
1939 12:17:19.385141 RO MCACHE 4. 0x76c4c000 0x00000fdc
1940 12:17:19.388464 CONSOLE 5. 0x76c2c000 0x00020000
1941 12:17:19.391859 FMAP 6. 0x76c2b000 0x00000578
1942 12:17:19.398295 TIME STAMP 7. 0x76c2a000 0x00000910
1943 12:17:19.401633 VBOOT WORK 8. 0x76c16000 0x00014000
1944 12:17:19.404959 ROMSTG STCK 9. 0x76c15000 0x00001000
1945 12:17:19.408420 AFTER CAR 10. 0x76c0a000 0x0000b000
1946 12:17:19.411769 RAMSTAGE 11. 0x76b97000 0x00073000
1947 12:17:19.414995 REFCODE 12. 0x76b42000 0x00055000
1948 12:17:19.418354 SMM BACKUP 13. 0x76b32000 0x00010000
1949 12:17:19.421949 4f444749 14. 0x76b30000 0x00002000
1950 12:17:19.425299 EXT VBT15. 0x76b2d000 0x0000219f
1951 12:17:19.431561 COREBOOT 16. 0x76b25000 0x00008000
1952 12:17:19.434960 ACPI 17. 0x76b01000 0x00024000
1953 12:17:19.438231 ACPI GNVS 18. 0x76b00000 0x00001000
1954 12:17:19.441642 RAMOOPS 19. 0x76a00000 0x00100000
1955 12:17:19.445127 TPM2 TCGLOG20. 0x769f0000 0x00010000
1956 12:17:19.448333 SMBIOS 21. 0x769ef000 0x00000800
1957 12:17:19.451835 IMD small region:
1958 12:17:19.454766 IMD ROOT 0. 0x76ffec00 0x00000400
1959 12:17:19.458236 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1960 12:17:19.461407 POWER STATE 2. 0x76ffeb80 0x00000044
1961 12:17:19.464797 ROMSTAGE 3. 0x76ffeb60 0x00000004
1962 12:17:19.471547 MEM INFO 4. 0x76ffe980 0x000001e0
1963 12:17:19.474836 BS: BS_WRITE_TABLES run times (exec / console): 8 / 484 ms
1964 12:17:19.478000 MTRR: Physical address space:
1965 12:17:19.484734 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1966 12:17:19.491401 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1967 12:17:19.498123 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1968 12:17:19.504821 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1969 12:17:19.511157 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1970 12:17:19.518265 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1971 12:17:19.521309 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1972 12:17:19.527910 MTRR: Fixed MSR 0x250 0x0606060606060606
1973 12:17:19.531422 MTRR: Fixed MSR 0x258 0x0606060606060606
1974 12:17:19.534559 MTRR: Fixed MSR 0x259 0x0000000000000000
1975 12:17:19.537692 MTRR: Fixed MSR 0x268 0x0606060606060606
1976 12:17:19.544437 MTRR: Fixed MSR 0x269 0x0606060606060606
1977 12:17:19.547495 MTRR: Fixed MSR 0x26a 0x0606060606060606
1978 12:17:19.550938 MTRR: Fixed MSR 0x26b 0x0606060606060606
1979 12:17:19.554553 MTRR: Fixed MSR 0x26c 0x0606060606060606
1980 12:17:19.561022 MTRR: Fixed MSR 0x26d 0x0606060606060606
1981 12:17:19.564053 MTRR: Fixed MSR 0x26e 0x0606060606060606
1982 12:17:19.567453 MTRR: Fixed MSR 0x26f 0x0606060606060606
1983 12:17:19.571120 call enable_fixed_mtrr()
1984 12:17:19.574178 CPU physical address size: 39 bits
1985 12:17:19.580861 MTRR: default type WB/UC MTRR counts: 6/6.
1986 12:17:19.584391 MTRR: UC selected as default type.
1987 12:17:19.590859 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1988 12:17:19.594183 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1989 12:17:19.600603 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1990 12:17:19.607602 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1991 12:17:19.613998 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1992 12:17:19.620545 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1993 12:17:19.620667
1994 12:17:19.623934 MTRR check
1995 12:17:19.624019 Fixed MTRRs : Enabled
1996 12:17:19.627435 Variable MTRRs: Enabled
1997 12:17:19.627522
1998 12:17:19.630643 MTRR: Fixed MSR 0x250 0x0606060606060606
1999 12:17:19.634004
2000 12:17:19.637290 MTRR: Fixed MSR 0x258 0x0606060606060606
2001 12:17:19.640687 MTRR: Fixed MSR 0x259 0x0000000000000000
2002 12:17:19.644193 MTRR: Fixed MSR 0x268 0x0606060606060606
2003 12:17:19.647434 MTRR: Fixed MSR 0x269 0x0606060606060606
2004 12:17:19.653721 MTRR: Fixed MSR 0x26a 0x0606060606060606
2005 12:17:19.657326 MTRR: Fixed MSR 0x26b 0x0606060606060606
2006 12:17:19.660556 MTRR: Fixed MSR 0x26c 0x0606060606060606
2007 12:17:19.664140 MTRR: Fixed MSR 0x26d 0x0606060606060606
2008 12:17:19.670607 MTRR: Fixed MSR 0x26e 0x0606060606060606
2009 12:17:19.673736 MTRR: Fixed MSR 0x26f 0x0606060606060606
2010 12:17:19.680398 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
2011 12:17:19.683476 call enable_fixed_mtrr()
2012 12:17:19.686809 Checking cr50 for pending updates
2013 12:17:19.690696 CPU physical address size: 39 bits
2014 12:17:19.694386 MTRR: Fixed MSR 0x250 0x0606060606060606
2015 12:17:19.697794 MTRR: Fixed MSR 0x250 0x0606060606060606
2016 12:17:19.700942 MTRR: Fixed MSR 0x258 0x0606060606060606
2017 12:17:19.707596 MTRR: Fixed MSR 0x259 0x0000000000000000
2018 12:17:19.710999 MTRR: Fixed MSR 0x268 0x0606060606060606
2019 12:17:19.713900 MTRR: Fixed MSR 0x269 0x0606060606060606
2020 12:17:19.717409 MTRR: Fixed MSR 0x26a 0x0606060606060606
2021 12:17:19.723978 MTRR: Fixed MSR 0x26b 0x0606060606060606
2022 12:17:19.727464 MTRR: Fixed MSR 0x26c 0x0606060606060606
2023 12:17:19.730515 MTRR: Fixed MSR 0x26d 0x0606060606060606
2024 12:17:19.734079 MTRR: Fixed MSR 0x26e 0x0606060606060606
2025 12:17:19.737462 MTRR: Fixed MSR 0x26f 0x0606060606060606
2026 12:17:19.740768
2027 12:17:19.744005 MTRR: Fixed MSR 0x258 0x0606060606060606
2028 12:17:19.747348 call enable_fixed_mtrr()
2029 12:17:19.750858 MTRR: Fixed MSR 0x259 0x0000000000000000
2030 12:17:19.754058 MTRR: Fixed MSR 0x268 0x0606060606060606
2031 12:17:19.760668 MTRR: Fixed MSR 0x269 0x0606060606060606
2032 12:17:19.763518 MTRR: Fixed MSR 0x26a 0x0606060606060606
2033 12:17:19.766879 MTRR: Fixed MSR 0x26b 0x0606060606060606
2034 12:17:19.770361 MTRR: Fixed MSR 0x26c 0x0606060606060606
2035 12:17:19.773946 MTRR: Fixed MSR 0x26d 0x0606060606060606
2036 12:17:19.780459 MTRR: Fixed MSR 0x26e 0x0606060606060606
2037 12:17:19.783812 MTRR: Fixed MSR 0x26f 0x0606060606060606
2038 12:17:19.786750 CPU physical address size: 39 bits
2039 12:17:19.790924 call enable_fixed_mtrr()
2040 12:17:19.794524 MTRR: Fixed MSR 0x250 0x0606060606060606
2041 12:17:19.801397 MTRR: Fixed MSR 0x250 0x0606060606060606
2042 12:17:19.804779 MTRR: Fixed MSR 0x258 0x0606060606060606
2043 12:17:19.808015 MTRR: Fixed MSR 0x259 0x0000000000000000
2044 12:17:19.811355 MTRR: Fixed MSR 0x268 0x0606060606060606
2045 12:17:19.818075 MTRR: Fixed MSR 0x269 0x0606060606060606
2046 12:17:19.821118 MTRR: Fixed MSR 0x26a 0x0606060606060606
2047 12:17:19.824565 MTRR: Fixed MSR 0x26b 0x0606060606060606
2048 12:17:19.827486 MTRR: Fixed MSR 0x26c 0x0606060606060606
2049 12:17:19.834279 MTRR: Fixed MSR 0x26d 0x0606060606060606
2050 12:17:19.837972 MTRR: Fixed MSR 0x26e 0x0606060606060606
2051 12:17:19.840744 MTRR: Fixed MSR 0x26f 0x0606060606060606
2052 12:17:19.847537 MTRR: Fixed MSR 0x258 0x0606060606060606
2053 12:17:19.851044 MTRR: Fixed MSR 0x259 0x0000000000000000
2054 12:17:19.854040 MTRR: Fixed MSR 0x268 0x0606060606060606
2055 12:17:19.857620 MTRR: Fixed MSR 0x269 0x0606060606060606
2056 12:17:19.860861 MTRR: Fixed MSR 0x26a 0x0606060606060606
2057 12:17:19.863895
2058 12:17:19.867620 MTRR: Fixed MSR 0x26b 0x0606060606060606
2059 12:17:19.870690 MTRR: Fixed MSR 0x26c 0x0606060606060606
2060 12:17:19.874215 MTRR: Fixed MSR 0x26d 0x0606060606060606
2061 12:17:19.877053 MTRR: Fixed MSR 0x26e 0x0606060606060606
2062 12:17:19.883848 MTRR: Fixed MSR 0x26f 0x0606060606060606
2063 12:17:19.887206 call enable_fixed_mtrr()
2064 12:17:19.890607 call enable_fixed_mtrr()
2065 12:17:19.894422 CPU physical address size: 39 bits
2066 12:17:19.894526 Reading cr50 TPM mode
2067 12:17:19.898047 MTRR: Fixed MSR 0x250 0x0606060606060606
2068 12:17:19.904391 MTRR: Fixed MSR 0x250 0x0606060606060606
2069 12:17:19.908005 MTRR: Fixed MSR 0x258 0x0606060606060606
2070 12:17:19.910970 MTRR: Fixed MSR 0x259 0x0000000000000000
2071 12:17:19.914403 MTRR: Fixed MSR 0x268 0x0606060606060606
2072 12:17:19.917645 MTRR: Fixed MSR 0x269 0x0606060606060606
2073 12:17:19.924206 MTRR: Fixed MSR 0x26a 0x0606060606060606
2074 12:17:19.927460 MTRR: Fixed MSR 0x26b 0x0606060606060606
2075 12:17:19.931056 MTRR: Fixed MSR 0x26c 0x0606060606060606
2076 12:17:19.934315 MTRR: Fixed MSR 0x26d 0x0606060606060606
2077 12:17:19.940719 MTRR: Fixed MSR 0x26e 0x0606060606060606
2078 12:17:19.944115 MTRR: Fixed MSR 0x26f 0x0606060606060606
2079 12:17:19.947627 MTRR: Fixed MSR 0x258 0x0606060606060606
2080 12:17:19.951076 call enable_fixed_mtrr()
2081 12:17:19.954510 MTRR: Fixed MSR 0x259 0x0000000000000000
2082 12:17:19.961019 MTRR: Fixed MSR 0x268 0x0606060606060606
2083 12:17:19.964851 MTRR: Fixed MSR 0x269 0x0606060606060606
2084 12:17:19.967403 MTRR: Fixed MSR 0x26a 0x0606060606060606
2085 12:17:19.970898 MTRR: Fixed MSR 0x26b 0x0606060606060606
2086 12:17:19.977266 MTRR: Fixed MSR 0x26c 0x0606060606060606
2087 12:17:19.980817 MTRR: Fixed MSR 0x26d 0x0606060606060606
2088 12:17:19.984241 MTRR: Fixed MSR 0x26e 0x0606060606060606
2089 12:17:19.987546 MTRR: Fixed MSR 0x26f 0x0606060606060606
2090 12:17:19.991311 CPU physical address size: 39 bits
2091 12:17:19.998021 call enable_fixed_mtrr()
2092 12:17:20.001465 BS: BS_PAYLOAD_LOAD entry times (exec / console): 213 / 6 ms
2093 12:17:20.004827 CPU physical address size: 39 bits
2094 12:17:20.011242 CPU physical address size: 39 bits
2095 12:17:20.014502 CPU physical address size: 39 bits
2096 12:17:20.021298 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2097 12:17:20.027955 Checking segment from ROM address 0xffc02b38
2098 12:17:20.031197 Checking segment from ROM address 0xffc02b54
2099 12:17:20.034752 Loading segment from ROM address 0xffc02b38
2100 12:17:20.037747 code (compression=0)
2101 12:17:20.044610 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2102 12:17:20.047938
2103 12:17:20.055147 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2104 12:17:20.057441 it's not compressed!
2105 12:17:20.195883 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2106 12:17:20.202576 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2107 12:17:20.209154 Loading segment from ROM address 0xffc02b54
2108 12:17:20.209254 Entry Point 0x30000000
2109 12:17:20.212253 Loaded segments
2110 12:17:20.218908 BS: BS_PAYLOAD_LOAD run times (exec / console): 147 / 63 ms
2111 12:17:20.261881 Finalizing chipset.
2112 12:17:20.265364 Finalizing SMM.
2113 12:17:20.265461 APMC done.
2114 12:17:20.271824 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2115 12:17:20.275150 mp_park_aps done after 0 msecs.
2116 12:17:20.278605 Jumping to boot code at 0x30000000(0x76b25000)
2117 12:17:20.288411 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2118 12:17:20.288500
2119 12:17:20.288585
2120 12:17:20.288648
2121 12:17:20.291985 Starting depthcharge on Voema...
2122 12:17:20.292072
2123 12:17:20.292491 end: 2.2.3 depthcharge-start (duration 00:00:16) [common]
2124 12:17:20.292606 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2125 12:17:20.292717 Setting prompt string to ['volteer:']
2126 12:17:20.292816 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:44)
2127 12:17:20.301484 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2128 12:17:20.301580
2129 12:17:20.308116 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2130 12:17:20.308200
2131 12:17:20.314836 Looking for NVMe Controller 0x3005f238 @ 00:1d:00
2132 12:17:20.314918
2133 12:17:20.318106 Failed to find eMMC card reader
2134 12:17:20.318197
2135 12:17:20.318264 Wipe memory regions:
2136 12:17:20.318340
2137 12:17:20.324832 [0x00000000001000, 0x000000000a0000)
2138 12:17:20.324915
2139 12:17:20.328384 [0x00000000100000, 0x00000030000000)
2140 12:17:20.328481
2141 12:17:20.357462 [0x00000032662db0, 0x000000769ef000)
2142 12:17:20.357555
2143 12:17:20.396793 [0x00000100000000, 0x00000280400000)
2144 12:17:20.396890
2145 12:17:20.601716 ec_init: CrosEC protocol v3 supported (256, 256)
2146 12:17:20.601858
2147 12:17:21.032082 R8152: Initializing
2148 12:17:21.032234
2149 12:17:21.035494 Version 6 (ocp_data = 5c30)
2150 12:17:21.035574
2151 12:17:21.038967 R8152: Done initializing
2152 12:17:21.039042
2153 12:17:21.042200 Adding net device
2154 12:17:21.042273
2155 12:17:21.346555 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2156 12:17:21.346688
2157 12:17:21.346764
2158 12:17:21.346829
2159 12:17:21.350040 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2161 12:17:21.450630 volteer: tftpboot 192.168.201.1 8948145/tftp-deploy-m3zcztrl/kernel/bzImage 8948145/tftp-deploy-m3zcztrl/kernel/cmdline 8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
2162 12:17:21.450768 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2163 12:17:21.450890 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:42)
2164 12:17:21.455538 tftpboot 192.168.201.1 8948145/tftp-deploy-m3zcztrl/kernel/bzImoy-m3zcztrl/kernel/cmdline 8948145/tftp-deploy-m3zcztrl/ramdisk/ramdisk.cpio.gz
2165 12:17:21.455658
2166 12:17:21.455727 Waiting for link
2167 12:17:21.455791
2168 12:17:21.657927 done.
2169 12:17:21.658057
2170 12:17:21.658128 MAC: 00:24:32:30:77:76
2171 12:17:21.658197
2172 12:17:21.661366 Sending DHCP discover... done.
2173 12:17:21.661442
2174 12:17:21.664790 Waiting for reply... done.
2175 12:17:21.664862
2176 12:17:21.668234 Sending DHCP request... done.
2177 12:17:21.668321
2178 12:17:21.671405 Waiting for reply... done.
2179 12:17:21.671482
2180 12:17:21.674679 My ip is 192.168.201.16
2181 12:17:21.674757
2182 12:17:21.678200 The DHCP server ip is 192.168.201.1
2183 12:17:21.678274
2184 12:17:21.684929 TFTP server IP predefined by user: 192.168.201.1
2185 12:17:21.685007
2186 12:17:21.691002 Bootfile predefined by user: 8948145/tftp-deploy-m3zcztrl/kernel/bzImage
2187 12:17:21.691087
2188 12:17:21.694340 Sending tftp read request... done.
2189 12:17:21.694419
2190 12:17:21.697744 Waiting for the transfer...
2191 12:17:21.697821
2192 12:17:22.221061 00000000 ################################################################
2193 12:17:22.221197
2194 12:17:22.731555 00080000 ################################################################
2195 12:17:22.731696
2196 12:17:23.244257 00100000 ################################################################
2197 12:17:23.244404
2198 12:17:23.754519 00180000 ################################################################
2199 12:17:23.754678
2200 12:17:24.264525 00200000 ################################################################
2201 12:17:24.264676
2202 12:17:24.773522 00280000 ################################################################
2203 12:17:24.773668
2204 12:17:25.285222 00300000 ################################################################
2205 12:17:25.285362
2206 12:17:25.796148 00380000 ################################################################
2207 12:17:25.796290
2208 12:17:26.318388 00400000 ################################################################
2209 12:17:26.318541
2210 12:17:26.865953 00480000 ################################################################
2211 12:17:26.866094
2212 12:17:27.423279 00500000 ################################################################
2213 12:17:27.423416
2214 12:17:27.980257 00580000 ################################################################
2215 12:17:27.980413
2216 12:17:28.546833 00600000 ################################################################
2217 12:17:28.546973
2218 12:17:29.109780 00680000 ################################################################
2219 12:17:29.109924
2220 12:17:29.352210 00700000 ############################ done.
2221 12:17:29.352349
2222 12:17:29.355675 The bootfile was 7569296 bytes long.
2223 12:17:29.355756
2224 12:17:29.359045 Sending tftp read request... done.
2225 12:17:29.359121
2226 12:17:29.362173 Waiting for the transfer...
2227 12:17:29.362248
2228 12:17:29.941611 00000000 ################################################################
2229 12:17:29.941754
2230 12:17:30.522634 00080000 ################################################################
2231 12:17:30.522780
2232 12:17:31.100421 00100000 ################################################################
2233 12:17:31.100571
2234 12:17:31.648934 00180000 ################################################################
2235 12:17:31.649078
2236 12:17:32.223809 00200000 ################################################################
2237 12:17:32.223968
2238 12:17:32.800627 00280000 ################################################################
2239 12:17:32.800785
2240 12:17:33.353791 00300000 ################################################################
2241 12:17:33.353939
2242 12:17:33.900167 00380000 ################################################################
2243 12:17:33.900320
2244 12:17:34.469643 00400000 ################################################################
2245 12:17:34.469802
2246 12:17:35.050985 00480000 ################################################################
2247 12:17:35.051126
2248 12:17:35.590370 00500000 ################################################################
2249 12:17:35.590509
2250 12:17:36.134898 00580000 ################################################################
2251 12:17:36.135039
2252 12:17:36.684106 00600000 ################################################################
2253 12:17:36.684247
2254 12:17:37.236250 00680000 ################################################################
2255 12:17:37.236426
2256 12:17:37.807402 00700000 ################################################################
2257 12:17:37.807551
2258 12:17:38.372028 00780000 ################################################################
2259 12:17:38.372172
2260 12:17:38.946029 00800000 ################################################################
2261 12:17:38.946179
2262 12:17:39.523170 00880000 ################################################################
2263 12:17:39.523320
2264 12:17:40.087604 00900000 ################################################################
2265 12:17:40.087754
2266 12:17:40.628545 00980000 ################################################################
2267 12:17:40.628693
2268 12:17:41.184124 00a00000 ################################################################
2269 12:17:41.184289
2270 12:17:41.761590 00a80000 ################################################################
2271 12:17:41.761741
2272 12:17:42.303034 00b00000 ################################################################
2273 12:17:42.303187
2274 12:17:42.884733 00b80000 ################################################################
2275 12:17:42.884881
2276 12:17:43.469811 00c00000 ################################################################
2277 12:17:43.470407
2278 12:17:44.177108 00c80000 ################################################################
2279 12:17:44.177729
2280 12:17:44.892114 00d00000 ################################################################
2281 12:17:44.892768
2282 12:17:45.560037 00d80000 ################################################################
2283 12:17:45.560594
2284 12:17:46.157886 00e00000 ################################################################
2285 12:17:46.158286
2286 12:17:46.776242 00e80000 ################################################################
2287 12:17:46.776785
2288 12:17:47.495558 00f00000 ################################################################
2289 12:17:47.496158
2290 12:17:48.202036 00f80000 ################################################################
2291 12:17:48.202724
2292 12:17:48.876657 01000000 ################################################################
2293 12:17:48.877214
2294 12:17:49.508186 01080000 ################################################################
2295 12:17:49.508813
2296 12:17:50.230118 01100000 ################################################################
2297 12:17:50.230715
2298 12:17:50.946459 01180000 ################################################################
2299 12:17:50.947123
2300 12:17:51.669115 01200000 ################################################################
2301 12:17:51.669724
2302 12:17:52.386893 01280000 ################################################################
2303 12:17:52.387047
2304 12:17:52.987987 01300000 ################################################################
2305 12:17:52.988129
2306 12:17:53.697826 01380000 ################################################################
2307 12:17:53.698391
2308 12:17:54.422931 01400000 ################################################################
2309 12:17:54.423565
2310 12:17:55.143993 01480000 ################################################################
2311 12:17:55.144617
2312 12:17:55.867463 01500000 ################################################################
2313 12:17:55.868065
2314 12:17:56.583542 01580000 ################################################################
2315 12:17:56.584179
2316 12:17:57.307112 01600000 ################################################################
2317 12:17:57.307716
2318 12:17:58.036106 01680000 ################################################################
2319 12:17:58.036732
2320 12:17:58.769842 01700000 ################################################################
2321 12:17:58.770501
2322 12:17:59.493225 01780000 ################################################################
2323 12:17:59.493876
2324 12:18:00.226465 01800000 ################################################################
2325 12:18:00.227117
2326 12:18:00.957127 01880000 ################################################################
2327 12:18:00.957764
2328 12:18:01.680917 01900000 ################################################################
2329 12:18:01.681532
2330 12:18:02.412585 01980000 ################################################################
2331 12:18:02.413151
2332 12:18:03.118170 01a00000 ################################################################
2333 12:18:03.118697
2334 12:18:03.845564 01a80000 ################################################################
2335 12:18:03.846172
2336 12:18:04.477316 01b00000 ################################################################
2337 12:18:04.477466
2338 12:18:05.085717 01b80000 ################################################################
2339 12:18:05.086038
2340 12:18:05.794131 01c00000 ################################################################
2341 12:18:05.794694
2342 12:18:06.414264 01c80000 ################################################################
2343 12:18:06.414817
2344 12:18:07.113141 01d00000 ################################################################
2345 12:18:07.113654
2346 12:18:07.775018 01d80000 ################################################################
2347 12:18:07.775251
2348 12:18:08.424307 01e00000 ################################################################
2349 12:18:08.424467
2350 12:18:09.114328 01e80000 ################################################################
2351 12:18:09.114964
2352 12:18:09.846130 01f00000 ################################################################
2353 12:18:09.846720
2354 12:18:10.558414 01f80000 ################################################################
2355 12:18:10.559035
2356 12:18:11.274772 02000000 ################################################################
2357 12:18:11.275383
2358 12:18:12.007252 02080000 ################################################################
2359 12:18:12.007926
2360 12:18:12.711592 02100000 ################################################################
2361 12:18:12.712201
2362 12:18:13.438145 02180000 ################################################################
2363 12:18:13.438727
2364 12:18:13.649515 02200000 #################### done.
2365 12:18:13.650114
2366 12:18:13.652596 Sending tftp read request... done.
2367 12:18:13.653084
2368 12:18:13.655931 Waiting for the transfer...
2369 12:18:13.656441
2370 12:18:13.656828 00000000 # done.
2371 12:18:13.657195
2372 12:18:13.666018 Command line loaded dynamically from TFTP file: 8948145/tftp-deploy-m3zcztrl/kernel/cmdline
2373 12:18:13.666607
2374 12:18:13.679474 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2375 12:18:13.680054
2376 12:18:13.689567 Shutting down all USB controllers.
2377 12:18:13.690052
2378 12:18:13.690434 Removing current net device
2379 12:18:13.690794
2380 12:18:13.692950 Finalizing coreboot
2381 12:18:13.693432
2382 12:18:13.700178 Exiting depthcharge with code 4 at timestamp: 62137986
2383 12:18:13.700805
2384 12:18:13.701194
2385 12:18:13.701647 Starting kernel ...
2386 12:18:13.702135
2387 12:18:13.702492
2388 12:18:13.702832
2389 12:18:13.704391 end: 2.2.4 bootloader-commands (duration 00:00:53) [common]
2390 12:18:13.704940 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
2391 12:18:13.705362 Setting prompt string to ['Linux version [0-9]']
2392 12:18:13.705763 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2393 12:18:13.706170 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2395 12:22:03.705888 end: 2.2.5 auto-login-action (duration 00:03:50) [common]
2397 12:22:03.707036 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 230 seconds'
2399 12:22:03.707882 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2402 12:22:03.709541 end: 2 depthcharge-action (duration 00:05:00) [common]
2404 12:22:03.710521 Cleaning after the job
2405 12:22:03.710608 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/ramdisk
2406 12:22:03.712761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/kernel
2407 12:22:03.713291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948145/tftp-deploy-m3zcztrl/modules
2408 12:22:03.713472 start: 4.1 power-off (timeout 00:00:30) [common]
2409 12:22:03.713619 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-9' '--port=1' '--command=off'
2410 12:22:03.732469 >> Command sent successfully.
2411 12:22:03.734341 Returned 0 in 0 seconds
2412 12:22:03.835604 end: 4.1 power-off (duration 00:00:00) [common]
2414 12:22:03.837203 start: 4.2 read-feedback (timeout 00:10:00) [common]
2415 12:22:03.838362 Listened to connection for namespace 'common' for up to 1s
2416 12:22:04.840738 Finalising connection for namespace 'common'
2417 12:22:04.841468 Disconnecting from shell: Finalise
2418 12:22:04.943096 end: 4.2 read-feedback (duration 00:00:01) [common]
2419 12:22:04.943703 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8948145
2420 12:22:05.006948 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8948145
2421 12:22:05.007165 JobError: Your job cannot terminate cleanly.