Boot log: asus-C436FA-Flip-hatch
- Kernel Errors: 0
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 0
- Warnings: 0
1 12:27:08.743666 lava-dispatcher, installed at version: 2022.11
2 12:27:08.743858 start: 0 validate
3 12:27:08.743984 Start time: 2023-01-31 12:27:08.743977+00:00 (UTC)
4 12:27:08.744106 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:27:08.744229 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230127.0%2Famd64%2Finitrd.cpio.gz exists
6 12:27:09.041713 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:27:09.042472 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:27:09.339079 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:27:09.339797 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230127.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 12:27:09.637000 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:27:09.637504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-cip%2Fv4.4.302-cip72%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:27:09.936070 validate duration: 1.19
14 12:27:09.936353 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:27:09.936452 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:27:09.936540 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:27:09.936637 Not decompressing ramdisk as can be used compressed.
18 12:27:09.936810 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230127.0/amd64/initrd.cpio.gz
19 12:27:09.936883 saving as /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/ramdisk/initrd.cpio.gz
20 12:27:09.936946 total size: 5432098 (5MB)
21 12:27:09.940037 progress 0% (0MB)
22 12:27:09.942437 progress 5% (0MB)
23 12:27:09.944775 progress 10% (0MB)
24 12:27:09.947157 progress 15% (0MB)
25 12:27:09.949521 progress 20% (1MB)
26 12:27:09.951764 progress 25% (1MB)
27 12:27:09.954107 progress 30% (1MB)
28 12:27:09.956510 progress 35% (1MB)
29 12:27:09.959138 progress 40% (2MB)
30 12:27:09.961358 progress 45% (2MB)
31 12:27:09.963193 progress 50% (2MB)
32 12:27:09.965727 progress 55% (2MB)
33 12:27:09.968047 progress 60% (3MB)
34 12:27:09.970283 progress 65% (3MB)
35 12:27:09.972641 progress 70% (3MB)
36 12:27:09.975415 progress 75% (3MB)
37 12:27:09.977246 progress 80% (4MB)
38 12:27:09.979651 progress 85% (4MB)
39 12:27:09.982299 progress 90% (4MB)
40 12:27:09.984111 progress 95% (4MB)
41 12:27:09.986333 progress 100% (5MB)
42 12:27:09.986654 5MB downloaded in 0.05s (104.23MB/s)
43 12:27:09.986837 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:27:09.987134 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:27:09.987240 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:27:09.987341 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:27:09.987463 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 12:27:09.987546 saving as /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/kernel/bzImage
50 12:27:09.987620 total size: 7569296 (7MB)
51 12:27:09.987692 No compression specified
52 12:27:09.989871 progress 0% (0MB)
53 12:27:09.993101 progress 5% (0MB)
54 12:27:09.996295 progress 10% (0MB)
55 12:27:09.999392 progress 15% (1MB)
56 12:27:10.002660 progress 20% (1MB)
57 12:27:10.005701 progress 25% (1MB)
58 12:27:10.008994 progress 30% (2MB)
59 12:27:10.012137 progress 35% (2MB)
60 12:27:10.015597 progress 40% (2MB)
61 12:27:10.018646 progress 45% (3MB)
62 12:27:10.021830 progress 50% (3MB)
63 12:27:10.025426 progress 55% (4MB)
64 12:27:10.028493 progress 60% (4MB)
65 12:27:10.031718 progress 65% (4MB)
66 12:27:10.035035 progress 70% (5MB)
67 12:27:10.038419 progress 75% (5MB)
68 12:27:10.041641 progress 80% (5MB)
69 12:27:10.044635 progress 85% (6MB)
70 12:27:10.047604 progress 90% (6MB)
71 12:27:10.051195 progress 95% (6MB)
72 12:27:10.054196 progress 100% (7MB)
73 12:27:10.054497 7MB downloaded in 0.07s (107.95MB/s)
74 12:27:10.054697 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:27:10.054935 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:27:10.055022 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:27:10.055107 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:27:10.055211 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230127.0/amd64/full.rootfs.tar.xz
80 12:27:10.055279 saving as /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/nfsrootfs/full.rootfs.tar
81 12:27:10.055341 total size: 207177260 (197MB)
82 12:27:10.055401 Using unxz to decompress xz
83 12:27:10.060486 progress 0% (0MB)
84 12:27:10.631658 progress 5% (9MB)
85 12:27:11.183227 progress 10% (19MB)
86 12:27:11.790375 progress 15% (29MB)
87 12:27:12.174824 progress 20% (39MB)
88 12:27:12.540729 progress 25% (49MB)
89 12:27:13.156591 progress 30% (59MB)
90 12:27:13.726359 progress 35% (69MB)
91 12:27:14.323964 progress 40% (79MB)
92 12:27:14.880129 progress 45% (88MB)
93 12:27:15.456860 progress 50% (98MB)
94 12:27:16.082365 progress 55% (108MB)
95 12:27:16.766421 progress 60% (118MB)
96 12:27:16.915941 progress 65% (128MB)
97 12:27:17.064954 progress 70% (138MB)
98 12:27:17.163230 progress 75% (148MB)
99 12:27:17.235829 progress 80% (158MB)
100 12:27:17.302623 progress 85% (167MB)
101 12:27:17.404412 progress 90% (177MB)
102 12:27:17.673436 progress 95% (187MB)
103 12:27:18.268283 progress 100% (197MB)
104 12:27:18.274011 197MB downloaded in 8.22s (24.04MB/s)
105 12:27:18.274259 end: 1.3.1 http-download (duration 00:00:08) [common]
107 12:27:18.274548 end: 1.3 download-retry (duration 00:00:08) [common]
108 12:27:18.274656 start: 1.4 download-retry (timeout 00:09:52) [common]
109 12:27:18.274747 start: 1.4.1 http-download (timeout 00:09:52) [common]
110 12:27:18.274860 downloading http://storage.kernelci.org/cip/linux-4.4.y-cip/v4.4.302-cip72/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 12:27:18.274929 saving as /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/modules/modules.tar
112 12:27:18.274994 total size: 51860 (0MB)
113 12:27:18.275058 Using unxz to decompress xz
114 12:27:18.280526 progress 63% (0MB)
115 12:27:18.280902 progress 100% (0MB)
116 12:27:18.284162 0MB downloaded in 0.01s (5.40MB/s)
117 12:27:18.284377 end: 1.4.1 http-download (duration 00:00:00) [common]
119 12:27:18.284657 end: 1.4 download-retry (duration 00:00:00) [common]
120 12:27:18.284753 start: 1.5 prepare-tftp-overlay (timeout 00:09:52) [common]
121 12:27:18.284849 start: 1.5.1 extract-nfsrootfs (timeout 00:09:52) [common]
122 12:27:20.251304 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/8948185/extract-nfsrootfs-i2edsw9p
123 12:27:20.251517 end: 1.5.1 extract-nfsrootfs (duration 00:00:02) [common]
124 12:27:20.251623 start: 1.5.2 lava-overlay (timeout 00:09:50) [common]
125 12:27:20.251790 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v
126 12:27:20.251891 makedir: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin
127 12:27:20.251976 makedir: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/tests
128 12:27:20.252088 makedir: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/results
129 12:27:20.252183 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-add-keys
130 12:27:20.252315 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-add-sources
131 12:27:20.252434 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-background-process-start
132 12:27:20.252557 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-background-process-stop
133 12:27:20.252668 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-common-functions
134 12:27:20.252779 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-echo-ipv4
135 12:27:20.252888 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-install-packages
136 12:27:20.252996 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-installed-packages
137 12:27:20.253106 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-os-build
138 12:27:20.253213 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-probe-channel
139 12:27:20.253322 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-probe-ip
140 12:27:20.253428 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-target-ip
141 12:27:20.253534 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-target-mac
142 12:27:20.253640 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-target-storage
143 12:27:20.253751 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-case
144 12:27:20.253861 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-event
145 12:27:20.253984 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-feedback
146 12:27:20.254107 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-raise
147 12:27:20.254213 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-reference
148 12:27:20.254320 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-runner
149 12:27:20.254426 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-set
150 12:27:20.254553 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-test-shell
151 12:27:20.254674 Updating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-add-keys (debian)
152 12:27:20.254784 Updating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-add-sources (debian)
153 12:27:20.254894 Updating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-install-packages (debian)
154 12:27:20.255002 Updating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-installed-packages (debian)
155 12:27:20.255110 Updating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/bin/lava-os-build (debian)
156 12:27:20.255205 Creating /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/environment
157 12:27:20.255290 LAVA metadata
158 12:27:20.255356 - LAVA_JOB_ID=8948185
159 12:27:20.255420 - LAVA_DISPATCHER_IP=192.168.201.1
160 12:27:20.255516 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:50) [common]
161 12:27:20.255582 skipped lava-vland-overlay
162 12:27:20.255657 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
163 12:27:20.255737 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
164 12:27:20.255800 skipped lava-multinode-overlay
165 12:27:20.255874 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
166 12:27:20.255955 start: 1.5.2.3 test-definition (timeout 00:09:50) [common]
167 12:27:20.256025 Loading test definitions
168 12:27:20.256114 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:50) [common]
169 12:27:20.256183 Using /lava-8948185 at stage 0
170 12:27:20.256406 uuid=8948185_1.5.2.3.1 testdef=None
171 12:27:20.256494 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
172 12:27:20.256580 start: 1.5.2.3.2 test-overlay (timeout 00:09:50) [common]
173 12:27:20.256988 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
175 12:27:20.257223 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:50) [common]
176 12:27:20.257705 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
178 12:27:20.257946 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
179 12:27:20.258401 runner path: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/0/tests/0_timesync-off test_uuid 8948185_1.5.2.3.1
180 12:27:20.258576 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
182 12:27:20.258826 start: 1.5.2.3.5 git-repo-action (timeout 00:09:50) [common]
183 12:27:20.258900 Using /lava-8948185 at stage 0
184 12:27:20.258995 Fetching tests from https://github.com/kernelci/test-definitions.git
185 12:27:20.259075 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/0/tests/1_kselftest-filesystems'
186 12:27:26.022912 Running '/usr/bin/git checkout kernelci.org
187 12:27:26.064544 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/0/tests/1_kselftest-filesystems/automated/linux/kselftest/kselftest.yaml
188 12:27:26.065322 uuid=8948185_1.5.2.3.5 testdef=None
189 12:27:26.065482 end: 1.5.2.3.5 git-repo-action (duration 00:00:06) [common]
191 12:27:26.065756 start: 1.5.2.3.6 test-overlay (timeout 00:09:44) [common]
192 12:27:26.066780 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
194 12:27:26.067085 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:44) [common]
195 12:27:26.067988 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
197 12:27:26.068239 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
198 12:27:26.069176 runner path: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/0/tests/1_kselftest-filesystems test_uuid 8948185_1.5.2.3.5
199 12:27:26.069270 BOARD='asus-C436FA-Flip-hatch'
200 12:27:26.069344 BRANCH='cip'
201 12:27:26.069410 SKIPFILE='skipfile-lkft.yaml'
202 12:27:26.069474 SKIP_INSTALL='True'
203 12:27:26.069533 TESTPROG_URL='None'
204 12:27:26.069593 TST_CASENAME=''
205 12:27:26.069650 TST_CMDFILES='filesystems'
206 12:27:26.069782 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
208 12:27:26.069997 Creating lava-test-runner.conf files
209 12:27:26.070063 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8948185/lava-overlay-vkkfs74v/lava-8948185/0 for stage 0
210 12:27:26.070147 - 0_timesync-off
211 12:27:26.070214 - 1_kselftest-filesystems
212 12:27:26.070304 end: 1.5.2.3 test-definition (duration 00:00:06) [common]
213 12:27:26.070393 start: 1.5.2.4 compress-overlay (timeout 00:09:44) [common]
214 12:27:33.571978 end: 1.5.2.4 compress-overlay (duration 00:00:08) [common]
215 12:27:33.572141 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
216 12:27:33.572238 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
217 12:27:33.572341 end: 1.5.2 lava-overlay (duration 00:00:13) [common]
218 12:27:33.572431 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
219 12:27:33.675177 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
220 12:27:33.675587 start: 1.5.4 extract-modules (timeout 00:09:36) [common]
221 12:27:33.675741 extracting modules file /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8948185/extract-nfsrootfs-i2edsw9p
222 12:27:33.679828 extracting modules file /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8948185/extract-overlay-ramdisk-e5jbfjh4/ramdisk
223 12:27:33.683555 end: 1.5.4 extract-modules (duration 00:00:00) [common]
224 12:27:33.683677 start: 1.5.5 apply-overlay-tftp (timeout 00:09:36) [common]
225 12:27:33.683774 [common] Applying overlay to NFS
226 12:27:33.683849 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8948185/compress-overlay-j8_yxpvn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8948185/extract-nfsrootfs-i2edsw9p
227 12:27:34.143282 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
228 12:27:34.143475 start: 1.5.6 configure-preseed-file (timeout 00:09:36) [common]
229 12:27:34.143575 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
230 12:27:34.143671 start: 1.5.7 compress-ramdisk (timeout 00:09:36) [common]
231 12:27:34.143761 Building ramdisk /var/lib/lava/dispatcher/tmp/8948185/extract-overlay-ramdisk-e5jbfjh4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8948185/extract-overlay-ramdisk-e5jbfjh4/ramdisk
232 12:27:34.176657 >> 24548 blocks
233 12:27:34.660440 rename /var/lib/lava/dispatcher/tmp/8948185/extract-overlay-ramdisk-e5jbfjh4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
234 12:27:34.660858 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
235 12:27:34.660981 start: 1.5.8 prepare-kernel (timeout 00:09:35) [common]
236 12:27:34.661089 start: 1.5.8.1 prepare-fit (timeout 00:09:35) [common]
237 12:27:34.661188 No mkimage arch provided, not using FIT.
238 12:27:34.661282 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
239 12:27:34.661386 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
240 12:27:34.661503 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
241 12:27:34.661603 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
242 12:27:34.661690 No LXC device requested
243 12:27:34.661776 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
244 12:27:34.661866 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
245 12:27:34.661953 end: 1.7 deploy-device-env (duration 00:00:00) [common]
246 12:27:34.662026 Checking files for TFTP limit of 4294967296 bytes.
247 12:27:34.662424 end: 1 tftp-deploy (duration 00:00:25) [common]
248 12:27:34.662571 start: 2 depthcharge-action (timeout 00:05:00) [common]
249 12:27:34.662675 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
250 12:27:34.662812 substitutions:
251 12:27:34.662881 - {DTB}: None
252 12:27:34.662946 - {INITRD}: 8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
253 12:27:34.663009 - {KERNEL}: 8948185/tftp-deploy-5jvubox5/kernel/bzImage
254 12:27:34.663069 - {LAVA_MAC}: None
255 12:27:34.663128 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/8948185/extract-nfsrootfs-i2edsw9p
256 12:27:34.663189 - {NFS_SERVER_IP}: 192.168.201.1
257 12:27:34.663247 - {PRESEED_CONFIG}: None
258 12:27:34.663303 - {PRESEED_LOCAL}: None
259 12:27:34.663359 - {RAMDISK}: 8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
260 12:27:34.663417 - {ROOT_PART}: None
261 12:27:34.663473 - {ROOT}: None
262 12:27:34.663529 - {SERVER_IP}: 192.168.201.1
263 12:27:34.663585 - {TEE}: None
264 12:27:34.663641 Parsed boot commands:
265 12:27:34.663697 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
266 12:27:34.663852 Parsed boot commands: tftpboot 192.168.201.1 8948185/tftp-deploy-5jvubox5/kernel/bzImage 8948185/tftp-deploy-5jvubox5/kernel/cmdline 8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
267 12:27:34.663944 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
268 12:27:34.664035 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
269 12:27:34.664135 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
270 12:27:34.664234 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
271 12:27:34.664308 Not connected, no need to disconnect.
272 12:27:34.664391 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
273 12:27:34.664475 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
274 12:27:34.664546 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-2'
275 12:27:34.667387 Setting prompt string to ['lava-test: # ']
276 12:27:34.667713 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
277 12:27:34.667839 end: 2.2.1 reset-connection (duration 00:00:00) [common]
278 12:27:34.667968 start: 2.2.2 reset-device (timeout 00:05:00) [common]
279 12:27:34.668091 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
280 12:27:34.668313 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-2' '--port=1' '--command=reboot'
281 12:27:34.687197 >> Command sent successfully.
282 12:27:34.689488 Returned 0 in 0 seconds
283 12:27:34.790266 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
285 12:27:34.790707 end: 2.2.2 reset-device (duration 00:00:00) [common]
286 12:27:34.790822 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
287 12:27:34.790945 Setting prompt string to 'Starting depthcharge on Helios...'
288 12:27:34.791013 Changing prompt to 'Starting depthcharge on Helios...'
289 12:27:34.791132 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
290 12:27:34.791413 [Enter `^Ec?' for help]
291 12:27:41.875212
292 12:27:41.875858
293 12:27:41.885505 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
294 12:27:41.888319 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
295 12:27:41.895157 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
296 12:27:41.898603 CPU: AES supported, TXT NOT supported, VT supported
297 12:27:41.904766 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
298 12:27:41.908228 PCH: device id 0284 (rev 00) is Cometlake-U Premium
299 12:27:41.914670 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
300 12:27:41.917842 VBOOT: Loading verstage.
301 12:27:41.921593 FMAP: Found "FLASH" version 1.1 at 0xc04000.
302 12:27:41.927769 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
303 12:27:41.934324 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
304 12:27:41.934862 CBFS @ c08000 size 3f8000
305 12:27:41.940871 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
306 12:27:41.944078 CBFS: Locating 'fallback/verstage'
307 12:27:41.947986 CBFS: Found @ offset 10fb80 size 1072c
308 12:27:41.950735
309 12:27:41.951349
310 12:27:41.951739
311 12:27:41.960414 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
312 12:27:41.976443 Probing TPM: . done!
313 12:27:41.979751 TPM ready after 0 ms
314 12:27:41.982960 Connected to device vid:did:rid of 1ae0:0028:00
315 12:27:41.992925 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
316 12:27:41.996569 Initialized TPM device CR50 revision 0
317 12:27:42.038524 tlcl_send_startup: Startup return code is 0
318 12:27:42.038735 TPM: setup succeeded
319 12:27:42.051014 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
320 12:27:42.054973 Chrome EC: UHEPI supported
321 12:27:42.058034 Phase 1
322 12:27:42.061358 FMAP: area GBB found @ c05000 (12288 bytes)
323 12:27:42.067851 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
324 12:27:42.071385 Phase 2
325 12:27:42.071475 Phase 3
326 12:27:42.074258 FMAP: area GBB found @ c05000 (12288 bytes)
327 12:27:42.081002 VB2:vb2_report_dev_firmware() This is developer signed firmware
328 12:27:42.087850 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
329 12:27:42.091182 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
330 12:27:42.097367 VB2:vb2_verify_keyblock() Checking keyblock signature...
331 12:27:42.113531 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
332 12:27:42.116794 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
333 12:27:42.123900 VB2:vb2_verify_fw_preamble() Verifying preamble.
334 12:27:42.127923 Phase 4
335 12:27:42.131469 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
336 12:27:42.137757 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
337 12:27:42.317725 VB2:vb2_rsa_verify_digest() Digest check failed!
338 12:27:42.324202 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
339 12:27:42.324676 Saving nvdata
340 12:27:42.327162 Reboot requested (10020007)
341 12:27:42.330489 board_reset() called!
342 12:27:42.330963 full_reset() called!
343 12:27:46.841832
344 12:27:46.841989
345 12:27:46.852117 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
346 12:27:46.855234 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
347 12:27:46.861863 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
348 12:27:46.864875 CPU: AES supported, TXT NOT supported, VT supported
349 12:27:46.871395 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
350 12:27:46.878003 PCH: device id 0284 (rev 00) is Cometlake-U Premium
351 12:27:46.881084 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
352 12:27:46.884493 VBOOT: Loading verstage.
353 12:27:46.891351 FMAP: Found "FLASH" version 1.1 at 0xc04000.
354 12:27:46.894806 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
355 12:27:46.901391 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
356 12:27:46.901477 CBFS @ c08000 size 3f8000
357 12:27:46.904737
358 12:27:46.907950 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
359 12:27:46.910941 CBFS: Locating 'fallback/verstage'
360 12:27:46.917409 CBFS: Found @ offset 10fb80 size 1072c
361 12:27:46.917498
362 12:27:46.917565
363 12:27:46.927122 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
364 12:27:46.943041 Probing TPM: . done!
365 12:27:46.946862 TPM ready after 0 ms
366 12:27:46.949847 Connected to device vid:did:rid of 1ae0:0028:00
367 12:27:46.959905 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
368 12:27:46.963297 Initialized TPM device CR50 revision 0
369 12:27:47.005777 tlcl_send_startup: Startup return code is 0
370 12:27:47.005896 TPM: setup succeeded
371 12:27:47.018377 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
372 12:27:47.022093 Chrome EC: UHEPI supported
373 12:27:47.025531 Phase 1
374 12:27:47.028776 FMAP: area GBB found @ c05000 (12288 bytes)
375 12:27:47.035213 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
376 12:27:47.041878 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
377 12:27:47.045121 Recovery requested (1009000e)
378 12:27:47.051059 Saving nvdata
379 12:27:47.057165 tlcl_extend: response is 0
380 12:27:47.065973 tlcl_extend: response is 0
381 12:27:47.072874 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
382 12:27:47.076477 CBFS @ c08000 size 3f8000
383 12:27:47.082994 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
384 12:27:47.086504 CBFS: Locating 'fallback/romstage'
385 12:27:47.089713 CBFS: Found @ offset 80 size 145fc
386 12:27:47.092583 Accumulated console time in verstage 98 ms
387 12:27:47.092671
388 12:27:47.092740
389 12:27:47.095848
390 12:27:47.105845 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
391 12:27:47.112531 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
392 12:27:47.115928 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
393 12:27:47.118811 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
394 12:27:47.125841 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
395 12:27:47.129013 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
396 12:27:47.132273 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
397 12:27:47.135739 TCO_STS: 0000 0000
398 12:27:47.138524 GEN_PMCON: e0015238 00000200
399 12:27:47.141851 GBLRST_CAUSE: 00000000 00000000
400 12:27:47.141940 prev_sleep_state 5
401 12:27:47.145698 Boot Count incremented to 45752
402 12:27:47.152596 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
403 12:27:47.156223 CBFS @ c08000 size 3f8000
404 12:27:47.162273 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
405 12:27:47.162368 CBFS: Locating 'fspm.bin'
406 12:27:47.169357 CBFS: Found @ offset 5ffc0 size 71000
407 12:27:47.172694 Chrome EC: UHEPI supported
408 12:27:47.178553 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
409 12:27:47.182624 Probing TPM: done!
410 12:27:47.189208 Connected to device vid:did:rid of 1ae0:0028:00
411 12:27:47.199488 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.23/cr50_v1.9308_87_mp.320-aa1dd98
412 12:27:47.205277 Initialized TPM device CR50 revision 0
413 12:27:47.214032 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
414 12:27:47.220678 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
415 12:27:47.224116
416 12:27:47.224205 MRC cache found, size 1948
417 12:27:47.227580 bootmode is set to: 2
418 12:27:47.230483 PRMRR disabled by config.
419 12:27:47.234029 SPD INDEX = 1
420 12:27:47.237115 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
421 12:27:47.240725 CBFS @ c08000 size 3f8000
422 12:27:47.247168 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
423 12:27:47.247259 CBFS: Locating 'spd.bin'
424 12:27:47.250311 CBFS: Found @ offset 5fb80 size 400
425 12:27:47.253921 SPD: module type is LPDDR3
426 12:27:47.257001 SPD: module part is
427 12:27:47.263974 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
428 12:27:47.267036 SPD: device width 4 bits, bus width 8 bits
429 12:27:47.270085 SPD: module size is 4096 MB (per channel)
430 12:27:47.273183 memory slot: 0 configuration done.
431 12:27:47.276886 memory slot: 2 configuration done.
432 12:27:47.280027
433 12:27:47.328414 CBMEM:
434 12:27:47.331822 IMD: root @ 99fff000 254 entries.
435 12:27:47.334986 IMD: root @ 99ffec00 62 entries.
436 12:27:47.338095 External stage cache:
437 12:27:47.341696 IMD: root @ 9abff000 254 entries.
438 12:27:47.344833 IMD: root @ 9abfec00 62 entries.
439 12:27:47.351821 Chrome EC: clear events_b mask to 0x0000000020004000
440 12:27:47.364013 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
441 12:27:47.377142 tlcl_write: response is 0
442 12:27:47.386179 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
443 12:27:47.393174 MRC: TPM MRC hash updated successfully.
444 12:27:47.393284 2 DIMMs found
445 12:27:47.396011 SMM Memory Map
446 12:27:47.399246 SMRAM : 0x9a000000 0x1000000
447 12:27:47.402708 Subregion 0: 0x9a000000 0xa00000
448 12:27:47.406075 Subregion 1: 0x9aa00000 0x200000
449 12:27:47.409488 Subregion 2: 0x9ac00000 0x400000
450 12:27:47.412619 top_of_ram = 0x9a000000
451 12:27:47.416340 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
452 12:27:47.422550 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
453 12:27:47.426192 MTRR Range: Start=ff000000 End=0 (Size 1000000)
454 12:27:47.432639 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
455 12:27:47.435706 CBFS @ c08000 size 3f8000
456 12:27:47.439245 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
457 12:27:47.442489 CBFS: Locating 'fallback/postcar'
458 12:27:47.448798 CBFS: Found @ offset 107000 size 4b44
459 12:27:47.455363 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
460 12:27:47.465500 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
461 12:27:47.468452 Processing 180 relocs. Offset value of 0x97c0c000
462 12:27:47.476445 Accumulated console time in romstage 286 ms
463 12:27:47.476530
464 12:27:47.476603
465 12:27:47.486721 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
466 12:27:47.493217 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
467 12:27:47.496085 CBFS @ c08000 size 3f8000
468 12:27:47.503165 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
469 12:27:47.506242 CBFS: Locating 'fallback/ramstage'
470 12:27:47.509589 CBFS: Found @ offset 43380 size 1b9e8
471 12:27:47.515875 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
472 12:27:47.548125 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
473 12:27:47.551428 Processing 3976 relocs. Offset value of 0x98db0000
474 12:27:47.558642 Accumulated console time in postcar 52 ms
475 12:27:47.558772
476 12:27:47.558841
477 12:27:47.568154 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
478 12:27:47.574621 FMAP: area RO_VPD found @ c00000 (16384 bytes)
479 12:27:47.577982 WARNING: RO_VPD is uninitialized or empty.
480 12:27:47.581394 FMAP: area RW_VPD found @ af8000 (8192 bytes)
481 12:27:47.587762 FMAP: area RW_VPD found @ af8000 (8192 bytes)
482 12:27:47.587893 Normal boot.
483 12:27:47.594231 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
484 12:27:47.597375 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
485 12:27:47.601010 CBFS @ c08000 size 3f8000
486 12:27:47.607750 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
487 12:27:47.610958 CBFS: Locating 'cpu_microcode_blob.bin'
488 12:27:47.614221 CBFS: Found @ offset 14700 size 2ec00
489 12:27:47.617520 microcode: sig=0x806ec pf=0x4 revision=0xc9
490 12:27:47.621055 Skip microcode update
491 12:27:47.627080 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
492 12:27:47.627168 CBFS @ c08000 size 3f8000
493 12:27:47.633820 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
494 12:27:47.637126 CBFS: Locating 'fsps.bin'
495 12:27:47.640604 CBFS: Found @ offset d1fc0 size 35000
496 12:27:47.666427 Detected 4 core, 8 thread CPU.
497 12:27:47.669706 Setting up SMI for CPU
498 12:27:47.673130 IED base = 0x9ac00000
499 12:27:47.673218 IED size = 0x00400000
500 12:27:47.676481 Will perform SMM setup.
501 12:27:47.683119 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
502 12:27:47.689351 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
503 12:27:47.692630 Processing 16 relocs. Offset value of 0x00030000
504 12:27:47.696505
505 12:27:47.696592 Attempting to start 7 APs
506 12:27:47.702586 Waiting for 10ms after sending INIT.
507 12:27:47.716252 Waiting for 1st SIPI to complete...AP: slot 4 apic_id 1.
508 12:27:47.716394 done.
509 12:27:47.719441 AP: slot 3 apic_id 5.
510 12:27:47.722635 AP: slot 2 apic_id 4.
511 12:27:47.722724 AP: slot 7 apic_id 6.
512 12:27:47.725794 AP: slot 6 apic_id 7.
513 12:27:47.729150 AP: slot 5 apic_id 2.
514 12:27:47.729237 AP: slot 1 apic_id 3.
515 12:27:47.732292
516 12:27:47.735880 Waiting for 2nd SIPI to complete...done.
517 12:27:47.742283 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
518 12:27:47.749128 Processing 13 relocs. Offset value of 0x00038000
519 12:27:47.755566 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
520 12:27:47.758916 Installing SMM handler to 0x9a000000
521 12:27:47.765143 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
522 12:27:47.771744 Processing 658 relocs. Offset value of 0x9a010000
523 12:27:47.778549 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
524 12:27:47.781694 Processing 13 relocs. Offset value of 0x9a008000
525 12:27:47.785001
526 12:27:47.788744 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
527 12:27:47.794929 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
528 12:27:47.801563 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
529 12:27:47.804946 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
530 12:27:47.807863
531 12:27:47.811343 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
532 12:27:47.817807 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
533 12:27:47.824450 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
534 12:27:47.831156 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
535 12:27:47.834276 Clearing SMI status registers
536 12:27:47.834362 SMI_STS: PM1
537 12:27:47.837764 PM1_STS: PWRBTN
538 12:27:47.837849 TCO_STS: SECOND_TO
539 12:27:47.841107 New SMBASE 0x9a000000
540 12:27:47.844542 In relocation handler: CPU 0
541 12:27:47.847771 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
542 12:27:47.854161 Writing SMRR. base = 0x9a000006, mask=0xff000800
543 12:27:47.854247 Relocation complete.
544 12:27:47.857500 New SMBASE 0x99fff000
545 12:27:47.860651 In relocation handler: CPU 4
546 12:27:47.863981 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
547 12:27:47.870801 Writing SMRR. base = 0x9a000006, mask=0xff000800
548 12:27:47.870902 Relocation complete.
549 12:27:47.874149 New SMBASE 0x99fffc00
550 12:27:47.877009 In relocation handler: CPU 1
551 12:27:47.880600 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
552 12:27:47.886935 Writing SMRR. base = 0x9a000006, mask=0xff000800
553 12:27:47.887020 Relocation complete.
554 12:27:47.890053 New SMBASE 0x99ffec00
555 12:27:47.893584 In relocation handler: CPU 5
556 12:27:47.896578 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
557 12:27:47.903192 Writing SMRR. base = 0x9a000006, mask=0xff000800
558 12:27:47.903278 Relocation complete.
559 12:27:47.906424 New SMBASE 0x99fff400
560 12:27:47.909706 In relocation handler: CPU 3
561 12:27:47.913043 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
562 12:27:47.919460 Writing SMRR. base = 0x9a000006, mask=0xff000800
563 12:27:47.919560 Relocation complete.
564 12:27:47.922693 New SMBASE 0x99fff800
565 12:27:47.926030 In relocation handler: CPU 2
566 12:27:47.929890 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
567 12:27:47.936173 Writing SMRR. base = 0x9a000006, mask=0xff000800
568 12:27:47.936319 Relocation complete.
569 12:27:47.939215 New SMBASE 0x99ffe400
570 12:27:47.942772 In relocation handler: CPU 7
571 12:27:47.945680 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
572 12:27:47.952565 Writing SMRR. base = 0x9a000006, mask=0xff000800
573 12:27:47.952711 Relocation complete.
574 12:27:47.955796 New SMBASE 0x99ffe800
575 12:27:47.959024 In relocation handler: CPU 6
576 12:27:47.962353 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
577 12:27:47.969144 Writing SMRR. base = 0x9a000006, mask=0xff000800
578 12:27:47.969230 Relocation complete.
579 12:27:47.972173 Initializing CPU #0
580 12:27:47.975659 CPU: vendor Intel device 806ec
581 12:27:47.978772 CPU: family 06, model 8e, stepping 0c
582 12:27:47.982014 Clearing out pending MCEs
583 12:27:47.985161 Setting up local APIC...
584 12:27:47.985268 apic_id: 0x00 done.
585 12:27:47.988301 Turbo is available but hidden
586 12:27:47.991819 Turbo is available and visible
587 12:27:47.994921 VMX status: enabled
588 12:27:47.998342 IA32_FEATURE_CONTROL status: locked
589 12:27:48.001547 Skip microcode update
590 12:27:48.001646 CPU #0 initialized
591 12:27:48.005017 Initializing CPU #4
592 12:27:48.005102 Initializing CPU #6
593 12:27:48.008085
594 12:27:48.008170 Initializing CPU #7
595 12:27:48.011398 CPU: vendor Intel device 806ec
596 12:27:48.014761 CPU: family 06, model 8e, stepping 0c
597 12:27:48.018342 CPU: vendor Intel device 806ec
598 12:27:48.021311 CPU: family 06, model 8e, stepping 0c
599 12:27:48.025488 Clearing out pending MCEs
600 12:27:48.028206 Clearing out pending MCEs
601 12:27:48.031620 Setting up local APIC...
602 12:27:48.034870 CPU: vendor Intel device 806ec
603 12:27:48.038077 CPU: family 06, model 8e, stepping 0c
604 12:27:48.041188 Clearing out pending MCEs
605 12:27:48.041310 Initializing CPU #1
606 12:27:48.044363 Initializing CPU #5
607 12:27:48.047592 CPU: vendor Intel device 806ec
608 12:27:48.051251 CPU: family 06, model 8e, stepping 0c
609 12:27:48.054369 CPU: vendor Intel device 806ec
610 12:27:48.057895 CPU: family 06, model 8e, stepping 0c
611 12:27:48.061125 Clearing out pending MCEs
612 12:27:48.064452 Clearing out pending MCEs
613 12:27:48.064611 Setting up local APIC...
614 12:27:48.067578 Setting up local APIC...
615 12:27:48.071267 apic_id: 0x07 done.
616 12:27:48.074873 Setting up local APIC...
617 12:27:48.075417 apic_id: 0x01 done.
618 12:27:48.077823 Initializing CPU #2
619 12:27:48.081138 Setting up local APIC...
620 12:27:48.081681 VMX status: enabled
621 12:27:48.084343 apic_id: 0x02 done.
622 12:27:48.084889 apic_id: 0x03 done.
623 12:27:48.087612
624 12:27:48.088056 VMX status: enabled
625 12:27:48.090901 VMX status: enabled
626 12:27:48.094027 IA32_FEATURE_CONTROL status: locked
627 12:27:48.097722 IA32_FEATURE_CONTROL status: locked
628 12:27:48.100990 Skip microcode update
629 12:27:48.101327 Skip microcode update
630 12:27:48.103582 CPU #5 initialized
631 12:27:48.103668 CPU #1 initialized
632 12:27:48.107195
633 12:27:48.110176 IA32_FEATURE_CONTROL status: locked
634 12:27:48.110264 Initializing CPU #3
635 12:27:48.113560 CPU: vendor Intel device 806ec
636 12:27:48.117538 CPU: family 06, model 8e, stepping 0c
637 12:27:48.120492 CPU: vendor Intel device 806ec
638 12:27:48.123726 CPU: family 06, model 8e, stepping 0c
639 12:27:48.127234 Clearing out pending MCEs
640 12:27:48.130227 Clearing out pending MCEs
641 12:27:48.133392 Setting up local APIC...
642 12:27:48.133547 Skip microcode update
643 12:27:48.136723 apic_id: 0x06 done.
644 12:27:48.140231 VMX status: enabled
645 12:27:48.140400 VMX status: enabled
646 12:27:48.143302 IA32_FEATURE_CONTROL status: locked
647 12:27:48.150044 IA32_FEATURE_CONTROL status: locked
648 12:27:48.150232 Skip microcode update
649 12:27:48.153256 Skip microcode update
650 12:27:48.153457 CPU #6 initialized
651 12:27:48.156464
652 12:27:48.156676 CPU #7 initialized
653 12:27:48.159677 apic_id: 0x05 done.
654 12:27:48.162770 Setting up local APIC...
655 12:27:48.163002 CPU #4 initialized
656 12:27:48.166486 apic_id: 0x04 done.
657 12:27:48.166747 VMX status: enabled
658 12:27:48.169691 VMX status: enabled
659 12:27:48.173147 IA32_FEATURE_CONTROL status: locked
660 12:27:48.177064 IA32_FEATURE_CONTROL status: locked
661 12:27:48.180075 Skip microcode update
662 12:27:48.183211 Skip microcode update
663 12:27:48.183649 CPU #3 initialized
664 12:27:48.186755 CPU #2 initialized
665 12:27:48.189539 bsp_do_flight_plan done after 452 msecs.
666 12:27:48.193072 CPU: frequency set to 4200 MHz
667 12:27:48.193614 Enabling SMIs.
668 12:27:48.196243 Locking SMM.
669 12:27:48.210459 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
670 12:27:48.213907 CBFS @ c08000 size 3f8000
671 12:27:48.220536 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
672 12:27:48.221079 CBFS: Locating 'vbt.bin'
673 12:27:48.223724 CBFS: Found @ offset 5f5c0 size 499
674 12:27:48.226788
675 12:27:48.230397 Found a VBT of 4608 bytes after decompression
676 12:27:48.414090 Display FSP Version Info HOB
677 12:27:48.417171 Reference Code - CPU = 9.0.1e.30
678 12:27:48.420166 uCode Version = 0.0.0.ca
679 12:27:48.423370 TXT ACM version = ff.ff.ff.ffff
680 12:27:48.426668 Display FSP Version Info HOB
681 12:27:48.430139 Reference Code - ME = 9.0.1e.30
682 12:27:48.433015 MEBx version = 0.0.0.0
683 12:27:48.436055 ME Firmware Version = Consumer SKU
684 12:27:48.439431 Display FSP Version Info HOB
685 12:27:48.442548 Reference Code - CML PCH = 9.0.1e.30
686 12:27:48.445947 PCH-CRID Status = Disabled
687 12:27:48.449442 PCH-CRID Original Value = ff.ff.ff.ffff
688 12:27:48.452468 PCH-CRID New Value = ff.ff.ff.ffff
689 12:27:48.455957 OPROM - RST - RAID = ff.ff.ff.ffff
690 12:27:48.458979 ChipsetInit Base Version = ff.ff.ff.ffff
691 12:27:48.465648 ChipsetInit Oem Version = ff.ff.ff.ffff
692 12:27:48.466131 Display FSP Version Info HOB
693 12:27:48.471896 Reference Code - SA - System Agent = 9.0.1e.30
694 12:27:48.475466 Reference Code - MRC = 0.7.1.6c
695 12:27:48.478957 SA - PCIe Version = 9.0.1e.30
696 12:27:48.481950 SA-CRID Status = Disabled
697 12:27:48.485156 SA-CRID Original Value = 0.0.0.c
698 12:27:48.485719 SA-CRID New Value = 0.0.0.c
699 12:27:48.488886
700 12:27:48.489333 OPROM - VBIOS = ff.ff.ff.ffff
701 12:27:48.492595 RTC Init
702 12:27:48.495459 Set power on after power failure.
703 12:27:48.496075 Disabling Deep S3
704 12:27:48.499363 Disabling Deep S3
705 12:27:48.502360 Disabling Deep S4
706 12:27:48.502953 Disabling Deep S4
707 12:27:48.505398 Disabling Deep S5
708 12:27:48.505846 Disabling Deep S5
709 12:27:48.511852 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 194 exit 1
710 12:27:48.515570 Enumerating buses...
711 12:27:48.518607 Show all devs... Before device enumeration.
712 12:27:48.521705 Root Device: enabled 1
713 12:27:48.525179 CPU_CLUSTER: 0: enabled 1
714 12:27:48.525745 DOMAIN: 0000: enabled 1
715 12:27:48.528563 APIC: 00: enabled 1
716 12:27:48.531672 PCI: 00:00.0: enabled 1
717 12:27:48.532273 PCI: 00:02.0: enabled 1
718 12:27:48.534720
719 12:27:48.535182 PCI: 00:04.0: enabled 0
720 12:27:48.538001 PCI: 00:05.0: enabled 0
721 12:27:48.541802 PCI: 00:12.0: enabled 1
722 12:27:48.542508 PCI: 00:12.5: enabled 0
723 12:27:48.544823 PCI: 00:12.6: enabled 0
724 12:27:48.547562 PCI: 00:14.0: enabled 1
725 12:27:48.550841 PCI: 00:14.1: enabled 0
726 12:27:48.551346 PCI: 00:14.3: enabled 1
727 12:27:48.554001 PCI: 00:14.5: enabled 0
728 12:27:48.557368 PCI: 00:15.0: enabled 1
729 12:27:48.560363 PCI: 00:15.1: enabled 1
730 12:27:48.560830 PCI: 00:15.2: enabled 0
731 12:27:48.563645 PCI: 00:15.3: enabled 0
732 12:27:48.567150 PCI: 00:16.0: enabled 1
733 12:27:48.570362 PCI: 00:16.1: enabled 0
734 12:27:48.570847 PCI: 00:16.2: enabled 0
735 12:27:48.573703 PCI: 00:16.3: enabled 0
736 12:27:48.577263 PCI: 00:16.4: enabled 0
737 12:27:48.580280 PCI: 00:16.5: enabled 0
738 12:27:48.580724 PCI: 00:17.0: enabled 1
739 12:27:48.583886 PCI: 00:19.0: enabled 1
740 12:27:48.587099 PCI: 00:19.1: enabled 0
741 12:27:48.590204 PCI: 00:19.2: enabled 0
742 12:27:48.590779 PCI: 00:1a.0: enabled 0
743 12:27:48.593656 PCI: 00:1c.0: enabled 0
744 12:27:48.596742 PCI: 00:1c.1: enabled 0
745 12:27:48.600013 PCI: 00:1c.2: enabled 0
746 12:27:48.600463 PCI: 00:1c.3: enabled 0
747 12:27:48.603014 PCI: 00:1c.4: enabled 0
748 12:27:48.606142 PCI: 00:1c.5: enabled 0
749 12:27:48.609475 PCI: 00:1c.6: enabled 0
750 12:27:48.609917 PCI: 00:1c.7: enabled 0
751 12:27:48.612904 PCI: 00:1d.0: enabled 1
752 12:27:48.615913 PCI: 00:1d.1: enabled 0
753 12:27:48.619263 PCI: 00:1d.2: enabled 0
754 12:27:48.619579 PCI: 00:1d.3: enabled 0
755 12:27:48.622673 PCI: 00:1d.4: enabled 0
756 12:27:48.626090 PCI: 00:1d.5: enabled 1
757 12:27:48.629072 PCI: 00:1e.0: enabled 1
758 12:27:48.629391 PCI: 00:1e.1: enabled 0
759 12:27:48.632243 PCI: 00:1e.2: enabled 1
760 12:27:48.635301 PCI: 00:1e.3: enabled 1
761 12:27:48.638595 PCI: 00:1f.0: enabled 1
762 12:27:48.638836 PCI: 00:1f.1: enabled 1
763 12:27:48.642099 PCI: 00:1f.2: enabled 1
764 12:27:48.645152 PCI: 00:1f.3: enabled 1
765 12:27:48.648304 PCI: 00:1f.4: enabled 1
766 12:27:48.648557 PCI: 00:1f.5: enabled 1
767 12:27:48.651581 PCI: 00:1f.6: enabled 0
768 12:27:48.655159 USB0 port 0: enabled 1
769 12:27:48.655398 I2C: 00:15: enabled 1
770 12:27:48.657998 I2C: 00:5d: enabled 1
771 12:27:48.661482 GENERIC: 0.0: enabled 1
772 12:27:48.664798 I2C: 00:1a: enabled 1
773 12:27:48.665037 I2C: 00:38: enabled 1
774 12:27:48.668028 I2C: 00:39: enabled 1
775 12:27:48.671693 I2C: 00:3a: enabled 1
776 12:27:48.672035 I2C: 00:3b: enabled 1
777 12:27:48.674615 PCI: 00:00.0: enabled 1
778 12:27:48.677626 SPI: 00: enabled 1
779 12:27:48.678002 SPI: 01: enabled 1
780 12:27:48.681319 PNP: 0c09.0: enabled 1
781 12:27:48.684500 USB2 port 0: enabled 1
782 12:27:48.685000 USB2 port 1: enabled 1
783 12:27:48.688033 USB2 port 2: enabled 0
784 12:27:48.691051 USB2 port 3: enabled 0
785 12:27:48.694766 USB2 port 5: enabled 0
786 12:27:48.695322 USB2 port 6: enabled 1
787 12:27:48.697727 USB2 port 9: enabled 1
788 12:27:48.700721 USB3 port 0: enabled 1
789 12:27:48.701166 USB3 port 1: enabled 1
790 12:27:48.704249 USB3 port 2: enabled 1
791 12:27:48.707570 USB3 port 3: enabled 1
792 12:27:48.710742 USB3 port 4: enabled 0
793 12:27:48.711294 APIC: 03: enabled 1
794 12:27:48.714396 APIC: 04: enabled 1
795 12:27:48.715001 APIC: 05: enabled 1
796 12:27:48.717017
797 12:27:48.717584 APIC: 01: enabled 1
798 12:27:48.720381 APIC: 02: enabled 1
799 12:27:48.720936 APIC: 07: enabled 1
800 12:27:48.724006 APIC: 06: enabled 1
801 12:27:48.727414 Compare with tree...
802 12:27:48.727968 Root Device: enabled 1
803 12:27:48.730145 CPU_CLUSTER: 0: enabled 1
804 12:27:48.733431 APIC: 00: enabled 1
805 12:27:48.736601 APIC: 03: enabled 1
806 12:27:48.737077 APIC: 04: enabled 1
807 12:27:48.740068 APIC: 05: enabled 1
808 12:27:48.743189 APIC: 01: enabled 1
809 12:27:48.743631 APIC: 02: enabled 1
810 12:27:48.746980 APIC: 07: enabled 1
811 12:27:48.749624 APIC: 06: enabled 1
812 12:27:48.750066 DOMAIN: 0000: enabled 1
813 12:27:48.753180 PCI: 00:00.0: enabled 1
814 12:27:48.756034 PCI: 00:02.0: enabled 1
815 12:27:48.760022 PCI: 00:04.0: enabled 0
816 12:27:48.762858 PCI: 00:05.0: enabled 0
817 12:27:48.763305 PCI: 00:12.0: enabled 1
818 12:27:48.766255
819 12:27:48.766734 PCI: 00:12.5: enabled 0
820 12:27:48.769210 PCI: 00:12.6: enabled 0
821 12:27:48.772681 PCI: 00:14.0: enabled 1
822 12:27:48.775896 USB0 port 0: enabled 1
823 12:27:48.778927 USB2 port 0: enabled 1
824 12:27:48.779408 USB2 port 1: enabled 1
825 12:27:48.782335 USB2 port 2: enabled 0
826 12:27:48.785545 USB2 port 3: enabled 0
827 12:27:48.788908 USB2 port 5: enabled 0
828 12:27:48.792423 USB2 port 6: enabled 1
829 12:27:48.795437 USB2 port 9: enabled 1
830 12:27:48.795882 USB3 port 0: enabled 1
831 12:27:48.798866 USB3 port 1: enabled 1
832 12:27:48.801801 USB3 port 2: enabled 1
833 12:27:48.805329 USB3 port 3: enabled 1
834 12:27:48.808691 USB3 port 4: enabled 0
835 12:27:48.811760 PCI: 00:14.1: enabled 0
836 12:27:48.812203 PCI: 00:14.3: enabled 1
837 12:27:48.815203 PCI: 00:14.5: enabled 0
838 12:27:48.818397 PCI: 00:15.0: enabled 1
839 12:27:48.821560 I2C: 00:15: enabled 1
840 12:27:48.824879 PCI: 00:15.1: enabled 1
841 12:27:48.825330 I2C: 00:5d: enabled 1
842 12:27:48.828031 GENERIC: 0.0: enabled 1
843 12:27:48.831521 PCI: 00:15.2: enabled 0
844 12:27:48.834481 PCI: 00:15.3: enabled 0
845 12:27:48.838145 PCI: 00:16.0: enabled 1
846 12:27:48.838629 PCI: 00:16.1: enabled 0
847 12:27:48.840905 PCI: 00:16.2: enabled 0
848 12:27:48.844175 PCI: 00:16.3: enabled 0
849 12:27:48.847970 PCI: 00:16.4: enabled 0
850 12:27:48.850975 PCI: 00:16.5: enabled 0
851 12:27:48.851456 PCI: 00:17.0: enabled 1
852 12:27:48.854121 PCI: 00:19.0: enabled 1
853 12:27:48.857663 I2C: 00:1a: enabled 1
854 12:27:48.860437 I2C: 00:38: enabled 1
855 12:27:48.863815 I2C: 00:39: enabled 1
856 12:27:48.864269 I2C: 00:3a: enabled 1
857 12:27:48.867032 I2C: 00:3b: enabled 1
858 12:27:48.870445 PCI: 00:19.1: enabled 0
859 12:27:48.873697 PCI: 00:19.2: enabled 0
860 12:27:48.876763 PCI: 00:1a.0: enabled 0
861 12:27:48.877292 PCI: 00:1c.0: enabled 0
862 12:27:48.880327 PCI: 00:1c.1: enabled 0
863 12:27:48.883261 PCI: 00:1c.2: enabled 0
864 12:27:48.886646 PCI: 00:1c.3: enabled 0
865 12:27:48.890035 PCI: 00:1c.4: enabled 0
866 12:27:48.890619 PCI: 00:1c.5: enabled 0
867 12:27:48.893171 PCI: 00:1c.6: enabled 0
868 12:27:48.896726 PCI: 00:1c.7: enabled 0
869 12:27:48.899610 PCI: 00:1d.0: enabled 1
870 12:27:48.902633 PCI: 00:1d.1: enabled 0
871 12:27:48.903104 PCI: 00:1d.2: enabled 0
872 12:27:48.906088 PCI: 00:1d.3: enabled 0
873 12:27:48.909682 PCI: 00:1d.4: enabled 0
874 12:27:48.912996 PCI: 00:1d.5: enabled 1
875 12:27:48.916000 PCI: 00:00.0: enabled 1
876 12:27:48.916450 PCI: 00:1e.0: enabled 1
877 12:27:48.918929 PCI: 00:1e.1: enabled 0
878 12:27:48.922494 PCI: 00:1e.2: enabled 1
879 12:27:48.925669 SPI: 00: enabled 1
880 12:27:48.928823 PCI: 00:1e.3: enabled 1
881 12:27:48.929143 SPI: 01: enabled 1
882 12:27:48.932149 PCI: 00:1f.0: enabled 1
883 12:27:48.935185 PNP: 0c09.0: enabled 1
884 12:27:48.938715 PCI: 00:1f.1: enabled 1
885 12:27:48.938911 PCI: 00:1f.2: enabled 1
886 12:27:48.942026 PCI: 00:1f.3: enabled 1
887 12:27:48.945012 PCI: 00:1f.4: enabled 1
888 12:27:48.948295 PCI: 00:1f.5: enabled 1
889 12:27:48.951563 PCI: 00:1f.6: enabled 0
890 12:27:48.951686 Root Device scanning...
891 12:27:48.955068 scan_static_bus for Root Device
892 12:27:48.958129 CPU_CLUSTER: 0 enabled
893 12:27:48.961567 DOMAIN: 0000 enabled
894 12:27:48.964789 DOMAIN: 0000 scanning...
895 12:27:48.967963 PCI: pci_scan_bus for bus 00
896 12:27:48.971432 PCI: 00:00.0 [8086/0000] ops
897 12:27:48.974643 PCI: 00:00.0 [8086/9b61] enabled
898 12:27:48.977630 PCI: 00:02.0 [8086/0000] bus ops
899 12:27:48.980756 PCI: 00:02.0 [8086/9b41] enabled
900 12:27:48.984026 PCI: 00:04.0 [8086/1903] disabled
901 12:27:48.987448 PCI: 00:08.0 [8086/1911] enabled
902 12:27:48.990769 PCI: 00:12.0 [8086/02f9] enabled
903 12:27:48.994225 PCI: 00:14.0 [8086/0000] bus ops
904 12:27:48.997362 PCI: 00:14.0 [8086/02ed] enabled
905 12:27:49.000394 PCI: 00:14.2 [8086/02ef] enabled
906 12:27:49.003819 PCI: 00:14.3 [8086/02f0] enabled
907 12:27:49.007069 PCI: 00:15.0 [8086/0000] bus ops
908 12:27:49.010292 PCI: 00:15.0 [8086/02e8] enabled
909 12:27:49.013692 PCI: 00:15.1 [8086/0000] bus ops
910 12:27:49.017319 PCI: 00:15.1 [8086/02e9] enabled
911 12:27:49.020431 PCI: 00:16.0 [8086/0000] ops
912 12:27:49.023773 PCI: 00:16.0 [8086/02e0] enabled
913 12:27:49.026739 PCI: 00:17.0 [8086/0000] ops
914 12:27:49.030374 PCI: 00:17.0 [8086/02d3] enabled
915 12:27:49.033563 PCI: 00:19.0 [8086/0000] bus ops
916 12:27:49.036783 PCI: 00:19.0 [8086/02c5] enabled
917 12:27:49.040061 PCI: 00:1d.0 [8086/0000] bus ops
918 12:27:49.043170 PCI: 00:1d.0 [8086/02b0] enabled
919 12:27:49.046424 PCI: Static device PCI: 00:1d.5 not found, disabling it.
920 12:27:49.049671
921 12:27:49.050219 PCI: 00:1e.0 [8086/0000] ops
922 12:27:49.052815 PCI: 00:1e.0 [8086/02a8] enabled
923 12:27:49.056442 PCI: 00:1e.2 [8086/0000] bus ops
924 12:27:49.059321 PCI: 00:1e.2 [8086/02aa] enabled
925 12:27:49.062599 PCI: 00:1e.3 [8086/0000] bus ops
926 12:27:49.066063 PCI: 00:1e.3 [8086/02ab] enabled
927 12:27:49.069036
928 12:27:49.069267 PCI: 00:1f.0 [8086/0000] bus ops
929 12:27:49.072352
930 12:27:49.075863 PCI: 00:1f.0 [8086/0284] enabled
931 12:27:49.079140 PCI: Static device PCI: 00:1f.1 not found, disabling it.
932 12:27:49.085468 PCI: Static device PCI: 00:1f.2 not found, disabling it.
933 12:27:49.088804 PCI: 00:1f.3 [8086/0000] bus ops
934 12:27:49.092260 PCI: 00:1f.3 [8086/02c8] enabled
935 12:27:49.095206 PCI: 00:1f.4 [8086/0000] bus ops
936 12:27:49.098453 PCI: 00:1f.4 [8086/02a3] enabled
937 12:27:49.101751 PCI: 00:1f.5 [8086/0000] bus ops
938 12:27:49.105055 PCI: 00:1f.5 [8086/02a4] enabled
939 12:27:49.108283 PCI: Leftover static devices:
940 12:27:49.108411 PCI: 00:05.0
941 12:27:49.111862 PCI: 00:12.5
942 12:27:49.111980 PCI: 00:12.6
943 12:27:49.114951 PCI: 00:14.1
944 12:27:49.115109 PCI: 00:14.5
945 12:27:49.118034 PCI: 00:15.2
946 12:27:49.118187 PCI: 00:15.3
947 12:27:49.118325 PCI: 00:16.1
948 12:27:49.121386 PCI: 00:16.2
949 12:27:49.121530 PCI: 00:16.3
950 12:27:49.124723 PCI: 00:16.4
951 12:27:49.124810 PCI: 00:16.5
952 12:27:49.124879 PCI: 00:19.1
953 12:27:49.127808 PCI: 00:19.2
954 12:27:49.127895 PCI: 00:1a.0
955 12:27:49.130935 PCI: 00:1c.0
956 12:27:49.131022 PCI: 00:1c.1
957 12:27:49.134126 PCI: 00:1c.2
958 12:27:49.134213 PCI: 00:1c.3
959 12:27:49.134299 PCI: 00:1c.4
960 12:27:49.137898 PCI: 00:1c.5
961 12:27:49.137988 PCI: 00:1c.6
962 12:27:49.140620 PCI: 00:1c.7
963 12:27:49.140737 PCI: 00:1d.1
964 12:27:49.140823 PCI: 00:1d.2
965 12:27:49.144166
966 12:27:49.144274 PCI: 00:1d.3
967 12:27:49.144364 PCI: 00:1d.4
968 12:27:49.147623 PCI: 00:1d.5
969 12:27:49.147713 PCI: 00:1e.1
970 12:27:49.150365 PCI: 00:1f.1
971 12:27:49.150468 PCI: 00:1f.2
972 12:27:49.150595 PCI: 00:1f.6
973 12:27:49.153905 PCI: Check your devicetree.cb.
974 12:27:49.157155 PCI: 00:02.0 scanning...
975 12:27:49.160361 scan_generic_bus for PCI: 00:02.0
976 12:27:49.163708 scan_generic_bus for PCI: 00:02.0 done
977 12:27:49.170377 scan_bus: scanning of bus PCI: 00:02.0 took 10201 usecs
978 12:27:49.173363 PCI: 00:14.0 scanning...
979 12:27:49.176758 scan_static_bus for PCI: 00:14.0
980 12:27:49.179942 USB0 port 0 enabled
981 12:27:49.180028 USB0 port 0 scanning...
982 12:27:49.183340 scan_static_bus for USB0 port 0
983 12:27:49.186693 USB2 port 0 enabled
984 12:27:49.189858 USB2 port 1 enabled
985 12:27:49.189947 USB2 port 2 disabled
986 12:27:49.193216 USB2 port 3 disabled
987 12:27:49.196540 USB2 port 5 disabled
988 12:27:49.196611 USB2 port 6 enabled
989 12:27:49.199497 USB2 port 9 enabled
990 12:27:49.202818 USB3 port 0 enabled
991 12:27:49.202891 USB3 port 1 enabled
992 12:27:49.206276 USB3 port 2 enabled
993 12:27:49.206345 USB3 port 3 enabled
994 12:27:49.209610 USB3 port 4 disabled
995 12:27:49.212761 USB2 port 0 scanning...
996 12:27:49.216127 scan_static_bus for USB2 port 0
997 12:27:49.219238 scan_static_bus for USB2 port 0 done
998 12:27:49.226002 scan_bus: scanning of bus USB2 port 0 took 9717 usecs
999 12:27:49.226092 USB2 port 1 scanning...
1000 12:27:49.229323 scan_static_bus for USB2 port 1
1001 12:27:49.235677 scan_static_bus for USB2 port 1 done
1002 12:27:49.239431 scan_bus: scanning of bus USB2 port 1 took 9703 usecs
1003 12:27:49.242286 USB2 port 6 scanning...
1004 12:27:49.245631 scan_static_bus for USB2 port 6
1005 12:27:49.249172 scan_static_bus for USB2 port 6 done
1006 12:27:49.255480 scan_bus: scanning of bus USB2 port 6 took 9709 usecs
1007 12:27:49.258792 USB2 port 9 scanning...
1008 12:27:49.261897 scan_static_bus for USB2 port 9
1009 12:27:49.265551 scan_static_bus for USB2 port 9 done
1010 12:27:49.268610 scan_bus: scanning of bus USB2 port 9 took 9702 usecs
1011 12:27:49.271922 USB3 port 0 scanning...
1012 12:27:49.274960 scan_static_bus for USB3 port 0
1013 12:27:49.278445 scan_static_bus for USB3 port 0 done
1014 12:27:49.285108 scan_bus: scanning of bus USB3 port 0 took 9715 usecs
1015 12:27:49.288496 USB3 port 1 scanning...
1016 12:27:49.291520 scan_static_bus for USB3 port 1
1017 12:27:49.294510 scan_static_bus for USB3 port 1 done
1018 12:27:49.300994 scan_bus: scanning of bus USB3 port 1 took 9700 usecs
1019 12:27:49.301072 USB3 port 2 scanning...
1020 12:27:49.304429 scan_static_bus for USB3 port 2
1021 12:27:49.310997 scan_static_bus for USB3 port 2 done
1022 12:27:49.314579 scan_bus: scanning of bus USB3 port 2 took 9708 usecs
1023 12:27:49.317684 USB3 port 3 scanning...
1024 12:27:49.320749 scan_static_bus for USB3 port 3
1025 12:27:49.324086 scan_static_bus for USB3 port 3 done
1026 12:27:49.330679 scan_bus: scanning of bus USB3 port 3 took 9711 usecs
1027 12:27:49.333590 scan_static_bus for USB0 port 0 done
1028 12:27:49.340304 scan_bus: scanning of bus USB0 port 0 took 155454 usecs
1029 12:27:49.343310 scan_static_bus for PCI: 00:14.0 done
1030 12:27:49.349911 scan_bus: scanning of bus PCI: 00:14.0 took 173070 usecs
1031 12:27:49.349993 PCI: 00:15.0 scanning...
1032 12:27:49.353197 scan_generic_bus for PCI: 00:15.0
1033 12:27:49.359945 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
1034 12:27:49.363029 scan_generic_bus for PCI: 00:15.0 done
1035 12:27:49.369488 scan_bus: scanning of bus PCI: 00:15.0 took 14287 usecs
1036 12:27:49.369581 PCI: 00:15.1 scanning...
1037 12:27:49.376042 scan_generic_bus for PCI: 00:15.1
1038 12:27:49.379483 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
1039 12:27:49.382978 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
1040 12:27:49.385891 scan_generic_bus for PCI: 00:15.1 done
1041 12:27:49.392375 scan_bus: scanning of bus PCI: 00:15.1 took 18599 usecs
1042 12:27:49.395770 PCI: 00:19.0 scanning...
1043 12:27:49.399174 scan_generic_bus for PCI: 00:19.0
1044 12:27:49.402160 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
1045 12:27:49.405403 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
1046 12:27:49.411989 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
1047 12:27:49.415267 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
1048 12:27:49.418458 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
1049 12:27:49.421878 scan_generic_bus for PCI: 00:19.0 done
1050 12:27:49.428214 scan_bus: scanning of bus PCI: 00:19.0 took 30747 usecs
1051 12:27:49.431381 PCI: 00:1d.0 scanning...
1052 12:27:49.434463 do_pci_scan_bridge for PCI: 00:1d.0
1053 12:27:49.438147 PCI: pci_scan_bus for bus 01
1054 12:27:49.441083 PCI: 01:00.0 [1c5c/1327] enabled
1055 12:27:49.444538 Enabling Common Clock Configuration
1056 12:27:49.447752 L1 Sub-State supported from root port 29
1057 12:27:49.451150
1058 12:27:49.451279 L1 Sub-State Support = 0xf
1059 12:27:49.454170 CommonModeRestoreTime = 0x28
1060 12:27:49.460661 Power On Value = 0x16, Power On Scale = 0x0
1061 12:27:49.460748 ASPM: Enabled L1
1062 12:27:49.467065 scan_bus: scanning of bus PCI: 00:1d.0 took 32795 usecs
1063 12:27:49.470730 PCI: 00:1e.2 scanning...
1064 12:27:49.473664 scan_generic_bus for PCI: 00:1e.2
1065 12:27:49.476905 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1066 12:27:49.480356 scan_generic_bus for PCI: 00:1e.2 done
1067 12:27:49.487479 scan_bus: scanning of bus PCI: 00:1e.2 took 14013 usecs
1068 12:27:49.490332 PCI: 00:1e.3 scanning...
1069 12:27:49.493534 scan_generic_bus for PCI: 00:1e.3
1070 12:27:49.497011 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1071 12:27:49.499955 scan_generic_bus for PCI: 00:1e.3 done
1072 12:27:49.506798 scan_bus: scanning of bus PCI: 00:1e.3 took 14020 usecs
1073 12:27:49.509760 PCI: 00:1f.0 scanning...
1074 12:27:49.513145 scan_static_bus for PCI: 00:1f.0
1075 12:27:49.513702 PNP: 0c09.0 enabled
1076 12:27:49.516504 scan_static_bus for PCI: 00:1f.0 done
1077 12:27:49.522970 scan_bus: scanning of bus PCI: 00:1f.0 took 12053 usecs
1078 12:27:49.526491 PCI: 00:1f.3 scanning...
1079 12:27:49.532760 scan_bus: scanning of bus PCI: 00:1f.3 took 2860 usecs
1080 12:27:49.533252 PCI: 00:1f.4 scanning...
1081 12:27:49.536638 scan_generic_bus for PCI: 00:1f.4
1082 12:27:49.539905
1083 12:27:49.542991 scan_generic_bus for PCI: 00:1f.4 done
1084 12:27:49.546350 scan_bus: scanning of bus PCI: 00:1f.4 took 10188 usecs
1085 12:27:49.549258 PCI: 00:1f.5 scanning...
1086 12:27:49.552531 scan_generic_bus for PCI: 00:1f.5
1087 12:27:49.556046 scan_generic_bus for PCI: 00:1f.5 done
1088 12:27:49.562284 scan_bus: scanning of bus PCI: 00:1f.5 took 10193 usecs
1089 12:27:49.568844 scan_bus: scanning of bus DOMAIN: 0000 took 605268 usecs
1090 12:27:49.572029 scan_static_bus for Root Device done
1091 12:27:49.578425 scan_bus: scanning of bus Root Device took 625139 usecs
1092 12:27:49.578541 done
1093 12:27:49.581658 Chrome EC: UHEPI supported
1094 12:27:49.588578 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1095 12:27:49.595172 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1096 12:27:49.601411 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1097 12:27:49.607914 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1098 12:27:49.611137 SPI flash protection: WPSW=0 SRP0=0
1099 12:27:49.614151 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1100 12:27:49.620821 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1101 12:27:49.624279 found VGA at PCI: 00:02.0
1102 12:27:49.627492 Setting up VGA for PCI: 00:02.0
1103 12:27:49.630456 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1104 12:27:49.637408 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1105 12:27:49.640346 Allocating resources...
1106 12:27:49.640434 Reading resources...
1107 12:27:49.646799 Root Device read_resources bus 0 link: 0
1108 12:27:49.650226 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1109 12:27:49.656657 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1110 12:27:49.660553 DOMAIN: 0000 read_resources bus 0 link: 0
1111 12:27:49.666336 PCI: 00:14.0 read_resources bus 0 link: 0
1112 12:27:49.669712 USB0 port 0 read_resources bus 0 link: 0
1113 12:27:49.677923 USB0 port 0 read_resources bus 0 link: 0 done
1114 12:27:49.681222 PCI: 00:14.0 read_resources bus 0 link: 0 done
1115 12:27:49.688758 PCI: 00:15.0 read_resources bus 1 link: 0
1116 12:27:49.691896 PCI: 00:15.0 read_resources bus 1 link: 0 done
1117 12:27:49.698479 PCI: 00:15.1 read_resources bus 2 link: 0
1118 12:27:49.701753 PCI: 00:15.1 read_resources bus 2 link: 0 done
1119 12:27:49.704871
1120 12:27:49.708275 PCI: 00:19.0 read_resources bus 3 link: 0
1121 12:27:49.715468 PCI: 00:19.0 read_resources bus 3 link: 0 done
1122 12:27:49.718832 PCI: 00:1d.0 read_resources bus 1 link: 0
1123 12:27:49.725401 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1124 12:27:49.728751 PCI: 00:1e.2 read_resources bus 4 link: 0
1125 12:27:49.735748 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1126 12:27:49.738959 PCI: 00:1e.3 read_resources bus 5 link: 0
1127 12:27:49.745502 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1128 12:27:49.748730 PCI: 00:1f.0 read_resources bus 0 link: 0
1129 12:27:49.755144 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1130 12:27:49.762117 DOMAIN: 0000 read_resources bus 0 link: 0 done
1131 12:27:49.765266 Root Device read_resources bus 0 link: 0 done
1132 12:27:49.768565 Done reading resources.
1133 12:27:49.774938 Show resources in subtree (Root Device)...After reading.
1134 12:27:49.778486 Root Device child on link 0 CPU_CLUSTER: 0
1135 12:27:49.782336 CPU_CLUSTER: 0 child on link 0 APIC: 00
1136 12:27:49.784915 APIC: 00
1137 12:27:49.785085 APIC: 03
1138 12:27:49.785218 APIC: 04
1139 12:27:49.788479
1140 12:27:49.788625 APIC: 05
1141 12:27:49.788739 APIC: 01
1142 12:27:49.791519 APIC: 02
1143 12:27:49.791645 APIC: 07
1144 12:27:49.791744 APIC: 06
1145 12:27:49.844156 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1146 12:27:49.844514 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1147 12:27:49.845090 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1148 12:27:49.845212 PCI: 00:00.0
1149 12:27:49.845694 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1150 12:27:49.845995 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1151 12:27:49.894006 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1152 12:27:49.894548 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1153 12:27:49.895157 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1154 12:27:49.895542 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1155 12:27:49.896433 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1156 12:27:49.896776 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1157 12:27:49.926488 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1158 12:27:49.926835 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1159 12:27:49.926947 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1160 12:27:49.930023 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1161 12:27:49.939920 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1162 12:27:49.949811 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1163 12:27:49.959739 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1164 12:27:49.969326 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1165 12:27:49.969417 PCI: 00:02.0
1166 12:27:49.978994 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1167 12:27:49.989090 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1168 12:27:49.998477 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1169 12:27:49.998595 PCI: 00:04.0
1170 12:27:50.001737 PCI: 00:08.0
1171 12:27:50.011553 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1172 12:27:50.011651 PCI: 00:12.0
1173 12:27:50.021591 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1174 12:27:50.025371
1175 12:27:50.028335 PCI: 00:14.0 child on link 0 USB0 port 0
1176 12:27:50.037871 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1177 12:27:50.041426 USB0 port 0 child on link 0 USB2 port 0
1178 12:27:50.044449 USB2 port 0
1179 12:27:50.044932 USB2 port 1
1180 12:27:50.047954 USB2 port 2
1181 12:27:50.048278 USB2 port 3
1182 12:27:50.050925 USB2 port 5
1183 12:27:50.051243 USB2 port 6
1184 12:27:50.054193
1185 12:27:50.054439 USB2 port 9
1186 12:27:50.057422 USB3 port 0
1187 12:27:50.057616 USB3 port 1
1188 12:27:50.060807 USB3 port 2
1189 12:27:50.061001 USB3 port 3
1190 12:27:50.064056 USB3 port 4
1191 12:27:50.064218 PCI: 00:14.2
1192 12:27:50.073916 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1193 12:27:50.083820 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1194 12:27:50.086767 PCI: 00:14.3
1195 12:27:50.096361 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1196 12:27:50.099798 PCI: 00:15.0 child on link 0 I2C: 01:15
1197 12:27:50.109796 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 12:27:50.113055 I2C: 01:15
1199 12:27:50.116177 PCI: 00:15.1 child on link 0 I2C: 02:5d
1200 12:27:50.125928 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 12:27:50.129175 I2C: 02:5d
1202 12:27:50.129398 GENERIC: 0.0
1203 12:27:50.132706 PCI: 00:16.0
1204 12:27:50.142234 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1205 12:27:50.142786 PCI: 00:17.0
1206 12:27:50.152337 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1207 12:27:50.161988 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1208 12:27:50.168381 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1209 12:27:50.178203 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1210 12:27:50.184648 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1211 12:27:50.194145 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1212 12:27:50.197456 PCI: 00:19.0 child on link 0 I2C: 03:1a
1213 12:27:50.210480 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1214 12:27:50.210615 I2C: 03:1a
1215 12:27:50.210714 I2C: 03:38
1216 12:27:50.213794 I2C: 03:39
1217 12:27:50.213916 I2C: 03:3a
1218 12:27:50.217166 I2C: 03:3b
1219 12:27:50.220244 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1220 12:27:50.230081 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1221 12:27:50.239596 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1222 12:27:50.249583 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1223 12:27:50.249674 PCI: 01:00.0
1224 12:27:50.259327 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1225 12:27:50.262369 PCI: 00:1e.0
1226 12:27:50.272303 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1227 12:27:50.282220 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1228 12:27:50.288688 PCI: 00:1e.2 child on link 0 SPI: 00
1229 12:27:50.298418 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 12:27:50.298747 SPI: 00
1231 12:27:50.301677 PCI: 00:1e.3 child on link 0 SPI: 01
1232 12:27:50.311798 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1233 12:27:50.315529 SPI: 01
1234 12:27:50.318302 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1235 12:27:50.327857 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1236 12:27:50.334605 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1237 12:27:50.337669 PNP: 0c09.0
1238 12:27:50.347719 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1239 12:27:50.348141 PCI: 00:1f.3
1240 12:27:50.357344 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1241 12:27:50.367326 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1242 12:27:50.370539 PCI: 00:1f.4
1243 12:27:50.377187 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1244 12:27:50.380278
1245 12:27:50.386718 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1246 12:27:50.390014 PCI: 00:1f.5
1247 12:27:50.399708 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1248 12:27:50.406429 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1249 12:27:50.413061 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1250 12:27:50.419209 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1251 12:27:50.422294 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1252 12:27:50.425706 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1253 12:27:50.429043 PCI: 00:17.0 18 * [0x60 - 0x67] io
1254 12:27:50.432497 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1255 12:27:50.438706 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1256 12:27:50.445180 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1257 12:27:50.454866 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1258 12:27:50.461448 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1259 12:27:50.468004 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1260 12:27:50.474488 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1261 12:27:50.481122 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1262 12:27:50.484253 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1263 12:27:50.490865 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1264 12:27:50.493814 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1265 12:27:50.500618 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1266 12:27:50.503766 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1267 12:27:50.510158 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1268 12:27:50.513642 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1269 12:27:50.520044 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1270 12:27:50.523446 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1271 12:27:50.529803 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1272 12:27:50.533260 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1273 12:27:50.539807 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1274 12:27:50.543188 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1275 12:27:50.549561 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1276 12:27:50.553248 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1277 12:27:50.559499 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1278 12:27:50.562838 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1279 12:27:50.569147 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1280 12:27:50.572386 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1281 12:27:50.578842 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1282 12:27:50.582193 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1283 12:27:50.588680 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1284 12:27:50.592418 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1285 12:27:50.601591 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1286 12:27:50.604767 avoid_fixed_resources: DOMAIN: 0000
1287 12:27:50.611408 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1288 12:27:50.617982 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1289 12:27:50.624808 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1290 12:27:50.630771 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1291 12:27:50.640912 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1292 12:27:50.647282 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1293 12:27:50.654057 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1294 12:27:50.663589 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1295 12:27:50.669979 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1296 12:27:50.676632 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1297 12:27:50.686730 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1298 12:27:50.692757 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1299 12:27:50.692838 Setting resources...
1300 12:27:50.699873 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1301 12:27:50.706002 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1302 12:27:50.709676 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1303 12:27:50.712516 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1304 12:27:50.715989 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1305 12:27:50.722474 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1306 12:27:50.729182 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1307 12:27:50.735574 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1308 12:27:50.742230 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1309 12:27:50.748176 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1310 12:27:50.751570 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1311 12:27:50.754744
1312 12:27:50.758214 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1313 12:27:50.761254 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1314 12:27:50.764747
1315 12:27:50.768339 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1316 12:27:50.771254 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1317 12:27:50.778123 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1318 12:27:50.781002 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1319 12:27:50.787624 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1320 12:27:50.791089 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1321 12:27:50.797022 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1322 12:27:50.800353 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1323 12:27:50.807060 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1324 12:27:50.810161 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1325 12:27:50.816819 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1326 12:27:50.819826 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1327 12:27:50.826347 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1328 12:27:50.830066 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1329 12:27:50.836213 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1330 12:27:50.839743 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1331 12:27:50.846015 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1332 12:27:50.849353 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1333 12:27:50.855780 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1334 12:27:50.862087 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1335 12:27:50.868972 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1336 12:27:50.878440 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1337 12:27:50.885001 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1338 12:27:50.888447 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1339 12:27:50.898236 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1340 12:27:50.901398 Root Device assign_resources, bus 0 link: 0
1341 12:27:50.908029 DOMAIN: 0000 assign_resources, bus 0 link: 0
1342 12:27:50.914673 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1343 12:27:50.924278 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1344 12:27:50.930558 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1345 12:27:50.940612 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1346 12:27:50.947040 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1347 12:27:50.956546 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1348 12:27:50.959907 PCI: 00:14.0 assign_resources, bus 0 link: 0
1349 12:27:50.966273 PCI: 00:14.0 assign_resources, bus 0 link: 0
1350 12:27:50.973080 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1351 12:27:50.982756 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1352 12:27:50.989214 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1353 12:27:50.999286 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1354 12:27:51.002647 PCI: 00:15.0 assign_resources, bus 1 link: 0
1355 12:27:51.005803 PCI: 00:15.0 assign_resources, bus 1 link: 0
1356 12:27:51.008605
1357 12:27:51.015480 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1358 12:27:51.018675 PCI: 00:15.1 assign_resources, bus 2 link: 0
1359 12:27:51.025492 PCI: 00:15.1 assign_resources, bus 2 link: 0
1360 12:27:51.031792 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1361 12:27:51.041537 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1362 12:27:51.048079 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1363 12:27:51.058049 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1364 12:27:51.064282 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1365 12:27:51.071123 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1366 12:27:51.080865 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1367 12:27:51.087321 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1368 12:27:51.093759 PCI: 00:19.0 assign_resources, bus 3 link: 0
1369 12:27:51.096874 PCI: 00:19.0 assign_resources, bus 3 link: 0
1370 12:27:51.106753 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1371 12:27:51.113652 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1372 12:27:51.116985
1373 12:27:51.123306 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1374 12:27:51.126777 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1375 12:27:51.136310 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1376 12:27:51.139689 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1377 12:27:51.149676 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1378 12:27:51.156121 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1379 12:27:51.162776 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1380 12:27:51.166004 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1381 12:27:51.176110 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1382 12:27:51.179131 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1383 12:27:51.186013 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1384 12:27:51.188859 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1385 12:27:51.195307 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1386 12:27:51.198755 LPC: Trying to open IO window from 800 size 1ff
1387 12:27:51.208640 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1388 12:27:51.215008 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1389 12:27:51.224340 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1390 12:27:51.231331 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1391 12:27:51.237537 DOMAIN: 0000 assign_resources, bus 0 link: 0
1392 12:27:51.241313 Root Device assign_resources, bus 0 link: 0
1393 12:27:51.244171 Done setting resources.
1394 12:27:51.250893 Show resources in subtree (Root Device)...After assigning values.
1395 12:27:51.254022 Root Device child on link 0 CPU_CLUSTER: 0
1396 12:27:51.257305 CPU_CLUSTER: 0 child on link 0 APIC: 00
1397 12:27:51.260238 APIC: 00
1398 12:27:51.260326 APIC: 03
1399 12:27:51.263807 APIC: 04
1400 12:27:51.263893 APIC: 05
1401 12:27:51.263961 APIC: 01
1402 12:27:51.266697 APIC: 02
1403 12:27:51.266783 APIC: 07
1404 12:27:51.270059 APIC: 06
1405 12:27:51.273695 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1406 12:27:51.283515 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1407 12:27:51.293163 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1408 12:27:51.296047 PCI: 00:00.0
1409 12:27:51.306231 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1410 12:27:51.316241 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1411 12:27:51.322499 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1412 12:27:51.332227 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1413 12:27:51.342337 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1414 12:27:51.351777 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1415 12:27:51.361521 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1416 12:27:51.371289 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1417 12:27:51.381254 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1418 12:27:51.387851 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1419 12:27:51.397420 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1420 12:27:51.407280 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1421 12:27:51.417132 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1422 12:27:51.426809 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1423 12:27:51.437032 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1424 12:27:51.446422 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1425 12:27:51.446512 PCI: 00:02.0
1426 12:27:51.456253 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1427 12:27:51.469238 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1428 12:27:51.479061 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1429 12:27:51.479150 PCI: 00:04.0
1430 12:27:51.482425 PCI: 00:08.0
1431 12:27:51.492434 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1432 12:27:51.492522 PCI: 00:12.0
1433 12:27:51.501954 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1434 12:27:51.508625 PCI: 00:14.0 child on link 0 USB0 port 0
1435 12:27:51.518115 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1436 12:27:51.521401 USB0 port 0 child on link 0 USB2 port 0
1437 12:27:51.524882 USB2 port 0
1438 12:27:51.524968 USB2 port 1
1439 12:27:51.527898 USB2 port 2
1440 12:27:51.527983 USB2 port 3
1441 12:27:51.531407 USB2 port 5
1442 12:27:51.534342 USB2 port 6
1443 12:27:51.534428 USB2 port 9
1444 12:27:51.537948 USB3 port 0
1445 12:27:51.538034 USB3 port 1
1446 12:27:51.540831 USB3 port 2
1447 12:27:51.540918 USB3 port 3
1448 12:27:51.544123 USB3 port 4
1449 12:27:51.544209 PCI: 00:14.2
1450 12:27:51.553971 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1451 12:27:51.567187 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1452 12:27:51.567293 PCI: 00:14.3
1453 12:27:51.577038 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1454 12:27:51.583403 PCI: 00:15.0 child on link 0 I2C: 01:15
1455 12:27:51.593358 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1456 12:27:51.593449 I2C: 01:15
1457 12:27:51.599506 PCI: 00:15.1 child on link 0 I2C: 02:5d
1458 12:27:51.609559 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1459 12:27:51.609650 I2C: 02:5d
1460 12:27:51.612748 GENERIC: 0.0
1461 12:27:51.612835 PCI: 00:16.0
1462 12:27:51.622452 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1463 12:27:51.625824 PCI: 00:17.0
1464 12:27:51.635638 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1465 12:27:51.645480 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1466 12:27:51.654903 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1467 12:27:51.664661 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1468 12:27:51.674336 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1469 12:27:51.684916 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1470 12:27:51.687692 PCI: 00:19.0 child on link 0 I2C: 03:1a
1471 12:27:51.697715 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1472 12:27:51.700943 I2C: 03:1a
1473 12:27:51.701062 I2C: 03:38
1474 12:27:51.703757 I2C: 03:39
1475 12:27:51.703888 I2C: 03:3a
1476 12:27:51.707540 I2C: 03:3b
1477 12:27:51.710328 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1478 12:27:51.719918 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1479 12:27:51.729811 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1480 12:27:51.739753 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1481 12:27:51.742897 PCI: 01:00.0
1482 12:27:51.753113 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1483 12:27:51.753566 PCI: 00:1e.0
1484 12:27:51.766006 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1485 12:27:51.775916 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1486 12:27:51.779266 PCI: 00:1e.2 child on link 0 SPI: 00
1487 12:27:51.788872 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1488 12:27:51.791653 SPI: 00
1489 12:27:51.795372 PCI: 00:1e.3 child on link 0 SPI: 01
1490 12:27:51.804738 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1491 12:27:51.805190 SPI: 01
1492 12:27:51.811466 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1493 12:27:51.817413 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1494 12:27:51.827664 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1495 12:27:51.830838 PNP: 0c09.0
1496 12:27:51.837498 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1497 12:27:51.840911 PCI: 00:1f.3
1498 12:27:51.850065 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1499 12:27:51.859957 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1500 12:27:51.863260 PCI: 00:1f.4
1501 12:27:51.873295 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1502 12:27:51.882902 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1503 12:27:51.882990 PCI: 00:1f.5
1504 12:27:51.892660 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1505 12:27:51.895856 Done allocating resources.
1506 12:27:51.902545 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1507 12:27:51.905860 Enabling resources...
1508 12:27:51.909072 PCI: 00:00.0 subsystem <- 8086/9b61
1509 12:27:51.912398 PCI: 00:00.0 cmd <- 06
1510 12:27:51.915514 PCI: 00:02.0 subsystem <- 8086/9b41
1511 12:27:51.919114 PCI: 00:02.0 cmd <- 03
1512 12:27:51.922023 PCI: 00:08.0 cmd <- 06
1513 12:27:51.925146 PCI: 00:12.0 subsystem <- 8086/02f9
1514 12:27:51.925226 PCI: 00:12.0 cmd <- 02
1515 12:27:51.932201 PCI: 00:14.0 subsystem <- 8086/02ed
1516 12:27:51.932288 PCI: 00:14.0 cmd <- 02
1517 12:27:51.935651 PCI: 00:14.2 cmd <- 02
1518 12:27:51.938940 PCI: 00:14.3 subsystem <- 8086/02f0
1519 12:27:51.941761 PCI: 00:14.3 cmd <- 02
1520 12:27:51.945453 PCI: 00:15.0 subsystem <- 8086/02e8
1521 12:27:51.948831 PCI: 00:15.0 cmd <- 02
1522 12:27:51.951617 PCI: 00:15.1 subsystem <- 8086/02e9
1523 12:27:51.955064 PCI: 00:15.1 cmd <- 02
1524 12:27:51.958037 PCI: 00:16.0 subsystem <- 8086/02e0
1525 12:27:51.961740 PCI: 00:16.0 cmd <- 02
1526 12:27:51.964878 PCI: 00:17.0 subsystem <- 8086/02d3
1527 12:27:51.968126 PCI: 00:17.0 cmd <- 03
1528 12:27:51.971121 PCI: 00:19.0 subsystem <- 8086/02c5
1529 12:27:51.974413 PCI: 00:19.0 cmd <- 02
1530 12:27:51.977805 PCI: 00:1d.0 bridge ctrl <- 0013
1531 12:27:51.981154 PCI: 00:1d.0 subsystem <- 8086/02b0
1532 12:27:51.984232 PCI: 00:1d.0 cmd <- 06
1533 12:27:51.987627 PCI: 00:1e.0 subsystem <- 8086/02a8
1534 12:27:51.987711 PCI: 00:1e.0 cmd <- 06
1535 12:27:51.994398 PCI: 00:1e.2 subsystem <- 8086/02aa
1536 12:27:51.994480 PCI: 00:1e.2 cmd <- 06
1537 12:27:51.998852 PCI: 00:1e.3 subsystem <- 8086/02ab
1538 12:27:52.001037
1539 12:27:52.001122 PCI: 00:1e.3 cmd <- 02
1540 12:27:52.004234 PCI: 00:1f.0 subsystem <- 8086/0284
1541 12:27:52.007585 PCI: 00:1f.0 cmd <- 407
1542 12:27:52.010866 PCI: 00:1f.3 subsystem <- 8086/02c8
1543 12:27:52.014331 PCI: 00:1f.3 cmd <- 02
1544 12:27:52.016830 PCI: 00:1f.4 subsystem <- 8086/02a3
1545 12:27:52.020319 PCI: 00:1f.4 cmd <- 03
1546 12:27:52.023368 PCI: 00:1f.5 subsystem <- 8086/02a4
1547 12:27:52.026492 PCI: 00:1f.5 cmd <- 406
1548 12:27:52.035777 PCI: 01:00.0 cmd <- 02
1549 12:27:52.041083 done.
1550 12:27:52.052584 ME: Version: 14.0.39.1367
1551 12:27:52.058707 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 11
1552 12:27:52.061856 Initializing devices...
1553 12:27:52.061937 Root Device init ...
1554 12:27:52.068264 Chrome EC: Set SMI mask to 0x0000000000000000
1555 12:27:52.075118 Chrome EC: clear events_b mask to 0x0000000000000000
1556 12:27:52.078313 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1557 12:27:52.084786 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1558 12:27:52.091362 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1559 12:27:52.094458 Chrome EC: Set WAKE mask to 0x0000000000000000
1560 12:27:52.100936 Root Device init finished in 35154 usecs
1561 12:27:52.103985 CPU_CLUSTER: 0 init ...
1562 12:27:52.107269 CPU_CLUSTER: 0 init finished in 2446 usecs
1563 12:27:52.113034 PCI: 00:00.0 init ...
1564 12:27:52.116142 CPU TDP: 15 Watts
1565 12:27:52.119412 CPU PL2 = 64 Watts
1566 12:27:52.122754 PCI: 00:00.0 init finished in 7071 usecs
1567 12:27:52.126000 PCI: 00:02.0 init ...
1568 12:27:52.129191 PCI: 00:02.0 init finished in 2253 usecs
1569 12:27:52.132481 PCI: 00:08.0 init ...
1570 12:27:52.135702 PCI: 00:08.0 init finished in 2252 usecs
1571 12:27:52.138940 PCI: 00:12.0 init ...
1572 12:27:52.142639 PCI: 00:12.0 init finished in 2250 usecs
1573 12:27:52.145762 PCI: 00:14.0 init ...
1574 12:27:52.148787 PCI: 00:14.0 init finished in 2251 usecs
1575 12:27:52.152091 PCI: 00:14.2 init ...
1576 12:27:52.155385 PCI: 00:14.2 init finished in 2253 usecs
1577 12:27:52.158673 PCI: 00:14.3 init ...
1578 12:27:52.162091 PCI: 00:14.3 init finished in 2260 usecs
1579 12:27:52.165500 PCI: 00:15.0 init ...
1580 12:27:52.168779 DW I2C bus 0 at 0xd121f000 (400 KHz)
1581 12:27:52.175043 PCI: 00:15.0 init finished in 5977 usecs
1582 12:27:52.175172 PCI: 00:15.1 init ...
1583 12:27:52.178162 DW I2C bus 1 at 0xd1220000 (400 KHz)
1584 12:27:52.181469
1585 12:27:52.185064 PCI: 00:15.1 init finished in 5974 usecs
1586 12:27:52.187933 PCI: 00:16.0 init ...
1587 12:27:52.191445 PCI: 00:16.0 init finished in 2250 usecs
1588 12:27:52.194721 PCI: 00:19.0 init ...
1589 12:27:52.197984 DW I2C bus 4 at 0xd1222000 (400 KHz)
1590 12:27:52.201363 PCI: 00:19.0 init finished in 5974 usecs
1591 12:27:52.204428 PCI: 00:1d.0 init ...
1592 12:27:52.207718 Initializing PCH PCIe bridge.
1593 12:27:52.210919 PCI: 00:1d.0 init finished in 5283 usecs
1594 12:27:52.214680 PCI: 00:1f.0 init ...
1595 12:27:52.217937 IOAPIC: Initializing IOAPIC at 0xfec00000
1596 12:27:52.224715 IOAPIC: Bootstrap Processor Local APIC = 0x00
1597 12:27:52.224807 IOAPIC: ID = 0x02
1598 12:27:52.227927 IOAPIC: Dumping registers
1599 12:27:52.231057 reg 0x0000: 0x02000000
1600 12:27:52.234377 reg 0x0001: 0x00770020
1601 12:27:52.237432 reg 0x0002: 0x00000000
1602 12:27:52.240995 PCI: 00:1f.0 init finished in 23521 usecs
1603 12:27:52.243966 PCI: 00:1f.4 init ...
1604 12:27:52.247168 PCI: 00:1f.4 init finished in 2262 usecs
1605 12:27:52.258957 PCI: 01:00.0 init ...
1606 12:27:52.262345 PCI: 01:00.0 init finished in 2243 usecs
1607 12:27:52.266759 PNP: 0c09.0 init ...
1608 12:27:52.270078 Google Chrome EC uptime: 11.042 seconds
1609 12:27:52.276480 Google Chrome AP resets since EC boot: 0
1610 12:27:52.279540 Google Chrome most recent AP reset causes:
1611 12:27:52.286112 Google Chrome EC reset flags at last EC boot: reset-pin
1612 12:27:52.289378 PNP: 0c09.0 init finished in 20563 usecs
1613 12:27:52.292682 Devices initialized
1614 12:27:52.295894 Show all devs... After init.
1615 12:27:52.295983 Root Device: enabled 1
1616 12:27:52.299346 CPU_CLUSTER: 0: enabled 1
1617 12:27:52.302355 DOMAIN: 0000: enabled 1
1618 12:27:52.302461 APIC: 00: enabled 1
1619 12:27:52.305464
1620 12:27:52.305565 PCI: 00:00.0: enabled 1
1621 12:27:52.309326 PCI: 00:02.0: enabled 1
1622 12:27:52.312598 PCI: 00:04.0: enabled 0
1623 12:27:52.312695 PCI: 00:05.0: enabled 0
1624 12:27:52.315495 PCI: 00:12.0: enabled 1
1625 12:27:52.318958 PCI: 00:12.5: enabled 0
1626 12:27:52.322123 PCI: 00:12.6: enabled 0
1627 12:27:52.322228 PCI: 00:14.0: enabled 1
1628 12:27:52.325373 PCI: 00:14.1: enabled 0
1629 12:27:52.328889 PCI: 00:14.3: enabled 1
1630 12:27:52.331900 PCI: 00:14.5: enabled 0
1631 12:27:52.331987 PCI: 00:15.0: enabled 1
1632 12:27:52.335089 PCI: 00:15.1: enabled 1
1633 12:27:52.338244 PCI: 00:15.2: enabled 0
1634 12:27:52.341463 PCI: 00:15.3: enabled 0
1635 12:27:52.341599 PCI: 00:16.0: enabled 1
1636 12:27:52.344977 PCI: 00:16.1: enabled 0
1637 12:27:52.347848 PCI: 00:16.2: enabled 0
1638 12:27:52.351718 PCI: 00:16.3: enabled 0
1639 12:27:52.351793 PCI: 00:16.4: enabled 0
1640 12:27:52.354705 PCI: 00:16.5: enabled 0
1641 12:27:52.357554 PCI: 00:17.0: enabled 1
1642 12:27:52.361062 PCI: 00:19.0: enabled 1
1643 12:27:52.361134 PCI: 00:19.1: enabled 0
1644 12:27:52.364047 PCI: 00:19.2: enabled 0
1645 12:27:52.367710 PCI: 00:1a.0: enabled 0
1646 12:27:52.371290 PCI: 00:1c.0: enabled 0
1647 12:27:52.371364 PCI: 00:1c.1: enabled 0
1648 12:27:52.374204 PCI: 00:1c.2: enabled 0
1649 12:27:52.377252 PCI: 00:1c.3: enabled 0
1650 12:27:52.380581 PCI: 00:1c.4: enabled 0
1651 12:27:52.380654 PCI: 00:1c.5: enabled 0
1652 12:27:52.383866 PCI: 00:1c.6: enabled 0
1653 12:27:52.387650 PCI: 00:1c.7: enabled 0
1654 12:27:52.390254 PCI: 00:1d.0: enabled 1
1655 12:27:52.390328 PCI: 00:1d.1: enabled 0
1656 12:27:52.393465 PCI: 00:1d.2: enabled 0
1657 12:27:52.396826 PCI: 00:1d.3: enabled 0
1658 12:27:52.400085 PCI: 00:1d.4: enabled 0
1659 12:27:52.400161 PCI: 00:1d.5: enabled 0
1660 12:27:52.403435 PCI: 00:1e.0: enabled 1
1661 12:27:52.406836 PCI: 00:1e.1: enabled 0
1662 12:27:52.410109 PCI: 00:1e.2: enabled 1
1663 12:27:52.410191 PCI: 00:1e.3: enabled 1
1664 12:27:52.413300 PCI: 00:1f.0: enabled 1
1665 12:27:52.416610 PCI: 00:1f.1: enabled 0
1666 12:27:52.419652 PCI: 00:1f.2: enabled 0
1667 12:27:52.419742 PCI: 00:1f.3: enabled 1
1668 12:27:52.422884 PCI: 00:1f.4: enabled 1
1669 12:27:52.426186 PCI: 00:1f.5: enabled 1
1670 12:27:52.429548 PCI: 00:1f.6: enabled 0
1671 12:27:52.429644 USB0 port 0: enabled 1
1672 12:27:52.432576 I2C: 01:15: enabled 1
1673 12:27:52.435917 I2C: 02:5d: enabled 1
1674 12:27:52.436021 GENERIC: 0.0: enabled 1
1675 12:27:52.439160 I2C: 03:1a: enabled 1
1676 12:27:52.442307 I2C: 03:38: enabled 1
1677 12:27:52.442414 I2C: 03:39: enabled 1
1678 12:27:52.445692 I2C: 03:3a: enabled 1
1679 12:27:52.448848 I2C: 03:3b: enabled 1
1680 12:27:52.452159 PCI: 00:00.0: enabled 1
1681 12:27:52.452247 SPI: 00: enabled 1
1682 12:27:52.455233 SPI: 01: enabled 1
1683 12:27:52.455321 PNP: 0c09.0: enabled 1
1684 12:27:52.458874
1685 12:27:52.458961 USB2 port 0: enabled 1
1686 12:27:52.461906 USB2 port 1: enabled 1
1687 12:27:52.465296 USB2 port 2: enabled 0
1688 12:27:52.465385 USB2 port 3: enabled 0
1689 12:27:52.468677 USB2 port 5: enabled 0
1690 12:27:52.471904 USB2 port 6: enabled 1
1691 12:27:52.475098 USB2 port 9: enabled 1
1692 12:27:52.475188 USB3 port 0: enabled 1
1693 12:27:52.478201 USB3 port 1: enabled 1
1694 12:27:52.481676 USB3 port 2: enabled 1
1695 12:27:52.481765 USB3 port 3: enabled 1
1696 12:27:52.484929 USB3 port 4: enabled 0
1697 12:27:52.487990 APIC: 03: enabled 1
1698 12:27:52.488079 APIC: 04: enabled 1
1699 12:27:52.491424 APIC: 05: enabled 1
1700 12:27:52.494446 APIC: 01: enabled 1
1701 12:27:52.494570 APIC: 02: enabled 1
1702 12:27:52.497874 APIC: 07: enabled 1
1703 12:27:52.497962 APIC: 06: enabled 1
1704 12:27:52.501570 PCI: 00:08.0: enabled 1
1705 12:27:52.504349 PCI: 00:14.2: enabled 1
1706 12:27:52.507675 PCI: 01:00.0: enabled 1
1707 12:27:52.511561 Disabling ACPI via APMC:
1708 12:27:52.514479 done.
1709 12:27:52.517616 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1710 12:27:52.521145 ELOG: NV offset 0xaf0000 size 0x4000
1711 12:27:52.527744 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1712 12:27:52.534650 ELOG: Event(17) added with size 13 at 2023-01-31 12:27:51 UTC
1713 12:27:52.541119 POST: Unexpected post code in previous boot: 0x25
1714 12:27:52.547933 ELOG: Event(A3) added with size 11 at 2023-01-31 12:27:51 UTC
1715 12:27:52.554112 ELOG: Event(A6) added with size 13 at 2023-01-31 12:27:51 UTC
1716 12:27:52.560649 ELOG: Event(92) added with size 9 at 2023-01-31 12:27:51 UTC
1717 12:27:52.567211 ELOG: Event(93) added with size 9 at 2023-01-31 12:27:51 UTC
1718 12:27:52.573579 ELOG: Event(9A) added with size 9 at 2023-01-31 12:27:51 UTC
1719 12:27:52.577180 ELOG: Event(9E) added with size 10 at 2023-01-31 12:27:51 UTC
1720 12:27:52.583394 ELOG: Event(9F) added with size 14 at 2023-01-31 12:27:51 UTC
1721 12:27:52.590026 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1722 12:27:52.596417 ELOG: Event(A1) added with size 10 at 2023-01-31 12:27:51 UTC
1723 12:27:52.606512 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1724 12:27:52.609552 ELOG: Event(A0) added with size 9 at 2023-01-31 12:27:51 UTC
1725 12:27:52.615989 elog_add_boot_reason: Logged dev mode boot
1726 12:27:52.616076 Finalize devices...
1727 12:27:52.619267 PCI: 00:17.0 final
1728 12:27:52.622843 Devices finalized
1729 12:27:52.625665 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1730 12:27:52.632278 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1731 12:27:52.635430 ME: HFSTS1 : 0x90000245
1732 12:27:52.638803 ME: HFSTS2 : 0x3B850126
1733 12:27:52.645409 ME: HFSTS3 : 0x00000020
1734 12:27:52.648756 ME: HFSTS4 : 0x00004800
1735 12:27:52.651880 ME: HFSTS5 : 0x00000000
1736 12:27:52.655273 ME: HFSTS6 : 0x40400006
1737 12:27:52.658380 ME: Manufacturing Mode : NO
1738 12:27:52.661683 ME: FW Partition Table : OK
1739 12:27:52.664838 ME: Bringup Loader Failure : NO
1740 12:27:52.668199 ME: Firmware Init Complete : YES
1741 12:27:52.671529 ME: Boot Options Present : NO
1742 12:27:52.674510 ME: Update In Progress : NO
1743 12:27:52.677905
1744 12:27:52.681006 ME: D0i3 Support : YES
1745 12:27:52.684573 ME: Low Power State Enabled : NO
1746 12:27:52.687794 ME: CPU Replaced : NO
1747 12:27:52.690813 ME: CPU Replacement Valid : YES
1748 12:27:52.694110 ME: Current Working State : 5
1749 12:27:52.697599 ME: Current Operation State : 1
1750 12:27:52.700700 ME: Current Operation Mode : 0
1751 12:27:52.703895 ME: Error Code : 0
1752 12:27:52.707326 ME: CPU Debug Disabled : YES
1753 12:27:52.710316 ME: TXT Support : NO
1754 12:27:52.713828 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1755 12:27:52.720343 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1756 12:27:52.723409 CBFS @ c08000 size 3f8000
1757 12:27:52.726943 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1758 12:27:52.733040 CBFS: Locating 'fallback/dsdt.aml'
1759 12:27:52.736541 CBFS: Found @ offset 10bb80 size 3fa5
1760 12:27:52.739865 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1761 12:27:52.742899 CBFS @ c08000 size 3f8000
1762 12:27:52.749620 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1763 12:27:52.752874 CBFS: Locating 'fallback/slic'
1764 12:27:52.756396 CBFS: 'fallback/slic' not found.
1765 12:27:52.759355
1766 12:27:52.763221 ACPI: Writing ACPI tables at 99b3e000.
1767 12:27:52.763299 ACPI: * FACS
1768 12:27:52.765910 ACPI: * DSDT
1769 12:27:52.769357 Ramoops buffer: 0x100000@0x99a3d000.
1770 12:27:52.772751 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1771 12:27:52.779319 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1772 12:27:52.782505 Google Chrome EC: version:
1773 12:27:52.785953 ro: helios_v2.0.2659-56403530b
1774 12:27:52.788860 rw: helios_v2.0.2849-c41de27e7d
1775 12:27:52.788936 running image: 1
1776 12:27:52.793467 ACPI: * FADT
1777 12:27:52.793543 SCI is IRQ9
1778 12:27:52.800051 ACPI: added table 1/32, length now 40
1779 12:27:52.800131 ACPI: * SSDT
1780 12:27:52.803483 Found 1 CPU(s) with 8 core(s) each.
1781 12:27:52.806677 Error: Could not locate 'wifi_sar' in VPD.
1782 12:27:52.810222
1783 12:27:52.813648 Checking CBFS for default SAR values
1784 12:27:52.816917 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1785 12:27:52.820007 CBFS @ c08000 size 3f8000
1786 12:27:52.826390 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1787 12:27:52.829729 CBFS: Locating 'wifi_sar_defaults.hex'
1788 12:27:52.832635 CBFS: Found @ offset 5fac0 size 77
1789 12:27:52.835852 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1790 12:27:52.842416 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1791 12:27:52.845868 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1792 12:27:52.852302 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1793 12:27:52.855758 failed to find key in VPD: dsm_calib_r0_0
1794 12:27:52.865459 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1795 12:27:52.872088 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1796 12:27:52.875073 failed to find key in VPD: dsm_calib_r0_1
1797 12:27:52.882081 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1798 12:27:52.885171
1799 12:27:52.888100 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1800 12:27:52.891509 failed to find key in VPD: dsm_calib_r0_2
1801 12:27:52.901131 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1802 12:27:52.907910 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1803 12:27:52.910942 failed to find key in VPD: dsm_calib_r0_3
1804 12:27:52.920572 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1805 12:27:52.923874 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1806 12:27:52.930639 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1807 12:27:52.933907 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1808 12:27:52.937446 EC returned error result code 1
1809 12:27:52.940620 EC returned error result code 1
1810 12:27:52.944024 EC returned error result code 1
1811 12:27:52.950449 PS2K: Bad resp from EC. Vivaldi disabled!
1812 12:27:52.954079 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1813 12:27:52.957129
1814 12:27:52.960117 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1815 12:27:52.967117 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1816 12:27:52.970053 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1817 12:27:52.976929 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1818 12:27:52.983229 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1819 12:27:52.989528 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1820 12:27:52.996219 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1821 12:27:52.999341 ACPI: added table 2/32, length now 44
1822 12:27:52.999427 ACPI: * MCFG
1823 12:27:53.002712 ACPI: added table 3/32, length now 48
1824 12:27:53.005728 ACPI: * TPM2
1825 12:27:53.009244 TPM2 log created at 99a2d000
1826 12:27:53.012422 ACPI: added table 4/32, length now 52
1827 12:27:53.012508 ACPI: * MADT
1828 12:27:53.015621
1829 12:27:53.015707 SCI is IRQ9
1830 12:27:53.019028 ACPI: added table 5/32, length now 56
1831 12:27:53.022056 current = 99b43ac0
1832 12:27:53.022142 ACPI: * DMAR
1833 12:27:53.025739 ACPI: added table 6/32, length now 60
1834 12:27:53.028950 ACPI: * IGD OpRegion
1835 12:27:53.031839 GMA: Found VBT in CBFS
1836 12:27:53.035182 GMA: Found valid VBT in CBFS
1837 12:27:53.038424 ACPI: added table 7/32, length now 64
1838 12:27:53.038518 ACPI: * HPET
1839 12:27:53.041927 ACPI: added table 8/32, length now 68
1840 12:27:53.045449
1841 12:27:53.045535 ACPI: done.
1842 12:27:53.048500 ACPI tables: 31744 bytes.
1843 12:27:53.051809 smbios_write_tables: 99a2c000
1844 12:27:53.054952 EC returned error result code 3
1845 12:27:53.057923 Couldn't obtain OEM name from CBI
1846 12:27:53.061505 Create SMBIOS type 17
1847 12:27:53.064804 PCI: 00:00.0 (Intel Cannonlake)
1848 12:27:53.064895 PCI: 00:14.3 (Intel WiFi)
1849 12:27:53.068130 SMBIOS tables: 939 bytes.
1850 12:27:53.074879 Writing table forward entry at 0x00000500
1851 12:27:53.077665 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1852 12:27:53.084153 Writing coreboot table at 0x99b62000
1853 12:27:53.087377 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1854 12:27:53.094087 1. 0000000000001000-000000000009ffff: RAM
1855 12:27:53.097358 2. 00000000000a0000-00000000000fffff: RESERVED
1856 12:27:53.100509 3. 0000000000100000-0000000099a2bfff: RAM
1857 12:27:53.107297 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1858 12:27:53.113745 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1859 12:27:53.116978 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1860 12:27:53.120132
1861 12:27:53.123503 7. 000000009a000000-000000009f7fffff: RESERVED
1862 12:27:53.127159 8. 00000000e0000000-00000000efffffff: RESERVED
1863 12:27:53.133285 9. 00000000fc000000-00000000fc000fff: RESERVED
1864 12:27:53.137075 10. 00000000fe000000-00000000fe00ffff: RESERVED
1865 12:27:53.142982 11. 00000000fed10000-00000000fed17fff: RESERVED
1866 12:27:53.146083 12. 00000000fed80000-00000000fed83fff: RESERVED
1867 12:27:53.152765 13. 00000000fed90000-00000000fed91fff: RESERVED
1868 12:27:53.156048 14. 00000000feda0000-00000000feda1fff: RESERVED
1869 12:27:53.162644 15. 0000000100000000-000000045e7fffff: RAM
1870 12:27:53.165802 Graphics framebuffer located at 0xc0000000
1871 12:27:53.169267 Passing 5 GPIOs to payload:
1872 12:27:53.172487 NAME | PORT | POLARITY | VALUE
1873 12:27:53.178988 write protect | undefined | high | low
1874 12:27:53.185411 lid | undefined | high | high
1875 12:27:53.188463 power | undefined | high | low
1876 12:27:53.195284 oprom | undefined | high | low
1877 12:27:53.198415 EC in RW | 0x000000cb | high | low
1878 12:27:53.201491 Board ID: 4
1879 12:27:53.204740 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1880 12:27:53.208203 CBFS @ c08000 size 3f8000
1881 12:27:53.214708 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1882 12:27:53.221197 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum f861
1883 12:27:53.224565 coreboot table: 1492 bytes.
1884 12:27:53.228013 IMD ROOT 0. 99fff000 00001000
1885 12:27:53.231086 IMD SMALL 1. 99ffe000 00001000
1886 12:27:53.234028 FSP MEMORY 2. 99c4e000 003b0000
1887 12:27:53.237639 CONSOLE 3. 99c2e000 00020000
1888 12:27:53.240560 FMAP 4. 99c2d000 0000054e
1889 12:27:53.243989 TIME STAMP 5. 99c2c000 00000910
1890 12:27:53.247517 VBOOT WORK 6. 99c18000 00014000
1891 12:27:53.250793 MRC DATA 7. 99c16000 00001958
1892 12:27:53.253914 ROMSTG STCK 8. 99c15000 00001000
1893 12:27:53.257164 AFTER CAR 9. 99c0b000 0000a000
1894 12:27:53.260410 RAMSTAGE 10. 99baf000 0005c000
1895 12:27:53.263557 REFCODE 11. 99b7a000 00035000
1896 12:27:53.266947 SMM BACKUP 12. 99b6a000 00010000
1897 12:27:53.270066 COREBOOT 13. 99b62000 00008000
1898 12:27:53.273420 ACPI 14. 99b3e000 00024000
1899 12:27:53.276685 ACPI GNVS 15. 99b3d000 00001000
1900 12:27:53.279920 RAMOOPS 16. 99a3d000 00100000
1901 12:27:53.283156 TPM2 TCGLOG17. 99a2d000 00010000
1902 12:27:53.286345 SMBIOS 18. 99a2c000 00000800
1903 12:27:53.289546 IMD small region:
1904 12:27:53.293238 IMD ROOT 0. 99ffec00 00000400
1905 12:27:53.296336 FSP RUNTIME 1. 99ffebe0 00000004
1906 12:27:53.299506 EC HOSTEVENT 2. 99ffebc0 00000008
1907 12:27:53.302585 POWER STATE 3. 99ffeb80 00000040
1908 12:27:53.305832 ROMSTAGE 4. 99ffeb60 00000004
1909 12:27:53.309063 MEM INFO 5. 99ffe9a0 000001b9
1910 12:27:53.312469 VPD 6. 99ffe920 0000006c
1911 12:27:53.315830 MTRR: Physical address space:
1912 12:27:53.322420 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1913 12:27:53.328615 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1914 12:27:53.335159 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1915 12:27:53.341888 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1916 12:27:53.348330 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1917 12:27:53.354469 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1918 12:27:53.361335 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1919 12:27:53.364356 MTRR: Fixed MSR 0x250 0x0606060606060606
1920 12:27:53.367966 MTRR: Fixed MSR 0x258 0x0606060606060606
1921 12:27:53.371186 MTRR: Fixed MSR 0x259 0x0000000000000000
1922 12:27:53.377586 MTRR: Fixed MSR 0x268 0x0606060606060606
1923 12:27:53.380695 MTRR: Fixed MSR 0x269 0x0606060606060606
1924 12:27:53.384061 MTRR: Fixed MSR 0x26a 0x0606060606060606
1925 12:27:53.387256 MTRR: Fixed MSR 0x26b 0x0606060606060606
1926 12:27:53.393793 MTRR: Fixed MSR 0x26c 0x0606060606060606
1927 12:27:53.397504 MTRR: Fixed MSR 0x26d 0x0606060606060606
1928 12:27:53.400311 MTRR: Fixed MSR 0x26e 0x0606060606060606
1929 12:27:53.403372 MTRR: Fixed MSR 0x26f 0x0606060606060606
1930 12:27:53.407285 call enable_fixed_mtrr()
1931 12:27:53.410398 CPU physical address size: 39 bits
1932 12:27:53.417070 MTRR: default type WB/UC MTRR counts: 6/8.
1933 12:27:53.420398 MTRR: WB selected as default type.
1934 12:27:53.426849 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1935 12:27:53.433573 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1936 12:27:53.436646 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1937 12:27:53.443156 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1938 12:27:53.449571 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1939 12:27:53.455969 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1940 12:27:53.462922 MTRR: Fixed MSR 0x250 0x0606060606060606
1941 12:27:53.465869 MTRR: Fixed MSR 0x258 0x0606060606060606
1942 12:27:53.469083 MTRR: Fixed MSR 0x259 0x0000000000000000
1943 12:27:53.472406 MTRR: Fixed MSR 0x268 0x0606060606060606
1944 12:27:53.479136 MTRR: Fixed MSR 0x269 0x0606060606060606
1945 12:27:53.482457 MTRR: Fixed MSR 0x26a 0x0606060606060606
1946 12:27:53.485510 MTRR: Fixed MSR 0x26b 0x0606060606060606
1947 12:27:53.488628 MTRR: Fixed MSR 0x26c 0x0606060606060606
1948 12:27:53.495290 MTRR: Fixed MSR 0x26d 0x0606060606060606
1949 12:27:53.499090 MTRR: Fixed MSR 0x26e 0x0606060606060606
1950 12:27:53.502239 MTRR: Fixed MSR 0x26f 0x0606060606060606
1951 12:27:53.502326
1952 12:27:53.505179 MTRR check
1953 12:27:53.505266 Fixed MTRRs : Enabled
1954 12:27:53.508319
1955 12:27:53.508406 Variable MTRRs: Enabled
1956 12:27:53.508475
1957 12:27:53.511579 call enable_fixed_mtrr()
1958 12:27:53.518462 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1959 12:27:53.521472 CPU physical address size: 39 bits
1960 12:27:53.524741 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1961 12:27:53.531272 MTRR: Fixed MSR 0x250 0x0606060606060606
1962 12:27:53.534381 MTRR: Fixed MSR 0x250 0x0606060606060606
1963 12:27:53.537635 MTRR: Fixed MSR 0x258 0x0606060606060606
1964 12:27:53.540866 MTRR: Fixed MSR 0x259 0x0000000000000000
1965 12:27:53.544257
1966 12:27:53.547472 MTRR: Fixed MSR 0x268 0x0606060606060606
1967 12:27:53.551106 MTRR: Fixed MSR 0x269 0x0606060606060606
1968 12:27:53.554164 MTRR: Fixed MSR 0x26a 0x0606060606060606
1969 12:27:53.557245 MTRR: Fixed MSR 0x26b 0x0606060606060606
1970 12:27:53.560443
1971 12:27:53.563983 MTRR: Fixed MSR 0x26c 0x0606060606060606
1972 12:27:53.566940 MTRR: Fixed MSR 0x26d 0x0606060606060606
1973 12:27:53.570112 MTRR: Fixed MSR 0x26e 0x0606060606060606
1974 12:27:53.576743 MTRR: Fixed MSR 0x26f 0x0606060606060606
1975 12:27:53.580049 MTRR: Fixed MSR 0x258 0x0606060606060606
1976 12:27:53.583263 call enable_fixed_mtrr()
1977 12:27:53.586497 MTRR: Fixed MSR 0x259 0x0000000000000000
1978 12:27:53.589891 MTRR: Fixed MSR 0x268 0x0606060606060606
1979 12:27:53.593346 MTRR: Fixed MSR 0x269 0x0606060606060606
1980 12:27:53.599658 MTRR: Fixed MSR 0x26a 0x0606060606060606
1981 12:27:53.602988 MTRR: Fixed MSR 0x26b 0x0606060606060606
1982 12:27:53.606361 MTRR: Fixed MSR 0x26c 0x0606060606060606
1983 12:27:53.609684 MTRR: Fixed MSR 0x26d 0x0606060606060606
1984 12:27:53.615803 MTRR: Fixed MSR 0x26e 0x0606060606060606
1985 12:27:53.618992 MTRR: Fixed MSR 0x26f 0x0606060606060606
1986 12:27:53.622146 CPU physical address size: 39 bits
1987 12:27:53.625730 call enable_fixed_mtrr()
1988 12:27:53.629149 MTRR: Fixed MSR 0x250 0x0606060606060606
1989 12:27:53.635528 MTRR: Fixed MSR 0x250 0x0606060606060606
1990 12:27:53.638781 MTRR: Fixed MSR 0x258 0x0606060606060606
1991 12:27:53.641818 MTRR: Fixed MSR 0x259 0x0000000000000000
1992 12:27:53.645182 MTRR: Fixed MSR 0x268 0x0606060606060606
1993 12:27:53.652145 MTRR: Fixed MSR 0x269 0x0606060606060606
1994 12:27:53.655187 MTRR: Fixed MSR 0x26a 0x0606060606060606
1995 12:27:53.658195 MTRR: Fixed MSR 0x26b 0x0606060606060606
1996 12:27:53.661700 MTRR: Fixed MSR 0x26c 0x0606060606060606
1997 12:27:53.668330 MTRR: Fixed MSR 0x26d 0x0606060606060606
1998 12:27:53.671489 MTRR: Fixed MSR 0x26e 0x0606060606060606
1999 12:27:53.674479 MTRR: Fixed MSR 0x26f 0x0606060606060606
2000 12:27:53.677997 MTRR: Fixed MSR 0x258 0x0606060606060606
2001 12:27:53.684278 MTRR: Fixed MSR 0x259 0x0000000000000000
2002 12:27:53.687535 MTRR: Fixed MSR 0x268 0x0606060606060606
2003 12:27:53.690886 MTRR: Fixed MSR 0x269 0x0606060606060606
2004 12:27:53.693986 MTRR: Fixed MSR 0x26a 0x0606060606060606
2005 12:27:53.700650 MTRR: Fixed MSR 0x26b 0x0606060606060606
2006 12:27:53.704136 MTRR: Fixed MSR 0x26c 0x0606060606060606
2007 12:27:53.707123 MTRR: Fixed MSR 0x26d 0x0606060606060606
2008 12:27:53.710393 MTRR: Fixed MSR 0x26e 0x0606060606060606
2009 12:27:53.716694 MTRR: Fixed MSR 0x26f 0x0606060606060606
2010 12:27:53.720245 call enable_fixed_mtrr()
2011 12:27:53.720332 call enable_fixed_mtrr()
2012 12:27:53.723340 CBFS @ c08000 size 3f8000
2013 12:27:53.729636 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
2014 12:27:53.732955 CBFS: Locating 'fallback/payload'
2015 12:27:53.736096 CPU physical address size: 39 bits
2016 12:27:53.739411 CPU physical address size: 39 bits
2017 12:27:53.742680 CBFS: Found @ offset 1c96c0 size 3f798
2018 12:27:53.745845
2019 12:27:53.749645 MTRR: Fixed MSR 0x250 0x0606060606060606
2020 12:27:53.752447 MTRR: Fixed MSR 0x250 0x0606060606060606
2021 12:27:53.755831 MTRR: Fixed MSR 0x258 0x0606060606060606
2022 12:27:53.762277 MTRR: Fixed MSR 0x259 0x0000000000000000
2023 12:27:53.765571 MTRR: Fixed MSR 0x268 0x0606060606060606
2024 12:27:53.769085 MTRR: Fixed MSR 0x269 0x0606060606060606
2025 12:27:53.772230 MTRR: Fixed MSR 0x26a 0x0606060606060606
2026 12:27:53.778459 MTRR: Fixed MSR 0x26b 0x0606060606060606
2027 12:27:53.781695 MTRR: Fixed MSR 0x26c 0x0606060606060606
2028 12:27:53.785058 MTRR: Fixed MSR 0x26d 0x0606060606060606
2029 12:27:53.788313 MTRR: Fixed MSR 0x26e 0x0606060606060606
2030 12:27:53.795053 MTRR: Fixed MSR 0x26f 0x0606060606060606
2031 12:27:53.798433 MTRR: Fixed MSR 0x258 0x0606060606060606
2032 12:27:53.801195 MTRR: Fixed MSR 0x259 0x0000000000000000
2033 12:27:53.804498 MTRR: Fixed MSR 0x268 0x0606060606060606
2034 12:27:53.811116 MTRR: Fixed MSR 0x269 0x0606060606060606
2035 12:27:53.814229 MTRR: Fixed MSR 0x26a 0x0606060606060606
2036 12:27:53.817559 MTRR: Fixed MSR 0x26b 0x0606060606060606
2037 12:27:53.821024 MTRR: Fixed MSR 0x26c 0x0606060606060606
2038 12:27:53.824107
2039 12:27:53.827409 MTRR: Fixed MSR 0x26d 0x0606060606060606
2040 12:27:53.830471 MTRR: Fixed MSR 0x26e 0x0606060606060606
2041 12:27:53.833876 MTRR: Fixed MSR 0x26f 0x0606060606060606
2042 12:27:53.837495 call enable_fixed_mtrr()
2043 12:27:53.840785 call enable_fixed_mtrr()
2044 12:27:53.843660 Checking segment from ROM address 0xffdd16f8
2045 12:27:53.846870 CPU physical address size: 39 bits
2046 12:27:53.850480 CPU physical address size: 39 bits
2047 12:27:53.857225 Checking segment from ROM address 0xffdd1714
2048 12:27:53.860509 CPU physical address size: 39 bits
2049 12:27:53.863799 Loading segment from ROM address 0xffdd16f8
2050 12:27:53.866956 code (compression=0)
2051 12:27:53.873540 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
2052 12:27:53.883644 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
2053 12:27:53.886735 it's not compressed!
2054 12:27:53.977924 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
2055 12:27:53.984608 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
2056 12:27:53.987784 Loading segment from ROM address 0xffdd1714
2057 12:27:53.991237 Entry Point 0x30000000
2058 12:27:53.994378 Loaded segments
2059 12:27:54.000480 Finalizing chipset.
2060 12:27:54.003170 Finalizing SMM.
2061 12:27:54.006667 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
2062 12:27:54.010009 mp_park_aps done after 0 msecs.
2063 12:27:54.016538 Jumping to boot code at 30000000(99b62000)
2064 12:27:54.022694 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
2065 12:27:54.022784
2066 12:27:54.022852
2067 12:27:54.022914
2068 12:27:54.026175 Starting depthcharge on Helios...
2069 12:27:54.026584 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
2070 12:27:54.026688 start: 2.2.4 bootloader-commands (timeout 00:04:41) [common]
2071 12:27:54.026777 Setting prompt string to ['hatch:']
2072 12:27:54.026856 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:41)
2073 12:27:54.029525
2074 12:27:54.035681 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2075 12:27:54.035768
2076 12:27:54.042379 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2077 12:27:54.042482
2078 12:27:54.048924 board_setup: Info: eMMC controller not present; skipping
2079 12:27:54.049012
2080 12:27:54.052106 New NVMe Controller 0x30053ac0 @ 00:1d:00
2081 12:27:54.052193
2082 12:27:54.058687 board_setup: Info: SDHCI controller not present; skipping
2083 12:27:54.058773
2084 12:27:54.064985 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2085 12:27:54.065072
2086 12:27:54.065139 Wipe memory regions:
2087 12:27:54.068320
2088 12:27:54.071669 [0x00000000001000, 0x000000000a0000)
2089 12:27:54.071791
2090 12:27:54.074839 [0x00000000100000, 0x00000030000000)
2091 12:27:54.074979
2092 12:27:54.142552 [0x00000030657430, 0x00000099a2c000)
2093 12:27:54.142661
2094 12:27:54.283717 [0x00000100000000, 0x0000045e800000)
2095 12:27:54.283847
2096 12:27:55.666640 R8152: Initializing
2097 12:27:55.666777
2098 12:27:55.669680 Version 9 (ocp_data = 6010)
2099 12:27:55.669753
2100 12:27:55.673914 R8152: Done initializing
2101 12:27:55.674001
2102 12:27:55.676964 Adding net device
2103 12:27:55.677050
2104 12:27:56.281292 R8152: Initializing
2105 12:27:56.281443
2106 12:27:56.284729 Version 6 (ocp_data = 5c30)
2107 12:27:56.284813
2108 12:27:56.287898 R8152: Done initializing
2109 12:27:56.287981
2110 12:27:56.294260 net_add_device: Attemp to include the same device
2111 12:27:56.294344
2112 12:27:56.301118 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2113 12:27:56.301202
2114 12:27:56.301267
2115 12:27:56.301327
2116 12:27:56.301598 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2118 12:27:56.402348 hatch: tftpboot 192.168.201.1 8948185/tftp-deploy-5jvubox5/kernel/bzImage 8948185/tftp-deploy-5jvubox5/kernel/cmdline 8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
2119 12:27:56.402480 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2120 12:27:56.402648 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
2121 12:27:56.406658 tftpboot 192.168.201.1 8948185/tftp-deploy-5jvubox5/kernel/bzImoy-5jvubox5/kernel/cmdline 8948185/tftp-deploy-5jvubox5/ramdisk/ramdisk.cpio.gz
2122 12:27:56.406745
2123 12:27:56.406810 Waiting for link
2124 12:27:56.406871
2125 12:27:56.607691 done.
2126 12:27:56.607825
2127 12:27:56.607892 MAC: 00:24:32:30:7f:7f
2128 12:27:56.607954
2129 12:27:56.610657 Sending DHCP discover... done.
2130 12:27:56.610742
2131 12:27:56.614051 Waiting for reply... done.
2132 12:27:56.614135
2133 12:27:56.617103 Sending DHCP request... done.
2134 12:27:56.617188
2135 12:27:56.623559 Waiting for reply... done.
2136 12:27:56.623644
2137 12:27:56.623710 My ip is 192.168.201.15
2138 12:27:56.623771
2139 12:27:56.630027 The DHCP server ip is 192.168.201.1
2140 12:27:56.630112
2141 12:27:56.633627 TFTP server IP predefined by user: 192.168.201.1
2142 12:27:56.633711
2143 12:27:56.639851 Bootfile predefined by user: 8948185/tftp-deploy-5jvubox5/kernel/bzImage
2144 12:27:56.639952
2145 12:27:56.643293 Sending tftp read request... done.
2146 12:27:56.643378
2147 12:27:56.646267 Waiting for the transfer...
2148 12:27:56.646364
2149 12:27:57.158648 00000000 ################################################################
2150 12:27:57.158800
2151 12:27:57.663932 00080000 ################################################################
2152 12:27:57.664087
2153 12:27:58.170138 00100000 ################################################################
2154 12:27:58.170291
2155 12:27:58.675781 00180000 ################################################################
2156 12:27:58.675931
2157 12:27:59.181617 00200000 ################################################################
2158 12:27:59.181774
2159 12:27:59.694582 00280000 ################################################################
2160 12:27:59.694764
2161 12:28:00.227553 00300000 ################################################################
2162 12:28:00.227723
2163 12:28:00.761528 00380000 ################################################################
2164 12:28:00.761725
2165 12:28:01.293555 00400000 ################################################################
2166 12:28:01.293709
2167 12:28:01.825544 00480000 ################################################################
2168 12:28:01.825696
2169 12:28:02.367442 00500000 ################################################################
2170 12:28:02.367616
2171 12:28:02.915244 00580000 ################################################################
2172 12:28:02.915388
2173 12:28:03.425090 00600000 ################################################################
2174 12:28:03.425236
2175 12:28:03.944281 00680000 ################################################################
2176 12:28:03.944430
2177 12:28:04.165252 00700000 ############################ done.
2178 12:28:04.165404
2179 12:28:04.168748 The bootfile was 7569296 bytes long.
2180 12:28:04.168823
2181 12:28:04.172103 Sending tftp read request... done.
2182 12:28:04.172213
2183 12:28:04.175435 Waiting for the transfer...
2184 12:28:04.175515
2185 12:28:04.709070 00000000 ################################################################
2186 12:28:04.709221
2187 12:28:05.240312 00080000 ################################################################
2188 12:28:05.240451
2189 12:28:05.769299 00100000 ################################################################
2190 12:28:05.769449
2191 12:28:06.397516 00180000 ################################################################
2192 12:28:06.398092
2193 12:28:07.074970 00200000 ################################################################
2194 12:28:07.075650
2195 12:28:07.669787 00280000 ################################################################
2196 12:28:07.670344
2197 12:28:08.269579 00300000 ################################################################
2198 12:28:08.270127
2199 12:28:08.859833 00380000 ################################################################
2200 12:28:08.860473
2201 12:28:09.465301 00400000 ################################################################
2202 12:28:09.465485
2203 12:28:10.064769 00480000 ################################################################
2204 12:28:10.065176
2205 12:28:10.372607 00500000 ################################ done.
2206 12:28:10.373123
2207 12:28:10.375911 Sending tftp read request... done.
2208 12:28:10.376325
2209 12:28:10.378782 Waiting for the transfer...
2210 12:28:10.379282
2211 12:28:10.379719 00000000 # done.
2212 12:28:10.380037
2213 12:28:10.388941 Command line loaded dynamically from TFTP file: 8948185/tftp-deploy-5jvubox5/kernel/cmdline
2214 12:28:10.389371
2215 12:28:10.414742 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/8948185/extract-nfsrootfs-i2edsw9p,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2216 12:28:10.415191
2217 12:28:10.421516 ec_init(0): CrosEC protocol v3 supported (256, 256)
2218 12:28:10.421932
2219 12:28:10.428484 Shutting down all USB controllers.
2220 12:28:10.428899
2221 12:28:10.429225 Removing current net device
2222 12:28:10.429527
2223 12:28:10.436486 Finalizing coreboot
2224 12:28:10.437052
2225 12:28:10.443050 Exiting depthcharge with code 4 at timestamp: 23748860
2226 12:28:10.443477
2227 12:28:10.443806
2228 12:28:10.444111 Starting kernel ...
2229 12:28:10.444402
2230 12:28:10.444688
2231 12:28:10.444965
2232 12:28:10.446028 end: 2.2.4 bootloader-commands (duration 00:00:16) [common]
2233 12:28:10.446473 start: 2.2.5 auto-login-action (timeout 00:04:24) [common]
2234 12:28:10.446844 Setting prompt string to ['Linux version [0-9]']
2235 12:28:10.447180 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2236 12:28:10.447513 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2238 12:32:34.446705 end: 2.2.5 auto-login-action (duration 00:04:24) [common]
2240 12:32:34.446960 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 264 seconds'
2242 12:32:34.447165 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2245 12:32:34.447485 end: 2 depthcharge-action (duration 00:05:00) [common]
2247 12:32:34.447765 Cleaning after the job
2248 12:32:34.447911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/ramdisk
2249 12:32:34.448422 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/kernel
2250 12:32:34.448990 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/nfsrootfs
2251 12:32:34.487589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8948185/tftp-deploy-5jvubox5/modules
2252 12:32:34.487894 start: 4.1 power-off (timeout 00:00:30) [common]
2253 12:32:34.488060 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-2' '--port=1' '--command=off'
2254 12:32:34.508072 >> Command sent successfully.
2255 12:32:34.510017 Returned 0 in 0 seconds
2256 12:32:34.610653 end: 4.1 power-off (duration 00:00:00) [common]
2258 12:32:34.610986 start: 4.2 read-feedback (timeout 00:10:00) [common]
2259 12:32:34.611225 Listened to connection for namespace 'common' for up to 1s
2260 12:32:35.614592 Finalising connection for namespace 'common'
2261 12:32:35.614838 Disconnecting from shell: Finalise
2262 12:32:35.715548 end: 4.2 read-feedback (duration 00:00:01) [common]
2263 12:32:35.715700 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8948185
2264 12:32:35.889048 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8948185
2265 12:32:35.889230 JobError: Your job cannot terminate cleanly.